From 5908b89f71d581d6f99e7e652a9555516ab0d12a Mon Sep 17 00:00:00 2001 From: uuuvn <83587632+uuuvn@users.noreply.github.com> Date: Sat, 29 Mar 2025 16:46:42 +0500 Subject: [PATCH] MI300X support (WIP) (#9585) --- autogen_stubs.sh | 31 + extra/amdpci/headers/gc_9_4_3_offset.h | 7450 ++ extra/amdpci/headers/gc_9_4_3_sh_mask.h | 31647 +++++++ extra/amdpci/headers/nbio_7_9_0_offset.h | 10004 +++ extra/amdpci/headers/nbio_7_9_0_sh_mask.h | 38900 ++++++++ extra/amdpci/headers/vega10_enum.h | 22532 +++++ extra/amdpci/overlay/gc_9_4_3.h | 7 + extra/hip_gpu_driver/soc15d.h | 444 + extra/hip_gpu_driver/vega10_sdma_pkt_open.h | 3335 + tinygrad/runtime/autogen/am/gc_9_4_3.py | 66438 ++++++++++++++ tinygrad/runtime/autogen/am/nbio_7_9_0.py | 84562 ++++++++++++++++++ tinygrad/runtime/autogen/am/pm4_soc15.py | 931 + tinygrad/runtime/autogen/am/sdma_4_0_0.py | 5209 ++ tinygrad/runtime/autogen/am/sdma_4_4_2.py | 5209 ++ tinygrad/runtime/autogen/am/vega10.py | 36196 ++++++++ tinygrad/runtime/ops_amd.py | 217 +- 16 files changed, 313047 insertions(+), 65 deletions(-) create mode 100644 extra/amdpci/headers/gc_9_4_3_offset.h create mode 100644 extra/amdpci/headers/gc_9_4_3_sh_mask.h create mode 100644 extra/amdpci/headers/nbio_7_9_0_offset.h create mode 100644 extra/amdpci/headers/nbio_7_9_0_sh_mask.h create mode 100644 extra/amdpci/headers/vega10_enum.h create mode 100644 extra/amdpci/overlay/gc_9_4_3.h create mode 100644 extra/hip_gpu_driver/soc15d.h create mode 100644 extra/hip_gpu_driver/vega10_sdma_pkt_open.h create mode 100644 tinygrad/runtime/autogen/am/gc_9_4_3.py create mode 100644 tinygrad/runtime/autogen/am/nbio_7_9_0.py create mode 100644 tinygrad/runtime/autogen/am/pm4_soc15.py create mode 100644 tinygrad/runtime/autogen/am/sdma_4_0_0.py create mode 100644 tinygrad/runtime/autogen/am/sdma_4_4_2.py create mode 100644 tinygrad/runtime/autogen/am/vega10.py diff --git a/autogen_stubs.sh b/autogen_stubs.sh index ff24974a4f..de0e5a0064 100755 --- a/autogen_stubs.sh +++ b/autogen_stubs.sh @@ -308,12 +308,23 @@ generate_am() { sed -i "s\(int64_t)\ \g" $BASE/am/am.py sed -i "s\AMDGPU_PTE_MTYPE_VG10(2)\AMDGPU_PTE_MTYPE_VG10(0, 2)\g" $BASE/am/am.py # incorrect parsing (TODO: remove when clang2py is gone). + clang2py -k cdefstum \ + extra/hip_gpu_driver/kfd_pm4_headers_ai.h \ + extra/hip_gpu_driver/soc15d.h \ + -o $BASE/am/pm4_soc15.py + fixup $BASE/am/pm4_soc15.py + clang2py -k cdefstum \ extra/hip_gpu_driver/kfd_pm4_headers_ai.h \ extra/hip_gpu_driver/nvd.h \ -o $BASE/am/pm4_nv.py fixup $BASE/am/pm4_nv.py + clang2py -k cdefstum \ + extra/amdpci/headers/vega10_enum.h \ + -o $BASE/am/vega10.py + fixup $BASE/am/vega10.py + clang2py -k cdefstum \ extra/amdpci/headers/navi10_enum.h \ -o $BASE/am/navi10.py @@ -341,6 +352,13 @@ generate_am() { -o $BASE/am/mp_11_0.py fixup $BASE/am/mp_11_0.py + clang2py -k cdefstum \ + extra/amdpci/headers/gc_9_4_3_offset.h \ + extra/amdpci/headers/gc_9_4_3_sh_mask.h \ + extra/amdpci/overlay/gc_9_4_3.h \ + -o $BASE/am/gc_9_4_3.py + fixup $BASE/am/gc_9_4_3.py + clang2py -k cdefstum \ extra/amdpci/headers/gc_10_3_0_offset.h \ extra/amdpci/headers/gc_10_3_0_sh_mask.h \ @@ -359,6 +377,13 @@ generate_am() { -o $BASE/am/gc_12_0_0.py fixup $BASE/am/gc_12_0_0.py + clang2py -k cdefstum \ + extra/hip_gpu_driver/sdma_registers.h \ + extra/hip_gpu_driver/vega10_sdma_pkt_open.h \ + --clang-args="-I/opt/rocm/include -x c++" \ + -o $BASE/am/sdma_4_0_0.py + fixup $BASE/am/sdma_4_0_0.py + clang2py -k cdefstum \ extra/hip_gpu_driver/sdma_registers.h \ extra/hip_gpu_driver/navi10_sdma_pkt_open.h \ @@ -403,6 +428,12 @@ generate_am() { -o $BASE/am/nbif_6_3_1.py fixup $BASE/am/nbif_6_3_1.py + clang2py -k cdefstum \ + extra/amdpci/headers/nbio_7_9_0_offset.h \ + extra/amdpci/headers/nbio_7_9_0_sh_mask.h \ + -o $BASE/am/nbio_7_9_0.py + fixup $BASE/am/nbio_7_9_0.py + clang2py -k cdefstum \ extra/amdpci/headers/osssys_6_0_0_offset.h \ extra/amdpci/headers/osssys_6_0_0_sh_mask.h \ diff --git a/extra/amdpci/headers/gc_9_4_3_offset.h b/extra/amdpci/headers/gc_9_4_3_offset.h new file mode 100644 index 0000000000..393963502b --- /dev/null +++ b/extra/amdpci/headers/gc_9_4_3_offset.h @@ -0,0 +1,7450 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _gc_9_4_3_OFFSET_HEADER +#define _gc_9_4_3_OFFSET_HEADER + + + +// addressBlock: xcd0_gc_grbmdec +// base address: 0x8000 +#define regGRBM_CNTL 0x0000 +#define regGRBM_CNTL_BASE_IDX 0 +#define regGRBM_SKEW_CNTL 0x0001 +#define regGRBM_SKEW_CNTL_BASE_IDX 0 +#define regGRBM_STATUS2 0x0002 +#define regGRBM_STATUS2_BASE_IDX 0 +#define regGRBM_PWR_CNTL 0x0003 +#define regGRBM_PWR_CNTL_BASE_IDX 0 +#define regGRBM_STATUS 0x0004 +#define regGRBM_STATUS_BASE_IDX 0 +#define regGRBM_STATUS_SE0 0x0005 +#define regGRBM_STATUS_SE0_BASE_IDX 0 +#define regGRBM_STATUS_SE1 0x0006 +#define regGRBM_STATUS_SE1_BASE_IDX 0 +#define regGRBM_SOFT_RESET 0x0008 +#define regGRBM_SOFT_RESET_BASE_IDX 0 +#define regGRBM_GFX_CLKEN_CNTL 0x000c +#define regGRBM_GFX_CLKEN_CNTL_BASE_IDX 0 +#define regGRBM_WAIT_IDLE_CLOCKS 0x000d +#define regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0 +#define regGRBM_STATUS_SE2 0x000e +#define regGRBM_STATUS_SE2_BASE_IDX 0 +#define regGRBM_STATUS_SE3 0x000f +#define regGRBM_STATUS_SE3_BASE_IDX 0 +#define regGRBM_READ_ERROR 0x0016 +#define regGRBM_READ_ERROR_BASE_IDX 0 +#define regGRBM_READ_ERROR2 0x0017 +#define regGRBM_READ_ERROR2_BASE_IDX 0 +#define regGRBM_INT_CNTL 0x0018 +#define regGRBM_INT_CNTL_BASE_IDX 0 +#define regGRBM_TRAP_OP 0x0019 +#define regGRBM_TRAP_OP_BASE_IDX 0 +#define regGRBM_TRAP_ADDR 0x001a +#define regGRBM_TRAP_ADDR_BASE_IDX 0 +#define regGRBM_TRAP_ADDR_MSK 0x001b +#define regGRBM_TRAP_ADDR_MSK_BASE_IDX 0 +#define regGRBM_TRAP_WD 0x001c +#define regGRBM_TRAP_WD_BASE_IDX 0 +#define regGRBM_TRAP_WD_MSK 0x001d +#define regGRBM_TRAP_WD_MSK_BASE_IDX 0 +#define regGRBM_WRITE_ERROR 0x001f +#define regGRBM_WRITE_ERROR_BASE_IDX 0 +#define regGRBM_IOV_ERROR 0x0020 +#define regGRBM_IOV_ERROR_BASE_IDX 0 +#define regGRBM_CHIP_REVISION 0x0021 +#define regGRBM_CHIP_REVISION_BASE_IDX 0 +#define regGRBM_GFX_CNTL 0x0022 +#define regGRBM_GFX_CNTL_BASE_IDX 0 +#define regGRBM_RSMU_CFG 0x0023 +#define regGRBM_RSMU_CFG_BASE_IDX 0 +#define regGRBM_IH_CREDIT 0x0024 +#define regGRBM_IH_CREDIT_BASE_IDX 0 +#define regGRBM_PWR_CNTL2 0x0025 +#define regGRBM_PWR_CNTL2_BASE_IDX 0 +#define regGRBM_UTCL2_INVAL_RANGE_START 0x0026 +#define regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0 +#define regGRBM_UTCL2_INVAL_RANGE_END 0x0027 +#define regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0 +#define regGRBM_RSMU_READ_ERROR 0x0028 +#define regGRBM_RSMU_READ_ERROR_BASE_IDX 0 +#define regGRBM_CHICKEN_BITS 0x0029 +#define regGRBM_CHICKEN_BITS_BASE_IDX 0 +#define regGRBM_FENCE_RANGE0 0x002a +#define regGRBM_FENCE_RANGE0_BASE_IDX 0 +#define regGRBM_FENCE_RANGE1 0x002b +#define regGRBM_FENCE_RANGE1_BASE_IDX 0 +#define regGRBM_IOV_READ_ERROR 0x002c +#define regGRBM_IOV_READ_ERROR_BASE_IDX 0 +#define regGRBM_NOWHERE 0x003f +#define regGRBM_NOWHERE_BASE_IDX 0 +#define regGRBM_SCRATCH_REG0 0x0040 +#define regGRBM_SCRATCH_REG0_BASE_IDX 0 +#define regGRBM_SCRATCH_REG1 0x0041 +#define regGRBM_SCRATCH_REG1_BASE_IDX 0 +#define regGRBM_SCRATCH_REG2 0x0042 +#define regGRBM_SCRATCH_REG2_BASE_IDX 0 +#define regGRBM_SCRATCH_REG3 0x0043 +#define regGRBM_SCRATCH_REG3_BASE_IDX 0 +#define regGRBM_SCRATCH_REG4 0x0044 +#define regGRBM_SCRATCH_REG4_BASE_IDX 0 +#define regGRBM_SCRATCH_REG5 0x0045 +#define regGRBM_SCRATCH_REG5_BASE_IDX 0 +#define regGRBM_SCRATCH_REG6 0x0046 +#define regGRBM_SCRATCH_REG6_BASE_IDX 0 +#define regGRBM_SCRATCH_REG7 0x0047 +#define regGRBM_SCRATCH_REG7_BASE_IDX 0 +#define regVIOLATION_DATA_ASYNC_VF_PROG 0x0048 +#define regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX 0 + + +// addressBlock: xcd0_gc_cpdec +// base address: 0x8200 +#define regCP_CPC_DEBUG_CNTL 0x0080 +#define regCP_CPC_DEBUG_CNTL_BASE_IDX 0 +#define regCP_CPF_DEBUG_CNTL 0x0082 +#define regCP_CPF_DEBUG_CNTL_BASE_IDX 0 +#define regCP_CPC_STATUS 0x0084 +#define regCP_CPC_STATUS_BASE_IDX 0 +#define regCP_CPC_BUSY_STAT 0x0085 +#define regCP_CPC_BUSY_STAT_BASE_IDX 0 +#define regCP_CPC_STALLED_STAT1 0x0086 +#define regCP_CPC_STALLED_STAT1_BASE_IDX 0 +#define regCP_CPF_STATUS 0x0087 +#define regCP_CPF_STATUS_BASE_IDX 0 +#define regCP_CPF_BUSY_STAT 0x0088 +#define regCP_CPF_BUSY_STAT_BASE_IDX 0 +#define regCP_CPF_STALLED_STAT1 0x0089 +#define regCP_CPF_STALLED_STAT1_BASE_IDX 0 +#define regCP_CPC_GRBM_FREE_COUNT 0x008b +#define regCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0 +#define regCP_CPC_PRIV_VIOLATION_ADDR 0x008c +#define regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX 0 +#define regCP_MEC_CNTL 0x008d +#define regCP_MEC_CNTL_BASE_IDX 0 +#define regCP_MEC_ME1_HEADER_DUMP 0x008e +#define regCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0 +#define regCP_MEC_ME2_HEADER_DUMP 0x008f +#define regCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0 +#define regCP_CPC_SCRATCH_INDEX 0x0090 +#define regCP_CPC_SCRATCH_INDEX_BASE_IDX 0 +#define regCP_CPC_SCRATCH_DATA 0x0091 +#define regCP_CPC_SCRATCH_DATA_BASE_IDX 0 +#define regCP_CPF_GRBM_FREE_COUNT 0x0092 +#define regCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0 +#define regCP_CPC_HALT_HYST_COUNT 0x00a7 +#define regCP_CPC_HALT_HYST_COUNT_BASE_IDX 0 +#define regCP_CE_COMPARE_COUNT 0x00c0 +#define regCP_CE_COMPARE_COUNT_BASE_IDX 0 +#define regCP_CE_DE_COUNT 0x00c1 +#define regCP_CE_DE_COUNT_BASE_IDX 0 +#define regCP_DE_CE_COUNT 0x00c2 +#define regCP_DE_CE_COUNT_BASE_IDX 0 +#define regCP_DE_LAST_INVAL_COUNT 0x00c3 +#define regCP_DE_LAST_INVAL_COUNT_BASE_IDX 0 +#define regCP_DE_DE_COUNT 0x00c4 +#define regCP_DE_DE_COUNT_BASE_IDX 0 +#define regCP_STALLED_STAT3 0x019c +#define regCP_STALLED_STAT3_BASE_IDX 0 +#define regCP_STALLED_STAT1 0x019d +#define regCP_STALLED_STAT1_BASE_IDX 0 +#define regCP_STALLED_STAT2 0x019e +#define regCP_STALLED_STAT2_BASE_IDX 0 +#define regCP_BUSY_STAT 0x019f +#define regCP_BUSY_STAT_BASE_IDX 0 +#define regCP_STAT 0x01a0 +#define regCP_STAT_BASE_IDX 0 +#define regCP_ME_HEADER_DUMP 0x01a1 +#define regCP_ME_HEADER_DUMP_BASE_IDX 0 +#define regCP_PFP_HEADER_DUMP 0x01a2 +#define regCP_PFP_HEADER_DUMP_BASE_IDX 0 +#define regCP_GRBM_FREE_COUNT 0x01a3 +#define regCP_GRBM_FREE_COUNT_BASE_IDX 0 +#define regCP_CE_HEADER_DUMP 0x01a4 +#define regCP_CE_HEADER_DUMP_BASE_IDX 0 +#define regCP_PFP_INSTR_PNTR 0x01a5 +#define regCP_PFP_INSTR_PNTR_BASE_IDX 0 +#define regCP_ME_INSTR_PNTR 0x01a6 +#define regCP_ME_INSTR_PNTR_BASE_IDX 0 +#define regCP_CE_INSTR_PNTR 0x01a7 +#define regCP_CE_INSTR_PNTR_BASE_IDX 0 +#define regCP_MEC1_INSTR_PNTR 0x01a8 +#define regCP_MEC1_INSTR_PNTR_BASE_IDX 0 +#define regCP_MEC2_INSTR_PNTR 0x01a9 +#define regCP_MEC2_INSTR_PNTR_BASE_IDX 0 +#define regCP_CSF_STAT 0x01b4 +#define regCP_CSF_STAT_BASE_IDX 0 +#define regCP_ME_CNTL 0x01b6 +#define regCP_ME_CNTL_BASE_IDX 0 +#define regCP_CNTX_STAT 0x01b8 +#define regCP_CNTX_STAT_BASE_IDX 0 +#define regCP_ME_PREEMPTION 0x01b9 +#define regCP_ME_PREEMPTION_BASE_IDX 0 +#define regCP_ROQ_THRESHOLDS 0x01bc +#define regCP_ROQ_THRESHOLDS_BASE_IDX 0 +#define regCP_MEQ_STQ_THRESHOLD 0x01bd +#define regCP_MEQ_STQ_THRESHOLD_BASE_IDX 0 +#define regCP_RB2_RPTR 0x01be +#define regCP_RB2_RPTR_BASE_IDX 0 +#define regCP_RB1_RPTR 0x01bf +#define regCP_RB1_RPTR_BASE_IDX 0 +#define regCP_RB0_RPTR 0x01c0 +#define regCP_RB0_RPTR_BASE_IDX 0 +#define regCP_RB_RPTR 0x01c0 +#define regCP_RB_RPTR_BASE_IDX 0 +#define regCP_RB_WPTR_DELAY 0x01c1 +#define regCP_RB_WPTR_DELAY_BASE_IDX 0 +#define regCP_RB_WPTR_POLL_CNTL 0x01c2 +#define regCP_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regCP_ROQ1_THRESHOLDS 0x01d5 +#define regCP_ROQ1_THRESHOLDS_BASE_IDX 0 +#define regCP_ROQ2_THRESHOLDS 0x01d6 +#define regCP_ROQ2_THRESHOLDS_BASE_IDX 0 +#define regCP_STQ_THRESHOLDS 0x01d7 +#define regCP_STQ_THRESHOLDS_BASE_IDX 0 +#define regCP_QUEUE_THRESHOLDS 0x01d8 +#define regCP_QUEUE_THRESHOLDS_BASE_IDX 0 +#define regCP_MEQ_THRESHOLDS 0x01d9 +#define regCP_MEQ_THRESHOLDS_BASE_IDX 0 +#define regCP_ROQ_AVAIL 0x01da +#define regCP_ROQ_AVAIL_BASE_IDX 0 +#define regCP_STQ_AVAIL 0x01db +#define regCP_STQ_AVAIL_BASE_IDX 0 +#define regCP_ROQ2_AVAIL 0x01dc +#define regCP_ROQ2_AVAIL_BASE_IDX 0 +#define regCP_MEQ_AVAIL 0x01dd +#define regCP_MEQ_AVAIL_BASE_IDX 0 +#define regCP_CMD_INDEX 0x01de +#define regCP_CMD_INDEX_BASE_IDX 0 +#define regCP_CMD_DATA 0x01df +#define regCP_CMD_DATA_BASE_IDX 0 +#define regCP_ROQ_RB_STAT 0x01e0 +#define regCP_ROQ_RB_STAT_BASE_IDX 0 +#define regCP_ROQ_IB1_STAT 0x01e1 +#define regCP_ROQ_IB1_STAT_BASE_IDX 0 +#define regCP_ROQ_IB2_STAT 0x01e2 +#define regCP_ROQ_IB2_STAT_BASE_IDX 0 +#define regCP_STQ_STAT 0x01e3 +#define regCP_STQ_STAT_BASE_IDX 0 +#define regCP_STQ_WR_STAT 0x01e4 +#define regCP_STQ_WR_STAT_BASE_IDX 0 +#define regCP_MEQ_STAT 0x01e5 +#define regCP_MEQ_STAT_BASE_IDX 0 +#define regCP_CEQ1_AVAIL 0x01e6 +#define regCP_CEQ1_AVAIL_BASE_IDX 0 +#define regCP_CEQ2_AVAIL 0x01e7 +#define regCP_CEQ2_AVAIL_BASE_IDX 0 +#define regCP_CE_ROQ_RB_STAT 0x01e8 +#define regCP_CE_ROQ_RB_STAT_BASE_IDX 0 +#define regCP_CE_ROQ_IB1_STAT 0x01e9 +#define regCP_CE_ROQ_IB1_STAT_BASE_IDX 0 +#define regCP_CE_ROQ_IB2_STAT 0x01ea +#define regCP_CE_ROQ_IB2_STAT_BASE_IDX 0 +#define regCP_INT_STAT_DEBUG 0x01f7 +#define regCP_INT_STAT_DEBUG_BASE_IDX 0 +#define regCP_DEBUG_CNTL 0x01f8 +#define regCP_DEBUG_CNTL_BASE_IDX 0 +#define regCP_PRIV_VIOLATION_ADDR 0x01fa +#define regCP_PRIV_VIOLATION_ADDR_BASE_IDX 0 + + +// addressBlock: xcd0_gc_padec +// base address: 0x8800 +#define regVGT_VTX_VECT_EJECT_REG 0x022c +#define regVGT_VTX_VECT_EJECT_REG_BASE_IDX 0 +#define regVGT_DMA_DATA_FIFO_DEPTH 0x022d +#define regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0 +#define regVGT_DMA_REQ_FIFO_DEPTH 0x022e +#define regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0 +#define regVGT_DRAW_INIT_FIFO_DEPTH 0x022f +#define regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0 +#define regVGT_LAST_COPY_STATE 0x0230 +#define regVGT_LAST_COPY_STATE_BASE_IDX 0 +#define regVGT_CACHE_INVALIDATION 0x0231 +#define regVGT_CACHE_INVALIDATION_BASE_IDX 0 +#define regVGT_RESET_DEBUG 0x0232 +#define regVGT_RESET_DEBUG_BASE_IDX 0 +#define regVGT_STRMOUT_DELAY 0x0233 +#define regVGT_STRMOUT_DELAY_BASE_IDX 0 +#define regVGT_FIFO_DEPTHS 0x0234 +#define regVGT_FIFO_DEPTHS_BASE_IDX 0 +#define regVGT_GS_VERTEX_REUSE 0x0235 +#define regVGT_GS_VERTEX_REUSE_BASE_IDX 0 +#define regVGT_MC_LAT_CNTL 0x0236 +#define regVGT_MC_LAT_CNTL_BASE_IDX 0 +#define regIA_CNTL_STATUS 0x0237 +#define regIA_CNTL_STATUS_BASE_IDX 0 +#define regVGT_CNTL_STATUS 0x023c +#define regVGT_CNTL_STATUS_BASE_IDX 0 +#define regWD_CNTL_STATUS 0x023f +#define regWD_CNTL_STATUS_BASE_IDX 0 +#define regCC_GC_PRIM_CONFIG 0x0240 +#define regCC_GC_PRIM_CONFIG_BASE_IDX 0 +#define regGC_USER_PRIM_CONFIG 0x0241 +#define regGC_USER_PRIM_CONFIG_BASE_IDX 0 +#define regWD_QOS 0x0242 +#define regWD_QOS_BASE_IDX 0 +#define regWD_UTCL1_CNTL 0x0243 +#define regWD_UTCL1_CNTL_BASE_IDX 0 +#define regWD_UTCL1_STATUS 0x0244 +#define regWD_UTCL1_STATUS_BASE_IDX 0 +#define regIA_UTCL1_CNTL 0x0246 +#define regIA_UTCL1_CNTL_BASE_IDX 0 +#define regIA_UTCL1_STATUS 0x0247 +#define regIA_UTCL1_STATUS_BASE_IDX 0 +#define regVGT_SYS_CONFIG 0x0263 +#define regVGT_SYS_CONFIG_BASE_IDX 0 +#define regVGT_VS_MAX_WAVE_ID 0x0268 +#define regVGT_VS_MAX_WAVE_ID_BASE_IDX 0 +#define regVGT_GS_MAX_WAVE_ID 0x0269 +#define regVGT_GS_MAX_WAVE_ID_BASE_IDX 0 +#define regGFX_PIPE_CONTROL 0x026d +#define regGFX_PIPE_CONTROL_BASE_IDX 0 +#define regCC_GC_SHADER_ARRAY_CONFIG 0x026f +#define regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0 +#define regGC_USER_SHADER_ARRAY_CONFIG 0x0270 +#define regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 0 +#define regVGT_DMA_PRIMITIVE_TYPE 0x0271 +#define regVGT_DMA_PRIMITIVE_TYPE_BASE_IDX 0 +#define regVGT_DMA_CONTROL 0x0272 +#define regVGT_DMA_CONTROL_BASE_IDX 0 +#define regVGT_DMA_LS_HS_CONFIG 0x0273 +#define regVGT_DMA_LS_HS_CONFIG_BASE_IDX 0 +#define regWD_BUF_RESOURCE_1 0x0276 +#define regWD_BUF_RESOURCE_1_BASE_IDX 0 +#define regWD_BUF_RESOURCE_2 0x0277 +#define regWD_BUF_RESOURCE_2_BASE_IDX 0 +#define regPA_CL_CNTL_STATUS 0x0284 +#define regPA_CL_CNTL_STATUS_BASE_IDX 0 +#define regPA_CL_ENHANCE 0x0285 +#define regPA_CL_ENHANCE_BASE_IDX 0 +#define regPA_CL_RESET_DEBUG 0x0286 +#define regPA_CL_RESET_DEBUG_BASE_IDX 0 +#define regPA_SU_CNTL_STATUS 0x0294 +#define regPA_SU_CNTL_STATUS_BASE_IDX 0 +#define regPA_SC_FIFO_DEPTH_CNTL 0x0295 +#define regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0 +#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x02c0 +#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x02c1 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 +#define regPA_SC_TRAP_SCREEN_HV_LOCK 0x02c2 +#define regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 +#define regPA_SC_FORCE_EOV_MAX_CNTS 0x02c9 +#define regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 0 +#define regPA_SC_BINNER_EVENT_CNTL_0 0x02cc +#define regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 0 +#define regPA_SC_BINNER_EVENT_CNTL_1 0x02cd +#define regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 0 +#define regPA_SC_BINNER_EVENT_CNTL_2 0x02ce +#define regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 0 +#define regPA_SC_BINNER_EVENT_CNTL_3 0x02cf +#define regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 0 +#define regPA_SC_BINNER_TIMEOUT_COUNTER 0x02d0 +#define regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 0 +#define regPA_SC_BINNER_PERF_CNTL_0 0x02d1 +#define regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 0 +#define regPA_SC_BINNER_PERF_CNTL_1 0x02d2 +#define regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 0 +#define regPA_SC_BINNER_PERF_CNTL_2 0x02d3 +#define regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 0 +#define regPA_SC_BINNER_PERF_CNTL_3 0x02d4 +#define regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 0 +#define regPA_SC_ENHANCE_2 0x02dc +#define regPA_SC_ENHANCE_2_BASE_IDX 0 +#define regPA_SC_FIFO_SIZE 0x02f3 +#define regPA_SC_FIFO_SIZE_BASE_IDX 0 +#define regPA_SC_IF_FIFO_SIZE 0x02f5 +#define regPA_SC_IF_FIFO_SIZE_BASE_IDX 0 +#define regPA_SC_PKR_WAVE_TABLE_CNTL 0x02f8 +#define regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 0 +#define regPA_UTCL1_CNTL1 0x02f9 +#define regPA_UTCL1_CNTL1_BASE_IDX 0 +#define regPA_UTCL1_CNTL2 0x02fa +#define regPA_UTCL1_CNTL2_BASE_IDX 0 +#define regPA_SIDEBAND_REQUEST_DELAYS 0x02fb +#define regPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX 0 +#define regPA_SC_ENHANCE 0x02fc +#define regPA_SC_ENHANCE_BASE_IDX 0 +#define regPA_SC_ENHANCE_1 0x02fd +#define regPA_SC_ENHANCE_1_BASE_IDX 0 +#define regPA_SC_DSM_CNTL 0x02fe +#define regPA_SC_DSM_CNTL_BASE_IDX 0 +#define regPA_SC_TILE_STEERING_CREST_OVERRIDE 0x02ff +#define regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 0 + + +// addressBlock: xcd0_gc_sqdec +// base address: 0x8c00 +#define regSQ_CONFIG 0x0300 +#define regSQ_CONFIG_BASE_IDX 0 +#define regSQC_CONFIG 0x0301 +#define regSQC_CONFIG_BASE_IDX 0 +#define regLDS_CONFIG 0x0302 +#define regLDS_CONFIG_BASE_IDX 0 +#define regSQ_RANDOM_WAVE_PRI 0x0303 +#define regSQ_RANDOM_WAVE_PRI_BASE_IDX 0 +#define regSQ_REG_CREDITS 0x0304 +#define regSQ_REG_CREDITS_BASE_IDX 0 +#define regSQ_FIFO_SIZES 0x0305 +#define regSQ_FIFO_SIZES_BASE_IDX 0 +#define regSQ_DSM_CNTL 0x0306 +#define regSQ_DSM_CNTL_BASE_IDX 0 +#define regSQ_DSM_CNTL2 0x0307 +#define regSQ_DSM_CNTL2_BASE_IDX 0 +#define regSQ_RUNTIME_CONFIG 0x0308 +#define regSQ_RUNTIME_CONFIG_BASE_IDX 0 +#define regSQ_DEBUG_STS_GLOBAL 0x0309 +#define regSQ_DEBUG_STS_GLOBAL_BASE_IDX 0 +#define regSH_MEM_BASES 0x030a +#define regSH_MEM_BASES_BASE_IDX 0 +#define regSQ_TIMEOUT_CONFIG 0x030b +#define regSQ_TIMEOUT_CONFIG_BASE_IDX 0 +#define regSQ_TIMEOUT_STATUS 0x030c +#define regSQ_TIMEOUT_STATUS_BASE_IDX 0 +#define regSH_MEM_CONFIG 0x030d +#define regSH_MEM_CONFIG_BASE_IDX 0 +#define regSP_MFMA_PORTD_RD_CONFIG 0x030e +#define regSP_MFMA_PORTD_RD_CONFIG_BASE_IDX 0 +#define regSH_CAC_CONFIG 0x030f +#define regSH_CAC_CONFIG_BASE_IDX 0 +#define regSQ_DEBUG_STS_GLOBAL2 0x0310 +#define regSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0 +#define regSQ_DEBUG_STS_GLOBAL3 0x0311 +#define regSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0 +#define regCC_GC_SHADER_RATE_CONFIG 0x0312 +#define regCC_GC_SHADER_RATE_CONFIG_BASE_IDX 0 +#define regGC_USER_SHADER_RATE_CONFIG 0x0313 +#define regGC_USER_SHADER_RATE_CONFIG_BASE_IDX 0 +#define regSQ_INTERRUPT_AUTO_MASK 0x0314 +#define regSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0 +#define regSQ_INTERRUPT_MSG_CTRL 0x0315 +#define regSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0 +#define regSQ_DEBUG_PERFCOUNT_TRAP 0x0316 +#define regSQ_DEBUG_PERFCOUNT_TRAP_BASE_IDX 0 +#define regSQ_UTCL1_CNTL1 0x0317 +#define regSQ_UTCL1_CNTL1_BASE_IDX 0 +#define regSQ_UTCL1_CNTL2 0x0318 +#define regSQ_UTCL1_CNTL2_BASE_IDX 0 +#define regSQ_UTCL1_STATUS 0x0319 +#define regSQ_UTCL1_STATUS_BASE_IDX 0 +#define regSQ_FED_INTERRUPT_STATUS 0x031a +#define regSQ_FED_INTERRUPT_STATUS_BASE_IDX 0 +#define regSQ_CGTS_CONFIG 0x031b +#define regSQ_CGTS_CONFIG_BASE_IDX 0 +#define regSQ_SHADER_TBA_LO 0x031c +#define regSQ_SHADER_TBA_LO_BASE_IDX 0 +#define regSQ_SHADER_TBA_HI 0x031d +#define regSQ_SHADER_TBA_HI_BASE_IDX 0 +#define regSQ_SHADER_TMA_LO 0x031e +#define regSQ_SHADER_TMA_LO_BASE_IDX 0 +#define regSQ_SHADER_TMA_HI 0x031f +#define regSQ_SHADER_TMA_HI_BASE_IDX 0 +#define regSQC_DSM_CNTL 0x0320 +#define regSQC_DSM_CNTL_BASE_IDX 0 +#define regSQC_DSM_CNTLA 0x0321 +#define regSQC_DSM_CNTLA_BASE_IDX 0 +#define regSQC_DSM_CNTLB 0x0322 +#define regSQC_DSM_CNTLB_BASE_IDX 0 +#define regSQC_DSM_CNTL2 0x0325 +#define regSQC_DSM_CNTL2_BASE_IDX 0 +#define regSQC_DSM_CNTL2A 0x0326 +#define regSQC_DSM_CNTL2A_BASE_IDX 0 +#define regSQC_DSM_CNTL2B 0x0327 +#define regSQC_DSM_CNTL2B_BASE_IDX 0 +#define regSQC_DSM_CNTL2E 0x032a +#define regSQC_DSM_CNTL2E_BASE_IDX 0 +#define regSQC_EDC_FUE_CNTL 0x032b +#define regSQC_EDC_FUE_CNTL_BASE_IDX 0 +#define regSQC_EDC_CNT2 0x032c +#define regSQC_EDC_CNT2_BASE_IDX 0 +#define regSQC_EDC_CNT3 0x032d +#define regSQC_EDC_CNT3_BASE_IDX 0 +#define regSQC_EDC_PARITY_CNT3 0x032e +#define regSQC_EDC_PARITY_CNT3_BASE_IDX 0 +#define regSQ_DEBUG 0x0332 +#define regSQ_DEBUG_BASE_IDX 0 +#define regSQ_PERF_SNAPSHOT_CTRL 0x0334 +#define regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX 0 +#define regSQ_DEBUG_FOR_INTERNAL_CTRL 0x0335 +#define regSQ_DEBUG_FOR_INTERNAL_CTRL_BASE_IDX 0 +#define regSQ_REG_TIMESTAMP 0x0374 +#define regSQ_REG_TIMESTAMP_BASE_IDX 0 +#define regSQ_CMD_TIMESTAMP 0x0375 +#define regSQ_CMD_TIMESTAMP_BASE_IDX 0 +#define regSQ_HOSTTRAP_STATUS 0x0376 +#define regSQ_HOSTTRAP_STATUS_BASE_IDX 0 +#define regSQ_IND_INDEX 0x0378 +#define regSQ_IND_INDEX_BASE_IDX 0 +#define regSQ_IND_DATA 0x0379 +#define regSQ_IND_DATA_BASE_IDX 0 +#define regSQ_CONFIG1 0x037a +#define regSQ_CONFIG1_BASE_IDX 0 +#define regSQ_CMD 0x037b +#define regSQ_CMD_BASE_IDX 0 +#define regSQ_TIME_HI 0x037c +#define regSQ_TIME_HI_BASE_IDX 0 +#define regSQ_TIME_LO 0x037d +#define regSQ_TIME_LO_BASE_IDX 0 +#define regSQ_DS_0 0x037f +#define regSQ_DS_0_BASE_IDX 0 +#define regSQ_DS_1 0x037f +#define regSQ_DS_1_BASE_IDX 0 +#define regSQ_EXP_0 0x037f +#define regSQ_EXP_0_BASE_IDX 0 +#define regSQ_EXP_1 0x037f +#define regSQ_EXP_1_BASE_IDX 0 +#define regSQ_FLAT_0 0x037f +#define regSQ_FLAT_0_BASE_IDX 0 +#define regSQ_FLAT_1 0x037f +#define regSQ_FLAT_1_BASE_IDX 0 +#define regSQ_GLBL_0 0x037f +#define regSQ_GLBL_0_BASE_IDX 0 +#define regSQ_GLBL_1 0x037f +#define regSQ_GLBL_1_BASE_IDX 0 +#define regSQ_INST 0x037f +#define regSQ_INST_BASE_IDX 0 +#define regSQ_MIMG_0 0x037f +#define regSQ_MIMG_0_BASE_IDX 0 +#define regSQ_MIMG_1 0x037f +#define regSQ_MIMG_1_BASE_IDX 0 +#define regSQ_MTBUF_0 0x037f +#define regSQ_MTBUF_0_BASE_IDX 0 +#define regSQ_MTBUF_1 0x037f +#define regSQ_MTBUF_1_BASE_IDX 0 +#define regSQ_MUBUF_0 0x037f +#define regSQ_MUBUF_0_BASE_IDX 0 +#define regSQ_MUBUF_1 0x037f +#define regSQ_MUBUF_1_BASE_IDX 0 +#define regSQ_SCRATCH_0 0x037f +#define regSQ_SCRATCH_0_BASE_IDX 0 +#define regSQ_SCRATCH_1 0x037f +#define regSQ_SCRATCH_1_BASE_IDX 0 +#define regSQ_SMEM_0 0x037f +#define regSQ_SMEM_0_BASE_IDX 0 +#define regSQ_SMEM_1 0x037f +#define regSQ_SMEM_1_BASE_IDX 0 +#define regSQ_SOP1 0x037f +#define regSQ_SOP1_BASE_IDX 0 +#define regSQ_SOP2 0x037f +#define regSQ_SOP2_BASE_IDX 0 +#define regSQ_SOPC 0x037f +#define regSQ_SOPC_BASE_IDX 0 +#define regSQ_SOPK 0x037f +#define regSQ_SOPK_BASE_IDX 0 +#define regSQ_SOPP 0x037f +#define regSQ_SOPP_BASE_IDX 0 +#define regSQ_VINTRP 0x037f +#define regSQ_VINTRP_BASE_IDX 0 +#define regSQ_VOP1 0x037f +#define regSQ_VOP1_BASE_IDX 0 +#define regSQ_VOP2 0x037f +#define regSQ_VOP2_BASE_IDX 0 +#define regSQ_VOP3P_0 0x037f +#define regSQ_VOP3P_0_BASE_IDX 0 +#define regSQ_VOP3P_1 0x037f +#define regSQ_VOP3P_1_BASE_IDX 0 +#define regSQ_VOP3P_MFMA_0 0x037f +#define regSQ_VOP3P_MFMA_0_BASE_IDX 0 +#define regSQ_VOP3P_MFMA_1 0x037f +#define regSQ_VOP3P_MFMA_1_BASE_IDX 0 +#define regSQ_VOP3_0 0x037f +#define regSQ_VOP3_0_BASE_IDX 0 +#define regSQ_VOP3_0_SDST_ENC 0x037f +#define regSQ_VOP3_0_SDST_ENC_BASE_IDX 0 +#define regSQ_VOP3_1 0x037f +#define regSQ_VOP3_1_BASE_IDX 0 +#define regSQ_VOPC 0x037f +#define regSQ_VOPC_BASE_IDX 0 +#define regSQ_VOP_DPP 0x037f +#define regSQ_VOP_DPP_BASE_IDX 0 +#define regSQ_VOP_SDWA 0x037f +#define regSQ_VOP_SDWA_BASE_IDX 0 +#define regSQ_VOP_SDWA_SDST_ENC 0x037f +#define regSQ_VOP_SDWA_SDST_ENC_BASE_IDX 0 +#define regSQ_LB_CTR_CTRL 0x0398 +#define regSQ_LB_CTR_CTRL_BASE_IDX 0 +#define regSQ_LB_DATA0 0x0399 +#define regSQ_LB_DATA0_BASE_IDX 0 +#define regSQ_LB_DATA1 0x039a +#define regSQ_LB_DATA1_BASE_IDX 0 +#define regSQ_LB_DATA2 0x039b +#define regSQ_LB_DATA2_BASE_IDX 0 +#define regSQ_LB_DATA3 0x039c +#define regSQ_LB_DATA3_BASE_IDX 0 +#define regSQ_LB_CTR_SEL 0x039d +#define regSQ_LB_CTR_SEL_BASE_IDX 0 +#define regSQ_LB_CTR0_CU 0x039e +#define regSQ_LB_CTR0_CU_BASE_IDX 0 +#define regSQ_LB_CTR1_CU 0x039f +#define regSQ_LB_CTR1_CU_BASE_IDX 0 +#define regSQ_LB_CTR2_CU 0x03a0 +#define regSQ_LB_CTR2_CU_BASE_IDX 0 +#define regSQ_LB_CTR3_CU 0x03a1 +#define regSQ_LB_CTR3_CU_BASE_IDX 0 +#define regSQC_EDC_CNT 0x03a2 +#define regSQC_EDC_CNT_BASE_IDX 0 +#define regSQ_EDC_SEC_CNT 0x03a3 +#define regSQ_EDC_SEC_CNT_BASE_IDX 0 +#define regSQ_EDC_DED_CNT 0x03a4 +#define regSQ_EDC_DED_CNT_BASE_IDX 0 +#define regSQ_EDC_INFO 0x03a5 +#define regSQ_EDC_INFO_BASE_IDX 0 +#define regSQ_EDC_CNT 0x03a6 +#define regSQ_EDC_CNT_BASE_IDX 0 +#define regSQ_EDC_FUE_CNTL 0x03a7 +#define regSQ_EDC_FUE_CNTL_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_CMN 0x03b0 +#define regSQ_THREAD_TRACE_WORD_CMN_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_EVENT 0x03b0 +#define regSQ_THREAD_TRACE_WORD_EVENT_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_INST 0x03b0 +#define regSQ_THREAD_TRACE_WORD_INST_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x03b0 +#define regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x03b0 +#define regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_ISSUE 0x03b0 +#define regSQ_THREAD_TRACE_WORD_ISSUE_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_MISC 0x03b0 +#define regSQ_THREAD_TRACE_WORD_MISC_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x03b0 +#define regSQ_THREAD_TRACE_WORD_PERF_1_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x03b0 +#define regSQ_THREAD_TRACE_WORD_REG_1_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x03b0 +#define regSQ_THREAD_TRACE_WORD_REG_2_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x03b0 +#define regSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x03b0 +#define regSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x03b0 +#define regSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_WAVE 0x03b0 +#define regSQ_THREAD_TRACE_WORD_WAVE_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_WAVE_START 0x03b0 +#define regSQ_THREAD_TRACE_WORD_WAVE_START_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x03b1 +#define regSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x03b1 +#define regSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x03b1 +#define regSQ_THREAD_TRACE_WORD_PERF_2_OF_2_BASE_IDX 0 +#define regSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x03b1 +#define regSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_BASE_IDX 0 +#define regSQ_WREXEC_EXEC_HI 0x03b1 +#define regSQ_WREXEC_EXEC_HI_BASE_IDX 0 +#define regSQ_WREXEC_EXEC_LO 0x03b1 +#define regSQ_WREXEC_EXEC_LO_BASE_IDX 0 +#define regSQ_BUF_RSRC_WORD0 0x03c0 +#define regSQ_BUF_RSRC_WORD0_BASE_IDX 0 +#define regSQ_BUF_RSRC_WORD1 0x03c1 +#define regSQ_BUF_RSRC_WORD1_BASE_IDX 0 +#define regSQ_BUF_RSRC_WORD2 0x03c2 +#define regSQ_BUF_RSRC_WORD2_BASE_IDX 0 +#define regSQ_BUF_RSRC_WORD3 0x03c3 +#define regSQ_BUF_RSRC_WORD3_BASE_IDX 0 +#define regSQ_IMG_RSRC_WORD0 0x03c4 +#define regSQ_IMG_RSRC_WORD0_BASE_IDX 0 +#define regSQ_IMG_RSRC_WORD1 0x03c5 +#define regSQ_IMG_RSRC_WORD1_BASE_IDX 0 +#define regSQ_IMG_RSRC_WORD2 0x03c6 +#define regSQ_IMG_RSRC_WORD2_BASE_IDX 0 +#define regSQ_IMG_RSRC_WORD3 0x03c7 +#define regSQ_IMG_RSRC_WORD3_BASE_IDX 0 +#define regSQ_IMG_RSRC_WORD4 0x03c8 +#define regSQ_IMG_RSRC_WORD4_BASE_IDX 0 +#define regSQ_IMG_RSRC_WORD5 0x03c9 +#define regSQ_IMG_RSRC_WORD5_BASE_IDX 0 +#define regSQ_IMG_RSRC_WORD6 0x03ca +#define regSQ_IMG_RSRC_WORD6_BASE_IDX 0 +#define regSQ_IMG_RSRC_WORD7 0x03cb +#define regSQ_IMG_RSRC_WORD7_BASE_IDX 0 +#define regSQ_IMG_SAMP_WORD0 0x03cc +#define regSQ_IMG_SAMP_WORD0_BASE_IDX 0 +#define regSQ_IMG_SAMP_WORD1 0x03cd +#define regSQ_IMG_SAMP_WORD1_BASE_IDX 0 +#define regSQ_IMG_SAMP_WORD2 0x03ce +#define regSQ_IMG_SAMP_WORD2_BASE_IDX 0 +#define regSQ_IMG_SAMP_WORD3 0x03cf +#define regSQ_IMG_SAMP_WORD3_BASE_IDX 0 +#define regSQ_FLAT_SCRATCH_WORD0 0x03d0 +#define regSQ_FLAT_SCRATCH_WORD0_BASE_IDX 0 +#define regSQ_FLAT_SCRATCH_WORD1 0x03d1 +#define regSQ_FLAT_SCRATCH_WORD1_BASE_IDX 0 +#define regSQ_M0_GPR_IDX_WORD 0x03d2 +#define regSQ_M0_GPR_IDX_WORD_BASE_IDX 0 +#define regSQC_ICACHE_UTCL1_CNTL1 0x03d3 +#define regSQC_ICACHE_UTCL1_CNTL1_BASE_IDX 0 +#define regSQC_ICACHE_UTCL1_CNTL2 0x03d4 +#define regSQC_ICACHE_UTCL1_CNTL2_BASE_IDX 0 +#define regSQC_DCACHE_UTCL1_CNTL1 0x03d5 +#define regSQC_DCACHE_UTCL1_CNTL1_BASE_IDX 0 +#define regSQC_DCACHE_UTCL1_CNTL2 0x03d6 +#define regSQC_DCACHE_UTCL1_CNTL2_BASE_IDX 0 +#define regSQC_ICACHE_UTCL1_STATUS 0x03d7 +#define regSQC_ICACHE_UTCL1_STATUS_BASE_IDX 0 +#define regSQC_DCACHE_UTCL1_STATUS 0x03d8 +#define regSQC_DCACHE_UTCL1_STATUS_BASE_IDX 0 +#define regSQC_UE_EDC_LO 0x03d9 +#define regSQC_UE_EDC_LO_BASE_IDX 0 +#define regSQC_UE_EDC_HI 0x03da +#define regSQC_UE_EDC_HI_BASE_IDX 0 +#define regSQC_CE_EDC_LO 0x03db +#define regSQC_CE_EDC_LO_BASE_IDX 0 +#define regSQC_CE_EDC_HI 0x03dc +#define regSQC_CE_EDC_HI_BASE_IDX 0 +#define regSQ_UE_ERR_STATUS_LO 0x03dd +#define regSQ_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regSQ_UE_ERR_STATUS_HI 0x03de +#define regSQ_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regSQ_CE_ERR_STATUS_LO 0x03df +#define regSQ_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regSQ_CE_ERR_STATUS_HI 0x03e0 +#define regSQ_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regLDS_UE_ERR_STATUS_LO 0x03e1 +#define regLDS_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regLDS_UE_ERR_STATUS_HI 0x03e2 +#define regLDS_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regLDS_CE_ERR_STATUS_LO 0x03e3 +#define regLDS_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regLDS_CE_ERR_STATUS_HI 0x03e4 +#define regLDS_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regSP0_UE_ERR_STATUS_LO 0x03e5 +#define regSP0_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regSP0_UE_ERR_STATUS_HI 0x03e6 +#define regSP0_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regSP0_CE_ERR_STATUS_LO 0x03e7 +#define regSP0_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regSP0_CE_ERR_STATUS_HI 0x03e8 +#define regSP0_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regSP1_UE_ERR_STATUS_LO 0x03e9 +#define regSP1_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regSP1_UE_ERR_STATUS_HI 0x03ea +#define regSP1_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regSP1_CE_ERR_STATUS_LO 0x03eb +#define regSP1_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regSP1_CE_ERR_STATUS_HI 0x03ec +#define regSP1_CE_ERR_STATUS_HI_BASE_IDX 0 + + +// addressBlock: xcd0_gc_shsdec +// base address: 0x9000 +#define regSX_DEBUG_BUSY 0x0414 +#define regSX_DEBUG_BUSY_BASE_IDX 0 +#define regSX_DEBUG_1 0x0419 +#define regSX_DEBUG_1_BASE_IDX 0 +#define regSPI_PS_MAX_WAVE_ID 0x043a +#define regSPI_PS_MAX_WAVE_ID_BASE_IDX 0 +#define regSPI_START_PHASE 0x043b +#define regSPI_START_PHASE_BASE_IDX 0 +#define regSPI_GFX_CNTL 0x043c +#define regSPI_GFX_CNTL_BASE_IDX 0 +#define regSPI_DEBUG_READ 0x0442 +#define regSPI_DEBUG_READ_BASE_IDX 0 +#define regSPI_DSM_CNTL 0x0443 +#define regSPI_DSM_CNTL_BASE_IDX 0 +#define regSPI_DSM_CNTL2 0x0444 +#define regSPI_DSM_CNTL2_BASE_IDX 0 +#define regSPI_EDC_CNT 0x0445 +#define regSPI_EDC_CNT_BASE_IDX 0 +#define regSPI_UE_ERR_STATUS_LO 0x0446 +#define regSPI_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regSPI_UE_ERR_STATUS_HI 0x0447 +#define regSPI_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regSPI_CE_ERR_STATUS_LO 0x0448 +#define regSPI_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regSPI_CE_ERR_STATUS_HI 0x0449 +#define regSPI_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regSPI_DEBUG_BUSY 0x0450 +#define regSPI_DEBUG_BUSY_BASE_IDX 0 +#define regSPI_CONFIG_PS_CU_EN 0x0452 +#define regSPI_CONFIG_PS_CU_EN_BASE_IDX 0 +#define regSPI_WF_LIFETIME_CNTL 0x04aa +#define regSPI_WF_LIFETIME_CNTL_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_0 0x04ab +#define regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_1 0x04ac +#define regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_2 0x04ad +#define regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_3 0x04ae +#define regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_4 0x04af +#define regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_5 0x04b0 +#define regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_6 0x04b1 +#define regSPI_WF_LIFETIME_LIMIT_6_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_7 0x04b2 +#define regSPI_WF_LIFETIME_LIMIT_7_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_8 0x04b3 +#define regSPI_WF_LIFETIME_LIMIT_8_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_9 0x04b4 +#define regSPI_WF_LIFETIME_LIMIT_9_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_0 0x04b5 +#define regSPI_WF_LIFETIME_STATUS_0_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_1 0x04b6 +#define regSPI_WF_LIFETIME_STATUS_1_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_2 0x04b7 +#define regSPI_WF_LIFETIME_STATUS_2_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_3 0x04b8 +#define regSPI_WF_LIFETIME_STATUS_3_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_4 0x04b9 +#define regSPI_WF_LIFETIME_STATUS_4_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_5 0x04ba +#define regSPI_WF_LIFETIME_STATUS_5_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_6 0x04bb +#define regSPI_WF_LIFETIME_STATUS_6_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_7 0x04bc +#define regSPI_WF_LIFETIME_STATUS_7_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_8 0x04bd +#define regSPI_WF_LIFETIME_STATUS_8_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_9 0x04be +#define regSPI_WF_LIFETIME_STATUS_9_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_10 0x04bf +#define regSPI_WF_LIFETIME_STATUS_10_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_11 0x04c0 +#define regSPI_WF_LIFETIME_STATUS_11_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_12 0x04c1 +#define regSPI_WF_LIFETIME_STATUS_12_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_13 0x04c2 +#define regSPI_WF_LIFETIME_STATUS_13_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_14 0x04c3 +#define regSPI_WF_LIFETIME_STATUS_14_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_15 0x04c4 +#define regSPI_WF_LIFETIME_STATUS_15_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_16 0x04c5 +#define regSPI_WF_LIFETIME_STATUS_16_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_17 0x04c6 +#define regSPI_WF_LIFETIME_STATUS_17_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_18 0x04c7 +#define regSPI_WF_LIFETIME_STATUS_18_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_19 0x04c8 +#define regSPI_WF_LIFETIME_STATUS_19_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_20 0x04c9 +#define regSPI_WF_LIFETIME_STATUS_20_BASE_IDX 0 +#define regSPI_WF_LIFETIME_DEBUG 0x04ca +#define regSPI_WF_LIFETIME_DEBUG_BASE_IDX 0 +#define regSPI_LB_CTR_CTRL 0x04d4 +#define regSPI_LB_CTR_CTRL_BASE_IDX 0 +#define regSPI_LB_CU_MASK 0x04d5 +#define regSPI_LB_CU_MASK_BASE_IDX 0 +#define regSPI_LB_DATA_REG 0x04d6 +#define regSPI_LB_DATA_REG_BASE_IDX 0 +#define regSPI_PG_ENABLE_STATIC_CU_MASK 0x04d7 +#define regSPI_PG_ENABLE_STATIC_CU_MASK_BASE_IDX 0 +#define regSPI_GDS_CREDITS 0x04d8 +#define regSPI_GDS_CREDITS_BASE_IDX 0 +#define regSPI_SX_EXPORT_BUFFER_SIZES 0x04d9 +#define regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX 0 +#define regSPI_SX_SCOREBOARD_BUFFER_SIZES 0x04da +#define regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_STATUS 0x04db +#define regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_0 0x04dc +#define regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_1 0x04dd +#define regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_2 0x04de +#define regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_3 0x04df +#define regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_4 0x04e0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_4_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_5 0x04e1 +#define regSPI_CSQ_WF_ACTIVE_COUNT_5_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_6 0x04e2 +#define regSPI_CSQ_WF_ACTIVE_COUNT_6_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_7 0x04e3 +#define regSPI_CSQ_WF_ACTIVE_COUNT_7_BASE_IDX 0 +#define regSPI_LB_DATA_WAVES 0x04e4 +#define regSPI_LB_DATA_WAVES_BASE_IDX 0 +#define regSPI_LB_DATA_PERCU_WAVE_HSGS 0x04e5 +#define regSPI_LB_DATA_PERCU_WAVE_HSGS_BASE_IDX 0 +#define regSPI_LB_DATA_PERCU_WAVE_VSPS 0x04e6 +#define regSPI_LB_DATA_PERCU_WAVE_VSPS_BASE_IDX 0 +#define regSPI_LB_DATA_PERCU_WAVE_CS 0x04e7 +#define regSPI_LB_DATA_PERCU_WAVE_CS_BASE_IDX 0 +#define regSPIS_DEBUG_READ 0x04ea +#define regSPIS_DEBUG_READ_BASE_IDX 0 +#define regBCI_DEBUG_READ 0x04eb +#define regBCI_DEBUG_READ_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSBA_LO 0x04ec +#define regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSBA_HI 0x04ed +#define regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSMA_LO 0x04ee +#define regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSMA_HI 0x04ef +#define regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_GPR_MIN 0x04f0 +#define regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSBA_LO 0x04f1 +#define regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSBA_HI 0x04f2 +#define regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSMA_LO 0x04f3 +#define regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSMA_HI 0x04f4 +#define regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_GPR_MIN 0x04f5 +#define regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 + + +// addressBlock: xcd0_gc_tpdec +// base address: 0x9400 +#define regTD_CNTL 0x0525 +#define regTD_CNTL_BASE_IDX 0 +#define regTD_STATUS 0x0526 +#define regTD_STATUS_BASE_IDX 0 +#define regTD_POWER_CNTL 0x052a +#define regTD_POWER_CNTL_BASE_IDX 0 +#define regTD_UE_EDC_LO 0x052b +#define regTD_UE_EDC_LO_BASE_IDX 0 +#define regTD_UE_EDC_HI 0x052c +#define regTD_UE_EDC_HI_BASE_IDX 0 +#define regTD_CE_EDC_LO 0x052d +#define regTD_CE_EDC_LO_BASE_IDX 0 +#define regTD_CE_EDC_HI 0x052e +#define regTD_CE_EDC_HI_BASE_IDX 0 +#define regTD_DSM_CNTL 0x052f +#define regTD_DSM_CNTL_BASE_IDX 0 +#define regTD_DSM_CNTL2 0x0530 +#define regTD_DSM_CNTL2_BASE_IDX 0 +#define regTD_SCRATCH 0x0533 +#define regTD_SCRATCH_BASE_IDX 0 +#define regTA_POWER_CNTL 0x0540 +#define regTA_POWER_CNTL_BASE_IDX 0 +#define regTA_CNTL 0x0541 +#define regTA_CNTL_BASE_IDX 0 +#define regTA_CNTL_AUX 0x0542 +#define regTA_CNTL_AUX_BASE_IDX 0 +#define regTA_FEATURE_CNTL 0x0543 +#define regTA_FEATURE_CNTL_BASE_IDX 0 +#define regTA_STATUS 0x0548 +#define regTA_STATUS_BASE_IDX 0 +#define regTA_SCRATCH 0x0564 +#define regTA_SCRATCH_BASE_IDX 0 +#define regTA_DSM_CNTL 0x0584 +#define regTA_DSM_CNTL_BASE_IDX 0 +#define regTA_DSM_CNTL2 0x0585 +#define regTA_DSM_CNTL2_BASE_IDX 0 +#define regTA_UE_EDC_LO 0x0587 +#define regTA_UE_EDC_LO_BASE_IDX 0 +#define regTA_UE_EDC_HI 0x0588 +#define regTA_UE_EDC_HI_BASE_IDX 0 +#define regTA_CE_EDC_LO 0x0589 +#define regTA_CE_EDC_LO_BASE_IDX 0 +#define regTA_CE_EDC_HI 0x058a +#define regTA_CE_EDC_HI_BASE_IDX 0 + + +// addressBlock: xcd0_gc_gdsdec +// base address: 0x9700 +#define regGDS_CONFIG 0x05c0 +#define regGDS_CONFIG_BASE_IDX 0 +#define regGDS_CNTL_STATUS 0x05c1 +#define regGDS_CNTL_STATUS_BASE_IDX 0 +#define regGDS_ENHANCE2 0x05c2 +#define regGDS_ENHANCE2_BASE_IDX 0 +#define regGDS_PROTECTION_FAULT 0x05c3 +#define regGDS_PROTECTION_FAULT_BASE_IDX 0 +#define regGDS_VM_PROTECTION_FAULT 0x05c4 +#define regGDS_VM_PROTECTION_FAULT_BASE_IDX 0 +#define regGDS_EDC_CNT 0x05c5 +#define regGDS_EDC_CNT_BASE_IDX 0 +#define regGDS_EDC_GRBM_CNT 0x05c6 +#define regGDS_EDC_GRBM_CNT_BASE_IDX 0 +#define regGDS_EDC_OA_DED 0x05c7 +#define regGDS_EDC_OA_DED_BASE_IDX 0 +#define regGDS_DSM_CNTL 0x05ca +#define regGDS_DSM_CNTL_BASE_IDX 0 +#define regGDS_EDC_OA_PHY_CNT 0x05cb +#define regGDS_EDC_OA_PHY_CNT_BASE_IDX 0 +#define regGDS_EDC_OA_PIPE_CNT 0x05cc +#define regGDS_EDC_OA_PIPE_CNT_BASE_IDX 0 +#define regGDS_DSM_CNTL2 0x05cd +#define regGDS_DSM_CNTL2_BASE_IDX 0 +#define regGDS_WD_GDS_CSB 0x05ce +#define regGDS_WD_GDS_CSB_BASE_IDX 0 +#define regGDS_UE_ERR_STATUS_LO 0x05cf +#define regGDS_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regGDS_UE_ERR_STATUS_HI 0x05d0 +#define regGDS_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regGDS_CE_ERR_STATUS_LO 0x05d1 +#define regGDS_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regGDS_CE_ERR_STATUS_HI 0x05d2 +#define regGDS_CE_ERR_STATUS_HI_BASE_IDX 0 + + +// addressBlock: xcd0_gc_rbdec +// base address: 0x9800 +#define regDB_DEBUG 0x060c +#define regDB_DEBUG_BASE_IDX 0 +#define regDB_DEBUG2 0x060d +#define regDB_DEBUG2_BASE_IDX 0 +#define regDB_DEBUG3 0x060e +#define regDB_DEBUG3_BASE_IDX 0 +#define regDB_DEBUG4 0x060f +#define regDB_DEBUG4_BASE_IDX 0 +#define regDB_CREDIT_LIMIT 0x0614 +#define regDB_CREDIT_LIMIT_BASE_IDX 0 +#define regDB_WATERMARKS 0x0615 +#define regDB_WATERMARKS_BASE_IDX 0 +#define regDB_SUBTILE_CONTROL 0x0616 +#define regDB_SUBTILE_CONTROL_BASE_IDX 0 +#define regDB_FREE_CACHELINES 0x0617 +#define regDB_FREE_CACHELINES_BASE_IDX 0 +#define regDB_FIFO_DEPTH1 0x0618 +#define regDB_FIFO_DEPTH1_BASE_IDX 0 +#define regDB_FIFO_DEPTH2 0x0619 +#define regDB_FIFO_DEPTH2_BASE_IDX 0 +#define regDB_EXCEPTION_CONTROL 0x061a +#define regDB_EXCEPTION_CONTROL_BASE_IDX 0 +#define regDB_RING_CONTROL 0x061b +#define regDB_RING_CONTROL_BASE_IDX 0 +#define regDB_MEM_ARB_WATERMARKS 0x061c +#define regDB_MEM_ARB_WATERMARKS_BASE_IDX 0 +#define regDB_RMI_CACHE_POLICY 0x061e +#define regDB_RMI_CACHE_POLICY_BASE_IDX 0 +#define regDB_DFSM_CONFIG 0x0630 +#define regDB_DFSM_CONFIG_BASE_IDX 0 +#define regDB_DFSM_WATERMARK 0x0631 +#define regDB_DFSM_WATERMARK_BASE_IDX 0 +#define regDB_DFSM_TILES_IN_FLIGHT 0x0632 +#define regDB_DFSM_TILES_IN_FLIGHT_BASE_IDX 0 +#define regDB_DFSM_PRIMS_IN_FLIGHT 0x0633 +#define regDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX 0 +#define regDB_DFSM_WATCHDOG 0x0634 +#define regDB_DFSM_WATCHDOG_BASE_IDX 0 +#define regDB_DFSM_FLUSH_ENABLE 0x0635 +#define regDB_DFSM_FLUSH_ENABLE_BASE_IDX 0 +#define regDB_DFSM_FLUSH_AUX_EVENT 0x0636 +#define regDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX 0 +#define regCC_RB_REDUNDANCY 0x063c +#define regCC_RB_REDUNDANCY_BASE_IDX 0 +#define regCC_RB_BACKEND_DISABLE 0x063d +#define regCC_RB_BACKEND_DISABLE_BASE_IDX 0 +#define regGB_ADDR_CONFIG 0x063e +#define regGB_ADDR_CONFIG_BASE_IDX 0 +#define regGB_BACKEND_MAP 0x063f +#define regGB_BACKEND_MAP_BASE_IDX 0 +#define regGB_GPU_ID 0x0640 +#define regGB_GPU_ID_BASE_IDX 0 +#define regCC_RB_DAISY_CHAIN 0x0641 +#define regCC_RB_DAISY_CHAIN_BASE_IDX 0 +#define regGB_ADDR_CONFIG_READ 0x0642 +#define regGB_ADDR_CONFIG_READ_BASE_IDX 0 +#define regGB_TILE_MODE0 0x0644 +#define regGB_TILE_MODE0_BASE_IDX 0 +#define regGB_TILE_MODE1 0x0645 +#define regGB_TILE_MODE1_BASE_IDX 0 +#define regGB_TILE_MODE2 0x0646 +#define regGB_TILE_MODE2_BASE_IDX 0 +#define regGB_TILE_MODE3 0x0647 +#define regGB_TILE_MODE3_BASE_IDX 0 +#define regGB_TILE_MODE4 0x0648 +#define regGB_TILE_MODE4_BASE_IDX 0 +#define regGB_TILE_MODE5 0x0649 +#define regGB_TILE_MODE5_BASE_IDX 0 +#define regGB_TILE_MODE6 0x064a +#define regGB_TILE_MODE6_BASE_IDX 0 +#define regGB_TILE_MODE7 0x064b +#define regGB_TILE_MODE7_BASE_IDX 0 +#define regGB_TILE_MODE8 0x064c +#define regGB_TILE_MODE8_BASE_IDX 0 +#define regGB_TILE_MODE9 0x064d +#define regGB_TILE_MODE9_BASE_IDX 0 +#define regGB_TILE_MODE10 0x064e +#define regGB_TILE_MODE10_BASE_IDX 0 +#define regGB_TILE_MODE11 0x064f +#define regGB_TILE_MODE11_BASE_IDX 0 +#define regGB_TILE_MODE12 0x0650 +#define regGB_TILE_MODE12_BASE_IDX 0 +#define regGB_TILE_MODE13 0x0651 +#define regGB_TILE_MODE13_BASE_IDX 0 +#define regGB_TILE_MODE14 0x0652 +#define regGB_TILE_MODE14_BASE_IDX 0 +#define regGB_TILE_MODE15 0x0653 +#define regGB_TILE_MODE15_BASE_IDX 0 +#define regGB_TILE_MODE16 0x0654 +#define regGB_TILE_MODE16_BASE_IDX 0 +#define regGB_TILE_MODE17 0x0655 +#define regGB_TILE_MODE17_BASE_IDX 0 +#define regGB_TILE_MODE18 0x0656 +#define regGB_TILE_MODE18_BASE_IDX 0 +#define regGB_TILE_MODE19 0x0657 +#define regGB_TILE_MODE19_BASE_IDX 0 +#define regGB_TILE_MODE20 0x0658 +#define regGB_TILE_MODE20_BASE_IDX 0 +#define regGB_TILE_MODE21 0x0659 +#define regGB_TILE_MODE21_BASE_IDX 0 +#define regGB_TILE_MODE22 0x065a +#define regGB_TILE_MODE22_BASE_IDX 0 +#define regGB_TILE_MODE23 0x065b +#define regGB_TILE_MODE23_BASE_IDX 0 +#define regGB_TILE_MODE24 0x065c +#define regGB_TILE_MODE24_BASE_IDX 0 +#define regGB_TILE_MODE25 0x065d +#define regGB_TILE_MODE25_BASE_IDX 0 +#define regGB_TILE_MODE26 0x065e +#define regGB_TILE_MODE26_BASE_IDX 0 +#define regGB_TILE_MODE27 0x065f +#define regGB_TILE_MODE27_BASE_IDX 0 +#define regGB_TILE_MODE28 0x0660 +#define regGB_TILE_MODE28_BASE_IDX 0 +#define regGB_TILE_MODE29 0x0661 +#define regGB_TILE_MODE29_BASE_IDX 0 +#define regGB_TILE_MODE30 0x0662 +#define regGB_TILE_MODE30_BASE_IDX 0 +#define regGB_TILE_MODE31 0x0663 +#define regGB_TILE_MODE31_BASE_IDX 0 +#define regGB_MACROTILE_MODE0 0x0664 +#define regGB_MACROTILE_MODE0_BASE_IDX 0 +#define regGB_MACROTILE_MODE1 0x0665 +#define regGB_MACROTILE_MODE1_BASE_IDX 0 +#define regGB_MACROTILE_MODE2 0x0666 +#define regGB_MACROTILE_MODE2_BASE_IDX 0 +#define regGB_MACROTILE_MODE3 0x0667 +#define regGB_MACROTILE_MODE3_BASE_IDX 0 +#define regGB_MACROTILE_MODE4 0x0668 +#define regGB_MACROTILE_MODE4_BASE_IDX 0 +#define regGB_MACROTILE_MODE5 0x0669 +#define regGB_MACROTILE_MODE5_BASE_IDX 0 +#define regGB_MACROTILE_MODE6 0x066a +#define regGB_MACROTILE_MODE6_BASE_IDX 0 +#define regGB_MACROTILE_MODE7 0x066b +#define regGB_MACROTILE_MODE7_BASE_IDX 0 +#define regGB_MACROTILE_MODE8 0x066c +#define regGB_MACROTILE_MODE8_BASE_IDX 0 +#define regGB_MACROTILE_MODE9 0x066d +#define regGB_MACROTILE_MODE9_BASE_IDX 0 +#define regGB_MACROTILE_MODE10 0x066e +#define regGB_MACROTILE_MODE10_BASE_IDX 0 +#define regGB_MACROTILE_MODE11 0x066f +#define regGB_MACROTILE_MODE11_BASE_IDX 0 +#define regGB_MACROTILE_MODE12 0x0670 +#define regGB_MACROTILE_MODE12_BASE_IDX 0 +#define regGB_MACROTILE_MODE13 0x0671 +#define regGB_MACROTILE_MODE13_BASE_IDX 0 +#define regGB_MACROTILE_MODE14 0x0672 +#define regGB_MACROTILE_MODE14_BASE_IDX 0 +#define regGB_MACROTILE_MODE15 0x0673 +#define regGB_MACROTILE_MODE15_BASE_IDX 0 +#define regCB_HW_CONTROL 0x0680 +#define regCB_HW_CONTROL_BASE_IDX 0 +#define regCB_HW_CONTROL_1 0x0681 +#define regCB_HW_CONTROL_1_BASE_IDX 0 +#define regCB_HW_CONTROL_2 0x0682 +#define regCB_HW_CONTROL_2_BASE_IDX 0 +#define regCB_HW_CONTROL_3 0x0683 +#define regCB_HW_CONTROL_3_BASE_IDX 0 +#define regCB_HW_MEM_ARBITER_RD 0x0686 +#define regCB_HW_MEM_ARBITER_RD_BASE_IDX 0 +#define regCB_HW_MEM_ARBITER_WR 0x0687 +#define regCB_HW_MEM_ARBITER_WR_BASE_IDX 0 +#define regCB_DCC_CONFIG 0x0688 +#define regCB_DCC_CONFIG_BASE_IDX 0 +#define regGC_USER_RB_REDUNDANCY 0x06de +#define regGC_USER_RB_REDUNDANCY_BASE_IDX 0 +#define regGC_USER_RB_BACKEND_DISABLE 0x06df +#define regGC_USER_RB_BACKEND_DISABLE_BASE_IDX 0 + + +// addressBlock: xcd0_gc_ea_gceadec +// base address: 0xa800 +#define regGCEA_DRAM_RD_CLI2GRP_MAP0 0x0a00 +#define regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regGCEA_DRAM_RD_CLI2GRP_MAP1 0x0a01 +#define regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regGCEA_DRAM_WR_CLI2GRP_MAP0 0x0a02 +#define regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regGCEA_DRAM_WR_CLI2GRP_MAP1 0x0a03 +#define regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regGCEA_DRAM_RD_GRP2VC_MAP 0x0a04 +#define regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 +#define regGCEA_DRAM_WR_GRP2VC_MAP 0x0a05 +#define regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 +#define regGCEA_DRAM_RD_LAZY 0x0a06 +#define regGCEA_DRAM_RD_LAZY_BASE_IDX 0 +#define regGCEA_DRAM_WR_LAZY 0x0a07 +#define regGCEA_DRAM_WR_LAZY_BASE_IDX 0 +#define regGCEA_DRAM_RD_CAM_CNTL 0x0a08 +#define regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX 0 +#define regGCEA_DRAM_WR_CAM_CNTL 0x0a09 +#define regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX 0 +#define regGCEA_DRAM_PAGE_BURST 0x0a0a +#define regGCEA_DRAM_PAGE_BURST_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_AGE 0x0a0b +#define regGCEA_DRAM_RD_PRI_AGE_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_AGE 0x0a0c +#define regGCEA_DRAM_WR_PRI_AGE_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_QUEUING 0x0a0d +#define regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_QUEUING 0x0a0e +#define regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_FIXED 0x0a0f +#define regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_FIXED 0x0a10 +#define regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_URGENCY 0x0a11 +#define regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_URGENCY 0x0a12 +#define regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI1 0x0a13 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI2 0x0a14 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI3 0x0a15 +#define regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI1 0x0a16 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI2 0x0a17 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI3 0x0a18 +#define regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regGCEA_IO_RD_CLI2GRP_MAP0 0x0ad5 +#define regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 +#define regGCEA_IO_RD_CLI2GRP_MAP1 0x0ad6 +#define regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 +#define regGCEA_IO_WR_CLI2GRP_MAP0 0x0ad7 +#define regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 +#define regGCEA_IO_WR_CLI2GRP_MAP1 0x0ad8 +#define regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 +#define regGCEA_IO_RD_COMBINE_FLUSH 0x0ad9 +#define regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX 0 +#define regGCEA_IO_WR_COMBINE_FLUSH 0x0ada +#define regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX 0 +#define regGCEA_IO_GROUP_BURST 0x0adb +#define regGCEA_IO_GROUP_BURST_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_AGE 0x0adc +#define regGCEA_IO_RD_PRI_AGE_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_AGE 0x0add +#define regGCEA_IO_WR_PRI_AGE_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_QUEUING 0x0ade +#define regGCEA_IO_RD_PRI_QUEUING_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_QUEUING 0x0adf +#define regGCEA_IO_WR_PRI_QUEUING_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_FIXED 0x0ae0 +#define regGCEA_IO_RD_PRI_FIXED_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_FIXED 0x0ae1 +#define regGCEA_IO_WR_PRI_FIXED_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_URGENCY 0x0ae2 +#define regGCEA_IO_RD_PRI_URGENCY_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_URGENCY 0x0ae3 +#define regGCEA_IO_WR_PRI_URGENCY_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_URGENCY_MASKING 0x0ae4 +#define regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_URGENCY_MASKING 0x0ae5 +#define regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_QUANT_PRI1 0x0ae6 +#define regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_QUANT_PRI2 0x0ae7 +#define regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 +#define regGCEA_IO_RD_PRI_QUANT_PRI3 0x0ae8 +#define regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_QUANT_PRI1 0x0ae9 +#define regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_QUANT_PRI2 0x0aea +#define regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 +#define regGCEA_IO_WR_PRI_QUANT_PRI3 0x0aeb +#define regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 +#define regGCEA_SDP_ARB_DRAM 0x0aec +#define regGCEA_SDP_ARB_DRAM_BASE_IDX 0 +#define regGCEA_SDP_ARB_FINAL 0x0aee +#define regGCEA_SDP_ARB_FINAL_BASE_IDX 0 +#define regGCEA_SDP_DRAM_PRIORITY 0x0aef +#define regGCEA_SDP_DRAM_PRIORITY_BASE_IDX 0 +#define regGCEA_SDP_IO_PRIORITY 0x0af1 +#define regGCEA_SDP_IO_PRIORITY_BASE_IDX 0 +#define regGCEA_SDP_CREDITS 0x0af2 +#define regGCEA_SDP_CREDITS_BASE_IDX 0 +#define regGCEA_SDP_TAG_RESERVE0 0x0af3 +#define regGCEA_SDP_TAG_RESERVE0_BASE_IDX 0 +#define regGCEA_SDP_TAG_RESERVE1 0x0af4 +#define regGCEA_SDP_TAG_RESERVE1_BASE_IDX 0 +#define regGCEA_SDP_VCC_RESERVE0 0x0af5 +#define regGCEA_SDP_VCC_RESERVE0_BASE_IDX 0 +#define regGCEA_SDP_VCC_RESERVE1 0x0af6 +#define regGCEA_SDP_VCC_RESERVE1_BASE_IDX 0 +#define regGCEA_SDP_VCD_RESERVE0 0x0af7 +#define regGCEA_SDP_VCD_RESERVE0_BASE_IDX 0 +#define regGCEA_SDP_VCD_RESERVE1 0x0af8 +#define regGCEA_SDP_VCD_RESERVE1_BASE_IDX 0 +#define regGCEA_SDP_REQ_CNTL 0x0af9 +#define regGCEA_SDP_REQ_CNTL_BASE_IDX 0 +#define regGCEA_MISC 0x0afa +#define regGCEA_MISC_BASE_IDX 0 +#define regGCEA_LATENCY_SAMPLING 0x0afb +#define regGCEA_LATENCY_SAMPLING_BASE_IDX 0 +#define regGCEA_PERFCOUNTER_LO 0x0afc +#define regGCEA_PERFCOUNTER_LO_BASE_IDX 0 +#define regGCEA_PERFCOUNTER_HI 0x0afd +#define regGCEA_PERFCOUNTER_HI_BASE_IDX 0 +#define regGCEA_PERFCOUNTER0_CFG 0x0afe +#define regGCEA_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regGCEA_PERFCOUNTER1_CFG 0x0aff +#define regGCEA_PERFCOUNTER1_CFG_BASE_IDX 0 + + +// addressBlock: xcd0_gc_ea_gceadec2 +// base address: 0x9c00 +#define regGCEA_PERFCOUNTER_RSLT_CNTL 0x0700 +#define regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regGCEA_MAM_CTRL 0x0701 +#define regGCEA_MAM_CTRL_BASE_IDX 0 +#define regGCEA_MAM_CTRL2 0x0702 +#define regGCEA_MAM_CTRL2_BASE_IDX 0 +#define regGCEA_UE_ERR_STATUS_LO 0x0706 +#define regGCEA_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regGCEA_UE_ERR_STATUS_HI 0x0707 +#define regGCEA_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regGCEA_DSM_CNTL 0x0708 +#define regGCEA_DSM_CNTL_BASE_IDX 0 +#define regGCEA_DSM_CNTLA 0x0709 +#define regGCEA_DSM_CNTLA_BASE_IDX 0 +#define regGCEA_DSM_CNTLB 0x070a +#define regGCEA_DSM_CNTLB_BASE_IDX 0 +#define regGCEA_DSM_CNTL2 0x070b +#define regGCEA_DSM_CNTL2_BASE_IDX 0 +#define regGCEA_DSM_CNTL2A 0x070c +#define regGCEA_DSM_CNTL2A_BASE_IDX 0 +#define regGCEA_DSM_CNTL2B 0x070d +#define regGCEA_DSM_CNTL2B_BASE_IDX 0 +#define regGCEA_TCC_XBR_CREDITS 0x070e +#define regGCEA_TCC_XBR_CREDITS_BASE_IDX 0 +#define regGCEA_TCC_XBR_MAXBURST 0x070f +#define regGCEA_TCC_XBR_MAXBURST_BASE_IDX 0 +#define regGCEA_PROBE_CNTL 0x0710 +#define regGCEA_PROBE_CNTL_BASE_IDX 0 +#define regGCEA_PROBE_MAP 0x0711 +#define regGCEA_PROBE_MAP_BASE_IDX 0 +#define regGCEA_ERR_STATUS 0x0712 +#define regGCEA_ERR_STATUS_BASE_IDX 0 +#define regGCEA_MISC2 0x0713 +#define regGCEA_MISC2_BASE_IDX 0 +#define regGCEA_SDP_BACKDOOR_CMDCREDITS0 0x0715 +#define regGCEA_SDP_BACKDOOR_CMDCREDITS0_BASE_IDX 0 +#define regGCEA_SDP_BACKDOOR_CMDCREDITS1 0x0716 +#define regGCEA_SDP_BACKDOOR_CMDCREDITS1_BASE_IDX 0 +#define regGCEA_SDP_BACKDOOR_DATACREDITS0 0x0717 +#define regGCEA_SDP_BACKDOOR_DATACREDITS0_BASE_IDX 0 +#define regGCEA_SDP_BACKDOOR_DATACREDITS1 0x0718 +#define regGCEA_SDP_BACKDOOR_DATACREDITS1_BASE_IDX 0 +#define regGCEA_SDP_BACKDOOR_MISCCREDITS 0x0719 +#define regGCEA_SDP_BACKDOOR_MISCCREDITS_BASE_IDX 0 +#define regGCEA_CE_ERR_STATUS_LO 0x071b +#define regGCEA_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regGCEA_CE_ERR_STATUS_HI 0x071d +#define regGCEA_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regGCEA_SDP_ENABLE 0x071f +#define regGCEA_SDP_ENABLE_BASE_IDX 0 + + +// addressBlock: xcd0_gc_ea_pwrdec +// base address: 0x3c000 +#define regGCEA_ICG_CTRL 0x50c4 +#define regGCEA_ICG_CTRL_BASE_IDX 1 + + +// addressBlock: xcd0_gc_rmi_rmidec +// base address: 0x9e00 +#define regRMI_GENERAL_CNTL 0x0780 +#define regRMI_GENERAL_CNTL_BASE_IDX 0 +#define regRMI_GENERAL_CNTL1 0x0781 +#define regRMI_GENERAL_CNTL1_BASE_IDX 0 +#define regRMI_GENERAL_STATUS 0x0782 +#define regRMI_GENERAL_STATUS_BASE_IDX 0 +#define regRMI_SUBBLOCK_STATUS0 0x0783 +#define regRMI_SUBBLOCK_STATUS0_BASE_IDX 0 +#define regRMI_SUBBLOCK_STATUS1 0x0784 +#define regRMI_SUBBLOCK_STATUS1_BASE_IDX 0 +#define regRMI_SUBBLOCK_STATUS2 0x0785 +#define regRMI_SUBBLOCK_STATUS2_BASE_IDX 0 +#define regRMI_SUBBLOCK_STATUS3 0x0786 +#define regRMI_SUBBLOCK_STATUS3_BASE_IDX 0 +#define regRMI_XBAR_CONFIG 0x0787 +#define regRMI_XBAR_CONFIG_BASE_IDX 0 +#define regRMI_PROBE_POP_LOGIC_CNTL 0x0788 +#define regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX 0 +#define regRMI_UTC_XNACK_N_MISC_CNTL 0x0789 +#define regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX 0 +#define regRMI_DEMUX_CNTL 0x078a +#define regRMI_DEMUX_CNTL_BASE_IDX 0 +#define regRMI_UTCL1_CNTL1 0x078b +#define regRMI_UTCL1_CNTL1_BASE_IDX 0 +#define regRMI_UTCL1_CNTL2 0x078c +#define regRMI_UTCL1_CNTL2_BASE_IDX 0 +#define regRMI_UTC_UNIT_CONFIG 0x078d +#define regRMI_UTC_UNIT_CONFIG_BASE_IDX 0 +#define regRMI_TCIW_FORMATTER0_CNTL 0x078e +#define regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX 0 +#define regRMI_TCIW_FORMATTER1_CNTL 0x078f +#define regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX 0 +#define regRMI_SCOREBOARD_CNTL 0x0790 +#define regRMI_SCOREBOARD_CNTL_BASE_IDX 0 +#define regRMI_SCOREBOARD_STATUS0 0x0791 +#define regRMI_SCOREBOARD_STATUS0_BASE_IDX 0 +#define regRMI_SCOREBOARD_STATUS1 0x0792 +#define regRMI_SCOREBOARD_STATUS1_BASE_IDX 0 +#define regRMI_SCOREBOARD_STATUS2 0x0793 +#define regRMI_SCOREBOARD_STATUS2_BASE_IDX 0 +#define regRMI_XBAR_ARBITER_CONFIG 0x0794 +#define regRMI_XBAR_ARBITER_CONFIG_BASE_IDX 0 +#define regRMI_XBAR_ARBITER_CONFIG_1 0x0795 +#define regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX 0 +#define regRMI_CLOCK_CNTRL 0x0796 +#define regRMI_CLOCK_CNTRL_BASE_IDX 0 +#define regRMI_UTCL1_STATUS 0x0797 +#define regRMI_UTCL1_STATUS_BASE_IDX 0 +#define regRMI_XNACK_DEBUG 0x079d +#define regRMI_XNACK_DEBUG_BASE_IDX 0 +#define regRMI_SPARE 0x079e +#define regRMI_SPARE_BASE_IDX 0 +#define regRMI_SPARE_1 0x079f +#define regRMI_SPARE_1_BASE_IDX 0 +#define regRMI_SPARE_2 0x07a0 +#define regRMI_SPARE_2_BASE_IDX 0 + + +// addressBlock: xcd0_gc_utcl2_atcl2dec +// base address: 0xa000 +#define regATC_L2_CNTL 0x0800 +#define regATC_L2_CNTL_BASE_IDX 0 +#define regATC_L2_CNTL2 0x0801 +#define regATC_L2_CNTL2_BASE_IDX 0 +#define regATC_L2_CACHE_DATA0 0x0804 +#define regATC_L2_CACHE_DATA0_BASE_IDX 0 +#define regATC_L2_CACHE_DATA1 0x0805 +#define regATC_L2_CACHE_DATA1_BASE_IDX 0 +#define regATC_L2_CACHE_DATA2 0x0806 +#define regATC_L2_CACHE_DATA2_BASE_IDX 0 +#define regATC_L2_CACHE_DATA3 0x0807 +#define regATC_L2_CACHE_DATA3_BASE_IDX 0 +#define regATC_L2_CNTL3 0x0808 +#define regATC_L2_CNTL3_BASE_IDX 0 +#define regATC_L2_STATUS 0x0809 +#define regATC_L2_STATUS_BASE_IDX 0 +#define regATC_L2_STATUS2 0x080a +#define regATC_L2_STATUS2_BASE_IDX 0 +#define regATC_L2_MISC_CG 0x080b +#define regATC_L2_MISC_CG_BASE_IDX 0 +#define regATC_L2_MEM_POWER_LS 0x080c +#define regATC_L2_MEM_POWER_LS_BASE_IDX 0 +#define regATC_L2_CGTT_CLK_CTRL 0x080d +#define regATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 +#define regATC_L2_CACHE_4K_DSM_INDEX 0x080f +#define regATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX 0 +#define regATC_L2_CACHE_32K_DSM_INDEX 0x0810 +#define regATC_L2_CACHE_32K_DSM_INDEX_BASE_IDX 0 +#define regATC_L2_CACHE_2M_DSM_INDEX 0x0811 +#define regATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX 0 +#define regATC_L2_CACHE_4K_DSM_CNTL 0x0812 +#define regATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX 0 +#define regATC_L2_CACHE_32K_DSM_CNTL 0x0813 +#define regATC_L2_CACHE_32K_DSM_CNTL_BASE_IDX 0 +#define regATC_L2_CACHE_2M_DSM_CNTL 0x0814 +#define regATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX 0 +#define regATC_L2_CNTL4 0x0815 +#define regATC_L2_CNTL4_BASE_IDX 0 +#define regATC_L2_MM_GROUP_RT_CLASSES 0x0816 +#define regATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 +#define regATC_L2_UE_ERR_STATUS_LO 0x081a +#define regATC_L2_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regATC_L2_UE_ERR_STATUS_HI 0x081b +#define regATC_L2_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regATC_L2_CE_ERR_STATUS_LO 0x081c +#define regATC_L2_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regATC_L2_CE_ERR_STATUS_HI 0x081d +#define regATC_L2_CE_ERR_STATUS_HI_BASE_IDX 0 + + +// addressBlock: xcd0_gc_utcl2_vml2pfdec +// base address: 0xa080 +#define regVM_L2_CNTL 0x0820 +#define regVM_L2_CNTL_BASE_IDX 0 +#define regVM_L2_CNTL2 0x0821 +#define regVM_L2_CNTL2_BASE_IDX 0 +#define regVM_L2_CNTL3 0x0822 +#define regVM_L2_CNTL3_BASE_IDX 0 +#define regVM_L2_STATUS 0x0823 +#define regVM_L2_STATUS_BASE_IDX 0 +#define regVM_DUMMY_PAGE_FAULT_CNTL 0x0824 +#define regVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 +#define regVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0825 +#define regVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 +#define regVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0826 +#define regVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_CNTL 0x0827 +#define regVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_CNTL2 0x0828 +#define regVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0829 +#define regVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_MM_CNTL4 0x082a +#define regVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_STATUS 0x082b +#define regVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_ADDR_LO32 0x082c +#define regVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_ADDR_HI32 0x082d +#define regVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x082e +#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 +#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x082f +#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0831 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0832 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0833 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0834 +#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 +#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0835 +#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 +#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0836 +#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 +#define regVM_L2_CNTL4 0x0837 +#define regVM_L2_CNTL4_BASE_IDX 0 +#define regVM_L2_CNTL5 0x0838 +#define regVM_L2_CNTL5_BASE_IDX 0 +#define regVM_L2_MM_GROUP_RT_CLASSES 0x0839 +#define regVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 +#define regVM_L2_BANK_SELECT_RESERVED_CID 0x083a +#define regVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 +#define regVM_L2_BANK_SELECT_RESERVED_CID2 0x083b +#define regVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 +#define regVM_L2_CACHE_PARITY_CNTL 0x083c +#define regVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 +#define regVM_L2_CGTT_CLK_CTRL 0x083d +#define regVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 +#define regVM_L2_CGTT_BUSY_CTRL 0x083e +#define regVM_L2_CGTT_BUSY_CTRL_BASE_IDX 0 +#define regVML2_MEM_ECC_INDEX 0x0842 +#define regVML2_MEM_ECC_INDEX_BASE_IDX 0 +#define regVML2_WALKER_MEM_ECC_INDEX 0x0843 +#define regVML2_WALKER_MEM_ECC_INDEX_BASE_IDX 0 +#define regUTCL2_MEM_ECC_INDEX 0x0844 +#define regUTCL2_MEM_ECC_INDEX_BASE_IDX 0 +#define regVML2_MEM_ECC_CNTL 0x0845 +#define regVML2_MEM_ECC_CNTL_BASE_IDX 0 +#define regVML2_WALKER_MEM_ECC_CNTL 0x0846 +#define regVML2_WALKER_MEM_ECC_CNTL_BASE_IDX 0 +#define regUTCL2_MEM_ECC_CNTL 0x0847 +#define regUTCL2_MEM_ECC_CNTL_BASE_IDX 0 +#define regVML2_MEM_ECC_STATUS 0x0848 +#define regVML2_MEM_ECC_STATUS_BASE_IDX 0 +#define regVML2_WALKER_MEM_ECC_STATUS 0x0849 +#define regVML2_WALKER_MEM_ECC_STATUS_BASE_IDX 0 +#define regUTCL2_MEM_ECC_STATUS 0x084a +#define regUTCL2_MEM_ECC_STATUS_BASE_IDX 0 +#define regUTCL2_EDC_MODE 0x084b +#define regUTCL2_EDC_MODE_BASE_IDX 0 +#define regUTCL2_EDC_CONFIG 0x084c +#define regUTCL2_EDC_CONFIG_BASE_IDX 0 +#define regVML2_UE_ERR_STATUS_LO 0x084d +#define regVML2_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regVML2_WALKER_UE_ERR_STATUS_LO 0x084e +#define regVML2_WALKER_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regUTCL2_UE_ERR_STATUS_LO 0x084f +#define regUTCL2_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regVML2_UE_ERR_STATUS_HI 0x0850 +#define regVML2_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regVML2_WALKER_UE_ERR_STATUS_HI 0x0851 +#define regVML2_WALKER_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regUTCL2_UE_ERR_STATUS_HI 0x0852 +#define regUTCL2_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regVML2_CE_ERR_STATUS_LO 0x0853 +#define regVML2_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regVML2_WALKER_CE_ERR_STATUS_LO 0x0854 +#define regVML2_WALKER_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regUTCL2_CE_ERR_STATUS_LO 0x0855 +#define regUTCL2_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regVML2_CE_ERR_STATUS_HI 0x0856 +#define regVML2_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regVML2_WALKER_CE_ERR_STATUS_HI 0x0857 +#define regVML2_WALKER_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regUTCL2_CE_ERR_STATUS_HI 0x0858 +#define regUTCL2_CE_ERR_STATUS_HI_BASE_IDX 0 + + +// addressBlock: xcd0_gc_utcl2_vml2vcdec +// base address: 0xa180 +#define regVM_CONTEXT0_CNTL 0x0860 +#define regVM_CONTEXT0_CNTL_BASE_IDX 0 +#define regVM_CONTEXT1_CNTL 0x0861 +#define regVM_CONTEXT1_CNTL_BASE_IDX 0 +#define regVM_CONTEXT2_CNTL 0x0862 +#define regVM_CONTEXT2_CNTL_BASE_IDX 0 +#define regVM_CONTEXT3_CNTL 0x0863 +#define regVM_CONTEXT3_CNTL_BASE_IDX 0 +#define regVM_CONTEXT4_CNTL 0x0864 +#define regVM_CONTEXT4_CNTL_BASE_IDX 0 +#define regVM_CONTEXT5_CNTL 0x0865 +#define regVM_CONTEXT5_CNTL_BASE_IDX 0 +#define regVM_CONTEXT6_CNTL 0x0866 +#define regVM_CONTEXT6_CNTL_BASE_IDX 0 +#define regVM_CONTEXT7_CNTL 0x0867 +#define regVM_CONTEXT7_CNTL_BASE_IDX 0 +#define regVM_CONTEXT8_CNTL 0x0868 +#define regVM_CONTEXT8_CNTL_BASE_IDX 0 +#define regVM_CONTEXT9_CNTL 0x0869 +#define regVM_CONTEXT9_CNTL_BASE_IDX 0 +#define regVM_CONTEXT10_CNTL 0x086a +#define regVM_CONTEXT10_CNTL_BASE_IDX 0 +#define regVM_CONTEXT11_CNTL 0x086b +#define regVM_CONTEXT11_CNTL_BASE_IDX 0 +#define regVM_CONTEXT12_CNTL 0x086c +#define regVM_CONTEXT12_CNTL_BASE_IDX 0 +#define regVM_CONTEXT13_CNTL 0x086d +#define regVM_CONTEXT13_CNTL_BASE_IDX 0 +#define regVM_CONTEXT14_CNTL 0x086e +#define regVM_CONTEXT14_CNTL_BASE_IDX 0 +#define regVM_CONTEXT15_CNTL 0x086f +#define regVM_CONTEXT15_CNTL_BASE_IDX 0 +#define regVM_CONTEXTS_DISABLE 0x0870 +#define regVM_CONTEXTS_DISABLE_BASE_IDX 0 +#define regVM_INVALIDATE_ENG0_SEM 0x0871 +#define regVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG1_SEM 0x0872 +#define regVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG2_SEM 0x0873 +#define regVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG3_SEM 0x0874 +#define regVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG4_SEM 0x0875 +#define regVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG5_SEM 0x0876 +#define regVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG6_SEM 0x0877 +#define regVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG7_SEM 0x0878 +#define regVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG8_SEM 0x0879 +#define regVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG9_SEM 0x087a +#define regVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG10_SEM 0x087b +#define regVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG11_SEM 0x087c +#define regVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG12_SEM 0x087d +#define regVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG13_SEM 0x087e +#define regVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG14_SEM 0x087f +#define regVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG15_SEM 0x0880 +#define regVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG16_SEM 0x0881 +#define regVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG17_SEM 0x0882 +#define regVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 +#define regVM_INVALIDATE_ENG0_REQ 0x0883 +#define regVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG1_REQ 0x0884 +#define regVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG2_REQ 0x0885 +#define regVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG3_REQ 0x0886 +#define regVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG4_REQ 0x0887 +#define regVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG5_REQ 0x0888 +#define regVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG6_REQ 0x0889 +#define regVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG7_REQ 0x088a +#define regVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG8_REQ 0x088b +#define regVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG9_REQ 0x088c +#define regVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG10_REQ 0x088d +#define regVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG11_REQ 0x088e +#define regVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG12_REQ 0x088f +#define regVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG13_REQ 0x0890 +#define regVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG14_REQ 0x0891 +#define regVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG15_REQ 0x0892 +#define regVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG16_REQ 0x0893 +#define regVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG17_REQ 0x0894 +#define regVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 +#define regVM_INVALIDATE_ENG0_ACK 0x0895 +#define regVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG1_ACK 0x0896 +#define regVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG2_ACK 0x0897 +#define regVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG3_ACK 0x0898 +#define regVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG4_ACK 0x0899 +#define regVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG5_ACK 0x089a +#define regVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG6_ACK 0x089b +#define regVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG7_ACK 0x089c +#define regVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG8_ACK 0x089d +#define regVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG9_ACK 0x089e +#define regVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG10_ACK 0x089f +#define regVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG11_ACK 0x08a0 +#define regVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG12_ACK 0x08a1 +#define regVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG13_ACK 0x08a2 +#define regVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG14_ACK 0x08a3 +#define regVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG15_ACK 0x08a4 +#define regVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG16_ACK 0x08a5 +#define regVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG17_ACK 0x08a6 +#define regVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 +#define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x08a7 +#define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x08a8 +#define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x08a9 +#define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x08aa +#define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x08ab +#define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x08ac +#define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x08ad +#define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x08ae +#define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x08af +#define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x08b0 +#define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x08b1 +#define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x08b2 +#define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x08b3 +#define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x08b4 +#define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x08b5 +#define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x08b6 +#define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x08b7 +#define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x08b8 +#define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x08b9 +#define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x08ba +#define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x08bb +#define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x08bc +#define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x08bd +#define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x08be +#define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x08bf +#define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x08c0 +#define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x08c1 +#define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x08c2 +#define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x08c3 +#define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x08c4 +#define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x08c5 +#define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x08c6 +#define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x08c7 +#define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x08c8 +#define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x08c9 +#define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 +#define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x08ca +#define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 +#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x08cb +#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x08cc +#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x08cd +#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x08ce +#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x08cf +#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x08d0 +#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x08d1 +#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x08d2 +#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x08d3 +#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x08d4 +#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x08d5 +#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x08d6 +#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x08d7 +#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x08d8 +#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x08d9 +#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x08da +#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x08db +#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x08dc +#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x08dd +#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x08de +#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x08df +#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x08e0 +#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x08e1 +#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x08e2 +#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x08e3 +#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x08e4 +#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x08e5 +#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x08e6 +#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x08e7 +#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x08e8 +#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x08e9 +#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x08ea +#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x08eb +#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x08ec +#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x08ed +#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x08ee +#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x08ef +#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x08f0 +#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x08f1 +#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x08f2 +#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x08f3 +#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x08f4 +#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x08f5 +#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x08f6 +#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x08f7 +#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x08f8 +#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x08f9 +#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x08fa +#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x08fb +#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x08fc +#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x08fd +#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x08fe +#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x08ff +#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0900 +#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0901 +#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0902 +#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0903 +#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0904 +#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0905 +#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0906 +#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0907 +#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0908 +#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0909 +#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x090a +#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x090b +#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x090c +#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x090d +#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x090e +#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x090f +#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0910 +#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0911 +#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0912 +#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0913 +#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0914 +#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0915 +#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0916 +#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0917 +#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0918 +#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0919 +#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x091a +#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x091b +#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x091c +#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x091d +#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x091e +#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x091f +#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0920 +#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0921 +#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0922 +#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0923 +#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0924 +#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0925 +#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0926 +#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0927 +#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0928 +#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0929 +#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x092a +#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 + + +// addressBlock: xcd0_gc_utcl2_vmsharedpfdec +// base address: 0xa500 +#define regMC_VM_NB_MMIOBASE 0x0940 +#define regMC_VM_NB_MMIOBASE_BASE_IDX 0 +#define regMC_VM_NB_MMIOLIMIT 0x0941 +#define regMC_VM_NB_MMIOLIMIT_BASE_IDX 0 +#define regMC_VM_NB_PCI_CTRL 0x0942 +#define regMC_VM_NB_PCI_CTRL_BASE_IDX 0 +#define regMC_VM_NB_PCI_ARB 0x0943 +#define regMC_VM_NB_PCI_ARB_BASE_IDX 0 +#define regMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0944 +#define regMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 +#define regMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0945 +#define regMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 +#define regMC_VM_NB_UPPER_TOP_OF_DRAM2 0x0946 +#define regMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 +#define regMC_VM_FB_OFFSET 0x0947 +#define regMC_VM_FB_OFFSET_BASE_IDX 0 +#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0948 +#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 +#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0949 +#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 +#define regMC_VM_STEERING 0x094a +#define regMC_VM_STEERING_BASE_IDX 0 +#define regMC_SHARED_VIRT_RESET_REQ 0x094b +#define regMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 +#define regMC_MEM_POWER_LS 0x094c +#define regMC_MEM_POWER_LS_BASE_IDX 0 +#define regMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x094d +#define regMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 +#define regMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x094e +#define regMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 +#define regMC_VM_APT_CNTL 0x0951 +#define regMC_VM_APT_CNTL_BASE_IDX 0 +#define regMC_VM_LOCAL_HBM_ADDRESS_START 0x0952 +#define regMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0 +#define regMC_VM_LOCAL_HBM_ADDRESS_END 0x0953 +#define regMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0 +#define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0954 +#define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0 +#define regUTCL2_CGTT_CLK_CTRL 0x0955 +#define regUTCL2_CGTT_CLK_CTRL_BASE_IDX 0 +#define regMC_VM_XGMI_LFB_CNTL 0x0957 +#define regMC_VM_XGMI_LFB_CNTL_BASE_IDX 0 +#define regMC_VM_XGMI_LFB_SIZE 0x0958 +#define regMC_VM_XGMI_LFB_SIZE_BASE_IDX 0 +#define regMC_VM_CACHEABLE_DRAM_CNTL 0x0959 +#define regMC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 0 +#define regMC_VM_HOST_MAPPING 0x095a +#define regMC_VM_HOST_MAPPING_BASE_IDX 0 + + +// addressBlock: xcd0_gc_utcl2_vmsharedvcdec +// base address: 0xa570 +#define regMC_VM_FB_LOCATION_BASE 0x095c +#define regMC_VM_FB_LOCATION_BASE_BASE_IDX 0 +#define regMC_VM_FB_LOCATION_TOP 0x095d +#define regMC_VM_FB_LOCATION_TOP_BASE_IDX 0 +#define regMC_VM_AGP_TOP 0x095e +#define regMC_VM_AGP_TOP_BASE_IDX 0 +#define regMC_VM_AGP_BOT 0x095f +#define regMC_VM_AGP_BOT_BASE_IDX 0 +#define regMC_VM_AGP_BASE 0x0960 +#define regMC_VM_AGP_BASE_BASE_IDX 0 +#define regMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0961 +#define regMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 +#define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0962 +#define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 +#define regMC_VM_MX_L1_TLB_CNTL 0x0963 +#define regMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 + + +// addressBlock: xcd0_gc_utcl2_l2tlbdec +// base address: 0xa5b0 +#define regL2TLB_TLB0_STATUS 0x096d +#define regL2TLB_TLB0_STATUS_BASE_IDX 0 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x096f +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 0 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x0970 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 0 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x0971 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 0 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x0972 +#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 0 + + +// addressBlock: xcd0_gc_tcdec +// base address: 0xac00 +#define regTCP_INVALIDATE 0x0b00 +#define regTCP_INVALIDATE_BASE_IDX 0 +#define regTCP_STATUS 0x0b01 +#define regTCP_STATUS_BASE_IDX 0 +#define regTCP_CNTL 0x0b02 +#define regTCP_CNTL_BASE_IDX 0 +#define regTCP_CHAN_STEER_0 0x0b03 +#define regTCP_CHAN_STEER_0_BASE_IDX 0 +#define regTCP_CHAN_STEER_1 0x0b04 +#define regTCP_CHAN_STEER_1_BASE_IDX 0 +#define regTCP_ADDR_CONFIG 0x0b05 +#define regTCP_ADDR_CONFIG_BASE_IDX 0 +#define regTCP_CREDIT 0x0b06 +#define regTCP_CREDIT_BASE_IDX 0 +#define regTCP_BUFFER_ADDR_HASH_CNTL 0x0b16 +#define regTCP_BUFFER_ADDR_HASH_CNTL_BASE_IDX 0 +#define regTC_CFG_L1_LOAD_POLICY0 0x0b1a +#define regTC_CFG_L1_LOAD_POLICY0_BASE_IDX 0 +#define regTC_CFG_L1_LOAD_POLICY1 0x0b1b +#define regTC_CFG_L1_LOAD_POLICY1_BASE_IDX 0 +#define regTC_CFG_L1_STORE_POLICY 0x0b1c +#define regTC_CFG_L1_STORE_POLICY_BASE_IDX 0 +#define regTC_CFG_L2_LOAD_POLICY0 0x0b1d +#define regTC_CFG_L2_LOAD_POLICY0_BASE_IDX 0 +#define regTC_CFG_L2_LOAD_POLICY1 0x0b1e +#define regTC_CFG_L2_LOAD_POLICY1_BASE_IDX 0 +#define regTC_CFG_L2_STORE_POLICY0 0x0b1f +#define regTC_CFG_L2_STORE_POLICY0_BASE_IDX 0 +#define regTC_CFG_L2_STORE_POLICY1 0x0b20 +#define regTC_CFG_L2_STORE_POLICY1_BASE_IDX 0 +#define regTC_CFG_L2_ATOMIC_POLICY 0x0b21 +#define regTC_CFG_L2_ATOMIC_POLICY_BASE_IDX 0 +#define regTC_CFG_L1_VOLATILE 0x0b22 +#define regTC_CFG_L1_VOLATILE_BASE_IDX 0 +#define regTC_CFG_L2_VOLATILE 0x0b23 +#define regTC_CFG_L2_VOLATILE_BASE_IDX 0 +#define regTCP_UE_EDC_HI_REG 0x0b54 +#define regTCP_UE_EDC_HI_REG_BASE_IDX 0 +#define regTCP_UE_EDC_LO_REG 0x0b55 +#define regTCP_UE_EDC_LO_REG_BASE_IDX 0 +#define regTCP_CE_EDC_HI_REG 0x0b56 +#define regTCP_CE_EDC_HI_REG_BASE_IDX 0 +#define regTCP_CE_EDC_LO_REG 0x0b57 +#define regTCP_CE_EDC_LO_REG_BASE_IDX 0 +#define regTCI_UE_EDC_HI_REG 0x0b58 +#define regTCI_UE_EDC_HI_REG_BASE_IDX 0 +#define regTCI_UE_EDC_LO_REG 0x0b59 +#define regTCI_UE_EDC_LO_REG_BASE_IDX 0 +#define regTCI_CE_EDC_HI_REG 0x0b5a +#define regTCI_CE_EDC_HI_REG_BASE_IDX 0 +#define regTCI_CE_EDC_LO_REG 0x0b5b +#define regTCI_CE_EDC_LO_REG_BASE_IDX 0 +#define regTCI_MISC 0x0b5c +#define regTCI_MISC_BASE_IDX 0 +#define regTCI_CNTL_3 0x0b5d +#define regTCI_CNTL_3_BASE_IDX 0 +#define regTCI_DSM_CNTL 0x0b5e +#define regTCI_DSM_CNTL_BASE_IDX 0 +#define regTCI_DSM_CNTL2 0x0b5f +#define regTCI_DSM_CNTL2_BASE_IDX 0 +#define regTCI_STATUS 0x0b61 +#define regTCI_STATUS_BASE_IDX 0 +#define regTCI_CNTL_1 0x0b62 +#define regTCI_CNTL_1_BASE_IDX 0 +#define regTCI_CNTL_2 0x0b63 +#define regTCI_CNTL_2_BASE_IDX 0 +#define regTCC_CTRL 0x0b80 +#define regTCC_CTRL_BASE_IDX 0 +#define regTCC_CTRL2 0x0b81 +#define regTCC_CTRL2_BASE_IDX 0 +#define regTCC_DSM_CNTL 0x0b86 +#define regTCC_DSM_CNTL_BASE_IDX 0 +#define regTCC_DSM_CNTLA 0x0b87 +#define regTCC_DSM_CNTLA_BASE_IDX 0 +#define regTCC_DSM_CNTL2 0x0b88 +#define regTCC_DSM_CNTL2_BASE_IDX 0 +#define regTCC_DSM_CNTL2A 0x0b89 +#define regTCC_DSM_CNTL2A_BASE_IDX 0 +#define regTCC_DSM_CNTL2B 0x0b8a +#define regTCC_DSM_CNTL2B_BASE_IDX 0 +#define regTCC_WBINVL2 0x0b8b +#define regTCC_WBINVL2_BASE_IDX 0 +#define regTCC_SOFT_RESET 0x0b8c +#define regTCC_SOFT_RESET_BASE_IDX 0 +#define regTCC_DSM_CNTL3 0x0b8e +#define regTCC_DSM_CNTL3_BASE_IDX 0 +#define regTCA_CTRL 0x0bc0 +#define regTCA_CTRL_BASE_IDX 0 +#define regTCA_BURST_MASK 0x0bc1 +#define regTCA_BURST_MASK_BASE_IDX 0 +#define regTCA_BURST_CTRL 0x0bc2 +#define regTCA_BURST_CTRL_BASE_IDX 0 +#define regTCA_DSM_CNTL 0x0bc3 +#define regTCA_DSM_CNTL_BASE_IDX 0 +#define regTCA_DSM_CNTL2 0x0bc4 +#define regTCA_DSM_CNTL2_BASE_IDX 0 +#define regTCX_CTRL 0x0bc6 +#define regTCX_CTRL_BASE_IDX 0 +#define regTCX_DSM_CNTL 0x0bc7 +#define regTCX_DSM_CNTL_BASE_IDX 0 +#define regTCX_DSM_CNTL2 0x0bc8 +#define regTCX_DSM_CNTL2_BASE_IDX 0 +#define regTCA_UE_ERR_STATUS_LO 0x0bc9 +#define regTCA_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regTCA_UE_ERR_STATUS_HI 0x0bca +#define regTCA_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regTCX_UE_ERR_STATUS_LO 0x0bcb +#define regTCX_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regTCX_UE_ERR_STATUS_HI 0x0bcc +#define regTCX_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regTCX_CE_ERR_STATUS_LO 0x0bcd +#define regTCX_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regTCX_CE_ERR_STATUS_HI 0x0bce +#define regTCX_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regTCC_UE_ERR_STATUS_LO 0x0bcf +#define regTCC_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regTCC_UE_ERR_STATUS_HI 0x0bd0 +#define regTCC_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regTCC_CE_ERR_STATUS_LO 0x0bd1 +#define regTCC_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regTCC_CE_ERR_STATUS_HI 0x0bd2 +#define regTCC_CE_ERR_STATUS_HI_BASE_IDX 0 + + +// addressBlock: xcd0_gc_shdec +// base address: 0xb000 +#define regSPI_SHADER_PGM_RSRC3_PS 0x0c07 +#define regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_PS 0x0c08 +#define regSPI_SHADER_PGM_LO_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_PS 0x0c09 +#define regSPI_SHADER_PGM_HI_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC1_PS 0x0c0a +#define regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_PS 0x0c0b +#define regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_0 0x0c0c +#define regSPI_SHADER_USER_DATA_PS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_1 0x0c0d +#define regSPI_SHADER_USER_DATA_PS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_2 0x0c0e +#define regSPI_SHADER_USER_DATA_PS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_3 0x0c0f +#define regSPI_SHADER_USER_DATA_PS_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_4 0x0c10 +#define regSPI_SHADER_USER_DATA_PS_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_5 0x0c11 +#define regSPI_SHADER_USER_DATA_PS_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_6 0x0c12 +#define regSPI_SHADER_USER_DATA_PS_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_7 0x0c13 +#define regSPI_SHADER_USER_DATA_PS_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_8 0x0c14 +#define regSPI_SHADER_USER_DATA_PS_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_9 0x0c15 +#define regSPI_SHADER_USER_DATA_PS_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_10 0x0c16 +#define regSPI_SHADER_USER_DATA_PS_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_11 0x0c17 +#define regSPI_SHADER_USER_DATA_PS_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_12 0x0c18 +#define regSPI_SHADER_USER_DATA_PS_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_13 0x0c19 +#define regSPI_SHADER_USER_DATA_PS_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_14 0x0c1a +#define regSPI_SHADER_USER_DATA_PS_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_15 0x0c1b +#define regSPI_SHADER_USER_DATA_PS_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_16 0x0c1c +#define regSPI_SHADER_USER_DATA_PS_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_17 0x0c1d +#define regSPI_SHADER_USER_DATA_PS_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_18 0x0c1e +#define regSPI_SHADER_USER_DATA_PS_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_19 0x0c1f +#define regSPI_SHADER_USER_DATA_PS_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_20 0x0c20 +#define regSPI_SHADER_USER_DATA_PS_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_21 0x0c21 +#define regSPI_SHADER_USER_DATA_PS_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_22 0x0c22 +#define regSPI_SHADER_USER_DATA_PS_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_23 0x0c23 +#define regSPI_SHADER_USER_DATA_PS_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_24 0x0c24 +#define regSPI_SHADER_USER_DATA_PS_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_25 0x0c25 +#define regSPI_SHADER_USER_DATA_PS_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_26 0x0c26 +#define regSPI_SHADER_USER_DATA_PS_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_27 0x0c27 +#define regSPI_SHADER_USER_DATA_PS_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_28 0x0c28 +#define regSPI_SHADER_USER_DATA_PS_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_29 0x0c29 +#define regSPI_SHADER_USER_DATA_PS_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_30 0x0c2a +#define regSPI_SHADER_USER_DATA_PS_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_31 0x0c2b +#define regSPI_SHADER_USER_DATA_PS_31_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC3_VS 0x0c46 +#define regSPI_SHADER_PGM_RSRC3_VS_BASE_IDX 0 +#define regSPI_SHADER_LATE_ALLOC_VS 0x0c47 +#define regSPI_SHADER_LATE_ALLOC_VS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_VS 0x0c48 +#define regSPI_SHADER_PGM_LO_VS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_VS 0x0c49 +#define regSPI_SHADER_PGM_HI_VS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC1_VS 0x0c4a +#define regSPI_SHADER_PGM_RSRC1_VS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_VS 0x0c4b +#define regSPI_SHADER_PGM_RSRC2_VS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_0 0x0c4c +#define regSPI_SHADER_USER_DATA_VS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_1 0x0c4d +#define regSPI_SHADER_USER_DATA_VS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_2 0x0c4e +#define regSPI_SHADER_USER_DATA_VS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_3 0x0c4f +#define regSPI_SHADER_USER_DATA_VS_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_4 0x0c50 +#define regSPI_SHADER_USER_DATA_VS_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_5 0x0c51 +#define regSPI_SHADER_USER_DATA_VS_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_6 0x0c52 +#define regSPI_SHADER_USER_DATA_VS_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_7 0x0c53 +#define regSPI_SHADER_USER_DATA_VS_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_8 0x0c54 +#define regSPI_SHADER_USER_DATA_VS_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_9 0x0c55 +#define regSPI_SHADER_USER_DATA_VS_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_10 0x0c56 +#define regSPI_SHADER_USER_DATA_VS_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_11 0x0c57 +#define regSPI_SHADER_USER_DATA_VS_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_12 0x0c58 +#define regSPI_SHADER_USER_DATA_VS_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_13 0x0c59 +#define regSPI_SHADER_USER_DATA_VS_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_14 0x0c5a +#define regSPI_SHADER_USER_DATA_VS_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_15 0x0c5b +#define regSPI_SHADER_USER_DATA_VS_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_16 0x0c5c +#define regSPI_SHADER_USER_DATA_VS_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_17 0x0c5d +#define regSPI_SHADER_USER_DATA_VS_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_18 0x0c5e +#define regSPI_SHADER_USER_DATA_VS_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_19 0x0c5f +#define regSPI_SHADER_USER_DATA_VS_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_20 0x0c60 +#define regSPI_SHADER_USER_DATA_VS_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_21 0x0c61 +#define regSPI_SHADER_USER_DATA_VS_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_22 0x0c62 +#define regSPI_SHADER_USER_DATA_VS_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_23 0x0c63 +#define regSPI_SHADER_USER_DATA_VS_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_24 0x0c64 +#define regSPI_SHADER_USER_DATA_VS_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_25 0x0c65 +#define regSPI_SHADER_USER_DATA_VS_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_26 0x0c66 +#define regSPI_SHADER_USER_DATA_VS_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_27 0x0c67 +#define regSPI_SHADER_USER_DATA_VS_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_28 0x0c68 +#define regSPI_SHADER_USER_DATA_VS_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_29 0x0c69 +#define regSPI_SHADER_USER_DATA_VS_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_30 0x0c6a +#define regSPI_SHADER_USER_DATA_VS_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_VS_31 0x0c6b +#define regSPI_SHADER_USER_DATA_VS_31_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_GS_VS 0x0c7c +#define regSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC4_GS 0x0c81 +#define regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_LO_GS 0x0c82 +#define regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_HI_GS 0x0c83 +#define regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_ES 0x0c84 +#define regSPI_SHADER_PGM_LO_ES_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_ES 0x0c85 +#define regSPI_SHADER_PGM_HI_ES_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC3_GS 0x0c87 +#define regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_GS 0x0c88 +#define regSPI_SHADER_PGM_LO_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_GS 0x0c89 +#define regSPI_SHADER_PGM_HI_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC1_GS 0x0c8a +#define regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_GS 0x0c8b +#define regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_0 0x0ccc +#define regSPI_SHADER_USER_DATA_ES_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_1 0x0ccd +#define regSPI_SHADER_USER_DATA_ES_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_2 0x0cce +#define regSPI_SHADER_USER_DATA_ES_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_3 0x0ccf +#define regSPI_SHADER_USER_DATA_ES_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_4 0x0cd0 +#define regSPI_SHADER_USER_DATA_ES_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_5 0x0cd1 +#define regSPI_SHADER_USER_DATA_ES_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_6 0x0cd2 +#define regSPI_SHADER_USER_DATA_ES_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_7 0x0cd3 +#define regSPI_SHADER_USER_DATA_ES_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_8 0x0cd4 +#define regSPI_SHADER_USER_DATA_ES_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_9 0x0cd5 +#define regSPI_SHADER_USER_DATA_ES_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_10 0x0cd6 +#define regSPI_SHADER_USER_DATA_ES_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_11 0x0cd7 +#define regSPI_SHADER_USER_DATA_ES_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_12 0x0cd8 +#define regSPI_SHADER_USER_DATA_ES_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_13 0x0cd9 +#define regSPI_SHADER_USER_DATA_ES_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_14 0x0cda +#define regSPI_SHADER_USER_DATA_ES_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_15 0x0cdb +#define regSPI_SHADER_USER_DATA_ES_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_16 0x0cdc +#define regSPI_SHADER_USER_DATA_ES_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_17 0x0cdd +#define regSPI_SHADER_USER_DATA_ES_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_18 0x0cde +#define regSPI_SHADER_USER_DATA_ES_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_19 0x0cdf +#define regSPI_SHADER_USER_DATA_ES_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_20 0x0ce0 +#define regSPI_SHADER_USER_DATA_ES_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_21 0x0ce1 +#define regSPI_SHADER_USER_DATA_ES_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_22 0x0ce2 +#define regSPI_SHADER_USER_DATA_ES_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_23 0x0ce3 +#define regSPI_SHADER_USER_DATA_ES_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_24 0x0ce4 +#define regSPI_SHADER_USER_DATA_ES_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_25 0x0ce5 +#define regSPI_SHADER_USER_DATA_ES_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_26 0x0ce6 +#define regSPI_SHADER_USER_DATA_ES_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_27 0x0ce7 +#define regSPI_SHADER_USER_DATA_ES_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_28 0x0ce8 +#define regSPI_SHADER_USER_DATA_ES_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_29 0x0ce9 +#define regSPI_SHADER_USER_DATA_ES_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_30 0x0cea +#define regSPI_SHADER_USER_DATA_ES_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ES_31 0x0ceb +#define regSPI_SHADER_USER_DATA_ES_31_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC4_HS 0x0d01 +#define regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_LO_HS 0x0d02 +#define regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_HI_HS 0x0d03 +#define regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_LS 0x0d04 +#define regSPI_SHADER_PGM_LO_LS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_LS 0x0d05 +#define regSPI_SHADER_PGM_HI_LS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC3_HS 0x0d07 +#define regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_HS 0x0d08 +#define regSPI_SHADER_PGM_LO_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_HS 0x0d09 +#define regSPI_SHADER_PGM_HI_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC1_HS 0x0d0a +#define regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_HS 0x0d0b +#define regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_0 0x0d0c +#define regSPI_SHADER_USER_DATA_LS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_1 0x0d0d +#define regSPI_SHADER_USER_DATA_LS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_2 0x0d0e +#define regSPI_SHADER_USER_DATA_LS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_3 0x0d0f +#define regSPI_SHADER_USER_DATA_LS_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_4 0x0d10 +#define regSPI_SHADER_USER_DATA_LS_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_5 0x0d11 +#define regSPI_SHADER_USER_DATA_LS_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_6 0x0d12 +#define regSPI_SHADER_USER_DATA_LS_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_7 0x0d13 +#define regSPI_SHADER_USER_DATA_LS_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_8 0x0d14 +#define regSPI_SHADER_USER_DATA_LS_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_9 0x0d15 +#define regSPI_SHADER_USER_DATA_LS_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_10 0x0d16 +#define regSPI_SHADER_USER_DATA_LS_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_11 0x0d17 +#define regSPI_SHADER_USER_DATA_LS_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_12 0x0d18 +#define regSPI_SHADER_USER_DATA_LS_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_13 0x0d19 +#define regSPI_SHADER_USER_DATA_LS_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_14 0x0d1a +#define regSPI_SHADER_USER_DATA_LS_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_15 0x0d1b +#define regSPI_SHADER_USER_DATA_LS_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_16 0x0d1c +#define regSPI_SHADER_USER_DATA_LS_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_17 0x0d1d +#define regSPI_SHADER_USER_DATA_LS_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_18 0x0d1e +#define regSPI_SHADER_USER_DATA_LS_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_19 0x0d1f +#define regSPI_SHADER_USER_DATA_LS_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_20 0x0d20 +#define regSPI_SHADER_USER_DATA_LS_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_21 0x0d21 +#define regSPI_SHADER_USER_DATA_LS_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_22 0x0d22 +#define regSPI_SHADER_USER_DATA_LS_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_23 0x0d23 +#define regSPI_SHADER_USER_DATA_LS_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_24 0x0d24 +#define regSPI_SHADER_USER_DATA_LS_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_25 0x0d25 +#define regSPI_SHADER_USER_DATA_LS_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_26 0x0d26 +#define regSPI_SHADER_USER_DATA_LS_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_27 0x0d27 +#define regSPI_SHADER_USER_DATA_LS_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_28 0x0d28 +#define regSPI_SHADER_USER_DATA_LS_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_29 0x0d29 +#define regSPI_SHADER_USER_DATA_LS_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_30 0x0d2a +#define regSPI_SHADER_USER_DATA_LS_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_LS_31 0x0d2b +#define regSPI_SHADER_USER_DATA_LS_31_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_0 0x0d4c +#define regSPI_SHADER_USER_DATA_COMMON_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_1 0x0d4d +#define regSPI_SHADER_USER_DATA_COMMON_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_2 0x0d4e +#define regSPI_SHADER_USER_DATA_COMMON_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_3 0x0d4f +#define regSPI_SHADER_USER_DATA_COMMON_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_4 0x0d50 +#define regSPI_SHADER_USER_DATA_COMMON_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_5 0x0d51 +#define regSPI_SHADER_USER_DATA_COMMON_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_6 0x0d52 +#define regSPI_SHADER_USER_DATA_COMMON_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_7 0x0d53 +#define regSPI_SHADER_USER_DATA_COMMON_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_8 0x0d54 +#define regSPI_SHADER_USER_DATA_COMMON_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_9 0x0d55 +#define regSPI_SHADER_USER_DATA_COMMON_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_10 0x0d56 +#define regSPI_SHADER_USER_DATA_COMMON_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_11 0x0d57 +#define regSPI_SHADER_USER_DATA_COMMON_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_12 0x0d58 +#define regSPI_SHADER_USER_DATA_COMMON_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_13 0x0d59 +#define regSPI_SHADER_USER_DATA_COMMON_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_14 0x0d5a +#define regSPI_SHADER_USER_DATA_COMMON_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_15 0x0d5b +#define regSPI_SHADER_USER_DATA_COMMON_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_16 0x0d5c +#define regSPI_SHADER_USER_DATA_COMMON_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_17 0x0d5d +#define regSPI_SHADER_USER_DATA_COMMON_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_18 0x0d5e +#define regSPI_SHADER_USER_DATA_COMMON_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_19 0x0d5f +#define regSPI_SHADER_USER_DATA_COMMON_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_20 0x0d60 +#define regSPI_SHADER_USER_DATA_COMMON_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_21 0x0d61 +#define regSPI_SHADER_USER_DATA_COMMON_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_22 0x0d62 +#define regSPI_SHADER_USER_DATA_COMMON_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_23 0x0d63 +#define regSPI_SHADER_USER_DATA_COMMON_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_24 0x0d64 +#define regSPI_SHADER_USER_DATA_COMMON_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_25 0x0d65 +#define regSPI_SHADER_USER_DATA_COMMON_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_26 0x0d66 +#define regSPI_SHADER_USER_DATA_COMMON_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_27 0x0d67 +#define regSPI_SHADER_USER_DATA_COMMON_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_28 0x0d68 +#define regSPI_SHADER_USER_DATA_COMMON_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_29 0x0d69 +#define regSPI_SHADER_USER_DATA_COMMON_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_30 0x0d6a +#define regSPI_SHADER_USER_DATA_COMMON_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_COMMON_31 0x0d6b +#define regSPI_SHADER_USER_DATA_COMMON_31_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_INITIATOR 0x0e00 +#define regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX 0 +#define regCOMPUTE_DIM_X 0x0e01 +#define regCOMPUTE_DIM_X_BASE_IDX 0 +#define regCOMPUTE_DIM_Y 0x0e02 +#define regCOMPUTE_DIM_Y_BASE_IDX 0 +#define regCOMPUTE_DIM_Z 0x0e03 +#define regCOMPUTE_DIM_Z_BASE_IDX 0 +#define regCOMPUTE_START_X 0x0e04 +#define regCOMPUTE_START_X_BASE_IDX 0 +#define regCOMPUTE_START_Y 0x0e05 +#define regCOMPUTE_START_Y_BASE_IDX 0 +#define regCOMPUTE_START_Z 0x0e06 +#define regCOMPUTE_START_Z_BASE_IDX 0 +#define regCOMPUTE_NUM_THREAD_X 0x0e07 +#define regCOMPUTE_NUM_THREAD_X_BASE_IDX 0 +#define regCOMPUTE_NUM_THREAD_Y 0x0e08 +#define regCOMPUTE_NUM_THREAD_Y_BASE_IDX 0 +#define regCOMPUTE_NUM_THREAD_Z 0x0e09 +#define regCOMPUTE_NUM_THREAD_Z_BASE_IDX 0 +#define regCOMPUTE_PIPELINESTAT_ENABLE 0x0e0a +#define regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 0 +#define regCOMPUTE_PERFCOUNT_ENABLE 0x0e0b +#define regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX 0 +#define regCOMPUTE_PGM_LO 0x0e0c +#define regCOMPUTE_PGM_LO_BASE_IDX 0 +#define regCOMPUTE_PGM_HI 0x0e0d +#define regCOMPUTE_PGM_HI_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_PKT_ADDR_LO 0x0e0e +#define regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_PKT_ADDR_HI 0x0e0f +#define regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x0e10 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x0e11 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 0 +#define regCOMPUTE_PGM_RSRC1 0x0e12 +#define regCOMPUTE_PGM_RSRC1_BASE_IDX 0 +#define regCOMPUTE_PGM_RSRC2 0x0e13 +#define regCOMPUTE_PGM_RSRC2_BASE_IDX 0 +#define regCOMPUTE_VMID 0x0e14 +#define regCOMPUTE_VMID_BASE_IDX 0 +#define regCOMPUTE_RESOURCE_LIMITS 0x0e15 +#define regCOMPUTE_RESOURCE_LIMITS_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE0 0x0e16 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE1 0x0e17 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 0 +#define regCOMPUTE_TMPRING_SIZE 0x0e18 +#define regCOMPUTE_TMPRING_SIZE_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE2 0x0e19 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE3 0x0e1a +#define regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0 +#define regCOMPUTE_RESTART_X 0x0e1b +#define regCOMPUTE_RESTART_X_BASE_IDX 0 +#define regCOMPUTE_RESTART_Y 0x0e1c +#define regCOMPUTE_RESTART_Y_BASE_IDX 0 +#define regCOMPUTE_RESTART_Z 0x0e1d +#define regCOMPUTE_RESTART_Z_BASE_IDX 0 +#define regCOMPUTE_THREAD_TRACE_ENABLE 0x0e1e +#define regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 0 +#define regCOMPUTE_MISC_RESERVED 0x0e1f +#define regCOMPUTE_MISC_RESERVED_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_ID 0x0e20 +#define regCOMPUTE_DISPATCH_ID_BASE_IDX 0 +#define regCOMPUTE_THREADGROUP_ID 0x0e21 +#define regCOMPUTE_THREADGROUP_ID_BASE_IDX 0 +#define regCOMPUTE_RELAUNCH 0x0e22 +#define regCOMPUTE_RELAUNCH_BASE_IDX 0 +#define regCOMPUTE_WAVE_RESTORE_ADDR_LO 0x0e23 +#define regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 0 +#define regCOMPUTE_WAVE_RESTORE_ADDR_HI 0x0e24 +#define regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 0 +#define regCOMPUTE_TG_CHUNK_SIZE 0x0e27 +#define regCOMPUTE_TG_CHUNK_SIZE_BASE_IDX 0 +#define regCOMPUTE_SHADER_CHKSUM 0x0e2c +#define regCOMPUTE_SHADER_CHKSUM_BASE_IDX 0 +#define regCOMPUTE_PGM_RSRC3 0x0e2d +#define regCOMPUTE_PGM_RSRC3_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_0 0x0e40 +#define regCOMPUTE_USER_DATA_0_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_1 0x0e41 +#define regCOMPUTE_USER_DATA_1_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_2 0x0e42 +#define regCOMPUTE_USER_DATA_2_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_3 0x0e43 +#define regCOMPUTE_USER_DATA_3_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_4 0x0e44 +#define regCOMPUTE_USER_DATA_4_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_5 0x0e45 +#define regCOMPUTE_USER_DATA_5_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_6 0x0e46 +#define regCOMPUTE_USER_DATA_6_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_7 0x0e47 +#define regCOMPUTE_USER_DATA_7_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_8 0x0e48 +#define regCOMPUTE_USER_DATA_8_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_9 0x0e49 +#define regCOMPUTE_USER_DATA_9_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_10 0x0e4a +#define regCOMPUTE_USER_DATA_10_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_11 0x0e4b +#define regCOMPUTE_USER_DATA_11_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_12 0x0e4c +#define regCOMPUTE_USER_DATA_12_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_13 0x0e4d +#define regCOMPUTE_USER_DATA_13_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_14 0x0e4e +#define regCOMPUTE_USER_DATA_14_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_15 0x0e4f +#define regCOMPUTE_USER_DATA_15_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_END 0x0e7e +#define regCOMPUTE_DISPATCH_END_BASE_IDX 0 +#define regCOMPUTE_NOWHERE 0x0e7f +#define regCOMPUTE_NOWHERE_BASE_IDX 0 + + +// addressBlock: xcd0_gc_cppdec +// base address: 0xc080 +#define regCP_DFY_CNTL 0x1020 +#define regCP_DFY_CNTL_BASE_IDX 0 +#define regCP_DFY_STAT 0x1021 +#define regCP_DFY_STAT_BASE_IDX 0 +#define regCP_DFY_ADDR_HI 0x1022 +#define regCP_DFY_ADDR_HI_BASE_IDX 0 +#define regCP_DFY_ADDR_LO 0x1023 +#define regCP_DFY_ADDR_LO_BASE_IDX 0 +#define regCP_DFY_DATA_0 0x1024 +#define regCP_DFY_DATA_0_BASE_IDX 0 +#define regCP_DFY_DATA_1 0x1025 +#define regCP_DFY_DATA_1_BASE_IDX 0 +#define regCP_DFY_DATA_2 0x1026 +#define regCP_DFY_DATA_2_BASE_IDX 0 +#define regCP_DFY_DATA_3 0x1027 +#define regCP_DFY_DATA_3_BASE_IDX 0 +#define regCP_DFY_DATA_4 0x1028 +#define regCP_DFY_DATA_4_BASE_IDX 0 +#define regCP_DFY_DATA_5 0x1029 +#define regCP_DFY_DATA_5_BASE_IDX 0 +#define regCP_DFY_DATA_6 0x102a +#define regCP_DFY_DATA_6_BASE_IDX 0 +#define regCP_DFY_DATA_7 0x102b +#define regCP_DFY_DATA_7_BASE_IDX 0 +#define regCP_DFY_DATA_8 0x102c +#define regCP_DFY_DATA_8_BASE_IDX 0 +#define regCP_DFY_DATA_9 0x102d +#define regCP_DFY_DATA_9_BASE_IDX 0 +#define regCP_DFY_DATA_10 0x102e +#define regCP_DFY_DATA_10_BASE_IDX 0 +#define regCP_DFY_DATA_11 0x102f +#define regCP_DFY_DATA_11_BASE_IDX 0 +#define regCP_DFY_DATA_12 0x1030 +#define regCP_DFY_DATA_12_BASE_IDX 0 +#define regCP_DFY_DATA_13 0x1031 +#define regCP_DFY_DATA_13_BASE_IDX 0 +#define regCP_DFY_DATA_14 0x1032 +#define regCP_DFY_DATA_14_BASE_IDX 0 +#define regCP_DFY_DATA_15 0x1033 +#define regCP_DFY_DATA_15_BASE_IDX 0 +#define regCP_DFY_CMD 0x1034 +#define regCP_DFY_CMD_BASE_IDX 0 +#define regCP_EOPQ_WAIT_TIME 0x1035 +#define regCP_EOPQ_WAIT_TIME_BASE_IDX 0 +#define regCP_CPC_MGCG_SYNC_CNTL 0x1036 +#define regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0 +#define regCPC_INT_INFO 0x1037 +#define regCPC_INT_INFO_BASE_IDX 0 +#define regCP_VIRT_STATUS 0x1038 +#define regCP_VIRT_STATUS_BASE_IDX 0 +#define regCPC_INT_ADDR 0x1039 +#define regCPC_INT_ADDR_BASE_IDX 0 +#define regCPC_INT_PASID 0x103a +#define regCPC_INT_PASID_BASE_IDX 0 +#define regCP_GFX_ERROR 0x103b +#define regCP_GFX_ERROR_BASE_IDX 0 +#define regCPG_UTCL1_CNTL 0x103c +#define regCPG_UTCL1_CNTL_BASE_IDX 0 +#define regCPC_UTCL1_CNTL 0x103d +#define regCPC_UTCL1_CNTL_BASE_IDX 0 +#define regCPF_UTCL1_CNTL 0x103e +#define regCPF_UTCL1_CNTL_BASE_IDX 0 +#define regCP_AQL_SMM_STATUS 0x103f +#define regCP_AQL_SMM_STATUS_BASE_IDX 0 +#define regCP_RB0_BASE 0x1040 +#define regCP_RB0_BASE_BASE_IDX 0 +#define regCP_RB_BASE 0x1040 +#define regCP_RB_BASE_BASE_IDX 0 +#define regCP_RB0_CNTL 0x1041 +#define regCP_RB0_CNTL_BASE_IDX 0 +#define regCP_RB_CNTL 0x1041 +#define regCP_RB_CNTL_BASE_IDX 0 +#define regCP_RB_RPTR_WR 0x1042 +#define regCP_RB_RPTR_WR_BASE_IDX 0 +#define regCP_RB0_RPTR_ADDR 0x1043 +#define regCP_RB0_RPTR_ADDR_BASE_IDX 0 +#define regCP_RB_RPTR_ADDR 0x1043 +#define regCP_RB_RPTR_ADDR_BASE_IDX 0 +#define regCP_RB0_RPTR_ADDR_HI 0x1044 +#define regCP_RB0_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB_RPTR_ADDR_HI 0x1044 +#define regCP_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB0_BUFSZ_MASK 0x1045 +#define regCP_RB0_BUFSZ_MASK_BASE_IDX 0 +#define regCP_RB_BUFSZ_MASK 0x1045 +#define regCP_RB_BUFSZ_MASK_BASE_IDX 0 +#define regCP_RB_WPTR_POLL_ADDR_LO 0x1046 +#define regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regCP_RB_WPTR_POLL_ADDR_HI 0x1047 +#define regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regGC_PRIV_MODE 0x1048 +#define regGC_PRIV_MODE_BASE_IDX 0 +#define regCP_INT_CNTL 0x1049 +#define regCP_INT_CNTL_BASE_IDX 0 +#define regCP_INT_STATUS 0x104a +#define regCP_INT_STATUS_BASE_IDX 0 +#define regCP_DEVICE_ID 0x104b +#define regCP_DEVICE_ID_BASE_IDX 0 +#define regCP_ME0_PIPE_PRIORITY_CNTS 0x104c +#define regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_RING_PRIORITY_CNTS 0x104c +#define regCP_RING_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_ME0_PIPE0_PRIORITY 0x104d +#define regCP_ME0_PIPE0_PRIORITY_BASE_IDX 0 +#define regCP_RING0_PRIORITY 0x104d +#define regCP_RING0_PRIORITY_BASE_IDX 0 +#define regCP_ME0_PIPE1_PRIORITY 0x104e +#define regCP_ME0_PIPE1_PRIORITY_BASE_IDX 0 +#define regCP_RING1_PRIORITY 0x104e +#define regCP_RING1_PRIORITY_BASE_IDX 0 +#define regCP_ME0_PIPE2_PRIORITY 0x104f +#define regCP_ME0_PIPE2_PRIORITY_BASE_IDX 0 +#define regCP_RING2_PRIORITY 0x104f +#define regCP_RING2_PRIORITY_BASE_IDX 0 +#define regCP_FATAL_ERROR 0x1050 +#define regCP_FATAL_ERROR_BASE_IDX 0 +#define regCP_RB_VMID 0x1051 +#define regCP_RB_VMID_BASE_IDX 0 +#define regCP_ME0_PIPE0_VMID 0x1052 +#define regCP_ME0_PIPE0_VMID_BASE_IDX 0 +#define regCP_ME0_PIPE1_VMID 0x1053 +#define regCP_ME0_PIPE1_VMID_BASE_IDX 0 +#define regCP_RB0_WPTR 0x1054 +#define regCP_RB0_WPTR_BASE_IDX 0 +#define regCP_RB_WPTR 0x1054 +#define regCP_RB_WPTR_BASE_IDX 0 +#define regCP_RB0_WPTR_HI 0x1055 +#define regCP_RB0_WPTR_HI_BASE_IDX 0 +#define regCP_RB_WPTR_HI 0x1055 +#define regCP_RB_WPTR_HI_BASE_IDX 0 +#define regCP_RB1_WPTR 0x1056 +#define regCP_RB1_WPTR_BASE_IDX 0 +#define regCP_RB1_WPTR_HI 0x1057 +#define regCP_RB1_WPTR_HI_BASE_IDX 0 +#define regCP_RB2_WPTR 0x1058 +#define regCP_RB2_WPTR_BASE_IDX 0 +#define regCP_RB_DOORBELL_CONTROL 0x1059 +#define regCP_RB_DOORBELL_CONTROL_BASE_IDX 0 +#define regCP_RB_DOORBELL_RANGE_LOWER 0x105a +#define regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0 +#define regCP_RB_DOORBELL_RANGE_UPPER 0x105b +#define regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0 +#define regCP_MEC_DOORBELL_RANGE_LOWER 0x105c +#define regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0 +#define regCP_MEC_DOORBELL_RANGE_UPPER 0x105d +#define regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0 +#define regCPG_UTCL1_ERROR 0x105e +#define regCPG_UTCL1_ERROR_BASE_IDX 0 +#define regCPC_UTCL1_ERROR 0x105f +#define regCPC_UTCL1_ERROR_BASE_IDX 0 +#define regCP_RB1_BASE 0x1060 +#define regCP_RB1_BASE_BASE_IDX 0 +#define regCP_RB1_CNTL 0x1061 +#define regCP_RB1_CNTL_BASE_IDX 0 +#define regCP_RB1_RPTR_ADDR 0x1062 +#define regCP_RB1_RPTR_ADDR_BASE_IDX 0 +#define regCP_RB1_RPTR_ADDR_HI 0x1063 +#define regCP_RB1_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB2_BASE 0x1065 +#define regCP_RB2_BASE_BASE_IDX 0 +#define regCP_RB2_CNTL 0x1066 +#define regCP_RB2_CNTL_BASE_IDX 0 +#define regCP_RB2_RPTR_ADDR 0x1067 +#define regCP_RB2_RPTR_ADDR_BASE_IDX 0 +#define regCP_RB2_RPTR_ADDR_HI 0x1068 +#define regCP_RB2_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB0_ACTIVE 0x1069 +#define regCP_RB0_ACTIVE_BASE_IDX 0 +#define regCP_RB_ACTIVE 0x1069 +#define regCP_RB_ACTIVE_BASE_IDX 0 +#define regCP_INT_CNTL_RING0 0x106a +#define regCP_INT_CNTL_RING0_BASE_IDX 0 +#define regCP_INT_CNTL_RING1 0x106b +#define regCP_INT_CNTL_RING1_BASE_IDX 0 +#define regCP_INT_CNTL_RING2 0x106c +#define regCP_INT_CNTL_RING2_BASE_IDX 0 +#define regCP_INT_STATUS_RING0 0x106d +#define regCP_INT_STATUS_RING0_BASE_IDX 0 +#define regCP_INT_STATUS_RING1 0x106e +#define regCP_INT_STATUS_RING1_BASE_IDX 0 +#define regCP_INT_STATUS_RING2 0x106f +#define regCP_INT_STATUS_RING2_BASE_IDX 0 +#define regCP_ME_F32_INTERRUPT 0x1073 +#define regCP_ME_F32_INTERRUPT_BASE_IDX 0 +#define regCP_PFP_F32_INTERRUPT 0x1074 +#define regCP_PFP_F32_INTERRUPT_BASE_IDX 0 +#define regCP_CE_F32_INTERRUPT 0x1075 +#define regCP_CE_F32_INTERRUPT_BASE_IDX 0 +#define regCP_MEC1_F32_INTERRUPT 0x1076 +#define regCP_MEC1_F32_INTERRUPT_BASE_IDX 0 +#define regCP_MEC2_F32_INTERRUPT 0x1077 +#define regCP_MEC2_F32_INTERRUPT_BASE_IDX 0 +#define regCP_PWR_CNTL 0x1078 +#define regCP_PWR_CNTL_BASE_IDX 0 +#define regCP_MEM_SLP_CNTL 0x1079 +#define regCP_MEM_SLP_CNTL_BASE_IDX 0 +#define regCP_ECC_DMA_FIRST_OCCURRENCE 0x107a +#define regCP_ECC_DMA_FIRST_OCCURRENCE_BASE_IDX 0 +#define regCP_ECC_FIRSTOCCURRENCE 0x107a +#define regCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0 +#define regCP_ECC_FIRSTOCCURRENCE_RING0 0x107b +#define regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0 +#define regCP_ECC_FIRSTOCCURRENCE_RING1 0x107c +#define regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0 +#define regCP_ECC_FIRSTOCCURRENCE_RING2 0x107d +#define regCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0 +#define regGB_EDC_MODE 0x107e +#define regGB_EDC_MODE_BASE_IDX 0 +#define regCP_DEBUG 0x107f +#define regCP_DEBUG_BASE_IDX 0 +#define regCP_CPF_DEBUG 0x1080 +#define regCP_CPF_DEBUG_BASE_IDX 0 +#define regCP_CPC_DEBUG 0x1081 +#define regCP_CPC_DEBUG_BASE_IDX 0 +#define regCP_CPC_DEBUG_2 0x1082 +#define regCP_CPC_DEBUG_2_BASE_IDX 0 +#define regCP_PQ_WPTR_POLL_CNTL 0x1083 +#define regCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0 +#define regCP_PQ_WPTR_POLL_CNTL1 0x1084 +#define regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0 +#define regCP_ME1_PIPE0_INT_CNTL 0x1085 +#define regCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE1_INT_CNTL 0x1086 +#define regCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE2_INT_CNTL 0x1087 +#define regCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE3_INT_CNTL 0x1088 +#define regCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0 +#define regCP_ME2_PIPE0_INT_CNTL 0x1089 +#define regCP_ME2_PIPE0_INT_CNTL_BASE_IDX 0 +#define regCP_ME2_PIPE1_INT_CNTL 0x108a +#define regCP_ME2_PIPE1_INT_CNTL_BASE_IDX 0 +#define regCP_ME2_PIPE2_INT_CNTL 0x108b +#define regCP_ME2_PIPE2_INT_CNTL_BASE_IDX 0 +#define regCP_ME2_PIPE3_INT_CNTL 0x108c +#define regCP_ME2_PIPE3_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE0_INT_STATUS 0x108d +#define regCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0 +#define regCP_ME1_PIPE1_INT_STATUS 0x108e +#define regCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0 +#define regCP_ME1_PIPE2_INT_STATUS 0x108f +#define regCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0 +#define regCP_ME1_PIPE3_INT_STATUS 0x1090 +#define regCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0 +#define regCP_ME2_PIPE0_INT_STATUS 0x1091 +#define regCP_ME2_PIPE0_INT_STATUS_BASE_IDX 0 +#define regCP_ME2_PIPE1_INT_STATUS 0x1092 +#define regCP_ME2_PIPE1_INT_STATUS_BASE_IDX 0 +#define regCP_ME2_PIPE2_INT_STATUS 0x1093 +#define regCP_ME2_PIPE2_INT_STATUS_BASE_IDX 0 +#define regCP_ME2_PIPE3_INT_STATUS 0x1094 +#define regCP_ME2_PIPE3_INT_STATUS_BASE_IDX 0 +#define regCP_ME1_INT_STAT_DEBUG 0x1095 +#define regCP_ME1_INT_STAT_DEBUG_BASE_IDX 0 +#define regCP_ME2_INT_STAT_DEBUG 0x1096 +#define regCP_ME2_INT_STAT_DEBUG_BASE_IDX 0 +#define regCC_GC_EDC_CONFIG 0x1098 +#define regCC_GC_EDC_CONFIG_BASE_IDX 0 +#define regCP_ME1_PIPE_PRIORITY_CNTS 0x1099 +#define regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_ME1_PIPE0_PRIORITY 0x109a +#define regCP_ME1_PIPE0_PRIORITY_BASE_IDX 0 +#define regCP_ME1_PIPE1_PRIORITY 0x109b +#define regCP_ME1_PIPE1_PRIORITY_BASE_IDX 0 +#define regCP_ME1_PIPE2_PRIORITY 0x109c +#define regCP_ME1_PIPE2_PRIORITY_BASE_IDX 0 +#define regCP_ME1_PIPE3_PRIORITY 0x109d +#define regCP_ME1_PIPE3_PRIORITY_BASE_IDX 0 +#define regCP_ME2_PIPE_PRIORITY_CNTS 0x109e +#define regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_ME2_PIPE0_PRIORITY 0x109f +#define regCP_ME2_PIPE0_PRIORITY_BASE_IDX 0 +#define regCP_ME2_PIPE1_PRIORITY 0x10a0 +#define regCP_ME2_PIPE1_PRIORITY_BASE_IDX 0 +#define regCP_ME2_PIPE2_PRIORITY 0x10a1 +#define regCP_ME2_PIPE2_PRIORITY_BASE_IDX 0 +#define regCP_ME2_PIPE3_PRIORITY 0x10a2 +#define regCP_ME2_PIPE3_PRIORITY_BASE_IDX 0 +#define regCP_CE_PRGRM_CNTR_START 0x10a3 +#define regCP_CE_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_PFP_PRGRM_CNTR_START 0x10a4 +#define regCP_PFP_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_ME_PRGRM_CNTR_START 0x10a5 +#define regCP_ME_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_MEC1_PRGRM_CNTR_START 0x10a6 +#define regCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_MEC2_PRGRM_CNTR_START 0x10a7 +#define regCP_MEC2_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_CE_INTR_ROUTINE_START 0x10a8 +#define regCP_CE_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_PFP_INTR_ROUTINE_START 0x10a9 +#define regCP_PFP_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_ME_INTR_ROUTINE_START 0x10aa +#define regCP_ME_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_MEC1_INTR_ROUTINE_START 0x10ab +#define regCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_MEC2_INTR_ROUTINE_START 0x10ac +#define regCP_MEC2_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_CONTEXT_CNTL 0x10ad +#define regCP_CONTEXT_CNTL_BASE_IDX 0 +#define regCP_MAX_CONTEXT 0x10ae +#define regCP_MAX_CONTEXT_BASE_IDX 0 +#define regCP_IQ_WAIT_TIME1 0x10af +#define regCP_IQ_WAIT_TIME1_BASE_IDX 0 +#define regCP_IQ_WAIT_TIME2 0x10b0 +#define regCP_IQ_WAIT_TIME2_BASE_IDX 0 +#define regCP_RB0_BASE_HI 0x10b1 +#define regCP_RB0_BASE_HI_BASE_IDX 0 +#define regCP_RB1_BASE_HI 0x10b2 +#define regCP_RB1_BASE_HI_BASE_IDX 0 +#define regCP_VMID_RESET 0x10b3 +#define regCP_VMID_RESET_BASE_IDX 0 +#define regCPC_INT_CNTL 0x10b4 +#define regCPC_INT_CNTL_BASE_IDX 0 +#define regCPC_INT_STATUS 0x10b5 +#define regCPC_INT_STATUS_BASE_IDX 0 +#define regCP_VMID_PREEMPT 0x10b6 +#define regCP_VMID_PREEMPT_BASE_IDX 0 +#define regCPC_INT_CNTX_ID 0x10b7 +#define regCPC_INT_CNTX_ID_BASE_IDX 0 +#define regCP_PQ_STATUS 0x10b8 +#define regCP_PQ_STATUS_BASE_IDX 0 +#define regCP_CPC_IC_BASE_LO 0x10b9 +#define regCP_CPC_IC_BASE_LO_BASE_IDX 0 +#define regCP_CPC_IC_BASE_HI 0x10ba +#define regCP_CPC_IC_BASE_HI_BASE_IDX 0 +#define regCP_CPC_IC_BASE_CNTL 0x10bb +#define regCP_CPC_IC_BASE_CNTL_BASE_IDX 0 +#define regCP_CPC_IC_OP_CNTL 0x10bc +#define regCP_CPC_IC_OP_CNTL_BASE_IDX 0 +#define regCP_MEC1_F32_INT_DIS 0x10bd +#define regCP_MEC1_F32_INT_DIS_BASE_IDX 0 +#define regCP_MEC2_F32_INT_DIS 0x10be +#define regCP_MEC2_F32_INT_DIS_BASE_IDX 0 +#define regCP_VMID_STATUS 0x10bf +#define regCP_VMID_STATUS_BASE_IDX 0 +#define regCPC_UE_ERR_STATUS_LO 0x10e0 +#define regCPC_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regCPC_UE_ERR_STATUS_HI 0x10e1 +#define regCPC_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regCPC_CE_ERR_STATUS_LO 0x10e2 +#define regCPC_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regCPC_CE_ERR_STATUS_HI 0x10e3 +#define regCPC_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regCPF_UE_ERR_STATUS_LO 0x10e4 +#define regCPF_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regCPF_UE_ERR_STATUS_HI 0x10e5 +#define regCPF_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regCPF_CE_ERR_STATUS_LO 0x10e6 +#define regCPF_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regCPF_CE_ERR_STATUS_HI 0x10e7 +#define regCPF_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regCPG_UE_ERR_STATUS_LO 0x10e8 +#define regCPG_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regCPG_UE_ERR_STATUS_HI 0x10e9 +#define regCPG_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regCPG_CE_ERR_STATUS_LO 0x10ea +#define regCPG_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regCPG_CE_ERR_STATUS_HI 0x10eb +#define regCPG_CE_ERR_STATUS_HI_BASE_IDX 0 + + +// addressBlock: xcd0_gc_cppdec2 +// base address: 0xc600 +#define regCP_RB_DOORBELL_CONTROL_SCH_0 0x1180 +#define regCP_RB_DOORBELL_CONTROL_SCH_0_BASE_IDX 0 +#define regCP_RB_DOORBELL_CONTROL_SCH_1 0x1181 +#define regCP_RB_DOORBELL_CONTROL_SCH_1_BASE_IDX 0 +#define regCP_RB_DOORBELL_CONTROL_SCH_2 0x1182 +#define regCP_RB_DOORBELL_CONTROL_SCH_2_BASE_IDX 0 +#define regCP_RB_DOORBELL_CONTROL_SCH_3 0x1183 +#define regCP_RB_DOORBELL_CONTROL_SCH_3_BASE_IDX 0 +#define regCP_RB_DOORBELL_CONTROL_SCH_4 0x1184 +#define regCP_RB_DOORBELL_CONTROL_SCH_4_BASE_IDX 0 +#define regCP_RB_DOORBELL_CONTROL_SCH_5 0x1185 +#define regCP_RB_DOORBELL_CONTROL_SCH_5_BASE_IDX 0 +#define regCP_RB_DOORBELL_CONTROL_SCH_6 0x1186 +#define regCP_RB_DOORBELL_CONTROL_SCH_6_BASE_IDX 0 +#define regCP_RB_DOORBELL_CONTROL_SCH_7 0x1187 +#define regCP_RB_DOORBELL_CONTROL_SCH_7_BASE_IDX 0 +#define regCP_RB_DOORBELL_CLEAR 0x1188 +#define regCP_RB_DOORBELL_CLEAR_BASE_IDX 0 +#define regCP_CPF_DSM_CNTL 0x1194 +#define regCP_CPF_DSM_CNTL_BASE_IDX 0 +#define regCP_CPG_DSM_CNTL 0x1195 +#define regCP_CPG_DSM_CNTL_BASE_IDX 0 +#define regCP_CPC_DSM_CNTL 0x1196 +#define regCP_CPC_DSM_CNTL_BASE_IDX 0 +#define regCP_CPF_DSM_CNTL2 0x1197 +#define regCP_CPF_DSM_CNTL2_BASE_IDX 0 +#define regCP_CPG_DSM_CNTL2 0x1198 +#define regCP_CPG_DSM_CNTL2_BASE_IDX 0 +#define regCP_CPC_DSM_CNTL2 0x1199 +#define regCP_CPC_DSM_CNTL2_BASE_IDX 0 +#define regCP_CPF_DSM_CNTL2A 0x119a +#define regCP_CPF_DSM_CNTL2A_BASE_IDX 0 +#define regCP_CPG_DSM_CNTL2A 0x119b +#define regCP_CPG_DSM_CNTL2A_BASE_IDX 0 +#define regCP_CPC_DSM_CNTL2A 0x119c +#define regCP_CPC_DSM_CNTL2A_BASE_IDX 0 +#define regCP_EDC_FUE_CNTL 0x119d +#define regCP_EDC_FUE_CNTL_BASE_IDX 0 +#define regCP_GFX_MQD_CONTROL 0x11a0 +#define regCP_GFX_MQD_CONTROL_BASE_IDX 0 +#define regCP_GFX_MQD_BASE_ADDR 0x11a1 +#define regCP_GFX_MQD_BASE_ADDR_BASE_IDX 0 +#define regCP_GFX_MQD_BASE_ADDR_HI 0x11a2 +#define regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_RB_STATUS 0x11a3 +#define regCP_RB_STATUS_BASE_IDX 0 +#define regCPG_UTCL1_STATUS 0x11b4 +#define regCPG_UTCL1_STATUS_BASE_IDX 0 +#define regCPC_UTCL1_STATUS 0x11b5 +#define regCPC_UTCL1_STATUS_BASE_IDX 0 +#define regCPF_UTCL1_STATUS 0x11b6 +#define regCPF_UTCL1_STATUS_BASE_IDX 0 +#define regCP_SD_CNTL 0x11b7 +#define regCP_SD_CNTL_BASE_IDX 0 +#define regCP_SOFT_RESET_CNTL 0x11b9 +#define regCP_SOFT_RESET_CNTL_BASE_IDX 0 +#define regCP_CPC_GFX_CNTL 0x11ba +#define regCP_CPC_GFX_CNTL_BASE_IDX 0 + + +// addressBlock: xcd0_gc_spipdec +// base address: 0xc700 +#define regSPI_ARB_PRIORITY 0x11c0 +#define regSPI_ARB_PRIORITY_BASE_IDX 0 +#define regSPI_ARB_CYCLES_0 0x11c1 +#define regSPI_ARB_CYCLES_0_BASE_IDX 0 +#define regSPI_ARB_CYCLES_1 0x11c2 +#define regSPI_ARB_CYCLES_1_BASE_IDX 0 +#define regSPI_CDBG_SYS_GFX 0x11c3 +#define regSPI_CDBG_SYS_GFX_BASE_IDX 0 +#define regSPI_CDBG_SYS_HP3D 0x11c4 +#define regSPI_CDBG_SYS_HP3D_BASE_IDX 0 +#define regSPI_CDBG_SYS_CS0 0x11c5 +#define regSPI_CDBG_SYS_CS0_BASE_IDX 0 +#define regSPI_CDBG_SYS_CS1 0x11c6 +#define regSPI_CDBG_SYS_CS1_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_GFX 0x11c7 +#define regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_HP3D 0x11c8 +#define regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS0 0x11c9 +#define regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS1 0x11ca +#define regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS2 0x11cb +#define regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS3 0x11cc +#define regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS4 0x11cd +#define regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS5 0x11ce +#define regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS6 0x11cf +#define regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS7 0x11d0 +#define regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0 +#define regSPI_GDBG_WAVE_CNTL 0x11d1 +#define regSPI_GDBG_WAVE_CNTL_BASE_IDX 0 +#define regSPI_GDBG_TRAP_CONFIG 0x11d2 +#define regSPI_GDBG_TRAP_CONFIG_BASE_IDX 0 +#define regSPI_GDBG_PER_VMID_CNTL 0x11d3 +#define regSPI_GDBG_PER_VMID_CNTL_BASE_IDX 0 +#define regSPI_GDBG_WAVE_CNTL3 0x11d5 +#define regSPI_GDBG_WAVE_CNTL3_BASE_IDX 0 +#define regSPI_SCRATCH_ADDR_CHECK 0x11d8 +#define regSPI_SCRATCH_ADDR_CHECK_BASE_IDX 0 +#define regSPI_SCRATCH_ADDR_STATUS 0x11d9 +#define regSPI_SCRATCH_ADDR_STATUS_BASE_IDX 0 +#define regSPI_RESET_DEBUG 0x11da +#define regSPI_RESET_DEBUG_BASE_IDX 0 +#define regSPI_COMPUTE_QUEUE_RESET 0x11db +#define regSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_0 0x11dc +#define regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_1 0x11dd +#define regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_2 0x11de +#define regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_3 0x11df +#define regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_4 0x11e0 +#define regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_5 0x11e1 +#define regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_6 0x11e2 +#define regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_7 0x11e3 +#define regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_8 0x11e4 +#define regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_9 0x11e5 +#define regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_0 0x11e6 +#define regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_1 0x11e7 +#define regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_2 0x11e8 +#define regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_3 0x11e9 +#define regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_4 0x11ea +#define regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_5 0x11eb +#define regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_6 0x11ec +#define regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_7 0x11ed +#define regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_8 0x11ee +#define regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_9 0x11ef +#define regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_10 0x11f0 +#define regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_11 0x11f1 +#define regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_10 0x11f2 +#define regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_11 0x11f3 +#define regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_12 0x11f4 +#define regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_13 0x11f5 +#define regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_14 0x11f6 +#define regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_CU_15 0x11f7 +#define regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_12 0x11f8 +#define regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_13 0x11f9 +#define regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_14 0x11fa +#define regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX 0 +#define regSPI_RESOURCE_RESERVE_EN_CU_15 0x11fb +#define regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX 0 +#define regSPI_COMPUTE_WF_CTX_SAVE 0x11fc +#define regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX 0 +#define regSPI_ARB_CNTL_0 0x11fd +#define regSPI_ARB_CNTL_0_BASE_IDX 0 + + +// addressBlock: xcd0_gc_cpphqddec +// base address: 0xc800 +#define regCP_HQD_GFX_CONTROL 0x123e +#define regCP_HQD_GFX_CONTROL_BASE_IDX 0 +#define regCP_HQD_GFX_STATUS 0x123f +#define regCP_HQD_GFX_STATUS_BASE_IDX 0 +#define regCP_HPD_ROQ_OFFSETS 0x1240 +#define regCP_HPD_ROQ_OFFSETS_BASE_IDX 0 +#define regCP_HPD_STATUS0 0x1241 +#define regCP_HPD_STATUS0_BASE_IDX 0 +#define regCP_HPD_UTCL1_CNTL 0x1242 +#define regCP_HPD_UTCL1_CNTL_BASE_IDX 0 +#define regCP_HPD_UTCL1_ERROR 0x1243 +#define regCP_HPD_UTCL1_ERROR_BASE_IDX 0 +#define regCP_HPD_UTCL1_ERROR_ADDR 0x1244 +#define regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0 +#define regCP_MQD_BASE_ADDR 0x1245 +#define regCP_MQD_BASE_ADDR_BASE_IDX 0 +#define regCP_MQD_BASE_ADDR_HI 0x1246 +#define regCP_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_ACTIVE 0x1247 +#define regCP_HQD_ACTIVE_BASE_IDX 0 +#define regCP_HQD_VMID 0x1248 +#define regCP_HQD_VMID_BASE_IDX 0 +#define regCP_HQD_PERSISTENT_STATE 0x1249 +#define regCP_HQD_PERSISTENT_STATE_BASE_IDX 0 +#define regCP_HQD_PIPE_PRIORITY 0x124a +#define regCP_HQD_PIPE_PRIORITY_BASE_IDX 0 +#define regCP_HQD_QUEUE_PRIORITY 0x124b +#define regCP_HQD_QUEUE_PRIORITY_BASE_IDX 0 +#define regCP_HQD_QUANTUM 0x124c +#define regCP_HQD_QUANTUM_BASE_IDX 0 +#define regCP_HQD_PQ_BASE 0x124d +#define regCP_HQD_PQ_BASE_BASE_IDX 0 +#define regCP_HQD_PQ_BASE_HI 0x124e +#define regCP_HQD_PQ_BASE_HI_BASE_IDX 0 +#define regCP_HQD_PQ_RPTR 0x124f +#define regCP_HQD_PQ_RPTR_BASE_IDX 0 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR 0x1250 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_POLL_ADDR 0x1252 +#define regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1253 +#define regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_PQ_DOORBELL_CONTROL 0x1254 +#define regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0 +#define regCP_HQD_PQ_CONTROL 0x1256 +#define regCP_HQD_PQ_CONTROL_BASE_IDX 0 +#define regCP_HQD_IB_BASE_ADDR 0x1257 +#define regCP_HQD_IB_BASE_ADDR_BASE_IDX 0 +#define regCP_HQD_IB_BASE_ADDR_HI 0x1258 +#define regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_IB_RPTR 0x1259 +#define regCP_HQD_IB_RPTR_BASE_IDX 0 +#define regCP_HQD_IB_CONTROL 0x125a +#define regCP_HQD_IB_CONTROL_BASE_IDX 0 +#define regCP_HQD_IQ_TIMER 0x125b +#define regCP_HQD_IQ_TIMER_BASE_IDX 0 +#define regCP_HQD_IQ_RPTR 0x125c +#define regCP_HQD_IQ_RPTR_BASE_IDX 0 +#define regCP_HQD_DEQUEUE_REQUEST 0x125d +#define regCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0 +#define regCP_HQD_DMA_OFFLOAD 0x125e +#define regCP_HQD_DMA_OFFLOAD_BASE_IDX 0 +#define regCP_HQD_OFFLOAD 0x125e +#define regCP_HQD_OFFLOAD_BASE_IDX 0 +#define regCP_HQD_SEMA_CMD 0x125f +#define regCP_HQD_SEMA_CMD_BASE_IDX 0 +#define regCP_HQD_MSG_TYPE 0x1260 +#define regCP_HQD_MSG_TYPE_BASE_IDX 0 +#define regCP_HQD_ATOMIC0_PREOP_LO 0x1261 +#define regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0 +#define regCP_HQD_ATOMIC0_PREOP_HI 0x1262 +#define regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0 +#define regCP_HQD_ATOMIC1_PREOP_LO 0x1263 +#define regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0 +#define regCP_HQD_ATOMIC1_PREOP_HI 0x1264 +#define regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0 +#define regCP_HQD_HQ_SCHEDULER0 0x1265 +#define regCP_HQD_HQ_SCHEDULER0_BASE_IDX 0 +#define regCP_HQD_HQ_STATUS0 0x1265 +#define regCP_HQD_HQ_STATUS0_BASE_IDX 0 +#define regCP_HQD_HQ_CONTROL0 0x1266 +#define regCP_HQD_HQ_CONTROL0_BASE_IDX 0 +#define regCP_HQD_HQ_SCHEDULER1 0x1266 +#define regCP_HQD_HQ_SCHEDULER1_BASE_IDX 0 +#define regCP_MQD_CONTROL 0x1267 +#define regCP_MQD_CONTROL_BASE_IDX 0 +#define regCP_HQD_HQ_STATUS1 0x1268 +#define regCP_HQD_HQ_STATUS1_BASE_IDX 0 +#define regCP_HQD_HQ_CONTROL1 0x1269 +#define regCP_HQD_HQ_CONTROL1_BASE_IDX 0 +#define regCP_HQD_EOP_BASE_ADDR 0x126a +#define regCP_HQD_EOP_BASE_ADDR_BASE_IDX 0 +#define regCP_HQD_EOP_BASE_ADDR_HI 0x126b +#define regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_EOP_CONTROL 0x126c +#define regCP_HQD_EOP_CONTROL_BASE_IDX 0 +#define regCP_HQD_EOP_RPTR 0x126d +#define regCP_HQD_EOP_RPTR_BASE_IDX 0 +#define regCP_HQD_EOP_WPTR 0x126e +#define regCP_HQD_EOP_WPTR_BASE_IDX 0 +#define regCP_HQD_EOP_EVENTS 0x126f +#define regCP_HQD_EOP_EVENTS_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x1270 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x1271 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_CONTROL 0x1272 +#define regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0 +#define regCP_HQD_CNTL_STACK_OFFSET 0x1273 +#define regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0 +#define regCP_HQD_CNTL_STACK_SIZE 0x1274 +#define regCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0 +#define regCP_HQD_WG_STATE_OFFSET 0x1275 +#define regCP_HQD_WG_STATE_OFFSET_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_SIZE 0x1276 +#define regCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0 +#define regCP_HQD_GDS_RESOURCE_STATE 0x1277 +#define regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0 +#define regCP_HQD_ERROR 0x1278 +#define regCP_HQD_ERROR_BASE_IDX 0 +#define regCP_HQD_EOP_WPTR_MEM 0x1279 +#define regCP_HQD_EOP_WPTR_MEM_BASE_IDX 0 +#define regCP_HQD_AQL_CONTROL 0x127a +#define regCP_HQD_AQL_CONTROL_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_LO 0x127b +#define regCP_HQD_PQ_WPTR_LO_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_HI 0x127c +#define regCP_HQD_PQ_WPTR_HI_BASE_IDX 0 +#define regCP_HQD_AQL_CONTROL_1 0x127d +#define regCP_HQD_AQL_CONTROL_1_BASE_IDX 0 +#define regCP_HQD_AQL_DISPATCH_ID 0x127e +#define regCP_HQD_AQL_DISPATCH_ID_BASE_IDX 0 +#define regCP_HQD_AQL_DISPATCH_ID_HI 0x127f +#define regCP_HQD_AQL_DISPATCH_ID_HI_BASE_IDX 0 + + +// addressBlock: xcd0_gc_tcpdec +// base address: 0xca80 +#define regTCP_WATCH0_ADDR_H 0x12a0 +#define regTCP_WATCH0_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH0_ADDR_L 0x12a1 +#define regTCP_WATCH0_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH0_CNTL 0x12a2 +#define regTCP_WATCH0_CNTL_BASE_IDX 0 +#define regTCP_WATCH1_ADDR_H 0x12a3 +#define regTCP_WATCH1_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH1_ADDR_L 0x12a4 +#define regTCP_WATCH1_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH1_CNTL 0x12a5 +#define regTCP_WATCH1_CNTL_BASE_IDX 0 +#define regTCP_WATCH2_ADDR_H 0x12a6 +#define regTCP_WATCH2_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH2_ADDR_L 0x12a7 +#define regTCP_WATCH2_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH2_CNTL 0x12a8 +#define regTCP_WATCH2_CNTL_BASE_IDX 0 +#define regTCP_WATCH3_ADDR_H 0x12a9 +#define regTCP_WATCH3_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH3_ADDR_L 0x12aa +#define regTCP_WATCH3_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH3_CNTL 0x12ab +#define regTCP_WATCH3_CNTL_BASE_IDX 0 +#define regTCP_GATCL1_CNTL 0x12b0 +#define regTCP_GATCL1_CNTL_BASE_IDX 0 +#define regTCP_ATC_EDC_GATCL1_CNT 0x12b1 +#define regTCP_ATC_EDC_GATCL1_CNT_BASE_IDX 0 +#define regTCP_GATCL1_DSM_CNTL 0x12b2 +#define regTCP_GATCL1_DSM_CNTL_BASE_IDX 0 +#define regTCP_DSM_CNTL 0x12b3 +#define regTCP_DSM_CNTL_BASE_IDX 0 +#define regTCP_CNTL2 0x12b4 +#define regTCP_CNTL2_BASE_IDX 0 +#define regTCP_UTCL1_CNTL1 0x12b5 +#define regTCP_UTCL1_CNTL1_BASE_IDX 0 +#define regTCP_UTCL1_CNTL2 0x12b6 +#define regTCP_UTCL1_CNTL2_BASE_IDX 0 +#define regTCP_UTCL1_STATUS 0x12b7 +#define regTCP_UTCL1_STATUS_BASE_IDX 0 +#define regTCP_DSM_CNTL2 0x12b8 +#define regTCP_DSM_CNTL2_BASE_IDX 0 +#define regTCP_PERFCOUNTER_FILTER 0x12b9 +#define regTCP_PERFCOUNTER_FILTER_BASE_IDX 0 +#define regTCP_PERFCOUNTER_FILTER_EN 0x12ba +#define regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX 0 + + +// addressBlock: xcd0_gc_gdspdec +// base address: 0xcc00 +#define regGDS_VMID0_BASE 0x1300 +#define regGDS_VMID0_BASE_BASE_IDX 0 +#define regGDS_VMID0_SIZE 0x1301 +#define regGDS_VMID0_SIZE_BASE_IDX 0 +#define regGDS_VMID1_BASE 0x1302 +#define regGDS_VMID1_BASE_BASE_IDX 0 +#define regGDS_VMID1_SIZE 0x1303 +#define regGDS_VMID1_SIZE_BASE_IDX 0 +#define regGDS_VMID2_BASE 0x1304 +#define regGDS_VMID2_BASE_BASE_IDX 0 +#define regGDS_VMID2_SIZE 0x1305 +#define regGDS_VMID2_SIZE_BASE_IDX 0 +#define regGDS_VMID3_BASE 0x1306 +#define regGDS_VMID3_BASE_BASE_IDX 0 +#define regGDS_VMID3_SIZE 0x1307 +#define regGDS_VMID3_SIZE_BASE_IDX 0 +#define regGDS_VMID4_BASE 0x1308 +#define regGDS_VMID4_BASE_BASE_IDX 0 +#define regGDS_VMID4_SIZE 0x1309 +#define regGDS_VMID4_SIZE_BASE_IDX 0 +#define regGDS_VMID5_BASE 0x130a +#define regGDS_VMID5_BASE_BASE_IDX 0 +#define regGDS_VMID5_SIZE 0x130b +#define regGDS_VMID5_SIZE_BASE_IDX 0 +#define regGDS_VMID6_BASE 0x130c +#define regGDS_VMID6_BASE_BASE_IDX 0 +#define regGDS_VMID6_SIZE 0x130d +#define regGDS_VMID6_SIZE_BASE_IDX 0 +#define regGDS_VMID7_BASE 0x130e +#define regGDS_VMID7_BASE_BASE_IDX 0 +#define regGDS_VMID7_SIZE 0x130f +#define regGDS_VMID7_SIZE_BASE_IDX 0 +#define regGDS_VMID8_BASE 0x1310 +#define regGDS_VMID8_BASE_BASE_IDX 0 +#define regGDS_VMID8_SIZE 0x1311 +#define regGDS_VMID8_SIZE_BASE_IDX 0 +#define regGDS_VMID9_BASE 0x1312 +#define regGDS_VMID9_BASE_BASE_IDX 0 +#define regGDS_VMID9_SIZE 0x1313 +#define regGDS_VMID9_SIZE_BASE_IDX 0 +#define regGDS_VMID10_BASE 0x1314 +#define regGDS_VMID10_BASE_BASE_IDX 0 +#define regGDS_VMID10_SIZE 0x1315 +#define regGDS_VMID10_SIZE_BASE_IDX 0 +#define regGDS_VMID11_BASE 0x1316 +#define regGDS_VMID11_BASE_BASE_IDX 0 +#define regGDS_VMID11_SIZE 0x1317 +#define regGDS_VMID11_SIZE_BASE_IDX 0 +#define regGDS_VMID12_BASE 0x1318 +#define regGDS_VMID12_BASE_BASE_IDX 0 +#define regGDS_VMID12_SIZE 0x1319 +#define regGDS_VMID12_SIZE_BASE_IDX 0 +#define regGDS_VMID13_BASE 0x131a +#define regGDS_VMID13_BASE_BASE_IDX 0 +#define regGDS_VMID13_SIZE 0x131b +#define regGDS_VMID13_SIZE_BASE_IDX 0 +#define regGDS_VMID14_BASE 0x131c +#define regGDS_VMID14_BASE_BASE_IDX 0 +#define regGDS_VMID14_SIZE 0x131d +#define regGDS_VMID14_SIZE_BASE_IDX 0 +#define regGDS_VMID15_BASE 0x131e +#define regGDS_VMID15_BASE_BASE_IDX 0 +#define regGDS_VMID15_SIZE 0x131f +#define regGDS_VMID15_SIZE_BASE_IDX 0 +#define regGDS_GWS_VMID0 0x1320 +#define regGDS_GWS_VMID0_BASE_IDX 0 +#define regGDS_GWS_VMID1 0x1321 +#define regGDS_GWS_VMID1_BASE_IDX 0 +#define regGDS_GWS_VMID2 0x1322 +#define regGDS_GWS_VMID2_BASE_IDX 0 +#define regGDS_GWS_VMID3 0x1323 +#define regGDS_GWS_VMID3_BASE_IDX 0 +#define regGDS_GWS_VMID4 0x1324 +#define regGDS_GWS_VMID4_BASE_IDX 0 +#define regGDS_GWS_VMID5 0x1325 +#define regGDS_GWS_VMID5_BASE_IDX 0 +#define regGDS_GWS_VMID6 0x1326 +#define regGDS_GWS_VMID6_BASE_IDX 0 +#define regGDS_GWS_VMID7 0x1327 +#define regGDS_GWS_VMID7_BASE_IDX 0 +#define regGDS_GWS_VMID8 0x1328 +#define regGDS_GWS_VMID8_BASE_IDX 0 +#define regGDS_GWS_VMID9 0x1329 +#define regGDS_GWS_VMID9_BASE_IDX 0 +#define regGDS_GWS_VMID10 0x132a +#define regGDS_GWS_VMID10_BASE_IDX 0 +#define regGDS_GWS_VMID11 0x132b +#define regGDS_GWS_VMID11_BASE_IDX 0 +#define regGDS_GWS_VMID12 0x132c +#define regGDS_GWS_VMID12_BASE_IDX 0 +#define regGDS_GWS_VMID13 0x132d +#define regGDS_GWS_VMID13_BASE_IDX 0 +#define regGDS_GWS_VMID14 0x132e +#define regGDS_GWS_VMID14_BASE_IDX 0 +#define regGDS_GWS_VMID15 0x132f +#define regGDS_GWS_VMID15_BASE_IDX 0 +#define regGDS_OA_VMID0 0x1330 +#define regGDS_OA_VMID0_BASE_IDX 0 +#define regGDS_OA_VMID1 0x1331 +#define regGDS_OA_VMID1_BASE_IDX 0 +#define regGDS_OA_VMID2 0x1332 +#define regGDS_OA_VMID2_BASE_IDX 0 +#define regGDS_OA_VMID3 0x1333 +#define regGDS_OA_VMID3_BASE_IDX 0 +#define regGDS_OA_VMID4 0x1334 +#define regGDS_OA_VMID4_BASE_IDX 0 +#define regGDS_OA_VMID5 0x1335 +#define regGDS_OA_VMID5_BASE_IDX 0 +#define regGDS_OA_VMID6 0x1336 +#define regGDS_OA_VMID6_BASE_IDX 0 +#define regGDS_OA_VMID7 0x1337 +#define regGDS_OA_VMID7_BASE_IDX 0 +#define regGDS_OA_VMID8 0x1338 +#define regGDS_OA_VMID8_BASE_IDX 0 +#define regGDS_OA_VMID9 0x1339 +#define regGDS_OA_VMID9_BASE_IDX 0 +#define regGDS_OA_VMID10 0x133a +#define regGDS_OA_VMID10_BASE_IDX 0 +#define regGDS_OA_VMID11 0x133b +#define regGDS_OA_VMID11_BASE_IDX 0 +#define regGDS_OA_VMID12 0x133c +#define regGDS_OA_VMID12_BASE_IDX 0 +#define regGDS_OA_VMID13 0x133d +#define regGDS_OA_VMID13_BASE_IDX 0 +#define regGDS_OA_VMID14 0x133e +#define regGDS_OA_VMID14_BASE_IDX 0 +#define regGDS_OA_VMID15 0x133f +#define regGDS_OA_VMID15_BASE_IDX 0 +#define regGDS_GWS_RESET0 0x1344 +#define regGDS_GWS_RESET0_BASE_IDX 0 +#define regGDS_GWS_RESET1 0x1345 +#define regGDS_GWS_RESET1_BASE_IDX 0 +#define regGDS_GWS_RESOURCE_RESET 0x1346 +#define regGDS_GWS_RESOURCE_RESET_BASE_IDX 0 +#define regGDS_COMPUTE_MAX_WAVE_ID 0x1348 +#define regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 0 +#define regGDS_OA_RESET_MASK 0x1349 +#define regGDS_OA_RESET_MASK_BASE_IDX 0 +#define regGDS_OA_RESET 0x134a +#define regGDS_OA_RESET_BASE_IDX 0 +#define regGDS_ENHANCE 0x134b +#define regGDS_ENHANCE_BASE_IDX 0 +#define regGDS_OA_CGPG_RESTORE 0x134c +#define regGDS_OA_CGPG_RESTORE_BASE_IDX 0 +#define regGDS_CS_CTXSW_STATUS 0x134d +#define regGDS_CS_CTXSW_STATUS_BASE_IDX 0 +#define regGDS_CS_CTXSW_CNT0 0x134e +#define regGDS_CS_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_CS_CTXSW_CNT1 0x134f +#define regGDS_CS_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_CS_CTXSW_CNT2 0x1350 +#define regGDS_CS_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_CS_CTXSW_CNT3 0x1351 +#define regGDS_CS_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_GFX_CTXSW_STATUS 0x1352 +#define regGDS_GFX_CTXSW_STATUS_BASE_IDX 0 +#define regGDS_VS_CTXSW_CNT0 0x1353 +#define regGDS_VS_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_VS_CTXSW_CNT1 0x1354 +#define regGDS_VS_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_VS_CTXSW_CNT2 0x1355 +#define regGDS_VS_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_VS_CTXSW_CNT3 0x1356 +#define regGDS_VS_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_PS0_CTXSW_CNT0 0x1357 +#define regGDS_PS0_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_PS0_CTXSW_CNT1 0x1358 +#define regGDS_PS0_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_PS0_CTXSW_CNT2 0x1359 +#define regGDS_PS0_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_PS0_CTXSW_CNT3 0x135a +#define regGDS_PS0_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_PS1_CTXSW_CNT0 0x135b +#define regGDS_PS1_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_PS1_CTXSW_CNT1 0x135c +#define regGDS_PS1_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_PS1_CTXSW_CNT2 0x135d +#define regGDS_PS1_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_PS1_CTXSW_CNT3 0x135e +#define regGDS_PS1_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_PS2_CTXSW_CNT0 0x135f +#define regGDS_PS2_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_PS2_CTXSW_CNT1 0x1360 +#define regGDS_PS2_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_PS2_CTXSW_CNT2 0x1361 +#define regGDS_PS2_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_PS2_CTXSW_CNT3 0x1362 +#define regGDS_PS2_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_PS3_CTXSW_CNT0 0x1363 +#define regGDS_PS3_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_PS3_CTXSW_CNT1 0x1364 +#define regGDS_PS3_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_PS3_CTXSW_CNT2 0x1365 +#define regGDS_PS3_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_PS3_CTXSW_CNT3 0x1366 +#define regGDS_PS3_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_PS4_CTXSW_CNT0 0x1367 +#define regGDS_PS4_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_PS4_CTXSW_CNT1 0x1368 +#define regGDS_PS4_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_PS4_CTXSW_CNT2 0x1369 +#define regGDS_PS4_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_PS4_CTXSW_CNT3 0x136a +#define regGDS_PS4_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_PS5_CTXSW_CNT0 0x136b +#define regGDS_PS5_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_PS5_CTXSW_CNT1 0x136c +#define regGDS_PS5_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_PS5_CTXSW_CNT2 0x136d +#define regGDS_PS5_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_PS5_CTXSW_CNT3 0x136e +#define regGDS_PS5_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_PS6_CTXSW_CNT0 0x136f +#define regGDS_PS6_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_PS6_CTXSW_CNT1 0x1370 +#define regGDS_PS6_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_PS6_CTXSW_CNT2 0x1371 +#define regGDS_PS6_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_PS6_CTXSW_CNT3 0x1372 +#define regGDS_PS6_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_PS7_CTXSW_CNT0 0x1373 +#define regGDS_PS7_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_PS7_CTXSW_CNT1 0x1374 +#define regGDS_PS7_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_PS7_CTXSW_CNT2 0x1375 +#define regGDS_PS7_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_PS7_CTXSW_CNT3 0x1376 +#define regGDS_PS7_CTXSW_CNT3_BASE_IDX 0 +#define regGDS_GS_CTXSW_CNT0 0x1377 +#define regGDS_GS_CTXSW_CNT0_BASE_IDX 0 +#define regGDS_GS_CTXSW_CNT1 0x1378 +#define regGDS_GS_CTXSW_CNT1_BASE_IDX 0 +#define regGDS_GS_CTXSW_CNT2 0x1379 +#define regGDS_GS_CTXSW_CNT2_BASE_IDX 0 +#define regGDS_GS_CTXSW_CNT3 0x137a +#define regGDS_GS_CTXSW_CNT3_BASE_IDX 0 + + +// addressBlock: xcd0_gc_rasdec +// base address: 0xce00 +#define regRAS_SIGNATURE_CONTROL 0x1380 +#define regRAS_SIGNATURE_CONTROL_BASE_IDX 0 +#define regRAS_SIGNATURE_MASK 0x1381 +#define regRAS_SIGNATURE_MASK_BASE_IDX 0 +#define regRAS_SX_SIGNATURE0 0x1382 +#define regRAS_SX_SIGNATURE0_BASE_IDX 0 +#define regRAS_SX_SIGNATURE1 0x1383 +#define regRAS_SX_SIGNATURE1_BASE_IDX 0 +#define regRAS_SX_SIGNATURE2 0x1384 +#define regRAS_SX_SIGNATURE2_BASE_IDX 0 +#define regRAS_SX_SIGNATURE3 0x1385 +#define regRAS_SX_SIGNATURE3_BASE_IDX 0 +#define regRAS_DB_SIGNATURE0 0x138b +#define regRAS_DB_SIGNATURE0_BASE_IDX 0 +#define regRAS_PA_SIGNATURE0 0x138c +#define regRAS_PA_SIGNATURE0_BASE_IDX 0 +#define regRAS_VGT_SIGNATURE0 0x138d +#define regRAS_VGT_SIGNATURE0_BASE_IDX 0 +#define regRAS_SQ_SIGNATURE0 0x138e +#define regRAS_SQ_SIGNATURE0_BASE_IDX 0 +#define regRAS_SC_SIGNATURE0 0x138f +#define regRAS_SC_SIGNATURE0_BASE_IDX 0 +#define regRAS_SC_SIGNATURE1 0x1390 +#define regRAS_SC_SIGNATURE1_BASE_IDX 0 +#define regRAS_SC_SIGNATURE2 0x1391 +#define regRAS_SC_SIGNATURE2_BASE_IDX 0 +#define regRAS_SC_SIGNATURE3 0x1392 +#define regRAS_SC_SIGNATURE3_BASE_IDX 0 +#define regRAS_SC_SIGNATURE4 0x1393 +#define regRAS_SC_SIGNATURE4_BASE_IDX 0 +#define regRAS_SC_SIGNATURE5 0x1394 +#define regRAS_SC_SIGNATURE5_BASE_IDX 0 +#define regRAS_SC_SIGNATURE6 0x1395 +#define regRAS_SC_SIGNATURE6_BASE_IDX 0 +#define regRAS_SC_SIGNATURE7 0x1396 +#define regRAS_SC_SIGNATURE7_BASE_IDX 0 +#define regRAS_IA_SIGNATURE0 0x1397 +#define regRAS_IA_SIGNATURE0_BASE_IDX 0 +#define regRAS_IA_SIGNATURE1 0x1398 +#define regRAS_IA_SIGNATURE1_BASE_IDX 0 +#define regRAS_SPI_SIGNATURE0 0x1399 +#define regRAS_SPI_SIGNATURE0_BASE_IDX 0 +#define regRAS_SPI_SIGNATURE1 0x139a +#define regRAS_SPI_SIGNATURE1_BASE_IDX 0 +#define regRAS_TA_SIGNATURE0 0x139b +#define regRAS_TA_SIGNATURE0_BASE_IDX 0 +#define regRAS_TD_SIGNATURE0 0x139c +#define regRAS_TD_SIGNATURE0_BASE_IDX 0 +#define regRAS_CB_SIGNATURE0 0x139d +#define regRAS_CB_SIGNATURE0_BASE_IDX 0 +#define regRAS_BCI_SIGNATURE0 0x139e +#define regRAS_BCI_SIGNATURE0_BASE_IDX 0 +#define regRAS_BCI_SIGNATURE1 0x139f +#define regRAS_BCI_SIGNATURE1_BASE_IDX 0 +#define regRAS_TA_SIGNATURE1 0x13a0 +#define regRAS_TA_SIGNATURE1_BASE_IDX 0 + + +// addressBlock: xcd0_gc_gfxdec0 +// base address: 0x28000 +#define regDB_RENDER_CONTROL 0x0000 +#define regDB_RENDER_CONTROL_BASE_IDX 1 +#define regDB_COUNT_CONTROL 0x0001 +#define regDB_COUNT_CONTROL_BASE_IDX 1 +#define regDB_DEPTH_VIEW 0x0002 +#define regDB_DEPTH_VIEW_BASE_IDX 1 +#define regDB_RENDER_OVERRIDE 0x0003 +#define regDB_RENDER_OVERRIDE_BASE_IDX 1 +#define regDB_RENDER_OVERRIDE2 0x0004 +#define regDB_RENDER_OVERRIDE2_BASE_IDX 1 +#define regDB_HTILE_DATA_BASE 0x0005 +#define regDB_HTILE_DATA_BASE_BASE_IDX 1 +#define regDB_HTILE_DATA_BASE_HI 0x0006 +#define regDB_HTILE_DATA_BASE_HI_BASE_IDX 1 +#define regDB_DEPTH_SIZE 0x0007 +#define regDB_DEPTH_SIZE_BASE_IDX 1 +#define regDB_DEPTH_BOUNDS_MIN 0x0008 +#define regDB_DEPTH_BOUNDS_MIN_BASE_IDX 1 +#define regDB_DEPTH_BOUNDS_MAX 0x0009 +#define regDB_DEPTH_BOUNDS_MAX_BASE_IDX 1 +#define regDB_STENCIL_CLEAR 0x000a +#define regDB_STENCIL_CLEAR_BASE_IDX 1 +#define regDB_DEPTH_CLEAR 0x000b +#define regDB_DEPTH_CLEAR_BASE_IDX 1 +#define regPA_SC_SCREEN_SCISSOR_TL 0x000c +#define regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1 +#define regPA_SC_SCREEN_SCISSOR_BR 0x000d +#define regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1 +#define regDB_Z_INFO 0x000e +#define regDB_Z_INFO_BASE_IDX 1 +#define regDB_STENCIL_INFO 0x000f +#define regDB_STENCIL_INFO_BASE_IDX 1 +#define regDB_Z_READ_BASE 0x0010 +#define regDB_Z_READ_BASE_BASE_IDX 1 +#define regDB_Z_READ_BASE_HI 0x0011 +#define regDB_Z_READ_BASE_HI_BASE_IDX 1 +#define regDB_STENCIL_READ_BASE 0x0012 +#define regDB_STENCIL_READ_BASE_BASE_IDX 1 +#define regDB_STENCIL_READ_BASE_HI 0x0013 +#define regDB_STENCIL_READ_BASE_HI_BASE_IDX 1 +#define regDB_Z_WRITE_BASE 0x0014 +#define regDB_Z_WRITE_BASE_BASE_IDX 1 +#define regDB_Z_WRITE_BASE_HI 0x0015 +#define regDB_Z_WRITE_BASE_HI_BASE_IDX 1 +#define regDB_STENCIL_WRITE_BASE 0x0016 +#define regDB_STENCIL_WRITE_BASE_BASE_IDX 1 +#define regDB_STENCIL_WRITE_BASE_HI 0x0017 +#define regDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 +#define regDB_DFSM_CONTROL 0x0018 +#define regDB_DFSM_CONTROL_BASE_IDX 1 +#define regDB_Z_INFO2 0x001a +#define regDB_Z_INFO2_BASE_IDX 1 +#define regDB_STENCIL_INFO2 0x001b +#define regDB_STENCIL_INFO2_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_0 0x007a +#define regCOHER_DEST_BASE_HI_0_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_1 0x007b +#define regCOHER_DEST_BASE_HI_1_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_2 0x007c +#define regCOHER_DEST_BASE_HI_2_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_3 0x007d +#define regCOHER_DEST_BASE_HI_3_BASE_IDX 1 +#define regCOHER_DEST_BASE_2 0x007e +#define regCOHER_DEST_BASE_2_BASE_IDX 1 +#define regCOHER_DEST_BASE_3 0x007f +#define regCOHER_DEST_BASE_3_BASE_IDX 1 +#define regPA_SC_WINDOW_OFFSET 0x0080 +#define regPA_SC_WINDOW_OFFSET_BASE_IDX 1 +#define regPA_SC_WINDOW_SCISSOR_TL 0x0081 +#define regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1 +#define regPA_SC_WINDOW_SCISSOR_BR 0x0082 +#define regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_RULE 0x0083 +#define regPA_SC_CLIPRECT_RULE_BASE_IDX 1 +#define regPA_SC_CLIPRECT_0_TL 0x0084 +#define regPA_SC_CLIPRECT_0_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_0_BR 0x0085 +#define regPA_SC_CLIPRECT_0_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_1_TL 0x0086 +#define regPA_SC_CLIPRECT_1_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_1_BR 0x0087 +#define regPA_SC_CLIPRECT_1_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_2_TL 0x0088 +#define regPA_SC_CLIPRECT_2_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_2_BR 0x0089 +#define regPA_SC_CLIPRECT_2_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_3_TL 0x008a +#define regPA_SC_CLIPRECT_3_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_3_BR 0x008b +#define regPA_SC_CLIPRECT_3_BR_BASE_IDX 1 +#define regPA_SC_EDGERULE 0x008c +#define regPA_SC_EDGERULE_BASE_IDX 1 +#define regPA_SU_HARDWARE_SCREEN_OFFSET 0x008d +#define regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1 +#define regCB_TARGET_MASK 0x008e +#define regCB_TARGET_MASK_BASE_IDX 1 +#define regCB_SHADER_MASK 0x008f +#define regCB_SHADER_MASK_BASE_IDX 1 +#define regPA_SC_GENERIC_SCISSOR_TL 0x0090 +#define regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1 +#define regPA_SC_GENERIC_SCISSOR_BR 0x0091 +#define regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1 +#define regCOHER_DEST_BASE_0 0x0092 +#define regCOHER_DEST_BASE_0_BASE_IDX 1 +#define regCOHER_DEST_BASE_1 0x0093 +#define regCOHER_DEST_BASE_1_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_0_TL 0x0094 +#define regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_0_BR 0x0095 +#define regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_1_TL 0x0096 +#define regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_1_BR 0x0097 +#define regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_2_TL 0x0098 +#define regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_2_BR 0x0099 +#define regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_3_TL 0x009a +#define regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_3_BR 0x009b +#define regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_4_TL 0x009c +#define regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_4_BR 0x009d +#define regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_5_TL 0x009e +#define regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_5_BR 0x009f +#define regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_6_TL 0x00a0 +#define regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_6_BR 0x00a1 +#define regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_7_TL 0x00a2 +#define regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_7_BR 0x00a3 +#define regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_8_TL 0x00a4 +#define regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_8_BR 0x00a5 +#define regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_9_TL 0x00a6 +#define regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_9_BR 0x00a7 +#define regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_10_TL 0x00a8 +#define regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_10_BR 0x00a9 +#define regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_11_TL 0x00aa +#define regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_11_BR 0x00ab +#define regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_12_TL 0x00ac +#define regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_12_BR 0x00ad +#define regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_13_TL 0x00ae +#define regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_13_BR 0x00af +#define regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_14_TL 0x00b0 +#define regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_14_BR 0x00b1 +#define regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_15_TL 0x00b2 +#define regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_15_BR 0x00b3 +#define regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_0 0x00b4 +#define regPA_SC_VPORT_ZMIN_0_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_0 0x00b5 +#define regPA_SC_VPORT_ZMAX_0_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_1 0x00b6 +#define regPA_SC_VPORT_ZMIN_1_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_1 0x00b7 +#define regPA_SC_VPORT_ZMAX_1_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_2 0x00b8 +#define regPA_SC_VPORT_ZMIN_2_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_2 0x00b9 +#define regPA_SC_VPORT_ZMAX_2_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_3 0x00ba +#define regPA_SC_VPORT_ZMIN_3_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_3 0x00bb +#define regPA_SC_VPORT_ZMAX_3_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_4 0x00bc +#define regPA_SC_VPORT_ZMIN_4_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_4 0x00bd +#define regPA_SC_VPORT_ZMAX_4_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_5 0x00be +#define regPA_SC_VPORT_ZMIN_5_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_5 0x00bf +#define regPA_SC_VPORT_ZMAX_5_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_6 0x00c0 +#define regPA_SC_VPORT_ZMIN_6_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_6 0x00c1 +#define regPA_SC_VPORT_ZMAX_6_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_7 0x00c2 +#define regPA_SC_VPORT_ZMIN_7_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_7 0x00c3 +#define regPA_SC_VPORT_ZMAX_7_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_8 0x00c4 +#define regPA_SC_VPORT_ZMIN_8_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_8 0x00c5 +#define regPA_SC_VPORT_ZMAX_8_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_9 0x00c6 +#define regPA_SC_VPORT_ZMIN_9_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_9 0x00c7 +#define regPA_SC_VPORT_ZMAX_9_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_10 0x00c8 +#define regPA_SC_VPORT_ZMIN_10_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_10 0x00c9 +#define regPA_SC_VPORT_ZMAX_10_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_11 0x00ca +#define regPA_SC_VPORT_ZMIN_11_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_11 0x00cb +#define regPA_SC_VPORT_ZMAX_11_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_12 0x00cc +#define regPA_SC_VPORT_ZMIN_12_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_12 0x00cd +#define regPA_SC_VPORT_ZMAX_12_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_13 0x00ce +#define regPA_SC_VPORT_ZMIN_13_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_13 0x00cf +#define regPA_SC_VPORT_ZMAX_13_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_14 0x00d0 +#define regPA_SC_VPORT_ZMIN_14_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_14 0x00d1 +#define regPA_SC_VPORT_ZMAX_14_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_15 0x00d2 +#define regPA_SC_VPORT_ZMIN_15_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_15 0x00d3 +#define regPA_SC_VPORT_ZMAX_15_BASE_IDX 1 +#define regPA_SC_RASTER_CONFIG 0x00d4 +#define regPA_SC_RASTER_CONFIG_BASE_IDX 1 +#define regPA_SC_RASTER_CONFIG_1 0x00d5 +#define regPA_SC_RASTER_CONFIG_1_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_CONTROL 0x00d6 +#define regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1 +#define regPA_SC_TILE_STEERING_OVERRIDE 0x00d7 +#define regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1 +#define regCP_PERFMON_CNTX_CNTL 0x00d8 +#define regCP_PERFMON_CNTX_CNTL_BASE_IDX 1 +#define regCP_PIPEID 0x00d9 +#define regCP_PIPEID_BASE_IDX 1 +#define regCP_RINGID 0x00d9 +#define regCP_RINGID_BASE_IDX 1 +#define regCP_VMID 0x00da +#define regCP_VMID_BASE_IDX 1 +#define regPA_SC_RIGHT_VERT_GRID 0x00e8 +#define regPA_SC_RIGHT_VERT_GRID_BASE_IDX 1 +#define regPA_SC_LEFT_VERT_GRID 0x00e9 +#define regPA_SC_LEFT_VERT_GRID_BASE_IDX 1 +#define regPA_SC_HORIZ_GRID 0x00ea +#define regPA_SC_HORIZ_GRID_BASE_IDX 1 +#define regVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 +#define regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 +#define regCB_BLEND_RED 0x0105 +#define regCB_BLEND_RED_BASE_IDX 1 +#define regCB_BLEND_GREEN 0x0106 +#define regCB_BLEND_GREEN_BASE_IDX 1 +#define regCB_BLEND_BLUE 0x0107 +#define regCB_BLEND_BLUE_BASE_IDX 1 +#define regCB_BLEND_ALPHA 0x0108 +#define regCB_BLEND_ALPHA_BASE_IDX 1 +#define regCB_DCC_CONTROL 0x0109 +#define regCB_DCC_CONTROL_BASE_IDX 1 +#define regDB_STENCIL_CONTROL 0x010b +#define regDB_STENCIL_CONTROL_BASE_IDX 1 +#define regDB_STENCILREFMASK 0x010c +#define regDB_STENCILREFMASK_BASE_IDX 1 +#define regDB_STENCILREFMASK_BF 0x010d +#define regDB_STENCILREFMASK_BF_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE 0x010f +#define regPA_CL_VPORT_XSCALE_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET 0x0110 +#define regPA_CL_VPORT_XOFFSET_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE 0x0111 +#define regPA_CL_VPORT_YSCALE_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET 0x0112 +#define regPA_CL_VPORT_YOFFSET_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE 0x0113 +#define regPA_CL_VPORT_ZSCALE_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET 0x0114 +#define regPA_CL_VPORT_ZOFFSET_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_1 0x0115 +#define regPA_CL_VPORT_XSCALE_1_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_1 0x0116 +#define regPA_CL_VPORT_XOFFSET_1_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_1 0x0117 +#define regPA_CL_VPORT_YSCALE_1_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_1 0x0118 +#define regPA_CL_VPORT_YOFFSET_1_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_1 0x0119 +#define regPA_CL_VPORT_ZSCALE_1_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_1 0x011a +#define regPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_2 0x011b +#define regPA_CL_VPORT_XSCALE_2_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_2 0x011c +#define regPA_CL_VPORT_XOFFSET_2_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_2 0x011d +#define regPA_CL_VPORT_YSCALE_2_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_2 0x011e +#define regPA_CL_VPORT_YOFFSET_2_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_2 0x011f +#define regPA_CL_VPORT_ZSCALE_2_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_2 0x0120 +#define regPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_3 0x0121 +#define regPA_CL_VPORT_XSCALE_3_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_3 0x0122 +#define regPA_CL_VPORT_XOFFSET_3_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_3 0x0123 +#define regPA_CL_VPORT_YSCALE_3_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_3 0x0124 +#define regPA_CL_VPORT_YOFFSET_3_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_3 0x0125 +#define regPA_CL_VPORT_ZSCALE_3_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_3 0x0126 +#define regPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_4 0x0127 +#define regPA_CL_VPORT_XSCALE_4_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_4 0x0128 +#define regPA_CL_VPORT_XOFFSET_4_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_4 0x0129 +#define regPA_CL_VPORT_YSCALE_4_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_4 0x012a +#define regPA_CL_VPORT_YOFFSET_4_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_4 0x012b +#define regPA_CL_VPORT_ZSCALE_4_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_4 0x012c +#define regPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_5 0x012d +#define regPA_CL_VPORT_XSCALE_5_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_5 0x012e +#define regPA_CL_VPORT_XOFFSET_5_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_5 0x012f +#define regPA_CL_VPORT_YSCALE_5_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_5 0x0130 +#define regPA_CL_VPORT_YOFFSET_5_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_5 0x0131 +#define regPA_CL_VPORT_ZSCALE_5_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_5 0x0132 +#define regPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_6 0x0133 +#define regPA_CL_VPORT_XSCALE_6_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_6 0x0134 +#define regPA_CL_VPORT_XOFFSET_6_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_6 0x0135 +#define regPA_CL_VPORT_YSCALE_6_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_6 0x0136 +#define regPA_CL_VPORT_YOFFSET_6_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_6 0x0137 +#define regPA_CL_VPORT_ZSCALE_6_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_6 0x0138 +#define regPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_7 0x0139 +#define regPA_CL_VPORT_XSCALE_7_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_7 0x013a +#define regPA_CL_VPORT_XOFFSET_7_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_7 0x013b +#define regPA_CL_VPORT_YSCALE_7_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_7 0x013c +#define regPA_CL_VPORT_YOFFSET_7_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_7 0x013d +#define regPA_CL_VPORT_ZSCALE_7_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_7 0x013e +#define regPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_8 0x013f +#define regPA_CL_VPORT_XSCALE_8_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_8 0x0140 +#define regPA_CL_VPORT_XOFFSET_8_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_8 0x0141 +#define regPA_CL_VPORT_YSCALE_8_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_8 0x0142 +#define regPA_CL_VPORT_YOFFSET_8_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_8 0x0143 +#define regPA_CL_VPORT_ZSCALE_8_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_8 0x0144 +#define regPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_9 0x0145 +#define regPA_CL_VPORT_XSCALE_9_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_9 0x0146 +#define regPA_CL_VPORT_XOFFSET_9_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_9 0x0147 +#define regPA_CL_VPORT_YSCALE_9_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_9 0x0148 +#define regPA_CL_VPORT_YOFFSET_9_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_9 0x0149 +#define regPA_CL_VPORT_ZSCALE_9_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_9 0x014a +#define regPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_10 0x014b +#define regPA_CL_VPORT_XSCALE_10_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_10 0x014c +#define regPA_CL_VPORT_XOFFSET_10_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_10 0x014d +#define regPA_CL_VPORT_YSCALE_10_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_10 0x014e +#define regPA_CL_VPORT_YOFFSET_10_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_10 0x014f +#define regPA_CL_VPORT_ZSCALE_10_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_10 0x0150 +#define regPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_11 0x0151 +#define regPA_CL_VPORT_XSCALE_11_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_11 0x0152 +#define regPA_CL_VPORT_XOFFSET_11_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_11 0x0153 +#define regPA_CL_VPORT_YSCALE_11_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_11 0x0154 +#define regPA_CL_VPORT_YOFFSET_11_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_11 0x0155 +#define regPA_CL_VPORT_ZSCALE_11_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_11 0x0156 +#define regPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_12 0x0157 +#define regPA_CL_VPORT_XSCALE_12_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_12 0x0158 +#define regPA_CL_VPORT_XOFFSET_12_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_12 0x0159 +#define regPA_CL_VPORT_YSCALE_12_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_12 0x015a +#define regPA_CL_VPORT_YOFFSET_12_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_12 0x015b +#define regPA_CL_VPORT_ZSCALE_12_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_12 0x015c +#define regPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_13 0x015d +#define regPA_CL_VPORT_XSCALE_13_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_13 0x015e +#define regPA_CL_VPORT_XOFFSET_13_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_13 0x015f +#define regPA_CL_VPORT_YSCALE_13_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_13 0x0160 +#define regPA_CL_VPORT_YOFFSET_13_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_13 0x0161 +#define regPA_CL_VPORT_ZSCALE_13_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_13 0x0162 +#define regPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_14 0x0163 +#define regPA_CL_VPORT_XSCALE_14_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_14 0x0164 +#define regPA_CL_VPORT_XOFFSET_14_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_14 0x0165 +#define regPA_CL_VPORT_YSCALE_14_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_14 0x0166 +#define regPA_CL_VPORT_YOFFSET_14_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_14 0x0167 +#define regPA_CL_VPORT_ZSCALE_14_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_14 0x0168 +#define regPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_15 0x0169 +#define regPA_CL_VPORT_XSCALE_15_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_15 0x016a +#define regPA_CL_VPORT_XOFFSET_15_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_15 0x016b +#define regPA_CL_VPORT_YSCALE_15_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_15 0x016c +#define regPA_CL_VPORT_YOFFSET_15_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_15 0x016d +#define regPA_CL_VPORT_ZSCALE_15_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_15 0x016e +#define regPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1 +#define regPA_CL_UCP_0_X 0x016f +#define regPA_CL_UCP_0_X_BASE_IDX 1 +#define regPA_CL_UCP_0_Y 0x0170 +#define regPA_CL_UCP_0_Y_BASE_IDX 1 +#define regPA_CL_UCP_0_Z 0x0171 +#define regPA_CL_UCP_0_Z_BASE_IDX 1 +#define regPA_CL_UCP_0_W 0x0172 +#define regPA_CL_UCP_0_W_BASE_IDX 1 +#define regPA_CL_UCP_1_X 0x0173 +#define regPA_CL_UCP_1_X_BASE_IDX 1 +#define regPA_CL_UCP_1_Y 0x0174 +#define regPA_CL_UCP_1_Y_BASE_IDX 1 +#define regPA_CL_UCP_1_Z 0x0175 +#define regPA_CL_UCP_1_Z_BASE_IDX 1 +#define regPA_CL_UCP_1_W 0x0176 +#define regPA_CL_UCP_1_W_BASE_IDX 1 +#define regPA_CL_UCP_2_X 0x0177 +#define regPA_CL_UCP_2_X_BASE_IDX 1 +#define regPA_CL_UCP_2_Y 0x0178 +#define regPA_CL_UCP_2_Y_BASE_IDX 1 +#define regPA_CL_UCP_2_Z 0x0179 +#define regPA_CL_UCP_2_Z_BASE_IDX 1 +#define regPA_CL_UCP_2_W 0x017a +#define regPA_CL_UCP_2_W_BASE_IDX 1 +#define regPA_CL_UCP_3_X 0x017b +#define regPA_CL_UCP_3_X_BASE_IDX 1 +#define regPA_CL_UCP_3_Y 0x017c +#define regPA_CL_UCP_3_Y_BASE_IDX 1 +#define regPA_CL_UCP_3_Z 0x017d +#define regPA_CL_UCP_3_Z_BASE_IDX 1 +#define regPA_CL_UCP_3_W 0x017e +#define regPA_CL_UCP_3_W_BASE_IDX 1 +#define regPA_CL_UCP_4_X 0x017f +#define regPA_CL_UCP_4_X_BASE_IDX 1 +#define regPA_CL_UCP_4_Y 0x0180 +#define regPA_CL_UCP_4_Y_BASE_IDX 1 +#define regPA_CL_UCP_4_Z 0x0181 +#define regPA_CL_UCP_4_Z_BASE_IDX 1 +#define regPA_CL_UCP_4_W 0x0182 +#define regPA_CL_UCP_4_W_BASE_IDX 1 +#define regPA_CL_UCP_5_X 0x0183 +#define regPA_CL_UCP_5_X_BASE_IDX 1 +#define regPA_CL_UCP_5_Y 0x0184 +#define regPA_CL_UCP_5_Y_BASE_IDX 1 +#define regPA_CL_UCP_5_Z 0x0185 +#define regPA_CL_UCP_5_Z_BASE_IDX 1 +#define regPA_CL_UCP_5_W 0x0186 +#define regPA_CL_UCP_5_W_BASE_IDX 1 +#define regPA_CL_PROG_NEAR_CLIP_Z 0x0187 +#define regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_0 0x0191 +#define regSPI_PS_INPUT_CNTL_0_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_1 0x0192 +#define regSPI_PS_INPUT_CNTL_1_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_2 0x0193 +#define regSPI_PS_INPUT_CNTL_2_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_3 0x0194 +#define regSPI_PS_INPUT_CNTL_3_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_4 0x0195 +#define regSPI_PS_INPUT_CNTL_4_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_5 0x0196 +#define regSPI_PS_INPUT_CNTL_5_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_6 0x0197 +#define regSPI_PS_INPUT_CNTL_6_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_7 0x0198 +#define regSPI_PS_INPUT_CNTL_7_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_8 0x0199 +#define regSPI_PS_INPUT_CNTL_8_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_9 0x019a +#define regSPI_PS_INPUT_CNTL_9_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_10 0x019b +#define regSPI_PS_INPUT_CNTL_10_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_11 0x019c +#define regSPI_PS_INPUT_CNTL_11_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_12 0x019d +#define regSPI_PS_INPUT_CNTL_12_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_13 0x019e +#define regSPI_PS_INPUT_CNTL_13_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_14 0x019f +#define regSPI_PS_INPUT_CNTL_14_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_15 0x01a0 +#define regSPI_PS_INPUT_CNTL_15_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_16 0x01a1 +#define regSPI_PS_INPUT_CNTL_16_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_17 0x01a2 +#define regSPI_PS_INPUT_CNTL_17_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_18 0x01a3 +#define regSPI_PS_INPUT_CNTL_18_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_19 0x01a4 +#define regSPI_PS_INPUT_CNTL_19_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_20 0x01a5 +#define regSPI_PS_INPUT_CNTL_20_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_21 0x01a6 +#define regSPI_PS_INPUT_CNTL_21_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_22 0x01a7 +#define regSPI_PS_INPUT_CNTL_22_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_23 0x01a8 +#define regSPI_PS_INPUT_CNTL_23_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_24 0x01a9 +#define regSPI_PS_INPUT_CNTL_24_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_25 0x01aa +#define regSPI_PS_INPUT_CNTL_25_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_26 0x01ab +#define regSPI_PS_INPUT_CNTL_26_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_27 0x01ac +#define regSPI_PS_INPUT_CNTL_27_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_28 0x01ad +#define regSPI_PS_INPUT_CNTL_28_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_29 0x01ae +#define regSPI_PS_INPUT_CNTL_29_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_30 0x01af +#define regSPI_PS_INPUT_CNTL_30_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_31 0x01b0 +#define regSPI_PS_INPUT_CNTL_31_BASE_IDX 1 +#define regSPI_VS_OUT_CONFIG 0x01b1 +#define regSPI_VS_OUT_CONFIG_BASE_IDX 1 +#define regSPI_PS_INPUT_ENA 0x01b3 +#define regSPI_PS_INPUT_ENA_BASE_IDX 1 +#define regSPI_PS_INPUT_ADDR 0x01b4 +#define regSPI_PS_INPUT_ADDR_BASE_IDX 1 +#define regSPI_INTERP_CONTROL_0 0x01b5 +#define regSPI_INTERP_CONTROL_0_BASE_IDX 1 +#define regSPI_PS_IN_CONTROL 0x01b6 +#define regSPI_PS_IN_CONTROL_BASE_IDX 1 +#define regSPI_BARYC_CNTL 0x01b8 +#define regSPI_BARYC_CNTL_BASE_IDX 1 +#define regSPI_TMPRING_SIZE 0x01ba +#define regSPI_TMPRING_SIZE_BASE_IDX 1 +#define regSPI_SHADER_POS_FORMAT 0x01c3 +#define regSPI_SHADER_POS_FORMAT_BASE_IDX 1 +#define regSPI_SHADER_Z_FORMAT 0x01c4 +#define regSPI_SHADER_Z_FORMAT_BASE_IDX 1 +#define regSPI_SHADER_COL_FORMAT 0x01c5 +#define regSPI_SHADER_COL_FORMAT_BASE_IDX 1 +#define regCB_BLEND0_CONTROL 0x01e0 +#define regCB_BLEND0_CONTROL_BASE_IDX 1 +#define regCB_BLEND1_CONTROL 0x01e1 +#define regCB_BLEND1_CONTROL_BASE_IDX 1 +#define regCB_BLEND2_CONTROL 0x01e2 +#define regCB_BLEND2_CONTROL_BASE_IDX 1 +#define regCB_BLEND3_CONTROL 0x01e3 +#define regCB_BLEND3_CONTROL_BASE_IDX 1 +#define regCB_BLEND4_CONTROL 0x01e4 +#define regCB_BLEND4_CONTROL_BASE_IDX 1 +#define regCB_BLEND5_CONTROL 0x01e5 +#define regCB_BLEND5_CONTROL_BASE_IDX 1 +#define regCB_BLEND6_CONTROL 0x01e6 +#define regCB_BLEND6_CONTROL_BASE_IDX 1 +#define regCB_BLEND7_CONTROL 0x01e7 +#define regCB_BLEND7_CONTROL_BASE_IDX 1 +#define regCB_MRT0_EPITCH 0x01e8 +#define regCB_MRT0_EPITCH_BASE_IDX 1 +#define regCB_MRT1_EPITCH 0x01e9 +#define regCB_MRT1_EPITCH_BASE_IDX 1 +#define regCB_MRT2_EPITCH 0x01ea +#define regCB_MRT2_EPITCH_BASE_IDX 1 +#define regCB_MRT3_EPITCH 0x01eb +#define regCB_MRT3_EPITCH_BASE_IDX 1 +#define regCB_MRT4_EPITCH 0x01ec +#define regCB_MRT4_EPITCH_BASE_IDX 1 +#define regCB_MRT5_EPITCH 0x01ed +#define regCB_MRT5_EPITCH_BASE_IDX 1 +#define regCB_MRT6_EPITCH 0x01ee +#define regCB_MRT6_EPITCH_BASE_IDX 1 +#define regCB_MRT7_EPITCH 0x01ef +#define regCB_MRT7_EPITCH_BASE_IDX 1 +#define regCS_COPY_STATE 0x01f3 +#define regCS_COPY_STATE_BASE_IDX 1 +#define regGFX_COPY_STATE 0x01f4 +#define regGFX_COPY_STATE_BASE_IDX 1 +#define regPA_CL_POINT_X_RAD 0x01f5 +#define regPA_CL_POINT_X_RAD_BASE_IDX 1 +#define regPA_CL_POINT_Y_RAD 0x01f6 +#define regPA_CL_POINT_Y_RAD_BASE_IDX 1 +#define regPA_CL_POINT_SIZE 0x01f7 +#define regPA_CL_POINT_SIZE_BASE_IDX 1 +#define regPA_CL_POINT_CULL_RAD 0x01f8 +#define regPA_CL_POINT_CULL_RAD_BASE_IDX 1 +#define regVGT_DMA_BASE_HI 0x01f9 +#define regVGT_DMA_BASE_HI_BASE_IDX 1 +#define regVGT_DMA_BASE 0x01fa +#define regVGT_DMA_BASE_BASE_IDX 1 +#define regVGT_DRAW_INITIATOR 0x01fc +#define regVGT_DRAW_INITIATOR_BASE_IDX 1 +#define regVGT_IMMED_DATA 0x01fd +#define regVGT_IMMED_DATA_BASE_IDX 1 +#define regVGT_EVENT_ADDRESS_REG 0x01fe +#define regVGT_EVENT_ADDRESS_REG_BASE_IDX 1 +#define regDB_DEPTH_CONTROL 0x0200 +#define regDB_DEPTH_CONTROL_BASE_IDX 1 +#define regDB_EQAA 0x0201 +#define regDB_EQAA_BASE_IDX 1 +#define regCB_COLOR_CONTROL 0x0202 +#define regCB_COLOR_CONTROL_BASE_IDX 1 +#define regDB_SHADER_CONTROL 0x0203 +#define regDB_SHADER_CONTROL_BASE_IDX 1 +#define regPA_CL_CLIP_CNTL 0x0204 +#define regPA_CL_CLIP_CNTL_BASE_IDX 1 +#define regPA_SU_SC_MODE_CNTL 0x0205 +#define regPA_SU_SC_MODE_CNTL_BASE_IDX 1 +#define regPA_CL_VTE_CNTL 0x0206 +#define regPA_CL_VTE_CNTL_BASE_IDX 1 +#define regPA_CL_VS_OUT_CNTL 0x0207 +#define regPA_CL_VS_OUT_CNTL_BASE_IDX 1 +#define regPA_CL_NANINF_CNTL 0x0208 +#define regPA_CL_NANINF_CNTL_BASE_IDX 1 +#define regPA_SU_LINE_STIPPLE_CNTL 0x0209 +#define regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX 1 +#define regPA_SU_LINE_STIPPLE_SCALE 0x020a +#define regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX 1 +#define regPA_SU_PRIM_FILTER_CNTL 0x020b +#define regPA_SU_PRIM_FILTER_CNTL_BASE_IDX 1 +#define regPA_SU_SMALL_PRIM_FILTER_CNTL 0x020c +#define regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX 1 +#define regPA_CL_OBJPRIM_ID_CNTL 0x020d +#define regPA_CL_OBJPRIM_ID_CNTL_BASE_IDX 1 +#define regPA_CL_NGG_CNTL 0x020e +#define regPA_CL_NGG_CNTL_BASE_IDX 1 +#define regPA_SU_OVER_RASTERIZATION_CNTL 0x020f +#define regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX 1 +#define regPA_STEREO_CNTL 0x0210 +#define regPA_STEREO_CNTL_BASE_IDX 1 +#define regPA_SU_POINT_SIZE 0x0280 +#define regPA_SU_POINT_SIZE_BASE_IDX 1 +#define regPA_SU_POINT_MINMAX 0x0281 +#define regPA_SU_POINT_MINMAX_BASE_IDX 1 +#define regPA_SU_LINE_CNTL 0x0282 +#define regPA_SU_LINE_CNTL_BASE_IDX 1 +#define regPA_SC_LINE_STIPPLE 0x0283 +#define regPA_SC_LINE_STIPPLE_BASE_IDX 1 +#define regVGT_OUTPUT_PATH_CNTL 0x0284 +#define regVGT_OUTPUT_PATH_CNTL_BASE_IDX 1 +#define regVGT_HOS_CNTL 0x0285 +#define regVGT_HOS_CNTL_BASE_IDX 1 +#define regVGT_HOS_MAX_TESS_LEVEL 0x0286 +#define regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX 1 +#define regVGT_HOS_MIN_TESS_LEVEL 0x0287 +#define regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX 1 +#define regVGT_HOS_REUSE_DEPTH 0x0288 +#define regVGT_HOS_REUSE_DEPTH_BASE_IDX 1 +#define regVGT_GROUP_PRIM_TYPE 0x0289 +#define regVGT_GROUP_PRIM_TYPE_BASE_IDX 1 +#define regVGT_GROUP_FIRST_DECR 0x028a +#define regVGT_GROUP_FIRST_DECR_BASE_IDX 1 +#define regVGT_GROUP_DECR 0x028b +#define regVGT_GROUP_DECR_BASE_IDX 1 +#define regVGT_GROUP_VECT_0_CNTL 0x028c +#define regVGT_GROUP_VECT_0_CNTL_BASE_IDX 1 +#define regVGT_GROUP_VECT_1_CNTL 0x028d +#define regVGT_GROUP_VECT_1_CNTL_BASE_IDX 1 +#define regVGT_GROUP_VECT_0_FMT_CNTL 0x028e +#define regVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX 1 +#define regVGT_GROUP_VECT_1_FMT_CNTL 0x028f +#define regVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX 1 +#define regVGT_GS_MODE 0x0290 +#define regVGT_GS_MODE_BASE_IDX 1 +#define regVGT_GS_ONCHIP_CNTL 0x0291 +#define regVGT_GS_ONCHIP_CNTL_BASE_IDX 1 +#define regPA_SC_MODE_CNTL_0 0x0292 +#define regPA_SC_MODE_CNTL_0_BASE_IDX 1 +#define regPA_SC_MODE_CNTL_1 0x0293 +#define regPA_SC_MODE_CNTL_1_BASE_IDX 1 +#define regVGT_ENHANCE 0x0294 +#define regVGT_ENHANCE_BASE_IDX 1 +#define regVGT_GS_PER_ES 0x0295 +#define regVGT_GS_PER_ES_BASE_IDX 1 +#define regVGT_ES_PER_GS 0x0296 +#define regVGT_ES_PER_GS_BASE_IDX 1 +#define regVGT_GS_PER_VS 0x0297 +#define regVGT_GS_PER_VS_BASE_IDX 1 +#define regVGT_GSVS_RING_OFFSET_1 0x0298 +#define regVGT_GSVS_RING_OFFSET_1_BASE_IDX 1 +#define regVGT_GSVS_RING_OFFSET_2 0x0299 +#define regVGT_GSVS_RING_OFFSET_2_BASE_IDX 1 +#define regVGT_GSVS_RING_OFFSET_3 0x029a +#define regVGT_GSVS_RING_OFFSET_3_BASE_IDX 1 +#define regVGT_GS_OUT_PRIM_TYPE 0x029b +#define regVGT_GS_OUT_PRIM_TYPE_BASE_IDX 1 +#define regIA_ENHANCE 0x029c +#define regIA_ENHANCE_BASE_IDX 1 +#define regVGT_DMA_SIZE 0x029d +#define regVGT_DMA_SIZE_BASE_IDX 1 +#define regVGT_DMA_MAX_SIZE 0x029e +#define regVGT_DMA_MAX_SIZE_BASE_IDX 1 +#define regVGT_DMA_INDEX_TYPE 0x029f +#define regVGT_DMA_INDEX_TYPE_BASE_IDX 1 +#define regWD_ENHANCE 0x02a0 +#define regWD_ENHANCE_BASE_IDX 1 +#define regVGT_PRIMITIVEID_EN 0x02a1 +#define regVGT_PRIMITIVEID_EN_BASE_IDX 1 +#define regVGT_DMA_NUM_INSTANCES 0x02a2 +#define regVGT_DMA_NUM_INSTANCES_BASE_IDX 1 +#define regVGT_PRIMITIVEID_RESET 0x02a3 +#define regVGT_PRIMITIVEID_RESET_BASE_IDX 1 +#define regVGT_EVENT_INITIATOR 0x02a4 +#define regVGT_EVENT_INITIATOR_BASE_IDX 1 +#define regVGT_GS_MAX_PRIMS_PER_SUBGROUP 0x02a5 +#define regVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1 +#define regVGT_DRAW_PAYLOAD_CNTL 0x02a6 +#define regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 +#define regVGT_INSTANCE_STEP_RATE_0 0x02a8 +#define regVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1 +#define regVGT_INSTANCE_STEP_RATE_1 0x02a9 +#define regVGT_INSTANCE_STEP_RATE_1_BASE_IDX 1 +#define regIA_MULTI_VGT_PARAM_BC 0x02aa +#define regIA_MULTI_VGT_PARAM_BC_BASE_IDX 1 +#define regVGT_ESGS_RING_ITEMSIZE 0x02ab +#define regVGT_ESGS_RING_ITEMSIZE_BASE_IDX 1 +#define regVGT_GSVS_RING_ITEMSIZE 0x02ac +#define regVGT_GSVS_RING_ITEMSIZE_BASE_IDX 1 +#define regVGT_REUSE_OFF 0x02ad +#define regVGT_REUSE_OFF_BASE_IDX 1 +#define regVGT_VTX_CNT_EN 0x02ae +#define regVGT_VTX_CNT_EN_BASE_IDX 1 +#define regDB_HTILE_SURFACE 0x02af +#define regDB_HTILE_SURFACE_BASE_IDX 1 +#define regDB_SRESULTS_COMPARE_STATE0 0x02b0 +#define regDB_SRESULTS_COMPARE_STATE0_BASE_IDX 1 +#define regDB_SRESULTS_COMPARE_STATE1 0x02b1 +#define regDB_SRESULTS_COMPARE_STATE1_BASE_IDX 1 +#define regDB_PRELOAD_CONTROL 0x02b2 +#define regDB_PRELOAD_CONTROL_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_SIZE_0 0x02b4 +#define regVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX 1 +#define regVGT_STRMOUT_VTX_STRIDE_0 0x02b5 +#define regVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_OFFSET_0 0x02b7 +#define regVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_SIZE_1 0x02b8 +#define regVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX 1 +#define regVGT_STRMOUT_VTX_STRIDE_1 0x02b9 +#define regVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_OFFSET_1 0x02bb +#define regVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_SIZE_2 0x02bc +#define regVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX 1 +#define regVGT_STRMOUT_VTX_STRIDE_2 0x02bd +#define regVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_OFFSET_2 0x02bf +#define regVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_SIZE_3 0x02c0 +#define regVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX 1 +#define regVGT_STRMOUT_VTX_STRIDE_3 0x02c1 +#define regVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_OFFSET_3 0x02c3 +#define regVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX 1 +#define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x02ca +#define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX 1 +#define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x02cb +#define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX 1 +#define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x02cc +#define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX 1 +#define regVGT_GS_MAX_VERT_OUT 0x02ce +#define regVGT_GS_MAX_VERT_OUT_BASE_IDX 1 +#define regVGT_TESS_DISTRIBUTION 0x02d4 +#define regVGT_TESS_DISTRIBUTION_BASE_IDX 1 +#define regVGT_SHADER_STAGES_EN 0x02d5 +#define regVGT_SHADER_STAGES_EN_BASE_IDX 1 +#define regVGT_LS_HS_CONFIG 0x02d6 +#define regVGT_LS_HS_CONFIG_BASE_IDX 1 +#define regVGT_GS_VERT_ITEMSIZE 0x02d7 +#define regVGT_GS_VERT_ITEMSIZE_BASE_IDX 1 +#define regVGT_GS_VERT_ITEMSIZE_1 0x02d8 +#define regVGT_GS_VERT_ITEMSIZE_1_BASE_IDX 1 +#define regVGT_GS_VERT_ITEMSIZE_2 0x02d9 +#define regVGT_GS_VERT_ITEMSIZE_2_BASE_IDX 1 +#define regVGT_GS_VERT_ITEMSIZE_3 0x02da +#define regVGT_GS_VERT_ITEMSIZE_3_BASE_IDX 1 +#define regVGT_TF_PARAM 0x02db +#define regVGT_TF_PARAM_BASE_IDX 1 +#define regDB_ALPHA_TO_MASK 0x02dc +#define regDB_ALPHA_TO_MASK_BASE_IDX 1 +#define regVGT_DISPATCH_DRAW_INDEX 0x02dd +#define regVGT_DISPATCH_DRAW_INDEX_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_DB_FMT_CNTL 0x02de +#define regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_CLAMP 0x02df +#define regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_FRONT_SCALE 0x02e0 +#define regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_FRONT_OFFSET 0x02e1 +#define regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_BACK_SCALE 0x02e2 +#define regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_BACK_OFFSET 0x02e3 +#define regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX 1 +#define regVGT_GS_INSTANCE_CNT 0x02e4 +#define regVGT_GS_INSTANCE_CNT_BASE_IDX 1 +#define regVGT_STRMOUT_CONFIG 0x02e5 +#define regVGT_STRMOUT_CONFIG_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_CONFIG 0x02e6 +#define regVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX 1 +#define regVGT_DMA_EVENT_INITIATOR 0x02e7 +#define regVGT_DMA_EVENT_INITIATOR_BASE_IDX 1 +#define regPA_SC_CENTROID_PRIORITY_0 0x02f5 +#define regPA_SC_CENTROID_PRIORITY_0_BASE_IDX 1 +#define regPA_SC_CENTROID_PRIORITY_1 0x02f6 +#define regPA_SC_CENTROID_PRIORITY_1_BASE_IDX 1 +#define regPA_SC_LINE_CNTL 0x02f7 +#define regPA_SC_LINE_CNTL_BASE_IDX 1 +#define regPA_SC_AA_CONFIG 0x02f8 +#define regPA_SC_AA_CONFIG_BASE_IDX 1 +#define regPA_SU_VTX_CNTL 0x02f9 +#define regPA_SU_VTX_CNTL_BASE_IDX 1 +#define regPA_CL_GB_VERT_CLIP_ADJ 0x02fa +#define regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX 1 +#define regPA_CL_GB_VERT_DISC_ADJ 0x02fb +#define regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX 1 +#define regPA_CL_GB_HORZ_CLIP_ADJ 0x02fc +#define regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX 1 +#define regPA_CL_GB_HORZ_DISC_ADJ 0x02fd +#define regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x02fe +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x02ff +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x0300 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x0301 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x0302 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x0303 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x0304 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x0305 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x0306 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x0307 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x0308 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x0309 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x030a +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x030b +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x030c +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x030d +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX 1 +#define regPA_SC_AA_MASK_X0Y0_X1Y0 0x030e +#define regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 1 +#define regPA_SC_AA_MASK_X0Y1_X1Y1 0x030f +#define regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 1 +#define regPA_SC_SHADER_CONTROL 0x0310 +#define regPA_SC_SHADER_CONTROL_BASE_IDX 1 +#define regPA_SC_BINNER_CNTL_0 0x0311 +#define regPA_SC_BINNER_CNTL_0_BASE_IDX 1 +#define regPA_SC_BINNER_CNTL_1 0x0312 +#define regPA_SC_BINNER_CNTL_1_BASE_IDX 1 +#define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0x0313 +#define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX 1 +#define regPA_SC_NGG_MODE_CNTL 0x0314 +#define regPA_SC_NGG_MODE_CNTL_BASE_IDX 1 +#define regVGT_VERTEX_REUSE_BLOCK_CNTL 0x0316 +#define regVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX 1 +#define regVGT_OUT_DEALLOC_CNTL 0x0317 +#define regVGT_OUT_DEALLOC_CNTL_BASE_IDX 1 +#define regCB_COLOR0_BASE 0x0318 +#define regCB_COLOR0_BASE_BASE_IDX 1 +#define regCB_COLOR0_BASE_EXT 0x0319 +#define regCB_COLOR0_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR0_ATTRIB2 0x031a +#define regCB_COLOR0_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR0_VIEW 0x031b +#define regCB_COLOR0_VIEW_BASE_IDX 1 +#define regCB_COLOR0_INFO 0x031c +#define regCB_COLOR0_INFO_BASE_IDX 1 +#define regCB_COLOR0_ATTRIB 0x031d +#define regCB_COLOR0_ATTRIB_BASE_IDX 1 +#define regCB_COLOR0_DCC_CONTROL 0x031e +#define regCB_COLOR0_DCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR0_CMASK 0x031f +#define regCB_COLOR0_CMASK_BASE_IDX 1 +#define regCB_COLOR0_CMASK_BASE_EXT 0x0320 +#define regCB_COLOR0_CMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR0_FMASK 0x0321 +#define regCB_COLOR0_FMASK_BASE_IDX 1 +#define regCB_COLOR0_FMASK_BASE_EXT 0x0322 +#define regCB_COLOR0_FMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR0_CLEAR_WORD0 0x0323 +#define regCB_COLOR0_CLEAR_WORD0_BASE_IDX 1 +#define regCB_COLOR0_CLEAR_WORD1 0x0324 +#define regCB_COLOR0_CLEAR_WORD1_BASE_IDX 1 +#define regCB_COLOR0_DCC_BASE 0x0325 +#define regCB_COLOR0_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR0_DCC_BASE_EXT 0x0326 +#define regCB_COLOR0_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR1_BASE 0x0327 +#define regCB_COLOR1_BASE_BASE_IDX 1 +#define regCB_COLOR1_BASE_EXT 0x0328 +#define regCB_COLOR1_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR1_ATTRIB2 0x0329 +#define regCB_COLOR1_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR1_VIEW 0x032a +#define regCB_COLOR1_VIEW_BASE_IDX 1 +#define regCB_COLOR1_INFO 0x032b +#define regCB_COLOR1_INFO_BASE_IDX 1 +#define regCB_COLOR1_ATTRIB 0x032c +#define regCB_COLOR1_ATTRIB_BASE_IDX 1 +#define regCB_COLOR1_DCC_CONTROL 0x032d +#define regCB_COLOR1_DCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR1_CMASK 0x032e +#define regCB_COLOR1_CMASK_BASE_IDX 1 +#define regCB_COLOR1_CMASK_BASE_EXT 0x032f +#define regCB_COLOR1_CMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR1_FMASK 0x0330 +#define regCB_COLOR1_FMASK_BASE_IDX 1 +#define regCB_COLOR1_FMASK_BASE_EXT 0x0331 +#define regCB_COLOR1_FMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR1_CLEAR_WORD0 0x0332 +#define regCB_COLOR1_CLEAR_WORD0_BASE_IDX 1 +#define regCB_COLOR1_CLEAR_WORD1 0x0333 +#define regCB_COLOR1_CLEAR_WORD1_BASE_IDX 1 +#define regCB_COLOR1_DCC_BASE 0x0334 +#define regCB_COLOR1_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR1_DCC_BASE_EXT 0x0335 +#define regCB_COLOR1_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR2_BASE 0x0336 +#define regCB_COLOR2_BASE_BASE_IDX 1 +#define regCB_COLOR2_BASE_EXT 0x0337 +#define regCB_COLOR2_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR2_ATTRIB2 0x0338 +#define regCB_COLOR2_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR2_VIEW 0x0339 +#define regCB_COLOR2_VIEW_BASE_IDX 1 +#define regCB_COLOR2_INFO 0x033a +#define regCB_COLOR2_INFO_BASE_IDX 1 +#define regCB_COLOR2_ATTRIB 0x033b +#define regCB_COLOR2_ATTRIB_BASE_IDX 1 +#define regCB_COLOR2_DCC_CONTROL 0x033c +#define regCB_COLOR2_DCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR2_CMASK 0x033d +#define regCB_COLOR2_CMASK_BASE_IDX 1 +#define regCB_COLOR2_CMASK_BASE_EXT 0x033e +#define regCB_COLOR2_CMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR2_FMASK 0x033f +#define regCB_COLOR2_FMASK_BASE_IDX 1 +#define regCB_COLOR2_FMASK_BASE_EXT 0x0340 +#define regCB_COLOR2_FMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR2_CLEAR_WORD0 0x0341 +#define regCB_COLOR2_CLEAR_WORD0_BASE_IDX 1 +#define regCB_COLOR2_CLEAR_WORD1 0x0342 +#define regCB_COLOR2_CLEAR_WORD1_BASE_IDX 1 +#define regCB_COLOR2_DCC_BASE 0x0343 +#define regCB_COLOR2_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR2_DCC_BASE_EXT 0x0344 +#define regCB_COLOR2_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR3_BASE 0x0345 +#define regCB_COLOR3_BASE_BASE_IDX 1 +#define regCB_COLOR3_BASE_EXT 0x0346 +#define regCB_COLOR3_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR3_ATTRIB2 0x0347 +#define regCB_COLOR3_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR3_VIEW 0x0348 +#define regCB_COLOR3_VIEW_BASE_IDX 1 +#define regCB_COLOR3_INFO 0x0349 +#define regCB_COLOR3_INFO_BASE_IDX 1 +#define regCB_COLOR3_ATTRIB 0x034a +#define regCB_COLOR3_ATTRIB_BASE_IDX 1 +#define regCB_COLOR3_DCC_CONTROL 0x034b +#define regCB_COLOR3_DCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR3_CMASK 0x034c +#define regCB_COLOR3_CMASK_BASE_IDX 1 +#define regCB_COLOR3_CMASK_BASE_EXT 0x034d +#define regCB_COLOR3_CMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR3_FMASK 0x034e +#define regCB_COLOR3_FMASK_BASE_IDX 1 +#define regCB_COLOR3_FMASK_BASE_EXT 0x034f +#define regCB_COLOR3_FMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR3_CLEAR_WORD0 0x0350 +#define regCB_COLOR3_CLEAR_WORD0_BASE_IDX 1 +#define regCB_COLOR3_CLEAR_WORD1 0x0351 +#define regCB_COLOR3_CLEAR_WORD1_BASE_IDX 1 +#define regCB_COLOR3_DCC_BASE 0x0352 +#define regCB_COLOR3_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR3_DCC_BASE_EXT 0x0353 +#define regCB_COLOR3_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR4_BASE 0x0354 +#define regCB_COLOR4_BASE_BASE_IDX 1 +#define regCB_COLOR4_BASE_EXT 0x0355 +#define regCB_COLOR4_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR4_ATTRIB2 0x0356 +#define regCB_COLOR4_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR4_VIEW 0x0357 +#define regCB_COLOR4_VIEW_BASE_IDX 1 +#define regCB_COLOR4_INFO 0x0358 +#define regCB_COLOR4_INFO_BASE_IDX 1 +#define regCB_COLOR4_ATTRIB 0x0359 +#define regCB_COLOR4_ATTRIB_BASE_IDX 1 +#define regCB_COLOR4_DCC_CONTROL 0x035a +#define regCB_COLOR4_DCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR4_CMASK 0x035b +#define regCB_COLOR4_CMASK_BASE_IDX 1 +#define regCB_COLOR4_CMASK_BASE_EXT 0x035c +#define regCB_COLOR4_CMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR4_FMASK 0x035d +#define regCB_COLOR4_FMASK_BASE_IDX 1 +#define regCB_COLOR4_FMASK_BASE_EXT 0x035e +#define regCB_COLOR4_FMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR4_CLEAR_WORD0 0x035f +#define regCB_COLOR4_CLEAR_WORD0_BASE_IDX 1 +#define regCB_COLOR4_CLEAR_WORD1 0x0360 +#define regCB_COLOR4_CLEAR_WORD1_BASE_IDX 1 +#define regCB_COLOR4_DCC_BASE 0x0361 +#define regCB_COLOR4_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR4_DCC_BASE_EXT 0x0362 +#define regCB_COLOR4_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR5_BASE 0x0363 +#define regCB_COLOR5_BASE_BASE_IDX 1 +#define regCB_COLOR5_BASE_EXT 0x0364 +#define regCB_COLOR5_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR5_ATTRIB2 0x0365 +#define regCB_COLOR5_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR5_VIEW 0x0366 +#define regCB_COLOR5_VIEW_BASE_IDX 1 +#define regCB_COLOR5_INFO 0x0367 +#define regCB_COLOR5_INFO_BASE_IDX 1 +#define regCB_COLOR5_ATTRIB 0x0368 +#define regCB_COLOR5_ATTRIB_BASE_IDX 1 +#define regCB_COLOR5_DCC_CONTROL 0x0369 +#define regCB_COLOR5_DCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR5_CMASK 0x036a +#define regCB_COLOR5_CMASK_BASE_IDX 1 +#define regCB_COLOR5_CMASK_BASE_EXT 0x036b +#define regCB_COLOR5_CMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR5_FMASK 0x036c +#define regCB_COLOR5_FMASK_BASE_IDX 1 +#define regCB_COLOR5_FMASK_BASE_EXT 0x036d +#define regCB_COLOR5_FMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR5_CLEAR_WORD0 0x036e +#define regCB_COLOR5_CLEAR_WORD0_BASE_IDX 1 +#define regCB_COLOR5_CLEAR_WORD1 0x036f +#define regCB_COLOR5_CLEAR_WORD1_BASE_IDX 1 +#define regCB_COLOR5_DCC_BASE 0x0370 +#define regCB_COLOR5_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR5_DCC_BASE_EXT 0x0371 +#define regCB_COLOR5_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR6_BASE 0x0372 +#define regCB_COLOR6_BASE_BASE_IDX 1 +#define regCB_COLOR6_BASE_EXT 0x0373 +#define regCB_COLOR6_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR6_ATTRIB2 0x0374 +#define regCB_COLOR6_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR6_VIEW 0x0375 +#define regCB_COLOR6_VIEW_BASE_IDX 1 +#define regCB_COLOR6_INFO 0x0376 +#define regCB_COLOR6_INFO_BASE_IDX 1 +#define regCB_COLOR6_ATTRIB 0x0377 +#define regCB_COLOR6_ATTRIB_BASE_IDX 1 +#define regCB_COLOR6_DCC_CONTROL 0x0378 +#define regCB_COLOR6_DCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR6_CMASK 0x0379 +#define regCB_COLOR6_CMASK_BASE_IDX 1 +#define regCB_COLOR6_CMASK_BASE_EXT 0x037a +#define regCB_COLOR6_CMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR6_FMASK 0x037b +#define regCB_COLOR6_FMASK_BASE_IDX 1 +#define regCB_COLOR6_FMASK_BASE_EXT 0x037c +#define regCB_COLOR6_FMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR6_CLEAR_WORD0 0x037d +#define regCB_COLOR6_CLEAR_WORD0_BASE_IDX 1 +#define regCB_COLOR6_CLEAR_WORD1 0x037e +#define regCB_COLOR6_CLEAR_WORD1_BASE_IDX 1 +#define regCB_COLOR6_DCC_BASE 0x037f +#define regCB_COLOR6_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR6_DCC_BASE_EXT 0x0380 +#define regCB_COLOR6_DCC_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR7_BASE 0x0381 +#define regCB_COLOR7_BASE_BASE_IDX 1 +#define regCB_COLOR7_BASE_EXT 0x0382 +#define regCB_COLOR7_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR7_ATTRIB2 0x0383 +#define regCB_COLOR7_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR7_VIEW 0x0384 +#define regCB_COLOR7_VIEW_BASE_IDX 1 +#define regCB_COLOR7_INFO 0x0385 +#define regCB_COLOR7_INFO_BASE_IDX 1 +#define regCB_COLOR7_ATTRIB 0x0386 +#define regCB_COLOR7_ATTRIB_BASE_IDX 1 +#define regCB_COLOR7_DCC_CONTROL 0x0387 +#define regCB_COLOR7_DCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR7_CMASK 0x0388 +#define regCB_COLOR7_CMASK_BASE_IDX 1 +#define regCB_COLOR7_CMASK_BASE_EXT 0x0389 +#define regCB_COLOR7_CMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR7_FMASK 0x038a +#define regCB_COLOR7_FMASK_BASE_IDX 1 +#define regCB_COLOR7_FMASK_BASE_EXT 0x038b +#define regCB_COLOR7_FMASK_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR7_CLEAR_WORD0 0x038c +#define regCB_COLOR7_CLEAR_WORD0_BASE_IDX 1 +#define regCB_COLOR7_CLEAR_WORD1 0x038d +#define regCB_COLOR7_CLEAR_WORD1_BASE_IDX 1 +#define regCB_COLOR7_DCC_BASE 0x038e +#define regCB_COLOR7_DCC_BASE_BASE_IDX 1 +#define regCB_COLOR7_DCC_BASE_EXT 0x038f +#define regCB_COLOR7_DCC_BASE_EXT_BASE_IDX 1 + + +// addressBlock: xcd0_gc_gfxudec +// base address: 0x30000 +#define regCP_EOP_DONE_ADDR_LO 0x2000 +#define regCP_EOP_DONE_ADDR_LO_BASE_IDX 1 +#define regCP_EOP_DONE_ADDR_HI 0x2001 +#define regCP_EOP_DONE_ADDR_HI_BASE_IDX 1 +#define regCP_EOP_DONE_DATA_LO 0x2002 +#define regCP_EOP_DONE_DATA_LO_BASE_IDX 1 +#define regCP_EOP_DONE_DATA_HI 0x2003 +#define regCP_EOP_DONE_DATA_HI_BASE_IDX 1 +#define regCP_EOP_LAST_FENCE_LO 0x2004 +#define regCP_EOP_LAST_FENCE_LO_BASE_IDX 1 +#define regCP_EOP_LAST_FENCE_HI 0x2005 +#define regCP_EOP_LAST_FENCE_HI_BASE_IDX 1 +#define regCP_STREAM_OUT_ADDR_LO 0x2006 +#define regCP_STREAM_OUT_ADDR_LO_BASE_IDX 1 +#define regCP_STREAM_OUT_ADDR_HI 0x2007 +#define regCP_STREAM_OUT_ADDR_HI_BASE_IDX 1 +#define regCP_NUM_PRIM_WRITTEN_COUNT0_LO 0x2008 +#define regCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX 1 +#define regCP_NUM_PRIM_WRITTEN_COUNT0_HI 0x2009 +#define regCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX 1 +#define regCP_NUM_PRIM_NEEDED_COUNT0_LO 0x200a +#define regCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX 1 +#define regCP_NUM_PRIM_NEEDED_COUNT0_HI 0x200b +#define regCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX 1 +#define regCP_NUM_PRIM_WRITTEN_COUNT1_LO 0x200c +#define regCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX 1 +#define regCP_NUM_PRIM_WRITTEN_COUNT1_HI 0x200d +#define regCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX 1 +#define regCP_NUM_PRIM_NEEDED_COUNT1_LO 0x200e +#define regCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX 1 +#define regCP_NUM_PRIM_NEEDED_COUNT1_HI 0x200f +#define regCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX 1 +#define regCP_NUM_PRIM_WRITTEN_COUNT2_LO 0x2010 +#define regCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX 1 +#define regCP_NUM_PRIM_WRITTEN_COUNT2_HI 0x2011 +#define regCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX 1 +#define regCP_NUM_PRIM_NEEDED_COUNT2_LO 0x2012 +#define regCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX 1 +#define regCP_NUM_PRIM_NEEDED_COUNT2_HI 0x2013 +#define regCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX 1 +#define regCP_NUM_PRIM_WRITTEN_COUNT3_LO 0x2014 +#define regCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX 1 +#define regCP_NUM_PRIM_WRITTEN_COUNT3_HI 0x2015 +#define regCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX 1 +#define regCP_NUM_PRIM_NEEDED_COUNT3_LO 0x2016 +#define regCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX 1 +#define regCP_NUM_PRIM_NEEDED_COUNT3_HI 0x2017 +#define regCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX 1 +#define regCP_PIPE_STATS_ADDR_LO 0x2018 +#define regCP_PIPE_STATS_ADDR_LO_BASE_IDX 1 +#define regCP_PIPE_STATS_ADDR_HI 0x2019 +#define regCP_PIPE_STATS_ADDR_HI_BASE_IDX 1 +#define regCP_VGT_IAVERT_COUNT_LO 0x201a +#define regCP_VGT_IAVERT_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_IAVERT_COUNT_HI 0x201b +#define regCP_VGT_IAVERT_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_IAPRIM_COUNT_LO 0x201c +#define regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_IAPRIM_COUNT_HI 0x201d +#define regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_GSPRIM_COUNT_LO 0x201e +#define regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_GSPRIM_COUNT_HI 0x201f +#define regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_VSINVOC_COUNT_LO 0x2020 +#define regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_VSINVOC_COUNT_HI 0x2021 +#define regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_GSINVOC_COUNT_LO 0x2022 +#define regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_GSINVOC_COUNT_HI 0x2023 +#define regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_HSINVOC_COUNT_LO 0x2024 +#define regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_HSINVOC_COUNT_HI 0x2025 +#define regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_DSINVOC_COUNT_LO 0x2026 +#define regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_DSINVOC_COUNT_HI 0x2027 +#define regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_PA_CINVOC_COUNT_LO 0x2028 +#define regCP_PA_CINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_PA_CINVOC_COUNT_HI 0x2029 +#define regCP_PA_CINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_PA_CPRIM_COUNT_LO 0x202a +#define regCP_PA_CPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_PA_CPRIM_COUNT_HI 0x202b +#define regCP_PA_CPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT0_LO 0x202c +#define regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT0_HI 0x202d +#define regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT1_LO 0x202e +#define regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT1_HI 0x202f +#define regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX 1 +#define regCP_VGT_CSINVOC_COUNT_LO 0x2030 +#define regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_CSINVOC_COUNT_HI 0x2031 +#define regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_PIPE_STATS_CONTROL 0x203d +#define regCP_PIPE_STATS_CONTROL_BASE_IDX 1 +#define regCP_STREAM_OUT_CONTROL 0x203e +#define regCP_STREAM_OUT_CONTROL_BASE_IDX 1 +#define regCP_STRMOUT_CNTL 0x203f +#define regCP_STRMOUT_CNTL_BASE_IDX 1 +#define regSCRATCH_REG0 0x2040 +#define regSCRATCH_REG0_BASE_IDX 1 +#define regSCRATCH_REG1 0x2041 +#define regSCRATCH_REG1_BASE_IDX 1 +#define regSCRATCH_REG2 0x2042 +#define regSCRATCH_REG2_BASE_IDX 1 +#define regSCRATCH_REG3 0x2043 +#define regSCRATCH_REG3_BASE_IDX 1 +#define regSCRATCH_REG4 0x2044 +#define regSCRATCH_REG4_BASE_IDX 1 +#define regSCRATCH_REG5 0x2045 +#define regSCRATCH_REG5_BASE_IDX 1 +#define regSCRATCH_REG6 0x2046 +#define regSCRATCH_REG6_BASE_IDX 1 +#define regSCRATCH_REG7 0x2047 +#define regSCRATCH_REG7_BASE_IDX 1 +#define regCP_APPEND_DATA_HI 0x204c +#define regCP_APPEND_DATA_HI_BASE_IDX 1 +#define regCP_APPEND_LAST_CS_FENCE_HI 0x204d +#define regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX 1 +#define regCP_APPEND_LAST_PS_FENCE_HI 0x204e +#define regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX 1 +#define regSCRATCH_UMSK 0x2050 +#define regSCRATCH_UMSK_BASE_IDX 1 +#define regSCRATCH_ADDR 0x2051 +#define regSCRATCH_ADDR_BASE_IDX 1 +#define regCP_PFP_ATOMIC_PREOP_LO 0x2052 +#define regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX 1 +#define regCP_PFP_ATOMIC_PREOP_HI 0x2053 +#define regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX 1 +#define regCP_PFP_GDS_ATOMIC0_PREOP_LO 0x2054 +#define regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 +#define regCP_PFP_GDS_ATOMIC0_PREOP_HI 0x2055 +#define regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 +#define regCP_PFP_GDS_ATOMIC1_PREOP_LO 0x2056 +#define regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 +#define regCP_PFP_GDS_ATOMIC1_PREOP_HI 0x2057 +#define regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 +#define regCP_APPEND_ADDR_LO 0x2058 +#define regCP_APPEND_ADDR_LO_BASE_IDX 1 +#define regCP_APPEND_ADDR_HI 0x2059 +#define regCP_APPEND_ADDR_HI_BASE_IDX 1 +#define regCP_APPEND_DATA_LO 0x205a +#define regCP_APPEND_DATA_LO_BASE_IDX 1 +#define regCP_APPEND_LAST_CS_FENCE_LO 0x205b +#define regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX 1 +#define regCP_APPEND_LAST_PS_FENCE_LO 0x205c +#define regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX 1 +#define regCP_ATOMIC_PREOP_LO 0x205d +#define regCP_ATOMIC_PREOP_LO_BASE_IDX 1 +#define regCP_ME_ATOMIC_PREOP_LO 0x205d +#define regCP_ME_ATOMIC_PREOP_LO_BASE_IDX 1 +#define regCP_ATOMIC_PREOP_HI 0x205e +#define regCP_ATOMIC_PREOP_HI_BASE_IDX 1 +#define regCP_ME_ATOMIC_PREOP_HI 0x205e +#define regCP_ME_ATOMIC_PREOP_HI_BASE_IDX 1 +#define regCP_GDS_ATOMIC0_PREOP_LO 0x205f +#define regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 +#define regCP_ME_GDS_ATOMIC0_PREOP_LO 0x205f +#define regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 +#define regCP_GDS_ATOMIC0_PREOP_HI 0x2060 +#define regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 +#define regCP_ME_GDS_ATOMIC0_PREOP_HI 0x2060 +#define regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 +#define regCP_GDS_ATOMIC1_PREOP_LO 0x2061 +#define regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 +#define regCP_ME_GDS_ATOMIC1_PREOP_LO 0x2061 +#define regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 +#define regCP_GDS_ATOMIC1_PREOP_HI 0x2062 +#define regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 +#define regCP_ME_GDS_ATOMIC1_PREOP_HI 0x2062 +#define regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 +#define regCP_ME_MC_WADDR_LO 0x2069 +#define regCP_ME_MC_WADDR_LO_BASE_IDX 1 +#define regCP_ME_MC_WADDR_HI 0x206a +#define regCP_ME_MC_WADDR_HI_BASE_IDX 1 +#define regCP_ME_MC_WDATA_LO 0x206b +#define regCP_ME_MC_WDATA_LO_BASE_IDX 1 +#define regCP_ME_MC_WDATA_HI 0x206c +#define regCP_ME_MC_WDATA_HI_BASE_IDX 1 +#define regCP_ME_MC_RADDR_LO 0x206d +#define regCP_ME_MC_RADDR_LO_BASE_IDX 1 +#define regCP_ME_MC_RADDR_HI 0x206e +#define regCP_ME_MC_RADDR_HI_BASE_IDX 1 +#define regCP_SEM_WAIT_TIMER 0x206f +#define regCP_SEM_WAIT_TIMER_BASE_IDX 1 +#define regCP_SIG_SEM_ADDR_LO 0x2070 +#define regCP_SIG_SEM_ADDR_LO_BASE_IDX 1 +#define regCP_SIG_SEM_ADDR_HI 0x2071 +#define regCP_SIG_SEM_ADDR_HI_BASE_IDX 1 +#define regCP_WAIT_REG_MEM_TIMEOUT 0x2074 +#define regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX 1 +#define regCP_WAIT_SEM_ADDR_LO 0x2075 +#define regCP_WAIT_SEM_ADDR_LO_BASE_IDX 1 +#define regCP_WAIT_SEM_ADDR_HI 0x2076 +#define regCP_WAIT_SEM_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_PFP_CONTROL 0x2077 +#define regCP_DMA_PFP_CONTROL_BASE_IDX 1 +#define regCP_DMA_ME_CONTROL 0x2078 +#define regCP_DMA_ME_CONTROL_BASE_IDX 1 +#define regCP_COHER_BASE_HI 0x2079 +#define regCP_COHER_BASE_HI_BASE_IDX 1 +#define regCP_COHER_START_DELAY 0x207b +#define regCP_COHER_START_DELAY_BASE_IDX 1 +#define regCP_COHER_CNTL 0x207c +#define regCP_COHER_CNTL_BASE_IDX 1 +#define regCP_COHER_SIZE 0x207d +#define regCP_COHER_SIZE_BASE_IDX 1 +#define regCP_COHER_BASE 0x207e +#define regCP_COHER_BASE_BASE_IDX 1 +#define regCP_COHER_STATUS 0x207f +#define regCP_COHER_STATUS_BASE_IDX 1 +#define regCP_DMA_ME_SRC_ADDR 0x2080 +#define regCP_DMA_ME_SRC_ADDR_BASE_IDX 1 +#define regCP_DMA_ME_SRC_ADDR_HI 0x2081 +#define regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_ME_DST_ADDR 0x2082 +#define regCP_DMA_ME_DST_ADDR_BASE_IDX 1 +#define regCP_DMA_ME_DST_ADDR_HI 0x2083 +#define regCP_DMA_ME_DST_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_ME_COMMAND 0x2084 +#define regCP_DMA_ME_COMMAND_BASE_IDX 1 +#define regCP_DMA_PFP_SRC_ADDR 0x2085 +#define regCP_DMA_PFP_SRC_ADDR_BASE_IDX 1 +#define regCP_DMA_PFP_SRC_ADDR_HI 0x2086 +#define regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_PFP_DST_ADDR 0x2087 +#define regCP_DMA_PFP_DST_ADDR_BASE_IDX 1 +#define regCP_DMA_PFP_DST_ADDR_HI 0x2088 +#define regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_PFP_COMMAND 0x2089 +#define regCP_DMA_PFP_COMMAND_BASE_IDX 1 +#define regCP_DMA_CNTL 0x208a +#define regCP_DMA_CNTL_BASE_IDX 1 +#define regCP_DMA_READ_TAGS 0x208b +#define regCP_DMA_READ_TAGS_BASE_IDX 1 +#define regCP_COHER_SIZE_HI 0x208c +#define regCP_COHER_SIZE_HI_BASE_IDX 1 +#define regCP_PFP_IB_CONTROL 0x208d +#define regCP_PFP_IB_CONTROL_BASE_IDX 1 +#define regCP_PFP_LOAD_CONTROL 0x208e +#define regCP_PFP_LOAD_CONTROL_BASE_IDX 1 +#define regCP_SCRATCH_INDEX 0x208f +#define regCP_SCRATCH_INDEX_BASE_IDX 1 +#define regCP_SCRATCH_DATA 0x2090 +#define regCP_SCRATCH_DATA_BASE_IDX 1 +#define regCP_RB_OFFSET 0x2091 +#define regCP_RB_OFFSET_BASE_IDX 1 +#define regCP_IB1_OFFSET 0x2092 +#define regCP_IB1_OFFSET_BASE_IDX 1 +#define regCP_IB2_OFFSET 0x2093 +#define regCP_IB2_OFFSET_BASE_IDX 1 +#define regCP_IB1_PREAMBLE_BEGIN 0x2094 +#define regCP_IB1_PREAMBLE_BEGIN_BASE_IDX 1 +#define regCP_IB1_PREAMBLE_END 0x2095 +#define regCP_IB1_PREAMBLE_END_BASE_IDX 1 +#define regCP_IB2_PREAMBLE_BEGIN 0x2096 +#define regCP_IB2_PREAMBLE_BEGIN_BASE_IDX 1 +#define regCP_IB2_PREAMBLE_END 0x2097 +#define regCP_IB2_PREAMBLE_END_BASE_IDX 1 +#define regCP_CE_IB1_OFFSET 0x2098 +#define regCP_CE_IB1_OFFSET_BASE_IDX 1 +#define regCP_CE_IB2_OFFSET 0x2099 +#define regCP_CE_IB2_OFFSET_BASE_IDX 1 +#define regCP_CE_COUNTER 0x209a +#define regCP_CE_COUNTER_BASE_IDX 1 +#define regCP_CE_RB_OFFSET 0x209b +#define regCP_CE_RB_OFFSET_BASE_IDX 1 +#define regCP_CE_INIT_CMD_BUFSZ 0x20bd +#define regCP_CE_INIT_CMD_BUFSZ_BASE_IDX 1 +#define regCP_CE_IB1_CMD_BUFSZ 0x20be +#define regCP_CE_IB1_CMD_BUFSZ_BASE_IDX 1 +#define regCP_CE_IB2_CMD_BUFSZ 0x20bf +#define regCP_CE_IB2_CMD_BUFSZ_BASE_IDX 1 +#define regCP_IB1_CMD_BUFSZ 0x20c0 +#define regCP_IB1_CMD_BUFSZ_BASE_IDX 1 +#define regCP_IB2_CMD_BUFSZ 0x20c1 +#define regCP_IB2_CMD_BUFSZ_BASE_IDX 1 +#define regCP_ST_CMD_BUFSZ 0x20c2 +#define regCP_ST_CMD_BUFSZ_BASE_IDX 1 +#define regCP_CE_INIT_BASE_LO 0x20c3 +#define regCP_CE_INIT_BASE_LO_BASE_IDX 1 +#define regCP_CE_INIT_BASE_HI 0x20c4 +#define regCP_CE_INIT_BASE_HI_BASE_IDX 1 +#define regCP_CE_INIT_BUFSZ 0x20c5 +#define regCP_CE_INIT_BUFSZ_BASE_IDX 1 +#define regCP_CE_IB1_BASE_LO 0x20c6 +#define regCP_CE_IB1_BASE_LO_BASE_IDX 1 +#define regCP_CE_IB1_BASE_HI 0x20c7 +#define regCP_CE_IB1_BASE_HI_BASE_IDX 1 +#define regCP_CE_IB1_BUFSZ 0x20c8 +#define regCP_CE_IB1_BUFSZ_BASE_IDX 1 +#define regCP_CE_IB2_BASE_LO 0x20c9 +#define regCP_CE_IB2_BASE_LO_BASE_IDX 1 +#define regCP_CE_IB2_BASE_HI 0x20ca +#define regCP_CE_IB2_BASE_HI_BASE_IDX 1 +#define regCP_CE_IB2_BUFSZ 0x20cb +#define regCP_CE_IB2_BUFSZ_BASE_IDX 1 +#define regCP_IB1_BASE_LO 0x20cc +#define regCP_IB1_BASE_LO_BASE_IDX 1 +#define regCP_IB1_BASE_HI 0x20cd +#define regCP_IB1_BASE_HI_BASE_IDX 1 +#define regCP_IB1_BUFSZ 0x20ce +#define regCP_IB1_BUFSZ_BASE_IDX 1 +#define regCP_IB2_BASE_LO 0x20cf +#define regCP_IB2_BASE_LO_BASE_IDX 1 +#define regCP_IB2_BASE_HI 0x20d0 +#define regCP_IB2_BASE_HI_BASE_IDX 1 +#define regCP_IB2_BUFSZ 0x20d1 +#define regCP_IB2_BUFSZ_BASE_IDX 1 +#define regCP_ST_BASE_LO 0x20d2 +#define regCP_ST_BASE_LO_BASE_IDX 1 +#define regCP_ST_BASE_HI 0x20d3 +#define regCP_ST_BASE_HI_BASE_IDX 1 +#define regCP_ST_BUFSZ 0x20d4 +#define regCP_ST_BUFSZ_BASE_IDX 1 +#define regCP_EOP_DONE_EVENT_CNTL 0x20d5 +#define regCP_EOP_DONE_EVENT_CNTL_BASE_IDX 1 +#define regCP_EOP_DONE_DATA_CNTL 0x20d6 +#define regCP_EOP_DONE_DATA_CNTL_BASE_IDX 1 +#define regCP_EOP_DONE_CNTX_ID 0x20d7 +#define regCP_EOP_DONE_CNTX_ID_BASE_IDX 1 +#define regCP_PFP_COMPLETION_STATUS 0x20ec +#define regCP_PFP_COMPLETION_STATUS_BASE_IDX 1 +#define regCP_CE_COMPLETION_STATUS 0x20ed +#define regCP_CE_COMPLETION_STATUS_BASE_IDX 1 +#define regCP_PRED_NOT_VISIBLE 0x20ee +#define regCP_PRED_NOT_VISIBLE_BASE_IDX 1 +#define regCP_PFP_METADATA_BASE_ADDR 0x20f0 +#define regCP_PFP_METADATA_BASE_ADDR_BASE_IDX 1 +#define regCP_PFP_METADATA_BASE_ADDR_HI 0x20f1 +#define regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX 1 +#define regCP_CE_METADATA_BASE_ADDR 0x20f2 +#define regCP_CE_METADATA_BASE_ADDR_BASE_IDX 1 +#define regCP_CE_METADATA_BASE_ADDR_HI 0x20f3 +#define regCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX 1 +#define regCP_DRAW_INDX_INDR_ADDR 0x20f4 +#define regCP_DRAW_INDX_INDR_ADDR_BASE_IDX 1 +#define regCP_DRAW_INDX_INDR_ADDR_HI 0x20f5 +#define regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX 1 +#define regCP_DISPATCH_INDR_ADDR 0x20f6 +#define regCP_DISPATCH_INDR_ADDR_BASE_IDX 1 +#define regCP_DISPATCH_INDR_ADDR_HI 0x20f7 +#define regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX 1 +#define regCP_INDEX_BASE_ADDR 0x20f8 +#define regCP_INDEX_BASE_ADDR_BASE_IDX 1 +#define regCP_INDEX_BASE_ADDR_HI 0x20f9 +#define regCP_INDEX_BASE_ADDR_HI_BASE_IDX 1 +#define regCP_INDEX_TYPE 0x20fa +#define regCP_INDEX_TYPE_BASE_IDX 1 +#define regCP_GDS_BKUP_ADDR 0x20fb +#define regCP_GDS_BKUP_ADDR_BASE_IDX 1 +#define regCP_GDS_BKUP_ADDR_HI 0x20fc +#define regCP_GDS_BKUP_ADDR_HI_BASE_IDX 1 +#define regCP_SAMPLE_STATUS 0x20fd +#define regCP_SAMPLE_STATUS_BASE_IDX 1 +#define regCP_ME_COHER_CNTL 0x20fe +#define regCP_ME_COHER_CNTL_BASE_IDX 1 +#define regCP_ME_COHER_SIZE 0x20ff +#define regCP_ME_COHER_SIZE_BASE_IDX 1 +#define regCP_ME_COHER_SIZE_HI 0x2100 +#define regCP_ME_COHER_SIZE_HI_BASE_IDX 1 +#define regCP_ME_COHER_BASE 0x2101 +#define regCP_ME_COHER_BASE_BASE_IDX 1 +#define regCP_ME_COHER_BASE_HI 0x2102 +#define regCP_ME_COHER_BASE_HI_BASE_IDX 1 +#define regCP_ME_COHER_STATUS 0x2103 +#define regCP_ME_COHER_STATUS_BASE_IDX 1 +#define regRLC_GPM_PERF_COUNT_0 0x2140 +#define regRLC_GPM_PERF_COUNT_0_BASE_IDX 1 +#define regRLC_GPM_PERF_COUNT_1 0x2141 +#define regRLC_GPM_PERF_COUNT_1_BASE_IDX 1 +#define regGRBM_GFX_INDEX 0x2200 +#define regGRBM_GFX_INDEX_BASE_IDX 1 +#define regVGT_GSVS_RING_SIZE 0x2241 +#define regVGT_GSVS_RING_SIZE_BASE_IDX 1 +#define regVGT_PRIMITIVE_TYPE 0x2242 +#define regVGT_PRIMITIVE_TYPE_BASE_IDX 1 +#define regVGT_INDEX_TYPE 0x2243 +#define regVGT_INDEX_TYPE_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x2244 +#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x2245 +#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x2246 +#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX 1 +#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x2247 +#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX 1 +#define regVGT_MAX_VTX_INDX 0x2248 +#define regVGT_MAX_VTX_INDX_BASE_IDX 1 +#define regVGT_MIN_VTX_INDX 0x2249 +#define regVGT_MIN_VTX_INDX_BASE_IDX 1 +#define regVGT_INDX_OFFSET 0x224a +#define regVGT_INDX_OFFSET_BASE_IDX 1 +#define regVGT_MULTI_PRIM_IB_RESET_EN 0x224b +#define regVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1 +#define regVGT_NUM_INDICES 0x224c +#define regVGT_NUM_INDICES_BASE_IDX 1 +#define regVGT_NUM_INSTANCES 0x224d +#define regVGT_NUM_INSTANCES_BASE_IDX 1 +#define regVGT_TF_RING_SIZE 0x224e +#define regVGT_TF_RING_SIZE_BASE_IDX 1 +#define regVGT_HS_OFFCHIP_PARAM 0x224f +#define regVGT_HS_OFFCHIP_PARAM_BASE_IDX 1 +#define regVGT_TF_MEMORY_BASE 0x2250 +#define regVGT_TF_MEMORY_BASE_BASE_IDX 1 +#define regVGT_TF_MEMORY_BASE_HI 0x2251 +#define regVGT_TF_MEMORY_BASE_HI_BASE_IDX 1 +#define regWD_POS_BUF_BASE 0x2252 +#define regWD_POS_BUF_BASE_BASE_IDX 1 +#define regWD_POS_BUF_BASE_HI 0x2253 +#define regWD_POS_BUF_BASE_HI_BASE_IDX 1 +#define regWD_CNTL_SB_BUF_BASE 0x2254 +#define regWD_CNTL_SB_BUF_BASE_BASE_IDX 1 +#define regWD_CNTL_SB_BUF_BASE_HI 0x2255 +#define regWD_CNTL_SB_BUF_BASE_HI_BASE_IDX 1 +#define regWD_INDEX_BUF_BASE 0x2256 +#define regWD_INDEX_BUF_BASE_BASE_IDX 1 +#define regWD_INDEX_BUF_BASE_HI 0x2257 +#define regWD_INDEX_BUF_BASE_HI_BASE_IDX 1 +#define regIA_MULTI_VGT_PARAM 0x2258 +#define regIA_MULTI_VGT_PARAM_BASE_IDX 1 +#define regVGT_INSTANCE_BASE_ID 0x225a +#define regVGT_INSTANCE_BASE_ID_BASE_IDX 1 +#define regPA_SU_LINE_STIPPLE_VALUE 0x2280 +#define regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX 1 +#define regPA_SC_LINE_STIPPLE_STATE 0x2281 +#define regPA_SC_LINE_STIPPLE_STATE_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MIN_0 0x2284 +#define regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MAX_0 0x2285 +#define regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MIN_1 0x2286 +#define regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MAX_1 0x228b +#define regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_HV_EN 0x22a0 +#define regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_H 0x22a1 +#define regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_V 0x22a2 +#define regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0x22a3 +#define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_COUNT 0x22a4 +#define regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_EN 0x22a8 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_H 0x22a9 +#define regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_V 0x22aa +#define regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0x22ab +#define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_COUNT 0x22ac +#define regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_HV_EN 0x22b0 +#define regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_H 0x22b1 +#define regPA_SC_TRAP_SCREEN_H_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_V 0x22b2 +#define regPA_SC_TRAP_SCREEN_V_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_OCCURRENCE 0x22b3 +#define regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_COUNT 0x22b4 +#define regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX 1 +#define regPA_STATE_STEREO_X 0x22b5 +#define regPA_STATE_STEREO_X_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BASE 0x2330 +#define regSQ_THREAD_TRACE_BASE_BASE_IDX 1 +#define regSQ_THREAD_TRACE_SIZE 0x2331 +#define regSQ_THREAD_TRACE_SIZE_BASE_IDX 1 +#define regSQ_THREAD_TRACE_MASK 0x2332 +#define regSQ_THREAD_TRACE_MASK_BASE_IDX 1 +#define regSQ_THREAD_TRACE_TOKEN_MASK 0x2333 +#define regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX 1 +#define regSQ_THREAD_TRACE_PERF_MASK 0x2334 +#define regSQ_THREAD_TRACE_PERF_MASK_BASE_IDX 1 +#define regSQ_THREAD_TRACE_CTRL 0x2335 +#define regSQ_THREAD_TRACE_CTRL_BASE_IDX 1 +#define regSQ_THREAD_TRACE_MODE 0x2336 +#define regSQ_THREAD_TRACE_MODE_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BASE2 0x2337 +#define regSQ_THREAD_TRACE_BASE2_BASE_IDX 1 +#define regSQ_THREAD_TRACE_TOKEN_MASK2 0x2338 +#define regSQ_THREAD_TRACE_TOKEN_MASK2_BASE_IDX 1 +#define regSQ_THREAD_TRACE_WPTR 0x2339 +#define regSQ_THREAD_TRACE_WPTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_STATUS 0x233a +#define regSQ_THREAD_TRACE_STATUS_BASE_IDX 1 +#define regSQ_THREAD_TRACE_HIWATER 0x233b +#define regSQ_THREAD_TRACE_HIWATER_BASE_IDX 1 +#define regSQ_THREAD_TRACE_CNTR 0x233c +#define regSQ_THREAD_TRACE_CNTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_0 0x2340 +#define regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_1 0x2341 +#define regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_2 0x2342 +#define regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_3 0x2343 +#define regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX 1 +#define regSQC_CACHES 0x2348 +#define regSQC_CACHES_BASE_IDX 1 +#define regSQC_WRITEBACK 0x2349 +#define regSQC_WRITEBACK_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT0_LOW 0x23c0 +#define regDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT0_HI 0x23c1 +#define regDB_OCCLUSION_COUNT0_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT1_LOW 0x23c2 +#define regDB_OCCLUSION_COUNT1_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT1_HI 0x23c3 +#define regDB_OCCLUSION_COUNT1_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT2_LOW 0x23c4 +#define regDB_OCCLUSION_COUNT2_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT2_HI 0x23c5 +#define regDB_OCCLUSION_COUNT2_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT3_LOW 0x23c6 +#define regDB_OCCLUSION_COUNT3_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT3_HI 0x23c7 +#define regDB_OCCLUSION_COUNT3_HI_BASE_IDX 1 +#define regDB_ZPASS_COUNT_LOW 0x23fe +#define regDB_ZPASS_COUNT_LOW_BASE_IDX 1 +#define regDB_ZPASS_COUNT_HI 0x23ff +#define regDB_ZPASS_COUNT_HI_BASE_IDX 1 +#define regGDS_RD_ADDR 0x2400 +#define regGDS_RD_ADDR_BASE_IDX 1 +#define regGDS_RD_DATA 0x2401 +#define regGDS_RD_DATA_BASE_IDX 1 +#define regGDS_RD_BURST_ADDR 0x2402 +#define regGDS_RD_BURST_ADDR_BASE_IDX 1 +#define regGDS_RD_BURST_COUNT 0x2403 +#define regGDS_RD_BURST_COUNT_BASE_IDX 1 +#define regGDS_RD_BURST_DATA 0x2404 +#define regGDS_RD_BURST_DATA_BASE_IDX 1 +#define regGDS_WR_ADDR 0x2405 +#define regGDS_WR_ADDR_BASE_IDX 1 +#define regGDS_WR_DATA 0x2406 +#define regGDS_WR_DATA_BASE_IDX 1 +#define regGDS_WR_BURST_ADDR 0x2407 +#define regGDS_WR_BURST_ADDR_BASE_IDX 1 +#define regGDS_WR_BURST_DATA 0x2408 +#define regGDS_WR_BURST_DATA_BASE_IDX 1 +#define regGDS_WRITE_COMPLETE 0x2409 +#define regGDS_WRITE_COMPLETE_BASE_IDX 1 +#define regGDS_ATOM_CNTL 0x240a +#define regGDS_ATOM_CNTL_BASE_IDX 1 +#define regGDS_ATOM_COMPLETE 0x240b +#define regGDS_ATOM_COMPLETE_BASE_IDX 1 +#define regGDS_ATOM_BASE 0x240c +#define regGDS_ATOM_BASE_BASE_IDX 1 +#define regGDS_ATOM_SIZE 0x240d +#define regGDS_ATOM_SIZE_BASE_IDX 1 +#define regGDS_ATOM_OFFSET0 0x240e +#define regGDS_ATOM_OFFSET0_BASE_IDX 1 +#define regGDS_ATOM_OFFSET1 0x240f +#define regGDS_ATOM_OFFSET1_BASE_IDX 1 +#define regGDS_ATOM_DST 0x2410 +#define regGDS_ATOM_DST_BASE_IDX 1 +#define regGDS_ATOM_OP 0x2411 +#define regGDS_ATOM_OP_BASE_IDX 1 +#define regGDS_ATOM_SRC0 0x2412 +#define regGDS_ATOM_SRC0_BASE_IDX 1 +#define regGDS_ATOM_SRC0_U 0x2413 +#define regGDS_ATOM_SRC0_U_BASE_IDX 1 +#define regGDS_ATOM_SRC1 0x2414 +#define regGDS_ATOM_SRC1_BASE_IDX 1 +#define regGDS_ATOM_SRC1_U 0x2415 +#define regGDS_ATOM_SRC1_U_BASE_IDX 1 +#define regGDS_ATOM_READ0 0x2416 +#define regGDS_ATOM_READ0_BASE_IDX 1 +#define regGDS_ATOM_READ0_U 0x2417 +#define regGDS_ATOM_READ0_U_BASE_IDX 1 +#define regGDS_ATOM_READ1 0x2418 +#define regGDS_ATOM_READ1_BASE_IDX 1 +#define regGDS_ATOM_READ1_U 0x2419 +#define regGDS_ATOM_READ1_U_BASE_IDX 1 +#define regGDS_GWS_RESOURCE_CNTL 0x241a +#define regGDS_GWS_RESOURCE_CNTL_BASE_IDX 1 +#define regGDS_GWS_RESOURCE 0x241b +#define regGDS_GWS_RESOURCE_BASE_IDX 1 +#define regGDS_GWS_RESOURCE_CNT 0x241c +#define regGDS_GWS_RESOURCE_CNT_BASE_IDX 1 +#define regGDS_OA_CNTL 0x241d +#define regGDS_OA_CNTL_BASE_IDX 1 +#define regGDS_OA_COUNTER 0x241e +#define regGDS_OA_COUNTER_BASE_IDX 1 +#define regGDS_OA_ADDRESS 0x241f +#define regGDS_OA_ADDRESS_BASE_IDX 1 +#define regGDS_OA_INCDEC 0x2420 +#define regGDS_OA_INCDEC_BASE_IDX 1 +#define regGDS_OA_RING_SIZE 0x2421 +#define regGDS_OA_RING_SIZE_BASE_IDX 1 +#define regSPI_CONFIG_CNTL 0x2440 +#define regSPI_CONFIG_CNTL_BASE_IDX 1 +#define regSPI_CONFIG_CNTL_1 0x2441 +#define regSPI_CONFIG_CNTL_1_BASE_IDX 1 +#define regSPI_CONFIG_CNTL_2 0x2442 +#define regSPI_CONFIG_CNTL_2_BASE_IDX 1 +#define regSPI_WAVE_LIMIT_CNTL 0x2443 +#define regSPI_WAVE_LIMIT_CNTL_BASE_IDX 1 + +// addressBlock: xcd0_gc_gccanedec +// base address: 0x33d00 +#define regGC_CANE_ERR_STATUS 0x2f4d +#define regGC_CANE_ERR_STATUS_BASE_IDX 1 +#define regGC_CANE_UE_ERR_STATUS_LO 0x2f4e +#define regGC_CANE_UE_ERR_STATUS_LO_BASE_IDX 1 +#define regGC_CANE_UE_ERR_STATUS_HI 0x2f4f +#define regGC_CANE_UE_ERR_STATUS_HI_BASE_IDX 1 +#define regGC_CANE_CE_ERR_STATUS_LO 0x2f50 +#define regGC_CANE_CE_ERR_STATUS_LO_BASE_IDX 1 +#define regGC_CANE_CE_ERR_STATUS_HI 0x2f51 +#define regGC_CANE_CE_ERR_STATUS_HI_BASE_IDX 1 + +// addressBlock: xcd0_gc_perfddec +// base address: 0x34000 +#define regCPG_PERFCOUNTER1_LO 0x3000 +#define regCPG_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCPG_PERFCOUNTER1_HI 0x3001 +#define regCPG_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_LO 0x3002 +#define regCPG_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_HI 0x3003 +#define regCPG_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCPC_PERFCOUNTER1_LO 0x3004 +#define regCPC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCPC_PERFCOUNTER1_HI 0x3005 +#define regCPC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_LO 0x3006 +#define regCPC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_HI 0x3007 +#define regCPC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCPF_PERFCOUNTER1_LO 0x3008 +#define regCPF_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCPF_PERFCOUNTER1_HI 0x3009 +#define regCPF_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_LO 0x300a +#define regCPF_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_HI 0x300b +#define regCPF_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCPF_LATENCY_STATS_DATA 0x300c +#define regCPF_LATENCY_STATS_DATA_BASE_IDX 1 +#define regCPG_LATENCY_STATS_DATA 0x300d +#define regCPG_LATENCY_STATS_DATA_BASE_IDX 1 +#define regCPC_LATENCY_STATS_DATA 0x300e +#define regCPC_LATENCY_STATS_DATA_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_LO 0x3040 +#define regGRBM_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_HI 0x3041 +#define regGRBM_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_LO 0x3043 +#define regGRBM_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_HI 0x3044 +#define regGRBM_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGRBM_SE0_PERFCOUNTER_LO 0x3045 +#define regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE0_PERFCOUNTER_HI 0x3046 +#define regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX 1 +#define regGRBM_SE1_PERFCOUNTER_LO 0x3047 +#define regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE1_PERFCOUNTER_HI 0x3048 +#define regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX 1 +#define regGRBM_SE2_PERFCOUNTER_LO 0x3049 +#define regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE2_PERFCOUNTER_HI 0x304a +#define regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX 1 +#define regGRBM_SE3_PERFCOUNTER_LO 0x304b +#define regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX 1 +#define regGRBM_SE3_PERFCOUNTER_HI 0x304c +#define regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX 1 +#define regWD_PERFCOUNTER0_LO 0x3080 +#define regWD_PERFCOUNTER0_LO_BASE_IDX 1 +#define regWD_PERFCOUNTER0_HI 0x3081 +#define regWD_PERFCOUNTER0_HI_BASE_IDX 1 +#define regWD_PERFCOUNTER1_LO 0x3082 +#define regWD_PERFCOUNTER1_LO_BASE_IDX 1 +#define regWD_PERFCOUNTER1_HI 0x3083 +#define regWD_PERFCOUNTER1_HI_BASE_IDX 1 +#define regWD_PERFCOUNTER2_LO 0x3084 +#define regWD_PERFCOUNTER2_LO_BASE_IDX 1 +#define regWD_PERFCOUNTER2_HI 0x3085 +#define regWD_PERFCOUNTER2_HI_BASE_IDX 1 +#define regWD_PERFCOUNTER3_LO 0x3086 +#define regWD_PERFCOUNTER3_LO_BASE_IDX 1 +#define regWD_PERFCOUNTER3_HI 0x3087 +#define regWD_PERFCOUNTER3_HI_BASE_IDX 1 +#define regIA_PERFCOUNTER0_LO 0x3088 +#define regIA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regIA_PERFCOUNTER0_HI 0x3089 +#define regIA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regIA_PERFCOUNTER1_LO 0x308a +#define regIA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regIA_PERFCOUNTER1_HI 0x308b +#define regIA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regIA_PERFCOUNTER2_LO 0x308c +#define regIA_PERFCOUNTER2_LO_BASE_IDX 1 +#define regIA_PERFCOUNTER2_HI 0x308d +#define regIA_PERFCOUNTER2_HI_BASE_IDX 1 +#define regIA_PERFCOUNTER3_LO 0x308e +#define regIA_PERFCOUNTER3_LO_BASE_IDX 1 +#define regIA_PERFCOUNTER3_HI 0x308f +#define regIA_PERFCOUNTER3_HI_BASE_IDX 1 +#define regVGT_PERFCOUNTER0_LO 0x3090 +#define regVGT_PERFCOUNTER0_LO_BASE_IDX 1 +#define regVGT_PERFCOUNTER0_HI 0x3091 +#define regVGT_PERFCOUNTER0_HI_BASE_IDX 1 +#define regVGT_PERFCOUNTER1_LO 0x3092 +#define regVGT_PERFCOUNTER1_LO_BASE_IDX 1 +#define regVGT_PERFCOUNTER1_HI 0x3093 +#define regVGT_PERFCOUNTER1_HI_BASE_IDX 1 +#define regVGT_PERFCOUNTER2_LO 0x3094 +#define regVGT_PERFCOUNTER2_LO_BASE_IDX 1 +#define regVGT_PERFCOUNTER2_HI 0x3095 +#define regVGT_PERFCOUNTER2_HI_BASE_IDX 1 +#define regVGT_PERFCOUNTER3_LO 0x3096 +#define regVGT_PERFCOUNTER3_LO_BASE_IDX 1 +#define regVGT_PERFCOUNTER3_HI 0x3097 +#define regVGT_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_LO 0x3100 +#define regPA_SU_PERFCOUNTER0_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_HI 0x3101 +#define regPA_SU_PERFCOUNTER0_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_LO 0x3102 +#define regPA_SU_PERFCOUNTER1_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_HI 0x3103 +#define regPA_SU_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_LO 0x3104 +#define regPA_SU_PERFCOUNTER2_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_HI 0x3105 +#define regPA_SU_PERFCOUNTER2_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_LO 0x3106 +#define regPA_SU_PERFCOUNTER3_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_HI 0x3107 +#define regPA_SU_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_LO 0x3140 +#define regPA_SC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_HI 0x3141 +#define regPA_SC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER1_LO 0x3142 +#define regPA_SC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER1_HI 0x3143 +#define regPA_SC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER2_LO 0x3144 +#define regPA_SC_PERFCOUNTER2_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER2_HI 0x3145 +#define regPA_SC_PERFCOUNTER2_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER3_LO 0x3146 +#define regPA_SC_PERFCOUNTER3_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER3_HI 0x3147 +#define regPA_SC_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER4_LO 0x3148 +#define regPA_SC_PERFCOUNTER4_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER4_HI 0x3149 +#define regPA_SC_PERFCOUNTER4_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER5_LO 0x314a +#define regPA_SC_PERFCOUNTER5_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER5_HI 0x314b +#define regPA_SC_PERFCOUNTER5_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER6_LO 0x314c +#define regPA_SC_PERFCOUNTER6_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER6_HI 0x314d +#define regPA_SC_PERFCOUNTER6_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER7_LO 0x314e +#define regPA_SC_PERFCOUNTER7_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER7_HI 0x314f +#define regPA_SC_PERFCOUNTER7_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_HI 0x3180 +#define regSPI_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_LO 0x3181 +#define regSPI_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_HI 0x3182 +#define regSPI_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_LO 0x3183 +#define regSPI_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_HI 0x3184 +#define regSPI_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_LO 0x3185 +#define regSPI_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_HI 0x3186 +#define regSPI_PERFCOUNTER3_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_LO 0x3187 +#define regSPI_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER4_HI 0x3188 +#define regSPI_PERFCOUNTER4_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER4_LO 0x3189 +#define regSPI_PERFCOUNTER4_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER5_HI 0x318a +#define regSPI_PERFCOUNTER5_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER5_LO 0x318b +#define regSPI_PERFCOUNTER5_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER0_LO 0x31c0 +#define regSQ_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER0_HI 0x31c1 +#define regSQ_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER1_LO 0x31c2 +#define regSQ_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER1_HI 0x31c3 +#define regSQ_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER2_LO 0x31c4 +#define regSQ_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER2_HI 0x31c5 +#define regSQ_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER3_LO 0x31c6 +#define regSQ_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER3_HI 0x31c7 +#define regSQ_PERFCOUNTER3_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER4_LO 0x31c8 +#define regSQ_PERFCOUNTER4_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER4_HI 0x31c9 +#define regSQ_PERFCOUNTER4_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER5_LO 0x31ca +#define regSQ_PERFCOUNTER5_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER5_HI 0x31cb +#define regSQ_PERFCOUNTER5_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER6_LO 0x31cc +#define regSQ_PERFCOUNTER6_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER6_HI 0x31cd +#define regSQ_PERFCOUNTER6_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER7_LO 0x31ce +#define regSQ_PERFCOUNTER7_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER7_HI 0x31cf +#define regSQ_PERFCOUNTER7_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER8_LO 0x31d0 +#define regSQ_PERFCOUNTER8_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER8_HI 0x31d1 +#define regSQ_PERFCOUNTER8_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER9_LO 0x31d2 +#define regSQ_PERFCOUNTER9_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER9_HI 0x31d3 +#define regSQ_PERFCOUNTER9_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER10_LO 0x31d4 +#define regSQ_PERFCOUNTER10_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER10_HI 0x31d5 +#define regSQ_PERFCOUNTER10_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER11_LO 0x31d6 +#define regSQ_PERFCOUNTER11_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER11_HI 0x31d7 +#define regSQ_PERFCOUNTER11_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER12_LO 0x31d8 +#define regSQ_PERFCOUNTER12_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER12_HI 0x31d9 +#define regSQ_PERFCOUNTER12_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER13_LO 0x31da +#define regSQ_PERFCOUNTER13_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER13_HI 0x31db +#define regSQ_PERFCOUNTER13_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER14_LO 0x31dc +#define regSQ_PERFCOUNTER14_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER14_HI 0x31dd +#define regSQ_PERFCOUNTER14_HI_BASE_IDX 1 +#define regSQ_PERFCOUNTER15_LO 0x31de +#define regSQ_PERFCOUNTER15_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER15_HI 0x31df +#define regSQ_PERFCOUNTER15_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER0_LO 0x3240 +#define regSX_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER0_HI 0x3241 +#define regSX_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER1_LO 0x3242 +#define regSX_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER1_HI 0x3243 +#define regSX_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER2_LO 0x3244 +#define regSX_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER2_HI 0x3245 +#define regSX_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER3_LO 0x3246 +#define regSX_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER3_HI 0x3247 +#define regSX_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGDS_PERFCOUNTER0_LO 0x3280 +#define regGDS_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGDS_PERFCOUNTER0_HI 0x3281 +#define regGDS_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGDS_PERFCOUNTER1_LO 0x3282 +#define regGDS_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGDS_PERFCOUNTER1_HI 0x3283 +#define regGDS_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGDS_PERFCOUNTER2_LO 0x3284 +#define regGDS_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGDS_PERFCOUNTER2_HI 0x3285 +#define regGDS_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGDS_PERFCOUNTER3_LO 0x3286 +#define regGDS_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGDS_PERFCOUNTER3_HI 0x3287 +#define regGDS_PERFCOUNTER3_HI_BASE_IDX 1 +#define regTA_PERFCOUNTER0_LO 0x32c0 +#define regTA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTA_PERFCOUNTER0_HI 0x32c1 +#define regTA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTA_PERFCOUNTER1_LO 0x32c2 +#define regTA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTA_PERFCOUNTER1_HI 0x32c3 +#define regTA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTD_PERFCOUNTER0_LO 0x3300 +#define regTD_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTD_PERFCOUNTER0_HI 0x3301 +#define regTD_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTD_PERFCOUNTER1_LO 0x3302 +#define regTD_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTD_PERFCOUNTER1_HI 0x3303 +#define regTD_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_LO 0x3340 +#define regTCP_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_HI 0x3341 +#define regTCP_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_LO 0x3342 +#define regTCP_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_HI 0x3343 +#define regTCP_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER2_LO 0x3344 +#define regTCP_PERFCOUNTER2_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER2_HI 0x3345 +#define regTCP_PERFCOUNTER2_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER3_LO 0x3346 +#define regTCP_PERFCOUNTER3_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER3_HI 0x3347 +#define regTCP_PERFCOUNTER3_HI_BASE_IDX 1 +#define regTCC_PERFCOUNTER0_LO 0x3380 +#define regTCC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTCC_PERFCOUNTER0_HI 0x3381 +#define regTCC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTCC_PERFCOUNTER1_LO 0x3382 +#define regTCC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTCC_PERFCOUNTER1_HI 0x3383 +#define regTCC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTCC_PERFCOUNTER2_LO 0x3384 +#define regTCC_PERFCOUNTER2_LO_BASE_IDX 1 +#define regTCC_PERFCOUNTER2_HI 0x3385 +#define regTCC_PERFCOUNTER2_HI_BASE_IDX 1 +#define regTCC_PERFCOUNTER3_LO 0x3386 +#define regTCC_PERFCOUNTER3_LO_BASE_IDX 1 +#define regTCC_PERFCOUNTER3_HI 0x3387 +#define regTCC_PERFCOUNTER3_HI_BASE_IDX 1 +#define regTCA_PERFCOUNTER0_LO 0x3390 +#define regTCA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTCA_PERFCOUNTER0_HI 0x3391 +#define regTCA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTCA_PERFCOUNTER1_LO 0x3392 +#define regTCA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTCA_PERFCOUNTER1_HI 0x3393 +#define regTCA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTCA_PERFCOUNTER2_LO 0x3394 +#define regTCA_PERFCOUNTER2_LO_BASE_IDX 1 +#define regTCA_PERFCOUNTER2_HI 0x3395 +#define regTCA_PERFCOUNTER2_HI_BASE_IDX 1 +#define regTCA_PERFCOUNTER3_LO 0x3396 +#define regTCA_PERFCOUNTER3_LO_BASE_IDX 1 +#define regTCA_PERFCOUNTER3_HI 0x3397 +#define regTCA_PERFCOUNTER3_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER0_LO 0x3406 +#define regCB_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER0_HI 0x3407 +#define regCB_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER1_LO 0x3408 +#define regCB_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER1_HI 0x3409 +#define regCB_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER2_LO 0x340a +#define regCB_PERFCOUNTER2_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER2_HI 0x340b +#define regCB_PERFCOUNTER2_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER3_LO 0x340c +#define regCB_PERFCOUNTER3_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER3_HI 0x340d +#define regCB_PERFCOUNTER3_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER0_LO 0x3440 +#define regDB_PERFCOUNTER0_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER0_HI 0x3441 +#define regDB_PERFCOUNTER0_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER1_LO 0x3442 +#define regDB_PERFCOUNTER1_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER1_HI 0x3443 +#define regDB_PERFCOUNTER1_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER2_LO 0x3444 +#define regDB_PERFCOUNTER2_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER2_HI 0x3445 +#define regDB_PERFCOUNTER2_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER3_LO 0x3446 +#define regDB_PERFCOUNTER3_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER3_HI 0x3447 +#define regDB_PERFCOUNTER3_HI_BASE_IDX 1 +#define regRLC_PERFCOUNTER0_LO 0x3480 +#define regRLC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regRLC_PERFCOUNTER0_HI 0x3481 +#define regRLC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regRLC_PERFCOUNTER1_LO 0x3482 +#define regRLC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regRLC_PERFCOUNTER1_HI 0x3483 +#define regRLC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_LO 0x34c0 +#define regRMI_PERFCOUNTER0_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_HI 0x34c1 +#define regRMI_PERFCOUNTER0_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER1_LO 0x34c2 +#define regRMI_PERFCOUNTER1_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER1_HI 0x34c3 +#define regRMI_PERFCOUNTER1_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_LO 0x34c4 +#define regRMI_PERFCOUNTER2_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_HI 0x34c5 +#define regRMI_PERFCOUNTER2_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER3_LO 0x34c6 +#define regRMI_PERFCOUNTER3_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER3_HI 0x34c7 +#define regRMI_PERFCOUNTER3_HI_BASE_IDX 1 + + +// addressBlock: xcd0_gc_utcl2_atcl2pfcntrdec +// base address: 0x35400 +#define regATC_L2_PERFCOUNTER_LO 0x3500 +#define regATC_L2_PERFCOUNTER_LO_BASE_IDX 1 +#define regATC_L2_PERFCOUNTER_HI 0x3501 +#define regATC_L2_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: xcd0_gc_utcl2_vml2prdec +// base address: 0x35408 +#define regMC_VM_L2_PERFCOUNTER_LO 0x3502 +#define regMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 +#define regMC_VM_L2_PERFCOUNTER_HI 0x3503 +#define regMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: xcd0_gc_utcl2_l2tlbprdec +// base address: 0x35448 +#define regL2TLB_PERFCOUNTER_LO 0x3512 +#define regL2TLB_PERFCOUNTER_LO_BASE_IDX 1 +#define regL2TLB_PERFCOUNTER_HI 0x3513 +#define regL2TLB_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: xcd0_gc_perfsdec +// base address: 0x36000 +#define regCPG_PERFCOUNTER1_SELECT 0x3800 +#define regCPG_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_SELECT1 0x3801 +#define regCPG_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_SELECT 0x3802 +#define regCPG_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCPC_PERFCOUNTER1_SELECT 0x3803 +#define regCPC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_SELECT1 0x3804 +#define regCPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCPF_PERFCOUNTER1_SELECT 0x3805 +#define regCPF_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_SELECT1 0x3806 +#define regCPF_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_SELECT 0x3807 +#define regCPF_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCP_PERFMON_CNTL 0x3808 +#define regCP_PERFMON_CNTL_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_SELECT 0x3809 +#define regCPC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCPF_TC_PERF_COUNTER_WINDOW_SELECT 0x380a +#define regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 +#define regCPG_TC_PERF_COUNTER_WINDOW_SELECT 0x380b +#define regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 +#define regCPF_LATENCY_STATS_SELECT 0x380c +#define regCPF_LATENCY_STATS_SELECT_BASE_IDX 1 +#define regCPG_LATENCY_STATS_SELECT 0x380d +#define regCPG_LATENCY_STATS_SELECT_BASE_IDX 1 +#define regCPC_LATENCY_STATS_SELECT 0x380e +#define regCPC_LATENCY_STATS_SELECT_BASE_IDX 1 +#define regCP_DRAW_OBJECT 0x3810 +#define regCP_DRAW_OBJECT_BASE_IDX 1 +#define regCP_DRAW_OBJECT_COUNTER 0x3811 +#define regCP_DRAW_OBJECT_COUNTER_BASE_IDX 1 +#define regCP_DRAW_WINDOW_MASK_HI 0x3812 +#define regCP_DRAW_WINDOW_MASK_HI_BASE_IDX 1 +#define regCP_DRAW_WINDOW_HI 0x3813 +#define regCP_DRAW_WINDOW_HI_BASE_IDX 1 +#define regCP_DRAW_WINDOW_LO 0x3814 +#define regCP_DRAW_WINDOW_LO_BASE_IDX 1 +#define regCP_DRAW_WINDOW_CNTL 0x3815 +#define regCP_DRAW_WINDOW_CNTL_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_SELECT 0x3840 +#define regGRBM_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_SELECT 0x3841 +#define regGRBM_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGRBM_SE0_PERFCOUNTER_SELECT 0x3842 +#define regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regGRBM_SE1_PERFCOUNTER_SELECT 0x3843 +#define regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regGRBM_SE2_PERFCOUNTER_SELECT 0x3844 +#define regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regGRBM_SE3_PERFCOUNTER_SELECT 0x3845 +#define regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX 1 +#define regWD_PERFCOUNTER0_SELECT 0x3880 +#define regWD_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regWD_PERFCOUNTER1_SELECT 0x3881 +#define regWD_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regWD_PERFCOUNTER2_SELECT 0x3882 +#define regWD_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regWD_PERFCOUNTER3_SELECT 0x3883 +#define regWD_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regIA_PERFCOUNTER0_SELECT 0x3884 +#define regIA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regIA_PERFCOUNTER1_SELECT 0x3885 +#define regIA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regIA_PERFCOUNTER2_SELECT 0x3886 +#define regIA_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regIA_PERFCOUNTER3_SELECT 0x3887 +#define regIA_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regIA_PERFCOUNTER0_SELECT1 0x3888 +#define regIA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regVGT_PERFCOUNTER0_SELECT 0x388c +#define regVGT_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regVGT_PERFCOUNTER1_SELECT 0x388d +#define regVGT_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regVGT_PERFCOUNTER2_SELECT 0x388e +#define regVGT_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regVGT_PERFCOUNTER3_SELECT 0x388f +#define regVGT_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regVGT_PERFCOUNTER0_SELECT1 0x3890 +#define regVGT_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regVGT_PERFCOUNTER1_SELECT1 0x3891 +#define regVGT_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regVGT_PERFCOUNTER_SEID_MASK 0x3894 +#define regVGT_PERFCOUNTER_SEID_MASK_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_SELECT 0x3900 +#define regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_SELECT1 0x3901 +#define regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_SELECT 0x3902 +#define regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_SELECT1 0x3903 +#define regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_SELECT 0x3904 +#define regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_SELECT 0x3905 +#define regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_SELECT 0x3940 +#define regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_SELECT1 0x3941 +#define regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER1_SELECT 0x3942 +#define regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER2_SELECT 0x3943 +#define regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER3_SELECT 0x3944 +#define regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER4_SELECT 0x3945 +#define regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER5_SELECT 0x3946 +#define regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER6_SELECT 0x3947 +#define regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER7_SELECT 0x3948 +#define regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_SELECT 0x3980 +#define regSPI_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_SELECT 0x3981 +#define regSPI_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_SELECT 0x3982 +#define regSPI_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_SELECT 0x3983 +#define regSPI_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_SELECT1 0x3984 +#define regSPI_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_SELECT1 0x3985 +#define regSPI_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_SELECT1 0x3986 +#define regSPI_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_SELECT1 0x3987 +#define regSPI_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER4_SELECT 0x3988 +#define regSPI_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER5_SELECT 0x3989 +#define regSPI_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER_BINS 0x398a +#define regSPI_PERFCOUNTER_BINS_BASE_IDX 1 +#define regSQ_PERFCOUNTER0_SELECT 0x39c0 +#define regSQ_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER1_SELECT 0x39c1 +#define regSQ_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER2_SELECT 0x39c2 +#define regSQ_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER3_SELECT 0x39c3 +#define regSQ_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER4_SELECT 0x39c4 +#define regSQ_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER5_SELECT 0x39c5 +#define regSQ_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER6_SELECT 0x39c6 +#define regSQ_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER7_SELECT 0x39c7 +#define regSQ_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER8_SELECT 0x39c8 +#define regSQ_PERFCOUNTER8_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER9_SELECT 0x39c9 +#define regSQ_PERFCOUNTER9_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER10_SELECT 0x39ca +#define regSQ_PERFCOUNTER10_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER11_SELECT 0x39cb +#define regSQ_PERFCOUNTER11_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER12_SELECT 0x39cc +#define regSQ_PERFCOUNTER12_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER13_SELECT 0x39cd +#define regSQ_PERFCOUNTER13_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER14_SELECT 0x39ce +#define regSQ_PERFCOUNTER14_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER15_SELECT 0x39cf +#define regSQ_PERFCOUNTER15_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER_CTRL 0x39e0 +#define regSQ_PERFCOUNTER_CTRL_BASE_IDX 1 +#define regSQ_PERFCOUNTER_MASK 0x39e1 +#define regSQ_PERFCOUNTER_MASK_BASE_IDX 1 +#define regSQ_PERFCOUNTER_CTRL2 0x39e2 +#define regSQ_PERFCOUNTER_CTRL2_BASE_IDX 1 +#define regSX_PERFCOUNTER0_SELECT 0x3a40 +#define regSX_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER1_SELECT 0x3a41 +#define regSX_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER2_SELECT 0x3a42 +#define regSX_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER3_SELECT 0x3a43 +#define regSX_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER0_SELECT1 0x3a44 +#define regSX_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regSX_PERFCOUNTER1_SELECT1 0x3a45 +#define regSX_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGDS_PERFCOUNTER0_SELECT 0x3a80 +#define regGDS_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGDS_PERFCOUNTER1_SELECT 0x3a81 +#define regGDS_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGDS_PERFCOUNTER2_SELECT 0x3a82 +#define regGDS_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGDS_PERFCOUNTER3_SELECT 0x3a83 +#define regGDS_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGDS_PERFCOUNTER0_SELECT1 0x3a84 +#define regGDS_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTA_PERFCOUNTER0_SELECT 0x3ac0 +#define regTA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTA_PERFCOUNTER0_SELECT1 0x3ac1 +#define regTA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTA_PERFCOUNTER1_SELECT 0x3ac2 +#define regTA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTD_PERFCOUNTER0_SELECT 0x3b00 +#define regTD_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTD_PERFCOUNTER0_SELECT1 0x3b01 +#define regTD_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTD_PERFCOUNTER1_SELECT 0x3b02 +#define regTD_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_SELECT 0x3b40 +#define regTCP_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_SELECT1 0x3b41 +#define regTCP_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_SELECT 0x3b42 +#define regTCP_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_SELECT1 0x3b43 +#define regTCP_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regTCP_PERFCOUNTER2_SELECT 0x3b44 +#define regTCP_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER3_SELECT 0x3b45 +#define regTCP_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regTCC_PERFCOUNTER0_SELECT 0x3b80 +#define regTCC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTCC_PERFCOUNTER0_SELECT1 0x3b81 +#define regTCC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTCC_PERFCOUNTER1_SELECT 0x3b82 +#define regTCC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTCC_PERFCOUNTER1_SELECT1 0x3b83 +#define regTCC_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regTCC_PERFCOUNTER2_SELECT 0x3b84 +#define regTCC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regTCC_PERFCOUNTER3_SELECT 0x3b85 +#define regTCC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regTCA_PERFCOUNTER0_SELECT 0x3b90 +#define regTCA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTCA_PERFCOUNTER0_SELECT1 0x3b91 +#define regTCA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTCA_PERFCOUNTER1_SELECT 0x3b92 +#define regTCA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTCA_PERFCOUNTER1_SELECT1 0x3b93 +#define regTCA_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regTCA_PERFCOUNTER2_SELECT 0x3b94 +#define regTCA_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regTCA_PERFCOUNTER3_SELECT 0x3b95 +#define regTCA_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER_FILTER 0x3c00 +#define regCB_PERFCOUNTER_FILTER_BASE_IDX 1 +#define regCB_PERFCOUNTER0_SELECT 0x3c01 +#define regCB_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER0_SELECT1 0x3c02 +#define regCB_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCB_PERFCOUNTER1_SELECT 0x3c03 +#define regCB_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER2_SELECT 0x3c04 +#define regCB_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER3_SELECT 0x3c05 +#define regCB_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER0_SELECT 0x3c40 +#define regDB_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER0_SELECT1 0x3c41 +#define regDB_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regDB_PERFCOUNTER1_SELECT 0x3c42 +#define regDB_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER1_SELECT1 0x3c43 +#define regDB_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regDB_PERFCOUNTER2_SELECT 0x3c44 +#define regDB_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER3_SELECT 0x3c46 +#define regDB_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regRLC_SPM_PERFMON_CNTL 0x3c80 +#define regRLC_SPM_PERFMON_CNTL_BASE_IDX 1 +#define regRLC_SPM_PERFMON_RING_BASE_LO 0x3c81 +#define regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 1 +#define regRLC_SPM_PERFMON_RING_BASE_HI 0x3c82 +#define regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX 1 +#define regRLC_SPM_PERFMON_RING_SIZE 0x3c83 +#define regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX 1 +#define regRLC_SPM_PERFMON_SEGMENT_SIZE 0x3c84 +#define regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX 1 +#define regRLC_SPM_SE_MUXSEL_ADDR 0x3c85 +#define regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX 1 +#define regRLC_SPM_SE_MUXSEL_DATA 0x3c86 +#define regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 1 +#define regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0x3c87 +#define regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0x3c88 +#define regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0x3c89 +#define regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0x3c8a +#define regRLC_SPM_CB_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0x3c8b +#define regRLC_SPM_DB_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0x3c8c +#define regRLC_SPM_PA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0x3c8d +#define regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0x3c8e +#define regRLC_SPM_IA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0x3c90 +#define regRLC_SPM_SC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0x3c91 +#define regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0x3c92 +#define regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0x3c93 +#define regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0x3c94 +#define regRLC_SPM_TA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0x3c95 +#define regRLC_SPM_TD_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0x3c96 +#define regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0x3c97 +#define regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0x3c98 +#define regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0x3c9a +#define regRLC_SPM_SX_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_MUXSEL_ADDR 0x3c9b +#define regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_MUXSEL_DATA 0x3c9c +#define regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX 1 +#define regRLC_SPM_RING_RDPTR 0x3c9d +#define regRLC_SPM_RING_RDPTR_BASE_IDX 1 +#define regRLC_SPM_SEGMENT_THRESHOLD 0x3c9e +#define regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX 1 +#define regRLC_SPM_RMI_PERFMON_SAMPLE_DELAY 0x3ca3 +#define regRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_BASE_IDX 1 +#define regRLC_SPM_PERFMON_SAMPLE_DELAY_MAX 0x3ca4 +#define regRLC_SPM_PERFMON_SAMPLE_DELAY_MAX_BASE_IDX 1 +#define regRLC_PERFMON_CNTL 0x3cc0 +#define regRLC_PERFMON_CNTL_BASE_IDX 1 +#define regRLC_PERFCOUNTER0_SELECT 0x3cc1 +#define regRLC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regRLC_PERFCOUNTER1_SELECT 0x3cc2 +#define regRLC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_CNTL 0x3cc3 +#define regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_WR_ADDR 0x3cc4 +#define regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_WR_DATA 0x3cc5 +#define regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_RD_ADDR 0x3cc6 +#define regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_RD_DATA 0x3cc7 +#define regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_SELECT 0x3d00 +#define regRMI_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_SELECT1 0x3d01 +#define regRMI_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regRMI_PERFCOUNTER1_SELECT 0x3d02 +#define regRMI_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_SELECT 0x3d03 +#define regRMI_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_SELECT1 0x3d04 +#define regRMI_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regRMI_PERFCOUNTER3_SELECT 0x3d05 +#define regRMI_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regRMI_PERF_COUNTER_CNTL 0x3d06 +#define regRMI_PERF_COUNTER_CNTL_BASE_IDX 1 + + +// addressBlock: xcd0_gc_utcl2_atcl2pfcntldec +// base address: 0x37500 +#define regATC_L2_PERFCOUNTER0_CFG 0x3d40 +#define regATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regATC_L2_PERFCOUNTER1_CFG 0x3d41 +#define regATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regATC_L2_PERFCOUNTER_RSLT_CNTL 0x3d42 +#define regATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: xcd0_gc_utcl2_vml2pldec +// base address: 0x37518 +#define regMC_VM_L2_PERFCOUNTER0_CFG 0x3d46 +#define regMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regMC_VM_L2_PERFCOUNTER1_CFG 0x3d47 +#define regMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regMC_VM_L2_PERFCOUNTER2_CFG 0x3d48 +#define regMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regMC_VM_L2_PERFCOUNTER3_CFG 0x3d49 +#define regMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regMC_VM_L2_PERFCOUNTER4_CFG 0x3d4a +#define regMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 +#define regMC_VM_L2_PERFCOUNTER5_CFG 0x3d4b +#define regMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 +#define regMC_VM_L2_PERFCOUNTER6_CFG 0x3d4c +#define regMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 +#define regMC_VM_L2_PERFCOUNTER7_CFG 0x3d4d +#define regMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 +#define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3d56 +#define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: xcd0_gc_utcl2_l2tlbpldec +// base address: 0x37578 +#define regL2TLB_PERFCOUNTER0_CFG 0x3d5e +#define regL2TLB_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regL2TLB_PERFCOUNTER1_CFG 0x3d5f +#define regL2TLB_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regL2TLB_PERFCOUNTER2_CFG 0x3d60 +#define regL2TLB_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regL2TLB_PERFCOUNTER3_CFG 0x3d61 +#define regL2TLB_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regL2TLB_PERFCOUNTER_RSLT_CNTL 0x3d62 +#define regL2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: xcd0_gc_gdflldec +// base address: 0x3a000 +#define regGDFLL_EDC_HYSTERESIS_CNTL 0x481b +#define regGDFLL_EDC_HYSTERESIS_CNTL_BASE_IDX 1 +#define regGDFLL_EDC_HYSTERESIS_STAT 0x481c +#define regGDFLL_EDC_HYSTERESIS_STAT_BASE_IDX 1 + + +// addressBlock: xcd0_gc_rlcpdec +// base address: 0x3b000 +#define regRLC_CNTL 0x4c00 +#define regRLC_CNTL_BASE_IDX 1 +#define regRLC_CGCG_CGLS_CTRL_2 0x4c03 +#define regRLC_CGCG_CGLS_CTRL_2_BASE_IDX 1 +#define regRLC_STAT 0x4c04 +#define regRLC_STAT_BASE_IDX 1 +#define regRLC_SAFE_MODE 0x4c05 +#define regRLC_SAFE_MODE_BASE_IDX 1 +#define regRLC_MEM_SLP_CNTL 0x4c06 +#define regRLC_MEM_SLP_CNTL_BASE_IDX 1 +#define regSMU_RLC_RESPONSE 0x4c07 +#define regSMU_RLC_RESPONSE_BASE_IDX 1 +#define regRLC_RLCV_SAFE_MODE 0x4c08 +#define regRLC_RLCV_SAFE_MODE_BASE_IDX 1 +#define regRLC_SMU_SAFE_MODE 0x4c09 +#define regRLC_SMU_SAFE_MODE_BASE_IDX 1 +#define regRLC_RLCV_COMMAND 0x4c0a +#define regRLC_RLCV_COMMAND_BASE_IDX 1 +#define regRLC_REFCLOCK_TIMESTAMP_LSB 0x4c0c +#define regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX 1 +#define regRLC_REFCLOCK_TIMESTAMP_MSB 0x4c0d +#define regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_0 0x4c0e +#define regRLC_GPM_TIMER_INT_0_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_1 0x4c0f +#define regRLC_GPM_TIMER_INT_1_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_2 0x4c10 +#define regRLC_GPM_TIMER_INT_2_BASE_IDX 1 +#define regRLC_GPM_TIMER_CTRL 0x4c11 +#define regRLC_GPM_TIMER_CTRL_BASE_IDX 1 +#define regRLC_LB_CNTR_MAX 0x4c12 +#define regRLC_LB_CNTR_MAX_BASE_IDX 1 +#define regRLC_GPM_TIMER_STAT 0x4c13 +#define regRLC_GPM_TIMER_STAT_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_3 0x4c15 +#define regRLC_GPM_TIMER_INT_3_BASE_IDX 1 +#define regRLC_SERDES_WR_NONCU_MASTER_MASK_1 0x4c16 +#define regRLC_SERDES_WR_NONCU_MASTER_MASK_1_BASE_IDX 1 +#define regRLC_SERDES_NONCU_MASTER_BUSY_1 0x4c17 +#define regRLC_SERDES_NONCU_MASTER_BUSY_1_BASE_IDX 1 +#define regRLC_INT_STAT 0x4c18 +#define regRLC_INT_STAT_BASE_IDX 1 +#define regRLC_LB_CNTL 0x4c19 +#define regRLC_LB_CNTL_BASE_IDX 1 +#define regRLC_MGCG_CTRL 0x4c1a +#define regRLC_MGCG_CTRL_BASE_IDX 1 +#define regRLC_LB_CNTR_INIT 0x4c1b +#define regRLC_LB_CNTR_INIT_BASE_IDX 1 +#define regRLC_LOAD_BALANCE_CNTR 0x4c1c +#define regRLC_LOAD_BALANCE_CNTR_BASE_IDX 1 +#define regRLC_JUMP_TABLE_RESTORE 0x4c1e +#define regRLC_JUMP_TABLE_RESTORE_BASE_IDX 1 +#define regRLC_PG_DELAY_2 0x4c1f +#define regRLC_PG_DELAY_2_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_LSB 0x4c24 +#define regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_MSB 0x4c25 +#define regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX 1 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT 0x4c26 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX 1 +#define regRLC_UCODE_CNTL 0x4c27 +#define regRLC_UCODE_CNTL_BASE_IDX 1 +#define regRLC_GPM_THREAD_RESET 0x4c28 +#define regRLC_GPM_THREAD_RESET_BASE_IDX 1 +#define regRLC_GPM_CP_DMA_COMPLETE_T0 0x4c29 +#define regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX 1 +#define regRLC_GPM_CP_DMA_COMPLETE_T1 0x4c2a +#define regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX 1 +#define regRLC_FIREWALL_VIOLATION 0x4c2b +#define regRLC_FIREWALL_VIOLATION_BASE_IDX 1 +#define regRLC_CLK_COUNT_GFXCLK_LSB 0x4c30 +#define regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_GFXCLK_MSB 0x4c31 +#define regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_REFCLK_LSB 0x4c32 +#define regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_REFCLK_MSB 0x4c33 +#define regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_CTRL 0x4c34 +#define regRLC_CLK_COUNT_CTRL_BASE_IDX 1 +#define regRLC_CLK_COUNT_STAT 0x4c35 +#define regRLC_CLK_COUNT_STAT_BASE_IDX 1 +#define regRLC_GPM_STAT 0x4c40 +#define regRLC_GPM_STAT_BASE_IDX 1 +#define regRLC_GPU_CLOCK_32_RES_SEL 0x4c41 +#define regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1 +#define regRLC_GPU_CLOCK_32 0x4c42 +#define regRLC_GPU_CLOCK_32_BASE_IDX 1 +#define regRLC_PG_CNTL 0x4c43 +#define regRLC_PG_CNTL_BASE_IDX 1 +#define regRLC_GPM_THREAD_PRIORITY 0x4c44 +#define regRLC_GPM_THREAD_PRIORITY_BASE_IDX 1 +#define regRLC_GPM_THREAD_ENABLE 0x4c45 +#define regRLC_GPM_THREAD_ENABLE_BASE_IDX 1 +#define regRLC_CGTT_MGCG_OVERRIDE 0x4c48 +#define regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX 1 +#define regRLC_CGCG_CGLS_CTRL 0x4c49 +#define regRLC_CGCG_CGLS_CTRL_BASE_IDX 1 +#define regRLC_CGCG_RAMP_CTRL 0x4c4a +#define regRLC_CGCG_RAMP_CTRL_BASE_IDX 1 +#define regRLC_DYN_PG_STATUS 0x4c4b +#define regRLC_DYN_PG_STATUS_BASE_IDX 1 +#define regRLC_DYN_PG_REQUEST 0x4c4c +#define regRLC_DYN_PG_REQUEST_BASE_IDX 1 +#define regRLC_PG_DELAY 0x4c4d +#define regRLC_PG_DELAY_BASE_IDX 1 +#define regRLC_CU_STATUS 0x4c4e +#define regRLC_CU_STATUS_BASE_IDX 1 +#define regRLC_LB_INIT_CU_MASK 0x4c4f +#define regRLC_LB_INIT_CU_MASK_BASE_IDX 1 +#define regRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x4c50 +#define regRLC_LB_ALWAYS_ACTIVE_CU_MASK_BASE_IDX 1 +#define regRLC_LB_PARAMS 0x4c51 +#define regRLC_LB_PARAMS_BASE_IDX 1 +#define regRLC_THREAD1_DELAY 0x4c52 +#define regRLC_THREAD1_DELAY_BASE_IDX 1 +#define regRLC_PG_ALWAYS_ON_CU_MASK 0x4c53 +#define regRLC_PG_ALWAYS_ON_CU_MASK_BASE_IDX 1 +#define regRLC_MAX_PG_CU 0x4c54 +#define regRLC_MAX_PG_CU_BASE_IDX 1 +#define regRLC_AUTO_PG_CTRL 0x4c55 +#define regRLC_AUTO_PG_CTRL_BASE_IDX 1 +#define regRLC_SMU_GRBM_REG_SAVE_CTRL 0x4c56 +#define regRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX 1 +#define regRLC_SERDES_RD_PENDING 0x4c58 +#define regRLC_SERDES_RD_PENDING_BASE_IDX 1 +#define regRLC_SERDES_RD_MASTER_INDEX 0x4c59 +#define regRLC_SERDES_RD_MASTER_INDEX_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_0 0x4c5a +#define regRLC_SERDES_RD_DATA_0_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_1 0x4c5b +#define regRLC_SERDES_RD_DATA_1_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_2 0x4c5c +#define regRLC_SERDES_RD_DATA_2_BASE_IDX 1 +#define regRLC_SERDES_WR_CU_MASTER_MASK 0x4c5d +#define regRLC_SERDES_WR_CU_MASTER_MASK_BASE_IDX 1 +#define regRLC_SERDES_WR_NONCU_MASTER_MASK 0x4c5e +#define regRLC_SERDES_WR_NONCU_MASTER_MASK_BASE_IDX 1 +#define regRLC_SERDES_WR_CTRL 0x4c5f +#define regRLC_SERDES_WR_CTRL_BASE_IDX 1 +#define regRLC_SERDES_WR_DATA 0x4c60 +#define regRLC_SERDES_WR_DATA_BASE_IDX 1 +#define regRLC_SERDES_CU_MASTER_BUSY 0x4c61 +#define regRLC_SERDES_CU_MASTER_BUSY_BASE_IDX 1 +#define regRLC_SERDES_NONCU_MASTER_BUSY 0x4c62 +#define regRLC_SERDES_NONCU_MASTER_BUSY_BASE_IDX 1 +#define regRLC_GPM_GENERAL_0 0x4c63 +#define regRLC_GPM_GENERAL_0_BASE_IDX 1 +#define regRLC_GPM_GENERAL_1 0x4c64 +#define regRLC_GPM_GENERAL_1_BASE_IDX 1 +#define regRLC_GPM_GENERAL_2 0x4c65 +#define regRLC_GPM_GENERAL_2_BASE_IDX 1 +#define regRLC_GPM_GENERAL_3 0x4c66 +#define regRLC_GPM_GENERAL_3_BASE_IDX 1 +#define regRLC_GPM_GENERAL_4 0x4c67 +#define regRLC_GPM_GENERAL_4_BASE_IDX 1 +#define regRLC_GPM_GENERAL_5 0x4c68 +#define regRLC_GPM_GENERAL_5_BASE_IDX 1 +#define regRLC_GPM_GENERAL_6 0x4c69 +#define regRLC_GPM_GENERAL_6_BASE_IDX 1 +#define regRLC_GPM_GENERAL_7 0x4c6a +#define regRLC_GPM_GENERAL_7_BASE_IDX 1 +#define regRLC_GPM_SCRATCH_ADDR 0x4c6c +#define regRLC_GPM_SCRATCH_ADDR_BASE_IDX 1 +#define regRLC_GPM_SCRATCH_DATA 0x4c6d +#define regRLC_GPM_SCRATCH_DATA_BASE_IDX 1 +#define regRLC_STATIC_PG_STATUS 0x4c6e +#define regRLC_STATIC_PG_STATUS_BASE_IDX 1 +#define regRLC_SPM_MC_CNTL 0x4c71 +#define regRLC_SPM_MC_CNTL_BASE_IDX 1 +#define regRLC_SPM_INT_CNTL 0x4c72 +#define regRLC_SPM_INT_CNTL_BASE_IDX 1 +#define regRLC_SPM_INT_STATUS 0x4c73 +#define regRLC_SPM_INT_STATUS_BASE_IDX 1 +#define regRLC_SMU_MESSAGE 0x4c76 +#define regRLC_SMU_MESSAGE_BASE_IDX 1 +#define regRLC_GPM_LOG_SIZE 0x4c77 +#define regRLC_GPM_LOG_SIZE_BASE_IDX 1 +#define regRLC_PG_DELAY_3 0x4c78 +#define regRLC_PG_DELAY_3_BASE_IDX 1 +#define regRLC_GPR_REG1 0x4c79 +#define regRLC_GPR_REG1_BASE_IDX 1 +#define regRLC_GPR_REG2 0x4c7a +#define regRLC_GPR_REG2_BASE_IDX 1 +#define regRLC_GPM_LOG_CONT 0x4c7b +#define regRLC_GPM_LOG_CONT_BASE_IDX 1 +#define regRLC_GPM_INT_DISABLE_TH0 0x4c7c +#define regRLC_GPM_INT_DISABLE_TH0_BASE_IDX 1 +#define regRLC_GPM_INT_FORCE_TH0 0x4c7e +#define regRLC_GPM_INT_FORCE_TH0_BASE_IDX 1 +#define regRLC_GPM_INT_FORCE_TH1 0x4c7f +#define regRLC_GPM_INT_FORCE_TH1_BASE_IDX 1 +#define regRLC_SRM_CNTL 0x4c80 +#define regRLC_SRM_CNTL_BASE_IDX 1 +#define regRLC_SRM_ARAM_ADDR 0x4c83 +#define regRLC_SRM_ARAM_ADDR_BASE_IDX 1 +#define regRLC_SRM_ARAM_DATA 0x4c84 +#define regRLC_SRM_ARAM_DATA_BASE_IDX 1 +#define regRLC_SRM_DRAM_ADDR 0x4c85 +#define regRLC_SRM_DRAM_ADDR_BASE_IDX 1 +#define regRLC_SRM_DRAM_DATA 0x4c86 +#define regRLC_SRM_DRAM_DATA_BASE_IDX 1 +#define regRLC_SRM_GPM_COMMAND 0x4c87 +#define regRLC_SRM_GPM_COMMAND_BASE_IDX 1 +#define regRLC_SRM_GPM_COMMAND_STATUS 0x4c88 +#define regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX 1 +#define regRLC_SRM_RLCV_COMMAND 0x4c89 +#define regRLC_SRM_RLCV_COMMAND_BASE_IDX 1 +#define regRLC_SRM_RLCV_COMMAND_STATUS 0x4c8a +#define regRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b +#define regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_1 0x4c8c +#define regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_2 0x4c8d +#define regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_3 0x4c8e +#define regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_4 0x4c8f +#define regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_5 0x4c90 +#define regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_6 0x4c91 +#define regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_7 0x4c92 +#define regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_0 0x4c93 +#define regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_1 0x4c94 +#define regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_2 0x4c95 +#define regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_3 0x4c96 +#define regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_4 0x4c97 +#define regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_5 0x4c98 +#define regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_6 0x4c99 +#define regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_7 0x4c9a +#define regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX 1 +#define regRLC_SRM_STAT 0x4c9b +#define regRLC_SRM_STAT_BASE_IDX 1 +#define regRLC_SRM_GPM_ABORT 0x4c9c +#define regRLC_SRM_GPM_ABORT_BASE_IDX 1 +#define regRLC_CSIB_ADDR_LO 0x4ca2 +#define regRLC_CSIB_ADDR_LO_BASE_IDX 1 +#define regRLC_CSIB_ADDR_HI 0x4ca3 +#define regRLC_CSIB_ADDR_HI_BASE_IDX 1 +#define regRLC_CSIB_LENGTH 0x4ca4 +#define regRLC_CSIB_LENGTH_BASE_IDX 1 +#define regRLC_SMU_COMMAND 0x4ca9 +#define regRLC_SMU_COMMAND_BASE_IDX 1 +#define regRLC_CP_SCHEDULERS 0x4caa +#define regRLC_CP_SCHEDULERS_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_1 0x4cab +#define regRLC_SMU_ARGUMENT_1_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_2 0x4cac +#define regRLC_SMU_ARGUMENT_2_BASE_IDX 1 +#define regRLC_GPM_GENERAL_8 0x4cad +#define regRLC_GPM_GENERAL_8_BASE_IDX 1 +#define regRLC_GPM_GENERAL_9 0x4cae +#define regRLC_GPM_GENERAL_9_BASE_IDX 1 +#define regRLC_GPM_GENERAL_10 0x4caf +#define regRLC_GPM_GENERAL_10_BASE_IDX 1 +#define regRLC_GPM_GENERAL_11 0x4cb0 +#define regRLC_GPM_GENERAL_11_BASE_IDX 1 +#define regRLC_GPM_GENERAL_12 0x4cb1 +#define regRLC_GPM_GENERAL_12_BASE_IDX 1 +#define regRLC_GPM_UTCL1_CNTL_0 0x4cb2 +#define regRLC_GPM_UTCL1_CNTL_0_BASE_IDX 1 +#define regRLC_GPM_UTCL1_CNTL_1 0x4cb3 +#define regRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1 +#define regRLC_GPM_UTCL1_CNTL_2 0x4cb4 +#define regRLC_GPM_UTCL1_CNTL_2_BASE_IDX 1 +#define regRLC_SPM_UTCL1_CNTL 0x4cb5 +#define regRLC_SPM_UTCL1_CNTL_BASE_IDX 1 +#define regRLC_UTCL1_STATUS_2 0x4cb6 +#define regRLC_UTCL1_STATUS_2_BASE_IDX 1 +#define regRLC_LB_THR_CONFIG_2 0x4cb8 +#define regRLC_LB_THR_CONFIG_2_BASE_IDX 1 +#define regRLC_LB_THR_CONFIG_3 0x4cb9 +#define regRLC_LB_THR_CONFIG_3_BASE_IDX 1 +#define regRLC_LB_THR_CONFIG_4 0x4cba +#define regRLC_LB_THR_CONFIG_4_BASE_IDX 1 +#define regRLC_SPM_UTCL1_ERROR_1 0x4cbc +#define regRLC_SPM_UTCL1_ERROR_1_BASE_IDX 1 +#define regRLC_SPM_UTCL1_ERROR_2 0x4cbd +#define regRLC_SPM_UTCL1_ERROR_2_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH0_ERROR_1 0x4cbe +#define regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX 1 +#define regRLC_LB_THR_CONFIG_1 0x4cbf +#define regRLC_LB_THR_CONFIG_1_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH0_ERROR_2 0x4cc0 +#define regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH1_ERROR_1 0x4cc1 +#define regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH1_ERROR_2 0x4cc2 +#define regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH2_ERROR_1 0x4cc3 +#define regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH2_ERROR_2 0x4cc4 +#define regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX 1 +#define regRLC_SEMAPHORE_0 0x4cc7 +#define regRLC_SEMAPHORE_0_BASE_IDX 1 +#define regRLC_SEMAPHORE_1 0x4cc8 +#define regRLC_SEMAPHORE_1_BASE_IDX 1 +#define regRLC_CP_EOF_INT 0x4cca +#define regRLC_CP_EOF_INT_BASE_IDX 1 +#define regRLC_CP_EOF_INT_CNT 0x4ccb +#define regRLC_CP_EOF_INT_CNT_BASE_IDX 1 +#define regRLC_SPARE_INT 0x4ccc +#define regRLC_SPARE_INT_BASE_IDX 1 +#define regRLC_PREWALKER_UTCL1_CNTL 0x4ccd +#define regRLC_PREWALKER_UTCL1_CNTL_BASE_IDX 1 +#define regRLC_PREWALKER_UTCL1_TRIG 0x4cce +#define regRLC_PREWALKER_UTCL1_TRIG_BASE_IDX 1 +#define regRLC_PREWALKER_UTCL1_ADDR_LSB 0x4ccf +#define regRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX 1 +#define regRLC_PREWALKER_UTCL1_ADDR_MSB 0x4cd0 +#define regRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX 1 +#define regRLC_PREWALKER_UTCL1_SIZE_LSB 0x4cd1 +#define regRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX 1 +#define regRLC_PREWALKER_UTCL1_SIZE_MSB 0x4cd2 +#define regRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX 1 +#define regRLC_DSM_TRIG 0x4cd3 +#define regRLC_DSM_TRIG_BASE_IDX 1 +#define regRLC_UTCL1_STATUS 0x4cd4 +#define regRLC_UTCL1_STATUS_BASE_IDX 1 +#define regRLC_R2I_CNTL_0 0x4cd5 +#define regRLC_R2I_CNTL_0_BASE_IDX 1 +#define regRLC_R2I_CNTL_1 0x4cd6 +#define regRLC_R2I_CNTL_1_BASE_IDX 1 +#define regRLC_R2I_CNTL_2 0x4cd7 +#define regRLC_R2I_CNTL_2_BASE_IDX 1 +#define regRLC_R2I_CNTL_3 0x4cd8 +#define regRLC_R2I_CNTL_3_BASE_IDX 1 +#define regRLC_UTCL2_CNTL 0x4cd9 +#define regRLC_UTCL2_CNTL_BASE_IDX 1 +#define regRLC_LBPW_CU_STAT 0x4cda +#define regRLC_LBPW_CU_STAT_BASE_IDX 1 +#define regRLC_DS_CNTL 0x4cdb +#define regRLC_DS_CNTL_BASE_IDX 1 +#define regRLC_GPM_INT_STAT_TH0 0x4cdc +#define regRLC_GPM_INT_STAT_TH0_BASE_IDX 1 +#define regRLC_GPM_GENERAL_13 0x4cdd +#define regRLC_GPM_GENERAL_13_BASE_IDX 1 +#define regRLC_GPM_GENERAL_14 0x4cde +#define regRLC_GPM_GENERAL_14_BASE_IDX 1 +#define regRLC_GPM_GENERAL_15 0x4cdf +#define regRLC_GPM_GENERAL_15_BASE_IDX 1 +#define regRLC_SPARE_INT_1 0x4ce0 +#define regRLC_SPARE_INT_1_BASE_IDX 1 +#define regRLC_RLCV_SPARE_INT_1 0x4ce1 +#define regRLC_RLCV_SPARE_INT_1_BASE_IDX 1 +#define regRLC_SEMAPHORE_2 0x4ce3 +#define regRLC_SEMAPHORE_2_BASE_IDX 1 +#define regRLC_SEMAPHORE_3 0x4ce4 +#define regRLC_SEMAPHORE_3_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_3 0x4ce5 +#define regRLC_SMU_ARGUMENT_3_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_4 0x4ce6 +#define regRLC_SMU_ARGUMENT_4_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_LSB_1 0x4ce8 +#define regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_MSB_1 0x4ce9 +#define regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX 1 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_1 0x4cea +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_LSB_2 0x4ceb +#define regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_MSB_2 0x4cec +#define regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX 1 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_2 0x4cef +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX 1 +#define regRLC_CPG_STAT_INVAL 0x4d09 +#define regRLC_CPG_STAT_INVAL_BASE_IDX 1 +#define regRLC_UE_ERR_STATUS_LOW 0x4d40 +#define regRLC_UE_ERR_STATUS_LOW_BASE_IDX 1 +#define regRLC_UE_ERR_STATUS_HIGH 0x4d41 +#define regRLC_UE_ERR_STATUS_HIGH_BASE_IDX 1 +#define regRLC_DSM_CNTL 0x4d42 +#define regRLC_DSM_CNTL_BASE_IDX 1 +#define regRLC_DSM_CNTLA 0x4d43 +#define regRLC_DSM_CNTLA_BASE_IDX 1 +#define regRLC_DSM_CNTL2 0x4d44 +#define regRLC_DSM_CNTL2_BASE_IDX 1 +#define regRLC_DSM_CNTL2A 0x4d45 +#define regRLC_DSM_CNTL2A_BASE_IDX 1 +#define regRLC_CE_ERR_STATUS_LOW 0x4d49 +#define regRLC_CE_ERR_STATUS_LOW_BASE_IDX 1 +#define regRLC_CE_ERR_STATUS_HIGH 0x4d4a +#define regRLC_CE_ERR_STATUS_HIGH_BASE_IDX 1 +#define regRLC_RLCV_SPARE_INT 0x4f30 +#define regRLC_RLCV_SPARE_INT_BASE_IDX 1 +#define regRLC_SMU_CLK_REQ 0x4f97 +#define regRLC_SMU_CLK_REQ_BASE_IDX 1 + + +// addressBlock: xcd0_gc_pwrdec +// base address: 0x3c000 +#define regCGTS_SM_CTRL_REG 0x5000 +#define regCGTS_SM_CTRL_REG_BASE_IDX 1 +#define regCGTS_RD_CTRL_REG 0x5001 +#define regCGTS_RD_CTRL_REG_BASE_IDX 1 +#define regCGTS_RD_REG 0x5002 +#define regCGTS_RD_REG_BASE_IDX 1 +#define regCGTS_TCC_DISABLE 0x5003 +#define regCGTS_TCC_DISABLE_BASE_IDX 1 +#define regCGTS_USER_TCC_DISABLE 0x5004 +#define regCGTS_USER_TCC_DISABLE_BASE_IDX 1 +#define regCGTS_CU0_SP0_CTRL_REG 0x5008 +#define regCGTS_CU0_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU0_LDS_SQ_CTRL_REG 0x5009 +#define regCGTS_CU0_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU0_TA_SQC_CTRL_REG 0x500a +#define regCGTS_CU0_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU0_SP1_CTRL_REG 0x500b +#define regCGTS_CU0_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU0_TD_TCP_CTRL_REG 0x500c +#define regCGTS_CU0_TD_TCP_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU1_SP0_CTRL_REG 0x500d +#define regCGTS_CU1_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU1_LDS_SQ_CTRL_REG 0x500e +#define regCGTS_CU1_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU1_TA_SQC_CTRL_REG 0x500f +#define regCGTS_CU1_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU1_SP1_CTRL_REG 0x5010 +#define regCGTS_CU1_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU1_TD_TCP_CTRL_REG 0x5011 +#define regCGTS_CU1_TD_TCP_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU2_SP0_CTRL_REG 0x5012 +#define regCGTS_CU2_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU2_LDS_SQ_CTRL_REG 0x5013 +#define regCGTS_CU2_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU2_TA_SQC_CTRL_REG 0x5014 +#define regCGTS_CU2_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU2_SP1_CTRL_REG 0x5015 +#define regCGTS_CU2_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU2_TD_TCP_CTRL_REG 0x5016 +#define regCGTS_CU2_TD_TCP_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU3_SP0_CTRL_REG 0x5017 +#define regCGTS_CU3_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU3_LDS_SQ_CTRL_REG 0x5018 +#define regCGTS_CU3_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU3_TA_SQC_CTRL_REG 0x5019 +#define regCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU3_SP1_CTRL_REG 0x501a +#define regCGTS_CU3_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU3_TD_TCP_CTRL_REG 0x501b +#define regCGTS_CU3_TD_TCP_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU4_SP0_CTRL_REG 0x501c +#define regCGTS_CU4_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU4_LDS_SQ_CTRL_REG 0x501d +#define regCGTS_CU4_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU4_TA_SQC_CTRL_REG 0x501e +#define regCGTS_CU4_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU4_SP1_CTRL_REG 0x501f +#define regCGTS_CU4_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU4_TD_TCP_CTRL_REG 0x5020 +#define regCGTS_CU4_TD_TCP_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU5_SP0_CTRL_REG 0x5021 +#define regCGTS_CU5_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU5_LDS_SQ_CTRL_REG 0x5022 +#define regCGTS_CU5_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU5_TA_SQC_CTRL_REG 0x5023 +#define regCGTS_CU5_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU5_SP1_CTRL_REG 0x5024 +#define regCGTS_CU5_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU5_TD_TCP_CTRL_REG 0x5025 +#define regCGTS_CU5_TD_TCP_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU6_SP0_CTRL_REG 0x5026 +#define regCGTS_CU6_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU6_LDS_SQ_CTRL_REG 0x5027 +#define regCGTS_CU6_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU6_TA_SQC_CTRL_REG 0x5028 +#define regCGTS_CU6_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU6_SP1_CTRL_REG 0x5029 +#define regCGTS_CU6_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU6_TD_TCP_CTRL_REG 0x502a +#define regCGTS_CU6_TD_TCP_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU7_SP0_CTRL_REG 0x502b +#define regCGTS_CU7_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU7_LDS_SQ_CTRL_REG 0x502c +#define regCGTS_CU7_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU7_TA_SQC_CTRL_REG 0x502d +#define regCGTS_CU7_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU7_SP1_CTRL_REG 0x502e +#define regCGTS_CU7_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU7_TD_TCP_CTRL_REG 0x502f +#define regCGTS_CU7_TD_TCP_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU8_SP0_CTRL_REG 0x5030 +#define regCGTS_CU8_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU8_LDS_SQ_CTRL_REG 0x5031 +#define regCGTS_CU8_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU8_TA_SQC_CTRL_REG 0x5032 +#define regCGTS_CU8_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU8_SP1_CTRL_REG 0x5033 +#define regCGTS_CU8_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU8_TD_TCP_CTRL_REG 0x5034 +#define regCGTS_CU8_TD_TCP_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU9_SP0_CTRL_REG 0x5035 +#define regCGTS_CU9_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU9_LDS_SQ_CTRL_REG 0x5036 +#define regCGTS_CU9_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU9_TA_SQC_CTRL_REG 0x5037 +#define regCGTS_CU9_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU9_SP1_CTRL_REG 0x5038 +#define regCGTS_CU9_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU9_TD_TCP_CTRL_REG 0x5039 +#define regCGTS_CU9_TD_TCP_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU10_SP0_CTRL_REG 0x503a +#define regCGTS_CU10_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU10_LDS_SQ_CTRL_REG 0x503b +#define regCGTS_CU10_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU10_TA_SQC_CTRL_REG 0x503c +#define regCGTS_CU10_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU10_SP1_CTRL_REG 0x503d +#define regCGTS_CU10_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU10_TD_TCP_CTRL_REG 0x503e +#define regCGTS_CU10_TD_TCP_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU11_SP0_CTRL_REG 0x503f +#define regCGTS_CU11_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU11_LDS_SQ_CTRL_REG 0x5040 +#define regCGTS_CU11_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU11_TA_SQC_CTRL_REG 0x5041 +#define regCGTS_CU11_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU11_SP1_CTRL_REG 0x5042 +#define regCGTS_CU11_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU11_TD_TCP_CTRL_REG 0x5043 +#define regCGTS_CU11_TD_TCP_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU12_SP0_CTRL_REG 0x5044 +#define regCGTS_CU12_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU12_LDS_SQ_CTRL_REG 0x5045 +#define regCGTS_CU12_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU12_TA_SQC_CTRL_REG 0x5046 +#define regCGTS_CU12_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU12_SP1_CTRL_REG 0x5047 +#define regCGTS_CU12_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU12_TD_TCP_CTRL_REG 0x5048 +#define regCGTS_CU12_TD_TCP_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU13_SP0_CTRL_REG 0x5049 +#define regCGTS_CU13_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU13_LDS_SQ_CTRL_REG 0x504a +#define regCGTS_CU13_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU13_TA_SQC_CTRL_REG 0x504b +#define regCGTS_CU13_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU13_SP1_CTRL_REG 0x504c +#define regCGTS_CU13_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU13_TD_TCP_CTRL_REG 0x504d +#define regCGTS_CU13_TD_TCP_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU14_SP0_CTRL_REG 0x504e +#define regCGTS_CU14_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU14_LDS_SQ_CTRL_REG 0x504f +#define regCGTS_CU14_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU14_TA_SQC_CTRL_REG 0x5050 +#define regCGTS_CU14_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU14_SP1_CTRL_REG 0x5051 +#define regCGTS_CU14_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU14_TD_TCP_CTRL_REG 0x5052 +#define regCGTS_CU14_TD_TCP_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU15_SP0_CTRL_REG 0x5053 +#define regCGTS_CU15_SP0_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU15_LDS_SQ_CTRL_REG 0x5054 +#define regCGTS_CU15_LDS_SQ_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU15_TA_SQC_CTRL_REG 0x5055 +#define regCGTS_CU15_TA_SQC_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU15_SP1_CTRL_REG 0x5056 +#define regCGTS_CU15_SP1_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU15_TD_TCP_CTRL_REG 0x5057 +#define regCGTS_CU15_TD_TCP_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU0_TCPI_CTRL_REG 0x5058 +#define regCGTS_CU0_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU1_TCPI_CTRL_REG 0x5059 +#define regCGTS_CU1_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU2_TCPI_CTRL_REG 0x505a +#define regCGTS_CU2_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU3_TCPI_CTRL_REG 0x505b +#define regCGTS_CU3_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU4_TCPI_CTRL_REG 0x505c +#define regCGTS_CU4_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU5_TCPI_CTRL_REG 0x505d +#define regCGTS_CU5_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU6_TCPI_CTRL_REG 0x505e +#define regCGTS_CU6_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU7_TCPI_CTRL_REG 0x505f +#define regCGTS_CU7_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU8_TCPI_CTRL_REG 0x5060 +#define regCGTS_CU8_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU9_TCPI_CTRL_REG 0x5061 +#define regCGTS_CU9_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU10_TCPI_CTRL_REG 0x5062 +#define regCGTS_CU10_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU11_TCPI_CTRL_REG 0x5063 +#define regCGTS_CU11_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU12_TCPI_CTRL_REG 0x5064 +#define regCGTS_CU12_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU13_TCPI_CTRL_REG 0x5065 +#define regCGTS_CU13_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU14_TCPI_CTRL_REG 0x5066 +#define regCGTS_CU14_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTS_CU15_TCPI_CTRL_REG 0x5067 +#define regCGTS_CU15_TCPI_CTRL_REG_BASE_IDX 1 +#define regCGTT_SPI_PS_CLK_CTRL 0x507d +#define regCGTT_SPI_PS_CLK_CTRL_BASE_IDX 1 +#define regCGTT_SPIS_CLK_CTRL 0x507e +#define regCGTT_SPIS_CLK_CTRL_BASE_IDX 1 +#define regCGTX_SPI_DEBUG_CLK_CTRL 0x507f +#define regCGTX_SPI_DEBUG_CLK_CTRL_BASE_IDX 1 +#define regCGTT_SPI_CLK_CTRL 0x5080 +#define regCGTT_SPI_CLK_CTRL_BASE_IDX 1 +#define regCGTT_PC_CLK_CTRL 0x5081 +#define regCGTT_PC_CLK_CTRL_BASE_IDX 1 +#define regCGTT_BCI_CLK_CTRL 0x5082 +#define regCGTT_BCI_CLK_CTRL_BASE_IDX 1 +#define regCGTT_VGT_CLK_CTRL 0x5084 +#define regCGTT_VGT_CLK_CTRL_BASE_IDX 1 +#define regCGTT_IA_CLK_CTRL 0x5085 +#define regCGTT_IA_CLK_CTRL_BASE_IDX 1 +#define regCGTT_WD_CLK_CTRL 0x5086 +#define regCGTT_WD_CLK_CTRL_BASE_IDX 1 +#define regCGTT_PA_CLK_CTRL 0x5088 +#define regCGTT_PA_CLK_CTRL_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL0 0x5089 +#define regCGTT_SC_CLK_CTRL0_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL1 0x508a +#define regCGTT_SC_CLK_CTRL1_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL2 0x508b +#define regCGTT_SC_CLK_CTRL2_BASE_IDX 1 +#define regCGTT_SQ_CLK_CTRL 0x508c +#define regCGTT_SQ_CLK_CTRL_BASE_IDX 1 +#define regCGTT_SQG_CLK_CTRL 0x508d +#define regCGTT_SQG_CLK_CTRL_BASE_IDX 1 +#define regSQ_ALU_CLK_CTRL 0x508e +#define regSQ_ALU_CLK_CTRL_BASE_IDX 1 +#define regSQ_TEX_CLK_CTRL 0x508f +#define regSQ_TEX_CLK_CTRL_BASE_IDX 1 +#define regSQ_LDS_CLK_CTRL 0x5090 +#define regSQ_LDS_CLK_CTRL_BASE_IDX 1 +#define regSQ_POWER_THROTTLE 0x5091 +#define regSQ_POWER_THROTTLE_BASE_IDX 1 +#define regSQ_POWER_THROTTLE2 0x5092 +#define regSQ_POWER_THROTTLE2_BASE_IDX 1 +#define regTD_CGTT_CTRL 0x509c +#define regTD_CGTT_CTRL_BASE_IDX 1 +#define regTA_CGTT_CTRL 0x509d +#define regTA_CGTT_CTRL_BASE_IDX 1 +#define regCGTT_TCPI_CLK_CTRL 0x509e +#define regCGTT_TCPI_CLK_CTRL_BASE_IDX 1 +#define regTCX_CGTT_SCLK_CTRL 0x50a3 +#define regTCX_CGTT_SCLK_CTRL_BASE_IDX 1 +#define regDB_CGTT_CLK_CTRL_0 0x50a4 +#define regDB_CGTT_CLK_CTRL_0_BASE_IDX 1 +#define regCB_CGTT_SCLK_CTRL 0x50a8 +#define regCB_CGTT_SCLK_CTRL_BASE_IDX 1 +#define regTCC_CGTT_SCLK_CTRL 0x50ac +#define regTCC_CGTT_SCLK_CTRL_BASE_IDX 1 +#define regTCC_CGTT_SCLK_CTRL2 0x50ad +#define regTCC_CGTT_SCLK_CTRL2_BASE_IDX 1 +#define regTCC_CGTT_SCLK_CTRL3 0x50ae +#define regTCC_CGTT_SCLK_CTRL3_BASE_IDX 1 +#define regTCA_CGTT_SCLK_CTRL 0x50af +#define regTCA_CGTT_SCLK_CTRL_BASE_IDX 1 +#define regCGTT_CP_CLK_CTRL 0x50b0 +#define regCGTT_CP_CLK_CTRL_BASE_IDX 1 +#define regCGTT_CPC_CLK_CTRL 0x50b2 +#define regCGTT_CPC_CLK_CTRL_BASE_IDX 1 +#define regCGTT_RLC_CLK_CTRL 0x50b5 +#define regCGTT_RLC_CLK_CTRL_BASE_IDX 1 +#define regRLC_GFX_RM_CNTL 0x50b6 +#define regRLC_GFX_RM_CNTL_BASE_IDX 1 +#define regRMI_CGTT_SCLK_CTRL 0x50c0 +#define regRMI_CGTT_SCLK_CTRL_BASE_IDX 1 +#define regCGTT_TCPF_CLK_CTRL 0x50c1 +#define regCGTT_TCPF_CLK_CTRL_BASE_IDX 1 + + +// addressBlock: xcd0_gc_hypdec +// base address: 0x3e000 +#define regCP_HYP_PFP_UCODE_ADDR 0x5814 +#define regCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 +#define regCP_PFP_UCODE_ADDR 0x5814 +#define regCP_PFP_UCODE_ADDR_BASE_IDX 1 +#define regCP_HYP_PFP_UCODE_DATA 0x5815 +#define regCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 +#define regCP_PFP_UCODE_DATA 0x5815 +#define regCP_PFP_UCODE_DATA_BASE_IDX 1 +#define regCP_HYP_ME_UCODE_ADDR 0x5816 +#define regCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 +#define regCP_ME_RAM_RADDR 0x5816 +#define regCP_ME_RAM_RADDR_BASE_IDX 1 +#define regCP_ME_RAM_WADDR 0x5816 +#define regCP_ME_RAM_WADDR_BASE_IDX 1 +#define regCP_HYP_ME_UCODE_DATA 0x5817 +#define regCP_HYP_ME_UCODE_DATA_BASE_IDX 1 +#define regCP_ME_RAM_DATA 0x5817 +#define regCP_ME_RAM_DATA_BASE_IDX 1 +#define regCP_CE_UCODE_ADDR 0x5818 +#define regCP_CE_UCODE_ADDR_BASE_IDX 1 +#define regCP_HYP_CE_UCODE_ADDR 0x5818 +#define regCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 +#define regCP_CE_UCODE_DATA 0x5819 +#define regCP_CE_UCODE_DATA_BASE_IDX 1 +#define regCP_HYP_CE_UCODE_DATA 0x5819 +#define regCP_HYP_CE_UCODE_DATA_BASE_IDX 1 +#define regCP_HYP_MEC1_UCODE_ADDR 0x581a +#define regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX 1 +#define regCP_MEC_ME1_UCODE_ADDR 0x581a +#define regCP_MEC_ME1_UCODE_ADDR_BASE_IDX 1 +#define regCP_HYP_MEC1_UCODE_DATA 0x581b +#define regCP_HYP_MEC1_UCODE_DATA_BASE_IDX 1 +#define regCP_MEC_ME1_UCODE_DATA 0x581b +#define regCP_MEC_ME1_UCODE_DATA_BASE_IDX 1 +#define regCP_HYP_MEC2_UCODE_ADDR 0x581c +#define regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX 1 +#define regCP_MEC_ME2_UCODE_ADDR 0x581c +#define regCP_MEC_ME2_UCODE_ADDR_BASE_IDX 1 +#define regCP_HYP_MEC2_UCODE_DATA 0x581d +#define regCP_HYP_MEC2_UCODE_DATA_BASE_IDX 1 +#define regCP_MEC_ME2_UCODE_DATA 0x581d +#define regCP_MEC_ME2_UCODE_DATA_BASE_IDX 1 +#define regCP_HYP_PFP_UCODE_CHKSUM 0x581e +#define regCP_HYP_PFP_UCODE_CHKSUM_BASE_IDX 1 +#define regCP_HYP_CE_UCODE_CHKSUM 0x581f +#define regCP_HYP_CE_UCODE_CHKSUM_BASE_IDX 1 +#define regCP_HYP_ME_UCODE_CHKSUM 0x5820 +#define regCP_HYP_ME_UCODE_CHKSUM_BASE_IDX 1 +#define regCP_HYP_MEC_ME1_UCODE_CHKSUM 0x5821 +#define regCP_HYP_MEC_ME1_UCODE_CHKSUM_BASE_IDX 1 +#define regCP_HYP_MEC_ME2_UCODE_CHKSUM 0x5822 +#define regCP_HYP_MEC_ME2_UCODE_CHKSUM_BASE_IDX 1 +#define regCP_HYP_XCP_CTL 0x5828 +#define regCP_HYP_XCP_CTL_BASE_IDX 1 +#define regRLC_GPM_UCODE_ADDR 0x583c +#define regRLC_GPM_UCODE_ADDR_BASE_IDX 1 +#define regRLC_GPM_UCODE_DATA 0x583d +#define regRLC_GPM_UCODE_DATA_BASE_IDX 1 +#define regGRBM_GFX_INDEX_SR_SELECT 0x5a00 +#define regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX 1 +#define regGRBM_GFX_INDEX_SR_DATA 0x5a01 +#define regGRBM_GFX_INDEX_SR_DATA_BASE_IDX 1 +#define regGRBM_GFX_CNTL_SR_SELECT 0x5a02 +#define regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX 1 +#define regGRBM_GFX_CNTL_SR_DATA 0x5a03 +#define regGRBM_GFX_CNTL_SR_DATA_BASE_IDX 1 +#define regGRBM_MCM_ADDR 0x5a07 +#define regGRBM_MCM_ADDR_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_ENABLE 0x5b00 +#define regRLC_GPU_IOV_VF_ENABLE_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG6 0x5b06 +#define regRLC_GPU_IOV_CFG_REG6_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG8 0x5b20 +#define regRLC_GPU_IOV_CFG_REG8_BASE_IDX 1 +#define regRLC_RLCV_TIMER_INT_0 0x5b25 +#define regRLC_RLCV_TIMER_INT_0_BASE_IDX 1 +#define regRLC_RLCV_TIMER_CTRL 0x5b26 +#define regRLC_RLCV_TIMER_CTRL_BASE_IDX 1 +#define regRLC_RLCV_TIMER_STAT 0x5b27 +#define regRLC_RLCV_TIMER_STAT_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS 0x5b2a +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0x5b2b +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0x5b2c +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_MASK 0x5b2d +#define regRLC_GPU_IOV_VF_MASK_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_0 0x5b2e +#define regRLC_HYP_SEMAPHORE_0_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_1 0x5b2f +#define regRLC_HYP_SEMAPHORE_1_BASE_IDX 1 +#define regRLC_CLK_CNTL 0x5b31 +#define regRLC_CLK_CNTL_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_BLOCK 0x5b34 +#define regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG1 0x5b35 +#define regRLC_GPU_IOV_CFG_REG1_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG2 0x5b36 +#define regRLC_GPU_IOV_CFG_REG2_BASE_IDX 1 +#define regRLC_GPU_IOV_VM_BUSY_STATUS 0x5b37 +#define regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_0 0x5b38 +#define regRLC_GPU_IOV_SCH_0_BASE_IDX 1 +#define regRLC_GPU_IOV_ACTIVE_FCN_ID 0x5b39 +#define regRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_3 0x5b3a +#define regRLC_GPU_IOV_SCH_3_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_1 0x5b3b +#define regRLC_GPU_IOV_SCH_1_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_2 0x5b3c +#define regRLC_GPU_IOV_SCH_2_BASE_IDX 1 +#define regRLC_GPU_IOV_INT_STAT 0x5b3f +#define regRLC_GPU_IOV_INT_STAT_BASE_IDX 1 +#define regRLC_RLCV_TIMER_INT_1 0x5b40 +#define regRLC_RLCV_TIMER_INT_1_BASE_IDX 1 +#define regRLC_GPU_IOV_UCODE_ADDR 0x5b42 +#define regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX 1 +#define regRLC_GPU_IOV_UCODE_DATA 0x5b43 +#define regRLC_GPU_IOV_UCODE_DATA_BASE_IDX 1 +#define regRLC_GPU_IOV_SCRATCH_ADDR 0x5b44 +#define regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX 1 +#define regRLC_GPU_IOV_SCRATCH_DATA 0x5b45 +#define regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX 1 +#define regRLC_GPU_IOV_F32_CNTL 0x5b46 +#define regRLC_GPU_IOV_F32_CNTL_BASE_IDX 1 +#define regRLC_GPU_IOV_F32_RESET 0x5b47 +#define regRLC_GPU_IOV_F32_RESET_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA0_STATUS 0x5b48 +#define regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA1_STATUS 0x5b49 +#define regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SMU_RESPONSE 0x5b4a +#define regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX 1 +#define regRLC_GPU_IOV_VIRT_RESET_REQ 0x5b4c +#define regRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX 1 +#define regRLC_GPU_IOV_RLC_RESPONSE 0x5b4d +#define regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX 1 +#define regRLC_GPU_IOV_INT_DISABLE 0x5b4e +#define regRLC_GPU_IOV_INT_DISABLE_BASE_IDX 1 +#define regRLC_GPU_IOV_INT_FORCE 0x5b4f +#define regRLC_GPU_IOV_INT_FORCE_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA0_BUSY_STATUS 0x5b50 +#define regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA1_BUSY_STATUS 0x5b51 +#define regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_2 0x5b52 +#define regRLC_HYP_SEMAPHORE_2_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_3 0x5b53 +#define regRLC_HYP_SEMAPHORE_3_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA2_STATUS 0x5b54 +#define regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA3_STATUS 0x5b55 +#define regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA4_STATUS 0x5b56 +#define regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA5_STATUS 0x5b57 +#define regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA6_STATUS 0x5b58 +#define regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA7_STATUS 0x5b59 +#define regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA2_BUSY_STATUS 0x5b5a +#define regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA3_BUSY_STATUS 0x5b5b +#define regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA4_BUSY_STATUS 0x5b5c +#define regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA5_BUSY_STATUS 0x5b5d +#define regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA6_BUSY_STATUS 0x5b5e +#define regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA7_BUSY_STATUS 0x5b5f +#define regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX 1 + + +// addressBlock: xcd0_gc_utcl2_vmsharedhvdec +// base address: 0x3ea00 +#define regMC_VM_FB_SIZE_OFFSET_VF0 0x5a80 +#define regMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF1 0x5a81 +#define regMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF2 0x5a82 +#define regMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF3 0x5a83 +#define regMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF4 0x5a84 +#define regMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF5 0x5a85 +#define regMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF6 0x5a86 +#define regMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF7 0x5a87 +#define regMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF8 0x5a88 +#define regMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF9 0x5a89 +#define regMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF10 0x5a8a +#define regMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF11 0x5a8b +#define regMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF12 0x5a8c +#define regMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF13 0x5a8d +#define regMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF14 0x5a8e +#define regMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 +#define regMC_VM_FB_SIZE_OFFSET_VF15 0x5a8f +#define regMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 +#define regVM_IOMMU_MMIO_CNTRL_1 0x5a90 +#define regVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 1 +#define regMC_VM_MARC_BASE_LO_0 0x5a91 +#define regMC_VM_MARC_BASE_LO_0_BASE_IDX 1 +#define regMC_VM_MARC_BASE_LO_1 0x5a92 +#define regMC_VM_MARC_BASE_LO_1_BASE_IDX 1 +#define regMC_VM_MARC_BASE_LO_2 0x5a93 +#define regMC_VM_MARC_BASE_LO_2_BASE_IDX 1 +#define regMC_VM_MARC_BASE_LO_3 0x5a94 +#define regMC_VM_MARC_BASE_LO_3_BASE_IDX 1 +#define regMC_VM_MARC_BASE_HI_0 0x5a95 +#define regMC_VM_MARC_BASE_HI_0_BASE_IDX 1 +#define regMC_VM_MARC_BASE_HI_1 0x5a96 +#define regMC_VM_MARC_BASE_HI_1_BASE_IDX 1 +#define regMC_VM_MARC_BASE_HI_2 0x5a97 +#define regMC_VM_MARC_BASE_HI_2_BASE_IDX 1 +#define regMC_VM_MARC_BASE_HI_3 0x5a98 +#define regMC_VM_MARC_BASE_HI_3_BASE_IDX 1 +#define regMC_VM_MARC_RELOC_LO_0 0x5a99 +#define regMC_VM_MARC_RELOC_LO_0_BASE_IDX 1 +#define regMC_VM_MARC_RELOC_LO_1 0x5a9a +#define regMC_VM_MARC_RELOC_LO_1_BASE_IDX 1 +#define regMC_VM_MARC_RELOC_LO_2 0x5a9b +#define regMC_VM_MARC_RELOC_LO_2_BASE_IDX 1 +#define regMC_VM_MARC_RELOC_LO_3 0x5a9c +#define regMC_VM_MARC_RELOC_LO_3_BASE_IDX 1 +#define regMC_VM_MARC_RELOC_HI_0 0x5a9d +#define regMC_VM_MARC_RELOC_HI_0_BASE_IDX 1 +#define regMC_VM_MARC_RELOC_HI_1 0x5a9e +#define regMC_VM_MARC_RELOC_HI_1_BASE_IDX 1 +#define regMC_VM_MARC_RELOC_HI_2 0x5a9f +#define regMC_VM_MARC_RELOC_HI_2_BASE_IDX 1 +#define regMC_VM_MARC_RELOC_HI_3 0x5aa0 +#define regMC_VM_MARC_RELOC_HI_3_BASE_IDX 1 +#define regMC_VM_MARC_LEN_LO_0 0x5aa1 +#define regMC_VM_MARC_LEN_LO_0_BASE_IDX 1 +#define regMC_VM_MARC_LEN_LO_1 0x5aa2 +#define regMC_VM_MARC_LEN_LO_1_BASE_IDX 1 +#define regMC_VM_MARC_LEN_LO_2 0x5aa3 +#define regMC_VM_MARC_LEN_LO_2_BASE_IDX 1 +#define regMC_VM_MARC_LEN_LO_3 0x5aa4 +#define regMC_VM_MARC_LEN_LO_3_BASE_IDX 1 +#define regMC_VM_MARC_LEN_HI_0 0x5aa5 +#define regMC_VM_MARC_LEN_HI_0_BASE_IDX 1 +#define regMC_VM_MARC_LEN_HI_1 0x5aa6 +#define regMC_VM_MARC_LEN_HI_1_BASE_IDX 1 +#define regMC_VM_MARC_LEN_HI_2 0x5aa7 +#define regMC_VM_MARC_LEN_HI_2_BASE_IDX 1 +#define regMC_VM_MARC_LEN_HI_3 0x5aa8 +#define regMC_VM_MARC_LEN_HI_3_BASE_IDX 1 +#define regVM_IOMMU_CONTROL_REGISTER 0x5aa9 +#define regVM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 +#define regVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x5aaa +#define regVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL 0x5aab +#define regVM_PCIE_ATS_CNTL_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_0 0x5aac +#define regVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_1 0x5aad +#define regVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_2 0x5aae +#define regVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_3 0x5aaf +#define regVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_4 0x5ab0 +#define regVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_5 0x5ab1 +#define regVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_6 0x5ab2 +#define regVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_7 0x5ab3 +#define regVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_8 0x5ab4 +#define regVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_9 0x5ab5 +#define regVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_10 0x5ab6 +#define regVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_11 0x5ab7 +#define regVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_12 0x5ab8 +#define regVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_13 0x5ab9 +#define regVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_14 0x5aba +#define regVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1 +#define regVM_PCIE_ATS_CNTL_VF_15 0x5abb +#define regVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1 +#define regMC_SHARED_ACTIVE_FCN_ID 0x5abc +#define regMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1 +#define regMC_VM_XGMI_GPUIOV_ENABLE 0x5abd +#define regMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 1 + + +// addressBlock: xcd0_gc_pspdec +// base address: 0x3f000 +#define regCPG_PSP_DEBUG 0x5c30 +#define regCPG_PSP_DEBUG_BASE_IDX 1 +#define regCPC_PSP_DEBUG 0x5c31 +#define regCPC_PSP_DEBUG_BASE_IDX 1 +#define regCP_PSP_XCP_CTL 0x5c34 +#define regCP_PSP_XCP_CTL_BASE_IDX 1 +#define regGRBM_SEC_CNTL 0x5e0b +#define regGRBM_SEC_CNTL_BASE_IDX 1 +#define regGRBM_IOV_ERROR_FIFO_DATA 0x5e12 +#define regGRBM_IOV_ERROR_FIFO_DATA_BASE_IDX 1 +#define regGRBM_DSM_BYPASS 0x5e13 +#define regGRBM_DSM_BYPASS_BASE_IDX 1 +#define regGRBM_CAM_INDEX 0x5e16 +#define regGRBM_CAM_INDEX_BASE_IDX 1 +#define regGRBM_HYP_CAM_INDEX 0x5e16 +#define regGRBM_HYP_CAM_INDEX_BASE_IDX 1 +#define regGRBM_CAM_DATA 0x5e17 +#define regGRBM_CAM_DATA_BASE_IDX 1 +#define regGRBM_HYP_CAM_DATA 0x5e17 +#define regGRBM_HYP_CAM_DATA_BASE_IDX 1 +#define regRLC_FWL_FIRST_VIOL_ADDR 0x5f37 +#define regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX 1 + + +// addressBlock: sqind +// base address: 0x0 +#define ixSQ_DEBUG_STS_LOCAL 0x0008 +#define ixSQ_DEBUG_CTRL_LOCAL 0x0009 +#define ixSQ_WAVE_VALID_AND_IDLE 0x000a +#define ixSQ_WAVE_MODE 0x0011 +#define ixSQ_WAVE_STATUS 0x0012 +#define ixSQ_WAVE_TRAPSTS 0x0013 +#define ixSQ_WAVE_HW_ID 0x0014 +#define ixSQ_WAVE_GPR_ALLOC 0x0015 +#define ixSQ_WAVE_LDS_ALLOC 0x0016 +#define ixSQ_WAVE_IB_STS 0x0017 +#define ixSQ_WAVE_PC_LO 0x0018 +#define ixSQ_WAVE_PC_HI 0x0019 +#define ixSQ_WAVE_INST_DW0 0x001a +#define ixSQ_WAVE_INST_DW1 0x001b +#define ixSQ_WAVE_IB_DBG0 0x001c +#define ixSQ_WAVE_IB_DBG1 0x001d +#define ixSQ_WAVE_FLUSH_IB 0x001e +#define ixSQ_WAVE_TTMP0 0x026c +#define ixSQ_WAVE_TTMP1 0x026d +#define ixSQ_WAVE_TTMP2 0x026e +#define ixSQ_WAVE_TTMP3 0x026f +#define ixSQ_WAVE_TTMP4 0x0270 +#define ixSQ_WAVE_TTMP5 0x0271 +#define ixSQ_WAVE_TTMP6 0x0272 +#define ixSQ_WAVE_TTMP7 0x0273 +#define ixSQ_WAVE_TTMP8 0x0274 +#define ixSQ_WAVE_TTMP9 0x0275 +#define ixSQ_WAVE_TTMP10 0x0276 +#define ixSQ_WAVE_TTMP11 0x0277 +#define ixSQ_WAVE_TTMP12 0x0278 +#define ixSQ_WAVE_TTMP13 0x0279 +#define ixSQ_WAVE_TTMP14 0x027a +#define ixSQ_WAVE_TTMP15 0x027b +#define ixSQ_WAVE_M0 0x027c +#define ixSQ_WAVE_EXEC_LO 0x027e +#define ixSQ_WAVE_EXEC_HI 0x027f +#define ixSQ_INTERRUPT_WORD_AUTO_CTXID 0x20c0 +#define ixSQ_INTERRUPT_WORD_AUTO_HI 0x20c0 +#define ixSQ_INTERRUPT_WORD_AUTO_LO 0x20c0 +#define ixSQ_INTERRUPT_WORD_CMN_CTXID 0x20c0 +#define ixSQ_INTERRUPT_WORD_CMN_HI 0x20c0 +#define ixSQ_INTERRUPT_WORD_WAVE_CTXID 0x20c0 +#define ixSQ_INTERRUPT_WORD_WAVE_HI 0x20c0 +#define ixSQ_INTERRUPT_WORD_WAVE_LO 0x20c0 + + +#endif diff --git a/extra/amdpci/headers/gc_9_4_3_sh_mask.h b/extra/amdpci/headers/gc_9_4_3_sh_mask.h new file mode 100644 index 0000000000..2bd9f3f102 --- /dev/null +++ b/extra/amdpci/headers/gc_9_4_3_sh_mask.h @@ -0,0 +1,31647 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _gc_9_4_3_SH_MASK_HEADER +#define _gc_9_4_3_SH_MASK_HEADER + + +// addressBlock: xcd0_gc_grbmdec +//GRBM_CNTL +#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 +#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f +#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL +#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L +//GRBM_SKEW_CNTL +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 +#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL +#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L +//GRBM_STATUS2 +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 +#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa +#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb +#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc +#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd +#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe +#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf +#define GRBM_STATUS2__EA_BUSY__SHIFT 0x10 +#define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11 +#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12 +#define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13 +#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14 +#define GRBM_STATUS2__CANE_BUSY__SHIFT 0x15 +#define GRBM_STATUS2__CANE_LINK_BUSY__SHIFT 0x16 +#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18 +#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19 +#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a +#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c +#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d +#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e +#define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L +#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L +#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L +#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L +#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L +#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L +#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L +#define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L +#define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L +#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L +#define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L +#define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L +#define GRBM_STATUS2__CANE_BUSY_MASK 0x00200000L +#define GRBM_STATUS2__CANE_LINK_BUSY_MASK 0x00400000L +#define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L +#define GRBM_STATUS2__TC_BUSY_MASK 0x02000000L +#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x04000000L +#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L +#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L +#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L +#define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L +//GRBM_PWR_CNTL +#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0 +#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2 +#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4 +#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6 +#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe +#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf +#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L +#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL +#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L +#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L +#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L +#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L +//GRBM_STATUS +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 +#define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x5 +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 +#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9 +#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc +#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd +#define GRBM_STATUS__TA_BUSY__SHIFT 0xe +#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf +#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10 +#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11 +#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12 +#define GRBM_STATUS__IA_BUSY__SHIFT 0x13 +#define GRBM_STATUS__SX_BUSY__SHIFT 0x14 +#define GRBM_STATUS__WD_BUSY__SHIFT 0x15 +#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 +#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 +#define GRBM_STATUS__SC_BUSY__SHIFT 0x18 +#define GRBM_STATUS__PA_BUSY__SHIFT 0x19 +#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a +#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c +#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d +#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e +#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL +#define GRBM_STATUS__RSMU_RQ_PENDING_MASK 0x00000020L +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L +#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L +#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L +#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L +#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L +#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L +#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L +#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L +#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L +#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L +#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L +#define GRBM_STATUS__WD_BUSY_MASK 0x00200000L +#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L +#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L +#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L +#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L +#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L +#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L +#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L +#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L +#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L +//GRBM_STATUS_SE0 +#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15 +#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L +#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L +#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L +//GRBM_STATUS_SE1 +#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15 +#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L +#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L +#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L +//GRBM_SOFT_RESET +#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 +#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 +#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 +#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 +#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 +#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 +#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14 +#define GRBM_SOFT_RESET__SOFT_RESET_CANE__SHIFT 0x15 +#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16 +#define GRBM_SOFT_RESET__SOFT_RESET_UTCL2__SHIFT 0x17 +#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L +#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L +#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L +#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L +#define GRBM_SOFT_RESET__SOFT_RESET_CANE_MASK 0x00200000L +#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L +#define GRBM_SOFT_RESET__SOFT_RESET_UTCL2_MASK 0x00800000L +//GRBM_GFX_CLKEN_CNTL +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L +//GRBM_WAIT_IDLE_CLOCKS +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL +//GRBM_STATUS_SE2 +#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15 +#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L +#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L +#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L +//GRBM_STATUS_SE3 +#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15 +#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L +#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L +#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L +//GRBM_READ_ERROR +#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 +#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 +#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 +#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f +#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL +#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L +#define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L +#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L +//GRBM_READ_ERROR2 +#define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10 +#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT 0x11 +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f +#define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L +#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 0x00020000L +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L +//GRBM_INT_CNTL +#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 +#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L +//GRBM_TRAP_OP +#define GRBM_TRAP_OP__RW__SHIFT 0x0 +#define GRBM_TRAP_OP__RW_MASK 0x00000001L +//GRBM_TRAP_ADDR +#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0 +#define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL +//GRBM_TRAP_ADDR_MSK +#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0 +#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL +//GRBM_TRAP_WD +#define GRBM_TRAP_WD__DATA__SHIFT 0x0 +#define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL +//GRBM_TRAP_WD_MSK +#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0 +#define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL +//GRBM_WRITE_ERROR +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0 +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT 0x1 +#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2 +#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5 +#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc +#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd +#define GRBM_WRITE_ERROR__TMZ__SHIFT 0x11 +#define GRBM_WRITE_ERROR__CP_SECURE_WR_ILLEGAL__SHIFT 0x12 +#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14 +#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16 +#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK 0x00000002L +#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL +#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000001E0L +#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L +#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L +#define GRBM_WRITE_ERROR__TMZ_MASK 0x00020000L +#define GRBM_WRITE_ERROR__CP_SECURE_WR_ILLEGAL_MASK 0x00040000L +#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L +#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L +#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L +//GRBM_IOV_ERROR +#define GRBM_IOV_ERROR__IOV_ADDR__SHIFT 0x2 +#define GRBM_IOV_ERROR__IOV_VFID__SHIFT 0x14 +#define GRBM_IOV_ERROR__IOV_VF__SHIFT 0x1a +#define GRBM_IOV_ERROR__IOV_OP__SHIFT 0x1b +#define GRBM_IOV_ERROR__IOV_ERROR__SHIFT 0x1f +#define GRBM_IOV_ERROR__IOV_ADDR_MASK 0x000FFFFCL +#define GRBM_IOV_ERROR__IOV_VFID_MASK 0x03F00000L +#define GRBM_IOV_ERROR__IOV_VF_MASK 0x04000000L +#define GRBM_IOV_ERROR__IOV_OP_MASK 0x08000000L +#define GRBM_IOV_ERROR__IOV_ERROR_MASK 0x80000000L +//GRBM_CHIP_REVISION +#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 +#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL +//GRBM_GFX_CNTL +#define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0 +#define GRBM_GFX_CNTL__MEID__SHIFT 0x2 +#define GRBM_GFX_CNTL__VMID__SHIFT 0x4 +#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 +#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L +#define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL +#define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L +#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L +//GRBM_RSMU_CFG +#define GRBM_RSMU_CFG__APERTURE_ID__SHIFT 0x0 +#define GRBM_RSMU_CFG__QOS__SHIFT 0xc +#define GRBM_RSMU_CFG__POSTED_WR__SHIFT 0x10 +#define GRBM_RSMU_CFG__DEBUG_MASK__SHIFT 0x11 +#define GRBM_RSMU_CFG__APERTURE_ID_MASK 0x00000FFFL +#define GRBM_RSMU_CFG__QOS_MASK 0x0000F000L +#define GRBM_RSMU_CFG__POSTED_WR_MASK 0x00010000L +#define GRBM_RSMU_CFG__DEBUG_MASK_MASK 0x00020000L +//GRBM_IH_CREDIT +#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 +#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L +//GRBM_PWR_CNTL2 +#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10 +#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14 +#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L +#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L +//GRBM_UTCL2_INVAL_RANGE_START +#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0 +#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL +//GRBM_UTCL2_INVAL_RANGE_END +#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0 +#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL +//GRBM_RSMU_READ_ERROR +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT 0x2 +#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT 0x14 +#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT 0x15 +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT 0x1b +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT 0x1f +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK 0x000FFFFCL +#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK 0x00100000L +#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK 0x07E00000L +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK 0x08000000L +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK 0x80000000L +//GRBM_CHICKEN_BITS +#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT 0x0 +#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK 0x00000001L +//GRBM_FENCE_RANGE0 +#define GRBM_FENCE_RANGE0__START__SHIFT 0x0 +#define GRBM_FENCE_RANGE0__END__SHIFT 0x10 +#define GRBM_FENCE_RANGE0__START_MASK 0x0000FFFFL +#define GRBM_FENCE_RANGE0__END_MASK 0xFFFF0000L +//GRBM_FENCE_RANGE1 +#define GRBM_FENCE_RANGE1__START__SHIFT 0x0 +#define GRBM_FENCE_RANGE1__END__SHIFT 0x10 +#define GRBM_FENCE_RANGE1__START_MASK 0x0000FFFFL +#define GRBM_FENCE_RANGE1__END_MASK 0xFFFF0000L +//GRBM_IOV_READ_ERROR +#define GRBM_IOV_READ_ERROR__IOV_ADDR__SHIFT 0x2 +#define GRBM_IOV_READ_ERROR__IOV_VFID__SHIFT 0x14 +#define GRBM_IOV_READ_ERROR__IOV_VF__SHIFT 0x1a +#define GRBM_IOV_READ_ERROR__IOV_OP__SHIFT 0x1b +#define GRBM_IOV_READ_ERROR__IOV_ERROR__SHIFT 0x1f +#define GRBM_IOV_READ_ERROR__IOV_ADDR_MASK 0x000FFFFCL +#define GRBM_IOV_READ_ERROR__IOV_VFID_MASK 0x03F00000L +#define GRBM_IOV_READ_ERROR__IOV_VF_MASK 0x04000000L +#define GRBM_IOV_READ_ERROR__IOV_OP_MASK 0x08000000L +#define GRBM_IOV_READ_ERROR__IOV_ERROR_MASK 0x80000000L +//GRBM_NOWHERE +#define GRBM_NOWHERE__DATA__SHIFT 0x0 +#define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG0 +#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 +#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG1 +#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 +#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG2 +#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 +#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG3 +#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 +#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG4 +#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 +#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG5 +#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 +#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG6 +#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 +#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG7 +#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 +#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL +//VIOLATION_DATA_ASYNC_VF_PROG +#define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID__SHIFT 0x0 +#define VIOLATION_DATA_ASYNC_VF_PROG__VFID__SHIFT 0x4 +#define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR__SHIFT 0x1f +#define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID_MASK 0x0000000FL +#define VIOLATION_DATA_ASYNC_VF_PROG__VFID_MASK 0x000003F0L +#define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR_MASK 0x80000000L + + +// addressBlock: xcd0_gc_cpdec +//CP_CPC_DEBUG_CNTL +#define CP_CPC_DEBUG_CNTL__DEBUG_INDX__SHIFT 0x0 +#define CP_CPC_DEBUG_CNTL__DEBUG_BUS_DC_GD_SEL__SHIFT 0x8 +#define CP_CPC_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS__SHIFT 0x10 +#define CP_CPC_DEBUG_CNTL__DEBUG_BUS_FLOP_EN__SHIFT 0x1f +#define CP_CPC_DEBUG_CNTL__DEBUG_INDX_MASK 0x0000007FL +#define CP_CPC_DEBUG_CNTL__DEBUG_BUS_DC_GD_SEL_MASK 0x00000700L +#define CP_CPC_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS_MASK 0x003F0000L +#define CP_CPC_DEBUG_CNTL__DEBUG_BUS_FLOP_EN_MASK 0x80000000L +//CP_CPF_DEBUG_CNTL +#define CP_CPF_DEBUG_CNTL__DEBUG_INDX__SHIFT 0x0 +#define CP_CPF_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS__SHIFT 0x10 +#define CP_CPF_DEBUG_CNTL__DEBUG_BUS_FLOP_EN__SHIFT 0x1f +#define CP_CPF_DEBUG_CNTL__DEBUG_INDX_MASK 0x0000007FL +#define CP_CPF_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS_MASK 0x003F0000L +#define CP_CPF_DEBUG_CNTL__DEBUG_BUS_FLOP_EN_MASK 0x80000000L +//CP_CPC_STATUS +#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 +#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 +#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 +#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 +#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 +#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 +#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 +#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 +#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa +#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb +#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc +#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd +#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe +#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d +#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e +#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f +#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L +#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L +#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L +#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L +#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L +#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L +#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L +#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L +#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L +#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L +#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L +#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L +#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L +#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L +#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L +#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L +//CP_CPC_BUSY_STAT +#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 +#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1 +#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 +#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 +#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 +#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 +#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 +#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 +#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 +#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 +#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa +#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb +#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc +#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd +#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 +#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11 +#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 +#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 +#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 +#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 +#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 +#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 +#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 +#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 +#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a +#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b +#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c +#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d +#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L +#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L +#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L +#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L +#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L +#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L +#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L +#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L +#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L +#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L +#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L +#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L +#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L +#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L +#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L +#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L +#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L +#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L +#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L +#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L +#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L +#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L +#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L +#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L +//CP_CPC_STALLED_STAT1 +#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 +#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 +#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 +#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd +#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16 +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17 +#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18 +#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L +#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L +#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L +#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L +#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L +#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L +//CP_CPF_STATUS +#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 +#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 +#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 +#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 +#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 +#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 +#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 +#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 +#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa +#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb +#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc +#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd +#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe +#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf +#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10 +#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11 +#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a +#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b +#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c +#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e +#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f +#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L +#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L +#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L +#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L +#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L +#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L +#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L +#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L +#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L +#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L +#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L +#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L +#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L +#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L +#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L +#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L +#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L +#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L +#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L +#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L +#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L +//CP_CPF_BUSY_STAT +#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 +#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 +#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 +#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 +#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 +#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9 +#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb +#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc +#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd +#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe +#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf +#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10 +#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 +#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 +#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 +#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 +#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 +#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 +#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 +#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 +#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 +#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a +#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b +#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c +#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d +#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e +#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f +#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L +#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L +#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L +#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L +#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L +#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L +#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L +#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L +#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L +#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x00000200L +#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L +#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L +#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L +#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L +#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L +#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L +#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L +#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L +#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L +#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L +#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L +#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L +#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L +#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L +#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L +#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L +//CP_CPF_STALLED_STAT1 +#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 +#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 +#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 +#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7 +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8 +#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9 +#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa +#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb +#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L +#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L +#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L +#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L +#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L +#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L +#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L +//CP_CPC_GRBM_FREE_COUNT +#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL +//CP_CPC_PRIV_VIOLATION_ADDR +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_STATUS__SHIFT 0x0 +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_OP__SHIFT 0x1 +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT 0x2 +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_APERTURE_ID__SHIFT 0x14 +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_STATUS_MASK 0x00000001L +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_OP_MASK 0x00000002L +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK 0x000FFFFCL +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_APERTURE_ID_MASK 0xFFF00000L +//CP_MEC_CNTL +#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 +#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10 +#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11 +#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12 +#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13 +#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14 +#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15 +#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c +#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d +#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e +#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f +#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L +#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L +#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L +#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L +#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L +#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L +#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L +#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L +#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L +#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L +#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L +//CP_MEC_ME1_HEADER_DUMP +#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_MEC_ME2_HEADER_DUMP +#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_CPC_SCRATCH_INDEX +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000003FFL +//CP_CPC_SCRATCH_DATA +#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL +//CP_CPF_GRBM_FREE_COUNT +#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L +//CP_CPC_HALT_HYST_COUNT +#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 +#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL +//CP_CE_COMPARE_COUNT +#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0 +#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL +//CP_CE_DE_COUNT +#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 +#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL +//CP_DE_CE_COUNT +#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0 +#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL +//CP_DE_LAST_INVAL_COUNT +#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0 +#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL +//CP_DE_DE_COUNT +#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 +#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL +//CP_STALLED_STAT3 +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf +#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10 +#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11 +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12 +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13 +#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14 +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L +#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L +#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L +#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L +//CP_STALLED_STAT1 +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2 +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4 +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd +#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L +#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L +//CP_STALLED_STAT2 +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15 +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16 +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L +//CP_BUSY_STAT +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 +#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 +#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 +#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 +#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa +#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc +#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd +#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf +#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 +#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 +#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 +#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 +#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 +#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L +#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L +#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L +#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L +#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L +#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L +#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L +#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L +#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L +#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L +#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L +#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L +#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L +#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L +//CP_STAT +#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 +#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa +#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb +#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc +#define CP_STAT__DC_BUSY__SHIFT 0xd +#define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe +#define CP_STAT__PFP_BUSY__SHIFT 0xf +#define CP_STAT__MEQ_BUSY__SHIFT 0x10 +#define CP_STAT__ME_BUSY__SHIFT 0x11 +#define CP_STAT__QUERY_BUSY__SHIFT 0x12 +#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13 +#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 +#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 +#define CP_STAT__DMA_BUSY__SHIFT 0x16 +#define CP_STAT__RCIU_BUSY__SHIFT 0x17 +#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 +#define CP_STAT__CE_BUSY__SHIFT 0x1a +#define CP_STAT__TCIU_BUSY__SHIFT 0x1b +#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e +#define CP_STAT__CP_BUSY__SHIFT 0x1f +#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L +#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L +#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L +#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L +#define CP_STAT__DC_BUSY_MASK 0x00002000L +#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L +#define CP_STAT__PFP_BUSY_MASK 0x00008000L +#define CP_STAT__MEQ_BUSY_MASK 0x00010000L +#define CP_STAT__ME_BUSY_MASK 0x00020000L +#define CP_STAT__QUERY_BUSY_MASK 0x00040000L +#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L +#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L +#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L +#define CP_STAT__DMA_BUSY_MASK 0x00400000L +#define CP_STAT__RCIU_BUSY_MASK 0x00800000L +#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L +#define CP_STAT__CE_BUSY_MASK 0x04000000L +#define CP_STAT__TCIU_BUSY_MASK 0x08000000L +#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L +#define CP_STAT__CP_BUSY_MASK 0x80000000L +//CP_ME_HEADER_DUMP +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0 +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_PFP_HEADER_DUMP +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0 +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_GRBM_FREE_COUNT +#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL +#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L +//CP_CE_HEADER_DUMP +#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0 +#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_PFP_INSTR_PNTR +#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_ME_INSTR_PNTR +#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_CE_INSTR_PNTR +#define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_MEC1_INSTR_PNTR +#define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_MEC2_INSTR_PNTR +#define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_CSF_STAT +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L +//CP_ME_CNTL +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 +#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10 +#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11 +#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12 +#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13 +#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14 +#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15 +#define CP_ME_CNTL__CE_HALT__SHIFT 0x18 +#define CP_ME_CNTL__CE_STEP__SHIFT 0x19 +#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a +#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b +#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c +#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L +#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L +#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L +#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L +#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L +#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L +#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L +#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L +#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L +#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L +#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L +#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L +#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L +//CP_CNTX_STAT +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L +//CP_ME_PREEMPTION +#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0 +#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L +//CP_ROQ_THRESHOLDS +#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0 +#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8 +#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL +#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L +//CP_MEQ_STQ_THRESHOLD +#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0 +#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL +//CP_RB2_RPTR +#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_RB1_RPTR +#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_RB0_RPTR +#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L +//CP_RB_WPTR_POLL_CNTL +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//CP_ROQ1_THRESHOLDS +#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 +#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8 +#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10 +#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18 +#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000FFL +#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000FF00L +#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00FF0000L +#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xFF000000L +//CP_ROQ2_THRESHOLDS +#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0 +#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8 +#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10 +#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18 +#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000FFL +#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000FF00L +#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00FF0000L +#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xFF000000L +//CP_STQ_THRESHOLDS +#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 +#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 +#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 +#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL +#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L +#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L +//CP_QUEUE_THRESHOLDS +#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0 +#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8 +#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL +#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L +//CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 +#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 +#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL +#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L +//CP_ROQ_AVAIL +#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 +#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 +#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007FFL +#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07FF0000L +//CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 +#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL +//CP_ROQ2_AVAIL +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007FFL +//CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 +#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL +//CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 +#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc +#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 +#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL +#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L +#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L +//CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 +#define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL +//CP_ROQ_RB_STAT +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003FFL +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03FF0000L +//CP_ROQ_IB1_STAT +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003FFL +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03FF0000L +//CP_ROQ_IB2_STAT +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003FFL +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03FF0000L +//CP_STQ_STAT +#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 +#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL +//CP_STQ_WR_STAT +#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 +#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL +//CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 +#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 +#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL +#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L +//CP_CEQ1_AVAIL +#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0 +#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10 +#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007FFL +#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07FF0000L +//CP_CEQ2_AVAIL +#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0 +#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007FFL +//CP_CE_ROQ_RB_STAT +#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0 +#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10 +#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003FFL +#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03FF0000L +//CP_CE_ROQ_IB1_STAT +#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0 +#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10 +#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003FFL +#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03FF0000L +//CP_CE_ROQ_IB2_STAT +#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0 +#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10 +#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003FFL +#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03FF0000L +//CP_INT_STAT_DEBUG +#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb +#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe +#define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10 +#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 +#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12 +#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13 +#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14 +#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15 +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16 +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 +#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a +#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b +#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d +#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e +#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f +#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x00000800L +#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L +#define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L +#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L +#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x00040000L +#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x00080000L +#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x00100000L +#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x00200000L +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L +#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L +#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L +#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L +#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L +#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L +#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L +//CP_DEBUG_CNTL +#define CP_DEBUG_CNTL__DEBUG_INDX__SHIFT 0x0 +#define CP_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS__SHIFT 0x10 +#define CP_DEBUG_CNTL__DEBUG_BUS_FLOP_EN__SHIFT 0x1f +#define CP_DEBUG_CNTL__DEBUG_INDX_MASK 0x0000007FL +#define CP_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS_MASK 0x003F0000L +#define CP_DEBUG_CNTL__DEBUG_BUS_FLOP_EN_MASK 0x80000000L +//CP_PRIV_VIOLATION_ADDR +#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT 0x0 +#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK 0x0000FFFFL + + +// addressBlock: xcd0_gc_padec +//VGT_VTX_VECT_EJECT_REG +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0 +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000007FL +//VGT_DMA_DATA_FIFO_DEPTH +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x9 +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001FFL +#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x0007FE00L +//VGT_DMA_REQ_FIFO_DEPTH +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL +//VGT_DRAW_INIT_FIFO_DEPTH +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL +//VGT_LAST_COPY_STATE +#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 +#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10 +#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L +#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L +//VGT_CACHE_INVALIDATION +#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0 +#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4 +#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5 +#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6 +#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9 +#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb +#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc +#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd +#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10 +#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15 +#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16 +#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19 +#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c +#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d +#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L +#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L +#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L +#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L +#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L +#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L +#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L +#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L +#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L +#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L +#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L +#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L +#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L +#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L +//VGT_RESET_DEBUG +#define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0 +#define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1 +#define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2 +#define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x00000001L +#define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x00000002L +#define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x00000004L +//VGT_STRMOUT_DELAY +#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0 +#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8 +#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb +#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe +#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11 +#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL +#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L +#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L +#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L +#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L +//VGT_FIFO_DEPTHS +#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0 +#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7 +#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8 +#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16 +#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL +#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L +#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L +#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x0FC00000L +//VGT_GS_VERTEX_REUSE +#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0 +#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL +//VGT_MC_LAT_CNTL +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL +//IA_CNTL_STATUS +#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0 +#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1 +#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2 +#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3 +#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4 +#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L +#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L +#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L +#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L +#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L +//VGT_CNTL_STATUS +#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0 +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1 +#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2 +#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3 +#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4 +#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5 +#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6 +#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7 +#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8 +#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9 +#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa +#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L +#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L +#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L +#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L +#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L +#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L +#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L +#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L +#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L +//WD_CNTL_STATUS +#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0 +#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1 +#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2 +#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3 +#define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L +#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L +#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L +#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L +//CC_GC_PRIM_CONFIG +#define CC_GC_PRIM_CONFIG__WRITE_DIS__SHIFT 0x0 +#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 +#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 +#define CC_GC_PRIM_CONFIG__WRITE_DIS_MASK 0x00000001L +#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L +#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L +//GC_USER_PRIM_CONFIG +#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 +#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 +#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L +#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L +//WD_QOS +#define WD_QOS__DRAW_STALL__SHIFT 0x0 +#define WD_QOS__DRAW_STALL_MASK 0x00000001L +//WD_UTCL1_CNTL +#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +//WD_UTCL1_STATUS +#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//IA_UTCL1_CNTL +#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d +#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L +//IA_UTCL1_STATUS +#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//VGT_SYS_CONFIG +#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0 +#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1 +#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7 +#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L +#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL +#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L +//VGT_VS_MAX_WAVE_ID +#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL +//VGT_GS_MAX_WAVE_ID +#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL +//GFX_PIPE_CONTROL +#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 +#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 +#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL +#define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L +//CC_GC_SHADER_ARRAY_CONFIG +#define CC_GC_SHADER_ARRAY_CONFIG__WRITE_DIS__SHIFT 0x0 +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 +#define CC_GC_SHADER_ARRAY_CONFIG__WRITE_DIS_MASK 0x00000001L +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L +//GC_USER_SHADER_ARRAY_CONFIG +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L +//VGT_DMA_PRIMITIVE_TYPE +#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 +#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL +//VGT_DMA_CONTROL +#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0 +#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11 +#define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13 +#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14 +#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT 0x15 +#define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT 0x16 +#define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT 0x17 +#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL +#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L +#define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L +#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L +#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK 0x00200000L +#define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK 0x00400000L +#define VGT_DMA_CONTROL__HW_USE_ONLY_MASK 0x00800000L +//VGT_DMA_LS_HS_CONFIG +#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 +#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L +//WD_BUF_RESOURCE_1 +#define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0 +#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10 +#define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL +#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L +//WD_BUF_RESOURCE_2 +#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0 +#define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf +#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10 +#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL +#define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L +#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L +//PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0 +#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1 +#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2 +#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L +#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L +#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L +//PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 +#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 +#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5 +#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6 +#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7 +#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8 +#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9 +#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb +#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc +#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe +#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT 0x11 +#define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT__SHIFT 0x12 +#define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET__SHIFT 0x13 +#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT 0x14 +#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT 0x15 +#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c +#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d +#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e +#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L +#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L +#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x00000020L +#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L +#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L +#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L +#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L +#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L +#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L +#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L +#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK 0x00020000L +#define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT_MASK 0x00040000L +#define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET_MASK 0x00080000L +#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK 0x00100000L +#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK 0x00200000L +#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L +//PA_CL_RESET_DEBUG +#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0 +#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x00000001L +//PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f +#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L +//PA_SC_FIFO_DEPTH_CNTL +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL +//PA_SC_P3D_TRAP_SCREEN_HV_LOCK +#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L +//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK +#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L +//PA_SC_TRAP_SCREEN_HV_LOCK +#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L +//PA_SC_FORCE_EOV_MAX_CNTS +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L +//PA_SC_BINNER_EVENT_CNTL_0 +#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L +//PA_SC_BINNER_EVENT_CNTL_1 +#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L +//PA_SC_BINNER_EVENT_CNTL_2 +#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L +//PA_SC_BINNER_EVENT_CNTL_3 +#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK 0xC0000000L +//PA_SC_BINNER_TIMEOUT_COUNTER +#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL +//PA_SC_BINNER_PERF_CNTL_0 +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14 +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17 +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L +//PA_SC_BINNER_PERF_CNTL_1 +#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5 +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa +#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L +//PA_SC_BINNER_PERF_CNTL_2 +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L +//PA_SC_BINNER_PERF_CNTL_3 +#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL +//PA_SC_ENHANCE_2 +#define PA_SC_ENHANCE_2__RESERVED_0__SHIFT 0x0 +#define PA_SC_ENHANCE_2__RESERVED_1__SHIFT 0x1 +#define PA_SC_ENHANCE_2__RESERVED_2__SHIFT 0x2 +#define PA_SC_ENHANCE_2__RESERVED_3__SHIFT 0x3 +#define PA_SC_ENHANCE_2__RESERVED_4__SHIFT 0x4 +#define PA_SC_ENHANCE_2__RESERVED_5__SHIFT 0x5 +#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN__SHIFT 0x6 +#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PIPELINE_PRIMID__SHIFT 0x7 +#define PA_SC_ENHANCE_2__RSVD__SHIFT 0x8 +#define PA_SC_ENHANCE_2__RESERVED_0_MASK 0x00000001L +#define PA_SC_ENHANCE_2__RESERVED_1_MASK 0x00000002L +#define PA_SC_ENHANCE_2__RESERVED_2_MASK 0x00000004L +#define PA_SC_ENHANCE_2__RESERVED_3_MASK 0x00000008L +#define PA_SC_ENHANCE_2__RESERVED_4_MASK 0x00000010L +#define PA_SC_ENHANCE_2__RESERVED_5_MASK 0x00000020L +#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN_MASK 0x00000040L +#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PIPELINE_PRIMID_MASK 0x00000080L +#define PA_SC_ENHANCE_2__RSVD_MASK 0xFFFFFF00L +//PA_SC_FIFO_SIZE +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15 +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L +//PA_SC_IF_FIFO_SIZE +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L +//PA_SC_PKR_WAVE_TABLE_CNTL +#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0 +#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL +//PA_UTCL1_CNTL1 +#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 +#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define PA_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 +#define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define PA_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 +#define PA_UTCL1_CNTL1__SPARE__SHIFT 0x10 +#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 +#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 +#define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 +#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 +#define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 +#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT 0x19 +#define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a +#define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L +#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define PA_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L +#define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define PA_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L +#define PA_UTCL1_CNTL1__SPARE_MASK 0x00010000L +#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L +#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L +#define PA_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L +#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L +#define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L +#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK 0x02000000L +#define PA_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L +#define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//PA_UTCL1_CNTL2 +#define PA_UTCL1_CNTL2__SPARE1__SHIFT 0x0 +#define PA_UTCL1_CNTL2__SPARE2__SHIFT 0x8 +#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define PA_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa +#define PA_UTCL1_CNTL2__SPARE3__SHIFT 0xb +#define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc +#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT 0xd +#define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf +#define PA_UTCL1_CNTL2__SPARE4__SHIFT 0x10 +#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 +#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 +#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 +#define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 +#define PA_UTCL1_CNTL2__SPARE5__SHIFT 0x19 +#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define PA_UTCL1_CNTL2__RESERVED__SHIFT 0x1b +#define PA_UTCL1_CNTL2__SPARE1_MASK 0x000000FFL +#define PA_UTCL1_CNTL2__SPARE2_MASK 0x00000100L +#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define PA_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L +#define PA_UTCL1_CNTL2__SPARE3_MASK 0x00000800L +#define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L +#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK 0x00002000L +#define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L +#define PA_UTCL1_CNTL2__SPARE4_MASK 0x00030000L +#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L +#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L +#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L +#define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L +#define PA_UTCL1_CNTL2__SPARE5_MASK 0x02000000L +#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +#define PA_UTCL1_CNTL2__RESERVED_MASK 0xF8000000L +//PA_SIDEBAND_REQUEST_DELAYS +#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0 +#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10 +#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL +#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L +//PA_SC_ENHANCE +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6 +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16 +#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17 +#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 +#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19 +#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a +#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b +#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c +#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L +#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L +#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L +#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L +#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L +#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L +#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L +#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L +//PA_SC_ENHANCE_1 +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0 +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1 +#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3 +#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4 +#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5 +#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6 +#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7 +#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8 +#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9 +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa +#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb +#define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK__SHIFT 0xc +#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xd +#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe +#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf +#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10 +#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x11 +#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12 +#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13 +#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14 +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15 +#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16 +#define PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT 0x17 +#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 +#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT 0x19 +#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1a +#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT 0x1b +#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT 0x1c +#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT 0x1d +#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT 0x1e +#define PA_SC_ENHANCE_1__RSVD__SHIFT 0x1f +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L +#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L +#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L +#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L +#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L +#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L +#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L +#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L +#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L +#define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK_MASK 0x00001000L +#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00002000L +#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L +#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L +#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L +#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L +#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L +#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L +#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L +#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L +#define PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK 0x00800000L +#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L +#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK 0x02000000L +#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK 0x04000000L +#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK 0x08000000L +#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK 0x10000000L +#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK 0x20000000L +#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK 0x40000000L +#define PA_SC_ENHANCE_1__RSVD_MASK 0x80000000L +//PA_SC_DSM_CNTL +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1 +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L +//PA_SC_TILE_STEERING_CREST_OVERRIDE +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0 +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1 +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5 +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L + + +// addressBlock: xcd0_gc_sqdec +//SQ_CONFIG +#define SQ_CONFIG__DISABLE_BARRIER_WAITCNT__SHIFT 0x0 +#define SQ_CONFIG__DISABLE_REPEATER_FGCG_CLOCK_GATING__SHIFT 0x1 +#define SQ_CONFIG__DISABLE_SPIPRIO_OVER_USERPRIO__SHIFT 0x2 +#define SQ_CONFIG__OVERRIDE_SP_MAI_ALU_BUSY__SHIFT 0x3 +#define SQ_CONFIG__DISABLE_RAM_CLOCK_GATING__SHIFT 0x4 +#define SQ_CONFIG__DISABLE_MAI_CO_EXEC__SHIFT 0x5 +#define SQ_CONFIG__OVERRIDE_MAI_ALU_BUSY__SHIFT 0x6 +#define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT 0x7 +#define SQ_CONFIG__DEBUG_EN__SHIFT 0x8 +#define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT 0x9 +#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT 0xa +#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0xb +#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc +#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd +#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe +#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf +#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10 +#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11 +#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12 +#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13 +#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15 +#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT 0x1c +#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d +#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT 0x1e +#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT 0x1f +#define SQ_CONFIG__DISABLE_BARRIER_WAITCNT_MASK 0x00000001L +#define SQ_CONFIG__DISABLE_REPEATER_FGCG_CLOCK_GATING_MASK 0x00000002L +#define SQ_CONFIG__DISABLE_SPIPRIO_OVER_USERPRIO_MASK 0x00000004L +#define SQ_CONFIG__OVERRIDE_SP_MAI_ALU_BUSY_MASK 0x00000008L +#define SQ_CONFIG__DISABLE_RAM_CLOCK_GATING_MASK 0x00000010L +#define SQ_CONFIG__DISABLE_MAI_CO_EXEC_MASK 0x00000020L +#define SQ_CONFIG__OVERRIDE_MAI_ALU_BUSY_MASK 0x00000040L +#define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK 0x00000080L +#define SQ_CONFIG__DEBUG_EN_MASK 0x00000100L +#define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK 0x00000200L +#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK 0x00000400L +#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L +#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L +#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L +#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L +#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L +#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x00010000L +#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x00020000L +#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L +#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L +#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0FE00000L +#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK 0x10000000L +#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L +#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK 0x40000000L +#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK 0x80000000L +//SQC_CONFIG +#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 +#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 +#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 +#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 +#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 +#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 +#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9 +#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa +#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb +#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc +#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe +#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf +#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10 +#define SQC_CONFIG__INST_PRF_COUNT__SHIFT 0x18 +#define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT 0x1d +#define SQC_CONFIG__DISABLE_PREFETCH_CROSS_4K_BOUNDARY_CHECK__SHIFT 0x1e +#define SQC_CONFIG__MEM_LS_DISABLE__SHIFT 0x1f +#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L +#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL +#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L +#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L +#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L +#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L +#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L +#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L +#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L +#define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L +#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L +#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L +#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L +#define SQC_CONFIG__INST_PRF_COUNT_MASK 0x1F000000L +#define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK 0x20000000L +#define SQC_CONFIG__DISABLE_PREFETCH_CROSS_4K_BOUNDARY_CHECK_MASK 0x40000000L +#define SQC_CONFIG__MEM_LS_DISABLE_MASK 0x80000000L +//LDS_CONFIG +#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0 +#define LDS_CONFIG__TMZ_VIOLATION_REPORTING__SHIFT 0x1 +#define LDS_CONFIG__DISABLE_RAM_CLOCK_GATING__SHIFT 0x2 +#define LDS_CONFIG__DISABLE_IDXCLK_MGCG__SHIFT 0x3 +#define LDS_CONFIG__DISABLE_MEMCLK_MGCG__SHIFT 0x4 +#define LDS_CONFIG__DISABLE_ATTRCLK_MGCG__SHIFT 0x5 +#define LDS_CONFIG__DISABLE_ATODFPCLK_MGCG__SHIFT 0x6 +#define LDS_CONFIG__DISABLE_PHASE_FGCG__SHIFT 0x7 +#define LDS_CONFIG__DISABLE_LDS_SP_READ_FGCG__SHIFT 0x8 +#define LDS_CONFIG__DISABLE_SP_DATA_CLOCK_GATING__SHIFT 0x9 +#define LDS_CONFIG__DISABLE_TD_DATA_CLOCK_GATING__SHIFT 0xa +#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L +#define LDS_CONFIG__TMZ_VIOLATION_REPORTING_MASK 0x00000002L +#define LDS_CONFIG__DISABLE_RAM_CLOCK_GATING_MASK 0x00000004L +#define LDS_CONFIG__DISABLE_IDXCLK_MGCG_MASK 0x00000008L +#define LDS_CONFIG__DISABLE_MEMCLK_MGCG_MASK 0x00000010L +#define LDS_CONFIG__DISABLE_ATTRCLK_MGCG_MASK 0x00000020L +#define LDS_CONFIG__DISABLE_ATODFPCLK_MGCG_MASK 0x00000040L +#define LDS_CONFIG__DISABLE_PHASE_FGCG_MASK 0x00000080L +#define LDS_CONFIG__DISABLE_LDS_SP_READ_FGCG_MASK 0x00000100L +#define LDS_CONFIG__DISABLE_SP_DATA_CLOCK_GATING_MASK 0x00000200L +#define LDS_CONFIG__DISABLE_TD_DATA_CLOCK_GATING_MASK 0x00000400L +//SQ_RANDOM_WAVE_PRI +#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 +#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 +#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa +#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL +#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L +#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x007FFC00L +//SQ_REG_CREDITS +#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0 +#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8 +#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c +#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d +#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e +#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f +#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003FL +#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000F00L +#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L +#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L +#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L +#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L +//SQ_FIFO_SIZES +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 +#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10 +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000F00L +#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L +//SQ_DSM_CNTL +#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0 +#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1 +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2 +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3 +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8 +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9 +#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11 +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14 +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15 +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18 +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19 +#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a +#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L +#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L +#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L +#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L +//SQ_DSM_CNTL2 +#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5 +#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8 +#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb +#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe +#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14 +#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a +#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L +#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L +#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L +#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L +#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L +#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L +//SQ_RUNTIME_CONFIG +#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT 0x0 +#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK 0x00000001L +//SQ_DEBUG_STS_GLOBAL +#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x1 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x4 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x10 +#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0x0000FFF0L +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0x0FFF0000L +//SH_MEM_BASES +#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0 +#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 +#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL +#define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L +//SQ_TIMEOUT_CONFIG +#define SQ_TIMEOUT_CONFIG__PERIOD_SEL__SHIFT 0x0 +#define SQ_TIMEOUT_CONFIG__TIMEOUT_FATAL_DISABLE__SHIFT 0x6 +#define SQ_TIMEOUT_CONFIG__TIMER_LONGER_SEL__SHIFT 0x7 +#define SQ_TIMEOUT_CONFIG__TIMEOUT_CONDITIONS_MASK__SHIFT 0x8 +#define SQ_TIMEOUT_CONFIG__PERIOD_SEL_MASK 0x0000003FL +#define SQ_TIMEOUT_CONFIG__TIMEOUT_FATAL_DISABLE_MASK 0x00000040L +#define SQ_TIMEOUT_CONFIG__TIMER_LONGER_SEL_MASK 0x00000080L +#define SQ_TIMEOUT_CONFIG__TIMEOUT_CONDITIONS_MASK_MASK 0x07FFFF00L +//SQ_TIMEOUT_STATUS +#define SQ_TIMEOUT_STATUS__WAVE_TIMEOUT__SHIFT 0x0 +#define SQ_TIMEOUT_STATUS__WAVE_TIMEOUT_MASK 0xFFFFFFFFL +//SH_MEM_CONFIG +#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0 +#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3 +#define SH_MEM_CONFIG__F8_MODE__SHIFT 0x8 +#define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT 0xc +#define SH_MEM_CONFIG__PRIVATE_NV__SHIFT 0xd +#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L +#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x00000018L +#define SH_MEM_CONFIG__F8_MODE_MASK 0x00000100L +#define SH_MEM_CONFIG__RETRY_DISABLE_MASK 0x00001000L +#define SH_MEM_CONFIG__PRIVATE_NV_MASK 0x00002000L +//SP_MFMA_PORTD_RD_CONFIG +#define SP_MFMA_PORTD_RD_CONFIG__SET__SHIFT 0x0 +#define SP_MFMA_PORTD_RD_CONFIG__TYPE__SHIFT 0x1 +#define SP_MFMA_PORTD_RD_CONFIG__LAST_PASS__SHIFT 0x4 +#define SP_MFMA_PORTD_RD_CONFIG__PORTD_PATTERN__SHIFT 0x9 +#define SP_MFMA_PORTD_RD_CONFIG__SET_MASK 0x00000001L +#define SP_MFMA_PORTD_RD_CONFIG__TYPE_MASK 0x0000000EL +#define SP_MFMA_PORTD_RD_CONFIG__LAST_PASS_MASK 0x000001F0L +#define SP_MFMA_PORTD_RD_CONFIG__PORTD_PATTERN_MASK 0x1FFFFE00L +//SH_CAC_CONFIG +#define SH_CAC_CONFIG__SQG_UTCL1_REPEATER_FGCG_DISABLE__SHIFT 0x0 +#define SH_CAC_CONFIG__SQC_UTCL1_REPEATER_FGCG_DISABLE__SHIFT 0x1 +#define SH_CAC_CONFIG__SPI_SQ_CMD_REPEATER_FGCG_DISABLE__SHIFT 0x2 +#define SH_CAC_CONFIG__SQ_MSG_REPEATER_FGCG_DISABLE__SHIFT 0x3 +#define SH_CAC_CONFIG__SQC_TC_REPEATER_FGCG_DISABLE__SHIFT 0x4 +#define SH_CAC_CONFIG__SQC_SQ_REPEATER_FGCG_DISABLE__SHIFT 0x5 +#define SH_CAC_CONFIG__SQG_TC_REPEATER_FGCG_DISABLE__SHIFT 0x6 +#define SH_CAC_CONFIG__SQC_DISABLE_RAM_CLOCK_GATING__SHIFT 0x8 +#define SH_CAC_CONFIG__SQG_DISABLE_RAM_CLOCK_GATING__SHIFT 0x9 +#define SH_CAC_CONFIG__SQC_MGCG_CLOCK_OFF_DELAY_CNT__SHIFT 0x10 +#define SH_CAC_CONFIG__SQC_MGCG_DISABLE__SHIFT 0x14 +#define SH_CAC_CONFIG__SQC_TC_REQ_CLKEN_CHICKENBIT__SHIFT 0x1c +#define SH_CAC_CONFIG__SQC_ICACHE_CTRL_MGCG_DISABLE__SHIFT 0x1d +#define SH_CAC_CONFIG__SQC_DCACHE_CTRL_MGCG_DISABLE__SHIFT 0x1e +#define SH_CAC_CONFIG__SQC_DISABLE_UTCL1_FGCG_PADDR__SHIFT 0x1f +#define SH_CAC_CONFIG__SQG_UTCL1_REPEATER_FGCG_DISABLE_MASK 0x00000001L +#define SH_CAC_CONFIG__SQC_UTCL1_REPEATER_FGCG_DISABLE_MASK 0x00000002L +#define SH_CAC_CONFIG__SPI_SQ_CMD_REPEATER_FGCG_DISABLE_MASK 0x00000004L +#define SH_CAC_CONFIG__SQ_MSG_REPEATER_FGCG_DISABLE_MASK 0x00000008L +#define SH_CAC_CONFIG__SQC_TC_REPEATER_FGCG_DISABLE_MASK 0x00000010L +#define SH_CAC_CONFIG__SQC_SQ_REPEATER_FGCG_DISABLE_MASK 0x00000020L +#define SH_CAC_CONFIG__SQG_TC_REPEATER_FGCG_DISABLE_MASK 0x00000040L +#define SH_CAC_CONFIG__SQC_DISABLE_RAM_CLOCK_GATING_MASK 0x00000100L +#define SH_CAC_CONFIG__SQG_DISABLE_RAM_CLOCK_GATING_MASK 0x00000200L +#define SH_CAC_CONFIG__SQC_MGCG_CLOCK_OFF_DELAY_CNT_MASK 0x000F0000L +#define SH_CAC_CONFIG__SQC_MGCG_DISABLE_MASK 0x0FF00000L +#define SH_CAC_CONFIG__SQC_TC_REQ_CLKEN_CHICKENBIT_MASK 0x10000000L +#define SH_CAC_CONFIG__SQC_ICACHE_CTRL_MGCG_DISABLE_MASK 0x20000000L +#define SH_CAC_CONFIG__SQC_DCACHE_CTRL_MGCG_DISABLE_MASK 0x40000000L +#define SH_CAC_CONFIG__SQC_DISABLE_UTCL1_FGCG_PADDR_MASK 0x80000000L +//SQ_DEBUG_STS_GLOBAL2 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x8 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x10 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x18 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000FFL +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000FF00L +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0x00FF0000L +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xFF000000L +//SQ_DEBUG_STS_GLOBAL3 +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x4 +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0x0000000FL +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x000003F0L +//CC_GC_SHADER_RATE_CONFIG +#define CC_GC_SHADER_RATE_CONFIG__WRITE_DIS__SHIFT 0x0 +#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 +#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 +#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 +#define CC_GC_SHADER_RATE_CONFIG__WRITE_DIS_MASK 0x00000001L +#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L +#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L +#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L +//GC_USER_SHADER_RATE_CONFIG +#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 +#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 +#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 +#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L +#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L +#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L +//SQ_INTERRUPT_AUTO_MASK +#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 +#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL +//SQ_INTERRUPT_MSG_CTRL +#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 +#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L +//SQ_DEBUG_PERFCOUNT_TRAP +#define SQ_DEBUG_PERFCOUNT_TRAP__ENABLE__SHIFT 0x0 +#define SQ_DEBUG_PERFCOUNT_TRAP__COUNTER__SHIFT 0x1 +#define SQ_DEBUG_PERFCOUNT_TRAP__LIMIT__SHIFT 0x4 +#define SQ_DEBUG_PERFCOUNT_TRAP__ENABLE_MASK 0x00000001L +#define SQ_DEBUG_PERFCOUNT_TRAP__COUNTER_MASK 0x0000000EL +#define SQ_DEBUG_PERFCOUNT_TRAP__LIMIT_MASK 0x0FFFFFF0L +//SQ_UTCL1_CNTL1 +#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 +#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 +#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define SQ_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 +#define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 +#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 +#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT 0x19 +#define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a +#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L +#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define SQ_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L +#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define SQ_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L +#define SQ_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L +#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L +#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L +#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK 0x02000000L +#define SQ_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L +#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//SQ_UTCL1_CNTL2 +#define SQ_UTCL1_CNTL2__SPARE__SHIFT 0x0 +#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 +#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa +#define SQ_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb +#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc +#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd +#define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf +#define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT 0x10 +#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT 0x1c +#define SQ_UTCL1_CNTL2__SPARE_MASK 0x000000FFL +#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L +#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define SQ_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L +#define SQ_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L +#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L +#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L +#define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L +#define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK 0x007F0000L +#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +#define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK 0xF0000000L +//SQ_UTCL1_STATUS +#define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define SQ_UTCL1_STATUS__RESERVED__SHIFT 0x3 +#define SQ_UTCL1_STATUS__UNUSED__SHIFT 0x10 +#define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define SQ_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define SQ_UTCL1_STATUS__RESERVED_MASK 0x0000FFF8L +#define SQ_UTCL1_STATUS__UNUSED_MASK 0xFFFF0000L +//SQ_FED_INTERRUPT_STATUS +#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_STATUS__SHIFT 0x0 +#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_SIMD_ID__SHIFT 0x2 +#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_WAVE_ID__SHIFT 0x4 +#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_CU_ID__SHIFT 0x8 +#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_VM_ID__SHIFT 0xc +#define SQ_FED_INTERRUPT_STATUS__TO_RSMU_DISABLE__SHIFT 0x10 +#define SQ_FED_INTERRUPT_STATUS__TO_IH_DISABLE__SHIFT 0x11 +#define SQ_FED_INTERRUPT_STATUS__FED_HALT_DISABLE__SHIFT 0x12 +#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_STATUS_MASK 0x00000001L +#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_SIMD_ID_MASK 0x0000000CL +#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_WAVE_ID_MASK 0x000000F0L +#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_CU_ID_MASK 0x00000F00L +#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_VM_ID_MASK 0x0000F000L +#define SQ_FED_INTERRUPT_STATUS__TO_RSMU_DISABLE_MASK 0x00010000L +#define SQ_FED_INTERRUPT_STATUS__TO_IH_DISABLE_MASK 0x00020000L +#define SQ_FED_INTERRUPT_STATUS__FED_HALT_DISABLE_MASK 0x00040000L +//SQ_CGTS_CONFIG +#define SQ_CGTS_CONFIG__DGEMM_EXTRA_BUSY_PASS__SHIFT 0x0 +#define SQ_CGTS_CONFIG__XDL_EXTRA_BUSY_PASS__SHIFT 0x4 +#define SQ_CGTS_CONFIG__VALU_EXTRA_BUSY_PASS__SHIFT 0x8 +#define SQ_CGTS_CONFIG__DLOP_EXTRA_BUSY_PASS__SHIFT 0xc +#define SQ_CGTS_CONFIG__XDL_EXTRA_GAP_PASS__SHIFT 0x10 +#define SQ_CGTS_CONFIG__DGEMM_EXTRA_GAP_PASS__SHIFT 0x12 +#define SQ_CGTS_CONFIG__DLOP_EXTRA_GAP_PASS__SHIFT 0x14 +#define SQ_CGTS_CONFIG__DGEMM_EXTRA_BUSY_PASS_MASK 0x0000000FL +#define SQ_CGTS_CONFIG__XDL_EXTRA_BUSY_PASS_MASK 0x000000F0L +#define SQ_CGTS_CONFIG__VALU_EXTRA_BUSY_PASS_MASK 0x00000F00L +#define SQ_CGTS_CONFIG__DLOP_EXTRA_BUSY_PASS_MASK 0x0000F000L +#define SQ_CGTS_CONFIG__XDL_EXTRA_GAP_PASS_MASK 0x00030000L +#define SQ_CGTS_CONFIG__DGEMM_EXTRA_GAP_PASS_MASK 0x000C0000L +#define SQ_CGTS_CONFIG__DLOP_EXTRA_GAP_PASS_MASK 0x00300000L +//SQ_SHADER_TBA_LO +#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0 +#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL +//SQ_SHADER_TBA_HI +#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0 +#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL +//SQ_SHADER_TMA_LO +#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0 +#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL +//SQ_SHADER_TMA_HI +#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0 +#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL +//SQC_DSM_CNTL +#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc +#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0xf +#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x18 +#define SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x1a +#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00800000L +#define SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x03000000L +#define SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x04000000L +//SQC_DSM_CNTLA +#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf +#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18 +#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a +#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L +#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L +//SQC_DSM_CNTLB +#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf +#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18 +#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a +#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L +#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L +//SQC_DSM_CNTL2 +#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x5 +#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x8 +#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0xb +#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc +#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xe +#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0xf +#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x11 +#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x14 +#define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000020L +#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L +#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000800L +#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L +#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00020000L +#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00100000L +#define SQC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//SQC_DSM_CNTL2A +#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5 +#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 +#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb +#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe +#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf +#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11 +#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14 +#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 +#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a +#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L +#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L +#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L +#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L +#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L +#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L +//SQC_DSM_CNTL2B +#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5 +#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 +#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb +#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe +#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf +#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11 +#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14 +#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 +#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a +#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L +#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L +#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L +#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L +#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L +#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L +//SQC_DSM_CNTL2E +#define SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x5 +#define SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000020L +//SQC_EDC_FUE_CNTL +#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0 +#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10 +#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL +#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L +//SQC_EDC_CNT2 +#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x0 +#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT 0x2 +#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0x4 +#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT 0x6 +#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x8 +#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT 0xa +#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0xc +#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT 0xe +#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x10 +#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT 0x12 +#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SEC_COUNT__SHIFT 0x14 +#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_DED_COUNT__SHIFT 0x16 +#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000003L +#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK 0x0000000CL +#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00000030L +#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK 0x000000C0L +#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000300L +#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK 0x00000C00L +#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00003000L +#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK 0x0000C000L +#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK 0x00030000L +#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK 0x000C0000L +#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SEC_COUNT_MASK 0x00300000L +#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_DED_COUNT_MASK 0x00C00000L +//SQC_EDC_CNT3 +#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x0 +#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT 0x2 +#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0x4 +#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT 0x6 +#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x8 +#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT 0xa +#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0xc +#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT 0xe +#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SEC_COUNT__SHIFT 0x10 +#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_DED_COUNT__SHIFT 0x12 +#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000003L +#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK 0x0000000CL +#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00000030L +#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK 0x000000C0L +#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000300L +#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK 0x00000C00L +#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00003000L +#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK 0x0000C000L +#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SEC_COUNT_MASK 0x00030000L +#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_DED_COUNT_MASK 0x000C0000L +//SQC_EDC_PARITY_CNT3 +#define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT__SHIFT 0x0 +#define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT__SHIFT 0x2 +#define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_SEC_COUNT__SHIFT 0x4 +#define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_DED_COUNT__SHIFT 0x6 +#define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_SEC_COUNT__SHIFT 0x8 +#define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_DED_COUNT__SHIFT 0xa +#define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_SEC_COUNT__SHIFT 0xc +#define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_DED_COUNT__SHIFT 0xe +#define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT__SHIFT 0x10 +#define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT__SHIFT 0x12 +#define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT__SHIFT 0x14 +#define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_DED_COUNT__SHIFT 0x16 +#define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_SEC_COUNT__SHIFT 0x18 +#define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_DED_COUNT__SHIFT 0x1a +#define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_SEC_COUNT__SHIFT 0x1c +#define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_DED_COUNT__SHIFT 0x1e +#define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT_MASK 0x00000003L +#define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT_MASK 0x0000000CL +#define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_SEC_COUNT_MASK 0x00000030L +#define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_DED_COUNT_MASK 0x000000C0L +#define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_SEC_COUNT_MASK 0x00000300L +#define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_DED_COUNT_MASK 0x00000C00L +#define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_SEC_COUNT_MASK 0x00003000L +#define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_DED_COUNT_MASK 0x0000C000L +#define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT_MASK 0x00030000L +#define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT_MASK 0x000C0000L +#define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT_MASK 0x00300000L +#define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_DED_COUNT_MASK 0x00C00000L +#define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_SEC_COUNT_MASK 0x03000000L +#define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_DED_COUNT_MASK 0x0C000000L +#define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_SEC_COUNT_MASK 0x30000000L +#define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_DED_COUNT_MASK 0xC0000000L +//SQ_DEBUG +#define SQ_DEBUG__SINGLE_MEMOP__SHIFT 0x0 +#define SQ_DEBUG__SINGLE_ALU_OP__SHIFT 0x1 +#define SQ_DEBUG__SINGLE_MEMOP_MASK 0x00000001L +#define SQ_DEBUG__SINGLE_ALU_OP_MASK 0x00000002L +//SQ_PERF_SNAPSHOT_CTRL +#define SQ_PERF_SNAPSHOT_CTRL__COUNT_INTVAL__SHIFT 0x0 +#define SQ_PERF_SNAPSHOT_CTRL__COUNT_SEL__SHIFT 0x5 +#define SQ_PERF_SNAPSHOT_CTRL__VMID_MASK__SHIFT 0x6 +#define SQ_PERF_SNAPSHOT_CTRL__ENABLE__SHIFT 0x16 +#define SQ_PERF_SNAPSHOT_CTRL__TEST_MODE__SHIFT 0x17 +#define SQ_PERF_SNAPSHOT_CTRL__COUNT_INTVAL_MASK 0x0000001FL +#define SQ_PERF_SNAPSHOT_CTRL__COUNT_SEL_MASK 0x00000020L +#define SQ_PERF_SNAPSHOT_CTRL__VMID_MASK_MASK 0x003FFFC0L +#define SQ_PERF_SNAPSHOT_CTRL__ENABLE_MASK 0x00400000L +#define SQ_PERF_SNAPSHOT_CTRL__TEST_MODE_MASK 0x00800000L +//SQ_DEBUG_FOR_INTERNAL_CTRL +#define SQ_DEBUG_FOR_INTERNAL_CTRL__FLAG_WR_ADDR_MATCH_FLAT_SCRATCH__SHIFT 0x0 +#define SQ_DEBUG_FOR_INTERNAL_CTRL__FLAG_RD_FLAT_SCRATCH_RETURN_ZERO__SHIFT 0x1 +#define SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_FLAT_SCRATCH_WRITE_PROTECT__SHIFT 0x2 +#define SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_FLAT_SCRATCH_READ_PROTECT__SHIFT 0x3 +#define SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_SNAPSHOT_TRAP_ON_BARRIER__SHIFT 0x4 +#define SQ_DEBUG_FOR_INTERNAL_CTRL__ENABLE_DED_TRIGGER_HALT__SHIFT 0x5 +#define SQ_DEBUG_FOR_INTERNAL_CTRL__FLAG_WR_ADDR_MATCH_FLAT_SCRATCH_MASK 0x00000001L +#define SQ_DEBUG_FOR_INTERNAL_CTRL__FLAG_RD_FLAT_SCRATCH_RETURN_ZERO_MASK 0x00000002L +#define SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_FLAT_SCRATCH_WRITE_PROTECT_MASK 0x00000004L +#define SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_FLAT_SCRATCH_READ_PROTECT_MASK 0x00000008L +#define SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_SNAPSHOT_TRAP_ON_BARRIER_MASK 0x00000010L +#define SQ_DEBUG_FOR_INTERNAL_CTRL__ENABLE_DED_TRIGGER_HALT_MASK 0x00000020L +//SQ_REG_TIMESTAMP +#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0 +#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL +//SQ_CMD_TIMESTAMP +#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0 +#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL +//SQ_HOSTTRAP_STATUS +#define SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT__SHIFT 0x0 +#define SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE__SHIFT 0x8 +#define SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT_MASK 0x000000FFL +#define SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE_MASK 0x00000100L +//SQ_IND_INDEX +#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 +#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 +#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6 +#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc +#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd +#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe +#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf +#define SQ_IND_INDEX__INDEX__SHIFT 0x10 +#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000FL +#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L +#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000FC0L +#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L +#define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L +#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L +#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L +#define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L +//SQ_IND_DATA +#define SQ_IND_DATA__DATA__SHIFT 0x0 +#define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL +//SQ_CONFIG1 +#define SQ_CONFIG1__DISABLE_XDL_PORTD_CO_EXEC__SHIFT 0x0 +#define SQ_CONFIG1__DISABLE_MGCG_ON_IBUF__SHIFT 0x1 +#define SQ_CONFIG1__DISABLE_MGCG_ON_PERF__SHIFT 0x2 +#define SQ_CONFIG1__DISABLE_MGCG_ON_EXP__SHIFT 0x3 +#define SQ_CONFIG1__DISABLE_MGCG_ON_SCA__SHIFT 0x4 +#define SQ_CONFIG1__DISABLE_MGCG_ON_SREG__SHIFT 0x5 +#define SQ_CONFIG1__DISABLE_MGCG_ON_VDEC__SHIFT 0x6 +#define SQ_CONFIG1__EXTRA_DGEMM_PROTECT_EN__SHIFT 0x7 +#define SQ_CONFIG1__DISABLE_VALU_COEXEC__SHIFT 0x8 +#define SQ_CONFIG1__DISABLE_WAVE_VALU_COEXEC__SHIFT 0x9 +#define SQ_CONFIG1__VGPR_ARB_PLUS1__SHIFT 0xa +#define SQ_CONFIG1__DISABLE_VGPR_COLLAPSE__SHIFT 0xb +#define SQ_CONFIG1__DISABLE_XNACK_CHECK_IN_RETRY_DISABLE__SHIFT 0xc +#define SQ_CONFIG1__DISABLE_BARRIER_ADDR_WATCH__SHIFT 0xd +#define SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_WAIT__SHIFT 0xe +#define SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_BACKOFF__SHIFT 0xf +#define SQ_CONFIG1__EXPAND_SP_CMD_FGCG__SHIFT 0x10 +#define SQ_CONFIG1__EXPAND_SP_EXPORT_FGCG__SHIFT 0x11 +#define SQ_CONFIG1__DISABLE_MGCG_ON_PERF_SNAP__SHIFT 0x12 +#define SQ_CONFIG1__DISABLE_VALU_COEXEC_MODE_AUTO_CLEAN__SHIFT 0x13 +#define SQ_CONFIG1__SP_CORE1_MGCG_OVERRIDE__SHIFT 0x14 +#define SQ_CONFIG1__SP_CORE4_MGCG_OVERRIDE__SHIFT 0x15 +#define SQ_CONFIG1__SP_CORE5_MGCG_OVERRIDE__SHIFT 0x16 +#define SQ_CONFIG1__DISABLE_SP_VGPR_COLLAPSE__SHIFT 0x17 +#define SQ_CONFIG1__SP_FGCG_REP_OVERRIDE__SHIFT 0x18 +#define SQ_CONFIG1__DPMACC_MGCG_OVERRIDE__SHIFT 0x19 +#define SQ_CONFIG1__XDLMACC_MGCG_OVERRIDE__SHIFT 0x1a +#define SQ_CONFIG1__TRANSMACC_MGCG_OVERRIDE__SHIFT 0x1b +#define SQ_CONFIG1__SPMACC_MGCG_OVERRIDE__SHIFT 0x1c +#define SQ_CONFIG1__DPMACC_DGEMM2X_MGCG_OVERRIDE__SHIFT 0x1d +#define SQ_CONFIG1__DISABLE_SP_VGPR_READ_SKIP__SHIFT 0x1e +#define SQ_CONFIG1__SP_SRC_1ST_BUFFER_MGCG_OVERRIDE__SHIFT 0x1f +#define SQ_CONFIG1__DISABLE_XDL_PORTD_CO_EXEC_MASK 0x00000001L +#define SQ_CONFIG1__DISABLE_MGCG_ON_IBUF_MASK 0x00000002L +#define SQ_CONFIG1__DISABLE_MGCG_ON_PERF_MASK 0x00000004L +#define SQ_CONFIG1__DISABLE_MGCG_ON_EXP_MASK 0x00000008L +#define SQ_CONFIG1__DISABLE_MGCG_ON_SCA_MASK 0x00000010L +#define SQ_CONFIG1__DISABLE_MGCG_ON_SREG_MASK 0x00000020L +#define SQ_CONFIG1__DISABLE_MGCG_ON_VDEC_MASK 0x00000040L +#define SQ_CONFIG1__EXTRA_DGEMM_PROTECT_EN_MASK 0x00000080L +#define SQ_CONFIG1__DISABLE_VALU_COEXEC_MASK 0x00000100L +#define SQ_CONFIG1__DISABLE_WAVE_VALU_COEXEC_MASK 0x00000200L +#define SQ_CONFIG1__VGPR_ARB_PLUS1_MASK 0x00000400L +#define SQ_CONFIG1__DISABLE_VGPR_COLLAPSE_MASK 0x00000800L +#define SQ_CONFIG1__DISABLE_XNACK_CHECK_IN_RETRY_DISABLE_MASK 0x00001000L +#define SQ_CONFIG1__DISABLE_BARRIER_ADDR_WATCH_MASK 0x00002000L +#define SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_WAIT_MASK 0x00004000L +#define SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_BACKOFF_MASK 0x00008000L +#define SQ_CONFIG1__EXPAND_SP_CMD_FGCG_MASK 0x00010000L +#define SQ_CONFIG1__EXPAND_SP_EXPORT_FGCG_MASK 0x00020000L +#define SQ_CONFIG1__DISABLE_MGCG_ON_PERF_SNAP_MASK 0x00040000L +#define SQ_CONFIG1__DISABLE_VALU_COEXEC_MODE_AUTO_CLEAN_MASK 0x00080000L +#define SQ_CONFIG1__SP_CORE1_MGCG_OVERRIDE_MASK 0x00100000L +#define SQ_CONFIG1__SP_CORE4_MGCG_OVERRIDE_MASK 0x00200000L +#define SQ_CONFIG1__SP_CORE5_MGCG_OVERRIDE_MASK 0x00400000L +#define SQ_CONFIG1__DISABLE_SP_VGPR_COLLAPSE_MASK 0x00800000L +#define SQ_CONFIG1__SP_FGCG_REP_OVERRIDE_MASK 0x01000000L +#define SQ_CONFIG1__DPMACC_MGCG_OVERRIDE_MASK 0x02000000L +#define SQ_CONFIG1__XDLMACC_MGCG_OVERRIDE_MASK 0x04000000L +#define SQ_CONFIG1__TRANSMACC_MGCG_OVERRIDE_MASK 0x08000000L +#define SQ_CONFIG1__SPMACC_MGCG_OVERRIDE_MASK 0x10000000L +#define SQ_CONFIG1__DPMACC_DGEMM2X_MGCG_OVERRIDE_MASK 0x20000000L +#define SQ_CONFIG1__DISABLE_SP_VGPR_READ_SKIP_MASK 0x40000000L +#define SQ_CONFIG1__SP_SRC_1ST_BUFFER_MGCG_OVERRIDE_MASK 0x80000000L +//SQ_CMD +#define SQ_CMD__CMD__SHIFT 0x0 +#define SQ_CMD__MODE__SHIFT 0x4 +#define SQ_CMD__CHECK_VMID__SHIFT 0x7 +#define SQ_CMD__DATA__SHIFT 0x8 +#define SQ_CMD__WAVE_ID__SHIFT 0x10 +#define SQ_CMD__SIMD_ID__SHIFT 0x14 +#define SQ_CMD__QUEUE_ID__SHIFT 0x18 +#define SQ_CMD__VM_ID__SHIFT 0x1c +#define SQ_CMD__CMD_MASK 0x00000007L +#define SQ_CMD__MODE_MASK 0x00000070L +#define SQ_CMD__CHECK_VMID_MASK 0x00000080L +#define SQ_CMD__DATA_MASK 0x00000F00L +#define SQ_CMD__WAVE_ID_MASK 0x000F0000L +#define SQ_CMD__SIMD_ID_MASK 0x00300000L +#define SQ_CMD__QUEUE_ID_MASK 0x07000000L +#define SQ_CMD__VM_ID_MASK 0xF0000000L +//SQ_TIME_HI +#define SQ_TIME_HI__TIME__SHIFT 0x0 +#define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL +//SQ_TIME_LO +#define SQ_TIME_LO__TIME__SHIFT 0x0 +#define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL +//SQ_DS_0 +#define SQ_DS_0__OFFSET0__SHIFT 0x0 +#define SQ_DS_0__OFFSET1__SHIFT 0x8 +#define SQ_DS_0__GDS__SHIFT 0x10 +#define SQ_DS_0__OP__SHIFT 0x11 +#define SQ_DS_0__ACC__SHIFT 0x19 +#define SQ_DS_0__ENCODING__SHIFT 0x1a +#define SQ_DS_0__OFFSET0_MASK 0x000000FFL +#define SQ_DS_0__OFFSET1_MASK 0x0000FF00L +#define SQ_DS_0__GDS_MASK 0x00010000L +#define SQ_DS_0__OP_MASK 0x01FE0000L +#define SQ_DS_0__ACC_MASK 0x02000000L +#define SQ_DS_0__ENCODING_MASK 0xFC000000L +//SQ_DS_1 +#define SQ_DS_1__ADDR__SHIFT 0x0 +#define SQ_DS_1__DATA0__SHIFT 0x8 +#define SQ_DS_1__DATA1__SHIFT 0x10 +#define SQ_DS_1__VDST__SHIFT 0x18 +#define SQ_DS_1__ADDR_MASK 0x000000FFL +#define SQ_DS_1__DATA0_MASK 0x0000FF00L +#define SQ_DS_1__DATA1_MASK 0x00FF0000L +#define SQ_DS_1__VDST_MASK 0xFF000000L +//SQ_EXP_0 +#define SQ_EXP_0__EN__SHIFT 0x0 +#define SQ_EXP_0__TGT__SHIFT 0x4 +#define SQ_EXP_0__COMPR__SHIFT 0xa +#define SQ_EXP_0__DONE__SHIFT 0xb +#define SQ_EXP_0__VM__SHIFT 0xc +#define SQ_EXP_0__ENCODING__SHIFT 0x1a +#define SQ_EXP_0__EN_MASK 0x0000000FL +#define SQ_EXP_0__TGT_MASK 0x000003F0L +#define SQ_EXP_0__COMPR_MASK 0x00000400L +#define SQ_EXP_0__DONE_MASK 0x00000800L +#define SQ_EXP_0__VM_MASK 0x00001000L +#define SQ_EXP_0__ENCODING_MASK 0xFC000000L +//SQ_EXP_1 +#define SQ_EXP_1__VSRC0__SHIFT 0x0 +#define SQ_EXP_1__VSRC1__SHIFT 0x8 +#define SQ_EXP_1__VSRC2__SHIFT 0x10 +#define SQ_EXP_1__VSRC3__SHIFT 0x18 +#define SQ_EXP_1__VSRC0_MASK 0x000000FFL +#define SQ_EXP_1__VSRC1_MASK 0x0000FF00L +#define SQ_EXP_1__VSRC2_MASK 0x00FF0000L +#define SQ_EXP_1__VSRC3_MASK 0xFF000000L +//SQ_FLAT_0 +#define SQ_FLAT_0__OFFSET__SHIFT 0x0 +#define SQ_FLAT_0__SVE__SHIFT 0xd +#define SQ_FLAT_0__SEG__SHIFT 0xe +#define SQ_FLAT_0__SC0__SHIFT 0x10 +#define SQ_FLAT_0__NT__SHIFT 0x11 +#define SQ_FLAT_0__OP__SHIFT 0x12 +#define SQ_FLAT_0__SC1__SHIFT 0x19 +#define SQ_FLAT_0__ENCODING__SHIFT 0x1a +#define SQ_FLAT_0__OFFSET_MASK 0x00000FFFL +#define SQ_FLAT_0__SVE_MASK 0x00002000L +#define SQ_FLAT_0__SEG_MASK 0x0000C000L +#define SQ_FLAT_0__SC0_MASK 0x00010000L +#define SQ_FLAT_0__NT_MASK 0x00020000L +#define SQ_FLAT_0__OP_MASK 0x01FC0000L +#define SQ_FLAT_0__SC1_MASK 0x02000000L +#define SQ_FLAT_0__ENCODING_MASK 0xFC000000L +//SQ_FLAT_1 +#define SQ_FLAT_1__ADDR__SHIFT 0x0 +#define SQ_FLAT_1__DATA__SHIFT 0x8 +#define SQ_FLAT_1__SADDR__SHIFT 0x10 +#define SQ_FLAT_1__ACC__SHIFT 0x17 +#define SQ_FLAT_1__VDST__SHIFT 0x18 +#define SQ_FLAT_1__ADDR_MASK 0x000000FFL +#define SQ_FLAT_1__DATA_MASK 0x0000FF00L +#define SQ_FLAT_1__SADDR_MASK 0x007F0000L +#define SQ_FLAT_1__ACC_MASK 0x00800000L +#define SQ_FLAT_1__VDST_MASK 0xFF000000L +//SQ_GLBL_0 +#define SQ_GLBL_0__OFFSET__SHIFT 0x0 +#define SQ_GLBL_0__SVE__SHIFT 0xd +#define SQ_GLBL_0__SEG__SHIFT 0xe +#define SQ_GLBL_0__SC0__SHIFT 0x10 +#define SQ_GLBL_0__NT__SHIFT 0x11 +#define SQ_GLBL_0__OP__SHIFT 0x12 +#define SQ_GLBL_0__SC1__SHIFT 0x19 +#define SQ_GLBL_0__ENCODING__SHIFT 0x1a +#define SQ_GLBL_0__OFFSET_MASK 0x00001FFFL +#define SQ_GLBL_0__SVE_MASK 0x00002000L +#define SQ_GLBL_0__SEG_MASK 0x0000C000L +#define SQ_GLBL_0__SC0_MASK 0x00010000L +#define SQ_GLBL_0__NT_MASK 0x00020000L +#define SQ_GLBL_0__OP_MASK 0x01FC0000L +#define SQ_GLBL_0__SC1_MASK 0x02000000L +#define SQ_GLBL_0__ENCODING_MASK 0xFC000000L +//SQ_GLBL_1 +#define SQ_GLBL_1__ADDR__SHIFT 0x0 +#define SQ_GLBL_1__DATA__SHIFT 0x8 +#define SQ_GLBL_1__SADDR__SHIFT 0x10 +#define SQ_GLBL_1__ACC__SHIFT 0x17 +#define SQ_GLBL_1__VDST__SHIFT 0x18 +#define SQ_GLBL_1__ADDR_MASK 0x000000FFL +#define SQ_GLBL_1__DATA_MASK 0x0000FF00L +#define SQ_GLBL_1__SADDR_MASK 0x007F0000L +#define SQ_GLBL_1__ACC_MASK 0x00800000L +#define SQ_GLBL_1__VDST_MASK 0xFF000000L +//SQ_INST +#define SQ_INST__ENCODING__SHIFT 0x0 +#define SQ_INST__ENCODING_MASK 0xFFFFFFFFL +//SQ_MIMG_0 +#define SQ_MIMG_0__OPM__SHIFT 0x0 +#define SQ_MIMG_0__SC1__SHIFT 0x7 +#define SQ_MIMG_0__DMASK__SHIFT 0x8 +#define SQ_MIMG_0__UNORM__SHIFT 0xc +#define SQ_MIMG_0__SC0__SHIFT 0xd +#define SQ_MIMG_0__DA__SHIFT 0xe +#define SQ_MIMG_0__A16__SHIFT 0xf +#define SQ_MIMG_0__ACC__SHIFT 0x10 +#define SQ_MIMG_0__LWE__SHIFT 0x11 +#define SQ_MIMG_0__OP__SHIFT 0x12 +#define SQ_MIMG_0__NT__SHIFT 0x19 +#define SQ_MIMG_0__ENCODING__SHIFT 0x1a +#define SQ_MIMG_0__OPM_MASK 0x00000001L +#define SQ_MIMG_0__SC1_MASK 0x00000080L +#define SQ_MIMG_0__DMASK_MASK 0x00000F00L +#define SQ_MIMG_0__UNORM_MASK 0x00001000L +#define SQ_MIMG_0__SC0_MASK 0x00002000L +#define SQ_MIMG_0__DA_MASK 0x00004000L +#define SQ_MIMG_0__A16_MASK 0x00008000L +#define SQ_MIMG_0__ACC_MASK 0x00010000L +#define SQ_MIMG_0__LWE_MASK 0x00020000L +#define SQ_MIMG_0__OP_MASK 0x01FC0000L +#define SQ_MIMG_0__NT_MASK 0x02000000L +#define SQ_MIMG_0__ENCODING_MASK 0xFC000000L +//SQ_MIMG_1 +#define SQ_MIMG_1__VADDR__SHIFT 0x0 +#define SQ_MIMG_1__VDATA__SHIFT 0x8 +#define SQ_MIMG_1__SRSRC__SHIFT 0x10 +#define SQ_MIMG_1__SSAMP__SHIFT 0x15 +#define SQ_MIMG_1__D16__SHIFT 0x1f +#define SQ_MIMG_1__VADDR_MASK 0x000000FFL +#define SQ_MIMG_1__VDATA_MASK 0x0000FF00L +#define SQ_MIMG_1__SRSRC_MASK 0x001F0000L +#define SQ_MIMG_1__SSAMP_MASK 0x03E00000L +#define SQ_MIMG_1__D16_MASK 0x80000000L +//SQ_MTBUF_0 +#define SQ_MTBUF_0__OFFSET__SHIFT 0x0 +#define SQ_MTBUF_0__OFFEN__SHIFT 0xc +#define SQ_MTBUF_0__IDXEN__SHIFT 0xd +#define SQ_MTBUF_0__SC0__SHIFT 0xe +#define SQ_MTBUF_0__OP__SHIFT 0xf +#define SQ_MTBUF_0__DFMT__SHIFT 0x13 +#define SQ_MTBUF_0__NFMT__SHIFT 0x17 +#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a +#define SQ_MTBUF_0__OFFSET_MASK 0x00000FFFL +#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L +#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L +#define SQ_MTBUF_0__SC0_MASK 0x00004000L +#define SQ_MTBUF_0__OP_MASK 0x00078000L +#define SQ_MTBUF_0__DFMT_MASK 0x00780000L +#define SQ_MTBUF_0__NFMT_MASK 0x03800000L +#define SQ_MTBUF_0__ENCODING_MASK 0xFC000000L +//SQ_MTBUF_1 +#define SQ_MTBUF_1__VADDR__SHIFT 0x0 +#define SQ_MTBUF_1__VDATA__SHIFT 0x8 +#define SQ_MTBUF_1__SRSRC__SHIFT 0x10 +#define SQ_MTBUF_1__SC1__SHIFT 0x15 +#define SQ_MTBUF_1__NT__SHIFT 0x16 +#define SQ_MTBUF_1__ACC__SHIFT 0x17 +#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18 +#define SQ_MTBUF_1__VADDR_MASK 0x000000FFL +#define SQ_MTBUF_1__VDATA_MASK 0x0000FF00L +#define SQ_MTBUF_1__SRSRC_MASK 0x001F0000L +#define SQ_MTBUF_1__SC1_MASK 0x00200000L +#define SQ_MTBUF_1__NT_MASK 0x00400000L +#define SQ_MTBUF_1__ACC_MASK 0x00800000L +#define SQ_MTBUF_1__SOFFSET_MASK 0xFF000000L +//SQ_MUBUF_0 +#define SQ_MUBUF_0__OFFSET__SHIFT 0x0 +#define SQ_MUBUF_0__OFFEN__SHIFT 0xc +#define SQ_MUBUF_0__IDXEN__SHIFT 0xd +#define SQ_MUBUF_0__SC0__SHIFT 0xe +#define SQ_MUBUF_0__SC1__SHIFT 0xf +#define SQ_MUBUF_0__LDS__SHIFT 0x10 +#define SQ_MUBUF_0__NT__SHIFT 0x11 +#define SQ_MUBUF_0__OP__SHIFT 0x12 +#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a +#define SQ_MUBUF_0__OFFSET_MASK 0x00000FFFL +#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L +#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L +#define SQ_MUBUF_0__SC0_MASK 0x00004000L +#define SQ_MUBUF_0__SC1_MASK 0x00008000L +#define SQ_MUBUF_0__LDS_MASK 0x00010000L +#define SQ_MUBUF_0__NT_MASK 0x00020000L +#define SQ_MUBUF_0__OP_MASK 0x01FC0000L +#define SQ_MUBUF_0__ENCODING_MASK 0xFC000000L +//SQ_MUBUF_1 +#define SQ_MUBUF_1__VADDR__SHIFT 0x0 +#define SQ_MUBUF_1__VDATA__SHIFT 0x8 +#define SQ_MUBUF_1__SRSRC__SHIFT 0x10 +#define SQ_MUBUF_1__ACC__SHIFT 0x17 +#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18 +#define SQ_MUBUF_1__VADDR_MASK 0x000000FFL +#define SQ_MUBUF_1__VDATA_MASK 0x0000FF00L +#define SQ_MUBUF_1__SRSRC_MASK 0x001F0000L +#define SQ_MUBUF_1__ACC_MASK 0x00800000L +#define SQ_MUBUF_1__SOFFSET_MASK 0xFF000000L +//SQ_SCRATCH_0 +#define SQ_SCRATCH_0__OFFSET__SHIFT 0x0 +#define SQ_SCRATCH_0__SVE__SHIFT 0xd +#define SQ_SCRATCH_0__SEG__SHIFT 0xe +#define SQ_SCRATCH_0__SC0__SHIFT 0x10 +#define SQ_SCRATCH_0__NT__SHIFT 0x11 +#define SQ_SCRATCH_0__OP__SHIFT 0x12 +#define SQ_SCRATCH_0__SC1__SHIFT 0x19 +#define SQ_SCRATCH_0__ENCODING__SHIFT 0x1a +#define SQ_SCRATCH_0__OFFSET_MASK 0x00001FFFL +#define SQ_SCRATCH_0__SVE_MASK 0x00002000L +#define SQ_SCRATCH_0__SEG_MASK 0x0000C000L +#define SQ_SCRATCH_0__SC0_MASK 0x00010000L +#define SQ_SCRATCH_0__NT_MASK 0x00020000L +#define SQ_SCRATCH_0__OP_MASK 0x01FC0000L +#define SQ_SCRATCH_0__SC1_MASK 0x02000000L +#define SQ_SCRATCH_0__ENCODING_MASK 0xFC000000L +//SQ_SCRATCH_1 +#define SQ_SCRATCH_1__ADDR__SHIFT 0x0 +#define SQ_SCRATCH_1__DATA__SHIFT 0x8 +#define SQ_SCRATCH_1__SADDR__SHIFT 0x10 +#define SQ_SCRATCH_1__ACC__SHIFT 0x17 +#define SQ_SCRATCH_1__VDST__SHIFT 0x18 +#define SQ_SCRATCH_1__ADDR_MASK 0x000000FFL +#define SQ_SCRATCH_1__DATA_MASK 0x0000FF00L +#define SQ_SCRATCH_1__SADDR_MASK 0x007F0000L +#define SQ_SCRATCH_1__ACC_MASK 0x00800000L +#define SQ_SCRATCH_1__VDST_MASK 0xFF000000L +//SQ_SMEM_0 +#define SQ_SMEM_0__SBASE__SHIFT 0x0 +#define SQ_SMEM_0__SDATA__SHIFT 0x6 +#define SQ_SMEM_0__SOFFSET_EN__SHIFT 0xe +#define SQ_SMEM_0__NV__SHIFT 0xf +#define SQ_SMEM_0__GLC__SHIFT 0x10 +#define SQ_SMEM_0__IMM__SHIFT 0x11 +#define SQ_SMEM_0__OP__SHIFT 0x12 +#define SQ_SMEM_0__ENCODING__SHIFT 0x1a +#define SQ_SMEM_0__SBASE_MASK 0x0000003FL +#define SQ_SMEM_0__SDATA_MASK 0x00001FC0L +#define SQ_SMEM_0__SOFFSET_EN_MASK 0x00004000L +#define SQ_SMEM_0__NV_MASK 0x00008000L +#define SQ_SMEM_0__GLC_MASK 0x00010000L +#define SQ_SMEM_0__IMM_MASK 0x00020000L +#define SQ_SMEM_0__OP_MASK 0x03FC0000L +#define SQ_SMEM_0__ENCODING_MASK 0xFC000000L +//SQ_SMEM_1 +#define SQ_SMEM_1__OFFSET__SHIFT 0x0 +#define SQ_SMEM_1__SOFFSET__SHIFT 0x19 +#define SQ_SMEM_1__OFFSET_MASK 0x001FFFFFL +#define SQ_SMEM_1__SOFFSET_MASK 0xFE000000L +//SQ_SOP1 +#define SQ_SOP1__SSRC0__SHIFT 0x0 +#define SQ_SOP1__OP__SHIFT 0x8 +#define SQ_SOP1__SDST__SHIFT 0x10 +#define SQ_SOP1__ENCODING__SHIFT 0x17 +#define SQ_SOP1__SSRC0_MASK 0x000000FFL +#define SQ_SOP1__OP_MASK 0x0000FF00L +#define SQ_SOP1__SDST_MASK 0x007F0000L +#define SQ_SOP1__ENCODING_MASK 0xFF800000L +//SQ_SOP2 +#define SQ_SOP2__SSRC0__SHIFT 0x0 +#define SQ_SOP2__SSRC1__SHIFT 0x8 +#define SQ_SOP2__SDST__SHIFT 0x10 +#define SQ_SOP2__OP__SHIFT 0x17 +#define SQ_SOP2__ENCODING__SHIFT 0x1e +#define SQ_SOP2__SSRC0_MASK 0x000000FFL +#define SQ_SOP2__SSRC1_MASK 0x0000FF00L +#define SQ_SOP2__SDST_MASK 0x007F0000L +#define SQ_SOP2__OP_MASK 0x3F800000L +#define SQ_SOP2__ENCODING_MASK 0xC0000000L +//SQ_SOPC +#define SQ_SOPC__SSRC0__SHIFT 0x0 +#define SQ_SOPC__SSRC1__SHIFT 0x8 +#define SQ_SOPC__OP__SHIFT 0x10 +#define SQ_SOPC__ENCODING__SHIFT 0x17 +#define SQ_SOPC__SSRC0_MASK 0x000000FFL +#define SQ_SOPC__SSRC1_MASK 0x0000FF00L +#define SQ_SOPC__OP_MASK 0x007F0000L +#define SQ_SOPC__ENCODING_MASK 0xFF800000L +//SQ_SOPK +#define SQ_SOPK__SIMM16__SHIFT 0x0 +#define SQ_SOPK__SDST__SHIFT 0x10 +#define SQ_SOPK__OP__SHIFT 0x17 +#define SQ_SOPK__ENCODING__SHIFT 0x1c +#define SQ_SOPK__SIMM16_MASK 0x0000FFFFL +#define SQ_SOPK__SDST_MASK 0x007F0000L +#define SQ_SOPK__OP_MASK 0x0F800000L +#define SQ_SOPK__ENCODING_MASK 0xF0000000L +//SQ_SOPP +#define SQ_SOPP__SIMM16__SHIFT 0x0 +#define SQ_SOPP__OP__SHIFT 0x10 +#define SQ_SOPP__ENCODING__SHIFT 0x17 +#define SQ_SOPP__SIMM16_MASK 0x0000FFFFL +#define SQ_SOPP__OP_MASK 0x007F0000L +#define SQ_SOPP__ENCODING_MASK 0xFF800000L +//SQ_VINTRP +#define SQ_VINTRP__VSRC__SHIFT 0x0 +#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8 +#define SQ_VINTRP__ATTR__SHIFT 0xa +#define SQ_VINTRP__OP__SHIFT 0x10 +#define SQ_VINTRP__VDST__SHIFT 0x12 +#define SQ_VINTRP__ENCODING__SHIFT 0x1a +#define SQ_VINTRP__VSRC_MASK 0x000000FFL +#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L +#define SQ_VINTRP__ATTR_MASK 0x0000FC00L +#define SQ_VINTRP__OP_MASK 0x00030000L +#define SQ_VINTRP__VDST_MASK 0x03FC0000L +#define SQ_VINTRP__ENCODING_MASK 0xFC000000L +//SQ_VOP1 +#define SQ_VOP1__SRC0__SHIFT 0x0 +#define SQ_VOP1__OP__SHIFT 0x9 +#define SQ_VOP1__VDST__SHIFT 0x11 +#define SQ_VOP1__ENCODING__SHIFT 0x19 +#define SQ_VOP1__SRC0_MASK 0x000001FFL +#define SQ_VOP1__OP_MASK 0x0001FE00L +#define SQ_VOP1__VDST_MASK 0x01FE0000L +#define SQ_VOP1__ENCODING_MASK 0xFE000000L +//SQ_VOP2 +#define SQ_VOP2__SRC0__SHIFT 0x0 +#define SQ_VOP2__VSRC1__SHIFT 0x9 +#define SQ_VOP2__VDST__SHIFT 0x11 +#define SQ_VOP2__OP__SHIFT 0x19 +#define SQ_VOP2__ENCODING__SHIFT 0x1f +#define SQ_VOP2__SRC0_MASK 0x000001FFL +#define SQ_VOP2__VSRC1_MASK 0x0001FE00L +#define SQ_VOP2__VDST_MASK 0x01FE0000L +#define SQ_VOP2__OP_MASK 0x7E000000L +#define SQ_VOP2__ENCODING_MASK 0x80000000L +//SQ_VOP3P_0 +#define SQ_VOP3P_0__VDST__SHIFT 0x0 +#define SQ_VOP3P_0__NEG_HI__SHIFT 0x8 +#define SQ_VOP3P_0__OP_SEL__SHIFT 0xb +#define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT 0xe +#define SQ_VOP3P_0__CLAMP__SHIFT 0xf +#define SQ_VOP3P_0__OP__SHIFT 0x10 +#define SQ_VOP3P_0__ENCODING__SHIFT 0x17 +#define SQ_VOP3P_0__VDST_MASK 0x000000FFL +#define SQ_VOP3P_0__NEG_HI_MASK 0x00000700L +#define SQ_VOP3P_0__OP_SEL_MASK 0x00003800L +#define SQ_VOP3P_0__OP_SEL_HI_2_MASK 0x00004000L +#define SQ_VOP3P_0__CLAMP_MASK 0x00008000L +#define SQ_VOP3P_0__OP_MASK 0x007F0000L +#define SQ_VOP3P_0__ENCODING_MASK 0xFF800000L +//SQ_VOP3P_1 +#define SQ_VOP3P_1__SRC0__SHIFT 0x0 +#define SQ_VOP3P_1__SRC1__SHIFT 0x9 +#define SQ_VOP3P_1__SRC2__SHIFT 0x12 +#define SQ_VOP3P_1__OP_SEL_HI__SHIFT 0x1b +#define SQ_VOP3P_1__NEG__SHIFT 0x1d +#define SQ_VOP3P_1__SRC0_MASK 0x000001FFL +#define SQ_VOP3P_1__SRC1_MASK 0x0003FE00L +#define SQ_VOP3P_1__SRC2_MASK 0x07FC0000L +#define SQ_VOP3P_1__OP_SEL_HI_MASK 0x18000000L +#define SQ_VOP3P_1__NEG_MASK 0xE0000000L +//SQ_VOP3P_MFMA_0 +#define SQ_VOP3P_MFMA_0__VDST__SHIFT 0x0 +#define SQ_VOP3P_MFMA_0__CBSZ__SHIFT 0x8 +#define SQ_VOP3P_MFMA_0__ABID__SHIFT 0xb +#define SQ_VOP3P_MFMA_0__ACC_CD__SHIFT 0xf +#define SQ_VOP3P_MFMA_0__OP__SHIFT 0x10 +#define SQ_VOP3P_MFMA_0__ENCODING__SHIFT 0x17 +#define SQ_VOP3P_MFMA_0__VDST_MASK 0x000000FFL +#define SQ_VOP3P_MFMA_0__CBSZ_MASK 0x00000700L +#define SQ_VOP3P_MFMA_0__ABID_MASK 0x00007800L +#define SQ_VOP3P_MFMA_0__ACC_CD_MASK 0x00008000L +#define SQ_VOP3P_MFMA_0__OP_MASK 0x007F0000L +#define SQ_VOP3P_MFMA_0__ENCODING_MASK 0xFF800000L +//SQ_VOP3P_MFMA_1 +#define SQ_VOP3P_MFMA_1__SRC0__SHIFT 0x0 +#define SQ_VOP3P_MFMA_1__SRC1__SHIFT 0x9 +#define SQ_VOP3P_MFMA_1__SRC2__SHIFT 0x12 +#define SQ_VOP3P_MFMA_1__ACC__SHIFT 0x1b +#define SQ_VOP3P_MFMA_1__BLGP__SHIFT 0x1d +#define SQ_VOP3P_MFMA_1__SRC0_MASK 0x000001FFL +#define SQ_VOP3P_MFMA_1__SRC1_MASK 0x0003FE00L +#define SQ_VOP3P_MFMA_1__SRC2_MASK 0x07FC0000L +#define SQ_VOP3P_MFMA_1__ACC_MASK 0x18000000L +#define SQ_VOP3P_MFMA_1__BLGP_MASK 0xE0000000L +//SQ_VOP3_0 +#define SQ_VOP3_0__VDST__SHIFT 0x0 +#define SQ_VOP3_0__ABS__SHIFT 0x8 +#define SQ_VOP3_0__OP_SEL__SHIFT 0xb +#define SQ_VOP3_0__CLAMP__SHIFT 0xf +#define SQ_VOP3_0__OP__SHIFT 0x10 +#define SQ_VOP3_0__ENCODING__SHIFT 0x1a +#define SQ_VOP3_0__VDST_MASK 0x000000FFL +#define SQ_VOP3_0__ABS_MASK 0x00000700L +#define SQ_VOP3_0__OP_SEL_MASK 0x00007800L +#define SQ_VOP3_0__CLAMP_MASK 0x00008000L +#define SQ_VOP3_0__OP_MASK 0x03FF0000L +#define SQ_VOP3_0__ENCODING_MASK 0xFC000000L +//SQ_VOP3_0_SDST_ENC +#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0 +#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8 +#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf +#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10 +#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a +#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000FFL +#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007F00L +#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x00008000L +#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03FF0000L +#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xFC000000L +//SQ_VOP3_1 +#define SQ_VOP3_1__SRC0__SHIFT 0x0 +#define SQ_VOP3_1__SRC1__SHIFT 0x9 +#define SQ_VOP3_1__SRC2__SHIFT 0x12 +#define SQ_VOP3_1__OMOD__SHIFT 0x1b +#define SQ_VOP3_1__NEG__SHIFT 0x1d +#define SQ_VOP3_1__SRC0_MASK 0x000001FFL +#define SQ_VOP3_1__SRC1_MASK 0x0003FE00L +#define SQ_VOP3_1__SRC2_MASK 0x07FC0000L +#define SQ_VOP3_1__OMOD_MASK 0x18000000L +#define SQ_VOP3_1__NEG_MASK 0xE0000000L +//SQ_VOPC +#define SQ_VOPC__SRC0__SHIFT 0x0 +#define SQ_VOPC__VSRC1__SHIFT 0x9 +#define SQ_VOPC__OP__SHIFT 0x11 +#define SQ_VOPC__ENCODING__SHIFT 0x19 +#define SQ_VOPC__SRC0_MASK 0x000001FFL +#define SQ_VOPC__VSRC1_MASK 0x0001FE00L +#define SQ_VOPC__OP_MASK 0x01FE0000L +#define SQ_VOPC__ENCODING_MASK 0xFE000000L +//SQ_VOP_DPP +#define SQ_VOP_DPP__SRC0__SHIFT 0x0 +#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8 +#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13 +#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14 +#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15 +#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16 +#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17 +#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18 +#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c +#define SQ_VOP_DPP__SRC0_MASK 0x000000FFL +#define SQ_VOP_DPP__DPP_CTRL_MASK 0x0001FF00L +#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x00080000L +#define SQ_VOP_DPP__SRC0_NEG_MASK 0x00100000L +#define SQ_VOP_DPP__SRC0_ABS_MASK 0x00200000L +#define SQ_VOP_DPP__SRC1_NEG_MASK 0x00400000L +#define SQ_VOP_DPP__SRC1_ABS_MASK 0x00800000L +#define SQ_VOP_DPP__BANK_MASK_MASK 0x0F000000L +#define SQ_VOP_DPP__ROW_MASK_MASK 0xF0000000L +//SQ_VOP_SDWA +#define SQ_VOP_SDWA__SRC0__SHIFT 0x0 +#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8 +#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb +#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd +#define SQ_VOP_SDWA__OMOD__SHIFT 0xe +#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10 +#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13 +#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14 +#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15 +#define SQ_VOP_SDWA__S0__SHIFT 0x17 +#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18 +#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b +#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c +#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d +#define SQ_VOP_SDWA__S1__SHIFT 0x1f +#define SQ_VOP_SDWA__SRC0_MASK 0x000000FFL +#define SQ_VOP_SDWA__DST_SEL_MASK 0x00000700L +#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x00001800L +#define SQ_VOP_SDWA__CLAMP_MASK 0x00002000L +#define SQ_VOP_SDWA__OMOD_MASK 0x0000C000L +#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x00070000L +#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x00080000L +#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x00100000L +#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x00200000L +#define SQ_VOP_SDWA__S0_MASK 0x00800000L +#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x07000000L +#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x08000000L +#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000L +#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000L +#define SQ_VOP_SDWA__S1_MASK 0x80000000L +//SQ_VOP_SDWA_SDST_ENC +#define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT 0x0 +#define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT 0x8 +#define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT 0xf +#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT 0x10 +#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT 0x13 +#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT 0x14 +#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT 0x15 +#define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT 0x17 +#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT 0x18 +#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT 0x1b +#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT 0x1c +#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT 0x1d +#define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT 0x1f +#define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK 0x000000FFL +#define SQ_VOP_SDWA_SDST_ENC__SDST_MASK 0x00007F00L +#define SQ_VOP_SDWA_SDST_ENC__SD_MASK 0x00008000L +#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK 0x00070000L +#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK 0x00080000L +#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK 0x00100000L +#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK 0x00200000L +#define SQ_VOP_SDWA_SDST_ENC__S0_MASK 0x00800000L +#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK 0x07000000L +#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK 0x08000000L +#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK 0x10000000L +#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK 0x20000000L +#define SQ_VOP_SDWA_SDST_ENC__S1_MASK 0x80000000L +//SQ_LB_CTR_CTRL +#define SQ_LB_CTR_CTRL__START__SHIFT 0x0 +#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1 +#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2 +#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L +#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L +#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L +//SQ_LB_DATA0 +#define SQ_LB_DATA0__DATA__SHIFT 0x0 +#define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL +//SQ_LB_DATA1 +#define SQ_LB_DATA1__DATA__SHIFT 0x0 +#define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL +//SQ_LB_DATA2 +#define SQ_LB_DATA2__DATA__SHIFT 0x0 +#define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL +//SQ_LB_DATA3 +#define SQ_LB_DATA3__DATA__SHIFT 0x0 +#define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL +//SQ_LB_CTR_SEL +#define SQ_LB_CTR_SEL__SEL0__SHIFT 0x0 +#define SQ_LB_CTR_SEL__SEL1__SHIFT 0x4 +#define SQ_LB_CTR_SEL__SEL2__SHIFT 0x8 +#define SQ_LB_CTR_SEL__SEL3__SHIFT 0xc +#define SQ_LB_CTR_SEL__SEL0_MASK 0x0000000FL +#define SQ_LB_CTR_SEL__SEL1_MASK 0x000000F0L +#define SQ_LB_CTR_SEL__SEL2_MASK 0x00000F00L +#define SQ_LB_CTR_SEL__SEL3_MASK 0x0000F000L +//SQ_LB_CTR0_CU +#define SQ_LB_CTR0_CU__SH0_MASK__SHIFT 0x0 +#define SQ_LB_CTR0_CU__SH1_MASK__SHIFT 0x10 +#define SQ_LB_CTR0_CU__SH0_MASK_MASK 0x0000FFFFL +#define SQ_LB_CTR0_CU__SH1_MASK_MASK 0xFFFF0000L +//SQ_LB_CTR1_CU +#define SQ_LB_CTR1_CU__SH0_MASK__SHIFT 0x0 +#define SQ_LB_CTR1_CU__SH1_MASK__SHIFT 0x10 +#define SQ_LB_CTR1_CU__SH0_MASK_MASK 0x0000FFFFL +#define SQ_LB_CTR1_CU__SH1_MASK_MASK 0xFFFF0000L +//SQ_LB_CTR2_CU +#define SQ_LB_CTR2_CU__SH0_MASK__SHIFT 0x0 +#define SQ_LB_CTR2_CU__SH1_MASK__SHIFT 0x10 +#define SQ_LB_CTR2_CU__SH0_MASK_MASK 0x0000FFFFL +#define SQ_LB_CTR2_CU__SH1_MASK_MASK 0xFFFF0000L +//SQ_LB_CTR3_CU +#define SQ_LB_CTR3_CU__SH0_MASK__SHIFT 0x0 +#define SQ_LB_CTR3_CU__SH1_MASK__SHIFT 0x10 +#define SQ_LB_CTR3_CU__SH0_MASK_MASK 0x0000FFFFL +#define SQ_LB_CTR3_CU__SH1_MASK_MASK 0xFFFF0000L +//SQC_EDC_CNT +#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x0 +#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x2 +#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x4 +#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT 0x6 +#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x8 +#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT 0xa +#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT 0xc +#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT 0xe +#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x10 +#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x12 +#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x14 +#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT 0x16 +#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x18 +#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x1a +#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1c +#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1e +#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000003L +#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK 0x0000000CL +#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK 0x00000030L +#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK 0x000000C0L +#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000300L +#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK 0x00000C00L +#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK 0x00003000L +#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK 0x0000C000L +#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00030000L +#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK 0x000C0000L +#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK 0x00300000L +#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK 0x00C00000L +#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK 0x03000000L +#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK 0x0C000000L +#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK 0x30000000L +#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK 0xC0000000L +//SQ_EDC_SEC_CNT +#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0 +#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8 +#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10 +#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0x000000FFL +#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0x0000FF00L +#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0x00FF0000L +//SQ_EDC_DED_CNT +#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0 +#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8 +#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10 +#define SQ_EDC_DED_CNT__LDS_DED_MASK 0x000000FFL +#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0x0000FF00L +#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0x00FF0000L +//SQ_EDC_INFO +#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0 +#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4 +#define SQ_EDC_INFO__SOURCE__SHIFT 0x6 +#define SQ_EDC_INFO__VM_ID__SHIFT 0x9 +#define SQ_EDC_INFO__WAVE_ID_MASK 0x0000000FL +#define SQ_EDC_INFO__SIMD_ID_MASK 0x00000030L +#define SQ_EDC_INFO__SOURCE_MASK 0x000001C0L +#define SQ_EDC_INFO__VM_ID_MASK 0x00001E00L +//SQ_EDC_CNT +#define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0 +#define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2 +#define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4 +#define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6 +#define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8 +#define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa +#define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc +#define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe +#define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10 +#define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12 +#define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14 +#define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16 +#define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18 +#define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a +#define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L +#define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL +#define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L +#define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L +#define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L +#define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L +#define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L +#define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L +#define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L +#define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L +#define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L +#define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L +#define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L +#define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L +//SQ_EDC_FUE_CNTL +#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0 +#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10 +#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL +#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L +//SQ_THREAD_TRACE_WORD_CMN +#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x000FL +#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x0010L +//SQ_THREAD_TRACE_WORD_EVENT +#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x000FL +#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x0010L +#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x0020L +#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x01C0L +#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xFC00L +//SQ_THREAD_TRACE_WORD_INST +#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb +#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x000FL +#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x0010L +#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x01E0L +#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x0600L +#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xF800L +//SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT 0xf +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001E0L +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK 0x00008000L +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xFFFF0000L +//SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__PRIV__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__PRIV_MASK 0x00000020L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003C0L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003C00L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000C000L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xFFFF0000L +//SQ_THREAD_TRACE_WORD_ISSUE +#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc +#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a +#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000C00L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000C000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000C0000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00C00000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0C000000L +//SQ_THREAD_TRACE_WORD_MISC +#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc +#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd +#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x000FL +#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x0FF0L +#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000L +#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xE000L +//SQ_THREAD_TRACE_WORD_PERF_1_OF_2 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003C0L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000C00L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01FFF000L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xFE000000L +//SQ_THREAD_TRACE_WORD_REG_1_OF_2 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001C00L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xFFFF0000L +//SQ_THREAD_TRACE_WORD_REG_2_OF_2 +#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x00000060L +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x00000180L +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0x0000FE00L +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xFFFF0000L +//SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 +#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0x0000FFFFL +//SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xFFFF0000L +//SQ_THREAD_TRACE_WORD_WAVE +#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x000FL +#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x0010L +#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x0020L +#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x03C0L +#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3C00L +#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xC000L +//SQ_THREAD_TRACE_WORD_WAVE_START +#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15 +#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16 +#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d +#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000FL +#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L +#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003C0L +#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003C00L +#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000C000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001F0000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1FC00000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xE0000000L +//SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 +#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00FFFFFFL +//SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xFFFFL +//SQ_THREAD_TRACE_WORD_PERF_2_OF_2 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003FL +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007FFC0L +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xFFF80000L +//SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xFFFFFFFFL +//SQ_WREXEC_EXEC_HI +#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0 +#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a +#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b +#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c +#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f +#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL +#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L +#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x08000000L +#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L +#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L +//SQ_WREXEC_EXEC_LO +#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0 +#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL +//SQ_BUF_RSRC_WORD0 +#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL +//SQ_BUF_RSRC_WORD1 +#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10 +#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e +#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f +#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000FFFFL +#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3FFF0000L +#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L +#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L +//SQ_BUF_RSRC_WORD2 +#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xFFFFFFFFL +//SQ_BUF_RSRC_WORD3 +#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 +#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 +#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc +#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf +#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT 0x13 +#define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT 0x14 +#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15 +#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17 +#define SQ_BUF_RSRC_WORD3__NV__SHIFT 0x1b +#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e +#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L +#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L +#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L +#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L +#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L +#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L +#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK 0x00080000L +#define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK 0x00100000L +#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L +#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L +#define SQ_BUF_RSRC_WORD3__NV_MASK 0x08000000L +#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xC0000000L +//SQ_IMG_RSRC_WORD0 +#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL +//SQ_IMG_RSRC_WORD1 +#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8 +#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14 +#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a +#define SQ_IMG_RSRC_WORD1__NV__SHIFT 0x1e +#define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT 0x1f +#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000FFL +#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000FFF00L +#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03F00000L +#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3C000000L +#define SQ_IMG_RSRC_WORD1__NV_MASK 0x40000000L +#define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK 0x80000000L +//SQ_IMG_RSRC_WORD2 +#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe +#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c +#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003FFFL +#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0FFFC000L +#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L +//SQ_IMG_RSRC_WORD3 +#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 +#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 +#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc +#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10 +#define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT 0x14 +#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c +#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L +#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L +#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L +#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L +#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000F000L +#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000F0000L +#define SQ_IMG_RSRC_WORD3__SW_MODE_MASK 0x01F00000L +#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xF0000000L +//SQ_IMG_RSRC_WORD4 +#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd +#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT 0x1d +#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001FFFL +#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x1FFFE000L +#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK 0xE0000000L +//SQ_IMG_RSRC_WORD5 +#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT 0xd +#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT 0x11 +#define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT 0x19 +#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT 0x1a +#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT 0x1b +#define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT 0x1c +#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001FFFL +#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK 0x0001E000L +#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK 0x01FE0000L +#define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK 0x02000000L +#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK 0x04000000L +#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK 0x08000000L +#define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK 0xF0000000L +//SQ_IMG_RSRC_WORD6 +#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc +#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14 +#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15 +#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16 +#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17 +#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18 +#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c +#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000FFFL +#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000FF000L +#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L +#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x00200000L +#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x00400000L +#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x00800000L +#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0x0F000000L +#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xF0000000L +//SQ_IMG_RSRC_WORD7 +#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xFFFFFFFFL +//SQ_IMG_SAMP_WORD0 +#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3 +#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6 +#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9 +#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc +#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf +#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10 +#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13 +#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14 +#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15 +#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b +#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c +#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d +#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f +#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L +#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L +#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001C0L +#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000E00L +#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L +#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L +#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L +#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L +#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L +#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07E00000L +#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L +#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L +#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L +#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000L +//SQ_IMG_SAMP_WORD1 +#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc +#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18 +#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c +#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000FFFL +#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00FFF000L +#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0F000000L +#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xF0000000L +//SQ_IMG_SAMP_WORD2 +#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe +#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14 +#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16 +#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18 +#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a +#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c +#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT 0x1d +#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e +#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003FFFL +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000FC000L +#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L +#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00C00000L +#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L +#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0C000000L +#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L +#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK 0x20000000L +#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L +#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000L +//SQ_IMG_SAMP_WORD3 +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT 0xc +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000FFFL +#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK 0x00001000L +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xC0000000L +//SQ_FLAT_SCRATCH_WORD0 +#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0 +#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x0007FFFFL +//SQ_FLAT_SCRATCH_WORD1 +#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0 +#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0x00FFFFFFL +//SQ_M0_GPR_IDX_WORD +#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0 +#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc +#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd +#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe +#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf +#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0x000000FFL +#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x00001000L +#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x00002000L +#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x00004000L +#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x00008000L +//SQC_ICACHE_UTCL1_CNTL1 +#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 +#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 +#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 +#define SQC_ICACHE_UTCL1_CNTL1__RESERVED__SHIFT 0x10 +#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 +#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 +#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 +#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 +#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 +#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 +#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a +#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L +#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L +#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L +#define SQC_ICACHE_UTCL1_CNTL1__RESERVED_MASK 0x00010000L +#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L +#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L +#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L +#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L +#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L +#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L +#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L +#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//SQC_ICACHE_UTCL1_CNTL2 +#define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0 +#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 +#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa +#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb +#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc +#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd +#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf +#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10 +#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 +#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 +#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 +#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 +#define SQC_ICACHE_UTCL1_CNTL2__RESERVED__SHIFT 0x19 +#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL +#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L +#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L +#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L +#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L +#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L +#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L +#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L +#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L +#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L +#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L +#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L +#define SQC_ICACHE_UTCL1_CNTL2__RESERVED_MASK 0x02000000L +#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +//SQC_DCACHE_UTCL1_CNTL1 +#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 +#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 +#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 +#define SQC_DCACHE_UTCL1_CNTL1__RESERVED__SHIFT 0x10 +#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 +#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 +#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 +#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 +#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 +#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 +#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a +#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L +#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L +#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L +#define SQC_DCACHE_UTCL1_CNTL1__RESERVED_MASK 0x00010000L +#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L +#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L +#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L +#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L +#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L +#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L +#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L +#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//SQC_DCACHE_UTCL1_CNTL2 +#define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0 +#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 +#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa +#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb +#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc +#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd +#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf +#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10 +#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 +#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 +#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 +#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 +#define SQC_DCACHE_UTCL1_CNTL2__RESERVED__SHIFT 0x19 +#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL +#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L +#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L +#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L +#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L +#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L +#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L +#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L +#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L +#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L +#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L +#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L +#define SQC_DCACHE_UTCL1_CNTL2__RESERVED_MASK 0x02000000L +#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +//SQC_ICACHE_UTCL1_STATUS +#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +//SQC_DCACHE_UTCL1_STATUS +#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +//SQC_UE_EDC_LO +#define SQC_UE_EDC_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define SQC_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1 +#define SQC_UE_EDC_LO__ADDRESS__SHIFT 0x2 +#define SQC_UE_EDC_LO__MEM_ID__SHIFT 0x18 +#define SQC_UE_EDC_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define SQC_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L +#define SQC_UE_EDC_LO__ADDRESS_MASK 0x00FFFFFCL +#define SQC_UE_EDC_LO__MEM_ID_MASK 0xFF000000L +//SQC_UE_EDC_HI +#define SQC_UE_EDC_HI__ECC__SHIFT 0x0 +#define SQC_UE_EDC_HI__PARITY__SHIFT 0x1 +#define SQC_UE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define SQC_UE_EDC_HI__ERR_INFO__SHIFT 0x3 +#define SQC_UE_EDC_HI__UE_CNT__SHIFT 0x17 +#define SQC_UE_EDC_HI__FED_CNT__SHIFT 0x1a +#define SQC_UE_EDC_HI__ECC_MASK 0x00000001L +#define SQC_UE_EDC_HI__PARITY_MASK 0x00000002L +#define SQC_UE_EDC_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define SQC_UE_EDC_HI__ERR_INFO_MASK 0x007FFFF8L +#define SQC_UE_EDC_HI__UE_CNT_MASK 0x03800000L +#define SQC_UE_EDC_HI__FED_CNT_MASK 0x1C000000L +//SQC_CE_EDC_LO +#define SQC_CE_EDC_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define SQC_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1 +#define SQC_CE_EDC_LO__ADDRESS__SHIFT 0x2 +#define SQC_CE_EDC_LO__MEM_ID__SHIFT 0x18 +#define SQC_CE_EDC_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define SQC_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L +#define SQC_CE_EDC_LO__ADDRESS_MASK 0x00FFFFFCL +#define SQC_CE_EDC_LO__MEM_ID_MASK 0xFF000000L +//SQC_CE_EDC_HI +#define SQC_CE_EDC_HI__ECC__SHIFT 0x0 +#define SQC_CE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define SQC_CE_EDC_HI__ERR_INFO__SHIFT 0x3 +#define SQC_CE_EDC_HI__CE_CNT__SHIFT 0x17 +#define SQC_CE_EDC_HI__POSION__SHIFT 0x1a +#define SQC_CE_EDC_HI__ECC_MASK 0x00000001L +#define SQC_CE_EDC_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define SQC_CE_EDC_HI__ERR_INFO_MASK 0x007FFFF8L +#define SQC_CE_EDC_HI__CE_CNT_MASK 0x03800000L +#define SQC_CE_EDC_HI__POSION_MASK 0x04000000L +//SQ_UE_ERR_STATUS_LO +#define SQ_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define SQ_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define SQ_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define SQ_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define SQ_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define SQ_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define SQ_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define SQ_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//SQ_UE_ERR_STATUS_HI +#define SQ_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define SQ_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define SQ_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define SQ_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define SQ_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define SQ_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define SQ_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define SQ_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define SQ_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define SQ_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define SQ_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define SQ_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define SQ_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define SQ_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//SQ_CE_ERR_STATUS_LO +#define SQ_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define SQ_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define SQ_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define SQ_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define SQ_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define SQ_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define SQ_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define SQ_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//SQ_CE_ERR_STATUS_HI +#define SQ_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define SQ_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define SQ_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define SQ_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define SQ_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define SQ_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define SQ_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define SQ_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define SQ_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define SQ_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define SQ_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define SQ_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define SQ_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define SQ_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L +//LDS_UE_ERR_STATUS_LO +#define LDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define LDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define LDS_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define LDS_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define LDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define LDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define LDS_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define LDS_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//LDS_UE_ERR_STATUS_HI +#define LDS_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define LDS_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define LDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define LDS_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define LDS_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define LDS_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define LDS_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define LDS_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define LDS_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define LDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define LDS_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define LDS_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define LDS_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define LDS_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//LDS_CE_ERR_STATUS_LO +#define LDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define LDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define LDS_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define LDS_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define LDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define LDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define LDS_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define LDS_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//LDS_CE_ERR_STATUS_HI +#define LDS_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define LDS_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define LDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define LDS_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define LDS_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define LDS_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define LDS_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define LDS_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define LDS_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define LDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define LDS_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define LDS_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define LDS_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define LDS_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L +//SP0_UE_ERR_STATUS_LO +#define SP0_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define SP0_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define SP0_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define SP0_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define SP0_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define SP0_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define SP0_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define SP0_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//SP0_UE_ERR_STATUS_HI +#define SP0_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define SP0_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define SP0_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define SP0_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define SP0_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define SP0_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define SP0_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define SP0_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define SP0_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define SP0_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define SP0_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define SP0_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define SP0_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define SP0_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//SP0_CE_ERR_STATUS_LO +#define SP0_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define SP0_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define SP0_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define SP0_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define SP0_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define SP0_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define SP0_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define SP0_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//SP0_CE_ERR_STATUS_HI +#define SP0_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define SP0_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define SP0_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define SP0_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define SP0_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define SP0_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define SP0_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define SP0_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define SP0_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define SP0_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define SP0_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define SP0_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define SP0_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define SP0_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L +//SP1_UE_ERR_STATUS_LO +#define SP1_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define SP1_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define SP1_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define SP1_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define SP1_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define SP1_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define SP1_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define SP1_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//SP1_UE_ERR_STATUS_HI +#define SP1_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define SP1_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define SP1_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define SP1_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define SP1_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define SP1_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define SP1_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define SP1_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define SP1_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define SP1_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define SP1_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define SP1_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define SP1_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define SP1_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//SP1_CE_ERR_STATUS_LO +#define SP1_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define SP1_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define SP1_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define SP1_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define SP1_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define SP1_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define SP1_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define SP1_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//SP1_CE_ERR_STATUS_HI +#define SP1_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define SP1_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define SP1_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define SP1_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define SP1_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define SP1_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define SP1_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define SP1_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define SP1_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define SP1_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define SP1_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define SP1_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define SP1_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define SP1_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L + + +// addressBlock: xcd0_gc_shsdec +//SX_DEBUG_BUSY +#define SX_DEBUG_BUSY__RESERVED__SHIFT 0x0 +#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x1b +#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x1c +#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d +#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x1e +#define SX_DEBUG_BUSY__PCDATA_VALID__SHIFT 0x1f +#define SX_DEBUG_BUSY__RESERVED_MASK 0x07FFFFFFL +#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x08000000L +#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000L +#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000L +#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000L +#define SX_DEBUG_BUSY__PCDATA_VALID_MASK 0x80000000L +//SX_DEBUG_1 +#define SX_DEBUG_1__RESERVED__SHIFT 0x0 +#define SX_DEBUG_1__DISABLE_REP_FGCG__SHIFT 0xd +#define SX_DEBUG_1__RESERVED_MASK 0x00001FFFL +#define SX_DEBUG_1__DISABLE_REP_FGCG_MASK 0x00002000L +//SPI_PS_MAX_WAVE_ID +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10 +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL +#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L +//SPI_START_PHASE +#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0 +#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2 +#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4 +#define SPI_START_PHASE__SPI_TD_GAP__SHIFT 0x6 +#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x00000003L +#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0x0000000CL +#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x00000030L +#define SPI_START_PHASE__SPI_TD_GAP_MASK 0x000003C0L +//SPI_GFX_CNTL +#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0 +#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L +//SPI_DEBUG_READ +#define SPI_DEBUG_READ__DATA__SHIFT 0x0 +#define SPI_DEBUG_READ__DATA_MASK 0xFFFFFFFFL +//SPI_DSM_CNTL +#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define SPI_DSM_CNTL__RESERVED__SHIFT 0x9 +#define SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define SPI_DSM_CNTL__UNUSED__SHIFT 0xf +#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define SPI_DSM_CNTL__RESERVED_MASK 0x00000E00L +#define SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define SPI_DSM_CNTL__UNUSED_MASK 0xFFFF8000L +//SPI_DSM_CNTL2 +#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x4 +#define SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_ENABLE_ERROR_INJECT__SHIFT 0xa +#define SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_SELECT_INJECT_DELAY__SHIFT 0xc +#define SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_ENABLE_ERROR_INJECT__SHIFT 0xd +#define SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_SELECT_INJECT_DELAY__SHIFT 0xf +#define SPI_DSM_CNTL2__RESERVED__SHIFT 0x10 +#define SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_ENABLE_ERROR_INJECT__SHIFT 0x13 +#define SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_SELECT_INJECT_DELAY__SHIFT 0x15 +#define SPI_DSM_CNTL2__UNUSED__SHIFT 0x16 +#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000003F0L +#define SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_ENABLE_ERROR_INJECT_MASK 0x00000C00L +#define SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_SELECT_INJECT_DELAY_MASK 0x00001000L +#define SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_ENABLE_ERROR_INJECT_MASK 0x00006000L +#define SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_SELECT_INJECT_DELAY_MASK 0x00008000L +#define SPI_DSM_CNTL2__RESERVED_MASK 0x00070000L +#define SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_ENABLE_ERROR_INJECT_MASK 0x00180000L +#define SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_SELECT_INJECT_DELAY_MASK 0x00200000L +#define SPI_DSM_CNTL2__UNUSED_MASK 0xFFC00000L +//SPI_EDC_CNT +#define SPI_EDC_CNT__SPI_SR_MEM_SEC_COUNT__SHIFT 0x0 +#define SPI_EDC_CNT__SPI_SR_MEM_DED_COUNT__SHIFT 0x2 +#define SPI_EDC_CNT__SPI_GDS_EXPREQ_SEC_COUNT__SHIFT 0x4 +#define SPI_EDC_CNT__SPI_GDS_EXPREQ_DED_COUNT__SHIFT 0x6 +#define SPI_EDC_CNT__SPI_WB_GRANT_30_SEC_COUNT__SHIFT 0x8 +#define SPI_EDC_CNT__SPI_WB_GRANT_30_DED_COUNT__SHIFT 0xa +#define SPI_EDC_CNT__RESERVED__SHIFT 0xc +#define SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT__SHIFT 0x10 +#define SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT__SHIFT 0x12 +#define SPI_EDC_CNT__UNUSED__SHIFT 0x14 +#define SPI_EDC_CNT__SPI_SR_MEM_SEC_COUNT_MASK 0x00000003L +#define SPI_EDC_CNT__SPI_SR_MEM_DED_COUNT_MASK 0x0000000CL +#define SPI_EDC_CNT__SPI_GDS_EXPREQ_SEC_COUNT_MASK 0x00000030L +#define SPI_EDC_CNT__SPI_GDS_EXPREQ_DED_COUNT_MASK 0x000000C0L +#define SPI_EDC_CNT__SPI_WB_GRANT_30_SEC_COUNT_MASK 0x00000300L +#define SPI_EDC_CNT__SPI_WB_GRANT_30_DED_COUNT_MASK 0x00000C00L +#define SPI_EDC_CNT__RESERVED_MASK 0x0000F000L +#define SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT_MASK 0x00030000L +#define SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT_MASK 0x000C0000L +#define SPI_EDC_CNT__UNUSED_MASK 0xFFF00000L +//SPI_UE_ERR_STATUS_LO +#define SPI_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define SPI_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define SPI_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define SPI_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define SPI_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define SPI_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define SPI_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define SPI_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//SPI_UE_ERR_STATUS_HI +#define SPI_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define SPI_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define SPI_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define SPI_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define SPI_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define SPI_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define SPI_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define SPI_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define SPI_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define SPI_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define SPI_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define SPI_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define SPI_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define SPI_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//SPI_CE_ERR_STATUS_LO +#define SPI_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define SPI_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define SPI_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define SPI_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define SPI_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define SPI_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define SPI_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define SPI_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//SPI_CE_ERR_STATUS_HI +#define SPI_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define SPI_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define SPI_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define SPI_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define SPI_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define SPI_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define SPI_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define SPI_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define SPI_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define SPI_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define SPI_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define SPI_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define SPI_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define SPI_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L +//SPI_DEBUG_BUSY +#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x0 +#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x1 +#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x2 +#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x3 +#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x4 +#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x5 +#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x6 +#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x7 +#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0x8 +#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0x9 +#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xa +#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xb +#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xc +#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xd +#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0xe +#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0xf +#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x10 +#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x11 +#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x12 +#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x13 +#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x14 +#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x15 +#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x00000001L +#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x00000002L +#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x00000004L +#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x00000008L +#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x00000010L +#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x00000020L +#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x00000040L +#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x00000080L +#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x00000100L +#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x00000200L +#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x00000400L +#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x00000800L +#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x00001000L +#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x00002000L +#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x00004000L +#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x00008000L +#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x00010000L +#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x00020000L +#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x00040000L +#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x00080000L +#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x00100000L +#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x00200000L +//SPI_CONFIG_PS_CU_EN +#define SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT 0x0 +#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT 0x1 +#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT 0x10 +#define SPI_CONFIG_PS_CU_EN__ENABLE_MASK 0x00000001L +#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK 0x0000FFFEL +#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK 0xFFFF0000L +//SPI_WF_LIFETIME_CNTL +#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0 +#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4 +#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL +#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L +//SPI_WF_LIFETIME_LIMIT_0 +#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_1 +#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_2 +#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_3 +#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_4 +#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_5 +#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_6 +#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_7 +#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_8 +#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_9 +#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_0 +#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_1 +#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_2 +#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_3 +#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_4 +#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_5 +#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_6 +#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_7 +#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_8 +#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_9 +#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_10 +#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_11 +#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_12 +#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_13 +#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_14 +#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_15 +#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_16 +#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_17 +#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_18 +#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_19 +#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_20 +#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_DEBUG +#define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0 +#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f +#define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000L +//SPI_LB_CTR_CTRL +#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0 +#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1 +#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3 +#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4 +#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L +#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L +#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L +#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L +//SPI_LB_CU_MASK +#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0 +#define SPI_LB_CU_MASK__CU_MASK_MASK 0xFFFFL +//SPI_LB_DATA_REG +#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0 +#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL +//SPI_PG_ENABLE_STATIC_CU_MASK +#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0 +#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xFFFFL +//SPI_GDS_CREDITS +#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0 +#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8 +#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10 +#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL +#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L +#define SPI_GDS_CREDITS__UNUSED_MASK 0xFFFF0000L +//SPI_SX_EXPORT_BUFFER_SIZES +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0 +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10 +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L +//SPI_SX_SCOREBOARD_BUFFER_SIZES +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L +//SPI_CSQ_WF_ACTIVE_STATUS +#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL +//SPI_CSQ_WF_ACTIVE_COUNT_0 +#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000001FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x01FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_1 +#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000001FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x01FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_2 +#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000001FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x01FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_3 +#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000001FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x01FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_4 +#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000001FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x01FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_5 +#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000001FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x01FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_6 +#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000001FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x01FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_7 +#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000001FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x01FF0000L +//SPI_LB_DATA_WAVES +#define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0 +#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10 +#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL +#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L +//SPI_LB_DATA_PERCU_WAVE_HSGS +#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT 0x0 +#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT 0x10 +#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK 0x0000FFFFL +#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK 0xFFFF0000L +//SPI_LB_DATA_PERCU_WAVE_VSPS +#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT 0x0 +#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT 0x10 +#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK 0x0000FFFFL +#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK 0xFFFF0000L +//SPI_LB_DATA_PERCU_WAVE_CS +#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT 0x0 +#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK 0xFFFFL +//SPIS_DEBUG_READ +#define SPIS_DEBUG_READ__DATA__SHIFT 0x0 +#define SPIS_DEBUG_READ__DATA_MASK 0xFFFFFFFFL +//BCI_DEBUG_READ +#define BCI_DEBUG_READ__DATA__SHIFT 0x0 +#define BCI_DEBUG_READ__DATA_MASK 0xFFFFFFL +//SPI_P0_TRAP_SCREEN_PSBA_LO +#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P0_TRAP_SCREEN_PSBA_HI +#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL +//SPI_P0_TRAP_SCREEN_PSMA_LO +#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P0_TRAP_SCREEN_PSMA_HI +#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL +//SPI_P0_TRAP_SCREEN_GPR_MIN +#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 +#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL +#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L +//SPI_P1_TRAP_SCREEN_PSBA_LO +#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P1_TRAP_SCREEN_PSBA_HI +#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL +//SPI_P1_TRAP_SCREEN_PSMA_LO +#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P1_TRAP_SCREEN_PSMA_HI +#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL +//SPI_P1_TRAP_SCREEN_GPR_MIN +#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 +#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL +#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L + + +// addressBlock: xcd0_gc_tpdec +//TD_CNTL +#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0 +#define TD_CNTL__TD_IN_CAC_CHICKENBITS__SHIFT 0x2 +#define TD_CNTL__TD_OUT_CAC_CHICKENBITS__SHIFT 0x6 +#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9 +#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb +#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14 +#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15 +#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17 +#define TD_CNTL__SRAM_FGCG_TD_KCLARR_LG__SHIFT 0x1b +#define TD_CNTL__RFGCG_CHICKEN__SHIFT 0x1c +#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L +#define TD_CNTL__TD_IN_CAC_CHICKENBITS_MASK 0x0000000CL +#define TD_CNTL__TD_OUT_CAC_CHICKENBITS_MASK 0x000000C0L +#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L +#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L +#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L +#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x00200000L +#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x00800000L +#define TD_CNTL__SRAM_FGCG_TD_KCLARR_LG_MASK 0x08000000L +#define TD_CNTL__RFGCG_CHICKEN_MASK 0x70000000L +//TD_STATUS +#define TD_STATUS__BUSY__SHIFT 0x1f +#define TD_STATUS__BUSY_MASK 0x80000000L +//TD_POWER_CNTL +#define TD_POWER_CNTL__MGCG_OUTPUTSTAGE__SHIFT 0x1 +#define TD_POWER_CNTL__MID0_THREAD_DATA__SHIFT 0x2 +#define TD_POWER_CNTL__MID2_ACCUM_DATA__SHIFT 0x3 +#define TD_POWER_CNTL__MGCG_OUTPUTSTAGE_MASK 0x00000002L +#define TD_POWER_CNTL__MID0_THREAD_DATA_MASK 0x00000004L +#define TD_POWER_CNTL__MID2_ACCUM_DATA_MASK 0x00000008L +//TD_UE_EDC_LO +#define TD_UE_EDC_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define TD_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1 +#define TD_UE_EDC_LO__ADDRESS__SHIFT 0x2 +#define TD_UE_EDC_LO__MEM_ID__SHIFT 0x18 +#define TD_UE_EDC_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define TD_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L +#define TD_UE_EDC_LO__ADDRESS_MASK 0x00FFFFFCL +#define TD_UE_EDC_LO__MEM_ID_MASK 0xFF000000L +//TD_UE_EDC_HI +#define TD_UE_EDC_HI__ECC__SHIFT 0x0 +#define TD_UE_EDC_HI__PARITY__SHIFT 0x1 +#define TD_UE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define TD_UE_EDC_HI__ERR_INFO__SHIFT 0x3 +#define TD_UE_EDC_HI__UE_CNT__SHIFT 0x17 +#define TD_UE_EDC_HI__FED_CNT__SHIFT 0x1a +#define TD_UE_EDC_HI__ECC_MASK 0x00000001L +#define TD_UE_EDC_HI__PARITY_MASK 0x00000002L +#define TD_UE_EDC_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define TD_UE_EDC_HI__ERR_INFO_MASK 0x007FFFF8L +#define TD_UE_EDC_HI__UE_CNT_MASK 0x03800000L +#define TD_UE_EDC_HI__FED_CNT_MASK 0x1C000000L +//TD_CE_EDC_LO +#define TD_CE_EDC_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define TD_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1 +#define TD_CE_EDC_LO__ADDRESS__SHIFT 0x2 +#define TD_CE_EDC_LO__MEM_ID__SHIFT 0x18 +#define TD_CE_EDC_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define TD_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L +#define TD_CE_EDC_LO__ADDRESS_MASK 0x00FFFFFCL +#define TD_CE_EDC_LO__MEM_ID_MASK 0xFF000000L +//TD_CE_EDC_HI +#define TD_CE_EDC_HI__ECC__SHIFT 0x0 +#define TD_CE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define TD_CE_EDC_HI__ERR_INFO__SHIFT 0x3 +#define TD_CE_EDC_HI__CE_CNT__SHIFT 0x17 +#define TD_CE_EDC_HI__POISON__SHIFT 0x1a +#define TD_CE_EDC_HI__ECC_MASK 0x00000001L +#define TD_CE_EDC_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define TD_CE_EDC_HI__ERR_INFO_MASK 0x007FFFF8L +#define TD_CE_EDC_HI__CE_CNT_MASK 0x03800000L +#define TD_CE_EDC_HI__POISON_MASK 0x04000000L +//TD_DSM_CNTL +#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L +//TD_DSM_CNTL2 +#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x5 +#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 +#define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x1a +#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L +#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L +#define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xFC000000L +//TD_SCRATCH +#define TD_SCRATCH__SCRATCH__SHIFT 0x0 +#define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL +//TA_POWER_CNTL +#define TA_POWER_CNTL__INPUT_CLK_EN_MODE__SHIFT 0x0 +#define TA_POWER_CNTL__LOD_CLK_EN_MODE__SHIFT 0x1 +#define TA_POWER_CNTL__WDP_CLK_EN_MODE__SHIFT 0x2 +#define TA_POWER_CNTL__INPUT_CLK_EN_MODE_MASK 0x00000001L +#define TA_POWER_CNTL__LOD_CLK_EN_MODE_MASK 0x00000002L +#define TA_POWER_CNTL__WDP_CLK_EN_MODE_MASK 0x00000004L +//TA_CNTL +#define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0 +#define TA_CNTL__SQ_XNACK_CREDIT__SHIFT 0x9 +#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd +#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10 +#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16 +#define TA_CNTL__FX_XNACK_CREDIT_MASK 0x0000007FL +#define TA_CNTL__SQ_XNACK_CREDIT_MASK 0x00001E00L +#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000E000L +#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L +#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L +//TA_CNTL_AUX +#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0 +#define TA_CNTL_AUX__RESERVED__SHIFT 0x1 +#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5 +#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7 +#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14 +#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15 +#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16 +#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17 +#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18 +#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19 +#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a +#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L +#define TA_CNTL_AUX__RESERVED_MASK 0x0000000EL +#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L +#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L +#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L +#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L +#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L +#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L +#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L +#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L +#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L +//TA_FEATURE_CNTL +#define TA_FEATURE_CNTL__ATOMIC_COALESCING_EN__SHIFT 0x4 +#define TA_FEATURE_CNTL__TA_ACFIFO_CHICKEN__SHIFT 0xb +#define TA_FEATURE_CNTL__TA_CAC_CHICKEN__SHIFT 0xc +#define TA_FEATURE_CNTL__AFIFO_SPLIT_CHICKEN__SHIFT 0xd +#define TA_FEATURE_CNTL__TA_DXFIFO_CHICKEN__SHIFT 0xe +#define TA_FEATURE_CNTL__ATOMIC_COALESCING_EN_MASK 0x00000030L +#define TA_FEATURE_CNTL__TA_ACFIFO_CHICKEN_MASK 0x00000800L +#define TA_FEATURE_CNTL__TA_CAC_CHICKEN_MASK 0x00001000L +#define TA_FEATURE_CNTL__AFIFO_SPLIT_CHICKEN_MASK 0x00002000L +#define TA_FEATURE_CNTL__TA_DXFIFO_CHICKEN_MASK 0x00004000L +//TA_STATUS +#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc +#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10 +#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14 +#define TA_STATUS__IN_BUSY__SHIFT 0x18 +#define TA_STATUS__FG_BUSY__SHIFT 0x19 +#define TA_STATUS__TA_BUSY__SHIFT 0x1c +#define TA_STATUS__FA_BUSY__SHIFT 0x1d +#define TA_STATUS__AL_BUSY__SHIFT 0x1e +#define TA_STATUS__BUSY__SHIFT 0x1f +#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L +#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L +#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L +#define TA_STATUS__IN_BUSY_MASK 0x01000000L +#define TA_STATUS__FG_BUSY_MASK 0x02000000L +#define TA_STATUS__TA_BUSY_MASK 0x10000000L +#define TA_STATUS__FA_BUSY_MASK 0x20000000L +#define TA_STATUS__AL_BUSY_MASK 0x40000000L +#define TA_STATUS__BUSY_MASK 0x80000000L +//TA_SCRATCH +#define TA_SCRATCH__SCRATCH__SHIFT 0x0 +#define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL +//TA_DSM_CNTL +#define TA_DSM_CNTL__TA_FS_DFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define TA_DSM_CNTL__TA_FS_DFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define TA_DSM_CNTL__TA_FX_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define TA_DSM_CNTL__TA_FX_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define TA_DSM_CNTL__TA_FS_CFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc +#define TA_DSM_CNTL__TA_FS_CFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define TA_DSM_CNTL__TA_FS_AFIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0xf +#define TA_DSM_CNTL__TA_FS_AFIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define TA_DSM_CNTL__TA_FS_AFIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define TA_DSM_CNTL__TA_FS_AFIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define TA_DSM_CNTL__TA_FS_DFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define TA_DSM_CNTL__TA_FS_DFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define TA_DSM_CNTL__TA_FX_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define TA_DSM_CNTL__TA_FX_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define TA_DSM_CNTL__TA_FS_CFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define TA_DSM_CNTL__TA_FS_CFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define TA_DSM_CNTL__TA_FS_AFIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define TA_DSM_CNTL__TA_FS_AFIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define TA_DSM_CNTL__TA_FS_AFIFO_HI_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define TA_DSM_CNTL__TA_FS_AFIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//TA_DSM_CNTL2 +#define TA_DSM_CNTL2__TA_FS_DFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TA_DSM_CNTL2__TA_FS_DFIFO_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TA_DSM_CNTL2__TA_FX_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define TA_DSM_CNTL2__TA_FX_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xb +#define TA_DSM_CNTL2__TA_FS_CFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc +#define TA_DSM_CNTL2__TA_FS_CFIFO_SELECT_INJECT_DELAY__SHIFT 0xe +#define TA_DSM_CNTL2__TA_FS_AFIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0xf +#define TA_DSM_CNTL2__TA_FS_AFIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x11 +#define TA_DSM_CNTL2__TA_FS_AFIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define TA_DSM_CNTL2__TA_FS_AFIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x14 +#define TA_DSM_CNTL2__TA_INJECT_DELAY__SHIFT 0x1a +#define TA_DSM_CNTL2__TA_FS_DFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TA_DSM_CNTL2__TA_FS_DFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TA_DSM_CNTL2__TA_FX_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define TA_DSM_CNTL2__TA_FX_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000800L +#define TA_DSM_CNTL2__TA_FS_CFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define TA_DSM_CNTL2__TA_FS_CFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L +#define TA_DSM_CNTL2__TA_FS_AFIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define TA_DSM_CNTL2__TA_FS_AFIFO_LO_SELECT_INJECT_DELAY_MASK 0x00020000L +#define TA_DSM_CNTL2__TA_FS_AFIFO_HI_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define TA_DSM_CNTL2__TA_FS_AFIFO_HI_SELECT_INJECT_DELAY_MASK 0x00100000L +#define TA_DSM_CNTL2__TA_INJECT_DELAY_MASK 0xFC000000L +//TA_UE_EDC_LO +#define TA_UE_EDC_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define TA_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1 +#define TA_UE_EDC_LO__ADDRESS__SHIFT 0x2 +#define TA_UE_EDC_LO__MEM_ID__SHIFT 0x18 +#define TA_UE_EDC_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define TA_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L +#define TA_UE_EDC_LO__ADDRESS_MASK 0x00FFFFFCL +#define TA_UE_EDC_LO__MEM_ID_MASK 0xFF000000L +//TA_UE_EDC_HI +#define TA_UE_EDC_HI__ECC__SHIFT 0x0 +#define TA_UE_EDC_HI__PARITY__SHIFT 0x1 +#define TA_UE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define TA_UE_EDC_HI__ERR_INFO__SHIFT 0x3 +#define TA_UE_EDC_HI__UE_CNT__SHIFT 0x17 +#define TA_UE_EDC_HI__FED_CNT__SHIFT 0x1a +#define TA_UE_EDC_HI__ECC_MASK 0x00000001L +#define TA_UE_EDC_HI__PARITY_MASK 0x00000002L +#define TA_UE_EDC_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define TA_UE_EDC_HI__ERR_INFO_MASK 0x007FFFF8L +#define TA_UE_EDC_HI__UE_CNT_MASK 0x03800000L +#define TA_UE_EDC_HI__FED_CNT_MASK 0x1C000000L +//TA_CE_EDC_LO +#define TA_CE_EDC_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define TA_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1 +#define TA_CE_EDC_LO__ADDRESS__SHIFT 0x2 +#define TA_CE_EDC_LO__MEM_ID__SHIFT 0x18 +#define TA_CE_EDC_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define TA_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L +#define TA_CE_EDC_LO__ADDRESS_MASK 0x00FFFFFCL +#define TA_CE_EDC_LO__MEM_ID_MASK 0xFF000000L +//TA_CE_EDC_HI +#define TA_CE_EDC_HI__ECC__SHIFT 0x0 +#define TA_CE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define TA_CE_EDC_HI__ERR_INFO__SHIFT 0x3 +#define TA_CE_EDC_HI__CE_CNT__SHIFT 0x17 +#define TA_CE_EDC_HI__POISON__SHIFT 0x1a +#define TA_CE_EDC_HI__ECC_MASK 0x00000001L +#define TA_CE_EDC_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define TA_CE_EDC_HI__ERR_INFO_MASK 0x007FFFF8L +#define TA_CE_EDC_HI__CE_CNT_MASK 0x03800000L +#define TA_CE_EDC_HI__POISON_MASK 0x04000000L + + +// addressBlock: xcd0_gc_gdsdec +//GDS_CONFIG +#define GDS_CONFIG__WRITE_DIS__SHIFT 0x0 +#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1 +#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3 +#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 +#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7 +#define GDS_CONFIG__SH4_GPR_PHASE_SEL__SHIFT 0x9 +#define GDS_CONFIG__SH5_GPR_PHASE_SEL__SHIFT 0xb +#define GDS_CONFIG__SH6_GPR_PHASE_SEL__SHIFT 0xd +#define GDS_CONFIG__SH7_GPR_PHASE_SEL__SHIFT 0xf +#define GDS_CONFIG__WRITE_DIS_MASK 0x00000001L +#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L +#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L +#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L +#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L +#define GDS_CONFIG__SH4_GPR_PHASE_SEL_MASK 0x00000600L +#define GDS_CONFIG__SH5_GPR_PHASE_SEL_MASK 0x00001800L +#define GDS_CONFIG__SH6_GPR_PHASE_SEL_MASK 0x00006000L +#define GDS_CONFIG__SH7_GPR_PHASE_SEL_MASK 0x00018000L +//GDS_CNTL_STATUS +#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0 +#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1 +#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2 +#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3 +#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4 +#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5 +#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6 +#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7 +#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8 +#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9 +#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa +#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb +#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc +#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd +#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe +#define GDS_CNTL_STATUS__CREDIT_BUSY4__SHIFT 0xf +#define GDS_CNTL_STATUS__CREDIT_BUSY5__SHIFT 0x10 +#define GDS_CNTL_STATUS__CREDIT_BUSY6__SHIFT 0x11 +#define GDS_CNTL_STATUS__CREDIT_BUSY7__SHIFT 0x12 +#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L +#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L +#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L +#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L +#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L +#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L +#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L +#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L +#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L +#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L +#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L +#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L +#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L +#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L +#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L +#define GDS_CNTL_STATUS__CREDIT_BUSY4_MASK 0x00008000L +#define GDS_CNTL_STATUS__CREDIT_BUSY5_MASK 0x00010000L +#define GDS_CNTL_STATUS__CREDIT_BUSY6_MASK 0x00020000L +#define GDS_CNTL_STATUS__CREDIT_BUSY7_MASK 0x00040000L +//GDS_ENHANCE2 +#define GDS_ENHANCE2__MISC__SHIFT 0x0 +#define GDS_ENHANCE2__GDS_TD_INTERFACES_FGCG_OVERRIDE__SHIFT 0x10 +#define GDS_ENHANCE2__GDS_PHY_CMD_RAM_FGCG_OVERRIDE__SHIFT 0x11 +#define GDS_ENHANCE2__GDS_FED_IN_PROPAGATE__SHIFT 0x12 +#define GDS_ENHANCE2__UNUSED__SHIFT 0x13 +#define GDS_ENHANCE2__MISC_MASK 0x0000FFFFL +#define GDS_ENHANCE2__GDS_TD_INTERFACES_FGCG_OVERRIDE_MASK 0x00010000L +#define GDS_ENHANCE2__GDS_PHY_CMD_RAM_FGCG_OVERRIDE_MASK 0x00020000L +#define GDS_ENHANCE2__GDS_FED_IN_PROPAGATE_MASK 0x00040000L +#define GDS_ENHANCE2__UNUSED_MASK 0xFFF80000L +//GDS_PROTECTION_FAULT +#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 +#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 +#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2 +#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3 +#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6 +#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa +#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc +#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 +#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L +#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L +#define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L +#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L +#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003C0L +#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000C00L +#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000F000L +#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L +//GDS_VM_PROTECTION_FAULT +#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 +#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 +#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2 +#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3 +#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4 +#define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT 0x5 +#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8 +#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 +#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L +#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L +#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L +#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L +#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L +#define GDS_VM_PROTECTION_FAULT__TMZ_MASK 0x00000020L +#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L +#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L +//GDS_EDC_CNT +#define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0 +#define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4 +#define GDS_EDC_CNT__UNUSED__SHIFT 0x6 +#define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L +#define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L +#define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L +//GDS_EDC_GRBM_CNT +#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0 +#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2 +#define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4 +#define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L +#define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL +#define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L +//GDS_EDC_OA_DED +#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0 +#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1 +#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2 +#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3 +#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4 +#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5 +#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6 +#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7 +#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8 +#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9 +#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa +#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb +#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc +#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L +#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L +#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L +#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L +#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L +#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L +#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L +#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L +#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L +#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L +#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L +#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L +#define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFF000L +//GDS_DSM_CNTL +#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0 +#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1 +#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3 +#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4 +#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6 +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7 +#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9 +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa +#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc +#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd +#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define GDS_DSM_CNTL__UNUSED__SHIFT 0xf +#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L +#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L +#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L +#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L +#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L +#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L +#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L +#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L +#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L +//GDS_EDC_OA_PHY_CNT +#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0 +#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2 +#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4 +#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6 +#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SEC__SHIFT 0x8 +#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_DED__SHIFT 0xa +#define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xc +#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L +#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL +#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L +#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L +#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SEC_MASK 0x00000300L +#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_DED_MASK 0x00000C00L +#define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFF000L +//GDS_EDC_OA_PIPE_CNT +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe +#define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10 +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L +#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L +#define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L +//GDS_DSM_CNTL2 +#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5 +#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb +#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf +#define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a +#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L +#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L +#define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L +//GDS_WD_GDS_CSB +#define GDS_WD_GDS_CSB__COUNTER__SHIFT 0x0 +#define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd +#define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL +#define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L +//GDS_UE_ERR_STATUS_LO +#define GDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define GDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define GDS_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define GDS_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define GDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define GDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define GDS_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define GDS_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//GDS_UE_ERR_STATUS_HI +#define GDS_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define GDS_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define GDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define GDS_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define GDS_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define GDS_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define GDS_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define GDS_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define GDS_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define GDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define GDS_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define GDS_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define GDS_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define GDS_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//GDS_CE_ERR_STATUS_LO +#define GDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define GDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define GDS_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define GDS_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define GDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define GDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define GDS_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define GDS_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//GDS_CE_ERR_STATUS_HI +#define GDS_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define GDS_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define GDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define GDS_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define GDS_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define GDS_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define GDS_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define GDS_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define GDS_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define GDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define GDS_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define GDS_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define GDS_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define GDS_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L + + +// addressBlock: xcd0_gc_rbdec +//DB_DEBUG +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0 +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1 +#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2 +#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3 +#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4 +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6 +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7 +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8 +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10 +#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11 +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12 +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13 +#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15 +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16 +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17 +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18 +#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d +#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e +#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L +#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L +#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L +#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L +#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L +#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L +#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L +#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L +#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L +//DB_DEBUG2 +#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0 +#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1 +#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2 +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3 +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4 +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5 +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6 +#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7 +#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8 +#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9 +#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe +#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf +#define DB_DEBUG2__RESERVED__SHIFT 0x10 +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11 +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12 +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13 +#define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID__SHIFT 0x1a +#define DB_DEBUG2__DISABLE_VR_PS_INVOKE__SHIFT 0x1b +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f +#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L +#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L +#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L +#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L +#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L +#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L +#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L +#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L +#define DB_DEBUG2__RESERVED_MASK 0x00010000L +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L +#define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID_MASK 0x04000000L +#define DB_DEBUG2__DISABLE_VR_PS_INVOKE_MASK 0x08000000L +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L +//DB_DEBUG3 +#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x0 +#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT 0x1 +#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2 +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3 +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4 +#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5 +#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6 +#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7 +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8 +#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9 +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa +#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb +#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf +#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10 +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11 +#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12 +#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13 +#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14 +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15 +#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16 +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17 +#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18 +#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19 +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b +#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c +#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d +#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e +#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f +#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L +#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK 0x00000002L +#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L +#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L +#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L +#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L +#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000200L +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L +#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L +#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00001000L +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L +#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x00010000L +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L +#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00040000L +#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L +#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L +#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L +#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L +#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L +#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L +#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000L +#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000L +#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000L +//DB_DEBUG4 +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0 +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1 +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2 +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3 +#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT 0x4 +#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0x5 +#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x6 +#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x7 +#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT 0x8 +#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x9 +#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa +#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0xb +#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT 0xc +#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd +#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0xe +#define DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT 0xf +#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0x10 +#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT 0x11 +#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT 0x12 +#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x13 +#define DB_DEBUG4__DISABLE_8PPC_OBJPRIMID_WHEN_NO_SHADER_EXPORTS__SHIFT 0x1e +#define DB_DEBUG4__FULL_TILE_CACHE_EVICT_ON_HALF_FULL__SHIFT 0x1f +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L +#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK 0x00000010L +#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00000020L +#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000040L +#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000080L +#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK 0x00000100L +#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L +#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L +#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L +#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK 0x00001000L +#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L +#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L +#define DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK 0x00008000L +#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00010000L +#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK 0x00020000L +#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK 0x00040000L +#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0x3FF80000L +#define DB_DEBUG4__DISABLE_8PPC_OBJPRIMID_WHEN_NO_SHADER_EXPORTS_MASK 0x40000000L +#define DB_DEBUG4__FULL_TILE_CACHE_EVICT_ON_HALF_FULL_MASK 0x80000000L +//DB_CREDIT_LIMIT +#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0 +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5 +#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa +#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18 +#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001FL +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L +#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001C00L +#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7F000000L +//DB_WATERMARKS +#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0 +#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5 +#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb +#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14 +#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e +#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f +#define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001FL +#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007E0L +#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L +#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000F8000L +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x0FF00000L +#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L +#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L +//DB_SUBTILE_CONTROL +#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0 +#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2 +#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4 +#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6 +#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8 +#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa +#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc +#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe +#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10 +#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12 +#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L +#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000CL +#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L +#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000C0L +#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L +#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000C00L +#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L +#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000C000L +#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L +#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000C0000L +//DB_FREE_CACHELINES +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0 +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7 +#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe +#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x14 +#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x18 +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007FL +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003F80L +#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x000FC000L +#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x00F00000L +#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xFF000000L +//DB_FIFO_DEPTH1 +#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT 0x0 +#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT 0x5 +#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa +#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10 +#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15 +#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK 0x0000001FL +#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK 0x000003E0L +#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000FC00L +#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001F0000L +#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1FE00000L +//DB_FIFO_DEPTH2 +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0 +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8 +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19 +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007F00L +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF8000L +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L +//DB_EXCEPTION_CONTROL +#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0 +#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1 +#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2 +#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L +#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L +#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L +//DB_RING_CONTROL +#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0 +#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L +//DB_MEM_ARB_WATERMARKS +#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0 +#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8 +#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10 +#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18 +#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L +#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L +#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L +#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L +//DB_RMI_CACHE_POLICY +#define DB_RMI_CACHE_POLICY__Z_RD__SHIFT 0x0 +#define DB_RMI_CACHE_POLICY__S_RD__SHIFT 0x1 +#define DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT 0x2 +#define DB_RMI_CACHE_POLICY__Z_WR__SHIFT 0x8 +#define DB_RMI_CACHE_POLICY__S_WR__SHIFT 0x9 +#define DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT 0xa +#define DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT 0xb +#define DB_RMI_CACHE_POLICY__CC_RD__SHIFT 0x10 +#define DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT 0x11 +#define DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT 0x12 +#define DB_RMI_CACHE_POLICY__DCC_RD__SHIFT 0x13 +#define DB_RMI_CACHE_POLICY__CC_WR__SHIFT 0x18 +#define DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT 0x19 +#define DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT 0x1a +#define DB_RMI_CACHE_POLICY__DCC_WR__SHIFT 0x1b +#define DB_RMI_CACHE_POLICY__Z_RD_MASK 0x00000001L +#define DB_RMI_CACHE_POLICY__S_RD_MASK 0x00000002L +#define DB_RMI_CACHE_POLICY__HTILE_RD_MASK 0x00000004L +#define DB_RMI_CACHE_POLICY__Z_WR_MASK 0x00000100L +#define DB_RMI_CACHE_POLICY__S_WR_MASK 0x00000200L +#define DB_RMI_CACHE_POLICY__HTILE_WR_MASK 0x00000400L +#define DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK 0x00000800L +#define DB_RMI_CACHE_POLICY__CC_RD_MASK 0x00010000L +#define DB_RMI_CACHE_POLICY__FMASK_RD_MASK 0x00020000L +#define DB_RMI_CACHE_POLICY__CMASK_RD_MASK 0x00040000L +#define DB_RMI_CACHE_POLICY__DCC_RD_MASK 0x00080000L +#define DB_RMI_CACHE_POLICY__CC_WR_MASK 0x01000000L +#define DB_RMI_CACHE_POLICY__FMASK_WR_MASK 0x02000000L +#define DB_RMI_CACHE_POLICY__CMASK_WR_MASK 0x04000000L +#define DB_RMI_CACHE_POLICY__DCC_WR_MASK 0x08000000L +//DB_DFSM_CONFIG +#define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT 0x0 +#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT 0x1 +#define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT 0x2 +#define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT 0x3 +#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT 0x8 +#define DB_DFSM_CONFIG__BYPASS_DFSM_MASK 0x00000001L +#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK 0x00000002L +#define DB_DFSM_CONFIG__DISABLE_POPS_MASK 0x00000004L +#define DB_DFSM_CONFIG__FORCE_FLUSH_MASK 0x00000008L +#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK 0x00007F00L +//DB_DFSM_WATERMARK +#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT 0x0 +#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT 0x10 +#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK 0x0000FFFFL +#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK 0xFFFF0000L +//DB_DFSM_TILES_IN_FLIGHT +#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0 +#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10 +#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL +#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L +//DB_DFSM_PRIMS_IN_FLIGHT +#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0 +#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10 +#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL +#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L +//DB_DFSM_WATCHDOG +#define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT 0x0 +#define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK 0xFFFFFFFFL +//DB_DFSM_FLUSH_ENABLE +#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT 0x0 +#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT 0x18 +#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT 0x1c +#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK 0x000003FFL +#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK 0x0F000000L +#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK 0xF0000000L +//DB_DFSM_FLUSH_AUX_EVENT +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT 0x0 +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT 0x8 +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT 0x10 +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT 0x18 +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK 0x000000FFL +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK 0x0000FF00L +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK 0x00FF0000L +#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK 0xFF000000L +//CC_RB_REDUNDANCY +#define CC_RB_REDUNDANCY__WRITE_DIS__SHIFT 0x0 +#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 +#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc +#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 +#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 +#define CC_RB_REDUNDANCY__WRITE_DIS_MASK 0x00000001L +#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L +#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L +#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L +#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L +//CC_RB_BACKEND_DISABLE +#define CC_RB_BACKEND_DISABLE__WRITE_DIS__SHIFT 0x0 +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 +#define CC_RB_BACKEND_DISABLE__WRITE_DIS_MASK 0x00000001L +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L +//GB_ADDR_CONFIG +#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 +#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a +#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define GB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f +#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L +#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L +#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define GB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L +//GB_BACKEND_MAP +#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0 +#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL +//GB_GPU_ID +#define GB_GPU_ID__GPU_ID__SHIFT 0x0 +#define GB_GPU_ID__GPU_ID_MASK 0x0000000FL +//CC_RB_DAISY_CHAIN +#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0 +#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4 +#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8 +#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc +#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10 +#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14 +#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18 +#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c +#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000FL +#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000F0L +#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000F00L +#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000F000L +#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000F0000L +#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00F00000L +#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0F000000L +#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xF0000000L +//GB_ADDR_CONFIG_READ +#define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT 0x15 +#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a +#define GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT 0x1c +#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT 0x1e +#define GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT 0x1f +#define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +#define GB_ADDR_CONFIG_READ__NUM_GPUS_MASK 0x00E00000L +#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L +#define GB_ADDR_CONFIG_READ__ROW_SIZE_MASK 0x30000000L +#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK 0x40000000L +#define GB_ADDR_CONFIG_READ__SE_ENABLE_MASK 0x80000000L +//GB_TILE_MODE0 +#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE1 +#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE2 +#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE3 +#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE4 +#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE5 +#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE6 +#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE7 +#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE8 +#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE9 +#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE10 +#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE11 +#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE12 +#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE13 +#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE14 +#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE15 +#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE16 +#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE17 +#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE18 +#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE19 +#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE20 +#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE21 +#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE22 +#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE23 +#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE24 +#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE25 +#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE26 +#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE27 +#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE28 +#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE29 +#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE30 +#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L +//GB_TILE_MODE31 +#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003CL +#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007C0L +#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01C00000L +#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L +//GB_MACROTILE_MODE0 +#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE1 +#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE2 +#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE3 +#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE4 +#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE5 +#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE6 +#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE7 +#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE8 +#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE9 +#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE10 +#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE11 +#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE12 +#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE13 +#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE14 +#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0x000000C0L +//GB_MACROTILE_MODE15 +#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x00000003L +#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0x0000000CL +#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x00000030L +#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0x000000C0L +//CB_HW_CONTROL +#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0 +#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6 +#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc +#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10 +#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12 +#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13 +#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15 +#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16 +#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b +#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c +#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d +#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e +#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f +#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000FL +#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003C0L +#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000F000L +#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L +#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L +#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L +#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L +#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L +#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L +#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L +#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L +#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L +#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L +//CB_HW_CONTROL_1 +#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0 +#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5 +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb +#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11 +#define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT 0x1a +#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001FL +#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007E0L +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001F800L +#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03FE0000L +#define CB_HW_CONTROL_1__RMI_CREDITS_MASK 0xFC000000L +//CB_HW_CONTROL_2 +#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0 +#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8 +#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf +#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18 +#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c +#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000FFL +#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007F00L +#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007F8000L +#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x0F000000L +#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xF0000000L +//CB_HW_CONTROL_3 +#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0 +#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1 +#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2 +#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3 +#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4 +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5 +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6 +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7 +#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8 +#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9 +#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa +#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb +#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc +#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd +#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT 0xe +#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0xf +#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0x10 +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0x11 +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT 0x12 +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0x13 +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT 0x14 +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0x15 +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT 0x16 +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x17 +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT 0x18 +#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT 0x19 +#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT 0x1a +#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT 0x1b +#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS__SHIFT 0x1c +#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L +#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L +#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x00000004L +#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x00000008L +#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x00000010L +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000020L +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x00000040L +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000080L +#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x00000100L +#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000200L +#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000400L +#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x00000800L +#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x00001000L +#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x00002000L +#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK 0x00004000L +#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00008000L +#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00010000L +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00020000L +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK 0x00040000L +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00080000L +#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK 0x00100000L +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00200000L +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK 0x00400000L +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00800000L +#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK 0x01000000L +#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK 0x02000000L +#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK 0x04000000L +#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK 0x08000000L +#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS_MASK 0x30000000L +//CB_HW_MEM_ARBITER_RD +#define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x0 +#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x2 +#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x6 +#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa +#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT 0xc +#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT 0xe +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0x10 +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0x12 +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x14 +#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x16 +#define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x17 +#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x1a +#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d +#define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L +#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003CL +#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003C0L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000C00L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK 0x00003000L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK 0x0000C000L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00030000L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x000C0000L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00300000L +#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00400000L +#define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x03800000L +#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x1C000000L +#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L +//CB_HW_MEM_ARBITER_WR +#define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x0 +#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x2 +#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x6 +#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa +#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT 0xc +#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT 0xe +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0x10 +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0x12 +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x14 +#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x16 +#define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x17 +#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x1a +#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d +#define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L +#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003CL +#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003C0L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000C00L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK 0x00003000L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK 0x0000C000L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00030000L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x000C0000L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00300000L +#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00400000L +#define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x03800000L +#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x1C000000L +#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L +//CB_DCC_CONFIG +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0 +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5 +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6 +#define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE__SHIFT 0x7 +#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8 +#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10 +#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18 +#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x0000001FL +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x00000020L +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x00000040L +#define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE_MASK 0x00000080L +#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0x0000FF00L +#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x007F0000L +#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0x0F000000L +#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xF0000000L +//GC_USER_RB_REDUNDANCY +#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc +#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 +#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L +#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L +//GC_USER_RB_BACKEND_DISABLE +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L + + +// addressBlock: xcd0_gc_ea_gceadec +//GCEA_DRAM_RD_CLI2GRP_MAP0 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//GCEA_DRAM_RD_CLI2GRP_MAP1 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//GCEA_DRAM_WR_CLI2GRP_MAP0 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//GCEA_DRAM_WR_CLI2GRP_MAP1 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//GCEA_DRAM_RD_GRP2VC_MAP +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//GCEA_DRAM_WR_GRP2VC_MAP +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//GCEA_DRAM_RD_LAZY +#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//GCEA_DRAM_WR_LAZY +#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//GCEA_DRAM_RD_CAM_CNTL +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//GCEA_DRAM_WR_CAM_CNTL +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//GCEA_DRAM_PAGE_BURST +#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//GCEA_DRAM_RD_PRI_AGE +#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//GCEA_DRAM_WR_PRI_AGE +#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//GCEA_DRAM_RD_PRI_QUEUING +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//GCEA_DRAM_WR_PRI_QUEUING +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//GCEA_DRAM_RD_PRI_FIXED +#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//GCEA_DRAM_WR_PRI_FIXED +#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//GCEA_DRAM_RD_PRI_URGENCY +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//GCEA_DRAM_WR_PRI_URGENCY +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//GCEA_DRAM_RD_PRI_QUANT_PRI1 +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_DRAM_RD_PRI_QUANT_PRI2 +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_DRAM_RD_PRI_QUANT_PRI3 +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_DRAM_WR_PRI_QUANT_PRI1 +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_DRAM_WR_PRI_QUANT_PRI2 +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_DRAM_WR_PRI_QUANT_PRI3 +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_RD_CLI2GRP_MAP0 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//GCEA_IO_RD_CLI2GRP_MAP1 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//GCEA_IO_WR_CLI2GRP_MAP0 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//GCEA_IO_WR_CLI2GRP_MAP1 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//GCEA_IO_RD_COMBINE_FLUSH +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L +//GCEA_IO_WR_COMBINE_FLUSH +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 +#define GCEA_IO_WR_COMBINE_FLUSH__DISABLE_MAM_CHAINING__SHIFT 0x12 +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L +#define GCEA_IO_WR_COMBINE_FLUSH__DISABLE_MAM_CHAINING_MASK 0x00040000L +//GCEA_IO_GROUP_BURST +#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//GCEA_IO_RD_PRI_AGE +#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//GCEA_IO_WR_PRI_AGE +#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//GCEA_IO_RD_PRI_QUEUING +#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//GCEA_IO_WR_PRI_QUEUING +#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//GCEA_IO_RD_PRI_FIXED +#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//GCEA_IO_WR_PRI_FIXED +#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//GCEA_IO_RD_PRI_URGENCY +#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//GCEA_IO_WR_PRI_URGENCY +#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//GCEA_IO_RD_PRI_URGENCY_MASKING +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//GCEA_IO_WR_PRI_URGENCY_MASKING +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//GCEA_IO_RD_PRI_QUANT_PRI1 +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_RD_PRI_QUANT_PRI2 +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_RD_PRI_QUANT_PRI3 +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_WR_PRI_QUANT_PRI1 +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_WR_PRI_QUANT_PRI2 +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_IO_WR_PRI_QUANT_PRI3 +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//GCEA_SDP_ARB_DRAM +#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 +#define GCEA_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define GCEA_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING__SHIFT 0x16 +#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L +#define GCEA_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +#define GCEA_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING_MASK 0x00400000L +//GCEA_SDP_ARB_FINAL +#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define GCEA_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +#define GCEA_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +#define GCEA_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +#define GCEA_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +#define GCEA_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +#define GCEA_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +#define GCEA_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +#define GCEA_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +#define GCEA_SDP_ARB_FINAL__DRAM_BURST_STRETCH__SHIFT 0x1b +#define GCEA_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1c +#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +#define GCEA_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +#define GCEA_SDP_ARB_FINAL__DRAM_BURST_STRETCH_MASK 0x08000000L +#define GCEA_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x10000000L +//GCEA_SDP_DRAM_PRIORITY +#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//GCEA_SDP_IO_PRIORITY +#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//GCEA_SDP_CREDITS +#define GCEA_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define GCEA_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define GCEA_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT 0x18 +#define GCEA_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define GCEA_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define GCEA_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS_MASK 0x3F000000L +//GCEA_SDP_TAG_RESERVE0 +#define GCEA_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define GCEA_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define GCEA_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define GCEA_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define GCEA_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define GCEA_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define GCEA_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define GCEA_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//GCEA_SDP_TAG_RESERVE1 +#define GCEA_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define GCEA_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define GCEA_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define GCEA_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define GCEA_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define GCEA_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define GCEA_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define GCEA_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//GCEA_SDP_VCC_RESERVE0 +#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//GCEA_SDP_VCC_RESERVE1 +#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//GCEA_SDP_VCD_RESERVE0 +#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//GCEA_SDP_VCD_RESERVE1 +#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//GCEA_SDP_REQ_CNTL +#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 +#define GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 +#define GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa +#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +#define GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L +#define GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L +#define GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L +//GCEA_MISC +#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 +#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 +#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 +#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 +#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 +#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 +#define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 +#define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 +#define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 +#define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 +#define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa +#define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb +#define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc +#define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd +#define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe +#define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf +#define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 +#define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 +#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 +#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a +#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b +#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c +#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d +#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e +#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f +#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L +#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L +#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L +#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L +#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L +#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L +#define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L +#define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L +#define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L +#define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L +#define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L +#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L +#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L +#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L +#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L +#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L +#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L +#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L +//GCEA_LATENCY_SAMPLING +#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//GCEA_PERFCOUNTER_LO +#define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//GCEA_PERFCOUNTER_HI +#define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//GCEA_PERFCOUNTER0_CFG +#define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//GCEA_PERFCOUNTER1_CFG +#define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L + + +// addressBlock: xcd0_gc_ea_gceadec2 +//GCEA_PERFCOUNTER_RSLT_CNTL +#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//GCEA_MAM_CTRL +#define GCEA_MAM_CTRL__ADRAM_MODE__SHIFT 0x0 +#define GCEA_MAM_CTRL__ADRAM_COALESCE_DISABLE__SHIFT 0x2 +#define GCEA_MAM_CTRL__ARAM_FLUSH_CNTR_THRESHOLD__SHIFT 0x3 +#define GCEA_MAM_CTRL__ARAM_FLUSH_CNTR_DISABLE__SHIFT 0x6 +#define GCEA_MAM_CTRL__ARAM_FORCE_FLUSH__SHIFT 0x7 +#define GCEA_MAM_CTRL__ALOG_MODE1_FILTER1_THRESHOLD__SHIFT 0x8 +#define GCEA_MAM_CTRL__ALOG_MODE1_FILTER2_BYPASS__SHIFT 0xb +#define GCEA_MAM_CTRL__ALOG_ACTIVE__SHIFT 0xc +#define GCEA_MAM_CTRL__SDP_PRIORITY__SHIFT 0xd +#define GCEA_MAM_CTRL__CLIENT_ID__SHIFT 0x11 +#define GCEA_MAM_CTRL__MAM_DISABLE__SHIFT 0x16 +#define GCEA_MAM_CTRL__ARAM_FLUSH_RB_SIZE__SHIFT 0x17 +#define GCEA_MAM_CTRL__ALOG_MODE__SHIFT 0x1b +#define GCEA_MAM_CTRL__ALOG_MODE2_LOCK_WINDOW__SHIFT 0x1c +#define GCEA_MAM_CTRL__ALOG_TRACK_2M_SEGMENT__SHIFT 0x1f +#define GCEA_MAM_CTRL__ADRAM_MODE_MASK 0x00000003L +#define GCEA_MAM_CTRL__ADRAM_COALESCE_DISABLE_MASK 0x00000004L +#define GCEA_MAM_CTRL__ARAM_FLUSH_CNTR_THRESHOLD_MASK 0x00000038L +#define GCEA_MAM_CTRL__ARAM_FLUSH_CNTR_DISABLE_MASK 0x00000040L +#define GCEA_MAM_CTRL__ARAM_FORCE_FLUSH_MASK 0x00000080L +#define GCEA_MAM_CTRL__ALOG_MODE1_FILTER1_THRESHOLD_MASK 0x00000700L +#define GCEA_MAM_CTRL__ALOG_MODE1_FILTER2_BYPASS_MASK 0x00000800L +#define GCEA_MAM_CTRL__ALOG_ACTIVE_MASK 0x00001000L +#define GCEA_MAM_CTRL__SDP_PRIORITY_MASK 0x0001E000L +#define GCEA_MAM_CTRL__CLIENT_ID_MASK 0x003E0000L +#define GCEA_MAM_CTRL__MAM_DISABLE_MASK 0x00400000L +#define GCEA_MAM_CTRL__ARAM_FLUSH_RB_SIZE_MASK 0x07800000L +#define GCEA_MAM_CTRL__ALOG_MODE_MASK 0x08000000L +#define GCEA_MAM_CTRL__ALOG_MODE2_LOCK_WINDOW_MASK 0x70000000L +#define GCEA_MAM_CTRL__ALOG_TRACK_2M_SEGMENT_MASK 0x80000000L +//GCEA_MAM_CTRL2 +#define GCEA_MAM_CTRL2__ALOG_MODE2_INTR_THRESHOLD__SHIFT 0x0 +#define GCEA_MAM_CTRL2__ALOG_SPACE_EN__SHIFT 0x2 +#define GCEA_MAM_CTRL2__ARAM_FLUSH_SNOOP_EN__SHIFT 0x5 +#define GCEA_MAM_CTRL2__ARAM_FLUSH_NOALLOC__SHIFT 0x6 +#define GCEA_MAM_CTRL2__RESERVED_FIELD__SHIFT 0x7 +#define GCEA_MAM_CTRL2__ADDR_HI__SHIFT 0x18 +#define GCEA_MAM_CTRL2__ALOG_MODE2_INTR_THRESHOLD_MASK 0x00000003L +#define GCEA_MAM_CTRL2__ALOG_SPACE_EN_MASK 0x0000001CL +#define GCEA_MAM_CTRL2__ARAM_FLUSH_SNOOP_EN_MASK 0x00000020L +#define GCEA_MAM_CTRL2__ARAM_FLUSH_NOALLOC_MASK 0x00000040L +#define GCEA_MAM_CTRL2__RESERVED_FIELD_MASK 0x00FFFF80L +#define GCEA_MAM_CTRL2__ADDR_HI_MASK 0xFF000000L +//GCEA_UE_ERR_STATUS_LO +#define GCEA_UE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define GCEA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define GCEA_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define GCEA_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define GCEA_UE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define GCEA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define GCEA_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define GCEA_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//GCEA_UE_ERR_STATUS_HI +#define GCEA_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define GCEA_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define GCEA_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define GCEA_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define GCEA_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define GCEA_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define GCEA_UE_ERR_STATUS_HI__RESERVED_FIELD__SHIFT 0x1d +#define GCEA_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define GCEA_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define GCEA_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define GCEA_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define GCEA_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define GCEA_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define GCEA_UE_ERR_STATUS_HI__RESERVED_FIELD_MASK 0xE0000000L +//GCEA_DSM_CNTL +#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +//GCEA_DSM_CNTLA +#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//GCEA_DSM_CNTLB +#define GCEA_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define GCEA_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define GCEA_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define GCEA_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define GCEA_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define GCEA_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define GCEA_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define GCEA_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define GCEA_DSM_CNTLB__MAM_A0MEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define GCEA_DSM_CNTLB__MAM_A0MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define GCEA_DSM_CNTLB__MAM_A1MEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define GCEA_DSM_CNTLB__MAM_A1MEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define GCEA_DSM_CNTLB__MAM_A2MEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define GCEA_DSM_CNTLB__MAM_A2MEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define GCEA_DSM_CNTLB__MAM_A3MEM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define GCEA_DSM_CNTLB__MAM_A3MEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define GCEA_DSM_CNTLB__MAM_AFMEM_DSM_IRRITATOR_DATA__SHIFT 0x18 +#define GCEA_DSM_CNTLB__MAM_AFMEM_ENABLE_SINGLE_WRITE__SHIFT 0x1a +#define GCEA_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define GCEA_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define GCEA_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define GCEA_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define GCEA_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define GCEA_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define GCEA_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define GCEA_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define GCEA_DSM_CNTLB__MAM_A0MEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define GCEA_DSM_CNTLB__MAM_A0MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define GCEA_DSM_CNTLB__MAM_A1MEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define GCEA_DSM_CNTLB__MAM_A1MEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define GCEA_DSM_CNTLB__MAM_A2MEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define GCEA_DSM_CNTLB__MAM_A2MEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define GCEA_DSM_CNTLB__MAM_A3MEM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define GCEA_DSM_CNTLB__MAM_A3MEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +#define GCEA_DSM_CNTLB__MAM_AFMEM_DSM_IRRITATOR_DATA_MASK 0x03000000L +#define GCEA_DSM_CNTLB__MAM_AFMEM_ENABLE_SINGLE_WRITE_MASK 0x04000000L +//GCEA_DSM_CNTL2 +#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define GCEA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//GCEA_DSM_CNTL2A +#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +//GCEA_DSM_CNTL2B +#define GCEA_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define GCEA_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define GCEA_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define GCEA_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define GCEA_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define GCEA_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define GCEA_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define GCEA_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define GCEA_DSM_CNTL2B__MAM_A0MEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define GCEA_DSM_CNTL2B__MAM_A0MEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define GCEA_DSM_CNTL2B__MAM_A1MEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define GCEA_DSM_CNTL2B__MAM_A1MEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define GCEA_DSM_CNTL2B__MAM_A2MEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define GCEA_DSM_CNTL2B__MAM_A2MEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define GCEA_DSM_CNTL2B__MAM_A3MEM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define GCEA_DSM_CNTL2B__MAM_A3MEM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define GCEA_DSM_CNTL2B__MAM_AFMEM_ENABLE_ERROR_INJECT__SHIFT 0x18 +#define GCEA_DSM_CNTL2B__MAM_AFMEM_SELECT_INJECT_DELAY__SHIFT 0x1a +#define GCEA_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define GCEA_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define GCEA_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define GCEA_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define GCEA_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define GCEA_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define GCEA_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define GCEA_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define GCEA_DSM_CNTL2B__MAM_A0MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define GCEA_DSM_CNTL2B__MAM_A0MEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define GCEA_DSM_CNTL2B__MAM_A1MEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define GCEA_DSM_CNTL2B__MAM_A1MEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define GCEA_DSM_CNTL2B__MAM_A2MEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define GCEA_DSM_CNTL2B__MAM_A2MEM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define GCEA_DSM_CNTL2B__MAM_A3MEM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define GCEA_DSM_CNTL2B__MAM_A3MEM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define GCEA_DSM_CNTL2B__MAM_AFMEM_ENABLE_ERROR_INJECT_MASK 0x03000000L +#define GCEA_DSM_CNTL2B__MAM_AFMEM_SELECT_INJECT_DELAY_MASK 0x04000000L +//GCEA_TCC_XBR_CREDITS +#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT 0x0 +#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT 0x6 +#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT__SHIFT 0x8 +#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE__SHIFT 0xe +#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT 0x10 +#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT 0x16 +#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT__SHIFT 0x18 +#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE__SHIFT 0x1e +#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT_MASK 0x0000003FL +#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE_MASK 0x000000C0L +#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT_MASK 0x00003F00L +#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE_MASK 0x0000C000L +#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT_MASK 0x003F0000L +#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE_MASK 0x00C00000L +#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT_MASK 0x3F000000L +#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE_MASK 0xC0000000L +//GCEA_TCC_XBR_MAXBURST +#define GCEA_TCC_XBR_MAXBURST__DRAM_RD__SHIFT 0x0 +#define GCEA_TCC_XBR_MAXBURST__IO_RD__SHIFT 0x4 +#define GCEA_TCC_XBR_MAXBURST__DRAM_WR__SHIFT 0x8 +#define GCEA_TCC_XBR_MAXBURST__IO_WR__SHIFT 0xc +#define GCEA_TCC_XBR_MAXBURST__DRAM_RD_MASK 0x0000000FL +#define GCEA_TCC_XBR_MAXBURST__IO_RD_MASK 0x000000F0L +#define GCEA_TCC_XBR_MAXBURST__DRAM_WR_MASK 0x00000F00L +#define GCEA_TCC_XBR_MAXBURST__IO_WR_MASK 0x0000F000L +//GCEA_PROBE_CNTL +#define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT 0x0 +#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT 0x5 +#define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK 0x0000001FL +#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK 0x00000020L +//GCEA_PROBE_MAP +#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC__SHIFT 0x0 +#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC__SHIFT 0x1 +#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC__SHIFT 0x2 +#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC__SHIFT 0x3 +#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC__SHIFT 0x4 +#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC__SHIFT 0x5 +#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC__SHIFT 0x6 +#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC__SHIFT 0x7 +#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC__SHIFT 0x8 +#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC__SHIFT 0x9 +#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC__SHIFT 0xa +#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC__SHIFT 0xb +#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC__SHIFT 0xc +#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC__SHIFT 0xd +#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC__SHIFT 0xe +#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC__SHIFT 0xf +#define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT 0x10 +#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC_MASK 0x00000001L +#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC_MASK 0x00000002L +#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC_MASK 0x00000004L +#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC_MASK 0x00000008L +#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC_MASK 0x00000010L +#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC_MASK 0x00000020L +#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC_MASK 0x00000040L +#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC_MASK 0x00000080L +#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC_MASK 0x00000100L +#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC_MASK 0x00000200L +#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC_MASK 0x00000400L +#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC_MASK 0x00000800L +#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC_MASK 0x00001000L +#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC_MASK 0x00002000L +#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC_MASK 0x00004000L +#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC_MASK 0x00008000L +#define GCEA_PROBE_MAP__INTLV_SIZE_MASK 0x00030000L +//GCEA_ERR_STATUS +#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define GCEA_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define GCEA_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe +#define GCEA_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf +#define GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 +#define GCEA_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 +#define GCEA_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 +#define GCEA_ERR_STATUS__FUE_FLAG_CLIENT__SHIFT 0x13 +#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define GCEA_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +#define GCEA_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L +#define GCEA_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L +#define GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L +#define GCEA_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L +#define GCEA_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L +#define GCEA_ERR_STATUS__FUE_FLAG_CLIENT_MASK 0x00080000L +//GCEA_MISC2 +#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 +#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 +#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 +#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 +#define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc +#define GCEA_MISC2__BLOCK_REQUESTS__SHIFT 0xd +#define GCEA_MISC2__REQUESTS_BLOCKED__SHIFT 0xe +#define GCEA_MISC2__FGCLKEN_OVERRIDE__SHIFT 0xf +#define GCEA_MISC2__DRAM_RD_THROTTLE__SHIFT 0x10 +#define GCEA_MISC2__DRAM_WR_THROTTLE__SHIFT 0x11 +#define GCEA_MISC2__GMI_RD_THROTTLE__SHIFT 0x12 +#define GCEA_MISC2__GMI_WR_THROTTLE__SHIFT 0x13 +#define GCEA_MISC2__CONTAIN_ILLEGAL_OP__SHIFT 0x14 +#define GCEA_MISC2__REPORT_ILLEGAL_OP__SHIFT 0x15 +#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L +#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L +#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL +#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L +#define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L +#define GCEA_MISC2__BLOCK_REQUESTS_MASK 0x00002000L +#define GCEA_MISC2__REQUESTS_BLOCKED_MASK 0x00004000L +#define GCEA_MISC2__FGCLKEN_OVERRIDE_MASK 0x00008000L +#define GCEA_MISC2__DRAM_RD_THROTTLE_MASK 0x00010000L +#define GCEA_MISC2__DRAM_WR_THROTTLE_MASK 0x00020000L +#define GCEA_MISC2__GMI_RD_THROTTLE_MASK 0x00040000L +#define GCEA_MISC2__GMI_WR_THROTTLE_MASK 0x00080000L +#define GCEA_MISC2__CONTAIN_ILLEGAL_OP_MASK 0x00100000L +#define GCEA_MISC2__REPORT_ILLEGAL_OP_MASK 0x00200000L +//GCEA_SDP_BACKDOOR_CMDCREDITS0 +#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED__SHIFT 0x0 +#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED__SHIFT 0x7 +#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED__SHIFT 0xe +#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED__SHIFT 0x15 +#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED__SHIFT 0x1c +#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED_MASK 0x0000007FL +#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED_MASK 0x00003F80L +#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED_MASK 0x001FC000L +#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L +#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED_MASK 0xF0000000L +//GCEA_SDP_BACKDOOR_CMDCREDITS1 +#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED__SHIFT 0x0 +#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED__SHIFT 0x3 +#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa +#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED__SHIFT 0x11 +#define GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED__SHIFT 0x18 +#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED_MASK 0x00000007L +#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED_MASK 0x000003F8L +#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L +#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L +#define GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED_MASK 0x7F000000L +//GCEA_SDP_BACKDOOR_DATACREDITS0 +#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED__SHIFT 0x0 +#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED__SHIFT 0x7 +#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED__SHIFT 0xe +#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED__SHIFT 0x15 +#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED__SHIFT 0x1c +#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED_MASK 0x0000007FL +#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED_MASK 0x00003F80L +#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED_MASK 0x001FC000L +#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L +#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED_MASK 0xF0000000L +//GCEA_SDP_BACKDOOR_DATACREDITS1 +#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED__SHIFT 0x0 +#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED__SHIFT 0x3 +#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa +#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED__SHIFT 0x11 +#define GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED__SHIFT 0x18 +#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED_MASK 0x00000007L +#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED_MASK 0x000003F8L +#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L +#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L +#define GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED_MASK 0x7F000000L +//GCEA_SDP_BACKDOOR_MISCCREDITS +#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT 0x0 +#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT 0x8 +#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED__SHIFT 0x10 +#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED__SHIFT 0x17 +#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK 0x000000FFL +#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK 0x0000FF00L +#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED_MASK 0x007F0000L +#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED_MASK 0x3F800000L +//GCEA_CE_ERR_STATUS_LO +#define GCEA_CE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define GCEA_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define GCEA_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define GCEA_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define GCEA_CE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define GCEA_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define GCEA_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define GCEA_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//GCEA_CE_ERR_STATUS_HI +#define GCEA_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD0__SHIFT 0x1 +#define GCEA_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define GCEA_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define GCEA_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define GCEA_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD1__SHIFT 0x1b +#define GCEA_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD0_MASK 0x00000002L +#define GCEA_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define GCEA_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define GCEA_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define GCEA_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD1_MASK 0xF8000000L +//GCEA_SDP_ENABLE +#define GCEA_SDP_ENABLE__ENABLE__SHIFT 0x0 +#define GCEA_SDP_ENABLE__ENABLE_MASK 0x00000001L + + +// addressBlock: xcd0_gc_ea_pwrdec +//GCEA_ICG_CTRL +#define GCEA_ICG_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x0 +#define GCEA_ICG_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1 +#define GCEA_ICG_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x2 +#define GCEA_ICG_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x3 +#define GCEA_ICG_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x00000001L +#define GCEA_ICG_CTRL__SOFT_OVERRIDE_READ_MASK 0x00000002L +#define GCEA_ICG_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x00000004L +#define GCEA_ICG_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x00000008L + + +// addressBlock: xcd0_gc_rmi_rmidec +//RMI_GENERAL_CNTL +#define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0 +#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1 +#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT 0x11 +#define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13 +#define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT 0x14 +#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15 +#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT 0x19 +#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT 0x1a +#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT 0x1b +#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT 0x1c +#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT 0x1d +#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT 0x1e +#define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L +#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL +#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK 0x00060000L +#define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L +#define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK 0x00100000L +#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L +#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK 0x02000000L +#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK 0x04000000L +#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK 0x08000000L +#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK 0x10000000L +#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK 0x20000000L +#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK 0x40000000L +//RMI_GENERAL_CNTL1 +#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0 +#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4 +#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6 +#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8 +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9 +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xa +#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT 0xb +#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT 0xc +#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL +#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L +#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L +#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000200L +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000400L +#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK 0x00000800L +#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK 0x00001000L +//RMI_GENERAL_STATUS +#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0 +#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1 +#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2 +#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3 +#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4 +#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5 +#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT 0x6 +#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7 +#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8 +#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9 +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa +#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb +#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc +#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd +#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf +#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x10 +#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x11 +#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT 0x12 +#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT 0x13 +#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT 0x14 +#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT 0x15 +#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT 0x1d +#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT 0x1e +#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f +#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L +#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L +#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L +#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L +#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L +#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L +#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK 0x00000040L +#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L +#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L +#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L +#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L +#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L +#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L +#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L +#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00010000L +#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00020000L +#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK 0x00040000L +#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK 0x00080000L +#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK 0x00100000L +#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK 0x1FE00000L +#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK 0x20000000L +#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK 0x40000000L +#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L +//RMI_SUBBLOCK_STATUS0 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11 +#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L +#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L +//RMI_SUBBLOCK_STATUS1 +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa +#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14 +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L +#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L +//RMI_SUBBLOCK_STATUS2 +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9 +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L +//RMI_SUBBLOCK_STATUS3 +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L +//RMI_XBAR_CONFIG +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0 +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2 +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6 +#define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7 +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8 +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc +#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd +#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT 0xe +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L +#define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L +#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L +#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK 0x00004000L +//RMI_PROBE_POP_LOGIC_CNTL +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0 +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7 +#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8 +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11 +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L +#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L +//RMI_UTC_XNACK_N_MISC_CNTL +#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0 +#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8 +#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc +#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd +#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL +#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L +#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L +#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L +//RMI_DEMUX_CNTL +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT 0x0 +#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x1 +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x4 +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6 +#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT 0x10 +#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x11 +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x14 +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16 +#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK 0x00000001L +#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000002L +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK 0x00000030L +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L +#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK 0x00010000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00020000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00300000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L +//RMI_UTCL1_CNTL1 +#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 +#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 +#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 +#define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 +#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 +#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 +#define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 +#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 +#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 +#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 +#define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a +#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L +#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L +#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L +#define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L +#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L +#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L +#define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L +#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L +#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L +#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L +#define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L +#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//RMI_UTCL1_CNTL2 +#define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0 +#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa +#define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb +#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc +#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd +#define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf +#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10 +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13 +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14 +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15 +#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19 +#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL +#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L +#define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L +#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L +#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L +#define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L +#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L +#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L +#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +//RMI_UTC_UNIT_CONFIG +#define RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN__SHIFT 0x0 +#define RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN_MASK 0x0000FFFFL +//RMI_TCIW_FORMATTER0_CNTL +#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT 0x0 +#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT 0x1 +#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 +#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT 0x13 +#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b +#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT 0x1c +#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d +#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT 0x1e +#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f +#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK 0x00000001L +#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK 0x000001FEL +#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L +#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK 0x07F80000L +#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L +#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK 0x10000000L +#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L +#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK 0x40000000L +#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L +//RMI_TCIW_FORMATTER1_CNTL +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0 +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1 +#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 +#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT 0x13 +#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b +#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT 0x1c +#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e +#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL +#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L +#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK 0x07F80000L +#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L +#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK 0x10000000L +#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L +#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L +//RMI_SCOREBOARD_CNTL +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0 +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1 +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2 +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3 +#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT 0x4 +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5 +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6 +#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT 0x7 +#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT 0x8 +#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9 +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L +#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK 0x00000010L +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L +#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK 0x00000080L +#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK 0x00000100L +#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L +//RMI_SCOREBOARD_STATUS0 +#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14 +#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15 +#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L +#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L +//RMI_SCOREBOARD_STATUS1 +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0 +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd +#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L +#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L +//RMI_SCOREBOARD_STATUS2 +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0 +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19 +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L +//RMI_XBAR_ARBITER_CONFIG +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L +//RMI_XBAR_ARBITER_CONFIG_1 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT 0x10 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT 0x18 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK 0x00FF0000L +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK 0xFF000000L +//RMI_CLOCK_CNTRL +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0 +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5 +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf +#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT 0x14 +#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT 0x19 +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L +#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK 0x01F00000L +#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK 0x3E000000L +//RMI_UTCL1_STATUS +#define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +//RMI_XNACK_DEBUG +#define RMI_XNACK_DEBUG__XNACK_PER_VMID__SHIFT 0x0 +#define RMI_XNACK_DEBUG__XNACK_PER_VMID_MASK 0x0000FFFFL +//RMI_SPARE +#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT 0x0 +#define RMI_SPARE__SPARE_BIT_1__SHIFT 0x1 +#define RMI_SPARE__SPARE_BIT_2__SHIFT 0x2 +#define RMI_SPARE__SPARE_BIT_3__SHIFT 0x3 +#define RMI_SPARE__SPARE_BIT_4__SHIFT 0x4 +#define RMI_SPARE__SPARE_BIT_5__SHIFT 0x5 +#define RMI_SPARE__SPARE_BIT_6__SHIFT 0x6 +#define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7 +#define RMI_SPARE__SPARE_BIT_8_0__SHIFT 0x8 +#define RMI_SPARE__SPARE_BIT_16_0__SHIFT 0x10 +#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK 0x00000001L +#define RMI_SPARE__SPARE_BIT_1_MASK 0x00000002L +#define RMI_SPARE__SPARE_BIT_2_MASK 0x00000004L +#define RMI_SPARE__SPARE_BIT_3_MASK 0x00000008L +#define RMI_SPARE__SPARE_BIT_4_MASK 0x00000010L +#define RMI_SPARE__SPARE_BIT_5_MASK 0x00000020L +#define RMI_SPARE__SPARE_BIT_6_MASK 0x00000040L +#define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L +#define RMI_SPARE__SPARE_BIT_8_0_MASK 0x0000FF00L +#define RMI_SPARE__SPARE_BIT_16_0_MASK 0xFFFF0000L +//RMI_SPARE_1 +#define RMI_SPARE_1__SPARE_BIT_8__SHIFT 0x0 +#define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1 +#define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2 +#define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3 +#define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4 +#define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5 +#define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6 +#define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7 +#define RMI_SPARE_1__SPARE_BIT_8_1__SHIFT 0x8 +#define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10 +#define RMI_SPARE_1__SPARE_BIT_8_MASK 0x00000001L +#define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L +#define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L +#define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L +#define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L +#define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L +#define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L +#define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L +#define RMI_SPARE_1__SPARE_BIT_8_1_MASK 0x0000FF00L +#define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L +//RMI_SPARE_2 +#define RMI_SPARE_2__SPARE_BIT_16__SHIFT 0x0 +#define RMI_SPARE_2__SPARE_BIT_17__SHIFT 0x1 +#define RMI_SPARE_2__SPARE_BIT_18__SHIFT 0x2 +#define RMI_SPARE_2__SPARE_BIT_19__SHIFT 0x3 +#define RMI_SPARE_2__SPARE_BIT_20__SHIFT 0x4 +#define RMI_SPARE_2__SPARE_BIT_21__SHIFT 0x5 +#define RMI_SPARE_2__SPARE_BIT_22__SHIFT 0x6 +#define RMI_SPARE_2__SPARE_BIT_23__SHIFT 0x7 +#define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT 0x8 +#define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT 0xc +#define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10 +#define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18 +#define RMI_SPARE_2__SPARE_BIT_16_MASK 0x00000001L +#define RMI_SPARE_2__SPARE_BIT_17_MASK 0x00000002L +#define RMI_SPARE_2__SPARE_BIT_18_MASK 0x00000004L +#define RMI_SPARE_2__SPARE_BIT_19_MASK 0x00000008L +#define RMI_SPARE_2__SPARE_BIT_20_MASK 0x00000010L +#define RMI_SPARE_2__SPARE_BIT_21_MASK 0x00000020L +#define RMI_SPARE_2__SPARE_BIT_22_MASK 0x00000040L +#define RMI_SPARE_2__SPARE_BIT_23_MASK 0x00000080L +#define RMI_SPARE_2__SPARE_BIT_4_0_MASK 0x00000F00L +#define RMI_SPARE_2__SPARE_BIT_4_1_MASK 0x0000F000L +#define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L +#define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L + + +// addressBlock: xcd0_gc_utcl2_atcl2dec +//ATC_L2_CNTL +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x8 +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0xb +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xe +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xf +#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x10 +#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x13 +#define ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x14 +#define ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT 0x16 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x00000300L +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00001800L +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00004000L +#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00008000L +#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00070000L +#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00080000L +#define ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK 0x00300000L +#define ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK 0x0FC00000L +//ATC_L2_CNTL2 +#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 +#define ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT 0x6 +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x9 +#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xb +#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0xc +#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xf +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x12 +#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL +#define ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK 0x000001C0L +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x00000600L +#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000800L +#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00007000L +#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00038000L +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00FC0000L +//ATC_L2_CACHE_DATA0 +#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 +#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 +#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 +#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 +#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L +#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L +#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL +#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L +//ATC_L2_CACHE_DATA1 +#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 +#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL +//ATC_L2_CACHE_DATA2 +#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 +#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL +//ATC_L2_CACHE_DATA3 +#define ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 +#define ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL +//ATC_L2_CNTL3 +#define ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE__SHIFT 0x6 +#define ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE__SHIFT 0xc +#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x12 +#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x15 +#define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x1b +#define ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0x1e +#define ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE_MASK 0x0000003FL +#define ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE_MASK 0x00000FC0L +#define ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE_MASK 0x0003F000L +#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x001C0000L +#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x07E00000L +#define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x38000000L +#define ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x40000000L +//ATC_L2_STATUS +#define ATC_L2_STATUS__BUSY__SHIFT 0x0 +#define ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS__SHIFT 0x1 +#define ATC_L2_STATUS__BUSY_MASK 0x00000001L +#define ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS_MASK 0x00000002L +//ATC_L2_STATUS2 +#define ATC_L2_STATUS2__UCE_MEM_ADDR__SHIFT 0x0 +#define ATC_L2_STATUS2__UCE_MEM_INST__SHIFT 0xc +#define ATC_L2_STATUS2__UCE_SRT_CACHE__SHIFT 0x14 +#define ATC_L2_STATUS2__UCE__SHIFT 0x15 +#define ATC_L2_STATUS2__UCE_MEM_ADDR_MASK 0x00000FFFL +#define ATC_L2_STATUS2__UCE_MEM_INST_MASK 0x000FF000L +#define ATC_L2_STATUS2__UCE_SRT_CACHE_MASK 0x00100000L +#define ATC_L2_STATUS2__UCE_MASK 0x00200000L +//ATC_L2_MISC_CG +#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 +#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 +#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L +#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L +#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L +//ATC_L2_MEM_POWER_LS +#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//ATC_L2_CGTT_CLK_CTRL +#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 +#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 +#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L +#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L +//ATC_L2_CACHE_4K_DSM_INDEX +#define ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT 0x0 +#define ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK 0x000000FFL +//ATC_L2_CACHE_32K_DSM_INDEX +#define ATC_L2_CACHE_32K_DSM_INDEX__INDEX__SHIFT 0x0 +#define ATC_L2_CACHE_32K_DSM_INDEX__INDEX_MASK 0x000000FFL +//ATC_L2_CACHE_2M_DSM_INDEX +#define ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT 0x0 +#define ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK 0x000000FFL +//ATC_L2_CACHE_4K_DSM_CNTL +#define ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 +#define ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc +#define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT 0xd +#define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT 0xf +#define ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT 0x11 +#define ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L +#define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L +#define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK 0x00018000L +#define ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK 0x00020000L +//ATC_L2_CACHE_32K_DSM_CNTL +#define ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 +#define ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc +#define ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT__SHIFT 0xd +#define ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT__SHIFT 0xf +#define ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE__SHIFT 0x11 +#define ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L +#define ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L +#define ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT_MASK 0x00018000L +#define ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE_MASK 0x00020000L +//ATC_L2_CACHE_2M_DSM_CNTL +#define ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 +#define ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc +#define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT 0xd +#define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT 0xf +#define ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT 0x11 +#define ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L +#define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK 0x00006000L +#define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK 0x00018000L +#define ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK 0x00020000L +//ATC_L2_CNTL4 +#define ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x0 +#define ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0xa +#define ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000003FFL +#define ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000FFC00L +//ATC_L2_MM_GROUP_RT_CLASSES +#define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0 +#define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL +//ATC_L2_UE_ERR_STATUS_LO +#define ATC_L2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define ATC_L2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define ATC_L2_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define ATC_L2_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define ATC_L2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define ATC_L2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define ATC_L2_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define ATC_L2_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//ATC_L2_UE_ERR_STATUS_HI +#define ATC_L2_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define ATC_L2_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define ATC_L2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define ATC_L2_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define ATC_L2_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define ATC_L2_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define ATC_L2_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define ATC_L2_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define ATC_L2_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define ATC_L2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define ATC_L2_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define ATC_L2_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define ATC_L2_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define ATC_L2_UE_ERR_STATUS_HI__RESERVED_MASK 0x60000000L +//ATC_L2_CE_ERR_STATUS_LO +#define ATC_L2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define ATC_L2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define ATC_L2_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define ATC_L2_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define ATC_L2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define ATC_L2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define ATC_L2_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define ATC_L2_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//ATC_L2_CE_ERR_STATUS_HI +#define ATC_L2_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define ATC_L2_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define ATC_L2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define ATC_L2_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define ATC_L2_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define ATC_L2_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define ATC_L2_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define ATC_L2_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define ATC_L2_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define ATC_L2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define ATC_L2_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define ATC_L2_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define ATC_L2_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define ATC_L2_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L + + +// addressBlock: xcd0_gc_utcl2_vml2pfdec +//VM_L2_CNTL +#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa +#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 +#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a +#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L +#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L +#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L +//VM_L2_CNTL2 +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 +#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a +#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L +#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L +#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L +//VM_L2_CNTL3 +#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d +#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e +#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f +#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L +#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L +#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L +//VM_L2_STATUS +#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 +#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 +#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 +#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 +#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 +#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 +#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL +#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L +#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L +#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L +#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L +#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L +//VM_DUMMY_PAGE_FAULT_CNTL +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL +//VM_DUMMY_PAGE_FAULT_ADDR_LO32 +#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 +#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//VM_DUMMY_PAGE_FAULT_ADDR_HI32 +#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 +#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL +//VM_L2_PROTECTION_FAULT_CNTL +#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 +#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 +#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 +#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 +#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 +#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 +#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 +#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd +#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d +#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e +#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f +#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L +#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L +#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L +#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L +#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L +#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L +#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L +#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L +#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L +#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L +#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L +#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L +#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L +//VM_L2_PROTECTION_FAULT_CNTL2 +#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 +#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 +#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 +#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 +#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL +#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L +#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L +#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L +#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L +//VM_L2_PROTECTION_FAULT_MM_CNTL3 +#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//VM_L2_PROTECTION_FAULT_MM_CNTL4 +#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//VM_L2_PROTECTION_FAULT_STATUS +#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 +#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 +#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 +#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 +#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 +#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 +#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 +#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 +#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 +#define VM_L2_PROTECTION_FAULT_STATUS__UCE__SHIFT 0x1d +#define VM_L2_PROTECTION_FAULT_STATUS__FED__SHIFT 0x1e +#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L +#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL +#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L +#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L +#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L +#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L +#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L +#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L +#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L +#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L +#define VM_L2_PROTECTION_FAULT_STATUS__UCE_MASK 0x20000000L +#define VM_L2_PROTECTION_FAULT_STATUS__FED_MASK 0x40000000L +//VM_L2_PROTECTION_FAULT_ADDR_LO32 +#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//VM_L2_PROTECTION_FAULT_ADDR_HI32 +#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 +#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 +#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL +//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL +//VM_L2_CNTL4 +#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 +#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 +#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 +#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 +#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 +#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c +#define VM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d +#define VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e +#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL +#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L +#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L +#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L +#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L +#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L +#define VM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L +#define VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L +//VM_L2_CNTL5 +#define VM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT 0x0 +#define VM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT 0x1 +#define VM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK 0x00000001L +#define VM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK 0x00000002L +//VM_L2_MM_GROUP_RT_CLASSES +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L +#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L +//VM_L2_BANK_SELECT_RESERVED_CID +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +//VM_L2_BANK_SELECT_RESERVED_CID2 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +//VM_L2_CACHE_PARITY_CNTL +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L +#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L +#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L +//VM_L2_CGTT_CLK_CTRL +#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 +#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 +#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L +#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L +//VM_L2_CGTT_BUSY_CTRL +#define VM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 +#define VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x4 +#define VM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000000FL +#define VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000010L +//VML2_MEM_ECC_INDEX +#define VML2_MEM_ECC_INDEX__INDEX__SHIFT 0x0 +#define VML2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL +//VML2_WALKER_MEM_ECC_INDEX +#define VML2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT 0x0 +#define VML2_WALKER_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL +//UTCL2_MEM_ECC_INDEX +#define UTCL2_MEM_ECC_INDEX__INDEX__SHIFT 0x0 +#define UTCL2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL +//VML2_MEM_ECC_CNTL +#define VML2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0 +#define VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define VML2_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc +#define VML2_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe +#define VML2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10 +#define VML2_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11 +#define VML2_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define VML2_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L +#define VML2_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L +#define VML2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L +#define VML2_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L +//VML2_WALKER_MEM_ECC_CNTL +#define VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0 +#define VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc +#define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe +#define VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10 +#define VML2_WALKER_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11 +#define VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L +#define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L +#define VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L +#define VML2_WALKER_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L +//UTCL2_MEM_ECC_CNTL +#define UTCL2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0 +#define UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define UTCL2_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc +#define UTCL2_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe +#define UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10 +#define UTCL2_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11 +#define UTCL2_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define UTCL2_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L +#define UTCL2_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L +#define UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L +#define UTCL2_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L +//VML2_MEM_ECC_STATUS +#define VML2_MEM_ECC_STATUS__UCE__SHIFT 0x0 +#define VML2_MEM_ECC_STATUS__FED__SHIFT 0x1 +#define VML2_MEM_ECC_STATUS__UCE_MASK 0x00000001L +#define VML2_MEM_ECC_STATUS__FED_MASK 0x00000002L +//VML2_WALKER_MEM_ECC_STATUS +#define VML2_WALKER_MEM_ECC_STATUS__UCE__SHIFT 0x0 +#define VML2_WALKER_MEM_ECC_STATUS__FED__SHIFT 0x1 +#define VML2_WALKER_MEM_ECC_STATUS__UCE_MASK 0x00000001L +#define VML2_WALKER_MEM_ECC_STATUS__FED_MASK 0x00000002L +//UTCL2_MEM_ECC_STATUS +#define UTCL2_MEM_ECC_STATUS__UCE__SHIFT 0x0 +#define UTCL2_MEM_ECC_STATUS__FED__SHIFT 0x1 +#define UTCL2_MEM_ECC_STATUS__UCE_MASK 0x00000001L +#define UTCL2_MEM_ECC_STATUS__FED_MASK 0x00000002L +//UTCL2_EDC_MODE +#define UTCL2_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf +#define UTCL2_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define UTCL2_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define UTCL2_EDC_MODE__DED_MODE__SHIFT 0x14 +#define UTCL2_EDC_MODE__PROP_FED__SHIFT 0x1d +#define UTCL2_EDC_MODE__BYPASS__SHIFT 0x1f +#define UTCL2_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L +#define UTCL2_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define UTCL2_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define UTCL2_EDC_MODE__DED_MODE_MASK 0x00300000L +#define UTCL2_EDC_MODE__PROP_FED_MASK 0x20000000L +#define UTCL2_EDC_MODE__BYPASS_MASK 0x80000000L +//UTCL2_EDC_CONFIG +#define UTCL2_EDC_CONFIG__WRITE_DIS__SHIFT 0x0 +#define UTCL2_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define UTCL2_EDC_CONFIG__WRITE_DIS_MASK 0x00000001L +#define UTCL2_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +//VML2_UE_ERR_STATUS_LO +#define VML2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define VML2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define VML2_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define VML2_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define VML2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define VML2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define VML2_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define VML2_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//VML2_WALKER_UE_ERR_STATUS_LO +#define VML2_WALKER_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define VML2_WALKER_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define VML2_WALKER_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define VML2_WALKER_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//UTCL2_UE_ERR_STATUS_LO +#define UTCL2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define UTCL2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define UTCL2_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define UTCL2_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define UTCL2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define UTCL2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define UTCL2_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define UTCL2_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//VML2_UE_ERR_STATUS_HI +#define VML2_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define VML2_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define VML2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define VML2_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define VML2_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define VML2_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define VML2_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define VML2_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define VML2_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define VML2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define VML2_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define VML2_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define VML2_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define VML2_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//VML2_WALKER_UE_ERR_STATUS_HI +#define VML2_WALKER_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define VML2_WALKER_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define VML2_WALKER_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define VML2_WALKER_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define VML2_WALKER_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define VML2_WALKER_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define VML2_WALKER_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define VML2_WALKER_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define VML2_WALKER_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define VML2_WALKER_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//UTCL2_UE_ERR_STATUS_HI +#define UTCL2_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define UTCL2_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define UTCL2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define UTCL2_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define UTCL2_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define UTCL2_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define UTCL2_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define UTCL2_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define UTCL2_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define UTCL2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define UTCL2_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define UTCL2_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define UTCL2_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define UTCL2_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//VML2_CE_ERR_STATUS_LO +#define VML2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define VML2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define VML2_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define VML2_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define VML2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define VML2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define VML2_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define VML2_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//VML2_WALKER_CE_ERR_STATUS_LO +#define VML2_WALKER_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define VML2_WALKER_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define VML2_WALKER_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define VML2_WALKER_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//UTCL2_CE_ERR_STATUS_LO +#define UTCL2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define UTCL2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define UTCL2_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define UTCL2_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define UTCL2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define UTCL2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define UTCL2_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define UTCL2_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//VML2_CE_ERR_STATUS_HI +#define VML2_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define VML2_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define VML2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define VML2_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define VML2_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define VML2_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define VML2_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define VML2_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define VML2_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define VML2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define VML2_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define VML2_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define VML2_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define VML2_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L +//VML2_WALKER_CE_ERR_STATUS_HI +#define VML2_WALKER_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define VML2_WALKER_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define VML2_WALKER_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define VML2_WALKER_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define VML2_WALKER_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define VML2_WALKER_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define VML2_WALKER_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define VML2_WALKER_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define VML2_WALKER_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define VML2_WALKER_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L +//UTCL2_CE_ERR_STATUS_HI +#define UTCL2_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define UTCL2_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define UTCL2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define UTCL2_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define UTCL2_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define UTCL2_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define UTCL2_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define UTCL2_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define UTCL2_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define UTCL2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define UTCL2_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define UTCL2_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define UTCL2_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define UTCL2_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L + + +// addressBlock: xcd0_gc_utcl2_vml2vcdec +//VM_CONTEXT0_CNTL +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//VM_CONTEXT1_CNTL +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//VM_CONTEXT2_CNTL +#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//VM_CONTEXT3_CNTL +#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//VM_CONTEXT4_CNTL +#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//VM_CONTEXT5_CNTL +#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//VM_CONTEXT6_CNTL +#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//VM_CONTEXT7_CNTL +#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//VM_CONTEXT8_CNTL +#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//VM_CONTEXT9_CNTL +#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//VM_CONTEXT10_CNTL +#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//VM_CONTEXT11_CNTL +#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//VM_CONTEXT12_CNTL +#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//VM_CONTEXT13_CNTL +#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//VM_CONTEXT14_CNTL +#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//VM_CONTEXT15_CNTL +#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//VM_CONTEXTS_DISABLE +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L +//VM_INVALIDATE_ENG0_SEM +#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG1_SEM +#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG2_SEM +#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG3_SEM +#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG4_SEM +#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG5_SEM +#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG6_SEM +#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG7_SEM +#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG8_SEM +#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG9_SEM +#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG10_SEM +#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG11_SEM +#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG12_SEM +#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG13_SEM +#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG14_SEM +#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG15_SEM +#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG16_SEM +#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG17_SEM +#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L +//VM_INVALIDATE_ENG0_REQ +#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG1_REQ +#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG2_REQ +#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG3_REQ +#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG4_REQ +#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG5_REQ +#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG6_REQ +#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG7_REQ +#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG8_REQ +#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG9_REQ +#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG10_REQ +#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG11_REQ +#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG12_REQ +#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG13_REQ +#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG14_REQ +#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG15_REQ +#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG16_REQ +#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG17_REQ +#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x18 +#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +#define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x01000000L +//VM_INVALIDATE_ENG0_ACK +#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG1_ACK +#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG2_ACK +#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG3_ACK +#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG4_ACK +#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG5_ACK +#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG6_ACK +#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG7_ACK +#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG8_ACK +#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG9_ACK +#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG10_ACK +#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG11_ACK +#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG12_ACK +#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG13_ACK +#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG14_ACK +#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG15_ACK +#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG16_ACK +#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG17_ACK +#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 +#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L +//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL + + +// addressBlock: xcd0_gc_utcl2_vmsharedpfdec +//MC_VM_NB_MMIOBASE +#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 +#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL +//MC_VM_NB_MMIOLIMIT +#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 +#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL +//MC_VM_NB_PCI_CTRL +#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 +#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L +//MC_VM_NB_PCI_ARB +#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 +#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L +//MC_VM_NB_TOP_OF_DRAM_SLOT1 +#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 +#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L +//MC_VM_NB_LOWER_TOP_OF_DRAM2 +#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 +#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 +#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L +#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L +//MC_VM_NB_UPPER_TOP_OF_DRAM2 +#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 +#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x0000FFFFL +//MC_VM_FB_OFFSET +#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL +//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL +//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL +//MC_VM_STEERING +#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 +#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L +//MC_SHARED_VIRT_RESET_REQ +#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L +//MC_MEM_POWER_LS +#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//MC_VM_CACHEABLE_DRAM_ADDRESS_START +#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL +//MC_VM_CACHEABLE_DRAM_ADDRESS_END +#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL +//MC_VM_APT_CNTL +#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 +#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 +#define MC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x2 +#define MC_VM_APT_CNTL__PERMS_GRANTED__SHIFT 0x3 +#define MC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT 0x4 +#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L +#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L +#define MC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000004L +#define MC_VM_APT_CNTL__PERMS_GRANTED_MASK 0x00000008L +#define MC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK 0x00000030L +//MC_VM_LOCAL_HBM_ADDRESS_START +#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL +//MC_VM_LOCAL_HBM_ADDRESS_END +#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL +//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL +#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 +#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L +//UTCL2_CGTT_CLK_CTRL +#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc +#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 +#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 +#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L +#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L +#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L +//MC_VM_XGMI_LFB_CNTL +#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 +#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4 +#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x0000000FL +#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x000000F0L +//MC_VM_XGMI_LFB_SIZE +#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 +#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0001FFFFL +//MC_VM_CACHEABLE_DRAM_CNTL +#define MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT 0x0 +#define MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK 0x00000001L +//MC_VM_HOST_MAPPING +#define MC_VM_HOST_MAPPING__MODE__SHIFT 0x0 +#define MC_VM_HOST_MAPPING__MODE_MASK 0x00000001L + + +// addressBlock: xcd0_gc_utcl2_vmsharedvcdec +//MC_VM_FB_LOCATION_BASE +#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 +#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL +//MC_VM_FB_LOCATION_TOP +#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 +#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL +//MC_VM_AGP_TOP +#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL +//MC_VM_AGP_BOT +#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL +//MC_VM_AGP_BASE +#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL +//MC_VM_SYSTEM_APERTURE_LOW_ADDR +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//MC_VM_SYSTEM_APERTURE_HIGH_ADDR +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//MC_VM_MX_L1_TLB_CNTL +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 +#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb +#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L +#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L +#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L + + +// addressBlock: xcd0_gc_utcl2_l2tlbdec +//L2TLB_TLB0_STATUS +#define L2TLB_TLB0_STATUS__BUSY__SHIFT 0x0 +#define L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define L2TLB_TLB0_STATUS__BUSY_MASK 0x00000001L +#define L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT 0x0 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK 0xFFFFFFFFL +//UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT 0x0 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT 0x4 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT 0x9 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT 0xd +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT 0xe +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT 0x10 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT 0x11 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT 0x12 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT 0x13 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT 0x1f +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK 0x0000000FL +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK 0x000000F0L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK 0x00001E00L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK 0x00002000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK 0x0000C000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK 0x00010000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK 0x00020000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK 0x00040000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK 0x0FF80000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK 0x80000000L +//UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT 0x0 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK 0xFFFFFFFFL +//UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT 0x0 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT 0x4 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT 0x7 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT 0xd +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT 0xe +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT 0xf +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT 0x10 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT 0x11 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT 0x12 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT 0x14 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT 0x15 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT 0x16 +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT 0x1f +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK 0x0000000FL +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK 0x00000070L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK 0x00001F80L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK 0x00002000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK 0x00004000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK 0x00008000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK 0x00010000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK 0x00020000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK 0x000C0000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK 0x00100000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK 0x00200000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK 0x00C00000L +#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK 0x80000000L + + +// addressBlock: xcd0_gc_tcdec +//TCP_INVALIDATE +#define TCP_INVALIDATE__START__SHIFT 0x0 +#define TCP_INVALIDATE__START_MASK 0x00000001L +//TCP_STATUS +#define TCP_STATUS__TCP_BUSY__SHIFT 0x0 +#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1 +#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2 +#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3 +#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4 +#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5 +#define TCP_STATUS__READ_BUSY__SHIFT 0x6 +#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7 +#define TCP_STATUS__VM_BUSY__SHIFT 0x8 +#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L +#define TCP_STATUS__INPUT_BUSY_MASK 0x00000002L +#define TCP_STATUS__ADRS_BUSY_MASK 0x00000004L +#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000008L +#define TCP_STATUS__CNTRL_BUSY_MASK 0x00000010L +#define TCP_STATUS__LFIFO_BUSY_MASK 0x00000020L +#define TCP_STATUS__READ_BUSY_MASK 0x00000040L +#define TCP_STATUS__FORMAT_BUSY_MASK 0x00000080L +#define TCP_STATUS__VM_BUSY_MASK 0x00000100L +//TCP_CNTL +#define TCP_CNTL__FORCE_HIT__SHIFT 0x0 +#define TCP_CNTL__FORCE_MISS__SHIFT 0x1 +#define TCP_CNTL__L1_SIZE__SHIFT 0x2 +#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4 +#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5 +#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf +#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16 +#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c +#define TCP_CNTL__FORCE_HIT_MASK 0x00000001L +#define TCP_CNTL__FORCE_MISS_MASK 0x00000002L +#define TCP_CNTL__L1_SIZE_MASK 0x0000000CL +#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x00000010L +#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x00000020L +#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001F8000L +#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0x0FC00000L +#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L +//TCP_CHAN_STEER_0 +#define TCP_CHAN_STEER_0__CHAN0__SHIFT 0x0 +#define TCP_CHAN_STEER_0__CHAN1__SHIFT 0x4 +#define TCP_CHAN_STEER_0__CHAN2__SHIFT 0x8 +#define TCP_CHAN_STEER_0__CHAN3__SHIFT 0xc +#define TCP_CHAN_STEER_0__CHAN4__SHIFT 0x10 +#define TCP_CHAN_STEER_0__CHAN5__SHIFT 0x14 +#define TCP_CHAN_STEER_0__CHAN6__SHIFT 0x18 +#define TCP_CHAN_STEER_0__CHAN7__SHIFT 0x1c +#define TCP_CHAN_STEER_0__CHAN0_MASK 0x0000000FL +#define TCP_CHAN_STEER_0__CHAN1_MASK 0x000000F0L +#define TCP_CHAN_STEER_0__CHAN2_MASK 0x00000F00L +#define TCP_CHAN_STEER_0__CHAN3_MASK 0x0000F000L +#define TCP_CHAN_STEER_0__CHAN4_MASK 0x000F0000L +#define TCP_CHAN_STEER_0__CHAN5_MASK 0x00F00000L +#define TCP_CHAN_STEER_0__CHAN6_MASK 0x0F000000L +#define TCP_CHAN_STEER_0__CHAN7_MASK 0xF0000000L +//TCP_CHAN_STEER_1 +#define TCP_CHAN_STEER_1__CHAN8__SHIFT 0x0 +#define TCP_CHAN_STEER_1__CHAN9__SHIFT 0x4 +#define TCP_CHAN_STEER_1__CHANA__SHIFT 0x8 +#define TCP_CHAN_STEER_1__CHANB__SHIFT 0xc +#define TCP_CHAN_STEER_1__CHANC__SHIFT 0x10 +#define TCP_CHAN_STEER_1__CHAND__SHIFT 0x14 +#define TCP_CHAN_STEER_1__CHANE__SHIFT 0x18 +#define TCP_CHAN_STEER_1__CHANF__SHIFT 0x1c +#define TCP_CHAN_STEER_1__CHAN8_MASK 0x0000000FL +#define TCP_CHAN_STEER_1__CHAN9_MASK 0x000000F0L +#define TCP_CHAN_STEER_1__CHANA_MASK 0x00000F00L +#define TCP_CHAN_STEER_1__CHANB_MASK 0x0000F000L +#define TCP_CHAN_STEER_1__CHANC_MASK 0x000F0000L +#define TCP_CHAN_STEER_1__CHAND_MASK 0x00F00000L +#define TCP_CHAN_STEER_1__CHANE_MASK 0x0F000000L +#define TCP_CHAN_STEER_1__CHANF_MASK 0xF0000000L +//TCP_ADDR_CONFIG +#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0 +#define TCP_ADDR_CONFIG__ENABLE64KHASH__SHIFT 0xb +#define TCP_ADDR_CONFIG__ENABLE2MHASH__SHIFT 0xc +#define TCP_ADDR_CONFIG__ENABLE1GHASH__SHIFT 0xd +#define TCP_ADDR_CONFIG__ENABLE1THASH__SHIFT 0xe +#define TCP_ADDR_CONFIG__ENABLE4KHASH__SHIFT 0xf +#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000001FL +#define TCP_ADDR_CONFIG__ENABLE64KHASH_MASK 0x00000800L +#define TCP_ADDR_CONFIG__ENABLE2MHASH_MASK 0x00001000L +#define TCP_ADDR_CONFIG__ENABLE1GHASH_MASK 0x00002000L +#define TCP_ADDR_CONFIG__ENABLE1THASH_MASK 0x00004000L +#define TCP_ADDR_CONFIG__ENABLE4KHASH_MASK 0x00008000L +//TCP_CREDIT +#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0 +#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10 +#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d +#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x000007FFL +#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007F0000L +#define TCP_CREDIT__TD_CREDIT_MASK 0xE0000000L +//TCP_BUFFER_ADDR_HASH_CNTL +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0 +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8 +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10 +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18 +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x00000007L +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x00000700L +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x00070000L +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x07000000L +//TC_CFG_L1_LOAD_POLICY0 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa +#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc +#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe +#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a +#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c +#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e +#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x00000003L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL +#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x00000030L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x00000300L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x00003000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x00030000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x00300000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x03000000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000L +#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L +//TC_CFG_L1_LOAD_POLICY1 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa +#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc +#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe +#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a +#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c +#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e +#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x00000003L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL +#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x00000030L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x00000300L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x00003000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x00030000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x00300000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x03000000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000L +#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L +//TC_CFG_L1_STORE_POLICY +#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0 +#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1 +#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2 +#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3 +#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4 +#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5 +#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6 +#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7 +#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8 +#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9 +#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa +#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb +#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc +#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd +#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe +#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf +#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10 +#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11 +#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12 +#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13 +#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14 +#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15 +#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16 +#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17 +#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18 +#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19 +#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a +#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b +#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c +#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d +#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e +#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f +#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x00000001L +#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x00000002L +#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x00000004L +#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x00000008L +#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x00000010L +#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x00000020L +#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x00000040L +#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x00000080L +#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x00000100L +#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x00000200L +#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x00000400L +#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x00000800L +#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x00001000L +#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x00002000L +#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x00004000L +#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x00008000L +#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x00010000L +#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x00020000L +#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x00040000L +#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x00080000L +#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x00100000L +#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x00200000L +#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x00400000L +#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x00800000L +#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x01000000L +#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x02000000L +#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x04000000L +#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x08000000L +#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000L +#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000L +#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000L +#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000L +//TC_CFG_L2_LOAD_POLICY0 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa +#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc +#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe +#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a +#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c +#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e +#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x00000003L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL +#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x00000030L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x00000300L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x00003000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x00030000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x00300000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x03000000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000L +#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L +//TC_CFG_L2_LOAD_POLICY1 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa +#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc +#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe +#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a +#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c +#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e +#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x00000003L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL +#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x00000030L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x00000300L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x00003000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x00030000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x00300000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x03000000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000L +#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L +//TC_CFG_L2_STORE_POLICY0 +#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0 +#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2 +#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4 +#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6 +#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8 +#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa +#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc +#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe +#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10 +#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12 +#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14 +#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16 +#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18 +#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a +#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c +#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e +#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x00000003L +#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0x0000000CL +#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x00000030L +#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0x000000C0L +#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x00000300L +#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0x00000C00L +#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x00003000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0x0000C000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x00030000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0x000C0000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x00300000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0x00C00000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x03000000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0x0C000000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000L +#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xC0000000L +//TC_CFG_L2_STORE_POLICY1 +#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0 +#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2 +#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4 +#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6 +#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8 +#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa +#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc +#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe +#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10 +#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12 +#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14 +#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16 +#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18 +#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a +#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c +#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e +#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x00000003L +#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0x0000000CL +#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x00000030L +#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0x000000C0L +#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x00000300L +#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0x00000C00L +#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x00003000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0x0000C000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x00030000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0x000C0000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x00300000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0x00C00000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x03000000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0x0C000000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000L +#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xC0000000L +//TC_CFG_L2_ATOMIC_POLICY +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x00000003L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0x0000000CL +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x00000030L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0x000000C0L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x00000300L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0x00000C00L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x00003000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0x0000C000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x00030000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0x000C0000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x00300000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0x00C00000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x03000000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0x0C000000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000L +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xC0000000L +//TC_CFG_L1_VOLATILE +#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0 +#define TC_CFG_L1_VOLATILE__VOL_MASK 0x0000000FL +//TC_CFG_L2_VOLATILE +#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0 +#define TC_CFG_L2_VOLATILE__VOL_MASK 0x0000000FL +//TCP_UE_EDC_HI_REG +#define TCP_UE_EDC_HI_REG__ECC__SHIFT 0x0 +#define TCP_UE_EDC_HI_REG__PARITY__SHIFT 0x1 +#define TCP_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define TCP_UE_EDC_HI_REG__ERR_INFO__SHIFT 0x3 +#define TCP_UE_EDC_HI_REG__UE_CNT__SHIFT 0x17 +#define TCP_UE_EDC_HI_REG__FED_CNT__SHIFT 0x1a +#define TCP_UE_EDC_HI_REG__RESERVED__SHIFT 0x1d +#define TCP_UE_EDC_HI_REG__ECC_MASK 0x00000001L +#define TCP_UE_EDC_HI_REG__PARITY_MASK 0x00000002L +#define TCP_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define TCP_UE_EDC_HI_REG__ERR_INFO_MASK 0x007FFFF8L +#define TCP_UE_EDC_HI_REG__UE_CNT_MASK 0x03800000L +#define TCP_UE_EDC_HI_REG__FED_CNT_MASK 0x1C000000L +#define TCP_UE_EDC_HI_REG__RESERVED_MASK 0xE0000000L +//TCP_UE_EDC_LO_REG +#define TCP_UE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT 0x0 +#define TCP_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1 +#define TCP_UE_EDC_LO_REG__ADDRESS__SHIFT 0x2 +#define TCP_UE_EDC_LO_REG__MEM_ID__SHIFT 0x18 +#define TCP_UE_EDC_LO_REG__STATUS_VALID_FLAG_MASK 0x00000001L +#define TCP_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L +#define TCP_UE_EDC_LO_REG__ADDRESS_MASK 0x00FFFFFCL +#define TCP_UE_EDC_LO_REG__MEM_ID_MASK 0xFF000000L +//TCP_CE_EDC_HI_REG +#define TCP_CE_EDC_HI_REG__ECC__SHIFT 0x0 +#define TCP_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define TCP_CE_EDC_HI_REG__ERR_INFO__SHIFT 0x3 +#define TCP_CE_EDC_HI_REG__CE_CNT__SHIFT 0x17 +#define TCP_CE_EDC_HI_REG__POISON__SHIFT 0x1a +#define TCP_CE_EDC_HI_REG__RESERVED__SHIFT 0x1b +#define TCP_CE_EDC_HI_REG__ECC_MASK 0x00000001L +#define TCP_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define TCP_CE_EDC_HI_REG__ERR_INFO_MASK 0x007FFFF8L +#define TCP_CE_EDC_HI_REG__CE_CNT_MASK 0x03800000L +#define TCP_CE_EDC_HI_REG__POISON_MASK 0x04000000L +#define TCP_CE_EDC_HI_REG__RESERVED_MASK 0xF8000000L +//TCP_CE_EDC_LO_REG +#define TCP_CE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT 0x0 +#define TCP_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1 +#define TCP_CE_EDC_LO_REG__ADDRESS__SHIFT 0x2 +#define TCP_CE_EDC_LO_REG__MEM_ID__SHIFT 0x18 +#define TCP_CE_EDC_LO_REG__STATUS_VALID_FLAG_MASK 0x00000001L +#define TCP_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L +#define TCP_CE_EDC_LO_REG__ADDRESS_MASK 0x00FFFFFCL +#define TCP_CE_EDC_LO_REG__MEM_ID_MASK 0xFF000000L +//TCI_UE_EDC_HI_REG +#define TCI_UE_EDC_HI_REG__ECC__SHIFT 0x0 +#define TCI_UE_EDC_HI_REG__PARITY__SHIFT 0x1 +#define TCI_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define TCI_UE_EDC_HI_REG__ERR_INFO__SHIFT 0x3 +#define TCI_UE_EDC_HI_REG__UE_CNT__SHIFT 0x17 +#define TCI_UE_EDC_HI_REG__FED_CNT__SHIFT 0x1a +#define TCI_UE_EDC_HI_REG__RESERVED__SHIFT 0x1d +#define TCI_UE_EDC_HI_REG__ECC_MASK 0x00000001L +#define TCI_UE_EDC_HI_REG__PARITY_MASK 0x00000002L +#define TCI_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define TCI_UE_EDC_HI_REG__ERR_INFO_MASK 0x007FFFF8L +#define TCI_UE_EDC_HI_REG__UE_CNT_MASK 0x03800000L +#define TCI_UE_EDC_HI_REG__FED_CNT_MASK 0x1C000000L +#define TCI_UE_EDC_HI_REG__RESERVED_MASK 0xE0000000L +//TCI_UE_EDC_LO_REG +#define TCI_UE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT 0x0 +#define TCI_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1 +#define TCI_UE_EDC_LO_REG__ADDRESS__SHIFT 0x2 +#define TCI_UE_EDC_LO_REG__MEM_ID__SHIFT 0x18 +#define TCI_UE_EDC_LO_REG__STATUS_VALID_FLAG_MASK 0x00000001L +#define TCI_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L +#define TCI_UE_EDC_LO_REG__ADDRESS_MASK 0x00FFFFFCL +#define TCI_UE_EDC_LO_REG__MEM_ID_MASK 0xFF000000L +//TCI_CE_EDC_HI_REG +#define TCI_CE_EDC_HI_REG__ECC__SHIFT 0x0 +#define TCI_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define TCI_CE_EDC_HI_REG__ERR_INFO__SHIFT 0x3 +#define TCI_CE_EDC_HI_REG__CE_CNT__SHIFT 0x17 +#define TCI_CE_EDC_HI_REG__POISON__SHIFT 0x1a +#define TCI_CE_EDC_HI_REG__RESERVED__SHIFT 0x1b +#define TCI_CE_EDC_HI_REG__ECC_MASK 0x00000001L +#define TCI_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define TCI_CE_EDC_HI_REG__ERR_INFO_MASK 0x007FFFF8L +#define TCI_CE_EDC_HI_REG__CE_CNT_MASK 0x03800000L +#define TCI_CE_EDC_HI_REG__POISON_MASK 0x04000000L +#define TCI_CE_EDC_HI_REG__RESERVED_MASK 0xF8000000L +//TCI_CE_EDC_LO_REG +#define TCI_CE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT 0x0 +#define TCI_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1 +#define TCI_CE_EDC_LO_REG__ADDRESS__SHIFT 0x2 +#define TCI_CE_EDC_LO_REG__MEM_ID__SHIFT 0x18 +#define TCI_CE_EDC_LO_REG__STATUS_VALID_FLAG_MASK 0x00000001L +#define TCI_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L +#define TCI_CE_EDC_LO_REG__ADDRESS_MASK 0x00FFFFFCL +#define TCI_CE_EDC_LO_REG__MEM_ID_MASK 0xFF000000L +//TCI_MISC +#define TCI_MISC__FGCG_REPEATER_DISABLE__SHIFT 0x0 +#define TCI_MISC__LEGACY_MGCG_DISABLE__SHIFT 0x1 +#define TCI_MISC__FGCG_REPEATER_DISABLE_MASK 0x00000001L +#define TCI_MISC__LEGACY_MGCG_DISABLE_MASK 0x00000002L +//TCI_CNTL_3 +#define TCI_CNTL_3__DISABLE_DOUBLING_L2_BANDWIDTH__SHIFT 0x0 +#define TCI_CNTL_3__COMBINING_DELAY_WINDOW__SHIFT 0x2 +#define TCI_CNTL_3__CHICKEN_BIT_TCR_MGCG__SHIFT 0x4 +#define TCI_CNTL_3__TCR_FGCG_REPEATER_DISABLE__SHIFT 0x7 +#define TCI_CNTL_3__DISABLE_DOUBLING_L2_BANDWIDTH_MASK 0x00000003L +#define TCI_CNTL_3__COMBINING_DELAY_WINDOW_MASK 0x0000000CL +#define TCI_CNTL_3__CHICKEN_BIT_TCR_MGCG_MASK 0x00000070L +#define TCI_CNTL_3__TCR_FGCG_REPEATER_DISABLE_MASK 0x00000080L +//TCI_DSM_CNTL +#define TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_DATA_SEL_MASK 0x00000003L +#define TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L +//TCI_DSM_CNTL2 +#define TCI_DSM_CNTL2__WRITE_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TCI_DSM_CNTL2__WRITE_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TCI_DSM_CNTL2__TCI_INJECT_DELAY__SHIFT 0x1a +#define TCI_DSM_CNTL2__WRITE_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TCI_DSM_CNTL2__WRITE_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TCI_DSM_CNTL2__TCI_INJECT_DELAY_MASK 0xFC000000L +//TCI_STATUS +#define TCI_STATUS__TCI_BUSY__SHIFT 0x0 +#define TCI_STATUS__TCI_BUSY_MASK 0x00000001L +//TCI_CNTL_1 +#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0 +#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10 +#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18 +#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000FFFFL +#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00FF0000L +#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xFF000000L +//TCI_CNTL_2 +#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0 +#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1 +#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L +#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001FEL +//TCC_CTRL +#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0 +#define TCC_CTRL__RATE__SHIFT 0x2 +#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4 +#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc +#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10 +#define TCC_CTRL__LINEAR_SET_HASH__SHIFT 0x15 +#define TCC_CTRL__OUTPUT_FIFO_CLK_MODE__SHIFT 0x16 +#define TCC_CTRL__EXECUTE_CLK_MODE__SHIFT 0x17 +#define TCC_CTRL__RETURN_BUFFER_CLK_MODE__SHIFT 0x19 +#define TCC_CTRL__SRC_FIFO_CLK_MODE__SHIFT 0x1a +#define TCC_CTRL__MC_WRITE_CLK_MODE__SHIFT 0x1b +#define TCC_CTRL__LATENCY_FIFO_CLK_MODE__SHIFT 0x1c +#define TCC_CTRL__DISABLE_SHARED_128B_READ_REQUEST__SHIFT 0x1d +#define TCC_CTRL__CACHE_SIZE_MASK 0x00000003L +#define TCC_CTRL__RATE_MASK 0x0000000CL +#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0x000000F0L +#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0x0000F000L +#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0x000F0000L +#define TCC_CTRL__LINEAR_SET_HASH_MASK 0x00200000L +#define TCC_CTRL__OUTPUT_FIFO_CLK_MODE_MASK 0x00400000L +#define TCC_CTRL__EXECUTE_CLK_MODE_MASK 0x01800000L +#define TCC_CTRL__RETURN_BUFFER_CLK_MODE_MASK 0x02000000L +#define TCC_CTRL__SRC_FIFO_CLK_MODE_MASK 0x04000000L +#define TCC_CTRL__MC_WRITE_CLK_MODE_MASK 0x08000000L +#define TCC_CTRL__LATENCY_FIFO_CLK_MODE_MASK 0x10000000L +#define TCC_CTRL__DISABLE_SHARED_128B_READ_REQUEST_MASK 0x20000000L +//TCC_CTRL2 +#define TCC_CTRL2__PROBE_FIFO_SIZE__SHIFT 0x0 +#define TCC_CTRL2__INF_NAN_CLAMP__SHIFT 0x10 +#define TCC_CTRL2__PROBE_FILTER_CTRL__SHIFT 0x11 +#define TCC_CTRL2__WAIT_CLK_STABLE_CNT__SHIFT 0x12 +#define TCC_CTRL2__TCC_TCX_REPEATER_FGCG_DISABLE__SHIFT 0x17 +#define TCC_CTRL2__TCC_EA0_RDREQ_FGCG_DISABLE__SHIFT 0x18 +#define TCC_CTRL2__TCC_EA0_WRREQ_FGCG_DISABLE__SHIFT 0x19 +#define TCC_CTRL2__TCC_TCX_ACK_REPEATER_FGCG_DISABLE__SHIFT 0x1a +#define TCC_CTRL2__TCC_TCA_HOLE_REPEATER_FGCG_DISABLE__SHIFT 0x1b +#define TCC_CTRL2__TCC_TCA_RTN_REPEATER_FGCG_DISABLE__SHIFT 0x1c +#define TCC_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK__SHIFT 0x1d +#define TCC_CTRL2__Enable_TCC_64K_2M_1G_1T_hash__SHIFT 0x1e +#define TCC_CTRL2__PROBE_FIFO_SIZE_MASK 0x0000000FL +#define TCC_CTRL2__INF_NAN_CLAMP_MASK 0x00010000L +#define TCC_CTRL2__PROBE_FILTER_CTRL_MASK 0x00020000L +#define TCC_CTRL2__WAIT_CLK_STABLE_CNT_MASK 0x007C0000L +#define TCC_CTRL2__TCC_TCX_REPEATER_FGCG_DISABLE_MASK 0x00800000L +#define TCC_CTRL2__TCC_EA0_RDREQ_FGCG_DISABLE_MASK 0x01000000L +#define TCC_CTRL2__TCC_EA0_WRREQ_FGCG_DISABLE_MASK 0x02000000L +#define TCC_CTRL2__TCC_TCX_ACK_REPEATER_FGCG_DISABLE_MASK 0x04000000L +#define TCC_CTRL2__TCC_TCA_HOLE_REPEATER_FGCG_DISABLE_MASK 0x08000000L +#define TCC_CTRL2__TCC_TCA_RTN_REPEATER_FGCG_DISABLE_MASK 0x10000000L +#define TCC_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK_MASK 0x20000000L +#define TCC_CTRL2__Enable_TCC_64K_2M_1G_1T_hash_MASK 0x40000000L +//TCC_DSM_CNTL +#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL__SHIFT 0x3 +#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL__SHIFT 0x6 +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL__SHIFT 0x9 +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE__SHIFT 0xb +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL__SHIFT 0xc +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE__SHIFT 0xe +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL__SHIFT 0xf +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 +#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x12 +#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 +#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x15 +#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x17 +#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL__SHIFT 0x18 +#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a +#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL__SHIFT 0x1b +#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d +#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL_MASK 0x00000003L +#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L +#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL_MASK 0x00000018L +#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL_MASK 0x000000C0L +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL_MASK 0x00000600L +#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL_MASK 0x00003000L +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL_MASK 0x00018000L +#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L +#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x000C0000L +#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L +#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x00600000L +#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L +#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL_MASK 0x03000000L +#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L +#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL_MASK 0x18000000L +#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L +//TCC_DSM_CNTLA +#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x3 +#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 +#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL__SHIFT 0x6 +#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 +#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL__SHIFT 0x9 +#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE__SHIFT 0xb +#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc +#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe +#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL__SHIFT 0xf +#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 +#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x12 +#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 +#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL__SHIFT 0x15 +#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x17 +#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL__SHIFT 0x18 +#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a +#define TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_DATA_SEL__SHIFT 0x1b +#define TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d +#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000003L +#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L +#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000018L +#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L +#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL_MASK 0x000000C0L +#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L +#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL_MASK 0x00000600L +#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L +#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L +#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L +#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL_MASK 0x00018000L +#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L +#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL_MASK 0x000C0000L +#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L +#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL_MASK 0x00600000L +#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L +#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL_MASK 0x03000000L +#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L +#define TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_DATA_SEL_MASK 0x18000000L +#define TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L +//TCC_DSM_CNTL2 +#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY__SHIFT 0x5 +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY__SHIFT 0x8 +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY__SHIFT 0xb +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT__SHIFT 0xc +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY__SHIFT 0xe +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT__SHIFT 0xf +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY__SHIFT 0x11 +#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x14 +#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x17 +#define TCC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY_MASK 0x00000020L +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY_MASK 0x00000100L +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY_MASK 0x00000800L +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY_MASK 0x00004000L +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY_MASK 0x00020000L +#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00100000L +#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00800000L +#define TCC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//TCC_DSM_CNTL2A +#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY__SHIFT 0x5 +#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY__SHIFT 0x8 +#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY__SHIFT 0xb +#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xc +#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY__SHIFT 0xe +#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT__SHIFT 0xf +#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY__SHIFT 0x11 +#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY__SHIFT 0x14 +#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY__SHIFT 0x17 +#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x18 +#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY__SHIFT 0x1a +#define TCC_DSM_CNTL2A__OUTPUT_FIFOS_ENABLE_ERROR_INJECT__SHIFT 0x1b +#define TCC_DSM_CNTL2A__OUTPUT_FIFOS_SELECT_INJECT_DELAY__SHIFT 0x1d +#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY_MASK 0x00000020L +#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY_MASK 0x00000100L +#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY_MASK 0x00000800L +#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY_MASK 0x00004000L +#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY_MASK 0x00020000L +#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY_MASK 0x00100000L +#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY_MASK 0x00800000L +#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT_MASK 0x03000000L +#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY_MASK 0x04000000L +#define TCC_DSM_CNTL2A__OUTPUT_FIFOS_ENABLE_ERROR_INJECT_MASK 0x18000000L +#define TCC_DSM_CNTL2A__OUTPUT_FIFOS_SELECT_INJECT_DELAY_MASK 0x20000000L +//TCC_DSM_CNTL2B +#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_ENABLE_ERROR_INJECT__SHIFT 0xc +#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_SELECT_INJECT_DELAY__SHIFT 0xe +#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_DATA_SEL__SHIFT 0xf +#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 +#define TCC_DSM_CNTL2B__RETURN_BUFFER_LEVEL_BUBBLE_THRESHOLD__SHIFT 0x12 +#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_SELECT_INJECT_DELAY_MASK 0x00004000L +#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_DATA_SEL_MASK 0x00018000L +#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L +#define TCC_DSM_CNTL2B__RETURN_BUFFER_LEVEL_BUBBLE_THRESHOLD_MASK 0x00FC0000L +//TCC_WBINVL2 +#define TCC_WBINVL2__DONE__SHIFT 0x4 +#define TCC_WBINVL2__DONE_MASK 0x00000010L +//TCC_SOFT_RESET +#define TCC_SOFT_RESET__HALT_FOR_RESET__SHIFT 0x0 +#define TCC_SOFT_RESET__HALT_FOR_RESET_MASK 0x00000001L +//TCC_DSM_CNTL3 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_DATA_SEL__SHIFT 0x3 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_DATA_SEL__SHIFT 0x6 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_DATA_SEL__SHIFT 0x9 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_SINGLE_WRITE__SHIFT 0xb +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_ENABLE_ERROR_INJECT__SHIFT 0xc +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_SELECT_INJECT_DELAY__SHIFT 0xe +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_ENABLE_ERROR_INJECT__SHIFT 0xf +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_SELECT_INJECT_DELAY__SHIFT 0x11 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_SELECT_INJECT_DELAY__SHIFT 0x14 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_SELECT_INJECT_DELAY__SHIFT 0x17 +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_DATA_SEL_MASK 0x00000003L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_DATA_SEL_MASK 0x00000018L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_DATA_SEL_MASK 0x000000C0L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_DATA_SEL_MASK 0x00000600L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_SELECT_INJECT_DELAY_MASK 0x00004000L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_SELECT_INJECT_DELAY_MASK 0x00020000L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_SELECT_INJECT_DELAY_MASK 0x00100000L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_SELECT_INJECT_DELAY_MASK 0x00800000L +//TCA_CTRL +#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0 +#define TCA_CTRL__RB_STILL_4_PHASE__SHIFT 0x4 +#define TCA_CTRL__RB_AS_TCI__SHIFT 0x5 +#define TCA_CTRL__DISABLE_UTCL2_PRIORITY__SHIFT 0x6 +#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER__SHIFT 0x7 +#define TCA_CTRL__TCA_TCC_FGCG_DISABLE__SHIFT 0x8 +#define TCA_CTRL__TCA_TCA_FGCG_DISABLE__SHIFT 0x9 +#define TCA_CTRL__TCA_TCH_FGCG_DISABLE__SHIFT 0xa +#define TCA_CTRL__TCA_TCX_FGCG_DISABLE__SHIFT 0xb +#define TCA_CTRL__TCA_RANDOM_REVERSE_PRIORITY_ENABLE__SHIFT 0xc +#define TCA_CTRL__RTN_CREDIT_THRESHOLD__SHIFT 0xd +#define TCA_CTRL__ACK_CREDIT_THRESHOLD__SHIFT 0x10 +#define TCA_CTRL__RTN_ARB_MODE__SHIFT 0x13 +#define TCA_CTRL__HOLE_ARB_SHARE_THRESHOLD__SHIFT 0x18 +#define TCA_CTRL__HOLE_ARB_LANE_THRESHOLD__SHIFT 0x1c +#define TCA_CTRL__HOLE_TIMEOUT_MASK 0x0000000FL +#define TCA_CTRL__RB_STILL_4_PHASE_MASK 0x00000010L +#define TCA_CTRL__RB_AS_TCI_MASK 0x00000020L +#define TCA_CTRL__DISABLE_UTCL2_PRIORITY_MASK 0x00000040L +#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER_MASK 0x00000080L +#define TCA_CTRL__TCA_TCC_FGCG_DISABLE_MASK 0x00000100L +#define TCA_CTRL__TCA_TCA_FGCG_DISABLE_MASK 0x00000200L +#define TCA_CTRL__TCA_TCH_FGCG_DISABLE_MASK 0x00000400L +#define TCA_CTRL__TCA_TCX_FGCG_DISABLE_MASK 0x00000800L +#define TCA_CTRL__TCA_RANDOM_REVERSE_PRIORITY_ENABLE_MASK 0x00001000L +#define TCA_CTRL__RTN_CREDIT_THRESHOLD_MASK 0x0000E000L +#define TCA_CTRL__ACK_CREDIT_THRESHOLD_MASK 0x00070000L +#define TCA_CTRL__RTN_ARB_MODE_MASK 0x00080000L +#define TCA_CTRL__HOLE_ARB_SHARE_THRESHOLD_MASK 0x07000000L +#define TCA_CTRL__HOLE_ARB_LANE_THRESHOLD_MASK 0x70000000L +//TCA_BURST_MASK +#define TCA_BURST_MASK__ADDR_MASK__SHIFT 0x0 +#define TCA_BURST_MASK__ADDR_MASK_MASK 0xFFFFFFFFL +//TCA_BURST_CTRL +#define TCA_BURST_CTRL__MAX_BURST__SHIFT 0x0 +#define TCA_BURST_CTRL__TCP_DISABLE__SHIFT 0x4 +#define TCA_BURST_CTRL__SQC_DISABLE__SHIFT 0x5 +#define TCA_BURST_CTRL__CPF_DISABLE__SHIFT 0x6 +#define TCA_BURST_CTRL__CPG_DISABLE__SHIFT 0x7 +#define TCA_BURST_CTRL__SQG_DISABLE__SHIFT 0xa +#define TCA_BURST_CTRL__UTCL2_DISABLE__SHIFT 0xb +#define TCA_BURST_CTRL__TPI_DISABLE__SHIFT 0xc +#define TCA_BURST_CTRL__RLC_DISABLE__SHIFT 0xd +#define TCA_BURST_CTRL__MAX_BURST_MASK 0x00000007L +#define TCA_BURST_CTRL__TCP_DISABLE_MASK 0x00000010L +#define TCA_BURST_CTRL__SQC_DISABLE_MASK 0x00000020L +#define TCA_BURST_CTRL__CPF_DISABLE_MASK 0x00000040L +#define TCA_BURST_CTRL__CPG_DISABLE_MASK 0x00000080L +#define TCA_BURST_CTRL__SQG_DISABLE_MASK 0x00000400L +#define TCA_BURST_CTRL__UTCL2_DISABLE_MASK 0x00000800L +#define TCA_BURST_CTRL__TPI_DISABLE_MASK 0x00001000L +#define TCA_BURST_CTRL__RLC_DISABLE_MASK 0x00002000L +//TCA_DSM_CNTL +#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x3 +#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 +#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000003L +#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L +#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000018L +#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L +//TCA_DSM_CNTL2 +#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x5 +#define TCA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000020L +#define TCA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//TCX_CTRL +#define TCX_CTRL__TCX_TCX_FGCG_DISABLE__SHIFT 0x0 +#define TCX_CTRL__TCX_TCR_FGCG_DISABLE__SHIFT 0x1 +#define TCX_CTRL__TCX_TCC_FGCG_DISABLE__SHIFT 0x2 +#define TCX_CTRL__TCX_TCX_FGCG_DISABLE_MASK 0x00000001L +#define TCX_CTRL__TCX_TCR_FGCG_DISABLE_MASK 0x00000002L +#define TCX_CTRL__TCX_TCC_FGCG_DISABLE_MASK 0x00000004L +//TCX_DSM_CNTL +#define TCX_DSM_CNTL__GROUP0_SED_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define TCX_DSM_CNTL__GROUP1_SED_IRRITATOR_DATA_SEL__SHIFT 0x2 +#define TCX_DSM_CNTL__GROUP2_SED_IRRITATOR_DATA_SEL__SHIFT 0x4 +#define TCX_DSM_CNTL__GROUP4_SED_IRRITATOR_DATA_SEL__SHIFT 0x8 +#define TCX_DSM_CNTL__GROUP5_SED_IRRITATOR_DATA_SEL__SHIFT 0xa +#define TCX_DSM_CNTL__GROUP6_SED_IRRITATOR_DATA_SEL__SHIFT 0xc +#define TCX_DSM_CNTL__GROUP8_SED_IRRITATOR_DATA_SEL__SHIFT 0x10 +#define TCX_DSM_CNTL__GROUP9_SED_IRRITATOR_DATA_SEL__SHIFT 0x12 +#define TCX_DSM_CNTL__GROUP10_SED_IRRITATOR_DATA_SEL__SHIFT 0x14 +#define TCX_DSM_CNTL__GROUP13_SED_IRRITATOR_DATA_SEL__SHIFT 0x1a +#define TCX_DSM_CNTL__GROUP14_SED_IRRITATOR_DATA_SEL__SHIFT 0x1c +#define TCX_DSM_CNTL__SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x1e +#define TCX_DSM_CNTL__GROUP0_SED_IRRITATOR_DATA_SEL_MASK 0x00000003L +#define TCX_DSM_CNTL__GROUP1_SED_IRRITATOR_DATA_SEL_MASK 0x0000000CL +#define TCX_DSM_CNTL__GROUP2_SED_IRRITATOR_DATA_SEL_MASK 0x00000030L +#define TCX_DSM_CNTL__GROUP4_SED_IRRITATOR_DATA_SEL_MASK 0x00000300L +#define TCX_DSM_CNTL__GROUP5_SED_IRRITATOR_DATA_SEL_MASK 0x00000C00L +#define TCX_DSM_CNTL__GROUP6_SED_IRRITATOR_DATA_SEL_MASK 0x00003000L +#define TCX_DSM_CNTL__GROUP8_SED_IRRITATOR_DATA_SEL_MASK 0x00030000L +#define TCX_DSM_CNTL__GROUP9_SED_IRRITATOR_DATA_SEL_MASK 0x000C0000L +#define TCX_DSM_CNTL__GROUP10_SED_IRRITATOR_DATA_SEL_MASK 0x00300000L +#define TCX_DSM_CNTL__GROUP13_SED_IRRITATOR_DATA_SEL_MASK 0x0C000000L +#define TCX_DSM_CNTL__GROUP14_SED_IRRITATOR_DATA_SEL_MASK 0x30000000L +#define TCX_DSM_CNTL__SED_IRRITATOR_SINGLE_WRITE_MASK 0x40000000L +//TCX_DSM_CNTL2 +#define TCX_DSM_CNTL2__SED_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TCX_DSM_CNTL2__SED_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TCX_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define TCX_DSM_CNTL2__SED_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TCX_DSM_CNTL2__SED_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TCX_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//TCA_UE_ERR_STATUS_LO +#define TCA_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define TCA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define TCA_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define TCA_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define TCA_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define TCA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define TCA_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define TCA_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//TCA_UE_ERR_STATUS_HI +#define TCA_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define TCA_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define TCA_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT 0x2 +#define TCA_UE_ERR_STATUS_HI__ERROR_INFO__SHIFT 0x3 +#define TCA_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define TCA_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define TCA_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define TCA_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define TCA_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK 0x00000004L +#define TCA_UE_ERR_STATUS_HI__ERROR_INFO_MASK 0x007FFFF8L +#define TCA_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define TCA_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +//TCX_UE_ERR_STATUS_LO +#define TCX_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define TCX_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define TCX_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define TCX_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define TCX_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define TCX_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define TCX_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define TCX_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//TCX_UE_ERR_STATUS_HI +#define TCX_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define TCX_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define TCX_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT 0x2 +#define TCX_UE_ERR_STATUS_HI__ERROR_INFO__SHIFT 0x3 +#define TCX_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define TCX_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define TCX_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define TCX_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define TCX_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK 0x00000004L +#define TCX_UE_ERR_STATUS_HI__ERROR_INFO_MASK 0x007FFFF8L +#define TCX_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define TCX_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +//TCX_CE_ERR_STATUS_LO +#define TCX_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define TCX_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define TCX_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define TCX_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define TCX_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define TCX_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define TCX_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define TCX_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//TCX_CE_ERR_STATUS_HI +#define TCX_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define TCX_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT 0x2 +#define TCX_CE_ERR_STATUS_HI__ERROR_INFO__SHIFT 0x3 +#define TCX_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define TCX_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define TCX_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define TCX_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK 0x00000004L +#define TCX_CE_ERR_STATUS_HI__ERROR_INFO_MASK 0x007FFFF8L +#define TCX_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define TCX_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +//TCC_UE_ERR_STATUS_LO +#define TCC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define TCC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define TCC_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define TCC_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define TCC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define TCC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define TCC_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define TCC_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//TCC_UE_ERR_STATUS_HI +#define TCC_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define TCC_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define TCC_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT 0x2 +#define TCC_UE_ERR_STATUS_HI__ERROR_INFO__SHIFT 0x3 +#define TCC_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define TCC_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define TCC_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define TCC_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define TCC_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK 0x00000004L +#define TCC_UE_ERR_STATUS_HI__ERROR_INFO_MASK 0x007FFFF8L +#define TCC_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define TCC_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +//TCC_CE_ERR_STATUS_LO +#define TCC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define TCC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define TCC_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define TCC_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define TCC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define TCC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define TCC_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define TCC_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//TCC_CE_ERR_STATUS_HI +#define TCC_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define TCC_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT 0x2 +#define TCC_CE_ERR_STATUS_HI__ERROR_INFO__SHIFT 0x3 +#define TCC_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define TCC_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define TCC_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define TCC_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK 0x00000004L +#define TCC_CE_ERR_STATUS_HI__ERROR_INFO_MASK 0x007FFFF8L +#define TCC_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define TCC_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L + + +// addressBlock: xcd0_gc_shdec +//SPI_SHADER_PGM_RSRC3_PS +#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000FFFFL +#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x003F0000L +#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L +#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE_MASK 0x3C000000L +//SPI_SHADER_PGM_LO_PS +#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_PS +#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_RSRC1_PS +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x1d +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000FF000L +#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L +#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000L +#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L +//SPI_SHADER_PGM_RSRC2_PS +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x19 +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000FF00L +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01FF0000L +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x10000000L +//SPI_SHADER_USER_DATA_PS_0 +#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_1 +#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_2 +#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_3 +#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_4 +#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_5 +#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_6 +#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_7 +#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_8 +#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_9 +#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_10 +#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_11 +#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_12 +#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_13 +#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_14 +#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_15 +#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_16 +#define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_17 +#define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_18 +#define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_19 +#define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_20 +#define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_21 +#define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_22 +#define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_23 +#define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_24 +#define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_25 +#define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_26 +#define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_27 +#define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_28 +#define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_29 +#define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_30 +#define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_31 +#define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC3_VS +#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0x0000FFFFL +#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x003F0000L +#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L +#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE_MASK 0x3C000000L +//SPI_SHADER_LATE_ALLOC_VS +#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0 +#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x0000003FL +//SPI_SHADER_PGM_LO_VS +#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_VS +#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_RSRC1_VS +#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x1e +#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT 0x1f +#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000FF000L +#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L +#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000L +#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK 0x80000000L +//SPI_SHADER_PGM_RSRC2_VS +#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb +#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd +#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L +#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L +#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x003FE000L +#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x01000000L +#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK 0x10000000L +//SPI_SHADER_USER_DATA_VS_0 +#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_1 +#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_2 +#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_3 +#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_4 +#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_5 +#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_6 +#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_7 +#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_8 +#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_9 +#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_10 +#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_11 +#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_12 +#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_13 +#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_14 +#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_15 +#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_16 +#define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_17 +#define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_18 +#define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_19 +#define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_20 +#define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_21 +#define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_22 +#define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_23 +#define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_24 +#define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_25 +#define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_26 +#define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_27 +#define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_28 +#define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_29 +#define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_30 +#define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_VS_31 +#define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_31__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC2_GS_VS +#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT 0x12 +#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT 0x13 +#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK 0x0000FF80L +#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK 0x00030000L +#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK 0x00040000L +#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK 0x07F80000L +#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK 0x10000000L +//SPI_SHADER_PGM_RSRC4_GS +#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH_MASK 0x0000007FL +#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x00003F80L +//SPI_SHADER_USER_DATA_ADDR_LO_GS +#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ADDR_HI_GS +#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_LO_ES +#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_ES +#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_RSRC3_GS +#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0x0000FFFFL +#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x003F0000L +#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L +#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE_MASK 0x3C000000L +//SPI_SHADER_PGM_LO_GS +#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_GS +#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_RSRC1_GS +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x1d +#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x1f +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000FF000L +#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L +#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000L +#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L +#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L +//SPI_SHADER_PGM_RSRC2_GS +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x12 +#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x13 +#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000FF80L +#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L +#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L +#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07F80000L +#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x10000000L +//SPI_SHADER_USER_DATA_ES_0 +#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_1 +#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_2 +#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_3 +#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_4 +#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_5 +#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_6 +#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_7 +#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_8 +#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_9 +#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_10 +#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_11 +#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_12 +#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_13 +#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_14 +#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_15 +#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_16 +#define SPI_SHADER_USER_DATA_ES_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_17 +#define SPI_SHADER_USER_DATA_ES_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_18 +#define SPI_SHADER_USER_DATA_ES_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_19 +#define SPI_SHADER_USER_DATA_ES_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_20 +#define SPI_SHADER_USER_DATA_ES_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_21 +#define SPI_SHADER_USER_DATA_ES_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_22 +#define SPI_SHADER_USER_DATA_ES_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_23 +#define SPI_SHADER_USER_DATA_ES_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_24 +#define SPI_SHADER_USER_DATA_ES_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_25 +#define SPI_SHADER_USER_DATA_ES_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_26 +#define SPI_SHADER_USER_DATA_ES_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_27 +#define SPI_SHADER_USER_DATA_ES_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_28 +#define SPI_SHADER_USER_DATA_ES_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_29 +#define SPI_SHADER_USER_DATA_ES_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_30 +#define SPI_SHADER_USER_DATA_ES_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ES_31 +#define SPI_SHADER_USER_DATA_ES_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_31__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC4_HS +#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH_MASK 0x0000007FL +//SPI_SHADER_USER_DATA_ADDR_LO_HS +#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ADDR_HI_HS +#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_LO_LS +#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_LS +#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_RSRC3_HS +#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE_MASK 0x00003C00L +#define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xFFFF0000L +//SPI_SHADER_PGM_LO_HS +#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_HS +#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xFFL +//SPI_SHADER_PGM_RSRC1_HS +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x1e +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000FF000L +#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L +#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L +//SPI_SHADER_PGM_RSRC2_HS +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0000FF80L +#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x01FF0000L +#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x10000000L +//SPI_SHADER_USER_DATA_LS_0 +#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_1 +#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_2 +#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_3 +#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_4 +#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_5 +#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_6 +#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_7 +#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_8 +#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_9 +#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_10 +#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_11 +#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_12 +#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_13 +#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_14 +#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_15 +#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_16 +#define SPI_SHADER_USER_DATA_LS_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_17 +#define SPI_SHADER_USER_DATA_LS_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_18 +#define SPI_SHADER_USER_DATA_LS_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_19 +#define SPI_SHADER_USER_DATA_LS_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_20 +#define SPI_SHADER_USER_DATA_LS_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_21 +#define SPI_SHADER_USER_DATA_LS_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_22 +#define SPI_SHADER_USER_DATA_LS_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_23 +#define SPI_SHADER_USER_DATA_LS_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_24 +#define SPI_SHADER_USER_DATA_LS_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_25 +#define SPI_SHADER_USER_DATA_LS_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_26 +#define SPI_SHADER_USER_DATA_LS_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_27 +#define SPI_SHADER_USER_DATA_LS_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_28 +#define SPI_SHADER_USER_DATA_LS_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_29 +#define SPI_SHADER_USER_DATA_LS_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_30 +#define SPI_SHADER_USER_DATA_LS_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_LS_31 +#define SPI_SHADER_USER_DATA_LS_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_31__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_0 +#define SPI_SHADER_USER_DATA_COMMON_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_1 +#define SPI_SHADER_USER_DATA_COMMON_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_2 +#define SPI_SHADER_USER_DATA_COMMON_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_3 +#define SPI_SHADER_USER_DATA_COMMON_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_4 +#define SPI_SHADER_USER_DATA_COMMON_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_5 +#define SPI_SHADER_USER_DATA_COMMON_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_6 +#define SPI_SHADER_USER_DATA_COMMON_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_7 +#define SPI_SHADER_USER_DATA_COMMON_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_8 +#define SPI_SHADER_USER_DATA_COMMON_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_9 +#define SPI_SHADER_USER_DATA_COMMON_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_10 +#define SPI_SHADER_USER_DATA_COMMON_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_11 +#define SPI_SHADER_USER_DATA_COMMON_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_12 +#define SPI_SHADER_USER_DATA_COMMON_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_13 +#define SPI_SHADER_USER_DATA_COMMON_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_14 +#define SPI_SHADER_USER_DATA_COMMON_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_15 +#define SPI_SHADER_USER_DATA_COMMON_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_16 +#define SPI_SHADER_USER_DATA_COMMON_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_17 +#define SPI_SHADER_USER_DATA_COMMON_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_18 +#define SPI_SHADER_USER_DATA_COMMON_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_19 +#define SPI_SHADER_USER_DATA_COMMON_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_20 +#define SPI_SHADER_USER_DATA_COMMON_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_21 +#define SPI_SHADER_USER_DATA_COMMON_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_22 +#define SPI_SHADER_USER_DATA_COMMON_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_23 +#define SPI_SHADER_USER_DATA_COMMON_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_24 +#define SPI_SHADER_USER_DATA_COMMON_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_25 +#define SPI_SHADER_USER_DATA_COMMON_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_26 +#define SPI_SHADER_USER_DATA_COMMON_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_27 +#define SPI_SHADER_USER_DATA_COMMON_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_28 +#define SPI_SHADER_USER_DATA_COMMON_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_29 +#define SPI_SHADER_USER_DATA_COMMON_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_30 +#define SPI_SHADER_USER_DATA_COMMON_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_COMMON_31 +#define SPI_SHADER_USER_DATA_COMMON_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_COMMON_31__DATA_MASK 0xFFFFFFFFL +//COMPUTE_DISPATCH_INITIATOR +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb +#define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT 0xc +#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L +#define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK 0x00001000L +#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L +//COMPUTE_DIM_X +#define COMPUTE_DIM_X__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_DIM_Y +#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_DIM_Z +#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_START_X +#define COMPUTE_START_X__START__SHIFT 0x0 +#define COMPUTE_START_X__START_MASK 0xFFFFFFFFL +//COMPUTE_START_Y +#define COMPUTE_START_Y__START__SHIFT 0x0 +#define COMPUTE_START_Y__START_MASK 0xFFFFFFFFL +//COMPUTE_START_Z +#define COMPUTE_START_Z__START__SHIFT 0x0 +#define COMPUTE_START_Z__START_MASK 0xFFFFFFFFL +//COMPUTE_NUM_THREAD_X +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000FFFFL +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//COMPUTE_NUM_THREAD_Y +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000FFFFL +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//COMPUTE_NUM_THREAD_Z +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//COMPUTE_PIPELINESTAT_ENABLE +#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 +#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L +//COMPUTE_PERFCOUNT_ENABLE +#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 +#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L +//COMPUTE_PGM_LO +#define COMPUTE_PGM_LO__DATA__SHIFT 0x0 +#define COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL +//COMPUTE_PGM_HI +#define COMPUTE_PGM_HI__DATA__SHIFT 0x0 +#define COMPUTE_PGM_HI__DATA_MASK 0x000000FFL +//COMPUTE_DISPATCH_PKT_ADDR_LO +#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL +//COMPUTE_DISPATCH_PKT_ADDR_HI +#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL +//COMPUTE_DISPATCH_SCRATCH_BASE_LO +#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL +//COMPUTE_DISPATCH_SCRATCH_BASE_HI +#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL +//COMPUTE_PGM_RSRC1 +#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 +#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 +#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa +#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc +#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 +#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15 +#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16 +#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17 +#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 +#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19 +#define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a +#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL +#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L +#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L +#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L +#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L +#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L +#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x00400000L +#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L +#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L +#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x02000000L +#define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L +//COMPUTE_PGM_RSRC2 +#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 +#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 +#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6 +#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 +#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 +#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd +#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf +#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 +#define COMPUTE_PGM_RSRC2__SKIP_USGPR0__SHIFT 0x1f +#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L +#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003EL +#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L +#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L +#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L +#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L +#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L +#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L +#define COMPUTE_PGM_RSRC2__SKIP_USGPR0_MASK 0x80000000L +//COMPUTE_VMID +#define COMPUTE_VMID__DATA__SHIFT 0x0 +#define COMPUTE_VMID__DATA_MASK 0x0000000FL +//COMPUTE_RESOURCE_LIMITS +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 +#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE__SHIFT 0x1b +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L +#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE_MASK 0x78000000L +//COMPUTE_STATIC_THREAD_MGMT_SE0 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE1 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_TMPRING_SIZE +#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 +#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc +#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL +#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L +//COMPUTE_STATIC_THREAD_MGMT_SE2 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE3 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_RESTART_X +#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL +//COMPUTE_RESTART_Y +#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL +//COMPUTE_RESTART_Z +#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL +//COMPUTE_THREAD_TRACE_ENABLE +#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 +#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L +//COMPUTE_MISC_RESERVED +#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 +#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5 +#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x00000003L +#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L +//COMPUTE_DISPATCH_ID +#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0 +#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL +//COMPUTE_THREADGROUP_ID +#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0 +#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL +//COMPUTE_RELAUNCH +#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0 +#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e +#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f +#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL +#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L +#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L +//COMPUTE_WAVE_RESTORE_ADDR_LO +#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0 +#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//COMPUTE_WAVE_RESTORE_ADDR_HI +#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0 +#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xFFFFL +//COMPUTE_TG_CHUNK_SIZE +#define COMPUTE_TG_CHUNK_SIZE__TG_CHUNK_SIZE__SHIFT 0x0 +#define COMPUTE_TG_CHUNK_SIZE__TG_CHUNK_SIZE_MASK 0x0000FFFFL +//COMPUTE_SHADER_CHKSUM +#define COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT 0x0 +#define COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK 0xFFFFFFFFL +//COMPUTE_PGM_RSRC3 +#define COMPUTE_PGM_RSRC3__ACCUM_OFFSET__SHIFT 0x0 +#define COMPUTE_PGM_RSRC3__TRAP_ON_START__SHIFT 0xa +#define COMPUTE_PGM_RSRC3__TRAP_ON_END__SHIFT 0xb +#define COMPUTE_PGM_RSRC3__TG_SPLIT__SHIFT 0x10 +#define COMPUTE_PGM_RSRC3__ACCUM_OFFSET_MASK 0x0000003FL +#define COMPUTE_PGM_RSRC3__TRAP_ON_START_MASK 0x00000400L +#define COMPUTE_PGM_RSRC3__TRAP_ON_END_MASK 0x00000800L +#define COMPUTE_PGM_RSRC3__TG_SPLIT_MASK 0x00010000L +//COMPUTE_USER_DATA_0 +#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_1 +#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_2 +#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_3 +#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_4 +#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_5 +#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_6 +#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_7 +#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_8 +#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_9 +#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_10 +#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_11 +#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_12 +#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_13 +#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_14 +#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_15 +#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL +//COMPUTE_DISPATCH_END +#define COMPUTE_DISPATCH_END__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_END__DATA_MASK 0xFFFFFFFFL +//COMPUTE_NOWHERE +#define COMPUTE_NOWHERE__DATA__SHIFT 0x0 +#define COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: xcd0_gc_cppdec +//CP_DFY_CNTL +#define CP_DFY_CNTL__POLICY__SHIFT 0x0 +#define CP_DFY_CNTL__MTYPE__SHIFT 0x2 +#define CP_DFY_CNTL__WRITE_DIS__SHIFT 0x1b +#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c +#define CP_DFY_CNTL__MODE__SHIFT 0x1d +#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f +#define CP_DFY_CNTL__POLICY_MASK 0x00000001L +#define CP_DFY_CNTL__MTYPE_MASK 0x0000000CL +#define CP_DFY_CNTL__WRITE_DIS_MASK 0x08000000L +#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000L +#define CP_DFY_CNTL__MODE_MASK 0x60000000L +#define CP_DFY_CNTL__ENABLE_MASK 0x80000000L +//CP_DFY_STAT +#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0 +#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10 +#define CP_DFY_STAT__BUSY__SHIFT 0x1f +#define CP_DFY_STAT__BURST_COUNT_MASK 0x0000FFFFL +#define CP_DFY_STAT__TAGS_PENDING_MASK 0x07FF0000L +#define CP_DFY_STAT__BUSY_MASK 0x80000000L +//CP_DFY_ADDR_HI +#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL +//CP_DFY_ADDR_LO +#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5 +#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xFFFFFFE0L +//CP_DFY_DATA_0 +#define CP_DFY_DATA_0__DATA__SHIFT 0x0 +#define CP_DFY_DATA_0__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_1 +#define CP_DFY_DATA_1__DATA__SHIFT 0x0 +#define CP_DFY_DATA_1__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_2 +#define CP_DFY_DATA_2__DATA__SHIFT 0x0 +#define CP_DFY_DATA_2__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_3 +#define CP_DFY_DATA_3__DATA__SHIFT 0x0 +#define CP_DFY_DATA_3__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_4 +#define CP_DFY_DATA_4__DATA__SHIFT 0x0 +#define CP_DFY_DATA_4__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_5 +#define CP_DFY_DATA_5__DATA__SHIFT 0x0 +#define CP_DFY_DATA_5__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_6 +#define CP_DFY_DATA_6__DATA__SHIFT 0x0 +#define CP_DFY_DATA_6__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_7 +#define CP_DFY_DATA_7__DATA__SHIFT 0x0 +#define CP_DFY_DATA_7__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_8 +#define CP_DFY_DATA_8__DATA__SHIFT 0x0 +#define CP_DFY_DATA_8__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_9 +#define CP_DFY_DATA_9__DATA__SHIFT 0x0 +#define CP_DFY_DATA_9__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_10 +#define CP_DFY_DATA_10__DATA__SHIFT 0x0 +#define CP_DFY_DATA_10__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_11 +#define CP_DFY_DATA_11__DATA__SHIFT 0x0 +#define CP_DFY_DATA_11__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_12 +#define CP_DFY_DATA_12__DATA__SHIFT 0x0 +#define CP_DFY_DATA_12__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_13 +#define CP_DFY_DATA_13__DATA__SHIFT 0x0 +#define CP_DFY_DATA_13__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_14 +#define CP_DFY_DATA_14__DATA__SHIFT 0x0 +#define CP_DFY_DATA_14__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_15 +#define CP_DFY_DATA_15__DATA__SHIFT 0x0 +#define CP_DFY_DATA_15__DATA_MASK 0xFFFFFFFFL +//CP_DFY_CMD +#define CP_DFY_CMD__OFFSET__SHIFT 0x0 +#define CP_DFY_CMD__SIZE__SHIFT 0x10 +#define CP_DFY_CMD__OFFSET_MASK 0x000001FFL +#define CP_DFY_CMD__SIZE_MASK 0xFFFF0000L +//CP_EOPQ_WAIT_TIME +#define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x0 +#define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa +#define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003FFL +#define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003FC00L +//CP_CPC_MGCG_SYNC_CNTL +#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0 +#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8 +#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL +#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L +//CPC_INT_INFO +#define CPC_INT_INFO__ADDR_HI__SHIFT 0x0 +#define CPC_INT_INFO__TYPE__SHIFT 0x10 +#define CPC_INT_INFO__VMID__SHIFT 0x14 +#define CPC_INT_INFO__QUEUE_ID__SHIFT 0x1c +#define CPC_INT_INFO__ADDR_HI_MASK 0x0000FFFFL +#define CPC_INT_INFO__TYPE_MASK 0x00010000L +#define CPC_INT_INFO__VMID_MASK 0x00F00000L +#define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L +//CP_VIRT_STATUS +#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0 +#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xFFFFFFFFL +//CPC_INT_ADDR +#define CPC_INT_ADDR__ADDR__SHIFT 0x0 +#define CPC_INT_ADDR__ADDR_MASK 0xFFFFFFFFL +//CPC_INT_PASID +#define CPC_INT_PASID__PASID__SHIFT 0x0 +#define CPC_INT_PASID__PASID_MASK 0x0000FFFFL +//CP_GFX_ERROR +#define CP_GFX_ERROR__EDC_ERROR_ID__SHIFT 0x0 +#define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x4 +#define CP_GFX_ERROR__RSVD1_ERROR__SHIFT 0x5 +#define CP_GFX_ERROR__RSVD2_ERROR__SHIFT 0x6 +#define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT 0x7 +#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT 0x8 +#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x9 +#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa +#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0xb +#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0xc +#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0xd +#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0xe +#define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0xf +#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT 0x10 +#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT 0x11 +#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x12 +#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x13 +#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x14 +#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x15 +#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT 0x16 +#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x17 +#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x18 +#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x19 +#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x1a +#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x1b +#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT 0x1c +#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT 0x1d +#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x1e +#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT 0x1f +#define CP_GFX_ERROR__EDC_ERROR_ID_MASK 0x0000000FL +#define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L +#define CP_GFX_ERROR__RSVD1_ERROR_MASK 0x00000020L +#define CP_GFX_ERROR__RSVD2_ERROR_MASK 0x00000040L +#define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK 0x00000080L +#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK 0x00000100L +#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L +#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L +#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L +#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L +#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L +#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L +#define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L +#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK 0x00010000L +#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK 0x00020000L +#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L +#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L +#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L +#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L +#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK 0x00400000L +#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L +#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L +#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L +#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L +#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L +#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK 0x10000000L +#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK 0x20000000L +#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L +#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK 0x80000000L +//CPG_UTCL1_CNTL +#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define CPG_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT 0x1d +#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e +#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define CPG_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK 0x20000000L +#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L +//CPC_UTCL1_CNTL +#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define CPC_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT 0x1d +#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e +#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define CPC_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK 0x20000000L +#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L +//CPF_UTCL1_CNTL +#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define CPF_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT 0x1d +#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e +#define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x1f +#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define CPF_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK 0x20000000L +#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L +#define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L +//CP_AQL_SMM_STATUS +#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x0 +#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xFFFFFFFFL +//CP_RB0_BASE +#define CP_RB0_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB0_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_RB_BASE +#define CP_RB_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_RB0_CNTL +#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11 +#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_RB0_CNTL__BUF_SWAP_MASK 0x00060000L +#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x01000000L +#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_RB_CNTL__CACHE_POLICY_MASK 0x01000000L +#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 +#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL +//CP_RB0_RPTR_ADDR +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_RB0_RPTR_ADDR_HI +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB_RPTR_ADDR_HI +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB0_BUFSZ_MASK +#define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x0 +#define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000FFFFFL +//CP_RB_BUFSZ_MASK +#define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x0 +#define CP_RB_BUFSZ_MASK__DATA_MASK 0x000FFFFFL +//CP_RB_WPTR_POLL_ADDR_LO +#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2 +#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL +//CP_RB_WPTR_POLL_ADDR_HI +#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0 +#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL +//GC_PRIV_MODE +#define GC_PRIV_MODE__MC_PRIV_MODE__SHIFT 0x0 +#define GC_PRIV_MODE__MC_PRIV_MODE_MASK 0x00000001L +//CP_INT_CNTL +#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_INT_STATUS +#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x10 +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L +//CP_DEVICE_ID +#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000FFL +//CP_ME0_PIPE_PRIORITY_CNTS +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_RING_PRIORITY_CNTS +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_ME0_PIPE0_PRIORITY +#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_RING0_PRIORITY +#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME0_PIPE1_PRIORITY +#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_RING1_PRIORITY +#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME0_PIPE2_PRIORITY +#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_RING2_PRIORITY +#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_FATAL_ERROR +#define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x0 +#define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x1 +#define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x2 +#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x3 +#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x4 +#define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L +#define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L +#define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L +#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L +#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L +//CP_RB_VMID +#define CP_RB_VMID__RB0_VMID__SHIFT 0x0 +#define CP_RB_VMID__RB1_VMID__SHIFT 0x8 +#define CP_RB_VMID__RB2_VMID__SHIFT 0x10 +#define CP_RB_VMID__RB0_VMID_MASK 0x0000000FL +#define CP_RB_VMID__RB1_VMID_MASK 0x00000F00L +#define CP_RB_VMID__RB2_VMID_MASK 0x000F0000L +//CP_ME0_PIPE0_VMID +#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0 +#define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000FL +//CP_ME0_PIPE1_VMID +#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0 +#define CP_ME0_PIPE1_VMID__VMID_MASK 0x0000000FL +//CP_RB0_WPTR +#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB0_WPTR__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB_WPTR__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB0_WPTR_HI +#define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x0 +#define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB_WPTR_HI +#define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x0 +#define CP_RB_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB1_WPTR +#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB1_WPTR__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB1_WPTR_HI +#define CP_RB1_WPTR_HI__RB_WPTR__SHIFT 0x0 +#define CP_RB1_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB2_WPTR +#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB2_WPTR__RB_WPTR_MASK 0x000FFFFFL +//CP_RB_DOORBELL_CONTROL +#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 +#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L +#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_RANGE_LOWER +#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 +#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL +//CP_RB_DOORBELL_RANGE_UPPER +#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 +#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL +//CP_MEC_DOORBELL_RANGE_LOWER +#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 +#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL +//CP_MEC_DOORBELL_RANGE_UPPER +#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 +#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL +//CPG_UTCL1_ERROR +#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 +#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L +//CPC_UTCL1_ERROR +#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 +#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L +//CP_RB1_BASE +#define CP_RB1_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB1_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_RB1_CNTL +#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x01000000L +#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_RB1_RPTR_ADDR +#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_RB1_RPTR_ADDR_HI +#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB2_BASE +#define CP_RB2_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB2_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_RB2_CNTL +#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x01000000L +#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_RB2_RPTR_ADDR +#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_RB2_RPTR_ADDR_HI +#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB0_ACTIVE +#define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L +//CP_RB_ACTIVE +#define CP_RB_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L +//CP_INT_CNTL_RING0 +#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_INT_CNTL_RING1 +#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L +#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x00040000L +#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x00200000L +#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_INT_CNTL_RING2 +#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L +#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x00040000L +#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x00200000L +#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_INT_STATUS_RING0 +#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x10 +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L +#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L +//CP_INT_STATUS_RING1 +#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT 0x10 +#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L +#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK 0x00010000L +#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x00040000L +#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x00200000L +#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L +//CP_INT_STATUS_RING2 +#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT 0x10 +#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L +#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK 0x00010000L +#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x00040000L +#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x00200000L +#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L +//CP_ME_F32_INTERRUPT +#define CP_ME_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0 +#define CP_ME_F32_INTERRUPT__TIME_STAMP_INT__SHIFT 0x1 +#define CP_ME_F32_INTERRUPT__ME_F32_INT_2__SHIFT 0x2 +#define CP_ME_F32_INTERRUPT__ME_F32_INT_3__SHIFT 0x3 +#define CP_ME_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L +#define CP_ME_F32_INTERRUPT__TIME_STAMP_INT_MASK 0x00000002L +#define CP_ME_F32_INTERRUPT__ME_F32_INT_2_MASK 0x00000004L +#define CP_ME_F32_INTERRUPT__ME_F32_INT_3_MASK 0x00000008L +//CP_PFP_F32_INTERRUPT +#define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0 +#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3__SHIFT 0x3 +#define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L +#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L +#define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L +#define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3_MASK 0x00000008L +//CP_CE_F32_INTERRUPT +#define CP_CE_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0 +#define CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x1 +#define CP_CE_F32_INTERRUPT__CE_F32_INT_2__SHIFT 0x2 +#define CP_CE_F32_INTERRUPT__CE_F32_INT_3__SHIFT 0x3 +#define CP_CE_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L +#define CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000002L +#define CP_CE_F32_INTERRUPT__CE_F32_INT_2_MASK 0x00000004L +#define CP_CE_F32_INTERRUPT__CE_F32_INT_3_MASK 0x00000008L +//CP_MEC1_F32_INTERRUPT +#define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT 0x0 +#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT 0x3 +#define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT 0x4 +#define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT 0x5 +#define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT 0x6 +#define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT 0x7 +#define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT 0x8 +#define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT__SHIFT 0x9 +#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF__SHIFT 0xa +#define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA__SHIFT 0xb +#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC__SHIFT 0xc +#define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT 0xd +#define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT 0xe +#define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT 0xf +#define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK 0x00000001L +#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L +#define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L +#define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT_MASK 0x00000008L +#define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT_MASK 0x00000010L +#define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK 0x00000020L +#define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT_MASK 0x00000040L +#define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT_MASK 0x00000080L +#define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT_MASK 0x00000100L +#define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT_MASK 0x00000200L +#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF_MASK 0x00000400L +#define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA_MASK 0x00000800L +#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC_MASK 0x00001000L +#define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK 0x00002000L +#define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK 0x00004000L +#define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK 0x00008000L +//CP_MEC2_F32_INTERRUPT +#define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT 0x0 +#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT 0x3 +#define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT 0x4 +#define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT 0x5 +#define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT 0x6 +#define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT 0x7 +#define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT 0x8 +#define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT__SHIFT 0x9 +#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPF__SHIFT 0xa +#define CP_MEC2_F32_INTERRUPT__GPF_INT_DMA__SHIFT 0xb +#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPC__SHIFT 0xc +#define CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT 0xd +#define CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT 0xe +#define CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT 0xf +#define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK 0x00000001L +#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L +#define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L +#define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT_MASK 0x00000008L +#define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT_MASK 0x00000010L +#define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK 0x00000020L +#define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT_MASK 0x00000040L +#define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT_MASK 0x00000080L +#define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT_MASK 0x00000100L +#define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT_MASK 0x00000200L +#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPF_MASK 0x00000400L +#define CP_MEC2_F32_INTERRUPT__GPF_INT_DMA_MASK 0x00000800L +#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPC_MASK 0x00001000L +#define CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK 0x00002000L +#define CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK 0x00004000L +#define CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK 0x00008000L +//CP_PWR_CNTL +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0 +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13 +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L +//CP_MEM_SLP_CNTL +#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0 +#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1 +#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 +#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10 +#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L +#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L +#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL +#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L +#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000FF00L +#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00FF0000L +#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L +//CP_ECC_DMA_FIRST_OCCURRENCE +#define CP_ECC_DMA_FIRST_OCCURRENCE__INTERFACE__SHIFT 0x0 +#define CP_ECC_DMA_FIRST_OCCURRENCE__CLIENT__SHIFT 0x4 +#define CP_ECC_DMA_FIRST_OCCURRENCE__ME__SHIFT 0x8 +#define CP_ECC_DMA_FIRST_OCCURRENCE__PIPE__SHIFT 0xa +#define CP_ECC_DMA_FIRST_OCCURRENCE__VMID__SHIFT 0x10 +#define CP_ECC_DMA_FIRST_OCCURRENCE__INTERFACE_MASK 0x00000003L +#define CP_ECC_DMA_FIRST_OCCURRENCE__CLIENT_MASK 0x000000F0L +#define CP_ECC_DMA_FIRST_OCCURRENCE__ME_MASK 0x00000300L +#define CP_ECC_DMA_FIRST_OCCURRENCE__PIPE_MASK 0x00000C00L +#define CP_ECC_DMA_FIRST_OCCURRENCE__VMID_MASK 0x000F0000L +//CP_ECC_FIRSTOCCURRENCE +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4 +#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8 +#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa +#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc +#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10 +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L +#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000F0L +#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L +#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000C00L +#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x00007000L +#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000F0000L +//CP_ECC_FIRSTOCCURRENCE_RING0 +#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xFFFFFFFFL +//CP_ECC_FIRSTOCCURRENCE_RING1 +#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xFFFFFFFFL +//CP_ECC_FIRSTOCCURRENCE_RING2 +#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xFFFFFFFFL +//GB_EDC_MODE +#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf +#define GB_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define GB_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define GB_EDC_MODE__DED_MODE__SHIFT 0x14 +#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d +#define GB_EDC_MODE__BYPASS__SHIFT 0x1f +#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L +#define GB_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define GB_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L +#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L +#define GB_EDC_MODE__BYPASS_MASK 0x80000000L +//CP_DEBUG +#define CP_DEBUG__CPG_REPEATER_FGCG_OVERRIDE__SHIFT 0x9 +#define CP_DEBUG__CPG_RAM_CLK_GATING_DISABLE__SHIFT 0xe +#define CP_DEBUG__DISABLE_GFX_HALT_ON_UTCL1_ERROR__SHIFT 0xf +#define CP_DEBUG__SURFSYNC_CNTX_RDADDR__SHIFT 0x10 +#define CP_DEBUG__BUSY_EXTENDER__SHIFT 0x13 +#define CP_DEBUG__PRIV_REG_INTERRUPT_ENABLE__SHIFT 0x15 +#define CP_DEBUG__INTERRUPT_ENABLE__SHIFT 0x16 +#define CP_DEBUG__PREDICATE_DISABLE__SHIFT 0x17 +#define CP_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT 0x18 +#define CP_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT 0x19 +#define CP_DEBUG__EVENT_FILT_DISABLE__SHIFT 0x1a +#define CP_DEBUG__CPG_TC_MTYPE_OVERRIDE__SHIFT 0x1b +#define CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT 0x1c +#define CP_DEBUG__CS_STATE_FILT_DISABLE__SHIFT 0x1d +#define CP_DEBUG__CS_PIPELINE_RESET_DISABLE__SHIFT 0x1e +#define CP_DEBUG__IB_PACKET_INJECTOR_DISABLE__SHIFT 0x1f +#define CP_DEBUG__CPG_REPEATER_FGCG_OVERRIDE_MASK 0x00000200L +#define CP_DEBUG__CPG_RAM_CLK_GATING_DISABLE_MASK 0x00004000L +#define CP_DEBUG__DISABLE_GFX_HALT_ON_UTCL1_ERROR_MASK 0x00008000L +#define CP_DEBUG__SURFSYNC_CNTX_RDADDR_MASK 0x00070000L +#define CP_DEBUG__BUSY_EXTENDER_MASK 0x00180000L +#define CP_DEBUG__PRIV_REG_INTERRUPT_ENABLE_MASK 0x00200000L +#define CP_DEBUG__INTERRUPT_ENABLE_MASK 0x00400000L +#define CP_DEBUG__PREDICATE_DISABLE_MASK 0x00800000L +#define CP_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK 0x01000000L +#define CP_DEBUG__OVERFLOW_BUSY_DISABLE_MASK 0x02000000L +#define CP_DEBUG__EVENT_FILT_DISABLE_MASK 0x04000000L +#define CP_DEBUG__CPG_TC_MTYPE_OVERRIDE_MASK 0x08000000L +#define CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE_MASK 0x10000000L +#define CP_DEBUG__CS_STATE_FILT_DISABLE_MASK 0x20000000L +#define CP_DEBUG__CS_PIPELINE_RESET_DISABLE_MASK 0x40000000L +#define CP_DEBUG__IB_PACKET_INJECTOR_DISABLE_MASK 0x80000000L +//CP_CPF_DEBUG +#define CP_CPF_DEBUG__QUE_MANAGER_CLR_DBELLUPD_DIS__SHIFT 0x6 +#define CP_CPF_DEBUG__CPF_REPEATER_FGCG_OVERRIDE__SHIFT 0x10 +#define CP_CPF_DEBUG__CPF_RAM_CLK_GATING_DISABLE__SHIFT 0x12 +#define CP_CPF_DEBUG__BUSY_EXTENDER__SHIFT 0x13 +#define CP_CPF_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT 0x18 +#define CP_CPF_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT 0x19 +#define CP_CPF_DEBUG__CPF_PRIORITY_YIELD_ACTIVE_DIS__SHIFT 0x1d +#define CP_CPF_DEBUG__CPF_TC_MTYPE_OVERRIDE__SHIFT 0x1e +#define CP_CPF_DEBUG__DBGU_TRIGGER__SHIFT 0x1f +#define CP_CPF_DEBUG__QUE_MANAGER_CLR_DBELLUPD_DIS_MASK 0x00000040L +#define CP_CPF_DEBUG__CPF_REPEATER_FGCG_OVERRIDE_MASK 0x00010000L +#define CP_CPF_DEBUG__CPF_RAM_CLK_GATING_DISABLE_MASK 0x00040000L +#define CP_CPF_DEBUG__BUSY_EXTENDER_MASK 0x00180000L +#define CP_CPF_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK 0x01000000L +#define CP_CPF_DEBUG__OVERFLOW_BUSY_DISABLE_MASK 0x02000000L +#define CP_CPF_DEBUG__CPF_PRIORITY_YIELD_ACTIVE_DIS_MASK 0x20000000L +#define CP_CPF_DEBUG__CPF_TC_MTYPE_OVERRIDE_MASK 0x40000000L +#define CP_CPF_DEBUG__DBGU_TRIGGER_MASK 0x80000000L +//CP_CPC_DEBUG +#define CP_CPC_DEBUG__CPC_PIPE_SEL__SHIFT 0x0 +#define CP_CPC_DEBUG__CPC_ROLLOVER_EVENT_DEBUG_EN__SHIFT 0x3 +#define CP_CPC_DEBUG__CPC_HARVESTING_CONTINUE_DISABLE__SHIFT 0xb +#define CP_CPC_DEBUG__CPC_HARVESTING_RELAUNCH_DISABLE__SHIFT 0xc +#define CP_CPC_DEBUG__CPC_HARVEST_AUTO_DISABLE__SHIFT 0xd +#define CP_CPC_DEBUG__CPC_HARVESTING_DISPATCH_DISABLE__SHIFT 0xe +#define CP_CPC_DEBUG__CPC_REPEATER_FGCG_OVERRIDE__SHIFT 0xf +#define CP_CPC_DEBUG__CPC_RAM_CLK_GATING_DISABLE__SHIFT 0x12 +#define CP_CPC_DEBUG__BUSY_EXTENDER__SHIFT 0x13 +#define CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE__SHIFT 0x15 +#define CP_CPC_DEBUG__RESERVED_INTERRUPT_ENABLE__SHIFT 0x16 +#define CP_CPC_DEBUG__RESTORE_FIFO_EMPTY_SEL__SHIFT 0x17 +#define CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT 0x18 +#define CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT 0x19 +#define CP_CPC_DEBUG__EVENT_FILT_DISABLE__SHIFT 0x1a +#define CP_CPC_DEBUG__PRIV_REG_INTERRUPT_ENABLE__SHIFT 0x1b +#define CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT 0x1c +#define CP_CPC_DEBUG__CS_STATE_FILT_DISABLE__SHIFT 0x1d +#define CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE__SHIFT 0x1f +#define CP_CPC_DEBUG__CPC_PIPE_SEL_MASK 0x00000003L +#define CP_CPC_DEBUG__CPC_ROLLOVER_EVENT_DEBUG_EN_MASK 0x00000008L +#define CP_CPC_DEBUG__CPC_HARVESTING_CONTINUE_DISABLE_MASK 0x00000800L +#define CP_CPC_DEBUG__CPC_HARVESTING_RELAUNCH_DISABLE_MASK 0x00001000L +#define CP_CPC_DEBUG__CPC_HARVEST_AUTO_DISABLE_MASK 0x00002000L +#define CP_CPC_DEBUG__CPC_HARVESTING_DISPATCH_DISABLE_MASK 0x00004000L +#define CP_CPC_DEBUG__CPC_REPEATER_FGCG_OVERRIDE_MASK 0x00008000L +#define CP_CPC_DEBUG__CPC_RAM_CLK_GATING_DISABLE_MASK 0x00040000L +#define CP_CPC_DEBUG__BUSY_EXTENDER_MASK 0x00180000L +#define CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE_MASK 0x00200000L +#define CP_CPC_DEBUG__RESERVED_INTERRUPT_ENABLE_MASK 0x00400000L +#define CP_CPC_DEBUG__RESTORE_FIFO_EMPTY_SEL_MASK 0x00800000L +#define CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK 0x01000000L +#define CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE_MASK 0x02000000L +#define CP_CPC_DEBUG__EVENT_FILT_DISABLE_MASK 0x04000000L +#define CP_CPC_DEBUG__PRIV_REG_INTERRUPT_ENABLE_MASK 0x08000000L +#define CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE_MASK 0x10000000L +#define CP_CPC_DEBUG__CS_STATE_FILT_DISABLE_MASK 0x20000000L +#define CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE_MASK 0x80000000L +//CP_CPC_DEBUG_2 +#define CP_CPC_DEBUG_2__DC_GD_PIPE3_QSWITCH_CNT__SHIFT 0x0 +#define CP_CPC_DEBUG_2__DC_GD_PIPE2_QSWITCH_CNT__SHIFT 0x8 +#define CP_CPC_DEBUG_2__DC_GD_PIPE1_QSWITCH_CNT__SHIFT 0x10 +#define CP_CPC_DEBUG_2__DC_GD_PIPE0_QSWITCH_CNT__SHIFT 0x18 +#define CP_CPC_DEBUG_2__DC_GD_PIPE3_QSWITCH_CNT_MASK 0x000000FFL +#define CP_CPC_DEBUG_2__DC_GD_PIPE2_QSWITCH_CNT_MASK 0x0000FF00L +#define CP_CPC_DEBUG_2__DC_GD_PIPE1_QSWITCH_CNT_MASK 0x00FF0000L +#define CP_CPC_DEBUG_2__DC_GD_PIPE0_QSWITCH_CNT_MASK 0xFF000000L +//CP_PQ_WPTR_POLL_CNTL +#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0 +#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x1d +#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e +#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f +#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000FFL +#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L +#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L +#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L +//CP_PQ_WPTR_POLL_CNTL1 +#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 +#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xFFFFFFFFL +//CP_ME1_PIPE0_INT_CNTL +#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE1_INT_CNTL +#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE2_INT_CNTL +#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE3_INT_CNTL +#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME2_PIPE0_INT_CNTL +#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME2_PIPE1_INT_CNTL +#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME2_PIPE2_INT_CNTL +#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME2_PIPE3_INT_CNTL +#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE0_INT_STATUS +#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME1_PIPE1_INT_STATUS +#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME1_PIPE2_INT_STATUS +#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME1_PIPE3_INT_STATUS +#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME2_PIPE0_INT_STATUS +#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME2_PIPE1_INT_STATUS +#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME2_PIPE2_INT_STATUS +#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME2_PIPE3_INT_STATUS +#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME1_INT_STAT_DEBUG +#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc +#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd +#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe +#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10 +#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 +#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a +#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b +#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d +#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e +#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f +#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x00001000L +#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x00002000L +#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L +#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L +#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L +#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L +#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L +#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L +#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L +#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L +#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L +//CP_ME2_INT_STAT_DEBUG +#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc +#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd +#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe +#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10 +#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 +#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 +#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a +#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b +#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d +#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e +#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f +#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x00001000L +#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x00002000L +#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L +#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L +#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L +#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L +#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L +#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L +#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L +#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L +#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L +#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L +//CC_GC_EDC_CONFIG +#define CC_GC_EDC_CONFIG__WRITE_DIS__SHIFT 0x0 +#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define CC_GC_EDC_CONFIG__ENABLE_IRRITATOR_CLK__SHIFT 0x2 +#define CC_GC_EDC_CONFIG__WRITE_DIS_MASK 0x00000001L +#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define CC_GC_EDC_CONFIG__ENABLE_IRRITATOR_CLK_MASK 0x00000004L +//CP_ME1_PIPE_PRIORITY_CNTS +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_ME1_PIPE0_PRIORITY +#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME1_PIPE1_PRIORITY +#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME1_PIPE2_PRIORITY +#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME1_PIPE3_PRIORITY +#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME2_PIPE_PRIORITY_CNTS +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_ME2_PIPE0_PRIORITY +#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME2_PIPE1_PRIORITY +#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME2_PIPE2_PRIORITY +#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME2_PIPE3_PRIORITY +#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_CE_PRGRM_CNTR_START +#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x000007FFL +//CP_PFP_PRGRM_CNTR_START +#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x00001FFFL +//CP_ME_PRGRM_CNTR_START +#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x00000FFFL +//CP_MEC1_PRGRM_CNTR_START +#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL +//CP_MEC2_PRGRM_CNTR_START +#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL +//CP_CE_INTR_ROUTINE_START +#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x000007FFL +//CP_PFP_INTR_ROUTINE_START +#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x00001FFFL +//CP_ME_INTR_ROUTINE_START +#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x00000FFFL +//CP_MEC1_INTR_ROUTINE_START +#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL +//CP_MEC2_INTR_ROUTINE_START +#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL +//CP_CONTEXT_CNTL +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x00000007L +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x00000070L +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x00070000L +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00700000L +//CP_MAX_CONTEXT +#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0 +#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L +//CP_IQ_WAIT_TIME1 +#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 +#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 +#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 +#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18 +#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL +#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L +#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L +#define CP_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L +//CP_IQ_WAIT_TIME2 +#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 +#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 +#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10 +#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 +#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL +#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L +#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0x00FF0000L +#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L +//CP_RB0_BASE_HI +#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000FFL +//CP_RB1_BASE_HI +#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000FFL +//CP_VMID_RESET +#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0 +#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000FFFFL +//CPC_INT_CNTL +#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CPC_INT_STATUS +#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_VMID_PREEMPT +#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0 +#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10 +#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000FFFFL +#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000F0000L +//CPC_INT_CNTX_ID +#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0 +#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL +//CP_PQ_STATUS +#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0 +#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1 +#define CP_PQ_STATUS__DOORBELL_UPDATED_EN__SHIFT 0x2 +#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L +#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L +#define CP_PQ_STATUS__DOORBELL_UPDATED_EN_MASK 0x00000004L +//CP_CPC_IC_BASE_LO +#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//CP_CPC_IC_BASE_HI +#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL +//CP_CPC_IC_BASE_CNTL +#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x01000000L +//CP_CPC_IC_OP_CNTL +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define CP_CPC_IC_OP_CNTL__ICACHE_INVALIDATED__SHIFT 0x6 +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +#define CP_CPC_IC_OP_CNTL__ICACHE_INVALIDATED_MASK 0x00000040L +//CP_MEC1_F32_INT_DIS +#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 +#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 +#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 +#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 +#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 +#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 +#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 +#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 +#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa +#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb +#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc +#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd +#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe +#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf +#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L +#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L +#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L +#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L +#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L +#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L +#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L +#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L +#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L +#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L +#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L +#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L +#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L +#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L +#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L +#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L +//CP_MEC2_F32_INT_DIS +#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 +#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 +#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 +#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 +#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 +#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 +#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 +#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 +#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa +#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb +#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc +#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd +#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe +#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf +#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L +#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L +#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L +#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L +#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L +#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L +#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L +#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L +#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L +#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L +#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L +#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L +#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L +#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L +#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L +#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L +//CP_VMID_STATUS +#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0 +#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10 +#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL +#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L +//CPC_UE_ERR_STATUS_LO +#define CPC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define CPC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define CPC_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define CPC_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define CPC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define CPC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define CPC_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define CPC_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//CPC_UE_ERR_STATUS_HI +#define CPC_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define CPC_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define CPC_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define CPC_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define CPC_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define CPC_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define CPC_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define CPC_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define CPC_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define CPC_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define CPC_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define CPC_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define CPC_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define CPC_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//CPC_CE_ERR_STATUS_LO +#define CPC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define CPC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define CPC_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define CPC_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define CPC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define CPC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define CPC_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define CPC_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//CPC_CE_ERR_STATUS_HI +#define CPC_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define CPC_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define CPC_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define CPC_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define CPC_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define CPC_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define CPC_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define CPC_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define CPC_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define CPC_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define CPC_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define CPC_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define CPC_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define CPC_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L +//CPF_UE_ERR_STATUS_LO +#define CPF_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define CPF_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define CPF_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define CPF_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define CPF_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define CPF_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define CPF_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define CPF_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//CPF_UE_ERR_STATUS_HI +#define CPF_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define CPF_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define CPF_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define CPF_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define CPF_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define CPF_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define CPF_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define CPF_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define CPF_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define CPF_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define CPF_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define CPF_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define CPF_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define CPF_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//CPF_CE_ERR_STATUS_LO +#define CPF_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define CPF_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define CPF_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define CPF_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define CPF_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define CPF_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define CPF_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define CPF_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//CPF_CE_ERR_STATUS_HI +#define CPF_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define CPF_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define CPF_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define CPF_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define CPF_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define CPF_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define CPF_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define CPF_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define CPF_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define CPF_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define CPF_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define CPF_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define CPF_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define CPF_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L +//CPG_UE_ERR_STATUS_LO +#define CPG_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define CPG_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define CPG_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define CPG_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define CPG_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define CPG_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define CPG_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define CPG_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//CPG_UE_ERR_STATUS_HI +#define CPG_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define CPG_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define CPG_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define CPG_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define CPG_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define CPG_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define CPG_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define CPG_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define CPG_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define CPG_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define CPG_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define CPG_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define CPG_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define CPG_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//CPG_CE_ERR_STATUS_LO +#define CPG_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define CPG_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define CPG_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define CPG_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define CPG_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define CPG_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define CPG_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define CPG_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//CPG_CE_ERR_STATUS_HI +#define CPG_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define CPG_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define CPG_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define CPG_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define CPG_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define CPG_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define CPG_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define CPG_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define CPG_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define CPG_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define CPG_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define CPG_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define CPG_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define CPG_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L + + +// addressBlock: xcd0_gc_cppdec2 +//CP_RB_DOORBELL_CONTROL_SCH_0 +#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CONTROL_SCH_1 +#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CONTROL_SCH_2 +#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CONTROL_SCH_3 +#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CONTROL_SCH_4 +#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CONTROL_SCH_5 +#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CONTROL_SCH_6 +#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CONTROL_SCH_7 +#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT_MASK 0x80000000L +//CP_RB_DOORBELL_CLEAR +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x0 +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x8 +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x9 +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0xb +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0xc +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0xd +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L +//CP_CPF_DSM_CNTL +#define CP_CPF_DSM_CNTL__CPF0_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define CP_CPF_DSM_CNTL__CPF0_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define CP_CPF_DSM_CNTL__CPF1_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define CP_CPF_DSM_CNTL__CPF1_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define CP_CPF_DSM_CNTL__CPF2_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define CP_CPF_DSM_CNTL__CPF2_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define CP_CPF_DSM_CNTL__CPF0_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define CP_CPF_DSM_CNTL__CPF0_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define CP_CPF_DSM_CNTL__CPF1_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define CP_CPF_DSM_CNTL__CPF1_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define CP_CPF_DSM_CNTL__CPF2_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define CP_CPF_DSM_CNTL__CPF2_ENABLE_SINGLE_WRITE_MASK 0x00000100L +//CP_CPG_DSM_CNTL +#define CP_CPG_DSM_CNTL__CPG0_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define CP_CPG_DSM_CNTL__CPG0_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define CP_CPG_DSM_CNTL__CPG1_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define CP_CPG_DSM_CNTL__CPG1_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define CP_CPG_DSM_CNTL__CPG2_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define CP_CPG_DSM_CNTL__CPG2_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define CP_CPG_DSM_CNTL__CPG0_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define CP_CPG_DSM_CNTL__CPG0_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define CP_CPG_DSM_CNTL__CPG1_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define CP_CPG_DSM_CNTL__CPG1_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define CP_CPG_DSM_CNTL__CPG2_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define CP_CPG_DSM_CNTL__CPG2_ENABLE_SINGLE_WRITE_MASK 0x00000100L +//CP_CPC_DSM_CNTL +#define CP_CPC_DSM_CNTL__CPC0_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define CP_CPC_DSM_CNTL__CPC0_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define CP_CPC_DSM_CNTL__CPC1_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define CP_CPC_DSM_CNTL__CPC1_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define CP_CPC_DSM_CNTL__CPC2_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define CP_CPC_DSM_CNTL__CPC2_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define CP_CPC_DSM_CNTL__CPC3_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define CP_CPC_DSM_CNTL__CPC3_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define CP_CPC_DSM_CNTL__CPC4_DSM_IRRITATOR_DATA__SHIFT 0xc +#define CP_CPC_DSM_CNTL__CPC4_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define CP_CPC_DSM_CNTL__CPC5_DSM_IRRITATOR_DATA__SHIFT 0xf +#define CP_CPC_DSM_CNTL__CPC5_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define CP_CPC_DSM_CNTL__CPC6_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define CP_CPC_DSM_CNTL__CPC6_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define CP_CPC_DSM_CNTL__CPC7_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define CP_CPC_DSM_CNTL__CPC7_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define CP_CPC_DSM_CNTL__CPC8_DSM_IRRITATOR_DATA__SHIFT 0x18 +#define CP_CPC_DSM_CNTL__CPC8_ENABLE_SINGLE_WRITE__SHIFT 0x1a +#define CP_CPC_DSM_CNTL__CPC0_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define CP_CPC_DSM_CNTL__CPC0_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define CP_CPC_DSM_CNTL__CPC1_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define CP_CPC_DSM_CNTL__CPC1_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define CP_CPC_DSM_CNTL__CPC2_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define CP_CPC_DSM_CNTL__CPC2_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define CP_CPC_DSM_CNTL__CPC3_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define CP_CPC_DSM_CNTL__CPC3_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define CP_CPC_DSM_CNTL__CPC4_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define CP_CPC_DSM_CNTL__CPC4_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define CP_CPC_DSM_CNTL__CPC5_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define CP_CPC_DSM_CNTL__CPC5_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define CP_CPC_DSM_CNTL__CPC6_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define CP_CPC_DSM_CNTL__CPC6_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define CP_CPC_DSM_CNTL__CPC7_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define CP_CPC_DSM_CNTL__CPC7_ENABLE_SINGLE_WRITE_MASK 0x00800000L +#define CP_CPC_DSM_CNTL__CPC8_DSM_IRRITATOR_DATA_MASK 0x03000000L +#define CP_CPC_DSM_CNTL__CPC8_ENABLE_SINGLE_WRITE_MASK 0x04000000L +//CP_CPF_DSM_CNTL2 +#define CP_CPF_DSM_CNTL2__CPF0_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define CP_CPF_DSM_CNTL2__CPF0_SELECT_INJECT_DELAY__SHIFT 0x2 +#define CP_CPF_DSM_CNTL2__CPF1_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define CP_CPF_DSM_CNTL2__CPF1_SELECT_INJECT_DELAY__SHIFT 0x5 +#define CP_CPF_DSM_CNTL2__CPF2_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define CP_CPF_DSM_CNTL2__CPF2_SELECT_INJECT_DELAY__SHIFT 0x8 +#define CP_CPF_DSM_CNTL2__CPF0_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define CP_CPF_DSM_CNTL2__CPF0_SELECT_INJECT_DELAY_MASK 0x00000004L +#define CP_CPF_DSM_CNTL2__CPF1_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define CP_CPF_DSM_CNTL2__CPF1_SELECT_INJECT_DELAY_MASK 0x00000020L +#define CP_CPF_DSM_CNTL2__CPF2_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define CP_CPF_DSM_CNTL2__CPF2_SELECT_INJECT_DELAY_MASK 0x00000100L +//CP_CPG_DSM_CNTL2 +#define CP_CPG_DSM_CNTL2__CPG0_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define CP_CPG_DSM_CNTL2__CPG0_SELECT_INJECT_DELAY__SHIFT 0x2 +#define CP_CPG_DSM_CNTL2__CPG1_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define CP_CPG_DSM_CNTL2__CPG1_SELECT_INJECT_DELAY__SHIFT 0x5 +#define CP_CPG_DSM_CNTL2__CPG2_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define CP_CPG_DSM_CNTL2__CPG2_SELECT_INJECT_DELAY__SHIFT 0x8 +#define CP_CPG_DSM_CNTL2__CPG0_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define CP_CPG_DSM_CNTL2__CPG0_SELECT_INJECT_DELAY_MASK 0x00000004L +#define CP_CPG_DSM_CNTL2__CPG1_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define CP_CPG_DSM_CNTL2__CPG1_SELECT_INJECT_DELAY_MASK 0x00000020L +#define CP_CPG_DSM_CNTL2__CPG2_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define CP_CPG_DSM_CNTL2__CPG2_SELECT_INJECT_DELAY_MASK 0x00000100L +//CP_CPC_DSM_CNTL2 +#define CP_CPC_DSM_CNTL2__CPC0_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define CP_CPC_DSM_CNTL2__CPC0_SELECT_INJECT_DELAY__SHIFT 0x2 +#define CP_CPC_DSM_CNTL2__CPC1_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define CP_CPC_DSM_CNTL2__CPC1_SELECT_INJECT_DELAY__SHIFT 0x5 +#define CP_CPC_DSM_CNTL2__CPC2_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define CP_CPC_DSM_CNTL2__CPC2_SELECT_INJECT_DELAY__SHIFT 0x8 +#define CP_CPC_DSM_CNTL2__CPC3_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define CP_CPC_DSM_CNTL2__CPC3_SELECT_INJECT_DELAY__SHIFT 0xb +#define CP_CPC_DSM_CNTL2__CPC4_ENABLE_ERROR_INJECT__SHIFT 0xc +#define CP_CPC_DSM_CNTL2__CPC4_SELECT_INJECT_DELAY__SHIFT 0xe +#define CP_CPC_DSM_CNTL2__CPC5_ENABLE_ERROR_INJECT__SHIFT 0xf +#define CP_CPC_DSM_CNTL2__CPC5_SELECT_INJECT_DELAY__SHIFT 0x11 +#define CP_CPC_DSM_CNTL2__CPC6_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define CP_CPC_DSM_CNTL2__CPC6_SELECT_INJECT_DELAY__SHIFT 0x14 +#define CP_CPC_DSM_CNTL2__CPC7_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define CP_CPC_DSM_CNTL2__CPC7_SELECT_INJECT_DELAY__SHIFT 0x17 +#define CP_CPC_DSM_CNTL2__CPC8_ENABLE_ERROR_INJECT__SHIFT 0x18 +#define CP_CPC_DSM_CNTL2__CPC8_SELECT_INJECT_DELAY__SHIFT 0x1a +#define CP_CPC_DSM_CNTL2__CPC0_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define CP_CPC_DSM_CNTL2__CPC0_SELECT_INJECT_DELAY_MASK 0x00000004L +#define CP_CPC_DSM_CNTL2__CPC1_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define CP_CPC_DSM_CNTL2__CPC1_SELECT_INJECT_DELAY_MASK 0x00000020L +#define CP_CPC_DSM_CNTL2__CPC2_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define CP_CPC_DSM_CNTL2__CPC2_SELECT_INJECT_DELAY_MASK 0x00000100L +#define CP_CPC_DSM_CNTL2__CPC3_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define CP_CPC_DSM_CNTL2__CPC3_SELECT_INJECT_DELAY_MASK 0x00000800L +#define CP_CPC_DSM_CNTL2__CPC4_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define CP_CPC_DSM_CNTL2__CPC4_SELECT_INJECT_DELAY_MASK 0x00004000L +#define CP_CPC_DSM_CNTL2__CPC5_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define CP_CPC_DSM_CNTL2__CPC5_SELECT_INJECT_DELAY_MASK 0x00020000L +#define CP_CPC_DSM_CNTL2__CPC6_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define CP_CPC_DSM_CNTL2__CPC6_SELECT_INJECT_DELAY_MASK 0x00100000L +#define CP_CPC_DSM_CNTL2__CPC7_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define CP_CPC_DSM_CNTL2__CPC7_SELECT_INJECT_DELAY_MASK 0x00800000L +#define CP_CPC_DSM_CNTL2__CPC8_ENABLE_ERROR_INJECT_MASK 0x03000000L +#define CP_CPC_DSM_CNTL2__CPC8_SELECT_INJECT_DELAY_MASK 0x04000000L +//CP_CPF_DSM_CNTL2A +#define CP_CPF_DSM_CNTL2A__CPF_INJECT_DELAY__SHIFT 0x0 +#define CP_CPF_DSM_CNTL2A__CPF_INJECT_DELAY_MASK 0x0000003FL +//CP_CPG_DSM_CNTL2A +#define CP_CPG_DSM_CNTL2A__CPG_INJECT_DELAY__SHIFT 0x0 +#define CP_CPG_DSM_CNTL2A__CPG_INJECT_DELAY_MASK 0x0000003FL +//CP_CPC_DSM_CNTL2A +#define CP_CPC_DSM_CNTL2A__CPC_INJECT_DELAY__SHIFT 0x0 +#define CP_CPC_DSM_CNTL2A__CPC_INJECT_DELAY_MASK 0x0000003FL +//CP_EDC_FUE_CNTL +#define CP_EDC_FUE_CNTL__CP_FUE_MASK__SHIFT 0x0 +#define CP_EDC_FUE_CNTL__SPI_FUE_MASK__SHIFT 0x1 +#define CP_EDC_FUE_CNTL__GDS_FUE_MASK__SHIFT 0x2 +#define CP_EDC_FUE_CNTL__TC_RLC_FUE_MASK__SHIFT 0x3 +#define CP_EDC_FUE_CNTL__TC_CPG_FUE_MASK__SHIFT 0x4 +#define CP_EDC_FUE_CNTL__TCA_FUE_MASK__SHIFT 0x5 +#define CP_EDC_FUE_CNTL__TCC_FUE_MASK__SHIFT 0x6 +#define CP_EDC_FUE_CNTL__UTCL2_FUE_MASK__SHIFT 0x7 +#define CP_EDC_FUE_CNTL__CP_FUE_FLAG__SHIFT 0x10 +#define CP_EDC_FUE_CNTL__SPI_FUE_FLAG__SHIFT 0x11 +#define CP_EDC_FUE_CNTL__GDS_FUE_FLAG__SHIFT 0x12 +#define CP_EDC_FUE_CNTL__TC_RLC_FUE_FLAG__SHIFT 0x13 +#define CP_EDC_FUE_CNTL__TC_CPG_FUE_FLAG__SHIFT 0x14 +#define CP_EDC_FUE_CNTL__TCA_FUE_FLAG__SHIFT 0x15 +#define CP_EDC_FUE_CNTL__TCC_FUE_FLAG__SHIFT 0x16 +#define CP_EDC_FUE_CNTL__UTCL2_FUE_FLAG__SHIFT 0x17 +#define CP_EDC_FUE_CNTL__CP_FUE_MASK_MASK 0x00000001L +#define CP_EDC_FUE_CNTL__SPI_FUE_MASK_MASK 0x00000002L +#define CP_EDC_FUE_CNTL__GDS_FUE_MASK_MASK 0x00000004L +#define CP_EDC_FUE_CNTL__TC_RLC_FUE_MASK_MASK 0x00000008L +#define CP_EDC_FUE_CNTL__TC_CPG_FUE_MASK_MASK 0x00000010L +#define CP_EDC_FUE_CNTL__TCA_FUE_MASK_MASK 0x00000020L +#define CP_EDC_FUE_CNTL__TCC_FUE_MASK_MASK 0x00000040L +#define CP_EDC_FUE_CNTL__UTCL2_FUE_MASK_MASK 0x00000080L +#define CP_EDC_FUE_CNTL__CP_FUE_FLAG_MASK 0x00010000L +#define CP_EDC_FUE_CNTL__SPI_FUE_FLAG_MASK 0x00020000L +#define CP_EDC_FUE_CNTL__GDS_FUE_FLAG_MASK 0x00040000L +#define CP_EDC_FUE_CNTL__TC_RLC_FUE_FLAG_MASK 0x00080000L +#define CP_EDC_FUE_CNTL__TC_CPG_FUE_FLAG_MASK 0x00100000L +#define CP_EDC_FUE_CNTL__TCA_FUE_FLAG_MASK 0x00200000L +#define CP_EDC_FUE_CNTL__TCC_FUE_FLAG_MASK 0x00400000L +#define CP_EDC_FUE_CNTL__UTCL2_FUE_FLAG_MASK 0x00800000L +//CP_GFX_MQD_CONTROL +#define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x0 +#define CP_GFX_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 +#define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000FL +#define CP_GFX_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L +#define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L +//CP_GFX_MQD_BASE_ADDR +#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 +#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL +//CP_GFX_MQD_BASE_ADDR_HI +#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL +//CP_RB_STATUS +#define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x0 +#define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x1 +#define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L +#define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L +//CPG_UTCL1_STATUS +#define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//CPC_UTCL1_STATUS +#define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//CPF_UTCL1_STATUS +#define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//CP_SD_CNTL +#define CP_SD_CNTL__CPF_EN__SHIFT 0x0 +#define CP_SD_CNTL__CPG_EN__SHIFT 0x1 +#define CP_SD_CNTL__CPC_EN__SHIFT 0x2 +#define CP_SD_CNTL__RLC_EN__SHIFT 0x3 +#define CP_SD_CNTL__SPI_EN__SHIFT 0x4 +#define CP_SD_CNTL__WD_EN__SHIFT 0x5 +#define CP_SD_CNTL__IA_EN__SHIFT 0x6 +#define CP_SD_CNTL__PA_EN__SHIFT 0x7 +#define CP_SD_CNTL__RMI_EN__SHIFT 0x8 +#define CP_SD_CNTL__EA_EN__SHIFT 0x9 +#define CP_SD_CNTL__CPF_EN_MASK 0x00000001L +#define CP_SD_CNTL__CPG_EN_MASK 0x00000002L +#define CP_SD_CNTL__CPC_EN_MASK 0x00000004L +#define CP_SD_CNTL__RLC_EN_MASK 0x00000008L +#define CP_SD_CNTL__SPI_EN_MASK 0x00000010L +#define CP_SD_CNTL__WD_EN_MASK 0x00000020L +#define CP_SD_CNTL__IA_EN_MASK 0x00000040L +#define CP_SD_CNTL__PA_EN_MASK 0x00000080L +#define CP_SD_CNTL__RMI_EN_MASK 0x00000100L +#define CP_SD_CNTL__EA_EN_MASK 0x00000200L +//CP_SOFT_RESET_CNTL +#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x0 +#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x1 +#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x2 +#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x3 +#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x4 +#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x5 +#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x6 +#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L +#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L +#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L +#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L +#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L +#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L +#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L +//CP_CPC_GFX_CNTL +#define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x0 +#define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x3 +#define CP_CPC_GFX_CNTL__MEID__SHIFT 0x5 +#define CP_CPC_GFX_CNTL__VALID__SHIFT 0x7 +#define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L +#define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L +#define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L +#define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L + + +// addressBlock: xcd0_gc_spipdec +//SPI_ARB_PRIORITY +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9 +#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc +#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe +#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10 +#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001C0L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000E00L +#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L +#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000C000L +#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L +#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000C0000L +//SPI_ARB_CYCLES_0 +#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0 +#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10 +#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000FFFFL +#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xFFFF0000L +//SPI_ARB_CYCLES_1 +#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0 +#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10 +#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000FFFFL +#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xFFFF0000L +//SPI_CDBG_SYS_GFX +#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0 +#define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1 +#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2 +#define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3 +#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4 +#define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5 +#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6 +#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x0001L +#define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x0002L +#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x0004L +#define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x0008L +#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x0010L +#define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x0020L +#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x0040L +//SPI_CDBG_SYS_HP3D +#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0 +#define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1 +#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2 +#define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3 +#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4 +#define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5 +#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x0001L +#define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x0002L +#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x0004L +#define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x0008L +#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x0010L +#define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x0020L +//SPI_CDBG_SYS_CS0 +#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0 +#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8 +#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10 +#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18 +#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0x000000FFL +#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0x0000FF00L +#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0x00FF0000L +#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xFF000000L +//SPI_CDBG_SYS_CS1 +#define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0 +#define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8 +#define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10 +#define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18 +#define SPI_CDBG_SYS_CS1__PIPE0_MASK 0x000000FFL +#define SPI_CDBG_SYS_CS1__PIPE1_MASK 0x0000FF00L +#define SPI_CDBG_SYS_CS1__PIPE2_MASK 0x00FF0000L +#define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xFF000000L +//SPI_WCL_PIPE_PERCENT_GFX +#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7 +#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc +#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11 +#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16 +#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007FL +#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0x00000F80L +#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001F000L +#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x003E0000L +#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07C00000L +//SPI_WCL_PIPE_PERCENT_HP3D +#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc +#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16 +#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007FL +#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001F000L +#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07C00000L +//SPI_WCL_PIPE_PERCENT_CS0 +#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS1 +#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS2 +#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS3 +#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS4 +#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS5 +#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS6 +#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7FL +//SPI_WCL_PIPE_PERCENT_CS7 +#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7FL +//SPI_GDBG_WAVE_CNTL +#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0 +#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x01L +//SPI_GDBG_TRAP_CONFIG +#define SPI_GDBG_TRAP_CONFIG__PIPE0_EN__SHIFT 0x0 +#define SPI_GDBG_TRAP_CONFIG__PIPE1_EN__SHIFT 0x8 +#define SPI_GDBG_TRAP_CONFIG__PIPE2_EN__SHIFT 0x10 +#define SPI_GDBG_TRAP_CONFIG__PIPE3_EN__SHIFT 0x18 +#define SPI_GDBG_TRAP_CONFIG__PIPE0_EN_MASK 0x000000FFL +#define SPI_GDBG_TRAP_CONFIG__PIPE1_EN_MASK 0x0000FF00L +#define SPI_GDBG_TRAP_CONFIG__PIPE2_EN_MASK 0x00FF0000L +#define SPI_GDBG_TRAP_CONFIG__PIPE3_EN_MASK 0xFF000000L +//SPI_GDBG_PER_VMID_CNTL +#define SPI_GDBG_PER_VMID_CNTL__STALL_VMID__SHIFT 0x0 +#define SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE__SHIFT 0x1 +#define SPI_GDBG_PER_VMID_CNTL__TRAP_EN__SHIFT 0x3 +#define SPI_GDBG_PER_VMID_CNTL__EXCP_EN__SHIFT 0x4 +#define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE__SHIFT 0xd +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START__SHIFT 0xe +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END__SHIFT 0xf +#define SPI_GDBG_PER_VMID_CNTL__STALL_VMID_MASK 0x0001L +#define SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE_MASK 0x0006L +#define SPI_GDBG_PER_VMID_CNTL__TRAP_EN_MASK 0x0008L +#define SPI_GDBG_PER_VMID_CNTL__EXCP_EN_MASK 0x1FF0L +#define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE_MASK 0x2000L +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START_MASK 0x4000L +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END_MASK 0x8000L +//SPI_GDBG_WAVE_CNTL3 +#define SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT 0x0 +#define SPI_GDBG_WAVE_CNTL3__STALL_VS__SHIFT 0x1 +#define SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT 0x2 +#define SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT 0x3 +#define SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT 0x4 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT 0x5 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT 0x6 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT 0x7 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT 0x8 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT 0x9 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT 0xa +#define SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT 0xb +#define SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT 0xc +#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT 0xd +#define SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT 0x1c +#define SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK 0x00000001L +#define SPI_GDBG_WAVE_CNTL3__STALL_VS_MASK 0x00000002L +#define SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK 0x00000004L +#define SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK 0x00000008L +#define SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK 0x00000010L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK 0x00000020L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK 0x00000040L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK 0x00000080L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK 0x00000100L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK 0x00000200L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK 0x00000400L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK 0x00000800L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK 0x00001000L +#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK 0x0FFFE000L +#define SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK 0x10000000L +//SPI_SCRATCH_ADDR_CHECK +#define SPI_SCRATCH_ADDR_CHECK__RESERVED__SHIFT 0x0 +#define SPI_SCRATCH_ADDR_CHECK__RESERVED_MASK 0x0FL +//SPI_SCRATCH_ADDR_STATUS +#define SPI_SCRATCH_ADDR_STATUS__WRITE_DIS__SHIFT 0x0 +#define SPI_SCRATCH_ADDR_STATUS__OVERFLOW_DETECTED__SHIFT 0x1 +#define SPI_SCRATCH_ADDR_STATUS__ME_ID__SHIFT 0x2 +#define SPI_SCRATCH_ADDR_STATUS__PIPE_ID__SHIFT 0x4 +#define SPI_SCRATCH_ADDR_STATUS__WRITE_DIS_MASK 0x01L +#define SPI_SCRATCH_ADDR_STATUS__OVERFLOW_DETECTED_MASK 0x02L +#define SPI_SCRATCH_ADDR_STATUS__ME_ID_MASK 0x0CL +#define SPI_SCRATCH_ADDR_STATUS__PIPE_ID_MASK 0x30L +//SPI_RESET_DEBUG +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x01L +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x02L +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x04L +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x08L +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x10L +//SPI_COMPUTE_QUEUE_RESET +#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 +#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L +//SPI_RESOURCE_RESERVE_CU_0 +#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_1 +#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_2 +#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_3 +#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_4 +#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_5 +#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_6 +#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_7 +#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_8 +#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_9 +#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_EN_CU_0 +#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_1 +#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_2 +#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_3 +#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_4 +#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_5 +#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_6 +#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_7 +#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_8 +#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_9 +#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_CU_10 +#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_11 +#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_EN_CU_10 +#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_11 +#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_CU_12 +#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_13 +#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_14 +#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_15 +#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_EN_CU_12 +#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_13 +#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_14 +#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_RESOURCE_RESERVE_EN_CU_15 +#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0x00FF0000L +#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x01000000L +//SPI_COMPUTE_WF_CTX_SAVE +#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0 +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1 +#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2 +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e +#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f +#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x00000002L +#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000L +#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L +//SPI_ARB_CNTL_0 +#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x0 +#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x4 +#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x8 +#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000FL +#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000F0L +#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000F00L + + +// addressBlock: xcd0_gc_cpphqddec +//CP_HQD_GFX_CONTROL +#define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x0 +#define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x4 +#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0xf +#define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000FL +#define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007FF0L +#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L +//CP_HQD_GFX_STATUS +#define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x0 +#define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000FFFFL +//CP_HPD_ROQ_OFFSETS +#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 +#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 +#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 +#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L +#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L +#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x003F0000L +//CP_HPD_STATUS0 +#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 +#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 +#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 +#define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x10 +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x11 +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x12 +#define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14 +#define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK__SHIFT 0x1d +#define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f +#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL +#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L +#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L +#define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L +#define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L +#define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK_MASK 0x20000000L +#define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L +//CP_HPD_UTCL1_CNTL +#define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x0 +#define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000FL +//CP_HPD_UTCL1_ERROR +#define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x0 +#define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x10 +#define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x14 +#define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x0000FFFFL +#define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x00010000L +#define CP_HPD_UTCL1_ERROR__VMID_MASK 0x00F00000L +//CP_HPD_UTCL1_ERROR_ADDR +#define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0xc +#define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xFFFFF000L +//CP_MQD_BASE_ADDR +#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 +#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL +//CP_MQD_BASE_ADDR_HI +#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL +//CP_HQD_ACTIVE +#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1 +#define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L +#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L +//CP_HQD_VMID +#define CP_HQD_VMID__VMID__SHIFT 0x0 +#define CP_HQD_VMID__IB_VMID__SHIFT 0x8 +#define CP_HQD_VMID__VQID__SHIFT 0x10 +#define CP_HQD_VMID__VMID_MASK 0x0000000FL +#define CP_HQD_VMID__IB_VMID_MASK 0x00000F00L +#define CP_HQD_VMID__VQID_MASK 0x03FF0000L +//CP_HQD_PERSISTENT_STATE +#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0 +#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8 +#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x15 +#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16 +#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x17 +#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x18 +#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x19 +#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x1a +#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x1b +#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c +#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d +#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e +#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f +#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L +#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003FF00L +#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L +#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L +#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L +#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L +#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L +#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L +#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L +#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L +#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L +#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L +#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L +//CP_HQD_PIPE_PRIORITY +#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0 +#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L +//CP_HQD_QUEUE_PRIORITY +#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 +#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL +//CP_HQD_QUANTUM +#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 +#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4 +#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 +#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f +#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L +#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L +#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003F00L +#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L +//CP_HQD_PQ_BASE +#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0 +#define CP_HQD_PQ_BASE__ADDR_MASK 0xFFFFFFFFL +//CP_HQD_PQ_BASE_HI +#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x000000FFL +//CP_HQD_PQ_RPTR +#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xFFFFFFFFL +//CP_HQD_PQ_RPTR_REPORT_ADDR +#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2 +#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xFFFFFFFCL +//CP_HQD_PQ_RPTR_REPORT_ADDR_HI +#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x0000FFFFL +//CP_HQD_PQ_WPTR_POLL_ADDR +#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x3 +#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xFFFFFFF8L +//CP_HQD_PQ_WPTR_POLL_ADDR_HI +#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_HQD_PQ_DOORBELL_CONTROL +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L +//CP_HQD_PQ_CONTROL +#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0 +#define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x6 +#define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x7 +#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8 +#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0xe +#define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0xf +#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT 0x10 +#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11 +#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14 +#define CP_HQD_PQ_CONTROL__TMZ__SHIFT 0x16 +#define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19 +#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b +#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c +#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d +#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e +#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f +#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL +#define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L +#define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L +#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L +#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L +#define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L +#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN_MASK 0x00010000L +#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00060000L +#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L +#define CP_HQD_PQ_CONTROL__TMZ_MASK 0x00400000L +#define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x01000000L +#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x06000000L +#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L +#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L +#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000L +#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L +#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L +//CP_HQD_IB_BASE_ADDR +#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2 +#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xFFFFFFFCL +//CP_HQD_IB_BASE_ADDR_HI +#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0 +#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x0000FFFFL +//CP_HQD_IB_RPTR +#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000FFFFFL +//CP_HQD_IB_CONTROL +#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0 +#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14 +#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_IB_CONTROL__IB_PRIV_STATE__SHIFT 0x1e +#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f +#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000FFFFFL +#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L +#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x01000000L +#define CP_HQD_IB_CONTROL__IB_PRIV_STATE_MASK 0x40000000L +#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L +//CP_HQD_IQ_TIMER +#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 +#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 +#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb +#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc +#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe +#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10 +#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 +#define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x19 +#define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c +#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d +#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e +#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f +#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL +#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L +#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L +#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L +#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L +#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003F0000L +#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L +#define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x01000000L +#define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x02000000L +#define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L +#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L +#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L +#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L +//CP_HQD_IQ_RPTR +#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0 +#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003FL +//CP_HQD_DEQUEUE_REQUEST +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000007L +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L +//CP_HQD_DMA_OFFLOAD +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L +//CP_HQD_OFFLOAD +#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 +#define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2 +#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3 +#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L +#define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L +#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L +//CP_HQD_SEMA_CMD +#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0 +#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 +#define CP_HQD_SEMA_CMD__RETRY_MASK 0x00000001L +#define CP_HQD_SEMA_CMD__RESULT_MASK 0x00000006L +//CP_HQD_MSG_TYPE +#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0 +#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4 +#define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L +#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L +//CP_HQD_ATOMIC0_PREOP_LO +#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL +//CP_HQD_ATOMIC0_PREOP_HI +#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL +//CP_HQD_ATOMIC1_PREOP_LO +#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL +//CP_HQD_ATOMIC1_PREOP_HI +#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL +//CP_HQD_HQ_SCHEDULER0 +#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0 +#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xFFFFFFFFL +//CP_HQD_HQ_STATUS0 +#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0 +#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2 +#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4 +#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7 +#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8 +#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9 +#define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT 0xa +#define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e +#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x1f +#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000003L +#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0x0000000CL +#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x00000070L +#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L +#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L +#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x00000200L +#define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK 0x3FFFFC00L +#define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L +#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L +//CP_HQD_HQ_CONTROL0 +#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0 +#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xFFFFFFFFL +//CP_HQD_HQ_SCHEDULER1 +#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0 +#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xFFFFFFFFL +//CP_MQD_CONTROL +#define CP_MQD_CONTROL__VMID__SHIFT 0x0 +#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 +#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc +#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd +#define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_MQD_CONTROL__VMID_MASK 0x0000000FL +#define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L +#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L +#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L +#define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L +//CP_HQD_HQ_STATUS1 +#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0 +#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xFFFFFFFFL +//CP_HQD_HQ_CONTROL1 +#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0 +#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xFFFFFFFFL +//CP_HQD_EOP_BASE_ADDR +#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//CP_HQD_EOP_BASE_ADDR_HI +#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x000000FFL +//CP_HQD_EOP_CONTROL +#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0 +#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8 +#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc +#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd +#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe +#define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x15 +#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x16 +#define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d +#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f +#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003FL +#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L +#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L +#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L +#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L +#define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L +#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L +#define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x01000000L +#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000L +#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000L +//CP_HQD_EOP_RPTR +#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0 +#define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x1c +#define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x1d +#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e +#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f +#define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001FFFL +#define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L +#define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L +#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L +#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L +//CP_HQD_EOP_WPTR +#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0 +#define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0xf +#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10 +#define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001FFFL +#define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L +#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1FFF0000L +//CP_HQD_EOP_EVENTS +#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0 +#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10 +#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000FFFL +#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L +//CP_HQD_CTX_SAVE_BASE_ADDR_LO +#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc +#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L +//CP_HQD_CTX_SAVE_BASE_ADDR_HI +#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_HQD_CTX_SAVE_CONTROL +#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 +#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000008L +#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L +//CP_HQD_CNTL_STACK_OFFSET +#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x0000FFFCL +//CP_HQD_CNTL_STACK_SIZE +#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc +#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x0000F000L +//CP_HQD_WG_STATE_OFFSET +#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x07FFFFFCL +//CP_HQD_CTX_SAVE_SIZE +#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc +#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x07FFF000L +//CP_HQD_GDS_RESOURCE_STATE +#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0 +#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1 +#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4 +#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc +#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L +#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L +#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003F0L +#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003F000L +//CP_HQD_ERROR +#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0 +#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4 +#define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x5 +#define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x8 +#define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x9 +#define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa +#define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0xb +#define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0xc +#define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0xd +#define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT 0xe +#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0xf +#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x10 +#define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x11 +#define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x12 +#define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x13 +#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0x0000000FL +#define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L +#define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L +#define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L +#define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L +#define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L +#define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L +#define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L +#define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L +#define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK 0x00004000L +#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L +#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L +#define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L +#define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L +#define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L +//CP_HQD_EOP_WPTR_MEM +#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0 +#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001FFFL +//CP_HQD_AQL_CONTROL +#define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x0 +#define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0xf +#define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x10 +#define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x1f +#define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007FFFL +#define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L +#define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7FFF0000L +#define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L +//CP_HQD_PQ_WPTR_LO +#define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x0 +#define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xFFFFFFFFL +//CP_HQD_PQ_WPTR_HI +#define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x0 +#define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xFFFFFFFFL +//CP_HQD_AQL_CONTROL_1 +#define CP_HQD_AQL_CONTROL_1__RESERVED__SHIFT 0x0 +#define CP_HQD_AQL_CONTROL_1__RESERVED_MASK 0xFFFFFFFFL +//CP_HQD_AQL_DISPATCH_ID +#define CP_HQD_AQL_DISPATCH_ID__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_AQL_DISPATCH_ID__CONSUMED_OFFSET_MASK 0xFFFFFFFFL +//CP_HQD_AQL_DISPATCH_ID_HI +#define CP_HQD_AQL_DISPATCH_ID_HI__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_AQL_DISPATCH_ID_HI__CONSUMED_OFFSET_MASK 0xFFFFFFFFL + + +// addressBlock: xcd0_gc_tcpdec +//TCP_WATCH0_ADDR_H +#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH0_ADDR_L +#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x7 +#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFF80L +//TCP_WATCH0_CNTL +#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH0_CNTL__ATC__SHIFT 0x1c +#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL +#define TCP_WATCH0_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH0_CNTL__ATC_MASK 0x10000000L +#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L +//TCP_WATCH1_ADDR_H +#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH1_ADDR_L +#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x7 +#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFF80L +//TCP_WATCH1_CNTL +#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH1_CNTL__ATC__SHIFT 0x1c +#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL +#define TCP_WATCH1_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH1_CNTL__ATC_MASK 0x10000000L +#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L +//TCP_WATCH2_ADDR_H +#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH2_ADDR_L +#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x7 +#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFF80L +//TCP_WATCH2_CNTL +#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH2_CNTL__ATC__SHIFT 0x1c +#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL +#define TCP_WATCH2_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH2_CNTL__ATC_MASK 0x10000000L +#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L +//TCP_WATCH3_ADDR_H +#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH3_ADDR_L +#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x7 +#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFF80L +//TCP_WATCH3_CNTL +#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH3_CNTL__ATC__SHIFT 0x1c +#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL +#define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH3_CNTL__ATC_MASK 0x10000000L +#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L +//TCP_GATCL1_CNTL +#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19 +#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a +#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b +#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x02000000L +#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x04000000L +#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x08000000L +#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//TCP_ATC_EDC_GATCL1_CNT +#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0 +#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0x000000FFL +//TCP_GATCL1_DSM_CNTL +#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0 +#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1 +#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2 +#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x00000001L +#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x00000002L +#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x00000004L +//TCP_DSM_CNTL +#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3 +#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 +#define TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x6 +#define TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 +#define TCP_DSM_CNTL__VM_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x9 +#define TCP_DSM_CNTL__VM_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0xb +#define TCP_DSM_CNTL__DB_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc +#define TCP_DSM_CNTL__DB_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe +#define TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_DATA_SEL__SHIFT 0xf +#define TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 +#define TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_DATA_SEL__SHIFT 0x12 +#define TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 +#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x00000003L +#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L +#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL_MASK 0x00000018L +#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L +#define TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_DATA_SEL_MASK 0x000000C0L +#define TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L +#define TCP_DSM_CNTL__VM_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000600L +#define TCP_DSM_CNTL__VM_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L +#define TCP_DSM_CNTL__DB_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L +#define TCP_DSM_CNTL__DB_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L +#define TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_DATA_SEL_MASK 0x00018000L +#define TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L +#define TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_DATA_SEL_MASK 0x000C0000L +#define TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L +//TCP_CNTL2 +#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0 +#define TCP_CNTL2__TCPF_FMT_MGCG_DISABLE__SHIFT 0x8 +#define TCP_CNTL2__TCPI_NEW_MGCG_CTRL_BIT__SHIFT 0xa +#define TCP_CNTL2__MISS_CLK_DISABLE__SHIFT 0xb +#define TCP_CNTL2__ADRS_CLK_DISABLE__SHIFT 0xc +#define TCP_CNTL2__VM_CLK_DISABLE__SHIFT 0xd +#define TCP_CNTL2__TAGRAM_CLK_DISABLE__SHIFT 0xe +#define TCP_CNTL2__LEGACY_MGCG_DISABLE__SHIFT 0xf +#define TCP_CNTL2__MEM_MID_GATE_MGCG_DISABLE__SHIFT 0x13 +#define TCP_CNTL2__UTCL1_MID_GATE_MGCG_DISABLE__SHIFT 0x14 +#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0x000000FFL +#define TCP_CNTL2__TCPF_FMT_MGCG_DISABLE_MASK 0x00000100L +#define TCP_CNTL2__TCPI_NEW_MGCG_CTRL_BIT_MASK 0x00000400L +#define TCP_CNTL2__MISS_CLK_DISABLE_MASK 0x00000800L +#define TCP_CNTL2__ADRS_CLK_DISABLE_MASK 0x00001000L +#define TCP_CNTL2__VM_CLK_DISABLE_MASK 0x00002000L +#define TCP_CNTL2__TAGRAM_CLK_DISABLE_MASK 0x00004000L +#define TCP_CNTL2__LEGACY_MGCG_DISABLE_MASK 0x00008000L +#define TCP_CNTL2__MEM_MID_GATE_MGCG_DISABLE_MASK 0x00080000L +#define TCP_CNTL2__UTCL1_MID_GATE_MGCG_DISABLE_MASK 0x00100000L +//TCP_UTCL1_CNTL1 +#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 +#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define TCP_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 +#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define TCP_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 +#define TCP_UTCL1_CNTL1__UTCL1_FGCG_REPEATER_DISABLE__SHIFT 0x10 +#define TCP_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 +#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 +#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 +#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 +#define TCP_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a +#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L +#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define TCP_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L +#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define TCP_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L +#define TCP_UTCL1_CNTL1__UTCL1_FGCG_REPEATER_DISABLE_MASK 0x00010000L +#define TCP_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L +#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L +#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L +#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L +#define TCP_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L +#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//TCP_UTCL1_CNTL2 +#define TCP_UTCL1_CNTL2__SPARE__SHIFT 0x0 +#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT 0xa +#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc +#define TCP_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf +#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define TCP_UTCL1_CNTL2__THRASHING_TIMEOUT_PROTECT_ENABLE__SHIFT 0x1b +#define TCP_UTCL1_CNTL2__THRASHING_ENABLE__SHIFT 0x1c +#define TCP_UTCL1_CNTL2__SPARE_MASK 0x000000FFL +#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define TCP_UTCL1_CNTL2__ANY_LINE_VALID_MASK 0x00000400L +#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L +#define TCP_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L +#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +#define TCP_UTCL1_CNTL2__THRASHING_TIMEOUT_PROTECT_ENABLE_MASK 0x08000000L +#define TCP_UTCL1_CNTL2__THRASHING_ENABLE_MASK 0x10000000L +//TCP_UTCL1_STATUS +#define TCP_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define TCP_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define TCP_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define TCP_UTCL1_STATUS__TIMEOUT_DETECTED__SHIFT 0x3 +#define TCP_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define TCP_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define TCP_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define TCP_UTCL1_STATUS__TIMEOUT_DETECTED_MASK 0x00000008L +//TCP_DSM_CNTL2 +#define TCP_DSM_CNTL2__CACHE_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define TCP_DSM_CNTL2__CACHE_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define TCP_DSM_CNTL2__LFIFO_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define TCP_DSM_CNTL2__LFIFO_RAM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define TCP_DSM_CNTL2__CMD_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define TCP_DSM_CNTL2__CMD_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 +#define TCP_DSM_CNTL2__VM_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define TCP_DSM_CNTL2__VM_FIFO_SELECT_INJECT_DELAY__SHIFT 0xb +#define TCP_DSM_CNTL2__DB_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define TCP_DSM_CNTL2__DB_RAM_SELECT_INJECT_DELAY__SHIFT 0xe +#define TCP_DSM_CNTL2__UTCL1_LFIFO0_ENABLE_ERROR_INJECT__SHIFT 0xf +#define TCP_DSM_CNTL2__UTCL1_LFIFO0_SELECT_INJECT_DELAY__SHIFT 0x11 +#define TCP_DSM_CNTL2__UTCL1_LFIFO1_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define TCP_DSM_CNTL2__UTCL1_LFIFO1_SELECT_INJECT_DELAY__SHIFT 0x14 +#define TCP_DSM_CNTL2__TCP_INJECT_DELAY__SHIFT 0x1a +#define TCP_DSM_CNTL2__CACHE_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define TCP_DSM_CNTL2__CACHE_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define TCP_DSM_CNTL2__LFIFO_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define TCP_DSM_CNTL2__LFIFO_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define TCP_DSM_CNTL2__CMD_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define TCP_DSM_CNTL2__CMD_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L +#define TCP_DSM_CNTL2__VM_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define TCP_DSM_CNTL2__VM_FIFO_SELECT_INJECT_DELAY_MASK 0x00000800L +#define TCP_DSM_CNTL2__DB_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define TCP_DSM_CNTL2__DB_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define TCP_DSM_CNTL2__UTCL1_LFIFO0_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define TCP_DSM_CNTL2__UTCL1_LFIFO0_SELECT_INJECT_DELAY_MASK 0x00020000L +#define TCP_DSM_CNTL2__UTCL1_LFIFO1_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define TCP_DSM_CNTL2__UTCL1_LFIFO1_SELECT_INJECT_DELAY_MASK 0x00100000L +#define TCP_DSM_CNTL2__TCP_INJECT_DELAY_MASK 0xFC000000L +//TCP_PERFCOUNTER_FILTER +#define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0 +#define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1 +#define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x2 +#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x5 +#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0xb +#define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0xf +#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x14 +#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x16 +#define TCP_PERFCOUNTER_FILTER__GLC__SHIFT 0x19 +#define TCP_PERFCOUNTER_FILTER__SLC__SHIFT 0x1a +#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0x1b +#define TCP_PERFCOUNTER_FILTER__ADDR_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L +#define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L +#define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001CL +#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x000007E0L +#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x00007800L +#define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x000F8000L +#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00300000L +#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x01C00000L +#define TCP_PERFCOUNTER_FILTER__GLC_MASK 0x02000000L +#define TCP_PERFCOUNTER_FILTER__SLC_MASK 0x04000000L +#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x08000000L +#define TCP_PERFCOUNTER_FILTER__ADDR_MODE_MASK 0x70000000L +//TCP_PERFCOUNTER_FILTER_EN +#define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x0 +#define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x1 +#define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x2 +#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x3 +#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x4 +#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x5 +#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x6 +#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x7 +#define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0x8 +#define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT 0x9 +#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xa +#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE__SHIFT 0xb +#define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L +#define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L +#define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L +#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L +#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L +#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L +#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L +#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L +#define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK 0x00000100L +#define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK 0x00000200L +#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000400L +#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE_MASK 0x00000800L + + +// addressBlock: xcd0_gc_gdspdec +//GDS_VMID0_BASE +#define GDS_VMID0_BASE__BASE__SHIFT 0x0 +#define GDS_VMID0_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID0_SIZE +#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID0_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID1_BASE +#define GDS_VMID1_BASE__BASE__SHIFT 0x0 +#define GDS_VMID1_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID1_SIZE +#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID1_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID2_BASE +#define GDS_VMID2_BASE__BASE__SHIFT 0x0 +#define GDS_VMID2_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID2_SIZE +#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID2_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID3_BASE +#define GDS_VMID3_BASE__BASE__SHIFT 0x0 +#define GDS_VMID3_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID3_SIZE +#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID3_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID4_BASE +#define GDS_VMID4_BASE__BASE__SHIFT 0x0 +#define GDS_VMID4_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID4_SIZE +#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID4_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID5_BASE +#define GDS_VMID5_BASE__BASE__SHIFT 0x0 +#define GDS_VMID5_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID5_SIZE +#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID5_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID6_BASE +#define GDS_VMID6_BASE__BASE__SHIFT 0x0 +#define GDS_VMID6_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID6_SIZE +#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID6_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID7_BASE +#define GDS_VMID7_BASE__BASE__SHIFT 0x0 +#define GDS_VMID7_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID7_SIZE +#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID7_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID8_BASE +#define GDS_VMID8_BASE__BASE__SHIFT 0x0 +#define GDS_VMID8_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID8_SIZE +#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID8_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID9_BASE +#define GDS_VMID9_BASE__BASE__SHIFT 0x0 +#define GDS_VMID9_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID9_SIZE +#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID9_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID10_BASE +#define GDS_VMID10_BASE__BASE__SHIFT 0x0 +#define GDS_VMID10_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID10_SIZE +#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID10_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID11_BASE +#define GDS_VMID11_BASE__BASE__SHIFT 0x0 +#define GDS_VMID11_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID11_SIZE +#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID11_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID12_BASE +#define GDS_VMID12_BASE__BASE__SHIFT 0x0 +#define GDS_VMID12_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID12_SIZE +#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID12_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID13_BASE +#define GDS_VMID13_BASE__BASE__SHIFT 0x0 +#define GDS_VMID13_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID13_SIZE +#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID13_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID14_BASE +#define GDS_VMID14_BASE__BASE__SHIFT 0x0 +#define GDS_VMID14_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID14_SIZE +#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID14_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_VMID15_BASE +#define GDS_VMID15_BASE__BASE__SHIFT 0x0 +#define GDS_VMID15_BASE__BASE_MASK 0x0000FFFFL +//GDS_VMID15_SIZE +#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID15_SIZE__SIZE_MASK 0x0001FFFFL +//GDS_GWS_VMID0 +#define GDS_GWS_VMID0__BASE__SHIFT 0x0 +#define GDS_GWS_VMID0__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID0__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID0__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID1 +#define GDS_GWS_VMID1__BASE__SHIFT 0x0 +#define GDS_GWS_VMID1__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID1__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID1__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID2 +#define GDS_GWS_VMID2__BASE__SHIFT 0x0 +#define GDS_GWS_VMID2__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID2__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID2__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID3 +#define GDS_GWS_VMID3__BASE__SHIFT 0x0 +#define GDS_GWS_VMID3__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID3__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID3__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID4 +#define GDS_GWS_VMID4__BASE__SHIFT 0x0 +#define GDS_GWS_VMID4__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID4__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID4__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID5 +#define GDS_GWS_VMID5__BASE__SHIFT 0x0 +#define GDS_GWS_VMID5__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID5__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID5__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID6 +#define GDS_GWS_VMID6__BASE__SHIFT 0x0 +#define GDS_GWS_VMID6__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID6__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID6__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID7 +#define GDS_GWS_VMID7__BASE__SHIFT 0x0 +#define GDS_GWS_VMID7__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID7__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID7__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID8 +#define GDS_GWS_VMID8__BASE__SHIFT 0x0 +#define GDS_GWS_VMID8__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID8__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID8__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID9 +#define GDS_GWS_VMID9__BASE__SHIFT 0x0 +#define GDS_GWS_VMID9__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID9__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID9__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID10 +#define GDS_GWS_VMID10__BASE__SHIFT 0x0 +#define GDS_GWS_VMID10__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID10__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID10__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID11 +#define GDS_GWS_VMID11__BASE__SHIFT 0x0 +#define GDS_GWS_VMID11__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID11__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID11__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID12 +#define GDS_GWS_VMID12__BASE__SHIFT 0x0 +#define GDS_GWS_VMID12__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID12__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID12__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID13 +#define GDS_GWS_VMID13__BASE__SHIFT 0x0 +#define GDS_GWS_VMID13__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID13__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID13__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID14 +#define GDS_GWS_VMID14__BASE__SHIFT 0x0 +#define GDS_GWS_VMID14__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID14__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID14__SIZE_MASK 0x007F0000L +//GDS_GWS_VMID15 +#define GDS_GWS_VMID15__BASE__SHIFT 0x0 +#define GDS_GWS_VMID15__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID15__BASE_MASK 0x0000003FL +#define GDS_GWS_VMID15__SIZE_MASK 0x007F0000L +//GDS_OA_VMID0 +#define GDS_OA_VMID0__MASK__SHIFT 0x0 +#define GDS_OA_VMID0__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID0__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID0__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID1 +#define GDS_OA_VMID1__MASK__SHIFT 0x0 +#define GDS_OA_VMID1__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID1__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID1__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID2 +#define GDS_OA_VMID2__MASK__SHIFT 0x0 +#define GDS_OA_VMID2__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID2__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID2__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID3 +#define GDS_OA_VMID3__MASK__SHIFT 0x0 +#define GDS_OA_VMID3__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID3__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID3__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID4 +#define GDS_OA_VMID4__MASK__SHIFT 0x0 +#define GDS_OA_VMID4__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID4__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID4__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID5 +#define GDS_OA_VMID5__MASK__SHIFT 0x0 +#define GDS_OA_VMID5__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID5__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID5__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID6 +#define GDS_OA_VMID6__MASK__SHIFT 0x0 +#define GDS_OA_VMID6__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID6__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID6__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID7 +#define GDS_OA_VMID7__MASK__SHIFT 0x0 +#define GDS_OA_VMID7__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID7__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID7__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID8 +#define GDS_OA_VMID8__MASK__SHIFT 0x0 +#define GDS_OA_VMID8__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID8__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID8__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID9 +#define GDS_OA_VMID9__MASK__SHIFT 0x0 +#define GDS_OA_VMID9__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID9__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID9__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID10 +#define GDS_OA_VMID10__MASK__SHIFT 0x0 +#define GDS_OA_VMID10__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID10__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID10__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID11 +#define GDS_OA_VMID11__MASK__SHIFT 0x0 +#define GDS_OA_VMID11__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID11__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID11__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID12 +#define GDS_OA_VMID12__MASK__SHIFT 0x0 +#define GDS_OA_VMID12__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID12__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID12__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID13 +#define GDS_OA_VMID13__MASK__SHIFT 0x0 +#define GDS_OA_VMID13__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID13__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID13__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID14 +#define GDS_OA_VMID14__MASK__SHIFT 0x0 +#define GDS_OA_VMID14__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID14__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID14__UNUSED_MASK 0xFFFF0000L +//GDS_OA_VMID15 +#define GDS_OA_VMID15__MASK__SHIFT 0x0 +#define GDS_OA_VMID15__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID15__MASK_MASK 0x0000FFFFL +#define GDS_OA_VMID15__UNUSED_MASK 0xFFFF0000L +//GDS_GWS_RESET0 +#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0 +#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1 +#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2 +#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3 +#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4 +#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5 +#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6 +#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7 +#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8 +#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9 +#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa +#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb +#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc +#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd +#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe +#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf +#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10 +#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11 +#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12 +#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13 +#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14 +#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15 +#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16 +#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17 +#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18 +#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19 +#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a +#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b +#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c +#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d +#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e +#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f +#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x00000001L +#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x00000002L +#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x00000004L +#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x00000008L +#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x00000010L +#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x00000020L +#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x00000040L +#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x00000080L +#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x00000100L +#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x00000200L +#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x00000400L +#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x00000800L +#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x00001000L +#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x00002000L +#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x00004000L +#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x00008000L +#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x00010000L +#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x00020000L +#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x00040000L +#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x00080000L +#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x00100000L +#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x00200000L +#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x00400000L +#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x00800000L +#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x01000000L +#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x02000000L +#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x04000000L +#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x08000000L +#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000L +#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000L +#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000L +#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000L +//GDS_GWS_RESET1 +#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0 +#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1 +#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2 +#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3 +#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4 +#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5 +#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6 +#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7 +#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8 +#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9 +#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa +#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb +#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc +#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd +#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe +#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf +#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10 +#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11 +#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12 +#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13 +#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14 +#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15 +#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16 +#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17 +#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18 +#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19 +#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a +#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b +#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c +#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d +#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e +#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f +#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x00000001L +#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x00000002L +#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x00000004L +#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x00000008L +#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x00000010L +#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x00000020L +#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x00000040L +#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x00000080L +#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x00000100L +#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x00000200L +#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x00000400L +#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x00000800L +#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x00001000L +#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x00002000L +#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x00004000L +#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x00008000L +#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x00010000L +#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x00020000L +#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x00040000L +#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x00080000L +#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x00100000L +#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x00200000L +#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x00400000L +#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x00800000L +#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x01000000L +#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x02000000L +#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x04000000L +#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x08000000L +#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000L +#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000L +#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000L +#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000L +//GDS_GWS_RESOURCE_RESET +#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0 +#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8 +#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L +#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000FF00L +//GDS_COMPUTE_MAX_WAVE_ID +#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL +//GDS_OA_RESET_MASK +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0 +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1 +#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2 +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT 0x3 +#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4 +#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5 +#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6 +#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7 +#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8 +#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9 +#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa +#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb +#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x00000001L +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x00000002L +#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x00000004L +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK 0x00000008L +#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x00000010L +#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x00000020L +#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x00000040L +#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x00000080L +#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x00000100L +#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x00000200L +#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x00000400L +#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x00000800L +#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xFFFFF000L +//GDS_OA_RESET +#define GDS_OA_RESET__RESET__SHIFT 0x0 +#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8 +#define GDS_OA_RESET__RESET_MASK 0x00000001L +#define GDS_OA_RESET__PIPE_ID_MASK 0x0000FF00L +//GDS_ENHANCE +#define GDS_ENHANCE__MISC__SHIFT 0x0 +#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10 +#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11 +#define GDS_ENHANCE__RD_BUF_TAG_MISS__SHIFT 0x12 +#define GDS_ENHANCE__GDSA_PC_CGTS_DIS__SHIFT 0x13 +#define GDS_ENHANCE__GDSO_PC_CGTS_DIS__SHIFT 0x14 +#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE__SHIFT 0x15 +#define GDS_ENHANCE__GDS_CLK_ENHANCE_DIS__SHIFT 0x16 +#define GDS_ENHANCE__DS_MEM_CLK_GATE_DIS__SHIFT 0x17 +#define GDS_ENHANCE__UNUSED__SHIFT 0x18 +#define GDS_ENHANCE__MISC_MASK 0x0000FFFFL +#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L +#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x00020000L +#define GDS_ENHANCE__RD_BUF_TAG_MISS_MASK 0x00040000L +#define GDS_ENHANCE__GDSA_PC_CGTS_DIS_MASK 0x00080000L +#define GDS_ENHANCE__GDSO_PC_CGTS_DIS_MASK 0x00100000L +#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE_MASK 0x00200000L +#define GDS_ENHANCE__GDS_CLK_ENHANCE_DIS_MASK 0x00400000L +#define GDS_ENHANCE__DS_MEM_CLK_GATE_DIS_MASK 0x00800000L +#define GDS_ENHANCE__UNUSED_MASK 0xFF000000L +//GDS_OA_CGPG_RESTORE +#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0 +#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8 +#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc +#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10 +#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14 +#define GDS_OA_CGPG_RESTORE__VMID_MASK 0x000000FFL +#define GDS_OA_CGPG_RESTORE__MEID_MASK 0x00000F00L +#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0x0000F000L +#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0x000F0000L +#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xFFF00000L +//GDS_CS_CTXSW_STATUS +#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0 +#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1 +#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2 +#define GDS_CS_CTXSW_STATUS__R_MASK 0x00000001L +#define GDS_CS_CTXSW_STATUS__W_MASK 0x00000002L +#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL +//GDS_CS_CTXSW_CNT0 +#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_CS_CTXSW_CNT1 +#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_CS_CTXSW_CNT2 +#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_CS_CTXSW_CNT3 +#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_GFX_CTXSW_STATUS +#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0 +#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1 +#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2 +#define GDS_GFX_CTXSW_STATUS__R_MASK 0x00000001L +#define GDS_GFX_CTXSW_STATUS__W_MASK 0x00000002L +#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL +//GDS_VS_CTXSW_CNT0 +#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_VS_CTXSW_CNT1 +#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_VS_CTXSW_CNT2 +#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_VS_CTXSW_CNT3 +#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS0_CTXSW_CNT0 +#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS0_CTXSW_CNT1 +#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS0_CTXSW_CNT2 +#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS0_CTXSW_CNT3 +#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS1_CTXSW_CNT0 +#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS1_CTXSW_CNT1 +#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS1_CTXSW_CNT2 +#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS1_CTXSW_CNT3 +#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS2_CTXSW_CNT0 +#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS2_CTXSW_CNT1 +#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS2_CTXSW_CNT2 +#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS2_CTXSW_CNT3 +#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS3_CTXSW_CNT0 +#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS3_CTXSW_CNT1 +#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS3_CTXSW_CNT2 +#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS3_CTXSW_CNT3 +#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS4_CTXSW_CNT0 +#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS4_CTXSW_CNT1 +#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS4_CTXSW_CNT2 +#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS4_CTXSW_CNT3 +#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS5_CTXSW_CNT0 +#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS5_CTXSW_CNT1 +#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS5_CTXSW_CNT2 +#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS5_CTXSW_CNT3 +#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS6_CTXSW_CNT0 +#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS6_CTXSW_CNT1 +#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS6_CTXSW_CNT2 +#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS6_CTXSW_CNT3 +#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_PS7_CTXSW_CNT0 +#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_PS7_CTXSW_CNT1 +#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_PS7_CTXSW_CNT2 +#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_PS7_CTXSW_CNT3 +#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xFFFF0000L +//GDS_GS_CTXSW_CNT0 +#define GDS_GS_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_GS_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_GS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL +#define GDS_GS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L +//GDS_GS_CTXSW_CNT1 +#define GDS_GS_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_GS_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_GS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL +#define GDS_GS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L +//GDS_GS_CTXSW_CNT2 +#define GDS_GS_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_GS_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_GS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL +#define GDS_GS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L +//GDS_GS_CTXSW_CNT3 +#define GDS_GS_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_GS_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_GS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL +#define GDS_GS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L + + +// addressBlock: xcd0_gc_rasdec +//RAS_SIGNATURE_CONTROL +#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0 +#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x00000001L +//RAS_SIGNATURE_MASK +#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0 +#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xFFFFFFFFL +//RAS_SX_SIGNATURE0 +#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SX_SIGNATURE1 +#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SX_SIGNATURE2 +#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0 +#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SX_SIGNATURE3 +#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0 +#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_DB_SIGNATURE0 +#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_PA_SIGNATURE0 +#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_VGT_SIGNATURE0 +#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SQ_SIGNATURE0 +#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SC_SIGNATURE0 +#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SC_SIGNATURE1 +#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SC_SIGNATURE2 +#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SC_SIGNATURE3 +#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SC_SIGNATURE4 +#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SC_SIGNATURE5 +#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SC_SIGNATURE6 +#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SC_SIGNATURE7 +#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_IA_SIGNATURE0 +#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_IA_SIGNATURE1 +#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SPI_SIGNATURE0 +#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_SPI_SIGNATURE1 +#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_TA_SIGNATURE0 +#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_TD_SIGNATURE0 +#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_CB_SIGNATURE0 +#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_BCI_SIGNATURE0 +#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_BCI_SIGNATURE1 +#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL +//RAS_TA_SIGNATURE1 +#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL + + +// addressBlock: xcd0_gc_gfxdec0 +//DB_RENDER_CONTROL +#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0 +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1 +#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2 +#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3 +#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4 +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5 +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6 +#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7 +#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8 +#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc +#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L +#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L +#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L +#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L +#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L +#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000F00L +#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L +//DB_COUNT_CONTROL +#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0 +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1 +#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4 +#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8 +#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc +#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10 +#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14 +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18 +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c +#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L +#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L +#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000F00L +#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000F000L +#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000F0000L +#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00F00000L +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0F000000L +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xF0000000L +//DB_DEPTH_VIEW +#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0 +#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd +#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18 +#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19 +#define DB_DEPTH_VIEW__MIPID__SHIFT 0x1a +#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007FFL +#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L +#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L +#define DB_DEPTH_VIEW__MIPID_MASK 0x3C000000L +//DB_RENDER_OVERRIDE +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4 +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6 +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7 +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8 +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9 +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa +#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd +#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf +#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10 +#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11 +#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12 +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13 +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15 +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000CL +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L +#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L +#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L +#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L +#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L +#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03E00000L +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L +//DB_RENDER_OVERRIDE2 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2 +#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5 +#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6 +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7 +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8 +#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9 +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa +#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb +#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12 +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15 +#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16 +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 +#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL +#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L +#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L +#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L +#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L +#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001C0000L +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L +#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L +#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L +//DB_HTILE_DATA_BASE +#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0 +#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_HTILE_DATA_BASE_HI +#define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_DEPTH_SIZE +#define DB_DEPTH_SIZE__X_MAX__SHIFT 0x0 +#define DB_DEPTH_SIZE__Y_MAX__SHIFT 0x10 +#define DB_DEPTH_SIZE__X_MAX_MASK 0x00003FFFL +#define DB_DEPTH_SIZE__Y_MAX_MASK 0x3FFF0000L +//DB_DEPTH_BOUNDS_MIN +#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0 +#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xFFFFFFFFL +//DB_DEPTH_BOUNDS_MAX +#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0 +#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xFFFFFFFFL +//DB_STENCIL_CLEAR +#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0 +#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000FFL +//DB_DEPTH_CLEAR +#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0 +#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xFFFFFFFFL +//PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L +//DB_Z_INFO +#define DB_Z_INFO__FORMAT__SHIFT 0x0 +#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2 +#define DB_Z_INFO__SW_MODE__SHIFT 0x4 +#define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT 0xc +#define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT 0xd +#define DB_Z_INFO__ITERATE_FLUSH__SHIFT 0xf +#define DB_Z_INFO__MAXMIP__SHIFT 0x10 +#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17 +#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b +#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c +#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d +#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e +#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f +#define DB_Z_INFO__FORMAT_MASK 0x00000003L +#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000CL +#define DB_Z_INFO__SW_MODE_MASK 0x000001F0L +#define DB_Z_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L +#define DB_Z_INFO__FAULT_BEHAVIOR_MASK 0x00006000L +#define DB_Z_INFO__ITERATE_FLUSH_MASK 0x00008000L +#define DB_Z_INFO__MAXMIP_MASK 0x000F0000L +#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L +#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L +#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L +#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L +#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000L +#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L +//DB_STENCIL_INFO +#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0 +#define DB_STENCIL_INFO__SW_MODE__SHIFT 0x4 +#define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT 0xc +#define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT 0xd +#define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT 0xf +#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d +#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e +#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L +#define DB_STENCIL_INFO__SW_MODE_MASK 0x000001F0L +#define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L +#define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK 0x00006000L +#define DB_STENCIL_INFO__ITERATE_FLUSH_MASK 0x00008000L +#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L +#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000L +//DB_Z_READ_BASE +#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0 +#define DB_Z_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_Z_READ_BASE_HI +#define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_STENCIL_READ_BASE +#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0 +#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_STENCIL_READ_BASE_HI +#define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_Z_WRITE_BASE +#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0 +#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_Z_WRITE_BASE_HI +#define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_STENCIL_WRITE_BASE +#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0 +#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_STENCIL_WRITE_BASE_HI +#define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_DFSM_CONTROL +#define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT 0x0 +#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT 0x2 +#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT 0x3 +#define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L +#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L +#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L +//DB_Z_INFO2 +#define DB_Z_INFO2__EPITCH__SHIFT 0x0 +#define DB_Z_INFO2__EPITCH_MASK 0x0000FFFFL +//DB_STENCIL_INFO2 +#define DB_STENCIL_INFO2__EPITCH__SHIFT 0x0 +#define DB_STENCIL_INFO2__EPITCH_MASK 0x0000FFFFL +//COHER_DEST_BASE_HI_0 +#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_HI_1 +#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_HI_2 +#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_HI_3 +#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xFFFFFFFFL +//COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xFFFFFFFFL +//PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10 +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000FFFFL +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xFFFF0000L +//PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_RULE +#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0 +#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000FFFFL +//PA_SC_CLIPRECT_0_TL +#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_0_BR +#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_1_TL +#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_1_BR +#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_2_TL +#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_2_BR +#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_3_TL +#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_3_BR +#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_EDGERULE +#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0 +#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4 +#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8 +#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc +#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12 +#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18 +#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c +#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000FL +#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000F0L +#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000F00L +#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003F000L +#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00FC0000L +#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0F000000L +#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xF0000000L +//PA_SU_HARDWARE_SCREEN_OFFSET +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001FFL +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01FF0000L +//CB_TARGET_MASK +#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0 +#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4 +#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8 +#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc +#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10 +#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14 +#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18 +#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c +#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000FL +#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000F0L +#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000F00L +#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000F000L +#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000F0000L +#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00F00000L +#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0F000000L +#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xF0000000L +//CB_SHADER_MASK +#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0 +#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4 +#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8 +#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc +#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10 +#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14 +#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18 +#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c +#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000FL +#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000F0L +#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000F00L +#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000F000L +#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000F0000L +#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00F00000L +#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0F000000L +#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xF0000000L +//PA_SC_GENERIC_SCISSOR_TL +#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_GENERIC_SCISSOR_BR +#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L +//COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xFFFFFFFFL +//COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xFFFFFFFFL +//PA_SC_VPORT_SCISSOR_0_TL +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_0_BR +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_1_TL +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_1_BR +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_2_TL +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_2_BR +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_3_TL +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_3_BR +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_4_TL +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_4_BR +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_5_TL +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_5_BR +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_6_TL +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_6_BR +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_7_TL +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_7_BR +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_8_TL +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_8_BR +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_9_TL +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_9_BR +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_10_TL +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_10_BR +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_11_TL +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_11_BR +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_12_TL +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_12_BR +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_13_TL +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_13_BR +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_14_TL +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_14_BR +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_SCISSOR_15_TL +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7FFF0000L +#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +//PA_SC_VPORT_SCISSOR_15_BR +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_VPORT_ZMIN_0 +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_0 +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_1 +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_1 +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_2 +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_2 +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_3 +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_3 +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_4 +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_4 +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_5 +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_5 +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_6 +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_6 +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_7 +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_7 +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_8 +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_8 +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_9 +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_9 +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_10 +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_10 +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_11 +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_11 +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_12 +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_12 +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_13 +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_13 +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_14 +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_14 +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_15 +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_15 +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_SC_RASTER_CONFIG +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0 +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2 +#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4 +#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6 +#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7 +#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8 +#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa +#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc +#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe +#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10 +#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12 +#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14 +#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18 +#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a +#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1d +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000CL +#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L +#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L +#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L +#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L +#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000C00L +#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L +#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000C000L +#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L +#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000C0000L +#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L +#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L +#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x1C000000L +#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0xE0000000L +//PA_SC_RASTER_CONFIG_1 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x5 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000001CL +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x000000E0L +//PA_SC_SCREEN_EXTENT_CONTROL +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2 +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000CL +//PA_SC_TILE_STEERING_OVERRIDE +#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0 +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1 +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5 +#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT 0x8 +#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L +#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK 0x00000100L +//CP_PERFMON_CNTX_CNTL +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L +//CP_PIPEID +#define CP_PIPEID__PIPE_ID__SHIFT 0x0 +#define CP_PIPEID__PIPE_ID_MASK 0x00000003L +//CP_RINGID +#define CP_RINGID__RINGID__SHIFT 0x0 +#define CP_RINGID__RINGID_MASK 0x00000003L +//CP_VMID +#define CP_VMID__VMID__SHIFT 0x0 +#define CP_VMID__VMID_MASK 0x0000000FL +//PA_SC_RIGHT_VERT_GRID +#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT 0x0 +#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT 0x8 +#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT 0x10 +#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT 0x18 +#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL +#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L +#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L +#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L +//PA_SC_LEFT_VERT_GRID +#define PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT 0x0 +#define PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT 0x8 +#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT 0x10 +#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT 0x18 +#define PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL +#define PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L +#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L +#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L +//PA_SC_HORIZ_GRID +#define PA_SC_HORIZ_GRID__TOP_QTR__SHIFT 0x0 +#define PA_SC_HORIZ_GRID__TOP_HALF__SHIFT 0x8 +#define PA_SC_HORIZ_GRID__BOT_HALF__SHIFT 0x10 +#define PA_SC_HORIZ_GRID__BOT_QTR__SHIFT 0x18 +#define PA_SC_HORIZ_GRID__TOP_QTR_MASK 0x000000FFL +#define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000FF00L +#define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00FF0000L +#define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xFF000000L +//VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL +//CB_BLEND_RED +#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 +#define CB_BLEND_RED__BLEND_RED_MASK 0xFFFFFFFFL +//CB_BLEND_GREEN +#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 +#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xFFFFFFFFL +//CB_BLEND_BLUE +#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 +#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xFFFFFFFFL +//CB_BLEND_ALPHA +#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 +#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xFFFFFFFFL +//CB_DCC_CONTROL +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1 +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2 +#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01__SHIFT 0x8 +#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE__SHIFT 0x9 +#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0xa +#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01__SHIFT 0xc +#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE__SHIFT 0xd +#define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG__SHIFT 0xe +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x00000002L +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x0000007CL +#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01_MASK 0x00000100L +#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE_MASK 0x00000200L +#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00000400L +#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01_MASK 0x00001000L +#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE_MASK 0x00002000L +#define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG_MASK 0x00004000L +//DB_STENCIL_CONTROL +#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0 +#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4 +#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8 +#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc +#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10 +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14 +#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000FL +#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000F0L +#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000F00L +#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000F000L +#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000F0000L +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00F00000L +//DB_STENCILREFMASK +#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0 +#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8 +#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10 +#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18 +#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000FFL +#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000FF00L +#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00FF0000L +#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xFF000000L +//DB_STENCILREFMASK_BF +#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0 +#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8 +#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10 +#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18 +#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000FFL +#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000FF00L +#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00FF0000L +#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xFF000000L +//PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_1 +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_1 +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_1 +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_1 +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_1 +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_1 +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_2 +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_2 +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_2 +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_2 +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_2 +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_2 +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_3 +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_3 +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_3 +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_3 +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_3 +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_3 +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_4 +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_4 +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_4 +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_4 +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_4 +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_4 +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_5 +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_5 +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_5 +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_5 +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_5 +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_5 +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_6 +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_6 +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_6 +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_6 +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_6 +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_6 +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_7 +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_7 +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_7 +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_7 +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_7 +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_7 +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_8 +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_8 +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_8 +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_8 +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_8 +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_8 +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_9 +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_9 +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_9 +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_9 +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_9 +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_9 +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_10 +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_10 +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_10 +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_10 +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_10 +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_10 +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_11 +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_11 +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_11 +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_11 +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_11 +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_11 +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_12 +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_12 +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_12 +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_12 +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_12 +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_12 +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_13 +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_13 +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_13 +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_13 +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_13 +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_13 +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_14 +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_14 +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_14 +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_14 +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_14 +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_14 +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_15 +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_15 +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_15 +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_15 +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_15 +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_15 +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_X +#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_Y +#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_Z +#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_W +#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_X +#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_Y +#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_Z +#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_W +#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_X +#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_Y +#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_Z +#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_W +#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_X +#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_Y +#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_Z +#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_W +#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_X +#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_Y +#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_Z +#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_W +#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_X +#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_Y +#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_Z +#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_W +#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_PROG_NEAR_CLIP_Z +#define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//SPI_PS_INPUT_CNTL_0 +#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_1 +#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_2 +#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_3 +#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_4 +#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_5 +#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_6 +#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_7 +#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_8 +#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_9 +#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_10 +#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_11 +#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_12 +#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_13 +#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_14 +#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_15 +#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_16 +#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_17 +#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_18 +#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_19 +#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001E000L +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_20 +#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_21 +#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_22 +#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_23 +#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_24 +#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_25 +#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_26 +#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_27 +#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_28 +#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_29 +#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_30 +#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_31 +#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L +//SPI_VS_OUT_CONFIG +#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1 +#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6 +#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003EL +#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L +//SPI_PS_INPUT_ENA +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0 +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1 +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2 +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3 +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4 +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5 +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6 +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8 +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9 +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L +//SPI_PS_INPUT_ADDR +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0 +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1 +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2 +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3 +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6 +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8 +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9 +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L +//SPI_INTERP_CONTROL_0 +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001CL +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000E0L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L +//SPI_PS_IN_CONTROL +#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 +#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6 +#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT 0x7 +#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT 0x8 +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe +#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003FL +#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L +#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK 0x00000080L +#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK 0x00000100L +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L +//SPI_BARYC_CNTL +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0 +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4 +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8 +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10 +#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14 +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18 +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L +#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L +//SPI_TMPRING_SIZE +#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0 +#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc +#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000FFFL +#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L +//SPI_SHADER_POS_FORMAT +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4 +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8 +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000FL +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000F0L +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000F00L +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000F000L +//SPI_SHADER_Z_FORMAT +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000FL +//SPI_SHADER_COL_FORMAT +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4 +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8 +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10 +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14 +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18 +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000FL +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000F0L +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000F00L +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000F000L +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000F0000L +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00F00000L +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0F000000L +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xF0000000L +//CB_BLEND0_CONTROL +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND1_CONTROL +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND2_CONTROL +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND3_CONTROL +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND4_CONTROL +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND5_CONTROL +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND6_CONTROL +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND7_CONTROL +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_MRT0_EPITCH +#define CB_MRT0_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT0_EPITCH__EPITCH_MASK 0x0000FFFFL +//CB_MRT1_EPITCH +#define CB_MRT1_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT1_EPITCH__EPITCH_MASK 0x0000FFFFL +//CB_MRT2_EPITCH +#define CB_MRT2_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT2_EPITCH__EPITCH_MASK 0x0000FFFFL +//CB_MRT3_EPITCH +#define CB_MRT3_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT3_EPITCH__EPITCH_MASK 0x0000FFFFL +//CB_MRT4_EPITCH +#define CB_MRT4_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT4_EPITCH__EPITCH_MASK 0x0000FFFFL +//CB_MRT5_EPITCH +#define CB_MRT5_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT5_EPITCH__EPITCH_MASK 0x0000FFFFL +//CB_MRT6_EPITCH +#define CB_MRT6_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT6_EPITCH__EPITCH_MASK 0x0000FFFFL +//CB_MRT7_EPITCH +#define CB_MRT7_EPITCH__EPITCH__SHIFT 0x0 +#define CB_MRT7_EPITCH__EPITCH_MASK 0x0000FFFFL +//CS_COPY_STATE +#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 +#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L +//GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 +#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L +//PA_CL_POINT_X_RAD +#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_POINT_Y_RAD +#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_POINT_SIZE +#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_POINT_CULL_RAD +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL +//VGT_DMA_BASE_HI +#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0 +#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000FFFFL +//VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0 +#define VGT_DMA_BASE__BASE_ADDR_MASK 0xFFFFFFFFL +//VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0 +#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2 +#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4 +#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5 +#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6 +#define VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT 0x7 +#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT 0x8 +#define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x1d +#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L +#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000CL +#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L +#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L +#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L +#define VGT_DRAW_INITIATOR__UNROLLED_INST_MASK 0x00000080L +#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK 0x00000100L +#define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xE0000000L +//VGT_IMMED_DATA +#define VGT_IMMED_DATA__DATA__SHIFT 0x0 +#define VGT_IMMED_DATA__DATA_MASK 0xFFFFFFFFL +//VGT_EVENT_ADDRESS_REG +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0 +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0FFFFFFFL +//DB_DEPTH_CONTROL +#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0 +#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1 +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2 +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3 +#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4 +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7 +#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8 +#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14 +#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e +#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f +#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L +#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L +#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L +#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L +#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L +#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L +#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L +//DB_EQAA +#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0 +#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4 +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8 +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10 +#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11 +#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12 +#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13 +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14 +#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15 +#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18 +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b +#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L +#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L +#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L +#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L +#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L +#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L +#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L +//CB_COLOR_CONTROL +#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0 +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3 +#define CB_COLOR_CONTROL__MODE__SHIFT 0x4 +#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10 +#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L +#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L +#define CB_COLOR_CONTROL__ROP3_MASK 0x00FF0000L +//DB_SHADER_CONTROL +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0 +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1 +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2 +#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4 +#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6 +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7 +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8 +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9 +#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd +#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf +#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x10 +#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT 0x11 +#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT 0x14 +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L +#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L +#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L +#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L +#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L +#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L +#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK 0x00020000L +#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK 0x00700000L +//PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 +#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1 +#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2 +#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 +#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4 +#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd +#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe +#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10 +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15 +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16 +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18 +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19 +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b +#define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA__SHIFT 0x1c +#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L +#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L +#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L +#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L +#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L +#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L +#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000C000L +#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L +#define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA_MASK 0x10000000L +//PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0 +#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1 +#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2 +#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10 +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 +#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x16 +#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x17 +#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L +#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L +#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000E0L +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L +#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L +#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L +//PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0 +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5 +#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8 +#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9 +#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L +#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L +#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L +#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L +//PA_CL_VS_OUT_CNTL +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10 +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11 +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12 +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13 +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 +#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19 +#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a +#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT 0x1b +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x04000000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK 0x08000000L +//PA_CL_NANINF_CNTL +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0 +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1 +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2 +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3 +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4 +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5 +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6 +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7 +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8 +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9 +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14 +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L +//PA_SU_LINE_STIPPLE_CNTL +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2 +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3 +#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4 +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L +#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L +//PA_SU_LINE_STIPPLE_SCALE +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xFFFFFFFFL +//PA_SU_PRIM_FILTER_CNTL +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0 +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1 +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4 +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5 +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7 +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8 +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000FF00L +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L +//PA_SU_SMALL_PRIM_FILTER_CNTL +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x0 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x1 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE__SHIFT 0x5 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE__SHIFT 0x6 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE_MASK 0x00000020L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE_MASK 0x00000040L +//PA_CL_OBJPRIM_ID_CNTL +#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x0 +#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x1 +#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID__SHIFT 0x2 +#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK 0x00000001L +#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK 0x00000002L +#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID_MASK 0x00000004L +//PA_CL_NGG_CNTL +#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x0 +#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x1 +#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L +#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L +//PA_SU_OVER_RASTERIZATION_CNTL +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x0 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x1 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x2 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x3 +#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x4 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L +#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L +//PA_STEREO_CNTL +#define PA_STEREO_CNTL__EN_STEREO__SHIFT 0x0 +#define PA_STEREO_CNTL__STEREO_MODE__SHIFT 0x1 +#define PA_STEREO_CNTL__RT_SLICE_MODE__SHIFT 0x5 +#define PA_STEREO_CNTL__RT_SLICE_OFFSET__SHIFT 0x8 +#define PA_STEREO_CNTL__VP_ID_MODE__SHIFT 0xa +#define PA_STEREO_CNTL__VP_ID_OFFSET__SHIFT 0xd +#define PA_STEREO_CNTL__EN_STEREO_MASK 0x00000001L +#define PA_STEREO_CNTL__STEREO_MODE_MASK 0x0000001EL +#define PA_STEREO_CNTL__RT_SLICE_MODE_MASK 0x000000E0L +#define PA_STEREO_CNTL__RT_SLICE_OFFSET_MASK 0x00000300L +#define PA_STEREO_CNTL__VP_ID_MODE_MASK 0x00001C00L +#define PA_STEREO_CNTL__VP_ID_OFFSET_MASK 0x0001E000L +//PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 +#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 +#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000FFFFL +#define PA_SU_POINT_SIZE__WIDTH_MASK 0xFFFF0000L +//PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0 +#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10 +#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000FFFFL +#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xFFFF0000L +//PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0 +#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000FFFFL +//PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0 +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d +#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000FFFFL +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00FF0000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L +//VGT_OUTPUT_PATH_CNTL +#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0 +#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L +//VGT_HOS_CNTL +#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0 +#define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L +//VGT_HOS_MAX_TESS_LEVEL +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0 +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xFFFFFFFFL +//VGT_HOS_MIN_TESS_LEVEL +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0 +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xFFFFFFFFL +//VGT_HOS_REUSE_DEPTH +#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0 +#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000FFL +//VGT_GROUP_PRIM_TYPE +#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0 +#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe +#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf +#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10 +#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001FL +#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L +#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L +#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L +//VGT_GROUP_FIRST_DECR +#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0 +#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000FL +//VGT_GROUP_DECR +#define VGT_GROUP_DECR__DECR__SHIFT 0x0 +#define VGT_GROUP_DECR__DECR_MASK 0x0000000FL +//VGT_GROUP_VECT_0_CNTL +#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0 +#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1 +#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2 +#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3 +#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8 +#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10 +#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L +#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L +#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L +#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L +#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000FF00L +#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00FF0000L +//VGT_GROUP_VECT_1_CNTL +#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0 +#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1 +#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2 +#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3 +#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8 +#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10 +#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L +#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L +#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L +#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L +#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000FF00L +#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00FF0000L +//VGT_GROUP_VECT_0_FMT_CNTL +#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0 +#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10 +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c +#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000FL +#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000F0L +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000F00L +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000F0000L +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L +#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0F000000L +#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xF0000000L +//VGT_GROUP_VECT_1_FMT_CNTL +#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0 +#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10 +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c +#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000FL +#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000F0L +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000F00L +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000F0000L +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L +#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0F000000L +#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xF0000000L +//VGT_GS_MODE +#define VGT_GS_MODE__MODE__SHIFT 0x0 +#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3 +#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4 +#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6 +#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb +#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc +#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd +#define VGT_GS_MODE__RESERVED_3__SHIFT 0xe +#define VGT_GS_MODE__RESERVED_4__SHIFT 0xf +#define VGT_GS_MODE__RESERVED_5__SHIFT 0x10 +#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11 +#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12 +#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13 +#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14 +#define VGT_GS_MODE__ONCHIP__SHIFT 0x15 +#define VGT_GS_MODE__MODE_MASK 0x00000007L +#define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L +#define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L +#define VGT_GS_MODE__RESERVED_1_MASK 0x000007C0L +#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L +#define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L +#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L +#define VGT_GS_MODE__RESERVED_3_MASK 0x00004000L +#define VGT_GS_MODE__RESERVED_4_MASK 0x00008000L +#define VGT_GS_MODE__RESERVED_5_MASK 0x00010000L +#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L +#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L +#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L +#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L +#define VGT_GS_MODE__ONCHIP_MASK 0x00600000L +//VGT_GS_ONCHIP_CNTL +#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0 +#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb +#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT 0x16 +#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x000007FFL +#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x003FF800L +#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK 0xFFC00000L +//PA_SC_MODE_CNTL_0 +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0 +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1 +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2 +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3 +#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT 0x4 +#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x5 +#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x6 +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L +#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK 0x00000010L +#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L +#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L +//PA_SC_MODE_CNTL_1 +#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0 +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1 +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4 +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7 +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8 +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9 +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10 +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c +#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00F00000L +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L +//VGT_ENHANCE +#define VGT_ENHANCE__MISC__SHIFT 0x0 +#define VGT_ENHANCE__MISC_MASK 0xFFFFFFFFL +//VGT_GS_PER_ES +#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0 +#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007FFL +//VGT_ES_PER_GS +#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0 +#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007FFL +//VGT_GS_PER_VS +#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0 +#define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000FL +//VGT_GSVS_RING_OFFSET_1 +#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0 +#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007FFFL +//VGT_GSVS_RING_OFFSET_2 +#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0 +#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007FFFL +//VGT_GSVS_RING_OFFSET_3 +#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0 +#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007FFFL +//VGT_GS_OUT_PRIM_TYPE +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16 +#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003FL +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003F00L +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003F0000L +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0FC00000L +#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L +//IA_ENHANCE +#define IA_ENHANCE__MISC__SHIFT 0x0 +#define IA_ENHANCE__MISC_MASK 0xFFFFFFFFL +//VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0 +#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xFFFFFFFFL +//VGT_DMA_MAX_SIZE +#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0 +#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xFFFFFFFFL +//VGT_DMA_INDEX_TYPE +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2 +#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4 +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6 +#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8 +#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9 +#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000CL +#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x00000040L +#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L +#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L +#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L +//WD_ENHANCE +#define WD_ENHANCE__MISC__SHIFT 0x0 +#define WD_ENHANCE__MISC_MASK 0xFFFFFFFFL +//VGT_PRIMITIVEID_EN +#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0 +#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1 +#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x2 +#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L +#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L +#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L +//VGT_DMA_NUM_INSTANCES +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL +//VGT_PRIMITIVEID_RESET +#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0 +#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xFFFFFFFFL +//VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 +#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b +#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL +#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L +//VGT_GS_MAX_PRIMS_PER_SUBGROUP +#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP__SHIFT 0x0 +#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP_MASK 0x0000FFFFL +//VGT_DRAW_PAYLOAD_CNTL +#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT 0x0 +#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x1 +#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID__SHIFT 0x2 +#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT 0x3 +#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK 0x00000001L +#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L +#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK 0x00000004L +#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000008L +//VGT_INSTANCE_STEP_RATE_0 +#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0 +#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL +//VGT_INSTANCE_STEP_RATE_1 +#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0 +#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xFFFFFFFFL +//IA_MULTI_VGT_PARAM_BC +//VGT_ESGS_RING_ITEMSIZE +#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 +#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL +//VGT_GSVS_RING_ITEMSIZE +#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 +#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL +//VGT_REUSE_OFF +#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0 +#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L +//VGT_VTX_CNT_EN +#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0 +#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L +//DB_HTILE_SURFACE +#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1 +#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2 +#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3 +#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4 +#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 +#define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT 0x12 +#define DB_HTILE_SURFACE__RB_ALIGNED__SHIFT 0x13 +#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L +#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x00000004L +#define DB_HTILE_SURFACE__PRELOAD_MASK 0x00000008L +#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x000003F0L +#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0x0000FC00L +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L +#define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK 0x00040000L +#define DB_HTILE_SURFACE__RB_ALIGNED_MASK 0x00080000L +//DB_SRESULTS_COMPARE_STATE0 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc +#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000FF0L +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000FF000L +#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L +//DB_SRESULTS_COMPARE_STATE1 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc +#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000FF0L +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000FF000L +#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L +//DB_PRELOAD_CONTROL +#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0 +#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8 +#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10 +#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18 +#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000FFL +#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000FF00L +#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00FF0000L +#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xFF000000L +//VGT_STRMOUT_BUFFER_SIZE_0 +#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_VTX_STRIDE_0 +#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003FFL +//VGT_STRMOUT_BUFFER_OFFSET_0 +#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xFFFFFFFFL +//VGT_STRMOUT_BUFFER_SIZE_1 +#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_VTX_STRIDE_1 +#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003FFL +//VGT_STRMOUT_BUFFER_OFFSET_1 +#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xFFFFFFFFL +//VGT_STRMOUT_BUFFER_SIZE_2 +#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_VTX_STRIDE_2 +#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003FFL +//VGT_STRMOUT_BUFFER_OFFSET_2 +#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xFFFFFFFFL +//VGT_STRMOUT_BUFFER_SIZE_3 +#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_VTX_STRIDE_3 +#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003FFL +//VGT_STRMOUT_BUFFER_OFFSET_3 +#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xFFFFFFFFL +//VGT_STRMOUT_DRAW_OPAQUE_OFFSET +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xFFFFFFFFL +//VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001FFL +//VGT_GS_MAX_VERT_OUT +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0 +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007FFL +//VGT_TESS_DISTRIBUTION +#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0 +#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8 +#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10 +#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18 +#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x1d +#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000FFL +#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000FF00L +#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00FF0000L +#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1F000000L +#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xE0000000L +//VGT_SHADER_STAGES_EN +#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0 +#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2 +#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3 +#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5 +#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6 +#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9 +#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa +#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb +#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc +#define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT 0xd +#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT 0xe +#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT 0xf +#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x13 +#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L +#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L +#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L +#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L +#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000C0L +#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x00000200L +#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x00000400L +#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x00000800L +#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x00001000L +#define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK 0x00002000L +#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK 0x00004000L +#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK 0x00078000L +#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00180000L +//VGT_LS_HS_CONFIG +#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0 +#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe +#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000FFL +#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000FC000L +//VGT_GS_VERT_ITEMSIZE +#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL +//VGT_GS_VERT_ITEMSIZE_1 +#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007FFFL +//VGT_GS_VERT_ITEMSIZE_2 +#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007FFFL +//VGT_GS_VERT_ITEMSIZE_3 +#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007FFFL +//VGT_TF_PARAM +#define VGT_TF_PARAM__TYPE__SHIFT 0x0 +#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2 +#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5 +#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8 +#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9 +#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe +#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf +#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11 +#define VGT_TF_PARAM__TYPE_MASK 0x00000003L +#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001CL +#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000E0L +#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x00000100L +#define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L +#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L +#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00008000L +#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L +//DB_ALPHA_TO_MASK +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe +#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000C00L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000C000L +#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L +//VGT_DISPATCH_DRAW_INDEX +#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0 +#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_DB_FMT_CNTL +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000FFL +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L +//PA_SU_POLY_OFFSET_CLAMP +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xFFFFFFFFL +//VGT_GS_INSTANCE_CNT +#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0 +#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2 +#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L +#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001FCL +//VGT_STRMOUT_CONFIG +#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0 +#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1 +#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2 +#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3 +#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4 +#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT 0x7 +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8 +#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f +#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L +#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L +#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L +#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L +#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK 0x00000080L +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000F00L +#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L +//VGT_STRMOUT_BUFFER_CONFIG +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000FL +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000F0L +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000F00L +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000F000L +//VGT_DMA_EVENT_INITIATOR +#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 +#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa +#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b +#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL +#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L +#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L +//PA_SC_CENTROID_PRIORITY_0 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000FL +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000F0L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000F00L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000F000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000F0000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00F00000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0F000000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xF0000000L +//PA_SC_CENTROID_PRIORITY_1 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000FL +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000F0L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000F00L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000F000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000F0000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00F00000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0F000000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xF0000000L +//PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9 +#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc +#define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION__SHIFT 0xd +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L +#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L +#define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION_MASK 0x00002000L +//PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0 +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4 +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14 +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18 +#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT 0x1a +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001E000L +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L +#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK 0x0C000000L +//PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0 +#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1 +#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3 +#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L +#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L +#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L +//PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_MASK_X0Y0_X1Y0 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000FFFFL +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xFFFF0000L +//PA_SC_AA_MASK_X0Y1_X1Y1 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000FFFFL +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xFFFF0000L +//PA_SC_SHADER_CONTROL +#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0 +#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x2 +#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x3 +#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L +#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L +#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L +//PA_SC_BINNER_CNTL_0 +#define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x0 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x2 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x3 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x4 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x7 +#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa +#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0xd +#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x12 +#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x13 +#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x1b +#define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1c +#define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L +#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L +#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L +#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L +#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07F80000L +#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L +#define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION_MASK 0x10000000L +//PA_SC_BINNER_CNTL_1 +#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x0 +#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x10 +#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000FFFFL +#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xFFFF0000L +//PA_SC_CONSERVATIVE_RASTERIZATION_CNTL +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x0 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x1 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x5 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x6 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0xb +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0xc +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0xd +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0xe +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT 0xf +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x10 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x12 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x13 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x14 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x15 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x16 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x17 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x18 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001EL +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003C0L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK 0x00008000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L +//PA_SC_NGG_MODE_CNTL +#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0 +#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL +//VGT_VERTEX_REUSE_BLOCK_CNTL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0 +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000FFL +//VGT_OUT_DEALLOC_CNTL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0 +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007FL +//CB_COLOR0_BASE +#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR0_BASE_EXT +#define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR0_ATTRIB2 +#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR0_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR0_VIEW +#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR0_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR0_INFO +#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR0_ATTRIB +#define CB_COLOR0_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR0_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR0_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR0_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR0_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR0_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR0_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR0_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR0_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR0_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR0_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR0_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR0_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR0_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR0_DCC_CONTROL +#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L +#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +#define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +//CB_COLOR0_CMASK +#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR0_CMASK_BASE_EXT +#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR0_FMASK +#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR0_FMASK_BASE_EXT +#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR0_CLEAR_WORD0 +#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR0_CLEAR_WORD1 +#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR0_DCC_BASE +#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR0_DCC_BASE_EXT +#define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR1_BASE +#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR1_BASE_EXT +#define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR1_ATTRIB2 +#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR1_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR1_VIEW +#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR1_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR1_INFO +#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR1_ATTRIB +#define CB_COLOR1_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR1_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR1_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR1_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR1_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR1_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR1_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR1_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR1_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR1_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR1_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR1_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR1_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR1_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR1_DCC_CONTROL +#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L +#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +#define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +//CB_COLOR1_CMASK +#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR1_CMASK_BASE_EXT +#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR1_FMASK +#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR1_FMASK_BASE_EXT +#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR1_CLEAR_WORD0 +#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR1_CLEAR_WORD1 +#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR1_DCC_BASE +#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR1_DCC_BASE_EXT +#define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR2_BASE +#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR2_BASE_EXT +#define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR2_ATTRIB2 +#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR2_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR2_VIEW +#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR2_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR2_INFO +#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR2_ATTRIB +#define CB_COLOR2_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR2_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR2_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR2_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR2_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR2_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR2_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR2_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR2_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR2_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR2_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR2_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR2_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR2_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR2_DCC_CONTROL +#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L +#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +#define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +//CB_COLOR2_CMASK +#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR2_CMASK_BASE_EXT +#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR2_FMASK +#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR2_FMASK_BASE_EXT +#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR2_CLEAR_WORD0 +#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR2_CLEAR_WORD1 +#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR2_DCC_BASE +#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR2_DCC_BASE_EXT +#define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR3_BASE +#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR3_BASE_EXT +#define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR3_ATTRIB2 +#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR3_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR3_VIEW +#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR3_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR3_INFO +#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR3_ATTRIB +#define CB_COLOR3_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR3_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR3_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR3_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR3_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR3_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR3_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR3_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR3_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR3_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR3_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR3_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR3_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR3_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR3_DCC_CONTROL +#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L +#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +#define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +//CB_COLOR3_CMASK +#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR3_CMASK_BASE_EXT +#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR3_FMASK +#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR3_FMASK_BASE_EXT +#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR3_CLEAR_WORD0 +#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR3_CLEAR_WORD1 +#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR3_DCC_BASE +#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR3_DCC_BASE_EXT +#define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR4_BASE +#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR4_BASE_EXT +#define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR4_ATTRIB2 +#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR4_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR4_VIEW +#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR4_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR4_INFO +#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR4_ATTRIB +#define CB_COLOR4_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR4_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR4_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR4_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR4_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR4_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR4_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR4_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR4_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR4_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR4_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR4_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR4_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR4_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR4_DCC_CONTROL +#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L +#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +#define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +//CB_COLOR4_CMASK +#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR4_CMASK_BASE_EXT +#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR4_FMASK +#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR4_FMASK_BASE_EXT +#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR4_CLEAR_WORD0 +#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR4_CLEAR_WORD1 +#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR4_DCC_BASE +#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR4_DCC_BASE_EXT +#define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR5_BASE +#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR5_BASE_EXT +#define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR5_ATTRIB2 +#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR5_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR5_VIEW +#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR5_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR5_INFO +#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR5_ATTRIB +#define CB_COLOR5_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR5_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR5_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR5_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR5_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR5_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR5_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR5_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR5_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR5_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR5_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR5_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR5_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR5_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR5_DCC_CONTROL +#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L +#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +#define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +//CB_COLOR5_CMASK +#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR5_CMASK_BASE_EXT +#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR5_FMASK +#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR5_FMASK_BASE_EXT +#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR5_CLEAR_WORD0 +#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR5_CLEAR_WORD1 +#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR5_DCC_BASE +#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR5_DCC_BASE_EXT +#define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR6_BASE +#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR6_BASE_EXT +#define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR6_ATTRIB2 +#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR6_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR6_VIEW +#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR6_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR6_INFO +#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR6_ATTRIB +#define CB_COLOR6_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR6_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR6_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR6_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR6_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR6_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR6_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR6_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR6_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR6_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR6_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR6_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR6_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR6_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR6_DCC_CONTROL +#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L +#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +#define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +//CB_COLOR6_CMASK +#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR6_CMASK_BASE_EXT +#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR6_FMASK +#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR6_FMASK_BASE_EXT +#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR6_CLEAR_WORD0 +#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR6_CLEAR_WORD1 +#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR6_DCC_BASE +#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR6_DCC_BASE_EXT +#define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR7_BASE +#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR7_BASE_EXT +#define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR7_ATTRIB2 +#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0xe +#define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT 0x1c +#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL +#define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L +#define CB_COLOR7_ATTRIB2__MAX_MIP_MASK 0xF0000000L +//CB_COLOR7_VIEW +#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT 0x18 +#define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007FFL +#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00FFE000L +#define CB_COLOR7_VIEW__MIP_LEVEL_MASK 0x0F000000L +//CB_COLOR7_INFO +#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007CL +#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L +#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000L +#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L +//CB_COLOR7_ATTRIB +#define CB_COLOR7_ATTRIB__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR7_ATTRIB__META_LINEAR__SHIFT 0xb +#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR7_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 +#define CB_COLOR7_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 +#define CB_COLOR7_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c +#define CB_COLOR7_ATTRIB__RB_ALIGNED__SHIFT 0x1e +#define CB_COLOR7_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f +#define CB_COLOR7_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL +#define CB_COLOR7_ATTRIB__META_LINEAR_MASK 0x00000800L +#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR7_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L +#define CB_COLOR7_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L +#define CB_COLOR7_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L +#define CB_COLOR7_ATTRIB__RB_ALIGNED_MASK 0x40000000L +#define CB_COLOR7_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L +//CB_COLOR7_DCC_CONTROL +#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 +#define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 +#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L +#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L +#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL +#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L +#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L +#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L +#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L +#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L +#define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L +#define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L +//CB_COLOR7_CMASK +#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_CMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR7_CMASK_BASE_EXT +#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR7_FMASK +#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_FMASK__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR7_FMASK_BASE_EXT +#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR7_CLEAR_WORD0 +#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL +//CB_COLOR7_CLEAR_WORD1 +#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL +//CB_COLOR7_DCC_BASE +#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR7_DCC_BASE_EXT +#define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL + + +// addressBlock: xcd0_gc_gfxudec +//CP_EOP_DONE_ADDR_LO +#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_EOP_DONE_ADDR_HI +#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_EOP_DONE_DATA_LO +#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0 +#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL +//CP_EOP_DONE_DATA_HI +#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0 +#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL +//CP_EOP_LAST_FENCE_LO +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0 +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xFFFFFFFFL +//CP_EOP_LAST_FENCE_HI +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0 +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xFFFFFFFFL +//CP_STREAM_OUT_ADDR_LO +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2 +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xFFFFFFFCL +//CP_STREAM_OUT_ADDR_HI +#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0 +#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0x0000FFFFL +//CP_NUM_PRIM_WRITTEN_COUNT0_LO +#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_WRITTEN_COUNT0_HI +#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT0_LO +#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT0_HI +#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_WRITTEN_COUNT1_LO +#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_WRITTEN_COUNT1_HI +#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT1_LO +#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT1_HI +#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_WRITTEN_COUNT2_LO +#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_WRITTEN_COUNT2_HI +#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT2_LO +#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT2_HI +#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_WRITTEN_COUNT3_LO +#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_WRITTEN_COUNT3_HI +#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT3_LO +#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xFFFFFFFFL +//CP_NUM_PRIM_NEEDED_COUNT3_HI +#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xFFFFFFFFL +//CP_PIPE_STATS_ADDR_LO +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2 +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xFFFFFFFCL +//CP_PIPE_STATS_ADDR_HI +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0 +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000FFFFL +//CP_VGT_IAVERT_COUNT_LO +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0 +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_IAVERT_COUNT_HI +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0 +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_IAPRIM_COUNT_LO +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0 +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_IAPRIM_COUNT_HI +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0 +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_GSPRIM_COUNT_LO +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0 +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_GSPRIM_COUNT_HI +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0 +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_VSINVOC_COUNT_LO +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_VSINVOC_COUNT_HI +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_GSINVOC_COUNT_LO +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_GSINVOC_COUNT_HI +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_HSINVOC_COUNT_LO +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_HSINVOC_COUNT_HI +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_DSINVOC_COUNT_LO +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_DSINVOC_COUNT_HI +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_PA_CINVOC_COUNT_LO +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0 +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_PA_CINVOC_COUNT_HI +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0 +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_PA_CPRIM_COUNT_LO +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0 +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xFFFFFFFFL +//CP_PA_CPRIM_COUNT_HI +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0 +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT0_LO +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT0_HI +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT1_LO +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT1_HI +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xFFFFFFFFL +//CP_VGT_CSINVOC_COUNT_LO +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_CSINVOC_COUNT_HI +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_PIPE_STATS_CONTROL +#define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x19 +#define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x02000000L +//CP_STREAM_OUT_CONTROL +#define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT 0x19 +#define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK 0x02000000L +//CP_STRMOUT_CNTL +#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0 +#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L +//SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 +#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL +//SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 +#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL +//SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 +#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL +//SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 +#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL +//SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 +#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL +//SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 +#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL +//SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 +#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL +//SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 +#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL +//CP_APPEND_DATA_HI +#define CP_APPEND_DATA_HI__DATA__SHIFT 0x0 +#define CP_APPEND_DATA_HI__DATA_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_CS_FENCE_HI +#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_PS_FENCE_HI +#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL +//SCRATCH_UMSK +#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0 +#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10 +#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000FFL +#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L +//SCRATCH_ADDR +#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0 +#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xFFFFFFFFL +//CP_PFP_ATOMIC_PREOP_LO +#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL +//CP_PFP_ATOMIC_PREOP_HI +#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL +//CP_PFP_GDS_ATOMIC0_PREOP_LO +#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL +//CP_PFP_GDS_ATOMIC0_PREOP_HI +#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL +//CP_PFP_GDS_ATOMIC1_PREOP_LO +#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL +//CP_PFP_GDS_ATOMIC1_PREOP_HI +#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL +//CP_APPEND_ADDR_LO +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2 +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xFFFFFFFCL +//CP_APPEND_ADDR_HI +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0 +#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10 +#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19 +#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000FFFFL +#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00010000L +#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x02000000L +#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xE0000000L +//CP_APPEND_DATA_LO +#define CP_APPEND_DATA_LO__DATA__SHIFT 0x0 +#define CP_APPEND_DATA_LO__DATA_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_CS_FENCE_LO +#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_PS_FENCE_LO +#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_ATOMIC_PREOP_LO +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL +//CP_ME_ATOMIC_PREOP_LO +#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL +//CP_ATOMIC_PREOP_HI +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL +//CP_ME_ATOMIC_PREOP_HI +#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL +//CP_GDS_ATOMIC0_PREOP_LO +#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL +//CP_ME_GDS_ATOMIC0_PREOP_LO +#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL +//CP_GDS_ATOMIC0_PREOP_HI +#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL +//CP_ME_GDS_ATOMIC0_PREOP_HI +#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL +//CP_GDS_ATOMIC1_PREOP_LO +#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL +//CP_ME_GDS_ATOMIC1_PREOP_LO +#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL +//CP_GDS_ATOMIC1_PREOP_HI +#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL +//CP_ME_GDS_ATOMIC1_PREOP_HI +#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL +//CP_ME_MC_WADDR_LO +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2 +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xFFFFFFFCL +//CP_ME_MC_WADDR_HI +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0 +#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16 +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000FFFFL +#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00400000L +//CP_ME_MC_WDATA_LO +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0 +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xFFFFFFFFL +//CP_ME_MC_WDATA_HI +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0 +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xFFFFFFFFL +//CP_ME_MC_RADDR_LO +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2 +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xFFFFFFFCL +//CP_ME_MC_RADDR_HI +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0 +#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16 +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000FFFFL +#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00400000L +//CP_SEM_WAIT_TIMER +#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0 +#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xFFFFFFFFL +//CP_SIG_SEM_ADDR_LO +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L +//CP_SIG_SEM_ADDR_HI +#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 +#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 +#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 +#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 +#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d +#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL +#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L +#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L +#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L +#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L +//CP_WAIT_REG_MEM_TIMEOUT +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0 +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xFFFFFFFFL +//CP_WAIT_SEM_ADDR_LO +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L +//CP_WAIT_SEM_ADDR_HI +#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 +#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 +#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 +#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 +#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d +#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL +#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L +#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L +#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L +#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L +//CP_DMA_PFP_CONTROL +#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa +#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd +#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14 +#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 +#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d +#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L +#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L +#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L +#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L +#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L +//CP_DMA_ME_CONTROL +#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa +#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd +#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14 +#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 +#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d +#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L +#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L +#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L +#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L +#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L +//CP_COHER_BASE_HI +#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 +#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL +//CP_COHER_START_DELAY +#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0 +#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003FL +//CP_COHER_CNTL +#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3 +#define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT 0x4 +#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT 0x5 +#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf +#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12 +#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16 +#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17 +#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19 +#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a +#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b +#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c +#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d +#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e +#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x00000008L +#define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK 0x00000010L +#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK 0x00000020L +#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L +#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L +#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L +#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L +#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L +#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L +#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L +#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L +#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L +#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000L +//CP_COHER_SIZE +#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 +#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL +//CP_COHER_BASE +#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 +#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL +//CP_COHER_STATUS +#define CP_COHER_STATUS__MEID__SHIFT 0x18 +#define CP_COHER_STATUS__STATUS__SHIFT 0x1f +#define CP_COHER_STATUS__MEID_MASK 0x03000000L +#define CP_COHER_STATUS__STATUS_MASK 0x80000000L +//CP_DMA_ME_SRC_ADDR +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0 +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_ME_SRC_ADDR_HI +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL +//CP_DMA_ME_DST_ADDR +#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0 +#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_ME_DST_ADDR_HI +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL +//CP_DMA_ME_COMMAND +#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0 +#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a +#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b +#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c +#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d +#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e +#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x1f +#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL +#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L +#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L +#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L +#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L +#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L +#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L +//CP_DMA_PFP_SRC_ADDR +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0 +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_PFP_SRC_ADDR_HI +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL +//CP_DMA_PFP_DST_ADDR +#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0 +#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_PFP_DST_ADDR_HI +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL +//CP_DMA_PFP_COMMAND +#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0 +#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a +#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b +#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c +#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d +#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e +#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x1f +#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL +#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L +#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L +#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L +#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L +#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L +#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L +//CP_DMA_CNTL +#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x0 +#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4 +#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10 +#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c +#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d +#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e +#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L +#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L +#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000F0000L +#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L +#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L +#define CP_DMA_CNTL__PIO_COUNT_MASK 0xC0000000L +//CP_DMA_READ_TAGS +#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0 +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c +#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03FFFFFFL +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L +//CP_COHER_SIZE_HI +#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 +#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL +//CP_PFP_IB_CONTROL +#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0 +#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000FFL +//CP_PFP_LOAD_CONTROL +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0 +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1 +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18 +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L +//CP_SCRATCH_INDEX +#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000FFL +//CP_SCRATCH_DATA +#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL +//CP_RB_OFFSET +#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0 +#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL +//CP_IB1_OFFSET +#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 +#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL +//CP_IB2_OFFSET +#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 +#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL +//CP_IB1_PREAMBLE_BEGIN +#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0 +#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000FFFFFL +//CP_IB1_PREAMBLE_END +#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0 +#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000FFFFFL +//CP_IB2_PREAMBLE_BEGIN +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0 +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000FFFFFL +//CP_IB2_PREAMBLE_END +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0 +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000FFFFFL +//CP_CE_IB1_OFFSET +#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 +#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL +//CP_CE_IB2_OFFSET +#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 +#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL +//CP_CE_COUNTER +#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0 +#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL +//CP_CE_RB_OFFSET +#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0 +#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL +//CP_CE_INIT_CMD_BUFSZ +#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT 0x0 +#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK 0x00000FFFL +//CP_CE_IB1_CMD_BUFSZ +#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 +#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL +//CP_CE_IB2_CMD_BUFSZ +#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 +#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL +//CP_IB1_CMD_BUFSZ +#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 +#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL +//CP_IB2_CMD_BUFSZ +#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 +#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL +//CP_ST_CMD_BUFSZ +#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x0 +#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000FFFFFL +//CP_CE_INIT_BASE_LO +#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5 +#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xFFFFFFE0L +//CP_CE_INIT_BASE_HI +#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0 +#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x0000FFFFL +//CP_CE_INIT_BUFSZ +#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0 +#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000FFFL +//CP_CE_IB1_BASE_LO +#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 +#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL +//CP_CE_IB1_BASE_HI +#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 +#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL +//CP_CE_IB1_BUFSZ +#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 +#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL +//CP_CE_IB2_BASE_LO +#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 +#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL +//CP_CE_IB2_BASE_HI +#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 +#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL +//CP_CE_IB2_BUFSZ +#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 +#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL +//CP_IB1_BASE_LO +#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 +#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL +//CP_IB1_BASE_HI +#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 +#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL +//CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 +#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL +//CP_IB2_BASE_LO +#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 +#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL +//CP_IB2_BASE_HI +#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 +#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL +//CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 +#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL +//CP_ST_BASE_LO +#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2 +#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xFFFFFFFCL +//CP_ST_BASE_HI +#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0 +#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000FFFFL +//CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0 +#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000FFFFFL +//CP_EOP_DONE_EVENT_CNTL +#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0 +#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc +#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x19 +#define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x1c +#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x0000007FL +#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x0003F000L +#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x02000000L +#define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L +//CP_EOP_DONE_DATA_CNTL +#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10 +#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18 +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d +#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L +#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xE0000000L +//CP_EOP_DONE_CNTX_ID +#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0 +#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL +//CP_PFP_COMPLETION_STATUS +#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0 +#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L +//CP_CE_COMPLETION_STATUS +#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0 +#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x00000003L +//CP_PRED_NOT_VISIBLE +#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0 +#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L +//CP_PFP_METADATA_BASE_ADDR +#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_PFP_METADATA_BASE_ADDR_HI +#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_CE_METADATA_BASE_ADDR +#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_CE_METADATA_BASE_ADDR_HI +#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_DRAW_INDX_INDR_ADDR +#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_DRAW_INDX_INDR_ADDR_HI +#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_DISPATCH_INDR_ADDR +#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_DISPATCH_INDR_ADDR_HI +#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_INDEX_BASE_ADDR +#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_INDEX_BASE_ADDR_HI +#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_INDEX_TYPE +#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +//CP_GDS_BKUP_ADDR +#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_GDS_BKUP_ADDR_HI +#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_SAMPLE_STATUS +#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0 +#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1 +#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2 +#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3 +#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4 +#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5 +#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6 +#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7 +#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L +#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L +#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L +#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L +#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L +#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L +#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L +#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L +//CP_ME_COHER_CNTL +#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0 +#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1 +#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6 +#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7 +#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8 +#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9 +#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa +#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb +#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc +#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd +#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe +#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13 +#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15 +#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L +#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L +#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L +#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L +#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L +#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L +#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L +#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L +#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L +#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L +#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L +#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L +#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L +//CP_ME_COHER_SIZE +#define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 +#define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL +//CP_ME_COHER_SIZE_HI +#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 +#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL +//CP_ME_COHER_BASE +#define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 +#define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL +//CP_ME_COHER_BASE_HI +#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 +#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL +//CP_ME_COHER_STATUS +#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0 +#define CP_ME_COHER_STATUS__STATUS__SHIFT 0x1f +#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000FFL +#define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L +//RLC_GPM_PERF_COUNT_0 +#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0 +#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4 +#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8 +#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc +#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10 +#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12 +#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14 +#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15 +#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000FL +#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000F0L +#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0x00000F00L +#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0x0000F000L +#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L +#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000C0000L +#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L +#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xFFE00000L +//RLC_GPM_PERF_COUNT_1 +#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0 +#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4 +#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8 +#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc +#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10 +#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12 +#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14 +#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15 +#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000FL +#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000F0L +#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0x00000F00L +#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0x0000F000L +#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L +#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000C0000L +#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L +#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xFFE00000L +//GRBM_GFX_INDEX +#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 +#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8 +#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 +#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f +#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000FFL +#define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000FF00L +#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00FF0000L +#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L +//VGT_GSVS_RING_SIZE +#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0 +#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL +//VGT_PRIMITIVE_TYPE +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL +//VGT_INDEX_TYPE +#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define VGT_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8 +#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +#define VGT_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L +//VGT_STRMOUT_BUFFER_FILLED_SIZE_0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_BUFFER_FILLED_SIZE_1 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_BUFFER_FILLED_SIZE_2 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_BUFFER_FILLED_SIZE_3 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xFFFFFFFFL +//VGT_MAX_VTX_INDX +#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 +#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL +//VGT_MIN_VTX_INDX +#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 +#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL +//VGT_INDX_OFFSET +#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 +#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL +//VGT_MULTI_PRIM_IB_RESET_EN +#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 +#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1 +#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L +#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L +//VGT_NUM_INDICES +#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0 +#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xFFFFFFFFL +//VGT_NUM_INSTANCES +#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 +#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL +//VGT_TF_RING_SIZE +#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 +#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL +//VGT_HS_OFFCHIP_PARAM +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000001FFL +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L +//VGT_TF_MEMORY_BASE +#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0 +#define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL +//VGT_TF_MEMORY_BASE_HI +#define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0 +#define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL +//WD_POS_BUF_BASE +#define WD_POS_BUF_BASE__BASE__SHIFT 0x0 +#define WD_POS_BUF_BASE__BASE_MASK 0xFFFFFFFFL +//WD_POS_BUF_BASE_HI +#define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT 0x0 +#define WD_POS_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL +//WD_CNTL_SB_BUF_BASE +#define WD_CNTL_SB_BUF_BASE__BASE__SHIFT 0x0 +#define WD_CNTL_SB_BUF_BASE__BASE_MASK 0xFFFFFFFFL +//WD_CNTL_SB_BUF_BASE_HI +#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT 0x0 +#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL +//WD_INDEX_BUF_BASE +#define WD_INDEX_BUF_BASE__BASE__SHIFT 0x0 +#define WD_INDEX_BUF_BASE__BASE_MASK 0xFFFFFFFFL +//WD_INDEX_BUF_BASE_HI +#define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT 0x0 +#define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL +//IA_MULTI_VGT_PARAM +#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0 +#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11 +#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13 +#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14 +#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC__SHIFT 0x15 +#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV__SHIFT 0x16 +#define IA_MULTI_VGT_PARAM__HW_USE_ONLY__SHIFT 0x17 +#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000FFFFL +#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L +#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L +#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L +#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK 0x00200000L +#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK 0x00400000L +#define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK 0x00800000L +//VGT_INSTANCE_BASE_ID +#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0 +#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL +//PA_SU_LINE_STIPPLE_VALUE +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00FFFFFFL +//PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000FL +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000FF00L +//PA_SC_SCREEN_EXTENT_MIN_0 +#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_EXTENT_MAX_0 +#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_EXTENT_MIN_1 +#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_EXTENT_MAX_1 +#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xFFFF0000L +//PA_SC_P3D_TRAP_SCREEN_HV_EN +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L +//PA_SC_P3D_TRAP_SCREEN_H +#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL +//PA_SC_P3D_TRAP_SCREEN_V +#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL +//PA_SC_P3D_TRAP_SCREEN_OCCURRENCE +#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL +//PA_SC_P3D_TRAP_SCREEN_COUNT +#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL +//PA_SC_HP3D_TRAP_SCREEN_HV_EN +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L +//PA_SC_HP3D_TRAP_SCREEN_H +#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL +//PA_SC_HP3D_TRAP_SCREEN_V +#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL +//PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE +#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL +//PA_SC_HP3D_TRAP_SCREEN_COUNT +#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL +//PA_SC_TRAP_SCREEN_HV_EN +#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L +#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L +//PA_SC_TRAP_SCREEN_H +#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL +//PA_SC_TRAP_SCREEN_V +#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL +//PA_SC_TRAP_SCREEN_OCCURRENCE +#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL +//PA_SC_TRAP_SCREEN_COUNT +#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL +//PA_STATE_STEREO_X +#define PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT 0x0 +#define PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_BASE +#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0 +#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_SIZE +#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0 +#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x003FFFFFL +//SQ_THREAD_TRACE_MASK +#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0 +#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5 +#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7 +#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8 +#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc +#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe +#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf +#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x0000001FL +#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x00000020L +#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x00000080L +#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0x00000F00L +#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x00003000L +#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x00004000L +#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x00008000L +//SQ_THREAD_TRACE_TOKEN_MASK +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18 +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0x0000FFFFL +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0x00FF0000L +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x01000000L +//SQ_THREAD_TRACE_PERF_MASK +#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0 +#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10 +#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0x0000FFFFL +#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xFFFF0000L +//SQ_THREAD_TRACE_CTRL +#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f +#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000L +//SQ_THREAD_TRACE_MODE +#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0 +#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3 +#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6 +#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9 +#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc +#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf +#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12 +#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15 +#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17 +#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19 +#define SQ_THREAD_TRACE_MODE__TC_PERF_EN__SHIFT 0x1a +#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b +#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d +#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e +#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f +#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x00000007L +#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x00000038L +#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x000001C0L +#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0x00000E00L +#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x00007000L +#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x00038000L +#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x001C0000L +#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x00600000L +#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x01800000L +#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x02000000L +#define SQ_THREAD_TRACE_MODE__TC_PERF_EN_MASK 0x04000000L +#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000L +#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000L +#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000L +#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000L +//SQ_THREAD_TRACE_BASE2 +#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0x0000000FL +//SQ_THREAD_TRACE_TOKEN_MASK2 +#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0 +#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_WPTR +#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e +#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3FFFFFFFL +#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xC0000000L +//SQ_THREAD_TRACE_STATUS +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0 +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10 +#define SQ_THREAD_TRACE_STATUS__UTC_ERROR__SHIFT 0x1c +#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d +#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e +#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x000003FFL +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x03FF0000L +#define SQ_THREAD_TRACE_STATUS__UTC_ERROR_MASK 0x10000000L +#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000L +#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000L +#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000L +//SQ_THREAD_TRACE_HIWATER +#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0 +#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x00000007L +//SQ_THREAD_TRACE_CNTR +#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_0 +#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_1 +#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_2 +#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_3 +#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xFFFFFFFFL +//SQC_CACHES +#define SQC_CACHES__TARGET_INST__SHIFT 0x0 +#define SQC_CACHES__TARGET_DATA__SHIFT 0x1 +#define SQC_CACHES__INVALIDATE__SHIFT 0x2 +#define SQC_CACHES__WRITEBACK__SHIFT 0x3 +#define SQC_CACHES__VOL__SHIFT 0x4 +#define SQC_CACHES__COMPLETE__SHIFT 0x10 +#define SQC_CACHES__TARGET_INST_MASK 0x00000001L +#define SQC_CACHES__TARGET_DATA_MASK 0x00000002L +#define SQC_CACHES__INVALIDATE_MASK 0x00000004L +#define SQC_CACHES__WRITEBACK_MASK 0x00000008L +#define SQC_CACHES__VOL_MASK 0x00000010L +#define SQC_CACHES__COMPLETE_MASK 0x00010000L +//SQC_WRITEBACK +#define SQC_WRITEBACK__DWB__SHIFT 0x0 +#define SQC_WRITEBACK__DIRTY__SHIFT 0x1 +#define SQC_WRITEBACK__DWB_MASK 0x00000001L +#define SQC_WRITEBACK__DIRTY_MASK 0x00000002L +//DB_OCCLUSION_COUNT0_LOW +#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT0_HI +#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7FFFFFFFL +//DB_OCCLUSION_COUNT1_LOW +#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT1_HI +#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7FFFFFFFL +//DB_OCCLUSION_COUNT2_LOW +#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT2_HI +#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7FFFFFFFL +//DB_OCCLUSION_COUNT3_LOW +#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT3_HI +#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7FFFFFFFL +//DB_ZPASS_COUNT_LOW +#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_ZPASS_COUNT_HI +#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0 +#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7FFFFFFFL +//GDS_RD_ADDR +#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0 +#define GDS_RD_ADDR__READ_ADDR_MASK 0xFFFFFFFFL +//GDS_RD_DATA +#define GDS_RD_DATA__READ_DATA__SHIFT 0x0 +#define GDS_RD_DATA__READ_DATA_MASK 0xFFFFFFFFL +//GDS_RD_BURST_ADDR +#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0 +#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xFFFFFFFFL +//GDS_RD_BURST_COUNT +#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0 +#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xFFFFFFFFL +//GDS_RD_BURST_DATA +#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0 +#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xFFFFFFFFL +//GDS_WR_ADDR +#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0 +#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL +//GDS_WR_DATA +#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0 +#define GDS_WR_DATA__WRITE_DATA_MASK 0xFFFFFFFFL +//GDS_WR_BURST_ADDR +#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0 +#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL +//GDS_WR_BURST_DATA +#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0 +#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xFFFFFFFFL +//GDS_WRITE_COMPLETE +#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0 +#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xFFFFFFFFL +//GDS_ATOM_CNTL +#define GDS_ATOM_CNTL__AINC__SHIFT 0x0 +#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6 +#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8 +#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa +#define GDS_ATOM_CNTL__AINC_MASK 0x0000003FL +#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000C0L +#define GDS_ATOM_CNTL__DMODE_MASK 0x00000300L +#define GDS_ATOM_CNTL__UNUSED2_MASK 0xFFFFFC00L +//GDS_ATOM_COMPLETE +#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0 +#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1 +#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L +#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xFFFFFFFEL +//GDS_ATOM_BASE +#define GDS_ATOM_BASE__BASE__SHIFT 0x0 +#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10 +#define GDS_ATOM_BASE__BASE_MASK 0x0000FFFFL +#define GDS_ATOM_BASE__UNUSED_MASK 0xFFFF0000L +//GDS_ATOM_SIZE +#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0 +#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10 +#define GDS_ATOM_SIZE__SIZE_MASK 0x0000FFFFL +#define GDS_ATOM_SIZE__UNUSED_MASK 0xFFFF0000L +//GDS_ATOM_OFFSET0 +#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0 +#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8 +#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000FFL +#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xFFFFFF00L +//GDS_ATOM_OFFSET1 +#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0 +#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8 +#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000FFL +#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xFFFFFF00L +//GDS_ATOM_DST +#define GDS_ATOM_DST__DST__SHIFT 0x0 +#define GDS_ATOM_DST__DST_MASK 0xFFFFFFFFL +//GDS_ATOM_OP +#define GDS_ATOM_OP__OP__SHIFT 0x0 +#define GDS_ATOM_OP__UNUSED__SHIFT 0x8 +#define GDS_ATOM_OP__OP_MASK 0x000000FFL +#define GDS_ATOM_OP__UNUSED_MASK 0xFFFFFF00L +//GDS_ATOM_SRC0 +#define GDS_ATOM_SRC0__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC0__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_SRC0_U +#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC0_U__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_SRC1 +#define GDS_ATOM_SRC1__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC1__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_SRC1_U +#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC1_U__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_READ0 +#define GDS_ATOM_READ0__DATA__SHIFT 0x0 +#define GDS_ATOM_READ0__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_READ0_U +#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0 +#define GDS_ATOM_READ0_U__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_READ1 +#define GDS_ATOM_READ1__DATA__SHIFT 0x0 +#define GDS_ATOM_READ1__DATA_MASK 0xFFFFFFFFL +//GDS_ATOM_READ1_U +#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0 +#define GDS_ATOM_READ1_U__DATA_MASK 0xFFFFFFFFL +//GDS_GWS_RESOURCE_CNTL +#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0 +#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6 +#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003FL +#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xFFFFFFC0L +//GDS_GWS_RESOURCE +#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0 +#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1 +#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xe +#define GDS_GWS_RESOURCE__DED__SHIFT 0xf +#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0x10 +#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x11 +#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1d +#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1e +#define GDS_GWS_RESOURCE__HALTED__SHIFT 0x1f +#define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L +#define GDS_GWS_RESOURCE__COUNTER_MASK 0x00003FFEL +#define GDS_GWS_RESOURCE__TYPE_MASK 0x00004000L +#define GDS_GWS_RESOURCE__DED_MASK 0x00008000L +#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00010000L +#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x1FFE0000L +#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x20000000L +#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x40000000L +#define GDS_GWS_RESOURCE__HALTED_MASK 0x80000000L +//GDS_GWS_RESOURCE_CNT +#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0 +#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10 +#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000FFFFL +#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xFFFF0000L +//GDS_OA_CNTL +#define GDS_OA_CNTL__INDEX__SHIFT 0x0 +#define GDS_OA_CNTL__UNUSED__SHIFT 0x4 +#define GDS_OA_CNTL__INDEX_MASK 0x0000000FL +#define GDS_OA_CNTL__UNUSED_MASK 0xFFFFFFF0L +//GDS_OA_COUNTER +#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0 +#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xFFFFFFFFL +//GDS_OA_ADDRESS +#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0 +#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10 +#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14 +#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16 +#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e +#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f +#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0x0000FFFFL +#define GDS_OA_ADDRESS__CRAWLER_MASK 0x000F0000L +#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x00300000L +#define GDS_OA_ADDRESS__UNUSED_MASK 0x3FC00000L +#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000L +#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000L +//GDS_OA_INCDEC +#define GDS_OA_INCDEC__VALUE__SHIFT 0x0 +#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f +#define GDS_OA_INCDEC__VALUE_MASK 0x7FFFFFFFL +#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000L +//GDS_OA_RING_SIZE +#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0 +#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xFFFFFFFFL +//SPI_CONFIG_CNTL +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0 +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15 +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18 +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19 +#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a +#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b +#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c +#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d +#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L +#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L +#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L +#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L +#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L +#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L +//SPI_CONFIG_CNTL_1 +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0 +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4 +#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE__SHIFT 0x5 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7 +#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa +#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe +#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf +#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10 +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L +#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE_MASK 0x00000020L +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L +#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L +#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L +#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L +#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xFFFF0000L +//SPI_CONFIG_CNTL_2 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L +//SPI_WAVE_LIMIT_CNTL +#define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN__SHIFT 0x0 +#define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN__SHIFT 0x2 +#define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN__SHIFT 0x4 +#define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN__SHIFT 0x6 +#define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN_MASK 0x00000003L +#define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN_MASK 0x0000000CL +#define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN_MASK 0x00000030L +#define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN_MASK 0x000000C0L + +// addressBlock: xcd0_gc_gccanedec +//GC_CANE_ERR_STATUS +#define GC_CANE_ERR_STATUS__SDPM_RDRSP_STATUS__SHIFT 0x0 +#define GC_CANE_ERR_STATUS__SDPM_WRRSP_STATUS__SHIFT 0x4 +#define GC_CANE_ERR_STATUS__SDPM_RDRSP_DATASTATUS__SHIFT 0x8 +#define GC_CANE_ERR_STATUS__SDPM_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define GC_CANE_ERR_STATUS__SDPS_DAT_ERROR__SHIFT 0xb +#define GC_CANE_ERR_STATUS__SDPS_DAT_PARITY_ERROR__SHIFT 0xc +#define GC_CANE_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xd +#define GC_CANE_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xe +#define GC_CANE_ERR_STATUS__BUSY_ON_UER_ERROR__SHIFT 0xf +#define GC_CANE_ERR_STATUS__FUE_FLAG__SHIFT 0x10 +#define GC_CANE_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0x11 +#define GC_CANE_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x12 +#define GC_CANE_ERR_STATUS__SDPM_RDRSP_STATUS_MASK 0x0000000FL +#define GC_CANE_ERR_STATUS__SDPM_WRRSP_STATUS_MASK 0x000000F0L +#define GC_CANE_ERR_STATUS__SDPM_RDRSP_DATASTATUS_MASK 0x00000300L +#define GC_CANE_ERR_STATUS__SDPM_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define GC_CANE_ERR_STATUS__SDPS_DAT_ERROR_MASK 0x00000800L +#define GC_CANE_ERR_STATUS__SDPS_DAT_PARITY_ERROR_MASK 0x00001000L +#define GC_CANE_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00002000L +#define GC_CANE_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00004000L +#define GC_CANE_ERR_STATUS__BUSY_ON_UER_ERROR_MASK 0x00008000L +#define GC_CANE_ERR_STATUS__FUE_FLAG_MASK 0x00010000L +#define GC_CANE_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00020000L +#define GC_CANE_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00040000L +//GC_CANE_UE_ERR_STATUS_LO +#define GC_CANE_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define GC_CANE_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define GC_CANE_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define GC_CANE_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define GC_CANE_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define GC_CANE_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define GC_CANE_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define GC_CANE_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//GC_CANE_UE_ERR_STATUS_HI +#define GC_CANE_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define GC_CANE_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define GC_CANE_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define GC_CANE_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define GC_CANE_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define GC_CANE_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define GC_CANE_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define GC_CANE_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define GC_CANE_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define GC_CANE_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define GC_CANE_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define GC_CANE_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +//GC_CANE_CE_ERR_STATUS_LO +#define GC_CANE_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define GC_CANE_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define GC_CANE_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define GC_CANE_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define GC_CANE_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define GC_CANE_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define GC_CANE_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define GC_CANE_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//GC_CANE_CE_ERR_STATUS_HI +#define GC_CANE_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define GC_CANE_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define GC_CANE_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define GC_CANE_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define GC_CANE_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define GC_CANE_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define GC_CANE_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define GC_CANE_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define GC_CANE_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define GC_CANE_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L + +// addressBlock: xcd0_gc_perfddec +//CPG_PERFCOUNTER1_LO +#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPG_PERFCOUNTER1_HI +#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPG_PERFCOUNTER0_LO +#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPG_PERFCOUNTER0_HI +#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER1_LO +#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER1_HI +#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER0_LO +#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER0_HI +#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER1_LO +#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER1_HI +#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER0_LO +#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER0_HI +#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPF_LATENCY_STATS_DATA +#define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x0 +#define CPF_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL +//CPG_LATENCY_STATS_DATA +#define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x0 +#define CPG_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL +//CPC_LATENCY_STATS_DATA +#define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x0 +#define CPC_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER0_LO +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER0_HI +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER1_LO +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER1_HI +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_SE0_PERFCOUNTER_LO +#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_SE0_PERFCOUNTER_HI +#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_SE1_PERFCOUNTER_LO +#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_SE1_PERFCOUNTER_HI +#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_SE2_PERFCOUNTER_LO +#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_SE2_PERFCOUNTER_HI +#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_SE3_PERFCOUNTER_LO +#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_SE3_PERFCOUNTER_HI +#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER0_LO +#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER0_HI +#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER1_LO +#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER1_HI +#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER2_LO +#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER2_HI +#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER3_LO +#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//WD_PERFCOUNTER3_HI +#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER0_LO +#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER0_HI +#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER1_LO +#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER1_HI +#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER2_LO +#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER2_HI +#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER3_LO +#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//IA_PERFCOUNTER3_HI +#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER0_LO +#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER0_HI +#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER1_LO +#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER1_HI +#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER2_LO +#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER2_HI +#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER3_LO +#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//VGT_PERFCOUNTER3_HI +#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER0_LO +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL +//PA_SU_PERFCOUNTER1_LO +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL +//PA_SU_PERFCOUNTER2_LO +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL +//PA_SU_PERFCOUNTER3_LO +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL +//PA_SC_PERFCOUNTER0_LO +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER1_LO +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER1_HI +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER2_LO +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER2_HI +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER3_LO +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER3_HI +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER4_LO +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER4_HI +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER5_LO +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER5_HI +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER6_LO +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER6_HI +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER7_LO +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER7_HI +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER0_HI +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER0_LO +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER1_HI +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER1_LO +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER2_HI +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER2_LO +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER3_HI +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER3_LO +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER4_HI +#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER4_LO +#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER5_HI +#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER5_LO +#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER0_LO +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER0_HI +#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER1_LO +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER1_HI +#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER2_LO +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER2_HI +#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER3_LO +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER3_HI +#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER4_LO +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER4_HI +#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER5_LO +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER5_HI +#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER6_LO +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER6_HI +#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER7_LO +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER7_HI +#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER8_LO +#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER8_HI +#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER9_LO +#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER9_HI +#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER10_LO +#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER10_HI +#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER11_LO +#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER11_HI +#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER12_LO +#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER12_HI +#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER13_LO +#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER13_HI +#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER14_LO +#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER14_HI +#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER15_LO +#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER15_HI +#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER0_LO +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER1_LO +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER1_HI +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER2_LO +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER2_HI +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER3_LO +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER3_HI +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER0_LO +#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER0_HI +#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER1_LO +#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER1_HI +#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER2_LO +#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER2_HI +#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER3_LO +#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GDS_PERFCOUNTER3_HI +#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER0_LO +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER0_HI +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER1_LO +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER1_HI +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER0_LO +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER0_HI +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER1_LO +#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER1_HI +#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER0_LO +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER0_HI +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER1_LO +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER1_HI +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER2_LO +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER2_HI +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER3_LO +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER3_HI +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER0_LO +#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER0_HI +#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER1_LO +#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER1_HI +#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER2_LO +#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER2_HI +#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER3_LO +#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCC_PERFCOUNTER3_HI +#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER0_LO +#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER0_HI +#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER1_LO +#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER1_HI +#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER2_LO +#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER2_HI +#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER3_LO +#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCA_PERFCOUNTER3_HI +#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER0_LO +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER0_HI +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER1_LO +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER1_HI +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER2_LO +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER2_HI +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER3_LO +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER3_HI +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER0_LO +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER0_HI +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER1_LO +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER1_HI +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER2_LO +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER2_HI +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER3_LO +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER3_HI +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER0_LO +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER0_HI +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER1_LO +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER1_HI +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER0_LO +#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER0_HI +#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER1_LO +#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER1_HI +#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER2_LO +#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER2_HI +#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER3_LO +#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER3_HI +#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL + + +// addressBlock: xcd0_gc_utcl2_atcl2pfcntrdec +//ATC_L2_PERFCOUNTER_LO +#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//ATC_L2_PERFCOUNTER_HI +#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: xcd0_gc_utcl2_vml2prdec +//MC_VM_L2_PERFCOUNTER_LO +#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MC_VM_L2_PERFCOUNTER_HI +#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: xcd0_gc_utcl2_l2tlbprdec +//L2TLB_PERFCOUNTER_LO +#define L2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define L2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//L2TLB_PERFCOUNTER_HI +#define L2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define L2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define L2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define L2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: xcd0_gc_perfsdec +//CPG_PERFCOUNTER1_SELECT +#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 +#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa +#define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL +#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L +#define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CPG_PERFCOUNTER0_SELECT1 +#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 +#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL +#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//CPG_PERFCOUNTER0_SELECT +#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 +#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa +#define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL +#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L +#define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CPC_PERFCOUNTER1_SELECT +#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 +#define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL +#define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CPC_PERFCOUNTER0_SELECT1 +#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 +#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL +#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//CPF_PERFCOUNTER1_SELECT +#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 +#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa +#define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL +#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L +#define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CPF_PERFCOUNTER0_SELECT1 +#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 +#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL +#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//CPF_PERFCOUNTER0_SELECT +#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 +#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa +#define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL +#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L +#define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L +//CPC_PERFCOUNTER0_SELECT +#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 +#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa +#define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL +#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L +#define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CPF_TC_PERF_COUNTER_WINDOW_SELECT +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L +//CPG_TC_PERF_COUNTER_WINDOW_SELECT +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L +//CPF_LATENCY_STATS_SELECT +#define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 +#define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e +#define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f +#define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL +#define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L +#define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L +//CPG_LATENCY_STATS_SELECT +#define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 +#define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e +#define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f +#define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL +#define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L +#define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L +//CPC_LATENCY_STATS_SELECT +#define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 +#define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e +#define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f +#define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x00000007L +#define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L +#define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L +//CP_DRAW_OBJECT +#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0 +#define CP_DRAW_OBJECT__OBJECT_MASK 0xFFFFFFFFL +//CP_DRAW_OBJECT_COUNTER +#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0 +#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000FFFFL +//CP_DRAW_WINDOW_MASK_HI +#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0 +#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xFFFFFFFFL +//CP_DRAW_WINDOW_HI +#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0 +#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xFFFFFFFFL +//CP_DRAW_WINDOW_LO +#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0 +#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10 +#define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000FFFFL +#define CP_DRAW_WINDOW_LO__MAX_MASK 0xFFFF0000L +//CP_DRAW_WINDOW_CNTL +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2 +#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L +#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L +//GRBM_PERFCOUNTER0_SELECT +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d +#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e +#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L +#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L +#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L +//GRBM_PERFCOUNTER1_SELECT +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d +#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e +#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L +#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L +#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L +//GRBM_SE0_PERFCOUNTER_SELECT +#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +//GRBM_SE1_PERFCOUNTER_SELECT +#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +//GRBM_SE2_PERFCOUNTER_SELECT +#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +//GRBM_SE3_PERFCOUNTER_SELECT +#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +//WD_PERFCOUNTER0_SELECT +#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL +#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//WD_PERFCOUNTER1_SELECT +#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL +#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//WD_PERFCOUNTER2_SELECT +#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL +#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//WD_PERFCOUNTER3_SELECT +#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL +#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//IA_PERFCOUNTER0_SELECT +#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//IA_PERFCOUNTER1_SELECT +#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL +#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//IA_PERFCOUNTER2_SELECT +#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL +#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//IA_PERFCOUNTER3_SELECT +#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL +#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//IA_PERFCOUNTER0_SELECT1 +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//VGT_PERFCOUNTER0_SELECT +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//VGT_PERFCOUNTER1_SELECT +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//VGT_PERFCOUNTER2_SELECT +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL +#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//VGT_PERFCOUNTER3_SELECT +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL +#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//VGT_PERFCOUNTER0_SELECT1 +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//VGT_PERFCOUNTER1_SELECT1 +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//VGT_PERFCOUNTER_SEID_MASK +#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0 +#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0x000000FFL +//PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SU_PERFCOUNTER0_SELECT1 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SU_PERFCOUNTER1_SELECT1 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SC_PERFCOUNTER0_SELECT1 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SC_PERFCOUNTER1_SELECT +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER2_SELECT +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER3_SELECT +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER4_SELECT +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER5_SELECT +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER6_SELECT +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER7_SELECT +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL +//SPI_PERFCOUNTER0_SELECT +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER1_SELECT +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER2_SELECT +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER3_SELECT +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER0_SELECT1 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER1_SELECT1 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER2_SELECT1 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER3_SELECT1 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER4_SELECT +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000000FFL +//SPI_PERFCOUNTER5_SELECT +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000000FFL +//SPI_PERFCOUNTER_BINS +#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0 +#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4 +#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8 +#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc +#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10 +#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14 +#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18 +#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c +#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000FL +#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000F0L +#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000F00L +#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000F000L +#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000F0000L +#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00F00000L +#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0F000000L +#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xF0000000L +//SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER4_SELECT +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER5_SELECT +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER6_SELECT +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER7_SELECT +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER8_SELECT +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER9_SELECT +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER10_SELECT +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER11_SELECT +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER12_SELECT +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER13_SELECT +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER14_SELECT +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER15_SELECT +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0x0000F000L +#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0x0F000000L +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER_CTRL +#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 +#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1 +#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 +#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3 +#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 +#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5 +#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 +#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8 +#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd +#define SQ_PERFCOUNTER_CTRL__VMID_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L +#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L +#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L +#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L +#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L +#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L +#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L +#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00001F00L +#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L +#define SQ_PERFCOUNTER_CTRL__VMID_MASK_MASK 0xFFFF0000L +//SQ_PERFCOUNTER_MASK +#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0 +#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0x0000FFFFL +#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xFFFF0000L +//SQ_PERFCOUNTER_CTRL2 +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L +//SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SX_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define SX_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define SX_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SX_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SX_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SX_PERFCOUNTER1_SELECT +#define SX_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SX_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define SX_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SX_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define SX_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SX_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SX_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SX_PERFCOUNTER2_SELECT +#define SX_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SX_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SX_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//SX_PERFCOUNTER3_SELECT +#define SX_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SX_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SX_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//SX_PERFCOUNTER0_SELECT1 +#define SX_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SX_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define SX_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SX_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SX_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SX_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SX_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SX_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SX_PERFCOUNTER1_SELECT1 +#define SX_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SX_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define SX_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SX_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SX_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SX_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SX_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SX_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GDS_PERFCOUNTER0_SELECT +#define GDS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GDS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GDS_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GDS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GDS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GDS_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GDS_PERFCOUNTER1_SELECT +#define GDS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GDS_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GDS_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GDS_PERFCOUNTER2_SELECT +#define GDS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GDS_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GDS_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GDS_PERFCOUNTER3_SELECT +#define GDS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GDS_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GDS_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GDS_PERFCOUNTER0_SELECT1 +#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TA_PERFCOUNTER0_SELECT +#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000007FL +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0001FC00L +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TA_PERFCOUNTER0_SELECT1 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x0000007FL +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0001FC00L +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TA_PERFCOUNTER1_SELECT +#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000007FL +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TD_PERFCOUNTER0_SELECT +#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0000FC00L +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TD_PERFCOUNTER0_SELECT1 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x0000003FL +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0000FC00L +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TD_PERFCOUNTER1_SELECT +#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL +#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER0_SELECT +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000007FL +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0001FC00L +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER0_SELECT1 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x0000007FL +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0001FC00L +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TCP_PERFCOUNTER1_SELECT +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000007FL +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0001FC00L +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER1_SELECT1 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x0000007FL +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x0001FC00L +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TCP_PERFCOUNTER2_SELECT +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x0000007FL +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER3_SELECT +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x0000007FL +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//TCC_PERFCOUNTER0_SELECT +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TCC_PERFCOUNTER0_SELECT1 +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L +//TCC_PERFCOUNTER1_SELECT +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TCC_PERFCOUNTER1_SELECT1 +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L +//TCC_PERFCOUNTER2_SELECT +#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//TCC_PERFCOUNTER3_SELECT +#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//TCA_PERFCOUNTER0_SELECT +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TCA_PERFCOUNTER0_SELECT1 +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L +//TCA_PERFCOUNTER1_SELECT +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TCA_PERFCOUNTER1_SELECT1 +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L +//TCA_PERFCOUNTER2_SELECT +#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//TCA_PERFCOUNTER3_SELECT +#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER_FILTER +#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0 +#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5 +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11 +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16 +#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L +#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000EL +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003E0L +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000E000L +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001C0000L +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00C00000L +//CB_PERFCOUNTER0_SELECT +#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL +#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L +#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER0_SELECT1 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CB_PERFCOUNTER1_SELECT +#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL +#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER2_SELECT +#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL +#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER3_SELECT +#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL +#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER0_SELECT +#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER0_SELECT1 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//DB_PERFCOUNTER1_SELECT +#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER1_SELECT1 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//DB_PERFCOUNTER2_SELECT +#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER3_SELECT +#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//RLC_SPM_PERFMON_CNTL +#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0 +#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc +#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10 +#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0x00000FFFL +#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L +#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x0000C000L +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xFFFF0000L +//RLC_SPM_PERFMON_RING_BASE_LO +#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xFFFFFFFFL +//RLC_SPM_PERFMON_RING_BASE_HI +#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10 +#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x0000FFFFL +#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xFFFF0000L +//RLC_SPM_PERFMON_RING_SIZE +#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xFFFFFFFFL +//RLC_SPM_PERFMON_SEGMENT_SIZE +#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f +#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x00000700L +#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000F800L +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x001F0000L +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x03E00000L +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7C000000L +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000L +//RLC_SPM_SE_MUXSEL_ADDR +#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 +#define RLC_SPM_SE_MUXSEL_ADDR__RESERVED__SHIFT 0x8 +#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0x000000FFL +#define RLC_SPM_SE_MUXSEL_ADDR__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_SE_MUXSEL_DATA +#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 +#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL +//RLC_SPM_CPG_PERFMON_SAMPLE_DELAY +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_CPC_PERFMON_SAMPLE_DELAY +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_CPF_PERFMON_SAMPLE_DELAY +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_CB_PERFMON_SAMPLE_DELAY +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_DB_PERFMON_SAMPLE_DELAY +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_PA_PERFMON_SAMPLE_DELAY +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_GDS_PERFMON_SAMPLE_DELAY +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_IA_PERFMON_SAMPLE_DELAY +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_SC_PERFMON_SAMPLE_DELAY +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_TCC_PERFMON_SAMPLE_DELAY +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_TCA_PERFMON_SAMPLE_DELAY +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_TCP_PERFMON_SAMPLE_DELAY +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_TA_PERFMON_SAMPLE_DELAY +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_TD_PERFMON_SAMPLE_DELAY +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_VGT_PERFMON_SAMPLE_DELAY +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_SPI_PERFMON_SAMPLE_DELAY +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_SQG_PERFMON_SAMPLE_DELAY +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_SX_PERFMON_SAMPLE_DELAY +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_GLOBAL_MUXSEL_ADDR +#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 +#define RLC_SPM_GLOBAL_MUXSEL_ADDR__RESERVED__SHIFT 0x7 +#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0x0000007FL +#define RLC_SPM_GLOBAL_MUXSEL_ADDR__RESERVED_MASK 0xFFFFFF80L +//RLC_SPM_GLOBAL_MUXSEL_DATA +#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 +#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL +//RLC_SPM_RING_RDPTR +#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0 +#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xFFFFFFFFL +//RLC_SPM_SEGMENT_THRESHOLD +#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0 +#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xFFFFFFFFL +//RLC_SPM_RMI_PERFMON_SAMPLE_DELAY +#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_PERFMON_SAMPLE_DELAY_MAX +#define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__PERFMON_MAX_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__RESERVED__SHIFT 0x8 +#define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__PERFMON_MAX_SAMPLE_DELAY_MASK 0x000000FFL +#define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__RESERVED_MASK 0xFFFFFF00L +//RLC_PERFMON_CNTL +#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L +//RLC_PERFCOUNTER0_SELECT +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL +//RLC_PERFCOUNTER1_SELECT +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL +//RLC_GPU_IOV_PERF_CNT_CNTL +#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x1 +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x2 +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x3 +#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L +#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xFFFFFFF8L +//RLC_GPU_IOV_PERF_CNT_WR_ADDR +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x4 +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x6 +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000000FL +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000030L +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xFFFFFFC0L +//RLC_GPU_IOV_PERF_CNT_WR_DATA +#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0x0000000FL +//RLC_GPU_IOV_PERF_CNT_RD_ADDR +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x4 +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x6 +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000000FL +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000030L +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xFFFFFFC0L +//RLC_GPU_IOV_PERF_CNT_RD_DATA +#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0x0000000FL +//RMI_PERFCOUNTER0_SELECT +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L +#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERFCOUNTER0_SELECT1 +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//RMI_PERFCOUNTER1_SELECT +#define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL +#define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERFCOUNTER2_SELECT +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x0007FC00L +#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERFCOUNTER2_SELECT1 +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000001FFL +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x0007FC00L +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//RMI_PERFCOUNTER3_SELECT +#define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL +#define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERF_COUNTER_CNTL +#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x0 +#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x2 +#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x4 +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x6 +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x8 +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0xe +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x13 +#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x19 +#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x1a +#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L +#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000CL +#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000C0L +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003C00L +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007C000L +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01F80000L +#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L +#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L + + +// addressBlock: xcd0_gc_utcl2_atcl2pfcntldec +//ATC_L2_PERFCOUNTER0_CFG +#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//ATC_L2_PERFCOUNTER1_CFG +#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//ATC_L2_PERFCOUNTER_RSLT_CNTL +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: xcd0_gc_utcl2_vml2pldec +//MC_VM_L2_PERFCOUNTER0_CFG +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER1_CFG +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER2_CFG +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER3_CFG +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER4_CFG +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER5_CFG +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER6_CFG +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER7_CFG +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L +#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L +#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L +//MC_VM_L2_PERFCOUNTER_RSLT_CNTL +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: xcd0_gc_utcl2_l2tlbpldec +//L2TLB_PERFCOUNTER0_CFG +#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define L2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define L2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define L2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define L2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define L2TLB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define L2TLB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//L2TLB_PERFCOUNTER1_CFG +#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define L2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define L2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define L2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define L2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define L2TLB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define L2TLB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//L2TLB_PERFCOUNTER2_CFG +#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define L2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define L2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define L2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define L2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define L2TLB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define L2TLB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//L2TLB_PERFCOUNTER3_CFG +#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define L2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define L2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define L2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define L2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define L2TLB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define L2TLB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//L2TLB_PERFCOUNTER_RSLT_CNTL +#define L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: xcd0_gc_gdflldec +//GDFLL_EDC_HYSTERESIS_CNTL +#define GDFLL_EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS__SHIFT 0x0 +#define GDFLL_EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS_MASK 0x000000FFL +//GDFLL_EDC_HYSTERESIS_STAT +#define GDFLL_EDC_HYSTERESIS_STAT__HYSTERESIS_CNT__SHIFT 0x0 +#define GDFLL_EDC_HYSTERESIS_STAT__EDC__SHIFT 0x8 +#define GDFLL_EDC_HYSTERESIS_STAT__HYSTERESIS_CNT_MASK 0x000000FFL +#define GDFLL_EDC_HYSTERESIS_STAT__EDC_MASK 0x00000100L + + +// addressBlock: xcd0_gc_rlcpdec +//RLC_CNTL +#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0 +#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1 +#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2 +#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3 +#define RLC_CNTL__RESERVED__SHIFT 0x4 +#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L +#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L +#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L +#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L +#define RLC_CNTL__RESERVED_MASK 0xFFFFFFF0L +//RLC_CGCG_CGLS_CTRL_2 +#define RLC_CGCG_CGLS_CTRL_2__CANE_STAT_BUSY_MASK__SHIFT 0x0 +#define RLC_CGCG_CGLS_CTRL_2__RESERVED__SHIFT 0x1 +#define RLC_CGCG_CGLS_CTRL_2__CANE_STAT_BUSY_MASK_MASK 0x00000001L +#define RLC_CGCG_CGLS_CTRL_2__RESERVED_MASK 0xFFFFFFFEL +//RLC_STAT +#define RLC_STAT__RLC_BUSY__SHIFT 0x0 +#define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x1 +#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x2 +#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x3 +#define RLC_STAT__MC_BUSY__SHIFT 0x4 +#define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x5 +#define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x6 +#define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x7 +#define RLC_STAT__RESERVED__SHIFT 0x8 +#define RLC_STAT__RLC_BUSY_MASK 0x00000001L +#define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000002L +#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000004L +#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000008L +#define RLC_STAT__MC_BUSY_MASK 0x00000010L +#define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L +#define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L +#define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L +#define RLC_STAT__RESERVED_MASK 0xFFFFFF00L +//RLC_SAFE_MODE +#define RLC_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_SAFE_MODE__CMD_MASK 0x00000001L +#define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001EL +#define RLC_SAFE_MODE__RESERVED1_MASK 0x000000E0L +#define RLC_SAFE_MODE__RESPONSE_MASK 0x00000F00L +#define RLC_SAFE_MODE__RESERVED_MASK 0xFFFFF000L +//RLC_MEM_SLP_CNTL +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0 +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1 +#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 +#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10 +#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L +#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL +#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000FF00L +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00FF0000L +#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L +//SMU_RLC_RESPONSE +#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0 +#define SMU_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL +//RLC_RLCV_SAFE_MODE +#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L +#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001EL +#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000E0L +#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000F00L +#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xFFFFF000L +//RLC_SMU_SAFE_MODE +#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_SMU_SAFE_MODE__CMD_MASK 0x00000001L +#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x0000001EL +#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0x000000E0L +#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0x00000F00L +#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xFFFFF000L +//RLC_RLCV_COMMAND +#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0 +#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4 +#define RLC_RLCV_COMMAND__CMD_MASK 0x0000000FL +#define RLC_RLCV_COMMAND__RESERVED_MASK 0xFFFFFFF0L +//RLC_REFCLOCK_TIMESTAMP_LSB +#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x0 +#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xFFFFFFFFL +//RLC_REFCLOCK_TIMESTAMP_MSB +#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x0 +#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_0 +#define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_1 +#define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_2 +#define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_CTRL +#define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 +#define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 +#define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x2 +#define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x3 +#define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0x4 +#define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L +#define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L +#define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L +#define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L +#define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xFFFFFFF0L +//RLC_LB_CNTR_MAX +#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0 +#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_STAT +#define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 +#define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 +#define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x2 +#define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x3 +#define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 +#define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 +#define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT 0xa +#define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC__SHIFT 0xb +#define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0xc +#define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L +#define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L +#define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L +#define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L +#define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L +#define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L +#define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC_MASK 0x00000400L +#define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC_MASK 0x00000800L +#define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xFFFFF000L +//RLC_GPM_TIMER_INT_3 +#define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xFFFFFFFFL +//RLC_SERDES_WR_NONCU_MASTER_MASK_1 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1__SHIFT 0x0 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1__SHIFT 0x10 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1__SHIFT 0x11 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK__SHIFT 0x12 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1__SHIFT 0x13 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK__SHIFT 0x14 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK__SHIFT 0x15 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK__SHIFT 0x16 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK__SHIFT 0x17 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK__SHIFT 0x18 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED__SHIFT 0x19 +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1_MASK 0x0000FFFFL +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1_MASK 0x00010000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1_MASK 0x00020000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK_MASK 0x00040000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1_MASK 0x00080000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK_MASK 0x00100000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK_MASK 0x00200000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK_MASK 0x00400000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK_MASK 0x00800000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK_MASK 0x01000000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_MASK 0xFE000000L +//RLC_SERDES_NONCU_MASTER_BUSY_1 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1__SHIFT 0x0 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1__SHIFT 0x10 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1__SHIFT 0x11 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1__SHIFT 0x12 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1__SHIFT 0x13 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY__SHIFT 0x14 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY__SHIFT 0x15 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY__SHIFT 0x16 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY__SHIFT 0x17 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY__SHIFT 0x18 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED__SHIFT 0x19 +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1_MASK 0x0000FFFFL +#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1_MASK 0x00010000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1_MASK 0x00020000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1_MASK 0x00040000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1_MASK 0x00080000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY_MASK 0x00100000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY_MASK 0x00200000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY_MASK 0x00400000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY_MASK 0x00800000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY_MASK 0x01000000L +#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_MASK 0xFE000000L +//RLC_INT_STAT +#define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x0 +#define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x8 +#define RLC_INT_STAT__RESERVED__SHIFT 0x9 +#define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000FFL +#define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L +#define RLC_INT_STAT__RESERVED_MASK 0xFFFFFE00L +//RLC_LB_CNTL +#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0 +#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1 +#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2 +#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3 +#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4 +#define RLC_LB_CNTL__RESERVED__SHIFT 0xc +#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L +#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L +#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L +#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L +#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0x00000FF0L +#define RLC_LB_CNTL__RESERVED_MASK 0xFFFFF000L +//RLC_MGCG_CTRL +#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0 +#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1 +#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2 +#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3 +#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7 +#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0xf +#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x10 +#define RLC_MGCG_CTRL__SPARE__SHIFT 0x11 +#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L +#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L +#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L +#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L +#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007F80L +#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x00008000L +#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x00010000L +#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L +//RLC_LB_CNTR_INIT +#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0 +#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xFFFFFFFFL +//RLC_LOAD_BALANCE_CNTR +#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0 +#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xFFFFFFFFL +//RLC_JUMP_TABLE_RESTORE +#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0 +#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xFFFFFFFFL +//RLC_PG_DELAY_2 +#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0 +#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8 +#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10 +#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000FFL +#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000FF00L +#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xFFFF0000L +//RLC_GPU_CLOCK_COUNT_LSB +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_MSB +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL +//RLC_CAPTURE_GPU_CLOCK_COUNT +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xFFFFFFFEL +//RLC_UCODE_CNTL +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0 +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xFFFFFFFFL +//RLC_GPM_THREAD_RESET +#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0 +#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1 +#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2 +#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3 +#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4 +#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L +#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L +#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L +#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L +#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xFFFFFFF0L +//RLC_GPM_CP_DMA_COMPLETE_T0 +#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x0 +#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x1 +#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L +#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPM_CP_DMA_COMPLETE_T1 +#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x0 +#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x1 +#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L +#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xFFFFFFFEL +//RLC_FIREWALL_VIOLATION +#define RLC_FIREWALL_VIOLATION__ADDR__SHIFT 0x0 +#define RLC_FIREWALL_VIOLATION__ADDR_MASK 0xFFFFFFFFL +//RLC_CLK_COUNT_GFXCLK_LSB +#define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER__SHIFT 0x0 +#define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER_MASK 0xFFFFFFFFL +//RLC_CLK_COUNT_GFXCLK_MSB +#define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER__SHIFT 0x0 +#define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER_MASK 0xFFFFFFFFL +//RLC_CLK_COUNT_REFCLK_LSB +#define RLC_CLK_COUNT_REFCLK_LSB__COUNTER__SHIFT 0x0 +#define RLC_CLK_COUNT_REFCLK_LSB__COUNTER_MASK 0xFFFFFFFFL +//RLC_CLK_COUNT_REFCLK_MSB +#define RLC_CLK_COUNT_REFCLK_MSB__COUNTER__SHIFT 0x0 +#define RLC_CLK_COUNT_REFCLK_MSB__COUNTER_MASK 0xFFFFFFFFL +//RLC_CLK_COUNT_CTRL +#define RLC_CLK_COUNT_CTRL__GFXCLK_RUN__SHIFT 0x0 +#define RLC_CLK_COUNT_CTRL__GFXCLK_RESET__SHIFT 0x1 +#define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE__SHIFT 0x2 +#define RLC_CLK_COUNT_CTRL__REFCLK_RUN__SHIFT 0x3 +#define RLC_CLK_COUNT_CTRL__REFCLK_RESET__SHIFT 0x4 +#define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE__SHIFT 0x5 +#define RLC_CLK_COUNT_CTRL__GFXCLK_RUN_MASK 0x00000001L +#define RLC_CLK_COUNT_CTRL__GFXCLK_RESET_MASK 0x00000002L +#define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE_MASK 0x00000004L +#define RLC_CLK_COUNT_CTRL__REFCLK_RUN_MASK 0x00000008L +#define RLC_CLK_COUNT_CTRL__REFCLK_RESET_MASK 0x00000010L +#define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE_MASK 0x00000020L +//RLC_CLK_COUNT_STAT +#define RLC_CLK_COUNT_STAT__GFXCLK_VALID__SHIFT 0x0 +#define RLC_CLK_COUNT_STAT__REFCLK_VALID__SHIFT 0x1 +#define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC__SHIFT 0x2 +#define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC__SHIFT 0x3 +#define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC__SHIFT 0x4 +#define RLC_CLK_COUNT_STAT__RESERVED__SHIFT 0x5 +#define RLC_CLK_COUNT_STAT__GFXCLK_VALID_MASK 0x00000001L +#define RLC_CLK_COUNT_STAT__REFCLK_VALID_MASK 0x00000002L +#define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC_MASK 0x00000004L +#define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC_MASK 0x00000008L +#define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC_MASK 0x00000010L +#define RLC_CLK_COUNT_STAT__RESERVED_MASK 0xFFFFFFE0L +//RLC_GPM_STAT +#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0 +#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 +#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 +#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 +#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 +#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 +#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 +#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 +#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 +#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 +#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa +#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb +#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc +#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd +#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe +#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf +#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10 +#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 +#define RLC_GPM_STAT__CMP_power_status__SHIFT 0x12 +#define RLC_GPM_STAT__RESERVED_1__SHIFT 0x13 +#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15 +#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16 +#define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT 0x17 +#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 +#define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L +#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L +#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L +#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L +#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L +#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L +#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L +#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L +#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L +#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L +#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L +#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L +#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L +#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x00002000L +#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x00004000L +#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x00008000L +#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x00010000L +#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L +#define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L +#define RLC_GPM_STAT__RESERVED_1_MASK 0x00180000L +#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L +#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L +#define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK 0x00800000L +#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L +//RLC_GPU_CLOCK_32_RES_SEL +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6 +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003FL +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xFFFFFFC0L +//RLC_GPU_CLOCK_32 +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0 +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xFFFFFFFFL +//RLC_PG_CNTL +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0 +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1 +#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2 +#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3 +#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4 +#define RLC_PG_CNTL__RESERVED__SHIFT 0x5 +#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe +#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12 +#define RLC_PG_CNTL__RESERVED1__SHIFT 0x13 +#define RLC_PG_CNTL__Ultra_Low_Voltage_Enable__SHIFT 0x15 +#define RLC_PG_CNTL__RESERVED2__SHIFT 0x16 +#define RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE__SHIFT 0x17 +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L +#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L +#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x00000008L +#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L +#define RLC_PG_CNTL__RESERVED_MASK 0x00003FE0L +#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L +#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L +#define RLC_PG_CNTL__RESERVED1_MASK 0x00180000L +#define RLC_PG_CNTL__Ultra_Low_Voltage_Enable_MASK 0x00200000L +#define RLC_PG_CNTL__RESERVED2_MASK 0x00400000L +#define RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK 0x00800000L +//RLC_GPM_THREAD_PRIORITY +#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0 +#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8 +#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10 +#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18 +#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000FFL +#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000FF00L +#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00FF0000L +#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xFF000000L +//RLC_GPM_THREAD_ENABLE +#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0 +#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1 +#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2 +#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3 +#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4 +#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L +#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L +#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L +#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L +#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xFFFFFFF0L +//RLC_CGTT_MGCG_OVERRIDE +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0__SHIFT 0x0 +#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x1 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x2 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x3 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x4 +#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x5 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x6 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x7 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE__SHIFT 0x8 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE__SHIFT 0x9 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_PERF_CLK_EN__SHIFT 0xa +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_11__SHIFT 0xb +#define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY__SHIFT 0x10 +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17__SHIFT 0x11 +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0_MASK 0x00000001L +#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L +#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK 0x00000100L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK 0x00000200L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_PERF_CLK_EN_MASK 0x00000400L +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_11_MASK 0x0000F800L +#define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK 0x00010000L +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17_MASK 0xFFFE0000L +//RLC_CGCG_CGLS_CTRL +#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0 +#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1 +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d +#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f +#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L +#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L +#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L +//RLC_CGCG_RAMP_CTRL +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0 +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10 +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000FL +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000F00L +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000F000L +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0FFF0000L +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xF0000000L +//RLC_DYN_PG_STATUS +#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 +#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL +//RLC_DYN_PG_REQUEST +#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0 +#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xFFFFFFFFL +//RLC_PG_DELAY +#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0 +#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8 +#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10 +#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18 +#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000FFL +#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000FF00L +#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00FF0000L +#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xFF000000L +//RLC_CU_STATUS +#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0 +#define RLC_CU_STATUS__WORK_PENDING_MASK 0xFFFFFFFFL +//RLC_LB_INIT_CU_MASK +#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0 +#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xFFFFFFFFL +//RLC_LB_ALWAYS_ACTIVE_CU_MASK +#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0 +#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xFFFFFFFFL +//RLC_LB_PARAMS +#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0 +#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10 +#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L +#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000FEL +#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000FF00L +#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xFFFF0000L +//RLC_THREAD1_DELAY +#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0 +#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8 +#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10 +#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18 +#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0x000000FFL +#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000FF00L +#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00FF0000L +#define RLC_THREAD1_DELAY__SPARE_MASK 0xFF000000L +//RLC_PG_ALWAYS_ON_CU_MASK +#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0 +#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xFFFFFFFFL +//RLC_MAX_PG_CU +#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0 +#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8 +#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0x000000FFL +#define RLC_MAX_PG_CU__SPARE_MASK 0xFFFFFF00L +//RLC_AUTO_PG_CTRL +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0 +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1 +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2 +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3 +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13 +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007FFF8L +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L +//RLC_SMU_GRBM_REG_SAVE_CTRL +#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0 +#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1 +#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x00000001L +#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xFFFFFFFEL +//RLC_SERDES_RD_PENDING +#define RLC_SERDES_RD_PENDING__RD_PENDING__SHIFT 0x0 +#define RLC_SERDES_RD_PENDING__RD_PENDING_MASK 0x00000001L +//RLC_SERDES_RD_MASTER_INDEX +#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0 +#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4 +#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xc +#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xd +#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0x11 +#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x13 +#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0x0000000FL +#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x00000030L +#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x000001C0L +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x00000E00L +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x00001000L +#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x0001E000L +#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x00060000L +#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xFFF80000L +//RLC_SERDES_RD_DATA_0 +#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_RD_DATA_1 +#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_RD_DATA_2 +#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_WR_CU_MASTER_MASK +#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0 +#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xFFFFFFFFL +//RLC_SERDES_WR_NONCU_MASTER_MASK +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK__SHIFT 0x18 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK__SHIFT 0x19 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x1a +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0x0000FFFFL +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x00010000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x00020000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x00040000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x00080000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x00100000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x00200000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x00400000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x00800000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK_MASK 0x01000000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK_MASK 0x02000000L +#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xFC000000L +//RLC_SERDES_WR_CTRL +#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0 +#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8 +#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9 +#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa +#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb +#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc +#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd +#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe +#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf +#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10 +#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a +#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b +#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c +#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0x000000FFL +#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x00000100L +#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x00000200L +#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x00000400L +#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x00000800L +#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x00001000L +#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x00002000L +#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x00004000L +#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x00008000L +#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x03FF0000L +#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x04000000L +#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x08000000L +#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xF0000000L +//RLC_SERDES_WR_DATA +#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0 +#define RLC_SERDES_WR_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_CU_MASTER_BUSY +#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0 +#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xFFFFFFFFL +//RLC_SERDES_NONCU_MASTER_BUSY +#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0 +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10 +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11 +#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12 +#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17 +#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY__SHIFT 0x18 +#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY__SHIFT 0x19 +#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x1a +#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0x0000FFFFL +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x00010000L +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x00020000L +#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x00040000L +#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x00080000L +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x00100000L +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x00200000L +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x00400000L +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x00800000L +#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY_MASK 0x01000000L +#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY_MASK 0x02000000L +#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xFC000000L +//RLC_GPM_GENERAL_0 +#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_0__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_1 +#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_1__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_2 +#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_2__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_3 +#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_3__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_4 +#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_4__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_5 +#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_5__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_6 +#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_6__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_7 +#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_7__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_SCRATCH_ADDR +#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0 +#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9 +#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x000001FFL +#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L +//RLC_GPM_SCRATCH_DATA +#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0 +#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_STATIC_PG_STATUS +#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 +#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL +//RLC_SPM_MC_CNTL +#define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x0 +#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT 0x4 +#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x5 +#define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x6 +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x7 +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x8 +#define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0xa +#define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000FL +#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK 0x00000010L +#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000020L +#define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000040L +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00000080L +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00000300L +#define RLC_SPM_MC_CNTL__RESERVED_MASK 0xFFFFFC00L +//RLC_SPM_INT_CNTL +#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0 +#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1 +#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L +#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xFFFFFFFEL +//RLC_SPM_INT_STATUS +#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0 +#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1 +#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L +#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xFFFFFFFEL +//RLC_SMU_MESSAGE +#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0 +#define RLC_SMU_MESSAGE__CMD_MASK 0xFFFFFFFFL +//RLC_GPM_LOG_SIZE +#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0 +#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xFFFFFFFFL +//RLC_PG_DELAY_3 +#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0 +#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8 +#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0x000000FFL +#define RLC_PG_DELAY_3__RESERVED_MASK 0xFFFFFF00L +//RLC_GPR_REG1 +#define RLC_GPR_REG1__DATA__SHIFT 0x0 +#define RLC_GPR_REG1__DATA_MASK 0xFFFFFFFFL +//RLC_GPR_REG2 +#define RLC_GPR_REG2__DATA__SHIFT 0x0 +#define RLC_GPR_REG2__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_LOG_CONT +#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0 +#define RLC_GPM_LOG_CONT__CONT_MASK 0xFFFFFFFFL +//RLC_GPM_INT_DISABLE_TH0 +#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0 +#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xFFFFFFFFL +//RLC_GPM_INT_FORCE_TH0 +#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0 +#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xFFFFFFFFL +//RLC_GPM_INT_FORCE_TH1 +#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0 +#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xFFFFFFFFL +//RLC_SRM_CNTL +#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0 +#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1 +#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2 +#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L +#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L +#define RLC_SRM_CNTL__RESERVED_MASK 0xFFFFFFFCL +//RLC_SRM_ARAM_ADDR +#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xb +#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x000007FFL +#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xFFFFF800L +//RLC_SRM_ARAM_DATA +#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0 +#define RLC_SRM_ARAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_DRAM_ADDR +#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xb +#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x000007FFL +#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xFFFFF800L +//RLC_SRM_DRAM_DATA +#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0 +#define RLC_SRM_DRAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_GPM_COMMAND +#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0 +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1 +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2 +#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5 +#define RLC_SRM_GPM_COMMAND__RESERVED_16__SHIFT 0x10 +#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11 +#define RLC_SRM_GPM_COMMAND__RESERVED_30_29__SHIFT 0x1d +#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f +#define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL +#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0000FFE0L +#define RLC_SRM_GPM_COMMAND__RESERVED_16_MASK 0x00010000L +#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x0FFE0000L +#define RLC_SRM_GPM_COMMAND__RESERVED_30_29_MASK 0x60000000L +#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000L +//RLC_SRM_GPM_COMMAND_STATUS +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 +#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2 +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L +#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL +//RLC_SRM_RLCV_COMMAND +#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0 +#define RLC_SRM_RLCV_COMMAND__INDEX_CNTL__SHIFT 0x1 +#define RLC_SRM_RLCV_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2 +#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x5 +#define RLC_SRM_RLCV_COMMAND__RESERVED_16__SHIFT 0x10 +#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x11 +#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c +#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f +#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x00000001L +#define RLC_SRM_RLCV_COMMAND__INDEX_CNTL_MASK 0x00000002L +#define RLC_SRM_RLCV_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL +#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0x0000FFE0L +#define RLC_SRM_RLCV_COMMAND__RESERVED_16_MASK 0x00010000L +#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0x0FFE0000L +#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000L +#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000L +//RLC_SRM_RLCV_COMMAND_STATUS +#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 +#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 +#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2 +#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L +#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L +#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL +//RLC_SRM_INDEX_CNTL_ADDR_0 +#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_ADDR_1 +#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_ADDR_2 +#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_ADDR_3 +#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_ADDR_4 +#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_ADDR_5 +#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_ADDR_6 +#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_ADDR_7 +#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0000FFFFL +#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xFFFF0000L +//RLC_SRM_INDEX_CNTL_DATA_0 +#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_1 +#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_2 +#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_3 +#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_4 +#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_5 +#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_6 +#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_7 +#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_STAT +#define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x0 +#define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT 0x1 +#define RLC_SRM_STAT__RESERVED__SHIFT 0x2 +#define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L +#define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK 0x00000002L +#define RLC_SRM_STAT__RESERVED_MASK 0xFFFFFFFCL +//RLC_SRM_GPM_ABORT +#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0 +#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1 +#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L +#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xFFFFFFFEL +//RLC_CSIB_ADDR_LO +#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0 +#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xFFFFFFFFL +//RLC_CSIB_ADDR_HI +#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0 +#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x0000FFFFL +//RLC_CSIB_LENGTH +#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0 +#define RLC_CSIB_LENGTH__LENGTH_MASK 0xFFFFFFFFL +//RLC_SMU_COMMAND +#define RLC_SMU_COMMAND__CMD__SHIFT 0x0 +#define RLC_SMU_COMMAND__CMD_MASK 0xFFFFFFFFL +//RLC_CP_SCHEDULERS +#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0 +#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8 +#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10 +#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18 +#define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000FFL +#define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000FF00L +#define RLC_CP_SCHEDULERS__scheduler2_MASK 0x00FF0000L +#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xFF000000L +//RLC_SMU_ARGUMENT_1 +#define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_1__ARG_MASK 0xFFFFFFFFL +//RLC_SMU_ARGUMENT_2 +#define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_2__ARG_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_8 +#define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_8__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_9 +#define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_9__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_10 +#define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_10__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_11 +#define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_11__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_12 +#define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_12__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_CNTL_0 +#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x18 +#define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x19 +#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x1a +#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x1c +#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L +#define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0x02000000L +#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L +#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L +//RLC_GPM_UTCL1_CNTL_1 +#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT 0x18 +#define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT 0x19 +#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT 0x1a +#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT 0x1c +#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK 0x01000000L +#define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK 0x02000000L +#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK 0x04000000L +#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK 0x10000000L +//RLC_GPM_UTCL1_CNTL_2 +#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT 0x18 +#define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT 0x19 +#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT 0x1a +#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT 0x1c +#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK 0x01000000L +#define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK 0x02000000L +#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK 0x04000000L +#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK 0x10000000L +//RLC_SPM_UTCL1_CNTL +#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x19 +#define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0x02000000L +#define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +//RLC_UTCL1_STATUS_2 +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x0 +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x1 +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x2 +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x3 +#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT 0x4 +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x5 +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x6 +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0x7 +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0x8 +#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT 0x9 +#define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0xa +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L +#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK 0x00000010L +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000020L +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000040L +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000080L +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000100L +#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK 0x00000200L +#define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xFFFFFC00L +//RLC_LB_THR_CONFIG_2 +#define RLC_LB_THR_CONFIG_2__DATA__SHIFT 0x0 +#define RLC_LB_THR_CONFIG_2__DATA_MASK 0xFFFFFFFFL +//RLC_LB_THR_CONFIG_3 +#define RLC_LB_THR_CONFIG_3__DATA__SHIFT 0x0 +#define RLC_LB_THR_CONFIG_3__DATA_MASK 0xFFFFFFFFL +//RLC_LB_THR_CONFIG_4 +#define RLC_LB_THR_CONFIG_4__DATA__SHIFT 0x0 +#define RLC_LB_THR_CONFIG_4__DATA_MASK 0xFFFFFFFFL +//RLC_SPM_UTCL1_ERROR_1 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L +//RLC_SPM_UTCL1_ERROR_2 +#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_TH0_ERROR_1 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L +//RLC_LB_THR_CONFIG_1 +#define RLC_LB_THR_CONFIG_1__DATA__SHIFT 0x0 +#define RLC_LB_THR_CONFIG_1__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_TH0_ERROR_2 +#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_TH1_ERROR_1 +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L +//RLC_GPM_UTCL1_TH1_ERROR_2 +#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_TH2_ERROR_1 +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L +//RLC_GPM_UTCL1_TH2_ERROR_2 +#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_SEMAPHORE_0 +#define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_0__RESERVED__SHIFT 0x5 +#define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL +#define RLC_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L +//RLC_SEMAPHORE_1 +#define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_1__RESERVED__SHIFT 0x5 +#define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL +#define RLC_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L +//RLC_CP_EOF_INT +#define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x0 +#define RLC_CP_EOF_INT__RESERVED__SHIFT 0x1 +#define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L +#define RLC_CP_EOF_INT__RESERVED_MASK 0xFFFFFFFEL +//RLC_CP_EOF_INT_CNT +#define RLC_CP_EOF_INT_CNT__CNT__SHIFT 0x0 +#define RLC_CP_EOF_INT_CNT__CNT_MASK 0xFFFFFFFFL +//RLC_SPARE_INT +#define RLC_SPARE_INT__INTERRUPT__SHIFT 0x0 +#define RLC_SPARE_INT__RESERVED__SHIFT 0x1 +#define RLC_SPARE_INT__INTERRUPT_MASK 0x00000001L +#define RLC_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL +//RLC_PREWALKER_UTCL1_CNTL +#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT 0x19 +#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK 0x02000000L +#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +//RLC_PREWALKER_UTCL1_TRIG +#define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT 0x0 +#define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT 0x1 +#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT 0x5 +#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT 0x6 +#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT 0x7 +#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT 0x8 +#define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT 0x9 +#define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT 0x1f +#define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK 0x00000001L +#define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK 0x0000001EL +#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK 0x00000020L +#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK 0x00000040L +#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK 0x00000080L +#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK 0x00000100L +#define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK 0x7FFFFE00L +#define RLC_PREWALKER_UTCL1_TRIG__READY_MASK 0x80000000L +//RLC_PREWALKER_UTCL1_ADDR_LSB +#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT 0x0 +#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK 0xFFFFFFFFL +//RLC_PREWALKER_UTCL1_ADDR_MSB +#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT 0x0 +#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK 0x0000FFFFL +//RLC_PREWALKER_UTCL1_SIZE_LSB +#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT 0x0 +#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK 0xFFFFFFFFL +//RLC_PREWALKER_UTCL1_SIZE_MSB +#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT 0x0 +#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK 0x00000003L +//RLC_DSM_TRIG +#define RLC_DSM_TRIG__START__SHIFT 0x0 +#define RLC_DSM_TRIG__START_MASK 0x00000001L +//RLC_UTCL1_STATUS +#define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x3 +#define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0xe +#define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x16 +#define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x1e +#define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000F8L +#define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000C000L +#define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00C00000L +#define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +#define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xC0000000L +//RLC_R2I_CNTL_0 +#define RLC_R2I_CNTL_0__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_0__Data_MASK 0xFFFFFFFFL +//RLC_R2I_CNTL_1 +#define RLC_R2I_CNTL_1__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_1__Data_MASK 0xFFFFFFFFL +//RLC_R2I_CNTL_2 +#define RLC_R2I_CNTL_2__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_2__Data_MASK 0xFFFFFFFFL +//RLC_R2I_CNTL_3 +#define RLC_R2I_CNTL_3__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_3__Data_MASK 0xFFFFFFFFL +//RLC_UTCL2_CNTL +#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0 +#define RLC_UTCL2_CNTL__IGNORE_PTE_PERMISSION__SHIFT 0x1 +#define RLC_UTCL2_CNTL__RESERVED__SHIFT 0x2 +#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L +#define RLC_UTCL2_CNTL__IGNORE_PTE_PERMISSION_MASK 0x00000002L +#define RLC_UTCL2_CNTL__RESERVED_MASK 0xFFFFFFFCL +//RLC_LBPW_CU_STAT +#define RLC_LBPW_CU_STAT__MAX_CU__SHIFT 0x0 +#define RLC_LBPW_CU_STAT__ON_CU__SHIFT 0x10 +#define RLC_LBPW_CU_STAT__MAX_CU_MASK 0x0000FFFFL +#define RLC_LBPW_CU_STAT__ON_CU_MASK 0xFFFF0000L +//RLC_DS_CNTL +#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x0 +#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x1 +#define RLC_DS_CNTL__GFX_CLK_TCC_RLC_GRBM_CC_RESIDENT_MASK__SHIFT 0x2 +#define RLC_DS_CNTL__GFX_CLK_EA_RLC_GRBM_STAT_BUSY_MASK__SHIFT 0x3 +#define RLC_DS_CNTL__RESRVED__SHIFT 0x4 +#define RLC_DS_CNTL__SOC_CLK_TCC_RLC_GRBM_CC_RESIDENT_MASK__SHIFT 0xe +#define RLC_DS_CNTL__SOC_CLK_EA_RLC_GRBM_STAT_BUSY_MASK__SHIFT 0xf +#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x10 +#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x11 +#define RLC_DS_CNTL__RESRVED_1__SHIFT 0x12 +#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000001L +#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000002L +#define RLC_DS_CNTL__GFX_CLK_TCC_RLC_GRBM_CC_RESIDENT_MASK_MASK 0x00000004L +#define RLC_DS_CNTL__GFX_CLK_EA_RLC_GRBM_STAT_BUSY_MASK_MASK 0x00000008L +#define RLC_DS_CNTL__RESRVED_MASK 0x00003FF0L +#define RLC_DS_CNTL__SOC_CLK_TCC_RLC_GRBM_CC_RESIDENT_MASK_MASK 0x00004000L +#define RLC_DS_CNTL__SOC_CLK_EA_RLC_GRBM_STAT_BUSY_MASK_MASK 0x00008000L +#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00010000L +#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00020000L +#define RLC_DS_CNTL__RESRVED_1_MASK 0xFFFC0000L +//RLC_GPM_INT_STAT_TH0 +#define RLC_GPM_INT_STAT_TH0__STATUS__SHIFT 0x0 +#define RLC_GPM_INT_STAT_TH0__STATUS_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_13 +#define RLC_GPM_GENERAL_13__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_13__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_14 +#define RLC_GPM_GENERAL_14__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_14__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_15 +#define RLC_GPM_GENERAL_15__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_15__DATA_MASK 0xFFFFFFFFL +//RLC_SPARE_INT_1 +#define RLC_SPARE_INT_1__INTERRUPT__SHIFT 0x0 +#define RLC_SPARE_INT_1__RESERVED__SHIFT 0x1 +#define RLC_SPARE_INT_1__INTERRUPT_MASK 0x00000001L +#define RLC_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCV_SPARE_INT_1 +#define RLC_RLCV_SPARE_INT_1__INTERRUPT__SHIFT 0x0 +#define RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT 0x1 +#define RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK 0x00000001L +#define RLC_RLCV_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL +//RLC_SEMAPHORE_2 +#define RLC_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_2__RESERVED__SHIFT 0x5 +#define RLC_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL +#define RLC_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L +//RLC_SEMAPHORE_3 +#define RLC_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_3__RESERVED__SHIFT 0x5 +#define RLC_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL +#define RLC_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L +//RLC_SMU_ARGUMENT_3 +#define RLC_SMU_ARGUMENT_3__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_3__ARG_MASK 0xFFFFFFFFL +//RLC_SMU_ARGUMENT_4 +#define RLC_SMU_ARGUMENT_4__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_4__ARG_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_LSB_1 +#define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_MSB_1 +#define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL +//RLC_CAPTURE_GPU_CLOCK_COUNT_1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED__SHIFT 0x1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE_MASK 0x00000001L +#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPU_CLOCK_COUNT_LSB_2 +#define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_MSB_2 +#define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL +//RLC_CAPTURE_GPU_CLOCK_COUNT_2 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED__SHIFT 0x1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE_MASK 0x00000001L +#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED_MASK 0xFFFFFFFEL +//RLC_CPG_STAT_INVAL +#define RLC_CPG_STAT_INVAL__CPG_stat_inval__SHIFT 0x0 +#define RLC_CPG_STAT_INVAL__CPG_stat_inval_MASK 0x00000001L +//RLC_UE_ERR_STATUS_LOW +#define RLC_UE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define RLC_UE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define RLC_UE_ERR_STATUS_LOW__ADDRESS__SHIFT 0x2 +#define RLC_UE_ERR_STATUS_LOW__MEMORY_ID__SHIFT 0x18 +#define RLC_UE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define RLC_UE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define RLC_UE_ERR_STATUS_LOW__ADDRESS_MASK 0x00FFFFFCL +#define RLC_UE_ERR_STATUS_LOW__MEMORY_ID_MASK 0xFF000000L +//RLC_UE_ERR_STATUS_HIGH +#define RLC_UE_ERR_STATUS_HIGH__ECC__SHIFT 0x0 +#define RLC_UE_ERR_STATUS_HIGH__PARITY__SHIFT 0x1 +#define RLC_UE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define RLC_UE_ERR_STATUS_HIGH__ERR_INFO__SHIFT 0x3 +#define RLC_UE_ERR_STATUS_HIGH__UE_CNT__SHIFT 0x17 +#define RLC_UE_ERR_STATUS_HIGH__FED_CNT__SHIFT 0x1a +#define RLC_UE_ERR_STATUS_HIGH__RESERVED__SHIFT 0x1d +#define RLC_UE_ERR_STATUS_HIGH__ECC_MASK 0x00000001L +#define RLC_UE_ERR_STATUS_HIGH__PARITY_MASK 0x00000002L +#define RLC_UE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define RLC_UE_ERR_STATUS_HIGH__ERR_INFO_MASK 0x007FFFF8L +#define RLC_UE_ERR_STATUS_HIGH__UE_CNT_MASK 0x03800000L +#define RLC_UE_ERR_STATUS_HIGH__FED_CNT_MASK 0x1C000000L +#define RLC_UE_ERR_STATUS_HIGH__RESERVED_MASK 0xE0000000L +//RLC_DSM_CNTL +#define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3 +#define RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 +#define RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_DATA_SEL__SHIFT 0x6 +#define RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 +#define RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x9 +#define RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xb +#define RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc +#define RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe +#define RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0xf +#define RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 +#define RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_DATA_SEL__SHIFT 0x12 +#define RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 +#define RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_DATA_SEL__SHIFT 0x15 +#define RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x17 +#define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_DATA_SEL_MASK 0x00000003L +#define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L +#define RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00000018L +#define RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L +#define RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_DATA_SEL_MASK 0x000000C0L +#define RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L +#define RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00000600L +#define RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L +#define RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L +#define RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L +#define RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00018000L +#define RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L +#define RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_DATA_SEL_MASK 0x000C0000L +#define RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L +#define RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_DATA_SEL_MASK 0x00600000L +#define RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L +//RLC_DSM_CNTLA +#define RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3 +#define RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 +#define RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x6 +#define RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 +#define RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x9 +#define RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xb +#define RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00000003L +#define RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L +#define RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00000018L +#define RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L +#define RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x000000C0L +#define RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L +#define RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00000600L +#define RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L +//RLC_DSM_CNTL2 +#define RLC_DSM_CNTL2__RLCG_INSTR_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define RLC_DSM_CNTL2__RLCG_INSTR_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define RLC_DSM_CNTL2__RLCV_INSTR_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define RLC_DSM_CNTL2__RLCV_INSTR_RAM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0xb +#define RLC_DSM_CNTL2__RLC_TCTAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define RLC_DSM_CNTL2__RLC_TCTAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe +#define RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define RLC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define RLC_DSM_CNTL2__RLCG_INSTR_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define RLC_DSM_CNTL2__RLCG_INSTR_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define RLC_DSM_CNTL2__RLCV_INSTR_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define RLC_DSM_CNTL2__RLCV_INSTR_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define RLC_DSM_CNTL2__RLC_TCTAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define RLC_DSM_CNTL2__RLC_TCTAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define RLC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//RLC_DSM_CNTL2A +#define RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0xb +#define RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L +//RLC_CE_ERR_STATUS_LOW +#define RLC_CE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define RLC_CE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define RLC_CE_ERR_STATUS_LOW__ADDRESS__SHIFT 0x2 +#define RLC_CE_ERR_STATUS_LOW__MEMORY_ID__SHIFT 0x18 +#define RLC_CE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define RLC_CE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define RLC_CE_ERR_STATUS_LOW__ADDRESS_MASK 0x00FFFFFCL +#define RLC_CE_ERR_STATUS_LOW__MEMORY_ID_MASK 0xFF000000L +//RLC_CE_ERR_STATUS_HIGH +#define RLC_CE_ERR_STATUS_HIGH__ECC__SHIFT 0x0 +#define RLC_CE_ERR_STATUS_HIGH__OTHER__SHIFT 0x1 +#define RLC_CE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define RLC_CE_ERR_STATUS_HIGH__ERR_INFO__SHIFT 0x3 +#define RLC_CE_ERR_STATUS_HIGH__CE_CNT__SHIFT 0x17 +#define RLC_CE_ERR_STATUS_HIGH__POISON__SHIFT 0x1a +#define RLC_CE_ERR_STATUS_HIGH__RESERVED__SHIFT 0x1b +#define RLC_CE_ERR_STATUS_HIGH__ECC_MASK 0x00000001L +#define RLC_CE_ERR_STATUS_HIGH__OTHER_MASK 0x00000002L +#define RLC_CE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define RLC_CE_ERR_STATUS_HIGH__ERR_INFO_MASK 0x007FFFF8L +#define RLC_CE_ERR_STATUS_HIGH__CE_CNT_MASK 0x03800000L +#define RLC_CE_ERR_STATUS_HIGH__POISON_MASK 0x04000000L +#define RLC_CE_ERR_STATUS_HIGH__RESERVED_MASK 0xF8000000L +//RLC_RLCV_SPARE_INT +#define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0 +#define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1 +#define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L +#define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL +//RLC_SMU_CLK_REQ +#define RLC_SMU_CLK_REQ__VALID__SHIFT 0x0 +#define RLC_SMU_CLK_REQ__VALID_MASK 0x00000001L + + +// addressBlock: xcd0_gc_pwrdec +//CGTS_SM_CTRL_REG +#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0 +#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4 +#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc +#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10 +#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11 +#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14 +#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15 +#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18 +#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL +#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L +#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L +#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L +#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L +#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L +#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L +#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xFF000000L +//CGTS_RD_CTRL_REG +#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0 +#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8 +#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001FL +#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001F00L +//CGTS_RD_REG +#define CGTS_RD_REG__READ_DATA__SHIFT 0x0 +#define CGTS_RD_REG__READ_DATA_MASK 0x00003FFFL +//CGTS_TCC_DISABLE +#define CGTS_TCC_DISABLE__WRITE_DIS__SHIFT 0x0 +#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 +#define CGTS_TCC_DISABLE__WRITE_DIS_MASK 0x00000001L +#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L +//CGTS_USER_TCC_DISABLE +#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 +#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L +//CGTS_CU0_SP0_CTRL_REG +#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU0_LDS_SQ_CTRL_REG +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU0_TA_SQC_CTRL_REG +#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU0_SP1_CTRL_REG +#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU0_TD_TCP_CTRL_REG +#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU1_SP0_CTRL_REG +#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU1_LDS_SQ_CTRL_REG +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU1_TA_SQC_CTRL_REG +#define CGTS_CU1_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU1_SP1_CTRL_REG +#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU1_TD_TCP_CTRL_REG +#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU2_SP0_CTRL_REG +#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU2_LDS_SQ_CTRL_REG +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU2_TA_SQC_CTRL_REG +#define CGTS_CU2_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU2_SP1_CTRL_REG +#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU2_TD_TCP_CTRL_REG +#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU3_SP0_CTRL_REG +#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU3_LDS_SQ_CTRL_REG +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU3_TA_SQC_CTRL_REG +#define CGTS_CU3_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU3_SP1_CTRL_REG +#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU3_TD_TCP_CTRL_REG +#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU4_SP0_CTRL_REG +#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU4_LDS_SQ_CTRL_REG +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU4_TA_SQC_CTRL_REG +#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU4_SP1_CTRL_REG +#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU4_TD_TCP_CTRL_REG +#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU5_SP0_CTRL_REG +#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU5_LDS_SQ_CTRL_REG +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU5_TA_SQC_CTRL_REG +#define CGTS_CU5_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU5_SP1_CTRL_REG +#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU5_TD_TCP_CTRL_REG +#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU6_SP0_CTRL_REG +#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU6_LDS_SQ_CTRL_REG +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU6_TA_SQC_CTRL_REG +#define CGTS_CU6_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU6_SP1_CTRL_REG +#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU6_TD_TCP_CTRL_REG +#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU7_SP0_CTRL_REG +#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU7_LDS_SQ_CTRL_REG +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU7_TA_SQC_CTRL_REG +#define CGTS_CU7_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU7_SP1_CTRL_REG +#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU7_TD_TCP_CTRL_REG +#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU8_SP0_CTRL_REG +#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU8_LDS_SQ_CTRL_REG +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU8_TA_SQC_CTRL_REG +#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU8_SP1_CTRL_REG +#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU8_TD_TCP_CTRL_REG +#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU9_SP0_CTRL_REG +#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU9_LDS_SQ_CTRL_REG +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU9_TA_SQC_CTRL_REG +#define CGTS_CU9_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU9_SP1_CTRL_REG +#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU9_TD_TCP_CTRL_REG +#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU10_SP0_CTRL_REG +#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU10_LDS_SQ_CTRL_REG +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU10_TA_SQC_CTRL_REG +#define CGTS_CU10_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU10_SP1_CTRL_REG +#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU10_TD_TCP_CTRL_REG +#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU11_SP0_CTRL_REG +#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU11_LDS_SQ_CTRL_REG +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU11_TA_SQC_CTRL_REG +#define CGTS_CU11_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU11_SP1_CTRL_REG +#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU11_TD_TCP_CTRL_REG +#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU12_SP0_CTRL_REG +#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU12_LDS_SQ_CTRL_REG +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU12_TA_SQC_CTRL_REG +#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU12_SP1_CTRL_REG +#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU12_TD_TCP_CTRL_REG +#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU13_SP0_CTRL_REG +#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU13_LDS_SQ_CTRL_REG +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU13_TA_SQC_CTRL_REG +#define CGTS_CU13_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU13_SP1_CTRL_REG +#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU13_TD_TCP_CTRL_REG +#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU14_SP0_CTRL_REG +#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU14_LDS_SQ_CTRL_REG +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU14_TA_SQC_CTRL_REG +#define CGTS_CU14_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L +#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L +#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU14_SP1_CTRL_REG +#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU14_TD_TCP_CTRL_REG +#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU15_SP0_CTRL_REG +#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x0000007FL +#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L +#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x007F0000L +#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L +#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU15_LDS_SQ_CTRL_REG +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU15_TA_SQC_CTRL_REG +#define CGTS_CU15_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L +//CGTS_CU15_SP1_CTRL_REG +#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x0000007FL +#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L +#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x007F0000L +#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L +#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU15_TD_TCP_CTRL_REG +#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L +#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L +#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L +#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L +#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L +//CGTS_CU0_TCPI_CTRL_REG +#define CGTS_CU0_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU0_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU1_TCPI_CTRL_REG +#define CGTS_CU1_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU1_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU2_TCPI_CTRL_REG +#define CGTS_CU2_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU2_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU3_TCPI_CTRL_REG +#define CGTS_CU3_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU3_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU4_TCPI_CTRL_REG +#define CGTS_CU4_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU4_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU5_TCPI_CTRL_REG +#define CGTS_CU5_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU5_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU6_TCPI_CTRL_REG +#define CGTS_CU6_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU6_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU7_TCPI_CTRL_REG +#define CGTS_CU7_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU7_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU8_TCPI_CTRL_REG +#define CGTS_CU8_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU8_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU9_TCPI_CTRL_REG +#define CGTS_CU9_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU9_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU10_TCPI_CTRL_REG +#define CGTS_CU10_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU10_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU11_TCPI_CTRL_REG +#define CGTS_CU11_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU11_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU12_TCPI_CTRL_REG +#define CGTS_CU12_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU12_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU13_TCPI_CTRL_REG +#define CGTS_CU13_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU13_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU14_TCPI_CTRL_REG +#define CGTS_CU14_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU14_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTS_CU15_TCPI_CTRL_REG +#define CGTS_CU15_TCPI_CTRL_REG__TCPI__SHIFT 0x0 +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_TCPI_CTRL_REG__RESERVED__SHIFT 0xc +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L +#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L +#define CGTS_CU15_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L +//CGTT_SPI_PS_CLK_CTRL +#define CGTT_SPI_PS_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10 +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11 +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12 +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13 +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14 +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15 +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16 +#define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18 +#define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19 +#define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a +#define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b +#define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c +#define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d +#define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e +#define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_SPI_PS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L +#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L +#define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L +#define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L +#define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L +#define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L +#define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L +#define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L +#define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L +#define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_SPIS_CLK_CTRL +#define CGTT_SPIS_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10 +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11 +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12 +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13 +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14 +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15 +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16 +#define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18 +#define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19 +#define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a +#define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b +#define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c +#define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d +#define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e +#define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_SPIS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L +#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L +#define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L +#define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L +#define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L +#define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L +#define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L +#define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L +#define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L +#define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTX_SPI_DEBUG_CLK_CTRL +#define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x0 +#define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x6 +#define CGTX_SPI_DEBUG_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x7 +#define CGTX_SPI_DEBUG_CLK_CTRL__SPI_SH_CLK_CONTROL__SHIFT 0x8 +#define CGTX_SPI_DEBUG_CLK_CTRL__SPI_REPEATER_FGCG_OVERRIDE__SHIFT 0x9 +#define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x0000003FL +#define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x00000040L +#define CGTX_SPI_DEBUG_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x00000080L +#define CGTX_SPI_DEBUG_CLK_CTRL__SPI_SH_CLK_CONTROL_MASK 0x00000100L +#define CGTX_SPI_DEBUG_CLK_CTRL__SPI_REPEATER_FGCG_OVERRIDE_MASK 0x00000200L +//CGTT_SPI_CLK_CTRL +#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14 +#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15 +#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16 +#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c +#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d +#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e +#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L +#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L +#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L +#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L +#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L +#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L +#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_PC_CLK_CTRL +#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE__SHIFT 0x11 +#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 +#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 +#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT 0x19 +#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT 0x1a +#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b +#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c +#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d +#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e +#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE_MASK 0x00020000L +#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L +#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L +#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK 0x02000000L +#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK 0x04000000L +#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L +#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L +#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L +#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L +#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_BCI_CLK_CTRL +#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18 +#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19 +#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a +#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b +#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c +#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d +#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e +#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x0000F000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L +#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L +#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L +#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L +#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L +#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L +#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L +#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_VGT_CLK_CTRL +#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0xf +#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x10 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9__SHIFT 0x18 +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19 +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a +#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b +#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c +#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d +#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L +#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9_MASK 0x01000000L +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L +#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L +#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L +#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000L +#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_IA_CLK_CTRL +#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 +#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L +#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x04000000L +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_WD_CLK_CTRL +#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0xf +#define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x10 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19 +#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a +#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b +#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c +#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d +#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e +#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L +#define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L +#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L +#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L +#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L +#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L +#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L +#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_PA_CLK_CTRL +#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_PA_CLK_CTRL__DEBUG_BUS_EN__SHIFT 0x17 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_PA_CLK_CTRL__DEBUG_BUS_EN_MASK 0x00800000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L +#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L +//CGTT_SC_CLK_CTRL0 +#define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT 0x10 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x11 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x12 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x13 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x14 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x15 +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x16 +#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x17 +#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT 0x18 +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1a +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1b +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL +#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK 0x00010000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00020000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00040000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00080000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00100000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00200000L +#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00400000L +#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L +#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK 0x01000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x02000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x04000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x08000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x40000000L +#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L +//CGTT_SC_CLK_CTRL1 +#define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT 0x0 +#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x11 +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x12 +#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT 0x13 +#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT 0x14 +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x15 +#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x16 +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x1a +#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT 0x1b +#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL +#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L +#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK 0x00080000L +#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK 0x00100000L +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L +#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L +#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK 0x08000000L +#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK 0x40000000L +//CGTT_SC_CLK_CTRL2 +#define CGTT_SC_CLK_CTRL2__ON_DELAY__SHIFT 0x0 +#define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE__SHIFT 0x1b +#define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL +#define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE_MASK 0x08000000L +#define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE_MASK 0x40000000L +//CGTT_SQ_CLK_CTRL +#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d +#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L +#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_SQG_CLK_CTRL +#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c +#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L +#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//SQ_ALU_CLK_CTRL +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L +//SQ_TEX_CLK_CTRL +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L +//SQ_LDS_CLK_CTRL +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L +//SQ_POWER_THROTTLE +#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0 +#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10 +#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e +#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x00003FFFL +#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3FFF0000L +#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xC0000000L +//SQ_POWER_THROTTLE2 +#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0 +#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f +#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x00003FFFL +#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L +#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L +#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000L +//TD_CGTT_CTRL +#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0 +#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL +#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//TA_CGTT_CTRL +#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0 +#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL +#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_TCPI_CLK_CTRL +#define CGTT_TCPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_TCPI_CLK_CTRL__SPARE__SHIFT 0xc +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_TCPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_TCPI_CLK_CTRL__SPARE_MASK 0x0000F000L +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//TCX_CGTT_SCLK_CTRL +#define TCX_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TCX_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +//DB_CGTT_CLK_CTRL_0 +#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0 +#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4 +#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f +#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000FL +#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x0000F000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L +//CB_CGTT_SCLK_CTRL +#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//TCC_CGTT_SCLK_CTRL +#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//TCC_CGTT_SCLK_CTRL2 +#define TCC_CGTT_SCLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 +#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b +#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c +#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d +#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e +#define TCC_CGTT_SCLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L +#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L +#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L +#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L +#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L +//TCC_CGTT_SCLK_CTRL3 +#define TCC_CGTT_SCLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE18__SHIFT 0xc +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE17__SHIFT 0xd +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE16__SHIFT 0xe +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE15__SHIFT 0xf +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE14__SHIFT 0x10 +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE13__SHIFT 0x11 +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE12__SHIFT 0x12 +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE11__SHIFT 0x13 +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE10__SHIFT 0x14 +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE9__SHIFT 0x15 +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE8__SHIFT 0x17 +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18 +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e +#define TCC_CGTT_SCLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE18_MASK 0x00001000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE17_MASK 0x00002000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE16_MASK 0x00004000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE15_MASK 0x00008000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE14_MASK 0x00010000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE13_MASK 0x00020000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE12_MASK 0x00040000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE11_MASK 0x00080000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE10_MASK 0x00100000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE9_MASK 0x00200000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE8_MASK 0x00800000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE7_MASK 0x01000000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L +#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L +//TCA_CGTT_SCLK_CTRL +#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_CP_CLK_CTRL +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//CGTT_CPC_CLK_CTRL +#define CGTT_CPC_CLK_CTRL__REG_CLK_OFF_HYSTERESIS__SHIFT 0x0 +#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CPC_CLK_CTRL__REG_CLK_OFF_HYSTERESIS_MASK 0x0000000FL +#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//CGTT_RLC_CLK_CTRL +#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//RLC_GFX_RM_CNTL +#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT 0x0 +#define RLC_GFX_RM_CNTL__RESERVED__SHIFT 0x1 +#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK 0x00000001L +#define RLC_GFX_RM_CNTL__RESERVED_MASK 0xFFFFFFFEL +//RMI_CGTT_SCLK_CTRL +#define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 +#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//CGTT_TCPF_CLK_CTRL +#define CGTT_TCPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_TCPF_CLK_CTRL__SPARE__SHIFT 0xc +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_TCPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_TCPF_CLK_CTRL__SPARE_MASK 0x0000F000L +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L + + +// addressBlock: xcd0_gc_hypdec +//CP_HYP_PFP_UCODE_ADDR +#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL +//CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL +//CP_HYP_PFP_UCODE_DATA +#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_HYP_ME_UCODE_ADDR +#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK 0x00001FFFL +//CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0 +#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x00001FFFL +//CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0 +#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x00001FFFL +//CP_HYP_ME_UCODE_DATA +#define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0 +#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xFFFFFFFFL +//CP_CE_UCODE_ADDR +#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL +//CP_HYP_CE_UCODE_ADDR +#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL +//CP_CE_UCODE_DATA +#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_HYP_CE_UCODE_DATA +#define CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_HYP_MEC1_UCODE_ADDR +#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL +//CP_MEC_ME1_UCODE_ADDR +#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL +//CP_HYP_MEC1_UCODE_DATA +#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_MEC_ME1_UCODE_DATA +#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_HYP_MEC2_UCODE_ADDR +#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL +//CP_MEC_ME2_UCODE_ADDR +#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL +//CP_HYP_MEC2_UCODE_DATA +#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_MEC_ME2_UCODE_DATA +#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_HYP_PFP_UCODE_CHKSUM +#define CP_HYP_PFP_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 +#define CP_HYP_PFP_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL +//CP_HYP_CE_UCODE_CHKSUM +#define CP_HYP_CE_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 +#define CP_HYP_CE_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL +//CP_HYP_ME_UCODE_CHKSUM +#define CP_HYP_ME_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 +#define CP_HYP_ME_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL +//CP_HYP_MEC_ME1_UCODE_CHKSUM +#define CP_HYP_MEC_ME1_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 +#define CP_HYP_MEC_ME1_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL +//CP_HYP_MEC_ME2_UCODE_CHKSUM +#define CP_HYP_MEC_ME2_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 +#define CP_HYP_MEC_ME2_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL +//CP_HYP_XCP_CTL +#define CP_HYP_XCP_CTL__VIRTUAL_XCC_ID__SHIFT 0x0 +#define CP_HYP_XCP_CTL__NUM_XCC_IN_XCP__SHIFT 0x3 +#define CP_HYP_XCP_CTL__VIRTUAL_XCC_ID_MASK 0x00000007L +#define CP_HYP_XCP_CTL__NUM_XCC_IN_XCP_MASK 0x00000078L +//RLC_GPM_UCODE_ADDR +#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xe +#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL +#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xFFFFC000L +//RLC_GPM_UCODE_DATA +#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//GRBM_GFX_INDEX_SR_SELECT +#define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x0 +#define GRBM_GFX_INDEX_SR_SELECT__VF_PF__SHIFT 0x1f +#define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L +#define GRBM_GFX_INDEX_SR_SELECT__VF_PF_MASK 0x80000000L +//GRBM_GFX_INDEX_SR_DATA +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x0 +#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX__SHIFT 0x8 +#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x10 +#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e +#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x000000FFL +#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX_MASK 0x0000FF00L +#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x00FF0000L +#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES_MASK 0x20000000L +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L +#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L +//GRBM_GFX_CNTL_SR_SELECT +#define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x0 +#define GRBM_GFX_CNTL_SR_SELECT__VF_PF__SHIFT 0x1f +#define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L +#define GRBM_GFX_CNTL_SR_SELECT__VF_PF_MASK 0x80000000L +//GRBM_GFX_CNTL_SR_DATA +#define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x0 +#define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x2 +#define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x4 +#define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x8 +#define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L +#define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000CL +#define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000F0L +#define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L +//GRBM_MCM_ADDR +#define GRBM_MCM_ADDR__MCM_ADDR_IH__SHIFT 0x0 +#define GRBM_MCM_ADDR__MCM_ADDR_IH_MASK 0x000000FFL +//RLC_GPU_IOV_VF_ENABLE +#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10 +#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000FFFEL +#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xFFFF0000L +//RLC_GPU_IOV_CFG_REG6 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7 +#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa +#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007FL +#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L +#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L +#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xFFFFFC00L +//RLC_GPU_IOV_CFG_REG8 +#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_RLCV_TIMER_INT_0 +#define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT 0x0 +#define RLC_RLCV_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL +//RLC_RLCV_TIMER_CTRL +#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 +#define RLC_RLCV_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 +#define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT 0x2 +#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L +#define RLC_RLCV_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L +#define RLC_RLCV_TIMER_CTRL__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCV_TIMER_STAT +#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 +#define RLC_RLCV_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 +#define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT 0x2 +#define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 +#define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 +#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L +#define RLC_RLCV_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L +#define RLC_RLCV_TIMER_STAT__RESERVED_MASK 0x000000FCL +#define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L +#define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L +//RLC_GPU_IOV_VF_DOORBELL_STATUS +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x1f +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x0000FFFFL +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED_MASK 0x7FFF0000L +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L +//RLC_GPU_IOV_VF_DOORBELL_STATUS_SET +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x0 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x1f +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x0000FFFFL +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED_MASK 0x7FFF0000L +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L +//RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x0 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x1f +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x0000FFFFL +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED_MASK 0x7FFF0000L +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L +//RLC_GPU_IOV_VF_MASK +#define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x0 +#define RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x0000FFFFL +#define RLC_GPU_IOV_VF_MASK__RESERVED_MASK 0xFFFF0000L +//RLC_HYP_SEMAPHORE_0 +#define RLC_HYP_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_0__RESERVED__SHIFT 0x5 +#define RLC_HYP_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL +#define RLC_HYP_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L +//RLC_HYP_SEMAPHORE_1 +#define RLC_HYP_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_1__RESERVED__SHIFT 0x5 +#define RLC_HYP_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL +#define RLC_HYP_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L +//RLC_CLK_CNTL +#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x0 +#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x2 +#define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL__SHIFT 0x4 +#define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL__SHIFT 0x5 +#define RLC_CLK_CNTL__RLC_TC_CLK_CNTL__SHIFT 0x6 +#define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL__SHIFT 0x7 +#define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE__SHIFT 0x8 +#define RLC_CLK_CNTL__RLC_EDC_OVERRIDE__SHIFT 0x9 +#define RLC_CLK_CNTL__RESERVED_11_10__SHIFT 0xa +#define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE__SHIFT 0xc +#define RLC_CLK_CNTL__RLC_DFLL_CLK_CNTL__SHIFT 0xd +#define RLC_CLK_CNTL__DBGBUS_CLK_ACTIVE_OVERRIDE__SHIFT 0xe +#define RLC_CLK_CNTL__RLC_CAC2_CLK_CNTL__SHIFT 0xf +#define RLC_CLK_CNTL__RESERVED_1__SHIFT 0x11 +#define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE__SHIFT 0x12 +#define RLC_CLK_CNTL__RESERVED__SHIFT 0x13 +#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x00000003L +#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x0000000CL +#define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL_MASK 0x00000010L +#define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL_MASK 0x00000020L +#define RLC_CLK_CNTL__RLC_TC_CLK_CNTL_MASK 0x00000040L +#define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL_MASK 0x00000080L +#define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK 0x00000100L +#define RLC_CLK_CNTL__RLC_EDC_OVERRIDE_MASK 0x00000200L +#define RLC_CLK_CNTL__RESERVED_11_10_MASK 0x00000C00L +#define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE_MASK 0x00001000L +#define RLC_CLK_CNTL__RLC_DFLL_CLK_CNTL_MASK 0x00002000L +#define RLC_CLK_CNTL__DBGBUS_CLK_ACTIVE_OVERRIDE_MASK 0x00004000L +#define RLC_CLK_CNTL__RLC_CAC2_CLK_CNTL_MASK 0x00018000L +#define RLC_CLK_CNTL__RESERVED_1_MASK 0x00020000L +#define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE_MASK 0x00040000L +#define RLC_CLK_CNTL__RESERVED_MASK 0xFFF80000L +//RLC_GPU_IOV_SCH_BLOCK +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x4 +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x8 +#define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000FL +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000F0L +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x00007F00L +#define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0x7FFF0000L +//RLC_GPU_IOV_CFG_REG1 +#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4 +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 +#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6 +#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8 +#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10 +#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18 +#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000FL +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L +#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000C0L +#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x0000FF00L +#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00FF0000L +#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xFF000000L +//RLC_GPU_IOV_CFG_REG2 +#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4 +#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0x0000000FL +#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xFFFFFFF0L +//RLC_GPU_IOV_VM_BUSY_STATUS +#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCH_0 +#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_ACTIVE_FCN_ID +#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f +#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL +#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L +//RLC_GPU_IOV_SCH_3 +#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCH_1 +#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCH_2 +#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_INT_STAT +#define RLC_GPU_IOV_INT_STAT__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_INT_STAT__STATUS_MASK 0xFFFFFFFFL +//RLC_RLCV_TIMER_INT_1 +#define RLC_RLCV_TIMER_INT_1__TIMER__SHIFT 0x0 +#define RLC_RLCV_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_UCODE_ADDR +#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc +#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL +#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L +//RLC_GPU_IOV_UCODE_DATA +#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCRATCH_ADDR +#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0 +#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9 +#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x000001FFL +#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L +//RLC_GPU_IOV_SCRATCH_DATA +#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_F32_CNTL +#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0 +#define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x00000001L +#define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPU_IOV_F32_RESET +#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0 +#define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x00000001L +#define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPU_IOV_SDMA0_STATUS +#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8 +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9 +#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd +#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x00000001L +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0x000000FEL +#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x00000100L +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0x00000E00L +#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x00001000L +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xFFFFE000L +//RLC_GPU_IOV_SDMA1_STATUS +#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8 +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9 +#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd +#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x00000001L +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0x000000FEL +#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x00000100L +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0x00000E00L +#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x00001000L +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xFFFFE000L +//RLC_GPU_IOV_SMU_RESPONSE +#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0 +#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_VIRT_RESET_REQ +#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 +#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f +#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0x0000FFFFL +#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7FFF0000L +#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000L +//RLC_GPU_IOV_RLC_RESPONSE +#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0 +#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_INT_DISABLE +#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0 +#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_INT_FORCE +#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0 +#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA0_BUSY_STATUS +#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA1_BUSY_STATUS +#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_HYP_SEMAPHORE_2 +#define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT 0x5 +#define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL +#define RLC_HYP_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L +//RLC_HYP_SEMAPHORE_3 +#define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT 0x5 +#define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL +#define RLC_HYP_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L +//RLC_GPU_IOV_SDMA2_STATUS +#define RLC_GPU_IOV_SDMA2_STATUS__PREEMPTED__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA2_STATUS__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_SDMA2_STATUS__SAVED__SHIFT 0x8 +#define RLC_GPU_IOV_SDMA2_STATUS__RESERVED1__SHIFT 0x9 +#define RLC_GPU_IOV_SDMA2_STATUS__RESTORED__SHIFT 0xc +#define RLC_GPU_IOV_SDMA2_STATUS__RESERVED2__SHIFT 0xd +#define RLC_GPU_IOV_SDMA2_STATUS__PREEMPTED_MASK 0x00000001L +#define RLC_GPU_IOV_SDMA2_STATUS__RESERVED_MASK 0x000000FEL +#define RLC_GPU_IOV_SDMA2_STATUS__SAVED_MASK 0x00000100L +#define RLC_GPU_IOV_SDMA2_STATUS__RESERVED1_MASK 0x00000E00L +#define RLC_GPU_IOV_SDMA2_STATUS__RESTORED_MASK 0x00001000L +#define RLC_GPU_IOV_SDMA2_STATUS__RESERVED2_MASK 0xFFFFE000L +//RLC_GPU_IOV_SDMA3_STATUS +#define RLC_GPU_IOV_SDMA3_STATUS__PREEMPTED__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA3_STATUS__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_SDMA3_STATUS__SAVED__SHIFT 0x8 +#define RLC_GPU_IOV_SDMA3_STATUS__RESERVED1__SHIFT 0x9 +#define RLC_GPU_IOV_SDMA3_STATUS__RESTORED__SHIFT 0xc +#define RLC_GPU_IOV_SDMA3_STATUS__RESERVED2__SHIFT 0xd +#define RLC_GPU_IOV_SDMA3_STATUS__PREEMPTED_MASK 0x00000001L +#define RLC_GPU_IOV_SDMA3_STATUS__RESERVED_MASK 0x000000FEL +#define RLC_GPU_IOV_SDMA3_STATUS__SAVED_MASK 0x00000100L +#define RLC_GPU_IOV_SDMA3_STATUS__RESERVED1_MASK 0x00000E00L +#define RLC_GPU_IOV_SDMA3_STATUS__RESTORED_MASK 0x00001000L +#define RLC_GPU_IOV_SDMA3_STATUS__RESERVED2_MASK 0xFFFFE000L +//RLC_GPU_IOV_SDMA4_STATUS +#define RLC_GPU_IOV_SDMA4_STATUS__PREEMPTED__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA4_STATUS__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_SDMA4_STATUS__SAVED__SHIFT 0x8 +#define RLC_GPU_IOV_SDMA4_STATUS__RESERVED1__SHIFT 0x9 +#define RLC_GPU_IOV_SDMA4_STATUS__RESTORED__SHIFT 0xc +#define RLC_GPU_IOV_SDMA4_STATUS__RESERVED2__SHIFT 0xd +#define RLC_GPU_IOV_SDMA4_STATUS__PREEMPTED_MASK 0x00000001L +#define RLC_GPU_IOV_SDMA4_STATUS__RESERVED_MASK 0x000000FEL +#define RLC_GPU_IOV_SDMA4_STATUS__SAVED_MASK 0x00000100L +#define RLC_GPU_IOV_SDMA4_STATUS__RESERVED1_MASK 0x00000E00L +#define RLC_GPU_IOV_SDMA4_STATUS__RESTORED_MASK 0x00001000L +#define RLC_GPU_IOV_SDMA4_STATUS__RESERVED2_MASK 0xFFFFE000L +//RLC_GPU_IOV_SDMA5_STATUS +#define RLC_GPU_IOV_SDMA5_STATUS__PREEMPTED__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA5_STATUS__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_SDMA5_STATUS__SAVED__SHIFT 0x8 +#define RLC_GPU_IOV_SDMA5_STATUS__RESERVED1__SHIFT 0x9 +#define RLC_GPU_IOV_SDMA5_STATUS__RESTORED__SHIFT 0xc +#define RLC_GPU_IOV_SDMA5_STATUS__RESERVED2__SHIFT 0xd +#define RLC_GPU_IOV_SDMA5_STATUS__PREEMPTED_MASK 0x00000001L +#define RLC_GPU_IOV_SDMA5_STATUS__RESERVED_MASK 0x000000FEL +#define RLC_GPU_IOV_SDMA5_STATUS__SAVED_MASK 0x00000100L +#define RLC_GPU_IOV_SDMA5_STATUS__RESERVED1_MASK 0x00000E00L +#define RLC_GPU_IOV_SDMA5_STATUS__RESTORED_MASK 0x00001000L +#define RLC_GPU_IOV_SDMA5_STATUS__RESERVED2_MASK 0xFFFFE000L +//RLC_GPU_IOV_SDMA6_STATUS +#define RLC_GPU_IOV_SDMA6_STATUS__PREEMPTED__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA6_STATUS__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_SDMA6_STATUS__SAVED__SHIFT 0x8 +#define RLC_GPU_IOV_SDMA6_STATUS__RESERVED1__SHIFT 0x9 +#define RLC_GPU_IOV_SDMA6_STATUS__RESTORED__SHIFT 0xc +#define RLC_GPU_IOV_SDMA6_STATUS__RESERVED2__SHIFT 0xd +#define RLC_GPU_IOV_SDMA6_STATUS__PREEMPTED_MASK 0x00000001L +#define RLC_GPU_IOV_SDMA6_STATUS__RESERVED_MASK 0x000000FEL +#define RLC_GPU_IOV_SDMA6_STATUS__SAVED_MASK 0x00000100L +#define RLC_GPU_IOV_SDMA6_STATUS__RESERVED1_MASK 0x00000E00L +#define RLC_GPU_IOV_SDMA6_STATUS__RESTORED_MASK 0x00001000L +#define RLC_GPU_IOV_SDMA6_STATUS__RESERVED2_MASK 0xFFFFE000L +//RLC_GPU_IOV_SDMA7_STATUS +#define RLC_GPU_IOV_SDMA7_STATUS__PREEMPTED__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA7_STATUS__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_SDMA7_STATUS__SAVED__SHIFT 0x8 +#define RLC_GPU_IOV_SDMA7_STATUS__RESERVED1__SHIFT 0x9 +#define RLC_GPU_IOV_SDMA7_STATUS__RESTORED__SHIFT 0xc +#define RLC_GPU_IOV_SDMA7_STATUS__RESERVED2__SHIFT 0xd +#define RLC_GPU_IOV_SDMA7_STATUS__PREEMPTED_MASK 0x00000001L +#define RLC_GPU_IOV_SDMA7_STATUS__RESERVED_MASK 0x000000FEL +#define RLC_GPU_IOV_SDMA7_STATUS__SAVED_MASK 0x00000100L +#define RLC_GPU_IOV_SDMA7_STATUS__RESERVED1_MASK 0x00000E00L +#define RLC_GPU_IOV_SDMA7_STATUS__RESTORED_MASK 0x00001000L +#define RLC_GPU_IOV_SDMA7_STATUS__RESERVED2_MASK 0xFFFFE000L +//RLC_GPU_IOV_SDMA2_BUSY_STATUS +#define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA3_BUSY_STATUS +#define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA4_BUSY_STATUS +#define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA5_BUSY_STATUS +#define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA6_BUSY_STATUS +#define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA7_BUSY_STATUS +#define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL + + +// addressBlock: xcd0_gc_utcl2_vmsharedhvdec +//MC_VM_FB_SIZE_OFFSET_VF0 +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF1 +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF2 +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF3 +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF4 +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF5 +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF6 +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF7 +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF8 +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF9 +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF10 +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF11 +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF12 +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF13 +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF14 +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L +//MC_VM_FB_SIZE_OFFSET_VF15 +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L +//VM_IOMMU_MMIO_CNTRL_1 +#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 +#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L +//MC_VM_MARC_BASE_LO_0 +#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L +//MC_VM_MARC_BASE_LO_1 +#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L +//MC_VM_MARC_BASE_LO_2 +#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L +//MC_VM_MARC_BASE_LO_3 +#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L +//MC_VM_MARC_BASE_HI_0 +#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL +//MC_VM_MARC_BASE_HI_1 +#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL +//MC_VM_MARC_BASE_HI_2 +#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL +//MC_VM_MARC_BASE_HI_3 +#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL +//MC_VM_MARC_RELOC_LO_0 +#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L +#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L +#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L +//MC_VM_MARC_RELOC_LO_1 +#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L +#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L +#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L +//MC_VM_MARC_RELOC_LO_2 +#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L +#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L +#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L +//MC_VM_MARC_RELOC_LO_3 +#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L +#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L +#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L +//MC_VM_MARC_RELOC_HI_0 +#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL +//MC_VM_MARC_RELOC_HI_1 +#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL +//MC_VM_MARC_RELOC_HI_2 +#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL +//MC_VM_MARC_RELOC_HI_3 +#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL +//MC_VM_MARC_LEN_LO_0 +#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L +//MC_VM_MARC_LEN_LO_1 +#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L +//MC_VM_MARC_LEN_LO_2 +#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L +//MC_VM_MARC_LEN_LO_3 +#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L +//MC_VM_MARC_LEN_HI_0 +#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL +//MC_VM_MARC_LEN_HI_1 +#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL +//MC_VM_MARC_LEN_HI_2 +#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL +//MC_VM_MARC_LEN_HI_3 +#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL +//VM_IOMMU_CONTROL_REGISTER +#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 +#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L +//VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER +#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd +#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L +//VM_PCIE_ATS_CNTL +#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 +#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L +#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_0 +#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_1 +#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_2 +#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_3 +#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_4 +#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_5 +#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_6 +#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_7 +#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_8 +#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_9 +#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_10 +#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_11 +#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_12 +#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_13 +#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_14 +#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L +//VM_PCIE_ATS_CNTL_VF_15 +#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f +#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L +//MC_SHARED_ACTIVE_FCN_ID +#define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//MC_VM_XGMI_GPUIOV_ENABLE +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT 0x0 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT 0x1 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT 0x2 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT 0x3 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT 0x4 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT 0x5 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT 0x6 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT 0x7 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT 0x8 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT 0x9 +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT 0xa +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT 0xb +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT 0xc +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT 0xd +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT 0xe +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT 0xf +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT 0x1f +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK 0x00000001L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK 0x00000002L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK 0x00000004L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK 0x00000008L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK 0x00000010L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK 0x00000020L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK 0x00000040L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK 0x00000080L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK 0x00000100L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK 0x00000200L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK 0x00000400L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK 0x00000800L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK 0x00001000L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK 0x00002000L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK 0x00004000L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK 0x00008000L +#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK 0x80000000L + + +// addressBlock: xcd0_gc_pspdec +//CPG_PSP_DEBUG +#define CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT 0x0 +#define CPG_PSP_DEBUG__VMID_VIOLATION_CNTL__SHIFT 0x2 +#define CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK 0x00000003L +#define CPG_PSP_DEBUG__VMID_VIOLATION_CNTL_MASK 0x00000004L +//CPC_PSP_DEBUG +#define CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT 0x0 +#define CPC_PSP_DEBUG__VMID_VIOLATION_CNTL__SHIFT 0x2 +#define CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE__SHIFT 0x3 +#define CPC_PSP_DEBUG__CPC_DC_FIX_DISABLE__SHIFT 0x4 +#define CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK 0x00000003L +#define CPC_PSP_DEBUG__VMID_VIOLATION_CNTL_MASK 0x00000004L +#define CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK 0x00000008L +#define CPC_PSP_DEBUG__CPC_DC_FIX_DISABLE_MASK 0x00000010L +//CP_PSP_XCP_CTL +#define CP_PSP_XCP_CTL__PHYSICAL_XCC_ID__SHIFT 0x0 +#define CP_PSP_XCP_CTL__XCC_DIE_ID__SHIFT 0x3 +#define CP_PSP_XCP_CTL__PHYSICAL_XCC_ID_MASK 0x00000007L +#define CP_PSP_XCP_CTL__XCC_DIE_ID_MASK 0x00000038L +//GRBM_SEC_CNTL +#define GRBM_SEC_CNTL__DEBUG_ENABLE__SHIFT 0x0 +#define GRBM_SEC_CNTL__DEBUG_ENABLE_MASK 0x00000001L +//GRBM_IOV_ERROR_FIFO_DATA +#define GRBM_IOV_ERROR_FIFO_DATA__IOV_ADDR__SHIFT 0x0 +#define GRBM_IOV_ERROR_FIFO_DATA__IOV_VFID__SHIFT 0x12 +#define GRBM_IOV_ERROR_FIFO_DATA__IOV_SSRCID__SHIFT 0x18 +#define GRBM_IOV_ERROR_FIFO_DATA__IOV_OP__SHIFT 0x1c +#define GRBM_IOV_ERROR_FIFO_DATA__IOV_VF__SHIFT 0x1d +#define GRBM_IOV_ERROR_FIFO_DATA__IOV_OVERFLOW__SHIFT 0x1e +#define GRBM_IOV_ERROR_FIFO_DATA__IOV_READ_VALID__SHIFT 0x1f +#define GRBM_IOV_ERROR_FIFO_DATA__IOV_ADDR_MASK 0x0003FFFFL +#define GRBM_IOV_ERROR_FIFO_DATA__IOV_VFID_MASK 0x00FC0000L +#define GRBM_IOV_ERROR_FIFO_DATA__IOV_SSRCID_MASK 0x0F000000L +#define GRBM_IOV_ERROR_FIFO_DATA__IOV_OP_MASK 0x10000000L +#define GRBM_IOV_ERROR_FIFO_DATA__IOV_VF_MASK 0x20000000L +#define GRBM_IOV_ERROR_FIFO_DATA__IOV_OVERFLOW_MASK 0x40000000L +#define GRBM_IOV_ERROR_FIFO_DATA__IOV_READ_VALID_MASK 0x80000000L +//GRBM_DSM_BYPASS +#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0 +#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2 +#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L +#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L +//GRBM_CAM_INDEX +#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 +#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L +//GRBM_HYP_CAM_INDEX +#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0 +#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x00000007L +//GRBM_CAM_DATA +#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 +#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 +#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL +#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L +//GRBM_HYP_CAM_DATA +#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0 +#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 +#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL +#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L +//RLC_FWL_FIRST_VIOL_ADDR +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_STATUS__SHIFT 0x0 +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP__SHIFT 0x1 +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR__SHIFT 0x2 +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_APERTURE_ID__SHIFT 0x14 +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_STATUS_MASK 0x00000001L +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP_MASK 0x00000002L +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR_MASK 0x000FFFFCL +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_APERTURE_ID_MASK 0xFFF00000L + + +// addressBlock: sqind +//SQ_DEBUG_STS_LOCAL +#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0 +#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4 +#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L +#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003F0L +//SQ_DEBUG_CTRL_LOCAL +#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0 +#define SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_NON_WAVE__SHIFT 0x8 +#define SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_MOPS_NON_WAVE__SHIFT 0x9 +#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0x000000FFL +#define SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_NON_WAVE_MASK 0x00000100L +#define SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_MOPS_NON_WAVE_MASK 0x00000200L +//SQ_WAVE_VALID_AND_IDLE +#define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT__SHIFT 0x0 +#define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT_MASK 0xFFFFFFFFL +//SQ_PERF_SNAPSHOT_DATA +//SQ_PERF_SNAPSHOT_DATA1 +//SQ_PERF_SNAPSHOT_PC_LO +//SQ_PERF_SNAPSHOT_PC_HI +//SQ_WAVE_MODE +#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0 +#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4 +#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8 +#define SQ_WAVE_MODE__IEEE__SHIFT 0x9 +#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa +#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0xb +#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc +#define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x17 +#define SQ_WAVE_MODE__POPS_PACKER0__SHIFT 0x18 +#define SQ_WAVE_MODE__POPS_PACKER1__SHIFT 0x19 +#define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x1a +#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b +#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c +#define SQ_WAVE_MODE__CSP__SHIFT 0x1d +#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000FL +#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000F0L +#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L +#define SQ_WAVE_MODE__IEEE_MASK 0x00000200L +#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L +#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x00000800L +#define SQ_WAVE_MODE__EXCP_EN_MASK 0x001FF000L +#define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L +#define SQ_WAVE_MODE__POPS_PACKER0_MASK 0x01000000L +#define SQ_WAVE_MODE__POPS_PACKER1_MASK 0x02000000L +#define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x04000000L +#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x08000000L +#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L +#define SQ_WAVE_MODE__CSP_MASK 0xE0000000L +//SQ_WAVE_STATUS +#define SQ_WAVE_STATUS__SCC__SHIFT 0x0 +#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1 +#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3 +#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5 +#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6 +#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7 +#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8 +#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9 +#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa +#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb +#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc +#define SQ_WAVE_STATUS__HALT__SHIFT 0xd +#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe +#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf +#define SQ_WAVE_STATUS__VALID__SHIFT 0x10 +#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11 +#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12 +#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13 +#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14 +#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x15 +#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16 +#define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x17 +#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b +#define SQ_WAVE_STATUS__SCRATCH_EN__SHIFT 0x1c +#define SQ_WAVE_STATUS__IDLE__SHIFT 0x1f +#define SQ_WAVE_STATUS__SCC_MASK 0x00000001L +#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L +#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x00000018L +#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L +#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L +#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L +#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L +#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L +#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L +#define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L +#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L +#define SQ_WAVE_STATUS__HALT_MASK 0x00002000L +#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L +#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x00008000L +#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L +#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L +#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L +#define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L +#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x00100000L +#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x00200000L +#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x00400000L +#define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L +#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L +#define SQ_WAVE_STATUS__SCRATCH_EN_MASK 0x10000000L +#define SQ_WAVE_STATUS__IDLE_MASK 0x80000000L +//SQ_WAVE_TRAPSTS +#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0 +#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa +#define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT 0xb +#define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT 0xc +#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10 +#define SQ_WAVE_TRAPSTS__HOST_TRAP__SHIFT 0x16 +#define SQ_WAVE_TRAPSTS__WAVE_END__SHIFT 0x18 +#define SQ_WAVE_TRAPSTS__TRAP_AFTER_INST__SHIFT 0x19 +#define SQ_WAVE_TRAPSTS__PERF_SNAPSHOT__SHIFT 0x1a +#define SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT 0x1c +#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d +#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x000001FFL +#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x00000400L +#define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK 0x00000800L +#define SQ_WAVE_TRAPSTS__EXCP_HI_MASK 0x00007000L +#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x003F0000L +#define SQ_WAVE_TRAPSTS__HOST_TRAP_MASK 0x00400000L +#define SQ_WAVE_TRAPSTS__WAVE_END_MASK 0x01000000L +#define SQ_WAVE_TRAPSTS__TRAP_AFTER_INST_MASK 0x02000000L +#define SQ_WAVE_TRAPSTS__PERF_SNAPSHOT_MASK 0x04000000L +#define SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK 0x10000000L +#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xE0000000L +//SQ_WAVE_HW_ID +#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0 +#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4 +#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6 +#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8 +#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc +#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd +#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10 +#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14 +#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18 +#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b +#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e +#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0x0000000FL +#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x00000030L +#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0x000000C0L +#define SQ_WAVE_HW_ID__CU_ID_MASK 0x00000F00L +#define SQ_WAVE_HW_ID__SH_ID_MASK 0x00001000L +#define SQ_WAVE_HW_ID__SE_ID_MASK 0x0000E000L +#define SQ_WAVE_HW_ID__TG_ID_MASK 0x000F0000L +#define SQ_WAVE_HW_ID__VM_ID_MASK 0x00F00000L +#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x07000000L +#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000L +#define SQ_WAVE_HW_ID__ME_ID_MASK 0xC0000000L +//SQ_WAVE_GPR_ALLOC +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0 +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x6 +#define SQ_WAVE_GPR_ALLOC__ACCV_OFFSET__SHIFT 0xc +#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x12 +#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18 +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x0000003FL +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x00000FC0L +#define SQ_WAVE_GPR_ALLOC__ACCV_OFFSET_MASK 0x0003F000L +#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x00FC0000L +#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0F000000L +//SQ_WAVE_LDS_ALLOC +#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0 +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc +#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000000FFL +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001FF000L +//SQ_WAVE_IB_STS +#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0 +#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4 +#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8 +#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc +#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf +#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10 +#define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT 0x16 +#define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000FL +#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L +#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00000F00L +#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x00007000L +#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x00008000L +#define SQ_WAVE_IB_STS__RCNT_MASK 0x001F0000L +#define SQ_WAVE_IB_STS__VM_CNT_HI_MASK 0x00C00000L +//SQ_WAVE_PC_LO +#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0 +#define SQ_WAVE_PC_LO__PC_LO_MASK 0xFFFFFFFFL +//SQ_WAVE_PC_HI +#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0 +#define SQ_WAVE_PC_HI__PC_HI_MASK 0x0000FFFFL +//SQ_WAVE_INST_DW0 +#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0 +#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xFFFFFFFFL +//SQ_WAVE_INST_DW1 +#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0 +#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xFFFFFFFFL +//SQ_WAVE_IB_DBG0 +#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0 +#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3 +#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4 +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5 +#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8 +#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa +#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10 +#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18 +#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a +#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b +#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d +#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI__SHIFT 0x1f +#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x00000007L +#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x00000008L +#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x00000010L +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0x000000E0L +#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x00000300L +#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0x00000C00L +#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x000F0000L +#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x03000000L +#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x04000000L +#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000L +#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000L +#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000L +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI_MASK 0x80000000L +//SQ_WAVE_IB_DBG1 +#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0 +#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1 +#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2 +#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4 +#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0xb +#define SQ_WAVE_IB_DBG1__RCNT__SHIFT 0x12 +#define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x19 +#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x00000001L +#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x00000002L +#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x00000004L +#define SQ_WAVE_IB_DBG1__XCNT_MASK 0x000001F0L +#define SQ_WAVE_IB_DBG1__QCNT_MASK 0x0000F800L +#define SQ_WAVE_IB_DBG1__RCNT_MASK 0x007C0000L +#define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xFE000000L +//SQ_WAVE_FLUSH_IB +#define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x0 +#define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP0 +#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP0__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP1 +#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP1__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP2 +#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP2__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP3 +#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP3__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP4 +#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP4__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP5 +#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP5__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP6 +#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP6__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP7 +#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP7__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP8 +#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP8__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP9 +#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP9__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP10 +#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP10__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP11 +#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP11__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP12 +#define SQ_WAVE_TTMP12__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP12__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP13 +#define SQ_WAVE_TTMP13__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP13__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP14 +#define SQ_WAVE_TTMP14__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP14__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP15 +#define SQ_WAVE_TTMP15__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP15__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_M0 +#define SQ_WAVE_M0__M0__SHIFT 0x0 +#define SQ_WAVE_M0__M0_MASK 0xFFFFFFFFL +//SQ_WAVE_EXEC_LO +#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0 +#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xFFFFFFFFL +//SQ_WAVE_EXEC_HI +#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0 +#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xFFFFFFFFL +//SQ_INTERRUPT_WORD_AUTO_CTXID +#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0x0 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 0x1 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 0x2 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 0x3 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 0x4 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 0x5 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 0x6 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 0x7 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 0x8 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 0x18 +#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 0x1a +#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x0000001L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x0000002L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x0000004L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x0000008L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x0000010L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x0000020L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x0000040L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x0000080L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x0000100L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x3000000L +#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0xC000000L +//SQ_INTERRUPT_WORD_AUTO_HI +#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID__SHIFT 0x8 +#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT 0xa +#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID_MASK 0x300L +#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING_MASK 0xC00L +//SQ_INTERRUPT_WORD_AUTO_LO +#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE__SHIFT 0x0 +#define SQ_INTERRUPT_WORD_AUTO_LO__WLT__SHIFT 0x1 +#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL__SHIFT 0x2 +#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP__SHIFT 0x3 +#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP__SHIFT 0x4 +#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW__SHIFT 0x5 +#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW__SHIFT 0x6 +#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW__SHIFT 0x7 +#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR__SHIFT 0x8 +#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_MASK 0x001L +#define SQ_INTERRUPT_WORD_AUTO_LO__WLT_MASK 0x002L +#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL_MASK 0x004L +#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP_MASK 0x008L +#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP_MASK 0x010L +#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW_MASK 0x020L +#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW_MASK 0x040L +#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW_MASK 0x080L +#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR_MASK 0x100L +//SQ_INTERRUPT_WORD_CMN_CTXID +#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID__SHIFT 0x18 +#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING__SHIFT 0x1a +#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID_MASK 0x3000000L +#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING_MASK 0xC000000L +//SQ_INTERRUPT_WORD_CMN_HI +#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID__SHIFT 0x8 +#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT 0xa +#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID_MASK 0x300L +#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING_MASK 0xC00L +//SQ_INTERRUPT_WORD_WAVE_CTXID +#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0x0 +#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 0xc +#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 0xd +#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 0xe +#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 0x12 +#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 0x14 +#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 0x18 +#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 0x1a +#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x0000FFFL +#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x0001000L +#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x0002000L +#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x003C000L +#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x00C0000L +#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x0F00000L +#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x3000000L +#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0xC000000L +//SQ_INTERRUPT_WORD_WAVE_HI +#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID__SHIFT 0x0 +#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID__SHIFT 0x4 +#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID__SHIFT 0x8 +#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT 0xa +#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID_MASK 0x00FL +#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID_MASK 0x0F0L +#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID_MASK 0x300L +#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING_MASK 0xC00L +//SQ_INTERRUPT_WORD_WAVE_LO +#define SQ_INTERRUPT_WORD_WAVE_LO__DATA__SHIFT 0x0 +#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID__SHIFT 0x18 +#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV__SHIFT 0x19 +#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID__SHIFT 0x1a +#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID__SHIFT 0x1e +#define SQ_INTERRUPT_WORD_WAVE_LO__DATA_MASK 0x00FFFFFFL +#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID_MASK 0x01000000L +#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV_MASK 0x02000000L +#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID_MASK 0x3C000000L +#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID_MASK 0xC0000000L + + + +#endif diff --git a/extra/amdpci/headers/nbio_7_9_0_offset.h b/extra/amdpci/headers/nbio_7_9_0_offset.h new file mode 100644 index 0000000000..c8a15c8f48 --- /dev/null +++ b/extra/amdpci/headers/nbio_7_9_0_offset.h @@ -0,0 +1,10004 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _nbio_7_9_0_OFFSET_HEADER +#define _nbio_7_9_0_OFFSET_HEADER + + + +// addressBlock: aid_nbio_nbif0_bif_bx_SYSDEC +// base address: 0x0 +#define regBIF_BX0_PCIE_INDEX 0x000c +#define regBIF_BX0_PCIE_INDEX_BASE_IDX 0 +#define regBIF_BX0_PCIE_DATA 0x000d +#define regBIF_BX0_PCIE_DATA_BASE_IDX 0 +#define regBIF_BX0_PCIE_INDEX2 0x000e +#define regBIF_BX0_PCIE_INDEX2_BASE_IDX 0 +#define regBIF_BX0_PCIE_DATA2 0x000f +#define regBIF_BX0_PCIE_DATA2_BASE_IDX 0 +#define regBIF_BX0_PCIE_INDEX_HI 0x0010 +#define regBIF_BX0_PCIE_INDEX_HI_BASE_IDX 0 +#define regBIF_BX0_PCIE_INDEX2_HI 0x0011 +#define regBIF_BX0_PCIE_INDEX2_HI_BASE_IDX 0 +#define regBIF_BX0_SBIOS_SCRATCH_0 0x0034 +#define regBIF_BX0_SBIOS_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_1 0x0035 +#define regBIF_BX0_SBIOS_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_2 0x0036 +#define regBIF_BX0_SBIOS_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_3 0x0037 +#define regBIF_BX0_SBIOS_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_0 0x0038 +#define regBIF_BX0_BIOS_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_1 0x0039 +#define regBIF_BX0_BIOS_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_2 0x003a +#define regBIF_BX0_BIOS_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_3 0x003b +#define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_4 0x003c +#define regBIF_BX0_BIOS_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_5 0x003d +#define regBIF_BX0_BIOS_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_6 0x003e +#define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_7 0x003f +#define regBIF_BX0_BIOS_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_8 0x0040 +#define regBIF_BX0_BIOS_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_9 0x0041 +#define regBIF_BX0_BIOS_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_10 0x0042 +#define regBIF_BX0_BIOS_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_11 0x0043 +#define regBIF_BX0_BIOS_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_12 0x0044 +#define regBIF_BX0_BIOS_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_13 0x0045 +#define regBIF_BX0_BIOS_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_14 0x0046 +#define regBIF_BX0_BIOS_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_15 0x0047 +#define regBIF_BX0_BIOS_SCRATCH_15_BASE_IDX 1 +#define regBIF_BX0_BIF_RLC_INTR_CNTL 0x004c +#define regBIF_BX0_BIF_RLC_INTR_CNTL_BASE_IDX 1 +#define regBIF_BX0_BIF_VCE_INTR_CNTL 0x004d +#define regBIF_BX0_BIF_VCE_INTR_CNTL_BASE_IDX 1 +#define regBIF_BX0_BIF_UVD_INTR_CNTL 0x004e +#define regBIF_BX0_BIF_UVD_INTR_CNTL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0 0x006c +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 0x006d +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1 0x006e +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 0x006f +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2 0x0070 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 0x0071 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3 0x0072 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 0x0073 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4 0x0074 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 0x0075 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5 0x0076 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 0x0077 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6 0x0078 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 0x0079 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7 0x007a +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 0x007b +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_CNTL 0x007c +#define regBIF_BX0_GFX_MMIOREG_CAM_CNTL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL 0x007d +#define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL 0x007e +#define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f +#define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_0 0x0080 +#define regBIF_BX0_DRIVER_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_1 0x0081 +#define regBIF_BX0_DRIVER_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_2 0x0082 +#define regBIF_BX0_DRIVER_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_3 0x0083 +#define regBIF_BX0_DRIVER_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_4 0x0084 +#define regBIF_BX0_DRIVER_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_5 0x0085 +#define regBIF_BX0_DRIVER_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_6 0x0086 +#define regBIF_BX0_DRIVER_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_7 0x0087 +#define regBIF_BX0_DRIVER_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_8 0x0088 +#define regBIF_BX0_DRIVER_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_9 0x0089 +#define regBIF_BX0_DRIVER_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_10 0x008a +#define regBIF_BX0_DRIVER_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_11 0x008b +#define regBIF_BX0_DRIVER_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_12 0x008c +#define regBIF_BX0_DRIVER_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_13 0x008d +#define regBIF_BX0_DRIVER_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_14 0x008e +#define regBIF_BX0_DRIVER_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_15 0x008f +#define regBIF_BX0_DRIVER_SCRATCH_15_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_0 0x0090 +#define regBIF_BX0_FW_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_1 0x0091 +#define regBIF_BX0_FW_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_2 0x0092 +#define regBIF_BX0_FW_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_3 0x0093 +#define regBIF_BX0_FW_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_4 0x0094 +#define regBIF_BX0_FW_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_5 0x0095 +#define regBIF_BX0_FW_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_6 0x0096 +#define regBIF_BX0_FW_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_7 0x0097 +#define regBIF_BX0_FW_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_8 0x0098 +#define regBIF_BX0_FW_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_9 0x0099 +#define regBIF_BX0_FW_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_10 0x009a +#define regBIF_BX0_FW_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_11 0x009b +#define regBIF_BX0_FW_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_12 0x009c +#define regBIF_BX0_FW_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_13 0x009d +#define regBIF_BX0_FW_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_14 0x009e +#define regBIF_BX0_FW_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_15 0x009f +#define regBIF_BX0_FW_SCRATCH_15_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_4 0x00a0 +#define regBIF_BX0_SBIOS_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_5 0x00a1 +#define regBIF_BX0_SBIOS_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_6 0x00a2 +#define regBIF_BX0_SBIOS_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_7 0x00a3 +#define regBIF_BX0_SBIOS_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_8 0x00a4 +#define regBIF_BX0_SBIOS_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_9 0x00a5 +#define regBIF_BX0_SBIOS_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_10 0x00a6 +#define regBIF_BX0_SBIOS_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_11 0x00a7 +#define regBIF_BX0_SBIOS_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_12 0x00a8 +#define regBIF_BX0_SBIOS_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_13 0x00a9 +#define regBIF_BX0_SBIOS_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_14 0x00aa +#define regBIF_BX0_SBIOS_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_15 0x00ab +#define regBIF_BX0_SBIOS_SCRATCH_15_BASE_IDX 1 + + +// addressBlock: aid_nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED 0x0060 +#define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH 0x0061 +#define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_CNTL 0x0063 +#define regRCC_DWN_DEV0_0_DN_PCIE_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL 0x0064 +#define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 0x0065 +#define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL 0x0066 +#define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL 0x0067 +#define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 0x0068 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC 0x0069 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 0x006a +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL 0x006c +#define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL 0x006d +#define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL 0x006e +#define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2 0x006f +#define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC 0x0070 +#define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP 0x0071 +#define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_ep_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH 0x0040 +#define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_CNTL 0x0042 +#define regRCC_EP_DEV0_0_EP_PCIE_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL 0x0043 +#define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS 0x0044 +#define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 0x0045 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL 0x0046 +#define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL 0x0047 +#define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x0049 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x004a +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x004a +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x004a +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x004a +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x004b +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x004b +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x004b +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x004b +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC 0x004c +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 0x004d +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP 0x004f +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0050 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL 0x0050 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0050 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0051 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0051 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0051 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0051 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0052 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0052 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0052 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL 0x0052 +#define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED 0x0053 +#define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL 0x0055 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID 0x0056 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL 0x0057 +#define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL 0x0058 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL 0x0059 +#define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_pf_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_PF0_MM_INDEX 0x0000 +#define regBIF_BX_PF0_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_PF0_MM_DATA 0x0001 +#define regBIF_BX_PF0_MM_DATA_BASE_IDX 0 +#define regBIF_BX_PF0_MM_INDEX_HI 0x0006 +#define regBIF_BX_PF0_MM_INDEX_HI_BASE_IDX 0 +#define regBIF_BX_PF0_RSMU_INDEX 0x0000 +#define regBIF_BX_PF0_RSMU_INDEX_BASE_IDX 1 +#define regBIF_BX_PF0_RSMU_DATA 0x0001 +#define regBIF_BX_PF0_RSMU_DATA_BASE_IDX 1 +#define regBIF_BX_PF0_RSMU_INDEX_HI 0x0002 +#define regBIF_BX_PF0_RSMU_INDEX_HI_BASE_IDX 1 + + +// addressBlock: aid_nbio_nbif0_bif_bx_BIFDEC1 +// base address: 0x0 +#define regBIF_BX0_CC_BIF_BX_STRAP0 0x00e2 +#define regBIF_BX0_CC_BIF_BX_STRAP0_BASE_IDX 2 +#define regBIF_BX0_CC_BIF_BX_PINSTRAP0 0x00e4 +#define regBIF_BX0_CC_BIF_BX_PINSTRAP0_BASE_IDX 2 +#define regBIF_BX0_BIF_MM_INDACCESS_CNTL 0x00e6 +#define regBIF_BX0_BIF_MM_INDACCESS_CNTL_BASE_IDX 2 +#define regBIF_BX0_BUS_CNTL 0x00e7 +#define regBIF_BX0_BUS_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_SCRATCH0 0x00e8 +#define regBIF_BX0_BIF_SCRATCH0_BASE_IDX 2 +#define regBIF_BX0_BIF_SCRATCH1 0x00e9 +#define regBIF_BX0_BIF_SCRATCH1_BASE_IDX 2 +#define regBIF_BX0_BX_RESET_EN 0x00ed +#define regBIF_BX0_BX_RESET_EN_BASE_IDX 2 +#define regBIF_BX0_MM_CFGREGS_CNTL 0x00ee +#define regBIF_BX0_MM_CFGREGS_CNTL_BASE_IDX 2 +#define regBIF_BX0_BX_RESET_CNTL 0x00f0 +#define regBIF_BX0_BX_RESET_CNTL_BASE_IDX 2 +#define regBIF_BX0_INTERRUPT_CNTL 0x00f1 +#define regBIF_BX0_INTERRUPT_CNTL_BASE_IDX 2 +#define regBIF_BX0_INTERRUPT_CNTL2 0x00f2 +#define regBIF_BX0_INTERRUPT_CNTL2_BASE_IDX 2 +#define regBIF_BX0_CLKREQB_PAD_CNTL 0x00f8 +#define regBIF_BX0_CLKREQB_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_FEATURES_CONTROL_MISC 0x00fb +#define regBIF_BX0_BIF_FEATURES_CONTROL_MISC_BASE_IDX 2 +#define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC 0x00fc +#define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 2 +#define regBIF_BX0_BIF_DOORBELL_CNTL 0x00fd +#define regBIF_BX0_BIF_DOORBELL_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_DOORBELL_INT_CNTL 0x00fe +#define regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_FB_EN 0x0100 +#define regBIF_BX0_BIF_FB_EN_BASE_IDX 2 +#define regBIF_BX0_BIF_INTR_CNTL 0x0101 +#define regBIF_BX0_BIF_INTR_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_MST_TRANS_PENDING_VF 0x0109 +#define regBIF_BX0_BIF_MST_TRANS_PENDING_VF_BASE_IDX 2 +#define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF 0x010a +#define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 2 +#define regBIF_BX0_BACO_CNTL 0x010b +#define regBIF_BX0_BACO_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIME0 0x010c +#define regBIF_BX0_BIF_BACO_EXIT_TIME0_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER1 0x010d +#define regBIF_BX0_BIF_BACO_EXIT_TIMER1_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER2 0x010e +#define regBIF_BX0_BIF_BACO_EXIT_TIMER2_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER3 0x010f +#define regBIF_BX0_BIF_BACO_EXIT_TIMER3_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER4 0x0110 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER4_BASE_IDX 2 +#define regBIF_BX0_MEM_TYPE_CNTL 0x0111 +#define regBIF_BX0_MEM_TYPE_CNTL_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL 0x0113 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_0 0x0114 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_0_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_1 0x0115 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_1_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_2 0x0116 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_2_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_3 0x0117 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_3_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_4 0x0118 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_4_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_5 0x0119 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_5_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_6 0x011a +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_6_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_7 0x011b +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_7_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_8 0x011c +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_8_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_9 0x011d +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_9_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_10 0x011e +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_10_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_11 0x011f +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_11_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_12 0x0120 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_12_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_13 0x0121 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_13_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_14 0x0122 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_14_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_15 0x0123 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_15_BASE_IDX 2 +#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL 0x012d +#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL 0x012e +#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_CNTL 0x012f +#define regBIF_BX0_BIF_RB_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_BASE 0x0130 +#define regBIF_BX0_BIF_RB_BASE_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_RPTR 0x0131 +#define regBIF_BX0_BIF_RB_RPTR_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_WPTR 0x0132 +#define regBIF_BX0_BIF_RB_WPTR_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_HI 0x0133 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_HI_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_LO 0x0134 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_LO_BASE_IDX 2 +#define regBIF_BX0_MAILBOX_INDEX 0x0135 +#define regBIF_BX0_MAILBOX_INDEX_BASE_IDX 2 +#define regBIF_BX0_BIF_MP1_INTR_CTRL 0x0142 +#define regBIF_BX0_BIF_MP1_INTR_CTRL_BASE_IDX 2 +#define regBIF_BX0_BIF_PERSTB_PAD_CNTL 0x0146 +#define regBIF_BX0_BIF_PERSTB_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_PX_EN_PAD_CNTL 0x0147 +#define regBIF_BX0_BIF_PX_EN_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL 0x0148 +#define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_CLKREQB_PAD_CNTL 0x0149 +#define regBIF_BX0_BIF_CLKREQB_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_PWRBRK_PAD_CNTL 0x014a +#define regBIF_BX0_BIF_PWRBRK_PAD_CNTL_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_DEV0_0_RCC_ERR_INT_CNTL 0x0086 +#define regRCC_DEV0_0_RCC_ERR_INT_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BACO_CNTL_MISC 0x0087 +#define regRCC_DEV0_0_RCC_BACO_CNTL_MISC_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_RESET_EN 0x0088 +#define regRCC_DEV0_0_RCC_RESET_EN_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_VDM_SUPPORT 0x0089 +#define regRCC_DEV0_0_RCC_VDM_SUPPORT_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 0x008a +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 0x008b +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_GPUIOV_REGION 0x008c +#define regRCC_DEV0_0_RCC_GPUIOV_REGION_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN 0x008d +#define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL 0x008e +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x008f +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE 0x008f +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE0 0x00be +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE1 0x00bf +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUS_CNTL 0x00c1 +#define regRCC_DEV0_0_RCC_BUS_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_CNTL 0x00c2 +#define regRCC_DEV0_0_RCC_CONFIG_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_F0_BASE 0x00c6 +#define regRCC_DEV0_0_RCC_CONFIG_F0_BASE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE 0x00c7 +#define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE 0x00c8 +#define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_XDMA_LO 0x00c9 +#define regRCC_DEV0_0_RCC_XDMA_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_XDMA_HI 0x00ca +#define regRCC_DEV0_0_RCC_XDMA_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC 0x00cb +#define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL1 0x00cc +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_LIST0 0x00cd +#define regRCC_DEV0_0_RCC_BUSNUM_LIST0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_LIST1 0x00ce +#define regRCC_DEV0_0_RCC_BUSNUM_LIST1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL2 0x00cf +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL2_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM 0x00d0 +#define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_HOST_BUSNUM 0x00d1 +#define regRCC_DEV0_0_RCC_HOST_BUSNUM_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI 0x00d2 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO 0x00d3 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI 0x00d4 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO 0x00d5 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI 0x00d6 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO 0x00d7 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI 0x00d8 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO 0x00d9 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0 0x00da +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1 0x00db +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL 0x00dd +#define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CMN_LINK_CNTL 0x00de +#define regRCC_DEV0_0_RCC_CMN_LINK_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE 0x00df +#define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL 0x00e0 +#define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_MH_ARB_CNTL 0x00e1 +#define regRCC_DEV0_0_RCC_MH_ARB_CNTL_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_rcc_strap_BIFDEC1 +// base address: 0x0 +#define regRCC_STRAP0_RCC_BIF_STRAP0 0x0000 +#define regRCC_STRAP0_RCC_BIF_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP1 0x0001 +#define regRCC_STRAP0_RCC_BIF_STRAP1_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP2 0x0002 +#define regRCC_STRAP0_RCC_BIF_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP3 0x0003 +#define regRCC_STRAP0_RCC_BIF_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP4 0x0004 +#define regRCC_STRAP0_RCC_BIF_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP5 0x0005 +#define regRCC_STRAP0_RCC_BIF_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP6 0x0006 +#define regRCC_STRAP0_RCC_BIF_STRAP6_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0 0x0007 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1 0x0008 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10 0x0009 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11 0x000a +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12 0x000b +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13 0x000c +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14 0x000d +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2 0x000e +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3 0x000f +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4 0x0010 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5 0x0011 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6 0x0012 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7 0x0013 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8 0x0014 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9 0x0015 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0 0x0016 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1 0x0017 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13 0x0018 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14 0x0019 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15 0x001a +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16 0x001b +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17 0x001c +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18 0x001d +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2 0x001e +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26 0x001f +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3 0x0020 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4 0x0021 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5 0x0022 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8 0x0024 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9 0x0025 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0 0x0026 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2 0x0032 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20 0x0033 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21 0x0034 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22 0x0035 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23 0x0036 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24 0x0037 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25 0x0038 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3 0x0039 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4 0x003a +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5 0x003b +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6 0x003c +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7 0x003d +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_PF0_BIF_BME_STATUS 0x00eb +#define regBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_PF0_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_CONTROL 0x013e +#define regBIF_BX_PF0_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_PF0_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_PF0_BIF_VMHV_MAILBOX_BASE_IDX 2 +#define regBIF_BX_PF0_PARTITION_COMPUTE_CAP 0x0161 +#define regBIF_BX_PF0_PARTITION_COMPUTE_CAP_BASE_IDX 2 +#define regBIF_BX_PF0_PARTITION_MEM_CAP 0x0162 +#define regBIF_BX_PF0_PARTITION_MEM_CAP_BASE_IDX 2 +#define regBIF_BX_PF0_PARTITION_COMPUTE_STATUS 0x0163 +#define regBIF_BX_PF0_PARTITION_COMPUTE_STATUS_BASE_IDX 2 +#define regBIF_BX_PF0_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_PF0_PARTITION_MEM_STATUS_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] +// base address: 0x3480 +#define regRCC_DEV0_EPF0_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_gdc_GDCDEC +// base address: 0x0 +#define regGDC0_A2S_CNTL_CL0 0x0000 +#define regGDC0_A2S_CNTL_CL0_BASE_IDX 3 +#define regGDC0_A2S_CNTL_CL1 0x0001 +#define regGDC0_A2S_CNTL_CL1_BASE_IDX 3 +#define regGDC0_A2S_CNTL3_CL0 0x0018 +#define regGDC0_A2S_CNTL3_CL0_BASE_IDX 3 +#define regGDC0_A2S_CNTL3_CL1 0x0019 +#define regGDC0_A2S_CNTL3_CL1_BASE_IDX 3 +#define regGDC0_A2S_CNTL_SW0 0x0030 +#define regGDC0_A2S_CNTL_SW0_BASE_IDX 3 +#define regGDC0_A2S_CNTL_SW1 0x0031 +#define regGDC0_A2S_CNTL_SW1_BASE_IDX 3 +#define regGDC0_A2S_CNTL_SW2 0x0032 +#define regGDC0_A2S_CNTL_SW2_BASE_IDX 3 +#define regGDC0_A2S_TAG_ALLOC_0 0x003d +#define regGDC0_A2S_TAG_ALLOC_0_BASE_IDX 3 +#define regGDC0_A2S_TAG_ALLOC_1 0x003e +#define regGDC0_A2S_TAG_ALLOC_1_BASE_IDX 3 +#define regGDC0_A2S_MISC_CNTL 0x0041 +#define regGDC0_A2S_MISC_CNTL_BASE_IDX 3 +#define regGDC0_SHUB_REGS_IF_CTL 0x0043 +#define regGDC0_SHUB_REGS_IF_CTL_BASE_IDX 3 +#define regGDC0_NGDC_MGCG_CTRL 0x004a +#define regGDC0_NGDC_MGCG_CTRL_BASE_IDX 3 +#define regGDC0_NGDC_RESERVED_0 0x004b +#define regGDC0_NGDC_RESERVED_0_BASE_IDX 3 +#define regGDC0_NGDC_RESERVED_1 0x004c +#define regGDC0_NGDC_RESERVED_1_BASE_IDX 3 +#define regGDC0_NBIF_GFX_DOORBELL_STATUS 0x004f +#define regGDC0_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 3 +#define regGDC0_ATDMA_MISC_CNTL 0x005d +#define regGDC0_ATDMA_MISC_CNTL_BASE_IDX 3 +#define regGDC0_S2A_MISC_CNTL 0x005f +#define regGDC0_S2A_MISC_CNTL_BASE_IDX 3 +#define regGDC0_NGDC_PG_MISC_CTRL 0x0078 +#define regGDC0_NGDC_PG_MISC_CTRL_BASE_IDX 3 +#define regGDC0_NGDC_PGMST_CTRL 0x0079 +#define regGDC0_NGDC_PGMST_CTRL_BASE_IDX 3 +#define regGDC0_NGDC_PGSLV_CTRL 0x007a +#define regGDC0_NGDC_PGSLV_CTRL_BASE_IDX 3 + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 0x0274 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL 0x02b6 +#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 +#define cfgPCIE_PAGE_REQ_CNTL 0x02c4 +#define cfgPCIE_PAGE_REQ_STATUS 0x02c6 +#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 +#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST 0x02d0 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP 0x02d4 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL 0x02d6 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST 0x02f0 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CAP 0x02f4 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL 0x02f6 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0 0x02f8 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1 0x02fc +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0 0x0300 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1 0x0304 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0 0x0308 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1 0x030c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST 0x0320 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x0324 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL 0x032e +#define cfgPCIE_SRIOV_ENH_CAP_LIST 0x0330 +#define cfgPCIE_SRIOV_CAP 0x0334 +#define cfgPCIE_SRIOV_CONTROL 0x0338 +#define cfgPCIE_SRIOV_STATUS 0x033a +#define cfgPCIE_SRIOV_INITIAL_VFS 0x033c +#define cfgPCIE_SRIOV_TOTAL_VFS 0x033e +#define cfgPCIE_SRIOV_NUM_VFS 0x0340 +#define cfgPCIE_SRIOV_FUNC_DEP_LINK 0x0342 +#define cfgPCIE_SRIOV_FIRST_VF_OFFSET 0x0344 +#define cfgPCIE_SRIOV_VF_STRIDE 0x0346 +#define cfgPCIE_SRIOV_VF_DEVICE_ID 0x034a +#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c +#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_0 0x0354 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_1 0x0358 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_2 0x035c +#define cfgPCIE_SRIOV_VF_BASE_ADDR_3 0x0360 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_4 0x0364 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_5 0x0368 +#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP 0x0404 +#define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS 0x0408 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_16GT 0x0414 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT 0x0418 +#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT 0x041c +#define cfgBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 +#define cfgBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 +#define cfgBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 +#define cfgBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 +#define cfgBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 +#define cfgBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 +#define cfgBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 +#define cfgBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 +#define cfgBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 +#define cfgBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 +#define cfgBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 +#define cfgBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 +#define cfgBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 +#define cfgBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a +#define cfgBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b +#define cfgBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c +#define cfgBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d +#define cfgBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e +#define cfgBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST 0x0450 +#define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP 0x0454 +#define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS 0x0456 +#define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL 0x0458 +#define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS 0x045a +#define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL 0x045c +#define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS 0x045e +#define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL 0x0460 +#define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS 0x0462 +#define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL 0x0464 +#define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS 0x0466 +#define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL 0x0468 +#define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS 0x046a +#define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL 0x046c +#define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS 0x046e +#define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL 0x0470 +#define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS 0x0472 +#define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL 0x0474 +#define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS 0x0476 +#define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL 0x0478 +#define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS 0x047a +#define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL 0x047c +#define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS 0x047e +#define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL 0x0480 +#define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS 0x0482 +#define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL 0x0484 +#define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS 0x0486 +#define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL 0x0488 +#define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS 0x048a +#define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL 0x048c +#define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS 0x048e +#define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL 0x0490 +#define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS 0x0492 +#define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL 0x0494 +#define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS 0x0496 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_32GT 0x0504 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT 0x0508 +#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT 0x050c +#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0700 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0704 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0708 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x070c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0710 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0714 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0718 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x071c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0720 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0724 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0728 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x0730 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x0734 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0738 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x073c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0740 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x0744 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0748 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x074c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0750 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x0754 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0758 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x075c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0760 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x0764 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0768 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x076c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0770 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x0774 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x0778 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x077c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x0780 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x0784 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x0788 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x078c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x0790 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x0794 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x0798 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x079c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x07a0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x07a4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x07a8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x07ac +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x07b0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x07c0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 0x07c4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 0x07c8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 0x07cc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 0x07d0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0 0x07f0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1 0x07f4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2 0x07f8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3 0x07fc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4 0x0800 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5 0x0804 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6 0x0808 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7 0x080c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8 0x0810 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0x0820 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0x0824 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0x0828 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0x082c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0x0830 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0x0834 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0x0838 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0x083c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0x0840 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0 0x0850 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1 0x0854 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2 0x0858 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3 0x085c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4 0x0860 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5 0x0864 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6 0x0868 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7 0x086c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8 0x0870 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0 0x0880 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1 0x0884 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2 0x0888 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3 0x088c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4 0x0890 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5 0x0894 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6 0x0898 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7 0x089c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8 0x08a0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0 0x08b0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1 0x08b4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2 0x08b8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3 0x08bc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4 0x08c0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5 0x08c4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6 0x08c8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7 0x08cc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8 0x08d0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0 0x08e0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1 0x08e4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2 0x08e8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3 0x08ec +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4 0x08f0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5 0x08f4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6 0x08f8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7 0x08fc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8 0x0900 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0 0x0910 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1 0x0914 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2 0x0918 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3 0x091c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4 0x0920 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5 0x0924 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6 0x0928 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7 0x092c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8 0x0930 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0 0x0940 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1 0x0944 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2 0x0948 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3 0x094c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4 0x0950 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5 0x0954 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6 0x0958 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7 0x095c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8 0x0960 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0 0x0970 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1 0x0974 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2 0x0978 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3 0x097c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4 0x0980 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5 0x0984 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6 0x0988 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7 0x098c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8 0x0990 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0 0x09a0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1 0x09a4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2 0x09a8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3 0x09ac +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4 0x09b0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5 0x09b4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6 0x09b8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7 0x09bc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8 0x09c0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0 0x09d0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1 0x09d4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2 0x09d8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3 0x09dc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4 0x09e0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5 0x09e4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6 0x09e8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7 0x09ec +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8 0x09f0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0 0x0a00 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1 0x0a04 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2 0x0a08 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3 0x0a0c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4 0x0a10 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5 0x0a14 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6 0x0a18 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7 0x0a1c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8 0x0a20 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0 0x0a30 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1 0x0a34 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2 0x0a38 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3 0x0a3c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4 0x0a40 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5 0x0a44 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6 0x0a48 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7 0x0a4c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8 0x0a50 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0 0x0a60 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1 0x0a64 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2 0x0a68 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3 0x0a6c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4 0x0a70 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5 0x0a74 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6 0x0a78 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7 0x0a7c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8 0x0a80 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0 0x0a90 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1 0x0a94 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2 0x0a98 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3 0x0a9c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4 0x0aa0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5 0x0aa4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6 0x0aa8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7 0x0aac +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8 0x0ab0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0 0x0ac0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1 0x0ac4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2 0x0ac8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3 0x0acc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4 0x0ad0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5 0x0ad4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6 0x0ad8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7 0x0adc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8 0x0ae0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0 0x0af0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1 0x0af4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2 0x0af8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3 0x0afc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4 0x0b00 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5 0x0b04 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6 0x0b08 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7 0x0b0c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8 0x0b10 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0 0x0b20 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1 0x0b24 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2 0x0b28 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3 0x0b2c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4 0x0b30 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5 0x0b34 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6 0x0b38 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7 0x0b3c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8 0x0b40 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0 0x0b50 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1 0x0b54 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2 0x0b58 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3 0x0b5c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4 0x0b60 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5 0x0b64 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6 0x0b68 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7 0x0b6c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8 0x0b70 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0 0x0b80 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1 0x0b84 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2 0x0b88 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3 0x0b8c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4 0x0b90 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5 0x0b94 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6 0x0b98 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7 0x0b9c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8 0x0ba0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE 0x0c00 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE 0x0c04 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE 0x0c08 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE 0x0c0c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS 0x0c10 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS 0x0c14 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS 0x0c18 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS 0x0c1c + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF1_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF1_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST 0x02d0 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP 0x02d4 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL 0x02d6 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +// base address: 0x10100000 +#define regBIF_CFG_DEV0_RC0_VENDOR_ID 0x0000 +#define regBIF_CFG_DEV0_RC0_VENDOR_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DEVICE_ID 0x0000 +#define regBIF_CFG_DEV0_RC0_DEVICE_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_COMMAND 0x0001 +#define regBIF_CFG_DEV0_RC0_COMMAND_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_STATUS 0x0001 +#define regBIF_CFG_DEV0_RC0_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_REVISION_ID 0x0002 +#define regBIF_CFG_DEV0_RC0_REVISION_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PROG_INTERFACE 0x0002 +#define regBIF_CFG_DEV0_RC0_PROG_INTERFACE_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SUB_CLASS 0x0002 +#define regBIF_CFG_DEV0_RC0_SUB_CLASS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_BASE_CLASS 0x0002 +#define regBIF_CFG_DEV0_RC0_BASE_CLASS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_CACHE_LINE 0x0003 +#define regBIF_CFG_DEV0_RC0_CACHE_LINE_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LATENCY 0x0003 +#define regBIF_CFG_DEV0_RC0_LATENCY_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_HEADER 0x0003 +#define regBIF_CFG_DEV0_RC0_HEADER_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_BIST 0x0003 +#define regBIF_CFG_DEV0_RC0_BIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_BASE_ADDR_1 0x0004 +#define regBIF_CFG_DEV0_RC0_BASE_ADDR_1_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_BASE_ADDR_2 0x0005 +#define regBIF_CFG_DEV0_RC0_BASE_ADDR_2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY 0x0006 +#define regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT 0x0007 +#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SECONDARY_STATUS 0x0007 +#define regBIF_CFG_DEV0_RC0_SECONDARY_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT 0x0008 +#define regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT 0x0009 +#define regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER 0x000a +#define regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER 0x000b +#define regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI 0x000c +#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_CAP_PTR 0x000d +#define regBIF_CFG_DEV0_RC0_CAP_PTR_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR 0x000e +#define regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_INTERRUPT_LINE 0x000f +#define regBIF_CFG_DEV0_RC0_INTERRUPT_LINE_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_INTERRUPT_PIN 0x000f +#define regBIF_CFG_DEV0_RC0_INTERRUPT_PIN_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL 0x000f +#define regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL 0x0010 +#define regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PMI_CAP_LIST 0x0014 +#define regBIF_CFG_DEV0_RC0_PMI_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PMI_CAP 0x0014 +#define regBIF_CFG_DEV0_RC0_PMI_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL 0x0015 +#define regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST 0x0016 +#define regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_CAP 0x0016 +#define regBIF_CFG_DEV0_RC0_PCIE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DEVICE_CAP 0x0017 +#define regBIF_CFG_DEV0_RC0_DEVICE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL 0x0018 +#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS 0x0018 +#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CAP 0x0019 +#define regBIF_CFG_DEV0_RC0_LINK_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL 0x001a +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS 0x001a +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SLOT_CAP 0x001b +#define regBIF_CFG_DEV0_RC0_SLOT_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SLOT_CNTL 0x001c +#define regBIF_CFG_DEV0_RC0_SLOT_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SLOT_STATUS 0x001c +#define regBIF_CFG_DEV0_RC0_SLOT_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_ROOT_CNTL 0x001d +#define regBIF_CFG_DEV0_RC0_ROOT_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_ROOT_CAP 0x001d +#define regBIF_CFG_DEV0_RC0_ROOT_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_ROOT_STATUS 0x001e +#define regBIF_CFG_DEV0_RC0_ROOT_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DEVICE_CAP2 0x001f +#define regBIF_CFG_DEV0_RC0_DEVICE_CAP2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL2 0x0020 +#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS2 0x0020 +#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CAP2 0x0021 +#define regBIF_CFG_DEV0_RC0_LINK_CAP2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL2 0x0022 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS2 0x0022 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SLOT_CAP2 0x0023 +#define regBIF_CFG_DEV0_RC0_SLOT_CAP2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SLOT_CNTL2 0x0024 +#define regBIF_CFG_DEV0_RC0_SLOT_CNTL2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SLOT_STATUS2 0x0024 +#define regBIF_CFG_DEV0_RC0_SLOT_STATUS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_CAP_LIST 0x0028 +#define regBIF_CFG_DEV0_RC0_MSI_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL 0x0028 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO 0x0029 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI 0x002a +#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA 0x002a +#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA 0x002a +#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 0x002b +#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64 0x002b +#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SSID_CAP_LIST 0x0030 +#define regBIF_CFG_DEV0_RC0_SSID_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SSID_CAP 0x0031 +#define regBIF_CFG_DEV0_RC0_SSID_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0040 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR 0x0041 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 0x0042 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 0x0043 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST 0x0044 +#define regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 0x0045 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 0x0046 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL 0x0047 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS 0x0047 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP 0x0048 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL 0x0049 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS 0x004a +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP 0x004b +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL 0x004c +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS 0x004d +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0050 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 0x0051 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 0x0052 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0054 +#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS 0x0055 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK 0x0056 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY 0x0057 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS 0x0058 +#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK 0x0059 +#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL 0x005a +#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 0x005b +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 0x005c +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 0x005d +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 0x005e +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD 0x005f +#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS 0x0060 +#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID 0x0061 +#define regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 0x0062 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 0x0063 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 0x0064 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 0x0065 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0x009c +#define regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 0x009d +#define regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS 0x009e +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0x009f +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0x009f +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0x00a0 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0x00a0 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0x00a1 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0x00a1 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0x00a2 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0x00a2 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0x00a3 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0x00a3 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0x00a4 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0x00a4 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0x00a5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0x00a5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0x00a6 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0x00a6 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST 0x00a8 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP 0x00a9 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL 0x00a9 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST 0x0100 +#define regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP 0x0101 +#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS 0x0102 +#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0104 +#define regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CAP_16GT 0x0105 +#define regBIF_CFG_DEV0_RC0_LINK_CAP_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT 0x0106 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT 0x0107 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0108 +#define regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0109 +#define regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x010a +#define regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT 0x010c +#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT 0x010c +#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT 0x010c +#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT 0x010c +#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT 0x010d +#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT 0x010d +#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT 0x010d +#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT 0x010d +#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT 0x010e +#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT 0x010e +#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT 0x010e +#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT 0x010e +#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT 0x010f +#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT 0x010f +#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT 0x010f +#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT 0x010f +#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST 0x0114 +#define regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP 0x0115 +#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS 0x0115 +#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL 0x0116 +#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS 0x0116 +#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL 0x0117 +#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS 0x0117 +#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL 0x0118 +#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS 0x0118 +#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL 0x0119 +#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS 0x0119 +#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL 0x011a +#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS 0x011a +#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL 0x011b +#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS 0x011b +#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL 0x011c +#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS 0x011c +#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL 0x011d +#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS 0x011d +#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL 0x011e +#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS 0x011e +#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL 0x011f +#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS 0x011f +#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL 0x0120 +#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS 0x0120 +#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL 0x0121 +#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS 0x0121 +#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL 0x0122 +#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS 0x0122 +#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL 0x0123 +#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS 0x0123 +#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL 0x0124 +#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS 0x0124 +#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL 0x0125 +#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS 0x0125 +#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CAP_32GT 0x0141 +#define regBIF_CFG_DEV0_RC0_LINK_CAP_32GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_32GT 0x0142 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_32GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_32GT 0x0143 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_32GT_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_0_VENDOR_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_0_COMMAND_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_0_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_0_REVISION_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_0_SUB_CLASS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_0_BASE_CLASS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_0_CACHE_LINE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_0_LATENCY_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_0_HEADER_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_0_BIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_0_CAP_PTR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_0_MIN_GRANT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0x10012 +#define regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0x10013 +#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0x10014 +#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP 0x10014 +#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0x10015 +#define regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_PBA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x10044 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x10045 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x10046 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0x10047 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0x10047 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x10048 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x10049 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x1004a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x1004b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x1004c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x1004d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x10050 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0x10051 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0x10052 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10054 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x10055 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0x10056 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x10057 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0x10058 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0x10059 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x1005a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0x1005b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0x1005c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0x1005d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0x1005e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x10062 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x10063 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x10064 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x10065 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x10080 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0x10081 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0x10082 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0x10083 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0x10084 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0x10085 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0x10086 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0x10087 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0x10088 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0x10089 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0x1008a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0x1008b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0x1008c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10090 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x10091 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0x10092 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0x10093 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x10094 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0x10095 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x10096 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0x10097 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0x10097 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10098 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10098 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10098 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10098 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10099 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10099 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10099 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10099 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x1009c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0x1009d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0x1009e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x1009f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x1009f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x100a0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x100a0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x100a1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x100a1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x100a2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x100a2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x100a3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x100a3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x100a4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x100a4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x100a5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x100a5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x100a6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x100a6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x100a8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0x100a9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0x100a9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST 0x100ac +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP 0x100ad +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL 0x100ad +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x100b0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL 0x100b1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS 0x100b1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x100b2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x100b3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0x100b4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0x100b5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0x100b5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST 0x100bc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP 0x100bd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL 0x100bd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 0x100be +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 0x100bf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 0x100c0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 0x100c1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 0x100c2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 0x100c3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x100c4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x100c5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x100c8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0x100c9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x100ca +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0x100cb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0x100cb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0x100cc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0x100cd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0x100ce +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0x100ce +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0x100cf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0x100cf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0x100d0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0x100d0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x100d1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0x100d1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0x100d2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x100d3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x100d4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x100d5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x100d6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x100d7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x100d8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x100d9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x100da +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x100db +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP 0x10101 +#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS 0x10102 +#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x10104 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT 0x10105 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT 0x10106 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT 0x10107 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x10108 +#define regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x10109 +#define regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x1010a +#define regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0x1010c +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0x1010c +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0x1010c +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0x1010c +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0x1010d +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0x1010d +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0x1010d +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0x1010d +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0x1010e +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0x1010e +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0x1010e +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0x1010e +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0x1010f +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0x1010f +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0x1010f +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0x1010f +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST 0x10114 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP 0x10115 +#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS 0x10115 +#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0x10116 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0x10116 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0x10117 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0x10117 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0x10118 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0x10118 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0x10119 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0x10119 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0x1011a +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0x1011a +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0x1011b +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0x1011b +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0x1011c +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0x1011c +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0x1011d +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0x1011d +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0x1011e +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0x1011e +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0x1011f +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0x1011f +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0x10120 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0x10120 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0x10121 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0x10121 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0x10122 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0x10122 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0x10123 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0x10123 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0x10124 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0x10124 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0x10125 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0x10125 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT 0x10141 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT 0x10142 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT 0x10143 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x101c0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x101c1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x101c2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x101c3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x101c4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x101c5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x101c6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x101c7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x101c8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x101c9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x101ca +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x101cc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x101cd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x101ce +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x101cf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x101d0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x101d1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x101d2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x101d3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x101d4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x101d5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x101d6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x101d7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x101d8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x101d9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x101da +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x101db +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x101dc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x101dd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x101de +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x101df +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x101e0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x101e1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x101e2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x101e3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x101e4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x101e5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x101e6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x101e7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x101e8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x101e9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x101ea +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x101eb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x101ec +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x101f0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 0x101f1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 0x101f2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 0x101f3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 0x101f4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0 0x101fc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1 0x101fd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2 0x101fe +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3 0x101ff +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4 0x10200 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5 0x10201 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6 0x10202 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7 0x10203 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8 0x10204 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0x10208 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0x10209 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0x1020a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0x1020b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0x1020c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0x1020d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0x1020e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0x1020f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0x10210 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0 0x10214 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1 0x10215 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2 0x10216 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3 0x10217 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4 0x10218 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5 0x10219 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6 0x1021a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7 0x1021b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8 0x1021c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0 0x10220 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1 0x10221 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2 0x10222 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3 0x10223 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4 0x10224 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5 0x10225 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6 0x10226 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7 0x10227 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8 0x10228 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0 0x1022c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1 0x1022d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2 0x1022e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3 0x1022f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4 0x10230 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5 0x10231 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6 0x10232 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7 0x10233 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8 0x10234 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0 0x10238 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1 0x10239 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2 0x1023a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3 0x1023b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4 0x1023c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5 0x1023d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6 0x1023e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7 0x1023f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8 0x10240 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0 0x10244 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1 0x10245 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2 0x10246 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3 0x10247 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4 0x10248 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5 0x10249 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6 0x1024a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7 0x1024b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8 0x1024c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0 0x10250 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1 0x10251 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2 0x10252 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3 0x10253 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4 0x10254 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5 0x10255 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6 0x10256 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7 0x10257 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8 0x10258 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0 0x1025c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1 0x1025d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2 0x1025e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3 0x1025f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4 0x10260 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5 0x10261 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6 0x10262 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7 0x10263 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8 0x10264 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0 0x10268 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1 0x10269 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2 0x1026a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3 0x1026b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4 0x1026c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5 0x1026d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6 0x1026e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7 0x1026f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8 0x10270 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0 0x10274 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1 0x10275 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2 0x10276 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3 0x10277 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4 0x10278 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5 0x10279 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6 0x1027a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7 0x1027b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8 0x1027c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0 0x10280 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1 0x10281 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2 0x10282 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3 0x10283 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4 0x10284 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5 0x10285 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6 0x10286 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7 0x10287 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8 0x10288 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0 0x1028c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1 0x1028d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2 0x1028e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3 0x1028f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4 0x10290 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5 0x10291 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6 0x10292 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7 0x10293 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8 0x10294 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0 0x10298 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1 0x10299 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2 0x1029a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3 0x1029b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4 0x1029c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5 0x1029d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6 0x1029e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7 0x1029f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8 0x102a0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0 0x102a4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1 0x102a5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2 0x102a6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3 0x102a7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4 0x102a8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5 0x102a9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6 0x102aa +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7 0x102ab +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8 0x102ac +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0 0x102b0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1 0x102b1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2 0x102b2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3 0x102b3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4 0x102b4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5 0x102b5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6 0x102b6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7 0x102b7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8 0x102b8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0 0x102bc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1 0x102bd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2 0x102be +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3 0x102bf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4 0x102c0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5 0x102c1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6 0x102c2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7 0x102c3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8 0x102c4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0 0x102c8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1 0x102c9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2 0x102ca +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3 0x102cb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4 0x102cc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5 0x102cd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6 0x102ce +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7 0x102cf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8 0x102d0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0 0x102d4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1 0x102d5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2 0x102d6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3 0x102d7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4 0x102d8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5 0x102d9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6 0x102da +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7 0x102db +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8 0x102dc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0 0x102e0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1 0x102e1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2 0x102e2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3 0x102e3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4 0x102e4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5 0x102e5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6 0x102e6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7 0x102e7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8 0x102e8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE 0x10300 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE 0x10301 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE 0x10302 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE 0x10303 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS 0x10304 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS 0x10305 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS 0x10306 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS 0x10307 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +// base address: 0x10141000 +#define regBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0x10400 +#define regBIF_CFG_DEV0_EPF1_0_VENDOR_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0x10400 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_COMMAND 0x10401 +#define regBIF_CFG_DEV0_EPF1_0_COMMAND_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_STATUS 0x10401 +#define regBIF_CFG_DEV0_EPF1_0_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_REVISION_ID 0x10402 +#define regBIF_CFG_DEV0_EPF1_0_REVISION_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0x10402 +#define regBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0x10402 +#define regBIF_CFG_DEV0_EPF1_0_SUB_CLASS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0x10402 +#define regBIF_CFG_DEV0_EPF1_0_BASE_CLASS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0x10403 +#define regBIF_CFG_DEV0_EPF1_0_CACHE_LINE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_LATENCY 0x10403 +#define regBIF_CFG_DEV0_EPF1_0_LATENCY_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_HEADER 0x10403 +#define regBIF_CFG_DEV0_EPF1_0_HEADER_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BIST 0x10403 +#define regBIF_CFG_DEV0_EPF1_0_BIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0x10404 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0x10405 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0x10406 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0x10407 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0x10408 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0x10409 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR 0x1040a +#define regBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0x1040b +#define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0x1040c +#define regBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_CAP_PTR 0x1040d +#define regBIF_CFG_DEV0_EPF1_0_CAP_PTR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0x1040f +#define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0x1040f +#define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0x1040f +#define regBIF_CFG_DEV0_EPF1_0_MIN_GRANT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0x1040f +#define regBIF_CFG_DEV0_EPF1_0_MAX_LATENCY_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0x10412 +#define regBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0x10413 +#define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0x10414 +#define regBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PMI_CAP 0x10414 +#define regBIF_CFG_DEV0_EPF1_0_PMI_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0x10415 +#define regBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0x10419 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0x10419 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0x1041a +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0x1041b +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0x1041b +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_LINK_CAP 0x1041c +#define regBIF_CFG_DEV0_EPF1_0_LINK_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0x1041d +#define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0x1041d +#define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0x10422 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0x10423 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0x10423 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0x10424 +#define regBIF_CFG_DEV0_EPF1_0_LINK_CAP2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0x10425 +#define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0x10425 +#define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0x10428 +#define regBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0x10428 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0x10429 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0x1042a +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0x1042a +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA 0x1042a +#define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MASK 0x1042b +#define regBIF_CFG_DEV0_EPF1_0_MSI_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0x1042b +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64 0x1042b +#define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0x1042c +#define regBIF_CFG_DEV0_EPF1_0_MSI_MASK_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0x1042c +#define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0x1042d +#define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0x10430 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0x10430 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0x10431 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_TABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0x10432 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_PBA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10440 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x10441 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x10442 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x10443 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10454 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x10455 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0x10456 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x10457 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0x10458 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0x10459 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x1045a +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0x1045b +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0x1045c +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0x1045d +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0x1045e +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x10462 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x10463 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x10464 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x10465 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x10480 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0x10481 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0x10482 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0x10483 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0x10484 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0x10485 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0x10486 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0x10487 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0x10488 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0x10489 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0x1048a +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0x1048b +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0x1048c +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10490 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x10491 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0x10492 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0x10493 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x10494 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0x10495 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x10496 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0x10497 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0x10497 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10498 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10498 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10498 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10498 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10499 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10499 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10499 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10499 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x104a8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0x104a9 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0x104a9 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0x104b4 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0x104b5 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0x104b5 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x104ca +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0x104cb +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0x104cb +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_DEV0_1_RCC_VDM_SUPPORT 0xc440 +#define regRCC_DEV0_1_RCC_VDM_SUPPORT_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_BUS_CNTL 0xc441 +#define regRCC_DEV0_1_RCC_BUS_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC 0xc442 +#define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL 0xc443 +#define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CMN_LINK_CNTL 0xc444 +#define regRCC_DEV0_1_RCC_CMN_LINK_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE 0xc445 +#define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL 0xc446 +#define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_MH_ARB_CNTL 0xc447 +#define regRCC_DEV0_1_RCC_MH_ARB_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 0xc448 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 0xc449 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_ep_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH 0xc44c +#define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_CNTL 0xc44e +#define regRCC_EP_DEV0_1_EP_PCIE_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL 0xc44f +#define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS 0xc450 +#define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 0xc451 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL 0xc452 +#define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL 0xc453 +#define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL 0xc454 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC 0xc455 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 0xc456 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP 0xc457 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0xc458 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL 0xc458 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0xc458 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0xc45a +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0xc45a +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0xc45a +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL 0xc45c +#define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED 0xc45d +#define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL 0xc45f +#define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID 0xc460 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL 0xc461 +#define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL 0xc462 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL 0xc463 +#define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED 0xc468 +#define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH 0xc469 +#define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_CNTL 0xc46b +#define regRCC_DWN_DEV0_1_DN_PCIE_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL 0xc46c +#define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 0xc46d +#define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL 0xc46e +#define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL 0xc46f +#define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 0xc470 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC 0xc471 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 0xc472 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL 0xc475 +#define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_BASE_IDX 8 +#define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL 0xc476 +#define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL_BASE_IDX 8 +#define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL 0xc477 +#define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_BASE_IDX 8 +#define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2 0xc478 +#define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_BASE_IDX 8 +#define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC 0xc479 +#define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_BASE_IDX 8 +#define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP 0xc47a +#define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_pfc_amdgfx_RCCPFCDEC +// base address: 0x10134000 +#define regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL 0xd040 +#define regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE 0xd041 +#define regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0 0xd042 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1 0xd043 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2 0xd044 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3 0xd045 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4 0xd046 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5 0xd047 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL 0xd048 +#define regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_pciemsix_0_usb_MSIXTDEC +// base address: 0x10168000 +#define regPCIEMSIX_VECT0_ADDR_LO 0x1a000 +#define regPCIEMSIX_VECT0_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT0_ADDR_HI 0x1a001 +#define regPCIEMSIX_VECT0_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT0_MSG_DATA 0x1a002 +#define regPCIEMSIX_VECT0_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT0_CONTROL 0x1a003 +#define regPCIEMSIX_VECT0_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT1_ADDR_LO 0x1a004 +#define regPCIEMSIX_VECT1_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT1_ADDR_HI 0x1a005 +#define regPCIEMSIX_VECT1_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT1_MSG_DATA 0x1a006 +#define regPCIEMSIX_VECT1_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT1_CONTROL 0x1a007 +#define regPCIEMSIX_VECT1_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT2_ADDR_LO 0x1a008 +#define regPCIEMSIX_VECT2_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT2_ADDR_HI 0x1a009 +#define regPCIEMSIX_VECT2_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT2_MSG_DATA 0x1a00a +#define regPCIEMSIX_VECT2_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT2_CONTROL 0x1a00b +#define regPCIEMSIX_VECT2_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT3_ADDR_LO 0x1a00c +#define regPCIEMSIX_VECT3_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT3_ADDR_HI 0x1a00d +#define regPCIEMSIX_VECT3_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT3_MSG_DATA 0x1a00e +#define regPCIEMSIX_VECT3_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT3_CONTROL 0x1a00f +#define regPCIEMSIX_VECT3_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT4_ADDR_LO 0x1a010 +#define regPCIEMSIX_VECT4_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT4_ADDR_HI 0x1a011 +#define regPCIEMSIX_VECT4_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT4_MSG_DATA 0x1a012 +#define regPCIEMSIX_VECT4_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT4_CONTROL 0x1a013 +#define regPCIEMSIX_VECT4_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT5_ADDR_LO 0x1a014 +#define regPCIEMSIX_VECT5_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT5_ADDR_HI 0x1a015 +#define regPCIEMSIX_VECT5_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT5_MSG_DATA 0x1a016 +#define regPCIEMSIX_VECT5_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT5_CONTROL 0x1a017 +#define regPCIEMSIX_VECT5_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT6_ADDR_LO 0x1a018 +#define regPCIEMSIX_VECT6_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT6_ADDR_HI 0x1a019 +#define regPCIEMSIX_VECT6_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT6_MSG_DATA 0x1a01a +#define regPCIEMSIX_VECT6_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT6_CONTROL 0x1a01b +#define regPCIEMSIX_VECT6_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT7_ADDR_LO 0x1a01c +#define regPCIEMSIX_VECT7_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT7_ADDR_HI 0x1a01d +#define regPCIEMSIX_VECT7_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT7_MSG_DATA 0x1a01e +#define regPCIEMSIX_VECT7_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT7_CONTROL 0x1a01f +#define regPCIEMSIX_VECT7_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT8_ADDR_LO 0x1a020 +#define regPCIEMSIX_VECT8_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT8_ADDR_HI 0x1a021 +#define regPCIEMSIX_VECT8_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT8_MSG_DATA 0x1a022 +#define regPCIEMSIX_VECT8_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT8_CONTROL 0x1a023 +#define regPCIEMSIX_VECT8_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT9_ADDR_LO 0x1a024 +#define regPCIEMSIX_VECT9_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT9_ADDR_HI 0x1a025 +#define regPCIEMSIX_VECT9_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT9_MSG_DATA 0x1a026 +#define regPCIEMSIX_VECT9_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT9_CONTROL 0x1a027 +#define regPCIEMSIX_VECT9_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT10_ADDR_LO 0x1a028 +#define regPCIEMSIX_VECT10_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT10_ADDR_HI 0x1a029 +#define regPCIEMSIX_VECT10_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT10_MSG_DATA 0x1a02a +#define regPCIEMSIX_VECT10_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT10_CONTROL 0x1a02b +#define regPCIEMSIX_VECT10_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT11_ADDR_LO 0x1a02c +#define regPCIEMSIX_VECT11_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT11_ADDR_HI 0x1a02d +#define regPCIEMSIX_VECT11_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT11_MSG_DATA 0x1a02e +#define regPCIEMSIX_VECT11_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT11_CONTROL 0x1a02f +#define regPCIEMSIX_VECT11_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT12_ADDR_LO 0x1a030 +#define regPCIEMSIX_VECT12_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT12_ADDR_HI 0x1a031 +#define regPCIEMSIX_VECT12_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT12_MSG_DATA 0x1a032 +#define regPCIEMSIX_VECT12_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT12_CONTROL 0x1a033 +#define regPCIEMSIX_VECT12_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT13_ADDR_LO 0x1a034 +#define regPCIEMSIX_VECT13_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT13_ADDR_HI 0x1a035 +#define regPCIEMSIX_VECT13_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT13_MSG_DATA 0x1a036 +#define regPCIEMSIX_VECT13_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT13_CONTROL 0x1a037 +#define regPCIEMSIX_VECT13_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT14_ADDR_LO 0x1a038 +#define regPCIEMSIX_VECT14_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT14_ADDR_HI 0x1a039 +#define regPCIEMSIX_VECT14_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT14_MSG_DATA 0x1a03a +#define regPCIEMSIX_VECT14_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT14_CONTROL 0x1a03b +#define regPCIEMSIX_VECT14_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT15_ADDR_LO 0x1a03c +#define regPCIEMSIX_VECT15_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT15_ADDR_HI 0x1a03d +#define regPCIEMSIX_VECT15_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT15_MSG_DATA 0x1a03e +#define regPCIEMSIX_VECT15_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT15_CONTROL 0x1a03f +#define regPCIEMSIX_VECT15_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT16_ADDR_LO 0x1a040 +#define regPCIEMSIX_VECT16_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT16_ADDR_HI 0x1a041 +#define regPCIEMSIX_VECT16_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT16_MSG_DATA 0x1a042 +#define regPCIEMSIX_VECT16_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT16_CONTROL 0x1a043 +#define regPCIEMSIX_VECT16_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT17_ADDR_LO 0x1a044 +#define regPCIEMSIX_VECT17_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT17_ADDR_HI 0x1a045 +#define regPCIEMSIX_VECT17_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT17_MSG_DATA 0x1a046 +#define regPCIEMSIX_VECT17_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT17_CONTROL 0x1a047 +#define regPCIEMSIX_VECT17_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT18_ADDR_LO 0x1a048 +#define regPCIEMSIX_VECT18_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT18_ADDR_HI 0x1a049 +#define regPCIEMSIX_VECT18_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT18_MSG_DATA 0x1a04a +#define regPCIEMSIX_VECT18_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT18_CONTROL 0x1a04b +#define regPCIEMSIX_VECT18_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT19_ADDR_LO 0x1a04c +#define regPCIEMSIX_VECT19_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT19_ADDR_HI 0x1a04d +#define regPCIEMSIX_VECT19_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT19_MSG_DATA 0x1a04e +#define regPCIEMSIX_VECT19_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT19_CONTROL 0x1a04f +#define regPCIEMSIX_VECT19_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT20_ADDR_LO 0x1a050 +#define regPCIEMSIX_VECT20_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT20_ADDR_HI 0x1a051 +#define regPCIEMSIX_VECT20_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT20_MSG_DATA 0x1a052 +#define regPCIEMSIX_VECT20_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT20_CONTROL 0x1a053 +#define regPCIEMSIX_VECT20_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT21_ADDR_LO 0x1a054 +#define regPCIEMSIX_VECT21_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT21_ADDR_HI 0x1a055 +#define regPCIEMSIX_VECT21_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT21_MSG_DATA 0x1a056 +#define regPCIEMSIX_VECT21_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT21_CONTROL 0x1a057 +#define regPCIEMSIX_VECT21_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT22_ADDR_LO 0x1a058 +#define regPCIEMSIX_VECT22_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT22_ADDR_HI 0x1a059 +#define regPCIEMSIX_VECT22_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT22_MSG_DATA 0x1a05a +#define regPCIEMSIX_VECT22_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT22_CONTROL 0x1a05b +#define regPCIEMSIX_VECT22_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT23_ADDR_LO 0x1a05c +#define regPCIEMSIX_VECT23_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT23_ADDR_HI 0x1a05d +#define regPCIEMSIX_VECT23_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT23_MSG_DATA 0x1a05e +#define regPCIEMSIX_VECT23_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT23_CONTROL 0x1a05f +#define regPCIEMSIX_VECT23_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT24_ADDR_LO 0x1a060 +#define regPCIEMSIX_VECT24_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT24_ADDR_HI 0x1a061 +#define regPCIEMSIX_VECT24_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT24_MSG_DATA 0x1a062 +#define regPCIEMSIX_VECT24_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT24_CONTROL 0x1a063 +#define regPCIEMSIX_VECT24_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT25_ADDR_LO 0x1a064 +#define regPCIEMSIX_VECT25_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT25_ADDR_HI 0x1a065 +#define regPCIEMSIX_VECT25_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT25_MSG_DATA 0x1a066 +#define regPCIEMSIX_VECT25_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT25_CONTROL 0x1a067 +#define regPCIEMSIX_VECT25_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT26_ADDR_LO 0x1a068 +#define regPCIEMSIX_VECT26_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT26_ADDR_HI 0x1a069 +#define regPCIEMSIX_VECT26_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT26_MSG_DATA 0x1a06a +#define regPCIEMSIX_VECT26_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT26_CONTROL 0x1a06b +#define regPCIEMSIX_VECT26_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT27_ADDR_LO 0x1a06c +#define regPCIEMSIX_VECT27_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT27_ADDR_HI 0x1a06d +#define regPCIEMSIX_VECT27_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT27_MSG_DATA 0x1a06e +#define regPCIEMSIX_VECT27_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT27_CONTROL 0x1a06f +#define regPCIEMSIX_VECT27_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT28_ADDR_LO 0x1a070 +#define regPCIEMSIX_VECT28_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT28_ADDR_HI 0x1a071 +#define regPCIEMSIX_VECT28_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT28_MSG_DATA 0x1a072 +#define regPCIEMSIX_VECT28_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT28_CONTROL 0x1a073 +#define regPCIEMSIX_VECT28_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT29_ADDR_LO 0x1a074 +#define regPCIEMSIX_VECT29_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT29_ADDR_HI 0x1a075 +#define regPCIEMSIX_VECT29_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT29_MSG_DATA 0x1a076 +#define regPCIEMSIX_VECT29_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT29_CONTROL 0x1a077 +#define regPCIEMSIX_VECT29_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT30_ADDR_LO 0x1a078 +#define regPCIEMSIX_VECT30_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT30_ADDR_HI 0x1a079 +#define regPCIEMSIX_VECT30_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT30_MSG_DATA 0x1a07a +#define regPCIEMSIX_VECT30_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT30_CONTROL 0x1a07b +#define regPCIEMSIX_VECT30_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT31_ADDR_LO 0x1a07c +#define regPCIEMSIX_VECT31_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT31_ADDR_HI 0x1a07d +#define regPCIEMSIX_VECT31_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT31_MSG_DATA 0x1a07e +#define regPCIEMSIX_VECT31_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT31_CONTROL 0x1a07f +#define regPCIEMSIX_VECT31_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT32_ADDR_LO 0x1a080 +#define regPCIEMSIX_VECT32_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT32_ADDR_HI 0x1a081 +#define regPCIEMSIX_VECT32_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT32_MSG_DATA 0x1a082 +#define regPCIEMSIX_VECT32_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT32_CONTROL 0x1a083 +#define regPCIEMSIX_VECT32_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT33_ADDR_LO 0x1a084 +#define regPCIEMSIX_VECT33_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT33_ADDR_HI 0x1a085 +#define regPCIEMSIX_VECT33_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT33_MSG_DATA 0x1a086 +#define regPCIEMSIX_VECT33_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT33_CONTROL 0x1a087 +#define regPCIEMSIX_VECT33_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT34_ADDR_LO 0x1a088 +#define regPCIEMSIX_VECT34_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT34_ADDR_HI 0x1a089 +#define regPCIEMSIX_VECT34_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT34_MSG_DATA 0x1a08a +#define regPCIEMSIX_VECT34_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT34_CONTROL 0x1a08b +#define regPCIEMSIX_VECT34_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT35_ADDR_LO 0x1a08c +#define regPCIEMSIX_VECT35_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT35_ADDR_HI 0x1a08d +#define regPCIEMSIX_VECT35_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT35_MSG_DATA 0x1a08e +#define regPCIEMSIX_VECT35_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT35_CONTROL 0x1a08f +#define regPCIEMSIX_VECT35_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT36_ADDR_LO 0x1a090 +#define regPCIEMSIX_VECT36_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT36_ADDR_HI 0x1a091 +#define regPCIEMSIX_VECT36_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT36_MSG_DATA 0x1a092 +#define regPCIEMSIX_VECT36_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT36_CONTROL 0x1a093 +#define regPCIEMSIX_VECT36_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT37_ADDR_LO 0x1a094 +#define regPCIEMSIX_VECT37_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT37_ADDR_HI 0x1a095 +#define regPCIEMSIX_VECT37_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT37_MSG_DATA 0x1a096 +#define regPCIEMSIX_VECT37_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT37_CONTROL 0x1a097 +#define regPCIEMSIX_VECT37_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT38_ADDR_LO 0x1a098 +#define regPCIEMSIX_VECT38_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT38_ADDR_HI 0x1a099 +#define regPCIEMSIX_VECT38_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT38_MSG_DATA 0x1a09a +#define regPCIEMSIX_VECT38_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT38_CONTROL 0x1a09b +#define regPCIEMSIX_VECT38_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT39_ADDR_LO 0x1a09c +#define regPCIEMSIX_VECT39_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT39_ADDR_HI 0x1a09d +#define regPCIEMSIX_VECT39_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT39_MSG_DATA 0x1a09e +#define regPCIEMSIX_VECT39_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT39_CONTROL 0x1a09f +#define regPCIEMSIX_VECT39_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT40_ADDR_LO 0x1a0a0 +#define regPCIEMSIX_VECT40_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT40_ADDR_HI 0x1a0a1 +#define regPCIEMSIX_VECT40_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT40_MSG_DATA 0x1a0a2 +#define regPCIEMSIX_VECT40_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT40_CONTROL 0x1a0a3 +#define regPCIEMSIX_VECT40_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT41_ADDR_LO 0x1a0a4 +#define regPCIEMSIX_VECT41_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT41_ADDR_HI 0x1a0a5 +#define regPCIEMSIX_VECT41_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT41_MSG_DATA 0x1a0a6 +#define regPCIEMSIX_VECT41_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT41_CONTROL 0x1a0a7 +#define regPCIEMSIX_VECT41_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT42_ADDR_LO 0x1a0a8 +#define regPCIEMSIX_VECT42_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT42_ADDR_HI 0x1a0a9 +#define regPCIEMSIX_VECT42_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT42_MSG_DATA 0x1a0aa +#define regPCIEMSIX_VECT42_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT42_CONTROL 0x1a0ab +#define regPCIEMSIX_VECT42_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT43_ADDR_LO 0x1a0ac +#define regPCIEMSIX_VECT43_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT43_ADDR_HI 0x1a0ad +#define regPCIEMSIX_VECT43_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT43_MSG_DATA 0x1a0ae +#define regPCIEMSIX_VECT43_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT43_CONTROL 0x1a0af +#define regPCIEMSIX_VECT43_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT44_ADDR_LO 0x1a0b0 +#define regPCIEMSIX_VECT44_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT44_ADDR_HI 0x1a0b1 +#define regPCIEMSIX_VECT44_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT44_MSG_DATA 0x1a0b2 +#define regPCIEMSIX_VECT44_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT44_CONTROL 0x1a0b3 +#define regPCIEMSIX_VECT44_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT45_ADDR_LO 0x1a0b4 +#define regPCIEMSIX_VECT45_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT45_ADDR_HI 0x1a0b5 +#define regPCIEMSIX_VECT45_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT45_MSG_DATA 0x1a0b6 +#define regPCIEMSIX_VECT45_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT45_CONTROL 0x1a0b7 +#define regPCIEMSIX_VECT45_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT46_ADDR_LO 0x1a0b8 +#define regPCIEMSIX_VECT46_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT46_ADDR_HI 0x1a0b9 +#define regPCIEMSIX_VECT46_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT46_MSG_DATA 0x1a0ba +#define regPCIEMSIX_VECT46_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT46_CONTROL 0x1a0bb +#define regPCIEMSIX_VECT46_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT47_ADDR_LO 0x1a0bc +#define regPCIEMSIX_VECT47_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT47_ADDR_HI 0x1a0bd +#define regPCIEMSIX_VECT47_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT47_MSG_DATA 0x1a0be +#define regPCIEMSIX_VECT47_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT47_CONTROL 0x1a0bf +#define regPCIEMSIX_VECT47_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT48_ADDR_LO 0x1a0c0 +#define regPCIEMSIX_VECT48_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT48_ADDR_HI 0x1a0c1 +#define regPCIEMSIX_VECT48_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT48_MSG_DATA 0x1a0c2 +#define regPCIEMSIX_VECT48_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT48_CONTROL 0x1a0c3 +#define regPCIEMSIX_VECT48_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT49_ADDR_LO 0x1a0c4 +#define regPCIEMSIX_VECT49_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT49_ADDR_HI 0x1a0c5 +#define regPCIEMSIX_VECT49_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT49_MSG_DATA 0x1a0c6 +#define regPCIEMSIX_VECT49_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT49_CONTROL 0x1a0c7 +#define regPCIEMSIX_VECT49_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT50_ADDR_LO 0x1a0c8 +#define regPCIEMSIX_VECT50_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT50_ADDR_HI 0x1a0c9 +#define regPCIEMSIX_VECT50_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT50_MSG_DATA 0x1a0ca +#define regPCIEMSIX_VECT50_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT50_CONTROL 0x1a0cb +#define regPCIEMSIX_VECT50_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT51_ADDR_LO 0x1a0cc +#define regPCIEMSIX_VECT51_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT51_ADDR_HI 0x1a0cd +#define regPCIEMSIX_VECT51_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT51_MSG_DATA 0x1a0ce +#define regPCIEMSIX_VECT51_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT51_CONTROL 0x1a0cf +#define regPCIEMSIX_VECT51_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT52_ADDR_LO 0x1a0d0 +#define regPCIEMSIX_VECT52_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT52_ADDR_HI 0x1a0d1 +#define regPCIEMSIX_VECT52_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT52_MSG_DATA 0x1a0d2 +#define regPCIEMSIX_VECT52_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT52_CONTROL 0x1a0d3 +#define regPCIEMSIX_VECT52_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT53_ADDR_LO 0x1a0d4 +#define regPCIEMSIX_VECT53_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT53_ADDR_HI 0x1a0d5 +#define regPCIEMSIX_VECT53_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT53_MSG_DATA 0x1a0d6 +#define regPCIEMSIX_VECT53_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT53_CONTROL 0x1a0d7 +#define regPCIEMSIX_VECT53_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT54_ADDR_LO 0x1a0d8 +#define regPCIEMSIX_VECT54_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT54_ADDR_HI 0x1a0d9 +#define regPCIEMSIX_VECT54_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT54_MSG_DATA 0x1a0da +#define regPCIEMSIX_VECT54_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT54_CONTROL 0x1a0db +#define regPCIEMSIX_VECT54_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT55_ADDR_LO 0x1a0dc +#define regPCIEMSIX_VECT55_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT55_ADDR_HI 0x1a0dd +#define regPCIEMSIX_VECT55_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT55_MSG_DATA 0x1a0de +#define regPCIEMSIX_VECT55_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT55_CONTROL 0x1a0df +#define regPCIEMSIX_VECT55_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT56_ADDR_LO 0x1a0e0 +#define regPCIEMSIX_VECT56_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT56_ADDR_HI 0x1a0e1 +#define regPCIEMSIX_VECT56_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT56_MSG_DATA 0x1a0e2 +#define regPCIEMSIX_VECT56_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT56_CONTROL 0x1a0e3 +#define regPCIEMSIX_VECT56_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT57_ADDR_LO 0x1a0e4 +#define regPCIEMSIX_VECT57_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT57_ADDR_HI 0x1a0e5 +#define regPCIEMSIX_VECT57_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT57_MSG_DATA 0x1a0e6 +#define regPCIEMSIX_VECT57_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT57_CONTROL 0x1a0e7 +#define regPCIEMSIX_VECT57_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT58_ADDR_LO 0x1a0e8 +#define regPCIEMSIX_VECT58_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT58_ADDR_HI 0x1a0e9 +#define regPCIEMSIX_VECT58_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT58_MSG_DATA 0x1a0ea +#define regPCIEMSIX_VECT58_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT58_CONTROL 0x1a0eb +#define regPCIEMSIX_VECT58_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT59_ADDR_LO 0x1a0ec +#define regPCIEMSIX_VECT59_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT59_ADDR_HI 0x1a0ed +#define regPCIEMSIX_VECT59_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT59_MSG_DATA 0x1a0ee +#define regPCIEMSIX_VECT59_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT59_CONTROL 0x1a0ef +#define regPCIEMSIX_VECT59_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT60_ADDR_LO 0x1a0f0 +#define regPCIEMSIX_VECT60_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT60_ADDR_HI 0x1a0f1 +#define regPCIEMSIX_VECT60_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT60_MSG_DATA 0x1a0f2 +#define regPCIEMSIX_VECT60_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT60_CONTROL 0x1a0f3 +#define regPCIEMSIX_VECT60_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT61_ADDR_LO 0x1a0f4 +#define regPCIEMSIX_VECT61_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT61_ADDR_HI 0x1a0f5 +#define regPCIEMSIX_VECT61_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT61_MSG_DATA 0x1a0f6 +#define regPCIEMSIX_VECT61_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT61_CONTROL 0x1a0f7 +#define regPCIEMSIX_VECT61_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT62_ADDR_LO 0x1a0f8 +#define regPCIEMSIX_VECT62_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT62_ADDR_HI 0x1a0f9 +#define regPCIEMSIX_VECT62_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT62_MSG_DATA 0x1a0fa +#define regPCIEMSIX_VECT62_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT62_CONTROL 0x1a0fb +#define regPCIEMSIX_VECT62_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT63_ADDR_LO 0x1a0fc +#define regPCIEMSIX_VECT63_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT63_ADDR_HI 0x1a0fd +#define regPCIEMSIX_VECT63_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT63_MSG_DATA 0x1a0fe +#define regPCIEMSIX_VECT63_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT63_CONTROL 0x1a0ff +#define regPCIEMSIX_VECT63_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT64_ADDR_LO 0x1a100 +#define regPCIEMSIX_VECT64_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT64_ADDR_HI 0x1a101 +#define regPCIEMSIX_VECT64_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT64_MSG_DATA 0x1a102 +#define regPCIEMSIX_VECT64_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT64_CONTROL 0x1a103 +#define regPCIEMSIX_VECT64_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT65_ADDR_LO 0x1a104 +#define regPCIEMSIX_VECT65_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT65_ADDR_HI 0x1a105 +#define regPCIEMSIX_VECT65_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT65_MSG_DATA 0x1a106 +#define regPCIEMSIX_VECT65_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT65_CONTROL 0x1a107 +#define regPCIEMSIX_VECT65_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT66_ADDR_LO 0x1a108 +#define regPCIEMSIX_VECT66_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT66_ADDR_HI 0x1a109 +#define regPCIEMSIX_VECT66_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT66_MSG_DATA 0x1a10a +#define regPCIEMSIX_VECT66_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT66_CONTROL 0x1a10b +#define regPCIEMSIX_VECT66_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT67_ADDR_LO 0x1a10c +#define regPCIEMSIX_VECT67_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT67_ADDR_HI 0x1a10d +#define regPCIEMSIX_VECT67_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT67_MSG_DATA 0x1a10e +#define regPCIEMSIX_VECT67_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT67_CONTROL 0x1a10f +#define regPCIEMSIX_VECT67_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT68_ADDR_LO 0x1a110 +#define regPCIEMSIX_VECT68_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT68_ADDR_HI 0x1a111 +#define regPCIEMSIX_VECT68_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT68_MSG_DATA 0x1a112 +#define regPCIEMSIX_VECT68_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT68_CONTROL 0x1a113 +#define regPCIEMSIX_VECT68_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT69_ADDR_LO 0x1a114 +#define regPCIEMSIX_VECT69_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT69_ADDR_HI 0x1a115 +#define regPCIEMSIX_VECT69_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT69_MSG_DATA 0x1a116 +#define regPCIEMSIX_VECT69_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT69_CONTROL 0x1a117 +#define regPCIEMSIX_VECT69_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT70_ADDR_LO 0x1a118 +#define regPCIEMSIX_VECT70_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT70_ADDR_HI 0x1a119 +#define regPCIEMSIX_VECT70_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT70_MSG_DATA 0x1a11a +#define regPCIEMSIX_VECT70_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT70_CONTROL 0x1a11b +#define regPCIEMSIX_VECT70_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT71_ADDR_LO 0x1a11c +#define regPCIEMSIX_VECT71_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT71_ADDR_HI 0x1a11d +#define regPCIEMSIX_VECT71_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT71_MSG_DATA 0x1a11e +#define regPCIEMSIX_VECT71_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT71_CONTROL 0x1a11f +#define regPCIEMSIX_VECT71_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT72_ADDR_LO 0x1a120 +#define regPCIEMSIX_VECT72_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT72_ADDR_HI 0x1a121 +#define regPCIEMSIX_VECT72_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT72_MSG_DATA 0x1a122 +#define regPCIEMSIX_VECT72_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT72_CONTROL 0x1a123 +#define regPCIEMSIX_VECT72_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT73_ADDR_LO 0x1a124 +#define regPCIEMSIX_VECT73_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT73_ADDR_HI 0x1a125 +#define regPCIEMSIX_VECT73_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT73_MSG_DATA 0x1a126 +#define regPCIEMSIX_VECT73_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT73_CONTROL 0x1a127 +#define regPCIEMSIX_VECT73_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT74_ADDR_LO 0x1a128 +#define regPCIEMSIX_VECT74_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT74_ADDR_HI 0x1a129 +#define regPCIEMSIX_VECT74_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT74_MSG_DATA 0x1a12a +#define regPCIEMSIX_VECT74_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT74_CONTROL 0x1a12b +#define regPCIEMSIX_VECT74_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT75_ADDR_LO 0x1a12c +#define regPCIEMSIX_VECT75_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT75_ADDR_HI 0x1a12d +#define regPCIEMSIX_VECT75_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT75_MSG_DATA 0x1a12e +#define regPCIEMSIX_VECT75_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT75_CONTROL 0x1a12f +#define regPCIEMSIX_VECT75_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT76_ADDR_LO 0x1a130 +#define regPCIEMSIX_VECT76_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT76_ADDR_HI 0x1a131 +#define regPCIEMSIX_VECT76_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT76_MSG_DATA 0x1a132 +#define regPCIEMSIX_VECT76_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT76_CONTROL 0x1a133 +#define regPCIEMSIX_VECT76_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT77_ADDR_LO 0x1a134 +#define regPCIEMSIX_VECT77_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT77_ADDR_HI 0x1a135 +#define regPCIEMSIX_VECT77_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT77_MSG_DATA 0x1a136 +#define regPCIEMSIX_VECT77_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT77_CONTROL 0x1a137 +#define regPCIEMSIX_VECT77_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT78_ADDR_LO 0x1a138 +#define regPCIEMSIX_VECT78_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT78_ADDR_HI 0x1a139 +#define regPCIEMSIX_VECT78_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT78_MSG_DATA 0x1a13a +#define regPCIEMSIX_VECT78_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT78_CONTROL 0x1a13b +#define regPCIEMSIX_VECT78_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT79_ADDR_LO 0x1a13c +#define regPCIEMSIX_VECT79_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT79_ADDR_HI 0x1a13d +#define regPCIEMSIX_VECT79_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT79_MSG_DATA 0x1a13e +#define regPCIEMSIX_VECT79_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT79_CONTROL 0x1a13f +#define regPCIEMSIX_VECT79_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT80_ADDR_LO 0x1a140 +#define regPCIEMSIX_VECT80_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT80_ADDR_HI 0x1a141 +#define regPCIEMSIX_VECT80_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT80_MSG_DATA 0x1a142 +#define regPCIEMSIX_VECT80_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT80_CONTROL 0x1a143 +#define regPCIEMSIX_VECT80_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT81_ADDR_LO 0x1a144 +#define regPCIEMSIX_VECT81_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT81_ADDR_HI 0x1a145 +#define regPCIEMSIX_VECT81_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT81_MSG_DATA 0x1a146 +#define regPCIEMSIX_VECT81_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT81_CONTROL 0x1a147 +#define regPCIEMSIX_VECT81_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT82_ADDR_LO 0x1a148 +#define regPCIEMSIX_VECT82_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT82_ADDR_HI 0x1a149 +#define regPCIEMSIX_VECT82_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT82_MSG_DATA 0x1a14a +#define regPCIEMSIX_VECT82_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT82_CONTROL 0x1a14b +#define regPCIEMSIX_VECT82_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT83_ADDR_LO 0x1a14c +#define regPCIEMSIX_VECT83_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT83_ADDR_HI 0x1a14d +#define regPCIEMSIX_VECT83_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT83_MSG_DATA 0x1a14e +#define regPCIEMSIX_VECT83_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT83_CONTROL 0x1a14f +#define regPCIEMSIX_VECT83_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT84_ADDR_LO 0x1a150 +#define regPCIEMSIX_VECT84_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT84_ADDR_HI 0x1a151 +#define regPCIEMSIX_VECT84_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT84_MSG_DATA 0x1a152 +#define regPCIEMSIX_VECT84_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT84_CONTROL 0x1a153 +#define regPCIEMSIX_VECT84_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT85_ADDR_LO 0x1a154 +#define regPCIEMSIX_VECT85_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT85_ADDR_HI 0x1a155 +#define regPCIEMSIX_VECT85_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT85_MSG_DATA 0x1a156 +#define regPCIEMSIX_VECT85_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT85_CONTROL 0x1a157 +#define regPCIEMSIX_VECT85_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT86_ADDR_LO 0x1a158 +#define regPCIEMSIX_VECT86_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT86_ADDR_HI 0x1a159 +#define regPCIEMSIX_VECT86_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT86_MSG_DATA 0x1a15a +#define regPCIEMSIX_VECT86_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT86_CONTROL 0x1a15b +#define regPCIEMSIX_VECT86_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT87_ADDR_LO 0x1a15c +#define regPCIEMSIX_VECT87_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT87_ADDR_HI 0x1a15d +#define regPCIEMSIX_VECT87_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT87_MSG_DATA 0x1a15e +#define regPCIEMSIX_VECT87_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT87_CONTROL 0x1a15f +#define regPCIEMSIX_VECT87_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT88_ADDR_LO 0x1a160 +#define regPCIEMSIX_VECT88_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT88_ADDR_HI 0x1a161 +#define regPCIEMSIX_VECT88_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT88_MSG_DATA 0x1a162 +#define regPCIEMSIX_VECT88_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT88_CONTROL 0x1a163 +#define regPCIEMSIX_VECT88_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT89_ADDR_LO 0x1a164 +#define regPCIEMSIX_VECT89_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT89_ADDR_HI 0x1a165 +#define regPCIEMSIX_VECT89_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT89_MSG_DATA 0x1a166 +#define regPCIEMSIX_VECT89_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT89_CONTROL 0x1a167 +#define regPCIEMSIX_VECT89_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT90_ADDR_LO 0x1a168 +#define regPCIEMSIX_VECT90_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT90_ADDR_HI 0x1a169 +#define regPCIEMSIX_VECT90_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT90_MSG_DATA 0x1a16a +#define regPCIEMSIX_VECT90_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT90_CONTROL 0x1a16b +#define regPCIEMSIX_VECT90_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT91_ADDR_LO 0x1a16c +#define regPCIEMSIX_VECT91_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT91_ADDR_HI 0x1a16d +#define regPCIEMSIX_VECT91_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT91_MSG_DATA 0x1a16e +#define regPCIEMSIX_VECT91_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT91_CONTROL 0x1a16f +#define regPCIEMSIX_VECT91_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT92_ADDR_LO 0x1a170 +#define regPCIEMSIX_VECT92_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT92_ADDR_HI 0x1a171 +#define regPCIEMSIX_VECT92_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT92_MSG_DATA 0x1a172 +#define regPCIEMSIX_VECT92_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT92_CONTROL 0x1a173 +#define regPCIEMSIX_VECT92_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT93_ADDR_LO 0x1a174 +#define regPCIEMSIX_VECT93_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT93_ADDR_HI 0x1a175 +#define regPCIEMSIX_VECT93_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT93_MSG_DATA 0x1a176 +#define regPCIEMSIX_VECT93_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT93_CONTROL 0x1a177 +#define regPCIEMSIX_VECT93_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT94_ADDR_LO 0x1a178 +#define regPCIEMSIX_VECT94_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT94_ADDR_HI 0x1a179 +#define regPCIEMSIX_VECT94_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT94_MSG_DATA 0x1a17a +#define regPCIEMSIX_VECT94_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT94_CONTROL 0x1a17b +#define regPCIEMSIX_VECT94_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT95_ADDR_LO 0x1a17c +#define regPCIEMSIX_VECT95_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT95_ADDR_HI 0x1a17d +#define regPCIEMSIX_VECT95_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT95_MSG_DATA 0x1a17e +#define regPCIEMSIX_VECT95_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT95_CONTROL 0x1a17f +#define regPCIEMSIX_VECT95_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT96_ADDR_LO 0x1a180 +#define regPCIEMSIX_VECT96_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT96_ADDR_HI 0x1a181 +#define regPCIEMSIX_VECT96_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT96_MSG_DATA 0x1a182 +#define regPCIEMSIX_VECT96_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT96_CONTROL 0x1a183 +#define regPCIEMSIX_VECT96_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT97_ADDR_LO 0x1a184 +#define regPCIEMSIX_VECT97_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT97_ADDR_HI 0x1a185 +#define regPCIEMSIX_VECT97_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT97_MSG_DATA 0x1a186 +#define regPCIEMSIX_VECT97_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT97_CONTROL 0x1a187 +#define regPCIEMSIX_VECT97_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT98_ADDR_LO 0x1a188 +#define regPCIEMSIX_VECT98_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT98_ADDR_HI 0x1a189 +#define regPCIEMSIX_VECT98_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT98_MSG_DATA 0x1a18a +#define regPCIEMSIX_VECT98_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT98_CONTROL 0x1a18b +#define regPCIEMSIX_VECT98_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT99_ADDR_LO 0x1a18c +#define regPCIEMSIX_VECT99_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT99_ADDR_HI 0x1a18d +#define regPCIEMSIX_VECT99_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT99_MSG_DATA 0x1a18e +#define regPCIEMSIX_VECT99_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT99_CONTROL 0x1a18f +#define regPCIEMSIX_VECT99_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT100_ADDR_LO 0x1a190 +#define regPCIEMSIX_VECT100_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT100_ADDR_HI 0x1a191 +#define regPCIEMSIX_VECT100_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT100_MSG_DATA 0x1a192 +#define regPCIEMSIX_VECT100_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT100_CONTROL 0x1a193 +#define regPCIEMSIX_VECT100_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT101_ADDR_LO 0x1a194 +#define regPCIEMSIX_VECT101_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT101_ADDR_HI 0x1a195 +#define regPCIEMSIX_VECT101_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT101_MSG_DATA 0x1a196 +#define regPCIEMSIX_VECT101_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT101_CONTROL 0x1a197 +#define regPCIEMSIX_VECT101_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT102_ADDR_LO 0x1a198 +#define regPCIEMSIX_VECT102_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT102_ADDR_HI 0x1a199 +#define regPCIEMSIX_VECT102_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT102_MSG_DATA 0x1a19a +#define regPCIEMSIX_VECT102_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT102_CONTROL 0x1a19b +#define regPCIEMSIX_VECT102_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT103_ADDR_LO 0x1a19c +#define regPCIEMSIX_VECT103_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT103_ADDR_HI 0x1a19d +#define regPCIEMSIX_VECT103_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT103_MSG_DATA 0x1a19e +#define regPCIEMSIX_VECT103_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT103_CONTROL 0x1a19f +#define regPCIEMSIX_VECT103_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT104_ADDR_LO 0x1a1a0 +#define regPCIEMSIX_VECT104_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT104_ADDR_HI 0x1a1a1 +#define regPCIEMSIX_VECT104_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT104_MSG_DATA 0x1a1a2 +#define regPCIEMSIX_VECT104_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT104_CONTROL 0x1a1a3 +#define regPCIEMSIX_VECT104_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT105_ADDR_LO 0x1a1a4 +#define regPCIEMSIX_VECT105_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT105_ADDR_HI 0x1a1a5 +#define regPCIEMSIX_VECT105_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT105_MSG_DATA 0x1a1a6 +#define regPCIEMSIX_VECT105_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT105_CONTROL 0x1a1a7 +#define regPCIEMSIX_VECT105_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT106_ADDR_LO 0x1a1a8 +#define regPCIEMSIX_VECT106_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT106_ADDR_HI 0x1a1a9 +#define regPCIEMSIX_VECT106_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT106_MSG_DATA 0x1a1aa +#define regPCIEMSIX_VECT106_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT106_CONTROL 0x1a1ab +#define regPCIEMSIX_VECT106_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT107_ADDR_LO 0x1a1ac +#define regPCIEMSIX_VECT107_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT107_ADDR_HI 0x1a1ad +#define regPCIEMSIX_VECT107_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT107_MSG_DATA 0x1a1ae +#define regPCIEMSIX_VECT107_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT107_CONTROL 0x1a1af +#define regPCIEMSIX_VECT107_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT108_ADDR_LO 0x1a1b0 +#define regPCIEMSIX_VECT108_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT108_ADDR_HI 0x1a1b1 +#define regPCIEMSIX_VECT108_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT108_MSG_DATA 0x1a1b2 +#define regPCIEMSIX_VECT108_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT108_CONTROL 0x1a1b3 +#define regPCIEMSIX_VECT108_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT109_ADDR_LO 0x1a1b4 +#define regPCIEMSIX_VECT109_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT109_ADDR_HI 0x1a1b5 +#define regPCIEMSIX_VECT109_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT109_MSG_DATA 0x1a1b6 +#define regPCIEMSIX_VECT109_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT109_CONTROL 0x1a1b7 +#define regPCIEMSIX_VECT109_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT110_ADDR_LO 0x1a1b8 +#define regPCIEMSIX_VECT110_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT110_ADDR_HI 0x1a1b9 +#define regPCIEMSIX_VECT110_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT110_MSG_DATA 0x1a1ba +#define regPCIEMSIX_VECT110_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT110_CONTROL 0x1a1bb +#define regPCIEMSIX_VECT110_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT111_ADDR_LO 0x1a1bc +#define regPCIEMSIX_VECT111_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT111_ADDR_HI 0x1a1bd +#define regPCIEMSIX_VECT111_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT111_MSG_DATA 0x1a1be +#define regPCIEMSIX_VECT111_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT111_CONTROL 0x1a1bf +#define regPCIEMSIX_VECT111_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT112_ADDR_LO 0x1a1c0 +#define regPCIEMSIX_VECT112_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT112_ADDR_HI 0x1a1c1 +#define regPCIEMSIX_VECT112_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT112_MSG_DATA 0x1a1c2 +#define regPCIEMSIX_VECT112_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT112_CONTROL 0x1a1c3 +#define regPCIEMSIX_VECT112_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT113_ADDR_LO 0x1a1c4 +#define regPCIEMSIX_VECT113_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT113_ADDR_HI 0x1a1c5 +#define regPCIEMSIX_VECT113_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT113_MSG_DATA 0x1a1c6 +#define regPCIEMSIX_VECT113_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT113_CONTROL 0x1a1c7 +#define regPCIEMSIX_VECT113_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT114_ADDR_LO 0x1a1c8 +#define regPCIEMSIX_VECT114_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT114_ADDR_HI 0x1a1c9 +#define regPCIEMSIX_VECT114_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT114_MSG_DATA 0x1a1ca +#define regPCIEMSIX_VECT114_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT114_CONTROL 0x1a1cb +#define regPCIEMSIX_VECT114_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT115_ADDR_LO 0x1a1cc +#define regPCIEMSIX_VECT115_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT115_ADDR_HI 0x1a1cd +#define regPCIEMSIX_VECT115_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT115_MSG_DATA 0x1a1ce +#define regPCIEMSIX_VECT115_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT115_CONTROL 0x1a1cf +#define regPCIEMSIX_VECT115_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT116_ADDR_LO 0x1a1d0 +#define regPCIEMSIX_VECT116_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT116_ADDR_HI 0x1a1d1 +#define regPCIEMSIX_VECT116_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT116_MSG_DATA 0x1a1d2 +#define regPCIEMSIX_VECT116_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT116_CONTROL 0x1a1d3 +#define regPCIEMSIX_VECT116_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT117_ADDR_LO 0x1a1d4 +#define regPCIEMSIX_VECT117_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT117_ADDR_HI 0x1a1d5 +#define regPCIEMSIX_VECT117_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT117_MSG_DATA 0x1a1d6 +#define regPCIEMSIX_VECT117_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT117_CONTROL 0x1a1d7 +#define regPCIEMSIX_VECT117_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT118_ADDR_LO 0x1a1d8 +#define regPCIEMSIX_VECT118_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT118_ADDR_HI 0x1a1d9 +#define regPCIEMSIX_VECT118_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT118_MSG_DATA 0x1a1da +#define regPCIEMSIX_VECT118_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT118_CONTROL 0x1a1db +#define regPCIEMSIX_VECT118_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT119_ADDR_LO 0x1a1dc +#define regPCIEMSIX_VECT119_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT119_ADDR_HI 0x1a1dd +#define regPCIEMSIX_VECT119_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT119_MSG_DATA 0x1a1de +#define regPCIEMSIX_VECT119_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT119_CONTROL 0x1a1df +#define regPCIEMSIX_VECT119_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT120_ADDR_LO 0x1a1e0 +#define regPCIEMSIX_VECT120_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT120_ADDR_HI 0x1a1e1 +#define regPCIEMSIX_VECT120_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT120_MSG_DATA 0x1a1e2 +#define regPCIEMSIX_VECT120_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT120_CONTROL 0x1a1e3 +#define regPCIEMSIX_VECT120_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT121_ADDR_LO 0x1a1e4 +#define regPCIEMSIX_VECT121_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT121_ADDR_HI 0x1a1e5 +#define regPCIEMSIX_VECT121_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT121_MSG_DATA 0x1a1e6 +#define regPCIEMSIX_VECT121_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT121_CONTROL 0x1a1e7 +#define regPCIEMSIX_VECT121_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT122_ADDR_LO 0x1a1e8 +#define regPCIEMSIX_VECT122_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT122_ADDR_HI 0x1a1e9 +#define regPCIEMSIX_VECT122_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT122_MSG_DATA 0x1a1ea +#define regPCIEMSIX_VECT122_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT122_CONTROL 0x1a1eb +#define regPCIEMSIX_VECT122_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT123_ADDR_LO 0x1a1ec +#define regPCIEMSIX_VECT123_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT123_ADDR_HI 0x1a1ed +#define regPCIEMSIX_VECT123_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT123_MSG_DATA 0x1a1ee +#define regPCIEMSIX_VECT123_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT123_CONTROL 0x1a1ef +#define regPCIEMSIX_VECT123_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT124_ADDR_LO 0x1a1f0 +#define regPCIEMSIX_VECT124_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT124_ADDR_HI 0x1a1f1 +#define regPCIEMSIX_VECT124_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT124_MSG_DATA 0x1a1f2 +#define regPCIEMSIX_VECT124_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT124_CONTROL 0x1a1f3 +#define regPCIEMSIX_VECT124_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT125_ADDR_LO 0x1a1f4 +#define regPCIEMSIX_VECT125_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT125_ADDR_HI 0x1a1f5 +#define regPCIEMSIX_VECT125_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT125_MSG_DATA 0x1a1f6 +#define regPCIEMSIX_VECT125_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT125_CONTROL 0x1a1f7 +#define regPCIEMSIX_VECT125_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT126_ADDR_LO 0x1a1f8 +#define regPCIEMSIX_VECT126_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT126_ADDR_HI 0x1a1f9 +#define regPCIEMSIX_VECT126_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT126_MSG_DATA 0x1a1fa +#define regPCIEMSIX_VECT126_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT126_CONTROL 0x1a1fb +#define regPCIEMSIX_VECT126_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT127_ADDR_LO 0x1a1fc +#define regPCIEMSIX_VECT127_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT127_ADDR_HI 0x1a1fd +#define regPCIEMSIX_VECT127_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT127_MSG_DATA 0x1a1fe +#define regPCIEMSIX_VECT127_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT127_CONTROL 0x1a1ff +#define regPCIEMSIX_VECT127_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT128_ADDR_LO 0x1a200 +#define regPCIEMSIX_VECT128_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT128_ADDR_HI 0x1a201 +#define regPCIEMSIX_VECT128_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT128_MSG_DATA 0x1a202 +#define regPCIEMSIX_VECT128_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT128_CONTROL 0x1a203 +#define regPCIEMSIX_VECT128_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT129_ADDR_LO 0x1a204 +#define regPCIEMSIX_VECT129_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT129_ADDR_HI 0x1a205 +#define regPCIEMSIX_VECT129_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT129_MSG_DATA 0x1a206 +#define regPCIEMSIX_VECT129_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT129_CONTROL 0x1a207 +#define regPCIEMSIX_VECT129_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT130_ADDR_LO 0x1a208 +#define regPCIEMSIX_VECT130_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT130_ADDR_HI 0x1a209 +#define regPCIEMSIX_VECT130_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT130_MSG_DATA 0x1a20a +#define regPCIEMSIX_VECT130_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT130_CONTROL 0x1a20b +#define regPCIEMSIX_VECT130_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT131_ADDR_LO 0x1a20c +#define regPCIEMSIX_VECT131_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT131_ADDR_HI 0x1a20d +#define regPCIEMSIX_VECT131_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT131_MSG_DATA 0x1a20e +#define regPCIEMSIX_VECT131_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT131_CONTROL 0x1a20f +#define regPCIEMSIX_VECT131_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT132_ADDR_LO 0x1a210 +#define regPCIEMSIX_VECT132_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT132_ADDR_HI 0x1a211 +#define regPCIEMSIX_VECT132_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT132_MSG_DATA 0x1a212 +#define regPCIEMSIX_VECT132_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT132_CONTROL 0x1a213 +#define regPCIEMSIX_VECT132_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT133_ADDR_LO 0x1a214 +#define regPCIEMSIX_VECT133_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT133_ADDR_HI 0x1a215 +#define regPCIEMSIX_VECT133_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT133_MSG_DATA 0x1a216 +#define regPCIEMSIX_VECT133_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT133_CONTROL 0x1a217 +#define regPCIEMSIX_VECT133_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT134_ADDR_LO 0x1a218 +#define regPCIEMSIX_VECT134_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT134_ADDR_HI 0x1a219 +#define regPCIEMSIX_VECT134_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT134_MSG_DATA 0x1a21a +#define regPCIEMSIX_VECT134_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT134_CONTROL 0x1a21b +#define regPCIEMSIX_VECT134_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT135_ADDR_LO 0x1a21c +#define regPCIEMSIX_VECT135_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT135_ADDR_HI 0x1a21d +#define regPCIEMSIX_VECT135_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT135_MSG_DATA 0x1a21e +#define regPCIEMSIX_VECT135_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT135_CONTROL 0x1a21f +#define regPCIEMSIX_VECT135_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT136_ADDR_LO 0x1a220 +#define regPCIEMSIX_VECT136_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT136_ADDR_HI 0x1a221 +#define regPCIEMSIX_VECT136_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT136_MSG_DATA 0x1a222 +#define regPCIEMSIX_VECT136_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT136_CONTROL 0x1a223 +#define regPCIEMSIX_VECT136_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT137_ADDR_LO 0x1a224 +#define regPCIEMSIX_VECT137_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT137_ADDR_HI 0x1a225 +#define regPCIEMSIX_VECT137_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT137_MSG_DATA 0x1a226 +#define regPCIEMSIX_VECT137_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT137_CONTROL 0x1a227 +#define regPCIEMSIX_VECT137_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT138_ADDR_LO 0x1a228 +#define regPCIEMSIX_VECT138_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT138_ADDR_HI 0x1a229 +#define regPCIEMSIX_VECT138_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT138_MSG_DATA 0x1a22a +#define regPCIEMSIX_VECT138_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT138_CONTROL 0x1a22b +#define regPCIEMSIX_VECT138_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT139_ADDR_LO 0x1a22c +#define regPCIEMSIX_VECT139_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT139_ADDR_HI 0x1a22d +#define regPCIEMSIX_VECT139_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT139_MSG_DATA 0x1a22e +#define regPCIEMSIX_VECT139_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT139_CONTROL 0x1a22f +#define regPCIEMSIX_VECT139_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT140_ADDR_LO 0x1a230 +#define regPCIEMSIX_VECT140_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT140_ADDR_HI 0x1a231 +#define regPCIEMSIX_VECT140_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT140_MSG_DATA 0x1a232 +#define regPCIEMSIX_VECT140_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT140_CONTROL 0x1a233 +#define regPCIEMSIX_VECT140_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT141_ADDR_LO 0x1a234 +#define regPCIEMSIX_VECT141_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT141_ADDR_HI 0x1a235 +#define regPCIEMSIX_VECT141_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT141_MSG_DATA 0x1a236 +#define regPCIEMSIX_VECT141_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT141_CONTROL 0x1a237 +#define regPCIEMSIX_VECT141_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT142_ADDR_LO 0x1a238 +#define regPCIEMSIX_VECT142_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT142_ADDR_HI 0x1a239 +#define regPCIEMSIX_VECT142_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT142_MSG_DATA 0x1a23a +#define regPCIEMSIX_VECT142_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT142_CONTROL 0x1a23b +#define regPCIEMSIX_VECT142_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT143_ADDR_LO 0x1a23c +#define regPCIEMSIX_VECT143_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT143_ADDR_HI 0x1a23d +#define regPCIEMSIX_VECT143_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT143_MSG_DATA 0x1a23e +#define regPCIEMSIX_VECT143_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT143_CONTROL 0x1a23f +#define regPCIEMSIX_VECT143_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT144_ADDR_LO 0x1a240 +#define regPCIEMSIX_VECT144_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT144_ADDR_HI 0x1a241 +#define regPCIEMSIX_VECT144_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT144_MSG_DATA 0x1a242 +#define regPCIEMSIX_VECT144_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT144_CONTROL 0x1a243 +#define regPCIEMSIX_VECT144_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT145_ADDR_LO 0x1a244 +#define regPCIEMSIX_VECT145_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT145_ADDR_HI 0x1a245 +#define regPCIEMSIX_VECT145_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT145_MSG_DATA 0x1a246 +#define regPCIEMSIX_VECT145_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT145_CONTROL 0x1a247 +#define regPCIEMSIX_VECT145_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT146_ADDR_LO 0x1a248 +#define regPCIEMSIX_VECT146_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT146_ADDR_HI 0x1a249 +#define regPCIEMSIX_VECT146_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT146_MSG_DATA 0x1a24a +#define regPCIEMSIX_VECT146_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT146_CONTROL 0x1a24b +#define regPCIEMSIX_VECT146_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT147_ADDR_LO 0x1a24c +#define regPCIEMSIX_VECT147_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT147_ADDR_HI 0x1a24d +#define regPCIEMSIX_VECT147_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT147_MSG_DATA 0x1a24e +#define regPCIEMSIX_VECT147_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT147_CONTROL 0x1a24f +#define regPCIEMSIX_VECT147_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT148_ADDR_LO 0x1a250 +#define regPCIEMSIX_VECT148_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT148_ADDR_HI 0x1a251 +#define regPCIEMSIX_VECT148_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT148_MSG_DATA 0x1a252 +#define regPCIEMSIX_VECT148_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT148_CONTROL 0x1a253 +#define regPCIEMSIX_VECT148_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT149_ADDR_LO 0x1a254 +#define regPCIEMSIX_VECT149_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT149_ADDR_HI 0x1a255 +#define regPCIEMSIX_VECT149_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT149_MSG_DATA 0x1a256 +#define regPCIEMSIX_VECT149_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT149_CONTROL 0x1a257 +#define regPCIEMSIX_VECT149_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT150_ADDR_LO 0x1a258 +#define regPCIEMSIX_VECT150_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT150_ADDR_HI 0x1a259 +#define regPCIEMSIX_VECT150_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT150_MSG_DATA 0x1a25a +#define regPCIEMSIX_VECT150_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT150_CONTROL 0x1a25b +#define regPCIEMSIX_VECT150_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT151_ADDR_LO 0x1a25c +#define regPCIEMSIX_VECT151_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT151_ADDR_HI 0x1a25d +#define regPCIEMSIX_VECT151_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT151_MSG_DATA 0x1a25e +#define regPCIEMSIX_VECT151_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT151_CONTROL 0x1a25f +#define regPCIEMSIX_VECT151_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT152_ADDR_LO 0x1a260 +#define regPCIEMSIX_VECT152_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT152_ADDR_HI 0x1a261 +#define regPCIEMSIX_VECT152_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT152_MSG_DATA 0x1a262 +#define regPCIEMSIX_VECT152_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT152_CONTROL 0x1a263 +#define regPCIEMSIX_VECT152_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT153_ADDR_LO 0x1a264 +#define regPCIEMSIX_VECT153_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT153_ADDR_HI 0x1a265 +#define regPCIEMSIX_VECT153_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT153_MSG_DATA 0x1a266 +#define regPCIEMSIX_VECT153_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT153_CONTROL 0x1a267 +#define regPCIEMSIX_VECT153_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT154_ADDR_LO 0x1a268 +#define regPCIEMSIX_VECT154_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT154_ADDR_HI 0x1a269 +#define regPCIEMSIX_VECT154_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT154_MSG_DATA 0x1a26a +#define regPCIEMSIX_VECT154_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT154_CONTROL 0x1a26b +#define regPCIEMSIX_VECT154_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT155_ADDR_LO 0x1a26c +#define regPCIEMSIX_VECT155_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT155_ADDR_HI 0x1a26d +#define regPCIEMSIX_VECT155_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT155_MSG_DATA 0x1a26e +#define regPCIEMSIX_VECT155_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT155_CONTROL 0x1a26f +#define regPCIEMSIX_VECT155_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT156_ADDR_LO 0x1a270 +#define regPCIEMSIX_VECT156_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT156_ADDR_HI 0x1a271 +#define regPCIEMSIX_VECT156_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT156_MSG_DATA 0x1a272 +#define regPCIEMSIX_VECT156_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT156_CONTROL 0x1a273 +#define regPCIEMSIX_VECT156_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT157_ADDR_LO 0x1a274 +#define regPCIEMSIX_VECT157_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT157_ADDR_HI 0x1a275 +#define regPCIEMSIX_VECT157_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT157_MSG_DATA 0x1a276 +#define regPCIEMSIX_VECT157_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT157_CONTROL 0x1a277 +#define regPCIEMSIX_VECT157_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT158_ADDR_LO 0x1a278 +#define regPCIEMSIX_VECT158_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT158_ADDR_HI 0x1a279 +#define regPCIEMSIX_VECT158_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT158_MSG_DATA 0x1a27a +#define regPCIEMSIX_VECT158_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT158_CONTROL 0x1a27b +#define regPCIEMSIX_VECT158_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT159_ADDR_LO 0x1a27c +#define regPCIEMSIX_VECT159_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT159_ADDR_HI 0x1a27d +#define regPCIEMSIX_VECT159_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT159_MSG_DATA 0x1a27e +#define regPCIEMSIX_VECT159_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT159_CONTROL 0x1a27f +#define regPCIEMSIX_VECT159_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT160_ADDR_LO 0x1a280 +#define regPCIEMSIX_VECT160_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT160_ADDR_HI 0x1a281 +#define regPCIEMSIX_VECT160_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT160_MSG_DATA 0x1a282 +#define regPCIEMSIX_VECT160_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT160_CONTROL 0x1a283 +#define regPCIEMSIX_VECT160_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT161_ADDR_LO 0x1a284 +#define regPCIEMSIX_VECT161_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT161_ADDR_HI 0x1a285 +#define regPCIEMSIX_VECT161_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT161_MSG_DATA 0x1a286 +#define regPCIEMSIX_VECT161_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT161_CONTROL 0x1a287 +#define regPCIEMSIX_VECT161_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT162_ADDR_LO 0x1a288 +#define regPCIEMSIX_VECT162_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT162_ADDR_HI 0x1a289 +#define regPCIEMSIX_VECT162_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT162_MSG_DATA 0x1a28a +#define regPCIEMSIX_VECT162_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT162_CONTROL 0x1a28b +#define regPCIEMSIX_VECT162_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT163_ADDR_LO 0x1a28c +#define regPCIEMSIX_VECT163_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT163_ADDR_HI 0x1a28d +#define regPCIEMSIX_VECT163_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT163_MSG_DATA 0x1a28e +#define regPCIEMSIX_VECT163_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT163_CONTROL 0x1a28f +#define regPCIEMSIX_VECT163_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT164_ADDR_LO 0x1a290 +#define regPCIEMSIX_VECT164_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT164_ADDR_HI 0x1a291 +#define regPCIEMSIX_VECT164_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT164_MSG_DATA 0x1a292 +#define regPCIEMSIX_VECT164_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT164_CONTROL 0x1a293 +#define regPCIEMSIX_VECT164_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT165_ADDR_LO 0x1a294 +#define regPCIEMSIX_VECT165_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT165_ADDR_HI 0x1a295 +#define regPCIEMSIX_VECT165_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT165_MSG_DATA 0x1a296 +#define regPCIEMSIX_VECT165_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT165_CONTROL 0x1a297 +#define regPCIEMSIX_VECT165_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT166_ADDR_LO 0x1a298 +#define regPCIEMSIX_VECT166_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT166_ADDR_HI 0x1a299 +#define regPCIEMSIX_VECT166_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT166_MSG_DATA 0x1a29a +#define regPCIEMSIX_VECT166_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT166_CONTROL 0x1a29b +#define regPCIEMSIX_VECT166_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT167_ADDR_LO 0x1a29c +#define regPCIEMSIX_VECT167_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT167_ADDR_HI 0x1a29d +#define regPCIEMSIX_VECT167_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT167_MSG_DATA 0x1a29e +#define regPCIEMSIX_VECT167_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT167_CONTROL 0x1a29f +#define regPCIEMSIX_VECT167_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT168_ADDR_LO 0x1a2a0 +#define regPCIEMSIX_VECT168_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT168_ADDR_HI 0x1a2a1 +#define regPCIEMSIX_VECT168_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT168_MSG_DATA 0x1a2a2 +#define regPCIEMSIX_VECT168_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT168_CONTROL 0x1a2a3 +#define regPCIEMSIX_VECT168_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT169_ADDR_LO 0x1a2a4 +#define regPCIEMSIX_VECT169_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT169_ADDR_HI 0x1a2a5 +#define regPCIEMSIX_VECT169_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT169_MSG_DATA 0x1a2a6 +#define regPCIEMSIX_VECT169_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT169_CONTROL 0x1a2a7 +#define regPCIEMSIX_VECT169_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT170_ADDR_LO 0x1a2a8 +#define regPCIEMSIX_VECT170_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT170_ADDR_HI 0x1a2a9 +#define regPCIEMSIX_VECT170_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT170_MSG_DATA 0x1a2aa +#define regPCIEMSIX_VECT170_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT170_CONTROL 0x1a2ab +#define regPCIEMSIX_VECT170_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT171_ADDR_LO 0x1a2ac +#define regPCIEMSIX_VECT171_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT171_ADDR_HI 0x1a2ad +#define regPCIEMSIX_VECT171_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT171_MSG_DATA 0x1a2ae +#define regPCIEMSIX_VECT171_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT171_CONTROL 0x1a2af +#define regPCIEMSIX_VECT171_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT172_ADDR_LO 0x1a2b0 +#define regPCIEMSIX_VECT172_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT172_ADDR_HI 0x1a2b1 +#define regPCIEMSIX_VECT172_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT172_MSG_DATA 0x1a2b2 +#define regPCIEMSIX_VECT172_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT172_CONTROL 0x1a2b3 +#define regPCIEMSIX_VECT172_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT173_ADDR_LO 0x1a2b4 +#define regPCIEMSIX_VECT173_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT173_ADDR_HI 0x1a2b5 +#define regPCIEMSIX_VECT173_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT173_MSG_DATA 0x1a2b6 +#define regPCIEMSIX_VECT173_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT173_CONTROL 0x1a2b7 +#define regPCIEMSIX_VECT173_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT174_ADDR_LO 0x1a2b8 +#define regPCIEMSIX_VECT174_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT174_ADDR_HI 0x1a2b9 +#define regPCIEMSIX_VECT174_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT174_MSG_DATA 0x1a2ba +#define regPCIEMSIX_VECT174_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT174_CONTROL 0x1a2bb +#define regPCIEMSIX_VECT174_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT175_ADDR_LO 0x1a2bc +#define regPCIEMSIX_VECT175_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT175_ADDR_HI 0x1a2bd +#define regPCIEMSIX_VECT175_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT175_MSG_DATA 0x1a2be +#define regPCIEMSIX_VECT175_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT175_CONTROL 0x1a2bf +#define regPCIEMSIX_VECT175_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT176_ADDR_LO 0x1a2c0 +#define regPCIEMSIX_VECT176_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT176_ADDR_HI 0x1a2c1 +#define regPCIEMSIX_VECT176_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT176_MSG_DATA 0x1a2c2 +#define regPCIEMSIX_VECT176_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT176_CONTROL 0x1a2c3 +#define regPCIEMSIX_VECT176_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT177_ADDR_LO 0x1a2c4 +#define regPCIEMSIX_VECT177_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT177_ADDR_HI 0x1a2c5 +#define regPCIEMSIX_VECT177_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT177_MSG_DATA 0x1a2c6 +#define regPCIEMSIX_VECT177_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT177_CONTROL 0x1a2c7 +#define regPCIEMSIX_VECT177_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT178_ADDR_LO 0x1a2c8 +#define regPCIEMSIX_VECT178_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT178_ADDR_HI 0x1a2c9 +#define regPCIEMSIX_VECT178_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT178_MSG_DATA 0x1a2ca +#define regPCIEMSIX_VECT178_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT178_CONTROL 0x1a2cb +#define regPCIEMSIX_VECT178_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT179_ADDR_LO 0x1a2cc +#define regPCIEMSIX_VECT179_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT179_ADDR_HI 0x1a2cd +#define regPCIEMSIX_VECT179_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT179_MSG_DATA 0x1a2ce +#define regPCIEMSIX_VECT179_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT179_CONTROL 0x1a2cf +#define regPCIEMSIX_VECT179_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT180_ADDR_LO 0x1a2d0 +#define regPCIEMSIX_VECT180_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT180_ADDR_HI 0x1a2d1 +#define regPCIEMSIX_VECT180_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT180_MSG_DATA 0x1a2d2 +#define regPCIEMSIX_VECT180_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT180_CONTROL 0x1a2d3 +#define regPCIEMSIX_VECT180_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT181_ADDR_LO 0x1a2d4 +#define regPCIEMSIX_VECT181_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT181_ADDR_HI 0x1a2d5 +#define regPCIEMSIX_VECT181_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT181_MSG_DATA 0x1a2d6 +#define regPCIEMSIX_VECT181_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT181_CONTROL 0x1a2d7 +#define regPCIEMSIX_VECT181_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT182_ADDR_LO 0x1a2d8 +#define regPCIEMSIX_VECT182_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT182_ADDR_HI 0x1a2d9 +#define regPCIEMSIX_VECT182_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT182_MSG_DATA 0x1a2da +#define regPCIEMSIX_VECT182_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT182_CONTROL 0x1a2db +#define regPCIEMSIX_VECT182_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT183_ADDR_LO 0x1a2dc +#define regPCIEMSIX_VECT183_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT183_ADDR_HI 0x1a2dd +#define regPCIEMSIX_VECT183_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT183_MSG_DATA 0x1a2de +#define regPCIEMSIX_VECT183_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT183_CONTROL 0x1a2df +#define regPCIEMSIX_VECT183_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT184_ADDR_LO 0x1a2e0 +#define regPCIEMSIX_VECT184_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT184_ADDR_HI 0x1a2e1 +#define regPCIEMSIX_VECT184_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT184_MSG_DATA 0x1a2e2 +#define regPCIEMSIX_VECT184_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT184_CONTROL 0x1a2e3 +#define regPCIEMSIX_VECT184_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT185_ADDR_LO 0x1a2e4 +#define regPCIEMSIX_VECT185_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT185_ADDR_HI 0x1a2e5 +#define regPCIEMSIX_VECT185_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT185_MSG_DATA 0x1a2e6 +#define regPCIEMSIX_VECT185_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT185_CONTROL 0x1a2e7 +#define regPCIEMSIX_VECT185_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT186_ADDR_LO 0x1a2e8 +#define regPCIEMSIX_VECT186_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT186_ADDR_HI 0x1a2e9 +#define regPCIEMSIX_VECT186_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT186_MSG_DATA 0x1a2ea +#define regPCIEMSIX_VECT186_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT186_CONTROL 0x1a2eb +#define regPCIEMSIX_VECT186_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT187_ADDR_LO 0x1a2ec +#define regPCIEMSIX_VECT187_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT187_ADDR_HI 0x1a2ed +#define regPCIEMSIX_VECT187_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT187_MSG_DATA 0x1a2ee +#define regPCIEMSIX_VECT187_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT187_CONTROL 0x1a2ef +#define regPCIEMSIX_VECT187_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT188_ADDR_LO 0x1a2f0 +#define regPCIEMSIX_VECT188_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT188_ADDR_HI 0x1a2f1 +#define regPCIEMSIX_VECT188_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT188_MSG_DATA 0x1a2f2 +#define regPCIEMSIX_VECT188_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT188_CONTROL 0x1a2f3 +#define regPCIEMSIX_VECT188_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT189_ADDR_LO 0x1a2f4 +#define regPCIEMSIX_VECT189_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT189_ADDR_HI 0x1a2f5 +#define regPCIEMSIX_VECT189_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT189_MSG_DATA 0x1a2f6 +#define regPCIEMSIX_VECT189_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT189_CONTROL 0x1a2f7 +#define regPCIEMSIX_VECT189_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT190_ADDR_LO 0x1a2f8 +#define regPCIEMSIX_VECT190_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT190_ADDR_HI 0x1a2f9 +#define regPCIEMSIX_VECT190_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT190_MSG_DATA 0x1a2fa +#define regPCIEMSIX_VECT190_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT190_CONTROL 0x1a2fb +#define regPCIEMSIX_VECT190_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT191_ADDR_LO 0x1a2fc +#define regPCIEMSIX_VECT191_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT191_ADDR_HI 0x1a2fd +#define regPCIEMSIX_VECT191_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT191_MSG_DATA 0x1a2fe +#define regPCIEMSIX_VECT191_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT191_CONTROL 0x1a2ff +#define regPCIEMSIX_VECT191_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT192_ADDR_LO 0x1a300 +#define regPCIEMSIX_VECT192_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT192_ADDR_HI 0x1a301 +#define regPCIEMSIX_VECT192_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT192_MSG_DATA 0x1a302 +#define regPCIEMSIX_VECT192_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT192_CONTROL 0x1a303 +#define regPCIEMSIX_VECT192_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT193_ADDR_LO 0x1a304 +#define regPCIEMSIX_VECT193_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT193_ADDR_HI 0x1a305 +#define regPCIEMSIX_VECT193_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT193_MSG_DATA 0x1a306 +#define regPCIEMSIX_VECT193_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT193_CONTROL 0x1a307 +#define regPCIEMSIX_VECT193_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT194_ADDR_LO 0x1a308 +#define regPCIEMSIX_VECT194_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT194_ADDR_HI 0x1a309 +#define regPCIEMSIX_VECT194_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT194_MSG_DATA 0x1a30a +#define regPCIEMSIX_VECT194_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT194_CONTROL 0x1a30b +#define regPCIEMSIX_VECT194_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT195_ADDR_LO 0x1a30c +#define regPCIEMSIX_VECT195_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT195_ADDR_HI 0x1a30d +#define regPCIEMSIX_VECT195_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT195_MSG_DATA 0x1a30e +#define regPCIEMSIX_VECT195_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT195_CONTROL 0x1a30f +#define regPCIEMSIX_VECT195_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT196_ADDR_LO 0x1a310 +#define regPCIEMSIX_VECT196_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT196_ADDR_HI 0x1a311 +#define regPCIEMSIX_VECT196_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT196_MSG_DATA 0x1a312 +#define regPCIEMSIX_VECT196_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT196_CONTROL 0x1a313 +#define regPCIEMSIX_VECT196_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT197_ADDR_LO 0x1a314 +#define regPCIEMSIX_VECT197_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT197_ADDR_HI 0x1a315 +#define regPCIEMSIX_VECT197_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT197_MSG_DATA 0x1a316 +#define regPCIEMSIX_VECT197_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT197_CONTROL 0x1a317 +#define regPCIEMSIX_VECT197_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT198_ADDR_LO 0x1a318 +#define regPCIEMSIX_VECT198_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT198_ADDR_HI 0x1a319 +#define regPCIEMSIX_VECT198_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT198_MSG_DATA 0x1a31a +#define regPCIEMSIX_VECT198_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT198_CONTROL 0x1a31b +#define regPCIEMSIX_VECT198_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT199_ADDR_LO 0x1a31c +#define regPCIEMSIX_VECT199_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT199_ADDR_HI 0x1a31d +#define regPCIEMSIX_VECT199_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT199_MSG_DATA 0x1a31e +#define regPCIEMSIX_VECT199_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT199_CONTROL 0x1a31f +#define regPCIEMSIX_VECT199_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT200_ADDR_LO 0x1a320 +#define regPCIEMSIX_VECT200_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT200_ADDR_HI 0x1a321 +#define regPCIEMSIX_VECT200_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT200_MSG_DATA 0x1a322 +#define regPCIEMSIX_VECT200_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT200_CONTROL 0x1a323 +#define regPCIEMSIX_VECT200_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT201_ADDR_LO 0x1a324 +#define regPCIEMSIX_VECT201_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT201_ADDR_HI 0x1a325 +#define regPCIEMSIX_VECT201_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT201_MSG_DATA 0x1a326 +#define regPCIEMSIX_VECT201_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT201_CONTROL 0x1a327 +#define regPCIEMSIX_VECT201_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT202_ADDR_LO 0x1a328 +#define regPCIEMSIX_VECT202_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT202_ADDR_HI 0x1a329 +#define regPCIEMSIX_VECT202_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT202_MSG_DATA 0x1a32a +#define regPCIEMSIX_VECT202_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT202_CONTROL 0x1a32b +#define regPCIEMSIX_VECT202_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT203_ADDR_LO 0x1a32c +#define regPCIEMSIX_VECT203_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT203_ADDR_HI 0x1a32d +#define regPCIEMSIX_VECT203_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT203_MSG_DATA 0x1a32e +#define regPCIEMSIX_VECT203_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT203_CONTROL 0x1a32f +#define regPCIEMSIX_VECT203_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT204_ADDR_LO 0x1a330 +#define regPCIEMSIX_VECT204_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT204_ADDR_HI 0x1a331 +#define regPCIEMSIX_VECT204_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT204_MSG_DATA 0x1a332 +#define regPCIEMSIX_VECT204_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT204_CONTROL 0x1a333 +#define regPCIEMSIX_VECT204_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT205_ADDR_LO 0x1a334 +#define regPCIEMSIX_VECT205_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT205_ADDR_HI 0x1a335 +#define regPCIEMSIX_VECT205_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT205_MSG_DATA 0x1a336 +#define regPCIEMSIX_VECT205_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT205_CONTROL 0x1a337 +#define regPCIEMSIX_VECT205_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT206_ADDR_LO 0x1a338 +#define regPCIEMSIX_VECT206_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT206_ADDR_HI 0x1a339 +#define regPCIEMSIX_VECT206_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT206_MSG_DATA 0x1a33a +#define regPCIEMSIX_VECT206_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT206_CONTROL 0x1a33b +#define regPCIEMSIX_VECT206_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT207_ADDR_LO 0x1a33c +#define regPCIEMSIX_VECT207_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT207_ADDR_HI 0x1a33d +#define regPCIEMSIX_VECT207_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT207_MSG_DATA 0x1a33e +#define regPCIEMSIX_VECT207_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT207_CONTROL 0x1a33f +#define regPCIEMSIX_VECT207_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT208_ADDR_LO 0x1a340 +#define regPCIEMSIX_VECT208_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT208_ADDR_HI 0x1a341 +#define regPCIEMSIX_VECT208_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT208_MSG_DATA 0x1a342 +#define regPCIEMSIX_VECT208_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT208_CONTROL 0x1a343 +#define regPCIEMSIX_VECT208_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT209_ADDR_LO 0x1a344 +#define regPCIEMSIX_VECT209_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT209_ADDR_HI 0x1a345 +#define regPCIEMSIX_VECT209_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT209_MSG_DATA 0x1a346 +#define regPCIEMSIX_VECT209_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT209_CONTROL 0x1a347 +#define regPCIEMSIX_VECT209_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT210_ADDR_LO 0x1a348 +#define regPCIEMSIX_VECT210_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT210_ADDR_HI 0x1a349 +#define regPCIEMSIX_VECT210_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT210_MSG_DATA 0x1a34a +#define regPCIEMSIX_VECT210_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT210_CONTROL 0x1a34b +#define regPCIEMSIX_VECT210_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT211_ADDR_LO 0x1a34c +#define regPCIEMSIX_VECT211_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT211_ADDR_HI 0x1a34d +#define regPCIEMSIX_VECT211_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT211_MSG_DATA 0x1a34e +#define regPCIEMSIX_VECT211_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT211_CONTROL 0x1a34f +#define regPCIEMSIX_VECT211_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT212_ADDR_LO 0x1a350 +#define regPCIEMSIX_VECT212_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT212_ADDR_HI 0x1a351 +#define regPCIEMSIX_VECT212_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT212_MSG_DATA 0x1a352 +#define regPCIEMSIX_VECT212_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT212_CONTROL 0x1a353 +#define regPCIEMSIX_VECT212_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT213_ADDR_LO 0x1a354 +#define regPCIEMSIX_VECT213_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT213_ADDR_HI 0x1a355 +#define regPCIEMSIX_VECT213_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT213_MSG_DATA 0x1a356 +#define regPCIEMSIX_VECT213_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT213_CONTROL 0x1a357 +#define regPCIEMSIX_VECT213_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT214_ADDR_LO 0x1a358 +#define regPCIEMSIX_VECT214_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT214_ADDR_HI 0x1a359 +#define regPCIEMSIX_VECT214_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT214_MSG_DATA 0x1a35a +#define regPCIEMSIX_VECT214_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT214_CONTROL 0x1a35b +#define regPCIEMSIX_VECT214_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT215_ADDR_LO 0x1a35c +#define regPCIEMSIX_VECT215_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT215_ADDR_HI 0x1a35d +#define regPCIEMSIX_VECT215_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT215_MSG_DATA 0x1a35e +#define regPCIEMSIX_VECT215_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT215_CONTROL 0x1a35f +#define regPCIEMSIX_VECT215_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT216_ADDR_LO 0x1a360 +#define regPCIEMSIX_VECT216_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT216_ADDR_HI 0x1a361 +#define regPCIEMSIX_VECT216_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT216_MSG_DATA 0x1a362 +#define regPCIEMSIX_VECT216_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT216_CONTROL 0x1a363 +#define regPCIEMSIX_VECT216_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT217_ADDR_LO 0x1a364 +#define regPCIEMSIX_VECT217_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT217_ADDR_HI 0x1a365 +#define regPCIEMSIX_VECT217_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT217_MSG_DATA 0x1a366 +#define regPCIEMSIX_VECT217_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT217_CONTROL 0x1a367 +#define regPCIEMSIX_VECT217_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT218_ADDR_LO 0x1a368 +#define regPCIEMSIX_VECT218_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT218_ADDR_HI 0x1a369 +#define regPCIEMSIX_VECT218_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT218_MSG_DATA 0x1a36a +#define regPCIEMSIX_VECT218_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT218_CONTROL 0x1a36b +#define regPCIEMSIX_VECT218_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT219_ADDR_LO 0x1a36c +#define regPCIEMSIX_VECT219_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT219_ADDR_HI 0x1a36d +#define regPCIEMSIX_VECT219_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT219_MSG_DATA 0x1a36e +#define regPCIEMSIX_VECT219_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT219_CONTROL 0x1a36f +#define regPCIEMSIX_VECT219_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT220_ADDR_LO 0x1a370 +#define regPCIEMSIX_VECT220_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT220_ADDR_HI 0x1a371 +#define regPCIEMSIX_VECT220_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT220_MSG_DATA 0x1a372 +#define regPCIEMSIX_VECT220_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT220_CONTROL 0x1a373 +#define regPCIEMSIX_VECT220_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT221_ADDR_LO 0x1a374 +#define regPCIEMSIX_VECT221_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT221_ADDR_HI 0x1a375 +#define regPCIEMSIX_VECT221_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT221_MSG_DATA 0x1a376 +#define regPCIEMSIX_VECT221_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT221_CONTROL 0x1a377 +#define regPCIEMSIX_VECT221_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT222_ADDR_LO 0x1a378 +#define regPCIEMSIX_VECT222_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT222_ADDR_HI 0x1a379 +#define regPCIEMSIX_VECT222_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT222_MSG_DATA 0x1a37a +#define regPCIEMSIX_VECT222_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT222_CONTROL 0x1a37b +#define regPCIEMSIX_VECT222_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT223_ADDR_LO 0x1a37c +#define regPCIEMSIX_VECT223_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT223_ADDR_HI 0x1a37d +#define regPCIEMSIX_VECT223_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT223_MSG_DATA 0x1a37e +#define regPCIEMSIX_VECT223_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT223_CONTROL 0x1a37f +#define regPCIEMSIX_VECT223_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT224_ADDR_LO 0x1a380 +#define regPCIEMSIX_VECT224_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT224_ADDR_HI 0x1a381 +#define regPCIEMSIX_VECT224_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT224_MSG_DATA 0x1a382 +#define regPCIEMSIX_VECT224_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT224_CONTROL 0x1a383 +#define regPCIEMSIX_VECT224_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT225_ADDR_LO 0x1a384 +#define regPCIEMSIX_VECT225_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT225_ADDR_HI 0x1a385 +#define regPCIEMSIX_VECT225_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT225_MSG_DATA 0x1a386 +#define regPCIEMSIX_VECT225_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT225_CONTROL 0x1a387 +#define regPCIEMSIX_VECT225_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT226_ADDR_LO 0x1a388 +#define regPCIEMSIX_VECT226_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT226_ADDR_HI 0x1a389 +#define regPCIEMSIX_VECT226_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT226_MSG_DATA 0x1a38a +#define regPCIEMSIX_VECT226_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT226_CONTROL 0x1a38b +#define regPCIEMSIX_VECT226_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT227_ADDR_LO 0x1a38c +#define regPCIEMSIX_VECT227_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT227_ADDR_HI 0x1a38d +#define regPCIEMSIX_VECT227_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT227_MSG_DATA 0x1a38e +#define regPCIEMSIX_VECT227_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT227_CONTROL 0x1a38f +#define regPCIEMSIX_VECT227_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT228_ADDR_LO 0x1a390 +#define regPCIEMSIX_VECT228_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT228_ADDR_HI 0x1a391 +#define regPCIEMSIX_VECT228_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT228_MSG_DATA 0x1a392 +#define regPCIEMSIX_VECT228_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT228_CONTROL 0x1a393 +#define regPCIEMSIX_VECT228_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT229_ADDR_LO 0x1a394 +#define regPCIEMSIX_VECT229_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT229_ADDR_HI 0x1a395 +#define regPCIEMSIX_VECT229_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT229_MSG_DATA 0x1a396 +#define regPCIEMSIX_VECT229_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT229_CONTROL 0x1a397 +#define regPCIEMSIX_VECT229_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT230_ADDR_LO 0x1a398 +#define regPCIEMSIX_VECT230_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT230_ADDR_HI 0x1a399 +#define regPCIEMSIX_VECT230_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT230_MSG_DATA 0x1a39a +#define regPCIEMSIX_VECT230_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT230_CONTROL 0x1a39b +#define regPCIEMSIX_VECT230_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT231_ADDR_LO 0x1a39c +#define regPCIEMSIX_VECT231_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT231_ADDR_HI 0x1a39d +#define regPCIEMSIX_VECT231_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT231_MSG_DATA 0x1a39e +#define regPCIEMSIX_VECT231_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT231_CONTROL 0x1a39f +#define regPCIEMSIX_VECT231_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT232_ADDR_LO 0x1a3a0 +#define regPCIEMSIX_VECT232_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT232_ADDR_HI 0x1a3a1 +#define regPCIEMSIX_VECT232_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT232_MSG_DATA 0x1a3a2 +#define regPCIEMSIX_VECT232_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT232_CONTROL 0x1a3a3 +#define regPCIEMSIX_VECT232_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT233_ADDR_LO 0x1a3a4 +#define regPCIEMSIX_VECT233_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT233_ADDR_HI 0x1a3a5 +#define regPCIEMSIX_VECT233_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT233_MSG_DATA 0x1a3a6 +#define regPCIEMSIX_VECT233_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT233_CONTROL 0x1a3a7 +#define regPCIEMSIX_VECT233_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT234_ADDR_LO 0x1a3a8 +#define regPCIEMSIX_VECT234_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT234_ADDR_HI 0x1a3a9 +#define regPCIEMSIX_VECT234_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT234_MSG_DATA 0x1a3aa +#define regPCIEMSIX_VECT234_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT234_CONTROL 0x1a3ab +#define regPCIEMSIX_VECT234_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT235_ADDR_LO 0x1a3ac +#define regPCIEMSIX_VECT235_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT235_ADDR_HI 0x1a3ad +#define regPCIEMSIX_VECT235_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT235_MSG_DATA 0x1a3ae +#define regPCIEMSIX_VECT235_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT235_CONTROL 0x1a3af +#define regPCIEMSIX_VECT235_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT236_ADDR_LO 0x1a3b0 +#define regPCIEMSIX_VECT236_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT236_ADDR_HI 0x1a3b1 +#define regPCIEMSIX_VECT236_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT236_MSG_DATA 0x1a3b2 +#define regPCIEMSIX_VECT236_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT236_CONTROL 0x1a3b3 +#define regPCIEMSIX_VECT236_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT237_ADDR_LO 0x1a3b4 +#define regPCIEMSIX_VECT237_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT237_ADDR_HI 0x1a3b5 +#define regPCIEMSIX_VECT237_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT237_MSG_DATA 0x1a3b6 +#define regPCIEMSIX_VECT237_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT237_CONTROL 0x1a3b7 +#define regPCIEMSIX_VECT237_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT238_ADDR_LO 0x1a3b8 +#define regPCIEMSIX_VECT238_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT238_ADDR_HI 0x1a3b9 +#define regPCIEMSIX_VECT238_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT238_MSG_DATA 0x1a3ba +#define regPCIEMSIX_VECT238_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT238_CONTROL 0x1a3bb +#define regPCIEMSIX_VECT238_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT239_ADDR_LO 0x1a3bc +#define regPCIEMSIX_VECT239_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT239_ADDR_HI 0x1a3bd +#define regPCIEMSIX_VECT239_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT239_MSG_DATA 0x1a3be +#define regPCIEMSIX_VECT239_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT239_CONTROL 0x1a3bf +#define regPCIEMSIX_VECT239_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT240_ADDR_LO 0x1a3c0 +#define regPCIEMSIX_VECT240_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT240_ADDR_HI 0x1a3c1 +#define regPCIEMSIX_VECT240_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT240_MSG_DATA 0x1a3c2 +#define regPCIEMSIX_VECT240_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT240_CONTROL 0x1a3c3 +#define regPCIEMSIX_VECT240_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT241_ADDR_LO 0x1a3c4 +#define regPCIEMSIX_VECT241_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT241_ADDR_HI 0x1a3c5 +#define regPCIEMSIX_VECT241_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT241_MSG_DATA 0x1a3c6 +#define regPCIEMSIX_VECT241_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT241_CONTROL 0x1a3c7 +#define regPCIEMSIX_VECT241_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT242_ADDR_LO 0x1a3c8 +#define regPCIEMSIX_VECT242_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT242_ADDR_HI 0x1a3c9 +#define regPCIEMSIX_VECT242_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT242_MSG_DATA 0x1a3ca +#define regPCIEMSIX_VECT242_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT242_CONTROL 0x1a3cb +#define regPCIEMSIX_VECT242_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT243_ADDR_LO 0x1a3cc +#define regPCIEMSIX_VECT243_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT243_ADDR_HI 0x1a3cd +#define regPCIEMSIX_VECT243_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT243_MSG_DATA 0x1a3ce +#define regPCIEMSIX_VECT243_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT243_CONTROL 0x1a3cf +#define regPCIEMSIX_VECT243_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT244_ADDR_LO 0x1a3d0 +#define regPCIEMSIX_VECT244_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT244_ADDR_HI 0x1a3d1 +#define regPCIEMSIX_VECT244_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT244_MSG_DATA 0x1a3d2 +#define regPCIEMSIX_VECT244_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT244_CONTROL 0x1a3d3 +#define regPCIEMSIX_VECT244_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT245_ADDR_LO 0x1a3d4 +#define regPCIEMSIX_VECT245_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT245_ADDR_HI 0x1a3d5 +#define regPCIEMSIX_VECT245_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT245_MSG_DATA 0x1a3d6 +#define regPCIEMSIX_VECT245_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT245_CONTROL 0x1a3d7 +#define regPCIEMSIX_VECT245_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT246_ADDR_LO 0x1a3d8 +#define regPCIEMSIX_VECT246_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT246_ADDR_HI 0x1a3d9 +#define regPCIEMSIX_VECT246_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT246_MSG_DATA 0x1a3da +#define regPCIEMSIX_VECT246_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT246_CONTROL 0x1a3db +#define regPCIEMSIX_VECT246_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT247_ADDR_LO 0x1a3dc +#define regPCIEMSIX_VECT247_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT247_ADDR_HI 0x1a3dd +#define regPCIEMSIX_VECT247_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT247_MSG_DATA 0x1a3de +#define regPCIEMSIX_VECT247_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT247_CONTROL 0x1a3df +#define regPCIEMSIX_VECT247_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT248_ADDR_LO 0x1a3e0 +#define regPCIEMSIX_VECT248_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT248_ADDR_HI 0x1a3e1 +#define regPCIEMSIX_VECT248_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT248_MSG_DATA 0x1a3e2 +#define regPCIEMSIX_VECT248_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT248_CONTROL 0x1a3e3 +#define regPCIEMSIX_VECT248_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT249_ADDR_LO 0x1a3e4 +#define regPCIEMSIX_VECT249_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT249_ADDR_HI 0x1a3e5 +#define regPCIEMSIX_VECT249_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT249_MSG_DATA 0x1a3e6 +#define regPCIEMSIX_VECT249_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT249_CONTROL 0x1a3e7 +#define regPCIEMSIX_VECT249_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT250_ADDR_LO 0x1a3e8 +#define regPCIEMSIX_VECT250_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT250_ADDR_HI 0x1a3e9 +#define regPCIEMSIX_VECT250_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT250_MSG_DATA 0x1a3ea +#define regPCIEMSIX_VECT250_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT250_CONTROL 0x1a3eb +#define regPCIEMSIX_VECT250_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT251_ADDR_LO 0x1a3ec +#define regPCIEMSIX_VECT251_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT251_ADDR_HI 0x1a3ed +#define regPCIEMSIX_VECT251_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT251_MSG_DATA 0x1a3ee +#define regPCIEMSIX_VECT251_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT251_CONTROL 0x1a3ef +#define regPCIEMSIX_VECT251_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT252_ADDR_LO 0x1a3f0 +#define regPCIEMSIX_VECT252_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT252_ADDR_HI 0x1a3f1 +#define regPCIEMSIX_VECT252_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT252_MSG_DATA 0x1a3f2 +#define regPCIEMSIX_VECT252_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT252_CONTROL 0x1a3f3 +#define regPCIEMSIX_VECT252_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT253_ADDR_LO 0x1a3f4 +#define regPCIEMSIX_VECT253_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT253_ADDR_HI 0x1a3f5 +#define regPCIEMSIX_VECT253_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT253_MSG_DATA 0x1a3f6 +#define regPCIEMSIX_VECT253_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT253_CONTROL 0x1a3f7 +#define regPCIEMSIX_VECT253_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT254_ADDR_LO 0x1a3f8 +#define regPCIEMSIX_VECT254_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT254_ADDR_HI 0x1a3f9 +#define regPCIEMSIX_VECT254_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT254_MSG_DATA 0x1a3fa +#define regPCIEMSIX_VECT254_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT254_CONTROL 0x1a3fb +#define regPCIEMSIX_VECT254_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT255_ADDR_LO 0x1a3fc +#define regPCIEMSIX_VECT255_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT255_ADDR_HI 0x1a3fd +#define regPCIEMSIX_VECT255_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT255_MSG_DATA 0x1a3fe +#define regPCIEMSIX_VECT255_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT255_CONTROL 0x1a3ff +#define regPCIEMSIX_VECT255_CONTROL_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_pciemsix_0_usb_MSIXPDEC +// base address: 0x10169000 +#define regPCIEMSIX_PBA_0 0x1a400 +#define regPCIEMSIX_PBA_0_BASE_IDX 8 +#define regPCIEMSIX_PBA_1 0x1a401 +#define regPCIEMSIX_PBA_1_BASE_IDX 8 +#define regPCIEMSIX_PBA_2 0x1a402 +#define regPCIEMSIX_PBA_2_BASE_IDX 8 +#define regPCIEMSIX_PBA_3 0x1a403 +#define regPCIEMSIX_PBA_3_BASE_IDX 8 +#define regPCIEMSIX_PBA_4 0x1a404 +#define regPCIEMSIX_PBA_4_BASE_IDX 8 +#define regPCIEMSIX_PBA_5 0x1a405 +#define regPCIEMSIX_PBA_5_BASE_IDX 8 +#define regPCIEMSIX_PBA_6 0x1a406 +#define regPCIEMSIX_PBA_6_BASE_IDX 8 +#define regPCIEMSIX_PBA_7 0x1a407 +#define regPCIEMSIX_PBA_7_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_swus_SUMDEC +// base address: 0x1013b000 +#define regSUM_INDEX 0xec38 +#define regSUM_INDEX_BASE_IDX 8 +#define regSUM_DATA 0xec39 +#define regSUM_DATA_BASE_IDX 8 +#define regSUM_INDEX_HI 0xec3b +#define regSUM_INDEX_HI_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_strap_rcc_strap_internal +// base address: 0x10100000 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0 0xc400 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1 0xc401 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2 0xc402 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3 0xc403 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4 0xc404 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5 0xc405 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6 0xc406 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7 0xc407 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8 0xc408 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9 0xc409 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10 0xc40a +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11 0xc40b +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12 0xc40c +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13 0xc40d +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14 0xc40e +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP0 0xc480 +#define regRCC_DEV1_PORT_STRAP0_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP1 0xc481 +#define regRCC_DEV1_PORT_STRAP1_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP2 0xc482 +#define regRCC_DEV1_PORT_STRAP2_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP3 0xc483 +#define regRCC_DEV1_PORT_STRAP3_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP4 0xc484 +#define regRCC_DEV1_PORT_STRAP4_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP5 0xc485 +#define regRCC_DEV1_PORT_STRAP5_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP6 0xc486 +#define regRCC_DEV1_PORT_STRAP6_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP7 0xc487 +#define regRCC_DEV1_PORT_STRAP7_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP8 0xc488 +#define regRCC_DEV1_PORT_STRAP8_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP9 0xc489 +#define regRCC_DEV1_PORT_STRAP9_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP10 0xc48a +#define regRCC_DEV1_PORT_STRAP10_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP11 0xc48b +#define regRCC_DEV1_PORT_STRAP11_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP12 0xc48c +#define regRCC_DEV1_PORT_STRAP12_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP13 0xc48d +#define regRCC_DEV1_PORT_STRAP13_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP14 0xc48e +#define regRCC_DEV1_PORT_STRAP14_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP0 0xc500 +#define regRCC_DEV2_PORT_STRAP0_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP1 0xc501 +#define regRCC_DEV2_PORT_STRAP1_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP2 0xc502 +#define regRCC_DEV2_PORT_STRAP2_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP3 0xc503 +#define regRCC_DEV2_PORT_STRAP3_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP4 0xc504 +#define regRCC_DEV2_PORT_STRAP4_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP5 0xc505 +#define regRCC_DEV2_PORT_STRAP5_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP6 0xc506 +#define regRCC_DEV2_PORT_STRAP6_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP7 0xc507 +#define regRCC_DEV2_PORT_STRAP7_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP8 0xc508 +#define regRCC_DEV2_PORT_STRAP8_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP9 0xc509 +#define regRCC_DEV2_PORT_STRAP9_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP10 0xc50a +#define regRCC_DEV2_PORT_STRAP10_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP11 0xc50b +#define regRCC_DEV2_PORT_STRAP11_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP12 0xc50c +#define regRCC_DEV2_PORT_STRAP12_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP13 0xc50d +#define regRCC_DEV2_PORT_STRAP13_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP14 0xc50e +#define regRCC_DEV2_PORT_STRAP14_BASE_IDX 8 +#define regRCC_STRAP1_RCC_BIF_STRAP0 0xc600 +#define regRCC_STRAP1_RCC_BIF_STRAP0_BASE_IDX 8 +#define regRCC_STRAP1_RCC_BIF_STRAP1 0xc601 +#define regRCC_STRAP1_RCC_BIF_STRAP1_BASE_IDX 8 +#define regRCC_STRAP1_RCC_BIF_STRAP2 0xc602 +#define regRCC_STRAP1_RCC_BIF_STRAP2_BASE_IDX 8 +#define regRCC_STRAP1_RCC_BIF_STRAP3 0xc603 +#define regRCC_STRAP1_RCC_BIF_STRAP3_BASE_IDX 8 +#define regRCC_STRAP1_RCC_BIF_STRAP4 0xc604 +#define regRCC_STRAP1_RCC_BIF_STRAP4_BASE_IDX 8 +#define regRCC_STRAP1_RCC_BIF_STRAP5 0xc605 +#define regRCC_STRAP1_RCC_BIF_STRAP5_BASE_IDX 8 +#define regRCC_STRAP1_RCC_BIF_STRAP6 0xc606 +#define regRCC_STRAP1_RCC_BIF_STRAP6_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0 0xd000 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1 0xd001 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2 0xd002 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3 0xd003 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4 0xd004 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5 0xd005 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8 0xd008 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9 0xd009 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13 0xd00d +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14 0xd00e +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15 0xd00f +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16 0xd010 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17 0xd011 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18 0xd012 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26 0xd01a +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0 0xd080 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2 0xd082 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3 0xd083 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4 0xd084 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5 0xd085 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6 0xd086 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7 0xd087 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20 0xd094 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21 0xd095 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22 0xd096 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23 0xd097 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24 0xd098 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25 0xd099 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP0 0xd100 +#define regRCC_DEV0_EPF2_STRAP0_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP2 0xd102 +#define regRCC_DEV0_EPF2_STRAP2_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP3 0xd103 +#define regRCC_DEV0_EPF2_STRAP3_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP4 0xd104 +#define regRCC_DEV0_EPF2_STRAP4_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP5 0xd105 +#define regRCC_DEV0_EPF2_STRAP5_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP6 0xd106 +#define regRCC_DEV0_EPF2_STRAP6_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP7 0xd107 +#define regRCC_DEV0_EPF2_STRAP7_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP10 0xd10a +#define regRCC_DEV0_EPF2_STRAP10_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP11 0xd10b +#define regRCC_DEV0_EPF2_STRAP11_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP12 0xd10c +#define regRCC_DEV0_EPF2_STRAP12_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP13 0xd10d +#define regRCC_DEV0_EPF2_STRAP13_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP14 0xd10e +#define regRCC_DEV0_EPF2_STRAP14_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP20 0xd114 +#define regRCC_DEV0_EPF2_STRAP20_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP0 0xd180 +#define regRCC_DEV0_EPF3_STRAP0_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP2 0xd182 +#define regRCC_DEV0_EPF3_STRAP2_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP3 0xd183 +#define regRCC_DEV0_EPF3_STRAP3_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP4 0xd184 +#define regRCC_DEV0_EPF3_STRAP4_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP5 0xd185 +#define regRCC_DEV0_EPF3_STRAP5_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP6 0xd186 +#define regRCC_DEV0_EPF3_STRAP6_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP7 0xd187 +#define regRCC_DEV0_EPF3_STRAP7_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP10 0xd18a +#define regRCC_DEV0_EPF3_STRAP10_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP11 0xd18b +#define regRCC_DEV0_EPF3_STRAP11_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP12 0xd18c +#define regRCC_DEV0_EPF3_STRAP12_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP13 0xd18d +#define regRCC_DEV0_EPF3_STRAP13_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP14 0xd18e +#define regRCC_DEV0_EPF3_STRAP14_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP20 0xd194 +#define regRCC_DEV0_EPF3_STRAP20_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP0 0xd200 +#define regRCC_DEV0_EPF4_STRAP0_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP2 0xd202 +#define regRCC_DEV0_EPF4_STRAP2_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP3 0xd203 +#define regRCC_DEV0_EPF4_STRAP3_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP4 0xd204 +#define regRCC_DEV0_EPF4_STRAP4_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP5 0xd205 +#define regRCC_DEV0_EPF4_STRAP5_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP6 0xd206 +#define regRCC_DEV0_EPF4_STRAP6_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP7 0xd207 +#define regRCC_DEV0_EPF4_STRAP7_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP13 0xd20d +#define regRCC_DEV0_EPF4_STRAP13_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP14 0xd20e +#define regRCC_DEV0_EPF4_STRAP14_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP0 0xd280 +#define regRCC_DEV0_EPF5_STRAP0_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP2 0xd282 +#define regRCC_DEV0_EPF5_STRAP2_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP3 0xd283 +#define regRCC_DEV0_EPF5_STRAP3_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP4 0xd284 +#define regRCC_DEV0_EPF5_STRAP4_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP5 0xd285 +#define regRCC_DEV0_EPF5_STRAP5_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP6 0xd286 +#define regRCC_DEV0_EPF5_STRAP6_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP7 0xd287 +#define regRCC_DEV0_EPF5_STRAP7_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP13 0xd28d +#define regRCC_DEV0_EPF5_STRAP13_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP14 0xd28e +#define regRCC_DEV0_EPF5_STRAP14_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP0 0xd300 +#define regRCC_DEV0_EPF6_STRAP0_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP2 0xd302 +#define regRCC_DEV0_EPF6_STRAP2_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP3 0xd303 +#define regRCC_DEV0_EPF6_STRAP3_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP4 0xd304 +#define regRCC_DEV0_EPF6_STRAP4_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP5 0xd305 +#define regRCC_DEV0_EPF6_STRAP5_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP6 0xd306 +#define regRCC_DEV0_EPF6_STRAP6_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP13 0xd30d +#define regRCC_DEV0_EPF6_STRAP13_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP14 0xd30e +#define regRCC_DEV0_EPF6_STRAP14_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP0 0xd380 +#define regRCC_DEV0_EPF7_STRAP0_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP2 0xd382 +#define regRCC_DEV0_EPF7_STRAP2_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP3 0xd383 +#define regRCC_DEV0_EPF7_STRAP3_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP4 0xd384 +#define regRCC_DEV0_EPF7_STRAP4_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP5 0xd385 +#define regRCC_DEV0_EPF7_STRAP5_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP6 0xd386 +#define regRCC_DEV0_EPF7_STRAP6_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP7 0xd387 +#define regRCC_DEV0_EPF7_STRAP7_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP13 0xd38d +#define regRCC_DEV0_EPF7_STRAP13_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP14 0xd38e +#define regRCC_DEV0_EPF7_STRAP14_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP0 0xd400 +#define regRCC_DEV1_EPF0_STRAP0_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP2 0xd402 +#define regRCC_DEV1_EPF0_STRAP2_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP3 0xd403 +#define regRCC_DEV1_EPF0_STRAP3_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP4 0xd404 +#define regRCC_DEV1_EPF0_STRAP4_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP5 0xd405 +#define regRCC_DEV1_EPF0_STRAP5_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP6 0xd406 +#define regRCC_DEV1_EPF0_STRAP6_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP7 0xd407 +#define regRCC_DEV1_EPF0_STRAP7_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP13 0xd40d +#define regRCC_DEV1_EPF0_STRAP13_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP14 0xd40e +#define regRCC_DEV1_EPF0_STRAP14_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP0 0xd480 +#define regRCC_DEV1_EPF1_STRAP0_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP2 0xd482 +#define regRCC_DEV1_EPF1_STRAP2_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP3 0xd483 +#define regRCC_DEV1_EPF1_STRAP3_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP4 0xd484 +#define regRCC_DEV1_EPF1_STRAP4_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP5 0xd485 +#define regRCC_DEV1_EPF1_STRAP5_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP6 0xd486 +#define regRCC_DEV1_EPF1_STRAP6_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP7 0xd487 +#define regRCC_DEV1_EPF1_STRAP7_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP13 0xd48d +#define regRCC_DEV1_EPF1_STRAP13_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP14 0xd48e +#define regRCC_DEV1_EPF1_STRAP14_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP0 0xd800 +#define regRCC_DEV2_EPF0_STRAP0_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP2 0xd802 +#define regRCC_DEV2_EPF0_STRAP2_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP3 0xd803 +#define regRCC_DEV2_EPF0_STRAP3_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP4 0xd804 +#define regRCC_DEV2_EPF0_STRAP4_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP5 0xd805 +#define regRCC_DEV2_EPF0_STRAP5_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP6 0xd806 +#define regRCC_DEV2_EPF0_STRAP6_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP7 0xd807 +#define regRCC_DEV2_EPF0_STRAP7_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP13 0xd80d +#define regRCC_DEV2_EPF0_STRAP13_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP14 0xd80e +#define regRCC_DEV2_EPF0_STRAP14_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP0 0xd880 +#define regRCC_DEV2_EPF1_STRAP0_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP2 0xd882 +#define regRCC_DEV2_EPF1_STRAP2_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP3 0xd883 +#define regRCC_DEV2_EPF1_STRAP3_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP4 0xd884 +#define regRCC_DEV2_EPF1_STRAP4_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP5 0xd885 +#define regRCC_DEV2_EPF1_STRAP5_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP6 0xd886 +#define regRCC_DEV2_EPF1_STRAP6_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP13 0xd88d +#define regRCC_DEV2_EPF1_STRAP13_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP14 0xd88e +#define regRCC_DEV2_EPF1_STRAP14_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP0 0xd900 +#define regRCC_DEV2_EPF2_STRAP0_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP2 0xd902 +#define regRCC_DEV2_EPF2_STRAP2_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP3 0xd903 +#define regRCC_DEV2_EPF2_STRAP3_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP4 0xd904 +#define regRCC_DEV2_EPF2_STRAP4_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP5 0xd905 +#define regRCC_DEV2_EPF2_STRAP5_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP6 0xd906 +#define regRCC_DEV2_EPF2_STRAP6_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP13 0xd90d +#define regRCC_DEV2_EPF2_STRAP13_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP14 0xd90e +#define regRCC_DEV2_EPF2_STRAP14_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_rst_bif_rst_regblk +// base address: 0x10100000 +#define regHARD_RST_CTRL 0xe000 +#define regHARD_RST_CTRL_BASE_IDX 8 +#define regSELF_SOFT_RST 0xe002 +#define regSELF_SOFT_RST_BASE_IDX 8 +#define regBIF_GFX_DRV_VPU_RST 0xe003 +#define regBIF_GFX_DRV_VPU_RST_BASE_IDX 8 +#define regBIF_RST_MISC_CTRL 0xe004 +#define regBIF_RST_MISC_CTRL_BASE_IDX 8 +#define regBIF_RST_MISC_CTRL2 0xe005 +#define regBIF_RST_MISC_CTRL2_BASE_IDX 8 +#define regBIF_RST_MISC_CTRL3 0xe006 +#define regBIF_RST_MISC_CTRL3_BASE_IDX 8 +#define regDEV0_PF0_FLR_RST_CTRL 0xe008 +#define regDEV0_PF0_FLR_RST_CTRL_BASE_IDX 8 +#define regDEV0_PF1_FLR_RST_CTRL 0xe009 +#define regDEV0_PF1_FLR_RST_CTRL_BASE_IDX 8 +#define regBIF_INST_RESET_INTR_STS 0xe010 +#define regBIF_INST_RESET_INTR_STS_BASE_IDX 8 +#define regBIF_PF_FLR_INTR_STS 0xe011 +#define regBIF_PF_FLR_INTR_STS_BASE_IDX 8 +#define regBIF_D3HOTD0_INTR_STS 0xe012 +#define regBIF_D3HOTD0_INTR_STS_BASE_IDX 8 +#define regBIF_POWER_INTR_STS 0xe014 +#define regBIF_POWER_INTR_STS_BASE_IDX 8 +#define regBIF_PF_DSTATE_INTR_STS 0xe015 +#define regBIF_PF_DSTATE_INTR_STS_BASE_IDX 8 +#define regSELF_SOFT_RST_2 0xe016 +#define regSELF_SOFT_RST_2_BASE_IDX 8 +#define regBIF_INST_RESET_INTR_MASK 0xe020 +#define regBIF_INST_RESET_INTR_MASK_BASE_IDX 8 +#define regBIF_PF_FLR_INTR_MASK 0xe021 +#define regBIF_PF_FLR_INTR_MASK_BASE_IDX 8 +#define regBIF_D3HOTD0_INTR_MASK 0xe022 +#define regBIF_D3HOTD0_INTR_MASK_BASE_IDX 8 +#define regBIF_POWER_INTR_MASK 0xe024 +#define regBIF_POWER_INTR_MASK_BASE_IDX 8 +#define regBIF_PF_DSTATE_INTR_MASK 0xe025 +#define regBIF_PF_DSTATE_INTR_MASK_BASE_IDX 8 +#define regBIF_PF_FLR_RST 0xe040 +#define regBIF_PF_FLR_RST_BASE_IDX 8 +#define regBIF_DEV0_PF0_DSTATE_VALUE 0xe050 +#define regBIF_DEV0_PF0_DSTATE_VALUE_BASE_IDX 8 +#define regBIF_DEV0_PF1_DSTATE_VALUE 0xe051 +#define regBIF_DEV0_PF1_DSTATE_VALUE_BASE_IDX 8 +#define regDEV0_PF0_D3HOTD0_RST_CTRL 0xe078 +#define regDEV0_PF0_D3HOTD0_RST_CTRL_BASE_IDX 8 +#define regDEV0_PF1_D3HOTD0_RST_CTRL 0xe079 +#define regDEV0_PF1_D3HOTD0_RST_CTRL_BASE_IDX 8 +#define regBIF_PORT0_DSTATE_VALUE 0xe230 +#define regBIF_PORT0_DSTATE_VALUE_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_misc_bif_misc_regblk +// base address: 0x10100000 +#define regREGS_ROM_OFFSET_CTRL 0xcc23 +#define regREGS_ROM_OFFSET_CTRL_BASE_IDX 8 +#define regNBIF_STRAP_BIOS_CNTL 0xcc81 +#define regNBIF_STRAP_BIOS_CNTL_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_0 0xcd00 +#define regDOORBELL0_CTRL_ENTRY_0_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_1 0xcd01 +#define regDOORBELL0_CTRL_ENTRY_1_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_2 0xcd02 +#define regDOORBELL0_CTRL_ENTRY_2_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_3 0xcd03 +#define regDOORBELL0_CTRL_ENTRY_3_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_4 0xcd04 +#define regDOORBELL0_CTRL_ENTRY_4_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_5 0xcd05 +#define regDOORBELL0_CTRL_ENTRY_5_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_6 0xcd06 +#define regDOORBELL0_CTRL_ENTRY_6_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_7 0xcd07 +#define regDOORBELL0_CTRL_ENTRY_7_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_8 0xcd08 +#define regDOORBELL0_CTRL_ENTRY_8_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_9 0xcd09 +#define regDOORBELL0_CTRL_ENTRY_9_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_10 0xcd0a +#define regDOORBELL0_CTRL_ENTRY_10_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_11 0xcd0b +#define regDOORBELL0_CTRL_ENTRY_11_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_12 0xcd0c +#define regDOORBELL0_CTRL_ENTRY_12_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_13 0xcd0d +#define regDOORBELL0_CTRL_ENTRY_13_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_14 0xcd0e +#define regDOORBELL0_CTRL_ENTRY_14_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_15 0xcd0f +#define regDOORBELL0_CTRL_ENTRY_15_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_16 0xcd10 +#define regDOORBELL0_CTRL_ENTRY_16_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_17 0xcd11 +#define regDOORBELL0_CTRL_ENTRY_17_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_18 0xcd12 +#define regDOORBELL0_CTRL_ENTRY_18_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_19 0xcd13 +#define regDOORBELL0_CTRL_ENTRY_19_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_20 0xcd14 +#define regDOORBELL0_CTRL_ENTRY_20_BASE_IDX 8 +#define regAID0_VF0_BASE_ADDR 0xcd40 +#define regAID0_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF0_BASE_ADDR 0xcd41 +#define regAID1_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF0_BASE_ADDR 0xcd42 +#define regAID2_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF0_BASE_ADDR 0xcd43 +#define regAID3_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF0_BASE_ADDR 0xcd44 +#define regAID0_XCC0_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF0_BASE_ADDR 0xcd45 +#define regAID0_XCC1_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF0_BASE_ADDR 0xcd46 +#define regAID1_XCC0_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF0_BASE_ADDR 0xcd47 +#define regAID1_XCC1_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF0_BASE_ADDR 0xcd48 +#define regAID2_XCC0_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF0_BASE_ADDR 0xcd49 +#define regAID2_XCC1_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF0_BASE_ADDR 0xcd4a +#define regAID3_XCC0_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF0_BASE_ADDR 0xcd4b +#define regAID3_XCC1_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF0_BASE_ADDR 0xcd4c +#define regAID0_NBIF_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF0_BASE_ADDR 0xcd4d +#define regAID0_ATHUB_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF0_BASE_ADDR 0xcd4e +#define regAID0_IH_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF0_BASE_ADDR 0xcd4f +#define regAID0_HDP_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID0_VF1_BASE_ADDR 0xcd50 +#define regAID0_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF1_BASE_ADDR 0xcd51 +#define regAID1_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF1_BASE_ADDR 0xcd52 +#define regAID2_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF1_BASE_ADDR 0xcd53 +#define regAID3_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF1_BASE_ADDR 0xcd54 +#define regAID0_XCC0_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF1_BASE_ADDR 0xcd55 +#define regAID0_XCC1_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF1_BASE_ADDR 0xcd56 +#define regAID1_XCC0_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF1_BASE_ADDR 0xcd57 +#define regAID1_XCC1_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF1_BASE_ADDR 0xcd58 +#define regAID2_XCC0_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF1_BASE_ADDR 0xcd59 +#define regAID2_XCC1_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF1_BASE_ADDR 0xcd5a +#define regAID3_XCC0_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF1_BASE_ADDR 0xcd5b +#define regAID3_XCC1_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF1_BASE_ADDR 0xcd5c +#define regAID0_NBIF_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF1_BASE_ADDR 0xcd5d +#define regAID0_ATHUB_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF1_BASE_ADDR 0xcd5e +#define regAID0_IH_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF1_BASE_ADDR 0xcd5f +#define regAID0_HDP_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID0_VF2_BASE_ADDR 0xcd60 +#define regAID0_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF2_BASE_ADDR 0xcd61 +#define regAID1_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF2_BASE_ADDR 0xcd62 +#define regAID2_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF2_BASE_ADDR 0xcd63 +#define regAID3_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF2_BASE_ADDR 0xcd64 +#define regAID0_XCC0_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF2_BASE_ADDR 0xcd65 +#define regAID0_XCC1_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF2_BASE_ADDR 0xcd66 +#define regAID1_XCC0_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF2_BASE_ADDR 0xcd67 +#define regAID1_XCC1_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF2_BASE_ADDR 0xcd68 +#define regAID2_XCC0_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF2_BASE_ADDR 0xcd69 +#define regAID2_XCC1_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF2_BASE_ADDR 0xcd6a +#define regAID3_XCC0_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF2_BASE_ADDR 0xcd6b +#define regAID3_XCC1_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF2_BASE_ADDR 0xcd6c +#define regAID0_NBIF_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF2_BASE_ADDR 0xcd6d +#define regAID0_ATHUB_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF2_BASE_ADDR 0xcd6e +#define regAID0_IH_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF2_BASE_ADDR 0xcd6f +#define regAID0_HDP_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID0_VF3_BASE_ADDR 0xcd70 +#define regAID0_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF3_BASE_ADDR 0xcd71 +#define regAID1_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF3_BASE_ADDR 0xcd72 +#define regAID2_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF3_BASE_ADDR 0xcd73 +#define regAID3_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF3_BASE_ADDR 0xcd74 +#define regAID0_XCC0_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF3_BASE_ADDR 0xcd75 +#define regAID0_XCC1_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF3_BASE_ADDR 0xcd76 +#define regAID1_XCC0_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF3_BASE_ADDR 0xcd77 +#define regAID1_XCC1_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF3_BASE_ADDR 0xcd78 +#define regAID2_XCC0_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF3_BASE_ADDR 0xcd79 +#define regAID2_XCC1_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF3_BASE_ADDR 0xcd7a +#define regAID3_XCC0_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF3_BASE_ADDR 0xcd7b +#define regAID3_XCC1_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF3_BASE_ADDR 0xcd7c +#define regAID0_NBIF_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF3_BASE_ADDR 0xcd7d +#define regAID0_ATHUB_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF3_BASE_ADDR 0xcd7e +#define regAID0_IH_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF3_BASE_ADDR 0xcd7f +#define regAID0_HDP_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID0_VF4_BASE_ADDR 0xcd80 +#define regAID0_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF4_BASE_ADDR 0xcd81 +#define regAID1_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF4_BASE_ADDR 0xcd82 +#define regAID2_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF4_BASE_ADDR 0xcd83 +#define regAID3_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF4_BASE_ADDR 0xcd84 +#define regAID0_XCC0_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF4_BASE_ADDR 0xcd85 +#define regAID0_XCC1_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF4_BASE_ADDR 0xcd86 +#define regAID1_XCC0_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF4_BASE_ADDR 0xcd87 +#define regAID1_XCC1_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF4_BASE_ADDR 0xcd88 +#define regAID2_XCC0_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF4_BASE_ADDR 0xcd89 +#define regAID2_XCC1_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF4_BASE_ADDR 0xcd8a +#define regAID3_XCC0_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF4_BASE_ADDR 0xcd8b +#define regAID3_XCC1_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF4_BASE_ADDR 0xcd8c +#define regAID0_NBIF_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF4_BASE_ADDR 0xcd8d +#define regAID0_ATHUB_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF4_BASE_ADDR 0xcd8e +#define regAID0_IH_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF4_BASE_ADDR 0xcd8f +#define regAID0_HDP_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID0_VF5_BASE_ADDR 0xcd90 +#define regAID0_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF5_BASE_ADDR 0xcd91 +#define regAID1_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF5_BASE_ADDR 0xcd92 +#define regAID2_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF5_BASE_ADDR 0xcd93 +#define regAID3_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF5_BASE_ADDR 0xcd94 +#define regAID0_XCC0_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF5_BASE_ADDR 0xcd95 +#define regAID0_XCC1_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF5_BASE_ADDR 0xcd96 +#define regAID1_XCC0_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF5_BASE_ADDR 0xcd97 +#define regAID1_XCC1_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF5_BASE_ADDR 0xcd98 +#define regAID2_XCC0_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF5_BASE_ADDR 0xcd99 +#define regAID2_XCC1_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF5_BASE_ADDR 0xcd9a +#define regAID3_XCC0_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF5_BASE_ADDR 0xcd9b +#define regAID3_XCC1_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF5_BASE_ADDR 0xcd9c +#define regAID0_NBIF_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF5_BASE_ADDR 0xcd9d +#define regAID0_ATHUB_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF5_BASE_ADDR 0xcd9e +#define regAID0_IH_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF5_BASE_ADDR 0xcd9f +#define regAID0_HDP_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID0_VF6_BASE_ADDR 0xcda0 +#define regAID0_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF6_BASE_ADDR 0xcda1 +#define regAID1_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF6_BASE_ADDR 0xcda2 +#define regAID2_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF6_BASE_ADDR 0xcda3 +#define regAID3_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF6_BASE_ADDR 0xcda4 +#define regAID0_XCC0_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF6_BASE_ADDR 0xcda5 +#define regAID0_XCC1_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF6_BASE_ADDR 0xcda6 +#define regAID1_XCC0_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF6_BASE_ADDR 0xcda7 +#define regAID1_XCC1_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF6_BASE_ADDR 0xcda8 +#define regAID2_XCC0_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF6_BASE_ADDR 0xcda9 +#define regAID2_XCC1_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF6_BASE_ADDR 0xcdaa +#define regAID3_XCC0_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF6_BASE_ADDR 0xcdab +#define regAID3_XCC1_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF6_BASE_ADDR 0xcdac +#define regAID0_NBIF_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF6_BASE_ADDR 0xcdad +#define regAID0_ATHUB_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF6_BASE_ADDR 0xcdae +#define regAID0_IH_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF6_BASE_ADDR 0xcdaf +#define regAID0_HDP_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID0_VF7_BASE_ADDR 0xcdb0 +#define regAID0_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF7_BASE_ADDR 0xcdb1 +#define regAID1_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF7_BASE_ADDR 0xcdb2 +#define regAID2_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF7_BASE_ADDR 0xcdb3 +#define regAID3_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF7_BASE_ADDR 0xcdb4 +#define regAID0_XCC0_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF7_BASE_ADDR 0xcdb5 +#define regAID0_XCC1_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF7_BASE_ADDR 0xcdb6 +#define regAID1_XCC0_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF7_BASE_ADDR 0xcdb7 +#define regAID1_XCC1_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF7_BASE_ADDR 0xcdb8 +#define regAID2_XCC0_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF7_BASE_ADDR 0xcdb9 +#define regAID2_XCC1_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF7_BASE_ADDR 0xcdba +#define regAID3_XCC0_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF7_BASE_ADDR 0xcdbb +#define regAID3_XCC1_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF7_BASE_ADDR 0xcdbc +#define regAID0_NBIF_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF7_BASE_ADDR 0xcdbd +#define regAID0_ATHUB_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF7_BASE_ADDR 0xcdbe +#define regAID0_IH_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF7_BASE_ADDR 0xcdbf +#define regAID0_HDP_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID0_PF_BASE_ADDR 0xcdc0 +#define regAID0_PF_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_PF_BASE_ADDR 0xcdc1 +#define regAID0_XCC0_PF_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_PF_BASE_ADDR 0xcdc2 +#define regAID0_XCC1_PF_BASE_ADDR_BASE_IDX 8 +#define regAID1_PF_BASE_ADDR 0xcdc3 +#define regAID1_PF_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_PF_BASE_ADDR 0xcdc4 +#define regAID1_XCC0_PF_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_PF_BASE_ADDR 0xcdc5 +#define regAID1_XCC1_PF_BASE_ADDR_BASE_IDX 8 +#define regAID2_PF_BASE_ADDR 0xcdc6 +#define regAID2_PF_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_PF_BASE_ADDR 0xcdc7 +#define regAID2_XCC0_PF_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_PF_BASE_ADDR 0xcdc8 +#define regAID2_XCC1_PF_BASE_ADDR_BASE_IDX 8 +#define regAID3_PF_BASE_ADDR 0xcdc9 +#define regAID3_PF_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_PF_BASE_ADDR 0xcdca +#define regAID3_XCC0_PF_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_PF_BASE_ADDR 0xcdcb +#define regAID3_XCC1_PF_BASE_ADDR_BASE_IDX 8 +#define regNBIF_RRMT_CNTL 0xcddc +#define regNBIF_RRMT_CNTL_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_PF 0xcf6e +#define regBIFC_DOORBELL_ACCESS_EN_PF_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF0 0xcf6f +#define regBIFC_DOORBELL_ACCESS_EN_VF0_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF1 0xcf70 +#define regBIFC_DOORBELL_ACCESS_EN_VF1_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF2 0xcf71 +#define regBIFC_DOORBELL_ACCESS_EN_VF2_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF3 0xcf72 +#define regBIFC_DOORBELL_ACCESS_EN_VF3_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF4 0xcf73 +#define regBIFC_DOORBELL_ACCESS_EN_VF4_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF5 0xcf74 +#define regBIFC_DOORBELL_ACCESS_EN_VF5_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF6 0xcf75 +#define regBIFC_DOORBELL_ACCESS_EN_VF6_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF7 0xcf76 +#define regBIFC_DOORBELL_ACCESS_EN_VF7_BASE_IDX 8 +#define regMISC_SCRATCH 0xe800 +#define regMISC_SCRATCH_BASE_IDX 8 +#define regINTR_LINE_POLARITY 0xe801 +#define regINTR_LINE_POLARITY_BASE_IDX 8 +#define regINTR_LINE_ENABLE 0xe802 +#define regINTR_LINE_ENABLE_BASE_IDX 8 +#define regOUTSTANDING_VC_ALLOC 0xe803 +#define regOUTSTANDING_VC_ALLOC_BASE_IDX 8 +#define regBIFC_MISC_CTRL0 0xe804 +#define regBIFC_MISC_CTRL0_BASE_IDX 8 +#define regBIFC_MISC_CTRL1 0xe805 +#define regBIFC_MISC_CTRL1_BASE_IDX 8 +#define regBIFC_BME_ERR_LOG_LB 0xe806 +#define regBIFC_BME_ERR_LOG_LB_BASE_IDX 8 +#define regBIFC_LC_TIMER_CTRL 0xe807 +#define regBIFC_LC_TIMER_CTRL_BASE_IDX 8 +#define regBIFC_RCCBIH_BME_ERR_LOG0 0xe808 +#define regBIFC_RCCBIH_BME_ERR_LOG0_BASE_IDX 8 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 0xe80a +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_BASE_IDX 8 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 0xe80b +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_BASE_IDX 8 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 0xe80c +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_BASE_IDX 8 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 0xe80d +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_BASE_IDX 8 +#define regBIFC_DMA_ATTR_CNTL2_DEV0 0xe81a +#define regBIFC_DMA_ATTR_CNTL2_DEV0_BASE_IDX 8 +#define regBME_DUMMY_CNTL_0 0xe825 +#define regBME_DUMMY_CNTL_0_BASE_IDX 8 +#define regBIFC_THT_CNTL 0xe827 +#define regBIFC_THT_CNTL_BASE_IDX 8 +#define regBIFC_HSTARB_CNTL 0xe828 +#define regBIFC_HSTARB_CNTL_BASE_IDX 8 +#define regBIFC_GSI_CNTL 0xe829 +#define regBIFC_GSI_CNTL_BASE_IDX 8 +#define regBIFC_PCIEFUNC_CNTL 0xe82a +#define regBIFC_PCIEFUNC_CNTL_BASE_IDX 8 +#define regBIFC_PASID_CHECK_DIS 0xe82b +#define regBIFC_PASID_CHECK_DIS_BASE_IDX 8 +#define regBIFC_SDP_CNTL_0 0xe82c +#define regBIFC_SDP_CNTL_0_BASE_IDX 8 +#define regBIFC_SDP_CNTL_1 0xe82d +#define regBIFC_SDP_CNTL_1_BASE_IDX 8 +#define regBIFC_PASID_STS 0xe82e +#define regBIFC_PASID_STS_BASE_IDX 8 +#define regBIFC_ATHUB_ACT_CNTL 0xe82f +#define regBIFC_ATHUB_ACT_CNTL_BASE_IDX 8 +#define regBIFC_PERF_CNTL_0 0xe830 +#define regBIFC_PERF_CNTL_0_BASE_IDX 8 +#define regBIFC_PERF_CNTL_1 0xe831 +#define regBIFC_PERF_CNTL_1_BASE_IDX 8 +#define regBIFC_PERF_CNT_MMIO_RD_L32BIT 0xe832 +#define regBIFC_PERF_CNT_MMIO_RD_L32BIT_BASE_IDX 8 +#define regBIFC_PERF_CNT_MMIO_WR_L32BIT 0xe833 +#define regBIFC_PERF_CNT_MMIO_WR_L32BIT_BASE_IDX 8 +#define regBIFC_PERF_CNT_DMA_RD_L32BIT 0xe834 +#define regBIFC_PERF_CNT_DMA_RD_L32BIT_BASE_IDX 8 +#define regBIFC_PERF_CNT_DMA_WR_L32BIT 0xe835 +#define regBIFC_PERF_CNT_DMA_WR_L32BIT_BASE_IDX 8 +#define regNBIF_REGIF_ERRSET_CTRL 0xe836 +#define regNBIF_REGIF_ERRSET_CTRL_BASE_IDX 8 +#define regBIFC_SDP_CNTL_2 0xe837 +#define regBIFC_SDP_CNTL_2_BASE_IDX 8 +#define regNBIF_PGMST_CTRL 0xe838 +#define regNBIF_PGMST_CTRL_BASE_IDX 8 +#define regNBIF_PGSLV_CTRL 0xe839 +#define regNBIF_PGSLV_CTRL_BASE_IDX 8 +#define regNBIF_PG_MISC_CTRL 0xe83a +#define regNBIF_PG_MISC_CTRL_BASE_IDX 8 +#define regSMN_MST_EP_CNTL3 0xe83c +#define regSMN_MST_EP_CNTL3_BASE_IDX 8 +#define regSMN_MST_EP_CNTL4 0xe83d +#define regSMN_MST_EP_CNTL4_BASE_IDX 8 +#define regSMN_MST_CNTL1 0xe83e +#define regSMN_MST_CNTL1_BASE_IDX 8 +#define regSMN_MST_EP_CNTL5 0xe83f +#define regSMN_MST_EP_CNTL5_BASE_IDX 8 +#define regBIF_SELFRING_BUFFER_VID 0xe840 +#define regBIF_SELFRING_BUFFER_VID_BASE_IDX 8 +#define regBIF_SELFRING_VECTOR_CNTL 0xe841 +#define regBIF_SELFRING_VECTOR_CNTL_BASE_IDX 8 +#define regNBIF_STRAP_WRITE_CTRL 0xe845 +#define regNBIF_STRAP_WRITE_CTRL_BASE_IDX 8 +#define regNBIF_INTX_DSTATE_MISC_CNTL 0xe846 +#define regNBIF_INTX_DSTATE_MISC_CNTL_BASE_IDX 8 +#define regNBIF_PENDING_MISC_CNTL 0xe847 +#define regNBIF_PENDING_MISC_CNTL_BASE_IDX 8 +#define regBIF_GMI_WRR_WEIGHT 0xe848 +#define regBIF_GMI_WRR_WEIGHT_BASE_IDX 8 +#define regBIF_GMI_WRR_WEIGHT2 0xe849 +#define regBIF_GMI_WRR_WEIGHT2_BASE_IDX 8 +#define regBIF_GMI_WRR_WEIGHT3 0xe84a +#define regBIF_GMI_WRR_WEIGHT3_BASE_IDX 8 +#define regNBIF_PWRBRK_REQUEST 0xe84c +#define regNBIF_PWRBRK_REQUEST_BASE_IDX 8 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F0 0xe850 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F0_BASE_IDX 8 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F1 0xe851 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F1_BASE_IDX 8 +#define regBIF_DMA_MP4_ERR_LOG 0xe870 +#define regBIF_DMA_MP4_ERR_LOG_BASE_IDX 8 +#define regBIF_PASID_ERR_LOG 0xe871 +#define regBIF_PASID_ERR_LOG_BASE_IDX 8 +#define regBIF_PASID_ERR_CLR 0xe872 +#define regBIF_PASID_ERR_CLR_BASE_IDX 8 +#define regNBIF_VWIRE_CTRL 0xe880 +#define regNBIF_VWIRE_CTRL_BASE_IDX 8 +#define regNBIF_SMN_VWR_VCHG_DIS_CTRL 0xe881 +#define regNBIF_SMN_VWR_VCHG_DIS_CTRL_BASE_IDX 8 +#define regNBIF_SMN_VWR_VCHG_RST_CTRL0 0xe882 +#define regNBIF_SMN_VWR_VCHG_RST_CTRL0_BASE_IDX 8 +#define regNBIF_SMN_VWR_VCHG_TRIG 0xe884 +#define regNBIF_SMN_VWR_VCHG_TRIG_BASE_IDX 8 +#define regNBIF_SMN_VWR_WTRIG_CNTL 0xe885 +#define regNBIF_SMN_VWR_WTRIG_CNTL_BASE_IDX 8 +#define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1 0xe886 +#define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1_BASE_IDX 8 +#define regNBIF_MGCG_CTRL_LCLK 0xe887 +#define regNBIF_MGCG_CTRL_LCLK_BASE_IDX 8 +#define regNBIF_DS_CTRL_LCLK 0xe888 +#define regNBIF_DS_CTRL_LCLK_BASE_IDX 8 +#define regSMN_MST_CNTL0 0xe889 +#define regSMN_MST_CNTL0_BASE_IDX 8 +#define regSMN_MST_EP_CNTL1 0xe88a +#define regSMN_MST_EP_CNTL1_BASE_IDX 8 +#define regSMN_MST_EP_CNTL2 0xe88b +#define regSMN_MST_EP_CNTL2_BASE_IDX 8 +#define regNBIF_SDP_VWR_VCHG_DIS_CTRL 0xe88c +#define regNBIF_SDP_VWR_VCHG_DIS_CTRL_BASE_IDX 8 +#define regNBIF_SDP_VWR_VCHG_RST_CTRL0 0xe88d +#define regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX 8 +#define regNBIF_SDP_VWR_VCHG_RST_CTRL1 0xe88e +#define regNBIF_SDP_VWR_VCHG_RST_CTRL1_BASE_IDX 8 +#define regNBIF_SDP_VWR_VCHG_TRIG 0xe88f +#define regNBIF_SDP_VWR_VCHG_TRIG_BASE_IDX 8 +#define regNBIF_SHUB_TODET_CTRL 0xe898 +#define regNBIF_SHUB_TODET_CTRL_BASE_IDX 8 +#define regNBIF_SHUB_TODET_CLIENT_CTRL 0xe899 +#define regNBIF_SHUB_TODET_CLIENT_CTRL_BASE_IDX 8 +#define regNBIF_SHUB_TODET_CLIENT_STATUS 0xe89a +#define regNBIF_SHUB_TODET_CLIENT_STATUS_BASE_IDX 8 +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL 0xe89b +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL_BASE_IDX 8 +#define regNBIF_SHUB_TODET_CLIENT_CTRL2 0xe89c +#define regNBIF_SHUB_TODET_CLIENT_CTRL2_BASE_IDX 8 +#define regNBIF_SHUB_TODET_CLIENT_STATUS2 0xe89d +#define regNBIF_SHUB_TODET_CLIENT_STATUS2_BASE_IDX 8 +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2 0xe89e +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2_BASE_IDX 8 +#define regBIFC_BME_ERR_LOG_HB 0xe8ab +#define regBIFC_BME_ERR_LOG_HB_BASE_IDX 8 +#define regBIFC_GFX_INT_MONITOR_MASK 0xe8ad +#define regBIFC_GFX_INT_MONITOR_MASK_BASE_IDX 8 +#define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC 0xe8c0 +#define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC_BASE_IDX 8 +#define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC 0xe8c1 +#define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC_BASE_IDX 8 +#define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC 0xe8c2 +#define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX 8 +#define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC 0xe8c3 +#define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX 8 +#define regDISCON_HYSTERESIS_HEAD_CTRL 0xe8c6 +#define regDISCON_HYSTERESIS_HEAD_CTRL_BASE_IDX 8 +#define regBIFC_EARLY_WAKEUP_CNTL 0xe8d2 +#define regBIFC_EARLY_WAKEUP_CNTL_BASE_IDX 8 +#define regBIFC_PERF_CNT_MMIO_RD_H16BIT 0xe8f0 +#define regBIFC_PERF_CNT_MMIO_RD_H16BIT_BASE_IDX 8 +#define regBIFC_PERF_CNT_MMIO_WR_H16BIT 0xe8f1 +#define regBIFC_PERF_CNT_MMIO_WR_H16BIT_BASE_IDX 8 +#define regBIFC_PERF_CNT_DMA_RD_H16BIT 0xe8f2 +#define regBIFC_PERF_CNT_DMA_RD_H16BIT_BASE_IDX 8 +#define regBIFC_PERF_CNT_DMA_WR_H16BIT 0xe8f3 +#define regBIFC_PERF_CNT_DMA_WR_H16BIT_BASE_IDX 8 +#define regBIFC_A2S_SDP_PORT_CTRL 0xeb00 +#define regBIFC_A2S_SDP_PORT_CTRL_BASE_IDX 8 +#define regBIFC_A2S_CNTL_SW0 0xeb01 +#define regBIFC_A2S_CNTL_SW0_BASE_IDX 8 +#define regBIFC_A2S_MISC_CNTL 0xeb02 +#define regBIFC_A2S_MISC_CNTL_BASE_IDX 8 +#define regBIFC_A2S_TAG_ALLOC_0 0xeb03 +#define regBIFC_A2S_TAG_ALLOC_0_BASE_IDX 8 +#define regBIFC_A2S_TAG_ALLOC_1 0xeb04 +#define regBIFC_A2S_TAG_ALLOC_1_BASE_IDX 8 +#define regBIFC_A2S_CNTL_CL0 0xeb05 +#define regBIFC_A2S_CNTL_CL0_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED 0x8d80 +#define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH 0x8d81 +#define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_CNTL 0x8d83 +#define regRCC_DWN_DEV0_2_DN_PCIE_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL 0x8d84 +#define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 0x8d85 +#define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL 0x8d86 +#define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL 0x8d87 +#define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0 0x8d88 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC 0x8d89 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2 0x8d8a +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL 0x8d8c +#define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL_BASE_IDX 8 +#define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL 0x8d8d +#define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL_BASE_IDX 8 +#define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL 0x8d8e +#define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL_BASE_IDX 8 +#define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2 0x8d8f +#define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2_BASE_IDX 8 +#define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC 0x8d90 +#define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC_BASE_IDX 8 +#define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP 0x8d91 +#define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_ep_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH 0x8d60 +#define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_CNTL 0x8d62 +#define regRCC_EP_DEV0_2_EP_PCIE_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL 0x8d63 +#define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS 0x8d64 +#define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 0x8d65 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL 0x8d66 +#define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL 0x8d67 +#define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL 0x8d69 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x8d6a +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x8d6a +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x8d6a +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x8d6a +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x8d6b +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x8d6b +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x8d6b +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x8d6b +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC 0x8d6c +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2 0x8d6d +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP 0x8d6f +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x8d70 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL 0x8d70 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x8d70 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x8d71 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x8d71 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x8d71 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x8d71 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x8d72 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x8d72 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x8d72 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL 0x8d72 +#define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED 0x8d73 +#define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL 0x8d75 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID 0x8d76 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL 0x8d77 +#define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL 0x8d78 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL 0x8d79 +#define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_DEV0_1_RCC_ERR_INT_CNTL 0x8da6 +#define regRCC_DEV0_1_RCC_ERR_INT_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_BACO_CNTL_MISC 0x8da7 +#define regRCC_DEV0_1_RCC_BACO_CNTL_MISC_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_RESET_EN 0x8da8 +#define regRCC_DEV0_1_RCC_RESET_EN_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_VDM_SUPPORT 0x8da9 +#define regRCC_DEV0_2_RCC_VDM_SUPPORT_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0 0x8daa +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1 0x8dab +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_GPUIOV_REGION 0x8dac +#define regRCC_DEV0_1_RCC_GPUIOV_REGION_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN 0x8dad +#define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL 0x8dae +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x8daf +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE 0x8daf +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE0 0x8dde +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE0_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE1 0x8ddf +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE1_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_BUS_CNTL 0x8de1 +#define regRCC_DEV0_2_RCC_BUS_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CONFIG_CNTL 0x8de2 +#define regRCC_DEV0_1_RCC_CONFIG_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CONFIG_F0_BASE 0x8de6 +#define regRCC_DEV0_1_RCC_CONFIG_F0_BASE_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE 0x8de7 +#define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE 0x8de8 +#define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_XDMA_LO 0x8de9 +#define regRCC_DEV0_1_RCC_XDMA_LO_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_XDMA_HI 0x8dea +#define regRCC_DEV0_1_RCC_XDMA_HI_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC 0x8deb +#define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL1 0x8dec +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL1_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_BUSNUM_LIST0 0x8ded +#define regRCC_DEV0_1_RCC_BUSNUM_LIST0_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_BUSNUM_LIST1 0x8dee +#define regRCC_DEV0_1_RCC_BUSNUM_LIST1_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL2 0x8def +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL2_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM 0x8df0 +#define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_HOST_BUSNUM 0x8df1 +#define regRCC_DEV0_1_RCC_HOST_BUSNUM_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI 0x8df2 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO 0x8df3 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI 0x8df4 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO 0x8df5 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI 0x8df6 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO 0x8df7 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI 0x8df8 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO 0x8df9 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0 0x8dfa +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1 0x8dfb +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL 0x8dfd +#define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_CMN_LINK_CNTL 0x8dfe +#define regRCC_DEV0_2_RCC_CMN_LINK_CNTL_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE 0x8dff +#define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL 0x8e00 +#define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_MH_ARB_CNTL 0x8e01 +#define regRCC_DEV0_2_RCC_MH_ARB_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_bx_SYSDEC +// base address: 0x10120000 +#define regBIF_BX1_PCIE_INDEX 0x800c +#define regBIF_BX1_PCIE_INDEX_BASE_IDX 8 +#define regBIF_BX1_PCIE_DATA 0x800d +#define regBIF_BX1_PCIE_DATA_BASE_IDX 8 +#define regBIF_BX1_PCIE_INDEX2 0x800e +#define regBIF_BX1_PCIE_INDEX2_BASE_IDX 8 +#define regBIF_BX1_PCIE_DATA2 0x800f +#define regBIF_BX1_PCIE_DATA2_BASE_IDX 8 +#define regBIF_BX1_PCIE_INDEX_HI 0x8010 +#define regBIF_BX1_PCIE_INDEX_HI_BASE_IDX 8 +#define regBIF_BX1_PCIE_INDEX2_HI 0x8011 +#define regBIF_BX1_PCIE_INDEX2_HI_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_0 0x8048 +#define regBIF_BX1_SBIOS_SCRATCH_0_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_1 0x8049 +#define regBIF_BX1_SBIOS_SCRATCH_1_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_2 0x804a +#define regBIF_BX1_SBIOS_SCRATCH_2_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_3 0x804b +#define regBIF_BX1_SBIOS_SCRATCH_3_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_0 0x804c +#define regBIF_BX1_BIOS_SCRATCH_0_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_1 0x804d +#define regBIF_BX1_BIOS_SCRATCH_1_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_2 0x804e +#define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_3 0x804f +#define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_4 0x8050 +#define regBIF_BX1_BIOS_SCRATCH_4_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_5 0x8051 +#define regBIF_BX1_BIOS_SCRATCH_5_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_6 0x8052 +#define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_7 0x8053 +#define regBIF_BX1_BIOS_SCRATCH_7_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_8 0x8054 +#define regBIF_BX1_BIOS_SCRATCH_8_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_9 0x8055 +#define regBIF_BX1_BIOS_SCRATCH_9_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_10 0x8056 +#define regBIF_BX1_BIOS_SCRATCH_10_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_11 0x8057 +#define regBIF_BX1_BIOS_SCRATCH_11_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_12 0x8058 +#define regBIF_BX1_BIOS_SCRATCH_12_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_13 0x8059 +#define regBIF_BX1_BIOS_SCRATCH_13_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_14 0x805a +#define regBIF_BX1_BIOS_SCRATCH_14_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_15 0x805b +#define regBIF_BX1_BIOS_SCRATCH_15_BASE_IDX 8 +#define regBIF_BX1_BIF_RLC_INTR_CNTL 0x8060 +#define regBIF_BX1_BIF_RLC_INTR_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_VCE_INTR_CNTL 0x8061 +#define regBIF_BX1_BIF_VCE_INTR_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_UVD_INTR_CNTL 0x8062 +#define regBIF_BX1_BIF_UVD_INTR_CNTL_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0 0x8080 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 0x8081 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1 0x8082 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 0x8083 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2 0x8084 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 0x8085 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3 0x8086 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 0x8087 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4 0x8088 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 0x8089 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5 0x808a +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 0x808b +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6 0x808c +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 0x808d +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7 0x808e +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 0x808f +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_CNTL 0x8090 +#define regBIF_BX1_GFX_MMIOREG_CAM_CNTL_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL 0x8091 +#define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL 0x8092 +#define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x8093 +#define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_0 0x8094 +#define regBIF_BX1_DRIVER_SCRATCH_0_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_1 0x8095 +#define regBIF_BX1_DRIVER_SCRATCH_1_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_2 0x8096 +#define regBIF_BX1_DRIVER_SCRATCH_2_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_3 0x8097 +#define regBIF_BX1_DRIVER_SCRATCH_3_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_4 0x8098 +#define regBIF_BX1_DRIVER_SCRATCH_4_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_5 0x8099 +#define regBIF_BX1_DRIVER_SCRATCH_5_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_6 0x809a +#define regBIF_BX1_DRIVER_SCRATCH_6_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_7 0x809b +#define regBIF_BX1_DRIVER_SCRATCH_7_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_8 0x809c +#define regBIF_BX1_DRIVER_SCRATCH_8_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_9 0x809d +#define regBIF_BX1_DRIVER_SCRATCH_9_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_10 0x809e +#define regBIF_BX1_DRIVER_SCRATCH_10_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_11 0x809f +#define regBIF_BX1_DRIVER_SCRATCH_11_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_12 0x80a0 +#define regBIF_BX1_DRIVER_SCRATCH_12_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_13 0x80a1 +#define regBIF_BX1_DRIVER_SCRATCH_13_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_14 0x80a2 +#define regBIF_BX1_DRIVER_SCRATCH_14_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_15 0x80a3 +#define regBIF_BX1_DRIVER_SCRATCH_15_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_0 0x80a4 +#define regBIF_BX1_FW_SCRATCH_0_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_1 0x80a5 +#define regBIF_BX1_FW_SCRATCH_1_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_2 0x80a6 +#define regBIF_BX1_FW_SCRATCH_2_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_3 0x80a7 +#define regBIF_BX1_FW_SCRATCH_3_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_4 0x80a8 +#define regBIF_BX1_FW_SCRATCH_4_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_5 0x80a9 +#define regBIF_BX1_FW_SCRATCH_5_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_6 0x80aa +#define regBIF_BX1_FW_SCRATCH_6_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_7 0x80ab +#define regBIF_BX1_FW_SCRATCH_7_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_8 0x80ac +#define regBIF_BX1_FW_SCRATCH_8_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_9 0x80ad +#define regBIF_BX1_FW_SCRATCH_9_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_10 0x80ae +#define regBIF_BX1_FW_SCRATCH_10_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_11 0x80af +#define regBIF_BX1_FW_SCRATCH_11_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_12 0x80b0 +#define regBIF_BX1_FW_SCRATCH_12_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_13 0x80b1 +#define regBIF_BX1_FW_SCRATCH_13_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_14 0x80b2 +#define regBIF_BX1_FW_SCRATCH_14_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_15 0x80b3 +#define regBIF_BX1_FW_SCRATCH_15_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_4 0x80b4 +#define regBIF_BX1_SBIOS_SCRATCH_4_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_5 0x80b5 +#define regBIF_BX1_SBIOS_SCRATCH_5_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_6 0x80b6 +#define regBIF_BX1_SBIOS_SCRATCH_6_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_7 0x80b7 +#define regBIF_BX1_SBIOS_SCRATCH_7_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_8 0x80b8 +#define regBIF_BX1_SBIOS_SCRATCH_8_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_9 0x80b9 +#define regBIF_BX1_SBIOS_SCRATCH_9_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_10 0x80ba +#define regBIF_BX1_SBIOS_SCRATCH_10_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_11 0x80bb +#define regBIF_BX1_SBIOS_SCRATCH_11_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_12 0x80bc +#define regBIF_BX1_SBIOS_SCRATCH_12_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_13 0x80bd +#define regBIF_BX1_SBIOS_SCRATCH_13_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_14 0x80be +#define regBIF_BX1_SBIOS_SCRATCH_14_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_15 0x80bf +#define regBIF_BX1_SBIOS_SCRATCH_15_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_bx_pf_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_PF1_MM_INDEX 0x8000 +#define regBIF_BX_PF1_MM_INDEX_BASE_IDX 8 +#define regBIF_BX_PF1_MM_DATA 0x8001 +#define regBIF_BX_PF1_MM_DATA_BASE_IDX 8 +#define regBIF_BX_PF1_MM_INDEX_HI 0x8006 +#define regBIF_BX_PF1_MM_INDEX_HI_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_bx_BIFDEC1 +// base address: 0x10120000 +#define regBIF_BX1_CC_BIF_BX_STRAP0 0x8e02 +#define regBIF_BX1_CC_BIF_BX_STRAP0_BASE_IDX 8 +#define regBIF_BX1_CC_BIF_BX_PINSTRAP0 0x8e04 +#define regBIF_BX1_CC_BIF_BX_PINSTRAP0_BASE_IDX 8 +#define regBIF_BX1_BIF_MM_INDACCESS_CNTL 0x8e06 +#define regBIF_BX1_BIF_MM_INDACCESS_CNTL_BASE_IDX 8 +#define regBIF_BX1_BUS_CNTL 0x8e07 +#define regBIF_BX1_BUS_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_SCRATCH0 0x8e08 +#define regBIF_BX1_BIF_SCRATCH0_BASE_IDX 8 +#define regBIF_BX1_BIF_SCRATCH1 0x8e09 +#define regBIF_BX1_BIF_SCRATCH1_BASE_IDX 8 +#define regBIF_BX1_BX_RESET_EN 0x8e0d +#define regBIF_BX1_BX_RESET_EN_BASE_IDX 8 +#define regBIF_BX1_MM_CFGREGS_CNTL 0x8e0e +#define regBIF_BX1_MM_CFGREGS_CNTL_BASE_IDX 8 +#define regBIF_BX1_BX_RESET_CNTL 0x8e10 +#define regBIF_BX1_BX_RESET_CNTL_BASE_IDX 8 +#define regBIF_BX1_INTERRUPT_CNTL 0x8e11 +#define regBIF_BX1_INTERRUPT_CNTL_BASE_IDX 8 +#define regBIF_BX1_INTERRUPT_CNTL2 0x8e12 +#define regBIF_BX1_INTERRUPT_CNTL2_BASE_IDX 8 +#define regBIF_BX1_CLKREQB_PAD_CNTL 0x8e18 +#define regBIF_BX1_CLKREQB_PAD_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_FEATURES_CONTROL_MISC 0x8e1b +#define regBIF_BX1_BIF_FEATURES_CONTROL_MISC_BASE_IDX 8 +#define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC 0x8e1c +#define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 8 +#define regBIF_BX1_BIF_DOORBELL_CNTL 0x8e1d +#define regBIF_BX1_BIF_DOORBELL_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_DOORBELL_INT_CNTL 0x8e1e +#define regBIF_BX1_BIF_DOORBELL_INT_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_FB_EN 0x8e20 +#define regBIF_BX1_BIF_FB_EN_BASE_IDX 8 +#define regBIF_BX1_BIF_INTR_CNTL 0x8e21 +#define regBIF_BX1_BIF_INTR_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_MST_TRANS_PENDING_VF 0x8e29 +#define regBIF_BX1_BIF_MST_TRANS_PENDING_VF_BASE_IDX 8 +#define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF 0x8e2a +#define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 8 +#define regBIF_BX1_BACO_CNTL 0x8e2b +#define regBIF_BX1_BACO_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_BACO_EXIT_TIME0 0x8e2c +#define regBIF_BX1_BIF_BACO_EXIT_TIME0_BASE_IDX 8 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER1 0x8e2d +#define regBIF_BX1_BIF_BACO_EXIT_TIMER1_BASE_IDX 8 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER2 0x8e2e +#define regBIF_BX1_BIF_BACO_EXIT_TIMER2_BASE_IDX 8 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER3 0x8e2f +#define regBIF_BX1_BIF_BACO_EXIT_TIMER3_BASE_IDX 8 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER4 0x8e30 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER4_BASE_IDX 8 +#define regBIF_BX1_MEM_TYPE_CNTL 0x8e31 +#define regBIF_BX1_MEM_TYPE_CNTL_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL 0x8e33 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_0 0x8e34 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_0_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_1 0x8e35 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_1_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_2 0x8e36 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_2_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_3 0x8e37 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_3_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_4 0x8e38 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_4_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_5 0x8e39 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_5_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_6 0x8e3a +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_6_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_7 0x8e3b +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_7_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_8 0x8e3c +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_8_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_9 0x8e3d +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_9_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_10 0x8e3e +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_10_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_11 0x8e3f +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_11_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_12 0x8e40 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_12_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_13 0x8e41 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_13_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_14 0x8e42 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_14_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_15 0x8e43 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_15_BASE_IDX 8 +#define regBIF_BX1_VF_REGWR_EN 0x8e44 +#define regBIF_BX1_VF_REGWR_EN_BASE_IDX 8 +#define regBIF_BX1_VF_DOORBELL_EN 0x8e45 +#define regBIF_BX1_VF_DOORBELL_EN_BASE_IDX 8 +#define regBIF_BX1_VF_FB_EN 0x8e46 +#define regBIF_BX1_VF_FB_EN_BASE_IDX 8 +#define regBIF_BX1_VF_REGWR_STATUS 0x8e47 +#define regBIF_BX1_VF_REGWR_STATUS_BASE_IDX 8 +#define regBIF_BX1_VF_DOORBELL_STATUS 0x8e48 +#define regBIF_BX1_VF_DOORBELL_STATUS_BASE_IDX 8 +#define regBIF_BX1_VF_FB_STATUS 0x8e49 +#define regBIF_BX1_VF_FB_STATUS_BASE_IDX 8 +#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL 0x8e4d +#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 8 +#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL 0x8e4e +#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_RB_CNTL 0x8e4f +#define regBIF_BX1_BIF_RB_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_RB_BASE 0x8e50 +#define regBIF_BX1_BIF_RB_BASE_BASE_IDX 8 +#define regBIF_BX1_BIF_RB_RPTR 0x8e51 +#define regBIF_BX1_BIF_RB_RPTR_BASE_IDX 8 +#define regBIF_BX1_BIF_RB_WPTR 0x8e52 +#define regBIF_BX1_BIF_RB_WPTR_BASE_IDX 8 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_HI 0x8e53 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_HI_BASE_IDX 8 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_LO 0x8e54 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_LO_BASE_IDX 8 +#define regBIF_BX1_MAILBOX_INDEX 0x8e55 +#define regBIF_BX1_MAILBOX_INDEX_BASE_IDX 8 +#define regBIF_BX1_BIF_MP1_INTR_CTRL 0x8e62 +#define regBIF_BX1_BIF_MP1_INTR_CTRL_BASE_IDX 8 +#define regBIF_BX1_BIF_PERSTB_PAD_CNTL 0x8e66 +#define regBIF_BX1_BIF_PERSTB_PAD_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_PX_EN_PAD_CNTL 0x8e67 +#define regBIF_BX1_BIF_PX_EN_PAD_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL 0x8e68 +#define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_CLKREQB_PAD_CNTL 0x8e69 +#define regBIF_BX1_BIF_CLKREQB_PAD_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_PWRBRK_PAD_CNTL 0x8e6a +#define regBIF_BX1_BIF_PWRBRK_PAD_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE 0x8e6b +#define regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE_BASE_IDX 8 +#define regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE 0x8e6c +#define regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_PF1_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_PF1_BIF_BME_STATUS_BASE_IDX 8 +#define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 8 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 8 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 8 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 8 +#define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 8 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 8 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 8 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 8 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_BASE_IDX 8 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_BASE_IDX 8 +#define regBIF_BX_PF1_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_PF1_BIF_TRANS_PENDING_BASE_IDX 8 +#define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_PF1_MAILBOX_CONTROL_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_PF1_MAILBOX_INT_CNTL_BASE_IDX 8 +#define regBIF_BX_PF1_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_PF1_BIF_VMHV_MAILBOX_BASE_IDX 8 +#define regBIF_BX_PF1_PARTITION_COMPUTE_CAP 0x8e81 +#define regBIF_BX_PF1_PARTITION_COMPUTE_CAP_BASE_IDX 8 +#define regBIF_BX_PF1_PARTITION_MEM_CAP 0x8e82 +#define regBIF_BX_PF1_PARTITION_MEM_CAP_BASE_IDX 8 +#define regBIF_BX_PF1_PARTITION_COMPUTE_STATUS 0x8e83 +#define regBIF_BX_PF1_PARTITION_COMPUTE_STATUS_BASE_IDX 8 +#define regBIF_BX_PF1_PARTITION_MEM_STATUS 0x8e84 +#define regBIF_BX_PF1_PARTITION_MEM_STATUS_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_strap_BIFDEC1:1 +// base address: 0x10120000 +#define regRCC_STRAP2_RCC_BIF_STRAP0 0x8d20 +#define regRCC_STRAP2_RCC_BIF_STRAP0_BASE_IDX 8 +#define regRCC_STRAP2_RCC_BIF_STRAP1 0x8d21 +#define regRCC_STRAP2_RCC_BIF_STRAP1_BASE_IDX 8 +#define regRCC_STRAP2_RCC_BIF_STRAP2 0x8d22 +#define regRCC_STRAP2_RCC_BIF_STRAP2_BASE_IDX 8 +#define regRCC_STRAP2_RCC_BIF_STRAP3 0x8d23 +#define regRCC_STRAP2_RCC_BIF_STRAP3_BASE_IDX 8 +#define regRCC_STRAP2_RCC_BIF_STRAP4 0x8d24 +#define regRCC_STRAP2_RCC_BIF_STRAP4_BASE_IDX 8 +#define regRCC_STRAP2_RCC_BIF_STRAP5 0x8d25 +#define regRCC_STRAP2_RCC_BIF_STRAP5_BASE_IDX 8 +#define regRCC_STRAP2_RCC_BIF_STRAP6 0x8d26 +#define regRCC_STRAP2_RCC_BIF_STRAP6_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0 0x8d27 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1 0x8d28 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10 0x8d29 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11 0x8d2a +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12 0x8d2b +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13 0x8d2c +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14 0x8d2d +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2 0x8d2e +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3 0x8d2f +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4 0x8d30 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5 0x8d31 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6 0x8d32 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7 0x8d33 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8 0x8d34 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9 0x8d35 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0 0x8d36 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1 0x8d37 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13 0x8d38 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14 0x8d39 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15 0x8d3a +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16 0x8d3b +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17 0x8d3c +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18 0x8d3d +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2 0x8d3e +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26 0x8d3f +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3 0x8d40 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4 0x8d41 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5 0x8d42 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8 0x8d44 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9 0x8d45 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0 0x8d46 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2 0x8d52 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20 0x8d53 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21 0x8d54 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22 0x8d55 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23 0x8d56 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24 0x8d57 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25 0x8d58 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3 0x8d59 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4 0x8d5a +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5 0x8d5b +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6 0x8d5c +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7 0x8d5d +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_gdc_hst_sion_SIONDEC +// base address: 0x1400000 +#define regS2A_DOORBELL_ENTRY_0_CTRL 0x7a80 +#define regS2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_1_CTRL 0x7a81 +#define regS2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_2_CTRL 0x7a82 +#define regS2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_3_CTRL 0x7a83 +#define regS2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_4_CTRL 0x7a84 +#define regS2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_5_CTRL 0x7a85 +#define regS2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_6_CTRL 0x7a86 +#define regS2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_7_CTRL 0x7a87 +#define regS2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_8_CTRL 0x7a88 +#define regS2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_9_CTRL 0x7a89 +#define regS2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_10_CTRL 0x7a8a +#define regS2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_11_CTRL 0x7a8b +#define regS2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_12_CTRL 0x7a8c +#define regS2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_13_CTRL 0x7a8d +#define regS2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_14_CTRL 0x7a8e +#define regS2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_15_CTRL 0x7a8f +#define regS2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_COMMON_CTRL_REG 0x7a90 +#define regS2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX 5 + + +// addressBlock: aid_nbio_nbif0_gdc_GDCDEC +// base address: 0x1400000 +#define regGDC1_A2S_CNTL_CL0 0x0ea0 +#define regGDC1_A2S_CNTL_CL0_BASE_IDX 5 +#define regGDC1_A2S_CNTL_CL1 0x0ea1 +#define regGDC1_A2S_CNTL_CL1_BASE_IDX 5 +#define regGDC1_A2S_CNTL3_CL0 0x0eb8 +#define regGDC1_A2S_CNTL3_CL0_BASE_IDX 5 +#define regGDC1_A2S_CNTL3_CL1 0x0eb9 +#define regGDC1_A2S_CNTL3_CL1_BASE_IDX 5 +#define regGDC1_A2S_CNTL_SW0 0x0ed0 +#define regGDC1_A2S_CNTL_SW0_BASE_IDX 5 +#define regGDC1_A2S_CNTL_SW1 0x0ed1 +#define regGDC1_A2S_CNTL_SW1_BASE_IDX 5 +#define regGDC1_A2S_CNTL_SW2 0x0ed2 +#define regGDC1_A2S_CNTL_SW2_BASE_IDX 5 +#define regGDC1_A2S_TAG_ALLOC_0 0x0edd +#define regGDC1_A2S_TAG_ALLOC_0_BASE_IDX 5 +#define regGDC1_A2S_TAG_ALLOC_1 0x0ede +#define regGDC1_A2S_TAG_ALLOC_1_BASE_IDX 5 +#define regGDC1_A2S_MISC_CNTL 0x0ee1 +#define regGDC1_A2S_MISC_CNTL_BASE_IDX 5 +#define regGDC1_SHUB_REGS_IF_CTL 0x0ee3 +#define regGDC1_SHUB_REGS_IF_CTL_BASE_IDX 5 +#define regGDC1_NGDC_MGCG_CTRL 0x0eea +#define regGDC1_NGDC_MGCG_CTRL_BASE_IDX 5 +#define regGDC1_NGDC_RESERVED_0 0x0eeb +#define regGDC1_NGDC_RESERVED_0_BASE_IDX 5 +#define regGDC1_NGDC_RESERVED_1 0x0eec +#define regGDC1_NGDC_RESERVED_1_BASE_IDX 5 +#define regGDC1_NBIF_GFX_DOORBELL_STATUS 0x0eef +#define regGDC1_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 5 +#define regGDC1_ATDMA_MISC_CNTL 0x0efd +#define regGDC1_ATDMA_MISC_CNTL_BASE_IDX 5 +#define regGDC1_S2A_MISC_CNTL 0x0eff +#define regGDC1_S2A_MISC_CNTL_BASE_IDX 5 +#define regGDC1_NGDC_EARLY_WAKEUP_CTRL 0x0f01 +#define regGDC1_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX 5 +#define regGDC1_NGDC_PG_MISC_CTRL 0x0f18 +#define regGDC1_NGDC_PG_MISC_CTRL_BASE_IDX 5 +#define regGDC1_NGDC_PGMST_CTRL 0x0f19 +#define regGDC1_NGDC_PGMST_CTRL_BASE_IDX 5 +#define regGDC1_NGDC_PGSLV_CTRL 0x0f1a +#define regGDC1_NGDC_PGSLV_CTRL_BASE_IDX 5 + + +// addressBlock: aid_nbio_nbif0_gdc_sec_GDCSEC_DEC +// base address: 0x1400000 +#define regXCC_DOORBELL_FENCE 0x740c +#define regXCC_DOORBELL_FENCE_BASE_IDX 5 + + +// addressBlock: aid_nbio_nbif0_gdc_rst_GDCRST_DEC +// base address: 0x1400000 +#define regSHUB_PF_FLR_RST 0x7c00 +#define regSHUB_PF_FLR_RST_BASE_IDX 5 +#define regSHUB_GFX_DRV_VPU_RST 0x7c01 +#define regSHUB_GFX_DRV_VPU_RST_BASE_IDX 5 +#define regSHUB_LINK_RESET 0x7c02 +#define regSHUB_LINK_RESET_BASE_IDX 5 +#define regSHUB_HARD_RST_CTRL 0x7c10 +#define regSHUB_HARD_RST_CTRL_BASE_IDX 5 +#define regSHUB_SOFT_RST_CTRL 0x7c11 +#define regSHUB_SOFT_RST_CTRL_BASE_IDX 5 +#define regSHUB_SDP_PORT_RST 0x7c12 +#define regSHUB_SDP_PORT_RST_BASE_IDX 5 +#define regSHUB_RST_MISC_TRL 0x7c13 +#define regSHUB_RST_MISC_TRL_BASE_IDX 5 + + +// addressBlock: aid_nbio_nbif0_syshub_mmreg_syshubdirect +// base address: 0x1400000 +#define regHST_CLK0_SW0_CL0_CNTL 0x4140 +#define regHST_CLK0_SW0_CL0_CNTL_BASE_IDX 5 +#define regHST_CLK0_SW1_CL0_CNTL 0x4160 +#define regHST_CLK0_SW1_CL0_CNTL_BASE_IDX 5 +#define regHST_CLK0_SW1_CL1_CNTL 0x4161 +#define regHST_CLK0_SW1_CL1_CNTL_BASE_IDX 5 +#define regHST_CLK0_SW1_CL2_CNTL 0x4162 +#define regHST_CLK0_SW1_CL2_CNTL_BASE_IDX 5 +#define regDMA_CLK0_SW0_CL0_CNTL 0x4240 +#define regDMA_CLK0_SW0_CL0_CNTL_BASE_IDX 5 +#define regDMA_CLK0_SW0_CL1_CNTL 0x4241 +#define regDMA_CLK0_SW0_CL1_CNTL_BASE_IDX 5 +#define regNIC400_1_ASIB_0_FN_MOD 0xc042 +#define regNIC400_1_ASIB_0_FN_MOD_BASE_IDX 5 +#define regNIC400_1_IB_0_FN_MOD 0xfc42 +#define regNIC400_1_IB_0_FN_MOD_BASE_IDX 5 +#define regNIC400_2_ASIB_0_FN_MOD 0x10c42 +#define regNIC400_2_ASIB_0_FN_MOD_BASE_IDX 5 +#define regNIC400_2_ASIB_0_QOS_CNTL 0x10c43 +#define regNIC400_2_ASIB_0_QOS_CNTL_BASE_IDX 5 +#define regNIC400_2_ASIB_0_MAX_OT 0x10c44 +#define regNIC400_2_ASIB_0_MAX_OT_BASE_IDX 5 +#define regNIC400_2_ASIB_0_MAX_COMB_OT 0x10c45 +#define regNIC400_2_ASIB_0_MAX_COMB_OT_BASE_IDX 5 +#define regNIC400_2_ASIB_0_AW_P 0x10c46 +#define regNIC400_2_ASIB_0_AW_P_BASE_IDX 5 +#define regNIC400_2_ASIB_0_AW_B 0x10c47 +#define regNIC400_2_ASIB_0_AW_B_BASE_IDX 5 +#define regNIC400_2_ASIB_0_AW_R 0x10c48 +#define regNIC400_2_ASIB_0_AW_R_BASE_IDX 5 +#define regNIC400_2_ASIB_0_AR_P 0x10c49 +#define regNIC400_2_ASIB_0_AR_P_BASE_IDX 5 +#define regNIC400_2_ASIB_0_AR_B 0x10c4a +#define regNIC400_2_ASIB_0_AR_B_BASE_IDX 5 +#define regNIC400_2_ASIB_0_AR_R 0x10c4b +#define regNIC400_2_ASIB_0_AR_R_BASE_IDX 5 +#define regNIC400_2_ASIB_0_TARGET_FC 0x10c4c +#define regNIC400_2_ASIB_0_TARGET_FC_BASE_IDX 5 +#define regNIC400_2_ASIB_0_KI_FC 0x10c4d +#define regNIC400_2_ASIB_0_KI_FC_BASE_IDX 5 +#define regNIC400_2_ASIB_0_QOS_RANGE 0x10c4e +#define regNIC400_2_ASIB_0_QOS_RANGE_BASE_IDX 5 +#define regNIC400_2_ASIB_1_FN_MOD 0x11042 +#define regNIC400_2_ASIB_1_FN_MOD_BASE_IDX 5 +#define regNIC400_2_ASIB_1_QOS_CNTL 0x11043 +#define regNIC400_2_ASIB_1_QOS_CNTL_BASE_IDX 5 +#define regNIC400_2_ASIB_1_MAX_OT 0x11044 +#define regNIC400_2_ASIB_1_MAX_OT_BASE_IDX 5 +#define regNIC400_2_ASIB_1_MAX_COMB_OT 0x11045 +#define regNIC400_2_ASIB_1_MAX_COMB_OT_BASE_IDX 5 +#define regNIC400_2_ASIB_1_AW_P 0x11046 +#define regNIC400_2_ASIB_1_AW_P_BASE_IDX 5 +#define regNIC400_2_ASIB_1_AW_B 0x11047 +#define regNIC400_2_ASIB_1_AW_B_BASE_IDX 5 +#define regNIC400_2_ASIB_1_AW_R 0x11048 +#define regNIC400_2_ASIB_1_AW_R_BASE_IDX 5 +#define regNIC400_2_ASIB_1_AR_P 0x11049 +#define regNIC400_2_ASIB_1_AR_P_BASE_IDX 5 +#define regNIC400_2_ASIB_1_AR_B 0x1104a +#define regNIC400_2_ASIB_1_AR_B_BASE_IDX 5 +#define regNIC400_2_ASIB_1_AR_R 0x1104b +#define regNIC400_2_ASIB_1_AR_R_BASE_IDX 5 +#define regNIC400_2_ASIB_1_TARGET_FC 0x1104c +#define regNIC400_2_ASIB_1_TARGET_FC_BASE_IDX 5 +#define regNIC400_2_ASIB_1_KI_FC 0x1104d +#define regNIC400_2_ASIB_1_KI_FC_BASE_IDX 5 +#define regNIC400_2_ASIB_1_QOS_RANGE 0x1104e +#define regNIC400_2_ASIB_1_QOS_RANGE_BASE_IDX 5 +#define regNIC400_2_IB_0_FN_MOD 0x13c42 +#define regNIC400_2_IB_0_FN_MOD_BASE_IDX 5 + + +// addressBlock: aid_nbio_iohub_nb_nbcfg_nb_cfgdec +// base address: 0x13b00000 +#define regNB_NBCFG0_NBCFG_SCRATCH_4 0xe8001e +#define regNB_NBCFG0_NBCFG_SCRATCH_4_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_misc_misc_cfgdec +// base address: 0x13b10000 +#define regNB_CNTL 0xe84000 +#define regNB_CNTL_BASE_IDX 8 +#define regNB_SPARE1 0xe84003 +#define regNB_SPARE1_BASE_IDX 8 +#define regNB_SPARE2 0xe84004 +#define regNB_SPARE2_BASE_IDX 8 +#define regNB_REVID 0xe84005 +#define regNB_REVID_BASE_IDX 8 +#define regNBIO_LCLK_DS_MASK 0xe84009 +#define regNBIO_LCLK_DS_MASK_BASE_IDX 8 +#define regNB_BUS_NUM_CNTL 0xe84011 +#define regNB_BUS_NUM_CNTL_BASE_IDX 8 +#define regNB_MMIOBASE 0xe84017 +#define regNB_MMIOBASE_BASE_IDX 8 +#define regNB_MMIOLIMIT 0xe84018 +#define regNB_MMIOLIMIT_BASE_IDX 8 +#define regNB_LOWER_TOP_OF_DRAM2 0xe84019 +#define regNB_LOWER_TOP_OF_DRAM2_BASE_IDX 8 +#define regNB_UPPER_TOP_OF_DRAM2 0xe8401a +#define regNB_UPPER_TOP_OF_DRAM2_BASE_IDX 8 +#define regNB_LOWER_DRAM2_BASE 0xe8401b +#define regNB_LOWER_DRAM2_BASE_BASE_IDX 8 +#define regNB_UPPER_DRAM2_BASE 0xe8401c +#define regNB_UPPER_DRAM2_BASE_BASE_IDX 8 +#define regSB_LOCATION 0xe8401f +#define regSB_LOCATION_BASE_IDX 8 +#define regSW_US_LOCATION 0xe84020 +#define regSW_US_LOCATION_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr0 0xe8402e +#define regNB_PROG_DEVICE_REMAP_PBr0_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr1 0xe8402f +#define regNB_PROG_DEVICE_REMAP_PBr1_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr2 0xe84030 +#define regNB_PROG_DEVICE_REMAP_PBr2_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr3 0xe84031 +#define regNB_PROG_DEVICE_REMAP_PBr3_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr4 0xe84032 +#define regNB_PROG_DEVICE_REMAP_PBr4_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr5 0xe84033 +#define regNB_PROG_DEVICE_REMAP_PBr5_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr6 0xe84034 +#define regNB_PROG_DEVICE_REMAP_PBr6_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr7 0xe84035 +#define regNB_PROG_DEVICE_REMAP_PBr7_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr8 0xe84036 +#define regNB_PROG_DEVICE_REMAP_PBr8_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr10 0xe84038 +#define regNB_PROG_DEVICE_REMAP_PBr10_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr11 0xe84039 +#define regNB_PROG_DEVICE_REMAP_PBr11_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr12 0xe8403a +#define regNB_PROG_DEVICE_REMAP_PBr12_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr13 0xe8403b +#define regNB_PROG_DEVICE_REMAP_PBr13_BASE_IDX 8 +#define regSW_NMI_CNTL 0xe84042 +#define regSW_NMI_CNTL_BASE_IDX 8 +#define regSW_SMI_CNTL 0xe84043 +#define regSW_SMI_CNTL_BASE_IDX 8 +#define regSW_SCI_CNTL 0xe84044 +#define regSW_SCI_CNTL_BASE_IDX 8 +#define regAPML_SW_STATUS 0xe84045 +#define regAPML_SW_STATUS_BASE_IDX 8 +#define regSW_GIC_SPI_CNTL 0xe84047 +#define regSW_GIC_SPI_CNTL_BASE_IDX 8 +#define regSW_SYNCFLOOD_CNTL 0xe84049 +#define regSW_SYNCFLOOD_CNTL_BASE_IDX 8 +#define regNB_TOP_OF_DRAM3 0xe8404e +#define regNB_TOP_OF_DRAM3_BASE_IDX 8 +#define regCAM_CONTROL 0xe84052 +#define regCAM_CONTROL_BASE_IDX 8 +#define regCAM_TARGET_INDEX_ADDR_BOTTOM 0xe84053 +#define regCAM_TARGET_INDEX_ADDR_BOTTOM_BASE_IDX 8 +#define regCAM_TARGET_INDEX_ADDR_TOP 0xe84054 +#define regCAM_TARGET_INDEX_ADDR_TOP_BASE_IDX 8 +#define regCAM_TARGET_INDEX_DATA 0xe84055 +#define regCAM_TARGET_INDEX_DATA_BASE_IDX 8 +#define regCAM_TARGET_INDEX_DATA_MASK 0xe84056 +#define regCAM_TARGET_INDEX_DATA_MASK_BASE_IDX 8 +#define regCAM_TARGET_DATA_ADDR_BOTTOM 0xe84057 +#define regCAM_TARGET_DATA_ADDR_BOTTOM_BASE_IDX 8 +#define regCAM_TARGET_DATA_ADDR_TOP 0xe84059 +#define regCAM_TARGET_DATA_ADDR_TOP_BASE_IDX 8 +#define regCAM_TARGET_DATA 0xe8405a +#define regCAM_TARGET_DATA_BASE_IDX 8 +#define regCAM_TARGET_DATA_MASK 0xe8405b +#define regCAM_TARGET_DATA_MASK_BASE_IDX 8 +#define regP_DMA_DROPPED_LOG_LOWER 0xe84060 +#define regP_DMA_DROPPED_LOG_LOWER_BASE_IDX 8 +#define regP_DMA_DROPPED_LOG_UPPER 0xe84061 +#define regP_DMA_DROPPED_LOG_UPPER_BASE_IDX 8 +#define regNP_DMA_DROPPED_LOG_LOWER 0xe84062 +#define regNP_DMA_DROPPED_LOG_LOWER_BASE_IDX 8 +#define regNP_DMA_DROPPED_LOG_UPPER 0xe84063 +#define regNP_DMA_DROPPED_LOG_UPPER_BASE_IDX 8 +#define regPCIE_VDM_NODE0_CTRL4 0xe84064 +#define regPCIE_VDM_NODE0_CTRL4_BASE_IDX 8 +#define regPCIE_VDM_CNTL2 0xe8408c +#define regPCIE_VDM_CNTL2_BASE_IDX 8 +#define regPCIE_VDM_CNTL3 0xe8408d +#define regPCIE_VDM_CNTL3_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT0_0 0xe84090 +#define regSTALL_CONTROL_XBARPORT0_0_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT0_1 0xe84091 +#define regSTALL_CONTROL_XBARPORT0_1_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT1_0 0xe84093 +#define regSTALL_CONTROL_XBARPORT1_0_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT1_1 0xe84094 +#define regSTALL_CONTROL_XBARPORT1_1_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT2_0 0xe84096 +#define regSTALL_CONTROL_XBARPORT2_0_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT2_1 0xe84097 +#define regSTALL_CONTROL_XBARPORT2_1_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT3_0 0xe84099 +#define regSTALL_CONTROL_XBARPORT3_0_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT3_1 0xe8409a +#define regSTALL_CONTROL_XBARPORT3_1_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT4_0 0xe8409c +#define regSTALL_CONTROL_XBARPORT4_0_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT4_1 0xe8409d +#define regSTALL_CONTROL_XBARPORT4_1_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT5_0 0xe8409f +#define regSTALL_CONTROL_XBARPORT5_0_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT5_1 0xe840a0 +#define regSTALL_CONTROL_XBARPORT5_1_BASE_IDX 8 +#define regNB_DRAM3_BASE 0xe840b1 +#define regNB_DRAM3_BASE_BASE_IDX 8 +#define regPSP_BASE_ADDR_LO 0xe840b8 +#define regPSP_BASE_ADDR_LO_BASE_IDX 8 +#define regPSP_BASE_ADDR_HI 0xe840b9 +#define regPSP_BASE_ADDR_HI_BASE_IDX 8 +#define regSMU_BASE_ADDR_LO 0xe840ba +#define regSMU_BASE_ADDR_LO_BASE_IDX 8 +#define regSMU_BASE_ADDR_HI 0xe840bb +#define regSMU_BASE_ADDR_HI_BASE_IDX 8 +#define regSCRATCH_4 0xe840fc +#define regSCRATCH_4_BASE_IDX 8 +#define regSCRATCH_5 0xe840fd +#define regSCRATCH_5_BASE_IDX 8 +#define regSMU_BLOCK_CPU 0xe840fe +#define regSMU_BLOCK_CPU_BASE_IDX 8 +#define regSMU_BLOCK_CPU_STATUS 0xe840ff +#define regSMU_BLOCK_CPU_STATUS_BASE_IDX 8 +#define regTRAP_STATUS 0xe84100 +#define regTRAP_STATUS_BASE_IDX 8 +#define regTRAP_REQUEST0 0xe84101 +#define regTRAP_REQUEST0_BASE_IDX 8 +#define regTRAP_REQUEST1 0xe84102 +#define regTRAP_REQUEST1_BASE_IDX 8 +#define regTRAP_REQUEST2 0xe84103 +#define regTRAP_REQUEST2_BASE_IDX 8 +#define regTRAP_REQUEST3 0xe84104 +#define regTRAP_REQUEST3_BASE_IDX 8 +#define regTRAP_REQUEST4 0xe84105 +#define regTRAP_REQUEST4_BASE_IDX 8 +#define regTRAP_REQUEST5 0xe84106 +#define regTRAP_REQUEST5_BASE_IDX 8 +#define regTRAP_REQUEST_DATASTRB0 0xe84108 +#define regTRAP_REQUEST_DATASTRB0_BASE_IDX 8 +#define regTRAP_REQUEST_DATASTRB1 0xe84109 +#define regTRAP_REQUEST_DATASTRB1_BASE_IDX 8 +#define regTRAP_REQUEST_DATA0 0xe84110 +#define regTRAP_REQUEST_DATA0_BASE_IDX 8 +#define regTRAP_REQUEST_DATA1 0xe84111 +#define regTRAP_REQUEST_DATA1_BASE_IDX 8 +#define regTRAP_REQUEST_DATA2 0xe84112 +#define regTRAP_REQUEST_DATA2_BASE_IDX 8 +#define regTRAP_REQUEST_DATA3 0xe84113 +#define regTRAP_REQUEST_DATA3_BASE_IDX 8 +#define regTRAP_REQUEST_DATA4 0xe84114 +#define regTRAP_REQUEST_DATA4_BASE_IDX 8 +#define regTRAP_REQUEST_DATA5 0xe84115 +#define regTRAP_REQUEST_DATA5_BASE_IDX 8 +#define regTRAP_REQUEST_DATA6 0xe84116 +#define regTRAP_REQUEST_DATA6_BASE_IDX 8 +#define regTRAP_REQUEST_DATA7 0xe84117 +#define regTRAP_REQUEST_DATA7_BASE_IDX 8 +#define regTRAP_REQUEST_DATA8 0xe84118 +#define regTRAP_REQUEST_DATA8_BASE_IDX 8 +#define regTRAP_REQUEST_DATA9 0xe84119 +#define regTRAP_REQUEST_DATA9_BASE_IDX 8 +#define regTRAP_REQUEST_DATA10 0xe8411a +#define regTRAP_REQUEST_DATA10_BASE_IDX 8 +#define regTRAP_REQUEST_DATA11 0xe8411b +#define regTRAP_REQUEST_DATA11_BASE_IDX 8 +#define regTRAP_REQUEST_DATA12 0xe8411c +#define regTRAP_REQUEST_DATA12_BASE_IDX 8 +#define regTRAP_REQUEST_DATA13 0xe8411d +#define regTRAP_REQUEST_DATA13_BASE_IDX 8 +#define regTRAP_REQUEST_DATA14 0xe8411e +#define regTRAP_REQUEST_DATA14_BASE_IDX 8 +#define regTRAP_REQUEST_DATA15 0xe8411f +#define regTRAP_REQUEST_DATA15_BASE_IDX 8 +#define regTRAP_RESPONSE_CONTROL 0xe84130 +#define regTRAP_RESPONSE_CONTROL_BASE_IDX 8 +#define regTRAP_RESPONSE0 0xe84131 +#define regTRAP_RESPONSE0_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA0 0xe84140 +#define regTRAP_RESPONSE_DATA0_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA1 0xe84141 +#define regTRAP_RESPONSE_DATA1_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA2 0xe84142 +#define regTRAP_RESPONSE_DATA2_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA3 0xe84143 +#define regTRAP_RESPONSE_DATA3_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA4 0xe84144 +#define regTRAP_RESPONSE_DATA4_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA5 0xe84145 +#define regTRAP_RESPONSE_DATA5_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA6 0xe84146 +#define regTRAP_RESPONSE_DATA6_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA7 0xe84147 +#define regTRAP_RESPONSE_DATA7_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA8 0xe84148 +#define regTRAP_RESPONSE_DATA8_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA9 0xe84149 +#define regTRAP_RESPONSE_DATA9_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA10 0xe8414a +#define regTRAP_RESPONSE_DATA10_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA11 0xe8414b +#define regTRAP_RESPONSE_DATA11_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA12 0xe8414c +#define regTRAP_RESPONSE_DATA12_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA13 0xe8414d +#define regTRAP_RESPONSE_DATA13_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA14 0xe8414e +#define regTRAP_RESPONSE_DATA14_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA15 0xe8414f +#define regTRAP_RESPONSE_DATA15_BASE_IDX 8 +#define regTRAP0_CONTROL0 0xe84200 +#define regTRAP0_CONTROL0_BASE_IDX 8 +#define regTRAP0_ADDRESS_LO 0xe84202 +#define regTRAP0_ADDRESS_LO_BASE_IDX 8 +#define regTRAP0_ADDRESS_HI 0xe84203 +#define regTRAP0_ADDRESS_HI_BASE_IDX 8 +#define regTRAP0_COMMAND 0xe84204 +#define regTRAP0_COMMAND_BASE_IDX 8 +#define regTRAP0_ADDRESS_LO_MASK 0xe84206 +#define regTRAP0_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP0_ADDRESS_HI_MASK 0xe84207 +#define regTRAP0_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP0_COMMAND_MASK 0xe84208 +#define regTRAP0_COMMAND_MASK_BASE_IDX 8 +#define regTRAP1_CONTROL0 0xe84210 +#define regTRAP1_CONTROL0_BASE_IDX 8 +#define regTRAP1_ADDRESS_LO 0xe84212 +#define regTRAP1_ADDRESS_LO_BASE_IDX 8 +#define regTRAP1_ADDRESS_HI 0xe84213 +#define regTRAP1_ADDRESS_HI_BASE_IDX 8 +#define regTRAP1_COMMAND 0xe84214 +#define regTRAP1_COMMAND_BASE_IDX 8 +#define regTRAP1_ADDRESS_LO_MASK 0xe84216 +#define regTRAP1_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP1_ADDRESS_HI_MASK 0xe84217 +#define regTRAP1_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP1_COMMAND_MASK 0xe84218 +#define regTRAP1_COMMAND_MASK_BASE_IDX 8 +#define regTRAP2_CONTROL0 0xe84220 +#define regTRAP2_CONTROL0_BASE_IDX 8 +#define regTRAP2_ADDRESS_LO 0xe84222 +#define regTRAP2_ADDRESS_LO_BASE_IDX 8 +#define regTRAP2_ADDRESS_HI 0xe84223 +#define regTRAP2_ADDRESS_HI_BASE_IDX 8 +#define regTRAP2_COMMAND 0xe84224 +#define regTRAP2_COMMAND_BASE_IDX 8 +#define regTRAP2_ADDRESS_LO_MASK 0xe84226 +#define regTRAP2_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP2_ADDRESS_HI_MASK 0xe84227 +#define regTRAP2_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP2_COMMAND_MASK 0xe84228 +#define regTRAP2_COMMAND_MASK_BASE_IDX 8 +#define regTRAP3_CONTROL0 0xe84230 +#define regTRAP3_CONTROL0_BASE_IDX 8 +#define regTRAP3_ADDRESS_LO 0xe84232 +#define regTRAP3_ADDRESS_LO_BASE_IDX 8 +#define regTRAP3_ADDRESS_HI 0xe84233 +#define regTRAP3_ADDRESS_HI_BASE_IDX 8 +#define regTRAP3_COMMAND 0xe84234 +#define regTRAP3_COMMAND_BASE_IDX 8 +#define regTRAP3_ADDRESS_LO_MASK 0xe84236 +#define regTRAP3_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP3_ADDRESS_HI_MASK 0xe84237 +#define regTRAP3_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP3_COMMAND_MASK 0xe84238 +#define regTRAP3_COMMAND_MASK_BASE_IDX 8 +#define regTRAP4_CONTROL0 0xe84240 +#define regTRAP4_CONTROL0_BASE_IDX 8 +#define regTRAP4_ADDRESS_LO 0xe84242 +#define regTRAP4_ADDRESS_LO_BASE_IDX 8 +#define regTRAP4_ADDRESS_HI 0xe84243 +#define regTRAP4_ADDRESS_HI_BASE_IDX 8 +#define regTRAP4_COMMAND 0xe84244 +#define regTRAP4_COMMAND_BASE_IDX 8 +#define regTRAP4_ADDRESS_LO_MASK 0xe84246 +#define regTRAP4_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP4_ADDRESS_HI_MASK 0xe84247 +#define regTRAP4_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP4_COMMAND_MASK 0xe84248 +#define regTRAP4_COMMAND_MASK_BASE_IDX 8 +#define regTRAP5_CONTROL0 0xe84250 +#define regTRAP5_CONTROL0_BASE_IDX 8 +#define regTRAP5_ADDRESS_LO 0xe84252 +#define regTRAP5_ADDRESS_LO_BASE_IDX 8 +#define regTRAP5_ADDRESS_HI 0xe84253 +#define regTRAP5_ADDRESS_HI_BASE_IDX 8 +#define regTRAP5_COMMAND 0xe84254 +#define regTRAP5_COMMAND_BASE_IDX 8 +#define regTRAP5_ADDRESS_LO_MASK 0xe84256 +#define regTRAP5_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP5_ADDRESS_HI_MASK 0xe84257 +#define regTRAP5_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP5_COMMAND_MASK 0xe84258 +#define regTRAP5_COMMAND_MASK_BASE_IDX 8 +#define regTRAP6_CONTROL0 0xe84260 +#define regTRAP6_CONTROL0_BASE_IDX 8 +#define regTRAP6_ADDRESS_LO 0xe84262 +#define regTRAP6_ADDRESS_LO_BASE_IDX 8 +#define regTRAP6_ADDRESS_HI 0xe84263 +#define regTRAP6_ADDRESS_HI_BASE_IDX 8 +#define regTRAP6_COMMAND 0xe84264 +#define regTRAP6_COMMAND_BASE_IDX 8 +#define regTRAP6_ADDRESS_LO_MASK 0xe84266 +#define regTRAP6_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP6_ADDRESS_HI_MASK 0xe84267 +#define regTRAP6_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP6_COMMAND_MASK 0xe84268 +#define regTRAP6_COMMAND_MASK_BASE_IDX 8 +#define regTRAP7_CONTROL0 0xe84270 +#define regTRAP7_CONTROL0_BASE_IDX 8 +#define regTRAP7_ADDRESS_LO 0xe84272 +#define regTRAP7_ADDRESS_LO_BASE_IDX 8 +#define regTRAP7_ADDRESS_HI 0xe84273 +#define regTRAP7_ADDRESS_HI_BASE_IDX 8 +#define regTRAP7_COMMAND 0xe84274 +#define regTRAP7_COMMAND_BASE_IDX 8 +#define regTRAP7_ADDRESS_LO_MASK 0xe84276 +#define regTRAP7_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP7_ADDRESS_HI_MASK 0xe84277 +#define regTRAP7_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP7_COMMAND_MASK 0xe84278 +#define regTRAP7_COMMAND_MASK_BASE_IDX 8 +#define regTRAP8_CONTROL0 0xe84280 +#define regTRAP8_CONTROL0_BASE_IDX 8 +#define regTRAP8_ADDRESS_LO 0xe84282 +#define regTRAP8_ADDRESS_LO_BASE_IDX 8 +#define regTRAP8_ADDRESS_HI 0xe84283 +#define regTRAP8_ADDRESS_HI_BASE_IDX 8 +#define regTRAP8_COMMAND 0xe84284 +#define regTRAP8_COMMAND_BASE_IDX 8 +#define regTRAP8_ADDRESS_LO_MASK 0xe84286 +#define regTRAP8_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP8_ADDRESS_HI_MASK 0xe84287 +#define regTRAP8_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP8_COMMAND_MASK 0xe84288 +#define regTRAP8_COMMAND_MASK_BASE_IDX 8 +#define regTRAP9_CONTROL0 0xe84290 +#define regTRAP9_CONTROL0_BASE_IDX 8 +#define regTRAP9_ADDRESS_LO 0xe84292 +#define regTRAP9_ADDRESS_LO_BASE_IDX 8 +#define regTRAP9_ADDRESS_HI 0xe84293 +#define regTRAP9_ADDRESS_HI_BASE_IDX 8 +#define regTRAP9_COMMAND 0xe84294 +#define regTRAP9_COMMAND_BASE_IDX 8 +#define regTRAP9_ADDRESS_LO_MASK 0xe84296 +#define regTRAP9_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP9_ADDRESS_HI_MASK 0xe84297 +#define regTRAP9_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP9_COMMAND_MASK 0xe84298 +#define regTRAP9_COMMAND_MASK_BASE_IDX 8 +#define regTRAP10_CONTROL0 0xe842a0 +#define regTRAP10_CONTROL0_BASE_IDX 8 +#define regTRAP10_ADDRESS_LO 0xe842a2 +#define regTRAP10_ADDRESS_LO_BASE_IDX 8 +#define regTRAP10_ADDRESS_HI 0xe842a3 +#define regTRAP10_ADDRESS_HI_BASE_IDX 8 +#define regTRAP10_COMMAND 0xe842a4 +#define regTRAP10_COMMAND_BASE_IDX 8 +#define regTRAP10_ADDRESS_LO_MASK 0xe842a6 +#define regTRAP10_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP10_ADDRESS_HI_MASK 0xe842a7 +#define regTRAP10_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP10_COMMAND_MASK 0xe842a8 +#define regTRAP10_COMMAND_MASK_BASE_IDX 8 +#define regTRAP11_CONTROL0 0xe842b0 +#define regTRAP11_CONTROL0_BASE_IDX 8 +#define regTRAP11_ADDRESS_LO 0xe842b2 +#define regTRAP11_ADDRESS_LO_BASE_IDX 8 +#define regTRAP11_ADDRESS_HI 0xe842b3 +#define regTRAP11_ADDRESS_HI_BASE_IDX 8 +#define regTRAP11_COMMAND 0xe842b4 +#define regTRAP11_COMMAND_BASE_IDX 8 +#define regTRAP11_ADDRESS_LO_MASK 0xe842b6 +#define regTRAP11_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP11_ADDRESS_HI_MASK 0xe842b7 +#define regTRAP11_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP11_COMMAND_MASK 0xe842b8 +#define regTRAP11_COMMAND_MASK_BASE_IDX 8 +#define regTRAP12_CONTROL0 0xe842c0 +#define regTRAP12_CONTROL0_BASE_IDX 8 +#define regTRAP12_ADDRESS_LO 0xe842c2 +#define regTRAP12_ADDRESS_LO_BASE_IDX 8 +#define regTRAP12_ADDRESS_HI 0xe842c3 +#define regTRAP12_ADDRESS_HI_BASE_IDX 8 +#define regTRAP12_COMMAND 0xe842c4 +#define regTRAP12_COMMAND_BASE_IDX 8 +#define regTRAP12_ADDRESS_LO_MASK 0xe842c6 +#define regTRAP12_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP12_ADDRESS_HI_MASK 0xe842c7 +#define regTRAP12_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP12_COMMAND_MASK 0xe842c8 +#define regTRAP12_COMMAND_MASK_BASE_IDX 8 +#define regTRAP13_CONTROL0 0xe842d0 +#define regTRAP13_CONTROL0_BASE_IDX 8 +#define regTRAP13_ADDRESS_LO 0xe842d2 +#define regTRAP13_ADDRESS_LO_BASE_IDX 8 +#define regTRAP13_ADDRESS_HI 0xe842d3 +#define regTRAP13_ADDRESS_HI_BASE_IDX 8 +#define regTRAP13_COMMAND 0xe842d4 +#define regTRAP13_COMMAND_BASE_IDX 8 +#define regTRAP13_ADDRESS_LO_MASK 0xe842d6 +#define regTRAP13_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP13_ADDRESS_HI_MASK 0xe842d7 +#define regTRAP13_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP13_COMMAND_MASK 0xe842d8 +#define regTRAP13_COMMAND_MASK_BASE_IDX 8 +#define regTRAP14_CONTROL0 0xe842e0 +#define regTRAP14_CONTROL0_BASE_IDX 8 +#define regTRAP14_ADDRESS_LO 0xe842e2 +#define regTRAP14_ADDRESS_LO_BASE_IDX 8 +#define regTRAP14_ADDRESS_HI 0xe842e3 +#define regTRAP14_ADDRESS_HI_BASE_IDX 8 +#define regTRAP14_COMMAND 0xe842e4 +#define regTRAP14_COMMAND_BASE_IDX 8 +#define regTRAP14_ADDRESS_LO_MASK 0xe842e6 +#define regTRAP14_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP14_ADDRESS_HI_MASK 0xe842e7 +#define regTRAP14_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP14_COMMAND_MASK 0xe842e8 +#define regTRAP14_COMMAND_MASK_BASE_IDX 8 +#define regTRAP15_CONTROL0 0xe842f0 +#define regTRAP15_CONTROL0_BASE_IDX 8 +#define regTRAP15_ADDRESS_LO 0xe842f2 +#define regTRAP15_ADDRESS_LO_BASE_IDX 8 +#define regTRAP15_ADDRESS_HI 0xe842f3 +#define regTRAP15_ADDRESS_HI_BASE_IDX 8 +#define regTRAP15_COMMAND 0xe842f4 +#define regTRAP15_COMMAND_BASE_IDX 8 +#define regTRAP15_ADDRESS_LO_MASK 0xe842f6 +#define regTRAP15_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP15_ADDRESS_HI_MASK 0xe842f7 +#define regTRAP15_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP15_COMMAND_MASK 0xe842f8 +#define regTRAP15_COMMAND_MASK_BASE_IDX 8 +#define regSB_COMMAND 0xe85000 +#define regSB_COMMAND_BASE_IDX 8 +#define regSB_SUB_BUS_NUMBER_LATENCY 0xe85001 +#define regSB_SUB_BUS_NUMBER_LATENCY_BASE_IDX 8 +#define regSB_IO_BASE_LIMIT 0xe85002 +#define regSB_IO_BASE_LIMIT_BASE_IDX 8 +#define regSB_MEM_BASE_LIMIT 0xe85003 +#define regSB_MEM_BASE_LIMIT_BASE_IDX 8 +#define regSB_PREF_BASE_LIMIT 0xe85004 +#define regSB_PREF_BASE_LIMIT_BASE_IDX 8 +#define regSB_PREF_BASE_UPPER 0xe85005 +#define regSB_PREF_BASE_UPPER_BASE_IDX 8 +#define regSB_PREF_LIMIT_UPPER 0xe85006 +#define regSB_PREF_LIMIT_UPPER_BASE_IDX 8 +#define regSB_IO_BASE_LIMIT_HI 0xe85007 +#define regSB_IO_BASE_LIMIT_HI_BASE_IDX 8 +#define regSB_IRQ_BRIDGE_CNTL 0xe85008 +#define regSB_IRQ_BRIDGE_CNTL_BASE_IDX 8 +#define regSB_EXT_BRIDGE_CNTL 0xe85009 +#define regSB_EXT_BRIDGE_CNTL_BASE_IDX 8 +#define regSB_PMI_STATUS_CNTL 0xe8500a +#define regSB_PMI_STATUS_CNTL_BASE_IDX 8 +#define regSB_SLOT_CAP 0xe8500b +#define regSB_SLOT_CAP_BASE_IDX 8 +#define regSB_ROOT_CNTL 0xe8500c +#define regSB_ROOT_CNTL_BASE_IDX 8 +#define regSB_DEVICE_CNTL2 0xe8500d +#define regSB_DEVICE_CNTL2_BASE_IDX 8 +#define regMCA_SMN_INT_REQ_ADDR 0xe85020 +#define regMCA_SMN_INT_REQ_ADDR_BASE_IDX 8 +#define regMCA_SMN_INT_MCM_ADDR 0xe85021 +#define regMCA_SMN_INT_MCM_ADDR_BASE_IDX 8 +#define regMCA_SMN_INT_APERTUREID 0xe85022 +#define regMCA_SMN_INT_APERTUREID_BASE_IDX 8 +#define regMCA_SMN_INT_CONTROL 0xe85023 +#define regMCA_SMN_INT_CONTROL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_rascfg_ras_cfgdec +// base address: 0x13b20000 +#define regPARITY_CONTROL_0 0xe88000 +#define regPARITY_CONTROL_0_BASE_IDX 8 +#define regPARITY_CONTROL_1 0xe88001 +#define regPARITY_CONTROL_1_BASE_IDX 8 +#define regPARITY_SEVERITY_CONTROL_UNCORR_0 0xe88002 +#define regPARITY_SEVERITY_CONTROL_UNCORR_0_BASE_IDX 8 +#define regPARITY_SEVERITY_CONTROL_CORR_0 0xe88004 +#define regPARITY_SEVERITY_CONTROL_CORR_0_BASE_IDX 8 +#define regPARITY_SEVERITY_CONTROL_UCP_0 0xe88006 +#define regPARITY_SEVERITY_CONTROL_UCP_0_BASE_IDX 8 +#define regRAS_GLOBAL_STATUS_LO 0xe88008 +#define regRAS_GLOBAL_STATUS_LO_BASE_IDX 8 +#define regRAS_GLOBAL_STATUS_HI 0xe88009 +#define regRAS_GLOBAL_STATUS_HI_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP0 0xe8800a +#define regPARITY_ERROR_STATUS_UNCORR_GRP0_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP1 0xe8800b +#define regPARITY_ERROR_STATUS_UNCORR_GRP1_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP2 0xe8800c +#define regPARITY_ERROR_STATUS_UNCORR_GRP2_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP3 0xe8800d +#define regPARITY_ERROR_STATUS_UNCORR_GRP3_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP4 0xe8800e +#define regPARITY_ERROR_STATUS_UNCORR_GRP4_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP5 0xe8800f +#define regPARITY_ERROR_STATUS_UNCORR_GRP5_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP6 0xe88010 +#define regPARITY_ERROR_STATUS_UNCORR_GRP6_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP7 0xe88011 +#define regPARITY_ERROR_STATUS_UNCORR_GRP7_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP10 0xe88014 +#define regPARITY_ERROR_STATUS_UNCORR_GRP10_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP11 0xe88015 +#define regPARITY_ERROR_STATUS_UNCORR_GRP11_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP12 0xe88016 +#define regPARITY_ERROR_STATUS_UNCORR_GRP12_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP13 0xe88017 +#define regPARITY_ERROR_STATUS_UNCORR_GRP13_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP14 0xe88018 +#define regPARITY_ERROR_STATUS_UNCORR_GRP14_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP15 0xe88019 +#define regPARITY_ERROR_STATUS_UNCORR_GRP15_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP16 0xe8801a +#define regPARITY_ERROR_STATUS_UNCORR_GRP16_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP0 0xe8801b +#define regPARITY_ERROR_STATUS_CORR_GRP0_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP1 0xe8801c +#define regPARITY_ERROR_STATUS_CORR_GRP1_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP2 0xe8801d +#define regPARITY_ERROR_STATUS_CORR_GRP2_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP3 0xe8801e +#define regPARITY_ERROR_STATUS_CORR_GRP3_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP4 0xe8801f +#define regPARITY_ERROR_STATUS_CORR_GRP4_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP5 0xe88020 +#define regPARITY_ERROR_STATUS_CORR_GRP5_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP6 0xe88021 +#define regPARITY_ERROR_STATUS_CORR_GRP6_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP7 0xe88022 +#define regPARITY_ERROR_STATUS_CORR_GRP7_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP10 0xe88025 +#define regPARITY_ERROR_STATUS_CORR_GRP10_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP11 0xe88026 +#define regPARITY_ERROR_STATUS_CORR_GRP11_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP12 0xe88027 +#define regPARITY_ERROR_STATUS_CORR_GRP12_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP13 0xe88028 +#define regPARITY_ERROR_STATUS_CORR_GRP13_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP14 0xe88029 +#define regPARITY_ERROR_STATUS_CORR_GRP14_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP15 0xe8802a +#define regPARITY_ERROR_STATUS_CORR_GRP15_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP16 0xe8802b +#define regPARITY_ERROR_STATUS_CORR_GRP16_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP17 0xe8802c +#define regPARITY_ERROR_STATUS_CORR_GRP17_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP0 0xe8802d +#define regPARITY_COUNTER_CORR_GRP0_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP1 0xe8802e +#define regPARITY_COUNTER_CORR_GRP1_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP2 0xe8802f +#define regPARITY_COUNTER_CORR_GRP2_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP3 0xe88030 +#define regPARITY_COUNTER_CORR_GRP3_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP4 0xe88031 +#define regPARITY_COUNTER_CORR_GRP4_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP5 0xe88032 +#define regPARITY_COUNTER_CORR_GRP5_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP6 0xe88033 +#define regPARITY_COUNTER_CORR_GRP6_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP7 0xe88034 +#define regPARITY_COUNTER_CORR_GRP7_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP10 0xe88037 +#define regPARITY_COUNTER_CORR_GRP10_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP11 0xe88038 +#define regPARITY_COUNTER_CORR_GRP11_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP12 0xe88039 +#define regPARITY_COUNTER_CORR_GRP12_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP13 0xe8803a +#define regPARITY_COUNTER_CORR_GRP13_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP14 0xe8803b +#define regPARITY_COUNTER_CORR_GRP14_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP15 0xe8803c +#define regPARITY_COUNTER_CORR_GRP15_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP16 0xe8803d +#define regPARITY_COUNTER_CORR_GRP16_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP17 0xe8803e +#define regPARITY_COUNTER_CORR_GRP17_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP0 0xe8803f +#define regPARITY_ERROR_STATUS_UCP_GRP0_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP1 0xe88040 +#define regPARITY_ERROR_STATUS_UCP_GRP1_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP2 0xe88041 +#define regPARITY_ERROR_STATUS_UCP_GRP2_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP3 0xe88042 +#define regPARITY_ERROR_STATUS_UCP_GRP3_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP4 0xe88043 +#define regPARITY_ERROR_STATUS_UCP_GRP4_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP5 0xe88044 +#define regPARITY_ERROR_STATUS_UCP_GRP5_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP6 0xe88045 +#define regPARITY_ERROR_STATUS_UCP_GRP6_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP7 0xe88046 +#define regPARITY_ERROR_STATUS_UCP_GRP7_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP10 0xe88049 +#define regPARITY_ERROR_STATUS_UCP_GRP10_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP11 0xe8804a +#define regPARITY_ERROR_STATUS_UCP_GRP11_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP12 0xe8804b +#define regPARITY_ERROR_STATUS_UCP_GRP12_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP0 0xe8804c +#define regPARITY_COUNTER_UCP_GRP0_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP1 0xe8804d +#define regPARITY_COUNTER_UCP_GRP1_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP2 0xe8804e +#define regPARITY_COUNTER_UCP_GRP2_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP3 0xe8804f +#define regPARITY_COUNTER_UCP_GRP3_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP4 0xe88050 +#define regPARITY_COUNTER_UCP_GRP4_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP5 0xe88051 +#define regPARITY_COUNTER_UCP_GRP5_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP6 0xe88052 +#define regPARITY_COUNTER_UCP_GRP6_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP7 0xe88053 +#define regPARITY_COUNTER_UCP_GRP7_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP10 0xe88056 +#define regPARITY_COUNTER_UCP_GRP10_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP11 0xe88057 +#define regPARITY_COUNTER_UCP_GRP11_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP12 0xe88058 +#define regPARITY_COUNTER_UCP_GRP12_BASE_IDX 8 +#define regMISC_SEVERITY_CONTROL 0xe88059 +#define regMISC_SEVERITY_CONTROL_BASE_IDX 8 +#define regMISC_RAS_CONTROL 0xe8805a +#define regMISC_RAS_CONTROL_BASE_IDX 8 +#define regRAS_SCRATCH_0 0xe8805b +#define regRAS_SCRATCH_0_BASE_IDX 8 +#define regRAS_SCRATCH_1 0xe8805c +#define regRAS_SCRATCH_1_BASE_IDX 8 +#define regErrEvent_ACTION_CONTROL 0xe8805d +#define regErrEvent_ACTION_CONTROL_BASE_IDX 8 +#define regParitySerr_ACTION_CONTROL 0xe8805e +#define regParitySerr_ACTION_CONTROL_BASE_IDX 8 +#define regParityFatal_ACTION_CONTROL 0xe8805f +#define regParityFatal_ACTION_CONTROL_BASE_IDX 8 +#define regParityNonFatal_ACTION_CONTROL 0xe88060 +#define regParityNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regParityCorr_ACTION_CONTROL 0xe88061 +#define regParityCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortASerr_ACTION_CONTROL 0xe88062 +#define regPCIE0PortASerr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortAIntFatal_ACTION_CONTROL 0xe88063 +#define regPCIE0PortAIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortAIntNonFatal_ACTION_CONTROL 0xe88064 +#define regPCIE0PortAIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortAIntCorr_ACTION_CONTROL 0xe88065 +#define regPCIE0PortAIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortAExtFatal_ACTION_CONTROL 0xe88066 +#define regPCIE0PortAExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortAExtNonFatal_ACTION_CONTROL 0xe88067 +#define regPCIE0PortAExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortAExtCorr_ACTION_CONTROL 0xe88068 +#define regPCIE0PortAExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortAParityErr_ACTION_CONTROL 0xe88069 +#define regPCIE0PortAParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBSerr_ACTION_CONTROL 0xe8806a +#define regPCIE0PortBSerr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBIntFatal_ACTION_CONTROL 0xe8806b +#define regPCIE0PortBIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBIntNonFatal_ACTION_CONTROL 0xe8806c +#define regPCIE0PortBIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBIntCorr_ACTION_CONTROL 0xe8806d +#define regPCIE0PortBIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBExtFatal_ACTION_CONTROL 0xe8806e +#define regPCIE0PortBExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBExtNonFatal_ACTION_CONTROL 0xe8806f +#define regPCIE0PortBExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBExtCorr_ACTION_CONTROL 0xe88070 +#define regPCIE0PortBExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBParityErr_ACTION_CONTROL 0xe88071 +#define regPCIE0PortBParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCSerr_ACTION_CONTROL 0xe88072 +#define regPCIE0PortCSerr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCIntFatal_ACTION_CONTROL 0xe88073 +#define regPCIE0PortCIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCIntNonFatal_ACTION_CONTROL 0xe88074 +#define regPCIE0PortCIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCIntCorr_ACTION_CONTROL 0xe88075 +#define regPCIE0PortCIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCExtFatal_ACTION_CONTROL 0xe88076 +#define regPCIE0PortCExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCExtNonFatal_ACTION_CONTROL 0xe88077 +#define regPCIE0PortCExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCExtCorr_ACTION_CONTROL 0xe88078 +#define regPCIE0PortCExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCParityErr_ACTION_CONTROL 0xe88079 +#define regPCIE0PortCParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDSerr_ACTION_CONTROL 0xe8807a +#define regPCIE0PortDSerr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDIntFatal_ACTION_CONTROL 0xe8807b +#define regPCIE0PortDIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDIntNonFatal_ACTION_CONTROL 0xe8807c +#define regPCIE0PortDIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDIntCorr_ACTION_CONTROL 0xe8807d +#define regPCIE0PortDIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDExtFatal_ACTION_CONTROL 0xe8807e +#define regPCIE0PortDExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDExtNonFatal_ACTION_CONTROL 0xe8807f +#define regPCIE0PortDExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDExtCorr_ACTION_CONTROL 0xe88080 +#define regPCIE0PortDExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDParityErr_ACTION_CONTROL 0xe88081 +#define regPCIE0PortDParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortESerr_ACTION_CONTROL 0xe88082 +#define regPCIE0PortESerr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortEIntFatal_ACTION_CONTROL 0xe88083 +#define regPCIE0PortEIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortEIntNonFatal_ACTION_CONTROL 0xe88084 +#define regPCIE0PortEIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortEIntCorr_ACTION_CONTROL 0xe88085 +#define regPCIE0PortEIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortEExtFatal_ACTION_CONTROL 0xe88086 +#define regPCIE0PortEExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortEExtNonFatal_ACTION_CONTROL 0xe88087 +#define regPCIE0PortEExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortEExtCorr_ACTION_CONTROL 0xe88088 +#define regPCIE0PortEExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortEParityErr_ACTION_CONTROL 0xe88089 +#define regPCIE0PortEParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFSerr_ACTION_CONTROL 0xe8808a +#define regPCIE0PortFSerr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFIntFatal_ACTION_CONTROL 0xe8808b +#define regPCIE0PortFIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFIntNonFatal_ACTION_CONTROL 0xe8808c +#define regPCIE0PortFIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFIntCorr_ACTION_CONTROL 0xe8808d +#define regPCIE0PortFIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFExtFatal_ACTION_CONTROL 0xe8808e +#define regPCIE0PortFExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFExtNonFatal_ACTION_CONTROL 0xe8808f +#define regPCIE0PortFExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFExtCorr_ACTION_CONTROL 0xe88090 +#define regPCIE0PortFExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFParityErr_ACTION_CONTROL 0xe88091 +#define regPCIE0PortFParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGSerr_ACTION_CONTROL 0xe88092 +#define regPCIE0PortGSerr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGIntFatal_ACTION_CONTROL 0xe88093 +#define regPCIE0PortGIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGIntNonFatal_ACTION_CONTROL 0xe88094 +#define regPCIE0PortGIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGIntCorr_ACTION_CONTROL 0xe88095 +#define regPCIE0PortGIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGExtFatal_ACTION_CONTROL 0xe88096 +#define regPCIE0PortGExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGExtNonFatal_ACTION_CONTROL 0xe88097 +#define regPCIE0PortGExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGExtCorr_ACTION_CONTROL 0xe88098 +#define regPCIE0PortGExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGParityErr_ACTION_CONTROL 0xe88099 +#define regPCIE0PortGParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortASerr_ACTION_CONTROL 0xe880ca +#define regNBIF1PortASerr_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortAIntFatal_ACTION_CONTROL 0xe880cb +#define regNBIF1PortAIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortAIntNonFatal_ACTION_CONTROL 0xe880cc +#define regNBIF1PortAIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortAIntCorr_ACTION_CONTROL 0xe880cd +#define regNBIF1PortAIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortAExtFatal_ACTION_CONTROL 0xe880ce +#define regNBIF1PortAExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortAExtNonFatal_ACTION_CONTROL 0xe880cf +#define regNBIF1PortAExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortAExtCorr_ACTION_CONTROL 0xe880d0 +#define regNBIF1PortAExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortAParityErr_ACTION_CONTROL 0xe880d1 +#define regNBIF1PortAParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regSYNCFLOOD_STATUS 0xe88200 +#define regSYNCFLOOD_STATUS_BASE_IDX 8 +#define regNMI_STATUS 0xe88201 +#define regNMI_STATUS_BASE_IDX 8 +#define regPOISON_ACTION_CONTROL 0xe88205 +#define regPOISON_ACTION_CONTROL_BASE_IDX 8 +#define regINTERNAL_POISON_STATUS 0xe88206 +#define regINTERNAL_POISON_STATUS_BASE_IDX 8 +#define regINTERNAL_POISON_MASK 0xe88207 +#define regINTERNAL_POISON_MASK_BASE_IDX 8 +#define regEGRESS_POISON_STATUS_LO 0xe88208 +#define regEGRESS_POISON_STATUS_LO_BASE_IDX 8 +#define regEGRESS_POISON_STATUS_HI 0xe88209 +#define regEGRESS_POISON_STATUS_HI_BASE_IDX 8 +#define regEGRESS_POISON_MASK_LO 0xe8820a +#define regEGRESS_POISON_MASK_LO_BASE_IDX 8 +#define regEGRESS_POISON_MASK_HI 0xe8820b +#define regEGRESS_POISON_MASK_HI_BASE_IDX 8 +#define regEGRESS_POISON_SEVERITY_DOWN 0xe8820c +#define regEGRESS_POISON_SEVERITY_DOWN_BASE_IDX 8 +#define regEGRESS_POISON_SEVERITY_UPPER 0xe8820d +#define regEGRESS_POISON_SEVERITY_UPPER_BASE_IDX 8 +#define regAPML_STATUS 0xe88370 +#define regAPML_STATUS_BASE_IDX 8 +#define regAPML_CONTROL 0xe88371 +#define regAPML_CONTROL_BASE_IDX 8 +#define regAPML_TRIGGER 0xe88372 +#define regAPML_TRIGGER_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg0_devind_cfgdecp +// base address: 0x13b31000 +#define regNB_PCIE0DEVINDCFG0_STEERING_CNTL 0xe8c403 +#define regNB_PCIE0DEVINDCFG0_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg1_devind_cfgdecp +// base address: 0x13b31400 +#define regNB_PCIE0DEVINDCFG1_STEERING_CNTL 0xe8c503 +#define regNB_PCIE0DEVINDCFG1_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg2_devind_cfgdecp +// base address: 0x13b31800 +#define regNB_PCIE0DEVINDCFG2_STEERING_CNTL 0xe8c603 +#define regNB_PCIE0DEVINDCFG2_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg3_devind_cfgdecp +// base address: 0x13b31c00 +#define regNB_PCIE0DEVINDCFG3_STEERING_CNTL 0xe8c703 +#define regNB_PCIE0DEVINDCFG3_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg4_devind_cfgdecp +// base address: 0x13b32000 +#define regNB_PCIE0DEVINDCFG4_STEERING_CNTL 0xe8c803 +#define regNB_PCIE0DEVINDCFG4_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg5_devind_cfgdecp +// base address: 0x13b32400 +#define regNB_PCIE0DEVINDCFG5_STEERING_CNTL 0xe8c903 +#define regNB_PCIE0DEVINDCFG5_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg6_devind_cfgdecp +// base address: 0x13b32800 +#define regNB_PCIE0DEVINDCFG6_STEERING_CNTL 0xe8ca03 +#define regNB_PCIE0DEVINDCFG6_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_NBIF1devindcfg0_devind_cfgdecp +// base address: 0x13b38000 +#define regNB_NBIF1DEVINDCFG0_STEERING_CNTL 0xe8e003 +#define regNB_NBIF1DEVINDCFG0_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_intSBdevindcfg0_devind_cfgdecp +// base address: 0x13b3c000 +#define regNB_INTSBDEVINDCFG0_STEERING_CNTL 0xe8f003 +#define regNB_INTSBDEVINDCFG0_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg0_pciercbdgind_cfgdec +// base address: 0x13b7d600 +#define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION 0xe9f5b7 +#define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX 0xe9f5b8 +#define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA 0xe9f5b9 +#define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg1_pciercbdgind_cfgdec +// base address: 0x13b7d700 +#define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION 0xe9f5f7 +#define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX 0xe9f5f8 +#define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA 0xe9f5f9 +#define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg2_pciercbdgind_cfgdec +// base address: 0x13b7d800 +#define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION 0xe9f637 +#define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX 0xe9f638 +#define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA 0xe9f639 +#define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg3_pciercbdgind_cfgdec +// base address: 0x13b7d900 +#define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION 0xe9f677 +#define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX 0xe9f678 +#define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA 0xe9f679 +#define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg4_pciercbdgind_cfgdec +// base address: 0x13b7da00 +#define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION 0xe9f6b7 +#define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX 0xe9f6b8 +#define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA 0xe9f6b9 +#define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg5_pciercbdgind_cfgdec +// base address: 0x13b7db00 +#define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION 0xe9f6f7 +#define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX 0xe9f6f8 +#define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA 0xe9f6f9 +#define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg6_pciercbdgind_cfgdec +// base address: 0x13b7dc00 +#define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION 0xe9f737 +#define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX 0xe9f738 +#define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA 0xe9f739 +#define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_NBIF1rcbdg_indcfg0_pciercbdgind_cfgdec +// base address: 0x13b7f200 +#define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION 0xe9fcb7 +#define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX 0xe9fcb8 +#define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA 0xe9fcb9 +#define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_iommu_l2a_l2acfg +// base address: 0x15700000 +#define regL2_PERF_CNTL_0 0x1580000 +#define regL2_PERF_CNTL_0_BASE_IDX 8 +#define regL2_PERF_COUNT_0 0x1580001 +#define regL2_PERF_COUNT_0_BASE_IDX 8 +#define regL2_PERF_COUNT_1 0x1580002 +#define regL2_PERF_COUNT_1_BASE_IDX 8 +#define regL2_PERF_CNTL_1 0x1580003 +#define regL2_PERF_CNTL_1_BASE_IDX 8 +#define regL2_PERF_COUNT_2 0x1580004 +#define regL2_PERF_COUNT_2_BASE_IDX 8 +#define regL2_PERF_COUNT_3 0x1580005 +#define regL2_PERF_COUNT_3_BASE_IDX 8 +#define regL2_STATUS_0 0x1580008 +#define regL2_STATUS_0_BASE_IDX 8 +#define regL2_CONTROL_0 0x158000c +#define regL2_CONTROL_0_BASE_IDX 8 +#define regL2_CONTROL_1 0x158000d +#define regL2_CONTROL_1_BASE_IDX 8 +#define regL2_DTC_CONTROL 0x1580010 +#define regL2_DTC_CONTROL_BASE_IDX 8 +#define regL2_DTC_HASH_CONTROL 0x1580011 +#define regL2_DTC_HASH_CONTROL_BASE_IDX 8 +#define regL2_DTC_WAY_CONTROL 0x1580012 +#define regL2_DTC_WAY_CONTROL_BASE_IDX 8 +#define regL2_ITC_CONTROL 0x1580014 +#define regL2_ITC_CONTROL_BASE_IDX 8 +#define regL2_ITC_HASH_CONTROL 0x1580015 +#define regL2_ITC_HASH_CONTROL_BASE_IDX 8 +#define regL2_ITC_WAY_CONTROL 0x1580016 +#define regL2_ITC_WAY_CONTROL_BASE_IDX 8 +#define regL2_PTC_A_CONTROL 0x1580018 +#define regL2_PTC_A_CONTROL_BASE_IDX 8 +#define regL2_PTC_A_HASH_CONTROL 0x1580019 +#define regL2_PTC_A_HASH_CONTROL_BASE_IDX 8 +#define regL2_PTC_A_WAY_CONTROL 0x158001a +#define regL2_PTC_A_WAY_CONTROL_BASE_IDX 8 +#define regL2A_UPDATE_FILTER_CNTL 0x1580022 +#define regL2A_UPDATE_FILTER_CNTL_BASE_IDX 8 +#define regL2_ERR_RULE_CONTROL_3 0x1580030 +#define regL2_ERR_RULE_CONTROL_3_BASE_IDX 8 +#define regL2_ERR_RULE_CONTROL_4 0x1580031 +#define regL2_ERR_RULE_CONTROL_4_BASE_IDX 8 +#define regL2_ERR_RULE_CONTROL_5 0x1580032 +#define regL2_ERR_RULE_CONTROL_5_BASE_IDX 8 +#define regL2_L2A_CK_GATE_CONTROL 0x1580033 +#define regL2_L2A_CK_GATE_CONTROL_BASE_IDX 8 +#define regL2_L2A_PGSIZE_CONTROL 0x1580034 +#define regL2_L2A_PGSIZE_CONTROL_BASE_IDX 8 +#define regL2_PWRGATE_CNTRL_REG_0 0x158003e +#define regL2_PWRGATE_CNTRL_REG_0_BASE_IDX 8 +#define regL2_PWRGATE_CNTRL_REG_3 0x1580041 +#define regL2_PWRGATE_CNTRL_REG_3_BASE_IDX 8 +#define regL2_ECO_CNTRL_0 0x1580042 +#define regL2_ECO_CNTRL_0_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_iommu_l2indx_l2indxcfg +// base address: 0x13f01000 +#define regL2_STATUS_1 0xf80448 +#define regL2_STATUS_1_BASE_IDX 8 +#define regL2_SB_LOCATION 0xf8044b +#define regL2_SB_LOCATION_BASE_IDX 8 +#define regL2_CONTROL_5 0xf8044c +#define regL2_CONTROL_5_BASE_IDX 8 +#define regL2_CONTROL_6 0xf8044f +#define regL2_CONTROL_6_BASE_IDX 8 +#define regL2_PDC_CONTROL 0xf80450 +#define regL2_PDC_CONTROL_BASE_IDX 8 +#define regL2_PDC_HASH_CONTROL 0xf80451 +#define regL2_PDC_HASH_CONTROL_BASE_IDX 8 +#define regL2_PDC_WAY_CONTROL 0xf80452 +#define regL2_PDC_WAY_CONTROL_BASE_IDX 8 +#define regL2B_UPDATE_FILTER_CNTL 0xf80453 +#define regL2B_UPDATE_FILTER_CNTL_BASE_IDX 8 +#define regL2_TW_CONTROL 0xf80454 +#define regL2_TW_CONTROL_BASE_IDX 8 +#define regL2_CP_CONTROL 0xf80456 +#define regL2_CP_CONTROL_BASE_IDX 8 +#define regL2_CP_CONTROL_1 0xf80457 +#define regL2_CP_CONTROL_1_BASE_IDX 8 +#define regL2_TW_CONTROL_1 0xf8045a +#define regL2_TW_CONTROL_1_BASE_IDX 8 +#define regL2_TW_CONTROL_2 0xf80461 +#define regL2_TW_CONTROL_2_BASE_IDX 8 +#define regL2_TW_CONTROL_3 0xf80462 +#define regL2_TW_CONTROL_3_BASE_IDX 8 +#define regL2_CREDIT_CONTROL_0 0xf80470 +#define regL2_CREDIT_CONTROL_0_BASE_IDX 8 +#define regL2_CREDIT_CONTROL_1 0xf80471 +#define regL2_CREDIT_CONTROL_1_BASE_IDX 8 +#define regL2_ERR_RULE_CONTROL_0 0xf80480 +#define regL2_ERR_RULE_CONTROL_0_BASE_IDX 8 +#define regL2_ERR_RULE_CONTROL_1 0xf80481 +#define regL2_ERR_RULE_CONTROL_1_BASE_IDX 8 +#define regL2_ERR_RULE_CONTROL_2 0xf80482 +#define regL2_ERR_RULE_CONTROL_2_BASE_IDX 8 +#define regL2_L2B_CK_GATE_CONTROL 0xf80490 +#define regL2_L2B_CK_GATE_CONTROL_BASE_IDX 8 +#define regPPR_CONTROL 0xf80492 +#define regPPR_CONTROL_BASE_IDX 8 +#define regL2_L2B_PGSIZE_CONTROL 0xf80494 +#define regL2_L2B_PGSIZE_CONTROL_BASE_IDX 8 +#define regL2_PERF_CNTL_2 0xf80499 +#define regL2_PERF_CNTL_2_BASE_IDX 8 +#define regL2_PERF_COUNT_4 0xf8049a +#define regL2_PERF_COUNT_4_BASE_IDX 8 +#define regL2_PERF_COUNT_5 0xf8049b +#define regL2_PERF_COUNT_5_BASE_IDX 8 +#define regL2_PERF_CNTL_3 0xf8049c +#define regL2_PERF_CNTL_3_BASE_IDX 8 +#define regL2_PERF_COUNT_6 0xf8049d +#define regL2_PERF_COUNT_6_BASE_IDX 8 +#define regL2_PERF_COUNT_7 0xf8049e +#define regL2_PERF_COUNT_7_BASE_IDX 8 +#define regL2B_SDP_PARITY_ERROR_EN 0xf804a2 +#define regL2B_SDP_PARITY_ERROR_EN_BASE_IDX 8 +#define regL2_ECO_CNTRL_1 0xf804a3 +#define regL2_ECO_CNTRL_1_BASE_IDX 8 +#define regL2_CP_CONTROL_2 0xf804bf +#define regL2_CP_CONTROL_2_BASE_IDX 8 +#define regL2_CP_CONTROL_3 0xf804c0 +#define regL2_CP_CONTROL_3_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_ioapiccfg_ioapic_cfgdec +// base address: 0x14300000 +#define regFEATURES_ENABLE 0x1080000 +#define regFEATURES_ENABLE_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_RC_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_RC_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_RC_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_RC_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_RC_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_RC_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_RC_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_RC_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_RC_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_RC_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_RC_HEADER 0x000e +#define cfgBIF_CFG_DEV0_RC_BIST 0x000f +#define cfgBIF_CFG_DEV0_RC_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_RC_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY 0x0018 +#define cfgBIF_CFG_DEV0_RC_IO_BASE_LIMIT 0x001c +#define cfgBIF_CFG_DEV0_RC_SECONDARY_STATUS 0x001e +#define cfgBIF_CFG_DEV0_RC_MEM_BASE_LIMIT 0x0020 +#define cfgBIF_CFG_DEV0_RC_PREF_BASE_LIMIT 0x0024 +#define cfgBIF_CFG_DEV0_RC_PREF_BASE_UPPER 0x0028 +#define cfgBIF_CFG_DEV0_RC_PREF_LIMIT_UPPER 0x002c +#define cfgBIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI 0x0030 +#define cfgBIF_CFG_DEV0_RC_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_RC_ROM_BASE_ADDR 0x0038 +#define cfgBIF_CFG_DEV0_RC_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_RC_INTERRUPT_PIN 0x003d +#define cfgIRQ_BRIDGE_CNTL 0x003e +#define cfgBIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL 0x0040 +#define cfgBIF_CFG_DEV0_RC_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_RC_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_RC_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_RC_PCIE_CAP_LIST 0x0058 +#define cfgBIF_CFG_DEV0_RC_PCIE_CAP 0x005a +#define cfgBIF_CFG_DEV0_RC_DEVICE_CAP 0x005c +#define cfgBIF_CFG_DEV0_RC_DEVICE_CNTL 0x0060 +#define cfgBIF_CFG_DEV0_RC_DEVICE_STATUS 0x0062 +#define cfgBIF_CFG_DEV0_RC_LINK_CAP 0x0064 +#define cfgBIF_CFG_DEV0_RC_LINK_CNTL 0x0068 +#define cfgBIF_CFG_DEV0_RC_LINK_STATUS 0x006a +#define cfgBIF_CFG_DEV0_RC_SLOT_CAP 0x006c +#define cfgBIF_CFG_DEV0_RC_SLOT_CNTL 0x0070 +#define cfgBIF_CFG_DEV0_RC_SLOT_STATUS 0x0072 +#define cfgBIF_CFG_DEV0_RC_ROOT_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_RC_ROOT_CAP 0x0076 +#define cfgBIF_CFG_DEV0_RC_ROOT_STATUS 0x0078 +#define cfgBIF_CFG_DEV0_RC_DEVICE_CAP2 0x007c +#define cfgBIF_CFG_DEV0_RC_DEVICE_CNTL2 0x0080 +#define cfgBIF_CFG_DEV0_RC_DEVICE_STATUS2 0x0082 +#define cfgBIF_CFG_DEV0_RC_LINK_CAP2 0x0084 +#define cfgBIF_CFG_DEV0_RC_LINK_CNTL2 0x0088 +#define cfgBIF_CFG_DEV0_RC_LINK_STATUS2 0x008a +#define cfgBIF_CFG_DEV0_RC_SLOT_CAP2 0x008c +#define cfgBIF_CFG_DEV0_RC_SLOT_CNTL2 0x0090 +#define cfgBIF_CFG_DEV0_RC_SLOT_STATUS2 0x0092 +#define cfgBIF_CFG_DEV0_RC_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_RC_SSID_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_RC_SSID_CAP 0x00c4 +#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD 0x017c +#define cfgBIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS 0x0180 +#define cfgBIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID 0x0184 +#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIF_CFG_DEV0_RC_PCIE_LINK_CNTL3 0x0274 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP 0x0404 +#define cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS 0x0408 +#define cfgBIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 +#define cfgBIF_CFG_DEV0_RC_LINK_CAP_16GT 0x0414 +#define cfgBIF_CFG_DEV0_RC_LINK_CNTL_16GT 0x0418 +#define cfgBIF_CFG_DEV0_RC_LINK_STATUS_16GT 0x041c +#define cfgBIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 +#define cfgBIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 +#define cfgBIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 +#define cfgBIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 +#define cfgBIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 +#define cfgBIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 +#define cfgBIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 +#define cfgBIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 +#define cfgBIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 +#define cfgBIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 +#define cfgBIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 +#define cfgBIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 +#define cfgBIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 +#define cfgBIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT 0x043a +#define cfgBIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT 0x043b +#define cfgBIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT 0x043c +#define cfgBIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT 0x043d +#define cfgBIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT 0x043e +#define cfgBIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT 0x043f +#define cfgBIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST 0x0450 +#define cfgBIF_CFG_DEV0_RC_MARGINING_PORT_CAP 0x0454 +#define cfgBIF_CFG_DEV0_RC_MARGINING_PORT_STATUS 0x0456 +#define cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL 0x0458 +#define cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS 0x045a +#define cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL 0x045c +#define cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS 0x045e +#define cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL 0x0460 +#define cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS 0x0462 +#define cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL 0x0464 +#define cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS 0x0466 +#define cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL 0x0468 +#define cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS 0x046a +#define cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL 0x046c +#define cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS 0x046e +#define cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL 0x0470 +#define cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS 0x0472 +#define cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL 0x0474 +#define cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS 0x0476 +#define cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL 0x0478 +#define cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS 0x047a +#define cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL 0x047c +#define cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS 0x047e +#define cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL 0x0480 +#define cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS 0x0482 +#define cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL 0x0484 +#define cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS 0x0486 +#define cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL 0x0488 +#define cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS 0x048a +#define cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL 0x048c +#define cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS 0x048e +#define cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL 0x0490 +#define cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS 0x0492 +#define cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL 0x0494 +#define cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS 0x0496 +#define cfgBIF_CFG_DEV0_RC_LINK_CAP_32GT 0x0504 +#define cfgBIF_CFG_DEV0_RC_LINK_CNTL_32GT 0x0508 +#define cfgBIF_CFG_DEV0_RC_LINK_STATUS_32GT 0x050c + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF2_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF2_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF2_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF2_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF2_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF2_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF2_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF3_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF3_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF3_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF3_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF3_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF3_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF3_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF4_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF4_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF4_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF4_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF4_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF4_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF4_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF5_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF5_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF5_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF5_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF5_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF5_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF5_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF6_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF6_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF6_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF6_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF6_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF6_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF6_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF7_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF7_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF7_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF7_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF7_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF7_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF7_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF0_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF1_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF2_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF3_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF4_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF5_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF6_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF7_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX 4 + + +#endif diff --git a/extra/amdpci/headers/nbio_7_9_0_sh_mask.h b/extra/amdpci/headers/nbio_7_9_0_sh_mask.h new file mode 100644 index 0000000000..a22481e7bc --- /dev/null +++ b/extra/amdpci/headers/nbio_7_9_0_sh_mask.h @@ -0,0 +1,38900 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _nbio_7_9_0_SH_MASK_HEADER +#define _nbio_7_9_0_SH_MASK_HEADER + + +// addressBlock: aid_nbio_nbif0_bif_bx_SYSDEC +//BIF_BX0_PCIE_INDEX +#define BIF_BX0_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 +#define BIF_BX0_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL +//BIF_BX0_PCIE_DATA +#define BIF_BX0_PCIE_DATA__PCIE_DATA__SHIFT 0x0 +#define BIF_BX0_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL +//BIF_BX0_PCIE_INDEX2 +#define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 +#define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL +//BIF_BX0_PCIE_DATA2 +#define BIF_BX0_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 +#define BIF_BX0_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL +//BIF_BX0_PCIE_INDEX_HI +#define BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT 0x0 +#define BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK 0x000000FFL +//BIF_BX0_PCIE_INDEX2_HI +#define BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT 0x0 +#define BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK 0x000000FFL +//BIF_BX0_SBIOS_SCRATCH_0 +#define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_1 +#define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_2 +#define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_3 +#define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_0 +#define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_1 +#define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_2 +#define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_3 +#define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_4 +#define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_5 +#define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_6 +#define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_7 +#define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_8 +#define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_9 +#define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_10 +#define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_11 +#define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_12 +#define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_13 +#define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_14 +#define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_15 +#define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX0_BIF_RLC_INTR_CNTL +//BIF_BX0_BIF_VCE_INTR_CNTL +//BIF_BX0_BIF_UVD_INTR_CNTL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR1 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR2 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR3 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR4 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR5 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR6 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR7 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_CNTL +#define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL +//BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL +#define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL +#define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL +#define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_0 +#define BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_1 +#define BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_2 +#define BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_3 +#define BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_4 +#define BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_5 +#define BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_6 +#define BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_7 +#define BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_8 +#define BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_9 +#define BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_10 +#define BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_11 +#define BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_12 +#define BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_13 +#define BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_14 +#define BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_15 +#define BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_0 +#define BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_1 +#define BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_2 +#define BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_3 +#define BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_4 +#define BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_5 +#define BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_6 +#define BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_7 +#define BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_8 +#define BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_9 +#define BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_10 +#define BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_11 +#define BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_12 +#define BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_13 +#define BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_14 +#define BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_15 +#define BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_4 +#define BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_5 +#define BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_6 +#define BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_7 +#define BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_8 +#define BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_9 +#define BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_10 +#define BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_11 +#define BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_12 +#define BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_13 +#define BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_14 +#define BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_15 +#define BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +//RCC_DWN_DEV0_0_DN_PCIE_RESERVED +#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_0_DN_PCIE_SCRATCH +#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_0_DN_PCIE_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +//RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 +#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L +//RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +//RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L +//RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L + + +// addressBlock: aid_nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +//RCC_DWNP_DEV0_0_PCIE_ERR_CNTL +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L +//RCC_DWNP_DEV0_0_PCIE_RX_CNTL +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +//RCC_DWNP_DEV0_0_PCIE_LC_CNTL2 +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC +#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L +//RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP +#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_ep_dev0_BIFDEC1 +//RCC_EP_DEV0_0_EP_PCIE_SCRATCH +#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_0_EP_PCIE_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_EP_DEV0_0_EP_PCIE_INT_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +//RCC_EP_DEV0_0_EP_PCIE_INT_STATUS +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L +//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +//RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +//RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +//RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC +#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 +#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L +//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL +#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL +//RCC_EP_DEV0_0_EP_PCIEP_RESERVED +#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_0_EP_PCIE_TX_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L +//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L + + +// addressBlock: aid_nbio_nbif0_bif_bx_pf_SYSPFVFDEC +//BIF_BX_PF0_MM_INDEX +#define BIF_BX_PF0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_PF0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_PF0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_PF0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_PF0_MM_DATA +#define BIF_BX_PF0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MM_INDEX_HI +#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL +//BIF_BX_PF0_RSMU_INDEX +#define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX__SHIFT 0x0 +#define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX_MASK 0xFFFFFFFFL +//BIF_BX_PF0_RSMU_DATA +#define BIF_BX_PF0_RSMU_DATA__RSMU_DATA__SHIFT 0x0 +#define BIF_BX_PF0_RSMU_DATA__RSMU_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_RSMU_INDEX_HI +#define BIF_BX_PF0_RSMU_INDEX_HI__RSMU_INDEX_HI__SHIFT 0x0 +#define BIF_BX_PF0_RSMU_INDEX_HI__RSMU_INDEX_HI_MASK 0x000000FFL + + +// addressBlock: aid_nbio_nbif0_bif_bx_BIFDEC1 +//BIF_BX0_CC_BIF_BX_STRAP0 +#define BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT 0x19 +#define BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK 0xFE000000L +//BIF_BX0_CC_BIF_BX_PINSTRAP0 +//BIF_BX0_BIF_MM_INDACCESS_CNTL +#define BIF_BX0_BIF_MM_INDACCESS_CNTL__WRITE_DIS__SHIFT 0x0 +#define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 +#define BIF_BX0_BIF_MM_INDACCESS_CNTL__WRITE_DIS_MASK 0x00000001L +#define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L +//BIF_BX0_BUS_CNTL +#define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 +#define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 +#define BIF_BX0_BUS_CNTL__SET_AZ_TC__SHIFT 0xa +#define BIF_BX0_BUS_CNTL__SET_MC_TC__SHIFT 0xd +#define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 +#define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 +#define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 +#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT 0x18 +#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19 +#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a +#define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT 0x1b +#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT 0x1c +#define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d +#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e +#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f +#define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L +#define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L +#define BIF_BX0_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L +#define BIF_BX0_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L +#define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L +#define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L +#define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L +#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK 0x01000000L +#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L +#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L +#define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK 0x08000000L +#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK 0x10000000L +#define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L +#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L +#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L +//BIF_BX0_BIF_SCRATCH0 +#define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 +#define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL +//BIF_BX0_BIF_SCRATCH1 +#define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 +#define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL +//BIF_BX0_BX_RESET_EN +#define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 +#define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L +//BIF_BX0_MM_CFGREGS_CNTL +#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 +#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 +#define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f +#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L +#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L +#define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L +//BIF_BX0_BX_RESET_CNTL +#define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 +#define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L +//BIF_BX0_INTERRUPT_CNTL +#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 +#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 +#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 +#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 +#define BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 +#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf +#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10 +#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11 +#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12 +#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L +#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L +#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L +#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L +#define BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L +#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L +#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L +#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L +#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L +//BIF_BX0_INTERRUPT_CNTL2 +#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 +#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL +//BIF_BX0_CLKREQB_PAD_CNTL +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L +//BIF_BX0_BIF_FEATURES_CONTROL_MISC +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT 0xb +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS__SHIFT 0xe +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT 0x10 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x19 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK 0x00000800L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS_MASK 0x00004000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK 0x01FF0000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x02000000L +//BIF_BX0_HDP_ATOMIC_CONTROL_MISC +#define BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT 0x0 +#define BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK 0x000000FFL +//BIF_BX0_BIF_DOORBELL_CNTL +#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 +#define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 +#define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 +#define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 +#define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b +#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L +#define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L +#define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L +#define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L +#define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L +//BIF_BX0_BIF_DOORBELL_INT_CNTL +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x17 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x1f +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x00800000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x80000000L +//BIF_BX0_BIF_FB_EN +#define BIF_BX0_BIF_FB_EN__FB_READ_EN__SHIFT 0x0 +#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 +#define BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L +#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L +//BIF_BX0_BIF_INTR_CNTL +#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0 +#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L +//BIF_BX0_BIF_MST_TRANS_PENDING_VF +#define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL +//BIF_BX0_BIF_SLV_TRANS_PENDING_VF +#define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x7FFFFFFFL +//BIF_BX0_BACO_CNTL +#define BIF_BX0_BACO_CNTL__BACO_EN__SHIFT 0x0 +#define BIF_BX0_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 +#define BIF_BX0_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 +#define BIF_BX0_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 +#define BIF_BX0_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 +#define BIF_BX0_BACO_CNTL__BACO_MODE__SHIFT 0x8 +#define BIF_BX0_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 +#define BIF_BX0_BACO_CNTL__PWRGOOD_VDDSOC__SHIFT 0x10 +#define BIF_BX0_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f +#define BIF_BX0_BACO_CNTL__BACO_EN_MASK 0x00000001L +#define BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L +#define BIF_BX0_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L +#define BIF_BX0_BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L +#define BIF_BX0_BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L +#define BIF_BX0_BACO_CNTL__BACO_MODE_MASK 0x00000100L +#define BIF_BX0_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L +#define BIF_BX0_BACO_CNTL__PWRGOOD_VDDSOC_MASK 0x00010000L +#define BIF_BX0_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L +//BIF_BX0_BIF_BACO_EXIT_TIME0 +#define BIF_BX0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX0_BIF_BACO_EXIT_TIMER1 +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18 +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L +//BIF_BX0_BIF_BACO_EXIT_TIMER2 +#define BIF_BX0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 +#define BIF_BX0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL +//BIF_BX0_BIF_BACO_EXIT_TIMER3 +#define BIF_BX0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX0_BIF_BACO_EXIT_TIMER4 +#define BIF_BX0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX0_MEM_TYPE_CNTL +#define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 +#define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L +//BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT 0x1 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT 0x8 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK 0x00000001L +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK 0x00000002L +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK 0x00000100L +//BIF_BX0_NBIF_GFX_ADDR_LUT_0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_1 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_2 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_3 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_4 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_5 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_6 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_7 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_8 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_9 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_10 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_11 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_12 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_13 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_14 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_15 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL +#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL +#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX0_BIF_RB_CNTL +#define BIF_BX0_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define BIF_BX0_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 +#define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 +#define BIF_BX0_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL__SHIFT 0x19 +#define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT 0x1a +#define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT 0x1d +#define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT 0x1e +#define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define BIF_BX0_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define BIF_BX0_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L +#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L +#define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L +#define BIF_BX0_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL_MASK 0x02000000L +#define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK 0x1C000000L +#define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK 0x20000000L +#define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK 0x40000000L +#define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L +//BIF_BX0_BIF_RB_BASE +#define BIF_BX0_BIF_RB_BASE__ADDR__SHIFT 0x0 +#define BIF_BX0_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//BIF_BX0_BIF_RB_RPTR +#define BIF_BX0_BIF_RB_RPTR__OFFSET__SHIFT 0x2 +#define BIF_BX0_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX0_BIF_RB_WPTR +#define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 +#define BIF_BX0_BIF_RB_WPTR__OFFSET__SHIFT 0x2 +#define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L +#define BIF_BX0_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX0_BIF_RB_WPTR_ADDR_HI +#define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL +//BIF_BX0_BIF_RB_WPTR_ADDR_LO +#define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//BIF_BX0_MAILBOX_INDEX +#define BIF_BX0_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 +#define BIF_BX0_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL +//BIF_BX0_BIF_MP1_INTR_CTRL +#define BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT 0x0 +#define BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK 0x00000001L +//BIF_BX0_BIF_PERSTB_PAD_CNTL +#define BIF_BX0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL +//BIF_BX0_BIF_PX_EN_PAD_CNTL +#define BIF_BX0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x00000FFFL +//BIF_BX0_BIF_REFPADKIN_PAD_CNTL +#define BIF_BX0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL +//BIF_BX0_BIF_CLKREQB_PAD_CNTL +#define BIF_BX0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x7FFFFFFFL +//BIF_BX0_BIF_PWRBRK_PAD_CNTL +#define BIF_BX0_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT 0x0 +#define BIF_BX0_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK 0x000000FFL + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_BIFDEC1 +//RCC_DEV0_0_RCC_ERR_INT_CNTL +#define RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0 +#define RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L +//RCC_DEV0_0_RCC_BACO_CNTL_MISC +#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 +#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L +#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L +//RCC_DEV0_0_RCC_RESET_EN +#define RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf +#define RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L +//RCC_DEV0_0_RCC_VDM_SUPPORT +#define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L +#define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L +#define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L +#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L +#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L +//RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L +//RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L +//RCC_DEV0_0_RCC_GPUIOV_REGION +#define RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 +#define RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 +#define RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION_MASK 0x0000000FL +#define RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION_MASK 0x000000F0L +//RCC_DEV0_0_RCC_GPU_HOSTVM_EN +#define RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT 0x0 +#define RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK 0x00000001L +//RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL +#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT 0x1 +#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK 0x00000001L +#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK 0x00000002L +//RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET +#define RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE +#define RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK 0xFFFFL +//RCC_DEV0_0_RCC_PEER_REG_RANGE0 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL +#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L +//RCC_DEV0_0_RCC_PEER_REG_RANGE1 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL +#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L +//RCC_DEV0_0_RCC_BUS_CNTL +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 +#define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc +#define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 +#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 +#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 +#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c +#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L +#define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L +#define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L +#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L +#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L +#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L +#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L +//RCC_DEV0_0_RCC_CONFIG_CNTL +#define RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 +#define RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 +#define RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L +#define RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L +#define RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L +//RCC_DEV0_0_RCC_CONFIG_F0_BASE +#define RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL +//RCC_DEV0_0_RCC_CONFIG_APER_SIZE +#define RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE +#define RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x07FFFFFFL +//RCC_DEV0_0_RCC_XDMA_LO +#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 +#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL +#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_XDMA_HI +#define RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 +#define RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL +//RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L +//RCC_DEV0_0_RCC_BUSNUM_CNTL1 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL +//RCC_DEV0_0_RCC_BUSNUM_LIST0 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1__SHIFT 0x8 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2__SHIFT 0x10 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3__SHIFT 0x18 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L +//RCC_DEV0_0_RCC_BUSNUM_LIST1 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5__SHIFT 0x8 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6__SHIFT 0x10 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7__SHIFT 0x18 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L +//RCC_DEV0_0_RCC_BUSNUM_CNTL2 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L +//RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM +#define RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L +//RCC_DEV0_0_RCC_HOST_BUSNUM +#define RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0 +#define RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL +//RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000FF00L +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00FF0000L +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xFF000000L +//RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000FF00L +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00FF0000L +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xFF000000L +//RCC_DEV0_0_RCC_DEV0_LINK_CNTL +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT 0x10 +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT 0x11 +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK 0x00010000L +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK 0x00020000L +//RCC_DEV0_0_RCC_CMN_LINK_CNTL +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L +//RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L +//RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL +#define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL +//RCC_DEV0_0_RCC_MH_ARB_CNTL +#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 +#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L +#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_BIFDEC2 +//RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_PBA +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L + + +// addressBlock: aid_nbio_nbif0_rcc_strap_BIFDEC1 +//RCC_STRAP0_RCC_BIF_STRAP0 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT 0x1 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x6 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT 0x1c +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK 0x00000001L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK 0x00000002L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000038L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00000040L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK 0x10000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L +//RCC_STRAP0_RCC_BIF_STRAP1 +#define RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1 +#define RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x2 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT 0x18 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT 0x19 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT 0x1e +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT 0x1f +#define RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L +#define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L +#define RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK 0x01000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK 0x02000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_MASK 0x40000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK 0x80000000L +//RCC_STRAP0_RCC_BIF_STRAP2 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN__SHIFT 0x7 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa +#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN_MASK 0x00000080L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L +#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L +//RCC_STRAP0_RCC_BIF_STRAP3 +#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_BIF_STRAP4 +#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_BIF_STRAP5 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT 0x15 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK 0x00200000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L +//RCC_STRAP0_RCC_BIF_STRAP6 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT 0x1 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT 0x2 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK 0x00000001L +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK 0x00000002L +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK 0x00000004L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT 0x5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK 0x00000020L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK 0x0007FFC0L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP11 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK 0x0FFF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK 0x40000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK 0x00FFFFFFL +//RCC_STRAP0_RCC_DEV0_PORT_STRAP13 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK 0x000FFE00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK 0xFFF00000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK 0x00000010L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x00E00000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x0F000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0xF0000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP1 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP13 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0xFF000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK 0x00FFF000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK 0x3E000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK 0x40000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK 0x00FFF000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP17 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT 0xd +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK 0x00001000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK 0x01FFE000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK 0x00000FFFL +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP2 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP26 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK 0x00000FFFL +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP3 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP4 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT 0xa +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK 0x00000400L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP5 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP8 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00780000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP9 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP2 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK 0x00800000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP20 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP21 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP22 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP23 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP24 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP25 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP3 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP4 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP5 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK 0x38000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP6 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP7 + + +// addressBlock: aid_nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +//BIF_BX_PF0_BIF_BME_STATUS +#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_PF0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF0_GPU_HDP_FLUSH_REQ +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF0_GPU_HDP_FLUSH_DONE +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF0_BIF_TRANS_PENDING +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_CONTROL +#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_PF0_MAILBOX_INT_CNTL +#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_PF0_BIF_VMHV_MAILBOX +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_PF0_PARTITION_COMPUTE_CAP +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_PF0_PARTITION_MEM_CAP +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_PF0_PARTITION_COMPUTE_STATUS +#define BIF_BX_PF0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_PF0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_PF0_PARTITION_MEM_STATUS +#define BIF_BX_PF0_PARTITION_MEM_STATUS__CHANGE_STATUE__SHIFT 0x0 +#define BIF_BX_PF0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_PF0_PARTITION_MEM_STATUS__CHANGE_STATUE_MASK 0x0000000FL +#define BIF_BX_PF0_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] +//RCC_DEV0_EPF0_RCC_ERR_LOG +#define RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: aid_nbio_nbif0_gdc_GDCDEC +//GDC0_A2S_CNTL_CL0 +#define GDC0_A2S_CNTL_CL0__NSNOOP_MAP__SHIFT 0x0 +#define GDC0_A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT 0x2 +#define GDC0_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT 0x4 +#define GDC0_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 +#define GDC0_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 +#define GDC0_A2S_CNTL_CL0__BLKLVL_MAP__SHIFT 0xa +#define GDC0_A2S_CNTL_CL0__DATERR_MAP__SHIFT 0xc +#define GDC0_A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT 0xe +#define GDC0_A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT 0x10 +#define GDC0_A2S_CNTL_CL0__RESP_WR_MAP__SHIFT 0x12 +#define GDC0_A2S_CNTL_CL0__RESP_RD_MAP__SHIFT 0x14 +#define GDC0_A2S_CNTL_CL0__RDRSP_ERRMAP__SHIFT 0x16 +#define GDC0_A2S_CNTL_CL0__RDRSP_SEL_MODE__SHIFT 0x18 +#define GDC0_A2S_CNTL_CL0__STATIC_VC_ENABLE__SHIFT 0x1b +#define GDC0_A2S_CNTL_CL0__STATIC_VC_VALUE__SHIFT 0x1c +#define GDC0_A2S_CNTL_CL0__NSNOOP_MAP_MASK 0x00000003L +#define GDC0_A2S_CNTL_CL0__REQPASSPW_VC0_MAP_MASK 0x0000000CL +#define GDC0_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP_MASK 0x00000030L +#define GDC0_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP_MASK 0x000000C0L +#define GDC0_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP_MASK 0x00000300L +#define GDC0_A2S_CNTL_CL0__BLKLVL_MAP_MASK 0x00000C00L +#define GDC0_A2S_CNTL_CL0__DATERR_MAP_MASK 0x00003000L +#define GDC0_A2S_CNTL_CL0__EXOKAY_WR_MAP_MASK 0x0000C000L +#define GDC0_A2S_CNTL_CL0__EXOKAY_RD_MAP_MASK 0x00030000L +#define GDC0_A2S_CNTL_CL0__RESP_WR_MAP_MASK 0x000C0000L +#define GDC0_A2S_CNTL_CL0__RESP_RD_MAP_MASK 0x00300000L +#define GDC0_A2S_CNTL_CL0__RDRSP_ERRMAP_MASK 0x00C00000L +#define GDC0_A2S_CNTL_CL0__RDRSP_SEL_MODE_MASK 0x07000000L +#define GDC0_A2S_CNTL_CL0__STATIC_VC_ENABLE_MASK 0x08000000L +#define GDC0_A2S_CNTL_CL0__STATIC_VC_VALUE_MASK 0x70000000L +//GDC0_A2S_CNTL_CL1 +#define GDC0_A2S_CNTL_CL1__NSNOOP_MAP__SHIFT 0x0 +#define GDC0_A2S_CNTL_CL1__REQPASSPW_VC0_MAP__SHIFT 0x2 +#define GDC0_A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__SHIFT 0x4 +#define GDC0_A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 +#define GDC0_A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 +#define GDC0_A2S_CNTL_CL1__BLKLVL_MAP__SHIFT 0xa +#define GDC0_A2S_CNTL_CL1__DATERR_MAP__SHIFT 0xc +#define GDC0_A2S_CNTL_CL1__EXOKAY_WR_MAP__SHIFT 0xe +#define GDC0_A2S_CNTL_CL1__EXOKAY_RD_MAP__SHIFT 0x10 +#define GDC0_A2S_CNTL_CL1__RESP_WR_MAP__SHIFT 0x12 +#define GDC0_A2S_CNTL_CL1__RESP_RD_MAP__SHIFT 0x14 +#define GDC0_A2S_CNTL_CL1__RDRSP_ERRMAP__SHIFT 0x16 +#define GDC0_A2S_CNTL_CL1__RDRSP_SEL_MODE__SHIFT 0x18 +#define GDC0_A2S_CNTL_CL1__STATIC_VC_ENABLE__SHIFT 0x1b +#define GDC0_A2S_CNTL_CL1__STATIC_VC_VALUE__SHIFT 0x1c +#define GDC0_A2S_CNTL_CL1__NSNOOP_MAP_MASK 0x00000003L +#define GDC0_A2S_CNTL_CL1__REQPASSPW_VC0_MAP_MASK 0x0000000CL +#define GDC0_A2S_CNTL_CL1__REQPASSPW_NVC0_MAP_MASK 0x00000030L +#define GDC0_A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP_MASK 0x000000C0L +#define GDC0_A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP_MASK 0x00000300L +#define GDC0_A2S_CNTL_CL1__BLKLVL_MAP_MASK 0x00000C00L +#define GDC0_A2S_CNTL_CL1__DATERR_MAP_MASK 0x00003000L +#define GDC0_A2S_CNTL_CL1__EXOKAY_WR_MAP_MASK 0x0000C000L +#define GDC0_A2S_CNTL_CL1__EXOKAY_RD_MAP_MASK 0x00030000L +#define GDC0_A2S_CNTL_CL1__RESP_WR_MAP_MASK 0x000C0000L +#define GDC0_A2S_CNTL_CL1__RESP_RD_MAP_MASK 0x00300000L +#define GDC0_A2S_CNTL_CL1__RDRSP_ERRMAP_MASK 0x00C00000L +#define GDC0_A2S_CNTL_CL1__RDRSP_SEL_MODE_MASK 0x07000000L +#define GDC0_A2S_CNTL_CL1__STATIC_VC_ENABLE_MASK 0x08000000L +#define GDC0_A2S_CNTL_CL1__STATIC_VC_VALUE_MASK 0x70000000L +//GDC0_A2S_CNTL3_CL0 +#define GDC0_A2S_CNTL3_CL0__FORCE_WR_PH__SHIFT 0x0 +#define GDC0_A2S_CNTL3_CL0__FORCE_WR_STEERING__SHIFT 0x2 +#define GDC0_A2S_CNTL3_CL0__WR_ST_TAG_MODE__SHIFT 0x3 +#define GDC0_A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY__SHIFT 0x4 +#define GDC0_A2S_CNTL3_CL0__FORCE_WR_PH_MASK 0x00000003L +#define GDC0_A2S_CNTL3_CL0__FORCE_WR_STEERING_MASK 0x00000004L +#define GDC0_A2S_CNTL3_CL0__WR_ST_TAG_MODE_MASK 0x00000008L +#define GDC0_A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY_MASK 0x000003F0L +//GDC0_A2S_CNTL3_CL1 +#define GDC0_A2S_CNTL3_CL1__FORCE_WR_PH__SHIFT 0x0 +#define GDC0_A2S_CNTL3_CL1__FORCE_WR_STEERING__SHIFT 0x2 +#define GDC0_A2S_CNTL3_CL1__WR_ST_TAG_MODE__SHIFT 0x3 +#define GDC0_A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY__SHIFT 0x4 +#define GDC0_A2S_CNTL3_CL1__FORCE_WR_PH_MASK 0x00000003L +#define GDC0_A2S_CNTL3_CL1__FORCE_WR_STEERING_MASK 0x00000004L +#define GDC0_A2S_CNTL3_CL1__WR_ST_TAG_MODE_MASK 0x00000008L +#define GDC0_A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY_MASK 0x000003F0L +//GDC0_A2S_CNTL_SW0 +#define GDC0_A2S_CNTL_SW0__STATIC_VC_ENABLE__SHIFT 0x0 +#define GDC0_A2S_CNTL_SW0__STATIC_VC_VALUE__SHIFT 0x1 +#define GDC0_A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__SHIFT 0x6 +#define GDC0_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define GDC0_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define GDC0_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define GDC0_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define GDC0_A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT 0x10 +#define GDC0_A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT 0x18 +#define GDC0_A2S_CNTL_SW0__STATIC_VC_ENABLE_MASK 0x00000001L +#define GDC0_A2S_CNTL_SW0__STATIC_VC_VALUE_MASK 0x0000000EL +#define GDC0_A2S_CNTL_SW0__FORCE_RSP_REORDER_EN_MASK 0x00000040L +#define GDC0_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define GDC0_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define GDC0_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define GDC0_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define GDC0_A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define GDC0_A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK 0xFF000000L +//GDC0_A2S_CNTL_SW1 +#define GDC0_A2S_CNTL_SW1__STATIC_VC_ENABLE__SHIFT 0x0 +#define GDC0_A2S_CNTL_SW1__STATIC_VC_VALUE__SHIFT 0x1 +#define GDC0_A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__SHIFT 0x6 +#define GDC0_A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define GDC0_A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define GDC0_A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define GDC0_A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define GDC0_A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT 0x10 +#define GDC0_A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT 0x18 +#define GDC0_A2S_CNTL_SW1__STATIC_VC_ENABLE_MASK 0x00000001L +#define GDC0_A2S_CNTL_SW1__STATIC_VC_VALUE_MASK 0x0000000EL +#define GDC0_A2S_CNTL_SW1__FORCE_RSP_REORDER_EN_MASK 0x00000040L +#define GDC0_A2S_CNTL_SW1__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define GDC0_A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define GDC0_A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define GDC0_A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define GDC0_A2S_CNTL_SW1__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define GDC0_A2S_CNTL_SW1__WRR_WR_WEIGHT_MASK 0xFF000000L +//GDC0_A2S_CNTL_SW2 +#define GDC0_A2S_CNTL_SW2__STATIC_VC_ENABLE__SHIFT 0x0 +#define GDC0_A2S_CNTL_SW2__STATIC_VC_VALUE__SHIFT 0x1 +#define GDC0_A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__SHIFT 0x6 +#define GDC0_A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define GDC0_A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define GDC0_A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define GDC0_A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define GDC0_A2S_CNTL_SW2__WRR_RD_WEIGHT__SHIFT 0x10 +#define GDC0_A2S_CNTL_SW2__WRR_WR_WEIGHT__SHIFT 0x18 +#define GDC0_A2S_CNTL_SW2__STATIC_VC_ENABLE_MASK 0x00000001L +#define GDC0_A2S_CNTL_SW2__STATIC_VC_VALUE_MASK 0x0000000EL +#define GDC0_A2S_CNTL_SW2__FORCE_RSP_REORDER_EN_MASK 0x00000040L +#define GDC0_A2S_CNTL_SW2__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define GDC0_A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define GDC0_A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define GDC0_A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define GDC0_A2S_CNTL_SW2__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define GDC0_A2S_CNTL_SW2__WRR_WR_WEIGHT_MASK 0xFF000000L +//GDC0_A2S_TAG_ALLOC_0 +#define GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT 0x0 +#define GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT 0x8 +#define GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT 0x10 +#define GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK 0x000000FFL +#define GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK 0x0000FF00L +#define GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK 0x00FF0000L +//GDC0_A2S_TAG_ALLOC_1 +#define GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT 0x0 +#define GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT 0x10 +#define GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT 0x18 +#define GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK 0x000000FFL +#define GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK 0x00FF0000L +#define GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK 0xFF000000L +//GDC0_A2S_MISC_CNTL +#define GDC0_A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT 0x0 +#define GDC0_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT 0x2 +#define GDC0_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE__SHIFT 0x3 +#define GDC0_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN__SHIFT 0x4 +#define GDC0_A2S_MISC_CNTL__RSP_REORDER_DIS__SHIFT 0x5 +#define GDC0_A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT 0x6 +#define GDC0_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x7 +#define GDC0_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x8 +#define GDC0_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0x9 +#define GDC0_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0xa +#define GDC0_A2S_MISC_CNTL__WR_TAG_SET_MIN__SHIFT 0x10 +#define GDC0_A2S_MISC_CNTL__RD_TAG_SET_MIN__SHIFT 0x15 +#define GDC0_A2S_MISC_CNTL__WRR_LRG_MODE__SHIFT 0x1a +#define GDC0_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE__SHIFT 0x1b +#define GDC0_A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK 0x00000003L +#define GDC0_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS_MASK 0x00000004L +#define GDC0_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE_MASK 0x00000008L +#define GDC0_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN_MASK 0x00000010L +#define GDC0_A2S_MISC_CNTL__RSP_REORDER_DIS_MASK 0x00000020L +#define GDC0_A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK 0x00000040L +#define GDC0_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000080L +#define GDC0_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000100L +#define GDC0_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY_MASK 0x00000200L +#define GDC0_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000400L +#define GDC0_A2S_MISC_CNTL__WR_TAG_SET_MIN_MASK 0x001F0000L +#define GDC0_A2S_MISC_CNTL__RD_TAG_SET_MIN_MASK 0x03E00000L +#define GDC0_A2S_MISC_CNTL__WRR_LRG_MODE_MASK 0x04000000L +#define GDC0_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE_MASK 0x08000000L +//GDC0_SHUB_REGS_IF_CTL +#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 +#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS__SHIFT 0x1 +#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L +#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS_MASK 0x00000002L +//GDC0_NGDC_MGCG_CTRL +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x0 +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x1 +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x2 +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT 0xa +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT 0xb +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT 0xc +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT 0xd +#define GDC0_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN__SHIFT 0xe +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK 0x00000001L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK 0x00000002L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK 0x000003FCL +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK 0x00000400L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK 0x00000800L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK 0x00001000L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK 0x00002000L +#define GDC0_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN_MASK 0x00004000L +//GDC0_NGDC_RESERVED_0 +#define GDC0_NGDC_RESERVED_0__RESERVED__SHIFT 0x0 +#define GDC0_NGDC_RESERVED_0__RESERVED_MASK 0xFFFFFFFFL +//GDC0_NGDC_RESERVED_1 +#define GDC0_NGDC_RESERVED_1__RESERVED__SHIFT 0x0 +#define GDC0_NGDC_RESERVED_1__RESERVED_MASK 0xFFFFFFFFL +//GDC0_NBIF_GFX_DOORBELL_STATUS +#define GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT 0x0 +#define GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK 0x0000FFFFL +//GDC0_ATDMA_MISC_CNTL +#define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0 +#define GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1 +#define GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT 0x2 +#define GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT 0x8 +#define GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT 0x10 +#define GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT 0x18 +#define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000001L +#define GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L +#define GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK 0x0000000CL +#define GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK 0x0000FF00L +#define GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK 0x00FF0000L +#define GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK 0xFF000000L +//GDC0_S2A_MISC_CNTL +#define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3 +#define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT 0x8 +#define GDC0_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT 0xa +#define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT 0xc +#define GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT 0xf +#define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT 0x10 +#define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L +#define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE_MASK 0x00000300L +#define GDC0_S2A_MISC_CNTL__RB_ARB_MODE_MASK 0x00000C00L +#define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK 0x00003000L +#define GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK 0x00008000L +#define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK 0x000F0000L +//GDC0_NGDC_PG_MISC_CTRL +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY__SHIFT 0xa +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1__SHIFT 0xd +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS__SHIFT 0xe +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2__SHIFT 0x10 +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18 +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY_MASK 0x00000400L +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1_MASK 0x00002000L +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS_MASK 0x00004000L +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2_MASK 0x00010000L +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L +//GDC0_NGDC_PGMST_CTRL +#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS__SHIFT 0x0 +#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN__SHIFT 0x8 +#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN__SHIFT 0xa +#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN__SHIFT 0xe +#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS_MASK 0x000000FFL +#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN_MASK 0x00000100L +#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L +#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L +//GDC0_NGDC_PGSLV_CTRL +#define GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0 +#define GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5 +#define GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS__SHIFT 0xa +#define GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL +#define GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L +#define GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS_MASK 0x00007C00L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_COMMAND +#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_STATUS +#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_LATENCY +#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_HEADER +#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_BIST +#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF0_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PMI_CAP +#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +//BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//PCIE_PAGE_REQ_ENH_CAP_LIST +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_PAGE_REQ_CNTL +#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 +#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 +#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L +#define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L +//PCIE_PAGE_REQ_STATUS +#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 +#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 +#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 +#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf +#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L +#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L +#define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L +#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L +//PCIE_OUTSTAND_PAGE_REQ_CAPACITY +#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 +#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL +//PCIE_OUTSTAND_PAGE_REQ_ALLOC +#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 +#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_MC_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//PCIE_SRIOV_ENH_CAP_LIST +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_SRIOV_CAP +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//PCIE_SRIOV_CONTROL +#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +#define PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L +//PCIE_SRIOV_STATUS +#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//PCIE_SRIOV_INITIAL_VFS +#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//PCIE_SRIOV_TOTAL_VFS +#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//PCIE_SRIOV_NUM_VFS +#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//PCIE_SRIOV_FUNC_DEP_LINK +#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL +//PCIE_SRIOV_FIRST_VF_OFFSET +#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//PCIE_SRIOV_VF_STRIDE +#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//PCIE_SRIOV_VF_DEVICE_ID +#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_0 +#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_1 +#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_2 +#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_3 +#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_4 +#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_5 +#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_LINK_CAP_16GT +#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LINK_CAP_32GT +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L +//BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L +//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x0000000FL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x000000F0L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN2SCH_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN3SCH_OFFSET__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET_MASK 0x0000FF00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN2SCH_OFFSET_MASK 0x00FF0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN3SCH_OFFSET_MASK 0xFF000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN4SCH_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN5SCH_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN6SCH_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN7SCH_OFFSET__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN4SCH_OFFSET_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN5SCH_OFFSET_MASK 0x0000FF00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN6SCH_OFFSET_MASK 0x00FF0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN7SCH_OFFSET_MASK 0xFF000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN8SCH_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN9SCH_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN10SCH_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN11SCH_OFFSET__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN8SCH_OFFSET_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN9SCH_OFFSET_MASK 0x0000FF00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN10SCH_OFFSET_MASK 0x00FF0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN11SCH_OFFSET_MASK 0xFF000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX0SCH_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX1SCH_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX2SCH_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX3SCH_OFFSET__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX0SCH_OFFSET_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX1SCH_OFFSET_MASK 0x0000FF00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX2SCH_OFFSET_MASK 0x00FF0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX3SCH_OFFSET_MASK 0xFF000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX4SCH_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX5SCH_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX6SCH_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX7SCH_OFFSET__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX4SCH_OFFSET_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX5SCH_OFFSET_MASK 0x0000FF00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX6SCH_OFFSET_MASK 0x00FF0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX7SCH_OFFSET_MASK 0xFF000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +//BIF_CFG_DEV0_EPF1_VENDOR_ID +#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_COMMAND +#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_STATUS +#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_REVISION_ID +#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_SUB_CLASS +#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_BASE_CLASS +#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_CACHE_LINE +#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_LATENCY +#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_HEADER +#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF1_BIST +#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF1_CAP_PTR +#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_MIN_GRANT +#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF1_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_PMI_CAP +#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_PCIE_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF1_LINK_CAP +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_LINK_CNTL +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF1_LINK_STATUS +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_MSI_MASK +#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSI_PENDING +#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_MSIX_PBA +#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +//BIF_CFG_DEV0_RC0_VENDOR_ID +#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_DEVICE_ID +#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_COMMAND +#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_RC0_STATUS +#define BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_REVISION_ID +#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_RC0_PROG_INTERFACE +#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_RC0_SUB_CLASS +#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC0_BASE_CLASS +#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC0_CACHE_LINE +#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_RC0_LATENCY +#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_RC0_HEADER +#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_RC0_BIST +#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_RC0_BASE_ADDR_1 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_BASE_ADDR_2 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIF_CFG_DEV0_RC0_SECONDARY_STATUS +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PREF_BASE_UPPER +#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER +#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_CAP_PTR +#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_RC0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_RC0_INTERRUPT_LINE +#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_RC0_INTERRUPT_PIN +#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L +//BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL +#define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIF_CFG_DEV0_RC0_PMI_CAP_LIST +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_PMI_CAP +#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_PCIE_CAP +#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_RC0_DEVICE_CAP +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_RC0_DEVICE_CNTL +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIF_CFG_DEV0_RC0_DEVICE_STATUS +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_RC0_LINK_CAP +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_LINK_CNTL +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_RC0_LINK_STATUS +#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_RC0_SLOT_CAP +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIF_CFG_DEV0_RC0_SLOT_CNTL +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__INBAND_PD_DISABLE__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__INBAND_PD_DISABLE_MASK 0x4000L +//BIF_CFG_DEV0_RC0_SLOT_STATUS +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIF_CFG_DEV0_RC0_ROOT_CNTL +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIF_CFG_DEV0_RC0_ROOT_CAP +#define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIF_CFG_DEV0_RC0_ROOT_STATUS +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIF_CFG_DEV0_RC0_DEVICE_CAP2 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_RC0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_LINK_CAP2 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_LINK_CNTL2 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_RC0_LINK_STATUS2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_SLOT_CAP2 +#define BIF_CFG_DEV0_RC0_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK 0x00000001L +//BIF_CFG_DEV0_RC0_SLOT_CNTL2 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_SLOT_STATUS2 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_MSI_CAP_LIST +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_MSI_MSG_DATA +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_SSID_CAP_LIST +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_SSID_CAP +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS_MASK 0x00000180L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID +#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_LINK_CAP_16GT +#define BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_LINK_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_LINK_STATUS_16GT +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LINK_CAP_32GT +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//BIF_CFG_DEV0_RC0_LINK_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L +//BIF_CFG_DEV0_RC0_LINK_STATUS_32GT +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +//BIF_CFG_DEV0_EPF0_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_COMMAND +#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_0_STATUS +#define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_LATENCY +#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_HEADER +#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_0_BIST +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PMI_CAP +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY +#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC +#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L +//BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x000000F0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN2SCH_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN3SCH_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN2SCH_OFFSET_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN3SCH_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN4SCH_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN5SCH_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN6SCH_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN7SCH_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN4SCH_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN5SCH_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN6SCH_OFFSET_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN7SCH_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN8SCH_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN9SCH_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN10SCH_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN11SCH_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN8SCH_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN9SCH_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN10SCH_OFFSET_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN11SCH_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX0SCH_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX1SCH_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX2SCH_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX3SCH_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX0SCH_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX1SCH_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX2SCH_OFFSET_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX3SCH_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX4SCH_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX5SCH_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX6SCH_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX7SCH_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX4SCH_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX5SCH_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX6SCH_OFFSET_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX7SCH_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +//BIF_CFG_DEV0_EPF1_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_COMMAND +#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_0_STATUS +#define BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_REVISION_ID +#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_LATENCY +#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_HEADER +#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF1_0_BIST +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF1_0_CAP_PTR +#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_PMI_CAP +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF1_0_LINK_CAP +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF1_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF1_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_MASK +#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_RCCPORTDEC +//RCC_DEV0_1_RCC_VDM_SUPPORT +#define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L +#define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L +#define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L +#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L +#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L +//RCC_DEV0_1_RCC_BUS_CNTL +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 +#define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc +#define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 +#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 +#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 +#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c +#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L +#define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L +#define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L +#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L +#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L +#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L +#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L +//RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L +//RCC_DEV0_1_RCC_DEV0_LINK_CNTL +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT 0x10 +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT 0x11 +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK 0x00010000L +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK 0x00020000L +//RCC_DEV0_1_RCC_CMN_LINK_CNTL +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L +//RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L +//RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL +#define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL +//RCC_DEV0_1_RCC_MH_ARB_CNTL +#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 +#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L +#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL +//RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L +//RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L + + +// addressBlock: aid_nbio_nbif0_rcc_ep_dev0_RCCPORTDEC +//RCC_EP_DEV0_1_EP_PCIE_SCRATCH +#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_1_EP_PCIE_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_EP_DEV0_1_EP_PCIE_INT_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +//RCC_EP_DEV0_1_EP_PCIE_INT_STATUS +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L +//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +//RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +//RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +//RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L +//RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC +#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 +#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L +//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL +#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL +//RCC_EP_DEV0_1_EP_PCIEP_RESERVED +#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_1_EP_PCIE_TX_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L +//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L + + +// addressBlock: aid_nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC +//RCC_DWN_DEV0_1_DN_PCIE_RESERVED +#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_1_DN_PCIE_SCRATCH +#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_1_DN_PCIE_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +//RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 +#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L +//RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +//RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L +//RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L + + +// addressBlock: aid_nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC +//RCC_DWNP_DEV0_1_PCIE_ERR_CNTL +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L +//RCC_DWNP_DEV0_1_PCIE_RX_CNTL +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +//RCC_DWNP_DEV0_1_PCIE_LC_CNTL2 +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC +#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L +//RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP +#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_pfc_amdgfx_RCCPFCDEC +//RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L +//RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL +#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 +#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L +#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L + + +// addressBlock: aid_nbio_nbif0_pciemsix_0_usb_MSIXTDEC +//PCIEMSIX_VECT0_ADDR_LO +#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT0_ADDR_HI +#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT0_MSG_DATA +#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT0_CONTROL +#define PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT1_ADDR_LO +#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT1_ADDR_HI +#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT1_MSG_DATA +#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT1_CONTROL +#define PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT2_ADDR_LO +#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT2_ADDR_HI +#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT2_MSG_DATA +#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT2_CONTROL +#define PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT3_ADDR_LO +#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT3_ADDR_HI +#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT3_MSG_DATA +#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT3_CONTROL +#define PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT4_ADDR_LO +#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT4_ADDR_HI +#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT4_MSG_DATA +#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT4_CONTROL +#define PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT5_ADDR_LO +#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT5_ADDR_HI +#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT5_MSG_DATA +#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT5_CONTROL +#define PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT6_ADDR_LO +#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT6_ADDR_HI +#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT6_MSG_DATA +#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT6_CONTROL +#define PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT7_ADDR_LO +#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT7_ADDR_HI +#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT7_MSG_DATA +#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT7_CONTROL +#define PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT8_ADDR_LO +#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT8_ADDR_HI +#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT8_MSG_DATA +#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT8_CONTROL +#define PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT9_ADDR_LO +#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT9_ADDR_HI +#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT9_MSG_DATA +#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT9_CONTROL +#define PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT10_ADDR_LO +#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT10_ADDR_HI +#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT10_MSG_DATA +#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT10_CONTROL +#define PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT11_ADDR_LO +#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT11_ADDR_HI +#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT11_MSG_DATA +#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT11_CONTROL +#define PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT12_ADDR_LO +#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT12_ADDR_HI +#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT12_MSG_DATA +#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT12_CONTROL +#define PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT13_ADDR_LO +#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT13_ADDR_HI +#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT13_MSG_DATA +#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT13_CONTROL +#define PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT14_ADDR_LO +#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT14_ADDR_HI +#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT14_MSG_DATA +#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT14_CONTROL +#define PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT15_ADDR_LO +#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT15_ADDR_HI +#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT15_MSG_DATA +#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT15_CONTROL +#define PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT16_ADDR_LO +#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT16_ADDR_HI +#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT16_MSG_DATA +#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT16_CONTROL +#define PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT17_ADDR_LO +#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT17_ADDR_HI +#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT17_MSG_DATA +#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT17_CONTROL +#define PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT18_ADDR_LO +#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT18_ADDR_HI +#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT18_MSG_DATA +#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT18_CONTROL +#define PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT19_ADDR_LO +#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT19_ADDR_HI +#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT19_MSG_DATA +#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT19_CONTROL +#define PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT20_ADDR_LO +#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT20_ADDR_HI +#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT20_MSG_DATA +#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT20_CONTROL +#define PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT21_ADDR_LO +#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT21_ADDR_HI +#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT21_MSG_DATA +#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT21_CONTROL +#define PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT22_ADDR_LO +#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT22_ADDR_HI +#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT22_MSG_DATA +#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT22_CONTROL +#define PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT23_ADDR_LO +#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT23_ADDR_HI +#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT23_MSG_DATA +#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT23_CONTROL +#define PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT24_ADDR_LO +#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT24_ADDR_HI +#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT24_MSG_DATA +#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT24_CONTROL +#define PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT25_ADDR_LO +#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT25_ADDR_HI +#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT25_MSG_DATA +#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT25_CONTROL +#define PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT26_ADDR_LO +#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT26_ADDR_HI +#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT26_MSG_DATA +#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT26_CONTROL +#define PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT27_ADDR_LO +#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT27_ADDR_HI +#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT27_MSG_DATA +#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT27_CONTROL +#define PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT28_ADDR_LO +#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT28_ADDR_HI +#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT28_MSG_DATA +#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT28_CONTROL +#define PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT29_ADDR_LO +#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT29_ADDR_HI +#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT29_MSG_DATA +#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT29_CONTROL +#define PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT30_ADDR_LO +#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT30_ADDR_HI +#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT30_MSG_DATA +#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT30_CONTROL +#define PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT31_ADDR_LO +#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT31_ADDR_HI +#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT31_MSG_DATA +#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT31_CONTROL +#define PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT32_ADDR_LO +#define PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT32_ADDR_HI +#define PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT32_MSG_DATA +#define PCIEMSIX_VECT32_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT32_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT32_CONTROL +#define PCIEMSIX_VECT32_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT32_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT33_ADDR_LO +#define PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT33_ADDR_HI +#define PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT33_MSG_DATA +#define PCIEMSIX_VECT33_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT33_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT33_CONTROL +#define PCIEMSIX_VECT33_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT33_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT34_ADDR_LO +#define PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT34_ADDR_HI +#define PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT34_MSG_DATA +#define PCIEMSIX_VECT34_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT34_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT34_CONTROL +#define PCIEMSIX_VECT34_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT34_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT35_ADDR_LO +#define PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT35_ADDR_HI +#define PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT35_MSG_DATA +#define PCIEMSIX_VECT35_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT35_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT35_CONTROL +#define PCIEMSIX_VECT35_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT35_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT36_ADDR_LO +#define PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT36_ADDR_HI +#define PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT36_MSG_DATA +#define PCIEMSIX_VECT36_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT36_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT36_CONTROL +#define PCIEMSIX_VECT36_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT36_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT37_ADDR_LO +#define PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT37_ADDR_HI +#define PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT37_MSG_DATA +#define PCIEMSIX_VECT37_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT37_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT37_CONTROL +#define PCIEMSIX_VECT37_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT37_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT38_ADDR_LO +#define PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT38_ADDR_HI +#define PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT38_MSG_DATA +#define PCIEMSIX_VECT38_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT38_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT38_CONTROL +#define PCIEMSIX_VECT38_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT38_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT39_ADDR_LO +#define PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT39_ADDR_HI +#define PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT39_MSG_DATA +#define PCIEMSIX_VECT39_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT39_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT39_CONTROL +#define PCIEMSIX_VECT39_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT39_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT40_ADDR_LO +#define PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT40_ADDR_HI +#define PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT40_MSG_DATA +#define PCIEMSIX_VECT40_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT40_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT40_CONTROL +#define PCIEMSIX_VECT40_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT40_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT41_ADDR_LO +#define PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT41_ADDR_HI +#define PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT41_MSG_DATA +#define PCIEMSIX_VECT41_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT41_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT41_CONTROL +#define PCIEMSIX_VECT41_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT41_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT42_ADDR_LO +#define PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT42_ADDR_HI +#define PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT42_MSG_DATA +#define PCIEMSIX_VECT42_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT42_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT42_CONTROL +#define PCIEMSIX_VECT42_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT42_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT43_ADDR_LO +#define PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT43_ADDR_HI +#define PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT43_MSG_DATA +#define PCIEMSIX_VECT43_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT43_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT43_CONTROL +#define PCIEMSIX_VECT43_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT43_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT44_ADDR_LO +#define PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT44_ADDR_HI +#define PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT44_MSG_DATA +#define PCIEMSIX_VECT44_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT44_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT44_CONTROL +#define PCIEMSIX_VECT44_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT44_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT45_ADDR_LO +#define PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT45_ADDR_HI +#define PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT45_MSG_DATA +#define PCIEMSIX_VECT45_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT45_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT45_CONTROL +#define PCIEMSIX_VECT45_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT45_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT46_ADDR_LO +#define PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT46_ADDR_HI +#define PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT46_MSG_DATA +#define PCIEMSIX_VECT46_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT46_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT46_CONTROL +#define PCIEMSIX_VECT46_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT46_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT47_ADDR_LO +#define PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT47_ADDR_HI +#define PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT47_MSG_DATA +#define PCIEMSIX_VECT47_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT47_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT47_CONTROL +#define PCIEMSIX_VECT47_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT47_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT48_ADDR_LO +#define PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT48_ADDR_HI +#define PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT48_MSG_DATA +#define PCIEMSIX_VECT48_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT48_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT48_CONTROL +#define PCIEMSIX_VECT48_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT48_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT49_ADDR_LO +#define PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT49_ADDR_HI +#define PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT49_MSG_DATA +#define PCIEMSIX_VECT49_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT49_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT49_CONTROL +#define PCIEMSIX_VECT49_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT49_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT50_ADDR_LO +#define PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT50_ADDR_HI +#define PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT50_MSG_DATA +#define PCIEMSIX_VECT50_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT50_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT50_CONTROL +#define PCIEMSIX_VECT50_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT50_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT51_ADDR_LO +#define PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT51_ADDR_HI +#define PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT51_MSG_DATA +#define PCIEMSIX_VECT51_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT51_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT51_CONTROL +#define PCIEMSIX_VECT51_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT51_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT52_ADDR_LO +#define PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT52_ADDR_HI +#define PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT52_MSG_DATA +#define PCIEMSIX_VECT52_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT52_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT52_CONTROL +#define PCIEMSIX_VECT52_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT52_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT53_ADDR_LO +#define PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT53_ADDR_HI +#define PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT53_MSG_DATA +#define PCIEMSIX_VECT53_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT53_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT53_CONTROL +#define PCIEMSIX_VECT53_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT53_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT54_ADDR_LO +#define PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT54_ADDR_HI +#define PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT54_MSG_DATA +#define PCIEMSIX_VECT54_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT54_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT54_CONTROL +#define PCIEMSIX_VECT54_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT54_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT55_ADDR_LO +#define PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT55_ADDR_HI +#define PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT55_MSG_DATA +#define PCIEMSIX_VECT55_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT55_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT55_CONTROL +#define PCIEMSIX_VECT55_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT55_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT56_ADDR_LO +#define PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT56_ADDR_HI +#define PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT56_MSG_DATA +#define PCIEMSIX_VECT56_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT56_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT56_CONTROL +#define PCIEMSIX_VECT56_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT56_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT57_ADDR_LO +#define PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT57_ADDR_HI +#define PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT57_MSG_DATA +#define PCIEMSIX_VECT57_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT57_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT57_CONTROL +#define PCIEMSIX_VECT57_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT57_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT58_ADDR_LO +#define PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT58_ADDR_HI +#define PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT58_MSG_DATA +#define PCIEMSIX_VECT58_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT58_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT58_CONTROL +#define PCIEMSIX_VECT58_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT58_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT59_ADDR_LO +#define PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT59_ADDR_HI +#define PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT59_MSG_DATA +#define PCIEMSIX_VECT59_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT59_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT59_CONTROL +#define PCIEMSIX_VECT59_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT59_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT60_ADDR_LO +#define PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT60_ADDR_HI +#define PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT60_MSG_DATA +#define PCIEMSIX_VECT60_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT60_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT60_CONTROL +#define PCIEMSIX_VECT60_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT60_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT61_ADDR_LO +#define PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT61_ADDR_HI +#define PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT61_MSG_DATA +#define PCIEMSIX_VECT61_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT61_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT61_CONTROL +#define PCIEMSIX_VECT61_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT61_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT62_ADDR_LO +#define PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT62_ADDR_HI +#define PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT62_MSG_DATA +#define PCIEMSIX_VECT62_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT62_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT62_CONTROL +#define PCIEMSIX_VECT62_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT62_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT63_ADDR_LO +#define PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT63_ADDR_HI +#define PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT63_MSG_DATA +#define PCIEMSIX_VECT63_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT63_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT63_CONTROL +#define PCIEMSIX_VECT63_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT63_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT64_ADDR_LO +#define PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT64_ADDR_HI +#define PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT64_MSG_DATA +#define PCIEMSIX_VECT64_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT64_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT64_CONTROL +#define PCIEMSIX_VECT64_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT64_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT65_ADDR_LO +#define PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT65_ADDR_HI +#define PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT65_MSG_DATA +#define PCIEMSIX_VECT65_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT65_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT65_CONTROL +#define PCIEMSIX_VECT65_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT65_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT66_ADDR_LO +#define PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT66_ADDR_HI +#define PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT66_MSG_DATA +#define PCIEMSIX_VECT66_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT66_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT66_CONTROL +#define PCIEMSIX_VECT66_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT66_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT67_ADDR_LO +#define PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT67_ADDR_HI +#define PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT67_MSG_DATA +#define PCIEMSIX_VECT67_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT67_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT67_CONTROL +#define PCIEMSIX_VECT67_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT67_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT68_ADDR_LO +#define PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT68_ADDR_HI +#define PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT68_MSG_DATA +#define PCIEMSIX_VECT68_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT68_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT68_CONTROL +#define PCIEMSIX_VECT68_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT68_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT69_ADDR_LO +#define PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT69_ADDR_HI +#define PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT69_MSG_DATA +#define PCIEMSIX_VECT69_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT69_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT69_CONTROL +#define PCIEMSIX_VECT69_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT69_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT70_ADDR_LO +#define PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT70_ADDR_HI +#define PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT70_MSG_DATA +#define PCIEMSIX_VECT70_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT70_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT70_CONTROL +#define PCIEMSIX_VECT70_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT70_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT71_ADDR_LO +#define PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT71_ADDR_HI +#define PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT71_MSG_DATA +#define PCIEMSIX_VECT71_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT71_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT71_CONTROL +#define PCIEMSIX_VECT71_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT71_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT72_ADDR_LO +#define PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT72_ADDR_HI +#define PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT72_MSG_DATA +#define PCIEMSIX_VECT72_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT72_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT72_CONTROL +#define PCIEMSIX_VECT72_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT72_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT73_ADDR_LO +#define PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT73_ADDR_HI +#define PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT73_MSG_DATA +#define PCIEMSIX_VECT73_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT73_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT73_CONTROL +#define PCIEMSIX_VECT73_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT73_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT74_ADDR_LO +#define PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT74_ADDR_HI +#define PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT74_MSG_DATA +#define PCIEMSIX_VECT74_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT74_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT74_CONTROL +#define PCIEMSIX_VECT74_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT74_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT75_ADDR_LO +#define PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT75_ADDR_HI +#define PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT75_MSG_DATA +#define PCIEMSIX_VECT75_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT75_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT75_CONTROL +#define PCIEMSIX_VECT75_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT75_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT76_ADDR_LO +#define PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT76_ADDR_HI +#define PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT76_MSG_DATA +#define PCIEMSIX_VECT76_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT76_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT76_CONTROL +#define PCIEMSIX_VECT76_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT76_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT77_ADDR_LO +#define PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT77_ADDR_HI +#define PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT77_MSG_DATA +#define PCIEMSIX_VECT77_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT77_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT77_CONTROL +#define PCIEMSIX_VECT77_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT77_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT78_ADDR_LO +#define PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT78_ADDR_HI +#define PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT78_MSG_DATA +#define PCIEMSIX_VECT78_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT78_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT78_CONTROL +#define PCIEMSIX_VECT78_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT78_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT79_ADDR_LO +#define PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT79_ADDR_HI +#define PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT79_MSG_DATA +#define PCIEMSIX_VECT79_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT79_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT79_CONTROL +#define PCIEMSIX_VECT79_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT79_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT80_ADDR_LO +#define PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT80_ADDR_HI +#define PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT80_MSG_DATA +#define PCIEMSIX_VECT80_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT80_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT80_CONTROL +#define PCIEMSIX_VECT80_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT80_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT81_ADDR_LO +#define PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT81_ADDR_HI +#define PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT81_MSG_DATA +#define PCIEMSIX_VECT81_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT81_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT81_CONTROL +#define PCIEMSIX_VECT81_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT81_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT82_ADDR_LO +#define PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT82_ADDR_HI +#define PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT82_MSG_DATA +#define PCIEMSIX_VECT82_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT82_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT82_CONTROL +#define PCIEMSIX_VECT82_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT82_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT83_ADDR_LO +#define PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT83_ADDR_HI +#define PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT83_MSG_DATA +#define PCIEMSIX_VECT83_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT83_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT83_CONTROL +#define PCIEMSIX_VECT83_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT83_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT84_ADDR_LO +#define PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT84_ADDR_HI +#define PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT84_MSG_DATA +#define PCIEMSIX_VECT84_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT84_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT84_CONTROL +#define PCIEMSIX_VECT84_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT84_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT85_ADDR_LO +#define PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT85_ADDR_HI +#define PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT85_MSG_DATA +#define PCIEMSIX_VECT85_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT85_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT85_CONTROL +#define PCIEMSIX_VECT85_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT85_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT86_ADDR_LO +#define PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT86_ADDR_HI +#define PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT86_MSG_DATA +#define PCIEMSIX_VECT86_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT86_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT86_CONTROL +#define PCIEMSIX_VECT86_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT86_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT87_ADDR_LO +#define PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT87_ADDR_HI +#define PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT87_MSG_DATA +#define PCIEMSIX_VECT87_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT87_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT87_CONTROL +#define PCIEMSIX_VECT87_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT87_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT88_ADDR_LO +#define PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT88_ADDR_HI +#define PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT88_MSG_DATA +#define PCIEMSIX_VECT88_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT88_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT88_CONTROL +#define PCIEMSIX_VECT88_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT88_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT89_ADDR_LO +#define PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT89_ADDR_HI +#define PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT89_MSG_DATA +#define PCIEMSIX_VECT89_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT89_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT89_CONTROL +#define PCIEMSIX_VECT89_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT89_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT90_ADDR_LO +#define PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT90_ADDR_HI +#define PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT90_MSG_DATA +#define PCIEMSIX_VECT90_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT90_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT90_CONTROL +#define PCIEMSIX_VECT90_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT90_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT91_ADDR_LO +#define PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT91_ADDR_HI +#define PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT91_MSG_DATA +#define PCIEMSIX_VECT91_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT91_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT91_CONTROL +#define PCIEMSIX_VECT91_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT91_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT92_ADDR_LO +#define PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT92_ADDR_HI +#define PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT92_MSG_DATA +#define PCIEMSIX_VECT92_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT92_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT92_CONTROL +#define PCIEMSIX_VECT92_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT92_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT93_ADDR_LO +#define PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT93_ADDR_HI +#define PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT93_MSG_DATA +#define PCIEMSIX_VECT93_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT93_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT93_CONTROL +#define PCIEMSIX_VECT93_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT93_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT94_ADDR_LO +#define PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT94_ADDR_HI +#define PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT94_MSG_DATA +#define PCIEMSIX_VECT94_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT94_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT94_CONTROL +#define PCIEMSIX_VECT94_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT94_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT95_ADDR_LO +#define PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT95_ADDR_HI +#define PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT95_MSG_DATA +#define PCIEMSIX_VECT95_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT95_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT95_CONTROL +#define PCIEMSIX_VECT95_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT95_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT96_ADDR_LO +#define PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT96_ADDR_HI +#define PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT96_MSG_DATA +#define PCIEMSIX_VECT96_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT96_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT96_CONTROL +#define PCIEMSIX_VECT96_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT96_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT97_ADDR_LO +#define PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT97_ADDR_HI +#define PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT97_MSG_DATA +#define PCIEMSIX_VECT97_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT97_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT97_CONTROL +#define PCIEMSIX_VECT97_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT97_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT98_ADDR_LO +#define PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT98_ADDR_HI +#define PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT98_MSG_DATA +#define PCIEMSIX_VECT98_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT98_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT98_CONTROL +#define PCIEMSIX_VECT98_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT98_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT99_ADDR_LO +#define PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT99_ADDR_HI +#define PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT99_MSG_DATA +#define PCIEMSIX_VECT99_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT99_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT99_CONTROL +#define PCIEMSIX_VECT99_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT99_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT100_ADDR_LO +#define PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT100_ADDR_HI +#define PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT100_MSG_DATA +#define PCIEMSIX_VECT100_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT100_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT100_CONTROL +#define PCIEMSIX_VECT100_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT100_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT101_ADDR_LO +#define PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT101_ADDR_HI +#define PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT101_MSG_DATA +#define PCIEMSIX_VECT101_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT101_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT101_CONTROL +#define PCIEMSIX_VECT101_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT101_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT102_ADDR_LO +#define PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT102_ADDR_HI +#define PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT102_MSG_DATA +#define PCIEMSIX_VECT102_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT102_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT102_CONTROL +#define PCIEMSIX_VECT102_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT102_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT103_ADDR_LO +#define PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT103_ADDR_HI +#define PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT103_MSG_DATA +#define PCIEMSIX_VECT103_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT103_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT103_CONTROL +#define PCIEMSIX_VECT103_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT103_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT104_ADDR_LO +#define PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT104_ADDR_HI +#define PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT104_MSG_DATA +#define PCIEMSIX_VECT104_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT104_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT104_CONTROL +#define PCIEMSIX_VECT104_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT104_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT105_ADDR_LO +#define PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT105_ADDR_HI +#define PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT105_MSG_DATA +#define PCIEMSIX_VECT105_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT105_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT105_CONTROL +#define PCIEMSIX_VECT105_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT105_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT106_ADDR_LO +#define PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT106_ADDR_HI +#define PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT106_MSG_DATA +#define PCIEMSIX_VECT106_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT106_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT106_CONTROL +#define PCIEMSIX_VECT106_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT106_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT107_ADDR_LO +#define PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT107_ADDR_HI +#define PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT107_MSG_DATA +#define PCIEMSIX_VECT107_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT107_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT107_CONTROL +#define PCIEMSIX_VECT107_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT107_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT108_ADDR_LO +#define PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT108_ADDR_HI +#define PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT108_MSG_DATA +#define PCIEMSIX_VECT108_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT108_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT108_CONTROL +#define PCIEMSIX_VECT108_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT108_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT109_ADDR_LO +#define PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT109_ADDR_HI +#define PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT109_MSG_DATA +#define PCIEMSIX_VECT109_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT109_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT109_CONTROL +#define PCIEMSIX_VECT109_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT109_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT110_ADDR_LO +#define PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT110_ADDR_HI +#define PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT110_MSG_DATA +#define PCIEMSIX_VECT110_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT110_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT110_CONTROL +#define PCIEMSIX_VECT110_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT110_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT111_ADDR_LO +#define PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT111_ADDR_HI +#define PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT111_MSG_DATA +#define PCIEMSIX_VECT111_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT111_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT111_CONTROL +#define PCIEMSIX_VECT111_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT111_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT112_ADDR_LO +#define PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT112_ADDR_HI +#define PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT112_MSG_DATA +#define PCIEMSIX_VECT112_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT112_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT112_CONTROL +#define PCIEMSIX_VECT112_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT112_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT113_ADDR_LO +#define PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT113_ADDR_HI +#define PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT113_MSG_DATA +#define PCIEMSIX_VECT113_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT113_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT113_CONTROL +#define PCIEMSIX_VECT113_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT113_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT114_ADDR_LO +#define PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT114_ADDR_HI +#define PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT114_MSG_DATA +#define PCIEMSIX_VECT114_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT114_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT114_CONTROL +#define PCIEMSIX_VECT114_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT114_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT115_ADDR_LO +#define PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT115_ADDR_HI +#define PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT115_MSG_DATA +#define PCIEMSIX_VECT115_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT115_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT115_CONTROL +#define PCIEMSIX_VECT115_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT115_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT116_ADDR_LO +#define PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT116_ADDR_HI +#define PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT116_MSG_DATA +#define PCIEMSIX_VECT116_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT116_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT116_CONTROL +#define PCIEMSIX_VECT116_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT116_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT117_ADDR_LO +#define PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT117_ADDR_HI +#define PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT117_MSG_DATA +#define PCIEMSIX_VECT117_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT117_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT117_CONTROL +#define PCIEMSIX_VECT117_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT117_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT118_ADDR_LO +#define PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT118_ADDR_HI +#define PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT118_MSG_DATA +#define PCIEMSIX_VECT118_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT118_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT118_CONTROL +#define PCIEMSIX_VECT118_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT118_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT119_ADDR_LO +#define PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT119_ADDR_HI +#define PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT119_MSG_DATA +#define PCIEMSIX_VECT119_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT119_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT119_CONTROL +#define PCIEMSIX_VECT119_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT119_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT120_ADDR_LO +#define PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT120_ADDR_HI +#define PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT120_MSG_DATA +#define PCIEMSIX_VECT120_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT120_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT120_CONTROL +#define PCIEMSIX_VECT120_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT120_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT121_ADDR_LO +#define PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT121_ADDR_HI +#define PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT121_MSG_DATA +#define PCIEMSIX_VECT121_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT121_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT121_CONTROL +#define PCIEMSIX_VECT121_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT121_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT122_ADDR_LO +#define PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT122_ADDR_HI +#define PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT122_MSG_DATA +#define PCIEMSIX_VECT122_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT122_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT122_CONTROL +#define PCIEMSIX_VECT122_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT122_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT123_ADDR_LO +#define PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT123_ADDR_HI +#define PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT123_MSG_DATA +#define PCIEMSIX_VECT123_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT123_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT123_CONTROL +#define PCIEMSIX_VECT123_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT123_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT124_ADDR_LO +#define PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT124_ADDR_HI +#define PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT124_MSG_DATA +#define PCIEMSIX_VECT124_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT124_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT124_CONTROL +#define PCIEMSIX_VECT124_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT124_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT125_ADDR_LO +#define PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT125_ADDR_HI +#define PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT125_MSG_DATA +#define PCIEMSIX_VECT125_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT125_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT125_CONTROL +#define PCIEMSIX_VECT125_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT125_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT126_ADDR_LO +#define PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT126_ADDR_HI +#define PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT126_MSG_DATA +#define PCIEMSIX_VECT126_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT126_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT126_CONTROL +#define PCIEMSIX_VECT126_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT126_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT127_ADDR_LO +#define PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT127_ADDR_HI +#define PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT127_MSG_DATA +#define PCIEMSIX_VECT127_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT127_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT127_CONTROL +#define PCIEMSIX_VECT127_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT127_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT128_ADDR_LO +#define PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT128_ADDR_HI +#define PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT128_MSG_DATA +#define PCIEMSIX_VECT128_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT128_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT128_CONTROL +#define PCIEMSIX_VECT128_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT128_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT129_ADDR_LO +#define PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT129_ADDR_HI +#define PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT129_MSG_DATA +#define PCIEMSIX_VECT129_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT129_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT129_CONTROL +#define PCIEMSIX_VECT129_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT129_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT130_ADDR_LO +#define PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT130_ADDR_HI +#define PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT130_MSG_DATA +#define PCIEMSIX_VECT130_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT130_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT130_CONTROL +#define PCIEMSIX_VECT130_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT130_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT131_ADDR_LO +#define PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT131_ADDR_HI +#define PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT131_MSG_DATA +#define PCIEMSIX_VECT131_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT131_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT131_CONTROL +#define PCIEMSIX_VECT131_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT131_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT132_ADDR_LO +#define PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT132_ADDR_HI +#define PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT132_MSG_DATA +#define PCIEMSIX_VECT132_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT132_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT132_CONTROL +#define PCIEMSIX_VECT132_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT132_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT133_ADDR_LO +#define PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT133_ADDR_HI +#define PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT133_MSG_DATA +#define PCIEMSIX_VECT133_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT133_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT133_CONTROL +#define PCIEMSIX_VECT133_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT133_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT134_ADDR_LO +#define PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT134_ADDR_HI +#define PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT134_MSG_DATA +#define PCIEMSIX_VECT134_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT134_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT134_CONTROL +#define PCIEMSIX_VECT134_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT134_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT135_ADDR_LO +#define PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT135_ADDR_HI +#define PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT135_MSG_DATA +#define PCIEMSIX_VECT135_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT135_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT135_CONTROL +#define PCIEMSIX_VECT135_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT135_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT136_ADDR_LO +#define PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT136_ADDR_HI +#define PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT136_MSG_DATA +#define PCIEMSIX_VECT136_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT136_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT136_CONTROL +#define PCIEMSIX_VECT136_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT136_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT137_ADDR_LO +#define PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT137_ADDR_HI +#define PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT137_MSG_DATA +#define PCIEMSIX_VECT137_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT137_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT137_CONTROL +#define PCIEMSIX_VECT137_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT137_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT138_ADDR_LO +#define PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT138_ADDR_HI +#define PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT138_MSG_DATA +#define PCIEMSIX_VECT138_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT138_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT138_CONTROL +#define PCIEMSIX_VECT138_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT138_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT139_ADDR_LO +#define PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT139_ADDR_HI +#define PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT139_MSG_DATA +#define PCIEMSIX_VECT139_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT139_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT139_CONTROL +#define PCIEMSIX_VECT139_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT139_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT140_ADDR_LO +#define PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT140_ADDR_HI +#define PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT140_MSG_DATA +#define PCIEMSIX_VECT140_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT140_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT140_CONTROL +#define PCIEMSIX_VECT140_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT140_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT141_ADDR_LO +#define PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT141_ADDR_HI +#define PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT141_MSG_DATA +#define PCIEMSIX_VECT141_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT141_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT141_CONTROL +#define PCIEMSIX_VECT141_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT141_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT142_ADDR_LO +#define PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT142_ADDR_HI +#define PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT142_MSG_DATA +#define PCIEMSIX_VECT142_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT142_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT142_CONTROL +#define PCIEMSIX_VECT142_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT142_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT143_ADDR_LO +#define PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT143_ADDR_HI +#define PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT143_MSG_DATA +#define PCIEMSIX_VECT143_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT143_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT143_CONTROL +#define PCIEMSIX_VECT143_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT143_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT144_ADDR_LO +#define PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT144_ADDR_HI +#define PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT144_MSG_DATA +#define PCIEMSIX_VECT144_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT144_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT144_CONTROL +#define PCIEMSIX_VECT144_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT144_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT145_ADDR_LO +#define PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT145_ADDR_HI +#define PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT145_MSG_DATA +#define PCIEMSIX_VECT145_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT145_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT145_CONTROL +#define PCIEMSIX_VECT145_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT145_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT146_ADDR_LO +#define PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT146_ADDR_HI +#define PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT146_MSG_DATA +#define PCIEMSIX_VECT146_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT146_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT146_CONTROL +#define PCIEMSIX_VECT146_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT146_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT147_ADDR_LO +#define PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT147_ADDR_HI +#define PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT147_MSG_DATA +#define PCIEMSIX_VECT147_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT147_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT147_CONTROL +#define PCIEMSIX_VECT147_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT147_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT148_ADDR_LO +#define PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT148_ADDR_HI +#define PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT148_MSG_DATA +#define PCIEMSIX_VECT148_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT148_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT148_CONTROL +#define PCIEMSIX_VECT148_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT148_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT149_ADDR_LO +#define PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT149_ADDR_HI +#define PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT149_MSG_DATA +#define PCIEMSIX_VECT149_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT149_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT149_CONTROL +#define PCIEMSIX_VECT149_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT149_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT150_ADDR_LO +#define PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT150_ADDR_HI +#define PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT150_MSG_DATA +#define PCIEMSIX_VECT150_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT150_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT150_CONTROL +#define PCIEMSIX_VECT150_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT150_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT151_ADDR_LO +#define PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT151_ADDR_HI +#define PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT151_MSG_DATA +#define PCIEMSIX_VECT151_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT151_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT151_CONTROL +#define PCIEMSIX_VECT151_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT151_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT152_ADDR_LO +#define PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT152_ADDR_HI +#define PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT152_MSG_DATA +#define PCIEMSIX_VECT152_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT152_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT152_CONTROL +#define PCIEMSIX_VECT152_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT152_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT153_ADDR_LO +#define PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT153_ADDR_HI +#define PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT153_MSG_DATA +#define PCIEMSIX_VECT153_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT153_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT153_CONTROL +#define PCIEMSIX_VECT153_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT153_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT154_ADDR_LO +#define PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT154_ADDR_HI +#define PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT154_MSG_DATA +#define PCIEMSIX_VECT154_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT154_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT154_CONTROL +#define PCIEMSIX_VECT154_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT154_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT155_ADDR_LO +#define PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT155_ADDR_HI +#define PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT155_MSG_DATA +#define PCIEMSIX_VECT155_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT155_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT155_CONTROL +#define PCIEMSIX_VECT155_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT155_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT156_ADDR_LO +#define PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT156_ADDR_HI +#define PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT156_MSG_DATA +#define PCIEMSIX_VECT156_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT156_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT156_CONTROL +#define PCIEMSIX_VECT156_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT156_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT157_ADDR_LO +#define PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT157_ADDR_HI +#define PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT157_MSG_DATA +#define PCIEMSIX_VECT157_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT157_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT157_CONTROL +#define PCIEMSIX_VECT157_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT157_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT158_ADDR_LO +#define PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT158_ADDR_HI +#define PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT158_MSG_DATA +#define PCIEMSIX_VECT158_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT158_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT158_CONTROL +#define PCIEMSIX_VECT158_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT158_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT159_ADDR_LO +#define PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT159_ADDR_HI +#define PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT159_MSG_DATA +#define PCIEMSIX_VECT159_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT159_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT159_CONTROL +#define PCIEMSIX_VECT159_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT159_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT160_ADDR_LO +#define PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT160_ADDR_HI +#define PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT160_MSG_DATA +#define PCIEMSIX_VECT160_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT160_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT160_CONTROL +#define PCIEMSIX_VECT160_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT160_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT161_ADDR_LO +#define PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT161_ADDR_HI +#define PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT161_MSG_DATA +#define PCIEMSIX_VECT161_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT161_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT161_CONTROL +#define PCIEMSIX_VECT161_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT161_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT162_ADDR_LO +#define PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT162_ADDR_HI +#define PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT162_MSG_DATA +#define PCIEMSIX_VECT162_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT162_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT162_CONTROL +#define PCIEMSIX_VECT162_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT162_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT163_ADDR_LO +#define PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT163_ADDR_HI +#define PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT163_MSG_DATA +#define PCIEMSIX_VECT163_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT163_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT163_CONTROL +#define PCIEMSIX_VECT163_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT163_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT164_ADDR_LO +#define PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT164_ADDR_HI +#define PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT164_MSG_DATA +#define PCIEMSIX_VECT164_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT164_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT164_CONTROL +#define PCIEMSIX_VECT164_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT164_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT165_ADDR_LO +#define PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT165_ADDR_HI +#define PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT165_MSG_DATA +#define PCIEMSIX_VECT165_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT165_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT165_CONTROL +#define PCIEMSIX_VECT165_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT165_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT166_ADDR_LO +#define PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT166_ADDR_HI +#define PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT166_MSG_DATA +#define PCIEMSIX_VECT166_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT166_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT166_CONTROL +#define PCIEMSIX_VECT166_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT166_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT167_ADDR_LO +#define PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT167_ADDR_HI +#define PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT167_MSG_DATA +#define PCIEMSIX_VECT167_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT167_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT167_CONTROL +#define PCIEMSIX_VECT167_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT167_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT168_ADDR_LO +#define PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT168_ADDR_HI +#define PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT168_MSG_DATA +#define PCIEMSIX_VECT168_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT168_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT168_CONTROL +#define PCIEMSIX_VECT168_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT168_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT169_ADDR_LO +#define PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT169_ADDR_HI +#define PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT169_MSG_DATA +#define PCIEMSIX_VECT169_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT169_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT169_CONTROL +#define PCIEMSIX_VECT169_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT169_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT170_ADDR_LO +#define PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT170_ADDR_HI +#define PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT170_MSG_DATA +#define PCIEMSIX_VECT170_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT170_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT170_CONTROL +#define PCIEMSIX_VECT170_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT170_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT171_ADDR_LO +#define PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT171_ADDR_HI +#define PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT171_MSG_DATA +#define PCIEMSIX_VECT171_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT171_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT171_CONTROL +#define PCIEMSIX_VECT171_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT171_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT172_ADDR_LO +#define PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT172_ADDR_HI +#define PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT172_MSG_DATA +#define PCIEMSIX_VECT172_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT172_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT172_CONTROL +#define PCIEMSIX_VECT172_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT172_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT173_ADDR_LO +#define PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT173_ADDR_HI +#define PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT173_MSG_DATA +#define PCIEMSIX_VECT173_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT173_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT173_CONTROL +#define PCIEMSIX_VECT173_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT173_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT174_ADDR_LO +#define PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT174_ADDR_HI +#define PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT174_MSG_DATA +#define PCIEMSIX_VECT174_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT174_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT174_CONTROL +#define PCIEMSIX_VECT174_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT174_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT175_ADDR_LO +#define PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT175_ADDR_HI +#define PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT175_MSG_DATA +#define PCIEMSIX_VECT175_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT175_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT175_CONTROL +#define PCIEMSIX_VECT175_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT175_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT176_ADDR_LO +#define PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT176_ADDR_HI +#define PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT176_MSG_DATA +#define PCIEMSIX_VECT176_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT176_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT176_CONTROL +#define PCIEMSIX_VECT176_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT176_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT177_ADDR_LO +#define PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT177_ADDR_HI +#define PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT177_MSG_DATA +#define PCIEMSIX_VECT177_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT177_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT177_CONTROL +#define PCIEMSIX_VECT177_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT177_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT178_ADDR_LO +#define PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT178_ADDR_HI +#define PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT178_MSG_DATA +#define PCIEMSIX_VECT178_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT178_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT178_CONTROL +#define PCIEMSIX_VECT178_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT178_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT179_ADDR_LO +#define PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT179_ADDR_HI +#define PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT179_MSG_DATA +#define PCIEMSIX_VECT179_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT179_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT179_CONTROL +#define PCIEMSIX_VECT179_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT179_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT180_ADDR_LO +#define PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT180_ADDR_HI +#define PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT180_MSG_DATA +#define PCIEMSIX_VECT180_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT180_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT180_CONTROL +#define PCIEMSIX_VECT180_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT180_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT181_ADDR_LO +#define PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT181_ADDR_HI +#define PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT181_MSG_DATA +#define PCIEMSIX_VECT181_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT181_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT181_CONTROL +#define PCIEMSIX_VECT181_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT181_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT182_ADDR_LO +#define PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT182_ADDR_HI +#define PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT182_MSG_DATA +#define PCIEMSIX_VECT182_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT182_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT182_CONTROL +#define PCIEMSIX_VECT182_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT182_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT183_ADDR_LO +#define PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT183_ADDR_HI +#define PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT183_MSG_DATA +#define PCIEMSIX_VECT183_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT183_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT183_CONTROL +#define PCIEMSIX_VECT183_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT183_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT184_ADDR_LO +#define PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT184_ADDR_HI +#define PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT184_MSG_DATA +#define PCIEMSIX_VECT184_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT184_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT184_CONTROL +#define PCIEMSIX_VECT184_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT184_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT185_ADDR_LO +#define PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT185_ADDR_HI +#define PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT185_MSG_DATA +#define PCIEMSIX_VECT185_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT185_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT185_CONTROL +#define PCIEMSIX_VECT185_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT185_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT186_ADDR_LO +#define PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT186_ADDR_HI +#define PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT186_MSG_DATA +#define PCIEMSIX_VECT186_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT186_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT186_CONTROL +#define PCIEMSIX_VECT186_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT186_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT187_ADDR_LO +#define PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT187_ADDR_HI +#define PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT187_MSG_DATA +#define PCIEMSIX_VECT187_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT187_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT187_CONTROL +#define PCIEMSIX_VECT187_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT187_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT188_ADDR_LO +#define PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT188_ADDR_HI +#define PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT188_MSG_DATA +#define PCIEMSIX_VECT188_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT188_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT188_CONTROL +#define PCIEMSIX_VECT188_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT188_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT189_ADDR_LO +#define PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT189_ADDR_HI +#define PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT189_MSG_DATA +#define PCIEMSIX_VECT189_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT189_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT189_CONTROL +#define PCIEMSIX_VECT189_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT189_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT190_ADDR_LO +#define PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT190_ADDR_HI +#define PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT190_MSG_DATA +#define PCIEMSIX_VECT190_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT190_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT190_CONTROL +#define PCIEMSIX_VECT190_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT190_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT191_ADDR_LO +#define PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT191_ADDR_HI +#define PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT191_MSG_DATA +#define PCIEMSIX_VECT191_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT191_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT191_CONTROL +#define PCIEMSIX_VECT191_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT191_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT192_ADDR_LO +#define PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT192_ADDR_HI +#define PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT192_MSG_DATA +#define PCIEMSIX_VECT192_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT192_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT192_CONTROL +#define PCIEMSIX_VECT192_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT192_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT193_ADDR_LO +#define PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT193_ADDR_HI +#define PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT193_MSG_DATA +#define PCIEMSIX_VECT193_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT193_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT193_CONTROL +#define PCIEMSIX_VECT193_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT193_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT194_ADDR_LO +#define PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT194_ADDR_HI +#define PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT194_MSG_DATA +#define PCIEMSIX_VECT194_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT194_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT194_CONTROL +#define PCIEMSIX_VECT194_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT194_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT195_ADDR_LO +#define PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT195_ADDR_HI +#define PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT195_MSG_DATA +#define PCIEMSIX_VECT195_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT195_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT195_CONTROL +#define PCIEMSIX_VECT195_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT195_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT196_ADDR_LO +#define PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT196_ADDR_HI +#define PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT196_MSG_DATA +#define PCIEMSIX_VECT196_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT196_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT196_CONTROL +#define PCIEMSIX_VECT196_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT196_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT197_ADDR_LO +#define PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT197_ADDR_HI +#define PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT197_MSG_DATA +#define PCIEMSIX_VECT197_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT197_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT197_CONTROL +#define PCIEMSIX_VECT197_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT197_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT198_ADDR_LO +#define PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT198_ADDR_HI +#define PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT198_MSG_DATA +#define PCIEMSIX_VECT198_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT198_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT198_CONTROL +#define PCIEMSIX_VECT198_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT198_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT199_ADDR_LO +#define PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT199_ADDR_HI +#define PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT199_MSG_DATA +#define PCIEMSIX_VECT199_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT199_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT199_CONTROL +#define PCIEMSIX_VECT199_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT199_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT200_ADDR_LO +#define PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT200_ADDR_HI +#define PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT200_MSG_DATA +#define PCIEMSIX_VECT200_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT200_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT200_CONTROL +#define PCIEMSIX_VECT200_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT200_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT201_ADDR_LO +#define PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT201_ADDR_HI +#define PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT201_MSG_DATA +#define PCIEMSIX_VECT201_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT201_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT201_CONTROL +#define PCIEMSIX_VECT201_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT201_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT202_ADDR_LO +#define PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT202_ADDR_HI +#define PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT202_MSG_DATA +#define PCIEMSIX_VECT202_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT202_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT202_CONTROL +#define PCIEMSIX_VECT202_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT202_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT203_ADDR_LO +#define PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT203_ADDR_HI +#define PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT203_MSG_DATA +#define PCIEMSIX_VECT203_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT203_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT203_CONTROL +#define PCIEMSIX_VECT203_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT203_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT204_ADDR_LO +#define PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT204_ADDR_HI +#define PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT204_MSG_DATA +#define PCIEMSIX_VECT204_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT204_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT204_CONTROL +#define PCIEMSIX_VECT204_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT204_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT205_ADDR_LO +#define PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT205_ADDR_HI +#define PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT205_MSG_DATA +#define PCIEMSIX_VECT205_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT205_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT205_CONTROL +#define PCIEMSIX_VECT205_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT205_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT206_ADDR_LO +#define PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT206_ADDR_HI +#define PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT206_MSG_DATA +#define PCIEMSIX_VECT206_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT206_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT206_CONTROL +#define PCIEMSIX_VECT206_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT206_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT207_ADDR_LO +#define PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT207_ADDR_HI +#define PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT207_MSG_DATA +#define PCIEMSIX_VECT207_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT207_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT207_CONTROL +#define PCIEMSIX_VECT207_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT207_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT208_ADDR_LO +#define PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT208_ADDR_HI +#define PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT208_MSG_DATA +#define PCIEMSIX_VECT208_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT208_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT208_CONTROL +#define PCIEMSIX_VECT208_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT208_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT209_ADDR_LO +#define PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT209_ADDR_HI +#define PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT209_MSG_DATA +#define PCIEMSIX_VECT209_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT209_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT209_CONTROL +#define PCIEMSIX_VECT209_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT209_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT210_ADDR_LO +#define PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT210_ADDR_HI +#define PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT210_MSG_DATA +#define PCIEMSIX_VECT210_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT210_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT210_CONTROL +#define PCIEMSIX_VECT210_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT210_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT211_ADDR_LO +#define PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT211_ADDR_HI +#define PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT211_MSG_DATA +#define PCIEMSIX_VECT211_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT211_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT211_CONTROL +#define PCIEMSIX_VECT211_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT211_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT212_ADDR_LO +#define PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT212_ADDR_HI +#define PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT212_MSG_DATA +#define PCIEMSIX_VECT212_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT212_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT212_CONTROL +#define PCIEMSIX_VECT212_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT212_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT213_ADDR_LO +#define PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT213_ADDR_HI +#define PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT213_MSG_DATA +#define PCIEMSIX_VECT213_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT213_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT213_CONTROL +#define PCIEMSIX_VECT213_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT213_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT214_ADDR_LO +#define PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT214_ADDR_HI +#define PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT214_MSG_DATA +#define PCIEMSIX_VECT214_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT214_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT214_CONTROL +#define PCIEMSIX_VECT214_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT214_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT215_ADDR_LO +#define PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT215_ADDR_HI +#define PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT215_MSG_DATA +#define PCIEMSIX_VECT215_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT215_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT215_CONTROL +#define PCIEMSIX_VECT215_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT215_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT216_ADDR_LO +#define PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT216_ADDR_HI +#define PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT216_MSG_DATA +#define PCIEMSIX_VECT216_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT216_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT216_CONTROL +#define PCIEMSIX_VECT216_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT216_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT217_ADDR_LO +#define PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT217_ADDR_HI +#define PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT217_MSG_DATA +#define PCIEMSIX_VECT217_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT217_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT217_CONTROL +#define PCIEMSIX_VECT217_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT217_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT218_ADDR_LO +#define PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT218_ADDR_HI +#define PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT218_MSG_DATA +#define PCIEMSIX_VECT218_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT218_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT218_CONTROL +#define PCIEMSIX_VECT218_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT218_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT219_ADDR_LO +#define PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT219_ADDR_HI +#define PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT219_MSG_DATA +#define PCIEMSIX_VECT219_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT219_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT219_CONTROL +#define PCIEMSIX_VECT219_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT219_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT220_ADDR_LO +#define PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT220_ADDR_HI +#define PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT220_MSG_DATA +#define PCIEMSIX_VECT220_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT220_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT220_CONTROL +#define PCIEMSIX_VECT220_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT220_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT221_ADDR_LO +#define PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT221_ADDR_HI +#define PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT221_MSG_DATA +#define PCIEMSIX_VECT221_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT221_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT221_CONTROL +#define PCIEMSIX_VECT221_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT221_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT222_ADDR_LO +#define PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT222_ADDR_HI +#define PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT222_MSG_DATA +#define PCIEMSIX_VECT222_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT222_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT222_CONTROL +#define PCIEMSIX_VECT222_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT222_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT223_ADDR_LO +#define PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT223_ADDR_HI +#define PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT223_MSG_DATA +#define PCIEMSIX_VECT223_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT223_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT223_CONTROL +#define PCIEMSIX_VECT223_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT223_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT224_ADDR_LO +#define PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT224_ADDR_HI +#define PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT224_MSG_DATA +#define PCIEMSIX_VECT224_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT224_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT224_CONTROL +#define PCIEMSIX_VECT224_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT224_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT225_ADDR_LO +#define PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT225_ADDR_HI +#define PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT225_MSG_DATA +#define PCIEMSIX_VECT225_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT225_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT225_CONTROL +#define PCIEMSIX_VECT225_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT225_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT226_ADDR_LO +#define PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT226_ADDR_HI +#define PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT226_MSG_DATA +#define PCIEMSIX_VECT226_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT226_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT226_CONTROL +#define PCIEMSIX_VECT226_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT226_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT227_ADDR_LO +#define PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT227_ADDR_HI +#define PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT227_MSG_DATA +#define PCIEMSIX_VECT227_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT227_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT227_CONTROL +#define PCIEMSIX_VECT227_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT227_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT228_ADDR_LO +#define PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT228_ADDR_HI +#define PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT228_MSG_DATA +#define PCIEMSIX_VECT228_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT228_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT228_CONTROL +#define PCIEMSIX_VECT228_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT228_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT229_ADDR_LO +#define PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT229_ADDR_HI +#define PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT229_MSG_DATA +#define PCIEMSIX_VECT229_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT229_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT229_CONTROL +#define PCIEMSIX_VECT229_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT229_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT230_ADDR_LO +#define PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT230_ADDR_HI +#define PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT230_MSG_DATA +#define PCIEMSIX_VECT230_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT230_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT230_CONTROL +#define PCIEMSIX_VECT230_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT230_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT231_ADDR_LO +#define PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT231_ADDR_HI +#define PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT231_MSG_DATA +#define PCIEMSIX_VECT231_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT231_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT231_CONTROL +#define PCIEMSIX_VECT231_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT231_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT232_ADDR_LO +#define PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT232_ADDR_HI +#define PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT232_MSG_DATA +#define PCIEMSIX_VECT232_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT232_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT232_CONTROL +#define PCIEMSIX_VECT232_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT232_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT233_ADDR_LO +#define PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT233_ADDR_HI +#define PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT233_MSG_DATA +#define PCIEMSIX_VECT233_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT233_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT233_CONTROL +#define PCIEMSIX_VECT233_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT233_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT234_ADDR_LO +#define PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT234_ADDR_HI +#define PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT234_MSG_DATA +#define PCIEMSIX_VECT234_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT234_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT234_CONTROL +#define PCIEMSIX_VECT234_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT234_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT235_ADDR_LO +#define PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT235_ADDR_HI +#define PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT235_MSG_DATA +#define PCIEMSIX_VECT235_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT235_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT235_CONTROL +#define PCIEMSIX_VECT235_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT235_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT236_ADDR_LO +#define PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT236_ADDR_HI +#define PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT236_MSG_DATA +#define PCIEMSIX_VECT236_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT236_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT236_CONTROL +#define PCIEMSIX_VECT236_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT236_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT237_ADDR_LO +#define PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT237_ADDR_HI +#define PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT237_MSG_DATA +#define PCIEMSIX_VECT237_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT237_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT237_CONTROL +#define PCIEMSIX_VECT237_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT237_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT238_ADDR_LO +#define PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT238_ADDR_HI +#define PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT238_MSG_DATA +#define PCIEMSIX_VECT238_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT238_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT238_CONTROL +#define PCIEMSIX_VECT238_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT238_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT239_ADDR_LO +#define PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT239_ADDR_HI +#define PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT239_MSG_DATA +#define PCIEMSIX_VECT239_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT239_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT239_CONTROL +#define PCIEMSIX_VECT239_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT239_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT240_ADDR_LO +#define PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT240_ADDR_HI +#define PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT240_MSG_DATA +#define PCIEMSIX_VECT240_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT240_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT240_CONTROL +#define PCIEMSIX_VECT240_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT240_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT241_ADDR_LO +#define PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT241_ADDR_HI +#define PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT241_MSG_DATA +#define PCIEMSIX_VECT241_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT241_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT241_CONTROL +#define PCIEMSIX_VECT241_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT241_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT242_ADDR_LO +#define PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT242_ADDR_HI +#define PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT242_MSG_DATA +#define PCIEMSIX_VECT242_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT242_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT242_CONTROL +#define PCIEMSIX_VECT242_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT242_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT243_ADDR_LO +#define PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT243_ADDR_HI +#define PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT243_MSG_DATA +#define PCIEMSIX_VECT243_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT243_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT243_CONTROL +#define PCIEMSIX_VECT243_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT243_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT244_ADDR_LO +#define PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT244_ADDR_HI +#define PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT244_MSG_DATA +#define PCIEMSIX_VECT244_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT244_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT244_CONTROL +#define PCIEMSIX_VECT244_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT244_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT245_ADDR_LO +#define PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT245_ADDR_HI +#define PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT245_MSG_DATA +#define PCIEMSIX_VECT245_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT245_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT245_CONTROL +#define PCIEMSIX_VECT245_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT245_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT246_ADDR_LO +#define PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT246_ADDR_HI +#define PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT246_MSG_DATA +#define PCIEMSIX_VECT246_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT246_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT246_CONTROL +#define PCIEMSIX_VECT246_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT246_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT247_ADDR_LO +#define PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT247_ADDR_HI +#define PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT247_MSG_DATA +#define PCIEMSIX_VECT247_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT247_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT247_CONTROL +#define PCIEMSIX_VECT247_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT247_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT248_ADDR_LO +#define PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT248_ADDR_HI +#define PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT248_MSG_DATA +#define PCIEMSIX_VECT248_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT248_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT248_CONTROL +#define PCIEMSIX_VECT248_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT248_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT249_ADDR_LO +#define PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT249_ADDR_HI +#define PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT249_MSG_DATA +#define PCIEMSIX_VECT249_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT249_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT249_CONTROL +#define PCIEMSIX_VECT249_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT249_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT250_ADDR_LO +#define PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT250_ADDR_HI +#define PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT250_MSG_DATA +#define PCIEMSIX_VECT250_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT250_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT250_CONTROL +#define PCIEMSIX_VECT250_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT250_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT251_ADDR_LO +#define PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT251_ADDR_HI +#define PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT251_MSG_DATA +#define PCIEMSIX_VECT251_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT251_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT251_CONTROL +#define PCIEMSIX_VECT251_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT251_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT252_ADDR_LO +#define PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT252_ADDR_HI +#define PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT252_MSG_DATA +#define PCIEMSIX_VECT252_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT252_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT252_CONTROL +#define PCIEMSIX_VECT252_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT252_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT253_ADDR_LO +#define PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT253_ADDR_HI +#define PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT253_MSG_DATA +#define PCIEMSIX_VECT253_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT253_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT253_CONTROL +#define PCIEMSIX_VECT253_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT253_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT254_ADDR_LO +#define PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT254_ADDR_HI +#define PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT254_MSG_DATA +#define PCIEMSIX_VECT254_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT254_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT254_CONTROL +#define PCIEMSIX_VECT254_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT254_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT255_ADDR_LO +#define PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT255_ADDR_HI +#define PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT255_MSG_DATA +#define PCIEMSIX_VECT255_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT255_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT255_CONTROL +#define PCIEMSIX_VECT255_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT255_CONTROL__MASK_BIT_MASK 0x00000001L + + +// addressBlock: aid_nbio_nbif0_pciemsix_0_usb_MSIXPDEC +//PCIEMSIX_PBA_0 +#define PCIEMSIX_PBA_0__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_0__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL +//PCIEMSIX_PBA_1 +#define PCIEMSIX_PBA_1__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_1__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL +//PCIEMSIX_PBA_2 +#define PCIEMSIX_PBA_2__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_2__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL +//PCIEMSIX_PBA_3 +#define PCIEMSIX_PBA_3__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_3__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL +//PCIEMSIX_PBA_4 +#define PCIEMSIX_PBA_4__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_4__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL +//PCIEMSIX_PBA_5 +#define PCIEMSIX_PBA_5__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_5__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL +//PCIEMSIX_PBA_6 +#define PCIEMSIX_PBA_6__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_6__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL +//PCIEMSIX_PBA_7 +#define PCIEMSIX_PBA_7__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_7__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_bif_swus_SUMDEC +//SUM_INDEX +#define SUM_INDEX__SUM_INDEX__SHIFT 0x0 +#define SUM_INDEX__SUM_INDEX_MASK 0xFFFFFFFFL +//SUM_DATA +#define SUM_DATA__SUM_DATA__SHIFT 0x0 +#define SUM_DATA__SUM_DATA_MASK 0xFFFFFFFFL +//SUM_INDEX_HI +#define SUM_INDEX_HI__SUM_INDEX_HI__SHIFT 0x0 +#define SUM_INDEX_HI__SUM_INDEX_HI_MASK 0x000000FFL + + +// addressBlock: aid_nbio_nbif0_rcc_strap_rcc_strap_internal +//RCC_STRAP1_RCC_DEV0_PORT_STRAP0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x00E00000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x0F000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0xF0000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT 0x5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK 0x00000020L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK 0x0007FFC0L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP11 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK 0x0FFF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK 0x40000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK 0x00FFFFFFL +//RCC_STRAP1_RCC_DEV0_PORT_STRAP13 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK 0x000FFE00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK 0xFFF00000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK 0x00000010L +//RCC_DEV1_PORT_STRAP0 +//RCC_DEV1_PORT_STRAP1 +//RCC_DEV1_PORT_STRAP2 +//RCC_DEV1_PORT_STRAP3 +//RCC_DEV1_PORT_STRAP4 +//RCC_DEV1_PORT_STRAP5 +//RCC_DEV1_PORT_STRAP6 +//RCC_DEV1_PORT_STRAP7 +//RCC_DEV1_PORT_STRAP8 +//RCC_DEV1_PORT_STRAP9 +//RCC_DEV1_PORT_STRAP10 +//RCC_DEV1_PORT_STRAP11 +//RCC_DEV1_PORT_STRAP12 +//RCC_DEV1_PORT_STRAP13 +//RCC_DEV1_PORT_STRAP14 +//RCC_DEV2_PORT_STRAP0 +//RCC_DEV2_PORT_STRAP1 +//RCC_DEV2_PORT_STRAP2 +//RCC_DEV2_PORT_STRAP3 +//RCC_DEV2_PORT_STRAP4 +//RCC_DEV2_PORT_STRAP5 +//RCC_DEV2_PORT_STRAP6 +//RCC_DEV2_PORT_STRAP7 +//RCC_DEV2_PORT_STRAP8 +//RCC_DEV2_PORT_STRAP9 +//RCC_DEV2_PORT_STRAP10 +//RCC_DEV2_PORT_STRAP11 +//RCC_DEV2_PORT_STRAP12 +//RCC_DEV2_PORT_STRAP13 +//RCC_DEV2_PORT_STRAP14 +//RCC_STRAP1_RCC_BIF_STRAP0 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT 0x1 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x6 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT 0x1c +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK 0x00000001L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK 0x00000002L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000038L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00000040L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK 0x10000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L +//RCC_STRAP1_RCC_BIF_STRAP1 +#define RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1 +#define RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x2 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT 0x18 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT 0x19 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT 0x1e +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT 0x1f +#define RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L +#define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L +#define RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK 0x01000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK 0x02000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_MASK 0x40000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK 0x80000000L +//RCC_STRAP1_RCC_BIF_STRAP2 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN__SHIFT 0x7 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa +#define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN_MASK 0x00000080L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L +#define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L +//RCC_STRAP1_RCC_BIF_STRAP3 +#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_BIF_STRAP4 +#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_BIF_STRAP5 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT 0x15 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK 0x00200000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L +//RCC_STRAP1_RCC_BIF_STRAP6 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT 0x1 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT 0x2 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK 0x00000001L +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK 0x00000002L +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK 0x00000004L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP1 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP2 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP3 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP4 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT 0xa +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK 0x00000400L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP5 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP8 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00780000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP9 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP13 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0xFF000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK 0x00FFF000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK 0x3E000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK 0x40000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK 0x00FFF000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP17 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT 0xd +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK 0x00001000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK 0x01FFE000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK 0x00000FFFL +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP26 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK 0x00000FFFL +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP2 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK 0x00800000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP3 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP4 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP5 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK 0x38000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP6 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L + + +// addressBlock: aid_nbio_nbif0_bif_rst_bif_rst_regblk +//HARD_RST_CTRL +#define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0 +#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1 +#define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2 +#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3 +#define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4 +#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5 +#define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6 +#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7 +#define HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x9 +#define HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT 0xa +#define HARD_RST_CTRL__STRAP_RST_EN__SHIFT 0x17 +#define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d +#define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e +#define HARD_RST_CTRL__CORE_RST_EN__SHIFT 0x1f +#define HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK 0x00000001L +#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK 0x00000002L +#define HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK 0x00000004L +#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK 0x00000008L +#define HARD_RST_CTRL__EP_CFG_RST_EN_MASK 0x00000010L +#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK 0x00000020L +#define HARD_RST_CTRL__EP_PRV_RST_EN_MASK 0x00000040L +#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK 0x00000080L +#define HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000200L +#define HARD_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000400L +#define HARD_RST_CTRL__STRAP_RST_EN_MASK 0x00800000L +#define HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK 0x20000000L +#define HARD_RST_CTRL__RELOAD_STRAP_EN_MASK 0x40000000L +#define HARD_RST_CTRL__CORE_RST_EN_MASK 0x80000000L +//SELF_SOFT_RST +#define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT 0x0 +#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT 0x1 +#define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT 0x2 +#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT 0x3 +#define SELF_SOFT_RST__EP0_CFG_RST__SHIFT 0x4 +#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT 0x5 +#define SELF_SOFT_RST__EP0_PRV_RST__SHIFT 0x6 +#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT 0x7 +#define SELF_SOFT_RST__HRPU_SDP_PORT_RST__SHIFT 0x18 +#define SELF_SOFT_RST__GSID_SDP_PORT_RST__SHIFT 0x19 +#define SELF_SOFT_RST__GMIU_SDP_PORT_RST__SHIFT 0x1a +#define SELF_SOFT_RST__GMID_SDP_PORT_RST__SHIFT 0x1b +#define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT 0x1d +#define SELF_SOFT_RST__RELOAD_STRAP__SHIFT 0x1e +#define SELF_SOFT_RST__CORE_RST__SHIFT 0x1f +#define SELF_SOFT_RST__DSPT0_CFG_RST_MASK 0x00000001L +#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK 0x00000002L +#define SELF_SOFT_RST__DSPT0_PRV_RST_MASK 0x00000004L +#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK 0x00000008L +#define SELF_SOFT_RST__EP0_CFG_RST_MASK 0x00000010L +#define SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK 0x00000020L +#define SELF_SOFT_RST__EP0_PRV_RST_MASK 0x00000040L +#define SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK 0x00000080L +#define SELF_SOFT_RST__HRPU_SDP_PORT_RST_MASK 0x01000000L +#define SELF_SOFT_RST__GSID_SDP_PORT_RST_MASK 0x02000000L +#define SELF_SOFT_RST__GMIU_SDP_PORT_RST_MASK 0x04000000L +#define SELF_SOFT_RST__GMID_SDP_PORT_RST_MASK 0x08000000L +#define SELF_SOFT_RST__CORE_STICKY_RST_MASK 0x20000000L +#define SELF_SOFT_RST__RELOAD_STRAP_MASK 0x40000000L +#define SELF_SOFT_RST__CORE_RST_MASK 0x80000000L +//BIF_GFX_DRV_VPU_RST +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT 0x0 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT 0x1 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT 0x2 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT 0x3 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT 0x4 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT 0x5 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT 0x6 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT 0x7 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK 0x00000001L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK 0x00000002L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK 0x00000004L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK 0x00000008L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK 0x00000010L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK 0x00000020L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK 0x00000040L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK 0x00000080L +//BIF_RST_MISC_CTRL +#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT 0x0 +#define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT 0x2 +#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT 0x4 +#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT 0x5 +#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT 0x6 +#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT 0x8 +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT 0x9 +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT 0xa +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT 0xd +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT 0xf +#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x11 +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT 0x17 +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT 0x18 +#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK 0x00000001L +#define BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK 0x0000000CL +#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK 0x00000010L +#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK 0x00000020L +#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK 0x00000040L +#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK 0x00000100L +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK 0x00000200L +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK 0x00001C00L +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK 0x00006000L +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK 0x00018000L +#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0x000E0000L +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK 0x00800000L +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK 0x03000000L +//BIF_RST_MISC_CTRL2 +#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_PROTECT__SHIFT 0x0 +#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_PROTECT__SHIFT 0x1 +#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_PROTECT__SHIFT 0x2 +#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT__SHIFT 0xf +#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT 0x10 +#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT 0x11 +#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT 0x12 +#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_DIS__SHIFT 0x1e +#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT 0x1f +#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_PROTECT_MASK 0x00000001L +#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_PROTECT_MASK 0x00000002L +#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_PROTECT_MASK 0x00000004L +#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_MASK 0x00008000L +#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK 0x00010000L +#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK 0x00020000L +#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK 0x00040000L +#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_DIS_MASK 0x40000000L +#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK 0x80000000L +//BIF_RST_MISC_CTRL3 +#define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT 0x0 +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT 0x4 +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT 0x6 +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT 0x7 +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT 0xa +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT 0xd +#define BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK 0x0000000FL +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK 0x00000030L +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK 0x00000040L +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK 0x00000380L +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK 0x00001C00L +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK 0x0000E000L +//DEV0_PF0_FLR_RST_CTRL +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT 0x5 +#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT 0x6 +#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT 0x7 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT 0x8 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT 0x9 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT 0xa +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT 0xb +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT 0xc +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT 0xd +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT 0xe +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT 0xf +#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10 +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT 0x1f +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN_MASK 0x00000020L +#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN_MASK 0x00000040L +#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN_MASK 0x00000080L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK 0x00000100L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK 0x00000200L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK 0x00000400L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK 0x00000800L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK 0x00001000L +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN_MASK 0x00002000L +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN_MASK 0x00004000L +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN_MASK 0x00008000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK 0x00010000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK 0x80000000L +//DEV0_PF1_FLR_RST_CTRL +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//BIF_INST_RESET_INTR_STS +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT 0x0 +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x1 +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT 0x2 +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT 0x3 +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT 0x4 +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK 0x00000001L +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000002L +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK 0x00000004L +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK 0x00000008L +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK 0x00000010L +//BIF_PF_FLR_INTR_STS +#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT 0x0 +#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT 0x1 +#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK 0x00000001L +#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK 0x00000002L +//BIF_D3HOTD0_INTR_STS +#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT 0x0 +#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT 0x1 +#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK 0x00000001L +#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK 0x00000002L +//BIF_POWER_INTR_STS +#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT 0x0 +#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT 0x10 +#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK 0x00000001L +#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK 0x00010000L +//BIF_PF_DSTATE_INTR_STS +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT 0x0 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT 0x1 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT 0x2 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT 0x3 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT 0x4 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT 0x5 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT 0x6 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT 0x7 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK 0x00000001L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK 0x00000002L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK 0x00000004L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK 0x00000008L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK 0x00000010L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK 0x00000020L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK 0x00000040L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK 0x00000080L +//SELF_SOFT_RST_2 +#define SELF_SOFT_RST_2__DSPT3_CFG_RST__SHIFT 0x0 +#define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST__SHIFT 0x1 +#define SELF_SOFT_RST_2__DSPT3_PRV_RST__SHIFT 0x2 +#define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST__SHIFT 0x3 +#define SELF_SOFT_RST_2__EP3_CFG_RST__SHIFT 0x4 +#define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST__SHIFT 0x5 +#define SELF_SOFT_RST_2__EP3_PRV_RST__SHIFT 0x6 +#define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST__SHIFT 0x7 +#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST__SHIFT 0x18 +#define SELF_SOFT_RST_2__STRAP_RST__SHIFT 0x19 +#define SELF_SOFT_RST_2__DSPT3_CFG_RST_MASK 0x00000001L +#define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST_MASK 0x00000002L +#define SELF_SOFT_RST_2__DSPT3_PRV_RST_MASK 0x00000004L +#define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST_MASK 0x00000008L +#define SELF_SOFT_RST_2__EP3_CFG_RST_MASK 0x00000010L +#define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST_MASK 0x00000020L +#define SELF_SOFT_RST_2__EP3_PRV_RST_MASK 0x00000040L +#define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST_MASK 0x00000080L +#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST_MASK 0x01000000L +#define SELF_SOFT_RST_2__STRAP_RST_MASK 0x02000000L +//BIF_INST_RESET_INTR_MASK +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT 0x0 +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x1 +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT 0x2 +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT 0x3 +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT 0x4 +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK 0x00000001L +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000002L +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK 0x00000004L +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK 0x00000008L +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK 0x00000010L +//BIF_PF_FLR_INTR_MASK +#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT 0x0 +#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT 0x1 +#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK 0x00000001L +#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK 0x00000002L +//BIF_D3HOTD0_INTR_MASK +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT 0x0 +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT 0x1 +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK 0x00000001L +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK 0x00000002L +//BIF_POWER_INTR_MASK +#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT 0x0 +#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT 0x10 +#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK 0x00000001L +#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK 0x00010000L +//BIF_PF_DSTATE_INTR_MASK +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT 0x0 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT 0x1 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT 0x2 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT 0x3 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT 0x4 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT 0x5 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT 0x6 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT 0x7 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK 0x00000001L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK 0x00000002L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK 0x00000004L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK 0x00000008L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK 0x00000010L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK 0x00000020L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK 0x00000040L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK 0x00000080L +//BIF_PF_FLR_RST +#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0 +#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1 +#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L +#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L +//BIF_DEV0_PF0_DSTATE_VALUE +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV0_PF1_DSTATE_VALUE +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L +//DEV0_PF0_D3HOTD0_RST_CTRL +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV0_PF1_D3HOTD0_RST_CTRL +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//BIF_PORT0_DSTATE_VALUE +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK 0x00030000L + + +// addressBlock: aid_nbio_nbif0_bif_misc_bif_misc_regblk +//REGS_ROM_OFFSET_CTRL +#define REGS_ROM_OFFSET_CTRL__ROM_OFFSET__SHIFT 0x0 +#define REGS_ROM_OFFSET_CTRL__ROM_OFFSET_MASK 0x7FL +//NBIF_STRAP_BIOS_CNTL +#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN__SHIFT 0x0 +#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN__SHIFT 0x1 +#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN_MASK 0x00000001L +#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN_MASK 0x00000002L +//DOORBELL0_CTRL_ENTRY_0 +#define DOORBELL0_CTRL_ENTRY_0__BIF_DOORBELL0_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_0__BIF_DOORBELL0_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_0__DOORBELL0_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_0__BIF_DOORBELL0_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_0__BIF_DOORBELL0_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_0__DOORBELL0_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_1 +#define DOORBELL0_CTRL_ENTRY_1__BIF_DOORBELL1_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_1__BIF_DOORBELL1_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_1__DOORBELL1_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_1__BIF_DOORBELL1_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_1__BIF_DOORBELL1_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_1__DOORBELL1_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_2 +#define DOORBELL0_CTRL_ENTRY_2__BIF_DOORBELL2_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_2__BIF_DOORBELL2_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_2__DOORBELL2_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_2__BIF_DOORBELL2_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_2__BIF_DOORBELL2_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_2__DOORBELL2_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_3 +#define DOORBELL0_CTRL_ENTRY_3__BIF_DOORBELL3_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_3__BIF_DOORBELL3_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_3__DOORBELL3_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_3__BIF_DOORBELL3_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_3__BIF_DOORBELL3_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_3__DOORBELL3_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_4 +#define DOORBELL0_CTRL_ENTRY_4__BIF_DOORBELL4_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_4__BIF_DOORBELL4_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_4__DOORBELL4_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_4__BIF_DOORBELL4_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_4__BIF_DOORBELL4_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_4__DOORBELL4_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_5 +#define DOORBELL0_CTRL_ENTRY_5__BIF_DOORBELL5_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_5__BIF_DOORBELL5_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_5__DOORBELL5_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_5__BIF_DOORBELL5_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_5__BIF_DOORBELL5_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_5__DOORBELL5_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_6 +#define DOORBELL0_CTRL_ENTRY_6__BIF_DOORBELL6_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_6__BIF_DOORBELL6_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_6__DOORBELL6_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_6__BIF_DOORBELL6_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_6__BIF_DOORBELL6_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_6__DOORBELL6_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_7 +#define DOORBELL0_CTRL_ENTRY_7__BIF_DOORBELL7_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_7__BIF_DOORBELL7_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_7__DOORBELL7_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_7__BIF_DOORBELL7_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_7__BIF_DOORBELL7_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_7__DOORBELL7_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_8 +#define DOORBELL0_CTRL_ENTRY_8__BIF_DOORBELL8_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_8__BIF_DOORBELL8_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_8__DOORBELL8_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_8__BIF_DOORBELL8_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_8__BIF_DOORBELL8_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_8__DOORBELL8_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_9 +#define DOORBELL0_CTRL_ENTRY_9__BIF_DOORBELL9_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_9__BIF_DOORBELL9_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_9__DOORBELL9_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_9__BIF_DOORBELL9_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_9__BIF_DOORBELL9_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_9__DOORBELL9_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_10 +#define DOORBELL0_CTRL_ENTRY_10__BIF_DOORBELL10_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_10__BIF_DOORBELL10_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_10__DOORBELL10_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_10__BIF_DOORBELL10_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_10__BIF_DOORBELL10_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_10__DOORBELL10_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_11 +#define DOORBELL0_CTRL_ENTRY_11__BIF_DOORBELL11_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_11__BIF_DOORBELL11_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_11__DOORBELL11_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_11__BIF_DOORBELL11_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_11__BIF_DOORBELL11_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_11__DOORBELL11_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_12 +#define DOORBELL0_CTRL_ENTRY_12__BIF_DOORBELL12_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_12__BIF_DOORBELL12_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_12__DOORBELL12_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_12__BIF_DOORBELL12_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_12__BIF_DOORBELL12_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_12__DOORBELL12_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_13 +#define DOORBELL0_CTRL_ENTRY_13__BIF_DOORBELL13_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_13__BIF_DOORBELL13_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_13__DOORBELL13_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_13__BIF_DOORBELL13_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_13__BIF_DOORBELL13_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_13__DOORBELL13_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_14 +#define DOORBELL0_CTRL_ENTRY_14__BIF_DOORBELL14_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_14__BIF_DOORBELL14_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_14__DOORBELL14_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_14__BIF_DOORBELL14_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_14__BIF_DOORBELL14_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_14__DOORBELL14_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_15 +#define DOORBELL0_CTRL_ENTRY_15__BIF_DOORBELL15_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_15__BIF_DOORBELL15_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_15__DOORBELL15_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_15__BIF_DOORBELL15_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_15__BIF_DOORBELL15_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_15__DOORBELL15_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_16 +#define DOORBELL0_CTRL_ENTRY_16__BIF_DOORBELL16_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_16__BIF_DOORBELL16_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_16__DOORBELL16_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_16__BIF_DOORBELL16_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_16__BIF_DOORBELL16_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_16__DOORBELL16_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_17 +#define DOORBELL0_CTRL_ENTRY_17__BIF_DOORBELL17_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_17__BIF_DOORBELL17_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_17__DOORBELL17_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_17__BIF_DOORBELL17_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_17__BIF_DOORBELL17_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_17__DOORBELL17_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_18 +#define DOORBELL0_CTRL_ENTRY_18__BIF_DOORBELL18_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_18__BIF_DOORBELL18_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_18__DOORBELL18_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_18__BIF_DOORBELL18_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_18__BIF_DOORBELL18_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_18__DOORBELL18_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_19 +#define DOORBELL0_CTRL_ENTRY_19__BIF_DOORBELL19_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_19__BIF_DOORBELL19_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_19__DOORBELL19_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_19__BIF_DOORBELL19_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_19__BIF_DOORBELL19_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_19__DOORBELL19_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_20 +#define DOORBELL0_CTRL_ENTRY_20__BIF_DOORBELL20_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_20__BIF_DOORBELL20_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_20__DOORBELL20_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_20__BIF_DOORBELL20_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_20__BIF_DOORBELL20_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_20__DOORBELL20_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//AID0_VF0_BASE_ADDR +#define AID0_VF0_BASE_ADDR__AID0_VF0_BASE_ADDR__SHIFT 0x0 +#define AID0_VF0_BASE_ADDR__AID0_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID1_VF0_BASE_ADDR +#define AID1_VF0_BASE_ADDR__AID1_VF0_BASE_ADDR__SHIFT 0x0 +#define AID1_VF0_BASE_ADDR__AID1_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID2_VF0_BASE_ADDR +#define AID2_VF0_BASE_ADDR__AID2_VF0_BASE_ADDR__SHIFT 0x0 +#define AID2_VF0_BASE_ADDR__AID2_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID3_VF0_BASE_ADDR +#define AID3_VF0_BASE_ADDR__AID3_VF0_BASE_ADDR__SHIFT 0x0 +#define AID3_VF0_BASE_ADDR__AID3_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID0_XCC0_VF0_BASE_ADDR +#define AID0_XCC0_VF0_BASE_ADDR__AID0_XCC0_VF0_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC0_VF0_BASE_ADDR__AID0_XCC0_VF0_BASE_ADDR_MASK 0x0001FFFFL +//AID0_XCC1_VF0_BASE_ADDR +#define AID0_XCC1_VF0_BASE_ADDR__AID0_XCC1_VF0_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC1_VF0_BASE_ADDR__AID0_XCC1_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC0_VF0_BASE_ADDR +#define AID1_XCC0_VF0_BASE_ADDR__AID1_XCC0_VF0_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC0_VF0_BASE_ADDR__AID1_XCC0_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC1_VF0_BASE_ADDR +#define AID1_XCC1_VF0_BASE_ADDR__AID1_XCC1_VF0_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC1_VF0_BASE_ADDR__AID1_XCC1_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC0_VF0_BASE_ADDR +#define AID2_XCC0_VF0_BASE_ADDR__AID2_XCC0_VF0_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC0_VF0_BASE_ADDR__AID2_XCC0_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC1_VF0_BASE_ADDR +#define AID2_XCC1_VF0_BASE_ADDR__AID2_XCC1_VF0_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC1_VF0_BASE_ADDR__AID2_XCC1_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC0_VF0_BASE_ADDR +#define AID3_XCC0_VF0_BASE_ADDR__AID3_XCC0_VF0_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC0_VF0_BASE_ADDR__AID3_XCC0_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC1_VF0_BASE_ADDR +#define AID3_XCC1_VF0_BASE_ADDR__AID3_XCC1_VF0_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC1_VF0_BASE_ADDR__AID3_XCC1_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID0_NBIF_VF0_BASE_ADDR +#define AID0_NBIF_VF0_BASE_ADDR__AID0_NBIF_VF0_BASE_ADDR__SHIFT 0x0 +#define AID0_NBIF_VF0_BASE_ADDR__AID0_NBIF_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID0_ATHUB_VF0_BASE_ADDR +#define AID0_ATHUB_VF0_BASE_ADDR__AID0_ATHUB_VF0_BASE_ADDR__SHIFT 0x0 +#define AID0_ATHUB_VF0_BASE_ADDR__AID0_ATHUB_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID0_IH_VF0_BASE_ADDR +#define AID0_IH_VF0_BASE_ADDR__AID0_IH_VF0_BASE_ADDR__SHIFT 0x0 +#define AID0_IH_VF0_BASE_ADDR__AID0_IH_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID0_HDP_VF0_BASE_ADDR +#define AID0_HDP_VF0_BASE_ADDR__AID0_HDP_VF0_BASE_ADDR__SHIFT 0x0 +#define AID0_HDP_VF0_BASE_ADDR__AID0_HDP_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID0_VF1_BASE_ADDR +#define AID0_VF1_BASE_ADDR__AID0_VF1_BASE_ADDR__SHIFT 0x0 +#define AID0_VF1_BASE_ADDR__AID0_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID1_VF1_BASE_ADDR +#define AID1_VF1_BASE_ADDR__AID1_VF1_BASE_ADDR__SHIFT 0x0 +#define AID1_VF1_BASE_ADDR__AID1_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID2_VF1_BASE_ADDR +#define AID2_VF1_BASE_ADDR__AID2_VF1_BASE_ADDR__SHIFT 0x0 +#define AID2_VF1_BASE_ADDR__AID2_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID3_VF1_BASE_ADDR +#define AID3_VF1_BASE_ADDR__AID3_VF1_BASE_ADDR__SHIFT 0x0 +#define AID3_VF1_BASE_ADDR__AID3_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID0_XCC0_VF1_BASE_ADDR +#define AID0_XCC0_VF1_BASE_ADDR__AID0_XCC0_VF1_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC0_VF1_BASE_ADDR__AID0_XCC0_VF1_BASE_ADDR_MASK 0x0001FFFFL +//AID0_XCC1_VF1_BASE_ADDR +#define AID0_XCC1_VF1_BASE_ADDR__AID0_XCC1_VF1_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC1_VF1_BASE_ADDR__AID0_XCC1_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC0_VF1_BASE_ADDR +#define AID1_XCC0_VF1_BASE_ADDR__AID1_XCC0_VF1_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC0_VF1_BASE_ADDR__AID1_XCC0_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC1_VF1_BASE_ADDR +#define AID1_XCC1_VF1_BASE_ADDR__AID1_XCC1_VF1_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC1_VF1_BASE_ADDR__AID1_XCC1_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC0_VF1_BASE_ADDR +#define AID2_XCC0_VF1_BASE_ADDR__AID2_XCC0_VF1_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC0_VF1_BASE_ADDR__AID2_XCC0_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC1_VF1_BASE_ADDR +#define AID2_XCC1_VF1_BASE_ADDR__AID2_XCC1_VF1_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC1_VF1_BASE_ADDR__AID2_XCC1_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC0_VF1_BASE_ADDR +#define AID3_XCC0_VF1_BASE_ADDR__AID3_XCC0_VF1_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC0_VF1_BASE_ADDR__AID3_XCC0_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC1_VF1_BASE_ADDR +#define AID3_XCC1_VF1_BASE_ADDR__AID3_XCC1_VF1_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC1_VF1_BASE_ADDR__AID3_XCC1_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID0_NBIF_VF1_BASE_ADDR +#define AID0_NBIF_VF1_BASE_ADDR__AID0_NBIF_VF1_BASE_ADDR__SHIFT 0x0 +#define AID0_NBIF_VF1_BASE_ADDR__AID0_NBIF_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID0_ATHUB_VF1_BASE_ADDR +#define AID0_ATHUB_VF1_BASE_ADDR__AID0_ATHUB_VF1_BASE_ADDR__SHIFT 0x0 +#define AID0_ATHUB_VF1_BASE_ADDR__AID0_ATHUB_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID0_IH_VF1_BASE_ADDR +#define AID0_IH_VF1_BASE_ADDR__AID0_IH_VF1_BASE_ADDR__SHIFT 0x0 +#define AID0_IH_VF1_BASE_ADDR__AID0_IH_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID0_HDP_VF1_BASE_ADDR +#define AID0_HDP_VF1_BASE_ADDR__AID0_HDP_VF1_BASE_ADDR__SHIFT 0x0 +#define AID0_HDP_VF1_BASE_ADDR__AID0_HDP_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID0_VF2_BASE_ADDR +#define AID0_VF2_BASE_ADDR__AID0_VF2_BASE_ADDR__SHIFT 0x0 +#define AID0_VF2_BASE_ADDR__AID0_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID1_VF2_BASE_ADDR +#define AID1_VF2_BASE_ADDR__AID1_VF2_BASE_ADDR__SHIFT 0x0 +#define AID1_VF2_BASE_ADDR__AID1_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID2_VF2_BASE_ADDR +#define AID2_VF2_BASE_ADDR__AID2_VF2_BASE_ADDR__SHIFT 0x0 +#define AID2_VF2_BASE_ADDR__AID2_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID3_VF2_BASE_ADDR +#define AID3_VF2_BASE_ADDR__AID3_VF2_BASE_ADDR__SHIFT 0x0 +#define AID3_VF2_BASE_ADDR__AID3_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID0_XCC0_VF2_BASE_ADDR +#define AID0_XCC0_VF2_BASE_ADDR__AID0_XCC0_VF2_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC0_VF2_BASE_ADDR__AID0_XCC0_VF2_BASE_ADDR_MASK 0x0001FFFFL +//AID0_XCC1_VF2_BASE_ADDR +#define AID0_XCC1_VF2_BASE_ADDR__AID0_XCC1_VF2_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC1_VF2_BASE_ADDR__AID0_XCC1_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC0_VF2_BASE_ADDR +#define AID1_XCC0_VF2_BASE_ADDR__AID1_XCC0_VF2_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC0_VF2_BASE_ADDR__AID1_XCC0_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC1_VF2_BASE_ADDR +#define AID1_XCC1_VF2_BASE_ADDR__AID1_XCC1_VF2_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC1_VF2_BASE_ADDR__AID1_XCC1_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC0_VF2_BASE_ADDR +#define AID2_XCC0_VF2_BASE_ADDR__AID2_XCC0_VF2_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC0_VF2_BASE_ADDR__AID2_XCC0_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC1_VF2_BASE_ADDR +#define AID2_XCC1_VF2_BASE_ADDR__AID2_XCC1_VF2_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC1_VF2_BASE_ADDR__AID2_XCC1_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC0_VF2_BASE_ADDR +#define AID3_XCC0_VF2_BASE_ADDR__AID3_XCC0_VF2_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC0_VF2_BASE_ADDR__AID3_XCC0_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC1_VF2_BASE_ADDR +#define AID3_XCC1_VF2_BASE_ADDR__AID3_XCC1_VF2_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC1_VF2_BASE_ADDR__AID3_XCC1_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID0_NBIF_VF2_BASE_ADDR +#define AID0_NBIF_VF2_BASE_ADDR__AID0_NBIF_VF2_BASE_ADDR__SHIFT 0x0 +#define AID0_NBIF_VF2_BASE_ADDR__AID0_NBIF_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID0_ATHUB_VF2_BASE_ADDR +#define AID0_ATHUB_VF2_BASE_ADDR__AID0_ATHUB_VF2_BASE_ADDR__SHIFT 0x0 +#define AID0_ATHUB_VF2_BASE_ADDR__AID0_ATHUB_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID0_IH_VF2_BASE_ADDR +#define AID0_IH_VF2_BASE_ADDR__AID0_IH_VF2_BASE_ADDR__SHIFT 0x0 +#define AID0_IH_VF2_BASE_ADDR__AID0_IH_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID0_HDP_VF2_BASE_ADDR +#define AID0_HDP_VF2_BASE_ADDR__AID0_HDP_VF2_BASE_ADDR__SHIFT 0x0 +#define AID0_HDP_VF2_BASE_ADDR__AID0_HDP_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID0_VF3_BASE_ADDR +#define AID0_VF3_BASE_ADDR__AID0_VF3_BASE_ADDR__SHIFT 0x0 +#define AID0_VF3_BASE_ADDR__AID0_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID1_VF3_BASE_ADDR +#define AID1_VF3_BASE_ADDR__AID1_VF3_BASE_ADDR__SHIFT 0x0 +#define AID1_VF3_BASE_ADDR__AID1_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID2_VF3_BASE_ADDR +#define AID2_VF3_BASE_ADDR__AID2_VF3_BASE_ADDR__SHIFT 0x0 +#define AID2_VF3_BASE_ADDR__AID2_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID3_VF3_BASE_ADDR +#define AID3_VF3_BASE_ADDR__AID3_VF3_BASE_ADDR__SHIFT 0x0 +#define AID3_VF3_BASE_ADDR__AID3_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID0_XCC0_VF3_BASE_ADDR +#define AID0_XCC0_VF3_BASE_ADDR__AID0_XCC0_VF3_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC0_VF3_BASE_ADDR__AID0_XCC0_VF3_BASE_ADDR_MASK 0x0001FFFFL +//AID0_XCC1_VF3_BASE_ADDR +#define AID0_XCC1_VF3_BASE_ADDR__AID0_XCC1_VF3_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC1_VF3_BASE_ADDR__AID0_XCC1_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC0_VF3_BASE_ADDR +#define AID1_XCC0_VF3_BASE_ADDR__AID1_XCC0_VF3_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC0_VF3_BASE_ADDR__AID1_XCC0_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC1_VF3_BASE_ADDR +#define AID1_XCC1_VF3_BASE_ADDR__AID1_XCC1_VF3_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC1_VF3_BASE_ADDR__AID1_XCC1_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC0_VF3_BASE_ADDR +#define AID2_XCC0_VF3_BASE_ADDR__AID2_XCC0_VF3_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC0_VF3_BASE_ADDR__AID2_XCC0_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC1_VF3_BASE_ADDR +#define AID2_XCC1_VF3_BASE_ADDR__AID2_XCC1_VF3_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC1_VF3_BASE_ADDR__AID2_XCC1_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC0_VF3_BASE_ADDR +#define AID3_XCC0_VF3_BASE_ADDR__AID3_XCC0_VF3_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC0_VF3_BASE_ADDR__AID3_XCC0_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC1_VF3_BASE_ADDR +#define AID3_XCC1_VF3_BASE_ADDR__AID3_XCC1_VF3_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC1_VF3_BASE_ADDR__AID3_XCC1_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID0_NBIF_VF3_BASE_ADDR +#define AID0_NBIF_VF3_BASE_ADDR__AID0_NBIF_VF3_BASE_ADDR__SHIFT 0x0 +#define AID0_NBIF_VF3_BASE_ADDR__AID0_NBIF_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID0_ATHUB_VF3_BASE_ADDR +#define AID0_ATHUB_VF3_BASE_ADDR__AID0_ATHUB_VF3_BASE_ADDR__SHIFT 0x0 +#define AID0_ATHUB_VF3_BASE_ADDR__AID0_ATHUB_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID0_IH_VF3_BASE_ADDR +#define AID0_IH_VF3_BASE_ADDR__AID0_IH_VF3_BASE_ADDR__SHIFT 0x0 +#define AID0_IH_VF3_BASE_ADDR__AID0_IH_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID0_HDP_VF3_BASE_ADDR +#define AID0_HDP_VF3_BASE_ADDR__AID0_HDP_VF3_BASE_ADDR__SHIFT 0x0 +#define AID0_HDP_VF3_BASE_ADDR__AID0_HDP_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID0_VF4_BASE_ADDR +#define AID0_VF4_BASE_ADDR__AID0_VF4_BASE_ADDR__SHIFT 0x0 +#define AID0_VF4_BASE_ADDR__AID0_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID1_VF4_BASE_ADDR +#define AID1_VF4_BASE_ADDR__AID1_VF4_BASE_ADDR__SHIFT 0x0 +#define AID1_VF4_BASE_ADDR__AID1_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID2_VF4_BASE_ADDR +#define AID2_VF4_BASE_ADDR__AID2_VF4_BASE_ADDR__SHIFT 0x0 +#define AID2_VF4_BASE_ADDR__AID2_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID3_VF4_BASE_ADDR +#define AID3_VF4_BASE_ADDR__AID3_VF4_BASE_ADDR__SHIFT 0x0 +#define AID3_VF4_BASE_ADDR__AID3_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID0_XCC0_VF4_BASE_ADDR +#define AID0_XCC0_VF4_BASE_ADDR__AID0_XCC0_VF4_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC0_VF4_BASE_ADDR__AID0_XCC0_VF4_BASE_ADDR_MASK 0x0001FFFFL +//AID0_XCC1_VF4_BASE_ADDR +#define AID0_XCC1_VF4_BASE_ADDR__AID0_XCC1_VF4_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC1_VF4_BASE_ADDR__AID0_XCC1_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC0_VF4_BASE_ADDR +#define AID1_XCC0_VF4_BASE_ADDR__AID1_XCC0_VF4_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC0_VF4_BASE_ADDR__AID1_XCC0_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC1_VF4_BASE_ADDR +#define AID1_XCC1_VF4_BASE_ADDR__AID1_XCC1_VF4_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC1_VF4_BASE_ADDR__AID1_XCC1_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC0_VF4_BASE_ADDR +#define AID2_XCC0_VF4_BASE_ADDR__AID2_XCC0_VF4_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC0_VF4_BASE_ADDR__AID2_XCC0_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC1_VF4_BASE_ADDR +#define AID2_XCC1_VF4_BASE_ADDR__AID2_XCC1_VF4_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC1_VF4_BASE_ADDR__AID2_XCC1_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC0_VF4_BASE_ADDR +#define AID3_XCC0_VF4_BASE_ADDR__AID3_XCC0_VF4_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC0_VF4_BASE_ADDR__AID3_XCC0_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC1_VF4_BASE_ADDR +#define AID3_XCC1_VF4_BASE_ADDR__AID3_XCC1_VF4_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC1_VF4_BASE_ADDR__AID3_XCC1_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID0_NBIF_VF4_BASE_ADDR +#define AID0_NBIF_VF4_BASE_ADDR__AID0_NBIF_VF4_BASE_ADDR__SHIFT 0x0 +#define AID0_NBIF_VF4_BASE_ADDR__AID0_NBIF_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID0_ATHUB_VF4_BASE_ADDR +#define AID0_ATHUB_VF4_BASE_ADDR__AID0_ATHUB_VF4_BASE_ADDR__SHIFT 0x0 +#define AID0_ATHUB_VF4_BASE_ADDR__AID0_ATHUB_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID0_IH_VF4_BASE_ADDR +#define AID0_IH_VF4_BASE_ADDR__AID0_IH_VF4_BASE_ADDR__SHIFT 0x0 +#define AID0_IH_VF4_BASE_ADDR__AID0_IH_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID0_HDP_VF4_BASE_ADDR +#define AID0_HDP_VF4_BASE_ADDR__AID0_HDP_VF4_BASE_ADDR__SHIFT 0x0 +#define AID0_HDP_VF4_BASE_ADDR__AID0_HDP_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID0_VF5_BASE_ADDR +#define AID0_VF5_BASE_ADDR__AID0_VF5_BASE_ADDR__SHIFT 0x0 +#define AID0_VF5_BASE_ADDR__AID0_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID1_VF5_BASE_ADDR +#define AID1_VF5_BASE_ADDR__AID1_VF5_BASE_ADDR__SHIFT 0x0 +#define AID1_VF5_BASE_ADDR__AID1_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID2_VF5_BASE_ADDR +#define AID2_VF5_BASE_ADDR__AID2_VF5_BASE_ADDR__SHIFT 0x0 +#define AID2_VF5_BASE_ADDR__AID2_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID3_VF5_BASE_ADDR +#define AID3_VF5_BASE_ADDR__AID3_VF5_BASE_ADDR__SHIFT 0x0 +#define AID3_VF5_BASE_ADDR__AID3_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID0_XCC0_VF5_BASE_ADDR +#define AID0_XCC0_VF5_BASE_ADDR__AID0_XCC0_VF5_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC0_VF5_BASE_ADDR__AID0_XCC0_VF5_BASE_ADDR_MASK 0x0001FFFFL +//AID0_XCC1_VF5_BASE_ADDR +#define AID0_XCC1_VF5_BASE_ADDR__AID0_XCC1_VF5_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC1_VF5_BASE_ADDR__AID0_XCC1_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC0_VF5_BASE_ADDR +#define AID1_XCC0_VF5_BASE_ADDR__AID1_XCC0_VF5_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC0_VF5_BASE_ADDR__AID1_XCC0_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC1_VF5_BASE_ADDR +#define AID1_XCC1_VF5_BASE_ADDR__AID1_XCC1_VF5_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC1_VF5_BASE_ADDR__AID1_XCC1_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC0_VF5_BASE_ADDR +#define AID2_XCC0_VF5_BASE_ADDR__AID2_XCC0_VF5_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC0_VF5_BASE_ADDR__AID2_XCC0_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC1_VF5_BASE_ADDR +#define AID2_XCC1_VF5_BASE_ADDR__AID2_XCC1_VF5_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC1_VF5_BASE_ADDR__AID2_XCC1_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC0_VF5_BASE_ADDR +#define AID3_XCC0_VF5_BASE_ADDR__AID3_XCC0_VF5_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC0_VF5_BASE_ADDR__AID3_XCC0_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC1_VF5_BASE_ADDR +#define AID3_XCC1_VF5_BASE_ADDR__AID3_XCC1_VF5_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC1_VF5_BASE_ADDR__AID3_XCC1_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID0_NBIF_VF5_BASE_ADDR +#define AID0_NBIF_VF5_BASE_ADDR__AID0_NBIF_VF5_BASE_ADDR__SHIFT 0x0 +#define AID0_NBIF_VF5_BASE_ADDR__AID0_NBIF_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID0_ATHUB_VF5_BASE_ADDR +#define AID0_ATHUB_VF5_BASE_ADDR__AID0_ATHUB_VF5_BASE_ADDR__SHIFT 0x0 +#define AID0_ATHUB_VF5_BASE_ADDR__AID0_ATHUB_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID0_IH_VF5_BASE_ADDR +#define AID0_IH_VF5_BASE_ADDR__AID0_IH_VF5_BASE_ADDR__SHIFT 0x0 +#define AID0_IH_VF5_BASE_ADDR__AID0_IH_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID0_HDP_VF5_BASE_ADDR +#define AID0_HDP_VF5_BASE_ADDR__AID0_HDP_VF5_BASE_ADDR__SHIFT 0x0 +#define AID0_HDP_VF5_BASE_ADDR__AID0_HDP_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID0_VF6_BASE_ADDR +#define AID0_VF6_BASE_ADDR__AID0_VF6_BASE_ADDR__SHIFT 0x0 +#define AID0_VF6_BASE_ADDR__AID0_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID1_VF6_BASE_ADDR +#define AID1_VF6_BASE_ADDR__AID1_VF6_BASE_ADDR__SHIFT 0x0 +#define AID1_VF6_BASE_ADDR__AID1_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID2_VF6_BASE_ADDR +#define AID2_VF6_BASE_ADDR__AID2_VF6_BASE_ADDR__SHIFT 0x0 +#define AID2_VF6_BASE_ADDR__AID2_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID3_VF6_BASE_ADDR +#define AID3_VF6_BASE_ADDR__AID3_VF6_BASE_ADDR__SHIFT 0x0 +#define AID3_VF6_BASE_ADDR__AID3_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID0_XCC0_VF6_BASE_ADDR +#define AID0_XCC0_VF6_BASE_ADDR__AID0_XCC0_VF6_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC0_VF6_BASE_ADDR__AID0_XCC0_VF6_BASE_ADDR_MASK 0x0001FFFFL +//AID0_XCC1_VF6_BASE_ADDR +#define AID0_XCC1_VF6_BASE_ADDR__AID0_XCC1_VF6_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC1_VF6_BASE_ADDR__AID0_XCC1_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC0_VF6_BASE_ADDR +#define AID1_XCC0_VF6_BASE_ADDR__AID1_XCC0_VF6_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC0_VF6_BASE_ADDR__AID1_XCC0_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC1_VF6_BASE_ADDR +#define AID1_XCC1_VF6_BASE_ADDR__AID1_XCC1_VF6_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC1_VF6_BASE_ADDR__AID1_XCC1_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC0_VF6_BASE_ADDR +#define AID2_XCC0_VF6_BASE_ADDR__AID2_XCC0_VF6_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC0_VF6_BASE_ADDR__AID2_XCC0_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC1_VF6_BASE_ADDR +#define AID2_XCC1_VF6_BASE_ADDR__AID2_XCC1_VF6_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC1_VF6_BASE_ADDR__AID2_XCC1_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC0_VF6_BASE_ADDR +#define AID3_XCC0_VF6_BASE_ADDR__AID3_XCC0_VF6_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC0_VF6_BASE_ADDR__AID3_XCC0_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC1_VF6_BASE_ADDR +#define AID3_XCC1_VF6_BASE_ADDR__AID3_XCC1_VF6_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC1_VF6_BASE_ADDR__AID3_XCC1_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID0_NBIF_VF6_BASE_ADDR +#define AID0_NBIF_VF6_BASE_ADDR__AID0_NBIF_VF6_BASE_ADDR__SHIFT 0x0 +#define AID0_NBIF_VF6_BASE_ADDR__AID0_NBIF_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID0_ATHUB_VF6_BASE_ADDR +#define AID0_ATHUB_VF6_BASE_ADDR__AID0_ATHUB_VF6_BASE_ADDR__SHIFT 0x0 +#define AID0_ATHUB_VF6_BASE_ADDR__AID0_ATHUB_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID0_IH_VF6_BASE_ADDR +#define AID0_IH_VF6_BASE_ADDR__AID0_IH_VF6_BASE_ADDR__SHIFT 0x0 +#define AID0_IH_VF6_BASE_ADDR__AID0_IH_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID0_HDP_VF6_BASE_ADDR +#define AID0_HDP_VF6_BASE_ADDR__AID0_HDP_VF6_BASE_ADDR__SHIFT 0x0 +#define AID0_HDP_VF6_BASE_ADDR__AID0_HDP_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID0_VF7_BASE_ADDR +#define AID0_VF7_BASE_ADDR__AID0_VF7_BASE_ADDR__SHIFT 0x0 +#define AID0_VF7_BASE_ADDR__AID0_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID1_VF7_BASE_ADDR +#define AID1_VF7_BASE_ADDR__AID1_VF7_BASE_ADDR__SHIFT 0x0 +#define AID1_VF7_BASE_ADDR__AID1_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID2_VF7_BASE_ADDR +#define AID2_VF7_BASE_ADDR__AID2_VF7_BASE_ADDR__SHIFT 0x0 +#define AID2_VF7_BASE_ADDR__AID2_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID3_VF7_BASE_ADDR +#define AID3_VF7_BASE_ADDR__AID3_VF7_BASE_ADDR__SHIFT 0x0 +#define AID3_VF7_BASE_ADDR__AID3_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID0_XCC0_VF7_BASE_ADDR +#define AID0_XCC0_VF7_BASE_ADDR__AID0_XCC0_VF7_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC0_VF7_BASE_ADDR__AID0_XCC0_VF7_BASE_ADDR_MASK 0x0001FFFFL +//AID0_XCC1_VF7_BASE_ADDR +#define AID0_XCC1_VF7_BASE_ADDR__AID0_XCC1_VF7_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC1_VF7_BASE_ADDR__AID0_XCC1_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC0_VF7_BASE_ADDR +#define AID1_XCC0_VF7_BASE_ADDR__AID1_XCC0_VF7_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC0_VF7_BASE_ADDR__AID1_XCC0_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC1_VF7_BASE_ADDR +#define AID1_XCC1_VF7_BASE_ADDR__AID1_XCC1_VF7_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC1_VF7_BASE_ADDR__AID1_XCC1_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC0_VF7_BASE_ADDR +#define AID2_XCC0_VF7_BASE_ADDR__AID2_XCC0_VF7_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC0_VF7_BASE_ADDR__AID2_XCC0_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC1_VF7_BASE_ADDR +#define AID2_XCC1_VF7_BASE_ADDR__AID2_XCC1_VF7_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC1_VF7_BASE_ADDR__AID2_XCC1_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC0_VF7_BASE_ADDR +#define AID3_XCC0_VF7_BASE_ADDR__AID3_XCC0_VF7_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC0_VF7_BASE_ADDR__AID3_XCC0_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC1_VF7_BASE_ADDR +#define AID3_XCC1_VF7_BASE_ADDR__AID3_XCC1_VF7_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC1_VF7_BASE_ADDR__AID3_XCC1_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID0_NBIF_VF7_BASE_ADDR +#define AID0_NBIF_VF7_BASE_ADDR__AID0_NBIF_VF7_BASE_ADDR__SHIFT 0x0 +#define AID0_NBIF_VF7_BASE_ADDR__AID0_NBIF_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID0_ATHUB_VF7_BASE_ADDR +#define AID0_ATHUB_VF7_BASE_ADDR__AID0_ATHUB_VF7_BASE_ADDR__SHIFT 0x0 +#define AID0_ATHUB_VF7_BASE_ADDR__AID0_ATHUB_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID0_IH_VF7_BASE_ADDR +#define AID0_IH_VF7_BASE_ADDR__AID0_IH_VF7_BASE_ADDR__SHIFT 0x0 +#define AID0_IH_VF7_BASE_ADDR__AID0_IH_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID0_HDP_VF7_BASE_ADDR +#define AID0_HDP_VF7_BASE_ADDR__AID0_HDP_VF7_BASE_ADDR__SHIFT 0x0 +#define AID0_HDP_VF7_BASE_ADDR__AID0_HDP_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID0_PF_BASE_ADDR +#define AID0_PF_BASE_ADDR__AID0_PF_BASE_ADDR__SHIFT 0x0 +#define AID0_PF_BASE_ADDR__AID0_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID0_XCC0_PF_BASE_ADDR +#define AID0_XCC0_PF_BASE_ADDR__AID0_XCC0_PF_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC0_PF_BASE_ADDR__AID0_XCC0_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID0_XCC1_PF_BASE_ADDR +#define AID0_XCC1_PF_BASE_ADDR__AID0_XCC1_PF_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC1_PF_BASE_ADDR__AID0_XCC1_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID1_PF_BASE_ADDR +#define AID1_PF_BASE_ADDR__AID1_PF_BASE_ADDR__SHIFT 0x0 +#define AID1_PF_BASE_ADDR__AID1_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC0_PF_BASE_ADDR +#define AID1_XCC0_PF_BASE_ADDR__AID1_XCC0_PF_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC0_PF_BASE_ADDR__AID1_XCC0_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC1_PF_BASE_ADDR +#define AID1_XCC1_PF_BASE_ADDR__AID1_XCC1_PF_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC1_PF_BASE_ADDR__AID1_XCC1_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID2_PF_BASE_ADDR +#define AID2_PF_BASE_ADDR__AID2_PF_BASE_ADDR__SHIFT 0x0 +#define AID2_PF_BASE_ADDR__AID2_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC0_PF_BASE_ADDR +#define AID2_XCC0_PF_BASE_ADDR__AID2_XCC0_PF_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC0_PF_BASE_ADDR__AID2_XCC0_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC1_PF_BASE_ADDR +#define AID2_XCC1_PF_BASE_ADDR__AID2_XCC1_PF_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC1_PF_BASE_ADDR__AID2_XCC1_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID3_PF_BASE_ADDR +#define AID3_PF_BASE_ADDR__AID3_PF_BASE_ADDR__SHIFT 0x0 +#define AID3_PF_BASE_ADDR__AID3_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC0_PF_BASE_ADDR +#define AID3_XCC0_PF_BASE_ADDR__AID3_XCC0_PF_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC0_PF_BASE_ADDR__AID3_XCC0_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC1_PF_BASE_ADDR +#define AID3_XCC1_PF_BASE_ADDR__AID3_XCC1_PF_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC1_PF_BASE_ADDR__AID3_XCC1_PF_BASE_ADDR_MASK 0x0000FFFFL +//NBIF_RRMT_CNTL +#define NBIF_RRMT_CNTL__PARTITION_MODE__SHIFT 0x0 +#define NBIF_RRMT_CNTL__AID_DIE_ID__SHIFT 0x4 +#define NBIF_RRMT_CNTL__RRMT_ENABLE__SHIFT 0x8 +#define NBIF_RRMT_CNTL__RRMT_Invalid_Address_H__SHIFT 0x18 +#define NBIF_RRMT_CNTL__PARTITION_MODE_MASK 0x00000007L +#define NBIF_RRMT_CNTL__AID_DIE_ID_MASK 0x00000030L +#define NBIF_RRMT_CNTL__RRMT_ENABLE_MASK 0x00000100L +#define NBIF_RRMT_CNTL__RRMT_Invalid_Address_H_MASK 0xFF000000L +//BIFC_DOORBELL_ACCESS_EN_PF +#define BIFC_DOORBELL_ACCESS_EN_PF__BIFC_DOORBELL_ACCESS_EN_PF__SHIFT 0x0 +#define BIFC_DOORBELL_ACCESS_EN_PF__BIFC_DOORBELL_ACCESS_EN_PF_MASK 0x000FFFFFL +//BIFC_DOORBELL_ACCESS_EN_VF0 +#define BIFC_DOORBELL_ACCESS_EN_VF0__BIFC_DOORBELL_ACCESS_EN_VF0__SHIFT 0x0 +#define BIFC_DOORBELL_ACCESS_EN_VF0__BIFC_DOORBELL_ACCESS_EN_VF0_MASK 0x000FFFFFL +//BIFC_DOORBELL_ACCESS_EN_VF1 +#define BIFC_DOORBELL_ACCESS_EN_VF1__BIFC_DOORBELL_ACCESS_EN_VF1__SHIFT 0x0 +#define BIFC_DOORBELL_ACCESS_EN_VF1__BIFC_DOORBELL_ACCESS_EN_VF1_MASK 0x000FFFFFL +//BIFC_DOORBELL_ACCESS_EN_VF2 +#define BIFC_DOORBELL_ACCESS_EN_VF2__BIFC_DOORBELL_ACCESS_EN_VF2__SHIFT 0x0 +#define BIFC_DOORBELL_ACCESS_EN_VF2__BIFC_DOORBELL_ACCESS_EN_VF2_MASK 0x000FFFFFL +//BIFC_DOORBELL_ACCESS_EN_VF3 +#define BIFC_DOORBELL_ACCESS_EN_VF3__BIFC_DOORBELL_ACCESS_EN_VF3__SHIFT 0x0 +#define BIFC_DOORBELL_ACCESS_EN_VF3__BIFC_DOORBELL_ACCESS_EN_VF3_MASK 0x000FFFFFL +//BIFC_DOORBELL_ACCESS_EN_VF4 +#define BIFC_DOORBELL_ACCESS_EN_VF4__BIFC_DOORBELL_ACCESS_EN_VF4__SHIFT 0x0 +#define BIFC_DOORBELL_ACCESS_EN_VF4__BIFC_DOORBELL_ACCESS_EN_VF4_MASK 0x000FFFFFL +//BIFC_DOORBELL_ACCESS_EN_VF5 +#define BIFC_DOORBELL_ACCESS_EN_VF5__BIFC_DOORBELL_ACCESS_EN_VF5__SHIFT 0x0 +#define BIFC_DOORBELL_ACCESS_EN_VF5__BIFC_DOORBELL_ACCESS_EN_VF5_MASK 0x000FFFFFL +//BIFC_DOORBELL_ACCESS_EN_VF6 +#define BIFC_DOORBELL_ACCESS_EN_VF6__BIFC_DOORBELL_ACCESS_EN_VF6__SHIFT 0x0 +#define BIFC_DOORBELL_ACCESS_EN_VF6__BIFC_DOORBELL_ACCESS_EN_VF6_MASK 0x000FFFFFL +//BIFC_DOORBELL_ACCESS_EN_VF7 +#define BIFC_DOORBELL_ACCESS_EN_VF7__BIFC_DOORBELL_ACCESS_EN_VF7__SHIFT 0x0 +#define BIFC_DOORBELL_ACCESS_EN_VF7__BIFC_DOORBELL_ACCESS_EN_VF7_MASK 0x000FFFFFL +//MISC_SCRATCH +#define MISC_SCRATCH__MISC_SCRATCH0__SHIFT 0x0 +#define MISC_SCRATCH__MISC_SCRATCH0_MASK 0xFFFFFFFFL +//INTR_LINE_POLARITY +#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT 0x0 +#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK 0x000000FFL +//INTR_LINE_ENABLE +#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT 0x0 +#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK 0x000000FFL +//OUTSTANDING_VC_ALLOC +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT 0x0 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT 0x2 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT 0x4 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT 0x6 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT 0x8 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT 0xa +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT 0xc +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT 0xe +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT 0x10 +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT 0x18 +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT 0x1a +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT 0x1c +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK 0x00000003L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK 0x0000000CL +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK 0x00000030L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK 0x000000C0L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK 0x00000300L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK 0x00000C00L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK 0x00003000L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK 0x0000C000L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK 0x000F0000L +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK 0x03000000L +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK 0x0C000000L +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK 0xF0000000L +//BIFC_MISC_CTRL0 +#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT 0x0 +#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT 0x1 +#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS__SHIFT 0x4 +#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT 0x8 +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P__SHIFT 0x9 +#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT 0xb +#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT 0xc +#define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS__SHIFT 0xd +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP__SHIFT 0xe +#define BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE__SHIFT 0xf +#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT 0x10 +#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT 0x11 +#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT 0x12 +#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT 0x13 +#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT 0x14 +#define BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN__SHIFT 0x15 +#define BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN__SHIFT 0x16 +#define BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST__SHIFT 0x17 +#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT 0x18 +#define BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST__SHIFT 0x19 +#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT 0x1a +#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT 0x1b +#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT 0x1c +#define BIFC_MISC_CTRL0__DMA_ALL_RST_PROTECT_STS_SEL__SHIFT 0x1d +#define BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST__SHIFT 0x1e +#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT 0x1f +#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN_MASK 0x00000001L +#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN_MASK 0x00000006L +#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS_MASK 0x000000F0L +#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK 0x00000100L +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P_MASK 0x00000200L +#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK 0x00000800L +#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK 0x00001000L +#define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS_MASK 0x00002000L +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP_MASK 0x00004000L +#define BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE_MASK 0x00008000L +#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK 0x00010000L +#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK 0x00020000L +#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK 0x00040000L +#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK 0x00080000L +#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK 0x00100000L +#define BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN_MASK 0x00200000L +#define BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN_MASK 0x00400000L +#define BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST_MASK 0x00800000L +#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK 0x01000000L +#define BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST_MASK 0x02000000L +#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK 0x04000000L +#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK 0x08000000L +#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK 0x10000000L +#define BIFC_MISC_CTRL0__DMA_ALL_RST_PROTECT_STS_SEL_MASK 0x20000000L +#define BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST_MASK 0x40000000L +#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK 0x80000000L +//BIFC_MISC_CTRL1 +#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT 0x0 +#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT 0x1 +#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT 0x2 +#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT 0x3 +#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT 0x4 +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT 0x5 +#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT 0x6 +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP__SHIFT 0x7 +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT 0x8 +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT 0xa +#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT 0xc +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT 0xd +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT 0xe +#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT 0xf +#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT 0x10 +#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT 0x11 +#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT 0x12 +#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT 0x13 +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT 0x14 +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE__SHIFT 0x15 +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE__SHIFT 0x16 +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG__SHIFT 0x17 +#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT 0x18 +#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT 0x19 +#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT 0x1a +#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT 0x1b +#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT 0x1c +#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN__SHIFT 0x1d +#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT 0x1e +#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK 0x00000001L +#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK 0x00000002L +#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK 0x00000004L +#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK 0x00000008L +#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK 0x00000010L +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK 0x00000020L +#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK 0x00000040L +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP_MASK 0x00000080L +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK 0x00000300L +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK 0x00000C00L +#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK 0x00001000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK 0x00002000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK 0x00004000L +#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK 0x00008000L +#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK 0x00010000L +#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK 0x00020000L +#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK 0x00040000L +#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK 0x00080000L +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK 0x00100000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_MASK 0x00200000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE_MASK 0x00400000L +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG_MASK 0x00800000L +#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK 0x01000000L +#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK 0x02000000L +#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK 0x04000000L +#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK 0x08000000L +#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK 0x10000000L +#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN_MASK 0x20000000L +#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK 0xC0000000L +//BIFC_BME_ERR_LOG_LB +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x0 +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x1 +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x10 +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x11 +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0_MASK 0x00000001L +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1_MASK 0x00000002L +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK 0x00010000L +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1_MASK 0x00020000L +//BIFC_LC_TIMER_CTRL +#define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE__SHIFT 0x0 +#define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE__SHIFT 0x10 +#define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE_MASK 0x0000FFFFL +#define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE_MASK 0xFFFF0000L +//BIFC_RCCBIH_BME_ERR_LOG0 +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x0 +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x1 +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x10 +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x11 +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00000001L +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00000002L +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00010000L +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00020000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0__SHIFT 0x4 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0__SHIFT 0xe +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1__SHIFT 0x14 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1__SHIFT 0x1e +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0_MASK 0x00000030L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0_MASK 0x0000C000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1_MASK 0x00300000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK 0x30000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1_MASK 0xC0000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2__SHIFT 0x4 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2__SHIFT 0xe +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3__SHIFT 0x14 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3__SHIFT 0x1e +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2_MASK 0x00000030L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2_MASK 0x0000C000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3_MASK 0x00300000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK 0x30000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3_MASK 0xC0000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4__SHIFT 0x4 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4__SHIFT 0xe +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5__SHIFT 0x14 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5__SHIFT 0x1e +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4_MASK 0x00000030L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4_MASK 0x0000C000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5_MASK 0x00300000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK 0x30000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5_MASK 0xC0000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6__SHIFT 0x4 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6__SHIFT 0xe +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7__SHIFT 0x14 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7__SHIFT 0x1e +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6_MASK 0x00000030L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6_MASK 0x0000C000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7_MASK 0x00300000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK 0x30000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7_MASK 0xC0000000L +//BIFC_DMA_ATTR_CNTL2_DEV0 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0__SHIFT 0x0 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1__SHIFT 0x4 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2__SHIFT 0x8 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3__SHIFT 0xc +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4__SHIFT 0x10 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5__SHIFT 0x14 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6__SHIFT 0x18 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7__SHIFT 0x1c +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0_MASK 0x00000001L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1_MASK 0x00000010L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2_MASK 0x00000100L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3_MASK 0x00001000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4_MASK 0x00010000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5_MASK 0x00100000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6_MASK 0x01000000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7_MASK 0x10000000L +//BME_DUMMY_CNTL_0 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT 0x0 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT 0x2 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT 0x4 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT 0x6 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT 0x8 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT 0xa +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT 0xc +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT 0xe +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK 0x00000003L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK 0x0000000CL +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK 0x00000030L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK 0x000000C0L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK 0x00000300L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK 0x00000C00L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK 0x00003000L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK 0x0000C000L +//BIFC_THT_CNTL +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT 0x0 +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT 0x4 +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT 0x8 +#define BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x10 +#define BIFC_THT_CNTL__THT_NTB_VC0_APER0_ADSC_PUSH_DIS__SHIFT 0x18 +#define BIFC_THT_CNTL__THT_NTB_VC0_OTHAPER_ADSC_PUSH_DIS__SHIFT 0x19 +#define BIFC_THT_CNTL__THT_NTB_VC1_APER0_ADSC_PUSH_DIS__SHIFT 0x1a +#define BIFC_THT_CNTL__THT_NTB_VC1_OTHAPER_ADSC_PUSH_DIS__SHIFT 0x1b +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0_MASK 0x0000000FL +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0_MASK 0x000000F0L +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1_MASK 0x00000F00L +#define BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN_MASK 0x00010000L +#define BIFC_THT_CNTL__THT_NTB_VC0_APER0_ADSC_PUSH_DIS_MASK 0x01000000L +#define BIFC_THT_CNTL__THT_NTB_VC0_OTHAPER_ADSC_PUSH_DIS_MASK 0x02000000L +#define BIFC_THT_CNTL__THT_NTB_VC1_APER0_ADSC_PUSH_DIS_MASK 0x04000000L +#define BIFC_THT_CNTL__THT_NTB_VC1_OTHAPER_ADSC_PUSH_DIS_MASK 0x08000000L +//BIFC_HSTARB_CNTL +#define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT 0x0 +#define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN__SHIFT 0x8 +#define BIFC_HSTARB_CNTL__SLVARB_MODE_MASK 0x00000003L +#define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN_MASK 0x00000100L +//BIFC_GSI_CNTL +#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT 0x0 +#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT 0x2 +#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT 0x5 +#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT 0x6 +#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT 0x7 +#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT 0x8 +#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT 0xa +#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT 0xc +#define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK__SHIFT 0xf +#define BIFC_GSI_CNTL__GSI_SMN_BURST_EN__SHIFT 0x10 +#define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN__SHIFT 0x11 +#define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE__SHIFT 0x1b +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH__SHIFT 0x1c +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH__SHIFT 0x1d +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD__SHIFT 0x1e +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL__SHIFT 0x1f +#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK 0x00000003L +#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK 0x0000001CL +#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK 0x00000020L +#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK 0x00000040L +#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK 0x00000080L +#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK 0x00000100L +#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK 0x00000C00L +#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK 0x00003000L +#define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK_MASK 0x00008000L +#define BIFC_GSI_CNTL__GSI_SMN_BURST_EN_MASK 0x00010000L +#define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN_MASK 0x00020000L +#define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE_MASK 0x08000000L +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH_MASK 0x10000000L +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH_MASK 0x20000000L +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD_MASK 0x40000000L +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL_MASK 0x80000000L +//BIFC_PCIEFUNC_CNTL +#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT 0x0 +#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK 0x0000FFFFL +//BIFC_PASID_CHECK_DIS +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0__SHIFT 0x0 +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1__SHIFT 0x1 +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0_MASK 0x00000001L +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1_MASK 0x00000002L +//BIFC_SDP_CNTL_0 +#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT 0x0 +#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT 0x8 +#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT 0x10 +#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT 0x18 +#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK 0x000000FFL +#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK 0x0000FF00L +#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK 0x00FF0000L +#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK 0xFF000000L +//BIFC_SDP_CNTL_1 +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT 0x0 +#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT 0x1 +#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT 0x2 +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT 0x3 +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x4 +#define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P__SHIFT 0x5 +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x7 +#define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN__SHIFT 0x8 +#define BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x9 +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK 0x00000001L +#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK 0x00000002L +#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK 0x00000004L +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK 0x00000008L +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000010L +#define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P_MASK 0x00000020L +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000080L +#define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN_MASK 0x00000100L +#define BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00000200L +//BIFC_PASID_STS +#define BIFC_PASID_STS__PASID_STS__SHIFT 0x0 +#define BIFC_PASID_STS__PASID_STS_MASK 0x0000000FL +//BIFC_ATHUB_ACT_CNTL +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE__SHIFT 0x0 +#define BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE__SHIFT 0x3 +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS__SHIFT 0x8 +#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT 0x9 +#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT 0xa +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE_MASK 0x00000007L +#define BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE_MASK 0x00000038L +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS_MASK 0x00000100L +#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER_MASK 0x00000200L +#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER_MASK 0x00000400L +//BIFC_PERF_CNTL_0 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT 0x0 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT 0x1 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT 0x8 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT 0x9 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT 0x10 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT 0x18 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK 0x00000001L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK 0x00000002L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK 0x00000100L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK 0x00000200L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK 0x007F0000L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK 0x7F000000L +//BIFC_PERF_CNTL_1 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT 0x0 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT 0x1 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT 0x4 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT 0x5 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT 0x8 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT 0x10 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK 0x00000001L +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK 0x00000002L +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK 0x00000010L +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK 0x00000020L +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK 0x0000FF00L +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK 0x01FF0000L +//BIFC_PERF_CNT_MMIO_RD_L32BIT +#define BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIFC_PERF_CNT_MMIO_WR_L32BIT +#define BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIFC_PERF_CNT_DMA_RD_L32BIT +#define BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIFC_PERF_CNT_DMA_WR_L32BIT +#define BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT_MASK 0xFFFFFFFFL +//NBIF_REGIF_ERRSET_CTRL +#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 +#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L +//BIFC_SDP_CNTL_2 +#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS__SHIFT 0x0 +#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H__SHIFT 0x8 +#define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H__SHIFT 0x10 +#define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H__SHIFT 0x18 +#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_MASK 0x000000FFL +#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H_MASK 0x00000F00L +#define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H_MASK 0x000F0000L +#define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H_MASK 0x0F000000L +//NBIF_PGMST_CTRL +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS__SHIFT 0x0 +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN__SHIFT 0x8 +#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN__SHIFT 0xa +#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN__SHIFT 0xe +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS_MASK 0x000000FFL +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN_MASK 0x00000100L +#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L +#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L +//NBIF_PGSLV_CTRL +#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS__SHIFT 0x0 +#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS_MASK 0x0000001FL +//NBIF_PG_MISC_CTRL +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0 +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5 +#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY__SHIFT 0xa +#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1__SHIFT 0xd +#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS__SHIFT 0xe +#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2__SHIFT 0x10 +#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18 +#define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK__SHIFT 0x1e +#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L +#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY_MASK 0x00000400L +#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1_MASK 0x00002000L +#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS_MASK 0x00004000L +#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2_MASK 0x00010000L +#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L +#define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK_MASK 0x40000000L +#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L +//SMN_MST_EP_CNTL3 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK 0x00000080L +//SMN_MST_EP_CNTL4 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK 0x00000080L +//SMN_MST_CNTL1 +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT 0x0 +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT 0x10 +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK 0x00000001L +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK 0x00010000L +//SMN_MST_EP_CNTL5 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK 0x00000080L +//BIF_SELFRING_BUFFER_VID +#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT 0x0 +#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID__SHIFT 0x8 +#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID__SHIFT 0x10 +#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK 0x000000FFL +#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID_MASK 0x0000FF00L +#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID_MASK 0x00FF0000L +//BIF_SELFRING_VECTOR_CNTL +#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT 0x0 +#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT 0x1 +#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK 0x00000001L +#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK 0x00000002L +//NBIF_STRAP_WRITE_CTRL +#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT 0x0 +#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE_MASK 0x00000001L +//NBIF_INTX_DSTATE_MISC_CNTL +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x0 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x1 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x2 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x3 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x4 +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP__SHIFT 0x5 +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN__SHIFT 0x6 +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x7 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00000001L +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00000002L +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00000004L +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00000008L +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00000010L +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP_MASK 0x00000020L +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN_MASK 0x00000040L +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000080L +//NBIF_PENDING_MISC_CNTL +#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS__SHIFT 0x0 +#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS__SHIFT 0x1 +#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS_MASK 0x00000001L +#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS_MASK 0x00000002L +//BIF_GMI_WRR_WEIGHT +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE__SHIFT 0x1d +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE__SHIFT 0x1e +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE__SHIFT 0x1f +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE_MASK 0x20000000L +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE_MASK 0x40000000L +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE_MASK 0x80000000L +//BIF_GMI_WRR_WEIGHT2 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT__SHIFT 0x0 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT__SHIFT 0x8 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT__SHIFT 0x10 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT__SHIFT 0x18 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT_MASK 0x000000FFL +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT_MASK 0x0000FF00L +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT_MASK 0x00FF0000L +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT_MASK 0xFF000000L +//BIF_GMI_WRR_WEIGHT3 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT__SHIFT 0x0 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT__SHIFT 0x8 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT__SHIFT 0x10 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT__SHIFT 0x18 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT_MASK 0x000000FFL +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT_MASK 0x0000FF00L +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT_MASK 0x00FF0000L +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT_MASK 0xFF000000L +//NBIF_PWRBRK_REQUEST +#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST__SHIFT 0x0 +#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST_MASK 0x00000001L +//BIF_ATOMIC_ERR_LOG_DEV0_F0 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x0 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x1 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x2 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0__SHIFT 0x3 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x10 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x11 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x12 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0__SHIFT 0x13 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00000001L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00000002L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00000004L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0_MASK 0x00000008L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00010000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00020000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00040000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0_MASK 0x00080000L +//BIF_ATOMIC_ERR_LOG_DEV0_F1 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1__SHIFT 0x0 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT 0x1 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1__SHIFT 0x2 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1__SHIFT 0x3 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1__SHIFT 0x10 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT 0x11 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1__SHIFT 0x12 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1__SHIFT 0x13 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1_MASK 0x00000001L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK 0x00000002L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1_MASK 0x00000004L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1_MASK 0x00000008L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1_MASK 0x00010000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK 0x00020000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1_MASK 0x00040000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1_MASK 0x00080000L +//BIF_DMA_MP4_ERR_LOG +#define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR__SHIFT 0x0 +#define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT 0x1 +#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR__SHIFT 0x10 +#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT 0x11 +#define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR_MASK 0x00000001L +#define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK 0x00000002L +#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR_MASK 0x00010000L +#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK 0x00020000L +//BIF_PASID_ERR_LOG +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0__SHIFT 0x0 +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1__SHIFT 0x1 +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0_MASK 0x00000001L +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1_MASK 0x00000002L +//BIF_PASID_ERR_CLR +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0__SHIFT 0x0 +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1__SHIFT 0x1 +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0_MASK 0x00000001L +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1_MASK 0x00000002L +//NBIF_VWIRE_CTRL +#define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS__SHIFT 0x0 +#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT 0x4 +#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT 0x8 +#define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS__SHIFT 0x10 +#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT 0x14 +#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT 0x1a +#define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS_MASK 0x00000001L +#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK 0x000000F0L +#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK 0x00000100L +#define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS_MASK 0x00010000L +#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK 0x00F00000L +#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK 0x0C000000L +//NBIF_SMN_VWR_VCHG_DIS_CTRL +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT 0x0 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT 0x1 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT 0x2 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT 0x3 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT 0x4 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT 0x5 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT 0x6 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS_MASK 0x00000001L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS_MASK 0x00000002L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS_MASK 0x00000004L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS_MASK 0x00000008L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS_MASK 0x00000010L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS_MASK 0x00000020L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS_MASK 0x00000040L +//NBIF_SMN_VWR_VCHG_RST_CTRL0 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT 0x0 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT 0x1 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT 0x2 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT 0x3 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT 0x4 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT 0x5 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT 0x6 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV_MASK 0x00000001L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV_MASK 0x00000002L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV_MASK 0x00000004L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV_MASK 0x00000008L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV_MASK 0x00000010L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV_MASK 0x00000020L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV_MASK 0x00000040L +//NBIF_SMN_VWR_VCHG_TRIG +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT 0x0 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT 0x1 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT 0x2 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT 0x3 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT 0x4 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT 0x5 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT 0x6 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG_MASK 0x00000001L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG_MASK 0x00000002L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG_MASK 0x00000004L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG_MASK 0x00000008L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG_MASK 0x00000010L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG_MASK 0x00000020L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG_MASK 0x00000040L +//NBIF_SMN_VWR_WTRIG_CNTL +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT 0x0 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT 0x1 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT 0x2 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT 0x3 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT 0x4 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT 0x5 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT 0x6 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS_MASK 0x00000001L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS_MASK 0x00000002L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS_MASK 0x00000004L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS_MASK 0x00000008L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS_MASK 0x00000010L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS_MASK 0x00000020L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS_MASK 0x00000040L +//NBIF_SMN_VWR_VCHG_DIS_CTRL_1 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT 0x0 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT 0x1 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT 0x2 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT 0x3 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT 0x4 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT 0x5 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT 0x6 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV_MASK 0x00000001L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV_MASK 0x00000002L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV_MASK 0x00000004L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV_MASK 0x00000008L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV_MASK 0x00000010L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV_MASK 0x00000020L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV_MASK 0x00000040L +//NBIF_MGCG_CTRL_LCLK +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT 0x0 +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT 0x1 +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT 0x2 +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT 0xa +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT 0xb +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK__SHIFT 0xc +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT 0xd +#define NBIF_MGCG_CTRL_LCLK__NBIF_SRAM_FGCG_EN_LCLK__SHIFT 0xe +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK 0x00000001L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK 0x00000002L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK 0x000003FCL +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK 0x00000400L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK 0x00000800L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK 0x00001000L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK 0x00002000L +#define NBIF_MGCG_CTRL_LCLK__NBIF_SRAM_FGCG_EN_LCLK_MASK 0x00004000L +//NBIF_DS_CTRL_LCLK +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT 0x0 +#define NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT 0x10 +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK 0x00000001L +#define NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK 0xFFFF0000L +//SMN_MST_CNTL0 +#define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT 0x0 +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT 0x8 +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT 0x9 +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT 0xa +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT 0xb +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT 0x10 +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT 0x14 +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT 0x18 +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT 0x1c +#define SMN_MST_CNTL0__SMN_ARB_MODE_MASK 0x00000003L +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK 0x00000100L +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK 0x00000200L +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK 0x00000400L +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK 0x00000800L +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK 0x00010000L +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK 0x00100000L +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK 0x01000000L +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK 0x10000000L +//SMN_MST_EP_CNTL1 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK 0x00000080L +//SMN_MST_EP_CNTL2 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK 0x00000080L +//NBIF_SDP_VWR_VCHG_DIS_CTRL +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK 0x01000000L +//NBIF_SDP_VWR_VCHG_RST_CTRL0 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK 0x01000000L +//NBIF_SDP_VWR_VCHG_RST_CTRL1 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK 0x01000000L +//NBIF_SDP_VWR_VCHG_TRIG +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK 0x01000000L +//NBIF_SHUB_TODET_CTRL +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN__SHIFT 0x0 +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN__SHIFT 0x1 +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT__SHIFT 0x8 +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT__SHIFT 0x10 +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN_MASK 0x00000001L +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN_MASK 0x00000002L +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT_MASK 0x00000700L +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT_MASK 0xFFFF0000L +//NBIF_SHUB_TODET_CLIENT_CTRL +#define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_CLIENT_STATUS +#define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_SYNCFLOOD_CTRL +#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN__SHIFT 0x0 +#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_CLIENT_CTRL2 +#define NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_CLIENT_STATUS2 +#define NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_SYNCFLOOD_CTRL2 +#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2__SHIFT 0x0 +#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2_MASK 0xFFFFFFFFL +//BIFC_BME_ERR_LOG_HB +//BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC +#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +//BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC +#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +//BIFC_GMI_SDP_REQ_POOLCRED_ALLOC +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//BIFC_GMI_SDP_DAT_POOLCRED_ALLOC +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//DISCON_HYSTERESIS_HEAD_CTRL +#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H__SHIFT 0x0 +#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H__SHIFT 0x8 +#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H_MASK 0x0000000FL +#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H_MASK 0x00000F00L +//BIFC_EARLY_WAKEUP_CNTL +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0x0 +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0x1 +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0x2 +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000001L +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00000002L +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00000004L +//BIFC_PERF_CNT_MMIO_RD_H16BIT +#define BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT_MASK 0x0000FFFFL +//BIFC_PERF_CNT_MMIO_WR_H16BIT +#define BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT_MASK 0x0000FFFFL +//BIFC_PERF_CNT_DMA_RD_H16BIT +#define BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT_MASK 0x0000FFFFL +//BIFC_PERF_CNT_DMA_WR_H16BIT +#define BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT_MASK 0x0000FFFFL +//BIFC_A2S_SDP_PORT_CTRL +#define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0 +#define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H__SHIFT 0x8 +#define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_DIS__SHIFT 0xc +#define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x000000FFL +#define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H_MASK 0x00000F00L +#define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_DIS_MASK 0x00001000L +//BIFC_A2S_CNTL_SW0 +#define BIFC_A2S_CNTL_SW0__RDRSP_ERRMAP__SHIFT 0x0 +#define BIFC_A2S_CNTL_SW0__RDRSP_SEL_MODE__SHIFT 0x2 +#define BIFC_A2S_CNTL_SW0__STATIC_VC_ENABLE__SHIFT 0x5 +#define BIFC_A2S_CNTL_SW0__STATIC_VC_VALUE__SHIFT 0x6 +#define BIFC_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define BIFC_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define BIFC_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define BIFC_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define BIFC_A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT 0x10 +#define BIFC_A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT 0x18 +#define BIFC_A2S_CNTL_SW0__RDRSP_ERRMAP_MASK 0x00000003L +#define BIFC_A2S_CNTL_SW0__RDRSP_SEL_MODE_MASK 0x0000001CL +#define BIFC_A2S_CNTL_SW0__STATIC_VC_ENABLE_MASK 0x00000020L +#define BIFC_A2S_CNTL_SW0__STATIC_VC_VALUE_MASK 0x000001C0L +#define BIFC_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define BIFC_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define BIFC_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define BIFC_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define BIFC_A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define BIFC_A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK 0xFF000000L +//BIFC_A2S_MISC_CNTL +#define BIFC_A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT 0x0 +#define BIFC_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT 0x2 +#define BIFC_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE__SHIFT 0x3 +#define BIFC_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN__SHIFT 0x4 +#define BIFC_A2S_MISC_CNTL__RSP_REORDER_DIS__SHIFT 0x5 +#define BIFC_A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT 0x6 +#define BIFC_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x7 +#define BIFC_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x8 +#define BIFC_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0x9 +#define BIFC_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0xa +#define BIFC_A2S_MISC_CNTL__WR_TAG_SET_MIN__SHIFT 0x10 +#define BIFC_A2S_MISC_CNTL__RD_TAG_SET_MIN__SHIFT 0x15 +#define BIFC_A2S_MISC_CNTL__WRR_LRG_MODE__SHIFT 0x1a +#define BIFC_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE__SHIFT 0x1b +#define BIFC_A2S_MISC_CNTL__BYPASS_OVERRIDE_EN__SHIFT 0x1c +#define BIFC_A2S_MISC_CNTL__BYPASS_OVERRIDE_VALUE__SHIFT 0x1d +#define BIFC_A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK 0x00000003L +#define BIFC_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS_MASK 0x00000004L +#define BIFC_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE_MASK 0x00000008L +#define BIFC_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN_MASK 0x00000010L +#define BIFC_A2S_MISC_CNTL__RSP_REORDER_DIS_MASK 0x00000020L +#define BIFC_A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK 0x00000040L +#define BIFC_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000080L +#define BIFC_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000100L +#define BIFC_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY_MASK 0x00000200L +#define BIFC_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000400L +#define BIFC_A2S_MISC_CNTL__WR_TAG_SET_MIN_MASK 0x001F0000L +#define BIFC_A2S_MISC_CNTL__RD_TAG_SET_MIN_MASK 0x03E00000L +#define BIFC_A2S_MISC_CNTL__WRR_LRG_MODE_MASK 0x04000000L +#define BIFC_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE_MASK 0x08000000L +#define BIFC_A2S_MISC_CNTL__BYPASS_OVERRIDE_EN_MASK 0x10000000L +#define BIFC_A2S_MISC_CNTL__BYPASS_OVERRIDE_VALUE_MASK 0x20000000L +//BIFC_A2S_TAG_ALLOC_0 +#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT 0x0 +#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT 0x8 +#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT 0x10 +#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK 0x000000FFL +#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK 0x0000FF00L +#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK 0x00FF0000L +//BIFC_A2S_TAG_ALLOC_1 +#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT 0x0 +#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT 0x10 +#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT 0x18 +#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK 0x000000FFL +#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK 0x00FF0000L +#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK 0xFF000000L +//BIFC_A2S_CNTL_CL0 +#define BIFC_A2S_CNTL_CL0__NSNOOP_MAP__SHIFT 0x0 +#define BIFC_A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT 0x2 +#define BIFC_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT 0x4 +#define BIFC_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 +#define BIFC_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 +#define BIFC_A2S_CNTL_CL0__BLKLVL_MAP__SHIFT 0xa +#define BIFC_A2S_CNTL_CL0__DATERR_MAP__SHIFT 0xc +#define BIFC_A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT 0xe +#define BIFC_A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT 0x10 +#define BIFC_A2S_CNTL_CL0__RESP_WR_MAP__SHIFT 0x12 +#define BIFC_A2S_CNTL_CL0__RESP_RD_MAP__SHIFT 0x14 +#define BIFC_A2S_CNTL_CL0__NSNOOP_MAP_MASK 0x00000003L +#define BIFC_A2S_CNTL_CL0__REQPASSPW_VC0_MAP_MASK 0x0000000CL +#define BIFC_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP_MASK 0x00000030L +#define BIFC_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP_MASK 0x000000C0L +#define BIFC_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP_MASK 0x00000300L +#define BIFC_A2S_CNTL_CL0__BLKLVL_MAP_MASK 0x00000C00L +#define BIFC_A2S_CNTL_CL0__DATERR_MAP_MASK 0x00003000L +#define BIFC_A2S_CNTL_CL0__EXOKAY_WR_MAP_MASK 0x0000C000L +#define BIFC_A2S_CNTL_CL0__EXOKAY_RD_MAP_MASK 0x00030000L +#define BIFC_A2S_CNTL_CL0__RESP_WR_MAP_MASK 0x000C0000L +#define BIFC_A2S_CNTL_CL0__RESP_RD_MAP_MASK 0x00300000L + + +// addressBlock: aid_nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +//RCC_DWN_DEV0_2_DN_PCIE_RESERVED +#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_2_DN_PCIE_SCRATCH +#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_2_DN_PCIE_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +//RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 +#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L +//RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +//RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L +//RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L + + +// addressBlock: aid_nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +//RCC_DWNP_DEV0_2_PCIE_ERR_CNTL +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L +//RCC_DWNP_DEV0_2_PCIE_RX_CNTL +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +//RCC_DWNP_DEV0_2_PCIE_LC_CNTL2 +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC +#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L +//RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP +#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_ep_dev0_BIFDEC1 +//RCC_EP_DEV0_2_EP_PCIE_SCRATCH +#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_2_EP_PCIE_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_EP_DEV0_2_EP_PCIE_INT_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +//RCC_EP_DEV0_2_EP_PCIE_INT_STATUS +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L +//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +//RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +//RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +//RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC +#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2 +#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L +//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL +#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL +//RCC_EP_DEV0_2_EP_PCIEP_RESERVED +#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_2_EP_PCIE_TX_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L +//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_BIFDEC1 +//RCC_DEV0_1_RCC_ERR_INT_CNTL +#define RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0 +#define RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L +//RCC_DEV0_1_RCC_BACO_CNTL_MISC +#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 +#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L +#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L +//RCC_DEV0_1_RCC_RESET_EN +#define RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf +#define RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L +//RCC_DEV0_2_RCC_VDM_SUPPORT +#define RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L +#define RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L +#define RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L +#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L +#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L +//RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L +//RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L +//RCC_DEV0_1_RCC_GPUIOV_REGION +#define RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 +#define RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 +#define RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION_MASK 0x0000000FL +#define RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION_MASK 0x000000F0L +//RCC_DEV0_1_RCC_GPU_HOSTVM_EN +#define RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT 0x0 +#define RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK 0x00000001L +//RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL +#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT 0x1 +#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK 0x00000001L +#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK 0x00000002L +//RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET +#define RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE +#define RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK 0xFFFFL +//RCC_DEV0_1_RCC_PEER_REG_RANGE0 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL +#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L +//RCC_DEV0_1_RCC_PEER_REG_RANGE1 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL +#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L +//RCC_DEV0_2_RCC_BUS_CNTL +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 +#define RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc +#define RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 +#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 +#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 +#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c +#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L +#define RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L +#define RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L +#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L +#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L +#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L +#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L +//RCC_DEV0_1_RCC_CONFIG_CNTL +#define RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 +#define RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 +#define RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L +#define RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L +#define RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L +//RCC_DEV0_1_RCC_CONFIG_F0_BASE +#define RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL +//RCC_DEV0_1_RCC_CONFIG_APER_SIZE +#define RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE +#define RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x07FFFFFFL +//RCC_DEV0_1_RCC_XDMA_LO +#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 +#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL +#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_XDMA_HI +#define RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 +#define RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL +//RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L +//RCC_DEV0_1_RCC_BUSNUM_CNTL1 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL +//RCC_DEV0_1_RCC_BUSNUM_LIST0 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1__SHIFT 0x8 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2__SHIFT 0x10 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3__SHIFT 0x18 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L +//RCC_DEV0_1_RCC_BUSNUM_LIST1 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5__SHIFT 0x8 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6__SHIFT 0x10 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7__SHIFT 0x18 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L +//RCC_DEV0_1_RCC_BUSNUM_CNTL2 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L +//RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM +#define RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L +//RCC_DEV0_1_RCC_HOST_BUSNUM +#define RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0 +#define RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL +//RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000FF00L +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00FF0000L +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xFF000000L +//RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000FF00L +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00FF0000L +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xFF000000L +//RCC_DEV0_2_RCC_DEV0_LINK_CNTL +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT 0x10 +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT 0x11 +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK 0x00010000L +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK 0x00020000L +//RCC_DEV0_2_RCC_CMN_LINK_CNTL +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L +//RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L +//RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL +#define RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 +#define RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL +//RCC_DEV0_2_RCC_MH_ARB_CNTL +#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 +#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 +#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L +#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL + + +// addressBlock: aid_nbio_nbif0_bif_bx_SYSDEC +//BIF_BX1_PCIE_INDEX +#define BIF_BX1_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 +#define BIF_BX1_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL +//BIF_BX1_PCIE_DATA +#define BIF_BX1_PCIE_DATA__PCIE_DATA__SHIFT 0x0 +#define BIF_BX1_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL +//BIF_BX1_PCIE_INDEX2 +#define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 +#define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL +//BIF_BX1_PCIE_DATA2 +#define BIF_BX1_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 +#define BIF_BX1_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL +//BIF_BX1_PCIE_INDEX_HI +#define BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT 0x0 +#define BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK 0x000000FFL +//BIF_BX1_PCIE_INDEX2_HI +#define BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT 0x0 +#define BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK 0x000000FFL +//BIF_BX1_SBIOS_SCRATCH_0 +#define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_1 +#define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_2 +#define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_3 +#define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_0 +#define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_1 +#define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_2 +#define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_3 +#define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_4 +#define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_5 +#define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_6 +#define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_7 +#define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_8 +#define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_9 +#define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_10 +#define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_11 +#define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_12 +#define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_13 +#define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_14 +#define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_15 +#define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX1_BIF_RLC_INTR_CNTL +//BIF_BX1_BIF_VCE_INTR_CNTL +//BIF_BX1_BIF_UVD_INTR_CNTL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR1 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR2 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR3 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR4 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR5 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR6 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR7 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_CNTL +#define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL +//BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL +#define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL +#define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL +#define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_0 +#define BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_1 +#define BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_2 +#define BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_3 +#define BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_4 +#define BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_5 +#define BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_6 +#define BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_7 +#define BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_8 +#define BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_9 +#define BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_10 +#define BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_11 +#define BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_12 +#define BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_13 +#define BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_14 +#define BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_15 +#define BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_0 +#define BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_1 +#define BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_2 +#define BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_3 +#define BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_4 +#define BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_5 +#define BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_6 +#define BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_7 +#define BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_8 +#define BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_9 +#define BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_10 +#define BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_11 +#define BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_12 +#define BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_13 +#define BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_14 +#define BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_15 +#define BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_4 +#define BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_5 +#define BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_6 +#define BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_7 +#define BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_8 +#define BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_9 +#define BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_10 +#define BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_11 +#define BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_12 +#define BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_13 +#define BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_14 +#define BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_15 +#define BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_bif_bx_pf_SYSPFVFDEC +//BIF_BX_PF1_MM_INDEX +#define BIF_BX_PF1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_PF1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_PF1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_PF1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_PF1_MM_DATA +#define BIF_BX_PF1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MM_INDEX_HI +#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_bif_bx_BIFDEC1 +//BIF_BX1_CC_BIF_BX_STRAP0 +#define BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT 0x19 +#define BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK 0xFE000000L +//BIF_BX1_CC_BIF_BX_PINSTRAP0 +//BIF_BX1_BIF_MM_INDACCESS_CNTL +#define BIF_BX1_BIF_MM_INDACCESS_CNTL__WRITE_DIS__SHIFT 0x0 +#define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 +#define BIF_BX1_BIF_MM_INDACCESS_CNTL__WRITE_DIS_MASK 0x00000001L +#define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L +//BIF_BX1_BUS_CNTL +#define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 +#define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 +#define BIF_BX1_BUS_CNTL__SET_AZ_TC__SHIFT 0xa +#define BIF_BX1_BUS_CNTL__SET_MC_TC__SHIFT 0xd +#define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 +#define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 +#define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 +#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT 0x18 +#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19 +#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a +#define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT 0x1b +#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT 0x1c +#define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d +#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e +#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f +#define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L +#define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L +#define BIF_BX1_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L +#define BIF_BX1_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L +#define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L +#define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L +#define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L +#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK 0x01000000L +#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L +#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L +#define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK 0x08000000L +#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK 0x10000000L +#define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L +#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L +#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L +//BIF_BX1_BIF_SCRATCH0 +#define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 +#define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL +//BIF_BX1_BIF_SCRATCH1 +#define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 +#define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL +//BIF_BX1_BX_RESET_EN +#define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 +#define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L +//BIF_BX1_MM_CFGREGS_CNTL +#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 +#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 +#define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f +#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L +#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L +#define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L +//BIF_BX1_BX_RESET_CNTL +#define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 +#define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L +//BIF_BX1_INTERRUPT_CNTL +#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 +#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 +#define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 +#define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 +#define BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 +#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf +#define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10 +#define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11 +#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12 +#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L +#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L +#define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L +#define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L +#define BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L +#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L +#define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L +#define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L +#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L +//BIF_BX1_INTERRUPT_CNTL2 +#define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 +#define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL +//BIF_BX1_CLKREQB_PAD_CNTL +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L +//BIF_BX1_BIF_FEATURES_CONTROL_MISC +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT 0xb +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS__SHIFT 0xe +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT 0x10 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x19 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK 0x00000800L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS_MASK 0x00004000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK 0x01FF0000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x02000000L +//BIF_BX1_HDP_ATOMIC_CONTROL_MISC +#define BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT 0x0 +#define BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK 0x000000FFL +//BIF_BX1_BIF_DOORBELL_CNTL +#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 +#define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 +#define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 +#define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 +#define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b +#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L +#define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L +#define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L +#define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L +#define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L +//BIF_BX1_BIF_DOORBELL_INT_CNTL +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x17 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x1f +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x00800000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x80000000L +//BIF_BX1_BIF_FB_EN +#define BIF_BX1_BIF_FB_EN__FB_READ_EN__SHIFT 0x0 +#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 +#define BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L +#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L +//BIF_BX1_BIF_INTR_CNTL +#define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0 +#define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L +//BIF_BX1_BIF_MST_TRANS_PENDING_VF +#define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL +//BIF_BX1_BIF_SLV_TRANS_PENDING_VF +#define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x7FFFFFFFL +//BIF_BX1_BACO_CNTL +#define BIF_BX1_BACO_CNTL__BACO_EN__SHIFT 0x0 +#define BIF_BX1_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 +#define BIF_BX1_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 +#define BIF_BX1_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 +#define BIF_BX1_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 +#define BIF_BX1_BACO_CNTL__BACO_MODE__SHIFT 0x8 +#define BIF_BX1_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 +#define BIF_BX1_BACO_CNTL__PWRGOOD_VDDSOC__SHIFT 0x10 +#define BIF_BX1_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f +#define BIF_BX1_BACO_CNTL__BACO_EN_MASK 0x00000001L +#define BIF_BX1_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L +#define BIF_BX1_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L +#define BIF_BX1_BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L +#define BIF_BX1_BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L +#define BIF_BX1_BACO_CNTL__BACO_MODE_MASK 0x00000100L +#define BIF_BX1_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L +#define BIF_BX1_BACO_CNTL__PWRGOOD_VDDSOC_MASK 0x00010000L +#define BIF_BX1_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L +//BIF_BX1_BIF_BACO_EXIT_TIME0 +#define BIF_BX1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX1_BIF_BACO_EXIT_TIMER1 +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18 +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L +//BIF_BX1_BIF_BACO_EXIT_TIMER2 +#define BIF_BX1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 +#define BIF_BX1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL +//BIF_BX1_BIF_BACO_EXIT_TIMER3 +#define BIF_BX1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX1_BIF_BACO_EXIT_TIMER4 +#define BIF_BX1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX1_MEM_TYPE_CNTL +#define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 +#define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L +//BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT 0x1 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT 0x8 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK 0x00000001L +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK 0x00000002L +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK 0x00000100L +//BIF_BX1_NBIF_GFX_ADDR_LUT_0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_1 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_2 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_3 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_4 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_5 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_6 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_7 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_8 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_9 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_10 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_11 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_12 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_13 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_14 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_15 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_VF_REGWR_EN +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0__SHIFT 0x0 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1__SHIFT 0x1 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2__SHIFT 0x2 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3__SHIFT 0x3 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4__SHIFT 0x4 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5__SHIFT 0x5 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6__SHIFT 0x6 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7__SHIFT 0x7 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8__SHIFT 0x8 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9__SHIFT 0x9 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10__SHIFT 0xa +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11__SHIFT 0xb +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12__SHIFT 0xc +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13__SHIFT 0xd +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14__SHIFT 0xe +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15__SHIFT 0xf +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16__SHIFT 0x10 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17__SHIFT 0x11 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18__SHIFT 0x12 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19__SHIFT 0x13 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20__SHIFT 0x14 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21__SHIFT 0x15 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22__SHIFT 0x16 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23__SHIFT 0x17 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24__SHIFT 0x18 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25__SHIFT 0x19 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26__SHIFT 0x1a +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27__SHIFT 0x1b +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28__SHIFT 0x1c +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29__SHIFT 0x1d +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30__SHIFT 0x1e +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0_MASK 0x00000001L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1_MASK 0x00000002L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2_MASK 0x00000004L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3_MASK 0x00000008L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4_MASK 0x00000010L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5_MASK 0x00000020L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6_MASK 0x00000040L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7_MASK 0x00000080L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8_MASK 0x00000100L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9_MASK 0x00000200L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10_MASK 0x00000400L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11_MASK 0x00000800L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12_MASK 0x00001000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13_MASK 0x00002000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14_MASK 0x00004000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15_MASK 0x00008000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16_MASK 0x00010000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17_MASK 0x00020000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18_MASK 0x00040000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19_MASK 0x00080000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20_MASK 0x00100000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21_MASK 0x00200000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22_MASK 0x00400000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23_MASK 0x00800000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24_MASK 0x01000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25_MASK 0x02000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26_MASK 0x04000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27_MASK 0x08000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28_MASK 0x10000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29_MASK 0x20000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30_MASK 0x40000000L +//BIF_BX1_VF_DOORBELL_EN +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0__SHIFT 0x0 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1__SHIFT 0x1 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2__SHIFT 0x2 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3__SHIFT 0x3 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4__SHIFT 0x4 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5__SHIFT 0x5 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6__SHIFT 0x6 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7__SHIFT 0x7 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8__SHIFT 0x8 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9__SHIFT 0x9 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10__SHIFT 0xa +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11__SHIFT 0xb +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12__SHIFT 0xc +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13__SHIFT 0xd +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14__SHIFT 0xe +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15__SHIFT 0xf +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16__SHIFT 0x10 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17__SHIFT 0x11 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18__SHIFT 0x12 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19__SHIFT 0x13 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20__SHIFT 0x14 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21__SHIFT 0x15 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22__SHIFT 0x16 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23__SHIFT 0x17 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24__SHIFT 0x18 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25__SHIFT 0x19 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26__SHIFT 0x1a +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27__SHIFT 0x1b +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28__SHIFT 0x1c +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29__SHIFT 0x1d +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30__SHIFT 0x1e +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS__SHIFT 0x1f +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0_MASK 0x00000001L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1_MASK 0x00000002L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2_MASK 0x00000004L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3_MASK 0x00000008L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4_MASK 0x00000010L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5_MASK 0x00000020L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6_MASK 0x00000040L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7_MASK 0x00000080L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8_MASK 0x00000100L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9_MASK 0x00000200L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10_MASK 0x00000400L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11_MASK 0x00000800L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12_MASK 0x00001000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13_MASK 0x00002000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14_MASK 0x00004000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15_MASK 0x00008000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16_MASK 0x00010000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17_MASK 0x00020000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18_MASK 0x00040000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19_MASK 0x00080000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20_MASK 0x00100000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21_MASK 0x00200000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22_MASK 0x00400000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23_MASK 0x00800000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24_MASK 0x01000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25_MASK 0x02000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26_MASK 0x04000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27_MASK 0x08000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28_MASK 0x10000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29_MASK 0x20000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30_MASK 0x40000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS_MASK 0x80000000L +//BIF_BX1_VF_FB_EN +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF0__SHIFT 0x0 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF1__SHIFT 0x1 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF2__SHIFT 0x2 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF3__SHIFT 0x3 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF4__SHIFT 0x4 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF5__SHIFT 0x5 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF6__SHIFT 0x6 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF7__SHIFT 0x7 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF8__SHIFT 0x8 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF9__SHIFT 0x9 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF10__SHIFT 0xa +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF11__SHIFT 0xb +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF12__SHIFT 0xc +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF13__SHIFT 0xd +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF14__SHIFT 0xe +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF15__SHIFT 0xf +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF16__SHIFT 0x10 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF17__SHIFT 0x11 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF18__SHIFT 0x12 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF19__SHIFT 0x13 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF20__SHIFT 0x14 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF21__SHIFT 0x15 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF22__SHIFT 0x16 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF23__SHIFT 0x17 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF24__SHIFT 0x18 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF25__SHIFT 0x19 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF26__SHIFT 0x1a +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF27__SHIFT 0x1b +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF28__SHIFT 0x1c +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF29__SHIFT 0x1d +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF30__SHIFT 0x1e +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF0_MASK 0x00000001L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF1_MASK 0x00000002L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF2_MASK 0x00000004L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF3_MASK 0x00000008L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF4_MASK 0x00000010L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF5_MASK 0x00000020L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF6_MASK 0x00000040L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF7_MASK 0x00000080L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF8_MASK 0x00000100L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF9_MASK 0x00000200L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF10_MASK 0x00000400L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF11_MASK 0x00000800L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF12_MASK 0x00001000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF13_MASK 0x00002000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF14_MASK 0x00004000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF15_MASK 0x00008000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF16_MASK 0x00010000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF17_MASK 0x00020000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF18_MASK 0x00040000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF19_MASK 0x00080000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF20_MASK 0x00100000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF21_MASK 0x00200000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF22_MASK 0x00400000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF23_MASK 0x00800000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF24_MASK 0x01000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF25_MASK 0x02000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF26_MASK 0x04000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF27_MASK 0x08000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF28_MASK 0x10000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF29_MASK 0x20000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF30_MASK 0x40000000L +//BIF_BX1_VF_REGWR_STATUS +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0__SHIFT 0x0 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1__SHIFT 0x1 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2__SHIFT 0x2 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3__SHIFT 0x3 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4__SHIFT 0x4 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5__SHIFT 0x5 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6__SHIFT 0x6 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7__SHIFT 0x7 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8__SHIFT 0x8 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9__SHIFT 0x9 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10__SHIFT 0xa +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11__SHIFT 0xb +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12__SHIFT 0xc +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13__SHIFT 0xd +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14__SHIFT 0xe +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15__SHIFT 0xf +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16__SHIFT 0x10 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17__SHIFT 0x11 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18__SHIFT 0x12 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19__SHIFT 0x13 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20__SHIFT 0x14 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21__SHIFT 0x15 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22__SHIFT 0x16 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23__SHIFT 0x17 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24__SHIFT 0x18 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25__SHIFT 0x19 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26__SHIFT 0x1a +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27__SHIFT 0x1b +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28__SHIFT 0x1c +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29__SHIFT 0x1d +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30__SHIFT 0x1e +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0_MASK 0x00000001L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1_MASK 0x00000002L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2_MASK 0x00000004L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3_MASK 0x00000008L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4_MASK 0x00000010L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5_MASK 0x00000020L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6_MASK 0x00000040L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7_MASK 0x00000080L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8_MASK 0x00000100L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9_MASK 0x00000200L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10_MASK 0x00000400L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11_MASK 0x00000800L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12_MASK 0x00001000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13_MASK 0x00002000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14_MASK 0x00004000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15_MASK 0x00008000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16_MASK 0x00010000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17_MASK 0x00020000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18_MASK 0x00040000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19_MASK 0x00080000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20_MASK 0x00100000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21_MASK 0x00200000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22_MASK 0x00400000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23_MASK 0x00800000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24_MASK 0x01000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25_MASK 0x02000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26_MASK 0x04000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27_MASK 0x08000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28_MASK 0x10000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29_MASK 0x20000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30_MASK 0x40000000L +//BIF_BX1_VF_DOORBELL_STATUS +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0__SHIFT 0x0 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1__SHIFT 0x1 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2__SHIFT 0x2 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3__SHIFT 0x3 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4__SHIFT 0x4 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5__SHIFT 0x5 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6__SHIFT 0x6 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7__SHIFT 0x7 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8__SHIFT 0x8 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9__SHIFT 0x9 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10__SHIFT 0xa +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11__SHIFT 0xb +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12__SHIFT 0xc +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13__SHIFT 0xd +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14__SHIFT 0xe +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15__SHIFT 0xf +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16__SHIFT 0x10 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17__SHIFT 0x11 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18__SHIFT 0x12 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19__SHIFT 0x13 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20__SHIFT 0x14 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21__SHIFT 0x15 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22__SHIFT 0x16 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23__SHIFT 0x17 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24__SHIFT 0x18 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25__SHIFT 0x19 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26__SHIFT 0x1a +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27__SHIFT 0x1b +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28__SHIFT 0x1c +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29__SHIFT 0x1d +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30__SHIFT 0x1e +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0_MASK 0x00000001L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1_MASK 0x00000002L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2_MASK 0x00000004L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3_MASK 0x00000008L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4_MASK 0x00000010L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5_MASK 0x00000020L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6_MASK 0x00000040L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7_MASK 0x00000080L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8_MASK 0x00000100L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9_MASK 0x00000200L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10_MASK 0x00000400L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11_MASK 0x00000800L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12_MASK 0x00001000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13_MASK 0x00002000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14_MASK 0x00004000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15_MASK 0x00008000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16_MASK 0x00010000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17_MASK 0x00020000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18_MASK 0x00040000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19_MASK 0x00080000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20_MASK 0x00100000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21_MASK 0x00200000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22_MASK 0x00400000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23_MASK 0x00800000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24_MASK 0x01000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25_MASK 0x02000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26_MASK 0x04000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27_MASK 0x08000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28_MASK 0x10000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29_MASK 0x20000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30_MASK 0x40000000L +//BIF_BX1_VF_FB_STATUS +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0__SHIFT 0x0 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1__SHIFT 0x1 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2__SHIFT 0x2 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3__SHIFT 0x3 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4__SHIFT 0x4 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5__SHIFT 0x5 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6__SHIFT 0x6 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7__SHIFT 0x7 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8__SHIFT 0x8 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9__SHIFT 0x9 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10__SHIFT 0xa +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11__SHIFT 0xb +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12__SHIFT 0xc +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13__SHIFT 0xd +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14__SHIFT 0xe +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15__SHIFT 0xf +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16__SHIFT 0x10 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17__SHIFT 0x11 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18__SHIFT 0x12 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19__SHIFT 0x13 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20__SHIFT 0x14 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21__SHIFT 0x15 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22__SHIFT 0x16 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23__SHIFT 0x17 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24__SHIFT 0x18 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25__SHIFT 0x19 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26__SHIFT 0x1a +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27__SHIFT 0x1b +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28__SHIFT 0x1c +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29__SHIFT 0x1d +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30__SHIFT 0x1e +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0_MASK 0x00000001L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1_MASK 0x00000002L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2_MASK 0x00000004L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3_MASK 0x00000008L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4_MASK 0x00000010L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5_MASK 0x00000020L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6_MASK 0x00000040L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7_MASK 0x00000080L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8_MASK 0x00000100L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9_MASK 0x00000200L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10_MASK 0x00000400L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11_MASK 0x00000800L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12_MASK 0x00001000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13_MASK 0x00002000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14_MASK 0x00004000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15_MASK 0x00008000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16_MASK 0x00010000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17_MASK 0x00020000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18_MASK 0x00040000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19_MASK 0x00080000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20_MASK 0x00100000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21_MASK 0x00200000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22_MASK 0x00400000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23_MASK 0x00800000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24_MASK 0x01000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25_MASK 0x02000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26_MASK 0x04000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27_MASK 0x08000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28_MASK 0x10000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29_MASK 0x20000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30_MASK 0x40000000L +//BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL +#define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL +#define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX1_BIF_RB_CNTL +#define BIF_BX1_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define BIF_BX1_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 +#define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 +#define BIF_BX1_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL__SHIFT 0x19 +#define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT 0x1a +#define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT 0x1d +#define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT 0x1e +#define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define BIF_BX1_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define BIF_BX1_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L +#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L +#define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L +#define BIF_BX1_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL_MASK 0x02000000L +#define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK 0x1C000000L +#define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK 0x20000000L +#define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK 0x40000000L +#define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L +//BIF_BX1_BIF_RB_BASE +#define BIF_BX1_BIF_RB_BASE__ADDR__SHIFT 0x0 +#define BIF_BX1_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//BIF_BX1_BIF_RB_RPTR +#define BIF_BX1_BIF_RB_RPTR__OFFSET__SHIFT 0x2 +#define BIF_BX1_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX1_BIF_RB_WPTR +#define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 +#define BIF_BX1_BIF_RB_WPTR__OFFSET__SHIFT 0x2 +#define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L +#define BIF_BX1_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX1_BIF_RB_WPTR_ADDR_HI +#define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL +//BIF_BX1_BIF_RB_WPTR_ADDR_LO +#define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//BIF_BX1_MAILBOX_INDEX +#define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 +#define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL +//BIF_BX1_BIF_MP1_INTR_CTRL +#define BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT 0x0 +#define BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK 0x00000001L +//BIF_BX1_BIF_PERSTB_PAD_CNTL +#define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL +//BIF_BX1_BIF_PX_EN_PAD_CNTL +#define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x00000FFFL +//BIF_BX1_BIF_REFPADKIN_PAD_CNTL +#define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL +//BIF_BX1_BIF_CLKREQB_PAD_CNTL +#define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x7FFFFFFFL +//BIF_BX1_BIF_PWRBRK_PAD_CNTL +#define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK 0x000000FFL +//BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE +#define BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE__SHIFT 0x0 +#define BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE_MASK 0x0000000FL +//BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE +#define BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE__SHIFT 0x0 +#define BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE_MASK 0x0000000FL + + +// addressBlock: aid_nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +//BIF_BX_PF1_BIF_BME_STATUS +#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_PF1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF1_GPU_HDP_FLUSH_REQ +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF1_GPU_HDP_FLUSH_DONE +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF1_BIF_TRANS_PENDING +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_CONTROL +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_PF1_MAILBOX_INT_CNTL +#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_PF1_BIF_VMHV_MAILBOX +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_PF1_PARTITION_COMPUTE_CAP +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_PF1_PARTITION_MEM_CAP +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_PF1_PARTITION_COMPUTE_STATUS +#define BIF_BX_PF1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_PF1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_PF1_PARTITION_MEM_STATUS +#define BIF_BX_PF1_PARTITION_MEM_STATUS__CHANGE_STATUE__SHIFT 0x0 +#define BIF_BX_PF1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_PF1_PARTITION_MEM_STATUS__CHANGE_STATUE_MASK 0x0000000FL +#define BIF_BX_PF1_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: aid_nbio_nbif0_rcc_strap_BIFDEC1:1 +//RCC_STRAP2_RCC_BIF_STRAP0 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT 0x1 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x6 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT 0x1c +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK 0x00000001L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK 0x00000002L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000038L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00000040L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK 0x10000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L +//RCC_STRAP2_RCC_BIF_STRAP1 +#define RCC_STRAP2_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1 +#define RCC_STRAP2_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x2 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT 0x18 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT 0x19 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT 0x1e +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT 0x1f +#define RCC_STRAP2_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L +#define RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L +#define RCC_STRAP2_RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK 0x01000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK 0x02000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_MASK 0x40000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK 0x80000000L +//RCC_STRAP2_RCC_BIF_STRAP2 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN__SHIFT 0x7 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa +#define RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN_MASK 0x00000080L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L +#define RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L +//RCC_STRAP2_RCC_BIF_STRAP3 +#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_BIF_STRAP4 +#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_BIF_STRAP5 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT 0x15 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK 0x00200000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L +//RCC_STRAP2_RCC_BIF_STRAP6 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT 0x1 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT 0x2 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK 0x00000001L +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK 0x00000002L +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK 0x00000004L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT 0x5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK 0x00000020L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK 0x0007FFC0L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP11 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK 0x0FFF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK 0x40000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK 0x00FFFFFFL +//RCC_STRAP2_RCC_DEV0_PORT_STRAP13 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK 0x000FFE00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK 0xFFF00000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK 0x00000010L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x00E00000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x0F000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0xF0000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP1 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP13 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0xFF000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK 0x00FFF000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK 0x3E000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK 0x40000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK 0x00FFF000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP17 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT 0xd +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK 0x00001000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK 0x01FFE000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK 0x00000FFFL +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP2 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP26 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK 0x00000FFFL +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP3 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP4 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT 0xa +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK 0x00000400L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP5 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP8 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00780000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP9 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP2 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK 0x00800000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP20 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP21 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP22 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP23 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP24 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP25 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP3 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP4 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP5 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK 0x38000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP6 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP7 + + +// addressBlock: aid_nbio_nbif0_gdc_hst_sion_SIONDEC +//S2A_DOORBELL_ENTRY_0_CTRL +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_1_CTRL +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_2_CTRL +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_3_CTRL +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_4_CTRL +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_5_CTRL +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_6_CTRL +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_7_CTRL +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_8_CTRL +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_9_CTRL +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_10_CTRL +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_11_CTRL +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_12_CTRL +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_13_CTRL +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_14_CTRL +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_15_CTRL +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_COMMON_CTRL_REG +#define S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT 0x0 +#define S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK 0x00000001L + + +// addressBlock: aid_nbio_nbif0_gdc_GDCDEC +//GDC1_A2S_CNTL_CL0 +#define GDC1_A2S_CNTL_CL0__NSNOOP_MAP__SHIFT 0x0 +#define GDC1_A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT 0x2 +#define GDC1_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT 0x4 +#define GDC1_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 +#define GDC1_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 +#define GDC1_A2S_CNTL_CL0__BLKLVL_MAP__SHIFT 0xa +#define GDC1_A2S_CNTL_CL0__DATERR_MAP__SHIFT 0xc +#define GDC1_A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT 0xe +#define GDC1_A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT 0x10 +#define GDC1_A2S_CNTL_CL0__RESP_WR_MAP__SHIFT 0x12 +#define GDC1_A2S_CNTL_CL0__RESP_RD_MAP__SHIFT 0x14 +#define GDC1_A2S_CNTL_CL0__RDRSP_ERRMAP__SHIFT 0x16 +#define GDC1_A2S_CNTL_CL0__RDRSP_SEL_MODE__SHIFT 0x18 +#define GDC1_A2S_CNTL_CL0__STATIC_VC_ENABLE__SHIFT 0x1b +#define GDC1_A2S_CNTL_CL0__STATIC_VC_VALUE__SHIFT 0x1c +#define GDC1_A2S_CNTL_CL0__NSNOOP_MAP_MASK 0x00000003L +#define GDC1_A2S_CNTL_CL0__REQPASSPW_VC0_MAP_MASK 0x0000000CL +#define GDC1_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP_MASK 0x00000030L +#define GDC1_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP_MASK 0x000000C0L +#define GDC1_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP_MASK 0x00000300L +#define GDC1_A2S_CNTL_CL0__BLKLVL_MAP_MASK 0x00000C00L +#define GDC1_A2S_CNTL_CL0__DATERR_MAP_MASK 0x00003000L +#define GDC1_A2S_CNTL_CL0__EXOKAY_WR_MAP_MASK 0x0000C000L +#define GDC1_A2S_CNTL_CL0__EXOKAY_RD_MAP_MASK 0x00030000L +#define GDC1_A2S_CNTL_CL0__RESP_WR_MAP_MASK 0x000C0000L +#define GDC1_A2S_CNTL_CL0__RESP_RD_MAP_MASK 0x00300000L +#define GDC1_A2S_CNTL_CL0__RDRSP_ERRMAP_MASK 0x00C00000L +#define GDC1_A2S_CNTL_CL0__RDRSP_SEL_MODE_MASK 0x07000000L +#define GDC1_A2S_CNTL_CL0__STATIC_VC_ENABLE_MASK 0x08000000L +#define GDC1_A2S_CNTL_CL0__STATIC_VC_VALUE_MASK 0x70000000L +//GDC1_A2S_CNTL_CL1 +#define GDC1_A2S_CNTL_CL1__NSNOOP_MAP__SHIFT 0x0 +#define GDC1_A2S_CNTL_CL1__REQPASSPW_VC0_MAP__SHIFT 0x2 +#define GDC1_A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__SHIFT 0x4 +#define GDC1_A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 +#define GDC1_A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 +#define GDC1_A2S_CNTL_CL1__BLKLVL_MAP__SHIFT 0xa +#define GDC1_A2S_CNTL_CL1__DATERR_MAP__SHIFT 0xc +#define GDC1_A2S_CNTL_CL1__EXOKAY_WR_MAP__SHIFT 0xe +#define GDC1_A2S_CNTL_CL1__EXOKAY_RD_MAP__SHIFT 0x10 +#define GDC1_A2S_CNTL_CL1__RESP_WR_MAP__SHIFT 0x12 +#define GDC1_A2S_CNTL_CL1__RESP_RD_MAP__SHIFT 0x14 +#define GDC1_A2S_CNTL_CL1__RDRSP_ERRMAP__SHIFT 0x16 +#define GDC1_A2S_CNTL_CL1__RDRSP_SEL_MODE__SHIFT 0x18 +#define GDC1_A2S_CNTL_CL1__STATIC_VC_ENABLE__SHIFT 0x1b +#define GDC1_A2S_CNTL_CL1__STATIC_VC_VALUE__SHIFT 0x1c +#define GDC1_A2S_CNTL_CL1__NSNOOP_MAP_MASK 0x00000003L +#define GDC1_A2S_CNTL_CL1__REQPASSPW_VC0_MAP_MASK 0x0000000CL +#define GDC1_A2S_CNTL_CL1__REQPASSPW_NVC0_MAP_MASK 0x00000030L +#define GDC1_A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP_MASK 0x000000C0L +#define GDC1_A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP_MASK 0x00000300L +#define GDC1_A2S_CNTL_CL1__BLKLVL_MAP_MASK 0x00000C00L +#define GDC1_A2S_CNTL_CL1__DATERR_MAP_MASK 0x00003000L +#define GDC1_A2S_CNTL_CL1__EXOKAY_WR_MAP_MASK 0x0000C000L +#define GDC1_A2S_CNTL_CL1__EXOKAY_RD_MAP_MASK 0x00030000L +#define GDC1_A2S_CNTL_CL1__RESP_WR_MAP_MASK 0x000C0000L +#define GDC1_A2S_CNTL_CL1__RESP_RD_MAP_MASK 0x00300000L +#define GDC1_A2S_CNTL_CL1__RDRSP_ERRMAP_MASK 0x00C00000L +#define GDC1_A2S_CNTL_CL1__RDRSP_SEL_MODE_MASK 0x07000000L +#define GDC1_A2S_CNTL_CL1__STATIC_VC_ENABLE_MASK 0x08000000L +#define GDC1_A2S_CNTL_CL1__STATIC_VC_VALUE_MASK 0x70000000L +//GDC1_A2S_CNTL3_CL0 +#define GDC1_A2S_CNTL3_CL0__FORCE_WR_PH__SHIFT 0x0 +#define GDC1_A2S_CNTL3_CL0__FORCE_WR_STEERING__SHIFT 0x2 +#define GDC1_A2S_CNTL3_CL0__WR_ST_TAG_MODE__SHIFT 0x3 +#define GDC1_A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY__SHIFT 0x4 +#define GDC1_A2S_CNTL3_CL0__FORCE_WR_PH_MASK 0x00000003L +#define GDC1_A2S_CNTL3_CL0__FORCE_WR_STEERING_MASK 0x00000004L +#define GDC1_A2S_CNTL3_CL0__WR_ST_TAG_MODE_MASK 0x00000008L +#define GDC1_A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY_MASK 0x000003F0L +//GDC1_A2S_CNTL3_CL1 +#define GDC1_A2S_CNTL3_CL1__FORCE_WR_PH__SHIFT 0x0 +#define GDC1_A2S_CNTL3_CL1__FORCE_WR_STEERING__SHIFT 0x2 +#define GDC1_A2S_CNTL3_CL1__WR_ST_TAG_MODE__SHIFT 0x3 +#define GDC1_A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY__SHIFT 0x4 +#define GDC1_A2S_CNTL3_CL1__FORCE_WR_PH_MASK 0x00000003L +#define GDC1_A2S_CNTL3_CL1__FORCE_WR_STEERING_MASK 0x00000004L +#define GDC1_A2S_CNTL3_CL1__WR_ST_TAG_MODE_MASK 0x00000008L +#define GDC1_A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY_MASK 0x000003F0L +//GDC1_A2S_CNTL_SW0 +#define GDC1_A2S_CNTL_SW0__STATIC_VC_ENABLE__SHIFT 0x0 +#define GDC1_A2S_CNTL_SW0__STATIC_VC_VALUE__SHIFT 0x1 +#define GDC1_A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__SHIFT 0x6 +#define GDC1_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define GDC1_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define GDC1_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define GDC1_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define GDC1_A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT 0x10 +#define GDC1_A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT 0x18 +#define GDC1_A2S_CNTL_SW0__STATIC_VC_ENABLE_MASK 0x00000001L +#define GDC1_A2S_CNTL_SW0__STATIC_VC_VALUE_MASK 0x0000000EL +#define GDC1_A2S_CNTL_SW0__FORCE_RSP_REORDER_EN_MASK 0x00000040L +#define GDC1_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define GDC1_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define GDC1_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define GDC1_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define GDC1_A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define GDC1_A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK 0xFF000000L +//GDC1_A2S_CNTL_SW1 +#define GDC1_A2S_CNTL_SW1__STATIC_VC_ENABLE__SHIFT 0x0 +#define GDC1_A2S_CNTL_SW1__STATIC_VC_VALUE__SHIFT 0x1 +#define GDC1_A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__SHIFT 0x6 +#define GDC1_A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define GDC1_A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define GDC1_A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define GDC1_A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define GDC1_A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT 0x10 +#define GDC1_A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT 0x18 +#define GDC1_A2S_CNTL_SW1__STATIC_VC_ENABLE_MASK 0x00000001L +#define GDC1_A2S_CNTL_SW1__STATIC_VC_VALUE_MASK 0x0000000EL +#define GDC1_A2S_CNTL_SW1__FORCE_RSP_REORDER_EN_MASK 0x00000040L +#define GDC1_A2S_CNTL_SW1__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define GDC1_A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define GDC1_A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define GDC1_A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define GDC1_A2S_CNTL_SW1__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define GDC1_A2S_CNTL_SW1__WRR_WR_WEIGHT_MASK 0xFF000000L +//GDC1_A2S_CNTL_SW2 +#define GDC1_A2S_CNTL_SW2__STATIC_VC_ENABLE__SHIFT 0x0 +#define GDC1_A2S_CNTL_SW2__STATIC_VC_VALUE__SHIFT 0x1 +#define GDC1_A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__SHIFT 0x6 +#define GDC1_A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define GDC1_A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define GDC1_A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define GDC1_A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define GDC1_A2S_CNTL_SW2__WRR_RD_WEIGHT__SHIFT 0x10 +#define GDC1_A2S_CNTL_SW2__WRR_WR_WEIGHT__SHIFT 0x18 +#define GDC1_A2S_CNTL_SW2__STATIC_VC_ENABLE_MASK 0x00000001L +#define GDC1_A2S_CNTL_SW2__STATIC_VC_VALUE_MASK 0x0000000EL +#define GDC1_A2S_CNTL_SW2__FORCE_RSP_REORDER_EN_MASK 0x00000040L +#define GDC1_A2S_CNTL_SW2__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define GDC1_A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define GDC1_A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define GDC1_A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define GDC1_A2S_CNTL_SW2__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define GDC1_A2S_CNTL_SW2__WRR_WR_WEIGHT_MASK 0xFF000000L +//GDC1_A2S_TAG_ALLOC_0 +#define GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT 0x0 +#define GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT 0x8 +#define GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT 0x10 +#define GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK 0x000000FFL +#define GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK 0x0000FF00L +#define GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK 0x00FF0000L +//GDC1_A2S_TAG_ALLOC_1 +#define GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT 0x0 +#define GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT 0x10 +#define GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT 0x18 +#define GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK 0x000000FFL +#define GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK 0x00FF0000L +#define GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK 0xFF000000L +//GDC1_A2S_MISC_CNTL +#define GDC1_A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT 0x0 +#define GDC1_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT 0x2 +#define GDC1_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE__SHIFT 0x3 +#define GDC1_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN__SHIFT 0x4 +#define GDC1_A2S_MISC_CNTL__RSP_REORDER_DIS__SHIFT 0x5 +#define GDC1_A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT 0x6 +#define GDC1_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x7 +#define GDC1_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x8 +#define GDC1_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0x9 +#define GDC1_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0xa +#define GDC1_A2S_MISC_CNTL__WR_TAG_SET_MIN__SHIFT 0x10 +#define GDC1_A2S_MISC_CNTL__RD_TAG_SET_MIN__SHIFT 0x15 +#define GDC1_A2S_MISC_CNTL__WRR_LRG_MODE__SHIFT 0x1a +#define GDC1_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE__SHIFT 0x1b +#define GDC1_A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK 0x00000003L +#define GDC1_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS_MASK 0x00000004L +#define GDC1_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE_MASK 0x00000008L +#define GDC1_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN_MASK 0x00000010L +#define GDC1_A2S_MISC_CNTL__RSP_REORDER_DIS_MASK 0x00000020L +#define GDC1_A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK 0x00000040L +#define GDC1_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000080L +#define GDC1_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000100L +#define GDC1_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY_MASK 0x00000200L +#define GDC1_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000400L +#define GDC1_A2S_MISC_CNTL__WR_TAG_SET_MIN_MASK 0x001F0000L +#define GDC1_A2S_MISC_CNTL__RD_TAG_SET_MIN_MASK 0x03E00000L +#define GDC1_A2S_MISC_CNTL__WRR_LRG_MODE_MASK 0x04000000L +#define GDC1_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE_MASK 0x08000000L +//GDC1_SHUB_REGS_IF_CTL +#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 +#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS__SHIFT 0x1 +#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L +#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS_MASK 0x00000002L +//GDC1_NGDC_MGCG_CTRL +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x0 +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x1 +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x2 +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT 0xa +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT 0xb +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT 0xc +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT 0xd +#define GDC1_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN__SHIFT 0xe +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK 0x00000001L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK 0x00000002L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK 0x000003FCL +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK 0x00000400L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK 0x00000800L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK 0x00001000L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK 0x00002000L +#define GDC1_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN_MASK 0x00004000L +//GDC1_NGDC_RESERVED_0 +#define GDC1_NGDC_RESERVED_0__RESERVED__SHIFT 0x0 +#define GDC1_NGDC_RESERVED_0__RESERVED_MASK 0xFFFFFFFFL +//GDC1_NGDC_RESERVED_1 +#define GDC1_NGDC_RESERVED_1__RESERVED__SHIFT 0x0 +#define GDC1_NGDC_RESERVED_1__RESERVED_MASK 0xFFFFFFFFL +//GDC1_NBIF_GFX_DOORBELL_STATUS +#define GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT 0x0 +#define GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK 0x0000FFFFL +//GDC1_ATDMA_MISC_CNTL +#define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0 +#define GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1 +#define GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT 0x2 +#define GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT 0x8 +#define GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT 0x10 +#define GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT 0x18 +#define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000001L +#define GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L +#define GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK 0x0000000CL +#define GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK 0x0000FF00L +#define GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK 0x00FF0000L +#define GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK 0xFF000000L +//GDC1_S2A_MISC_CNTL +#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3 +#define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT 0x8 +#define GDC1_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT 0xa +#define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT 0xc +#define GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT 0xf +#define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT 0x10 +#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L +#define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE_MASK 0x00000300L +#define GDC1_S2A_MISC_CNTL__RB_ARB_MODE_MASK 0x00000C00L +#define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK 0x00003000L +#define GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK 0x00008000L +#define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK 0x000F0000L +//GDC1_NGDC_EARLY_WAKEUP_CTRL +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0x0 +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0x1 +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0x2 +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000001L +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00000002L +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00000004L +//GDC1_NGDC_PG_MISC_CTRL +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY__SHIFT 0xa +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1__SHIFT 0xd +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS__SHIFT 0xe +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2__SHIFT 0x10 +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18 +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY_MASK 0x00000400L +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1_MASK 0x00002000L +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS_MASK 0x00004000L +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2_MASK 0x00010000L +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L +//GDC1_NGDC_PGMST_CTRL +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS__SHIFT 0x0 +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN__SHIFT 0x8 +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN__SHIFT 0xa +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN__SHIFT 0xe +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS_MASK 0x000000FFL +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN_MASK 0x00000100L +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L +//GDC1_NGDC_PGSLV_CTRL +#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0 +#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5 +#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS__SHIFT 0xa +#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL +#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L +#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS_MASK 0x00007C00L + + +// addressBlock: aid_nbio_nbif0_gdc_sec_GDCSEC_DEC +//XCC_DOORBELL_FENCE +#define XCC_DOORBELL_FENCE__XCC_0_DOORBELL_FENCE__SHIFT 0x0 +#define XCC_DOORBELL_FENCE__XCC_1_DOORBELL_FENCE__SHIFT 0x1 +#define XCC_DOORBELL_FENCE__XCC_2_DOORBELL_FENCE__SHIFT 0x2 +#define XCC_DOORBELL_FENCE__XCC_3_DOORBELL_FENCE__SHIFT 0x3 +#define XCC_DOORBELL_FENCE__XCC_4_DOORBELL_FENCE__SHIFT 0x4 +#define XCC_DOORBELL_FENCE__XCC_5_DOORBELL_FENCE__SHIFT 0x5 +#define XCC_DOORBELL_FENCE__XCC_6_DOORBELL_FENCE__SHIFT 0x6 +#define XCC_DOORBELL_FENCE__XCC_7_DOORBELL_FENCE__SHIFT 0x7 +#define XCC_DOORBELL_FENCE__SHUB_SLV_MODE__SHIFT 0x10 +#define XCC_DOORBELL_FENCE__RMOTE_CP_SENT__SHIFT 0x11 +#define XCC_DOORBELL_FENCE__CP_0_SENT__SHIFT 0x12 +#define XCC_DOORBELL_FENCE__CP_1_SENT__SHIFT 0x13 +#define XCC_DOORBELL_FENCE__CP_2_SENT__SHIFT 0x14 +#define XCC_DOORBELL_FENCE__CP_3_SENT__SHIFT 0x15 +#define XCC_DOORBELL_FENCE__CP_4_SENT__SHIFT 0x16 +#define XCC_DOORBELL_FENCE__CP_5_SENT__SHIFT 0x17 +#define XCC_DOORBELL_FENCE__CP_6_SENT__SHIFT 0x18 +#define XCC_DOORBELL_FENCE__CP_7_SENT__SHIFT 0x19 +#define XCC_DOORBELL_FENCE__REMOTE_CLIENT_SENT__SHIFT 0x1a +#define XCC_DOORBELL_FENCE__REMOTE_CLIENT_CLR_PENDING__SHIFT 0x1b +#define XCC_DOORBELL_FENCE__XCC_0_DOORBELL_FENCE_MASK 0x00000001L +#define XCC_DOORBELL_FENCE__XCC_1_DOORBELL_FENCE_MASK 0x00000002L +#define XCC_DOORBELL_FENCE__XCC_2_DOORBELL_FENCE_MASK 0x00000004L +#define XCC_DOORBELL_FENCE__XCC_3_DOORBELL_FENCE_MASK 0x00000008L +#define XCC_DOORBELL_FENCE__XCC_4_DOORBELL_FENCE_MASK 0x00000010L +#define XCC_DOORBELL_FENCE__XCC_5_DOORBELL_FENCE_MASK 0x00000020L +#define XCC_DOORBELL_FENCE__XCC_6_DOORBELL_FENCE_MASK 0x00000040L +#define XCC_DOORBELL_FENCE__XCC_7_DOORBELL_FENCE_MASK 0x00000080L +#define XCC_DOORBELL_FENCE__SHUB_SLV_MODE_MASK 0x00010000L +#define XCC_DOORBELL_FENCE__RMOTE_CP_SENT_MASK 0x00020000L +#define XCC_DOORBELL_FENCE__CP_0_SENT_MASK 0x00040000L +#define XCC_DOORBELL_FENCE__CP_1_SENT_MASK 0x00080000L +#define XCC_DOORBELL_FENCE__CP_2_SENT_MASK 0x00100000L +#define XCC_DOORBELL_FENCE__CP_3_SENT_MASK 0x00200000L +#define XCC_DOORBELL_FENCE__CP_4_SENT_MASK 0x00400000L +#define XCC_DOORBELL_FENCE__CP_5_SENT_MASK 0x00800000L +#define XCC_DOORBELL_FENCE__CP_6_SENT_MASK 0x01000000L +#define XCC_DOORBELL_FENCE__CP_7_SENT_MASK 0x02000000L +#define XCC_DOORBELL_FENCE__REMOTE_CLIENT_SENT_MASK 0x04000000L +#define XCC_DOORBELL_FENCE__REMOTE_CLIENT_CLR_PENDING_MASK 0x08000000L + + +// addressBlock: aid_nbio_nbif0_gdc_rst_GDCRST_DEC +//SHUB_PF_FLR_RST +#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0 +#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1 +#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L +#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L +//SHUB_GFX_DRV_VPU_RST +#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST__SHIFT 0x0 +#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST_MASK 0x00000001L +//SHUB_LINK_RESET +#define SHUB_LINK_RESET__LINK_P0_RESET__SHIFT 0x0 +#define SHUB_LINK_RESET__LINK_P1_RESET__SHIFT 0x1 +#define SHUB_LINK_RESET__LINK_P2_RESET__SHIFT 0x2 +#define SHUB_LINK_RESET__LINK_P3_RESET__SHIFT 0x3 +#define SHUB_LINK_RESET__LINK_P0_RESET_MASK 0x00000001L +#define SHUB_LINK_RESET__LINK_P1_RESET_MASK 0x00000002L +#define SHUB_LINK_RESET__LINK_P2_RESET_MASK 0x00000004L +#define SHUB_LINK_RESET__LINK_P3_RESET_MASK 0x00000008L +//SHUB_HARD_RST_CTRL +#define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT 0x0 +#define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT 0x1 +#define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT 0x2 +#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 +#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 +#define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT 0x5 +#define SHUB_HARD_RST_CTRL__COR_RESET_EN_MASK 0x00000001L +#define SHUB_HARD_RST_CTRL__REG_RESET_EN_MASK 0x00000002L +#define SHUB_HARD_RST_CTRL__STY_RESET_EN_MASK 0x00000004L +#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L +#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L +#define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000020L +//SHUB_SOFT_RST_CTRL +#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT 0x0 +#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT 0x1 +#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT 0x2 +#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 +#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 +#define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN__SHIFT 0x5 +#define SHUB_SOFT_RST_CTRL__COR_RESET_EN_MASK 0x00000001L +#define SHUB_SOFT_RST_CTRL__REG_RESET_EN_MASK 0x00000002L +#define SHUB_SOFT_RST_CTRL__STY_RESET_EN_MASK 0x00000004L +#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L +#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L +#define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000020L +//SHUB_SDP_PORT_RST +#define SHUB_SDP_PORT_RST__A2S_SDP_PORT_RST__SHIFT 0x0 +#define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST__SHIFT 0x1 +#define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST__SHIFT 0x2 +#define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST__SHIFT 0x3 +#define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST__SHIFT 0x4 +#define SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST__SHIFT 0x6 +#define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST__SHIFT 0x8 +#define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST__SHIFT 0x9 +#define SHUB_SDP_PORT_RST__MPDMATF_DMA_SDP_PORT_RST__SHIFT 0xa +#define SHUB_SDP_PORT_RST__MPDMAPM_DMA_SDP_PORT_RST__SHIFT 0xb +#define SHUB_SDP_PORT_RST__MPDMATF_HST_SDP_PORT_RST__SHIFT 0xc +#define SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST__SHIFT 0xd +#define SHUB_SDP_PORT_RST__SION_AON_RST__SHIFT 0x18 +#define SHUB_SDP_PORT_RST__A2S_SDP_PORT_RST_MASK 0x00000001L +#define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST_MASK 0x00000002L +#define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST_MASK 0x00000004L +#define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST_MASK 0x00000008L +#define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST_MASK 0x00000010L +#define SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST_MASK 0x00000040L +#define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST_MASK 0x00000100L +#define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST_MASK 0x00000200L +#define SHUB_SDP_PORT_RST__MPDMATF_DMA_SDP_PORT_RST_MASK 0x00000400L +#define SHUB_SDP_PORT_RST__MPDMAPM_DMA_SDP_PORT_RST_MASK 0x00000800L +#define SHUB_SDP_PORT_RST__MPDMATF_HST_SDP_PORT_RST_MASK 0x00001000L +#define SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST_MASK 0x00002000L +#define SHUB_SDP_PORT_RST__SION_AON_RST_MASK 0x01000000L + + +// addressBlock: aid_nbio_nbif0_syshub_mmreg_syshubdirect +//HST_CLK0_SW0_CL0_CNTL +#define HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//HST_CLK0_SW1_CL0_CNTL +#define HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//HST_CLK0_SW1_CL1_CNTL +#define HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//HST_CLK0_SW1_CL2_CNTL +#define HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//DMA_CLK0_SW0_CL0_CNTL +#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//DMA_CLK0_SW0_CL1_CNTL +#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//NIC400_1_ASIB_0_FN_MOD +#define NIC400_1_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_1_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_1_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_1_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_1_IB_0_FN_MOD +#define NIC400_1_IB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_1_IB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_1_IB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_1_IB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_2_ASIB_0_FN_MOD +#define NIC400_2_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_2_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_2_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_2_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_2_ASIB_0_QOS_CNTL +#define NIC400_2_ASIB_0_QOS_CNTL__en_aw_rate__SHIFT 0x0 +#define NIC400_2_ASIB_0_QOS_CNTL__en_ar_rate__SHIFT 0x1 +#define NIC400_2_ASIB_0_QOS_CNTL__en_awar_rate__SHIFT 0x2 +#define NIC400_2_ASIB_0_QOS_CNTL__en_aw_fc__SHIFT 0x3 +#define NIC400_2_ASIB_0_QOS_CNTL__en_ar_fc__SHIFT 0x4 +#define NIC400_2_ASIB_0_QOS_CNTL__en_aw_ot__SHIFT 0x5 +#define NIC400_2_ASIB_0_QOS_CNTL__en_ar_ot__SHIFT 0x6 +#define NIC400_2_ASIB_0_QOS_CNTL__en_awar_ot__SHIFT 0x7 +#define NIC400_2_ASIB_0_QOS_CNTL__mode_aw_fc__SHIFT 0x10 +#define NIC400_2_ASIB_0_QOS_CNTL__mode_ar_fc__SHIFT 0x14 +#define NIC400_2_ASIB_0_QOS_CNTL__en_aw_rate_MASK 0x00000001L +#define NIC400_2_ASIB_0_QOS_CNTL__en_ar_rate_MASK 0x00000002L +#define NIC400_2_ASIB_0_QOS_CNTL__en_awar_rate_MASK 0x00000004L +#define NIC400_2_ASIB_0_QOS_CNTL__en_aw_fc_MASK 0x00000008L +#define NIC400_2_ASIB_0_QOS_CNTL__en_ar_fc_MASK 0x00000010L +#define NIC400_2_ASIB_0_QOS_CNTL__en_aw_ot_MASK 0x00000020L +#define NIC400_2_ASIB_0_QOS_CNTL__en_ar_ot_MASK 0x00000040L +#define NIC400_2_ASIB_0_QOS_CNTL__en_awar_ot_MASK 0x00000080L +#define NIC400_2_ASIB_0_QOS_CNTL__mode_aw_fc_MASK 0x00010000L +#define NIC400_2_ASIB_0_QOS_CNTL__mode_ar_fc_MASK 0x00100000L +//NIC400_2_ASIB_0_MAX_OT +#define NIC400_2_ASIB_0_MAX_OT__aw_max_otf__SHIFT 0x0 +#define NIC400_2_ASIB_0_MAX_OT__aw_max_oti__SHIFT 0x8 +#define NIC400_2_ASIB_0_MAX_OT__ar_max_otf__SHIFT 0x10 +#define NIC400_2_ASIB_0_MAX_OT__ar_max_oti__SHIFT 0x18 +#define NIC400_2_ASIB_0_MAX_OT__aw_max_otf_MASK 0x000000FFL +#define NIC400_2_ASIB_0_MAX_OT__aw_max_oti_MASK 0x00003F00L +#define NIC400_2_ASIB_0_MAX_OT__ar_max_otf_MASK 0x00FF0000L +#define NIC400_2_ASIB_0_MAX_OT__ar_max_oti_MASK 0x3F000000L +//NIC400_2_ASIB_0_MAX_COMB_OT +#define NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_otf__SHIFT 0x0 +#define NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_oti__SHIFT 0x8 +#define NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_otf_MASK 0x000000FFL +#define NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_oti_MASK 0x00007F00L +//NIC400_2_ASIB_0_AW_P +#define NIC400_2_ASIB_0_AW_P__aw_p__SHIFT 0x18 +#define NIC400_2_ASIB_0_AW_P__aw_p_MASK 0xFF000000L +//NIC400_2_ASIB_0_AW_B +#define NIC400_2_ASIB_0_AW_B__aw_b__SHIFT 0x0 +#define NIC400_2_ASIB_0_AW_B__aw_b_MASK 0x0000FFFFL +//NIC400_2_ASIB_0_AW_R +#define NIC400_2_ASIB_0_AW_R__aw_r__SHIFT 0x14 +#define NIC400_2_ASIB_0_AW_R__aw_r_MASK 0xFFF00000L +//NIC400_2_ASIB_0_AR_P +#define NIC400_2_ASIB_0_AR_P__ar_p__SHIFT 0x18 +#define NIC400_2_ASIB_0_AR_P__ar_p_MASK 0xFF000000L +//NIC400_2_ASIB_0_AR_B +#define NIC400_2_ASIB_0_AR_B__ar_b__SHIFT 0x0 +#define NIC400_2_ASIB_0_AR_B__ar_b_MASK 0x0000FFFFL +//NIC400_2_ASIB_0_AR_R +#define NIC400_2_ASIB_0_AR_R__ar_r__SHIFT 0x14 +#define NIC400_2_ASIB_0_AR_R__ar_r_MASK 0xFFF00000L +//NIC400_2_ASIB_0_TARGET_FC +#define NIC400_2_ASIB_0_TARGET_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_2_ASIB_0_TARGET_FC__ar_tgt_latency__SHIFT 0x10 +#define NIC400_2_ASIB_0_TARGET_FC__aw_tgt_latency_MASK 0x00000FFFL +#define NIC400_2_ASIB_0_TARGET_FC__ar_tgt_latency_MASK 0x0FFF0000L +//NIC400_2_ASIB_0_KI_FC +#define NIC400_2_ASIB_0_KI_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_2_ASIB_0_KI_FC__ar_tgt_latency__SHIFT 0x8 +#define NIC400_2_ASIB_0_KI_FC__aw_tgt_latency_MASK 0x00000007L +#define NIC400_2_ASIB_0_KI_FC__ar_tgt_latency_MASK 0x00000700L +//NIC400_2_ASIB_0_QOS_RANGE +#define NIC400_2_ASIB_0_QOS_RANGE__aw_min_qos__SHIFT 0x0 +#define NIC400_2_ASIB_0_QOS_RANGE__aw_max_qos__SHIFT 0x8 +#define NIC400_2_ASIB_0_QOS_RANGE__ar_min_qos__SHIFT 0x10 +#define NIC400_2_ASIB_0_QOS_RANGE__ar_max_qos__SHIFT 0x18 +#define NIC400_2_ASIB_0_QOS_RANGE__aw_min_qos_MASK 0x0000000FL +#define NIC400_2_ASIB_0_QOS_RANGE__aw_max_qos_MASK 0x00000F00L +#define NIC400_2_ASIB_0_QOS_RANGE__ar_min_qos_MASK 0x000F0000L +#define NIC400_2_ASIB_0_QOS_RANGE__ar_max_qos_MASK 0x0F000000L +//NIC400_2_ASIB_1_FN_MOD +#define NIC400_2_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_2_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_2_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_2_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_2_ASIB_1_QOS_CNTL +#define NIC400_2_ASIB_1_QOS_CNTL__en_aw_rate__SHIFT 0x0 +#define NIC400_2_ASIB_1_QOS_CNTL__en_ar_rate__SHIFT 0x1 +#define NIC400_2_ASIB_1_QOS_CNTL__en_awar_rate__SHIFT 0x2 +#define NIC400_2_ASIB_1_QOS_CNTL__en_aw_fc__SHIFT 0x3 +#define NIC400_2_ASIB_1_QOS_CNTL__en_ar_fc__SHIFT 0x4 +#define NIC400_2_ASIB_1_QOS_CNTL__en_aw_ot__SHIFT 0x5 +#define NIC400_2_ASIB_1_QOS_CNTL__en_ar_ot__SHIFT 0x6 +#define NIC400_2_ASIB_1_QOS_CNTL__en_awar_ot__SHIFT 0x7 +#define NIC400_2_ASIB_1_QOS_CNTL__mode_aw_fc__SHIFT 0x10 +#define NIC400_2_ASIB_1_QOS_CNTL__mode_ar_fc__SHIFT 0x14 +#define NIC400_2_ASIB_1_QOS_CNTL__en_aw_rate_MASK 0x00000001L +#define NIC400_2_ASIB_1_QOS_CNTL__en_ar_rate_MASK 0x00000002L +#define NIC400_2_ASIB_1_QOS_CNTL__en_awar_rate_MASK 0x00000004L +#define NIC400_2_ASIB_1_QOS_CNTL__en_aw_fc_MASK 0x00000008L +#define NIC400_2_ASIB_1_QOS_CNTL__en_ar_fc_MASK 0x00000010L +#define NIC400_2_ASIB_1_QOS_CNTL__en_aw_ot_MASK 0x00000020L +#define NIC400_2_ASIB_1_QOS_CNTL__en_ar_ot_MASK 0x00000040L +#define NIC400_2_ASIB_1_QOS_CNTL__en_awar_ot_MASK 0x00000080L +#define NIC400_2_ASIB_1_QOS_CNTL__mode_aw_fc_MASK 0x00010000L +#define NIC400_2_ASIB_1_QOS_CNTL__mode_ar_fc_MASK 0x00100000L +//NIC400_2_ASIB_1_MAX_OT +#define NIC400_2_ASIB_1_MAX_OT__aw_max_otf__SHIFT 0x0 +#define NIC400_2_ASIB_1_MAX_OT__aw_max_oti__SHIFT 0x8 +#define NIC400_2_ASIB_1_MAX_OT__ar_max_otf__SHIFT 0x10 +#define NIC400_2_ASIB_1_MAX_OT__ar_max_oti__SHIFT 0x18 +#define NIC400_2_ASIB_1_MAX_OT__aw_max_otf_MASK 0x000000FFL +#define NIC400_2_ASIB_1_MAX_OT__aw_max_oti_MASK 0x00003F00L +#define NIC400_2_ASIB_1_MAX_OT__ar_max_otf_MASK 0x00FF0000L +#define NIC400_2_ASIB_1_MAX_OT__ar_max_oti_MASK 0x3F000000L +//NIC400_2_ASIB_1_MAX_COMB_OT +#define NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_otf__SHIFT 0x0 +#define NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_oti__SHIFT 0x8 +#define NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_otf_MASK 0x000000FFL +#define NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_oti_MASK 0x00007F00L +//NIC400_2_ASIB_1_AW_P +#define NIC400_2_ASIB_1_AW_P__aw_p__SHIFT 0x18 +#define NIC400_2_ASIB_1_AW_P__aw_p_MASK 0xFF000000L +//NIC400_2_ASIB_1_AW_B +#define NIC400_2_ASIB_1_AW_B__aw_b__SHIFT 0x0 +#define NIC400_2_ASIB_1_AW_B__aw_b_MASK 0x0000FFFFL +//NIC400_2_ASIB_1_AW_R +#define NIC400_2_ASIB_1_AW_R__aw_r__SHIFT 0x14 +#define NIC400_2_ASIB_1_AW_R__aw_r_MASK 0xFFF00000L +//NIC400_2_ASIB_1_AR_P +#define NIC400_2_ASIB_1_AR_P__ar_p__SHIFT 0x18 +#define NIC400_2_ASIB_1_AR_P__ar_p_MASK 0xFF000000L +//NIC400_2_ASIB_1_AR_B +#define NIC400_2_ASIB_1_AR_B__ar_b__SHIFT 0x0 +#define NIC400_2_ASIB_1_AR_B__ar_b_MASK 0x0000FFFFL +//NIC400_2_ASIB_1_AR_R +#define NIC400_2_ASIB_1_AR_R__ar_r__SHIFT 0x14 +#define NIC400_2_ASIB_1_AR_R__ar_r_MASK 0xFFF00000L +//NIC400_2_ASIB_1_TARGET_FC +#define NIC400_2_ASIB_1_TARGET_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_2_ASIB_1_TARGET_FC__ar_tgt_latency__SHIFT 0x10 +#define NIC400_2_ASIB_1_TARGET_FC__aw_tgt_latency_MASK 0x00000FFFL +#define NIC400_2_ASIB_1_TARGET_FC__ar_tgt_latency_MASK 0x0FFF0000L +//NIC400_2_ASIB_1_KI_FC +#define NIC400_2_ASIB_1_KI_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_2_ASIB_1_KI_FC__ar_tgt_latency__SHIFT 0x8 +#define NIC400_2_ASIB_1_KI_FC__aw_tgt_latency_MASK 0x00000007L +#define NIC400_2_ASIB_1_KI_FC__ar_tgt_latency_MASK 0x00000700L +//NIC400_2_ASIB_1_QOS_RANGE +#define NIC400_2_ASIB_1_QOS_RANGE__aw_min_qos__SHIFT 0x0 +#define NIC400_2_ASIB_1_QOS_RANGE__aw_max_qos__SHIFT 0x8 +#define NIC400_2_ASIB_1_QOS_RANGE__ar_min_qos__SHIFT 0x10 +#define NIC400_2_ASIB_1_QOS_RANGE__ar_max_qos__SHIFT 0x18 +#define NIC400_2_ASIB_1_QOS_RANGE__aw_min_qos_MASK 0x0000000FL +#define NIC400_2_ASIB_1_QOS_RANGE__aw_max_qos_MASK 0x00000F00L +#define NIC400_2_ASIB_1_QOS_RANGE__ar_min_qos_MASK 0x000F0000L +#define NIC400_2_ASIB_1_QOS_RANGE__ar_max_qos_MASK 0x0F000000L +//NIC400_2_IB_0_FN_MOD +#define NIC400_2_IB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_2_IB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_2_IB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_2_IB_0_FN_MOD__write_iss_override_MASK 0x00000002L + + +// addressBlock: aid_nbio_iohub_nb_nbcfg_nb_cfgdec +//NB_NBCFG0_NBCFG_SCRATCH_4 +#define NB_NBCFG0_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4__SHIFT 0x0 +#define NB_NBCFG0_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_iohub_nb_misc_misc_cfgdec +//NB_CNTL +#define NB_CNTL__HWINIT_WR_LOCK__SHIFT 0x7 +#define NB_CNTL__HWINIT_WR_LOCK_MASK 0x00000080L +//NB_SPARE1 +#define NB_SPARE1__NB_SPARE1_RW__SHIFT 0x0 +#define NB_SPARE1__NB_SPARE1_RW_MASK 0xFFFFFFFFL +//NB_SPARE2 +#define NB_SPARE2__NB_SPARE2_RW1C_0__SHIFT 0x0 +#define NB_SPARE2__NB_SPARE2_RW1C_1__SHIFT 0x1 +#define NB_SPARE2__NB_SPARE2_RW1C_2__SHIFT 0x2 +#define NB_SPARE2__NB_SPARE2_RW1C_3__SHIFT 0x3 +#define NB_SPARE2__NB_SPARE2_RW1C_4__SHIFT 0x4 +#define NB_SPARE2__NB_SPARE2_RW1C_5__SHIFT 0x5 +#define NB_SPARE2__NB_SPARE2_RW1C_6__SHIFT 0x6 +#define NB_SPARE2__NB_SPARE2_RW1C_7__SHIFT 0x7 +#define NB_SPARE2__NB_SPARE2_RW1C_8__SHIFT 0x8 +#define NB_SPARE2__NB_SPARE2_RW1C_9__SHIFT 0x9 +#define NB_SPARE2__NB_SPARE2_RW1C_10__SHIFT 0xa +#define NB_SPARE2__NB_SPARE2_RW1C_11__SHIFT 0xb +#define NB_SPARE2__NB_SPARE2_RW1C_12__SHIFT 0xc +#define NB_SPARE2__NB_SPARE2_RW1C_13__SHIFT 0xd +#define NB_SPARE2__NB_SPARE2_RW1C_14__SHIFT 0xe +#define NB_SPARE2__NB_SPARE2_RW1C_15__SHIFT 0xf +#define NB_SPARE2__NB_SPARE2_RW1C_16__SHIFT 0x10 +#define NB_SPARE2__NB_SPARE2_RW1C_17__SHIFT 0x11 +#define NB_SPARE2__NB_SPARE2_RW1C_18__SHIFT 0x12 +#define NB_SPARE2__NB_SPARE2_RW1C_19__SHIFT 0x13 +#define NB_SPARE2__NB_SPARE2_RW1C_20__SHIFT 0x14 +#define NB_SPARE2__NB_SPARE2_RW1C_21__SHIFT 0x15 +#define NB_SPARE2__NB_SPARE2_RW1C_22__SHIFT 0x16 +#define NB_SPARE2__NB_SPARE2_RW1C_23__SHIFT 0x17 +#define NB_SPARE2__NB_SPARE2_RW1C_24__SHIFT 0x18 +#define NB_SPARE2__NB_SPARE2_RW1C_25__SHIFT 0x19 +#define NB_SPARE2__NB_SPARE2_RW1C_26__SHIFT 0x1a +#define NB_SPARE2__NB_SPARE2_RW1C_27__SHIFT 0x1b +#define NB_SPARE2__NB_SPARE2_RW1C_28__SHIFT 0x1c +#define NB_SPARE2__NB_SPARE2_RW1C_29__SHIFT 0x1d +#define NB_SPARE2__NB_SPARE2_RW1C_30__SHIFT 0x1e +#define NB_SPARE2__NB_SPARE2_RW1C_31__SHIFT 0x1f +#define NB_SPARE2__NB_SPARE2_RW1C_0_MASK 0x00000001L +#define NB_SPARE2__NB_SPARE2_RW1C_1_MASK 0x00000002L +#define NB_SPARE2__NB_SPARE2_RW1C_2_MASK 0x00000004L +#define NB_SPARE2__NB_SPARE2_RW1C_3_MASK 0x00000008L +#define NB_SPARE2__NB_SPARE2_RW1C_4_MASK 0x00000010L +#define NB_SPARE2__NB_SPARE2_RW1C_5_MASK 0x00000020L +#define NB_SPARE2__NB_SPARE2_RW1C_6_MASK 0x00000040L +#define NB_SPARE2__NB_SPARE2_RW1C_7_MASK 0x00000080L +#define NB_SPARE2__NB_SPARE2_RW1C_8_MASK 0x00000100L +#define NB_SPARE2__NB_SPARE2_RW1C_9_MASK 0x00000200L +#define NB_SPARE2__NB_SPARE2_RW1C_10_MASK 0x00000400L +#define NB_SPARE2__NB_SPARE2_RW1C_11_MASK 0x00000800L +#define NB_SPARE2__NB_SPARE2_RW1C_12_MASK 0x00001000L +#define NB_SPARE2__NB_SPARE2_RW1C_13_MASK 0x00002000L +#define NB_SPARE2__NB_SPARE2_RW1C_14_MASK 0x00004000L +#define NB_SPARE2__NB_SPARE2_RW1C_15_MASK 0x00008000L +#define NB_SPARE2__NB_SPARE2_RW1C_16_MASK 0x00010000L +#define NB_SPARE2__NB_SPARE2_RW1C_17_MASK 0x00020000L +#define NB_SPARE2__NB_SPARE2_RW1C_18_MASK 0x00040000L +#define NB_SPARE2__NB_SPARE2_RW1C_19_MASK 0x00080000L +#define NB_SPARE2__NB_SPARE2_RW1C_20_MASK 0x00100000L +#define NB_SPARE2__NB_SPARE2_RW1C_21_MASK 0x00200000L +#define NB_SPARE2__NB_SPARE2_RW1C_22_MASK 0x00400000L +#define NB_SPARE2__NB_SPARE2_RW1C_23_MASK 0x00800000L +#define NB_SPARE2__NB_SPARE2_RW1C_24_MASK 0x01000000L +#define NB_SPARE2__NB_SPARE2_RW1C_25_MASK 0x02000000L +#define NB_SPARE2__NB_SPARE2_RW1C_26_MASK 0x04000000L +#define NB_SPARE2__NB_SPARE2_RW1C_27_MASK 0x08000000L +#define NB_SPARE2__NB_SPARE2_RW1C_28_MASK 0x10000000L +#define NB_SPARE2__NB_SPARE2_RW1C_29_MASK 0x20000000L +#define NB_SPARE2__NB_SPARE2_RW1C_30_MASK 0x40000000L +#define NB_SPARE2__NB_SPARE2_RW1C_31_MASK 0x80000000L +//NB_REVID +#define NB_REVID__REVISION_ID__SHIFT 0x0 +#define NB_REVID__REVISION_ID_MASK 0x000003FFL +//NBIO_LCLK_DS_MASK +#define NBIO_LCLK_DS_MASK__LCLK_DS_MASK__SHIFT 0x0 +#define NBIO_LCLK_DS_MASK__LCLK_DS_MASK_MASK 0xFFFFFFFFL +//NB_BUS_NUM_CNTL +#define NB_BUS_NUM_CNTL__NB_BUS_NUM__SHIFT 0x0 +#define NB_BUS_NUM_CNTL__NB_BUS_LAT_Mode__SHIFT 0x8 +#define NB_BUS_NUM_CNTL__NB_SEGMENT__SHIFT 0x10 +#define NB_BUS_NUM_CNTL__NB_BUS_NUM_MASK 0x000000FFL +#define NB_BUS_NUM_CNTL__NB_BUS_LAT_Mode_MASK 0x00000100L +#define NB_BUS_NUM_CNTL__NB_SEGMENT_MASK 0x00FF0000L +//NB_MMIOBASE +#define NB_MMIOBASE__MMIOBASE__SHIFT 0x0 +#define NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL +//NB_MMIOLIMIT +#define NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 +#define NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL +//NB_LOWER_TOP_OF_DRAM2 +#define NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 +#define NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 +#define NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L +#define NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L +//NB_UPPER_TOP_OF_DRAM2 +#define NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 +#define NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x000001FFL +//NB_LOWER_DRAM2_BASE +#define NB_LOWER_DRAM2_BASE__LOWER_DRAM2_BASE__SHIFT 0x17 +#define NB_LOWER_DRAM2_BASE__LOWER_DRAM2_BASE_MASK 0xFF800000L +//NB_UPPER_DRAM2_BASE +#define NB_UPPER_DRAM2_BASE__UPPER_DRAM2_BASE__SHIFT 0x0 +#define NB_UPPER_DRAM2_BASE__UPPER_DRAM2_BASE_MASK 0x000001FFL +//SB_LOCATION +#define SB_LOCATION__SBlocated_Port__SHIFT 0x0 +#define SB_LOCATION__SBlocated_Core__SHIFT 0x10 +#define SB_LOCATION__SBlocated_Port_MASK 0x0000FFFFL +#define SB_LOCATION__SBlocated_Core_MASK 0xFFFF0000L +//SW_US_LOCATION +#define SW_US_LOCATION__SW_USlocated_Port__SHIFT 0x0 +#define SW_US_LOCATION__SW_USlocated_Core__SHIFT 0x10 +#define SW_US_LOCATION__SW_USlocated_Port_MASK 0x0000FFFFL +#define SW_US_LOCATION__SW_USlocated_Core_MASK 0xFFFF0000L +//NB_PROG_DEVICE_REMAP_PBr0 +#define NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr1 +#define NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr2 +#define NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr3 +#define NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr4 +#define NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr5 +#define NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr6 +#define NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr7 +#define NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr8 +#define NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr10 +#define NB_PROG_DEVICE_REMAP_PBr10__PBr10_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr10__PBr10_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr11 +#define NB_PROG_DEVICE_REMAP_PBr11__PBr11_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr11__PBr11_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr12 +#define NB_PROG_DEVICE_REMAP_PBr12__PBr12_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr12__PBr12_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr13 +#define NB_PROG_DEVICE_REMAP_PBr13__PBr13_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr13__PBr13_DevFnMap_MASK 0x000000FFL +//SW_NMI_CNTL +#define SW_NMI_CNTL__SW_NMI_Status__SHIFT 0x0 +#define SW_NMI_CNTL__SW_NMI_Status_MASK 0xFFFFFFFFL +//SW_SMI_CNTL +#define SW_SMI_CNTL__SW_SMI_Status__SHIFT 0x0 +#define SW_SMI_CNTL__SW_SMI_Status_MASK 0xFFFFFFFFL +//SW_SCI_CNTL +#define SW_SCI_CNTL__SW_SCI_Status__SHIFT 0x0 +#define SW_SCI_CNTL__SW_SCI_Status_MASK 0xFFFFFFFFL +//APML_SW_STATUS +#define APML_SW_STATUS__APML_NMI_STATUS__SHIFT 0x0 +#define APML_SW_STATUS__APML_NMI_STATUS_MASK 0x00000001L +//SW_GIC_SPI_CNTL +#define SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector__SHIFT 0x0 +#define SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector__SHIFT 0x8 +#define SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector__SHIFT 0x10 +#define SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector_MASK 0x000000FFL +#define SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector_MASK 0x0000FF00L +#define SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector_MASK 0x00FF0000L +//SW_SYNCFLOOD_CNTL +#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE__SHIFT 0x0 +#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML__SHIFT 0x1 +#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE_MASK 0x00000001L +#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML_MASK 0x00000002L +//NB_TOP_OF_DRAM3 +#define NB_TOP_OF_DRAM3__TOM3_LIMIT__SHIFT 0x0 +#define NB_TOP_OF_DRAM3__TOM3_ENABLE__SHIFT 0x1f +#define NB_TOP_OF_DRAM3__TOM3_LIMIT_MASK 0x3FFFFFFFL +#define NB_TOP_OF_DRAM3__TOM3_ENABLE_MASK 0x80000000L +//CAM_CONTROL +#define CAM_CONTROL__CAM_En__SHIFT 0x0 +#define CAM_CONTROL__Op__SHIFT 0x1 +#define CAM_CONTROL__AccessType__SHIFT 0x2 +#define CAM_CONTROL__DataMatchEn__SHIFT 0x3 +#define CAM_CONTROL__VC__SHIFT 0x4 +#define CAM_CONTROL__CrossTrigger__SHIFT 0x8 +#define CAM_CONTROL__CAM_En_MASK 0x00000001L +#define CAM_CONTROL__Op_MASK 0x00000002L +#define CAM_CONTROL__AccessType_MASK 0x00000004L +#define CAM_CONTROL__DataMatchEn_MASK 0x00000008L +#define CAM_CONTROL__VC_MASK 0x00000070L +#define CAM_CONTROL__CrossTrigger_MASK 0x00000F00L +//CAM_TARGET_INDEX_ADDR_BOTTOM +#define CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom__SHIFT 0x0 +#define CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom_MASK 0xFFFFFFFFL +//CAM_TARGET_INDEX_ADDR_TOP +#define CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop__SHIFT 0x0 +#define CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop_MASK 0xFFFFFFFFL +//CAM_TARGET_INDEX_DATA +#define CAM_TARGET_INDEX_DATA__IndexData__SHIFT 0x0 +#define CAM_TARGET_INDEX_DATA__IndexData_MASK 0xFFFFFFFFL +//CAM_TARGET_INDEX_DATA_MASK +#define CAM_TARGET_INDEX_DATA_MASK__IndexDataMask__SHIFT 0x0 +#define CAM_TARGET_INDEX_DATA_MASK__IndexDataMask_MASK 0xFFFFFFFFL +//CAM_TARGET_DATA_ADDR_BOTTOM +#define CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom__SHIFT 0x0 +#define CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom_MASK 0xFFFFFFFFL +//CAM_TARGET_DATA_ADDR_TOP +#define CAM_TARGET_DATA_ADDR_TOP__DataAddrTop__SHIFT 0x0 +#define CAM_TARGET_DATA_ADDR_TOP__DataAddrTop_MASK 0xFFFFFFFFL +//CAM_TARGET_DATA +#define CAM_TARGET_DATA__Data__SHIFT 0x0 +#define CAM_TARGET_DATA__Data_MASK 0xFFFFFFFFL +//CAM_TARGET_DATA_MASK +#define CAM_TARGET_DATA_MASK__DataMask__SHIFT 0x0 +#define CAM_TARGET_DATA_MASK__DataMask_MASK 0xFFFFFFFFL +//P_DMA_DROPPED_LOG_LOWER +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_0__SHIFT 0x0 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_1__SHIFT 0x1 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_2__SHIFT 0x2 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_3__SHIFT 0x3 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_4__SHIFT 0x4 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_5__SHIFT 0x5 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_6__SHIFT 0x6 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_7__SHIFT 0x7 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_8__SHIFT 0x8 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_9__SHIFT 0x9 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_10__SHIFT 0xa +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_11__SHIFT 0xb +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_12__SHIFT 0xc +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_13__SHIFT 0xd +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_14__SHIFT 0xe +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_15__SHIFT 0xf +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_16__SHIFT 0x10 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_17__SHIFT 0x11 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_18__SHIFT 0x12 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_19__SHIFT 0x13 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_20__SHIFT 0x14 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_21__SHIFT 0x15 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_22__SHIFT 0x16 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_23__SHIFT 0x17 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_24__SHIFT 0x18 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_25__SHIFT 0x19 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_26__SHIFT 0x1a +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_27__SHIFT 0x1b +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_28__SHIFT 0x1c +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_29__SHIFT 0x1d +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_30__SHIFT 0x1e +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_31__SHIFT 0x1f +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_0_MASK 0x00000001L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_1_MASK 0x00000002L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_2_MASK 0x00000004L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_3_MASK 0x00000008L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_4_MASK 0x00000010L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_5_MASK 0x00000020L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_6_MASK 0x00000040L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_7_MASK 0x00000080L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_8_MASK 0x00000100L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_9_MASK 0x00000200L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_10_MASK 0x00000400L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_11_MASK 0x00000800L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_12_MASK 0x00001000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_13_MASK 0x00002000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_14_MASK 0x00004000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_15_MASK 0x00008000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_16_MASK 0x00010000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_17_MASK 0x00020000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_18_MASK 0x00040000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_19_MASK 0x00080000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_20_MASK 0x00100000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_21_MASK 0x00200000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_22_MASK 0x00400000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_23_MASK 0x00800000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_24_MASK 0x01000000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_25_MASK 0x02000000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_26_MASK 0x04000000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_27_MASK 0x08000000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_28_MASK 0x10000000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_29_MASK 0x20000000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_30_MASK 0x40000000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_31_MASK 0x80000000L +//P_DMA_DROPPED_LOG_UPPER +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_0__SHIFT 0x0 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_1__SHIFT 0x1 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_2__SHIFT 0x2 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_3__SHIFT 0x3 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_4__SHIFT 0x4 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_5__SHIFT 0x5 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_6__SHIFT 0x6 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_7__SHIFT 0x7 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_8__SHIFT 0x8 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_9__SHIFT 0x9 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_10__SHIFT 0xa +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_11__SHIFT 0xb +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_12__SHIFT 0xc +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_13__SHIFT 0xd +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_14__SHIFT 0xe +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_15__SHIFT 0xf +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_16__SHIFT 0x10 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_17__SHIFT 0x11 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_18__SHIFT 0x12 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_19__SHIFT 0x13 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_20__SHIFT 0x14 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_21__SHIFT 0x15 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_22__SHIFT 0x16 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_23__SHIFT 0x17 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_24__SHIFT 0x18 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_25__SHIFT 0x19 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_26__SHIFT 0x1a +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_27__SHIFT 0x1b +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_28__SHIFT 0x1c +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_29__SHIFT 0x1d +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_30__SHIFT 0x1e +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_31__SHIFT 0x1f +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_0_MASK 0x00000001L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_1_MASK 0x00000002L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_2_MASK 0x00000004L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_3_MASK 0x00000008L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_4_MASK 0x00000010L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_5_MASK 0x00000020L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_6_MASK 0x00000040L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_7_MASK 0x00000080L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_8_MASK 0x00000100L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_9_MASK 0x00000200L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_10_MASK 0x00000400L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_11_MASK 0x00000800L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_12_MASK 0x00001000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_13_MASK 0x00002000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_14_MASK 0x00004000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_15_MASK 0x00008000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_16_MASK 0x00010000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_17_MASK 0x00020000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_18_MASK 0x00040000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_19_MASK 0x00080000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_20_MASK 0x00100000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_21_MASK 0x00200000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_22_MASK 0x00400000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_23_MASK 0x00800000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_24_MASK 0x01000000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_25_MASK 0x02000000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_26_MASK 0x04000000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_27_MASK 0x08000000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_28_MASK 0x10000000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_29_MASK 0x20000000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_30_MASK 0x40000000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_31_MASK 0x80000000L +//NP_DMA_DROPPED_LOG_LOWER +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_0__SHIFT 0x0 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_1__SHIFT 0x1 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_2__SHIFT 0x2 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_3__SHIFT 0x3 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_4__SHIFT 0x4 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_5__SHIFT 0x5 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_6__SHIFT 0x6 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_7__SHIFT 0x7 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_8__SHIFT 0x8 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_9__SHIFT 0x9 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_10__SHIFT 0xa +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_11__SHIFT 0xb +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_12__SHIFT 0xc +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_13__SHIFT 0xd +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_14__SHIFT 0xe +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_15__SHIFT 0xf +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_16__SHIFT 0x10 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_17__SHIFT 0x11 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_18__SHIFT 0x12 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_19__SHIFT 0x13 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_20__SHIFT 0x14 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_21__SHIFT 0x15 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_22__SHIFT 0x16 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_23__SHIFT 0x17 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_24__SHIFT 0x18 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_25__SHIFT 0x19 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_26__SHIFT 0x1a +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_27__SHIFT 0x1b +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_28__SHIFT 0x1c +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_29__SHIFT 0x1d +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_30__SHIFT 0x1e +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_31__SHIFT 0x1f +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_0_MASK 0x00000001L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_1_MASK 0x00000002L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_2_MASK 0x00000004L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_3_MASK 0x00000008L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_4_MASK 0x00000010L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_5_MASK 0x00000020L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_6_MASK 0x00000040L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_7_MASK 0x00000080L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_8_MASK 0x00000100L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_9_MASK 0x00000200L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_10_MASK 0x00000400L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_11_MASK 0x00000800L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_12_MASK 0x00001000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_13_MASK 0x00002000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_14_MASK 0x00004000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_15_MASK 0x00008000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_16_MASK 0x00010000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_17_MASK 0x00020000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_18_MASK 0x00040000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_19_MASK 0x00080000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_20_MASK 0x00100000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_21_MASK 0x00200000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_22_MASK 0x00400000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_23_MASK 0x00800000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_24_MASK 0x01000000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_25_MASK 0x02000000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_26_MASK 0x04000000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_27_MASK 0x08000000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_28_MASK 0x10000000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_29_MASK 0x20000000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_30_MASK 0x40000000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_31_MASK 0x80000000L +//NP_DMA_DROPPED_LOG_UPPER +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_0__SHIFT 0x0 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_1__SHIFT 0x1 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_2__SHIFT 0x2 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_3__SHIFT 0x3 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_4__SHIFT 0x4 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_5__SHIFT 0x5 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_6__SHIFT 0x6 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_7__SHIFT 0x7 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_8__SHIFT 0x8 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_9__SHIFT 0x9 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_10__SHIFT 0xa +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_11__SHIFT 0xb +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_12__SHIFT 0xc +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_13__SHIFT 0xd +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_14__SHIFT 0xe +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_15__SHIFT 0xf +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_16__SHIFT 0x10 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_17__SHIFT 0x11 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_18__SHIFT 0x12 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_19__SHIFT 0x13 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_20__SHIFT 0x14 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_21__SHIFT 0x15 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_22__SHIFT 0x16 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_23__SHIFT 0x17 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_24__SHIFT 0x18 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_25__SHIFT 0x19 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_26__SHIFT 0x1a +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_27__SHIFT 0x1b +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_28__SHIFT 0x1c +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_29__SHIFT 0x1d +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_30__SHIFT 0x1e +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_31__SHIFT 0x1f +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_0_MASK 0x00000001L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_1_MASK 0x00000002L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_2_MASK 0x00000004L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_3_MASK 0x00000008L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_4_MASK 0x00000010L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_5_MASK 0x00000020L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_6_MASK 0x00000040L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_7_MASK 0x00000080L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_8_MASK 0x00000100L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_9_MASK 0x00000200L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_10_MASK 0x00000400L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_11_MASK 0x00000800L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_12_MASK 0x00001000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_13_MASK 0x00002000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_14_MASK 0x00004000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_15_MASK 0x00008000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_16_MASK 0x00010000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_17_MASK 0x00020000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_18_MASK 0x00040000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_19_MASK 0x00080000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_20_MASK 0x00100000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_21_MASK 0x00200000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_22_MASK 0x00400000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_23_MASK 0x00800000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_24_MASK 0x01000000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_25_MASK 0x02000000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_26_MASK 0x04000000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_27_MASK 0x08000000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_28_MASK 0x10000000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_29_MASK 0x20000000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_30_MASK 0x40000000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_31_MASK 0x80000000L +//PCIE_VDM_NODE0_CTRL4 +#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE__SHIFT 0x0 +#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT__SHIFT 0x8 +#define PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT__SHIFT 0x1f +#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE_MASK 0x000000FFL +#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT_MASK 0x0000FF00L +#define PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT_MASK 0x80000000L +//PCIE_VDM_CNTL2 +#define PCIE_VDM_CNTL2__VdmP2pMode__SHIFT 0x0 +#define PCIE_VDM_CNTL2__MCTPEndpointEn__SHIFT 0x2 +#define PCIE_VDM_CNTL2__MCTPMultiSegEn__SHIFT 0x3 +#define PCIE_VDM_CNTL2__MCTPT2SMUEn__SHIFT 0x4 +#define PCIE_VDM_CNTL2__AMDVDM2SMUEn__SHIFT 0x5 +#define PCIE_VDM_CNTL2__OtherVDM2SMUEn__SHIFT 0x6 +#define PCIE_VDM_CNTL2__RouteAllToMCTPMaster__SHIFT 0x7 +#define PCIE_VDM_CNTL2__MCTPMasterSeg__SHIFT 0x8 +#define PCIE_VDM_CNTL2__MCTPMasterID__SHIFT 0x10 +#define PCIE_VDM_CNTL2__VdmP2pMode_MASK 0x00000003L +#define PCIE_VDM_CNTL2__MCTPEndpointEn_MASK 0x00000004L +#define PCIE_VDM_CNTL2__MCTPMultiSegEn_MASK 0x00000008L +#define PCIE_VDM_CNTL2__MCTPT2SMUEn_MASK 0x00000010L +#define PCIE_VDM_CNTL2__AMDVDM2SMUEn_MASK 0x00000020L +#define PCIE_VDM_CNTL2__OtherVDM2SMUEn_MASK 0x00000040L +#define PCIE_VDM_CNTL2__RouteAllToMCTPMaster_MASK 0x00000080L +#define PCIE_VDM_CNTL2__MCTPMasterSeg_MASK 0x0000FF00L +#define PCIE_VDM_CNTL2__MCTPMasterID_MASK 0xFFFF0000L +//PCIE_VDM_CNTL3 +#define PCIE_VDM_CNTL3__APMTPMasterValid__SHIFT 0xf +#define PCIE_VDM_CNTL3__APMTPMasterID__SHIFT 0x10 +#define PCIE_VDM_CNTL3__APMTPMasterValid_MASK 0x00008000L +#define PCIE_VDM_CNTL3__APMTPMasterID_MASK 0xFFFF0000L +//STALL_CONTROL_XBARPORT0_0 +#define STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT0_0__StallVC5ReqEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT0_0__StallVC5ReqEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT0_1 +#define STALL_CONTROL_XBARPORT0_1__StallVC0RspEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT0_1__StallVC1RspEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT0_1__StallVC2RspEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT0_1__StallVC3RspEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT0_1__StallVC4RspEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT0_1__StallVC5RspEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT0_1__StallVC7RspEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT0_1__StallVC0RspEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT0_1__StallVC1RspEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT0_1__StallVC2RspEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT0_1__StallVC3RspEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT0_1__StallVC4RspEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT0_1__StallVC5RspEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT0_1__StallVC7RspEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT1_0 +#define STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT1_0__StallVC5ReqEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT1_0__StallVC5ReqEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT1_1 +#define STALL_CONTROL_XBARPORT1_1__StallVC0RspEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT1_1__StallVC1RspEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT1_1__StallVC2RspEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT1_1__StallVC3RspEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT1_1__StallVC4RspEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT1_1__StallVC5RspEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT1_1__StallVC7RspEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT1_1__StallVC0RspEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT1_1__StallVC1RspEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT1_1__StallVC2RspEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT1_1__StallVC3RspEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT1_1__StallVC4RspEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT1_1__StallVC5RspEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT1_1__StallVC7RspEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT2_0 +#define STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT2_0__StallVC5ReqEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT2_0__StallVC5ReqEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT2_1 +#define STALL_CONTROL_XBARPORT2_1__StallVC0RspEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT2_1__StallVC1RspEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT2_1__StallVC2RspEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT2_1__StallVC3RspEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT2_1__StallVC4RspEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT2_1__StallVC5RspEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT2_1__StallVC7RspEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT2_1__StallVC0RspEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT2_1__StallVC1RspEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT2_1__StallVC2RspEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT2_1__StallVC3RspEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT2_1__StallVC4RspEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT2_1__StallVC5RspEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT2_1__StallVC7RspEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT3_0 +#define STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT3_0__StallVC5ReqEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT3_0__StallVC5ReqEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT3_1 +#define STALL_CONTROL_XBARPORT3_1__StallVC0RspEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT3_1__StallVC1RspEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT3_1__StallVC2RspEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT3_1__StallVC3RspEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT3_1__StallVC4RspEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT3_1__StallVC5RspEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT3_1__StallVC7RspEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT3_1__StallVC0RspEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT3_1__StallVC1RspEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT3_1__StallVC2RspEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT3_1__StallVC3RspEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT3_1__StallVC4RspEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT3_1__StallVC5RspEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT3_1__StallVC7RspEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT4_0 +#define STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT4_0__StallVC5ReqEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT4_0__StallVC5ReqEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT4_1 +#define STALL_CONTROL_XBARPORT4_1__StallVC0RspEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT4_1__StallVC1RspEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT4_1__StallVC2RspEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT4_1__StallVC3RspEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT4_1__StallVC4RspEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT4_1__StallVC5RspEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT4_1__StallVC7RspEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT4_1__StallVC0RspEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT4_1__StallVC1RspEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT4_1__StallVC2RspEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT4_1__StallVC3RspEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT4_1__StallVC4RspEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT4_1__StallVC5RspEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT4_1__StallVC7RspEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT5_0 +#define STALL_CONTROL_XBARPORT5_0__StallVC0ReqEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT5_0__StallVC1ReqEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT5_0__StallVC2ReqEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT5_0__StallVC3ReqEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT5_0__StallVC4ReqEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT5_0__StallVC5ReqEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT5_0__StallVC7ReqEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT5_0__StallVC0ReqEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT5_0__StallVC1ReqEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT5_0__StallVC2ReqEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT5_0__StallVC3ReqEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT5_0__StallVC4ReqEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT5_0__StallVC5ReqEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT5_0__StallVC7ReqEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT5_1 +#define STALL_CONTROL_XBARPORT5_1__StallVC0RspEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT5_1__StallVC1RspEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT5_1__StallVC2RspEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT5_1__StallVC3RspEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT5_1__StallVC4RspEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT5_1__StallVC5RspEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT5_1__StallVC7RspEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT5_1__StallVC0RspEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT5_1__StallVC1RspEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT5_1__StallVC2RspEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT5_1__StallVC3RspEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT5_1__StallVC4RspEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT5_1__StallVC5RspEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT5_1__StallVC7RspEn_MASK 0x30000000L +//NB_DRAM3_BASE +#define NB_DRAM3_BASE__DRAM3_BASE__SHIFT 0x0 +#define NB_DRAM3_BASE__DRAM3_BASE_MASK 0x3FFFFFFFL +//PSP_BASE_ADDR_LO +#define PSP_BASE_ADDR_LO__PSP_MMIO_EN__SHIFT 0x0 +#define PSP_BASE_ADDR_LO__PSP_MMIO_LOCK__SHIFT 0x8 +#define PSP_BASE_ADDR_LO__PSP_BASE_ADDR_LO__SHIFT 0x14 +#define PSP_BASE_ADDR_LO__PSP_MMIO_EN_MASK 0x00000001L +#define PSP_BASE_ADDR_LO__PSP_MMIO_LOCK_MASK 0x00000100L +#define PSP_BASE_ADDR_LO__PSP_BASE_ADDR_LO_MASK 0xFFF00000L +//PSP_BASE_ADDR_HI +#define PSP_BASE_ADDR_HI__PSP_BASE_ADDR_HI__SHIFT 0x0 +#define PSP_BASE_ADDR_HI__PSP_BASE_ADDR_HI_MASK 0x0000FFFFL +//SMU_BASE_ADDR_LO +#define SMU_BASE_ADDR_LO__SMU_MMIO_EN__SHIFT 0x0 +#define SMU_BASE_ADDR_LO__SMU_MMIO_LOCK__SHIFT 0x1 +#define SMU_BASE_ADDR_LO__SMU_BASE_ADDR_LO__SHIFT 0x14 +#define SMU_BASE_ADDR_LO__SMU_MMIO_EN_MASK 0x00000001L +#define SMU_BASE_ADDR_LO__SMU_MMIO_LOCK_MASK 0x00000002L +#define SMU_BASE_ADDR_LO__SMU_BASE_ADDR_LO_MASK 0xFFF00000L +//SMU_BASE_ADDR_HI +#define SMU_BASE_ADDR_HI__SMU_BASE_ADDR_HI__SHIFT 0x0 +#define SMU_BASE_ADDR_HI__SMU_BASE_ADDR_HI_MASK 0x0000FFFFL +//SCRATCH_4 +#define SCRATCH_4__SCRATCH_4__SHIFT 0x0 +#define SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL +//SCRATCH_5 +#define SCRATCH_5__SCRATCH_5__SHIFT 0x0 +#define SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL +//SMU_BLOCK_CPU +#define SMU_BLOCK_CPU__SMUBlockCPU_Valid__SHIFT 0x0 +#define SMU_BLOCK_CPU__SMUBlockCPU_Valid_MASK 0x00000001L +//SMU_BLOCK_CPU_STATUS +#define SMU_BLOCK_CPU_STATUS__SMUBlockCPU_Status__SHIFT 0x0 +#define SMU_BLOCK_CPU_STATUS__SMUBlockCPU_Status_MASK 0x00000001L +//TRAP_STATUS +#define TRAP_STATUS__TrapReqValid__SHIFT 0x0 +#define TRAP_STATUS__TrapNumber__SHIFT 0x8 +#define TRAP_STATUS__TrapS2Vld__SHIFT 0xc +#define TRAP_STATUS__TrapS2Number__SHIFT 0x10 +#define TRAP_STATUS__TrapReqValid_MASK 0x00000001L +#define TRAP_STATUS__TrapNumber_MASK 0x00000F00L +#define TRAP_STATUS__TrapS2Vld_MASK 0x00001000L +#define TRAP_STATUS__TrapS2Number_MASK 0x03FF0000L +//TRAP_REQUEST0 +#define TRAP_REQUEST0__TrapReqAddrLo__SHIFT 0x2 +#define TRAP_REQUEST0__TrapReqAddrLo_MASK 0xFFFFFFFCL +//TRAP_REQUEST1 +#define TRAP_REQUEST1__TrapReqAddrHi__SHIFT 0x0 +#define TRAP_REQUEST1__TrapReqAddrHi_MASK 0xFFFFFFFFL +//TRAP_REQUEST2 +#define TRAP_REQUEST2__TrapReqCmd__SHIFT 0x0 +#define TRAP_REQUEST2__TrapAttr__SHIFT 0x8 +#define TRAP_REQUEST2__TrapReqLen__SHIFT 0x10 +#define TRAP_REQUEST2__TrapReqCmd_MASK 0x0000003FL +#define TRAP_REQUEST2__TrapAttr_MASK 0x0000FF00L +#define TRAP_REQUEST2__TrapReqLen_MASK 0x003F0000L +//TRAP_REQUEST3 +#define TRAP_REQUEST3__TrapReqVC__SHIFT 0x0 +#define TRAP_REQUEST3__TrapReqBlockLevel__SHIFT 0x4 +#define TRAP_REQUEST3__TrapReqChain__SHIFT 0x6 +#define TRAP_REQUEST3__TrapReqIO__SHIFT 0x7 +#define TRAP_REQUEST3__TrapReqPassPW__SHIFT 0x8 +#define TRAP_REQUEST3__TrapReqRspPassPW__SHIFT 0x9 +#define TRAP_REQUEST3__TrapReqUnitID__SHIFT 0x10 +#define TRAP_REQUEST3__TrapReqVC_MASK 0x00000007L +#define TRAP_REQUEST3__TrapReqBlockLevel_MASK 0x00000030L +#define TRAP_REQUEST3__TrapReqChain_MASK 0x00000040L +#define TRAP_REQUEST3__TrapReqIO_MASK 0x00000080L +#define TRAP_REQUEST3__TrapReqPassPW_MASK 0x00000100L +#define TRAP_REQUEST3__TrapReqRspPassPW_MASK 0x00000200L +#define TRAP_REQUEST3__TrapReqUnitID_MASK 0x003F0000L +//TRAP_REQUEST4 +#define TRAP_REQUEST4__TrapReqSecLevel__SHIFT 0x0 +#define TRAP_REQUEST4__TrapReqSecLevel_MASK 0x0000000FL +//TRAP_REQUEST5 +#define TRAP_REQUEST5__TrapReqDataVC__SHIFT 0x0 +#define TRAP_REQUEST5__TrapReqDataErr__SHIFT 0x4 +#define TRAP_REQUEST5__TrapReqDataParity__SHIFT 0x8 +#define TRAP_REQUEST5__TrapReqDataVC_MASK 0x00000007L +#define TRAP_REQUEST5__TrapReqDataErr_MASK 0x00000010L +#define TRAP_REQUEST5__TrapReqDataParity_MASK 0x0000FF00L +//TRAP_REQUEST_DATASTRB0 +#define TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0__SHIFT 0x0 +#define TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATASTRB1 +#define TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1__SHIFT 0x0 +#define TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA0 +#define TRAP_REQUEST_DATA0__TrapReqData0__SHIFT 0x0 +#define TRAP_REQUEST_DATA0__TrapReqData0_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA1 +#define TRAP_REQUEST_DATA1__TrapReqData1__SHIFT 0x0 +#define TRAP_REQUEST_DATA1__TrapReqData1_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA2 +#define TRAP_REQUEST_DATA2__TrapReqData2__SHIFT 0x0 +#define TRAP_REQUEST_DATA2__TrapReqData2_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA3 +#define TRAP_REQUEST_DATA3__TrapReqData3__SHIFT 0x0 +#define TRAP_REQUEST_DATA3__TrapReqData3_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA4 +#define TRAP_REQUEST_DATA4__TrapReqData4__SHIFT 0x0 +#define TRAP_REQUEST_DATA4__TrapReqData4_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA5 +#define TRAP_REQUEST_DATA5__TrapReqData5__SHIFT 0x0 +#define TRAP_REQUEST_DATA5__TrapReqData5_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA6 +#define TRAP_REQUEST_DATA6__TrapReqData6__SHIFT 0x0 +#define TRAP_REQUEST_DATA6__TrapReqData6_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA7 +#define TRAP_REQUEST_DATA7__TrapReqData7__SHIFT 0x0 +#define TRAP_REQUEST_DATA7__TrapReqData7_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA8 +#define TRAP_REQUEST_DATA8__TrapReqData8__SHIFT 0x0 +#define TRAP_REQUEST_DATA8__TrapReqData8_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA9 +#define TRAP_REQUEST_DATA9__TrapReqData9__SHIFT 0x0 +#define TRAP_REQUEST_DATA9__TrapReqData9_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA10 +#define TRAP_REQUEST_DATA10__TrapReqData10__SHIFT 0x0 +#define TRAP_REQUEST_DATA10__TrapReqData10_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA11 +#define TRAP_REQUEST_DATA11__TrapReqData11__SHIFT 0x0 +#define TRAP_REQUEST_DATA11__TrapReqData11_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA12 +#define TRAP_REQUEST_DATA12__TrapReqData12__SHIFT 0x0 +#define TRAP_REQUEST_DATA12__TrapReqData12_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA13 +#define TRAP_REQUEST_DATA13__TrapReqData13__SHIFT 0x0 +#define TRAP_REQUEST_DATA13__TrapReqData13_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA14 +#define TRAP_REQUEST_DATA14__TrapReqData14__SHIFT 0x0 +#define TRAP_REQUEST_DATA14__TrapReqData14_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA15 +#define TRAP_REQUEST_DATA15__TrapReqData15__SHIFT 0x0 +#define TRAP_REQUEST_DATA15__TrapReqData15_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_CONTROL +#define TRAP_RESPONSE_CONTROL__TrapRspTrigger__SHIFT 0x0 +#define TRAP_RESPONSE_CONTROL__TrapRspReqPassthru__SHIFT 0x1 +#define TRAP_RESPONSE_CONTROL__TrapRspTrigger_MASK 0x00000001L +#define TRAP_RESPONSE_CONTROL__TrapRspReqPassthru_MASK 0x00000002L +//TRAP_RESPONSE0 +#define TRAP_RESPONSE0__TrapRspPassPW__SHIFT 0x0 +#define TRAP_RESPONSE0__TrapRspStatus__SHIFT 0x4 +#define TRAP_RESPONSE0__TrapRspDataStatus__SHIFT 0x10 +#define TRAP_RESPONSE0__TrapRspPassPW_MASK 0x00000001L +#define TRAP_RESPONSE0__TrapRspStatus_MASK 0x000000F0L +#define TRAP_RESPONSE0__TrapRspDataStatus_MASK 0x00FF0000L +//TRAP_RESPONSE_DATA0 +#define TRAP_RESPONSE_DATA0__TrapRdRspData0__SHIFT 0x0 +#define TRAP_RESPONSE_DATA0__TrapRdRspData0_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA1 +#define TRAP_RESPONSE_DATA1__TrapRdRspData1__SHIFT 0x0 +#define TRAP_RESPONSE_DATA1__TrapRdRspData1_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA2 +#define TRAP_RESPONSE_DATA2__TrapRdRspData2__SHIFT 0x0 +#define TRAP_RESPONSE_DATA2__TrapRdRspData2_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA3 +#define TRAP_RESPONSE_DATA3__TrapRdRspData3__SHIFT 0x0 +#define TRAP_RESPONSE_DATA3__TrapRdRspData3_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA4 +#define TRAP_RESPONSE_DATA4__TrapRdRspData4__SHIFT 0x0 +#define TRAP_RESPONSE_DATA4__TrapRdRspData4_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA5 +#define TRAP_RESPONSE_DATA5__TrapRdRspData5__SHIFT 0x0 +#define TRAP_RESPONSE_DATA5__TrapRdRspData5_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA6 +#define TRAP_RESPONSE_DATA6__TrapRdRspData6__SHIFT 0x0 +#define TRAP_RESPONSE_DATA6__TrapRdRspData6_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA7 +#define TRAP_RESPONSE_DATA7__TrapRdRspData7__SHIFT 0x0 +#define TRAP_RESPONSE_DATA7__TrapRdRspData7_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA8 +#define TRAP_RESPONSE_DATA8__TrapRdRspData8__SHIFT 0x0 +#define TRAP_RESPONSE_DATA8__TrapRdRspData8_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA9 +#define TRAP_RESPONSE_DATA9__TrapRdRspData9__SHIFT 0x0 +#define TRAP_RESPONSE_DATA9__TrapRdRspData9_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA10 +#define TRAP_RESPONSE_DATA10__TrapRdRspData10__SHIFT 0x0 +#define TRAP_RESPONSE_DATA10__TrapRdRspData10_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA11 +#define TRAP_RESPONSE_DATA11__TrapRdRspData11__SHIFT 0x0 +#define TRAP_RESPONSE_DATA11__TrapRdRspData11_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA12 +#define TRAP_RESPONSE_DATA12__TrapRdRspData12__SHIFT 0x0 +#define TRAP_RESPONSE_DATA12__TrapRdRspData12_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA13 +#define TRAP_RESPONSE_DATA13__TrapRdRspData13__SHIFT 0x0 +#define TRAP_RESPONSE_DATA13__TrapRdRspData13_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA14 +#define TRAP_RESPONSE_DATA14__TrapRdRspData14__SHIFT 0x0 +#define TRAP_RESPONSE_DATA14__TrapRdRspData14_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA15 +#define TRAP_RESPONSE_DATA15__TrapRdRspData15__SHIFT 0x0 +#define TRAP_RESPONSE_DATA15__TrapRdRspData15_MASK 0xFFFFFFFFL +//TRAP0_CONTROL0 +#define TRAP0_CONTROL0__Trap0En__SHIFT 0x0 +#define TRAP0_CONTROL0__Trap0SMUIntr__SHIFT 0x3 +#define TRAP0_CONTROL0__Trap0Stage2Ptr__SHIFT 0xe +#define TRAP0_CONTROL0__Trap0CrossTrigger__SHIFT 0x18 +#define TRAP0_CONTROL0__Trap0Stage2En__SHIFT 0x1f +#define TRAP0_CONTROL0__Trap0En_MASK 0x00000001L +#define TRAP0_CONTROL0__Trap0SMUIntr_MASK 0x00000008L +#define TRAP0_CONTROL0__Trap0Stage2Ptr_MASK 0x00FFC000L +#define TRAP0_CONTROL0__Trap0CrossTrigger_MASK 0x0F000000L +#define TRAP0_CONTROL0__Trap0Stage2En_MASK 0x80000000L +//TRAP0_ADDRESS_LO +#define TRAP0_ADDRESS_LO__Trap0AddrLo__SHIFT 0x2 +#define TRAP0_ADDRESS_LO__Trap0AddrLo_MASK 0xFFFFFFFCL +//TRAP0_ADDRESS_HI +#define TRAP0_ADDRESS_HI__Trap0AddrHi__SHIFT 0x0 +#define TRAP0_ADDRESS_HI__Trap0AddrHi_MASK 0xFFFFFFFFL +//TRAP0_COMMAND +#define TRAP0_COMMAND__Trap0Cmd0__SHIFT 0x0 +#define TRAP0_COMMAND__Trap0Cmd1__SHIFT 0x8 +#define TRAP0_COMMAND__Trap0Cmd0_MASK 0x0000003FL +#define TRAP0_COMMAND__Trap0Cmd1_MASK 0x00003F00L +//TRAP0_ADDRESS_LO_MASK +#define TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask__SHIFT 0x2 +#define TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask_MASK 0xFFFFFFFCL +//TRAP0_ADDRESS_HI_MASK +#define TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask__SHIFT 0x0 +#define TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask_MASK 0xFFFFFFFFL +//TRAP0_COMMAND_MASK +#define TRAP0_COMMAND_MASK__Trap0Cmd0Mask__SHIFT 0x0 +#define TRAP0_COMMAND_MASK__Trap0Cmd1Mask__SHIFT 0x8 +#define TRAP0_COMMAND_MASK__Trap0Cmd0Mask_MASK 0x0000003FL +#define TRAP0_COMMAND_MASK__Trap0Cmd1Mask_MASK 0x00003F00L +//TRAP1_CONTROL0 +#define TRAP1_CONTROL0__Trap1En__SHIFT 0x0 +#define TRAP1_CONTROL0__Trap1SMUIntr__SHIFT 0x3 +#define TRAP1_CONTROL0__Trap1Stage2Ptr__SHIFT 0xe +#define TRAP1_CONTROL0__Trap1CrossTrigger__SHIFT 0x18 +#define TRAP1_CONTROL0__Trap1Stage2En__SHIFT 0x1f +#define TRAP1_CONTROL0__Trap1En_MASK 0x00000001L +#define TRAP1_CONTROL0__Trap1SMUIntr_MASK 0x00000008L +#define TRAP1_CONTROL0__Trap1Stage2Ptr_MASK 0x00FFC000L +#define TRAP1_CONTROL0__Trap1CrossTrigger_MASK 0x0F000000L +#define TRAP1_CONTROL0__Trap1Stage2En_MASK 0x80000000L +//TRAP1_ADDRESS_LO +#define TRAP1_ADDRESS_LO__Trap1AddrLo__SHIFT 0x2 +#define TRAP1_ADDRESS_LO__Trap1AddrLo_MASK 0xFFFFFFFCL +//TRAP1_ADDRESS_HI +#define TRAP1_ADDRESS_HI__Trap1AddrHi__SHIFT 0x0 +#define TRAP1_ADDRESS_HI__Trap1AddrHi_MASK 0xFFFFFFFFL +//TRAP1_COMMAND +#define TRAP1_COMMAND__Trap1Cmd0__SHIFT 0x0 +#define TRAP1_COMMAND__Trap1Cmd1__SHIFT 0x8 +#define TRAP1_COMMAND__Trap1Cmd0_MASK 0x0000003FL +#define TRAP1_COMMAND__Trap1Cmd1_MASK 0x00003F00L +//TRAP1_ADDRESS_LO_MASK +#define TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask__SHIFT 0x2 +#define TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask_MASK 0xFFFFFFFCL +//TRAP1_ADDRESS_HI_MASK +#define TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask__SHIFT 0x0 +#define TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask_MASK 0xFFFFFFFFL +//TRAP1_COMMAND_MASK +#define TRAP1_COMMAND_MASK__Trap1Cmd0Mask__SHIFT 0x0 +#define TRAP1_COMMAND_MASK__Trap1Cmd1Mask__SHIFT 0x8 +#define TRAP1_COMMAND_MASK__Trap1Cmd0Mask_MASK 0x0000003FL +#define TRAP1_COMMAND_MASK__Trap1Cmd1Mask_MASK 0x00003F00L +//TRAP2_CONTROL0 +#define TRAP2_CONTROL0__Trap2En__SHIFT 0x0 +#define TRAP2_CONTROL0__Trap2SMUIntr__SHIFT 0x3 +#define TRAP2_CONTROL0__Trap2Stage2Ptr__SHIFT 0xe +#define TRAP2_CONTROL0__Trap2CrossTrigger__SHIFT 0x18 +#define TRAP2_CONTROL0__Trap2Stage2En__SHIFT 0x1f +#define TRAP2_CONTROL0__Trap2En_MASK 0x00000001L +#define TRAP2_CONTROL0__Trap2SMUIntr_MASK 0x00000008L +#define TRAP2_CONTROL0__Trap2Stage2Ptr_MASK 0x00FFC000L +#define TRAP2_CONTROL0__Trap2CrossTrigger_MASK 0x0F000000L +#define TRAP2_CONTROL0__Trap2Stage2En_MASK 0x80000000L +//TRAP2_ADDRESS_LO +#define TRAP2_ADDRESS_LO__Trap2AddrLo__SHIFT 0x2 +#define TRAP2_ADDRESS_LO__Trap2AddrLo_MASK 0xFFFFFFFCL +//TRAP2_ADDRESS_HI +#define TRAP2_ADDRESS_HI__Trap2AddrHi__SHIFT 0x0 +#define TRAP2_ADDRESS_HI__Trap2AddrHi_MASK 0xFFFFFFFFL +//TRAP2_COMMAND +#define TRAP2_COMMAND__Trap2Cmd0__SHIFT 0x0 +#define TRAP2_COMMAND__Trap2Cmd1__SHIFT 0x8 +#define TRAP2_COMMAND__Trap2Cmd0_MASK 0x0000003FL +#define TRAP2_COMMAND__Trap2Cmd1_MASK 0x00003F00L +//TRAP2_ADDRESS_LO_MASK +#define TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask__SHIFT 0x2 +#define TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask_MASK 0xFFFFFFFCL +//TRAP2_ADDRESS_HI_MASK +#define TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask__SHIFT 0x0 +#define TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask_MASK 0xFFFFFFFFL +//TRAP2_COMMAND_MASK +#define TRAP2_COMMAND_MASK__Trap2Cmd0Mask__SHIFT 0x0 +#define TRAP2_COMMAND_MASK__Trap2Cmd1Mask__SHIFT 0x8 +#define TRAP2_COMMAND_MASK__Trap2Cmd0Mask_MASK 0x0000003FL +#define TRAP2_COMMAND_MASK__Trap2Cmd1Mask_MASK 0x00003F00L +//TRAP3_CONTROL0 +#define TRAP3_CONTROL0__Trap3En__SHIFT 0x0 +#define TRAP3_CONTROL0__Trap3SMUIntr__SHIFT 0x3 +#define TRAP3_CONTROL0__Trap3Stage2Ptr__SHIFT 0xe +#define TRAP3_CONTROL0__Trap3CrossTrigger__SHIFT 0x18 +#define TRAP3_CONTROL0__Trap3Stage2En__SHIFT 0x1f +#define TRAP3_CONTROL0__Trap3En_MASK 0x00000001L +#define TRAP3_CONTROL0__Trap3SMUIntr_MASK 0x00000008L +#define TRAP3_CONTROL0__Trap3Stage2Ptr_MASK 0x00FFC000L +#define TRAP3_CONTROL0__Trap3CrossTrigger_MASK 0x0F000000L +#define TRAP3_CONTROL0__Trap3Stage2En_MASK 0x80000000L +//TRAP3_ADDRESS_LO +#define TRAP3_ADDRESS_LO__Trap3AddrLo__SHIFT 0x2 +#define TRAP3_ADDRESS_LO__Trap3AddrLo_MASK 0xFFFFFFFCL +//TRAP3_ADDRESS_HI +#define TRAP3_ADDRESS_HI__Trap3AddrHi__SHIFT 0x0 +#define TRAP3_ADDRESS_HI__Trap3AddrHi_MASK 0xFFFFFFFFL +//TRAP3_COMMAND +#define TRAP3_COMMAND__Trap3Cmd0__SHIFT 0x0 +#define TRAP3_COMMAND__Trap3Cmd1__SHIFT 0x8 +#define TRAP3_COMMAND__Trap3Cmd0_MASK 0x0000003FL +#define TRAP3_COMMAND__Trap3Cmd1_MASK 0x00003F00L +//TRAP3_ADDRESS_LO_MASK +#define TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask__SHIFT 0x2 +#define TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask_MASK 0xFFFFFFFCL +//TRAP3_ADDRESS_HI_MASK +#define TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask__SHIFT 0x0 +#define TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask_MASK 0xFFFFFFFFL +//TRAP3_COMMAND_MASK +#define TRAP3_COMMAND_MASK__Trap3Cmd0Mask__SHIFT 0x0 +#define TRAP3_COMMAND_MASK__Trap3Cmd1Mask__SHIFT 0x8 +#define TRAP3_COMMAND_MASK__Trap3Cmd0Mask_MASK 0x0000003FL +#define TRAP3_COMMAND_MASK__Trap3Cmd1Mask_MASK 0x00003F00L +//TRAP4_CONTROL0 +#define TRAP4_CONTROL0__Trap4En__SHIFT 0x0 +#define TRAP4_CONTROL0__Trap4SMUIntr__SHIFT 0x3 +#define TRAP4_CONTROL0__Trap4Stage2Ptr__SHIFT 0xe +#define TRAP4_CONTROL0__Trap4CrossTrigger__SHIFT 0x18 +#define TRAP4_CONTROL0__Trap4Stage2En__SHIFT 0x1f +#define TRAP4_CONTROL0__Trap4En_MASK 0x00000001L +#define TRAP4_CONTROL0__Trap4SMUIntr_MASK 0x00000008L +#define TRAP4_CONTROL0__Trap4Stage2Ptr_MASK 0x00FFC000L +#define TRAP4_CONTROL0__Trap4CrossTrigger_MASK 0x0F000000L +#define TRAP4_CONTROL0__Trap4Stage2En_MASK 0x80000000L +//TRAP4_ADDRESS_LO +#define TRAP4_ADDRESS_LO__Trap4AddrLo__SHIFT 0x2 +#define TRAP4_ADDRESS_LO__Trap4AddrLo_MASK 0xFFFFFFFCL +//TRAP4_ADDRESS_HI +#define TRAP4_ADDRESS_HI__Trap4AddrHi__SHIFT 0x0 +#define TRAP4_ADDRESS_HI__Trap4AddrHi_MASK 0xFFFFFFFFL +//TRAP4_COMMAND +#define TRAP4_COMMAND__Trap4Cmd0__SHIFT 0x0 +#define TRAP4_COMMAND__Trap4Cmd1__SHIFT 0x8 +#define TRAP4_COMMAND__Trap4Cmd0_MASK 0x0000003FL +#define TRAP4_COMMAND__Trap4Cmd1_MASK 0x00003F00L +//TRAP4_ADDRESS_LO_MASK +#define TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask__SHIFT 0x2 +#define TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask_MASK 0xFFFFFFFCL +//TRAP4_ADDRESS_HI_MASK +#define TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask__SHIFT 0x0 +#define TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask_MASK 0xFFFFFFFFL +//TRAP4_COMMAND_MASK +#define TRAP4_COMMAND_MASK__Trap4Cmd0Mask__SHIFT 0x0 +#define TRAP4_COMMAND_MASK__Trap4Cmd1Mask__SHIFT 0x8 +#define TRAP4_COMMAND_MASK__Trap4Cmd0Mask_MASK 0x0000003FL +#define TRAP4_COMMAND_MASK__Trap4Cmd1Mask_MASK 0x00003F00L +//TRAP5_CONTROL0 +#define TRAP5_CONTROL0__Trap5En__SHIFT 0x0 +#define TRAP5_CONTROL0__Trap5SMUIntr__SHIFT 0x3 +#define TRAP5_CONTROL0__Trap5Stage2Ptr__SHIFT 0xe +#define TRAP5_CONTROL0__Trap5CrossTrigger__SHIFT 0x18 +#define TRAP5_CONTROL0__Trap5Stage2En__SHIFT 0x1f +#define TRAP5_CONTROL0__Trap5En_MASK 0x00000001L +#define TRAP5_CONTROL0__Trap5SMUIntr_MASK 0x00000008L +#define TRAP5_CONTROL0__Trap5Stage2Ptr_MASK 0x00FFC000L +#define TRAP5_CONTROL0__Trap5CrossTrigger_MASK 0x0F000000L +#define TRAP5_CONTROL0__Trap5Stage2En_MASK 0x80000000L +//TRAP5_ADDRESS_LO +#define TRAP5_ADDRESS_LO__Trap5AddrLo__SHIFT 0x2 +#define TRAP5_ADDRESS_LO__Trap5AddrLo_MASK 0xFFFFFFFCL +//TRAP5_ADDRESS_HI +#define TRAP5_ADDRESS_HI__Trap5AddrHi__SHIFT 0x0 +#define TRAP5_ADDRESS_HI__Trap5AddrHi_MASK 0xFFFFFFFFL +//TRAP5_COMMAND +#define TRAP5_COMMAND__Trap5Cmd0__SHIFT 0x0 +#define TRAP5_COMMAND__Trap5Cmd1__SHIFT 0x8 +#define TRAP5_COMMAND__Trap5Cmd0_MASK 0x0000003FL +#define TRAP5_COMMAND__Trap5Cmd1_MASK 0x00003F00L +//TRAP5_ADDRESS_LO_MASK +#define TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask__SHIFT 0x2 +#define TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask_MASK 0xFFFFFFFCL +//TRAP5_ADDRESS_HI_MASK +#define TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask__SHIFT 0x0 +#define TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask_MASK 0xFFFFFFFFL +//TRAP5_COMMAND_MASK +#define TRAP5_COMMAND_MASK__Trap5Cmd0Mask__SHIFT 0x0 +#define TRAP5_COMMAND_MASK__Trap5Cmd1Mask__SHIFT 0x8 +#define TRAP5_COMMAND_MASK__Trap5Cmd0Mask_MASK 0x0000003FL +#define TRAP5_COMMAND_MASK__Trap5Cmd1Mask_MASK 0x00003F00L +//TRAP6_CONTROL0 +#define TRAP6_CONTROL0__Trap6En__SHIFT 0x0 +#define TRAP6_CONTROL0__Trap6SMUIntr__SHIFT 0x3 +#define TRAP6_CONTROL0__Trap6Stage2Ptr__SHIFT 0xe +#define TRAP6_CONTROL0__Trap6CrossTrigger__SHIFT 0x18 +#define TRAP6_CONTROL0__Trap6Stage2En__SHIFT 0x1f +#define TRAP6_CONTROL0__Trap6En_MASK 0x00000001L +#define TRAP6_CONTROL0__Trap6SMUIntr_MASK 0x00000008L +#define TRAP6_CONTROL0__Trap6Stage2Ptr_MASK 0x00FFC000L +#define TRAP6_CONTROL0__Trap6CrossTrigger_MASK 0x0F000000L +#define TRAP6_CONTROL0__Trap6Stage2En_MASK 0x80000000L +//TRAP6_ADDRESS_LO +#define TRAP6_ADDRESS_LO__Trap6AddrLo__SHIFT 0x2 +#define TRAP6_ADDRESS_LO__Trap6AddrLo_MASK 0xFFFFFFFCL +//TRAP6_ADDRESS_HI +#define TRAP6_ADDRESS_HI__Trap6AddrHi__SHIFT 0x0 +#define TRAP6_ADDRESS_HI__Trap6AddrHi_MASK 0xFFFFFFFFL +//TRAP6_COMMAND +#define TRAP6_COMMAND__Trap6Cmd0__SHIFT 0x0 +#define TRAP6_COMMAND__Trap6Cmd1__SHIFT 0x8 +#define TRAP6_COMMAND__Trap6Cmd0_MASK 0x0000003FL +#define TRAP6_COMMAND__Trap6Cmd1_MASK 0x00003F00L +//TRAP6_ADDRESS_LO_MASK +#define TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask__SHIFT 0x2 +#define TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask_MASK 0xFFFFFFFCL +//TRAP6_ADDRESS_HI_MASK +#define TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask__SHIFT 0x0 +#define TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask_MASK 0xFFFFFFFFL +//TRAP6_COMMAND_MASK +#define TRAP6_COMMAND_MASK__Trap6Cmd0Mask__SHIFT 0x0 +#define TRAP6_COMMAND_MASK__Trap6Cmd1Mask__SHIFT 0x8 +#define TRAP6_COMMAND_MASK__Trap6Cmd0Mask_MASK 0x0000003FL +#define TRAP6_COMMAND_MASK__Trap6Cmd1Mask_MASK 0x00003F00L +//TRAP7_CONTROL0 +#define TRAP7_CONTROL0__Trap7En__SHIFT 0x0 +#define TRAP7_CONTROL0__Trap7SMUIntr__SHIFT 0x3 +#define TRAP7_CONTROL0__Trap7Stage2Ptr__SHIFT 0xe +#define TRAP7_CONTROL0__Trap7CrossTrigger__SHIFT 0x18 +#define TRAP7_CONTROL0__Trap7Stage2En__SHIFT 0x1f +#define TRAP7_CONTROL0__Trap7En_MASK 0x00000001L +#define TRAP7_CONTROL0__Trap7SMUIntr_MASK 0x00000008L +#define TRAP7_CONTROL0__Trap7Stage2Ptr_MASK 0x00FFC000L +#define TRAP7_CONTROL0__Trap7CrossTrigger_MASK 0x0F000000L +#define TRAP7_CONTROL0__Trap7Stage2En_MASK 0x80000000L +//TRAP7_ADDRESS_LO +#define TRAP7_ADDRESS_LO__Trap7AddrLo__SHIFT 0x2 +#define TRAP7_ADDRESS_LO__Trap7AddrLo_MASK 0xFFFFFFFCL +//TRAP7_ADDRESS_HI +#define TRAP7_ADDRESS_HI__Trap7AddrHi__SHIFT 0x0 +#define TRAP7_ADDRESS_HI__Trap7AddrHi_MASK 0xFFFFFFFFL +//TRAP7_COMMAND +#define TRAP7_COMMAND__Trap7Cmd0__SHIFT 0x0 +#define TRAP7_COMMAND__Trap7Cmd1__SHIFT 0x8 +#define TRAP7_COMMAND__Trap7Cmd0_MASK 0x0000003FL +#define TRAP7_COMMAND__Trap7Cmd1_MASK 0x00003F00L +//TRAP7_ADDRESS_LO_MASK +#define TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask__SHIFT 0x2 +#define TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask_MASK 0xFFFFFFFCL +//TRAP7_ADDRESS_HI_MASK +#define TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask__SHIFT 0x0 +#define TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask_MASK 0xFFFFFFFFL +//TRAP7_COMMAND_MASK +#define TRAP7_COMMAND_MASK__Trap7Cmd0Mask__SHIFT 0x0 +#define TRAP7_COMMAND_MASK__Trap7Cmd1Mask__SHIFT 0x8 +#define TRAP7_COMMAND_MASK__Trap7Cmd0Mask_MASK 0x0000003FL +#define TRAP7_COMMAND_MASK__Trap7Cmd1Mask_MASK 0x00003F00L +//TRAP8_CONTROL0 +#define TRAP8_CONTROL0__Trap8En__SHIFT 0x0 +#define TRAP8_CONTROL0__Trap8SMUIntr__SHIFT 0x3 +#define TRAP8_CONTROL0__Trap8Stage2Ptr__SHIFT 0xe +#define TRAP8_CONTROL0__Trap8CrossTrigger__SHIFT 0x18 +#define TRAP8_CONTROL0__Trap8Stage2En__SHIFT 0x1f +#define TRAP8_CONTROL0__Trap8En_MASK 0x00000001L +#define TRAP8_CONTROL0__Trap8SMUIntr_MASK 0x00000008L +#define TRAP8_CONTROL0__Trap8Stage2Ptr_MASK 0x00FFC000L +#define TRAP8_CONTROL0__Trap8CrossTrigger_MASK 0x0F000000L +#define TRAP8_CONTROL0__Trap8Stage2En_MASK 0x80000000L +//TRAP8_ADDRESS_LO +#define TRAP8_ADDRESS_LO__Trap8AddrLo__SHIFT 0x2 +#define TRAP8_ADDRESS_LO__Trap8AddrLo_MASK 0xFFFFFFFCL +//TRAP8_ADDRESS_HI +#define TRAP8_ADDRESS_HI__Trap8AddrHi__SHIFT 0x0 +#define TRAP8_ADDRESS_HI__Trap8AddrHi_MASK 0xFFFFFFFFL +//TRAP8_COMMAND +#define TRAP8_COMMAND__Trap8Cmd0__SHIFT 0x0 +#define TRAP8_COMMAND__Trap8Cmd1__SHIFT 0x8 +#define TRAP8_COMMAND__Trap8Cmd0_MASK 0x0000003FL +#define TRAP8_COMMAND__Trap8Cmd1_MASK 0x00003F00L +//TRAP8_ADDRESS_LO_MASK +#define TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask__SHIFT 0x2 +#define TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask_MASK 0xFFFFFFFCL +//TRAP8_ADDRESS_HI_MASK +#define TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask__SHIFT 0x0 +#define TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask_MASK 0xFFFFFFFFL +//TRAP8_COMMAND_MASK +#define TRAP8_COMMAND_MASK__Trap8Cmd0Mask__SHIFT 0x0 +#define TRAP8_COMMAND_MASK__Trap8Cmd1Mask__SHIFT 0x8 +#define TRAP8_COMMAND_MASK__Trap8Cmd0Mask_MASK 0x0000003FL +#define TRAP8_COMMAND_MASK__Trap8Cmd1Mask_MASK 0x00003F00L +//TRAP9_CONTROL0 +#define TRAP9_CONTROL0__Trap9En__SHIFT 0x0 +#define TRAP9_CONTROL0__Trap9SMUIntr__SHIFT 0x3 +#define TRAP9_CONTROL0__Trap9Stage2Ptr__SHIFT 0xe +#define TRAP9_CONTROL0__Trap9CrossTrigger__SHIFT 0x18 +#define TRAP9_CONTROL0__Trap9Stage2En__SHIFT 0x1f +#define TRAP9_CONTROL0__Trap9En_MASK 0x00000001L +#define TRAP9_CONTROL0__Trap9SMUIntr_MASK 0x00000008L +#define TRAP9_CONTROL0__Trap9Stage2Ptr_MASK 0x00FFC000L +#define TRAP9_CONTROL0__Trap9CrossTrigger_MASK 0x0F000000L +#define TRAP9_CONTROL0__Trap9Stage2En_MASK 0x80000000L +//TRAP9_ADDRESS_LO +#define TRAP9_ADDRESS_LO__Trap9AddrLo__SHIFT 0x2 +#define TRAP9_ADDRESS_LO__Trap9AddrLo_MASK 0xFFFFFFFCL +//TRAP9_ADDRESS_HI +#define TRAP9_ADDRESS_HI__Trap9AddrHi__SHIFT 0x0 +#define TRAP9_ADDRESS_HI__Trap9AddrHi_MASK 0xFFFFFFFFL +//TRAP9_COMMAND +#define TRAP9_COMMAND__Trap9Cmd0__SHIFT 0x0 +#define TRAP9_COMMAND__Trap9Cmd1__SHIFT 0x8 +#define TRAP9_COMMAND__Trap9Cmd0_MASK 0x0000003FL +#define TRAP9_COMMAND__Trap9Cmd1_MASK 0x00003F00L +//TRAP9_ADDRESS_LO_MASK +#define TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask__SHIFT 0x2 +#define TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask_MASK 0xFFFFFFFCL +//TRAP9_ADDRESS_HI_MASK +#define TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask__SHIFT 0x0 +#define TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask_MASK 0xFFFFFFFFL +//TRAP9_COMMAND_MASK +#define TRAP9_COMMAND_MASK__Trap9Cmd0Mask__SHIFT 0x0 +#define TRAP9_COMMAND_MASK__Trap9Cmd1Mask__SHIFT 0x8 +#define TRAP9_COMMAND_MASK__Trap9Cmd0Mask_MASK 0x0000003FL +#define TRAP9_COMMAND_MASK__Trap9Cmd1Mask_MASK 0x00003F00L +//TRAP10_CONTROL0 +#define TRAP10_CONTROL0__Trap10En__SHIFT 0x0 +#define TRAP10_CONTROL0__Trap10SMUIntr__SHIFT 0x3 +#define TRAP10_CONTROL0__Trap10Stage2Ptr__SHIFT 0xe +#define TRAP10_CONTROL0__Trap10CrossTrigger__SHIFT 0x18 +#define TRAP10_CONTROL0__Trap10Stage2En__SHIFT 0x1f +#define TRAP10_CONTROL0__Trap10En_MASK 0x00000001L +#define TRAP10_CONTROL0__Trap10SMUIntr_MASK 0x00000008L +#define TRAP10_CONTROL0__Trap10Stage2Ptr_MASK 0x00FFC000L +#define TRAP10_CONTROL0__Trap10CrossTrigger_MASK 0x0F000000L +#define TRAP10_CONTROL0__Trap10Stage2En_MASK 0x80000000L +//TRAP10_ADDRESS_LO +#define TRAP10_ADDRESS_LO__Trap10AddrLo__SHIFT 0x2 +#define TRAP10_ADDRESS_LO__Trap10AddrLo_MASK 0xFFFFFFFCL +//TRAP10_ADDRESS_HI +#define TRAP10_ADDRESS_HI__Trap10AddrHi__SHIFT 0x0 +#define TRAP10_ADDRESS_HI__Trap10AddrHi_MASK 0xFFFFFFFFL +//TRAP10_COMMAND +#define TRAP10_COMMAND__Trap10Cmd0__SHIFT 0x0 +#define TRAP10_COMMAND__Trap10Cmd1__SHIFT 0x8 +#define TRAP10_COMMAND__Trap10Cmd0_MASK 0x0000003FL +#define TRAP10_COMMAND__Trap10Cmd1_MASK 0x00003F00L +//TRAP10_ADDRESS_LO_MASK +#define TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask__SHIFT 0x2 +#define TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask_MASK 0xFFFFFFFCL +//TRAP10_ADDRESS_HI_MASK +#define TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask__SHIFT 0x0 +#define TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask_MASK 0xFFFFFFFFL +//TRAP10_COMMAND_MASK +#define TRAP10_COMMAND_MASK__Trap10Cmd0Mask__SHIFT 0x0 +#define TRAP10_COMMAND_MASK__Trap10Cmd1Mask__SHIFT 0x8 +#define TRAP10_COMMAND_MASK__Trap10Cmd0Mask_MASK 0x0000003FL +#define TRAP10_COMMAND_MASK__Trap10Cmd1Mask_MASK 0x00003F00L +//TRAP11_CONTROL0 +#define TRAP11_CONTROL0__Trap11En__SHIFT 0x0 +#define TRAP11_CONTROL0__Trap11SMUIntr__SHIFT 0x3 +#define TRAP11_CONTROL0__Trap11Stage2Ptr__SHIFT 0xe +#define TRAP11_CONTROL0__Trap11CrossTrigger__SHIFT 0x18 +#define TRAP11_CONTROL0__Trap11Stage2En__SHIFT 0x1f +#define TRAP11_CONTROL0__Trap11En_MASK 0x00000001L +#define TRAP11_CONTROL0__Trap11SMUIntr_MASK 0x00000008L +#define TRAP11_CONTROL0__Trap11Stage2Ptr_MASK 0x00FFC000L +#define TRAP11_CONTROL0__Trap11CrossTrigger_MASK 0x0F000000L +#define TRAP11_CONTROL0__Trap11Stage2En_MASK 0x80000000L +//TRAP11_ADDRESS_LO +#define TRAP11_ADDRESS_LO__Trap11AddrLo__SHIFT 0x2 +#define TRAP11_ADDRESS_LO__Trap11AddrLo_MASK 0xFFFFFFFCL +//TRAP11_ADDRESS_HI +#define TRAP11_ADDRESS_HI__Trap11AddrHi__SHIFT 0x0 +#define TRAP11_ADDRESS_HI__Trap11AddrHi_MASK 0xFFFFFFFFL +//TRAP11_COMMAND +#define TRAP11_COMMAND__Trap11Cmd0__SHIFT 0x0 +#define TRAP11_COMMAND__Trap11Cmd1__SHIFT 0x8 +#define TRAP11_COMMAND__Trap11Cmd0_MASK 0x0000003FL +#define TRAP11_COMMAND__Trap11Cmd1_MASK 0x00003F00L +//TRAP11_ADDRESS_LO_MASK +#define TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask__SHIFT 0x2 +#define TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask_MASK 0xFFFFFFFCL +//TRAP11_ADDRESS_HI_MASK +#define TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask__SHIFT 0x0 +#define TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask_MASK 0xFFFFFFFFL +//TRAP11_COMMAND_MASK +#define TRAP11_COMMAND_MASK__Trap11Cmd0Mask__SHIFT 0x0 +#define TRAP11_COMMAND_MASK__Trap11Cmd1Mask__SHIFT 0x8 +#define TRAP11_COMMAND_MASK__Trap11Cmd0Mask_MASK 0x0000003FL +#define TRAP11_COMMAND_MASK__Trap11Cmd1Mask_MASK 0x00003F00L +//TRAP12_CONTROL0 +#define TRAP12_CONTROL0__Trap12En__SHIFT 0x0 +#define TRAP12_CONTROL0__Trap12SMUIntr__SHIFT 0x3 +#define TRAP12_CONTROL0__Trap12Stage2Ptr__SHIFT 0xe +#define TRAP12_CONTROL0__Trap12CrossTrigger__SHIFT 0x18 +#define TRAP12_CONTROL0__Trap12Stage2En__SHIFT 0x1f +#define TRAP12_CONTROL0__Trap12En_MASK 0x00000001L +#define TRAP12_CONTROL0__Trap12SMUIntr_MASK 0x00000008L +#define TRAP12_CONTROL0__Trap12Stage2Ptr_MASK 0x00FFC000L +#define TRAP12_CONTROL0__Trap12CrossTrigger_MASK 0x0F000000L +#define TRAP12_CONTROL0__Trap12Stage2En_MASK 0x80000000L +//TRAP12_ADDRESS_LO +#define TRAP12_ADDRESS_LO__Trap12AddrLo__SHIFT 0x2 +#define TRAP12_ADDRESS_LO__Trap12AddrLo_MASK 0xFFFFFFFCL +//TRAP12_ADDRESS_HI +#define TRAP12_ADDRESS_HI__Trap12AddrHi__SHIFT 0x0 +#define TRAP12_ADDRESS_HI__Trap12AddrHi_MASK 0xFFFFFFFFL +//TRAP12_COMMAND +#define TRAP12_COMMAND__Trap12Cmd0__SHIFT 0x0 +#define TRAP12_COMMAND__Trap12Cmd1__SHIFT 0x8 +#define TRAP12_COMMAND__Trap12Cmd0_MASK 0x0000003FL +#define TRAP12_COMMAND__Trap12Cmd1_MASK 0x00003F00L +//TRAP12_ADDRESS_LO_MASK +#define TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask__SHIFT 0x2 +#define TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask_MASK 0xFFFFFFFCL +//TRAP12_ADDRESS_HI_MASK +#define TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask__SHIFT 0x0 +#define TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask_MASK 0xFFFFFFFFL +//TRAP12_COMMAND_MASK +#define TRAP12_COMMAND_MASK__Trap12Cmd0Mask__SHIFT 0x0 +#define TRAP12_COMMAND_MASK__Trap12Cmd1Mask__SHIFT 0x8 +#define TRAP12_COMMAND_MASK__Trap12Cmd0Mask_MASK 0x0000003FL +#define TRAP12_COMMAND_MASK__Trap12Cmd1Mask_MASK 0x00003F00L +//TRAP13_CONTROL0 +#define TRAP13_CONTROL0__Trap13En__SHIFT 0x0 +#define TRAP13_CONTROL0__Trap13SMUIntr__SHIFT 0x3 +#define TRAP13_CONTROL0__Trap13Stage2Ptr__SHIFT 0xe +#define TRAP13_CONTROL0__Trap13CrossTrigger__SHIFT 0x18 +#define TRAP13_CONTROL0__Trap13Stage2En__SHIFT 0x1f +#define TRAP13_CONTROL0__Trap13En_MASK 0x00000001L +#define TRAP13_CONTROL0__Trap13SMUIntr_MASK 0x00000008L +#define TRAP13_CONTROL0__Trap13Stage2Ptr_MASK 0x00FFC000L +#define TRAP13_CONTROL0__Trap13CrossTrigger_MASK 0x0F000000L +#define TRAP13_CONTROL0__Trap13Stage2En_MASK 0x80000000L +//TRAP13_ADDRESS_LO +#define TRAP13_ADDRESS_LO__Trap13AddrLo__SHIFT 0x2 +#define TRAP13_ADDRESS_LO__Trap13AddrLo_MASK 0xFFFFFFFCL +//TRAP13_ADDRESS_HI +#define TRAP13_ADDRESS_HI__Trap13AddrHi__SHIFT 0x0 +#define TRAP13_ADDRESS_HI__Trap13AddrHi_MASK 0xFFFFFFFFL +//TRAP13_COMMAND +#define TRAP13_COMMAND__Trap13Cmd0__SHIFT 0x0 +#define TRAP13_COMMAND__Trap13Cmd1__SHIFT 0x8 +#define TRAP13_COMMAND__Trap13Cmd0_MASK 0x0000003FL +#define TRAP13_COMMAND__Trap13Cmd1_MASK 0x00003F00L +//TRAP13_ADDRESS_LO_MASK +#define TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask__SHIFT 0x2 +#define TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask_MASK 0xFFFFFFFCL +//TRAP13_ADDRESS_HI_MASK +#define TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask__SHIFT 0x0 +#define TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask_MASK 0xFFFFFFFFL +//TRAP13_COMMAND_MASK +#define TRAP13_COMMAND_MASK__Trap13Cmd0Mask__SHIFT 0x0 +#define TRAP13_COMMAND_MASK__Trap13Cmd1Mask__SHIFT 0x8 +#define TRAP13_COMMAND_MASK__Trap13Cmd0Mask_MASK 0x0000003FL +#define TRAP13_COMMAND_MASK__Trap13Cmd1Mask_MASK 0x00003F00L +//TRAP14_CONTROL0 +#define TRAP14_CONTROL0__Trap14En__SHIFT 0x0 +#define TRAP14_CONTROL0__Trap14SMUIntr__SHIFT 0x3 +#define TRAP14_CONTROL0__Trap14Stage2Ptr__SHIFT 0xe +#define TRAP14_CONTROL0__Trap14CrossTrigger__SHIFT 0x18 +#define TRAP14_CONTROL0__Trap14Stage2En__SHIFT 0x1f +#define TRAP14_CONTROL0__Trap14En_MASK 0x00000001L +#define TRAP14_CONTROL0__Trap14SMUIntr_MASK 0x00000008L +#define TRAP14_CONTROL0__Trap14Stage2Ptr_MASK 0x00FFC000L +#define TRAP14_CONTROL0__Trap14CrossTrigger_MASK 0x0F000000L +#define TRAP14_CONTROL0__Trap14Stage2En_MASK 0x80000000L +//TRAP14_ADDRESS_LO +#define TRAP14_ADDRESS_LO__Trap14AddrLo__SHIFT 0x2 +#define TRAP14_ADDRESS_LO__Trap14AddrLo_MASK 0xFFFFFFFCL +//TRAP14_ADDRESS_HI +#define TRAP14_ADDRESS_HI__Trap14AddrHi__SHIFT 0x0 +#define TRAP14_ADDRESS_HI__Trap14AddrHi_MASK 0xFFFFFFFFL +//TRAP14_COMMAND +#define TRAP14_COMMAND__Trap14Cmd0__SHIFT 0x0 +#define TRAP14_COMMAND__Trap14Cmd1__SHIFT 0x8 +#define TRAP14_COMMAND__Trap14Cmd0_MASK 0x0000003FL +#define TRAP14_COMMAND__Trap14Cmd1_MASK 0x00003F00L +//TRAP14_ADDRESS_LO_MASK +#define TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask__SHIFT 0x2 +#define TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask_MASK 0xFFFFFFFCL +//TRAP14_ADDRESS_HI_MASK +#define TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask__SHIFT 0x0 +#define TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask_MASK 0xFFFFFFFFL +//TRAP14_COMMAND_MASK +#define TRAP14_COMMAND_MASK__Trap14Cmd0Mask__SHIFT 0x0 +#define TRAP14_COMMAND_MASK__Trap14Cmd1Mask__SHIFT 0x8 +#define TRAP14_COMMAND_MASK__Trap14Cmd0Mask_MASK 0x0000003FL +#define TRAP14_COMMAND_MASK__Trap14Cmd1Mask_MASK 0x00003F00L +//TRAP15_CONTROL0 +#define TRAP15_CONTROL0__Trap15En__SHIFT 0x0 +#define TRAP15_CONTROL0__Trap15SMUIntr__SHIFT 0x3 +#define TRAP15_CONTROL0__Trap15Stage2Ptr__SHIFT 0xe +#define TRAP15_CONTROL0__Trap15CrossTrigger__SHIFT 0x18 +#define TRAP15_CONTROL0__Trap15Stage2En__SHIFT 0x1f +#define TRAP15_CONTROL0__Trap15En_MASK 0x00000001L +#define TRAP15_CONTROL0__Trap15SMUIntr_MASK 0x00000008L +#define TRAP15_CONTROL0__Trap15Stage2Ptr_MASK 0x00FFC000L +#define TRAP15_CONTROL0__Trap15CrossTrigger_MASK 0x0F000000L +#define TRAP15_CONTROL0__Trap15Stage2En_MASK 0x80000000L +//TRAP15_ADDRESS_LO +#define TRAP15_ADDRESS_LO__Trap15AddrLo__SHIFT 0x2 +#define TRAP15_ADDRESS_LO__Trap15AddrLo_MASK 0xFFFFFFFCL +//TRAP15_ADDRESS_HI +#define TRAP15_ADDRESS_HI__Trap15AddrHi__SHIFT 0x0 +#define TRAP15_ADDRESS_HI__Trap15AddrHi_MASK 0xFFFFFFFFL +//TRAP15_COMMAND +#define TRAP15_COMMAND__Trap15Cmd0__SHIFT 0x0 +#define TRAP15_COMMAND__Trap15Cmd1__SHIFT 0x8 +#define TRAP15_COMMAND__Trap15Cmd0_MASK 0x0000003FL +#define TRAP15_COMMAND__Trap15Cmd1_MASK 0x00003F00L +//TRAP15_ADDRESS_LO_MASK +#define TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask__SHIFT 0x2 +#define TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask_MASK 0xFFFFFFFCL +//TRAP15_ADDRESS_HI_MASK +#define TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask__SHIFT 0x0 +#define TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask_MASK 0xFFFFFFFFL +//TRAP15_COMMAND_MASK +#define TRAP15_COMMAND_MASK__Trap15Cmd0Mask__SHIFT 0x0 +#define TRAP15_COMMAND_MASK__Trap15Cmd1Mask__SHIFT 0x8 +#define TRAP15_COMMAND_MASK__Trap15Cmd0Mask_MASK 0x0000003FL +#define TRAP15_COMMAND_MASK__Trap15Cmd1Mask_MASK 0x00003F00L +//SB_COMMAND +#define SB_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define SB_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define SB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define SB_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define SB_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define SB_COMMAND__BUS_MASTER_EN_MASK 0x0004L +//SB_SUB_BUS_NUMBER_LATENCY +#define SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +//SB_IO_BASE_LIMIT +#define SB_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define SB_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define SB_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define SB_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//SB_MEM_BASE_LIMIT +#define SB_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define SB_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//SB_PREF_BASE_LIMIT +#define SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//SB_PREF_BASE_UPPER +#define SB_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define SB_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//SB_PREF_LIMIT_UPPER +#define SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//SB_IO_BASE_LIMIT_HI +#define SB_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define SB_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//SB_IRQ_BRIDGE_CNTL +#define SB_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define SB_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define SB_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define SB_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define SB_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define SB_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +//SB_EXT_BRIDGE_CNTL +#define SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//SB_PMI_STATUS_CNTL +#define SB_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define SB_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L +//SB_SLOT_CAP +#define SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +//SB_ROOT_CNTL +#define SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//SB_DEVICE_CNTL2 +#define SB_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define SB_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +//MCA_SMN_INT_REQ_ADDR +#define MCA_SMN_INT_REQ_ADDR__SMN_INT_REQ_ADDR__SHIFT 0x0 +#define MCA_SMN_INT_REQ_ADDR__SMN_INT_REQ_ADDR_MASK 0x000FFFFFL +//MCA_SMN_INT_MCM_ADDR +#define MCA_SMN_INT_MCM_ADDR__SMN_INT_MCM_ADDR__SHIFT 0x0 +#define MCA_SMN_INT_MCM_ADDR__SMN_INT_MCM_ADDR_MASK 0x000000FFL +//MCA_SMN_INT_APERTUREID +#define MCA_SMN_INT_APERTUREID__SMN_INT_APERTUREID__SHIFT 0x0 +#define MCA_SMN_INT_APERTUREID__SMN_INT_APERTUREID_MASK 0x00000FFFL +//MCA_SMN_INT_CONTROL +#define MCA_SMN_INT_CONTROL__MCACrossTrigger__SHIFT 0x0 +#define MCA_SMN_INT_CONTROL__MCACrossTrigger_MASK 0x0000000FL + + +// addressBlock: aid_nbio_iohub_nb_rascfg_ras_cfgdec +//PARITY_CONTROL_0 +#define PARITY_CONTROL_0__ParityCorrThreshold__SHIFT 0x0 +#define PARITY_CONTROL_0__ParityUCPThreshold__SHIFT 0x10 +#define PARITY_CONTROL_0__ParityCorrThreshold_MASK 0x0000FFFFL +#define PARITY_CONTROL_0__ParityUCPThreshold_MASK 0xFFFF0000L +//PARITY_CONTROL_1 +#define PARITY_CONTROL_1__ParityErrGenGroupSel__SHIFT 0x0 +#define PARITY_CONTROL_1__ParityErrGenGroupTypeSel__SHIFT 0x8 +#define PARITY_CONTROL_1__ParityErrGenIdSel__SHIFT 0xb +#define PARITY_CONTROL_1__ParityErrGenCmd__SHIFT 0x10 +#define PARITY_CONTROL_1__ParityErrGenTrigger__SHIFT 0x1e +#define PARITY_CONTROL_1__ParityErrGenInjectAllow__SHIFT 0x1f +#define PARITY_CONTROL_1__ParityErrGenGroupSel_MASK 0x000000FFL +#define PARITY_CONTROL_1__ParityErrGenGroupTypeSel_MASK 0x00000100L +#define PARITY_CONTROL_1__ParityErrGenIdSel_MASK 0x0000F800L +#define PARITY_CONTROL_1__ParityErrGenCmd_MASK 0x000F0000L +#define PARITY_CONTROL_1__ParityErrGenTrigger_MASK 0x40000000L +#define PARITY_CONTROL_1__ParityErrGenInjectAllow_MASK 0x80000000L +//PARITY_SEVERITY_CONTROL_UNCORR_0 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0__SHIFT 0x0 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1__SHIFT 0x2 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2__SHIFT 0x4 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3__SHIFT 0x6 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4__SHIFT 0x8 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp5__SHIFT 0xa +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp6__SHIFT 0xc +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp7__SHIFT 0xe +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp8__SHIFT 0x10 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp9__SHIFT 0x12 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp10__SHIFT 0x14 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp11__SHIFT 0x16 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp12__SHIFT 0x18 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp13__SHIFT 0x1a +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp14__SHIFT 0x1c +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp15__SHIFT 0x1e +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0_MASK 0x00000003L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1_MASK 0x0000000CL +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2_MASK 0x00000030L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3_MASK 0x000000C0L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4_MASK 0x00000300L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp5_MASK 0x00000C00L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp6_MASK 0x00003000L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp7_MASK 0x0000C000L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp8_MASK 0x00030000L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp9_MASK 0x000C0000L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp10_MASK 0x00300000L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp11_MASK 0x00C00000L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp12_MASK 0x03000000L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp13_MASK 0x0C000000L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp14_MASK 0x30000000L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp15_MASK 0xC0000000L +//PARITY_SEVERITY_CONTROL_CORR_0 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0__SHIFT 0x0 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1__SHIFT 0x2 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2__SHIFT 0x4 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3__SHIFT 0x6 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4__SHIFT 0x8 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp5__SHIFT 0xa +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp6__SHIFT 0xc +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp7__SHIFT 0xe +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp8__SHIFT 0x10 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp9__SHIFT 0x12 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp10__SHIFT 0x14 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp11__SHIFT 0x16 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp12__SHIFT 0x18 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp13__SHIFT 0x1a +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp14__SHIFT 0x1c +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp15__SHIFT 0x1e +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0_MASK 0x00000003L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1_MASK 0x0000000CL +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2_MASK 0x00000030L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3_MASK 0x000000C0L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4_MASK 0x00000300L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp5_MASK 0x00000C00L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp6_MASK 0x00003000L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp7_MASK 0x0000C000L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp8_MASK 0x00030000L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp9_MASK 0x000C0000L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp10_MASK 0x00300000L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp11_MASK 0x00C00000L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp12_MASK 0x03000000L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp13_MASK 0x0C000000L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp14_MASK 0x30000000L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp15_MASK 0xC0000000L +//PARITY_SEVERITY_CONTROL_UCP_0 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0__SHIFT 0x0 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1__SHIFT 0x2 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2__SHIFT 0x4 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3__SHIFT 0x6 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4__SHIFT 0x8 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp5__SHIFT 0xa +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp6__SHIFT 0xc +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp7__SHIFT 0xe +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp8__SHIFT 0x10 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp9__SHIFT 0x12 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp10__SHIFT 0x14 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp11__SHIFT 0x16 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp12__SHIFT 0x18 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0_MASK 0x00000003L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1_MASK 0x0000000CL +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2_MASK 0x00000030L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3_MASK 0x000000C0L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4_MASK 0x00000300L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp5_MASK 0x00000C00L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp6_MASK 0x00003000L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp7_MASK 0x0000C000L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp8_MASK 0x00030000L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp9_MASK 0x000C0000L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp10_MASK 0x00300000L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp11_MASK 0x00C00000L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp12_MASK 0x03000000L +//RAS_GLOBAL_STATUS_LO +#define RAS_GLOBAL_STATUS_LO__ParityErrCorr__SHIFT 0x0 +#define RAS_GLOBAL_STATUS_LO__ParityErrNonFatal__SHIFT 0x1 +#define RAS_GLOBAL_STATUS_LO__ParityErrFatal__SHIFT 0x2 +#define RAS_GLOBAL_STATUS_LO__ParityErrSerr__SHIFT 0x3 +#define RAS_GLOBAL_STATUS_LO__HPLGWA_NMI__SHIFT 0x6 +#define RAS_GLOBAL_STATUS_LO__HPLGWA_SCI__SHIFT 0x7 +#define RAS_GLOBAL_STATUS_LO__HPLGWA_SMI__SHIFT 0x8 +#define RAS_GLOBAL_STATUS_LO__SW_SMI__SHIFT 0x9 +#define RAS_GLOBAL_STATUS_LO__SW_SCI__SHIFT 0xa +#define RAS_GLOBAL_STATUS_LO__SW_NMI__SHIFT 0xb +#define RAS_GLOBAL_STATUS_LO__APML_NMI__SHIFT 0xc +#define RAS_GLOBAL_STATUS_LO__APML_SyncFld__SHIFT 0xd +#define RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI__SHIFT 0xe +#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private__SHIFT 0xf +#define RAS_GLOBAL_STATUS_LO__ParityErrCorr_MASK 0x00000001L +#define RAS_GLOBAL_STATUS_LO__ParityErrNonFatal_MASK 0x00000002L +#define RAS_GLOBAL_STATUS_LO__ParityErrFatal_MASK 0x00000004L +#define RAS_GLOBAL_STATUS_LO__ParityErrSerr_MASK 0x00000008L +#define RAS_GLOBAL_STATUS_LO__HPLGWA_NMI_MASK 0x00000040L +#define RAS_GLOBAL_STATUS_LO__HPLGWA_SCI_MASK 0x00000080L +#define RAS_GLOBAL_STATUS_LO__HPLGWA_SMI_MASK 0x00000100L +#define RAS_GLOBAL_STATUS_LO__SW_SMI_MASK 0x00000200L +#define RAS_GLOBAL_STATUS_LO__SW_SCI_MASK 0x00000400L +#define RAS_GLOBAL_STATUS_LO__SW_NMI_MASK 0x00000800L +#define RAS_GLOBAL_STATUS_LO__APML_NMI_MASK 0x00001000L +#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_MASK 0x00002000L +#define RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI_MASK 0x00004000L +#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private_MASK 0x00008000L +//RAS_GLOBAL_STATUS_HI +#define RAS_GLOBAL_STATUS_HI__PCIE0PortAErr__SHIFT 0x0 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortBErr__SHIFT 0x1 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortCErr__SHIFT 0x2 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortDErr__SHIFT 0x3 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortEErr__SHIFT 0x4 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortFErr__SHIFT 0x5 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortGErr__SHIFT 0x6 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortHErr__SHIFT 0x7 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortIErr__SHIFT 0x8 +#define RAS_GLOBAL_STATUS_HI__PCIE1PortAErr__SHIFT 0x9 +#define RAS_GLOBAL_STATUS_HI__PCIE1PortBErr__SHIFT 0xa +#define RAS_GLOBAL_STATUS_HI__PCIE1PortCErr__SHIFT 0xb +#define RAS_GLOBAL_STATUS_HI__PCIE1PortDErr__SHIFT 0xc +#define RAS_GLOBAL_STATUS_HI__NBIF1PortAErr__SHIFT 0xd +#define RAS_GLOBAL_STATUS_HI__PCIE0PortAErr_MASK 0x00000001L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortBErr_MASK 0x00000002L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortCErr_MASK 0x00000004L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortDErr_MASK 0x00000008L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortEErr_MASK 0x00000010L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortFErr_MASK 0x00000020L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortGErr_MASK 0x00000040L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortHErr_MASK 0x00000080L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortIErr_MASK 0x00000100L +#define RAS_GLOBAL_STATUS_HI__PCIE1PortAErr_MASK 0x00000200L +#define RAS_GLOBAL_STATUS_HI__PCIE1PortBErr_MASK 0x00000400L +#define RAS_GLOBAL_STATUS_HI__PCIE1PortCErr_MASK 0x00000800L +#define RAS_GLOBAL_STATUS_HI__PCIE1PortDErr_MASK 0x00001000L +#define RAS_GLOBAL_STATUS_HI__NBIF1PortAErr_MASK 0x00002000L +//PARITY_ERROR_STATUS_UNCORR_GRP0 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP1 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP2 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP3 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP4 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP5 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP6 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP7 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP10 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP11 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP12 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP13 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP14 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP15 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP16 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP0 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP1 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP2 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP3 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP4 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP5 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP6 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP7 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP10 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP11 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP12 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP13 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP14 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP15 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP16 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP17 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP0 +#define PARITY_COUNTER_CORR_GRP0__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP0__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP0__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP0__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP1 +#define PARITY_COUNTER_CORR_GRP1__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP1__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP1__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP1__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP2 +#define PARITY_COUNTER_CORR_GRP2__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP2__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP2__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP2__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP3 +#define PARITY_COUNTER_CORR_GRP3__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP3__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP3__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP3__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP4 +#define PARITY_COUNTER_CORR_GRP4__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP4__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP4__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP4__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP5 +#define PARITY_COUNTER_CORR_GRP5__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP5__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP5__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP5__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP6 +#define PARITY_COUNTER_CORR_GRP6__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP6__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP6__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP6__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP7 +#define PARITY_COUNTER_CORR_GRP7__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP7__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP7__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP7__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP10 +#define PARITY_COUNTER_CORR_GRP10__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP10__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP10__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP10__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP11 +#define PARITY_COUNTER_CORR_GRP11__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP11__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP11__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP11__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP12 +#define PARITY_COUNTER_CORR_GRP12__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP12__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP12__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP12__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP13 +#define PARITY_COUNTER_CORR_GRP13__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP13__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP13__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP13__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP14 +#define PARITY_COUNTER_CORR_GRP14__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP14__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP14__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP14__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP15 +#define PARITY_COUNTER_CORR_GRP15__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP15__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP15__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP15__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP16 +#define PARITY_COUNTER_CORR_GRP16__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP16__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP16__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP16__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP17 +#define PARITY_COUNTER_CORR_GRP17__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP17__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP17__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP17__ResetEn_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP0 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP1 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP2 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP3 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP4 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP5 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP6 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP7 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP10 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP11 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP12 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP0 +#define PARITY_COUNTER_UCP_GRP0__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP0__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP0__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP0__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP1 +#define PARITY_COUNTER_UCP_GRP1__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP1__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP1__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP1__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP2 +#define PARITY_COUNTER_UCP_GRP2__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP2__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP2__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP2__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP3 +#define PARITY_COUNTER_UCP_GRP3__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP3__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP3__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP3__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP4 +#define PARITY_COUNTER_UCP_GRP4__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP4__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP4__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP4__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP5 +#define PARITY_COUNTER_UCP_GRP5__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP5__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP5__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP5__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP6 +#define PARITY_COUNTER_UCP_GRP6__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP6__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP6__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP6__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP7 +#define PARITY_COUNTER_UCP_GRP7__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP7__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP7__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP7__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP10 +#define PARITY_COUNTER_UCP_GRP10__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP10__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP10__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP10__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP11 +#define PARITY_COUNTER_UCP_GRP11__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP11__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP11__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP11__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP12 +#define PARITY_COUNTER_UCP_GRP12__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP12__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP12__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP12__ResetEn_MASK 0x80000000L +//MISC_SEVERITY_CONTROL +#define MISC_SEVERITY_CONTROL__ErrEventErrSev__SHIFT 0x4 +#define MISC_SEVERITY_CONTROL__PcieParityErrSev__SHIFT 0x6 +#define MISC_SEVERITY_CONTROL__ErrEventErrSev_MASK 0x00000030L +#define MISC_SEVERITY_CONTROL__PcieParityErrSev_MASK 0x000000C0L +//MISC_RAS_CONTROL +#define MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En__SHIFT 0x2 +#define MISC_RAS_CONTROL__GNB_SB_LinkNeverDis__SHIFT 0x3 +#define MISC_RAS_CONTROL__InterruptOutputDis__SHIFT 0x9 +#define MISC_RAS_CONTROL__LinkDisOutputDis__SHIFT 0xa +#define MISC_RAS_CONTROL__SyncFldOutputDis__SHIFT 0xb +#define MISC_RAS_CONTROL__PCIe_NMI_En__SHIFT 0xc +#define MISC_RAS_CONTROL__PCIe_SCI_En__SHIFT 0xd +#define MISC_RAS_CONTROL__PCIe_SMI_En__SHIFT 0xe +#define MISC_RAS_CONTROL__SW_SCI_En__SHIFT 0xf +#define MISC_RAS_CONTROL__SW_SMI_En__SHIFT 0x10 +#define MISC_RAS_CONTROL__SW_NMI_En__SHIFT 0x11 +#define MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En_MASK 0x00000004L +#define MISC_RAS_CONTROL__GNB_SB_LinkNeverDis_MASK 0x00000008L +#define MISC_RAS_CONTROL__InterruptOutputDis_MASK 0x00000200L +#define MISC_RAS_CONTROL__LinkDisOutputDis_MASK 0x00000400L +#define MISC_RAS_CONTROL__SyncFldOutputDis_MASK 0x00000800L +#define MISC_RAS_CONTROL__PCIe_NMI_En_MASK 0x00001000L +#define MISC_RAS_CONTROL__PCIe_SCI_En_MASK 0x00002000L +#define MISC_RAS_CONTROL__PCIe_SMI_En_MASK 0x00004000L +#define MISC_RAS_CONTROL__SW_SCI_En_MASK 0x00008000L +#define MISC_RAS_CONTROL__SW_SMI_En_MASK 0x00010000L +#define MISC_RAS_CONTROL__SW_NMI_En_MASK 0x00020000L +//RAS_SCRATCH_0 +#define RAS_SCRATCH_0__SCRATCH_0__SHIFT 0x0 +#define RAS_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL +//RAS_SCRATCH_1 +#define RAS_SCRATCH_1__SCRATCH_1__SHIFT 0x0 +#define RAS_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL +//ErrEvent_ACTION_CONTROL +#define ErrEvent_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define ErrEvent_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define ErrEvent_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define ErrEvent_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define ErrEvent_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define ErrEvent_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define ErrEvent_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define ErrEvent_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//ParitySerr_ACTION_CONTROL +#define ParitySerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define ParitySerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define ParitySerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define ParitySerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define ParitySerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define ParitySerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define ParitySerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define ParitySerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//ParityFatal_ACTION_CONTROL +#define ParityFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define ParityFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define ParityFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define ParityFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define ParityFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define ParityFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define ParityFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define ParityFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//ParityNonFatal_ACTION_CONTROL +#define ParityNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define ParityNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define ParityNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define ParityNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define ParityNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define ParityNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define ParityNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define ParityNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//ParityCorr_ACTION_CONTROL +#define ParityCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define ParityCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define ParityCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define ParityCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define ParityCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define ParityCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define ParityCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define ParityCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortASerr_ACTION_CONTROL +#define PCIE0PortASerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortASerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortASerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortASerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortASerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortASerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortASerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortASerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortAIntFatal_ACTION_CONTROL +#define PCIE0PortAIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortAIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortAIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortAIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortAIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortAIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortAIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortAIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortAIntNonFatal_ACTION_CONTROL +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortAIntCorr_ACTION_CONTROL +#define PCIE0PortAIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortAIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortAIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortAIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortAIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortAIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortAIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortAIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortAExtFatal_ACTION_CONTROL +#define PCIE0PortAExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortAExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortAExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortAExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortAExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortAExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortAExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortAExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortAExtNonFatal_ACTION_CONTROL +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortAExtCorr_ACTION_CONTROL +#define PCIE0PortAExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortAExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortAExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortAExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortAExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortAExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortAExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortAExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortAParityErr_ACTION_CONTROL +#define PCIE0PortAParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortAParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortAParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortAParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortAParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortAParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortAParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortAParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBSerr_ACTION_CONTROL +#define PCIE0PortBSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBIntFatal_ACTION_CONTROL +#define PCIE0PortBIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBIntNonFatal_ACTION_CONTROL +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBIntCorr_ACTION_CONTROL +#define PCIE0PortBIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBExtFatal_ACTION_CONTROL +#define PCIE0PortBExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBExtNonFatal_ACTION_CONTROL +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBExtCorr_ACTION_CONTROL +#define PCIE0PortBExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBParityErr_ACTION_CONTROL +#define PCIE0PortBParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCSerr_ACTION_CONTROL +#define PCIE0PortCSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCIntFatal_ACTION_CONTROL +#define PCIE0PortCIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCIntNonFatal_ACTION_CONTROL +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCIntCorr_ACTION_CONTROL +#define PCIE0PortCIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCExtFatal_ACTION_CONTROL +#define PCIE0PortCExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCExtNonFatal_ACTION_CONTROL +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCExtCorr_ACTION_CONTROL +#define PCIE0PortCExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCParityErr_ACTION_CONTROL +#define PCIE0PortCParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDSerr_ACTION_CONTROL +#define PCIE0PortDSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDIntFatal_ACTION_CONTROL +#define PCIE0PortDIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDIntNonFatal_ACTION_CONTROL +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDIntCorr_ACTION_CONTROL +#define PCIE0PortDIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDExtFatal_ACTION_CONTROL +#define PCIE0PortDExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDExtNonFatal_ACTION_CONTROL +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDExtCorr_ACTION_CONTROL +#define PCIE0PortDExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDParityErr_ACTION_CONTROL +#define PCIE0PortDParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortESerr_ACTION_CONTROL +#define PCIE0PortESerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortESerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortESerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortESerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortESerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortESerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortESerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortESerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortEIntFatal_ACTION_CONTROL +#define PCIE0PortEIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortEIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortEIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortEIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortEIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortEIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortEIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortEIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortEIntNonFatal_ACTION_CONTROL +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortEIntCorr_ACTION_CONTROL +#define PCIE0PortEIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortEIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortEIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortEIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortEIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortEIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortEIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortEIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortEExtFatal_ACTION_CONTROL +#define PCIE0PortEExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortEExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortEExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortEExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortEExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortEExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortEExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortEExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortEExtNonFatal_ACTION_CONTROL +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortEExtCorr_ACTION_CONTROL +#define PCIE0PortEExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortEExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortEExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortEExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortEExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortEExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortEExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortEExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortEParityErr_ACTION_CONTROL +#define PCIE0PortEParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortEParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortEParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortEParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortEParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortEParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortEParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortEParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFSerr_ACTION_CONTROL +#define PCIE0PortFSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFIntFatal_ACTION_CONTROL +#define PCIE0PortFIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFIntNonFatal_ACTION_CONTROL +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFIntCorr_ACTION_CONTROL +#define PCIE0PortFIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFExtFatal_ACTION_CONTROL +#define PCIE0PortFExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFExtNonFatal_ACTION_CONTROL +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFExtCorr_ACTION_CONTROL +#define PCIE0PortFExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFParityErr_ACTION_CONTROL +#define PCIE0PortFParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGSerr_ACTION_CONTROL +#define PCIE0PortGSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGIntFatal_ACTION_CONTROL +#define PCIE0PortGIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGIntNonFatal_ACTION_CONTROL +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGIntCorr_ACTION_CONTROL +#define PCIE0PortGIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGExtFatal_ACTION_CONTROL +#define PCIE0PortGExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGExtNonFatal_ACTION_CONTROL +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGExtCorr_ACTION_CONTROL +#define PCIE0PortGExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGParityErr_ACTION_CONTROL +#define PCIE0PortGParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortASerr_ACTION_CONTROL +#define NBIF1PortASerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortASerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortASerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortASerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortASerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortASerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortASerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortASerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortAIntFatal_ACTION_CONTROL +#define NBIF1PortAIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortAIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortAIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortAIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortAIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortAIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortAIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortAIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortAIntNonFatal_ACTION_CONTROL +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortAIntCorr_ACTION_CONTROL +#define NBIF1PortAIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortAIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortAIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortAIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortAIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortAIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortAIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortAIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortAExtFatal_ACTION_CONTROL +#define NBIF1PortAExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortAExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortAExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortAExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortAExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortAExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortAExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortAExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortAExtNonFatal_ACTION_CONTROL +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortAExtCorr_ACTION_CONTROL +#define NBIF1PortAExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortAExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortAExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortAExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortAExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortAExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortAExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortAExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortAParityErr_ACTION_CONTROL +#define NBIF1PortAParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortAParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortAParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortAParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortAParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortAParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortAParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortAParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//SYNCFLOOD_STATUS +#define SYNCFLOOD_STATUS__SyncfloodFromRASCntl__SHIFT 0x0 +#define SYNCFLOOD_STATUS__SyncfloodFromAPML__SHIFT 0x1 +#define SYNCFLOOD_STATUS__SyncfloodFromPin__SHIFT 0x2 +#define SYNCFLOOD_STATUS__SyncfloodFromPrivate__SHIFT 0x4 +#define SYNCFLOOD_STATUS__SyncfloodFromMCA__SHIFT 0x5 +#define SYNCFLOOD_STATUS__SyncfloodFromRASCntl_MASK 0x00000001L +#define SYNCFLOOD_STATUS__SyncfloodFromAPML_MASK 0x00000002L +#define SYNCFLOOD_STATUS__SyncfloodFromPin_MASK 0x00000004L +#define SYNCFLOOD_STATUS__SyncfloodFromPrivate_MASK 0x00000010L +#define SYNCFLOOD_STATUS__SyncfloodFromMCA_MASK 0x00000020L +//NMI_STATUS +#define NMI_STATUS__NMIFromPin__SHIFT 0x0 +#define NMI_STATUS__NMIFromPin_MASK 0x00000001L +//POISON_ACTION_CONTROL +#define POISON_ACTION_CONTROL__IntPoisonAPMLErrEn__SHIFT 0x0 +#define POISON_ACTION_CONTROL__IntPoisonIntrGenSel__SHIFT 0x1 +#define POISON_ACTION_CONTROL__IntPoisonLinkDisEn__SHIFT 0x3 +#define POISON_ACTION_CONTROL__IntPoisonSyncFloodEn__SHIFT 0x4 +#define POISON_ACTION_CONTROL__EgressPoisonLSAPMLErrEn__SHIFT 0x8 +#define POISON_ACTION_CONTROL__EgressPoisonLSIntrGenSel__SHIFT 0x9 +#define POISON_ACTION_CONTROL__EgressPoisonLSLinkDisEn__SHIFT 0xb +#define POISON_ACTION_CONTROL__EgressPoisonLSSyncFloodEn__SHIFT 0xc +#define POISON_ACTION_CONTROL__EgressPoisonHSAPMLErrEn__SHIFT 0x10 +#define POISON_ACTION_CONTROL__EgressPoisonHSIntrGenSel__SHIFT 0x11 +#define POISON_ACTION_CONTROL__EgressPoisonHSLinkDisEn__SHIFT 0x13 +#define POISON_ACTION_CONTROL__EgressPoisonHSSyncFloodEn__SHIFT 0x14 +#define POISON_ACTION_CONTROL__IntPoisonAPMLErrEn_MASK 0x00000001L +#define POISON_ACTION_CONTROL__IntPoisonIntrGenSel_MASK 0x00000006L +#define POISON_ACTION_CONTROL__IntPoisonLinkDisEn_MASK 0x00000008L +#define POISON_ACTION_CONTROL__IntPoisonSyncFloodEn_MASK 0x00000010L +#define POISON_ACTION_CONTROL__EgressPoisonLSAPMLErrEn_MASK 0x00000100L +#define POISON_ACTION_CONTROL__EgressPoisonLSIntrGenSel_MASK 0x00000600L +#define POISON_ACTION_CONTROL__EgressPoisonLSLinkDisEn_MASK 0x00000800L +#define POISON_ACTION_CONTROL__EgressPoisonLSSyncFloodEn_MASK 0x00001000L +#define POISON_ACTION_CONTROL__EgressPoisonHSAPMLErrEn_MASK 0x00010000L +#define POISON_ACTION_CONTROL__EgressPoisonHSIntrGenSel_MASK 0x00060000L +#define POISON_ACTION_CONTROL__EgressPoisonHSLinkDisEn_MASK 0x00080000L +#define POISON_ACTION_CONTROL__EgressPoisonHSSyncFloodEn_MASK 0x00100000L +//INTERNAL_POISON_STATUS +#define INTERNAL_POISON_STATUS__IntPoisonStatus_0__SHIFT 0x0 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_1__SHIFT 0x1 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_2__SHIFT 0x2 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_3__SHIFT 0x3 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_4__SHIFT 0x4 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_5__SHIFT 0x5 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_6__SHIFT 0x6 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_7__SHIFT 0x7 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_0_MASK 0x00000001L +#define INTERNAL_POISON_STATUS__IntPoisonStatus_1_MASK 0x00000002L +#define INTERNAL_POISON_STATUS__IntPoisonStatus_2_MASK 0x00000004L +#define INTERNAL_POISON_STATUS__IntPoisonStatus_3_MASK 0x00000008L +#define INTERNAL_POISON_STATUS__IntPoisonStatus_4_MASK 0x00000010L +#define INTERNAL_POISON_STATUS__IntPoisonStatus_5_MASK 0x00000020L +#define INTERNAL_POISON_STATUS__IntPoisonStatus_6_MASK 0x00000040L +#define INTERNAL_POISON_STATUS__IntPoisonStatus_7_MASK 0x00000080L +//INTERNAL_POISON_MASK +#define INTERNAL_POISON_MASK__IntPoisonMask__SHIFT 0x0 +#define INTERNAL_POISON_MASK__IntPoisonMask_MASK 0x000000FFL +//EGRESS_POISON_STATUS_LO +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0__SHIFT 0x0 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1__SHIFT 0x1 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2__SHIFT 0x2 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3__SHIFT 0x3 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4__SHIFT 0x4 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5__SHIFT 0x5 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6__SHIFT 0x6 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7__SHIFT 0x7 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8__SHIFT 0x8 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9__SHIFT 0x9 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10__SHIFT 0xa +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11__SHIFT 0xb +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12__SHIFT 0xc +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13__SHIFT 0xd +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14__SHIFT 0xe +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15__SHIFT 0xf +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16__SHIFT 0x10 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17__SHIFT 0x11 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18__SHIFT 0x12 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19__SHIFT 0x13 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20__SHIFT 0x14 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21__SHIFT 0x15 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22__SHIFT 0x16 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23__SHIFT 0x17 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24__SHIFT 0x18 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25__SHIFT 0x19 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26__SHIFT 0x1a +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27__SHIFT 0x1b +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28__SHIFT 0x1c +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29__SHIFT 0x1d +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30__SHIFT 0x1e +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31__SHIFT 0x1f +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0_MASK 0x00000001L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1_MASK 0x00000002L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2_MASK 0x00000004L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3_MASK 0x00000008L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4_MASK 0x00000010L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5_MASK 0x00000020L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6_MASK 0x00000040L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7_MASK 0x00000080L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8_MASK 0x00000100L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9_MASK 0x00000200L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10_MASK 0x00000400L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11_MASK 0x00000800L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12_MASK 0x00001000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13_MASK 0x00002000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14_MASK 0x00004000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15_MASK 0x00008000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16_MASK 0x00010000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17_MASK 0x00020000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18_MASK 0x00040000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19_MASK 0x00080000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20_MASK 0x00100000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21_MASK 0x00200000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22_MASK 0x00400000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23_MASK 0x00800000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24_MASK 0x01000000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25_MASK 0x02000000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26_MASK 0x04000000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27_MASK 0x08000000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28_MASK 0x10000000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29_MASK 0x20000000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30_MASK 0x40000000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31_MASK 0x80000000L +//EGRESS_POISON_STATUS_HI +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0__SHIFT 0x0 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1__SHIFT 0x1 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2__SHIFT 0x2 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3__SHIFT 0x3 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4__SHIFT 0x4 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5__SHIFT 0x5 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6__SHIFT 0x6 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7__SHIFT 0x7 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8__SHIFT 0x8 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9__SHIFT 0x9 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10__SHIFT 0xa +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11__SHIFT 0xb +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12__SHIFT 0xc +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13__SHIFT 0xd +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14__SHIFT 0xe +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15__SHIFT 0xf +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16__SHIFT 0x10 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17__SHIFT 0x11 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18__SHIFT 0x12 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19__SHIFT 0x13 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20__SHIFT 0x14 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21__SHIFT 0x15 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22__SHIFT 0x16 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23__SHIFT 0x17 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24__SHIFT 0x18 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25__SHIFT 0x19 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26__SHIFT 0x1a +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27__SHIFT 0x1b +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28__SHIFT 0x1c +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29__SHIFT 0x1d +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30__SHIFT 0x1e +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31__SHIFT 0x1f +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0_MASK 0x00000001L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1_MASK 0x00000002L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2_MASK 0x00000004L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3_MASK 0x00000008L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4_MASK 0x00000010L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5_MASK 0x00000020L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6_MASK 0x00000040L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7_MASK 0x00000080L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8_MASK 0x00000100L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9_MASK 0x00000200L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10_MASK 0x00000400L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11_MASK 0x00000800L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12_MASK 0x00001000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13_MASK 0x00002000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14_MASK 0x00004000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15_MASK 0x00008000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16_MASK 0x00010000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17_MASK 0x00020000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18_MASK 0x00040000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19_MASK 0x00080000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20_MASK 0x00100000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21_MASK 0x00200000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22_MASK 0x00400000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23_MASK 0x00800000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24_MASK 0x01000000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25_MASK 0x02000000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26_MASK 0x04000000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27_MASK 0x08000000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28_MASK 0x10000000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29_MASK 0x20000000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30_MASK 0x40000000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31_MASK 0x80000000L +//EGRESS_POISON_MASK_LO +#define EGRESS_POISON_MASK_LO__EgressPoisonMaskLo__SHIFT 0x0 +#define EGRESS_POISON_MASK_LO__EgressPoisonMaskLo_MASK 0xFFFFFFFFL +//EGRESS_POISON_MASK_HI +#define EGRESS_POISON_MASK_HI__EgressPoisonMaskHi__SHIFT 0x0 +#define EGRESS_POISON_MASK_HI__EgressPoisonMaskHi_MASK 0xFFFFFFFFL +//EGRESS_POISON_SEVERITY_DOWN +#define EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown__SHIFT 0x0 +#define EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown_MASK 0xFFFFFFFFL +//EGRESS_POISON_SEVERITY_UPPER +#define EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper__SHIFT 0x0 +#define EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper_MASK 0xFFFFFFFFL +//APML_STATUS +#define APML_STATUS__APML_Corr__SHIFT 0x0 +#define APML_STATUS__APML_NonFatal__SHIFT 0x1 +#define APML_STATUS__APML_Fatal__SHIFT 0x2 +#define APML_STATUS__APML_Serr__SHIFT 0x3 +#define APML_STATUS__APML_IntPoisonErr__SHIFT 0x4 +#define APML_STATUS__APML_EgressPoisonErrLo__SHIFT 0x5 +#define APML_STATUS__APML_EgressPoisonErrHi__SHIFT 0x6 +#define APML_STATUS__APML_Corr_MASK 0x00000001L +#define APML_STATUS__APML_NonFatal_MASK 0x00000002L +#define APML_STATUS__APML_Fatal_MASK 0x00000004L +#define APML_STATUS__APML_Serr_MASK 0x00000008L +#define APML_STATUS__APML_IntPoisonErr_MASK 0x00000010L +#define APML_STATUS__APML_EgressPoisonErrLo_MASK 0x00000020L +#define APML_STATUS__APML_EgressPoisonErrHi_MASK 0x00000040L +//APML_CONTROL +#define APML_CONTROL__APML_NMI_En__SHIFT 0x0 +#define APML_CONTROL__APML_SyncFlood_En__SHIFT 0x1 +#define APML_CONTROL__APML_OutputDis__SHIFT 0x8 +#define APML_CONTROL__APML_NMI_En_MASK 0x00000001L +#define APML_CONTROL__APML_SyncFlood_En_MASK 0x00000002L +#define APML_CONTROL__APML_OutputDis_MASK 0x00000100L +//APML_TRIGGER +#define APML_TRIGGER__APML_NMI_TRIGGER__SHIFT 0x0 +#define APML_TRIGGER__APML_NMI_TRIGGER_MASK 0x00000001L + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg0_devind_cfgdecp +//NB_PCIE0DEVINDCFG0_STEERING_CNTL +#define NB_PCIE0DEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG0_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG0_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg1_devind_cfgdecp +//NB_PCIE0DEVINDCFG1_STEERING_CNTL +#define NB_PCIE0DEVINDCFG1_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG1_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG1_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG1_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg2_devind_cfgdecp +//NB_PCIE0DEVINDCFG2_STEERING_CNTL +#define NB_PCIE0DEVINDCFG2_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG2_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG2_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG2_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg3_devind_cfgdecp +//NB_PCIE0DEVINDCFG3_STEERING_CNTL +#define NB_PCIE0DEVINDCFG3_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG3_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG3_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG3_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg4_devind_cfgdecp +//NB_PCIE0DEVINDCFG4_STEERING_CNTL +#define NB_PCIE0DEVINDCFG4_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG4_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG4_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG4_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg5_devind_cfgdecp +//NB_PCIE0DEVINDCFG5_STEERING_CNTL +#define NB_PCIE0DEVINDCFG5_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG5_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG5_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG5_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg6_devind_cfgdecp +//NB_PCIE0DEVINDCFG6_STEERING_CNTL +#define NB_PCIE0DEVINDCFG6_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG6_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG6_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG6_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L + + +// addressBlock: aid_nbio_iohub_nb_NBIF1devindcfg0_devind_cfgdecp +//NB_NBIF1DEVINDCFG0_STEERING_CNTL +#define NB_NBIF1DEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_NBIF1DEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_NBIF1DEVINDCFG0_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_NBIF1DEVINDCFG0_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L + + +// addressBlock: aid_nbio_iohub_nb_intSBdevindcfg0_devind_cfgdecp +//NB_INTSBDEVINDCFG0_STEERING_CNTL +#define NB_INTSBDEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_INTSBDEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_INTSBDEVINDCFG0_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_INTSBDEVINDCFG0_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg0_pciercbdgind_cfgdec +//NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION +#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK 0x000000FFL +//NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX +#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA +#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg1_pciercbdgind_cfgdec +//NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION +#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK 0x000000FFL +//NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX +#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA +#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg2_pciercbdgind_cfgdec +//NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION +#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK 0x000000FFL +//NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX +#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA +#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg3_pciercbdgind_cfgdec +//NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION +#define NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK 0x000000FFL +//NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX +#define NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA +#define NB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg4_pciercbdgind_cfgdec +//NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION +#define NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK 0x000000FFL +//NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX +#define NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA +#define NB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg5_pciercbdgind_cfgdec +//NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION +#define NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK 0x000000FFL +//NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX +#define NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA +#define NB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg6_pciercbdgind_cfgdec +//NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION +#define NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK 0x000000FFL +//NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX +#define NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA +#define NB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_iohub_nb_NBIF1rcbdg_indcfg0_pciercbdgind_cfgdec +//NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION +#define NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT 0x0 +#define NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK 0x000000FFL +//NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX +#define NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA +#define NB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_iohub_iommu_l2a_l2acfg +//L2_PERF_CNTL_0 +#define L2_PERF_CNTL_0__L2PerfEvent0__SHIFT 0x0 +#define L2_PERF_CNTL_0__L2PerfEvent1__SHIFT 0x8 +#define L2_PERF_CNTL_0__L2PerfCountUpper0__SHIFT 0x10 +#define L2_PERF_CNTL_0__L2PerfCountUpper1__SHIFT 0x18 +#define L2_PERF_CNTL_0__L2PerfEvent0_MASK 0x000000FFL +#define L2_PERF_CNTL_0__L2PerfEvent1_MASK 0x0000FF00L +#define L2_PERF_CNTL_0__L2PerfCountUpper0_MASK 0x00FF0000L +#define L2_PERF_CNTL_0__L2PerfCountUpper1_MASK 0xFF000000L +//L2_PERF_COUNT_0 +#define L2_PERF_COUNT_0__L2PerfCount0__SHIFT 0x0 +#define L2_PERF_COUNT_0__L2PerfCount0_MASK 0xFFFFFFFFL +//L2_PERF_COUNT_1 +#define L2_PERF_COUNT_1__L2PerfCount1__SHIFT 0x0 +#define L2_PERF_COUNT_1__L2PerfCount1_MASK 0xFFFFFFFFL +//L2_PERF_CNTL_1 +#define L2_PERF_CNTL_1__L2PerfEvent2__SHIFT 0x0 +#define L2_PERF_CNTL_1__L2PerfEvent3__SHIFT 0x8 +#define L2_PERF_CNTL_1__L2PerfCountUpper2__SHIFT 0x10 +#define L2_PERF_CNTL_1__L2PerfCountUpper3__SHIFT 0x18 +#define L2_PERF_CNTL_1__L2PerfEvent2_MASK 0x000000FFL +#define L2_PERF_CNTL_1__L2PerfEvent3_MASK 0x0000FF00L +#define L2_PERF_CNTL_1__L2PerfCountUpper2_MASK 0x00FF0000L +#define L2_PERF_CNTL_1__L2PerfCountUpper3_MASK 0xFF000000L +//L2_PERF_COUNT_2 +#define L2_PERF_COUNT_2__L2PerfCount2__SHIFT 0x0 +#define L2_PERF_COUNT_2__L2PerfCount2_MASK 0xFFFFFFFFL +//L2_PERF_COUNT_3 +#define L2_PERF_COUNT_3__L2PerfCount3__SHIFT 0x0 +#define L2_PERF_COUNT_3__L2PerfCount3_MASK 0xFFFFFFFFL +//L2_STATUS_0 +#define L2_STATUS_0__L2STATUS0__SHIFT 0x0 +#define L2_STATUS_0__L2STATUS0_MASK 0xFFFFFFFFL +//L2_CONTROL_0 +#define L2_CONTROL_0__AllowL1CacheVZero__SHIFT 0x1 +#define L2_CONTROL_0__AllowL1CacheATSRsp__SHIFT 0x2 +#define L2_CONTROL_0__DTCHitVZeroOrIVZero__SHIFT 0x3 +#define L2_CONTROL_0__SIDEPTEOnUntransExcl__SHIFT 0xa +#define L2_CONTROL_0__SIDEPTEOnAddrTransExcl__SHIFT 0xb +#define L2_CONTROL_0__AllowL1CacheLargePagemode0__SHIFT 0x13 +#define L2_CONTROL_0__IFifoBurstLength__SHIFT 0x14 +#define L2_CONTROL_0__IFifoClientPriority__SHIFT 0x18 +#define L2_CONTROL_0__AllowL1CacheVZero_MASK 0x00000002L +#define L2_CONTROL_0__AllowL1CacheATSRsp_MASK 0x00000004L +#define L2_CONTROL_0__DTCHitVZeroOrIVZero_MASK 0x00000008L +#define L2_CONTROL_0__SIDEPTEOnUntransExcl_MASK 0x00000400L +#define L2_CONTROL_0__SIDEPTEOnAddrTransExcl_MASK 0x00000800L +#define L2_CONTROL_0__AllowL1CacheLargePagemode0_MASK 0x00080000L +#define L2_CONTROL_0__IFifoBurstLength_MASK 0x00F00000L +#define L2_CONTROL_0__IFifoClientPriority_MASK 0xFF000000L +//L2_CONTROL_1 +#define L2_CONTROL_1__SeqInvBurstLimitInv__SHIFT 0x0 +#define L2_CONTROL_1__SeqInvBurstLimitL2Req__SHIFT 0x8 +#define L2_CONTROL_1__SeqInvBurstLimitEn__SHIFT 0x10 +#define L2_CONTROL_1__DBUSDis__SHIFT 0x11 +#define L2_CONTROL_1__PerfThreshold__SHIFT 0x18 +#define L2_CONTROL_1__SeqInvBurstLimitInv_MASK 0x000000FFL +#define L2_CONTROL_1__SeqInvBurstLimitL2Req_MASK 0x0000FF00L +#define L2_CONTROL_1__SeqInvBurstLimitEn_MASK 0x00010000L +#define L2_CONTROL_1__DBUSDis_MASK 0x00020000L +#define L2_CONTROL_1__PerfThreshold_MASK 0xFF000000L +//L2_DTC_CONTROL +#define L2_DTC_CONTROL__DTCLRUUpdatePri__SHIFT 0x3 +#define L2_DTC_CONTROL__DTCParityEn__SHIFT 0x4 +#define L2_DTC_CONTROL__DTCInvalidationSel__SHIFT 0x8 +#define L2_DTC_CONTROL__DTCSoftInvalidate__SHIFT 0xa +#define L2_DTC_CONTROL__DTCBypass__SHIFT 0xd +#define L2_DTC_CONTROL__DTCParitySupport__SHIFT 0xf +#define L2_DTC_CONTROL__DTCWays__SHIFT 0x10 +#define L2_DTC_CONTROL__DTCEntries__SHIFT 0x1c +#define L2_DTC_CONTROL__DTCLRUUpdatePri_MASK 0x00000008L +#define L2_DTC_CONTROL__DTCParityEn_MASK 0x00000010L +#define L2_DTC_CONTROL__DTCInvalidationSel_MASK 0x00000300L +#define L2_DTC_CONTROL__DTCSoftInvalidate_MASK 0x00000400L +#define L2_DTC_CONTROL__DTCBypass_MASK 0x00002000L +#define L2_DTC_CONTROL__DTCParitySupport_MASK 0x00008000L +#define L2_DTC_CONTROL__DTCWays_MASK 0x00FF0000L +#define L2_DTC_CONTROL__DTCEntries_MASK 0xF0000000L +//L2_DTC_HASH_CONTROL +#define L2_DTC_HASH_CONTROL__DTCAddressMask__SHIFT 0x10 +#define L2_DTC_HASH_CONTROL__DTCAddressMask_MASK 0xFFFF0000L +//L2_DTC_WAY_CONTROL +#define L2_DTC_WAY_CONTROL__DTCWayDisable__SHIFT 0x0 +#define L2_DTC_WAY_CONTROL__DTCWayAccessDisable__SHIFT 0x10 +#define L2_DTC_WAY_CONTROL__DTCWayDisable_MASK 0x0000FFFFL +#define L2_DTC_WAY_CONTROL__DTCWayAccessDisable_MASK 0xFFFF0000L +//L2_ITC_CONTROL +#define L2_ITC_CONTROL__ITCLRUUpdatePri__SHIFT 0x3 +#define L2_ITC_CONTROL__ITCParityEn__SHIFT 0x4 +#define L2_ITC_CONTROL__ITCInvalidationSel__SHIFT 0x8 +#define L2_ITC_CONTROL__ITCSoftInvalidate__SHIFT 0xa +#define L2_ITC_CONTROL__ITCBypass__SHIFT 0xd +#define L2_ITC_CONTROL__ITCParitySupport__SHIFT 0xf +#define L2_ITC_CONTROL__ITCWays__SHIFT 0x10 +#define L2_ITC_CONTROL__ITCEntries__SHIFT 0x1c +#define L2_ITC_CONTROL__ITCLRUUpdatePri_MASK 0x00000008L +#define L2_ITC_CONTROL__ITCParityEn_MASK 0x00000010L +#define L2_ITC_CONTROL__ITCInvalidationSel_MASK 0x00000300L +#define L2_ITC_CONTROL__ITCSoftInvalidate_MASK 0x00000400L +#define L2_ITC_CONTROL__ITCBypass_MASK 0x00002000L +#define L2_ITC_CONTROL__ITCParitySupport_MASK 0x00008000L +#define L2_ITC_CONTROL__ITCWays_MASK 0x00FF0000L +#define L2_ITC_CONTROL__ITCEntries_MASK 0xF0000000L +//L2_ITC_HASH_CONTROL +#define L2_ITC_HASH_CONTROL__ITCAddressMask__SHIFT 0x10 +#define L2_ITC_HASH_CONTROL__ITCAddressMask_MASK 0xFFFF0000L +//L2_ITC_WAY_CONTROL +#define L2_ITC_WAY_CONTROL__ITCWayDisable__SHIFT 0x0 +#define L2_ITC_WAY_CONTROL__ITCWayAccessDisable__SHIFT 0x10 +#define L2_ITC_WAY_CONTROL__ITCWayDisable_MASK 0x0000FFFFL +#define L2_ITC_WAY_CONTROL__ITCWayAccessDisable_MASK 0xFFFF0000L +//L2_PTC_A_CONTROL +#define L2_PTC_A_CONTROL__PTCAStoreFinalATSeperate__SHIFT 0x1 +#define L2_PTC_A_CONTROL__PTCAStorePartialATSeperate__SHIFT 0x2 +#define L2_PTC_A_CONTROL__PTCALRUUpdatePri__SHIFT 0x3 +#define L2_PTC_A_CONTROL__PTCAParityEn__SHIFT 0x4 +#define L2_PTC_A_CONTROL__PTCAInvalidationSel__SHIFT 0x8 +#define L2_PTC_A_CONTROL__PTCASoftInvalidate__SHIFT 0xa +#define L2_PTC_A_CONTROL__PTCA2MMode__SHIFT 0xb +#define L2_PTC_A_CONTROL__PCTA_Inv_Overlapping_Pages__SHIFT 0xc +#define L2_PTC_A_CONTROL__PTCABypass__SHIFT 0xd +#define L2_PTC_A_CONTROL__PTCAFastInvalidateGuest__SHIFT 0xe +#define L2_PTC_A_CONTROL__PTCAParitySupport__SHIFT 0xf +#define L2_PTC_A_CONTROL__PTCAWays__SHIFT 0x10 +#define L2_PTC_A_CONTROL__PTCAEntries__SHIFT 0x1c +#define L2_PTC_A_CONTROL__PTCAStoreFinalATSeperate_MASK 0x00000002L +#define L2_PTC_A_CONTROL__PTCAStorePartialATSeperate_MASK 0x00000004L +#define L2_PTC_A_CONTROL__PTCALRUUpdatePri_MASK 0x00000008L +#define L2_PTC_A_CONTROL__PTCAParityEn_MASK 0x00000010L +#define L2_PTC_A_CONTROL__PTCAInvalidationSel_MASK 0x00000300L +#define L2_PTC_A_CONTROL__PTCASoftInvalidate_MASK 0x00000400L +#define L2_PTC_A_CONTROL__PTCA2MMode_MASK 0x00000800L +#define L2_PTC_A_CONTROL__PCTA_Inv_Overlapping_Pages_MASK 0x00001000L +#define L2_PTC_A_CONTROL__PTCABypass_MASK 0x00002000L +#define L2_PTC_A_CONTROL__PTCAFastInvalidateGuest_MASK 0x00004000L +#define L2_PTC_A_CONTROL__PTCAParitySupport_MASK 0x00008000L +#define L2_PTC_A_CONTROL__PTCAWays_MASK 0x00FF0000L +#define L2_PTC_A_CONTROL__PTCAEntries_MASK 0xF0000000L +//L2_PTC_A_HASH_CONTROL +#define L2_PTC_A_HASH_CONTROL__PTCAAddressMask__SHIFT 0x10 +#define L2_PTC_A_HASH_CONTROL__PTCAAddressMask_MASK 0xFFFF0000L +//L2_PTC_A_WAY_CONTROL +#define L2_PTC_A_WAY_CONTROL__PTCAWayDisable__SHIFT 0x0 +#define L2_PTC_A_WAY_CONTROL__PTCAWayAccessDisable__SHIFT 0x10 +#define L2_PTC_A_WAY_CONTROL__PTCAWayDisable_MASK 0x0000FFFFL +#define L2_PTC_A_WAY_CONTROL__PTCAWayAccessDisable_MASK 0xFFFF0000L +//L2A_UPDATE_FILTER_CNTL +#define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_Bypass__SHIFT 0x0 +#define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_RdLatency__SHIFT 0x1 +#define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_Bypass_MASK 0x00000001L +#define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_RdLatency_MASK 0x0000001EL +//L2_ERR_RULE_CONTROL_3 +#define L2_ERR_RULE_CONTROL_3__ERRRuleLock1__SHIFT 0x0 +#define L2_ERR_RULE_CONTROL_3__ERRRuleDisable3__SHIFT 0x4 +#define L2_ERR_RULE_CONTROL_3__ERRRuleLock1_MASK 0x00000001L +#define L2_ERR_RULE_CONTROL_3__ERRRuleDisable3_MASK 0xFFFFFFF0L +//L2_ERR_RULE_CONTROL_4 +#define L2_ERR_RULE_CONTROL_4__ERRRuleDisable4__SHIFT 0x0 +#define L2_ERR_RULE_CONTROL_4__ERRRuleDisable4_MASK 0xFFFFFFFFL +//L2_ERR_RULE_CONTROL_5 +#define L2_ERR_RULE_CONTROL_5__ERRRuleDisable5__SHIFT 0x0 +#define L2_ERR_RULE_CONTROL_5__ERRRuleDisable5_MASK 0xFFFFFFFFL +//L2_L2A_CK_GATE_CONTROL +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ARegsDisable__SHIFT 0x0 +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ADynamicDisable__SHIFT 0x1 +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ACacheDisable__SHIFT 0x2 +#define L2_L2A_CK_GATE_CONTROL__CKGateL2APerfDisable__SHIFT 0x3 +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ALength__SHIFT 0x10 +#define L2_L2A_CK_GATE_CONTROL__CKGateL2AStop__SHIFT 0x12 +#define L2_L2A_CK_GATE_CONTROL__CKGateL2APortClkDis__SHIFT 0x14 +#define L2_L2A_CK_GATE_CONTROL__Reserved__SHIFT 0x15 +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ARegsDisable_MASK 0x00000001L +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ADynamicDisable_MASK 0x00000002L +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ACacheDisable_MASK 0x00000004L +#define L2_L2A_CK_GATE_CONTROL__CKGateL2APerfDisable_MASK 0x00000008L +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ALength_MASK 0x00030000L +#define L2_L2A_CK_GATE_CONTROL__CKGateL2AStop_MASK 0x000C0000L +#define L2_L2A_CK_GATE_CONTROL__CKGateL2APortClkDis_MASK 0x00100000L +#define L2_L2A_CK_GATE_CONTROL__Reserved_MASK 0xFFE00000L +//L2_L2A_PGSIZE_CONTROL +#define L2_L2A_PGSIZE_CONTROL__L2AREG_GST_PGSIZE__SHIFT 0x0 +#define L2_L2A_PGSIZE_CONTROL__L2AREG_HOST_PGSIZE__SHIFT 0x8 +#define L2_L2A_PGSIZE_CONTROL__L2AREG_PTCSCAN_MODE__SHIFT 0x11 +#define L2_L2A_PGSIZE_CONTROL__L2AREG_GST_PGSIZE_MASK 0x0000007FL +#define L2_L2A_PGSIZE_CONTROL__L2AREG_HOST_PGSIZE_MASK 0x00007F00L +#define L2_L2A_PGSIZE_CONTROL__L2AREG_PTCSCAN_MODE_MASK 0x000E0000L +//L2_PWRGATE_CNTRL_REG_0 +#define L2_PWRGATE_CNTRL_REG_0__IP_PG_thres__SHIFT 0x0 +#define L2_PWRGATE_CNTRL_REG_0__IP_PG_thres_MASK 0xFFFFFFFFL +//L2_PWRGATE_CNTRL_REG_3 +#define L2_PWRGATE_CNTRL_REG_3__IP_PG_en__SHIFT 0x0 +#define L2_PWRGATE_CNTRL_REG_3__IP_PG_busy__SHIFT 0x1 +#define L2_PWRGATE_CNTRL_REG_3__L2_PG_STATUS__SHIFT 0x2 +#define L2_PWRGATE_CNTRL_REG_3__CFG_FW_PG_EXIT_EN__SHIFT 0x3 +#define L2_PWRGATE_CNTRL_REG_3__IP_PG_en_MASK 0x00000001L +#define L2_PWRGATE_CNTRL_REG_3__IP_PG_busy_MASK 0x00000002L +#define L2_PWRGATE_CNTRL_REG_3__L2_PG_STATUS_MASK 0x00000004L +#define L2_PWRGATE_CNTRL_REG_3__CFG_FW_PG_EXIT_EN_MASK 0x00000018L +//L2_ECO_CNTRL_0 +#define L2_ECO_CNTRL_0__L2_ECO_0__SHIFT 0x0 +#define L2_ECO_CNTRL_0__L2_ECO_0_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_iohub_iommu_l2indx_l2indxcfg +//L2_STATUS_1 +#define L2_STATUS_1__L2STATUS1__SHIFT 0x0 +#define L2_STATUS_1__L2STATUS1_MASK 0xFFFFFFFFL +//L2_SB_LOCATION +#define L2_SB_LOCATION__SBlocated_Port__SHIFT 0x0 +#define L2_SB_LOCATION__SBlocated_Core__SHIFT 0x10 +#define L2_SB_LOCATION__SBlocated_Port_MASK 0x0000FFFFL +#define L2_SB_LOCATION__SBlocated_Core_MASK 0xFFFF0000L +//L2_CONTROL_5 +#define L2_CONTROL_5__QueueArbFBPri__SHIFT 0x0 +#define L2_CONTROL_5__FC1Dis__SHIFT 0x2 +#define L2_CONTROL_5__DTCUpdateVOneIVZero__SHIFT 0x3 +#define L2_CONTROL_5__DTCUpdateVZeroIVOne__SHIFT 0x4 +#define L2_CONTROL_5__FC3Dis__SHIFT 0x6 +#define L2_CONTROL_5__ForceTWonVCQoS__SHIFT 0xb +#define L2_CONTROL_5__GST_partial_ptc_cntrl__SHIFT 0xc +#define L2_CONTROL_5__STORE_PDPE_QOS_PTC__SHIFT 0x14 +#define L2_CONTROL_5__DTCUpdatePri__SHIFT 0x19 +#define L2_CONTROL_5__L2B_L2A_v1_trans_credits__SHIFT 0x1a +#define L2_CONTROL_5__QueueArbFBPri_MASK 0x00000001L +#define L2_CONTROL_5__FC1Dis_MASK 0x00000004L +#define L2_CONTROL_5__DTCUpdateVOneIVZero_MASK 0x00000008L +#define L2_CONTROL_5__DTCUpdateVZeroIVOne_MASK 0x00000010L +#define L2_CONTROL_5__FC3Dis_MASK 0x00000040L +#define L2_CONTROL_5__ForceTWonVCQoS_MASK 0x00000800L +#define L2_CONTROL_5__GST_partial_ptc_cntrl_MASK 0x0007F000L +#define L2_CONTROL_5__STORE_PDPE_QOS_PTC_MASK 0x00100000L +#define L2_CONTROL_5__DTCUpdatePri_MASK 0x02000000L +#define L2_CONTROL_5__L2B_L2A_v1_trans_credits_MASK 0xFC000000L +//L2_CONTROL_6 +#define L2_CONTROL_6__SeqInvBurstLimitInv__SHIFT 0x0 +#define L2_CONTROL_6__SeqInvBurstLimitPDCReq__SHIFT 0x8 +#define L2_CONTROL_6__SeqInvBurstLimitEn__SHIFT 0x10 +#define L2_CONTROL_6__Perf2Threshold__SHIFT 0x18 +#define L2_CONTROL_6__SeqInvBurstLimitInv_MASK 0x000000FFL +#define L2_CONTROL_6__SeqInvBurstLimitPDCReq_MASK 0x0000FF00L +#define L2_CONTROL_6__SeqInvBurstLimitEn_MASK 0x00010000L +#define L2_CONTROL_6__Perf2Threshold_MASK 0xFF000000L +//L2_PDC_CONTROL +#define L2_PDC_CONTROL__PDCLRUUpdatePri__SHIFT 0x3 +#define L2_PDC_CONTROL__PDCParityEn__SHIFT 0x4 +#define L2_PDC_CONTROL__PDCInvalidationSel__SHIFT 0x8 +#define L2_PDC_CONTROL__PDCSoftInvalidate__SHIFT 0xa +#define L2_PDC_CONTROL__PDC_Inv_Overlapping_Pages__SHIFT 0xb +#define L2_PDC_CONTROL__PDCSearchDirection__SHIFT 0xc +#define L2_PDC_CONTROL__PDCBypass__SHIFT 0xd +#define L2_PDC_CONTROL__PDCModeLookupFix__SHIFT 0xe +#define L2_PDC_CONTROL__PDCParitySupport__SHIFT 0xf +#define L2_PDC_CONTROL__PDCWays__SHIFT 0x10 +#define L2_PDC_CONTROL__PDCEntries__SHIFT 0x1c +#define L2_PDC_CONTROL__PDCLRUUpdatePri_MASK 0x00000008L +#define L2_PDC_CONTROL__PDCParityEn_MASK 0x00000010L +#define L2_PDC_CONTROL__PDCInvalidationSel_MASK 0x00000300L +#define L2_PDC_CONTROL__PDCSoftInvalidate_MASK 0x00000400L +#define L2_PDC_CONTROL__PDC_Inv_Overlapping_Pages_MASK 0x00000800L +#define L2_PDC_CONTROL__PDCSearchDirection_MASK 0x00001000L +#define L2_PDC_CONTROL__PDCBypass_MASK 0x00002000L +#define L2_PDC_CONTROL__PDCModeLookupFix_MASK 0x00004000L +#define L2_PDC_CONTROL__PDCParitySupport_MASK 0x00008000L +#define L2_PDC_CONTROL__PDCWays_MASK 0x00FF0000L +#define L2_PDC_CONTROL__PDCEntries_MASK 0xF0000000L +//L2_PDC_HASH_CONTROL +#define L2_PDC_HASH_CONTROL__PDCAddressMask__SHIFT 0x10 +#define L2_PDC_HASH_CONTROL__PDCAddressMask_MASK 0xFFFF0000L +//L2_PDC_WAY_CONTROL +#define L2_PDC_WAY_CONTROL__PDCWayDisable__SHIFT 0x0 +#define L2_PDC_WAY_CONTROL__PDCWayAccessDisable__SHIFT 0x10 +#define L2_PDC_WAY_CONTROL__PDCWayDisable_MASK 0x0000FFFFL +#define L2_PDC_WAY_CONTROL__PDCWayAccessDisable_MASK 0xFFFF0000L +//L2B_UPDATE_FILTER_CNTL +#define L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_Bypass__SHIFT 0x0 +#define L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_RdLatency__SHIFT 0x1 +#define L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_Bypass_MASK 0x00000001L +#define L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_RdLatency_MASK 0x0000001EL +//L2_TW_CONTROL +#define L2_TW_CONTROL__RESERVED__SHIFT 0x0 +#define L2_TW_CONTROL__TWForceCoherent__SHIFT 0x6 +#define L2_TW_CONTROL__TWPrefetchEn__SHIFT 0x8 +#define L2_TW_CONTROL__TWPrefetchOnly4KDis__SHIFT 0x9 +#define L2_TW_CONTROL__TWPTEOnUntransExcl__SHIFT 0xa +#define L2_TW_CONTROL__TWPTEOnAddrTransExcl__SHIFT 0xb +#define L2_TW_CONTROL__TWPrefetchRange__SHIFT 0xc +#define L2_TW_CONTROL__TWFilter_Dis__SHIFT 0x10 +#define L2_TW_CONTROL__TWFilter_64B_Dis__SHIFT 0x11 +#define L2_TW_CONTROL__TWContWalkOnPErrDis__SHIFT 0x12 +#define L2_TW_CONTROL__TWSetAccessBit_Dis__SHIFT 0x13 +#define L2_TW_CONTROL__TWClearAPBit_Dis__SHIFT 0x14 +#define L2_TW_CONTROL__TWCacheNestedPTE__SHIFT 0x19 +#define L2_TW_CONTROL__RESERVED_MASK 0x0000003FL +#define L2_TW_CONTROL__TWForceCoherent_MASK 0x00000040L +#define L2_TW_CONTROL__TWPrefetchEn_MASK 0x00000100L +#define L2_TW_CONTROL__TWPrefetchOnly4KDis_MASK 0x00000200L +#define L2_TW_CONTROL__TWPTEOnUntransExcl_MASK 0x00000400L +#define L2_TW_CONTROL__TWPTEOnAddrTransExcl_MASK 0x00000800L +#define L2_TW_CONTROL__TWPrefetchRange_MASK 0x00007000L +#define L2_TW_CONTROL__TWFilter_Dis_MASK 0x00010000L +#define L2_TW_CONTROL__TWFilter_64B_Dis_MASK 0x00020000L +#define L2_TW_CONTROL__TWContWalkOnPErrDis_MASK 0x00040000L +#define L2_TW_CONTROL__TWSetAccessBit_Dis_MASK 0x00080000L +#define L2_TW_CONTROL__TWClearAPBit_Dis_MASK 0x00100000L +#define L2_TW_CONTROL__TWCacheNestedPTE_MASK 0x02000000L +//L2_CP_CONTROL +#define L2_CP_CONTROL__CPPrefetchDis__SHIFT 0x0 +#define L2_CP_CONTROL__CPFlushOnWait__SHIFT 0x1 +#define L2_CP_CONTROL__CPFlushOnInv__SHIFT 0x2 +#define L2_CP_CONTROL__CPStallCmdErrForIOTLBCmpl__SHIFT 0x3 +#define L2_CP_CONTROL__CPForceReqPassPW__SHIFT 0x4 +#define L2_CP_CONTROL__CPForceOneOutstandingCommand__SHIFT 0x5 +#define L2_CP_CONTROL__CPRdDelay__SHIFT 0x10 +#define L2_CP_CONTROL__CPPrefetchDis_MASK 0x00000001L +#define L2_CP_CONTROL__CPFlushOnWait_MASK 0x00000002L +#define L2_CP_CONTROL__CPFlushOnInv_MASK 0x00000004L +#define L2_CP_CONTROL__CPStallCmdErrForIOTLBCmpl_MASK 0x00000008L +#define L2_CP_CONTROL__CPForceReqPassPW_MASK 0x00000010L +#define L2_CP_CONTROL__CPForceOneOutstandingCommand_MASK 0x00000020L +#define L2_CP_CONTROL__CPRdDelay_MASK 0xFFFF0000L +//L2_CP_CONTROL_1 +#define L2_CP_CONTROL_1__CPL1Off__SHIFT 0x0 +#define L2_CP_CONTROL_1__Reserved__SHIFT 0x10 +#define L2_CP_CONTROL_1__CPL1Off_MASK 0x0000FFFFL +#define L2_CP_CONTROL_1__Reserved_MASK 0xFFFF0000L +//L2_TW_CONTROL_1 +#define L2_TW_CONTROL_1__TWTraceEn__SHIFT 0x0 +#define L2_TW_CONTROL_1__TWTraceNoWrap__SHIFT 0x1 +#define L2_TW_CONTROL_1__TWTraceForceDisable__SHIFT 0x2 +#define L2_TW_CONTROL_1__TWTraceMask__SHIFT 0xf +#define L2_TW_CONTROL_1__TWTraceEn_MASK 0x00000001L +#define L2_TW_CONTROL_1__TWTraceNoWrap_MASK 0x00000002L +#define L2_TW_CONTROL_1__TWTraceForceDisable_MASK 0x00000004L +#define L2_TW_CONTROL_1__TWTraceMask_MASK 0xFFFF8000L +//L2_TW_CONTROL_2 +#define L2_TW_CONTROL_2__TWTraceAddrLo__SHIFT 0xc +#define L2_TW_CONTROL_2__TWTraceAddrLo_MASK 0xFFFFF000L +//L2_TW_CONTROL_3 +#define L2_TW_CONTROL_3__TWTraceAddrHi__SHIFT 0x0 +#define L2_TW_CONTROL_3__TWTraceAddrHi_MASK 0xFFFFFFFFL +//L2_CREDIT_CONTROL_0 +#define L2_CREDIT_CONTROL_0__FC1Credits__SHIFT 0x0 +#define L2_CREDIT_CONTROL_0__FC1Override__SHIFT 0x7 +#define L2_CREDIT_CONTROL_0__FC3Credits__SHIFT 0xf +#define L2_CREDIT_CONTROL_0__FC3Override__SHIFT 0x15 +#define L2_CREDIT_CONTROL_0__FC1Credits_MASK 0x0000007FL +#define L2_CREDIT_CONTROL_0__FC1Override_MASK 0x00000080L +#define L2_CREDIT_CONTROL_0__FC3Credits_MASK 0x001F8000L +#define L2_CREDIT_CONTROL_0__FC3Override_MASK 0x00200000L +//L2_CREDIT_CONTROL_1 +#define L2_CREDIT_CONTROL_1__CP_PREFETCH_credits__SHIFT 0x10 +#define L2_CREDIT_CONTROL_1__PPR_MCIF_credits__SHIFT 0x14 +#define L2_CREDIT_CONTROL_1__CP_PREFETCH_credits_MASK 0x000F0000L +#define L2_CREDIT_CONTROL_1__PPR_MCIF_credits_MASK 0x00F00000L +//L2_ERR_RULE_CONTROL_0 +#define L2_ERR_RULE_CONTROL_0__ERRRuleLock0__SHIFT 0x0 +#define L2_ERR_RULE_CONTROL_0__ERRRuleDisable0__SHIFT 0x1 +#define L2_ERR_RULE_CONTROL_0__ERRRuleLock0_MASK 0x00000001L +#define L2_ERR_RULE_CONTROL_0__ERRRuleDisable0_MASK 0xFFFFFFFEL +//L2_ERR_RULE_CONTROL_1 +#define L2_ERR_RULE_CONTROL_1__ERRRuleDisable1__SHIFT 0x0 +#define L2_ERR_RULE_CONTROL_1__ERRRuleDisable1_MASK 0xFFFFFFFFL +//L2_ERR_RULE_CONTROL_2 +#define L2_ERR_RULE_CONTROL_2__ERRRuleDisable2__SHIFT 0x0 +#define L2_ERR_RULE_CONTROL_2__ERRRuleDisable2_MASK 0xFFFFFFFFL +//L2_L2B_CK_GATE_CONTROL +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BRegsDisable__SHIFT 0x0 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BDynamicDisable__SHIFT 0x1 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BMiscDisable__SHIFT 0x2 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BCacheDisable__SHIFT 0x3 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BAPCDisable__SHIFT 0x4 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BPerfDisable__SHIFT 0x5 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BPortClkDis__SHIFT 0x6 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BLength__SHIFT 0x10 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BStop__SHIFT 0x12 +#define L2_L2B_CK_GATE_CONTROL__Reserved__SHIFT 0x14 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BRegsDisable_MASK 0x00000001L +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BDynamicDisable_MASK 0x00000002L +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BMiscDisable_MASK 0x00000004L +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BCacheDisable_MASK 0x00000008L +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BAPCDisable_MASK 0x00000010L +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BPerfDisable_MASK 0x00000020L +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BPortClkDis_MASK 0x00000040L +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BLength_MASK 0x00030000L +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BStop_MASK 0x000C0000L +#define L2_L2B_CK_GATE_CONTROL__Reserved_MASK 0xFFF00000L +//PPR_CONTROL +#define PPR_CONTROL__PPR_IntTimeDelay__SHIFT 0x0 +#define PPR_CONTROL__PPR_IntReqDelay__SHIFT 0x8 +#define PPR_CONTROL__PPR_IntCoallesce_En__SHIFT 0x10 +#define PPR_CONTROL__PPR_IntTimeDelay_MASK 0x000000FFL +#define PPR_CONTROL__PPR_IntReqDelay_MASK 0x0000FF00L +#define PPR_CONTROL__PPR_IntCoallesce_En_MASK 0x00010000L +//L2_L2B_PGSIZE_CONTROL +#define L2_L2B_PGSIZE_CONTROL__L2BREG_GST_PGSIZE__SHIFT 0x0 +#define L2_L2B_PGSIZE_CONTROL__L2BREG_HOST_PGSIZE__SHIFT 0x8 +#define L2_L2B_PGSIZE_CONTROL__L2BREG_GST_PGSIZE_MASK 0x0000007FL +#define L2_L2B_PGSIZE_CONTROL__L2BREG_HOST_PGSIZE_MASK 0x00007F00L +//L2_PERF_CNTL_2 +#define L2_PERF_CNTL_2__L2PerfEvent4__SHIFT 0x0 +#define L2_PERF_CNTL_2__L2PerfEvent5__SHIFT 0x8 +#define L2_PERF_CNTL_2__L2PerfCountUpper4__SHIFT 0x10 +#define L2_PERF_CNTL_2__L2PerfCountUpper5__SHIFT 0x18 +#define L2_PERF_CNTL_2__L2PerfEvent4_MASK 0x000000FFL +#define L2_PERF_CNTL_2__L2PerfEvent5_MASK 0x0000FF00L +#define L2_PERF_CNTL_2__L2PerfCountUpper4_MASK 0x00FF0000L +#define L2_PERF_CNTL_2__L2PerfCountUpper5_MASK 0xFF000000L +//L2_PERF_COUNT_4 +#define L2_PERF_COUNT_4__L2PerfCount4__SHIFT 0x0 +#define L2_PERF_COUNT_4__L2PerfCount4_MASK 0xFFFFFFFFL +//L2_PERF_COUNT_5 +#define L2_PERF_COUNT_5__L2PerfCount5__SHIFT 0x0 +#define L2_PERF_COUNT_5__L2PerfCount5_MASK 0xFFFFFFFFL +//L2_PERF_CNTL_3 +#define L2_PERF_CNTL_3__L2PerfEvent6__SHIFT 0x0 +#define L2_PERF_CNTL_3__L2PerfEvent7__SHIFT 0x8 +#define L2_PERF_CNTL_3__L2PerfCountUpper6__SHIFT 0x10 +#define L2_PERF_CNTL_3__L2PerfCountUpper7__SHIFT 0x18 +#define L2_PERF_CNTL_3__L2PerfEvent6_MASK 0x000000FFL +#define L2_PERF_CNTL_3__L2PerfEvent7_MASK 0x0000FF00L +#define L2_PERF_CNTL_3__L2PerfCountUpper6_MASK 0x00FF0000L +#define L2_PERF_CNTL_3__L2PerfCountUpper7_MASK 0xFF000000L +//L2_PERF_COUNT_6 +#define L2_PERF_COUNT_6__L2PerfCount6__SHIFT 0x0 +#define L2_PERF_COUNT_6__L2PerfCount6_MASK 0xFFFFFFFFL +//L2_PERF_COUNT_7 +#define L2_PERF_COUNT_7__L2PerfCount7__SHIFT 0x0 +#define L2_PERF_COUNT_7__L2PerfCount7_MASK 0xFFFFFFFFL +//L2B_SDP_PARITY_ERROR_EN +#define L2B_SDP_PARITY_ERROR_EN__DVM_PARITY_ERROR_EN__SHIFT 0x0 +#define L2B_SDP_PARITY_ERROR_EN__CP_PARITY_ERROR_EN__SHIFT 0x1 +#define L2B_SDP_PARITY_ERROR_EN__TWW_PARITY_ERROR_EN__SHIFT 0x2 +#define L2B_SDP_PARITY_ERROR_EN__VFMMIO_PARITY_ERROR_EN__SHIFT 0x3 +#define L2B_SDP_PARITY_ERROR_EN__MSG_PARITY_ERROR_EN__SHIFT 0x4 +#define L2B_SDP_PARITY_ERROR_EN__DVM_PARITY_ERROR_EN_MASK 0x00000001L +#define L2B_SDP_PARITY_ERROR_EN__CP_PARITY_ERROR_EN_MASK 0x00000002L +#define L2B_SDP_PARITY_ERROR_EN__TWW_PARITY_ERROR_EN_MASK 0x00000004L +#define L2B_SDP_PARITY_ERROR_EN__VFMMIO_PARITY_ERROR_EN_MASK 0x00000008L +#define L2B_SDP_PARITY_ERROR_EN__MSG_PARITY_ERROR_EN_MASK 0x00000010L +//L2_ECO_CNTRL_1 +#define L2_ECO_CNTRL_1__L2_ECO_1__SHIFT 0x0 +#define L2_ECO_CNTRL_1__L2_ECO_1_MASK 0xFFFFFFFFL +//L2_CP_CONTROL_2 +#define L2_CP_CONTROL_2__OVERCONSTRAIN_CMD_WQ_ON_INV__SHIFT 0x0 +#define L2_CP_CONTROL_2__LEGACY_CWWB_PATH__SHIFT 0x1 +#define L2_CP_CONTROL_2__gstcp_always_refetch_v1__SHIFT 0x2 +#define L2_CP_CONTROL_2__inv_waitcmpl_mode__SHIFT 0x16 +#define L2_CP_CONTROL_2__inv_dvmsync_mode__SHIFT 0x18 +#define L2_CP_CONTROL_2__inv_pspflush_mode__SHIFT 0x1a +#define L2_CP_CONTROL_2__wqmask_propagation_latency__SHIFT 0x1c +#define L2_CP_CONTROL_2__OVERCONSTRAIN_CMD_WQ_ON_INV_MASK 0x00000001L +#define L2_CP_CONTROL_2__LEGACY_CWWB_PATH_MASK 0x00000002L +#define L2_CP_CONTROL_2__gstcp_always_refetch_v1_MASK 0x00000004L +#define L2_CP_CONTROL_2__inv_waitcmpl_mode_MASK 0x00C00000L +#define L2_CP_CONTROL_2__inv_dvmsync_mode_MASK 0x03000000L +#define L2_CP_CONTROL_2__inv_pspflush_mode_MASK 0x0C000000L +#define L2_CP_CONTROL_2__wqmask_propagation_latency_MASK 0xF0000000L +//L2_CP_CONTROL_3 +#define L2_CP_CONTROL_3__INV_CMD_PRIORITY__SHIFT 0x0 +#define L2_CP_CONTROL_3__WAIT_CMD_PRIORITY__SHIFT 0x4 +#define L2_CP_CONTROL_3__SYNC_CMD_PRIORITY__SHIFT 0x8 +#define L2_CP_CONTROL_3__PSP_CMD_PRIORITY__SHIFT 0xc +#define L2_CP_CONTROL_3__INV_CMD_PRIORITY_MASK 0x0000000FL +#define L2_CP_CONTROL_3__WAIT_CMD_PRIORITY_MASK 0x000000F0L +#define L2_CP_CONTROL_3__SYNC_CMD_PRIORITY_MASK 0x00000F00L +#define L2_CP_CONTROL_3__PSP_CMD_PRIORITY_MASK 0x0000F000L + + +// addressBlock: aid_nbio_iohub_nb_ioapiccfg_ioapic_cfgdec +//FEATURES_ENABLE +#define FEATURES_ENABLE__Ioapic_id_ext_en__SHIFT 0x2 +#define FEATURES_ENABLE__Ioapic_sb_feature_en__SHIFT 0x4 +#define FEATURES_ENABLE__Ioapic_secondary_en__SHIFT 0x5 +#define FEATURES_ENABLE__Ioapic_processor_mode__SHIFT 0x8 +#define FEATURES_ENABLE__INTx_LevelOnlyMode__SHIFT 0x9 +#define FEATURES_ENABLE__Ioapic_id_ext_en_MASK 0x00000004L +#define FEATURES_ENABLE__Ioapic_sb_feature_en_MASK 0x00000010L +#define FEATURES_ENABLE__Ioapic_secondary_en_MASK 0x00000020L +#define FEATURES_ENABLE__Ioapic_processor_mode_MASK 0x00000100L +#define FEATURES_ENABLE__INTx_LevelOnlyMode_MASK 0x00000200L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +//BIF_CFG_DEV0_RC_VENDOR_ID +#define BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_DEVICE_ID +#define BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_COMMAND +#define BIF_CFG_DEV0_RC_COMMAND__IOEN_DN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_RC_COMMAND__IOEN_DN_MASK 0x0001L +#define BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN_MASK 0x0002L +#define BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_RC_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_RC_STATUS +#define BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_RC_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_RC_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC_REVISION_ID +#define BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_RC_PROG_INTERFACE +#define BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_RC_SUB_CLASS +#define BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC_BASE_CLASS +#define BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC_CACHE_LINE +#define BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_RC_LATENCY +#define BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_RC_HEADER +#define BIF_CFG_DEV0_RC_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_RC_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_RC_BIST +#define BIF_CFG_DEV0_RC_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_RC_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_RC_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_RC_BASE_ADDR_1 +#define BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_BASE_ADDR_2 +#define BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_IO_BASE_LIMIT +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIF_CFG_DEV0_RC_SECONDARY_STATUS +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC_MEM_BASE_LIMIT +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PREF_BASE_LIMIT +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PREF_BASE_UPPER +#define BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER +#define BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC_CAP_PTR +#define BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_RC_ROM_BASE_ADDR +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_RC_INTERRUPT_LINE +#define BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_RC_INTERRUPT_PIN +#define BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//IRQ_BRIDGE_CNTL +#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8 +#define IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9 +#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa +#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb +#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +#define IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L +#define IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L +#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L +#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L +//BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL +#define BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIF_CFG_DEV0_RC_PMI_CAP_LIST +#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC_PMI_CAP +#define BIF_CFG_DEV0_RC_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_RC_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_PCIE_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC_PCIE_CAP +#define BIF_CFG_DEV0_RC_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_RC_DEVICE_CAP +#define BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_RC_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_RC_DEVICE_CNTL +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIF_CFG_DEV0_RC_DEVICE_STATUS +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_RC_LINK_CAP +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_LINK_CNTL +#define BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_RC_LINK_STATUS +#define BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_RC_SLOT_CAP +#define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIF_CFG_DEV0_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIF_CFG_DEV0_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIF_CFG_DEV0_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIF_CFG_DEV0_RC_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIF_CFG_DEV0_RC_SLOT_CNTL +#define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIF_CFG_DEV0_RC_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIF_CFG_DEV0_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_RC_SLOT_CNTL__INBAND_PD_DISABLE__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__INBAND_PD_DISABLE_MASK 0x4000L +//BIF_CFG_DEV0_RC_SLOT_STATUS +#define BIF_CFG_DEV0_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIF_CFG_DEV0_RC_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIF_CFG_DEV0_RC_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIF_CFG_DEV0_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIF_CFG_DEV0_RC_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIF_CFG_DEV0_RC_ROOT_CNTL +#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIF_CFG_DEV0_RC_ROOT_CAP +#define BIF_CFG_DEV0_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIF_CFG_DEV0_RC_ROOT_STATUS +#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIF_CFG_DEV0_RC_DEVICE_CAP2 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_RC_DEVICE_CNTL2 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_RC_DEVICE_STATUS2 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_LINK_CAP2 +#define BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_RC_LINK_CNTL2 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_RC_LINK_STATUS2 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_RC_SLOT_CAP2 +#define BIF_CFG_DEV0_RC_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK 0x00000001L +//BIF_CFG_DEV0_RC_SLOT_CNTL2 +#define BIF_CFG_DEV0_RC_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_SLOT_STATUS2 +#define BIF_CFG_DEV0_RC_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_MSI_CAP_LIST +#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC_MSI_MSG_CNTL +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_MSI_MSG_DATA +#define BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_SSID_CAP_LIST +#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC_SSID_CAP +#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS_MASK 0x00000180L +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID +#define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_ACS_CAP +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_RC_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_LINK_CAP_16GT +#define BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_LINK_CNTL_16GT +#define BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_LINK_STATUS_16GT +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_MARGINING_PORT_CAP +#define BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS +#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LINK_CAP_32GT +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//BIF_CFG_DEV0_RC_LINK_CNTL_32GT +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L +//BIF_CFG_DEV0_RC_LINK_STATUS_32GT +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_COMMAND +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF0_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_LATENCY +#define BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_HEADER +#define BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF0_BIST +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_COMMAND +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF1_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_LATENCY +#define BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_HEADER +#define BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF1_BIST +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_COMMAND +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF2_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_LATENCY +#define BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_HEADER +#define BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF2_BIST +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF2_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF2_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_COMMAND +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF3_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_LATENCY +#define BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_HEADER +#define BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF3_BIST +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF3_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF3_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_COMMAND +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF4_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_LATENCY +#define BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_HEADER +#define BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF4_BIST +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF4_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF4_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_COMMAND +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF5_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_LATENCY +#define BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_HEADER +#define BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF5_BIST +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF5_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF5_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_COMMAND +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF6_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_LATENCY +#define BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_HEADER +#define BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF6_BIST +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF6_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF6_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_COMMAND +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF7_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_LATENCY +#define BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_HEADER +#define BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF7_BIST +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF7_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF7_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF0_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF0_MM_DATA +#define BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF0_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF1_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF1_MM_DATA +#define BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF1_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF2_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF2_MM_DATA +#define BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF2_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF3_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF3_MM_DATA +#define BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF3_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF4_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF4_MM_DATA +#define BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF4_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF5_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF5_MM_DATA +#define BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF5_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF6_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF6_MM_DATA +#define BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF6_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF7_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF7_MM_DATA +#define BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF7_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +#endif diff --git a/extra/amdpci/headers/vega10_enum.h b/extra/amdpci/headers/vega10_enum.h new file mode 100644 index 0000000000..adf1b75466 --- /dev/null +++ b/extra/amdpci/headers/vega10_enum.h @@ -0,0 +1,22532 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#if !defined (_vega10_ENUM_HEADER) +#define _vega10_ENUM_HEADER + +#ifndef _DRIVER_BUILD +#ifndef GL_ZERO +#define GL__ZERO BLEND_ZERO +#define GL__ONE BLEND_ONE +#define GL__SRC_COLOR BLEND_SRC_COLOR +#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR +#define GL__DST_COLOR BLEND_DST_COLOR +#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR +#define GL__SRC_ALPHA BLEND_SRC_ALPHA +#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA +#define GL__DST_ALPHA BLEND_DST_ALPHA +#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA +#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE +#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR +#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR +#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA +#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA +#endif +#endif + +/******************************************************* + * GDS DATA_TYPE Enums + *******************************************************/ + +#ifndef ENUMS_GDS_PERFCOUNT_SELECT_H +#define ENUMS_GDS_PERFCOUNT_SELECT_H +typedef enum GDS_PERFCOUNT_SELECT { + GDS_PERF_SEL_DS_ADDR_CONFL = 0, + GDS_PERF_SEL_DS_BANK_CONFL = 1, + GDS_PERF_SEL_WBUF_FLUSH = 2, + GDS_PERF_SEL_WR_COMP = 3, + GDS_PERF_SEL_WBUF_WR = 4, + GDS_PERF_SEL_RBUF_HIT = 5, + GDS_PERF_SEL_RBUF_MISS = 6, + GDS_PERF_SEL_SE0_SH0_NORET = 7, + GDS_PERF_SEL_SE0_SH0_RET = 8, + GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9, + GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10, + GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11, + GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12, + GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13, + GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14, + GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15, + GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16, + GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17, + GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18, + GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19, + GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20, + GDS_PERF_SEL_SE0_SH1_NORET = 21, + GDS_PERF_SEL_SE0_SH1_RET = 22, + GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23, + GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24, + GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25, + GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26, + GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27, + GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28, + GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29, + GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30, + GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31, + GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32, + GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33, + GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34, + GDS_PERF_SEL_SE1_SH0_NORET = 35, + GDS_PERF_SEL_SE1_SH0_RET = 36, + GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37, + GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38, + GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39, + GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40, + GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41, + GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42, + GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43, + GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44, + GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45, + GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46, + GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47, + GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48, + GDS_PERF_SEL_SE1_SH1_NORET = 49, + GDS_PERF_SEL_SE1_SH1_RET = 50, + GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51, + GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52, + GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53, + GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54, + GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55, + GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56, + GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57, + GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58, + GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59, + GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60, + GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61, + GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62, + GDS_PERF_SEL_SE2_SH0_NORET = 63, + GDS_PERF_SEL_SE2_SH0_RET = 64, + GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65, + GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66, + GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67, + GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68, + GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69, + GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70, + GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71, + GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72, + GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73, + GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74, + GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75, + GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76, + GDS_PERF_SEL_SE2_SH1_NORET = 77, + GDS_PERF_SEL_SE2_SH1_RET = 78, + GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79, + GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80, + GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81, + GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82, + GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83, + GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84, + GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85, + GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86, + GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87, + GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88, + GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89, + GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90, + GDS_PERF_SEL_SE3_SH0_NORET = 91, + GDS_PERF_SEL_SE3_SH0_RET = 92, + GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93, + GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94, + GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95, + GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96, + GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97, + GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98, + GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99, + GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100, + GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101, + GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102, + GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103, + GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104, + GDS_PERF_SEL_SE3_SH1_NORET = 105, + GDS_PERF_SEL_SE3_SH1_RET = 106, + GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107, + GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108, + GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109, + GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110, + GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111, + GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112, + GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113, + GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114, + GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115, + GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116, + GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117, + GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118, + GDS_PERF_SEL_GWS_RELEASED = 119, + GDS_PERF_SEL_GWS_BYPASS = 120, +} GDS_PERFCOUNT_SELECT; +#endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/ + +/******************************************************* + * Chip Enums + *******************************************************/ + +/* + * MEM_PWR_FORCE_CTRL enum + */ + +typedef enum MEM_PWR_FORCE_CTRL { +NO_FORCE_REQUEST = 0x00000000, +FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, +FORCE_DEEP_SLEEP_REQUEST = 0x00000002, +FORCE_SHUT_DOWN_REQUEST = 0x00000003, +} MEM_PWR_FORCE_CTRL; + +/* + * MEM_PWR_FORCE_CTRL2 enum + */ + +typedef enum MEM_PWR_FORCE_CTRL2 { +NO_FORCE_REQ = 0x00000000, +FORCE_LIGHT_SLEEP_REQ = 0x00000001, +} MEM_PWR_FORCE_CTRL2; + +/* + * MEM_PWR_DIS_CTRL enum + */ + +typedef enum MEM_PWR_DIS_CTRL { +ENABLE_MEM_PWR_CTRL = 0x00000000, +DISABLE_MEM_PWR_CTRL = 0x00000001, +} MEM_PWR_DIS_CTRL; + +/* + * MEM_PWR_SEL_CTRL enum + */ + +typedef enum MEM_PWR_SEL_CTRL { +DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000, +DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001, +DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002, +} MEM_PWR_SEL_CTRL; + +/* + * MEM_PWR_SEL_CTRL2 enum + */ + +typedef enum MEM_PWR_SEL_CTRL2 { +DYNAMIC_DEEP_SLEEP_EN = 0x00000000, +DYNAMIC_LIGHT_SLEEP_EN = 0x00000001, +} MEM_PWR_SEL_CTRL2; + +/* + * RowSize enum + */ + +typedef enum RowSize { +ADDR_CONFIG_1KB_ROW = 0x00000000, +ADDR_CONFIG_2KB_ROW = 0x00000001, +ADDR_CONFIG_4KB_ROW = 0x00000002, +} RowSize; + +/* + * SurfaceEndian enum + */ + +typedef enum SurfaceEndian { +ENDIAN_NONE = 0x00000000, +ENDIAN_8IN16 = 0x00000001, +ENDIAN_8IN32 = 0x00000002, +ENDIAN_8IN64 = 0x00000003, +} SurfaceEndian; + +/* + * ArrayMode enum + */ + +typedef enum ArrayMode { +ARRAY_LINEAR_GENERAL = 0x00000000, +ARRAY_LINEAR_ALIGNED = 0x00000001, +ARRAY_1D_TILED_THIN1 = 0x00000002, +ARRAY_1D_TILED_THICK = 0x00000003, +ARRAY_2D_TILED_THIN1 = 0x00000004, +ARRAY_PRT_TILED_THIN1 = 0x00000005, +ARRAY_PRT_2D_TILED_THIN1 = 0x00000006, +ARRAY_2D_TILED_THICK = 0x00000007, +ARRAY_2D_TILED_XTHICK = 0x00000008, +ARRAY_PRT_TILED_THICK = 0x00000009, +ARRAY_PRT_2D_TILED_THICK = 0x0000000a, +ARRAY_PRT_3D_TILED_THIN1 = 0x0000000b, +ARRAY_3D_TILED_THIN1 = 0x0000000c, +ARRAY_3D_TILED_THICK = 0x0000000d, +ARRAY_3D_TILED_XTHICK = 0x0000000e, +ARRAY_PRT_3D_TILED_THICK = 0x0000000f, +} ArrayMode; + +/* + * NumPipes enum + */ + +typedef enum NumPipes { +ADDR_CONFIG_1_PIPE = 0x00000000, +ADDR_CONFIG_2_PIPE = 0x00000001, +ADDR_CONFIG_4_PIPE = 0x00000002, +ADDR_CONFIG_8_PIPE = 0x00000003, +ADDR_CONFIG_16_PIPE = 0x00000004, +ADDR_CONFIG_32_PIPE = 0x00000005, +} NumPipes; + +/* + * NumBanksConfig enum + */ + +typedef enum NumBanksConfig { +ADDR_CONFIG_1_BANK = 0x00000000, +ADDR_CONFIG_2_BANK = 0x00000001, +ADDR_CONFIG_4_BANK = 0x00000002, +ADDR_CONFIG_8_BANK = 0x00000003, +ADDR_CONFIG_16_BANK = 0x00000004, +} NumBanksConfig; + +/* + * PipeInterleaveSize enum + */ + +typedef enum PipeInterleaveSize { +ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000, +ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001, +ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 0x00000002, +ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 0x00000003, +} PipeInterleaveSize; + +/* + * BankInterleaveSize enum + */ + +typedef enum BankInterleaveSize { +ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000, +ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001, +ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002, +ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003, +} BankInterleaveSize; + +/* + * NumShaderEngines enum + */ + +typedef enum NumShaderEngines { +ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000, +ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001, +ADDR_CONFIG_4_SHADER_ENGINE = 0x00000002, +ADDR_CONFIG_8_SHADER_ENGINE = 0x00000003, +} NumShaderEngines; + +/* + * NumRbPerShaderEngine enum + */ + +typedef enum NumRbPerShaderEngine { +ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0x00000000, +ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 0x00000001, +ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 0x00000002, +} NumRbPerShaderEngine; + +/* + * NumGPUs enum + */ + +typedef enum NumGPUs { +ADDR_CONFIG_1_GPU = 0x00000000, +ADDR_CONFIG_2_GPU = 0x00000001, +ADDR_CONFIG_4_GPU = 0x00000002, +ADDR_CONFIG_8_GPU = 0x00000003, +} NumGPUs; + +/* + * NumMaxCompressedFragments enum + */ + +typedef enum NumMaxCompressedFragments { +ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0x00000000, +ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 0x00000001, +ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 0x00000002, +ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 0x00000003, +} NumMaxCompressedFragments; + +/* + * ShaderEngineTileSize enum + */ + +typedef enum ShaderEngineTileSize { +ADDR_CONFIG_SE_TILE_16 = 0x00000000, +ADDR_CONFIG_SE_TILE_32 = 0x00000001, +} ShaderEngineTileSize; + +/* + * MultiGPUTileSize enum + */ + +typedef enum MultiGPUTileSize { +ADDR_CONFIG_GPU_TILE_16 = 0x00000000, +ADDR_CONFIG_GPU_TILE_32 = 0x00000001, +ADDR_CONFIG_GPU_TILE_64 = 0x00000002, +ADDR_CONFIG_GPU_TILE_128 = 0x00000003, +} MultiGPUTileSize; + +/* + * NumLowerPipes enum + */ + +typedef enum NumLowerPipes { +ADDR_CONFIG_1_LOWER_PIPES = 0x00000000, +ADDR_CONFIG_2_LOWER_PIPES = 0x00000001, +} NumLowerPipes; + +/* + * ColorTransform enum + */ + +typedef enum ColorTransform { +DCC_CT_AUTO = 0x00000000, +DCC_CT_NONE = 0x00000001, +ABGR_TO_A_BG_G_RB = 0x00000002, +BGRA_TO_BG_G_RB_A = 0x00000003, +} ColorTransform; + +/* + * CompareRef enum + */ + +typedef enum CompareRef { +REF_NEVER = 0x00000000, +REF_LESS = 0x00000001, +REF_EQUAL = 0x00000002, +REF_LEQUAL = 0x00000003, +REF_GREATER = 0x00000004, +REF_NOTEQUAL = 0x00000005, +REF_GEQUAL = 0x00000006, +REF_ALWAYS = 0x00000007, +} CompareRef; + +/* + * ReadSize enum + */ + +typedef enum ReadSize { +READ_256_BITS = 0x00000000, +READ_512_BITS = 0x00000001, +} ReadSize; + +/* + * DepthFormat enum + */ + +typedef enum DepthFormat { +DEPTH_INVALID = 0x00000000, +DEPTH_16 = 0x00000001, +DEPTH_X8_24 = 0x00000002, +DEPTH_8_24 = 0x00000003, +DEPTH_X8_24_FLOAT = 0x00000004, +DEPTH_8_24_FLOAT = 0x00000005, +DEPTH_32_FLOAT = 0x00000006, +DEPTH_X24_8_32_FLOAT = 0x00000007, +} DepthFormat; + +/* + * ZFormat enum + */ + +typedef enum ZFormat { +Z_INVALID = 0x00000000, +Z_16 = 0x00000001, +Z_24 = 0x00000002, +Z_32_FLOAT = 0x00000003, +} ZFormat; + +/* + * StencilFormat enum + */ + +typedef enum StencilFormat { +STENCIL_INVALID = 0x00000000, +STENCIL_8 = 0x00000001, +} StencilFormat; + +/* + * CmaskMode enum + */ + +typedef enum CmaskMode { +CMASK_CLEAR_NONE = 0x00000000, +CMASK_CLEAR_ONE = 0x00000001, +CMASK_CLEAR_ALL = 0x00000002, +CMASK_ANY_EXPANDED = 0x00000003, +CMASK_ALPHA0_FRAG1 = 0x00000004, +CMASK_ALPHA0_FRAG2 = 0x00000005, +CMASK_ALPHA0_FRAG4 = 0x00000006, +CMASK_ALPHA0_FRAGS = 0x00000007, +CMASK_ALPHA1_FRAG1 = 0x00000008, +CMASK_ALPHA1_FRAG2 = 0x00000009, +CMASK_ALPHA1_FRAG4 = 0x0000000a, +CMASK_ALPHA1_FRAGS = 0x0000000b, +CMASK_ALPHAX_FRAG1 = 0x0000000c, +CMASK_ALPHAX_FRAG2 = 0x0000000d, +CMASK_ALPHAX_FRAG4 = 0x0000000e, +CMASK_ALPHAX_FRAGS = 0x0000000f, +} CmaskMode; + +/* + * QuadExportFormat enum + */ + +typedef enum QuadExportFormat { +EXPORT_UNUSED = 0x00000000, +EXPORT_32_R = 0x00000001, +EXPORT_32_GR = 0x00000002, +EXPORT_32_AR = 0x00000003, +EXPORT_FP16_ABGR = 0x00000004, +EXPORT_UNSIGNED16_ABGR = 0x00000005, +EXPORT_SIGNED16_ABGR = 0x00000006, +EXPORT_32_ABGR = 0x00000007, +EXPORT_32BPP_8PIX = 0x00000008, +EXPORT_16_16_UNSIGNED_8PIX = 0x00000009, +EXPORT_16_16_SIGNED_8PIX = 0x0000000a, +EXPORT_16_16_FLOAT_8PIX = 0x0000000b, +} QuadExportFormat; + +/* + * QuadExportFormatOld enum + */ + +typedef enum QuadExportFormatOld { +EXPORT_4P_32BPC_ABGR = 0x00000000, +EXPORT_4P_16BPC_ABGR = 0x00000001, +EXPORT_4P_32BPC_GR = 0x00000002, +EXPORT_4P_32BPC_AR = 0x00000003, +EXPORT_2P_32BPC_ABGR = 0x00000004, +EXPORT_8P_32BPC_R = 0x00000005, +} QuadExportFormatOld; + +/* + * ColorFormat enum + */ + +typedef enum ColorFormat { +COLOR_INVALID = 0x00000000, +COLOR_8 = 0x00000001, +COLOR_16 = 0x00000002, +COLOR_8_8 = 0x00000003, +COLOR_32 = 0x00000004, +COLOR_16_16 = 0x00000005, +COLOR_10_11_11 = 0x00000006, +COLOR_11_11_10 = 0x00000007, +COLOR_10_10_10_2 = 0x00000008, +COLOR_2_10_10_10 = 0x00000009, +COLOR_8_8_8_8 = 0x0000000a, +COLOR_32_32 = 0x0000000b, +COLOR_16_16_16_16 = 0x0000000c, +COLOR_RESERVED_13 = 0x0000000d, +COLOR_32_32_32_32 = 0x0000000e, +COLOR_RESERVED_15 = 0x0000000f, +COLOR_5_6_5 = 0x00000010, +COLOR_1_5_5_5 = 0x00000011, +COLOR_5_5_5_1 = 0x00000012, +COLOR_4_4_4_4 = 0x00000013, +COLOR_8_24 = 0x00000014, +COLOR_24_8 = 0x00000015, +COLOR_X24_8_32_FLOAT = 0x00000016, +COLOR_RESERVED_23 = 0x00000017, +COLOR_RESERVED_24 = 0x00000018, +COLOR_RESERVED_25 = 0x00000019, +COLOR_RESERVED_26 = 0x0000001a, +COLOR_RESERVED_27 = 0x0000001b, +COLOR_RESERVED_28 = 0x0000001c, +COLOR_RESERVED_29 = 0x0000001d, +COLOR_RESERVED_30 = 0x0000001e, +COLOR_2_10_10_10_6E4 = 0x0000001f, +} ColorFormat; + +/* + * SurfaceFormat enum + */ + +typedef enum SurfaceFormat { +FMT_INVALID = 0x00000000, +FMT_8 = 0x00000001, +FMT_16 = 0x00000002, +FMT_8_8 = 0x00000003, +FMT_32 = 0x00000004, +FMT_16_16 = 0x00000005, +FMT_10_11_11 = 0x00000006, +FMT_11_11_10 = 0x00000007, +FMT_10_10_10_2 = 0x00000008, +FMT_2_10_10_10 = 0x00000009, +FMT_8_8_8_8 = 0x0000000a, +FMT_32_32 = 0x0000000b, +FMT_16_16_16_16 = 0x0000000c, +FMT_32_32_32 = 0x0000000d, +FMT_32_32_32_32 = 0x0000000e, +FMT_RESERVED_4 = 0x0000000f, +FMT_5_6_5 = 0x00000010, +FMT_1_5_5_5 = 0x00000011, +FMT_5_5_5_1 = 0x00000012, +FMT_4_4_4_4 = 0x00000013, +FMT_8_24 = 0x00000014, +FMT_24_8 = 0x00000015, +FMT_X24_8_32_FLOAT = 0x00000016, +FMT_RESERVED_33 = 0x00000017, +FMT_11_11_10_FLOAT = 0x00000018, +FMT_16_FLOAT = 0x00000019, +FMT_32_FLOAT = 0x0000001a, +FMT_16_16_FLOAT = 0x0000001b, +FMT_8_24_FLOAT = 0x0000001c, +FMT_24_8_FLOAT = 0x0000001d, +FMT_32_32_FLOAT = 0x0000001e, +FMT_10_11_11_FLOAT = 0x0000001f, +FMT_16_16_16_16_FLOAT = 0x00000020, +FMT_3_3_2 = 0x00000021, +FMT_6_5_5 = 0x00000022, +FMT_32_32_32_32_FLOAT = 0x00000023, +FMT_RESERVED_36 = 0x00000024, +FMT_1 = 0x00000025, +FMT_1_REVERSED = 0x00000026, +FMT_GB_GR = 0x00000027, +FMT_BG_RG = 0x00000028, +FMT_32_AS_8 = 0x00000029, +FMT_32_AS_8_8 = 0x0000002a, +FMT_5_9_9_9_SHAREDEXP = 0x0000002b, +FMT_8_8_8 = 0x0000002c, +FMT_16_16_16 = 0x0000002d, +FMT_16_16_16_FLOAT = 0x0000002e, +FMT_4_4 = 0x0000002f, +FMT_32_32_32_FLOAT = 0x00000030, +FMT_BC1 = 0x00000031, +FMT_BC2 = 0x00000032, +FMT_BC3 = 0x00000033, +FMT_BC4 = 0x00000034, +FMT_BC5 = 0x00000035, +FMT_BC6 = 0x00000036, +FMT_BC7 = 0x00000037, +FMT_32_AS_32_32_32_32 = 0x00000038, +FMT_APC3 = 0x00000039, +FMT_APC4 = 0x0000003a, +FMT_APC5 = 0x0000003b, +FMT_APC6 = 0x0000003c, +FMT_APC7 = 0x0000003d, +FMT_CTX1 = 0x0000003e, +FMT_RESERVED_63 = 0x0000003f, +} SurfaceFormat; + +/* + * BUF_DATA_FORMAT enum + */ + +typedef enum BUF_DATA_FORMAT { +BUF_DATA_FORMAT_INVALID = 0x00000000, +BUF_DATA_FORMAT_8 = 0x00000001, +BUF_DATA_FORMAT_16 = 0x00000002, +BUF_DATA_FORMAT_8_8 = 0x00000003, +BUF_DATA_FORMAT_32 = 0x00000004, +BUF_DATA_FORMAT_16_16 = 0x00000005, +BUF_DATA_FORMAT_10_11_11 = 0x00000006, +BUF_DATA_FORMAT_11_11_10 = 0x00000007, +BUF_DATA_FORMAT_10_10_10_2 = 0x00000008, +BUF_DATA_FORMAT_2_10_10_10 = 0x00000009, +BUF_DATA_FORMAT_8_8_8_8 = 0x0000000a, +BUF_DATA_FORMAT_32_32 = 0x0000000b, +BUF_DATA_FORMAT_16_16_16_16 = 0x0000000c, +BUF_DATA_FORMAT_32_32_32 = 0x0000000d, +BUF_DATA_FORMAT_32_32_32_32 = 0x0000000e, +BUF_DATA_FORMAT_RESERVED_15 = 0x0000000f, +} BUF_DATA_FORMAT; + +/* + * IMG_DATA_FORMAT enum + */ + +typedef enum IMG_DATA_FORMAT { +IMG_DATA_FORMAT_INVALID = 0x00000000, +IMG_DATA_FORMAT_8 = 0x00000001, +IMG_DATA_FORMAT_16 = 0x00000002, +IMG_DATA_FORMAT_8_8 = 0x00000003, +IMG_DATA_FORMAT_32 = 0x00000004, +IMG_DATA_FORMAT_16_16 = 0x00000005, +IMG_DATA_FORMAT_10_11_11 = 0x00000006, +IMG_DATA_FORMAT_11_11_10 = 0x00000007, +IMG_DATA_FORMAT_10_10_10_2 = 0x00000008, +IMG_DATA_FORMAT_2_10_10_10 = 0x00000009, +IMG_DATA_FORMAT_8_8_8_8 = 0x0000000a, +IMG_DATA_FORMAT_32_32 = 0x0000000b, +IMG_DATA_FORMAT_16_16_16_16 = 0x0000000c, +IMG_DATA_FORMAT_32_32_32 = 0x0000000d, +IMG_DATA_FORMAT_32_32_32_32 = 0x0000000e, +IMG_DATA_FORMAT_RESERVED_15 = 0x0000000f, +IMG_DATA_FORMAT_5_6_5 = 0x00000010, +IMG_DATA_FORMAT_1_5_5_5 = 0x00000011, +IMG_DATA_FORMAT_5_5_5_1 = 0x00000012, +IMG_DATA_FORMAT_4_4_4_4 = 0x00000013, +IMG_DATA_FORMAT_8_24 = 0x00000014, +IMG_DATA_FORMAT_24_8 = 0x00000015, +IMG_DATA_FORMAT_X24_8_32 = 0x00000016, +IMG_DATA_FORMAT_8_AS_8_8_8_8 = 0x00000017, +IMG_DATA_FORMAT_ETC2_RGB = 0x00000018, +IMG_DATA_FORMAT_ETC2_RGBA = 0x00000019, +IMG_DATA_FORMAT_ETC2_R = 0x0000001a, +IMG_DATA_FORMAT_ETC2_RG = 0x0000001b, +IMG_DATA_FORMAT_ETC2_RGBA1 = 0x0000001c, +IMG_DATA_FORMAT_RESERVED_29 = 0x0000001d, +IMG_DATA_FORMAT_RESERVED_30 = 0x0000001e, +IMG_DATA_FORMAT_6E4 = 0x0000001f, +IMG_DATA_FORMAT_GB_GR = 0x00000020, +IMG_DATA_FORMAT_BG_RG = 0x00000021, +IMG_DATA_FORMAT_5_9_9_9 = 0x00000022, +IMG_DATA_FORMAT_BC1 = 0x00000023, +IMG_DATA_FORMAT_BC2 = 0x00000024, +IMG_DATA_FORMAT_BC3 = 0x00000025, +IMG_DATA_FORMAT_BC4 = 0x00000026, +IMG_DATA_FORMAT_BC5 = 0x00000027, +IMG_DATA_FORMAT_BC6 = 0x00000028, +IMG_DATA_FORMAT_BC7 = 0x00000029, +IMG_DATA_FORMAT_16_AS_32_32 = 0x0000002a, +IMG_DATA_FORMAT_16_AS_16_16_16_16 = 0x0000002b, +IMG_DATA_FORMAT_16_AS_32_32_32_32 = 0x0000002c, +IMG_DATA_FORMAT_FMASK = 0x0000002d, +IMG_DATA_FORMAT_ASTC_2D_LDR = 0x0000002e, +IMG_DATA_FORMAT_ASTC_2D_HDR = 0x0000002f, +IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB = 0x00000030, +IMG_DATA_FORMAT_ASTC_3D_LDR = 0x00000031, +IMG_DATA_FORMAT_ASTC_3D_HDR = 0x00000032, +IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB = 0x00000033, +IMG_DATA_FORMAT_N_IN_16 = 0x00000034, +IMG_DATA_FORMAT_N_IN_16_16 = 0x00000035, +IMG_DATA_FORMAT_N_IN_16_16_16_16 = 0x00000036, +IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16 = 0x00000037, +IMG_DATA_FORMAT_RESERVED_56 = 0x00000038, +IMG_DATA_FORMAT_4_4 = 0x00000039, +IMG_DATA_FORMAT_6_5_5 = 0x0000003a, +IMG_DATA_FORMAT_RESERVED_59 = 0x0000003b, +IMG_DATA_FORMAT_RESERVED_60 = 0x0000003c, +IMG_DATA_FORMAT_8_AS_32 = 0x0000003d, +IMG_DATA_FORMAT_8_AS_32_32 = 0x0000003e, +IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x0000003f, +} IMG_DATA_FORMAT; + +/* + * BUF_NUM_FORMAT enum + */ + +typedef enum BUF_NUM_FORMAT { +BUF_NUM_FORMAT_UNORM = 0x00000000, +BUF_NUM_FORMAT_SNORM = 0x00000001, +BUF_NUM_FORMAT_USCALED = 0x00000002, +BUF_NUM_FORMAT_SSCALED = 0x00000003, +BUF_NUM_FORMAT_UINT = 0x00000004, +BUF_NUM_FORMAT_SINT = 0x00000005, +BUF_NUM_FORMAT_UNORM_UINT = 0x00000006, +BUF_NUM_FORMAT_FLOAT = 0x00000007, +} BUF_NUM_FORMAT; + +/* + * IMG_NUM_FORMAT enum + */ + +typedef enum IMG_NUM_FORMAT { +IMG_NUM_FORMAT_UNORM = 0x00000000, +IMG_NUM_FORMAT_SNORM = 0x00000001, +IMG_NUM_FORMAT_USCALED = 0x00000002, +IMG_NUM_FORMAT_SSCALED = 0x00000003, +IMG_NUM_FORMAT_UINT = 0x00000004, +IMG_NUM_FORMAT_SINT = 0x00000005, +IMG_NUM_FORMAT_UNORM_UINT = 0x00000006, +IMG_NUM_FORMAT_FLOAT = 0x00000007, +IMG_NUM_FORMAT_RESERVED_8 = 0x00000008, +IMG_NUM_FORMAT_SRGB = 0x00000009, +IMG_NUM_FORMAT_RESERVED_10 = 0x0000000a, +IMG_NUM_FORMAT_RESERVED_11 = 0x0000000b, +IMG_NUM_FORMAT_RESERVED_12 = 0x0000000c, +IMG_NUM_FORMAT_RESERVED_13 = 0x0000000d, +IMG_NUM_FORMAT_RESERVED_14 = 0x0000000e, +IMG_NUM_FORMAT_RESERVED_15 = 0x0000000f, +} IMG_NUM_FORMAT; + +/* + * IMG_NUM_FORMAT_FMASK enum + */ + +typedef enum IMG_NUM_FORMAT_FMASK { +IMG_NUM_FORMAT_FMASK_8_2_1 = 0x00000000, +IMG_NUM_FORMAT_FMASK_8_4_1 = 0x00000001, +IMG_NUM_FORMAT_FMASK_8_8_1 = 0x00000002, +IMG_NUM_FORMAT_FMASK_8_2_2 = 0x00000003, +IMG_NUM_FORMAT_FMASK_8_4_2 = 0x00000004, +IMG_NUM_FORMAT_FMASK_8_4_4 = 0x00000005, +IMG_NUM_FORMAT_FMASK_16_16_1 = 0x00000006, +IMG_NUM_FORMAT_FMASK_16_8_2 = 0x00000007, +IMG_NUM_FORMAT_FMASK_32_16_2 = 0x00000008, +IMG_NUM_FORMAT_FMASK_32_8_4 = 0x00000009, +IMG_NUM_FORMAT_FMASK_32_8_8 = 0x0000000a, +IMG_NUM_FORMAT_FMASK_64_16_4 = 0x0000000b, +IMG_NUM_FORMAT_FMASK_64_16_8 = 0x0000000c, +IMG_NUM_FORMAT_FMASK_RESERVED_13 = 0x0000000d, +IMG_NUM_FORMAT_FMASK_RESERVED_14 = 0x0000000e, +IMG_NUM_FORMAT_FMASK_RESERVED_15 = 0x0000000f, +} IMG_NUM_FORMAT_FMASK; + +/* + * IMG_NUM_FORMAT_N_IN_16 enum + */ + +typedef enum IMG_NUM_FORMAT_N_IN_16 { +IMG_NUM_FORMAT_N_IN_16_RESERVED_0 = 0x00000000, +IMG_NUM_FORMAT_N_IN_16_UNORM_10 = 0x00000001, +IMG_NUM_FORMAT_N_IN_16_UNORM_9 = 0x00000002, +IMG_NUM_FORMAT_N_IN_16_RESERVED_3 = 0x00000003, +IMG_NUM_FORMAT_N_IN_16_UINT_10 = 0x00000004, +IMG_NUM_FORMAT_N_IN_16_UINT_9 = 0x00000005, +IMG_NUM_FORMAT_N_IN_16_RESERVED_6 = 0x00000006, +IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10 = 0x00000007, +IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9 = 0x00000008, +IMG_NUM_FORMAT_N_IN_16_RESERVED_9 = 0x00000009, +IMG_NUM_FORMAT_N_IN_16_RESERVED_10 = 0x0000000a, +IMG_NUM_FORMAT_N_IN_16_RESERVED_11 = 0x0000000b, +IMG_NUM_FORMAT_N_IN_16_RESERVED_12 = 0x0000000c, +IMG_NUM_FORMAT_N_IN_16_RESERVED_13 = 0x0000000d, +IMG_NUM_FORMAT_N_IN_16_RESERVED_14 = 0x0000000e, +IMG_NUM_FORMAT_N_IN_16_RESERVED_15 = 0x0000000f, +} IMG_NUM_FORMAT_N_IN_16; + +/* + * IMG_NUM_FORMAT_ASTC_2D enum + */ + +typedef enum IMG_NUM_FORMAT_ASTC_2D { +IMG_NUM_FORMAT_ASTC_2D_4x4 = 0x00000000, +IMG_NUM_FORMAT_ASTC_2D_5x4 = 0x00000001, +IMG_NUM_FORMAT_ASTC_2D_5x5 = 0x00000002, +IMG_NUM_FORMAT_ASTC_2D_6x5 = 0x00000003, +IMG_NUM_FORMAT_ASTC_2D_6x6 = 0x00000004, +IMG_NUM_FORMAT_ASTC_2D_8x5 = 0x00000005, +IMG_NUM_FORMAT_ASTC_2D_8x6 = 0x00000006, +IMG_NUM_FORMAT_ASTC_2D_8x8 = 0x00000007, +IMG_NUM_FORMAT_ASTC_2D_10x5 = 0x00000008, +IMG_NUM_FORMAT_ASTC_2D_10x6 = 0x00000009, +IMG_NUM_FORMAT_ASTC_2D_10x8 = 0x0000000a, +IMG_NUM_FORMAT_ASTC_2D_10x10 = 0x0000000b, +IMG_NUM_FORMAT_ASTC_2D_12x10 = 0x0000000c, +IMG_NUM_FORMAT_ASTC_2D_12x12 = 0x0000000d, +IMG_NUM_FORMAT_ASTC_2D_RESERVED_14 = 0x0000000e, +IMG_NUM_FORMAT_ASTC_2D_RESERVED_15 = 0x0000000f, +} IMG_NUM_FORMAT_ASTC_2D; + +/* + * IMG_NUM_FORMAT_ASTC_3D enum + */ + +typedef enum IMG_NUM_FORMAT_ASTC_3D { +IMG_NUM_FORMAT_ASTC_3D_3x3x3 = 0x00000000, +IMG_NUM_FORMAT_ASTC_3D_4x3x3 = 0x00000001, +IMG_NUM_FORMAT_ASTC_3D_4x4x3 = 0x00000002, +IMG_NUM_FORMAT_ASTC_3D_4x4x4 = 0x00000003, +IMG_NUM_FORMAT_ASTC_3D_5x4x4 = 0x00000004, +IMG_NUM_FORMAT_ASTC_3D_5x5x4 = 0x00000005, +IMG_NUM_FORMAT_ASTC_3D_5x5x5 = 0x00000006, +IMG_NUM_FORMAT_ASTC_3D_6x5x5 = 0x00000007, +IMG_NUM_FORMAT_ASTC_3D_6x6x5 = 0x00000008, +IMG_NUM_FORMAT_ASTC_3D_6x6x6 = 0x00000009, +IMG_NUM_FORMAT_ASTC_3D_RESERVED_10 = 0x0000000a, +IMG_NUM_FORMAT_ASTC_3D_RESERVED_11 = 0x0000000b, +IMG_NUM_FORMAT_ASTC_3D_RESERVED_12 = 0x0000000c, +IMG_NUM_FORMAT_ASTC_3D_RESERVED_13 = 0x0000000d, +IMG_NUM_FORMAT_ASTC_3D_RESERVED_14 = 0x0000000e, +IMG_NUM_FORMAT_ASTC_3D_RESERVED_15 = 0x0000000f, +} IMG_NUM_FORMAT_ASTC_3D; + +/* + * TileType enum + */ + +typedef enum TileType { +ARRAY_COLOR_TILE = 0x00000000, +ARRAY_DEPTH_TILE = 0x00000001, +} TileType; + +/* + * NonDispTilingOrder enum + */ + +typedef enum NonDispTilingOrder { +ADDR_SURF_MICRO_TILING_DISPLAY = 0x00000000, +ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x00000001, +} NonDispTilingOrder; + +/* + * MicroTileMode enum + */ + +typedef enum MicroTileMode { +ADDR_SURF_DISPLAY_MICRO_TILING = 0x00000000, +ADDR_SURF_THIN_MICRO_TILING = 0x00000001, +ADDR_SURF_DEPTH_MICRO_TILING = 0x00000002, +ADDR_SURF_ROTATED_MICRO_TILING = 0x00000003, +ADDR_SURF_THICK_MICRO_TILING = 0x00000004, +} MicroTileMode; + +/* + * TileSplit enum + */ + +typedef enum TileSplit { +ADDR_SURF_TILE_SPLIT_64B = 0x00000000, +ADDR_SURF_TILE_SPLIT_128B = 0x00000001, +ADDR_SURF_TILE_SPLIT_256B = 0x00000002, +ADDR_SURF_TILE_SPLIT_512B = 0x00000003, +ADDR_SURF_TILE_SPLIT_1KB = 0x00000004, +ADDR_SURF_TILE_SPLIT_2KB = 0x00000005, +ADDR_SURF_TILE_SPLIT_4KB = 0x00000006, +} TileSplit; + +/* + * SampleSplit enum + */ + +typedef enum SampleSplit { +ADDR_SURF_SAMPLE_SPLIT_1 = 0x00000000, +ADDR_SURF_SAMPLE_SPLIT_2 = 0x00000001, +ADDR_SURF_SAMPLE_SPLIT_4 = 0x00000002, +ADDR_SURF_SAMPLE_SPLIT_8 = 0x00000003, +} SampleSplit; + +/* + * PipeConfig enum + */ + +typedef enum PipeConfig { +ADDR_SURF_P2 = 0x00000000, +ADDR_SURF_P2_RESERVED0 = 0x00000001, +ADDR_SURF_P2_RESERVED1 = 0x00000002, +ADDR_SURF_P2_RESERVED2 = 0x00000003, +ADDR_SURF_P4_8x16 = 0x00000004, +ADDR_SURF_P4_16x16 = 0x00000005, +ADDR_SURF_P4_16x32 = 0x00000006, +ADDR_SURF_P4_32x32 = 0x00000007, +ADDR_SURF_P8_16x16_8x16 = 0x00000008, +ADDR_SURF_P8_16x32_8x16 = 0x00000009, +ADDR_SURF_P8_32x32_8x16 = 0x0000000a, +ADDR_SURF_P8_16x32_16x16 = 0x0000000b, +ADDR_SURF_P8_32x32_16x16 = 0x0000000c, +ADDR_SURF_P8_32x32_16x32 = 0x0000000d, +ADDR_SURF_P8_32x64_32x32 = 0x0000000e, +ADDR_SURF_P8_RESERVED0 = 0x0000000f, +ADDR_SURF_P16_32x32_8x16 = 0x00000010, +ADDR_SURF_P16_32x32_16x16 = 0x00000011, +} PipeConfig; + +/* + * SeEnable enum + */ + +typedef enum SeEnable { +ADDR_CONFIG_DISABLE_SE = 0x00000000, +ADDR_CONFIG_ENABLE_SE = 0x00000001, +} SeEnable; + +/* + * NumBanks enum + */ + +typedef enum NumBanks { +ADDR_SURF_2_BANK = 0x00000000, +ADDR_SURF_4_BANK = 0x00000001, +ADDR_SURF_8_BANK = 0x00000002, +ADDR_SURF_16_BANK = 0x00000003, +} NumBanks; + +/* + * BankWidth enum + */ + +typedef enum BankWidth { +ADDR_SURF_BANK_WIDTH_1 = 0x00000000, +ADDR_SURF_BANK_WIDTH_2 = 0x00000001, +ADDR_SURF_BANK_WIDTH_4 = 0x00000002, +ADDR_SURF_BANK_WIDTH_8 = 0x00000003, +} BankWidth; + +/* + * BankHeight enum + */ + +typedef enum BankHeight { +ADDR_SURF_BANK_HEIGHT_1 = 0x00000000, +ADDR_SURF_BANK_HEIGHT_2 = 0x00000001, +ADDR_SURF_BANK_HEIGHT_4 = 0x00000002, +ADDR_SURF_BANK_HEIGHT_8 = 0x00000003, +} BankHeight; + +/* + * BankWidthHeight enum + */ + +typedef enum BankWidthHeight { +ADDR_SURF_BANK_WH_1 = 0x00000000, +ADDR_SURF_BANK_WH_2 = 0x00000001, +ADDR_SURF_BANK_WH_4 = 0x00000002, +ADDR_SURF_BANK_WH_8 = 0x00000003, +} BankWidthHeight; + +/* + * MacroTileAspect enum + */ + +typedef enum MacroTileAspect { +ADDR_SURF_MACRO_ASPECT_1 = 0x00000000, +ADDR_SURF_MACRO_ASPECT_2 = 0x00000001, +ADDR_SURF_MACRO_ASPECT_4 = 0x00000002, +ADDR_SURF_MACRO_ASPECT_8 = 0x00000003, +} MacroTileAspect; + +/* + * GATCL1RequestType enum + */ + +typedef enum GATCL1RequestType { +GATCL1_TYPE_NORMAL = 0x00000000, +GATCL1_TYPE_SHOOTDOWN = 0x00000001, +GATCL1_TYPE_BYPASS = 0x00000002, +} GATCL1RequestType; + +/* + * UTCL1RequestType enum + */ + +typedef enum UTCL1RequestType { +UTCL1_TYPE_NORMAL = 0x00000000, +UTCL1_TYPE_SHOOTDOWN = 0x00000001, +UTCL1_TYPE_BYPASS = 0x00000002, +} UTCL1RequestType; + +/* + * UTCL1FaultType enum + */ + +typedef enum UTCL1FaultType { +UTCL1_XNACK_SUCCESS = 0x00000000, +UTCL1_XNACK_RETRY = 0x00000001, +UTCL1_XNACK_PRT = 0x00000002, +UTCL1_XNACK_NO_RETRY = 0x00000003, +} UTCL1FaultType; + +/* + * TCC_CACHE_POLICIES enum + */ + +typedef enum TCC_CACHE_POLICIES { +TCC_CACHE_POLICY_LRU = 0x00000000, +TCC_CACHE_POLICY_STREAM = 0x00000001, +} TCC_CACHE_POLICIES; + +/* + * MTYPE enum + */ + +typedef enum MTYPE { +MTYPE_NC = 0x00000000, +MTYPE_WC = 0x00000001, +MTYPE_RW = 0x00000001, +MTYPE_CC = 0x00000002, +MTYPE_UC = 0x00000003, +} MTYPE; + +/* + * RMI_CID enum + */ + +typedef enum RMI_CID { +RMI_CID_CC = 0x00000000, +RMI_CID_FC = 0x00000001, +RMI_CID_CM = 0x00000002, +RMI_CID_DC = 0x00000003, +RMI_CID_Z = 0x00000004, +RMI_CID_S = 0x00000005, +RMI_CID_TILE = 0x00000006, +RMI_CID_ZPCPSD = 0x00000007, +} RMI_CID; + +/* + * PERFMON_COUNTER_MODE enum + */ + +typedef enum PERFMON_COUNTER_MODE { +PERFMON_COUNTER_MODE_ACCUM = 0x00000000, +PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x00000001, +PERFMON_COUNTER_MODE_MAX = 0x00000002, +PERFMON_COUNTER_MODE_DIRTY = 0x00000003, +PERFMON_COUNTER_MODE_SAMPLE = 0x00000004, +PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005, +PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006, +PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x00000007, +PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x00000008, +PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x00000009, +PERFMON_COUNTER_MODE_RESERVED = 0x0000000f, +} PERFMON_COUNTER_MODE; + +/* + * PERFMON_SPM_MODE enum + */ + +typedef enum PERFMON_SPM_MODE { +PERFMON_SPM_MODE_OFF = 0x00000000, +PERFMON_SPM_MODE_16BIT_CLAMP = 0x00000001, +PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x00000002, +PERFMON_SPM_MODE_32BIT_CLAMP = 0x00000003, +PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x00000004, +PERFMON_SPM_MODE_RESERVED_5 = 0x00000005, +PERFMON_SPM_MODE_RESERVED_6 = 0x00000006, +PERFMON_SPM_MODE_RESERVED_7 = 0x00000007, +PERFMON_SPM_MODE_TEST_MODE_0 = 0x00000008, +PERFMON_SPM_MODE_TEST_MODE_1 = 0x00000009, +PERFMON_SPM_MODE_TEST_MODE_2 = 0x0000000a, +} PERFMON_SPM_MODE; + +/* + * SurfaceTiling enum + */ + +typedef enum SurfaceTiling { +ARRAY_LINEAR = 0x00000000, +ARRAY_TILED = 0x00000001, +} SurfaceTiling; + +/* + * SurfaceArray enum + */ + +typedef enum SurfaceArray { +ARRAY_1D = 0x00000000, +ARRAY_2D = 0x00000001, +ARRAY_3D = 0x00000002, +ARRAY_3D_SLICE = 0x00000003, +} SurfaceArray; + +/* + * ColorArray enum + */ + +typedef enum ColorArray { +ARRAY_2D_ALT_COLOR = 0x00000000, +ARRAY_2D_COLOR = 0x00000001, +ARRAY_3D_SLICE_COLOR = 0x00000003, +} ColorArray; + +/* + * DepthArray enum + */ + +typedef enum DepthArray { +ARRAY_2D_ALT_DEPTH = 0x00000000, +ARRAY_2D_DEPTH = 0x00000001, +} DepthArray; + +/* + * ENUM_NUM_SIMD_PER_CU enum + */ + +typedef enum ENUM_NUM_SIMD_PER_CU { +NUM_SIMD_PER_CU = 0x00000004, +} ENUM_NUM_SIMD_PER_CU; + +/* + * DSM_ENABLE_ERROR_INJECT enum + */ + +typedef enum DSM_ENABLE_ERROR_INJECT { +DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000, +DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001, +DSM_ENABLE_ERROR_INJECT_DOUBLE = 0x00000002, +DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED = 0x00000003, +} DSM_ENABLE_ERROR_INJECT; + +/* + * DSM_SELECT_INJECT_DELAY enum + */ + +typedef enum DSM_SELECT_INJECT_DELAY { +DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000, +DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001, +} DSM_SELECT_INJECT_DELAY; + +/* + * SWIZZLE_TYPE_ENUM enum + */ + +typedef enum SWIZZLE_TYPE_ENUM { +SW_Z = 0x00000000, +SW_S = 0x00000001, +SW_D = 0x00000002, +SW_R = 0x00000003, +SW_L = 0x00000004, +} SWIZZLE_TYPE_ENUM; + +/* + * TC_MICRO_TILE_MODE enum + */ + +typedef enum TC_MICRO_TILE_MODE { +MICRO_TILE_MODE_LINEAR = 0x00000000, +MICRO_TILE_MODE_ROTATED = 0x00000001, +MICRO_TILE_MODE_STD_2D = 0x00000002, +MICRO_TILE_MODE_STD_3D = 0x00000003, +MICRO_TILE_MODE_DISPLAY_2D = 0x00000004, +MICRO_TILE_MODE_DISPLAY_3D = 0x00000005, +MICRO_TILE_MODE_Z_2D = 0x00000006, +MICRO_TILE_MODE_Z_3D = 0x00000007, +} TC_MICRO_TILE_MODE; + +/* + * SWIZZLE_MODE_ENUM enum + */ + +typedef enum SWIZZLE_MODE_ENUM { +SW_LINEAR = 0x00000000, +SW_256B_S = 0x00000001, +SW_256B_D = 0x00000002, +SW_256B_R = 0x00000003, +SW_4KB_Z = 0x00000004, +SW_4KB_S = 0x00000005, +SW_4KB_D = 0x00000006, +SW_4KB_R = 0x00000007, +SW_64KB_Z = 0x00000008, +SW_64KB_S = 0x00000009, +SW_64KB_D = 0x0000000a, +SW_64KB_R = 0x0000000b, +SW_VAR_Z = 0x0000000c, +SW_VAR_S = 0x0000000d, +SW_VAR_D = 0x0000000e, +SW_VAR_R = 0x0000000f, +SW_RESERVED_16 = 0x00000010, +SW_RESERVED_17 = 0x00000011, +SW_RESERVED_18 = 0x00000012, +SW_RESERVED_19 = 0x00000013, +SW_4KB_Z_X = 0x00000014, +SW_4KB_S_X = 0x00000015, +SW_4KB_D_X = 0x00000016, +SW_4KB_R_X = 0x00000017, +SW_64KB_Z_X = 0x00000018, +SW_64KB_S_X = 0x00000019, +SW_64KB_D_X = 0x0000001a, +SW_64KB_R_X = 0x0000001b, +SW_VAR_Z_X = 0x0000001c, +SW_VAR_S_X = 0x0000001d, +SW_VAR_D_X = 0x0000001e, +SW_VAR_R_X = 0x0000001f, +SW_RESERVED_12 = 0x00000020, +SW_RESERVED_13 = 0x00000021, +SW_RESERVED_14 = 0x00000022, +SW_RESERVED_15 = 0x00000023, +} SWIZZLE_MODE_ENUM; + +/* + * PipeTiling enum + */ + +typedef enum PipeTiling { +CONFIG_1_PIPE = 0x00000000, +CONFIG_2_PIPE = 0x00000001, +CONFIG_4_PIPE = 0x00000002, +CONFIG_8_PIPE = 0x00000003, +} PipeTiling; + +/* + * BankTiling enum + */ + +typedef enum BankTiling { +CONFIG_4_BANK = 0x00000000, +CONFIG_8_BANK = 0x00000001, +} BankTiling; + +/* + * GroupInterleave enum + */ + +typedef enum GroupInterleave { +CONFIG_256B_GROUP = 0x00000000, +CONFIG_512B_GROUP = 0x00000001, +} GroupInterleave; + +/* + * RowTiling enum + */ + +typedef enum RowTiling { +CONFIG_1KB_ROW = 0x00000000, +CONFIG_2KB_ROW = 0x00000001, +CONFIG_4KB_ROW = 0x00000002, +CONFIG_8KB_ROW = 0x00000003, +CONFIG_1KB_ROW_OPT = 0x00000004, +CONFIG_2KB_ROW_OPT = 0x00000005, +CONFIG_4KB_ROW_OPT = 0x00000006, +CONFIG_8KB_ROW_OPT = 0x00000007, +} RowTiling; + +/* + * BankSwapBytes enum + */ + +typedef enum BankSwapBytes { +CONFIG_128B_SWAPS = 0x00000000, +CONFIG_256B_SWAPS = 0x00000001, +CONFIG_512B_SWAPS = 0x00000002, +CONFIG_1KB_SWAPS = 0x00000003, +} BankSwapBytes; + +/* + * SampleSplitBytes enum + */ + +typedef enum SampleSplitBytes { +CONFIG_1KB_SPLIT = 0x00000000, +CONFIG_2KB_SPLIT = 0x00000001, +CONFIG_4KB_SPLIT = 0x00000002, +CONFIG_8KB_SPLIT = 0x00000003, +} SampleSplitBytes; + +/******************************************************* + * AZSTREAM Enums + *******************************************************/ + +/* + * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR { +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 0x00000001, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR; + +/* + * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR { +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 0x00000001, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR; + +/* + * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS { +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 0x00000001, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS; + +/* + * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY { +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 0x00000001, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY; + +/* + * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE { +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 0x00000001, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE; + +/* + * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE { +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 0x00000001, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE; + +/* + * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE { +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 0x00000001, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE; + +/* + * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN { +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 0x00000001, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN; + +/* + * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET { +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 0x00000001, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET; + +/* + * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE { +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001, +} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE; + +/* + * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE { +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004, +} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE; + +/* + * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR { +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007, +} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR; + +/* + * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE { +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005, +} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE; + +/* + * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum + */ + +typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS { +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 0x00000008, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 0x00000009, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 0x0000000a, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 0x0000000b, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 0x0000000c, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 0x0000000d, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 0x0000000e, +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 0x0000000f, +} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS; + +/******************************************************* + * BLNDV Enums + *******************************************************/ + +/* + * BLNDV_CONTROL_BLND_MODE enum + */ + +typedef enum BLNDV_CONTROL_BLND_MODE { +BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x00000000, +BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x00000001, +BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x00000002, +BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x00000003, +} BLNDV_CONTROL_BLND_MODE; + +/* + * BLNDV_CONTROL_BLND_STEREO_TYPE enum + */ + +typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE { +BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0x00000000, +BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 0x00000001, +BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 0x00000002, +BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x00000003, +} BLNDV_CONTROL_BLND_STEREO_TYPE; + +/* + * BLNDV_CONTROL_BLND_STEREO_POLARITY enum + */ + +typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY { +BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW = 0x00000000, +BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x00000001, +} BLNDV_CONTROL_BLND_STEREO_POLARITY; + +/* + * BLNDV_CONTROL_BLND_FEEDTHROUGH_EN enum + */ + +typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN { +BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x00000000, +BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x00000001, +} BLNDV_CONTROL_BLND_FEEDTHROUGH_EN; + +/* + * BLNDV_CONTROL_BLND_ALPHA_MODE enum + */ + +typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE { +BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x00000000, +BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001, +BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x00000002, +BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x00000003, +} BLNDV_CONTROL_BLND_ALPHA_MODE; + +/* + * BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY enum + */ + +typedef enum BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY { +BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE = 0x00000000, +BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE = 0x00000001, +} BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY; + +/* + * BLNDV_CONTROL_BLND_MULTIPLIED_MODE enum + */ + +typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE { +BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x00000000, +BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x00000001, +} BLNDV_CONTROL_BLND_MULTIPLIED_MODE; + +/* + * BLNDV_SM_CONTROL2_SM_MODE enum + */ + +typedef enum BLNDV_SM_CONTROL2_SM_MODE { +BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x00000000, +BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x00000002, +BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004, +BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006, +} BLNDV_SM_CONTROL2_SM_MODE; + +/* + * BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE enum + */ + +typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE { +BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x00000000, +BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x00000001, +} BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE; + +/* + * BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE enum + */ + +typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE { +BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x00000000, +BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x00000001, +} BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE; + +/* + * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL enum + */ + +typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL { +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000, +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001, +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002, +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003, +} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL; + +/* + * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL enum + */ + +typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL { +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000, +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001, +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002, +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003, +} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL; + +/* + * BLNDV_CONTROL2_PTI_ENABLE enum + */ + +typedef enum BLNDV_CONTROL2_PTI_ENABLE { +BLNDV_CONTROL2_PTI_ENABLE_FALSE = 0x00000000, +BLNDV_CONTROL2_PTI_ENABLE_TRUE = 0x00000001, +} BLNDV_CONTROL2_PTI_ENABLE; + +/* + * BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN enum + */ + +typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN { +BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x00000000, +BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x00000001, +} BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN; + +/* + * BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN enum + */ + +typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN { +BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x00000000, +BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x00000001, +} BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN; + +/* + * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK enum + */ + +typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK { +BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0x00000000, +BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 0x00000001, +} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK; + +/* + * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK enum + */ + +typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK { +BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0x00000000, +BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 0x00000001, +} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK; + +/* + * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK enum + */ + +typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK { +BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0x00000000, +BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 0x00000001, +} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK; + +/* + * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK enum + */ + +typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK { +BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0x00000000, +BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 0x00000001, +} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; + +/* + * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK enum + */ + +typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK { +BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0x00000000, +BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 0x00000001, +} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK; + +/* + * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK enum + */ + +typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK { +BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0x00000000, +BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 0x00000001, +} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK; + +/* + * BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK enum + */ + +typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK { +BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x00000000, +BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x00000001, +} BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK; + +/* + * BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK enum + */ + +typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK { +BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x00000000, +BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x00000001, +} BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK; + +/* + * BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE enum + */ + +typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE { +BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x00000000, +BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x00000001, +} BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE; + +/* + * BLNDV_DEBUG_BLND_CNV_MUX_SELECT enum + */ + +typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT { +BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x00000000, +BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x00000001, +} BLNDV_DEBUG_BLND_CNV_MUX_SELECT; + +/* + * BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN enum + */ + +typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN { +BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000, +BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001, +} BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN; + +/******************************************************* + * LBV Enums + *******************************************************/ + +/* + * LBV_PIXEL_DEPTH enum + */ + +typedef enum LBV_PIXEL_DEPTH { +PIXEL_DEPTH_30BPP = 0x00000000, +PIXEL_DEPTH_24BPP = 0x00000001, +PIXEL_DEPTH_18BPP = 0x00000002, +PIXEL_DEPTH_38BPP = 0x00000003, +} LBV_PIXEL_DEPTH; + +/* + * LBV_PIXEL_EXPAN_MODE enum + */ + +typedef enum LBV_PIXEL_EXPAN_MODE { +PIXEL_EXPAN_MODE_ZERO_EXP = 0x00000000, +PIXEL_EXPAN_MODE_DYN_EXP = 0x00000001, +} LBV_PIXEL_EXPAN_MODE; + +/* + * LBV_INTERLEAVE_EN enum + */ + +typedef enum LBV_INTERLEAVE_EN { +INTERLEAVE_DIS = 0x00000000, +INTERLEAVE_EN = 0x00000001, +} LBV_INTERLEAVE_EN; + +/* + * LBV_PIXEL_REDUCE_MODE enum + */ + +typedef enum LBV_PIXEL_REDUCE_MODE { +PIXEL_REDUCE_MODE_TRUNCATION = 0x00000000, +PIXEL_REDUCE_MODE_ROUNDING = 0x00000001, +} LBV_PIXEL_REDUCE_MODE; + +/* + * LBV_DYNAMIC_PIXEL_DEPTH enum + */ + +typedef enum LBV_DYNAMIC_PIXEL_DEPTH { +DYNAMIC_PIXEL_DEPTH_36BPP = 0x00000000, +DYNAMIC_PIXEL_DEPTH_30BPP = 0x00000001, +} LBV_DYNAMIC_PIXEL_DEPTH; + +/* + * LBV_DITHER_EN enum + */ + +typedef enum LBV_DITHER_EN { +DITHER_DIS = 0x00000000, +DITHER_EN = 0x00000001, +} LBV_DITHER_EN; + +/* + * LBV_DOWNSCALE_PREFETCH_EN enum + */ + +typedef enum LBV_DOWNSCALE_PREFETCH_EN { +DOWNSCALE_PREFETCH_DIS = 0x00000000, +DOWNSCALE_PREFETCH_EN = 0x00000001, +} LBV_DOWNSCALE_PREFETCH_EN; + +/* + * LBV_MEMORY_CONFIG enum + */ + +typedef enum LBV_MEMORY_CONFIG { +MEMORY_CONFIG_0 = 0x00000000, +MEMORY_CONFIG_1 = 0x00000001, +MEMORY_CONFIG_2 = 0x00000002, +MEMORY_CONFIG_3 = 0x00000003, +} LBV_MEMORY_CONFIG; + +/* + * LBV_SYNC_RESET_SEL2 enum + */ + +typedef enum LBV_SYNC_RESET_SEL2 { +SYNC_RESET_SEL2_VBLANK = 0x00000000, +SYNC_RESET_SEL2_VSYNC = 0x00000001, +} LBV_SYNC_RESET_SEL2; + +/* + * LBV_SYNC_DURATION enum + */ + +typedef enum LBV_SYNC_DURATION { +SYNC_DURATION_16 = 0x00000000, +SYNC_DURATION_32 = 0x00000001, +SYNC_DURATION_64 = 0x00000002, +SYNC_DURATION_128 = 0x00000003, +} LBV_SYNC_DURATION; + +/******************************************************* + * CRTC Enums + *******************************************************/ + +/* + * CRTC_CONTROL_CRTC_START_POINT_CNTL enum + */ + +typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL { +CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x00000000, +CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x00000001, +} CRTC_CONTROL_CRTC_START_POINT_CNTL; + +/* + * CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL enum + */ + +typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL { +CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x00000000, +CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x00000001, +} CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL; + +/* + * CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL enum + */ + +typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL { +CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0x00000000, +CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT = 0x00000001, +CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x00000002, +CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST = 0x00000003, +} CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL; + +/* + * CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY enum + */ + +typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY { +CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0x00000000, +CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x00000001, +} CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY; + +/* + * CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE enum + */ + +typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE { +CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE = 0x00000000, +CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x00000001, +} CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE; + +/* + * CRTC_CONTROL_CRTC_SOF_PULL_EN enum + */ + +typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN { +CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE = 0x00000000, +CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE = 0x00000001, +} CRTC_CONTROL_CRTC_SOF_PULL_EN; + +/* + * CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL enum + */ + +typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL { +CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE = 0x00000000, +CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE = 0x00000001, +} CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL; + +/* + * CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL enum + */ + +typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL { +CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE = 0x00000000, +CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE = 0x00000001, +} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL; + +/* + * CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL enum + */ + +typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL { +CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE = 0x00000000, +CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE = 0x00000001, +} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL; + +/* + * CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN enum + */ + +typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN { +CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE = 0x00000000, +CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE = 0x00000001, +} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN; + +/* + * CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC enum + */ + +typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC { +CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000, +CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 0x00000001, +} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC; + +/* + * CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT enum + */ + +typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT { +CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000, +CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE = 0x00000001, +} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT; + +/* + * CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK enum + */ + +typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK { +CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0x00000000, +CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE = 0x00000001, +} CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK; + +/* + * CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR enum + */ + +typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR { +CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000, +CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE = 0x00000001, +} CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR; + +/* + * CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL enum + */ + +typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL { +CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE = 0x00000000, +CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE = 0x00000001, +} CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL; + +/* + * CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN enum + */ + +typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN { +CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE = 0x00000000, +CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE = 0x00000001, +} CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN; + +/* + * CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT enum + */ + +typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT { +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER = 0x00000001, +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER = 0x00000002, +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF = 0x00000005, +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE = 0x00000006, +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA = 0x00000007, +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA = 0x00000008, +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB = 0x00000009, +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB = 0x0000000a, +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1 = 0x0000000b, +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2 = 0x0000000c, +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD = 0x0000000d, +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC = 0x0000000e, +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0 = 0x00000010, +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1 = 0x00000011, +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2 = 0x00000012, +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON = 0x00000013, +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA = 0x00000014, +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB = 0x00000015, +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW = 0x00000016, +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW = 0x00000017, +} CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT; + +/* + * CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT enum + */ + +typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT { +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE = 0x00000001, +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA = 0x00000002, +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB = 0x00000003, +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA = 0x00000004, +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB = 0x00000005, +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 0x00000006, +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC = 0x00000007, +} CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT; + +/* + * CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN enum + */ + +typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN { +CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE = 0x00000000, +CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x00000001, +} CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN; + +/* + * CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR enum + */ + +typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR { +CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE = 0x00000000, +CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE = 0x00000001, +} CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR; + +/* + * CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT enum + */ + +typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT { +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER = 0x00000001, +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER = 0x00000002, +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF = 0x00000005, +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE = 0x00000006, +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA = 0x00000007, +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA = 0x00000008, +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB = 0x00000009, +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB = 0x0000000a, +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1 = 0x0000000b, +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2 = 0x0000000c, +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD = 0x0000000d, +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC = 0x0000000e, +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0 = 0x00000010, +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1 = 0x00000011, +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2 = 0x00000012, +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON = 0x00000013, +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA = 0x00000014, +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB = 0x00000015, +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW = 0x00000016, +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW = 0x00000017, +} CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT; + +/* + * CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT enum + */ + +typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT { +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE = 0x00000001, +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA = 0x00000002, +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB = 0x00000003, +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA = 0x00000004, +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB = 0x00000005, +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 0x00000006, +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC = 0x00000007, +} CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT; + +/* + * CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN enum + */ + +typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN { +CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE = 0x00000000, +CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x00000001, +} CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN; + +/* + * CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR enum + */ + +typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR { +CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE = 0x00000000, +CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE = 0x00000001, +} CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR; + +/* + * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE enum + */ + +typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE { +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE = 0x00000000, +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT = 0x00000001, +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 0x00000002, +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED = 0x00000003, +} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE; + +/* + * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK enum + */ + +typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK { +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE = 0x00000000, +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE = 0x00000001, +} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK; + +/* + * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL enum + */ + +typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL { +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0x00000000, +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 0x00000001, +} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL; + +/* + * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR enum + */ + +typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR { +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000, +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE = 0x00000001, +} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR; + +/* + * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT enum + */ + +typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT { +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0x00000000, +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 0x00000001, +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 0x00000002, +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 0x00000003, +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 0x00000004, +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 0x00000005, +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 0x00000006, +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 0x00000007, +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 0x00000008, +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK = 0x00000009, +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL = 0x0000000a, +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 0x0000000b, +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 0x0000000c, +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 0x0000000d, +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 0x0000000e, +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 0x0000000f, +} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT; + +/* + * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY enum + */ + +typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY { +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE = 0x00000000, +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE = 0x00000001, +} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY; + +/* + * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY enum + */ + +typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY { +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE = 0x00000000, +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE = 0x00000001, +} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY; + +/* + * CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE enum + */ + +typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE { +CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO = 0x00000000, +CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT = 0x00000001, +CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT = 0x00000002, +CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED = 0x00000003, +} CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE; + +/* + * CRTC_CONTROL_CRTC_MASTER_EN enum + */ + +typedef enum CRTC_CONTROL_CRTC_MASTER_EN { +CRTC_CONTROL_CRTC_MASTER_EN_FALSE = 0x00000000, +CRTC_CONTROL_CRTC_MASTER_EN_TRUE = 0x00000001, +} CRTC_CONTROL_CRTC_MASTER_EN; + +/* + * CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN enum + */ + +typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN { +CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE = 0x00000000, +CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE = 0x00000001, +} CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN; + +/* + * CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE enum + */ + +typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE { +CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE = 0x00000000, +CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE = 0x00000001, +} CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE; + +/* + * CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE enum + */ + +typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE { +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE = 0x00000000, +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE = 0x00000001, +} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE; + +/* + * CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD enum + */ + +typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD { +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT = 0x00000000, +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD = 0x00000001, +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN = 0x00000002, +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 0x00000003, +} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD; + +/* + * CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY enum + */ + +typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY { +CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE = 0x00000000, +CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE = 0x00000001, +} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY; + +/* + * CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT enum + */ + +typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT { +CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE = 0x00000000, +CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE = 0x00000001, +} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT; + +/* + * CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN enum + */ + +typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN { +CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE = 0x00000000, +CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE = 0x00000001, +} CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN; + +/* + * CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE enum + */ + +typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE { +CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000, +CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 0x00000001, +} CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE; + +/* + * CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR enum + */ + +typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR { +CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000, +CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 0x00000001, +} CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR; + +/* + * CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE enum + */ + +typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE { +CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE = 0x00000000, +CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 0x00000001, +CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 0x00000002, +CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED = 0x00000003, +} CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE; + +/* + * CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY enum + */ + +typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY { +CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0x00000000, +CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 0x00000001, +} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY; + +/* + * CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY enum + */ + +typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY { +CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE = 0x00000000, +CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE = 0x00000001, +} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY; + +/* + * CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY enum + */ + +typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY { +CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE = 0x00000000, +CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE = 0x00000001, +} CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY; + +/* + * CRTC_STEREO_CONTROL_CRTC_STEREO_EN enum + */ + +typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN { +CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE = 0x00000000, +CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE = 0x00000001, +} CRTC_STEREO_CONTROL_CRTC_STEREO_EN; + +/* + * CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR enum + */ + +typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR { +CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0x00000000, +CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE = 0x00000001, +} CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR; + +/* + * CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL enum + */ + +typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL { +CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0x00000000, +CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 0x00000001, +CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 0x00000002, +CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 0x00000003, +} CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL; + +/* + * CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY enum + */ + +typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY { +CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE = 0x00000000, +CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE = 0x00000001, +} CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY; + +/* + * CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY enum + */ + +typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY { +CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE = 0x00000000, +CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE = 0x00000001, +} CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY; + +/* + * CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN enum + */ + +typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN { +CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE = 0x00000000, +CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE = 0x00000001, +} CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN; + +/* + * CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN enum + */ + +typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN { +CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE = 0x00000000, +CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE = 0x00000001, +} CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN; + +/* + * CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK enum + */ + +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK { +CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE = 0x00000000, +CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE = 0x00000001, +} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK; + +/* + * CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE enum + */ + +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE { +CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE = 0x00000000, +CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE = 0x00000001, +} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE; + +/* + * CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK enum + */ + +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK { +CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE = 0x00000000, +CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE = 0x00000001, +} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK; + +/* + * CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE enum + */ + +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE { +CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE = 0x00000000, +CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE = 0x00000001, +} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE; + +/* + * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK enum + */ + +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK { +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE = 0x00000000, +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE = 0x00000001, +} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK; + +/* + * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE enum + */ + +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE { +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0x00000000, +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE = 0x00000001, +} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE; + +/* + * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK enum + */ + +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK { +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0x00000000, +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 0x00000001, +} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK; + +/* + * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum + */ + +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE { +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0x00000000, +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 0x00000001, +} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE; + +/* + * CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK enum + */ + +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK { +CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE = 0x00000000, +CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE = 0x00000001, +} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK; + +/* + * CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE enum + */ + +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE { +CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0x00000000, +CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE = 0x00000001, +} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE; + +/* + * CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK enum + */ + +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK { +CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE = 0x00000000, +CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE = 0x00000001, +} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK; + +/* + * CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE enum + */ + +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE { +CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0x00000000, +CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE = 0x00000001, +} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE; + +/* + * CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK enum + */ + +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK { +CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE = 0x00000000, +CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE = 0x00000001, +} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK; + +/* + * CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE enum + */ + +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE { +CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE = 0x00000000, +CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE = 0x00000001, +} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE; + +/* + * CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK enum + */ + +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK { +CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE = 0x00000000, +CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE = 0x00000001, +} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK; + +/* + * CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE enum + */ + +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE { +CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0x00000000, +CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE = 0x00000001, +} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE; + +/* + * CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK enum + */ + +typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK { +CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE = 0x00000000, +CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE = 0x00000001, +} CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK; + +/* + * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY enum + */ + +typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY { +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE = 0x00000000, +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE = 0x00000001, +} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY; + +/* + * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN enum + */ + +typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN { +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE = 0x00000000, +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE = 0x00000001, +} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN; + +/* + * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE enum + */ + +typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE { +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0 = 0x00000000, +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1 = 0x00000001, +} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE; + +/* + * CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE enum + */ + +typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE { +CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE = 0x00000000, +CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE = 0x00000001, +} CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE; + +/* + * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN enum + */ + +typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN { +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE = 0x00000000, +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE = 0x00000001, +} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN; + +/* + * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE enum + */ + +typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE { +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB = 0x00000000, +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601 = 0x00000001, +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709 = 0x00000002, +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS = 0x00000003, +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS = 0x00000004, +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB = 0x00000005, +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB = 0x00000006, +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS = 0x00000007, +} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE; + +/* + * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE enum + */ + +typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE { +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE = 0x00000000, +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE = 0x00000001, +} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE; + +/* + * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT enum + */ + +typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT { +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC = 0x00000000, +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC = 0x00000001, +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC = 0x00000002, +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED = 0x00000003, +} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT; + +/* + * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum + */ + +typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK { +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x00000000, +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x00000001, +} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK; + +/* + * MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK enum + */ + +typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK { +MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE = 0x00000000, +MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE = 0x00000001, +} MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK; + +/* + * MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK enum + */ + +typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK { +MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0x00000000, +MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 0x00000001, +} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK; + +/* + * MASTER_UPDATE_MODE_MASTER_UPDATE_MODE enum + */ + +typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE { +MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN = 0x00000000, +MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA = 0x00000001, +MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA = 0x00000002, +MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE = 0x00000003, +} MASTER_UPDATE_MODE_MASTER_UPDATE_MODE; + +/* + * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum + */ + +typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE { +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0x00000000, +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN = 0x00000001, +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD = 0x00000002, +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 0x00000003, +} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE; + +/* + * CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE enum + */ + +typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE { +CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE = 0x00000000, +CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG = 0x00000001, +CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL = 0x00000002, +} CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE; + +/* + * CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR enum + */ + +typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR { +CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0x00000000, +CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE = 0x00000001, +} CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR; + +/* + * CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR enum + */ + +typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR { +CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0x00000000, +CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE = 0x00000001, +} CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR; + +/* + * CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR enum + */ + +typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR { +CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE = 0x00000000, +CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE = 0x00000001, +} CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR; + +/* + * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum + */ + +typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY { +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0x00000000, +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 0x00000001, +} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY; + +/* + * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE enum + */ + +typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE { +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000, +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 0x00000001, +} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE; + +/* + * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR enum + */ + +typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR { +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000, +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE = 0x00000001, +} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR; + +/* + * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE enum + */ + +typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE { +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0x00000000, +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 0x00000001, +} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE; + +/* + * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR enum + */ + +typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR { +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000, +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE = 0x00000001, +} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR; + +/* + * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE enum + */ + +typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE { +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000, +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 0x00000001, +} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE; + +/* + * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE enum + */ + +typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE { +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0x00000000, +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 0x00000001, +} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE; + +/* + * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR enum + */ + +typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR { +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000, +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE = 0x00000001, +} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR; + +/* + * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE enum + */ + +typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE { +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000, +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 0x00000001, +} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE; + +/* + * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE enum + */ + +typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE { +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0x00000000, +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 0x00000001, +} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE; + +/* + * CRTC_CRC_CNTL_CRTC_CRC_EN enum + */ + +typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN { +CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE = 0x00000000, +CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE = 0x00000001, +} CRTC_CRC_CNTL_CRTC_CRC_EN; + +/* + * CRTC_CRC_CNTL_CRTC_CRC_CONT_EN enum + */ + +typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN { +CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE = 0x00000000, +CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE = 0x00000001, +} CRTC_CRC_CNTL_CRTC_CRC_CONT_EN; + +/* + * CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE enum + */ + +typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE { +CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT = 0x00000000, +CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT = 0x00000001, +CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES = 0x00000002, +CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS = 0x00000003, +} CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE; + +/* + * CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE enum + */ + +typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE { +CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP = 0x00000000, +CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM = 0x00000001, +CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002, +CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 0x00000003, +} CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE; + +/* + * CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS enum + */ + +typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS { +CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000, +CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 0x00000001, +} CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS; + +/* + * CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT enum + */ + +typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT { +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB = 0x00000000, +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B = 0x00000001, +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB = 0x00000002, +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B = 0x00000003, +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB = 0x00000004, +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B = 0x00000005, +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB = 0x00000006, +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B = 0x00000007, +} CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT; + +/* + * CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT enum + */ + +typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT { +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB = 0x00000000, +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B = 0x00000001, +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB = 0x00000002, +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B = 0x00000003, +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB = 0x00000004, +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B = 0x00000005, +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB = 0x00000006, +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B = 0x00000007, +} CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT; + +/* + * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE enum + */ + +typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE { +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE = 0x00000000, +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT = 0x00000001, +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS = 0x00000002, +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED = 0x00000003, +} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE; + +/* + * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE enum + */ + +typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE { +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE = 0x00000000, +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE = 0x00000001, +} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE; + +/* + * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE enum + */ + +typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE { +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE = 0x00000000, +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE = 0x00000001, +} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE; + +/* + * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW enum + */ + +typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW { +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel = 0x00000000, +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel = 0x00000001, +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel = 0x00000002, +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel = 0x00000003, +} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW; + +/* + * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE enum + */ + +typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE { +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE = 0x00000000, +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE = 0x00000001, +} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE; + +/* + * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE enum + */ + +typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE { +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0x00000000, +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE = 0x00000001, +} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE; + +/* + * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY enum + */ + +typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY { +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE = 0x00000000, +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE = 0x00000001, +} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY; + +/* + * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY enum + */ + +typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY { +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE = 0x00000000, +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE = 0x00000001, +} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY; + +/* + * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE enum + */ + +typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE { +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE = 0x00000000, +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE = 0x00000001, +} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE; + +/* + * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE enum + */ + +typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE { +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE = 0x00000000, +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE = 0x00000001, +} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE; + +/* + * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR enum + */ + +typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR { +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0x00000000, +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE = 0x00000001, +} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR; + +/* + * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE enum + */ + +typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE { +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE = 0x00000000, +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE = 0x00000001, +} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE; + +/* + * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT enum + */ + +typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT { +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME = 0x00000000, +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME = 0x00000001, +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME = 0x00000002, +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME = 0x00000003, +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME = 0x00000004, +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME = 0x00000005, +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME = 0x00000006, +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME = 0x00000007, +} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT; + +/* + * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE enum + */ + +typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE { +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE = 0x00000000, +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE = 0x00000001, +} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE; + +/* + * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR enum + */ + +typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR { +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE = 0x00000000, +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE = 0x00000001, +} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR; + +/* + * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE enum + */ + +typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE { +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE = 0x00000000, +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE = 0x00000001, +} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE; + +/* + * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE enum + */ + +typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE { +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE = 0x00000000, +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE = 0x00000001, +} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE; + +/* + * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR enum + */ + +typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR { +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0x00000000, +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE = 0x00000001, +} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR; + +/* + * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE enum + */ + +typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE { +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE = 0x00000000, +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE = 0x00000001, +} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE; + +/* + * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE enum + */ + +typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE { +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE = 0x00000000, +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE = 0x00000001, +} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE; + +/* + * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR enum + */ + +typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR { +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE = 0x00000000, +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE = 0x00000001, +} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR; + +/* + * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE enum + */ + +typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE { +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE = 0x00000000, +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE = 0x00000001, +} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE; + +/* + * CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE enum + */ + +typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE { +CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE = 0x00000000, +CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE = 0x00000001, +} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE; + +/* + * CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE enum + */ + +typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE { +CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0x00000000, +CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON = 0x00000001, +} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE; + +/* + * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN enum + */ + +typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN { +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE = 0x00000000, +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE = 0x00000001, +} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN; + +/* + * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB enum + */ + +typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB { +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE = 0x00000000, +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE = 0x00000001, +} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB; + +/* + * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE enum + */ + +typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE { +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0x00000000, +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 0x00000001, +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 0x00000002, +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 0x00000003, +} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE; + +/* + * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR enum + */ + +typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR { +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0x00000000, +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 0x00000001, +} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR; + +/* + * CRTC_V_SYNC_A_POL enum + */ + +typedef enum CRTC_V_SYNC_A_POL { +CRTC_V_SYNC_A_POL_HIGH = 0x00000000, +CRTC_V_SYNC_A_POL_LOW = 0x00000001, +} CRTC_V_SYNC_A_POL; + +/* + * CRTC_H_SYNC_A_POL enum + */ + +typedef enum CRTC_H_SYNC_A_POL { +CRTC_H_SYNC_A_POL_HIGH = 0x00000000, +CRTC_H_SYNC_A_POL_LOW = 0x00000001, +} CRTC_H_SYNC_A_POL; + +/* + * CRTC_HORZ_REPETITION_COUNT enum + */ + +typedef enum CRTC_HORZ_REPETITION_COUNT { +CRTC_HORZ_REPETITION_COUNT_0 = 0x00000000, +CRTC_HORZ_REPETITION_COUNT_1 = 0x00000001, +CRTC_HORZ_REPETITION_COUNT_2 = 0x00000002, +CRTC_HORZ_REPETITION_COUNT_3 = 0x00000003, +CRTC_HORZ_REPETITION_COUNT_4 = 0x00000004, +CRTC_HORZ_REPETITION_COUNT_5 = 0x00000005, +CRTC_HORZ_REPETITION_COUNT_6 = 0x00000006, +CRTC_HORZ_REPETITION_COUNT_7 = 0x00000007, +CRTC_HORZ_REPETITION_COUNT_8 = 0x00000008, +CRTC_HORZ_REPETITION_COUNT_9 = 0x00000009, +CRTC_HORZ_REPETITION_COUNT_10 = 0x0000000a, +CRTC_HORZ_REPETITION_COUNT_11 = 0x0000000b, +CRTC_HORZ_REPETITION_COUNT_12 = 0x0000000c, +CRTC_HORZ_REPETITION_COUNT_13 = 0x0000000d, +CRTC_HORZ_REPETITION_COUNT_14 = 0x0000000e, +CRTC_HORZ_REPETITION_COUNT_15 = 0x0000000f, +} CRTC_HORZ_REPETITION_COUNT; + +/* + * CRTC_DRR_MODE_DBUF_UPDATE_MODE enum + */ + +typedef enum CRTC_DRR_MODE_DBUF_UPDATE_MODE { +CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE = 0x00000000, +CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL = 0x00000001, +CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF = 0x00000002, +CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF = 0x00000003, +} CRTC_DRR_MODE_DBUF_UPDATE_MODE; + +/******************************************************* + * FMT Enums + *******************************************************/ + +/* + * FMT_CONTROL_PIXEL_ENCODING enum + */ + +typedef enum FMT_CONTROL_PIXEL_ENCODING { +FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x00000000, +FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x00000001, +FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 0x00000002, +FMT_CONTROL_PIXEL_ENCODING_RESERVED = 0x00000003, +} FMT_CONTROL_PIXEL_ENCODING; + +/* + * FMT_CONTROL_SUBSAMPLING_MODE enum + */ + +typedef enum FMT_CONTROL_SUBSAMPLING_MODE { +FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x00000000, +FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x00000001, +FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 0x00000002, +FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 0x00000003, +} FMT_CONTROL_SUBSAMPLING_MODE; + +/* + * FMT_CONTROL_SUBSAMPLING_ORDER enum + */ + +typedef enum FMT_CONTROL_SUBSAMPLING_ORDER { +FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x00000000, +FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x00000001, +} FMT_CONTROL_SUBSAMPLING_ORDER; + +/* + * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum + */ + +typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS { +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0x00000000, +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 0x00000001, +} FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS; + +/* + * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum + */ + +typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE { +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x00000000, +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x00000001, +} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE; + +/* + * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum + */ + +typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH { +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x00000000, +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x00000001, +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x00000002, +} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH; + +/* + * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum + */ + +typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH { +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x00000000, +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001, +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x00000002, +} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH; + +/* + * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum + */ + +typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH { +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0x00000000, +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 0x00000001, +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 0x00000002, +} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH; + +/* + * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum + */ + +typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL { +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x00000000, +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x00000001, +} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL; + +/* + * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum + */ + +typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL { +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x00000000, +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x00000001, +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x00000002, +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x00000003, +} FMT_BIT_DEPTH_CONTROL_25FRC_SEL; + +/* + * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum + */ + +typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL { +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x00000000, +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x00000001, +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x00000002, +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x00000003, +} FMT_BIT_DEPTH_CONTROL_50FRC_SEL; + +/* + * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum + */ + +typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL { +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x00000000, +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x00000001, +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x00000002, +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x00000003, +} FMT_BIT_DEPTH_CONTROL_75FRC_SEL; + +/* + * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT enum + */ + +typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT { +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN = 0x00000000, +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN = 0x00000001, +} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT; + +/* + * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum + */ + +typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 { +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0x00000000, +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 0x00000001, +} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0; + +/* + * FMT_CLAMP_CNTL_COLOR_FORMAT enum + */ + +typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT { +FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x00000000, +FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x00000001, +FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x00000002, +FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 0x00000003, +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x00000004, +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x00000005, +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x00000006, +FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x00000007, +} FMT_CLAMP_CNTL_COLOR_FORMAT; + +/* + * FMT_CRC_CNTL_CONT_EN enum + */ + +typedef enum FMT_CRC_CNTL_CONT_EN { +FMT_CRC_CNTL_CONT_EN_ONE_SHOT = 0x00000000, +FMT_CRC_CNTL_CONT_EN_CONT = 0x00000001, +} FMT_CRC_CNTL_CONT_EN; + +/* + * FMT_CRC_CNTL_INCLUDE_OVERSCAN enum + */ + +typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN { +FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE = 0x00000000, +FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE = 0x00000001, +} FMT_CRC_CNTL_INCLUDE_OVERSCAN; + +/* + * FMT_CRC_CNTL_ONLY_BLANKB enum + */ + +typedef enum FMT_CRC_CNTL_ONLY_BLANKB { +FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD = 0x00000000, +FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK = 0x00000001, +} FMT_CRC_CNTL_ONLY_BLANKB; + +/* + * FMT_CRC_CNTL_PSR_MODE_ENABLE enum + */ + +typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE { +FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL = 0x00000000, +FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC = 0x00000001, +} FMT_CRC_CNTL_PSR_MODE_ENABLE; + +/* + * FMT_CRC_CNTL_INTERLACE_MODE enum + */ + +typedef enum FMT_CRC_CNTL_INTERLACE_MODE { +FMT_CRC_CNTL_INTERLACE_MODE_TOP = 0x00000000, +FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM = 0x00000001, +FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002, +FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH = 0x00000003, +} FMT_CRC_CNTL_INTERLACE_MODE; + +/* + * FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE enum + */ + +typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE { +FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL = 0x00000000, +FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN = 0x00000001, +} FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE; + +/* + * FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT enum + */ + +typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT { +FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN = 0x00000000, +FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD = 0x00000001, +} FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT; + +/* + * FMT_DEBUG_CNTL_COLOR_SELECT enum + */ + +typedef enum FMT_DEBUG_CNTL_COLOR_SELECT { +FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0x00000000, +FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 0x00000001, +FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 0x00000002, +FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 0x00000003, +} FMT_DEBUG_CNTL_COLOR_SELECT; + +/* + * FMT_SPATIAL_DITHER_MODE enum + */ + +typedef enum FMT_SPATIAL_DITHER_MODE { +FMT_SPATIAL_DITHER_MODE_0 = 0x00000000, +FMT_SPATIAL_DITHER_MODE_1 = 0x00000001, +FMT_SPATIAL_DITHER_MODE_2 = 0x00000002, +FMT_SPATIAL_DITHER_MODE_3 = 0x00000003, +} FMT_SPATIAL_DITHER_MODE; + +/* + * FMT_STEREOSYNC_OVR_POL enum + */ + +typedef enum FMT_STEREOSYNC_OVR_POL { +FMT_STEREOSYNC_OVR_POL_INVERTED = 0x00000000, +FMT_STEREOSYNC_OVR_POL_NOT_INVERTED = 0x00000001, +} FMT_STEREOSYNC_OVR_POL; + +/* + * FMT_DYNAMIC_EXP_MODE enum + */ + +typedef enum FMT_DYNAMIC_EXP_MODE { +FMT_DYNAMIC_EXP_MODE_10to12 = 0x00000000, +FMT_DYNAMIC_EXP_MODE_8to12 = 0x00000001, +} FMT_DYNAMIC_EXP_MODE; + +/******************************************************* + * HPD Enums + *******************************************************/ + +/* + * HPD_INT_CONTROL_ACK enum + */ + +typedef enum HPD_INT_CONTROL_ACK { +HPD_INT_CONTROL_ACK_0 = 0x00000000, +HPD_INT_CONTROL_ACK_1 = 0x00000001, +} HPD_INT_CONTROL_ACK; + +/* + * HPD_INT_CONTROL_POLARITY enum + */ + +typedef enum HPD_INT_CONTROL_POLARITY { +HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x00000000, +HPD_INT_CONTROL_GEN_INT_ON_CON = 0x00000001, +} HPD_INT_CONTROL_POLARITY; + +/* + * HPD_INT_CONTROL_RX_INT_ACK enum + */ + +typedef enum HPD_INT_CONTROL_RX_INT_ACK { +HPD_INT_CONTROL_RX_INT_ACK_0 = 0x00000000, +HPD_INT_CONTROL_RX_INT_ACK_1 = 0x00000001, +} HPD_INT_CONTROL_RX_INT_ACK; + +/******************************************************* + * LB Enums + *******************************************************/ + +/* + * LB_DATA_FORMAT_PIXEL_DEPTH enum + */ + +typedef enum LB_DATA_FORMAT_PIXEL_DEPTH { +LB_DATA_FORMAT_PIXEL_DEPTH_30BPP = 0x00000000, +LB_DATA_FORMAT_PIXEL_DEPTH_24BPP = 0x00000001, +LB_DATA_FORMAT_PIXEL_DEPTH_18BPP = 0x00000002, +LB_DATA_FORMAT_PIXEL_DEPTH_36BPP = 0x00000003, +} LB_DATA_FORMAT_PIXEL_DEPTH; + +/* + * LB_DATA_FORMAT_PIXEL_EXPAN_MODE enum + */ + +typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE { +LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION = 0x00000000, +LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION = 0x00000001, +} LB_DATA_FORMAT_PIXEL_EXPAN_MODE; + +/* + * LB_DATA_FORMAT_PIXEL_REDUCE_MODE enum + */ + +typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE { +LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION = 0x00000000, +LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING = 0x00000001, +} LB_DATA_FORMAT_PIXEL_REDUCE_MODE; + +/* + * LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH enum + */ + +typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH { +LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP = 0x00000000, +LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP = 0x00000001, +} LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH; + +/* + * LB_DATA_FORMAT_INTERLEAVE_EN enum + */ + +typedef enum LB_DATA_FORMAT_INTERLEAVE_EN { +LB_DATA_FORMAT_INTERLEAVE_DISABLE = 0x00000000, +LB_DATA_FORMAT_INTERLEAVE_ENABLE = 0x00000001, +} LB_DATA_FORMAT_INTERLEAVE_EN; + +/* + * LB_DATA_FORMAT_REQUEST_MODE enum + */ + +typedef enum LB_DATA_FORMAT_REQUEST_MODE { +LB_DATA_FORMAT_REQUEST_MODE_NORMAL = 0x00000000, +LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE = 0x00000001, +} LB_DATA_FORMAT_REQUEST_MODE; + +/* + * LB_DATA_FORMAT_ALPHA_EN enum + */ + +typedef enum LB_DATA_FORMAT_ALPHA_EN { +LB_DATA_FORMAT_ALPHA_DISABLE = 0x00000000, +LB_DATA_FORMAT_ALPHA_ENABLE = 0x00000001, +} LB_DATA_FORMAT_ALPHA_EN; + +/* + * LB_VLINE_START_END_VLINE_INV enum + */ + +typedef enum LB_VLINE_START_END_VLINE_INV { +LB_VLINE_START_END_VLINE_NORMAL = 0x00000000, +LB_VLINE_START_END_VLINE_INVERSE = 0x00000001, +} LB_VLINE_START_END_VLINE_INV; + +/* + * LB_VLINE2_START_END_VLINE2_INV enum + */ + +typedef enum LB_VLINE2_START_END_VLINE2_INV { +LB_VLINE2_START_END_VLINE2_NORMAL = 0x00000000, +LB_VLINE2_START_END_VLINE2_INVERSE = 0x00000001, +} LB_VLINE2_START_END_VLINE2_INV; + +/* + * LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK enum + */ + +typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK { +LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE = 0x00000000, +LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE = 0x00000001, +} LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK; + +/* + * LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK enum + */ + +typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK { +LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE = 0x00000000, +LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE = 0x00000001, +} LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK; + +/* + * LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK enum + */ + +typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK { +LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE = 0x00000000, +LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE = 0x00000001, +} LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK; + +/* + * LB_VLINE_STATUS_VLINE_ACK enum + */ + +typedef enum LB_VLINE_STATUS_VLINE_ACK { +LB_VLINE_STATUS_VLINE_NORMAL = 0x00000000, +LB_VLINE_STATUS_VLINE_CLEAR = 0x00000001, +} LB_VLINE_STATUS_VLINE_ACK; + +/* + * LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE enum + */ + +typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE { +LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000, +LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED = 0x00000001, +} LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE; + +/* + * LB_VLINE2_STATUS_VLINE2_ACK enum + */ + +typedef enum LB_VLINE2_STATUS_VLINE2_ACK { +LB_VLINE2_STATUS_VLINE2_NORMAL = 0x00000000, +LB_VLINE2_STATUS_VLINE2_CLEAR = 0x00000001, +} LB_VLINE2_STATUS_VLINE2_ACK; + +/* + * LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE enum + */ + +typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE { +LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000, +LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED = 0x00000001, +} LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE; + +/* + * LB_VBLANK_STATUS_VBLANK_ACK enum + */ + +typedef enum LB_VBLANK_STATUS_VBLANK_ACK { +LB_VBLANK_STATUS_VBLANK_NORMAL = 0x00000000, +LB_VBLANK_STATUS_VBLANK_CLEAR = 0x00000001, +} LB_VBLANK_STATUS_VBLANK_ACK; + +/* + * LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE enum + */ + +typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE { +LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000, +LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED = 0x00000001, +} LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE; + +/* + * LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL enum + */ + +typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL { +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE = 0x00000000, +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK = 0x00000001, +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET = 0x00000002, +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET = 0x00000003, +} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL; + +/* + * LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 enum + */ + +typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 { +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK = 0x00000000, +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC = 0x00000001, +} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2; + +/* + * LB_SYNC_RESET_SEL_LB_SYNC_DURATION enum + */ + +typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION { +LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS = 0x00000000, +LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS = 0x00000001, +LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 0x00000002, +LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS = 0x00000003, +} LB_SYNC_RESET_SEL_LB_SYNC_DURATION; + +/* + * LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN enum + */ + +typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN { +LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE = 0x00000000, +LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE = 0x00000001, +} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN; + +/* + * LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN enum + */ + +typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN { +LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE = 0x00000000, +LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE = 0x00000001, +} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN; + +/* + * LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK enum + */ + +typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK { +LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL = 0x00000000, +LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET = 0x00000001, +} LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK; + +/* + * LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK enum + */ + +typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK { +LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL = 0x00000000, +LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET = 0x00000001, +} LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK; + +/* + * LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE enum + */ + +typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE { +LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 0x00000002, +LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP = 0x00000003, +} LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE; + +/* + * LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET enum + */ + +typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET { +LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL = 0x00000000, +LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE = 0x00000001, +} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET; + +/* + * LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK enum + */ + +typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK { +LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0 = 0x00000000, +LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1 = 0x00000001, +} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK; + +/* + * LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE enum + */ + +typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE { +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT = 0x00000000, +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG = 0x00000001, +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE = 0x00000002, +} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE; + +/* + * LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE enum + */ + +typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE { +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE = 0x00000000, +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN = 0x00000001, +} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE; + +/* + * LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE enum + */ + +typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE { +ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER = 0x00000001, +ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE = 0x00000002, +} LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE; + +/* + * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL enum + */ + +typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL { +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0 = 0x00000000, +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1 = 0x00000001, +} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL; + +/* + * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE enum + */ + +typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE { +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE = 0x00000000, +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE = 0x00000001, +} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE; + +/* + * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO enum + */ + +typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO { +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO = 0x00000000, +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO = 0x00000001, +} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO; + +/* + * LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN enum + */ + +typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN { +LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0 = 0x00000000, +LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1 = 0x00000001, +} LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN; + +/******************************************************* + * DIG Enums + *******************************************************/ + +/* + * HDMI_KEEPOUT_MODE enum + */ + +typedef enum HDMI_KEEPOUT_MODE { +HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0x00000000, +HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 0x00000001, +} HDMI_KEEPOUT_MODE; + +/* + * HDMI_DATA_SCRAMBLE_EN enum + */ + +typedef enum HDMI_DATA_SCRAMBLE_EN { +HDMI_DATA_SCRAMBLE_DISABLE = 0x00000000, +HDMI_DATA_SCRAMBLE_ENABLE = 0x00000001, +} HDMI_DATA_SCRAMBLE_EN; + +/* + * HDMI_CLOCK_CHANNEL_RATE enum + */ + +typedef enum HDMI_CLOCK_CHANNEL_RATE { +HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x00000000, +HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x00000001, +} HDMI_CLOCK_CHANNEL_RATE; + +/* + * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum + */ + +typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED { +HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0x00000000, +HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 0x00000001, +} HDMI_NO_EXTRA_NULL_PACKET_FILLED; + +/* + * HDMI_PACKET_GEN_VERSION enum + */ + +typedef enum HDMI_PACKET_GEN_VERSION { +HDMI_PACKET_GEN_VERSION_OLD = 0x00000000, +HDMI_PACKET_GEN_VERSION_NEW = 0x00000001, +} HDMI_PACKET_GEN_VERSION; + +/* + * HDMI_ERROR_ACK enum + */ + +typedef enum HDMI_ERROR_ACK { +HDMI_ERROR_ACK_INT = 0x00000000, +HDMI_ERROR_NOT_ACK = 0x00000001, +} HDMI_ERROR_ACK; + +/* + * HDMI_ERROR_MASK enum + */ + +typedef enum HDMI_ERROR_MASK { +HDMI_ERROR_MASK_INT = 0x00000000, +HDMI_ERROR_NOT_MASK = 0x00000001, +} HDMI_ERROR_MASK; + +/* + * HDMI_DEEP_COLOR_DEPTH enum + */ + +typedef enum HDMI_DEEP_COLOR_DEPTH { +HDMI_DEEP_COLOR_DEPTH_24BPP = 0x00000000, +HDMI_DEEP_COLOR_DEPTH_30BPP = 0x00000001, +HDMI_DEEP_COLOR_DEPTH_36BPP = 0x00000002, +HDMI_DEEP_COLOR_DEPTH_RESERVED = 0x00000003, +} HDMI_DEEP_COLOR_DEPTH; + +/* + * HDMI_AUDIO_DELAY_EN enum + */ + +typedef enum HDMI_AUDIO_DELAY_EN { +HDMI_AUDIO_DELAY_DISABLE = 0x00000000, +HDMI_AUDIO_DELAY_58CLK = 0x00000001, +HDMI_AUDIO_DELAY_56CLK = 0x00000002, +HDMI_AUDIO_DELAY_RESERVED = 0x00000003, +} HDMI_AUDIO_DELAY_EN; + +/* + * HDMI_AUDIO_SEND_MAX_PACKETS enum + */ + +typedef enum HDMI_AUDIO_SEND_MAX_PACKETS { +HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0x00000000, +HDMI_SEND_MAX_AUDIO_PACKETS = 0x00000001, +} HDMI_AUDIO_SEND_MAX_PACKETS; + +/* + * HDMI_ACR_SEND enum + */ + +typedef enum HDMI_ACR_SEND { +HDMI_ACR_NOT_SEND = 0x00000000, +HDMI_ACR_PKT_SEND = 0x00000001, +} HDMI_ACR_SEND; + +/* + * HDMI_ACR_CONT enum + */ + +typedef enum HDMI_ACR_CONT { +HDMI_ACR_CONT_DISABLE = 0x00000000, +HDMI_ACR_CONT_ENABLE = 0x00000001, +} HDMI_ACR_CONT; + +/* + * HDMI_ACR_SELECT enum + */ + +typedef enum HDMI_ACR_SELECT { +HDMI_ACR_SELECT_HW = 0x00000000, +HDMI_ACR_SELECT_32K = 0x00000001, +HDMI_ACR_SELECT_44K = 0x00000002, +HDMI_ACR_SELECT_48K = 0x00000003, +} HDMI_ACR_SELECT; + +/* + * HDMI_ACR_SOURCE enum + */ + +typedef enum HDMI_ACR_SOURCE { +HDMI_ACR_SOURCE_HW = 0x00000000, +HDMI_ACR_SOURCE_SW = 0x00000001, +} HDMI_ACR_SOURCE; + +/* + * HDMI_ACR_N_MULTIPLE enum + */ + +typedef enum HDMI_ACR_N_MULTIPLE { +HDMI_ACR_0_MULTIPLE_RESERVED = 0x00000000, +HDMI_ACR_1_MULTIPLE = 0x00000001, +HDMI_ACR_2_MULTIPLE = 0x00000002, +HDMI_ACR_3_MULTIPLE_RESERVED = 0x00000003, +HDMI_ACR_4_MULTIPLE = 0x00000004, +HDMI_ACR_5_MULTIPLE_RESERVED = 0x00000005, +HDMI_ACR_6_MULTIPLE_RESERVED = 0x00000006, +HDMI_ACR_7_MULTIPLE_RESERVED = 0x00000007, +} HDMI_ACR_N_MULTIPLE; + +/* + * HDMI_ACR_AUDIO_PRIORITY enum + */ + +typedef enum HDMI_ACR_AUDIO_PRIORITY { +HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x00000000, +HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x00000001, +} HDMI_ACR_AUDIO_PRIORITY; + +/* + * HDMI_NULL_SEND enum + */ + +typedef enum HDMI_NULL_SEND { +HDMI_NULL_NOT_SEND = 0x00000000, +HDMI_NULL_PKT_SEND = 0x00000001, +} HDMI_NULL_SEND; + +/* + * HDMI_GC_SEND enum + */ + +typedef enum HDMI_GC_SEND { +HDMI_GC_NOT_SEND = 0x00000000, +HDMI_GC_PKT_SEND = 0x00000001, +} HDMI_GC_SEND; + +/* + * HDMI_GC_CONT enum + */ + +typedef enum HDMI_GC_CONT { +HDMI_GC_CONT_DISABLE = 0x00000000, +HDMI_GC_CONT_ENABLE = 0x00000001, +} HDMI_GC_CONT; + +/* + * HDMI_ISRC_SEND enum + */ + +typedef enum HDMI_ISRC_SEND { +HDMI_ISRC_NOT_SEND = 0x00000000, +HDMI_ISRC_PKT_SEND = 0x00000001, +} HDMI_ISRC_SEND; + +/* + * HDMI_ISRC_CONT enum + */ + +typedef enum HDMI_ISRC_CONT { +HDMI_ISRC_CONT_DISABLE = 0x00000000, +HDMI_ISRC_CONT_ENABLE = 0x00000001, +} HDMI_ISRC_CONT; + +/* + * HDMI_AVI_INFO_SEND enum + */ + +typedef enum HDMI_AVI_INFO_SEND { +HDMI_AVI_INFO_NOT_SEND = 0x00000000, +HDMI_AVI_INFO_PKT_SEND = 0x00000001, +} HDMI_AVI_INFO_SEND; + +/* + * HDMI_AVI_INFO_CONT enum + */ + +typedef enum HDMI_AVI_INFO_CONT { +HDMI_AVI_INFO_CONT_DISABLE = 0x00000000, +HDMI_AVI_INFO_CONT_ENABLE = 0x00000001, +} HDMI_AVI_INFO_CONT; + +/* + * HDMI_AUDIO_INFO_SEND enum + */ + +typedef enum HDMI_AUDIO_INFO_SEND { +HDMI_AUDIO_INFO_NOT_SEND = 0x00000000, +HDMI_AUDIO_INFO_PKT_SEND = 0x00000001, +} HDMI_AUDIO_INFO_SEND; + +/* + * HDMI_AUDIO_INFO_CONT enum + */ + +typedef enum HDMI_AUDIO_INFO_CONT { +HDMI_AUDIO_INFO_CONT_DISABLE = 0x00000000, +HDMI_AUDIO_INFO_CONT_ENABLE = 0x00000001, +} HDMI_AUDIO_INFO_CONT; + +/* + * HDMI_MPEG_INFO_SEND enum + */ + +typedef enum HDMI_MPEG_INFO_SEND { +HDMI_MPEG_INFO_NOT_SEND = 0x00000000, +HDMI_MPEG_INFO_PKT_SEND = 0x00000001, +} HDMI_MPEG_INFO_SEND; + +/* + * HDMI_MPEG_INFO_CONT enum + */ + +typedef enum HDMI_MPEG_INFO_CONT { +HDMI_MPEG_INFO_CONT_DISABLE = 0x00000000, +HDMI_MPEG_INFO_CONT_ENABLE = 0x00000001, +} HDMI_MPEG_INFO_CONT; + +/* + * HDMI_GENERIC0_SEND enum + */ + +typedef enum HDMI_GENERIC0_SEND { +HDMI_GENERIC0_NOT_SEND = 0x00000000, +HDMI_GENERIC0_PKT_SEND = 0x00000001, +} HDMI_GENERIC0_SEND; + +/* + * HDMI_GENERIC0_CONT enum + */ + +typedef enum HDMI_GENERIC0_CONT { +HDMI_GENERIC0_CONT_DISABLE = 0x00000000, +HDMI_GENERIC0_CONT_ENABLE = 0x00000001, +} HDMI_GENERIC0_CONT; + +/* + * HDMI_GENERIC1_SEND enum + */ + +typedef enum HDMI_GENERIC1_SEND { +HDMI_GENERIC1_NOT_SEND = 0x00000000, +HDMI_GENERIC1_PKT_SEND = 0x00000001, +} HDMI_GENERIC1_SEND; + +/* + * HDMI_GENERIC1_CONT enum + */ + +typedef enum HDMI_GENERIC1_CONT { +HDMI_GENERIC1_CONT_DISABLE = 0x00000000, +HDMI_GENERIC1_CONT_ENABLE = 0x00000001, +} HDMI_GENERIC1_CONT; + +/* + * HDMI_GC_AVMUTE_CONT enum + */ + +typedef enum HDMI_GC_AVMUTE_CONT { +HDMI_GC_AVMUTE_CONT_DISABLE = 0x00000000, +HDMI_GC_AVMUTE_CONT_ENABLE = 0x00000001, +} HDMI_GC_AVMUTE_CONT; + +/* + * HDMI_PACKING_PHASE_OVERRIDE enum + */ + +typedef enum HDMI_PACKING_PHASE_OVERRIDE { +HDMI_PACKING_PHASE_SET_BY_HW = 0x00000000, +HDMI_PACKING_PHASE_SET_BY_SW = 0x00000001, +} HDMI_PACKING_PHASE_OVERRIDE; + +/* + * HDMI_GENERIC2_SEND enum + */ + +typedef enum HDMI_GENERIC2_SEND { +HDMI_GENERIC2_NOT_SEND = 0x00000000, +HDMI_GENERIC2_PKT_SEND = 0x00000001, +} HDMI_GENERIC2_SEND; + +/* + * HDMI_GENERIC2_CONT enum + */ + +typedef enum HDMI_GENERIC2_CONT { +HDMI_GENERIC2_CONT_DISABLE = 0x00000000, +HDMI_GENERIC2_CONT_ENABLE = 0x00000001, +} HDMI_GENERIC2_CONT; + +/* + * HDMI_GENERIC3_SEND enum + */ + +typedef enum HDMI_GENERIC3_SEND { +HDMI_GENERIC3_NOT_SEND = 0x00000000, +HDMI_GENERIC3_PKT_SEND = 0x00000001, +} HDMI_GENERIC3_SEND; + +/* + * HDMI_GENERIC3_CONT enum + */ + +typedef enum HDMI_GENERIC3_CONT { +HDMI_GENERIC3_CONT_DISABLE = 0x00000000, +HDMI_GENERIC3_CONT_ENABLE = 0x00000001, +} HDMI_GENERIC3_CONT; + +/* + * TMDS_PIXEL_ENCODING enum + */ + +typedef enum TMDS_PIXEL_ENCODING { +TMDS_PIXEL_ENCODING_444_OR_420 = 0x00000000, +TMDS_PIXEL_ENCODING_422 = 0x00000001, +} TMDS_PIXEL_ENCODING; + +/* + * TMDS_COLOR_FORMAT enum + */ + +typedef enum TMDS_COLOR_FORMAT { +TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0x00000000, +TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 0x00000001, +TMDS_COLOR_FORMAT_DUAL30BPP = 0x00000002, +TMDS_COLOR_FORMAT_RESERVED = 0x00000003, +} TMDS_COLOR_FORMAT; + +/* + * TMDS_STEREOSYNC_CTL_SEL_REG enum + */ + +typedef enum TMDS_STEREOSYNC_CTL_SEL_REG { +TMDS_STEREOSYNC_CTL0 = 0x00000000, +TMDS_STEREOSYNC_CTL1 = 0x00000001, +TMDS_STEREOSYNC_CTL2 = 0x00000002, +TMDS_STEREOSYNC_CTL3 = 0x00000003, +} TMDS_STEREOSYNC_CTL_SEL_REG; + +/* + * TMDS_CTL0_DATA_SEL enum + */ + +typedef enum TMDS_CTL0_DATA_SEL { +TMDS_CTL0_DATA_SEL0_RESERVED = 0x00000000, +TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 0x00000001, +TMDS_CTL0_DATA_SEL2_VSYNC = 0x00000002, +TMDS_CTL0_DATA_SEL3_RESERVED = 0x00000003, +TMDS_CTL0_DATA_SEL4_HSYNC = 0x00000004, +TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 0x00000005, +TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 0x00000006, +TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 0x00000007, +} TMDS_CTL0_DATA_SEL; + +/* + * TMDS_CTL0_DATA_INVERT enum + */ + +typedef enum TMDS_CTL0_DATA_INVERT { +TMDS_CTL0_DATA_NORMAL = 0x00000000, +TMDS_CTL0_DATA_INVERT_EN = 0x00000001, +} TMDS_CTL0_DATA_INVERT; + +/* + * TMDS_CTL0_DATA_MODULATION enum + */ + +typedef enum TMDS_CTL0_DATA_MODULATION { +TMDS_CTL0_DATA_MODULATION_DISABLE = 0x00000000, +TMDS_CTL0_DATA_MODULATION_BIT0 = 0x00000001, +TMDS_CTL0_DATA_MODULATION_BIT1 = 0x00000002, +TMDS_CTL0_DATA_MODULATION_BIT2 = 0x00000003, +} TMDS_CTL0_DATA_MODULATION; + +/* + * TMDS_CTL0_PATTERN_OUT_EN enum + */ + +typedef enum TMDS_CTL0_PATTERN_OUT_EN { +TMDS_CTL0_PATTERN_OUT_DISABLE = 0x00000000, +TMDS_CTL0_PATTERN_OUT_ENABLE = 0x00000001, +} TMDS_CTL0_PATTERN_OUT_EN; + +/* + * TMDS_CTL1_DATA_SEL enum + */ + +typedef enum TMDS_CTL1_DATA_SEL { +TMDS_CTL1_DATA_SEL0_RESERVED = 0x00000000, +TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 0x00000001, +TMDS_CTL1_DATA_SEL2_VSYNC = 0x00000002, +TMDS_CTL1_DATA_SEL3_RESERVED = 0x00000003, +TMDS_CTL1_DATA_SEL4_HSYNC = 0x00000004, +TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 0x00000005, +TMDS_CTL1_DATA_SEL8_BLANK_TIME = 0x00000006, +TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 0x00000007, +} TMDS_CTL1_DATA_SEL; + +/* + * TMDS_CTL1_DATA_INVERT enum + */ + +typedef enum TMDS_CTL1_DATA_INVERT { +TMDS_CTL1_DATA_NORMAL = 0x00000000, +TMDS_CTL1_DATA_INVERT_EN = 0x00000001, +} TMDS_CTL1_DATA_INVERT; + +/* + * TMDS_CTL1_DATA_MODULATION enum + */ + +typedef enum TMDS_CTL1_DATA_MODULATION { +TMDS_CTL1_DATA_MODULATION_DISABLE = 0x00000000, +TMDS_CTL1_DATA_MODULATION_BIT0 = 0x00000001, +TMDS_CTL1_DATA_MODULATION_BIT1 = 0x00000002, +TMDS_CTL1_DATA_MODULATION_BIT2 = 0x00000003, +} TMDS_CTL1_DATA_MODULATION; + +/* + * TMDS_CTL1_PATTERN_OUT_EN enum + */ + +typedef enum TMDS_CTL1_PATTERN_OUT_EN { +TMDS_CTL1_PATTERN_OUT_DISABLE = 0x00000000, +TMDS_CTL1_PATTERN_OUT_ENABLE = 0x00000001, +} TMDS_CTL1_PATTERN_OUT_EN; + +/* + * TMDS_CTL2_DATA_SEL enum + */ + +typedef enum TMDS_CTL2_DATA_SEL { +TMDS_CTL2_DATA_SEL0_RESERVED = 0x00000000, +TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 0x00000001, +TMDS_CTL2_DATA_SEL2_VSYNC = 0x00000002, +TMDS_CTL2_DATA_SEL3_RESERVED = 0x00000003, +TMDS_CTL2_DATA_SEL4_HSYNC = 0x00000004, +TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 0x00000005, +TMDS_CTL2_DATA_SEL8_BLANK_TIME = 0x00000006, +TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 0x00000007, +} TMDS_CTL2_DATA_SEL; + +/* + * TMDS_CTL2_DATA_INVERT enum + */ + +typedef enum TMDS_CTL2_DATA_INVERT { +TMDS_CTL2_DATA_NORMAL = 0x00000000, +TMDS_CTL2_DATA_INVERT_EN = 0x00000001, +} TMDS_CTL2_DATA_INVERT; + +/* + * TMDS_CTL2_DATA_MODULATION enum + */ + +typedef enum TMDS_CTL2_DATA_MODULATION { +TMDS_CTL2_DATA_MODULATION_DISABLE = 0x00000000, +TMDS_CTL2_DATA_MODULATION_BIT0 = 0x00000001, +TMDS_CTL2_DATA_MODULATION_BIT1 = 0x00000002, +TMDS_CTL2_DATA_MODULATION_BIT2 = 0x00000003, +} TMDS_CTL2_DATA_MODULATION; + +/* + * TMDS_CTL2_PATTERN_OUT_EN enum + */ + +typedef enum TMDS_CTL2_PATTERN_OUT_EN { +TMDS_CTL2_PATTERN_OUT_DISABLE = 0x00000000, +TMDS_CTL2_PATTERN_OUT_ENABLE = 0x00000001, +} TMDS_CTL2_PATTERN_OUT_EN; + +/* + * TMDS_CTL3_DATA_INVERT enum + */ + +typedef enum TMDS_CTL3_DATA_INVERT { +TMDS_CTL3_DATA_NORMAL = 0x00000000, +TMDS_CTL3_DATA_INVERT_EN = 0x00000001, +} TMDS_CTL3_DATA_INVERT; + +/* + * TMDS_CTL3_DATA_MODULATION enum + */ + +typedef enum TMDS_CTL3_DATA_MODULATION { +TMDS_CTL3_DATA_MODULATION_DISABLE = 0x00000000, +TMDS_CTL3_DATA_MODULATION_BIT0 = 0x00000001, +TMDS_CTL3_DATA_MODULATION_BIT1 = 0x00000002, +TMDS_CTL3_DATA_MODULATION_BIT2 = 0x00000003, +} TMDS_CTL3_DATA_MODULATION; + +/* + * TMDS_CTL3_PATTERN_OUT_EN enum + */ + +typedef enum TMDS_CTL3_PATTERN_OUT_EN { +TMDS_CTL3_PATTERN_OUT_DISABLE = 0x00000000, +TMDS_CTL3_PATTERN_OUT_ENABLE = 0x00000001, +} TMDS_CTL3_PATTERN_OUT_EN; + +/* + * TMDS_CTL3_DATA_SEL enum + */ + +typedef enum TMDS_CTL3_DATA_SEL { +TMDS_CTL3_DATA_SEL0_RESERVED = 0x00000000, +TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 0x00000001, +TMDS_CTL3_DATA_SEL2_VSYNC = 0x00000002, +TMDS_CTL3_DATA_SEL3_RESERVED = 0x00000003, +TMDS_CTL3_DATA_SEL4_HSYNC = 0x00000004, +TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 0x00000005, +TMDS_CTL3_DATA_SEL8_BLANK_TIME = 0x00000006, +TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 0x00000007, +} TMDS_CTL3_DATA_SEL; + +/* + * DIG_FE_CNTL_SOURCE_SELECT enum + */ + +typedef enum DIG_FE_CNTL_SOURCE_SELECT { +DIG_FE_SOURCE_FROM_FMT0 = 0x00000000, +DIG_FE_SOURCE_FROM_FMT1 = 0x00000001, +DIG_FE_SOURCE_FROM_FMT2 = 0x00000002, +DIG_FE_SOURCE_FROM_FMT3 = 0x00000003, +DIG_FE_SOURCE_FROM_FMT4 = 0x00000004, +DIG_FE_SOURCE_FROM_FMT5 = 0x00000005, +} DIG_FE_CNTL_SOURCE_SELECT; + +/* + * DIG_FE_CNTL_STEREOSYNC_SELECT enum + */ + +typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT { +DIG_FE_STEREOSYNC_FROM_FMT0 = 0x00000000, +DIG_FE_STEREOSYNC_FROM_FMT1 = 0x00000001, +DIG_FE_STEREOSYNC_FROM_FMT2 = 0x00000002, +DIG_FE_STEREOSYNC_FROM_FMT3 = 0x00000003, +DIG_FE_STEREOSYNC_FROM_FMT4 = 0x00000004, +DIG_FE_STEREOSYNC_FROM_FMT5 = 0x00000005, +} DIG_FE_CNTL_STEREOSYNC_SELECT; + +/* + * DIG_FIFO_READ_CLOCK_SRC enum + */ + +typedef enum DIG_FIFO_READ_CLOCK_SRC { +DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0x00000000, +DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x00000001, +} DIG_FIFO_READ_CLOCK_SRC; + +/* + * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum + */ + +typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL { +DIG_OUTPUT_CRC_ON_LINK0 = 0x00000000, +DIG_OUTPUT_CRC_ON_LINK1 = 0x00000001, +} DIG_OUTPUT_CRC_CNTL_LINK_SEL; + +/* + * DIG_OUTPUT_CRC_DATA_SEL enum + */ + +typedef enum DIG_OUTPUT_CRC_DATA_SEL { +DIG_OUTPUT_CRC_FOR_FULLFRAME = 0x00000000, +DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 0x00000001, +DIG_OUTPUT_CRC_FOR_VBI = 0x00000002, +DIG_OUTPUT_CRC_FOR_AUDIO = 0x00000003, +} DIG_OUTPUT_CRC_DATA_SEL; + +/* + * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum + */ + +typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN { +DIG_IN_NORMAL_OPERATION = 0x00000000, +DIG_IN_DEBUG_MODE = 0x00000001, +} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN; + +/* + * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum + */ + +typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL { +DIG_10BIT_TEST_PATTERN = 0x00000000, +DIG_ALTERNATING_TEST_PATTERN = 0x00000001, +} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL; + +/* + * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum + */ + +typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN { +DIG_TEST_PATTERN_NORMAL = 0x00000000, +DIG_TEST_PATTERN_RANDOM = 0x00000001, +} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN; + +/* + * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum + */ + +typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET { +DIG_RANDOM_PATTERN_ENABLED = 0x00000000, +DIG_RANDOM_PATTERN_RESETED = 0x00000001, +} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET; + +/* + * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum + */ + +typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN { +DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0x00000000, +DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x00000001, +} DIG_TEST_PATTERN_EXTERNAL_RESET_EN; + +/* + * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum + */ + +typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT { +DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x00000000, +DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 0x00000001, +} DIG_RANDOM_PATTERN_SEED_RAN_PAT; + +/* + * DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL enum + */ + +typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL { +DIG_FIFO_USE_OVERWRITE_LEVEL = 0x00000000, +DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 0x00000001, +} DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL; + +/* + * DIG_FIFO_ERROR_ACK enum + */ + +typedef enum DIG_FIFO_ERROR_ACK { +DIG_FIFO_ERROR_ACK_INT = 0x00000000, +DIG_FIFO_ERROR_NOT_ACK = 0x00000001, +} DIG_FIFO_ERROR_ACK; + +/* + * DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE enum + */ + +typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE { +DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0x00000000, +DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 0x00000001, +} DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE; + +/* + * DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX enum + */ + +typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX { +DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0x00000000, +DIG_FIFO_FORCE_RECOMP_MINMAX = 0x00000001, +} DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX; + +/* + * AFMT_INTERRUPT_STATUS_CHG_MASK enum + */ + +typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK { +AFMT_INTERRUPT_DISABLE = 0x00000000, +AFMT_INTERRUPT_ENABLE = 0x00000001, +} AFMT_INTERRUPT_STATUS_CHG_MASK; + +/* + * HDMI_GC_AVMUTE enum + */ + +typedef enum HDMI_GC_AVMUTE { +HDMI_GC_AVMUTE_SET = 0x00000000, +HDMI_GC_AVMUTE_UNSET = 0x00000001, +} HDMI_GC_AVMUTE; + +/* + * HDMI_DEFAULT_PAHSE enum + */ + +typedef enum HDMI_DEFAULT_PAHSE { +HDMI_DEFAULT_PHASE_IS_0 = 0x00000000, +HDMI_DEFAULT_PHASE_IS_1 = 0x00000001, +} HDMI_DEFAULT_PAHSE; + +/* + * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum + */ + +typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD { +AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0x00000000, +AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 0x00000001, +} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD; + +/* + * AUDIO_LAYOUT_SELECT enum + */ + +typedef enum AUDIO_LAYOUT_SELECT { +AUDIO_LAYOUT_0 = 0x00000000, +AUDIO_LAYOUT_1 = 0x00000001, +} AUDIO_LAYOUT_SELECT; + +/* + * AFMT_AUDIO_CRC_CONTROL_CONT enum + */ + +typedef enum AFMT_AUDIO_CRC_CONTROL_CONT { +AFMT_AUDIO_CRC_ONESHOT = 0x00000000, +AFMT_AUDIO_CRC_AUTO_RESTART = 0x00000001, +} AFMT_AUDIO_CRC_CONTROL_CONT; + +/* + * AFMT_AUDIO_CRC_CONTROL_SOURCE enum + */ + +typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE { +AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0x00000000, +AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 0x00000001, +} AFMT_AUDIO_CRC_CONTROL_SOURCE; + +/* + * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum + */ + +typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL { +AFMT_AUDIO_CRC_CH0_SIG = 0x00000000, +AFMT_AUDIO_CRC_CH1_SIG = 0x00000001, +AFMT_AUDIO_CRC_CH2_SIG = 0x00000002, +AFMT_AUDIO_CRC_CH3_SIG = 0x00000003, +AFMT_AUDIO_CRC_CH4_SIG = 0x00000004, +AFMT_AUDIO_CRC_CH5_SIG = 0x00000005, +AFMT_AUDIO_CRC_CH6_SIG = 0x00000006, +AFMT_AUDIO_CRC_CH7_SIG = 0x00000007, +AFMT_AUDIO_CRC_RESERVED_8 = 0x00000008, +AFMT_AUDIO_CRC_RESERVED_9 = 0x00000009, +AFMT_AUDIO_CRC_RESERVED_10 = 0x0000000a, +AFMT_AUDIO_CRC_RESERVED_11 = 0x0000000b, +AFMT_AUDIO_CRC_RESERVED_12 = 0x0000000c, +AFMT_AUDIO_CRC_RESERVED_13 = 0x0000000d, +AFMT_AUDIO_CRC_RESERVED_14 = 0x0000000e, +AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 0x0000000f, +} AFMT_AUDIO_CRC_CONTROL_CH_SEL; + +/* + * AFMT_RAMP_CONTROL0_SIGN enum + */ + +typedef enum AFMT_RAMP_CONTROL0_SIGN { +AFMT_RAMP_SIGNED = 0x00000000, +AFMT_RAMP_UNSIGNED = 0x00000001, +} AFMT_RAMP_CONTROL0_SIGN; + +/* + * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum + */ + +typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND { +AFMT_AUDIO_PACKET_SENT_DISABLED = 0x00000000, +AFMT_AUDIO_PACKET_SENT_ENABLED = 0x00000001, +} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND; + +/* + * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum + */ + +typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS { +AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0x00000000, +AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 0x00000001, +} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS; + +/* + * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum + */ + +typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE { +AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0x00000000, +AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 0x00000001, +} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE; + +/* + * AFMT_AUDIO_SRC_CONTROL_SELECT enum + */ + +typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT { +AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0x00000000, +AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 0x00000001, +AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 0x00000002, +AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 0x00000003, +AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 0x00000004, +AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 0x00000005, +AFMT_AUDIO_SRC_RESERVED = 0x00000006, +} AFMT_AUDIO_SRC_CONTROL_SELECT; + +/* + * DIG_BE_CNTL_MODE enum + */ + +typedef enum DIG_BE_CNTL_MODE { +DIG_BE_DP_SST_MODE = 0x00000000, +DIG_BE_RESERVED1 = 0x00000001, +DIG_BE_TMDS_DVI_MODE = 0x00000002, +DIG_BE_TMDS_HDMI_MODE = 0x00000003, +DIG_BE_SDVO_RESERVED = 0x00000004, +DIG_BE_DP_MST_MODE = 0x00000005, +DIG_BE_RESERVED2 = 0x00000006, +DIG_BE_RESERVED3 = 0x00000007, +} DIG_BE_CNTL_MODE; + +/* + * DIG_BE_CNTL_HPD_SELECT enum + */ + +typedef enum DIG_BE_CNTL_HPD_SELECT { +DIG_BE_CNTL_HPD1 = 0x00000000, +DIG_BE_CNTL_HPD2 = 0x00000001, +DIG_BE_CNTL_HPD3 = 0x00000002, +DIG_BE_CNTL_HPD4 = 0x00000003, +DIG_BE_CNTL_HPD5 = 0x00000004, +DIG_BE_CNTL_HPD6 = 0x00000005, +} DIG_BE_CNTL_HPD_SELECT; + +/* + * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum + */ + +typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT { +LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0x00000000, +LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 0x00000001, +} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT; + +/* + * TMDS_SYNC_PHASE enum + */ + +typedef enum TMDS_SYNC_PHASE { +TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0x00000000, +TMDS_SYNC_PHASE_ON_FRAME_START = 0x00000001, +} TMDS_SYNC_PHASE; + +/* + * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum + */ + +typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL { +TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0x00000000, +TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 0x00000001, +} TMDS_DATA_SYNCHRONIZATION_DSINTSEL; + +/* + * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum + */ + +typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK { +TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0x00000000, +TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 0x00000001, +} TMDS_TRANSMITTER_ENABLE_HPD_MASK; + +/* + * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum + */ + +typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK { +TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0x00000000, +TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 0x00000001, +} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK; + +/* + * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum + */ + +typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK { +TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0x00000000, +TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 0x00000001, +} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK; + +/* + * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum + */ + +typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK { +TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0x00000000, +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 0x00000001, +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x00000002, +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 0x00000003, +} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK; + +/* + * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum + */ + +typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA { +TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0x00000000, +TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 0x00000001, +} TMDS_TRANSMITTER_CONTROL_IDSCKSELA; + +/* + * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum + */ + +typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB { +TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0x00000000, +TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 0x00000001, +} TMDS_TRANSMITTER_CONTROL_IDSCKSELB; + +/* + * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum + */ + +typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN { +TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0x00000000, +TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 0x00000001, +} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN; + +/* + * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum + */ + +typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK { +TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0x00000000, +TMDS_TRANSMITTER_PLL_RST_ON_HPD = 0x00000001, +} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK; + +/* + * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum + */ + +typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS { +TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0x00000000, +TMDS_TRANSMITTER_TMCLK_FROM_PADS = 0x00000001, +} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS; + +/* + * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum + */ + +typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS { +TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0x00000000, +TMDS_TRANSMITTER_TDCLK_FROM_PADS = 0x00000001, +} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS; + +/* + * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum + */ + +typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN { +TMDS_TRANSMITTER_PLLSEL_BY_HW = 0x00000000, +TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 0x00000001, +} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN; + +/* + * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum + */ + +typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA { +TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0x00000000, +TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 0x00000001, +} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA; + +/* + * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum + */ + +typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB { +TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0x00000000, +TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 0x00000001, +} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB; + +/* + * TMDS_REG_TEST_OUTPUTA_CNTLA enum + */ + +typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA { +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0x00000000, +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 0x00000001, +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 0x00000002, +TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 0x00000003, +} TMDS_REG_TEST_OUTPUTA_CNTLA; + +/* + * TMDS_REG_TEST_OUTPUTB_CNTLB enum + */ + +typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB { +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0x00000000, +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 0x00000001, +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 0x00000002, +TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 0x00000003, +} TMDS_REG_TEST_OUTPUTB_CNTLB; + +/******************************************************* + * DCP Enums + *******************************************************/ + +/* + * DCP_GRPH_ENABLE enum + */ + +typedef enum DCP_GRPH_ENABLE { +DCP_GRPH_ENABLE_FALSE = 0x00000000, +DCP_GRPH_ENABLE_TRUE = 0x00000001, +} DCP_GRPH_ENABLE; + +/* + * DCP_GRPH_KEYER_ALPHA_SEL enum + */ + +typedef enum DCP_GRPH_KEYER_ALPHA_SEL { +DCP_GRPH_KEYER_ALPHA_SEL_FALSE = 0x00000000, +DCP_GRPH_KEYER_ALPHA_SEL_TRUE = 0x00000001, +} DCP_GRPH_KEYER_ALPHA_SEL; + +/* + * DCP_GRPH_DEPTH enum + */ + +typedef enum DCP_GRPH_DEPTH { +DCP_GRPH_DEPTH_8BPP = 0x00000000, +DCP_GRPH_DEPTH_16BPP = 0x00000001, +DCP_GRPH_DEPTH_32BPP = 0x00000002, +DCP_GRPH_DEPTH_64BPP = 0x00000003, +} DCP_GRPH_DEPTH; + +/* + * DCP_GRPH_NUM_BANKS enum + */ + +typedef enum DCP_GRPH_NUM_BANKS { +DCP_GRPH_NUM_BANKS_1BANK = 0x00000000, +DCP_GRPH_NUM_BANKS_2BANK = 0x00000001, +DCP_GRPH_NUM_BANKS_4BANK = 0x00000002, +DCP_GRPH_NUM_BANKS_8BANK = 0x00000003, +DCP_GRPH_NUM_BANKS_16BANK = 0x00000004, +} DCP_GRPH_NUM_BANKS; + +/* + * DCP_GRPH_NUM_PIPES enum + */ + +typedef enum DCP_GRPH_NUM_PIPES { +DCP_GRPH_NUM_PIPES_1PIPE = 0x00000000, +DCP_GRPH_NUM_PIPES_2PIPE = 0x00000001, +DCP_GRPH_NUM_PIPES_4PIPE = 0x00000002, +DCP_GRPH_NUM_PIPES_8PIPE = 0x00000003, +} DCP_GRPH_NUM_PIPES; + +/* + * DCP_GRPH_FORMAT enum + */ + +typedef enum DCP_GRPH_FORMAT { +DCP_GRPH_FORMAT_8BPP = 0x00000000, +DCP_GRPH_FORMAT_16BPP = 0x00000001, +DCP_GRPH_FORMAT_32BPP = 0x00000002, +DCP_GRPH_FORMAT_64BPP = 0x00000003, +} DCP_GRPH_FORMAT; + +/* + * DCP_GRPH_ADDRESS_TRANSLATION_ENABLE enum + */ + +typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE { +DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE = 0x00000000, +DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE = 0x00000001, +} DCP_GRPH_ADDRESS_TRANSLATION_ENABLE; + +/* + * DCP_GRPH_SW_MODE enum + */ + +typedef enum DCP_GRPH_SW_MODE { +DCP_GRPH_SW_MODE_0 = 0x00000000, +DCP_GRPH_SW_MODE_2 = 0x00000002, +DCP_GRPH_SW_MODE_3 = 0x00000003, +DCP_GRPH_SW_MODE_22 = 0x00000016, +DCP_GRPH_SW_MODE_23 = 0x00000017, +DCP_GRPH_SW_MODE_26 = 0x0000001a, +DCP_GRPH_SW_MODE_27 = 0x0000001b, +DCP_GRPH_SW_MODE_30 = 0x0000001e, +DCP_GRPH_SW_MODE_31 = 0x0000001f, +} DCP_GRPH_SW_MODE; + +/* + * DCP_GRPH_COLOR_EXPANSION_MODE enum + */ + +typedef enum DCP_GRPH_COLOR_EXPANSION_MODE { +DCP_GRPH_COLOR_EXPANSION_MODE_DEXP = 0x00000000, +DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP = 0x00000001, +} DCP_GRPH_COLOR_EXPANSION_MODE; + +/* + * DCP_GRPH_LUT_10BIT_BYPASS_EN enum + */ + +typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN { +DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE = 0x00000000, +DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE = 0x00000001, +} DCP_GRPH_LUT_10BIT_BYPASS_EN; + +/* + * DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN enum + */ + +typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN { +DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE = 0x00000000, +DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE = 0x00000001, +} DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN; + +/* + * DCP_GRPH_ENDIAN_SWAP enum + */ + +typedef enum DCP_GRPH_ENDIAN_SWAP { +DCP_GRPH_ENDIAN_SWAP_NONE = 0x00000000, +DCP_GRPH_ENDIAN_SWAP_8IN16 = 0x00000001, +DCP_GRPH_ENDIAN_SWAP_8IN32 = 0x00000002, +DCP_GRPH_ENDIAN_SWAP_8IN64 = 0x00000003, +} DCP_GRPH_ENDIAN_SWAP; + +/* + * DCP_GRPH_RED_CROSSBAR enum + */ + +typedef enum DCP_GRPH_RED_CROSSBAR { +DCP_GRPH_RED_CROSSBAR_FROM_R = 0x00000000, +DCP_GRPH_RED_CROSSBAR_FROM_G = 0x00000001, +DCP_GRPH_RED_CROSSBAR_FROM_B = 0x00000002, +DCP_GRPH_RED_CROSSBAR_FROM_A = 0x00000003, +} DCP_GRPH_RED_CROSSBAR; + +/* + * DCP_GRPH_GREEN_CROSSBAR enum + */ + +typedef enum DCP_GRPH_GREEN_CROSSBAR { +DCP_GRPH_GREEN_CROSSBAR_FROM_G = 0x00000000, +DCP_GRPH_GREEN_CROSSBAR_FROM_B = 0x00000001, +DCP_GRPH_GREEN_CROSSBAR_FROM_A = 0x00000002, +DCP_GRPH_GREEN_CROSSBAR_FROM_R = 0x00000003, +} DCP_GRPH_GREEN_CROSSBAR; + +/* + * DCP_GRPH_BLUE_CROSSBAR enum + */ + +typedef enum DCP_GRPH_BLUE_CROSSBAR { +DCP_GRPH_BLUE_CROSSBAR_FROM_B = 0x00000000, +DCP_GRPH_BLUE_CROSSBAR_FROM_A = 0x00000001, +DCP_GRPH_BLUE_CROSSBAR_FROM_R = 0x00000002, +DCP_GRPH_BLUE_CROSSBAR_FROM_G = 0x00000003, +} DCP_GRPH_BLUE_CROSSBAR; + +/* + * DCP_GRPH_ALPHA_CROSSBAR enum + */ + +typedef enum DCP_GRPH_ALPHA_CROSSBAR { +DCP_GRPH_ALPHA_CROSSBAR_FROM_A = 0x00000000, +DCP_GRPH_ALPHA_CROSSBAR_FROM_R = 0x00000001, +DCP_GRPH_ALPHA_CROSSBAR_FROM_G = 0x00000002, +DCP_GRPH_ALPHA_CROSSBAR_FROM_B = 0x00000003, +} DCP_GRPH_ALPHA_CROSSBAR; + +/* + * DCP_GRPH_PRIMARY_DFQ_ENABLE enum + */ + +typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE { +DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE = 0x00000000, +DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE = 0x00000001, +} DCP_GRPH_PRIMARY_DFQ_ENABLE; + +/* + * DCP_GRPH_SECONDARY_DFQ_ENABLE enum + */ + +typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE { +DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE = 0x00000000, +DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE = 0x00000001, +} DCP_GRPH_SECONDARY_DFQ_ENABLE; + +/* + * DCP_GRPH_INPUT_GAMMA_MODE enum + */ + +typedef enum DCP_GRPH_INPUT_GAMMA_MODE { +DCP_GRPH_INPUT_GAMMA_MODE_LUT = 0x00000000, +DCP_GRPH_INPUT_GAMMA_MODE_BYPASS = 0x00000001, +} DCP_GRPH_INPUT_GAMMA_MODE; + +/* + * DCP_GRPH_MODE_UPDATE_PENDING enum + */ + +typedef enum DCP_GRPH_MODE_UPDATE_PENDING { +DCP_GRPH_MODE_UPDATE_PENDING_FALSE = 0x00000000, +DCP_GRPH_MODE_UPDATE_PENDING_TRUE = 0x00000001, +} DCP_GRPH_MODE_UPDATE_PENDING; + +/* + * DCP_GRPH_MODE_UPDATE_TAKEN enum + */ + +typedef enum DCP_GRPH_MODE_UPDATE_TAKEN { +DCP_GRPH_MODE_UPDATE_TAKEN_FALSE = 0x00000000, +DCP_GRPH_MODE_UPDATE_TAKEN_TRUE = 0x00000001, +} DCP_GRPH_MODE_UPDATE_TAKEN; + +/* + * DCP_GRPH_SURFACE_UPDATE_PENDING enum + */ + +typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING { +DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE = 0x00000000, +DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE = 0x00000001, +} DCP_GRPH_SURFACE_UPDATE_PENDING; + +/* + * DCP_GRPH_SURFACE_UPDATE_TAKEN enum + */ + +typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN { +DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE = 0x00000000, +DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE = 0x00000001, +} DCP_GRPH_SURFACE_UPDATE_TAKEN; + +/* + * DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE enum + */ + +typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE { +DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE = 0x00000000, +DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE = 0x00000001, +} DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE; + +/* + * DCP_GRPH_UPDATE_LOCK enum + */ + +typedef enum DCP_GRPH_UPDATE_LOCK { +DCP_GRPH_UPDATE_LOCK_FALSE = 0x00000000, +DCP_GRPH_UPDATE_LOCK_TRUE = 0x00000001, +} DCP_GRPH_UPDATE_LOCK; + +/* + * DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK enum + */ + +typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK { +DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE = 0x00000000, +DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE = 0x00000001, +} DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK; + +/* + * DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE enum + */ + +typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE { +DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x00000000, +DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x00000001, +} DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE; + +/* + * DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE enum + */ + +typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE { +DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x00000000, +DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x00000001, +} DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE; + +/* + * DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN enum + */ + +typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN { +DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE = 0x00000000, +DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE = 0x00000001, +} DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN; + +/* + * DCP_GRPH_XDMA_SUPER_AA_EN enum + */ + +typedef enum DCP_GRPH_XDMA_SUPER_AA_EN { +DCP_GRPH_XDMA_SUPER_AA_EN_FALSE = 0x00000000, +DCP_GRPH_XDMA_SUPER_AA_EN_TRUE = 0x00000001, +} DCP_GRPH_XDMA_SUPER_AA_EN; + +/* + * DCP_GRPH_DFQ_RESET enum + */ + +typedef enum DCP_GRPH_DFQ_RESET { +DCP_GRPH_DFQ_RESET_FALSE = 0x00000000, +DCP_GRPH_DFQ_RESET_TRUE = 0x00000001, +} DCP_GRPH_DFQ_RESET; + +/* + * DCP_GRPH_DFQ_SIZE enum + */ + +typedef enum DCP_GRPH_DFQ_SIZE { +DCP_GRPH_DFQ_SIZE_DEEP1 = 0x00000000, +DCP_GRPH_DFQ_SIZE_DEEP2 = 0x00000001, +DCP_GRPH_DFQ_SIZE_DEEP3 = 0x00000002, +DCP_GRPH_DFQ_SIZE_DEEP4 = 0x00000003, +DCP_GRPH_DFQ_SIZE_DEEP5 = 0x00000004, +DCP_GRPH_DFQ_SIZE_DEEP6 = 0x00000005, +DCP_GRPH_DFQ_SIZE_DEEP7 = 0x00000006, +DCP_GRPH_DFQ_SIZE_DEEP8 = 0x00000007, +} DCP_GRPH_DFQ_SIZE; + +/* + * DCP_GRPH_DFQ_MIN_FREE_ENTRIES enum + */ + +typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES { +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1 = 0x00000000, +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2 = 0x00000001, +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3 = 0x00000002, +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4 = 0x00000003, +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5 = 0x00000004, +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6 = 0x00000005, +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7 = 0x00000006, +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8 = 0x00000007, +} DCP_GRPH_DFQ_MIN_FREE_ENTRIES; + +/* + * DCP_GRPH_DFQ_RESET_ACK enum + */ + +typedef enum DCP_GRPH_DFQ_RESET_ACK { +DCP_GRPH_DFQ_RESET_ACK_FALSE = 0x00000000, +DCP_GRPH_DFQ_RESET_ACK_TRUE = 0x00000001, +} DCP_GRPH_DFQ_RESET_ACK; + +/* + * DCP_GRPH_PFLIP_INT_CLEAR enum + */ + +typedef enum DCP_GRPH_PFLIP_INT_CLEAR { +DCP_GRPH_PFLIP_INT_CLEAR_FALSE = 0x00000000, +DCP_GRPH_PFLIP_INT_CLEAR_TRUE = 0x00000001, +} DCP_GRPH_PFLIP_INT_CLEAR; + +/* + * DCP_GRPH_PFLIP_INT_MASK enum + */ + +typedef enum DCP_GRPH_PFLIP_INT_MASK { +DCP_GRPH_PFLIP_INT_MASK_FALSE = 0x00000000, +DCP_GRPH_PFLIP_INT_MASK_TRUE = 0x00000001, +} DCP_GRPH_PFLIP_INT_MASK; + +/* + * DCP_GRPH_PFLIP_INT_TYPE enum + */ + +typedef enum DCP_GRPH_PFLIP_INT_TYPE { +DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL = 0x00000000, +DCP_GRPH_PFLIP_INT_TYPE_PULSE = 0x00000001, +} DCP_GRPH_PFLIP_INT_TYPE; + +/* + * DCP_GRPH_PRESCALE_SELECT enum + */ + +typedef enum DCP_GRPH_PRESCALE_SELECT { +DCP_GRPH_PRESCALE_SELECT_FIXED = 0x00000000, +DCP_GRPH_PRESCALE_SELECT_FLOATING = 0x00000001, +} DCP_GRPH_PRESCALE_SELECT; + +/* + * DCP_GRPH_PRESCALE_R_SIGN enum + */ + +typedef enum DCP_GRPH_PRESCALE_R_SIGN { +DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED = 0x00000000, +DCP_GRPH_PRESCALE_R_SIGN_SIGNED = 0x00000001, +} DCP_GRPH_PRESCALE_R_SIGN; + +/* + * DCP_GRPH_PRESCALE_G_SIGN enum + */ + +typedef enum DCP_GRPH_PRESCALE_G_SIGN { +DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED = 0x00000000, +DCP_GRPH_PRESCALE_G_SIGN_SIGNED = 0x00000001, +} DCP_GRPH_PRESCALE_G_SIGN; + +/* + * DCP_GRPH_PRESCALE_B_SIGN enum + */ + +typedef enum DCP_GRPH_PRESCALE_B_SIGN { +DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED = 0x00000000, +DCP_GRPH_PRESCALE_B_SIGN_SIGNED = 0x00000001, +} DCP_GRPH_PRESCALE_B_SIGN; + +/* + * DCP_GRPH_PRESCALE_BYPASS enum + */ + +typedef enum DCP_GRPH_PRESCALE_BYPASS { +DCP_GRPH_PRESCALE_BYPASS_FALSE = 0x00000000, +DCP_GRPH_PRESCALE_BYPASS_TRUE = 0x00000001, +} DCP_GRPH_PRESCALE_BYPASS; + +/* + * DCP_INPUT_CSC_GRPH_MODE enum + */ + +typedef enum DCP_INPUT_CSC_GRPH_MODE { +DCP_INPUT_CSC_GRPH_MODE_BYPASS = 0x00000000, +DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF = 0x00000001, +DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF = 0x00000002, +DCP_INPUT_CSC_GRPH_MODE_RESERVED = 0x00000003, +} DCP_INPUT_CSC_GRPH_MODE; + +/* + * DCP_OUTPUT_CSC_GRPH_MODE enum + */ + +typedef enum DCP_OUTPUT_CSC_GRPH_MODE { +DCP_OUTPUT_CSC_GRPH_MODE_BYPASS = 0x00000000, +DCP_OUTPUT_CSC_GRPH_MODE_RGB = 0x00000001, +DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601 = 0x00000002, +DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709 = 0x00000003, +DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF = 0x00000004, +DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF = 0x00000005, +DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0 = 0x00000006, +DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1 = 0x00000007, +} DCP_OUTPUT_CSC_GRPH_MODE; + +/* + * DCP_DENORM_MODE enum + */ + +typedef enum DCP_DENORM_MODE { +DCP_DENORM_MODE_UNITY = 0x00000000, +DCP_DENORM_MODE_6BIT = 0x00000001, +DCP_DENORM_MODE_8BIT = 0x00000002, +DCP_DENORM_MODE_10BIT = 0x00000003, +DCP_DENORM_MODE_11BIT = 0x00000004, +DCP_DENORM_MODE_12BIT = 0x00000005, +DCP_DENORM_MODE_RESERVED0 = 0x00000006, +DCP_DENORM_MODE_RESERVED1 = 0x00000007, +} DCP_DENORM_MODE; + +/* + * DCP_DENORM_14BIT_OUT enum + */ + +typedef enum DCP_DENORM_14BIT_OUT { +DCP_DENORM_14BIT_OUT_FALSE = 0x00000000, +DCP_DENORM_14BIT_OUT_TRUE = 0x00000001, +} DCP_DENORM_14BIT_OUT; + +/* + * DCP_OUT_ROUND_TRUNC_MODE enum + */ + +typedef enum DCP_OUT_ROUND_TRUNC_MODE { +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12 = 0x00000000, +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11 = 0x00000001, +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10 = 0x00000002, +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9 = 0x00000003, +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8 = 0x00000004, +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED = 0x00000005, +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14 = 0x00000006, +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13 = 0x00000007, +DCP_OUT_ROUND_TRUNC_MODE_ROUND_12 = 0x00000008, +DCP_OUT_ROUND_TRUNC_MODE_ROUND_11 = 0x00000009, +DCP_OUT_ROUND_TRUNC_MODE_ROUND_10 = 0x0000000a, +DCP_OUT_ROUND_TRUNC_MODE_ROUND_9 = 0x0000000b, +DCP_OUT_ROUND_TRUNC_MODE_ROUND_8 = 0x0000000c, +DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED = 0x0000000d, +DCP_OUT_ROUND_TRUNC_MODE_ROUND_14 = 0x0000000e, +DCP_OUT_ROUND_TRUNC_MODE_ROUND_13 = 0x0000000f, +} DCP_OUT_ROUND_TRUNC_MODE; + +/* + * DCP_KEY_MODE enum + */ + +typedef enum DCP_KEY_MODE { +DCP_KEY_MODE_ALPHA0 = 0x00000000, +DCP_KEY_MODE_ALPHA1 = 0x00000001, +DCP_KEY_MODE_IN_RANGE_ALPHA1 = 0x00000002, +DCP_KEY_MODE_IN_RANGE_ALPHA0 = 0x00000003, +} DCP_KEY_MODE; + +/* + * DCP_GRPH_DEGAMMA_MODE enum + */ + +typedef enum DCP_GRPH_DEGAMMA_MODE { +DCP_GRPH_DEGAMMA_MODE_BYPASS = 0x00000000, +DCP_GRPH_DEGAMMA_MODE_ROMA = 0x00000001, +DCP_GRPH_DEGAMMA_MODE_ROMB = 0x00000002, +DCP_GRPH_DEGAMMA_MODE_RESERVED = 0x00000003, +} DCP_GRPH_DEGAMMA_MODE; + +/* + * DCP_CURSOR_DEGAMMA_MODE enum + */ + +typedef enum DCP_CURSOR_DEGAMMA_MODE { +DCP_CURSOR_DEGAMMA_MODE_BYPASS = 0x00000000, +DCP_CURSOR_DEGAMMA_MODE_ROMA = 0x00000001, +DCP_CURSOR_DEGAMMA_MODE_ROMB = 0x00000002, +DCP_CURSOR_DEGAMMA_MODE_RESERVED = 0x00000003, +} DCP_CURSOR_DEGAMMA_MODE; + +/* + * DCP_GRPH_GAMUT_REMAP_MODE enum + */ + +typedef enum DCP_GRPH_GAMUT_REMAP_MODE { +DCP_GRPH_GAMUT_REMAP_MODE_BYPASS = 0x00000000, +DCP_GRPH_GAMUT_REMAP_MODE_ROMA = 0x00000001, +DCP_GRPH_GAMUT_REMAP_MODE_ROMB = 0x00000002, +DCP_GRPH_GAMUT_REMAP_MODE_RESERVED = 0x00000003, +} DCP_GRPH_GAMUT_REMAP_MODE; + +/* + * DCP_SPATIAL_DITHER_EN enum + */ + +typedef enum DCP_SPATIAL_DITHER_EN { +DCP_SPATIAL_DITHER_EN_FALSE = 0x00000000, +DCP_SPATIAL_DITHER_EN_TRUE = 0x00000001, +} DCP_SPATIAL_DITHER_EN; + +/* + * DCP_SPATIAL_DITHER_MODE enum + */ + +typedef enum DCP_SPATIAL_DITHER_MODE { +DCP_SPATIAL_DITHER_MODE_BYPASS = 0x00000000, +DCP_SPATIAL_DITHER_MODE_ROMA = 0x00000001, +DCP_SPATIAL_DITHER_MODE_ROMB = 0x00000002, +DCP_SPATIAL_DITHER_MODE_RESERVED = 0x00000003, +} DCP_SPATIAL_DITHER_MODE; + +/* + * DCP_SPATIAL_DITHER_DEPTH enum + */ + +typedef enum DCP_SPATIAL_DITHER_DEPTH { +DCP_SPATIAL_DITHER_DEPTH_30BPP = 0x00000000, +DCP_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001, +DCP_SPATIAL_DITHER_DEPTH_36BPP = 0x00000002, +DCP_SPATIAL_DITHER_DEPTH_UNDEFINED = 0x00000003, +} DCP_SPATIAL_DITHER_DEPTH; + +/* + * DCP_FRAME_RANDOM_ENABLE enum + */ + +typedef enum DCP_FRAME_RANDOM_ENABLE { +DCP_FRAME_RANDOM_ENABLE_FALSE = 0x00000000, +DCP_FRAME_RANDOM_ENABLE_TRUE = 0x00000001, +} DCP_FRAME_RANDOM_ENABLE; + +/* + * DCP_RGB_RANDOM_ENABLE enum + */ + +typedef enum DCP_RGB_RANDOM_ENABLE { +DCP_RGB_RANDOM_ENABLE_FALSE = 0x00000000, +DCP_RGB_RANDOM_ENABLE_TRUE = 0x00000001, +} DCP_RGB_RANDOM_ENABLE; + +/* + * DCP_HIGHPASS_RANDOM_ENABLE enum + */ + +typedef enum DCP_HIGHPASS_RANDOM_ENABLE { +DCP_HIGHPASS_RANDOM_ENABLE_FALSE = 0x00000000, +DCP_HIGHPASS_RANDOM_ENABLE_TRUE = 0x00000001, +} DCP_HIGHPASS_RANDOM_ENABLE; + +/* + * DCP_CURSOR_EN enum + */ + +typedef enum DCP_CURSOR_EN { +DCP_CURSOR_EN_FALSE = 0x00000000, +DCP_CURSOR_EN_TRUE = 0x00000001, +} DCP_CURSOR_EN; + +/* + * DCP_CUR_INV_TRANS_CLAMP enum + */ + +typedef enum DCP_CUR_INV_TRANS_CLAMP { +DCP_CUR_INV_TRANS_CLAMP_FALSE = 0x00000000, +DCP_CUR_INV_TRANS_CLAMP_TRUE = 0x00000001, +} DCP_CUR_INV_TRANS_CLAMP; + +/* + * DCP_CURSOR_MODE enum + */ + +typedef enum DCP_CURSOR_MODE { +DCP_CURSOR_MODE_MONO_2BPP = 0x00000000, +DCP_CURSOR_MODE_24BPP_1BIT = 0x00000001, +DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI = 0x00000002, +DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI = 0x00000003, +} DCP_CURSOR_MODE; + +/* + * DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM enum + */ + +typedef enum DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM { +DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE = 0x00000000, +DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO = 0x00000001, +} DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM; + +/* + * DCP_CURSOR_2X_MAGNIFY enum + */ + +typedef enum DCP_CURSOR_2X_MAGNIFY { +DCP_CURSOR_2X_MAGNIFY_FALSE = 0x00000000, +DCP_CURSOR_2X_MAGNIFY_TRUE = 0x00000001, +} DCP_CURSOR_2X_MAGNIFY; + +/* + * DCP_CURSOR_FORCE_MC_ON enum + */ + +typedef enum DCP_CURSOR_FORCE_MC_ON { +DCP_CURSOR_FORCE_MC_ON_FALSE = 0x00000000, +DCP_CURSOR_FORCE_MC_ON_TRUE = 0x00000001, +} DCP_CURSOR_FORCE_MC_ON; + +/* + * DCP_CURSOR_URGENT_CONTROL enum + */ + +typedef enum DCP_CURSOR_URGENT_CONTROL { +DCP_CURSOR_URGENT_CONTROL_MODE_0 = 0x00000000, +DCP_CURSOR_URGENT_CONTROL_MODE_1 = 0x00000001, +DCP_CURSOR_URGENT_CONTROL_MODE_2 = 0x00000002, +DCP_CURSOR_URGENT_CONTROL_MODE_3 = 0x00000003, +DCP_CURSOR_URGENT_CONTROL_MODE_4 = 0x00000004, +} DCP_CURSOR_URGENT_CONTROL; + +/* + * DCP_CURSOR_UPDATE_PENDING enum + */ + +typedef enum DCP_CURSOR_UPDATE_PENDING { +DCP_CURSOR_UPDATE_PENDING_FALSE = 0x00000000, +DCP_CURSOR_UPDATE_PENDING_TRUE = 0x00000001, +} DCP_CURSOR_UPDATE_PENDING; + +/* + * DCP_CURSOR_UPDATE_TAKEN enum + */ + +typedef enum DCP_CURSOR_UPDATE_TAKEN { +DCP_CURSOR_UPDATE_TAKEN_FALSE = 0x00000000, +DCP_CURSOR_UPDATE_TAKEN_TRUE = 0x00000001, +} DCP_CURSOR_UPDATE_TAKEN; + +/* + * DCP_CURSOR_UPDATE_LOCK enum + */ + +typedef enum DCP_CURSOR_UPDATE_LOCK { +DCP_CURSOR_UPDATE_LOCK_FALSE = 0x00000000, +DCP_CURSOR_UPDATE_LOCK_TRUE = 0x00000001, +} DCP_CURSOR_UPDATE_LOCK; + +/* + * DCP_CURSOR_DISABLE_MULTIPLE_UPDATE enum + */ + +typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE { +DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE = 0x00000000, +DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE = 0x00000001, +} DCP_CURSOR_DISABLE_MULTIPLE_UPDATE; + +/* + * DCP_CURSOR_UPDATE_STEREO_MODE enum + */ + +typedef enum DCP_CURSOR_UPDATE_STEREO_MODE { +DCP_CURSOR_UPDATE_STEREO_MODE_BOTH = 0x00000000, +DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY = 0x00000001, +DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED = 0x00000002, +DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY = 0x00000003, +} DCP_CURSOR_UPDATE_STEREO_MODE; + +/* + * DCP_CUR2_INV_TRANS_CLAMP enum + */ + +typedef enum DCP_CUR2_INV_TRANS_CLAMP { +DCP_CUR2_INV_TRANS_CLAMP_FALSE = 0x00000000, +DCP_CUR2_INV_TRANS_CLAMP_TRUE = 0x00000001, +} DCP_CUR2_INV_TRANS_CLAMP; + +/* + * DCP_CUR_REQUEST_FILTER_DIS enum + */ + +typedef enum DCP_CUR_REQUEST_FILTER_DIS { +DCP_CUR_REQUEST_FILTER_DIS_FALSE = 0x00000000, +DCP_CUR_REQUEST_FILTER_DIS_TRUE = 0x00000001, +} DCP_CUR_REQUEST_FILTER_DIS; + +/* + * DCP_CURSOR_STEREO_EN enum + */ + +typedef enum DCP_CURSOR_STEREO_EN { +DCP_CURSOR_STEREO_EN_FALSE = 0x00000000, +DCP_CURSOR_STEREO_EN_TRUE = 0x00000001, +} DCP_CURSOR_STEREO_EN; + +/* + * DCP_CURSOR_STEREO_OFFSET_YNX enum + */ + +typedef enum DCP_CURSOR_STEREO_OFFSET_YNX { +DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION = 0x00000000, +DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION = 0x00000001, +} DCP_CURSOR_STEREO_OFFSET_YNX; + +/* + * DCP_DC_LUT_RW_MODE enum + */ + +typedef enum DCP_DC_LUT_RW_MODE { +DCP_DC_LUT_RW_MODE_256_ENTRY = 0x00000000, +DCP_DC_LUT_RW_MODE_PWL = 0x00000001, +} DCP_DC_LUT_RW_MODE; + +/* + * DCP_DC_LUT_VGA_ACCESS_ENABLE enum + */ + +typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE { +DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE = 0x00000000, +DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE = 0x00000001, +} DCP_DC_LUT_VGA_ACCESS_ENABLE; + +/* + * DCP_DC_LUT_AUTOFILL enum + */ + +typedef enum DCP_DC_LUT_AUTOFILL { +DCP_DC_LUT_AUTOFILL_FALSE = 0x00000000, +DCP_DC_LUT_AUTOFILL_TRUE = 0x00000001, +} DCP_DC_LUT_AUTOFILL; + +/* + * DCP_DC_LUT_AUTOFILL_DONE enum + */ + +typedef enum DCP_DC_LUT_AUTOFILL_DONE { +DCP_DC_LUT_AUTOFILL_DONE_FALSE = 0x00000000, +DCP_DC_LUT_AUTOFILL_DONE_TRUE = 0x00000001, +} DCP_DC_LUT_AUTOFILL_DONE; + +/* + * DCP_DC_LUT_INC_B enum + */ + +typedef enum DCP_DC_LUT_INC_B { +DCP_DC_LUT_INC_B_NA = 0x00000000, +DCP_DC_LUT_INC_B_2 = 0x00000001, +DCP_DC_LUT_INC_B_4 = 0x00000002, +DCP_DC_LUT_INC_B_8 = 0x00000003, +DCP_DC_LUT_INC_B_16 = 0x00000004, +DCP_DC_LUT_INC_B_32 = 0x00000005, +DCP_DC_LUT_INC_B_64 = 0x00000006, +DCP_DC_LUT_INC_B_128 = 0x00000007, +DCP_DC_LUT_INC_B_256 = 0x00000008, +DCP_DC_LUT_INC_B_512 = 0x00000009, +} DCP_DC_LUT_INC_B; + +/* + * DCP_DC_LUT_DATA_B_SIGNED_EN enum + */ + +typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN { +DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE = 0x00000000, +DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE = 0x00000001, +} DCP_DC_LUT_DATA_B_SIGNED_EN; + +/* + * DCP_DC_LUT_DATA_B_FLOAT_POINT_EN enum + */ + +typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN { +DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE = 0x00000000, +DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE = 0x00000001, +} DCP_DC_LUT_DATA_B_FLOAT_POINT_EN; + +/* + * DCP_DC_LUT_DATA_B_FORMAT enum + */ + +typedef enum DCP_DC_LUT_DATA_B_FORMAT { +DCP_DC_LUT_DATA_B_FORMAT_U0P10 = 0x00000000, +DCP_DC_LUT_DATA_B_FORMAT_S1P10 = 0x00000001, +DCP_DC_LUT_DATA_B_FORMAT_U1P11 = 0x00000002, +DCP_DC_LUT_DATA_B_FORMAT_U0P12 = 0x00000003, +} DCP_DC_LUT_DATA_B_FORMAT; + +/* + * DCP_DC_LUT_INC_G enum + */ + +typedef enum DCP_DC_LUT_INC_G { +DCP_DC_LUT_INC_G_NA = 0x00000000, +DCP_DC_LUT_INC_G_2 = 0x00000001, +DCP_DC_LUT_INC_G_4 = 0x00000002, +DCP_DC_LUT_INC_G_8 = 0x00000003, +DCP_DC_LUT_INC_G_16 = 0x00000004, +DCP_DC_LUT_INC_G_32 = 0x00000005, +DCP_DC_LUT_INC_G_64 = 0x00000006, +DCP_DC_LUT_INC_G_128 = 0x00000007, +DCP_DC_LUT_INC_G_256 = 0x00000008, +DCP_DC_LUT_INC_G_512 = 0x00000009, +} DCP_DC_LUT_INC_G; + +/* + * DCP_DC_LUT_DATA_G_SIGNED_EN enum + */ + +typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN { +DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE = 0x00000000, +DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE = 0x00000001, +} DCP_DC_LUT_DATA_G_SIGNED_EN; + +/* + * DCP_DC_LUT_DATA_G_FLOAT_POINT_EN enum + */ + +typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN { +DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE = 0x00000000, +DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE = 0x00000001, +} DCP_DC_LUT_DATA_G_FLOAT_POINT_EN; + +/* + * DCP_DC_LUT_DATA_G_FORMAT enum + */ + +typedef enum DCP_DC_LUT_DATA_G_FORMAT { +DCP_DC_LUT_DATA_G_FORMAT_U0P10 = 0x00000000, +DCP_DC_LUT_DATA_G_FORMAT_S1P10 = 0x00000001, +DCP_DC_LUT_DATA_G_FORMAT_U1P11 = 0x00000002, +DCP_DC_LUT_DATA_G_FORMAT_U0P12 = 0x00000003, +} DCP_DC_LUT_DATA_G_FORMAT; + +/* + * DCP_DC_LUT_INC_R enum + */ + +typedef enum DCP_DC_LUT_INC_R { +DCP_DC_LUT_INC_R_NA = 0x00000000, +DCP_DC_LUT_INC_R_2 = 0x00000001, +DCP_DC_LUT_INC_R_4 = 0x00000002, +DCP_DC_LUT_INC_R_8 = 0x00000003, +DCP_DC_LUT_INC_R_16 = 0x00000004, +DCP_DC_LUT_INC_R_32 = 0x00000005, +DCP_DC_LUT_INC_R_64 = 0x00000006, +DCP_DC_LUT_INC_R_128 = 0x00000007, +DCP_DC_LUT_INC_R_256 = 0x00000008, +DCP_DC_LUT_INC_R_512 = 0x00000009, +} DCP_DC_LUT_INC_R; + +/* + * DCP_DC_LUT_DATA_R_SIGNED_EN enum + */ + +typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN { +DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE = 0x00000000, +DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE = 0x00000001, +} DCP_DC_LUT_DATA_R_SIGNED_EN; + +/* + * DCP_DC_LUT_DATA_R_FLOAT_POINT_EN enum + */ + +typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN { +DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE = 0x00000000, +DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE = 0x00000001, +} DCP_DC_LUT_DATA_R_FLOAT_POINT_EN; + +/* + * DCP_DC_LUT_DATA_R_FORMAT enum + */ + +typedef enum DCP_DC_LUT_DATA_R_FORMAT { +DCP_DC_LUT_DATA_R_FORMAT_U0P10 = 0x00000000, +DCP_DC_LUT_DATA_R_FORMAT_S1P10 = 0x00000001, +DCP_DC_LUT_DATA_R_FORMAT_U1P11 = 0x00000002, +DCP_DC_LUT_DATA_R_FORMAT_U0P12 = 0x00000003, +} DCP_DC_LUT_DATA_R_FORMAT; + +/* + * DCP_CRC_ENABLE enum + */ + +typedef enum DCP_CRC_ENABLE { +DCP_CRC_ENABLE_FALSE = 0x00000000, +DCP_CRC_ENABLE_TRUE = 0x00000001, +} DCP_CRC_ENABLE; + +/* + * DCP_CRC_SOURCE_SEL enum + */ + +typedef enum DCP_CRC_SOURCE_SEL { +DCP_CRC_SOURCE_SEL_OUTPUT_PIX = 0x00000000, +DCP_CRC_SOURCE_SEL_INPUT_L32 = 0x00000001, +DCP_CRC_SOURCE_SEL_INPUT_H32 = 0x00000002, +DCP_CRC_SOURCE_SEL_OUTPUT_CNTL = 0x00000004, +} DCP_CRC_SOURCE_SEL; + +/* + * DCP_CRC_LINE_SEL enum + */ + +typedef enum DCP_CRC_LINE_SEL { +DCP_CRC_LINE_SEL_RESERVED = 0x00000000, +DCP_CRC_LINE_SEL_EVEN = 0x00000001, +DCP_CRC_LINE_SEL_ODD = 0x00000002, +DCP_CRC_LINE_SEL_BOTH = 0x00000003, +} DCP_CRC_LINE_SEL; + +/* + * DCP_GRPH_FLIP_RATE enum + */ + +typedef enum DCP_GRPH_FLIP_RATE { +DCP_GRPH_FLIP_RATE_1FRAME = 0x00000000, +DCP_GRPH_FLIP_RATE_2FRAME = 0x00000001, +DCP_GRPH_FLIP_RATE_3FRAME = 0x00000002, +DCP_GRPH_FLIP_RATE_4FRAME = 0x00000003, +DCP_GRPH_FLIP_RATE_5FRAME = 0x00000004, +DCP_GRPH_FLIP_RATE_6FRAME = 0x00000005, +DCP_GRPH_FLIP_RATE_7FRAME = 0x00000006, +DCP_GRPH_FLIP_RATE_8FRAME = 0x00000007, +} DCP_GRPH_FLIP_RATE; + +/* + * DCP_GRPH_FLIP_RATE_ENABLE enum + */ + +typedef enum DCP_GRPH_FLIP_RATE_ENABLE { +DCP_GRPH_FLIP_RATE_ENABLE_FALSE = 0x00000000, +DCP_GRPH_FLIP_RATE_ENABLE_TRUE = 0x00000001, +} DCP_GRPH_FLIP_RATE_ENABLE; + +/* + * DCP_GSL0_EN enum + */ + +typedef enum DCP_GSL0_EN { +DCP_GSL0_EN_FALSE = 0x00000000, +DCP_GSL0_EN_TRUE = 0x00000001, +} DCP_GSL0_EN; + +/* + * DCP_GSL1_EN enum + */ + +typedef enum DCP_GSL1_EN { +DCP_GSL1_EN_FALSE = 0x00000000, +DCP_GSL1_EN_TRUE = 0x00000001, +} DCP_GSL1_EN; + +/* + * DCP_GSL2_EN enum + */ + +typedef enum DCP_GSL2_EN { +DCP_GSL2_EN_FALSE = 0x00000000, +DCP_GSL2_EN_TRUE = 0x00000001, +} DCP_GSL2_EN; + +/* + * DCP_GSL_MASTER_EN enum + */ + +typedef enum DCP_GSL_MASTER_EN { +DCP_GSL_MASTER_EN_FALSE = 0x00000000, +DCP_GSL_MASTER_EN_TRUE = 0x00000001, +} DCP_GSL_MASTER_EN; + +/* + * DCP_GSL_XDMA_GROUP enum + */ + +typedef enum DCP_GSL_XDMA_GROUP { +DCP_GSL_XDMA_GROUP_VSYNC = 0x00000000, +DCP_GSL_XDMA_GROUP_HSYNC0 = 0x00000001, +DCP_GSL_XDMA_GROUP_HSYNC1 = 0x00000002, +DCP_GSL_XDMA_GROUP_HSYNC2 = 0x00000003, +} DCP_GSL_XDMA_GROUP; + +/* + * DCP_GSL_XDMA_GROUP_UNDERFLOW_EN enum + */ + +typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN { +DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE = 0x00000000, +DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE = 0x00000001, +} DCP_GSL_XDMA_GROUP_UNDERFLOW_EN; + +/* + * DCP_GSL_SYNC_SOURCE enum + */ + +typedef enum DCP_GSL_SYNC_SOURCE { +DCP_GSL_SYNC_SOURCE_FLIP = 0x00000000, +DCP_GSL_SYNC_SOURCE_PHASE0 = 0x00000001, +DCP_GSL_SYNC_SOURCE_RESET = 0x00000002, +DCP_GSL_SYNC_SOURCE_PHASE1 = 0x00000003, +} DCP_GSL_SYNC_SOURCE; + +/* + * DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC enum + */ + +typedef enum DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC { +DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_DIS = 0x00000000, +DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_EN = 0x00000001, +} DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC; + +/* + * DCP_GSL_DELAY_SURFACE_UPDATE_PENDING enum + */ + +typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING { +DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE = 0x00000000, +DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE = 0x00000001, +} DCP_GSL_DELAY_SURFACE_UPDATE_PENDING; + +/* + * DCP_TEST_DEBUG_WRITE_EN enum + */ + +typedef enum DCP_TEST_DEBUG_WRITE_EN { +DCP_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000, +DCP_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001, +} DCP_TEST_DEBUG_WRITE_EN; + +/* + * DCP_GRPH_STEREOSYNC_FLIP_EN enum + */ + +typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN { +DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE = 0x00000000, +DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE = 0x00000001, +} DCP_GRPH_STEREOSYNC_FLIP_EN; + +/* + * DCP_GRPH_STEREOSYNC_FLIP_MODE enum + */ + +typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE { +DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP = 0x00000000, +DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0 = 0x00000001, +DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET = 0x00000002, +DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1 = 0x00000003, +} DCP_GRPH_STEREOSYNC_FLIP_MODE; + +/* + * DCP_GRPH_STEREOSYNC_SELECT_DISABLE enum + */ + +typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE { +DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE = 0x00000000, +DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE = 0x00000001, +} DCP_GRPH_STEREOSYNC_SELECT_DISABLE; + +/* + * DCP_GRPH_ROTATION_ANGLE enum + */ + +typedef enum DCP_GRPH_ROTATION_ANGLE { +DCP_GRPH_ROTATION_ANGLE_0 = 0x00000000, +DCP_GRPH_ROTATION_ANGLE_90 = 0x00000001, +DCP_GRPH_ROTATION_ANGLE_180 = 0x00000002, +DCP_GRPH_ROTATION_ANGLE_270 = 0x00000003, +} DCP_GRPH_ROTATION_ANGLE; + +/* + * DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN enum + */ + +typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN { +DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE = 0x00000000, +DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE = 0x00000001, +} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN; + +/* + * DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE enum + */ + +typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE { +DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM = 0x00000000, +DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE = 0x00000001, +} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE; + +/* + * DCP_GRPH_REGAMMA_MODE enum + */ + +typedef enum DCP_GRPH_REGAMMA_MODE { +DCP_GRPH_REGAMMA_MODE_BYPASS = 0x00000000, +DCP_GRPH_REGAMMA_MODE_SRGB = 0x00000001, +DCP_GRPH_REGAMMA_MODE_XVYCC = 0x00000002, +DCP_GRPH_REGAMMA_MODE_PROGA = 0x00000003, +DCP_GRPH_REGAMMA_MODE_PROGB = 0x00000004, +} DCP_GRPH_REGAMMA_MODE; + +/* + * DCP_ALPHA_ROUND_TRUNC_MODE enum + */ + +typedef enum DCP_ALPHA_ROUND_TRUNC_MODE { +DCP_ALPHA_ROUND_TRUNC_MODE_ROUND = 0x00000000, +DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC = 0x00000001, +} DCP_ALPHA_ROUND_TRUNC_MODE; + +/* + * DCP_CURSOR_ALPHA_BLND_ENA enum + */ + +typedef enum DCP_CURSOR_ALPHA_BLND_ENA { +DCP_CURSOR_ALPHA_BLND_ENA_FALSE = 0x00000000, +DCP_CURSOR_ALPHA_BLND_ENA_TRUE = 0x00000001, +} DCP_CURSOR_ALPHA_BLND_ENA; + +/* + * DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK enum + */ + +typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK { +DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE = 0x00000000, +DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE = 0x00000001, +} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK; + +/* + * DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK enum + */ + +typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK { +DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE = 0x00000000, +DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE = 0x00000001, +} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK; + +/* + * DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK enum + */ + +typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK { +DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE = 0x00000000, +DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE = 0x00000001, +} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK; + +/* + * DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK enum + */ + +typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK { +DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE = 0x00000000, +DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE = 0x00000001, +} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK; + +/* + * DCP_GRPH_SURFACE_COUNTER_EN enum + */ + +typedef enum DCP_GRPH_SURFACE_COUNTER_EN { +DCP_GRPH_SURFACE_COUNTER_EN_DISABLE = 0x00000000, +DCP_GRPH_SURFACE_COUNTER_EN_ENABLE = 0x00000001, +} DCP_GRPH_SURFACE_COUNTER_EN; + +/* + * DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT enum + */ + +typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT { +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0 = 0x00000000, +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1 = 0x00000001, +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2 = 0x00000002, +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3 = 0x00000003, +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4 = 0x00000004, +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5 = 0x00000005, +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6 = 0x00000006, +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7 = 0x00000007, +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8 = 0x00000008, +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9 = 0x00000009, +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10 = 0x0000000a, +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11 = 0x0000000b, +} DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT; + +/* + * DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED enum + */ + +typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED { +DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO = 0x00000000, +DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES = 0x00000001, +} DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED; + +/* + * DCP_GRPH_XDMA_FLIP_TYPE_CLEAR enum + */ + +typedef enum DCP_GRPH_XDMA_FLIP_TYPE_CLEAR { +DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_DISABLE = 0x00000000, +DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_ENABLE = 0x00000001, +} DCP_GRPH_XDMA_FLIP_TYPE_CLEAR; + +/* + * DCP_GRPH_XDMA_DRR_MODE_ENABLE enum + */ + +typedef enum DCP_GRPH_XDMA_DRR_MODE_ENABLE { +DCP_GRPH_XDMA_DRR_MODE_ENABLE_DISABLE = 0x00000000, +DCP_GRPH_XDMA_DRR_MODE_ENABLE_ENABLE = 0x00000001, +} DCP_GRPH_XDMA_DRR_MODE_ENABLE; + +/* + * DCP_GRPH_XDMA_MULTIFLIP_ENABLE enum + */ + +typedef enum DCP_GRPH_XDMA_MULTIFLIP_ENABLE { +DCP_GRPH_XDMA_MULTIFLIP_ENABLE_DISABLE = 0x00000000, +DCP_GRPH_XDMA_MULTIFLIP_ENABLE_ENABLE = 0x00000001, +} DCP_GRPH_XDMA_MULTIFLIP_ENABLE; + +/* + * DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK enum + */ + +typedef enum DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK { +DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_FALSE = 0x00000000, +DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_TRUE = 0x00000001, +} DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK; + +/* + * DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK enum + */ + +typedef enum DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK { +DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_FALSE = 0x00000000, +DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_TRUE = 0x00000001, +} DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK; + +/******************************************************* + * DC_PERFMON Enums + *******************************************************/ + +/* + * PERFCOUNTER_CVALUE_SEL enum + */ + +typedef enum PERFCOUNTER_CVALUE_SEL { +PERFCOUNTER_CVALUE_SEL_47_0 = 0x00000000, +PERFCOUNTER_CVALUE_SEL_15_0 = 0x00000001, +PERFCOUNTER_CVALUE_SEL_31_16 = 0x00000002, +PERFCOUNTER_CVALUE_SEL_47_32 = 0x00000003, +PERFCOUNTER_CVALUE_SEL_11_0 = 0x00000004, +PERFCOUNTER_CVALUE_SEL_23_12 = 0x00000005, +PERFCOUNTER_CVALUE_SEL_35_24 = 0x00000006, +PERFCOUNTER_CVALUE_SEL_47_36 = 0x00000007, +} PERFCOUNTER_CVALUE_SEL; + +/* + * PERFCOUNTER_INC_MODE enum + */ + +typedef enum PERFCOUNTER_INC_MODE { +PERFCOUNTER_INC_MODE_MULTI_BIT = 0x00000000, +PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x00000001, +PERFCOUNTER_INC_MODE_LSB = 0x00000002, +PERFCOUNTER_INC_MODE_POS_EDGE = 0x00000003, +PERFCOUNTER_INC_MODE_NEG_EDGE = 0x00000004, +} PERFCOUNTER_INC_MODE; + +/* + * PERFCOUNTER_HW_CNTL_SEL enum + */ + +typedef enum PERFCOUNTER_HW_CNTL_SEL { +PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x00000000, +PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x00000001, +} PERFCOUNTER_HW_CNTL_SEL; + +/* + * PERFCOUNTER_RUNEN_MODE enum + */ + +typedef enum PERFCOUNTER_RUNEN_MODE { +PERFCOUNTER_RUNEN_MODE_LEVEL = 0x00000000, +PERFCOUNTER_RUNEN_MODE_EDGE = 0x00000001, +} PERFCOUNTER_RUNEN_MODE; + +/* + * PERFCOUNTER_CNTOFF_START_DIS enum + */ + +typedef enum PERFCOUNTER_CNTOFF_START_DIS { +PERFCOUNTER_CNTOFF_START_ENABLE = 0x00000000, +PERFCOUNTER_CNTOFF_START_DISABLE = 0x00000001, +} PERFCOUNTER_CNTOFF_START_DIS; + +/* + * PERFCOUNTER_RESTART_EN enum + */ + +typedef enum PERFCOUNTER_RESTART_EN { +PERFCOUNTER_RESTART_DISABLE = 0x00000000, +PERFCOUNTER_RESTART_ENABLE = 0x00000001, +} PERFCOUNTER_RESTART_EN; + +/* + * PERFCOUNTER_INT_EN enum + */ + +typedef enum PERFCOUNTER_INT_EN { +PERFCOUNTER_INT_DISABLE = 0x00000000, +PERFCOUNTER_INT_ENABLE = 0x00000001, +} PERFCOUNTER_INT_EN; + +/* + * PERFCOUNTER_OFF_MASK enum + */ + +typedef enum PERFCOUNTER_OFF_MASK { +PERFCOUNTER_OFF_MASK_DISABLE = 0x00000000, +PERFCOUNTER_OFF_MASK_ENABLE = 0x00000001, +} PERFCOUNTER_OFF_MASK; + +/* + * PERFCOUNTER_ACTIVE enum + */ + +typedef enum PERFCOUNTER_ACTIVE { +PERFCOUNTER_IS_IDLE = 0x00000000, +PERFCOUNTER_IS_ACTIVE = 0x00000001, +} PERFCOUNTER_ACTIVE; + +/* + * PERFCOUNTER_INT_TYPE enum + */ + +typedef enum PERFCOUNTER_INT_TYPE { +PERFCOUNTER_INT_TYPE_LEVEL = 0x00000000, +PERFCOUNTER_INT_TYPE_PULSE = 0x00000001, +} PERFCOUNTER_INT_TYPE; + +/* + * PERFCOUNTER_COUNTED_VALUE_TYPE enum + */ + +typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE { +PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x00000000, +PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x00000001, +PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 0x00000002, +} PERFCOUNTER_COUNTED_VALUE_TYPE; + +/* + * PERFCOUNTER_CNTL_SEL enum + */ + +typedef enum PERFCOUNTER_CNTL_SEL { +PERFCOUNTER_CNTL_SEL_0 = 0x00000000, +PERFCOUNTER_CNTL_SEL_1 = 0x00000001, +PERFCOUNTER_CNTL_SEL_2 = 0x00000002, +PERFCOUNTER_CNTL_SEL_3 = 0x00000003, +PERFCOUNTER_CNTL_SEL_4 = 0x00000004, +PERFCOUNTER_CNTL_SEL_5 = 0x00000005, +PERFCOUNTER_CNTL_SEL_6 = 0x00000006, +PERFCOUNTER_CNTL_SEL_7 = 0x00000007, +} PERFCOUNTER_CNTL_SEL; + +/* + * PERFCOUNTER_CNT0_STATE enum + */ + +typedef enum PERFCOUNTER_CNT0_STATE { +PERFCOUNTER_CNT0_STATE_RESET = 0x00000000, +PERFCOUNTER_CNT0_STATE_START = 0x00000001, +PERFCOUNTER_CNT0_STATE_FREEZE = 0x00000002, +PERFCOUNTER_CNT0_STATE_HW = 0x00000003, +} PERFCOUNTER_CNT0_STATE; + +/* + * PERFCOUNTER_STATE_SEL0 enum + */ + +typedef enum PERFCOUNTER_STATE_SEL0 { +PERFCOUNTER_STATE_SEL0_GLOBAL = 0x00000000, +PERFCOUNTER_STATE_SEL0_LOCAL = 0x00000001, +} PERFCOUNTER_STATE_SEL0; + +/* + * PERFCOUNTER_CNT1_STATE enum + */ + +typedef enum PERFCOUNTER_CNT1_STATE { +PERFCOUNTER_CNT1_STATE_RESET = 0x00000000, +PERFCOUNTER_CNT1_STATE_START = 0x00000001, +PERFCOUNTER_CNT1_STATE_FREEZE = 0x00000002, +PERFCOUNTER_CNT1_STATE_HW = 0x00000003, +} PERFCOUNTER_CNT1_STATE; + +/* + * PERFCOUNTER_STATE_SEL1 enum + */ + +typedef enum PERFCOUNTER_STATE_SEL1 { +PERFCOUNTER_STATE_SEL1_GLOBAL = 0x00000000, +PERFCOUNTER_STATE_SEL1_LOCAL = 0x00000001, +} PERFCOUNTER_STATE_SEL1; + +/* + * PERFCOUNTER_CNT2_STATE enum + */ + +typedef enum PERFCOUNTER_CNT2_STATE { +PERFCOUNTER_CNT2_STATE_RESET = 0x00000000, +PERFCOUNTER_CNT2_STATE_START = 0x00000001, +PERFCOUNTER_CNT2_STATE_FREEZE = 0x00000002, +PERFCOUNTER_CNT2_STATE_HW = 0x00000003, +} PERFCOUNTER_CNT2_STATE; + +/* + * PERFCOUNTER_STATE_SEL2 enum + */ + +typedef enum PERFCOUNTER_STATE_SEL2 { +PERFCOUNTER_STATE_SEL2_GLOBAL = 0x00000000, +PERFCOUNTER_STATE_SEL2_LOCAL = 0x00000001, +} PERFCOUNTER_STATE_SEL2; + +/* + * PERFCOUNTER_CNT3_STATE enum + */ + +typedef enum PERFCOUNTER_CNT3_STATE { +PERFCOUNTER_CNT3_STATE_RESET = 0x00000000, +PERFCOUNTER_CNT3_STATE_START = 0x00000001, +PERFCOUNTER_CNT3_STATE_FREEZE = 0x00000002, +PERFCOUNTER_CNT3_STATE_HW = 0x00000003, +} PERFCOUNTER_CNT3_STATE; + +/* + * PERFCOUNTER_STATE_SEL3 enum + */ + +typedef enum PERFCOUNTER_STATE_SEL3 { +PERFCOUNTER_STATE_SEL3_GLOBAL = 0x00000000, +PERFCOUNTER_STATE_SEL3_LOCAL = 0x00000001, +} PERFCOUNTER_STATE_SEL3; + +/* + * PERFCOUNTER_CNT4_STATE enum + */ + +typedef enum PERFCOUNTER_CNT4_STATE { +PERFCOUNTER_CNT4_STATE_RESET = 0x00000000, +PERFCOUNTER_CNT4_STATE_START = 0x00000001, +PERFCOUNTER_CNT4_STATE_FREEZE = 0x00000002, +PERFCOUNTER_CNT4_STATE_HW = 0x00000003, +} PERFCOUNTER_CNT4_STATE; + +/* + * PERFCOUNTER_STATE_SEL4 enum + */ + +typedef enum PERFCOUNTER_STATE_SEL4 { +PERFCOUNTER_STATE_SEL4_GLOBAL = 0x00000000, +PERFCOUNTER_STATE_SEL4_LOCAL = 0x00000001, +} PERFCOUNTER_STATE_SEL4; + +/* + * PERFCOUNTER_CNT5_STATE enum + */ + +typedef enum PERFCOUNTER_CNT5_STATE { +PERFCOUNTER_CNT5_STATE_RESET = 0x00000000, +PERFCOUNTER_CNT5_STATE_START = 0x00000001, +PERFCOUNTER_CNT5_STATE_FREEZE = 0x00000002, +PERFCOUNTER_CNT5_STATE_HW = 0x00000003, +} PERFCOUNTER_CNT5_STATE; + +/* + * PERFCOUNTER_STATE_SEL5 enum + */ + +typedef enum PERFCOUNTER_STATE_SEL5 { +PERFCOUNTER_STATE_SEL5_GLOBAL = 0x00000000, +PERFCOUNTER_STATE_SEL5_LOCAL = 0x00000001, +} PERFCOUNTER_STATE_SEL5; + +/* + * PERFCOUNTER_CNT6_STATE enum + */ + +typedef enum PERFCOUNTER_CNT6_STATE { +PERFCOUNTER_CNT6_STATE_RESET = 0x00000000, +PERFCOUNTER_CNT6_STATE_START = 0x00000001, +PERFCOUNTER_CNT6_STATE_FREEZE = 0x00000002, +PERFCOUNTER_CNT6_STATE_HW = 0x00000003, +} PERFCOUNTER_CNT6_STATE; + +/* + * PERFCOUNTER_STATE_SEL6 enum + */ + +typedef enum PERFCOUNTER_STATE_SEL6 { +PERFCOUNTER_STATE_SEL6_GLOBAL = 0x00000000, +PERFCOUNTER_STATE_SEL6_LOCAL = 0x00000001, +} PERFCOUNTER_STATE_SEL6; + +/* + * PERFCOUNTER_CNT7_STATE enum + */ + +typedef enum PERFCOUNTER_CNT7_STATE { +PERFCOUNTER_CNT7_STATE_RESET = 0x00000000, +PERFCOUNTER_CNT7_STATE_START = 0x00000001, +PERFCOUNTER_CNT7_STATE_FREEZE = 0x00000002, +PERFCOUNTER_CNT7_STATE_HW = 0x00000003, +} PERFCOUNTER_CNT7_STATE; + +/* + * PERFCOUNTER_STATE_SEL7 enum + */ + +typedef enum PERFCOUNTER_STATE_SEL7 { +PERFCOUNTER_STATE_SEL7_GLOBAL = 0x00000000, +PERFCOUNTER_STATE_SEL7_LOCAL = 0x00000001, +} PERFCOUNTER_STATE_SEL7; + +/* + * PERFMON_STATE enum + */ + +typedef enum PERFMON_STATE { +PERFMON_STATE_RESET = 0x00000000, +PERFMON_STATE_START = 0x00000001, +PERFMON_STATE_FREEZE = 0x00000002, +PERFMON_STATE_HW = 0x00000003, +} PERFMON_STATE; + +/* + * PERFMON_CNTOFF_AND_OR enum + */ + +typedef enum PERFMON_CNTOFF_AND_OR { +PERFMON_CNTOFF_OR = 0x00000000, +PERFMON_CNTOFF_AND = 0x00000001, +} PERFMON_CNTOFF_AND_OR; + +/* + * PERFMON_CNTOFF_INT_EN enum + */ + +typedef enum PERFMON_CNTOFF_INT_EN { +PERFMON_CNTOFF_INT_DISABLE = 0x00000000, +PERFMON_CNTOFF_INT_ENABLE = 0x00000001, +} PERFMON_CNTOFF_INT_EN; + +/* + * PERFMON_CNTOFF_INT_TYPE enum + */ + +typedef enum PERFMON_CNTOFF_INT_TYPE { +PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x00000000, +PERFMON_CNTOFF_INT_TYPE_PULSE = 0x00000001, +} PERFMON_CNTOFF_INT_TYPE; + +/******************************************************* + * SCL Enums + *******************************************************/ + +/* + * SCL_C_RAM_TAP_PAIR_IDX enum + */ + +typedef enum SCL_C_RAM_TAP_PAIR_IDX { +SCL_C_RAM_TAP_PAIR_ID0 = 0x00000000, +SCL_C_RAM_TAP_PAIR_ID1 = 0x00000001, +SCL_C_RAM_TAP_PAIR_ID2 = 0x00000002, +SCL_C_RAM_TAP_PAIR_ID3 = 0x00000003, +SCL_C_RAM_TAP_PAIR_ID4 = 0x00000004, +} SCL_C_RAM_TAP_PAIR_IDX; + +/* + * SCL_C_RAM_PHASE enum + */ + +typedef enum SCL_C_RAM_PHASE { +SCL_C_RAM_PHASE_0 = 0x00000000, +SCL_C_RAM_PHASE_1 = 0x00000001, +SCL_C_RAM_PHASE_2 = 0x00000002, +SCL_C_RAM_PHASE_3 = 0x00000003, +SCL_C_RAM_PHASE_4 = 0x00000004, +SCL_C_RAM_PHASE_5 = 0x00000005, +SCL_C_RAM_PHASE_6 = 0x00000006, +SCL_C_RAM_PHASE_7 = 0x00000007, +SCL_C_RAM_PHASE_8 = 0x00000008, +} SCL_C_RAM_PHASE; + +/* + * SCL_C_RAM_FILTER_TYPE enum + */ + +typedef enum SCL_C_RAM_FILTER_TYPE { +SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT = 0x00000000, +SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT = 0x00000001, +SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT = 0x00000002, +SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT = 0x00000003, +} SCL_C_RAM_FILTER_TYPE; + +/* + * SCL_MODE_SEL enum + */ + +typedef enum SCL_MODE_SEL { +SCL_MODE_RGB_BYPASS = 0x00000000, +SCL_MODE_RGB_SCALING = 0x00000001, +SCL_MODE_YCBCR_SCALING = 0x00000002, +SCL_MODE_YCBCR_BYPASS = 0x00000003, +} SCL_MODE_SEL; + +/* + * SCL_PSCL_EN enum + */ + +typedef enum SCL_PSCL_EN { +SCL_PSCL_DISABLE = 0x00000000, +SCL_PSCL_ENANBLE = 0x00000001, +} SCL_PSCL_EN; + +/* + * SCL_V_NUM_OF_TAPS enum + */ + +typedef enum SCL_V_NUM_OF_TAPS { +SCL_V_NUM_OF_TAPS_1 = 0x00000000, +SCL_V_NUM_OF_TAPS_2 = 0x00000001, +SCL_V_NUM_OF_TAPS_3 = 0x00000002, +SCL_V_NUM_OF_TAPS_4 = 0x00000003, +SCL_V_NUM_OF_TAPS_5 = 0x00000004, +SCL_V_NUM_OF_TAPS_6 = 0x00000005, +} SCL_V_NUM_OF_TAPS; + +/* + * SCL_H_NUM_OF_TAPS enum + */ + +typedef enum SCL_H_NUM_OF_TAPS { +SCL_H_NUM_OF_TAPS_1 = 0x00000000, +SCL_H_NUM_OF_TAPS_2 = 0x00000001, +SCL_H_NUM_OF_TAPS_4 = 0x00000003, +SCL_H_NUM_OF_TAPS_6 = 0x00000005, +SCL_H_NUM_OF_TAPS_8 = 0x00000007, +SCL_H_NUM_OF_TAPS_10 = 0x00000009, +} SCL_H_NUM_OF_TAPS; + +/* + * SCL_BOUNDARY_MODE enum + */ + +typedef enum SCL_BOUNDARY_MODE { +SCL_BOUNDARY_MODE_BLACK = 0x00000000, +SCL_BOUNDARY_MODE_EDGE = 0x00000001, +} SCL_BOUNDARY_MODE; + +/* + * SCL_EARLY_EOL_MOD enum + */ + +typedef enum SCL_EARLY_EOL_MOD { +SCL_EARLY_EOL_MODE_CRTC = 0x00000000, +SCL_EARLY_EOL_MODE_INTERNAL = 0x00000001, +} SCL_EARLY_EOL_MOD; + +/* + * SCL_BYPASS_MODE enum + */ + +typedef enum SCL_BYPASS_MODE { +SCL_BYPASS_MODE_MC_MR = 0x00000000, +SCL_BYPASS_MODE_AC_NR = 0x00000001, +SCL_BYPASS_MODE_AC_AR = 0x00000002, +SCL_BYPASS_MODE_RESERVED = 0x00000003, +} SCL_BYPASS_MODE; + +/* + * SCL_V_MANUAL_REPLICATE_FACTOR enum + */ + +typedef enum SCL_V_MANUAL_REPLICATE_FACTOR { +SCL_V_MANUAL_REPLICATE_FACTOR_1 = 0x00000000, +SCL_V_MANUAL_REPLICATE_FACTOR_2 = 0x00000001, +SCL_V_MANUAL_REPLICATE_FACTOR_3 = 0x00000002, +SCL_V_MANUAL_REPLICATE_FACTOR_4 = 0x00000003, +SCL_V_MANUAL_REPLICATE_FACTOR_5 = 0x00000004, +SCL_V_MANUAL_REPLICATE_FACTOR_6 = 0x00000005, +SCL_V_MANUAL_REPLICATE_FACTOR_7 = 0x00000006, +SCL_V_MANUAL_REPLICATE_FACTOR_8 = 0x00000007, +SCL_V_MANUAL_REPLICATE_FACTOR_9 = 0x00000008, +SCL_V_MANUAL_REPLICATE_FACTOR_10 = 0x00000009, +SCL_V_MANUAL_REPLICATE_FACTOR_11 = 0x0000000a, +SCL_V_MANUAL_REPLICATE_FACTOR_12 = 0x0000000b, +SCL_V_MANUAL_REPLICATE_FACTOR_13 = 0x0000000c, +SCL_V_MANUAL_REPLICATE_FACTOR_14 = 0x0000000d, +SCL_V_MANUAL_REPLICATE_FACTOR_15 = 0x0000000e, +SCL_V_MANUAL_REPLICATE_FACTOR_16 = 0x0000000f, +} SCL_V_MANUAL_REPLICATE_FACTOR; + +/* + * SCL_H_MANUAL_REPLICATE_FACTOR enum + */ + +typedef enum SCL_H_MANUAL_REPLICATE_FACTOR { +SCL_H_MANUAL_REPLICATE_FACTOR_1 = 0x00000000, +SCL_H_MANUAL_REPLICATE_FACTOR_2 = 0x00000001, +SCL_H_MANUAL_REPLICATE_FACTOR_3 = 0x00000002, +SCL_H_MANUAL_REPLICATE_FACTOR_4 = 0x00000003, +SCL_H_MANUAL_REPLICATE_FACTOR_5 = 0x00000004, +SCL_H_MANUAL_REPLICATE_FACTOR_6 = 0x00000005, +SCL_H_MANUAL_REPLICATE_FACTOR_7 = 0x00000006, +SCL_H_MANUAL_REPLICATE_FACTOR_8 = 0x00000007, +SCL_H_MANUAL_REPLICATE_FACTOR_9 = 0x00000008, +SCL_H_MANUAL_REPLICATE_FACTOR_10 = 0x00000009, +SCL_H_MANUAL_REPLICATE_FACTOR_11 = 0x0000000a, +SCL_H_MANUAL_REPLICATE_FACTOR_12 = 0x0000000b, +SCL_H_MANUAL_REPLICATE_FACTOR_13 = 0x0000000c, +SCL_H_MANUAL_REPLICATE_FACTOR_14 = 0x0000000d, +SCL_H_MANUAL_REPLICATE_FACTOR_15 = 0x0000000e, +SCL_H_MANUAL_REPLICATE_FACTOR_16 = 0x0000000f, +} SCL_H_MANUAL_REPLICATE_FACTOR; + +/* + * SCL_V_CALC_AUTO_RATIO_EN enum + */ + +typedef enum SCL_V_CALC_AUTO_RATIO_EN { +SCL_V_CALC_AUTO_RATIO_DISABLE = 0x00000000, +SCL_V_CALC_AUTO_RATIO_ENABLE = 0x00000001, +} SCL_V_CALC_AUTO_RATIO_EN; + +/* + * SCL_H_CALC_AUTO_RATIO_EN enum + */ + +typedef enum SCL_H_CALC_AUTO_RATIO_EN { +SCL_H_CALC_AUTO_RATIO_DISABLE = 0x00000000, +SCL_H_CALC_AUTO_RATIO_ENABLE = 0x00000001, +} SCL_H_CALC_AUTO_RATIO_EN; + +/* + * SCL_H_FILTER_PICK_NEAREST enum + */ + +typedef enum SCL_H_FILTER_PICK_NEAREST { +SCL_H_FILTER_PICK_NEAREST_DISABLE = 0x00000000, +SCL_H_FILTER_PICK_NEAREST_ENABLE = 0x00000001, +} SCL_H_FILTER_PICK_NEAREST; + +/* + * SCL_H_2TAP_HARDCODE_COEF_EN enum + */ + +typedef enum SCL_H_2TAP_HARDCODE_COEF_EN { +SCL_H_2TAP_HARDCODE_COEF_DISABLE = 0x00000000, +SCL_H_2TAP_HARDCODE_COEF_ENABLE = 0x00000001, +} SCL_H_2TAP_HARDCODE_COEF_EN; + +/* + * SCL_V_FILTER_PICK_NEAREST enum + */ + +typedef enum SCL_V_FILTER_PICK_NEAREST { +SCL_V_FILTER_PICK_NEAREST_DISABLE = 0x00000000, +SCL_V_FILTER_PICK_NEAREST_ENABLE = 0x00000001, +} SCL_V_FILTER_PICK_NEAREST; + +/* + * SCL_V_2TAP_HARDCODE_COEF_EN enum + */ + +typedef enum SCL_V_2TAP_HARDCODE_COEF_EN { +SCL_V_2TAP_HARDCODE_COEF_DISABLE = 0x00000000, +SCL_V_2TAP_HARDCODE_COEF_ENABLE = 0x00000001, +} SCL_V_2TAP_HARDCODE_COEF_EN; + +/* + * SCL_UPDATE_TAKEN enum + */ + +typedef enum SCL_UPDATE_TAKEN { +SCL_UPDATE_TAKEN_NO = 0x00000000, +SCL_UPDATE_TAKEN_YES = 0x00000001, +} SCL_UPDATE_TAKEN; + +/* + * SCL_UPDATE_LOCK enum + */ + +typedef enum SCL_UPDATE_LOCK { +SCL_UPDATE_UNLOCKED = 0x00000000, +SCL_UPDATE_LOCKED = 0x00000001, +} SCL_UPDATE_LOCK; + +/* + * SCL_COEF_UPDATE_COMPLETE enum + */ + +typedef enum SCL_COEF_UPDATE_COMPLETE { +SCL_COEF_UPDATE_NOT_COMPLETED = 0x00000000, +SCL_COEF_UPDATE_COMPLETED = 0x00000001, +} SCL_COEF_UPDATE_COMPLETE; + +/* + * SCL_HF_SHARP_SCALE_FACTOR enum + */ + +typedef enum SCL_HF_SHARP_SCALE_FACTOR { +SCL_HF_SHARP_SCALE_FACTOR_0 = 0x00000000, +SCL_HF_SHARP_SCALE_FACTOR_1 = 0x00000001, +SCL_HF_SHARP_SCALE_FACTOR_2 = 0x00000002, +SCL_HF_SHARP_SCALE_FACTOR_3 = 0x00000003, +SCL_HF_SHARP_SCALE_FACTOR_4 = 0x00000004, +SCL_HF_SHARP_SCALE_FACTOR_5 = 0x00000005, +SCL_HF_SHARP_SCALE_FACTOR_6 = 0x00000006, +SCL_HF_SHARP_SCALE_FACTOR_7 = 0x00000007, +} SCL_HF_SHARP_SCALE_FACTOR; + +/* + * SCL_HF_SHARP_EN enum + */ + +typedef enum SCL_HF_SHARP_EN { +SCL_HF_SHARP_DISABLE = 0x00000000, +SCL_HF_SHARP_ENABLE = 0x00000001, +} SCL_HF_SHARP_EN; + +/* + * SCL_VF_SHARP_SCALE_FACTOR enum + */ + +typedef enum SCL_VF_SHARP_SCALE_FACTOR { +SCL_VF_SHARP_SCALE_FACTOR_0 = 0x00000000, +SCL_VF_SHARP_SCALE_FACTOR_1 = 0x00000001, +SCL_VF_SHARP_SCALE_FACTOR_2 = 0x00000002, +SCL_VF_SHARP_SCALE_FACTOR_3 = 0x00000003, +SCL_VF_SHARP_SCALE_FACTOR_4 = 0x00000004, +SCL_VF_SHARP_SCALE_FACTOR_5 = 0x00000005, +SCL_VF_SHARP_SCALE_FACTOR_6 = 0x00000006, +SCL_VF_SHARP_SCALE_FACTOR_7 = 0x00000007, +} SCL_VF_SHARP_SCALE_FACTOR; + +/* + * SCL_VF_SHARP_EN enum + */ + +typedef enum SCL_VF_SHARP_EN { +SCL_VF_SHARP_DISABLE = 0x00000000, +SCL_VF_SHARP_ENABLE = 0x00000001, +} SCL_VF_SHARP_EN; + +/* + * SCL_ALU_DISABLE enum + */ + +typedef enum SCL_ALU_DISABLE { +SCL_ALU_ENABLED = 0x00000000, +SCL_ALU_DISABLED = 0x00000001, +} SCL_ALU_DISABLE; + +/* + * SCL_HOST_CONFLICT_MASK enum + */ + +typedef enum SCL_HOST_CONFLICT_MASK { +SCL_HOST_CONFLICT_DISABLE_INTERRUPT = 0x00000000, +SCL_HOST_CONFLICT_ENABLE_INTERRUPT = 0x00000001, +} SCL_HOST_CONFLICT_MASK; + +/* + * SCL_SCL_MODE_CHANGE_MASK enum + */ + +typedef enum SCL_SCL_MODE_CHANGE_MASK { +SCL_MODE_CHANGE_DISABLE_INTERRUPT = 0x00000000, +SCL_MODE_CHANGE_ENABLE_INTERRUPT = 0x00000001, +} SCL_SCL_MODE_CHANGE_MASK; + +/******************************************************* + * SCLV Enums + *******************************************************/ + +/* + * SCLV_MODE_SEL enum + */ + +typedef enum SCLV_MODE_SEL { +SCLV_MODE_RGB_BYPASS = 0x00000000, +SCLV_MODE_RGB_SCALING = 0x00000001, +SCLV_MODE_YCBCR_SCALING = 0x00000002, +SCLV_MODE_YCBCR_BYPASS = 0x00000003, +} SCLV_MODE_SEL; + +/* + * SCLV_INTERLACE_SOURCE enum + */ + +typedef enum SCLV_INTERLACE_SOURCE { +INTERLACE_SOURCE_PROGRESSIVE = 0x00000000, +INTERLACE_SOURCE_INTERLEAVE = 0x00000001, +INTERLACE_SOURCE_STACK = 0x00000002, +} SCLV_INTERLACE_SOURCE; + +/* + * SCLV_UPDATE_LOCK enum + */ + +typedef enum SCLV_UPDATE_LOCK { +UPDATE_UNLOCKED = 0x00000000, +UPDATE_LOCKED = 0x00000001, +} SCLV_UPDATE_LOCK; + +/* + * SCLV_COEF_UPDATE_COMPLETE enum + */ + +typedef enum SCLV_COEF_UPDATE_COMPLETE { +COEF_UPDATE_NOT_COMPLETE = 0x00000000, +COEF_UPDATE_COMPLETE = 0x00000001, +} SCLV_COEF_UPDATE_COMPLETE; + +/******************************************************* + * DPRX_SD Enums + *******************************************************/ + +/* + * DPRX_SD_PIXEL_ENCODING enum + */ + +typedef enum DPRX_SD_PIXEL_ENCODING { +PIXEL_FORMAT_RGB_444 = 0x00000000, +PIXEL_FORMAT_YCBCR_444 = 0x00000001, +PIXEL_FORMAT_YCBCR_422 = 0x00000002, +PIXEL_FORMAT_Y_ONLY = 0x00000003, +} DPRX_SD_PIXEL_ENCODING; + +/* + * DPRX_SD_COMPONENT_DEPTH enum + */ + +typedef enum DPRX_SD_COMPONENT_DEPTH { +COMPONENT_DEPTH_6BPC = 0x00000000, +COMPONENT_DEPTH_8BPC = 0x00000001, +COMPONENT_DEPTH_10BPC = 0x00000002, +COMPONENT_DEPTH_12BPC = 0x00000003, +COMPONENT_DEPTH_16BPC = 0x00000004, +} DPRX_SD_COMPONENT_DEPTH; + +/******************************************************* + * AZF0STREAM Enums + *******************************************************/ + +/* + * AZ_LATENCY_COUNTER_CONTROL enum + */ + +typedef enum AZ_LATENCY_COUNTER_CONTROL { +AZ_LATENCY_COUNTER_NO_RESET = 0x00000000, +AZ_LATENCY_COUNTER_RESET_DONE = 0x00000001, +} AZ_LATENCY_COUNTER_CONTROL; + +/******************************************************* + * BLND Enums + *******************************************************/ + +/* + * BLND_CONTROL_BLND_MODE enum + */ + +typedef enum BLND_CONTROL_BLND_MODE { +BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x00000000, +BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x00000001, +BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x00000002, +BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x00000003, +} BLND_CONTROL_BLND_MODE; + +/* + * BLND_CONTROL_BLND_STEREO_TYPE enum + */ + +typedef enum BLND_CONTROL_BLND_STEREO_TYPE { +BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0x00000000, +BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 0x00000001, +BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 0x00000002, +BLND_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x00000003, +} BLND_CONTROL_BLND_STEREO_TYPE; + +/* + * BLND_CONTROL_BLND_STEREO_POLARITY enum + */ + +typedef enum BLND_CONTROL_BLND_STEREO_POLARITY { +BLND_CONTROL_BLND_STEREO_POLARITY_LOW = 0x00000000, +BLND_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x00000001, +} BLND_CONTROL_BLND_STEREO_POLARITY; + +/* + * BLND_CONTROL_BLND_FEEDTHROUGH_EN enum + */ + +typedef enum BLND_CONTROL_BLND_FEEDTHROUGH_EN { +BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x00000000, +BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x00000001, +} BLND_CONTROL_BLND_FEEDTHROUGH_EN; + +/* + * BLND_CONTROL_BLND_ALPHA_MODE enum + */ + +typedef enum BLND_CONTROL_BLND_ALPHA_MODE { +BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x00000000, +BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001, +BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x00000002, +BLND_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x00000003, +} BLND_CONTROL_BLND_ALPHA_MODE; + +/* + * BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY enum + */ + +typedef enum BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY { +BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE = 0x00000000, +BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE = 0x00000001, +} BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY; + +/* + * BLND_CONTROL_BLND_MULTIPLIED_MODE enum + */ + +typedef enum BLND_CONTROL_BLND_MULTIPLIED_MODE { +BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x00000000, +BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x00000001, +} BLND_CONTROL_BLND_MULTIPLIED_MODE; + +/* + * BLND_SM_CONTROL2_SM_MODE enum + */ + +typedef enum BLND_SM_CONTROL2_SM_MODE { +BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x00000000, +BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x00000002, +BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004, +BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006, +} BLND_SM_CONTROL2_SM_MODE; + +/* + * BLND_SM_CONTROL2_SM_FRAME_ALTERNATE enum + */ + +typedef enum BLND_SM_CONTROL2_SM_FRAME_ALTERNATE { +BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x00000000, +BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x00000001, +} BLND_SM_CONTROL2_SM_FRAME_ALTERNATE; + +/* + * BLND_SM_CONTROL2_SM_FIELD_ALTERNATE enum + */ + +typedef enum BLND_SM_CONTROL2_SM_FIELD_ALTERNATE { +BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x00000000, +BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x00000001, +} BLND_SM_CONTROL2_SM_FIELD_ALTERNATE; + +/* + * BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL enum + */ + +typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL { +BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000, +BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001, +BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002, +BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003, +} BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL; + +/* + * BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL enum + */ + +typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL { +BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000, +BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001, +BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002, +BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003, +} BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL; + +/* + * BLND_CONTROL2_PTI_ENABLE enum + */ + +typedef enum BLND_CONTROL2_PTI_ENABLE { +BLND_CONTROL2_PTI_ENABLE_FALSE = 0x00000000, +BLND_CONTROL2_PTI_ENABLE_TRUE = 0x00000001, +} BLND_CONTROL2_PTI_ENABLE; + +/* + * BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN enum + */ + +typedef enum BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN { +BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x00000000, +BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x00000001, +} BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN; + +/* + * BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN enum + */ + +typedef enum BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN { +BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x00000000, +BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x00000001, +} BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN; + +/* + * BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK enum + */ + +typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK { +BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0x00000000, +BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 0x00000001, +} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK; + +/* + * BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK enum + */ + +typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK { +BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0x00000000, +BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 0x00000001, +} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK; + +/* + * BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK enum + */ + +typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK { +BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0x00000000, +BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 0x00000001, +} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK; + +/* + * BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK enum + */ + +typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK { +BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0x00000000, +BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 0x00000001, +} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; + +/* + * BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK enum + */ + +typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK { +BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0x00000000, +BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 0x00000001, +} BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK; + +/* + * BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK enum + */ + +typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK { +BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0x00000000, +BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 0x00000001, +} BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK; + +/* + * BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK enum + */ + +typedef enum BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK { +BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x00000000, +BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x00000001, +} BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK; + +/* + * BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK enum + */ + +typedef enum BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK { +BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x00000000, +BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x00000001, +} BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK; + +/* + * BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE enum + */ + +typedef enum BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE { +BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x00000000, +BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x00000001, +} BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE; + +/* + * BLND_DEBUG_BLND_CNV_MUX_SELECT enum + */ + +typedef enum BLND_DEBUG_BLND_CNV_MUX_SELECT { +BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x00000000, +BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x00000001, +} BLND_DEBUG_BLND_CNV_MUX_SELECT; + +/* + * BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN enum + */ + +typedef enum BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN { +BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000, +BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001, +} BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN; + +/******************************************************* + * AZF0ENDPOINT Enums + *******************************************************/ + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; + +/* + * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum + */ + +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES { +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000, +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE { +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS { +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE { +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE { +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE { +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY { +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED { +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; + +/* + * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE { +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; + +/* + * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE { +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000, +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001, +} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; + +/* + * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE { +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0x00000000, +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 0x00000001, +} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; + +/******************************************************* + * AZF0INPUTENDPOINT Enums + *******************************************************/ + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; + +/* + * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES { +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000, +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE { +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; + +/* + * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum + */ + +typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE { +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0x00000000, +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 0x00000001, +} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; + +/******************************************************* + * UNP Enums + *******************************************************/ + +/* + * UNP_GRPH_EN enum + */ + +typedef enum UNP_GRPH_EN { +UNP_GRPH_DISABLED = 0x00000000, +UNP_GRPH_ENABLED = 0x00000001, +} UNP_GRPH_EN; + +/* + * UNP_GRPH_DEPTH enum + */ + +typedef enum UNP_GRPH_DEPTH { +UNP_GRPH_8BPP = 0x00000000, +UNP_GRPH_16BPP = 0x00000001, +UNP_GRPH_32BPP = 0x00000002, +} UNP_GRPH_DEPTH; + +/* + * UNP_GRPH_NUM_BANKS enum + */ + +typedef enum UNP_GRPH_NUM_BANKS { +UNP_GRPH_ADDR_SURF_2_BANK = 0x00000000, +UNP_GRPH_ADDR_SURF_4_BANK = 0x00000001, +UNP_GRPH_ADDR_SURF_8_BANK = 0x00000002, +UNP_GRPH_ADDR_SURF_16_BANK = 0x00000003, +} UNP_GRPH_NUM_BANKS; + +/* + * UNP_GRPH_BANK_WIDTH enum + */ + +typedef enum UNP_GRPH_BANK_WIDTH { +UNP_GRPH_ADDR_SURF_BANK_WIDTH_1 = 0x00000000, +UNP_GRPH_ADDR_SURF_BANK_WIDTH_2 = 0x00000001, +UNP_GRPH_ADDR_SURF_BANK_WIDTH_4 = 0x00000002, +UNP_GRPH_ADDR_SURF_BANK_WIDTH_8 = 0x00000003, +} UNP_GRPH_BANK_WIDTH; + +/* + * UNP_GRPH_BANK_HEIGHT enum + */ + +typedef enum UNP_GRPH_BANK_HEIGHT { +UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1 = 0x00000000, +UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2 = 0x00000001, +UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4 = 0x00000002, +UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8 = 0x00000003, +} UNP_GRPH_BANK_HEIGHT; + +/* + * UNP_GRPH_TILE_SPLIT enum + */ + +typedef enum UNP_GRPH_TILE_SPLIT { +UNP_ADDR_SURF_TILE_SPLIT_64B = 0x00000000, +UNP_ADDR_SURF_TILE_SPLIT_128B = 0x00000001, +UNP_ADDR_SURF_TILE_SPLIT_256B = 0x00000002, +UNP_ADDR_SURF_TILE_SPLIT_512B = 0x00000003, +UNP_ADDR_SURF_TILE_SPLIT_1KB = 0x00000004, +UNP_ADDR_SURF_TILE_SPLIT_2KB = 0x00000005, +UNP_ADDR_SURF_TILE_SPLIT_4KB = 0x00000006, +} UNP_GRPH_TILE_SPLIT; + +/* + * UNP_GRPH_ADDRESS_TRANSLATION_ENABLE enum + */ + +typedef enum UNP_GRPH_ADDRESS_TRANSLATION_ENABLE { +UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0 = 0x00000000, +UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1 = 0x00000001, +} UNP_GRPH_ADDRESS_TRANSLATION_ENABLE; + +/* + * UNP_GRPH_MACRO_TILE_ASPECT enum + */ + +typedef enum UNP_GRPH_MACRO_TILE_ASPECT { +UNP_ADDR_SURF_MACRO_ASPECT_1 = 0x00000000, +UNP_ADDR_SURF_MACRO_ASPECT_2 = 0x00000001, +UNP_ADDR_SURF_MACRO_ASPECT_4 = 0x00000002, +UNP_ADDR_SURF_MACRO_ASPECT_8 = 0x00000003, +} UNP_GRPH_MACRO_TILE_ASPECT; + +/* + * UNP_GRPH_COLOR_EXPANSION_MODE enum + */ + +typedef enum UNP_GRPH_COLOR_EXPANSION_MODE { +UNP_GRPH_DYNAMIC_EXPANSION = 0x00000000, +UNP_GRPH_ZERO_EXPANSION = 0x00000001, +} UNP_GRPH_COLOR_EXPANSION_MODE; + +/* + * UNP_VIDEO_FORMAT enum + */ + +typedef enum UNP_VIDEO_FORMAT { +UNP_VIDEO_FORMAT0 = 0x00000000, +UNP_VIDEO_FORMAT1 = 0x00000001, +UNP_VIDEO_FORMAT_YUV420_YCbCr = 0x00000002, +UNP_VIDEO_FORMAT_YUV420_YCrCb = 0x00000003, +UNP_VIDEO_FORMAT_YUV422_YCb = 0x00000004, +UNP_VIDEO_FORMAT_YUV422_YCr = 0x00000005, +UNP_VIDEO_FORMAT_YUV422_CbY = 0x00000006, +UNP_VIDEO_FORMAT_YUV422_CrY = 0x00000007, +} UNP_VIDEO_FORMAT; + +/* + * UNP_GRPH_ENDIAN_SWAP enum + */ + +typedef enum UNP_GRPH_ENDIAN_SWAP { +UNP_GRPH_ENDIAN_SWAP_NONE = 0x00000000, +UNP_GRPH_ENDIAN_SWAP_8IN16 = 0x00000001, +UNP_GRPH_ENDIAN_SWAP_8IN32 = 0x00000002, +UNP_GRPH_ENDIAN_SWAP_8IN43 = 0x00000003, +} UNP_GRPH_ENDIAN_SWAP; + +/* + * UNP_GRPH_RED_CROSSBAR enum + */ + +typedef enum UNP_GRPH_RED_CROSSBAR { +UNP_GRPH_RED_CROSSBAR_R_Cr = 0x00000000, +UNP_GRPH_RED_CROSSBAR_G_Y = 0x00000001, +UNP_GRPH_RED_CROSSBAR_B_Cb = 0x00000002, +UNP_GRPH_RED_CROSSBAR_A = 0x00000003, +} UNP_GRPH_RED_CROSSBAR; + +/* + * UNP_GRPH_GREEN_CROSSBAR enum + */ + +typedef enum UNP_GRPH_GREEN_CROSSBAR { +UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y = 0x00000000, +UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C = 0x00000001, +UNP_UNP_GRPH_GREEN_CROSSBAR_A = 0x00000002, +UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr = 0x00000003, +} UNP_GRPH_GREEN_CROSSBAR; + +/* + * UNP_GRPH_BLUE_CROSSBAR enum + */ + +typedef enum UNP_GRPH_BLUE_CROSSBAR { +UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C = 0x00000000, +UNP_GRPH_BLUE_CROSSBAR_A = 0x00000001, +UNP_GRPH_BLUE_CROSSBAR_R_Cr = 0x00000002, +UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y = 0x00000003, +} UNP_GRPH_BLUE_CROSSBAR; + +/* + * UNP_GRPH_MODE_UPDATE_LOCKG enum + */ + +typedef enum UNP_GRPH_MODE_UPDATE_LOCKG { +UNP_GRPH_UPDATE_LOCK_0 = 0x00000000, +UNP_GRPH_UPDATE_LOCK_1 = 0x00000001, +} UNP_GRPH_MODE_UPDATE_LOCKG; + +/* + * UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK enum + */ + +typedef enum UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK { +UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0 = 0x00000000, +UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1 = 0x00000001, +} UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK; + +/* + * UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE enum + */ + +typedef enum UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE { +UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0 = 0x00000000, +UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1 = 0x00000001, +} UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE; + +/* + * UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE enum + */ + +typedef enum UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE { +UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0 = 0x00000000, +UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1 = 0x00000001, +} UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE; + +/* + * UNP_GRPH_STEREOSYNC_FLIP_EN enum + */ + +typedef enum UNP_GRPH_STEREOSYNC_FLIP_EN { +UNP_GRPH_STEREOSYNC_FLIP_DISABLE = 0x00000000, +UNP_GRPH_STEREOSYNC_FLIP_ENABLE = 0x00000001, +} UNP_GRPH_STEREOSYNC_FLIP_EN; + +/* + * UNP_GRPH_STEREOSYNC_FLIP_MODE enum + */ + +typedef enum UNP_GRPH_STEREOSYNC_FLIP_MODE { +UNP_GRPH_STEREOSYNC_FLIP_MODE_0 = 0x00000000, +UNP_GRPH_STEREOSYNC_FLIP_MODE_1 = 0x00000001, +UNP_GRPH_STEREOSYNC_FLIP_MODE_2 = 0x00000002, +UNP_GRPH_STEREOSYNC_FLIP_MODE_3 = 0x00000003, +} UNP_GRPH_STEREOSYNC_FLIP_MODE; + +/* + * UNP_GRPH_STACK_INTERLACE_FLIP_EN enum + */ + +typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_EN { +UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE = 0x00000000, +UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE = 0x00000001, +} UNP_GRPH_STACK_INTERLACE_FLIP_EN; + +/* + * UNP_GRPH_STACK_INTERLACE_FLIP_MODE enum + */ + +typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_MODE { +UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0 = 0x00000000, +UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1 = 0x00000001, +UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2 = 0x00000002, +UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3 = 0x00000003, +} UNP_GRPH_STACK_INTERLACE_FLIP_MODE; + +/* + * UNP_GRPH_STEREOSYNC_SELECT_DISABLE enum + */ + +typedef enum UNP_GRPH_STEREOSYNC_SELECT_DISABLE { +UNP_GRPH_STEREOSYNC_SELECT_EN = 0x00000000, +UNP_GRPH_STEREOSYNC_SELECT_DIS = 0x00000001, +} UNP_GRPH_STEREOSYNC_SELECT_DISABLE; + +/* + * UNP_CRC_SOURCE_SEL enum + */ + +typedef enum UNP_CRC_SOURCE_SEL { +UNP_CRC_SOURCE_SEL_NP_TO_LBV = 0x00000000, +UNP_CRC_SOURCE_SEL_LOWER32 = 0x00000001, +UNP_CRC_SOURCE_SEL_RESERVED = 0x00000002, +UNP_CRC_SOURCE_SEL_LOWER16 = 0x00000003, +UNP_CRC_SOURCE_SEL_UNP_TO_LBV = 0x00000004, +} UNP_CRC_SOURCE_SEL; + +/* + * UNP_CRC_LINE_SEL enum + */ + +typedef enum UNP_CRC_LINE_SEL { +UNP_CRC_LINE_SEL_RESERVED = 0x00000000, +UNP_CRC_LINE_SEL_EVEN_ONLY = 0x00000001, +UNP_CRC_LINE_SEL_ODD_ONLY = 0x00000002, +UNP_CRC_LINE_SEL_ODD_EVEN = 0x00000003, +} UNP_CRC_LINE_SEL; + +/* + * UNP_ROTATION_ANGLE enum + */ + +typedef enum UNP_ROTATION_ANGLE { +UNP_ROTATION_ANGLE_0 = 0x00000000, +UNP_ROTATION_ANGLE_90 = 0x00000001, +UNP_ROTATION_ANGLE_180 = 0x00000002, +UNP_ROTATION_ANGLE_270 = 0x00000003, +UNP_ROTATION_ANGLE_0m = 0x00000004, +UNP_ROTATION_ANGLE_90m = 0x00000005, +UNP_ROTATION_ANGLE_180m = 0x00000006, +UNP_ROTATION_ANGLE_270m = 0x00000007, +} UNP_ROTATION_ANGLE; + +/* + * UNP_PIXEL_DROP enum + */ + +typedef enum UNP_PIXEL_DROP { +UNP_PIXEL_NO_DROP = 0x00000000, +UNP_PIXEL_DROPPING = 0x00000001, +} UNP_PIXEL_DROP; + +/* + * UNP_BUFFER_MODE enum + */ + +typedef enum UNP_BUFFER_MODE { +UNP_BUFFER_MODE_LUMA = 0x00000000, +UNP_BUFFER_MODE_LUMA_CHROMA = 0x00000001, +} UNP_BUFFER_MODE; + +/******************************************************* + * DP Enums + *******************************************************/ + +/* + * DP_LINK_TRAINING_COMPLETE enum + */ + +typedef enum DP_LINK_TRAINING_COMPLETE { +DP_LINK_TRAINING_NOT_COMPLETE = 0x00000000, +DP_LINK_TRAINING_ALREADY_COMPLETE = 0x00000001, +} DP_LINK_TRAINING_COMPLETE; + +/* + * DP_EMBEDDED_PANEL_MODE enum + */ + +typedef enum DP_EMBEDDED_PANEL_MODE { +DP_EXTERNAL_PANEL = 0x00000000, +DP_EMBEDDED_PANEL = 0x00000001, +} DP_EMBEDDED_PANEL_MODE; + +/* + * DP_PIXEL_ENCODING enum + */ + +typedef enum DP_PIXEL_ENCODING { +DP_PIXEL_ENCODING_RGB444 = 0x00000000, +DP_PIXEL_ENCODING_YCBCR422 = 0x00000001, +DP_PIXEL_ENCODING_YCBCR444 = 0x00000002, +DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x00000003, +DP_PIXEL_ENCODING_Y_ONLY = 0x00000004, +DP_PIXEL_ENCODING_YCBCR420 = 0x00000005, +DP_PIXEL_ENCODING_RESERVED = 0x00000006, +} DP_PIXEL_ENCODING; + +/* + * DP_DYN_RANGE enum + */ + +typedef enum DP_DYN_RANGE { +DP_DYN_VESA_RANGE = 0x00000000, +DP_DYN_CEA_RANGE = 0x00000001, +} DP_DYN_RANGE; + +/* + * DP_YCBCR_RANGE enum + */ + +typedef enum DP_YCBCR_RANGE { +DP_YCBCR_RANGE_BT601_5 = 0x00000000, +DP_YCBCR_RANGE_BT709_5 = 0x00000001, +} DP_YCBCR_RANGE; + +/* + * DP_COMPONENT_DEPTH enum + */ + +typedef enum DP_COMPONENT_DEPTH { +DP_COMPONENT_DEPTH_6BPC = 0x00000000, +DP_COMPONENT_DEPTH_8BPC = 0x00000001, +DP_COMPONENT_DEPTH_10BPC = 0x00000002, +DP_COMPONENT_DEPTH_12BPC = 0x00000003, +DP_COMPONENT_DEPTH_16BPC_RESERVED = 0x00000004, +DP_COMPONENT_DEPTH_RESERVED = 0x00000005, +} DP_COMPONENT_DEPTH; + +/* + * DP_MSA_MISC0_OVERRIDE_ENABLE enum + */ + +typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE { +MSA_MISC0_OVERRIDE_DISABLE = 0x00000000, +MSA_MISC0_OVERRIDE_ENABLE = 0x00000001, +} DP_MSA_MISC0_OVERRIDE_ENABLE; + +/* + * DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE enum + */ + +typedef enum DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE { +MSA_MISC1_BIT7_OVERRIDE_DISABLE = 0x00000000, +MSA_MISC1_BIT7_OVERRIDE_ENABLE = 0x00000001, +} DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE; + +/* + * DP_UDI_LANES enum + */ + +typedef enum DP_UDI_LANES { +DP_UDI_1_LANE = 0x00000000, +DP_UDI_2_LANES = 0x00000001, +DP_UDI_LANES_RESERVED = 0x00000002, +DP_UDI_4_LANES = 0x00000003, +} DP_UDI_LANES; + +/* + * DP_VID_STREAM_DIS_DEFER enum + */ + +typedef enum DP_VID_STREAM_DIS_DEFER { +DP_VID_STREAM_DIS_NO_DEFER = 0x00000000, +DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 0x00000001, +DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x00000002, +} DP_VID_STREAM_DIS_DEFER; + +/* + * DP_STEER_OVERFLOW_ACK enum + */ + +typedef enum DP_STEER_OVERFLOW_ACK { +DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0x00000000, +DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001, +} DP_STEER_OVERFLOW_ACK; + +/* + * DP_STEER_OVERFLOW_MASK enum + */ + +typedef enum DP_STEER_OVERFLOW_MASK { +DP_STEER_OVERFLOW_MASKED = 0x00000000, +DP_STEER_OVERFLOW_UNMASK = 0x00000001, +} DP_STEER_OVERFLOW_MASK; + +/* + * DP_TU_OVERFLOW_ACK enum + */ + +typedef enum DP_TU_OVERFLOW_ACK { +DP_TU_OVERFLOW_ACK_NO_EFFECT = 0x00000000, +DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001, +} DP_TU_OVERFLOW_ACK; + +/* + * DPHY_ALT_SCRAMBLER_RESET_EN enum + */ + +typedef enum DPHY_ALT_SCRAMBLER_RESET_EN { +DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE = 0x00000000, +DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION = 0x00000001, +} DPHY_ALT_SCRAMBLER_RESET_EN; + +/* + * DPHY_ALT_SCRAMBLER_RESET_SEL enum + */ + +typedef enum DPHY_ALT_SCRAMBLER_RESET_SEL { +DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE = 0x00000000, +DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE = 0x00000001, +} DPHY_ALT_SCRAMBLER_RESET_SEL; + +/* + * DP_VID_TIMING_MODE enum + */ + +typedef enum DP_VID_TIMING_MODE { +DP_VID_TIMING_MODE_ASYNC = 0x00000000, +DP_VID_TIMING_MODE_SYNC = 0x00000001, +} DP_VID_TIMING_MODE; + +/* + * DP_VID_M_N_DOUBLE_BUFFER_MODE enum + */ + +typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE { +DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x00000000, +DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 0x00000001, +} DP_VID_M_N_DOUBLE_BUFFER_MODE; + +/* + * DP_VID_M_N_GEN_EN enum + */ + +typedef enum DP_VID_M_N_GEN_EN { +DP_VID_M_N_PROGRAMMED_VIA_REG = 0x00000000, +DP_VID_M_N_CALC_AUTO = 0x00000001, +} DP_VID_M_N_GEN_EN; + +/* + * DP_VID_M_DOUBLE_VALUE_EN enum + */ + +typedef enum DP_VID_M_DOUBLE_VALUE_EN { +DP_VID_M_INPUT_PIXEL_RATE = 0x00000000, +DP_VID_M_DOUBLE_INPUT_PIXEL_RATE = 0x00000001, +} DP_VID_M_DOUBLE_VALUE_EN; + +/* + * DP_VID_ENHANCED_FRAME_MODE enum + */ + +typedef enum DP_VID_ENHANCED_FRAME_MODE { +VID_NORMAL_FRAME_MODE = 0x00000000, +VID_ENHANCED_MODE = 0x00000001, +} DP_VID_ENHANCED_FRAME_MODE; + +/* + * DP_VID_MSA_TOP_FIELD_MODE enum + */ + +typedef enum DP_VID_MSA_TOP_FIELD_MODE { +DP_TOP_FIELD_ONLY = 0x00000000, +DP_TOP_PLUS_BOTTOM_FIELD = 0x00000001, +} DP_VID_MSA_TOP_FIELD_MODE; + +/* + * DP_VID_VBID_FIELD_POL enum + */ + +typedef enum DP_VID_VBID_FIELD_POL { +DP_VID_VBID_FIELD_POL_NORMAL = 0x00000000, +DP_VID_VBID_FIELD_POL_INV = 0x00000001, +} DP_VID_VBID_FIELD_POL; + +/* + * DP_VID_STREAM_DISABLE_ACK enum + */ + +typedef enum DP_VID_STREAM_DISABLE_ACK { +ID_STREAM_DISABLE_NO_ACK = 0x00000000, +ID_STREAM_DISABLE_ACKED = 0x00000001, +} DP_VID_STREAM_DISABLE_ACK; + +/* + * DP_VID_STREAM_DISABLE_MASK enum + */ + +typedef enum DP_VID_STREAM_DISABLE_MASK { +VID_STREAM_DISABLE_MASKED = 0x00000000, +VID_STREAM_DISABLE_UNMASK = 0x00000001, +} DP_VID_STREAM_DISABLE_MASK; + +/* + * DPHY_ATEST_SEL_LANE0 enum + */ + +typedef enum DPHY_ATEST_SEL_LANE0 { +DPHY_ATEST_LANE0_PRBS_PATTERN = 0x00000000, +DPHY_ATEST_LANE0_REG_PATTERN = 0x00000001, +} DPHY_ATEST_SEL_LANE0; + +/* + * DPHY_ATEST_SEL_LANE1 enum + */ + +typedef enum DPHY_ATEST_SEL_LANE1 { +DPHY_ATEST_LANE1_PRBS_PATTERN = 0x00000000, +DPHY_ATEST_LANE1_REG_PATTERN = 0x00000001, +} DPHY_ATEST_SEL_LANE1; + +/* + * DPHY_ATEST_SEL_LANE2 enum + */ + +typedef enum DPHY_ATEST_SEL_LANE2 { +DPHY_ATEST_LANE2_PRBS_PATTERN = 0x00000000, +DPHY_ATEST_LANE2_REG_PATTERN = 0x00000001, +} DPHY_ATEST_SEL_LANE2; + +/* + * DPHY_ATEST_SEL_LANE3 enum + */ + +typedef enum DPHY_ATEST_SEL_LANE3 { +DPHY_ATEST_LANE3_PRBS_PATTERN = 0x00000000, +DPHY_ATEST_LANE3_REG_PATTERN = 0x00000001, +} DPHY_ATEST_SEL_LANE3; + +/* + * DPHY_SCRAMBLER_SEL enum + */ + +typedef enum DPHY_SCRAMBLER_SEL { +DPHY_SCRAMBLER_SEL_LANE_DATA = 0x00000000, +DPHY_SCRAMBLER_SEL_DBG_DATA = 0x00000001, +} DPHY_SCRAMBLER_SEL; + +/* + * DPHY_BYPASS enum + */ + +typedef enum DPHY_BYPASS { +DPHY_8B10B_OUTPUT = 0x00000000, +DPHY_DBG_OUTPUT = 0x00000001, +} DPHY_BYPASS; + +/* + * DPHY_SKEW_BYPASS enum + */ + +typedef enum DPHY_SKEW_BYPASS { +DPHY_WITH_SKEW = 0x00000000, +DPHY_NO_SKEW = 0x00000001, +} DPHY_SKEW_BYPASS; + +/* + * DPHY_TRAINING_PATTERN_SEL enum + */ + +typedef enum DPHY_TRAINING_PATTERN_SEL { +DPHY_TRAINING_PATTERN_1 = 0x00000000, +DPHY_TRAINING_PATTERN_2 = 0x00000001, +DPHY_TRAINING_PATTERN_3 = 0x00000002, +DPHY_TRAINING_PATTERN_4 = 0x00000003, +} DPHY_TRAINING_PATTERN_SEL; + +/* + * DPHY_8B10B_RESET enum + */ + +typedef enum DPHY_8B10B_RESET { +DPHY_8B10B_NOT_RESET = 0x00000000, +DPHY_8B10B_RESETET = 0x00000001, +} DPHY_8B10B_RESET; + +/* + * DP_DPHY_8B10B_EXT_DISP enum + */ + +typedef enum DP_DPHY_8B10B_EXT_DISP { +DP_DPHY_8B10B_EXT_DISP_ZERO = 0x00000000, +DP_DPHY_8B10B_EXT_DISP_ONE = 0x00000001, +} DP_DPHY_8B10B_EXT_DISP; + +/* + * DPHY_8B10B_CUR_DISP enum + */ + +typedef enum DPHY_8B10B_CUR_DISP { +DPHY_8B10B_CUR_DISP_ZERO = 0x00000000, +DPHY_8B10B_CUR_DISP_ONE = 0x00000001, +} DPHY_8B10B_CUR_DISP; + +/* + * DPHY_PRBS_EN enum + */ + +typedef enum DPHY_PRBS_EN { +DPHY_PRBS_DISABLE = 0x00000000, +DPHY_PRBS_ENABLE = 0x00000001, +} DPHY_PRBS_EN; + +/* + * DPHY_PRBS_SEL enum + */ + +typedef enum DPHY_PRBS_SEL { +DPHY_PRBS7_SELECTED = 0x00000000, +DPHY_PRBS23_SELECTED = 0x00000001, +DPHY_PRBS11_SELECTED = 0x00000002, +} DPHY_PRBS_SEL; + +/* + * DPHY_SCRAMBLER_DIS enum + */ + +typedef enum DPHY_SCRAMBLER_DIS { +DPHY_SCR_ENABLED = 0x00000000, +DPHY_SCR_DISABLED = 0x00000001, +} DPHY_SCRAMBLER_DIS; + +/* + * DPHY_SCRAMBLER_ADVANCE enum + */ + +typedef enum DPHY_SCRAMBLER_ADVANCE { +DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY = 0x00000000, +DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL = 0x00000001, +} DPHY_SCRAMBLER_ADVANCE; + +/* + * DPHY_SCRAMBLER_KCODE enum + */ + +typedef enum DPHY_SCRAMBLER_KCODE { +DPHY_SCRAMBLER_KCODE_DISABLED = 0x00000000, +DPHY_SCRAMBLER_KCODE_ENABLED = 0x00000001, +} DPHY_SCRAMBLER_KCODE; + +/* + * DPHY_LOAD_BS_COUNT_START enum + */ + +typedef enum DPHY_LOAD_BS_COUNT_START { +DPHY_LOAD_BS_COUNT_STARTED = 0x00000000, +DPHY_LOAD_BS_COUNT_NOT_STARTED = 0x00000001, +} DPHY_LOAD_BS_COUNT_START; + +/* + * DPHY_CRC_EN enum + */ + +typedef enum DPHY_CRC_EN { +DPHY_CRC_DISABLED = 0x00000000, +DPHY_CRC_ENABLED = 0x00000001, +} DPHY_CRC_EN; + +/* + * DPHY_CRC_CONT_EN enum + */ + +typedef enum DPHY_CRC_CONT_EN { +DPHY_CRC_ONE_SHOT = 0x00000000, +DPHY_CRC_CONTINUOUS = 0x00000001, +} DPHY_CRC_CONT_EN; + +/* + * DPHY_CRC_FIELD enum + */ + +typedef enum DPHY_CRC_FIELD { +DPHY_CRC_START_FROM_TOP_FIELD = 0x00000000, +DPHY_CRC_START_FROM_BOTTOM_FIELD = 0x00000001, +} DPHY_CRC_FIELD; + +/* + * DPHY_CRC_SEL enum + */ + +typedef enum DPHY_CRC_SEL { +DPHY_CRC_LANE0_SELECTED = 0x00000000, +DPHY_CRC_LANE1_SELECTED = 0x00000001, +DPHY_CRC_LANE2_SELECTED = 0x00000002, +DPHY_CRC_LANE3_SELECTED = 0x00000003, +} DPHY_CRC_SEL; + +/* + * DPHY_RX_FAST_TRAINING_CAPABLE enum + */ + +typedef enum DPHY_RX_FAST_TRAINING_CAPABLE { +DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0x00000000, +DPHY_FAST_TRAINING_CAPABLE = 0x00000001, +} DPHY_RX_FAST_TRAINING_CAPABLE; + +/* + * DP_SEC_COLLISION_ACK enum + */ + +typedef enum DP_SEC_COLLISION_ACK { +DP_SEC_COLLISION_ACK_NO_EFFECT = 0x00000000, +DP_SEC_COLLISION_ACK_CLR_FLAG = 0x00000001, +} DP_SEC_COLLISION_ACK; + +/* + * DP_SEC_AUDIO_MUTE enum + */ + +typedef enum DP_SEC_AUDIO_MUTE { +DP_SEC_AUDIO_MUTE_HW_CTRL = 0x00000000, +DP_SEC_AUDIO_MUTE_SW_CTRL = 0x00000001, +} DP_SEC_AUDIO_MUTE; + +/* + * DP_SEC_TIMESTAMP_MODE enum + */ + +typedef enum DP_SEC_TIMESTAMP_MODE { +DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0x00000000, +DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 0x00000001, +} DP_SEC_TIMESTAMP_MODE; + +/* + * DP_SEC_ASP_PRIORITY enum + */ + +typedef enum DP_SEC_ASP_PRIORITY { +DP_SEC_ASP_LOW_PRIORITY = 0x00000000, +DP_SEC_ASP_HIGH_PRIORITY = 0x00000001, +} DP_SEC_ASP_PRIORITY; + +/* + * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum + */ + +typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE { +DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0x00000000, +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x00000001, +} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE; + +/* + * DP_MSE_SAT_UPDATE_ACT enum + */ + +typedef enum DP_MSE_SAT_UPDATE_ACT { +DP_MSE_SAT_UPDATE_NO_ACTION = 0x00000000, +DP_MSE_SAT_UPDATE_WITH_TRIGGER = 0x00000001, +DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 0x00000002, +} DP_MSE_SAT_UPDATE_ACT; + +/* + * DP_MSE_LINK_LINE enum + */ + +typedef enum DP_MSE_LINK_LINE { +DP_MSE_LINK_LINE_32_MTP_LONG = 0x00000000, +DP_MSE_LINK_LINE_64_MTP_LONG = 0x00000001, +DP_MSE_LINK_LINE_128_MTP_LONG = 0x00000002, +DP_MSE_LINK_LINE_256_MTP_LONG = 0x00000003, +} DP_MSE_LINK_LINE; + +/* + * DP_MSE_BLANK_CODE enum + */ + +typedef enum DP_MSE_BLANK_CODE { +DP_MSE_BLANK_CODE_SF_FILLED = 0x00000000, +DP_MSE_BLANK_CODE_ZERO_FILLED = 0x00000001, +} DP_MSE_BLANK_CODE; + +/* + * DP_MSE_TIMESTAMP_MODE enum + */ + +typedef enum DP_MSE_TIMESTAMP_MODE { +DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0x00000000, +DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 0x00000001, +} DP_MSE_TIMESTAMP_MODE; + +/* + * DP_MSE_ZERO_ENCODER enum + */ + +typedef enum DP_MSE_ZERO_ENCODER { +DP_MSE_NOT_ZERO_FE_ENCODER = 0x00000000, +DP_MSE_ZERO_FE_ENCODER = 0x00000001, +} DP_MSE_ZERO_ENCODER; + +/* + * DP_MSE_OUTPUT_DPDBG_DATA enum + */ + +typedef enum DP_MSE_OUTPUT_DPDBG_DATA { +DP_MSE_OUTPUT_DPDBG_DATA_DIS = 0x00000000, +DP_MSE_OUTPUT_DPDBG_DATA_EN = 0x00000001, +} DP_MSE_OUTPUT_DPDBG_DATA; + +/* + * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum + */ + +typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE { +DP_DPHY_HBR2_PASS_THROUGH = 0x00000000, +DP_DPHY_HBR2_PATTERN_1 = 0x00000001, +DP_DPHY_HBR2_PATTERN_2_NEG = 0x00000002, +DP_DPHY_HBR2_PATTERN_3 = 0x00000003, +DP_DPHY_HBR2_PATTERN_2_POS = 0x00000006, +} DP_DPHY_HBR2_PATTERN_CONTROL_MODE; + +/* + * DPHY_CRC_MST_PHASE_ERROR_ACK enum + */ + +typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK { +DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0x00000000, +DPHY_CRC_MST_PHASE_ERROR_ACKED = 0x00000001, +} DPHY_CRC_MST_PHASE_ERROR_ACK; + +/* + * DPHY_SW_FAST_TRAINING_START enum + */ + +typedef enum DPHY_SW_FAST_TRAINING_START { +DPHY_SW_FAST_TRAINING_NOT_STARTED = 0x00000000, +DPHY_SW_FAST_TRAINING_STARTED = 0x00000001, +} DPHY_SW_FAST_TRAINING_START; + +/* + * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum + */ + +typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN { +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0x00000000, +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x00000001, +} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN; + +/* + * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum + */ + +typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK { +DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0x00000000, +DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 0x00000001, +} DP_DPHY_FAST_TRAINING_COMPLETE_MASK; + +/* + * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum + */ + +typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK { +DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0x00000000, +DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 0x00000001, +} DP_DPHY_FAST_TRAINING_COMPLETE_ACK; + +/* + * DP_MSA_V_TIMING_OVERRIDE_EN enum + */ + +typedef enum DP_MSA_V_TIMING_OVERRIDE_EN { +MSA_V_TIMING_OVERRIDE_DISABLED = 0x00000000, +MSA_V_TIMING_OVERRIDE_ENABLED = 0x00000001, +} DP_MSA_V_TIMING_OVERRIDE_EN; + +/* + * DP_SEC_GSP0_PRIORITY enum + */ + +typedef enum DP_SEC_GSP0_PRIORITY { +SEC_GSP0_PRIORITY_LOW = 0x00000000, +SEC_GSP0_PRIORITY_HIGH = 0x00000001, +} DP_SEC_GSP0_PRIORITY; + +/* + * DP_SEC_GSP0_SEND enum + */ + +typedef enum DP_SEC_GSP0_SEND { +NOT_SENT = 0x00000000, +FORCE_SENT = 0x00000001, +} DP_SEC_GSP0_SEND; + +/******************************************************* + * COL_MAN Enums + *******************************************************/ + +/* + * COL_MAN_UPDATE_LOCK enum + */ + +typedef enum COL_MAN_UPDATE_LOCK { +COL_MAN_UPDATE_UNLOCKED = 0x00000000, +COL_MAN_UPDATE_LOCKED = 0x00000001, +} COL_MAN_UPDATE_LOCK; + +/* + * COL_MAN_DISABLE_MULTIPLE_UPDATE enum + */ + +typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE { +COL_MAN_MULTIPLE_UPDATE = 0x00000000, +COL_MAN_MULTIPLE_UPDAT_EDISABLE = 0x00000001, +} COL_MAN_DISABLE_MULTIPLE_UPDATE; + +/* + * COL_MAN_INPUTCSC_MODE enum + */ + +typedef enum COL_MAN_INPUTCSC_MODE { +INPUTCSC_MODE_BYPASS = 0x00000000, +INPUTCSC_MODE_A = 0x00000001, +INPUTCSC_MODE_B = 0x00000002, +INPUTCSC_MODE_UNITY = 0x00000003, +} COL_MAN_INPUTCSC_MODE; + +/* + * COL_MAN_INPUTCSC_TYPE enum + */ + +typedef enum COL_MAN_INPUTCSC_TYPE { +INPUTCSC_TYPE_12_0 = 0x00000000, +INPUTCSC_TYPE_10_2 = 0x00000001, +INPUTCSC_TYPE_8_4 = 0x00000002, +} COL_MAN_INPUTCSC_TYPE; + +/* + * COL_MAN_INPUTCSC_CONVERT enum + */ + +typedef enum COL_MAN_INPUTCSC_CONVERT { +INPUTCSC_ROUND = 0x00000000, +INPUTCSC_TRUNCATE = 0x00000001, +} COL_MAN_INPUTCSC_CONVERT; + +/* + * COL_MAN_PRESCALE_MODE enum + */ + +typedef enum COL_MAN_PRESCALE_MODE { +PRESCALE_MODE_BYPASS = 0x00000000, +PRESCALE_MODE_PROGRAM = 0x00000001, +PRESCALE_MODE_UNITY = 0x00000002, +} COL_MAN_PRESCALE_MODE; + +/* + * COL_MAN_INPUT_GAMMA_MODE enum + */ + +typedef enum COL_MAN_INPUT_GAMMA_MODE { +INGAMMA_MODE_BYPASS = 0x00000000, +INGAMMA_MODE_FIX = 0x00000001, +INGAMMA_MODE_FLOAT = 0x00000002, +} COL_MAN_INPUT_GAMMA_MODE; + +/* + * COL_MAN_OUTPUT_CSC_MODE enum + */ + +typedef enum COL_MAN_OUTPUT_CSC_MODE { +COL_MAN_OUTPUT_CSC_BYPASS = 0x00000000, +COL_MAN_OUTPUT_CSC_RGB = 0x00000001, +COL_MAN_OUTPUT_CSC_YCrCb601 = 0x00000002, +COL_MAN_OUTPUT_CSC_YCrCb709 = 0x00000003, +COL_MAN_OUTPUT_CSC_A = 0x00000004, +COL_MAN_OUTPUT_CSC_B = 0x00000005, +COL_MAN_OUTPUT_CSC_UNITY = 0x00000006, +} COL_MAN_OUTPUT_CSC_MODE; + +/* + * COL_MAN_DENORM_CLAMP_CONTROL enum + */ + +typedef enum COL_MAN_DENORM_CLAMP_CONTROL { +DENORM_CLAMP_MODE_UNITY = 0x00000000, +DENORM_CLAMP_MODE_8 = 0x00000001, +DENORM_CLAMP_MODE_10 = 0x00000002, +DENORM_CLAMP_MODE_12 = 0x00000003, +} COL_MAN_DENORM_CLAMP_CONTROL; + +/* + * COL_MAN_REGAMMA_MODE_CONTROL enum + */ + +typedef enum COL_MAN_REGAMMA_MODE_CONTROL { +COL_MAN_REGAMMA_MODE_BYPASS = 0x00000000, +COL_MAN_REGAMMA_MODE_ROM_A = 0x00000001, +COL_MAN_REGAMMA_MODE_ROM_B = 0x00000002, +COL_MAN_REGAMMA_MODE_A = 0x00000003, +COL_MAN_REGAMMA_MODE_B = 0x00000004, +} COL_MAN_REGAMMA_MODE_CONTROL; + +/* + * COL_MAN_GLOBAL_PASSTHROUGH_ENABLE enum + */ + +typedef enum COL_MAN_GLOBAL_PASSTHROUGH_ENABLE { +CM_GLOBAL_PASSTHROUGH_DISBALE = 0x00000000, +CM_GLOBAL_PASSTHROUGH_ENABLE = 0x00000001, +} COL_MAN_GLOBAL_PASSTHROUGH_ENABLE; + +/* + * COL_MAN_DEGAMMA_MODE enum + */ + +typedef enum COL_MAN_DEGAMMA_MODE { +DEGAMMA_MODE_BYPASS = 0x00000000, +DEGAMMA_MODE_A = 0x00000001, +DEGAMMA_MODE_B = 0x00000002, +} COL_MAN_DEGAMMA_MODE; + +/* + * COL_MAN_GAMUT_REMAP_MODE enum + */ + +typedef enum COL_MAN_GAMUT_REMAP_MODE { +GAMUT_REMAP_MODE_BYPASS = 0x00000000, +GAMUT_REMAP_MODE_1 = 0x00000001, +GAMUT_REMAP_MODE_2 = 0x00000002, +GAMUT_REMAP_MODE_3 = 0x00000003, +} COL_MAN_GAMUT_REMAP_MODE; + +/******************************************************* + * MCIF_WB Enums + *******************************************************/ + +/******************************************************* + * DP_AUX Enums + *******************************************************/ + +/* + * DP_AUX_CONTROL_HPD_SEL enum + */ + +typedef enum DP_AUX_CONTROL_HPD_SEL { +DP_AUX_CONTROL_HPD1_SELECTED = 0x00000000, +DP_AUX_CONTROL_HPD2_SELECTED = 0x00000001, +DP_AUX_CONTROL_HPD3_SELECTED = 0x00000002, +DP_AUX_CONTROL_HPD4_SELECTED = 0x00000003, +DP_AUX_CONTROL_HPD5_SELECTED = 0x00000004, +DP_AUX_CONTROL_HPD6_SELECTED = 0x00000005, +} DP_AUX_CONTROL_HPD_SEL; + +/* + * DP_AUX_CONTROL_TEST_MODE enum + */ + +typedef enum DP_AUX_CONTROL_TEST_MODE { +DP_AUX_CONTROL_TEST_MODE_DISABLE = 0x00000000, +DP_AUX_CONTROL_TEST_MODE_ENABLE = 0x00000001, +} DP_AUX_CONTROL_TEST_MODE; + +/* + * DP_AUX_SW_CONTROL_SW_GO enum + */ + +typedef enum DP_AUX_SW_CONTROL_SW_GO { +DP_AUX_SW_CONTROL_SW__NOT_GO = 0x00000000, +DP_AUX_SW_CONTROL_SW__GO = 0x00000001, +} DP_AUX_SW_CONTROL_SW_GO; + +/* + * DP_AUX_SW_CONTROL_LS_READ_TRIG enum + */ + +typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG { +DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0x00000000, +DP_AUX_SW_CONTROL_LS_READ__TRIG = 0x00000001, +} DP_AUX_SW_CONTROL_LS_READ_TRIG; + +/* + * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum + */ + +typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY { +DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0x00000000, +DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 0x00000001, +DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x00000002, +DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 0x00000003, +} DP_AUX_ARB_CONTROL_ARB_PRIORITY; + +/* + * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum + */ + +typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ { +DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0x00000000, +DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 0x00000001, +} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ; + +/* + * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum + */ + +typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG { +DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x00000000, +DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 0x00000001, +} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG; + +/* + * DP_AUX_INT_ACK enum + */ + +typedef enum DP_AUX_INT_ACK { +DP_AUX_INT__NOT_ACK = 0x00000000, +DP_AUX_INT__ACK = 0x00000001, +} DP_AUX_INT_ACK; + +/* + * DP_AUX_LS_UPDATE_ACK enum + */ + +typedef enum DP_AUX_LS_UPDATE_ACK { +DP_AUX_INT_LS_UPDATE_NOT_ACK = 0x00000000, +DP_AUX_INT_LS_UPDATE_ACK = 0x00000001, +} DP_AUX_LS_UPDATE_ACK; + +/* + * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum + */ + +typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL { +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0x00000000, +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 0x00000001, +} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL; + +/* + * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum + */ + +typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE { +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x00000000, +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x00000001, +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x00000002, +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x00000003, +} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE; + +/* + * DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN enum + */ + +typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN { +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US = 0x00000000, +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US = 0x00000001, +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US = 0x00000002, +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US = 0x00000003, +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US = 0x00000004, +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US = 0x00000005, +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US = 0x00000006, +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US = 0x00000007, +} DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN; + +/* + * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum + */ + +typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY { +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x00000000, +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 0x00000001, +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 0x00000002, +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 0x00000003, +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 0x00000004, +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 0x00000005, +} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY; + +/* + * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum + */ + +typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW { +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x00000000, +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x00000001, +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x00000002, +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 0x00000003, +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 0x00000004, +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 0x00000005, +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 0x00000006, +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 0x00000007, +} DP_AUX_DPHY_RX_CONTROL_START_WINDOW; + +/* + * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum + */ + +typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW { +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0x00000000, +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 0x00000001, +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 0x00000002, +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 0x00000003, +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 0x00000004, +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 0x00000005, +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 0x00000006, +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 0x00000007, +} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW; + +/* + * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum + */ + +typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN { +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0x00000000, +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 0x00000001, +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 0x00000002, +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 0x00000003, +} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN; + +/* + * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum + */ + +typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT { +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000000, +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000001, +} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; + +/* + * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum + */ + +typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START { +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0x00000000, +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 0x00000001, +} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START; + +/* + * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum + */ + +typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP { +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0x00000000, +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 0x00000001, +} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP; + +/* + * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum + */ + +typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN { +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0x00000000, +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 0x00000001, +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 0x00000002, +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 0x00000003, +} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN; + +/* + * DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN enum + */ + +typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN { +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US = 0x00000000, +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US = 0x00000001, +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US = 0x00000002, +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US = 0x00000003, +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US = 0x00000004, +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US = 0x00000005, +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US = 0x00000006, +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US = 0x00000007, +} DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN; + +/* + * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum + */ + +typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD { +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0x00000000, +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 0x00000001, +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x00000002, +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 0x00000003, +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 0x00000004, +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 0x00000005, +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 0x00000006, +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 0x00000007, +} DP_AUX_DPHY_RX_DETECTION_THRESHOLD; + +/* + * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum + */ + +typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ { +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0x00000000, +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 0x00000001, +} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ; + +/* + * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum + */ + +typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW { +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0x00000000, +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 0x00000001, +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 0x00000002, +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 0x00000003, +} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW; + +/* + * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum + */ + +typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT { +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0x00000000, +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 0x00000001, +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 0x00000002, +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 0x00000003, +} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT; + +/* + * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum + */ + +typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN { +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0x00000000, +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 0x00000001, +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 0x00000002, +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 0x00000003, +} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN; + +/* + * DP_AUX_ERR_OCCURRED_ACK enum + */ + +typedef enum DP_AUX_ERR_OCCURRED_ACK { +DP_AUX_ERR_OCCURRED__NOT_ACK = 0x00000000, +DP_AUX_ERR_OCCURRED__ACK = 0x00000001, +} DP_AUX_ERR_OCCURRED_ACK; + +/* + * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum + */ + +typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK { +DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0x00000000, +DP_AUX_POTENTIAL_ERR_REACHED__ACK = 0x00000001, +} DP_AUX_POTENTIAL_ERR_REACHED_ACK; + +/* + * DP_AUX_DEFINITE_ERR_REACHED_ACK enum + */ + +typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK { +ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x00000000, +ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 0x00000001, +} DP_AUX_DEFINITE_ERR_REACHED_ACK; + +/* + * DP_AUX_RESET enum + */ + +typedef enum DP_AUX_RESET { +DP_AUX_RESET_DEASSERTED = 0x00000000, +DP_AUX_RESET_ASSERTED = 0x00000001, +} DP_AUX_RESET; + +/* + * DP_AUX_RESET_DONE enum + */ + +typedef enum DP_AUX_RESET_DONE { +DP_AUX_RESET_SEQUENCE_NOT_DONE = 0x00000000, +DP_AUX_RESET_SEQUENCE_DONE = 0x00000001, +} DP_AUX_RESET_DONE; + +/******************************************************* + * DSI Enums + *******************************************************/ + +/* + * DSI_COMMAND_MODE_SRC_FORMAT enum + */ + +typedef enum DSI_COMMAND_MODE_SRC_FORMAT { +DSI_COMMAND_SRC_FORMAT_RGB8BIT = 0x00000002, +DSI_COMMAND_SRC_FORMAT_RGB332 = 0x00000003, +DSI_COMMAND_SRC_FORMAT_RGB444 = 0x00000004, +DSI_COMMAND_SRC_FORMAT_RGB555 = 0x00000005, +DSI_COMMAND_SRC_FORMAT_RGB565 = 0x00000006, +DSI_COMMAND_SRC_FORMAT_RGB888 = 0x00000008, +} DSI_COMMAND_MODE_SRC_FORMAT; + +/* + * DSI_COMMAND_MODE_DST_FORMAT enum + */ + +typedef enum DSI_COMMAND_MODE_DST_FORMAT { +DSI_COMMAND_DST_FORMAT_RGB111 = 0x00000000, +DSI_COMMAND_DST_FORMAT_RGB332 = 0x00000003, +DSI_COMMAND_DST_FORMAT_RGB444 = 0x00000004, +DSI_COMMAND_DST_FORMAT_RGB565 = 0x00000006, +DSI_COMMAND_DST_FORMAT_RGB666 = 0x00000007, +DSI_COMMAND_DST_FORMAT_RGB888 = 0x00000008, +} DSI_COMMAND_MODE_DST_FORMAT; + +/* + * DSI_FLAG_CLR enum + */ + +typedef enum DSI_FLAG_CLR { +DSI_FLAG_NO_CLEAR = 0x00000000, +DSI_FLAG_CLEAR = 0x00000001, +} DSI_FLAG_CLR; + +/* + * DSI_BIT_SWAP enum + */ + +typedef enum DSI_BIT_SWAP { +DSI_BIT_SWAP_DISABLE = 0x00000000, +DSI_BIT_SWAP_ENABLE = 0x00000001, +} DSI_BIT_SWAP; + +/* + * DSI_CLK_GATING enum + */ + +typedef enum DSI_CLK_GATING { +DSI_CLK_GATING_ENABLE = 0x00000000, +DSI_CLK_GATING_DISABLE = 0x00000001, +} DSI_CLK_GATING; + +/* + * DSI_LANE_ULPS_REQUEST enum + */ + +typedef enum DSI_LANE_ULPS_REQUEST { +DSI_LANE_ULPS_REQUEST_DEASSERT = 0x00000000, +DSI_LANE_ULPS_REQUEST_ASSERT = 0x00000001, +} DSI_LANE_ULPS_REQUEST; + +/* + * DSI_LANE_ULPS_EXIT enum + */ + +typedef enum DSI_LANE_ULPS_EXIT { +DSI_LANE_ULPS_EXIT_DEASSERT = 0x00000000, +DSI_LANE_ULPS_EXIT_ASSERT = 0x00000001, +} DSI_LANE_ULPS_EXIT; + +/* + * DSI_LANE_FORCE_TX_STOP enum + */ + +typedef enum DSI_LANE_FORCE_TX_STOP { +DSI_LANE_FORCE_TX_STOP_DEASSERT = 0x00000000, +DSI_LANE_FORCE_TX_STOP_ASSERT = 0x00000001, +} DSI_LANE_FORCE_TX_STOP; + +/* + * DSI_CLOCK_LANE_HS_FORCE_REQUEST enum + */ + +typedef enum DSI_CLOCK_LANE_HS_FORCE_REQUEST { +DSI_CLOCK_LANE_HS_FORCE_REQUEST_DEASSERT = 0x00000000, +DSI_CLOCK_LANE_HS_FORCE_REQUEST_ASSERT = 0x00000001, +} DSI_CLOCK_LANE_HS_FORCE_REQUEST; + +/* + * DSI_CONTROLLER_EN enum + */ + +typedef enum DSI_CONTROLLER_EN { +DSI_CONTROLLER_DISABLE = 0x00000000, +DSI_CONTROLLER_ENABLE = 0x00000001, +} DSI_CONTROLLER_EN; + +/* + * DSI_VIDEO_MODE_EN enum + */ + +typedef enum DSI_VIDEO_MODE_EN { +DSI_VIDEO_MODE_DISABLE = 0x00000000, +DSI_VIDEO_MODE_ENABLE = 0x00000001, +} DSI_VIDEO_MODE_EN; + +/* + * DSI_CMD_MODE_EN enum + */ + +typedef enum DSI_CMD_MODE_EN { +DSI_CMD_MODE_DISABLE = 0x00000000, +DSI_CMD_MODE_ENABLE = 0x00000001, +} DSI_CMD_MODE_EN; + +/* + * DSI_DATA_LANE0_EN enum + */ + +typedef enum DSI_DATA_LANE0_EN { +DSI_DATA_LANE0_DISABLE = 0x00000000, +DSI_DATA_LANE0_ENABLE = 0x00000001, +} DSI_DATA_LANE0_EN; + +/* + * DSI_DATA_LANE1_EN enum + */ + +typedef enum DSI_DATA_LANE1_EN { +DSI_DATA_LANE1_DISABLE = 0x00000000, +DSI_DATA_LANE1_ENABLE = 0x00000001, +} DSI_DATA_LANE1_EN; + +/* + * DSI_DATA_LANE2_EN enum + */ + +typedef enum DSI_DATA_LANE2_EN { +DSI_DATA_LANE2_DISABLE = 0x00000000, +DSI_DATA_LANE2_ENABLE = 0x00000001, +} DSI_DATA_LANE2_EN; + +/* + * DSI_DATA_LANE3_EN enum + */ + +typedef enum DSI_DATA_LANE3_EN { +DSI_DATA_LANE3_DISABLE = 0x00000000, +DSI_DATA_LANE3_ENABLE = 0x00000001, +} DSI_DATA_LANE3_EN; + +/* + * DSI_CLOCK_LANE_EN enum + */ + +typedef enum DSI_CLOCK_LANE_EN { +DSI_CLOCK_LANE_DISABLE = 0x00000000, +DSI_CLOCK_LANE_ENABLE = 0x00000001, +} DSI_CLOCK_LANE_EN; + +/* + * DSI_PHY_DATA_LANE0_EN enum + */ + +typedef enum DSI_PHY_DATA_LANE0_EN { +DSI_PHY_DATA_LANE0_DISABLE = 0x00000000, +DSI_PHY_DATA_LANE0_ENABLE = 0x00000001, +} DSI_PHY_DATA_LANE0_EN; + +/* + * DSI_PHY_DATA_LANE1_EN enum + */ + +typedef enum DSI_PHY_DATA_LANE1_EN { +DSI_PHY_DATA_LANE1_DISABLE = 0x00000000, +DSI_PHY_DATA_LANE1_ENABLE = 0x00000001, +} DSI_PHY_DATA_LANE1_EN; + +/* + * DSI_PHY_DATA_LANE2_EN enum + */ + +typedef enum DSI_PHY_DATA_LANE2_EN { +DSI_PHY_DATA_LANE2_DISABLE = 0x00000000, +DSI_PHY_DATA_LANE2_ENABLE = 0x00000001, +} DSI_PHY_DATA_LANE2_EN; + +/* + * DSI_PHY_DATA_LANE3_EN enum + */ + +typedef enum DSI_PHY_DATA_LANE3_EN { +DSI_PHY_DATA_LANE3_DISABLE = 0x00000000, +DSI_PHY_DATA_LANE3_ENABLE = 0x00000001, +} DSI_PHY_DATA_LANE3_EN; + +/* + * DSI_RESET_DISPCLK enum + */ + +typedef enum DSI_RESET_DISPCLK { +DSI_NO_RESET_ON_DISPCLK_DOMAIN_LOGIC = 0x00000000, +DSI_RESET_ON_DISPCLK_DOMAIN_LOGIC = 0x00000001, +} DSI_RESET_DISPCLK; + +/* + * DSI_RESET_DSICLK enum + */ + +typedef enum DSI_RESET_DSICLK { +DSI_NO_RESET_ON_DSICLK_DOMAIN_LOGIC = 0x00000000, +DSI_RESET_ON_DSICLK_DOMAIN_LOGIC = 0x00000001, +} DSI_RESET_DSICLK; + +/* + * DSI_RESET_BYTECLK enum + */ + +typedef enum DSI_RESET_BYTECLK { +DSI_NO_RESET_ON_BYTECLK_DOMAIN_LOGIC = 0x00000000, +DSI_RESET_ON_BYTECLK_DOMAIN_LOGIC = 0x00000001, +} DSI_RESET_BYTECLK; + +/* + * DSI_RESET_ESCCLK enum + */ + +typedef enum DSI_RESET_ESCCLK { +DSI_NO_RESET_ON_ESCCLK_DOMAIN_LOGIC = 0x00000000, +DSI_RESET_ON_ESCCLK_DOMAIN_LOGIC = 0x00000001, +} DSI_RESET_ESCCLK; + +/* + * DSI_CRTC_SEL enum + */ + +typedef enum DSI_CRTC_SEL { +DSI_GET_PIXEL_STREAM_FROM_FMT0 = 0x00000000, +DSI_GET_PIXEL_STREAM_FROM_FMT1 = 0x00000001, +DSI_GET_PIXEL_STREAM_FROM_FMT2 = 0x00000002, +DSI_GET_PIXEL_STREAM_FROM_FMT3 = 0x00000003, +DSI_GET_PIXEL_STREAM_FROM_FMT4 = 0x00000004, +DSI_GET_PIXEL_STREAM_FROM_FMT5 = 0x00000005, +} DSI_CRTC_SEL; + +/* + * DSI_PACKET_BYTE_MSB_LSB_FLIP enum + */ + +typedef enum DSI_PACKET_BYTE_MSB_LSB_FLIP { +DSI_PACKET_BYTE_MSB_LSB_FLIP_NO_SWAP = 0x00000000, +DSI_PACKET_BYTE_MSB_LSB_FLIP_SWAP = 0x00000001, +} DSI_PACKET_BYTE_MSB_LSB_FLIP; + +/* + * DSI_VIDEO_MODE_DST_FORMAT enum + */ + +typedef enum DSI_VIDEO_MODE_DST_FORMAT { +DSI_VIDEO_DST_FORMAT_RGB565 = 0x00000000, +DSI_VIDEO_DST_FORMAT_RGB666_PACKED = 0x00000001, +DSI_VIDEO_DST_FORMAT_RGB666_LOOSELY_PACKED = 0x00000002, +DSI_VIDEO_DST_FORMAT_RGB888 = 0x00000003, +} DSI_VIDEO_MODE_DST_FORMAT; + +/* + * DSI_VIDEO_TRAFFIC_MODE enum + */ + +typedef enum DSI_VIDEO_TRAFFIC_MODE { +DSI_TRAFFIC_MODE_SYNC_PULSES = 0x00000000, +DSI_TRAFFIC_MODE_SYNC_EVENTS = 0x00000001, +DSI_TRAFFIC_MODE_BURST = 0x00000002, +DSI_TRAFFIC_MODE_RESERVED = 0x00000003, +} DSI_VIDEO_TRAFFIC_MODE; + +/* + * DSI_VIDEO_BLLP_PWR_MODE enum + */ + +typedef enum DSI_VIDEO_BLLP_PWR_MODE { +DSI_VIDEO_BLLP_PWR_MODE_HS = 0x00000000, +DSI_VIDEO_BLLP_PWR_MODE_LP = 0x00000001, +} DSI_VIDEO_BLLP_PWR_MODE; + +/* + * DSI_VIDEO_EOF_BLLP_PWR_MODE enum + */ + +typedef enum DSI_VIDEO_EOF_BLLP_PWR_MODE { +DSI_VIDEO_EOF_BLLP_PWR_MODE_HS = 0x00000000, +DSI_VIDEO_EOF_BLLP_PWR_MODE_LP = 0x00000001, +} DSI_VIDEO_EOF_BLLP_PWR_MODE; + +/* + * DSI_VIDEO_PWR_MODE enum + */ + +typedef enum DSI_VIDEO_PWR_MODE { +DSI_VIDEO_PWR_MODE_HS = 0x00000000, +DSI_VIDEO_PWR_MODE_LP = 0x00000001, +} DSI_VIDEO_PWR_MODE; + +/* + * DSI_VIDEO_PULSE_MODE_OPT enum + */ + +typedef enum DSI_VIDEO_PULSE_MODE_OPT { +PULSE_MODE_OPT_NO_HSA = 0x00000000, +PULSE_MODE_OPT_SEND = 0x00000001, +} DSI_VIDEO_PULSE_MODE_OPT; + +/* + * DSI_RGB_SWAP enum + */ + +typedef enum DSI_RGB_SWAP { +DSI_SWAP_RGB = 0x00000000, +DSI_SWAP_RBG = 0x00000001, +DSI_SWAP_BGR = 0x00000002, +DSI_SWAP_BRG = 0x00000003, +DSI_SWAP_GRB = 0x00000004, +DSI_SWAP_GBR = 0x00000005, +} DSI_RGB_SWAP; + +/* + * DSI_CMD_PACKET_TYPE enum + */ + +typedef enum DSI_CMD_PACKET_TYPE { +DSI_CMD_PACKET_TYPE_SHORT = 0x00000000, +DSI_CMD_PACKET_TYPE_LONG = 0x00000001, +} DSI_CMD_PACKET_TYPE; + +/* + * DSI_CMD_PWR_MODE enum + */ + +typedef enum DSI_CMD_PWR_MODE { +DSI_CMD_PWR_MODE_HS = 0x00000000, +DSI_CMD_PWR_MODE_LP = 0x00000001, +} DSI_CMD_PWR_MODE; + +/* + * DSI_CMD_EMBEDDED_MODE enum + */ + +typedef enum DSI_CMD_EMBEDDED_MODE { +CMD_EMBEDDED_MODE_DISABLE = 0x00000000, +CMD_EMBEDDED_MODE_ENABLE = 0x00000001, +} DSI_CMD_EMBEDDED_MODE; + +/* + * DSI_CMD_ORDER enum + */ + +typedef enum DSI_CMD_ORDER { +DSI_CMD_ORDER_COMMAND_FIRST = 0x00000000, +DSI_CMD_ORDER_DATA_FIRST = 0x00000001, +} DSI_CMD_ORDER; + +/* + * DSI_DATA_BUFFER_ID enum + */ + +typedef enum DSI_DATA_BUFFER_ID { +DSI_DATA_BUFFER_OFFSET0 = 0x00000000, +DSI_DATA_BUFFER_OFFSET1 = 0x00000001, +} DSI_DATA_BUFFER_ID; + +/* + * DSI_DWORD_BYTE_SWAP enum + */ + +typedef enum DSI_DWORD_BYTE_SWAP { +DWORD_BYTE_SWAP_NO_SWAP = 0x00000000, +DWORD_BYTE_SWAP_BYTE_SWAP = 0x00000001, +DWORD_BYTE_SWAP_WORD_SWAP = 0x00000002, +DWORD_BYTE_SWAP_BOTH_SWAP = 0x00000003, +} DSI_DWORD_BYTE_SWAP; + +/* + * DSI_INSERT_DCS_COMMAND enum + */ + +typedef enum DSI_INSERT_DCS_COMMAND { +DSI_INSERT_DCS_COMMAND_DISABLE = 0x00000000, +DSI_INSERT_DCS_COMMAND_ENABLE = 0x00000001, +} DSI_INSERT_DCS_COMMAND; + +/* + * DSI_DMAFIFO_WRITE_WATERMARK enum + */ + +typedef enum DSI_DMAFIFO_WRITE_WATERMARK { +DSI_DMAFIFO_WRITE_WATERMARK_HALF = 0x00000000, +DSI_DMAFIFO_WRITE_WATERMARK_FOURTH = 0x00000001, +DSI_DMAFIFO_WRITE_WATERMARK_EIGHTH = 0x00000002, +DSI_DMAFIFO_WRITE_WATERMARK_SIXTEENTH = 0x00000003, +} DSI_DMAFIFO_WRITE_WATERMARK; + +/* + * DSI_DMAFIFO_READ_WATERMARK enum + */ + +typedef enum DSI_DMAFIFO_READ_WATERMARK { +DSI_DMAFIFO_READ_WATERMARK_HALF = 0x00000000, +DSI_DMAFIFO_READ_WATERMARK_FOURTH = 0x00000001, +DSI_DMAFIFO_READ_WATERMARK_EIGHTH = 0x00000002, +DSI_DMAFIFO_READ_WATERMARK_SIXTEENTH = 0x00000003, +} DSI_DMAFIFO_READ_WATERMARK; + +/* + * DSI_USE_DENG_LENGTH enum + */ + +typedef enum DSI_USE_DENG_LENGTH { +DSI_USE_DENG_LENGTH_DISABLE = 0x00000000, +DSI_USE_DENG_LENGTH_ENABLE = 0x00000001, +} DSI_USE_DENG_LENGTH; + +/* + * DSI_COMMAND_TRIGGER_MODE enum + */ + +typedef enum DSI_COMMAND_TRIGGER_MODE { +DSI_COMMAND_TRIGGER_MODE_AUTO = 0x00000000, +DSI_COMMAND_TRIGGER_MODE_MANUAL = 0x00000001, +} DSI_COMMAND_TRIGGER_MODE; + +/* + * DSI_COMMAND_TRIGGER_SEL enum + */ + +typedef enum DSI_COMMAND_TRIGGER_SEL { +DSI_COMMAND_TRIGGER_SEL_NONE = 0x00000000, +DSI_COMMAND_TRIGGER_SEL_CRTC = 0x00000001, +DSI_COMMAND_TRIGGER_SEL_TE = 0x00000002, +DSI_COMMAND_TRIGGER_SEL_HW = 0x00000003, +} DSI_COMMAND_TRIGGER_SEL; + +/* + * DSI_HW_SOURCE_SEL enum + */ + +typedef enum DSI_HW_SOURCE_SEL { +HW_SOURCE_SEL_NONE = 0x00000000, +HW_SOURCE_SEL_DSC_VUP = 0x00000001, +HW_SOURCE_SEL_DSC_VLP = 0x00000002, +HW_SOURCE_SEL_DSC_JPEG = 0x00000003, +} DSI_HW_SOURCE_SEL; + +/* + * DSI_COMMAND_TRIGGER_ORDER enum + */ + +typedef enum DSI_COMMAND_TRIGGER_ORDER { +DSI_COMMAND_TRIGGER_ORDER_DMA = 0x00000000, +DSI_COMMAND_TRIGGER_ORDER_DENG = 0x00000001, +} DSI_COMMAND_TRIGGER_ORDER; + +/* + * DSI_TE_SRC_SEL enum + */ + +typedef enum DSI_TE_SRC_SEL { +DSI_TE_SEL_LINK = 0x00000000, +DSI_TE_SEL_PIN = 0x00000001, +} DSI_TE_SRC_SEL; + +/* + * DSI_EXT_TE_MUX enum + */ + +typedef enum DSI_EXT_TE_MUX { +DSI_XT_TE_MUX_LCDD17 = 0x00000000, +DSI_XT_TE_MUX_DCLK = 0x00000001, +DSI_XT_TE_MUX_SS = 0x00000002, +DSI_XT_TE_MUX_GCLK = 0x00000003, +DSI_XT_TE_MUX_GOE = 0x00000004, +DSI_XT_TE_MUX_DINV = 0x00000005, +DSI_XT_TE_MUX_FRAME = 0x00000006, +DSI_XT_TE_MUX_GPIO4 = 0x00000007, +DSI_XT_TE_MUX_GPIO5 = 0x00000008, +} DSI_EXT_TE_MUX; + +/* + * DSI_EXT_TE_MODE enum + */ + +typedef enum DSI_EXT_TE_MODE { +DSI_EXT_TE_MODE_VSYNC_EDGE = 0x00000000, +DSI_EXT_TE_MODE_VSYNC_WIDTH = 0x00000001, +DSI_EXT_TE_MODE_HVSYNC_EDGE = 0x00000002, +DSI_EXT_TE_MODE_HVSYNC_WIDTH = 0x00000003, +} DSI_EXT_TE_MODE; + +/* + * DSI_EXT_RESET_POL enum + */ + +typedef enum DSI_EXT_RESET_POL { +DSI_EXT_RESET_POL_HIGH = 0x00000000, +DSI_EXT_RESET_POL_LOW = 0x00000001, +} DSI_EXT_RESET_POL; + +/* + * DSI_EXT_TE_POL enum + */ + +typedef enum DSI_EXT_TE_POL { +DSI_EXT_TE_POL_RISING = 0x00000000, +DSI_EXT_TE_POL_FALLING = 0x00000001, +} DSI_EXT_TE_POL; + +/* + * DSI_RESET_PANEL enum + */ + +typedef enum DSI_RESET_PANEL { +DSI_RESET_PANEL_DEASSERT = 0x00000000, +DSI_RESET_PANEL_ASSERT = 0x00000001, +} DSI_RESET_PANEL; + +/* + * DSI_CRC_ENABLE enum + */ + +typedef enum DSI_CRC_ENABLE { +DSI_CRC_CAL_DISABLE = 0x00000000, +DSI_CRC_CAL_ENABLE = 0x00000001, +} DSI_CRC_ENABLE; + +/* + * DSI_TX_EOT_APPEND enum + */ + +typedef enum DSI_TX_EOT_APPEND { +DSI_TX_EOT_APPEND_DISABLE = 0x00000000, +DSI_TX_EOT_APPEND_ENABLE = 0x00000001, +} DSI_TX_EOT_APPEND; + +/* + * DSI_RX_EOT_IGNORE enum + */ + +typedef enum DSI_RX_EOT_IGNORE { +DSI_RX_EOT_IGNORE_DISABLE = 0x00000000, +DSI_RX_EOT_IGNORE_ENABLE = 0x00000001, +} DSI_RX_EOT_IGNORE; + +/* + * DSI_MIPI_BIST_RESET enum + */ + +typedef enum DSI_MIPI_BIST_RESET { +DSI_MIPI_BIST_RESET_DEASSERT = 0x00000000, +DSI_MIPI_BIST_RESET_ASSERT = 0x00000001, +} DSI_MIPI_BIST_RESET; + +/* + * DSI_MIPI_BIST_VIDEO_FRMT enum + */ + +typedef enum DSI_MIPI_BIST_VIDEO_FRMT { +DSI_MIPI_BIST_VIDEO_FRMT_YUV422 = 0x00000000, +DSI_MIPI_BIST_VIDEO_FRMT_RAW8 = 0x00000001, +} DSI_MIPI_BIST_VIDEO_FRMT; + +/* + * DSI_MIPI_BIST_START enum + */ + +typedef enum DSI_MIPI_BIST_START { +DSI_MIPI_BIST_START_DEASSERT = 0x00000000, +DSI_MIPI_BIST_START_ASSERT = 0x00000001, +} DSI_MIPI_BIST_START; + +/* + * DSI_DBG_CLK_SEL enum + */ + +typedef enum DSI_DBG_CLK_SEL { +DSI_TEST_CLK_SEL_DISPCLK_P = 0x00000000, +DSI_TEST_CLK_SEL_DISPCLK_G = 0x00000001, +DSI_TEST_CLK_SEL_DISPCLK_R = 0x00000002, +DSI_TEST_CLK_SEL_ESCCLK_G = 0x00000003, +DSI_TEST_CLK_SEL_BYTECLK_G = 0x00000004, +DSI_TEST_CLK_SEL_DSICLK_P = 0x00000005, +DSI_TEST_CLK_SEL_DSICLK_R = 0x00000006, +DSI_TEST_CLK_SEL_DSICLK_G = 0x00000007, +DSI_TEST_CLK_SEL_DSICLK_TRN = 0x00000008, +} DSI_DBG_CLK_SEL; + +/* + * DSI_DENG_FIFO_USE_OVERWRITE_LEVEL enum + */ + +typedef enum DSI_DENG_FIFO_USE_OVERWRITE_LEVEL { +DSI_DENG_FIFO_LEVEL_OVERWRITE = 0x00000000, +DSI_DENG_FIFO_LEVEL_CAL_AVERAGE = 0x00000001, +} DSI_DENG_FIFO_USE_OVERWRITE_LEVEL; + +/* + * DSI_DENG_FIFO_FORCE_RECAL_AVERAGE enum + */ + +typedef enum DSI_DENG_FIFO_FORCE_RECAL_AVERAGE { +DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_DEASSERT = 0x00000000, +DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_ASSERT = 0x00000001, +} DSI_DENG_FIFO_FORCE_RECAL_AVERAGE; + +/* + * DSI_DENG_FIFO_FORCE_RECOMP_MINMAX enum + */ + +typedef enum DSI_DENG_FIFO_FORCE_RECOMP_MINMAX { +DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_DEASSERT = 0x00000000, +DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_ASSERT = 0x00000001, +} DSI_DENG_FIFO_FORCE_RECOMP_MINMAX; + +/* + * DSI_DENG_FIFO_START enum + */ + +typedef enum DSI_DENG_FIFO_START { +DSI_DENG_FIFO_START_DEASSERT = 0x00000000, +DSI_DENG_FIFO_START_ASSERT = 0x00000001, +} DSI_DENG_FIFO_START; + +/* + * DSI_USE_CMDFIFO enum + */ + +typedef enum DSI_USE_CMDFIFO { +DSI_CMD_USE_DMAFIFO = 0x00000000, +DSI_CMD_USE_CMDFIFO = 0x00000001, +} DSI_USE_CMDFIFO; + +/* + * DSI_CRTC_FREEZE_TRIG enum + */ + +typedef enum DSI_CRTC_FREEZE_TRIG { +DSI_CRTC_FREEZE_TRIG_DEASSERT = 0x00000000, +DSI_CRTC_FREEZE_TRIG_ASSERT = 0x00000001, +} DSI_CRTC_FREEZE_TRIG; + +/* + * DSI_PERF_LATENCY_SEL enum + */ + +typedef enum DSI_PERF_LATENCY_SEL { +DSI_PERF_LATENCY_SEL_DATA_LANE0 = 0x00000000, +DSI_PERF_LATENCY_SEL_DATA_LANE1 = 0x00000001, +DSI_PERF_LATENCY_SEL_DATA_LANE2 = 0x00000002, +DSI_PERF_LATENCY_SEL_DATA_LANE3 = 0x00000003, +} DSI_PERF_LATENCY_SEL; + +/* + * DSI_DEBUG_DSICLK_SEL enum + */ + +typedef enum DSI_DEBUG_DSICLK_SEL { +DSI_DEBUG_DSICLK_SEL_VIDEO_ENGINE = 0x00000000, +DSI_DEBUG_DSICLK_SEL_CMD_ENGINE = 0x00000001, +DSI_DEBUG_DSICLK_SEL_RESYNC_FIFO = 0x00000002, +DSI_DEBUG_DSICLK_SEL_CMDFIFO = 0x00000003, +DSI_DEBUG_DSICLK_SEL_CMDBUFFER = 0x00000004, +DSI_DEBUG_DSICLK_SEL_AFIFO = 0x00000005, +DSI_DEBUG_DSICLK_SEL_LANECTRL = 0x00000006, +} DSI_DEBUG_DSICLK_SEL; + +/* + * DSI_DEBUG_BYTECLK_SEL enum + */ + +typedef enum DSI_DEBUG_BYTECLK_SEL { +DSI_DEBUG_BYTECLK_SEL_AFIFO = 0x00000000, +DSI_DEBUG_BYTECLK_SEL_LANEFIFO0 = 0x00000001, +DSI_DEBUG_BYTECLK_SEL_LANEFIFO1 = 0x00000002, +DSI_DEBUG_BYTECLK_SEL_LANEFIFO2 = 0x00000003, +DSI_DEBUG_BYTECLK_SEL_LANEFIFO3 = 0x00000004, +DSI_DEBUG_BYTECLK_SEL_LANEBUF0 = 0x00000005, +DSI_DEBUG_BYTECLK_SEL_LANEBUF1 = 0x00000006, +DSI_DEBUG_BYTECLK_SEL_LANEBUF2 = 0x00000007, +DSI_DEBUG_BYTECLK_SEL_LANEBUF3 = 0x00000008, +DSI_DEBUG_BYTECLK_SEL_PINGPONG0 = 0x00000009, +DSI_DEBUG_BYTECLK_SEL_PINGPONG1 = 0x0000000a, +DSI_DEBUG_BYTECLK_SEL_PINGPING2 = 0x0000000b, +DSI_DEBUG_BYTECLK_SEL_PINGPING3 = 0x0000000c, +DSI_DEBUG_BYTECLK_SEL_EOT = 0x0000000d, +DSI_DEBUG_BYTECLK_SEL_LANECTRL = 0x0000000e, +} DSI_DEBUG_BYTECLK_SEL; + +/******************************************************* + * DCIO_CHIP Enums + *******************************************************/ + +/* + * DCIOCHIP_HPD_SEL enum + */ + +typedef enum DCIOCHIP_HPD_SEL { +DCIOCHIP_HPD_SEL_ASYNC = 0x00000000, +DCIOCHIP_HPD_SEL_CLOCKED = 0x00000001, +} DCIOCHIP_HPD_SEL; + +/* + * DCIOCHIP_PAD_MODE enum + */ + +typedef enum DCIOCHIP_PAD_MODE { +DCIOCHIP_PAD_MODE_DDC = 0x00000000, +DCIOCHIP_PAD_MODE_DP = 0x00000001, +} DCIOCHIP_PAD_MODE; + +/* + * DCIOCHIP_AUXSLAVE_PAD_MODE enum + */ + +typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE { +DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0x00000000, +DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 0x00000001, +} DCIOCHIP_AUXSLAVE_PAD_MODE; + +/* + * DCIOCHIP_INVERT enum + */ + +typedef enum DCIOCHIP_INVERT { +DCIOCHIP_POL_NON_INVERT = 0x00000000, +DCIOCHIP_POL_INVERT = 0x00000001, +} DCIOCHIP_INVERT; + +/* + * DCIOCHIP_PD_EN enum + */ + +typedef enum DCIOCHIP_PD_EN { +DCIOCHIP_PD_EN_NOTALLOW = 0x00000000, +DCIOCHIP_PD_EN_ALLOW = 0x00000001, +} DCIOCHIP_PD_EN; + +/* + * DCIOCHIP_GPIO_MASK_EN enum + */ + +typedef enum DCIOCHIP_GPIO_MASK_EN { +DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x00000000, +DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x00000001, +} DCIOCHIP_GPIO_MASK_EN; + +/* + * DCIOCHIP_MASK enum + */ + +typedef enum DCIOCHIP_MASK { +DCIOCHIP_MASK_DISABLE = 0x00000000, +DCIOCHIP_MASK_ENABLE = 0x00000001, +} DCIOCHIP_MASK; + +/* + * DCIOCHIP_GPIO_I2C_MASK enum + */ + +typedef enum DCIOCHIP_GPIO_I2C_MASK { +DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0x00000000, +DCIOCHIP_GPIO_I2C_MASK_ENABLE = 0x00000001, +} DCIOCHIP_GPIO_I2C_MASK; + +/* + * DCIOCHIP_GPIO_I2C_DRIVE enum + */ + +typedef enum DCIOCHIP_GPIO_I2C_DRIVE { +DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0x00000000, +DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 0x00000001, +} DCIOCHIP_GPIO_I2C_DRIVE; + +/* + * DCIOCHIP_GPIO_I2C_EN enum + */ + +typedef enum DCIOCHIP_GPIO_I2C_EN { +DCIOCHIP_GPIO_I2C_DISABLE = 0x00000000, +DCIOCHIP_GPIO_I2C_ENABLE = 0x00000001, +} DCIOCHIP_GPIO_I2C_EN; + +/* + * DCIOCHIP_MASK_4BIT enum + */ + +typedef enum DCIOCHIP_MASK_4BIT { +DCIOCHIP_MASK_4BIT_DISABLE = 0x00000000, +DCIOCHIP_MASK_4BIT_ENABLE = 0x0000000f, +} DCIOCHIP_MASK_4BIT; + +/* + * DCIOCHIP_ENABLE_4BIT enum + */ + +typedef enum DCIOCHIP_ENABLE_4BIT { +DCIOCHIP_4BIT_DISABLE = 0x00000000, +DCIOCHIP_4BIT_ENABLE = 0x0000000f, +} DCIOCHIP_ENABLE_4BIT; + +/* + * DCIOCHIP_MASK_5BIT enum + */ + +typedef enum DCIOCHIP_MASK_5BIT { +DCIOCHIP_MASIK_5BIT_DISABLE = 0x00000000, +DCIOCHIP_MASIK_5BIT_ENABLE = 0x0000001f, +} DCIOCHIP_MASK_5BIT; + +/* + * DCIOCHIP_ENABLE_5BIT enum + */ + +typedef enum DCIOCHIP_ENABLE_5BIT { +DCIOCHIP_5BIT_DISABLE = 0x00000000, +DCIOCHIP_5BIT_ENABLE = 0x0000001f, +} DCIOCHIP_ENABLE_5BIT; + +/* + * DCIOCHIP_MASK_2BIT enum + */ + +typedef enum DCIOCHIP_MASK_2BIT { +DCIOCHIP_MASK_2BIT_DISABLE = 0x00000000, +DCIOCHIP_MASK_2BIT_ENABLE = 0x00000003, +} DCIOCHIP_MASK_2BIT; + +/* + * DCIOCHIP_ENABLE_2BIT enum + */ + +typedef enum DCIOCHIP_ENABLE_2BIT { +DCIOCHIP_2BIT_DISABLE = 0x00000000, +DCIOCHIP_2BIT_ENABLE = 0x00000003, +} DCIOCHIP_ENABLE_2BIT; + +/* + * DCIOCHIP_REF_27_SRC_SEL enum + */ + +typedef enum DCIOCHIP_REF_27_SRC_SEL { +DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x00000000, +DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x00000001, +DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x00000002, +DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x00000003, +} DCIOCHIP_REF_27_SRC_SEL; + +/* + * DCIOCHIP_DVO_VREFPON enum + */ + +typedef enum DCIOCHIP_DVO_VREFPON { +DCIOCHIP_DVO_VREFPON_DISABLE = 0x00000000, +DCIOCHIP_DVO_VREFPON_ENABLE = 0x00000001, +} DCIOCHIP_DVO_VREFPON; + +/* + * DCIOCHIP_DVO_VREFSEL enum + */ + +typedef enum DCIOCHIP_DVO_VREFSEL { +DCIOCHIP_DVO_VREFSEL_ONCHIP = 0x00000000, +DCIOCHIP_DVO_VREFSEL_EXTERNAL = 0x00000001, +} DCIOCHIP_DVO_VREFSEL; + +/* + * DCIOCHIP_SPDIF1_IMODE enum + */ + +typedef enum DCIOCHIP_SPDIF1_IMODE { +DCIOCHIP_SPDIF1_IMODE_OE_A = 0x00000000, +DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO = 0x00000001, +} DCIOCHIP_SPDIF1_IMODE; + +/* + * DCIOCHIP_AUX_FALLSLEWSEL enum + */ + +typedef enum DCIOCHIP_AUX_FALLSLEWSEL { +DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0x00000000, +DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 0x00000001, +DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 0x00000002, +DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 0x00000003, +} DCIOCHIP_AUX_FALLSLEWSEL; + +/* + * DCIOCHIP_AUX_SPIKESEL enum + */ + +typedef enum DCIOCHIP_AUX_SPIKESEL { +DCIOCHIP_AUX_SPIKESEL_50NS = 0x00000000, +DCIOCHIP_AUX_SPIKESEL_10NS = 0x00000001, +} DCIOCHIP_AUX_SPIKESEL; + +/* + * DCIOCHIP_AUX_CSEL0P9 enum + */ + +typedef enum DCIOCHIP_AUX_CSEL0P9 { +DCIOCHIP_AUX_CSEL_DEC1P0 = 0x00000000, +DCIOCHIP_AUX_CSEL_DEC0P9 = 0x00000001, +} DCIOCHIP_AUX_CSEL0P9; + +/* + * DCIOCHIP_AUX_CSEL1P1 enum + */ + +typedef enum DCIOCHIP_AUX_CSEL1P1 { +DCIOCHIP_AUX_CSEL_INC1P0 = 0x00000000, +DCIOCHIP_AUX_CSEL_INC1P1 = 0x00000001, +} DCIOCHIP_AUX_CSEL1P1; + +/* + * DCIOCHIP_AUX_RSEL0P9 enum + */ + +typedef enum DCIOCHIP_AUX_RSEL0P9 { +DCIOCHIP_AUX_RSEL_DEC1P0 = 0x00000000, +DCIOCHIP_AUX_RSEL_DEC0P9 = 0x00000001, +} DCIOCHIP_AUX_RSEL0P9; + +/* + * DCIOCHIP_AUX_RSEL1P1 enum + */ + +typedef enum DCIOCHIP_AUX_RSEL1P1 { +DCIOCHIP_AUX_RSEL_INC1P0 = 0x00000000, +DCIOCHIP_AUX_RSEL_INC1P1 = 0x00000001, +} DCIOCHIP_AUX_RSEL1P1; + +/******************************************************* + * AZCONTROLLER Enums + *******************************************************/ + +/* + * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum + */ + +typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL { +GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0x00000000, +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 0x00000001, +} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL; + +/* + * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum + */ + +typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED { +GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0x00000000, +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 0x00000001, +} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED; + +/* + * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum + */ + +typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS { +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0x00000000, +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 0x00000001, +} GENERIC_AZ_CONTROLLER_REGISTER_STATUS; + +/* + * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum + */ + +typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED { +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0x00000000, +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 0x00000001, +} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED; + +/* + * AZ_GLOBAL_CAPABILITIES enum + */ + +typedef enum AZ_GLOBAL_CAPABILITIES { +AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0x00000000, +AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 0x00000001, +} AZ_GLOBAL_CAPABILITIES; + +/* + * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum + */ + +typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE { +ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0x00000000, +ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 0x00000001, +} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE; + +/* + * GLOBAL_CONTROL_FLUSH_CONTROL enum + */ + +typedef enum GLOBAL_CONTROL_FLUSH_CONTROL { +FLUSH_CONTROL_FLUSH_NOT_STARTED = 0x00000000, +FLUSH_CONTROL_FLUSH_STARTED = 0x00000001, +} GLOBAL_CONTROL_FLUSH_CONTROL; + +/* + * GLOBAL_CONTROL_CONTROLLER_RESET enum + */ + +typedef enum GLOBAL_CONTROL_CONTROLLER_RESET { +CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0x00000000, +CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 0x00000001, +} GLOBAL_CONTROL_CONTROLLER_RESET; + +/* + * AZ_STATE_CHANGE_STATUS enum + */ + +typedef enum AZ_STATE_CHANGE_STATUS { +AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0x00000000, +AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 0x00000001, +} AZ_STATE_CHANGE_STATUS; + +/* + * GLOBAL_STATUS_FLUSH_STATUS enum + */ + +typedef enum GLOBAL_STATUS_FLUSH_STATUS { +GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0x00000000, +GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 0x00000001, +} GLOBAL_STATUS_FLUSH_STATUS; + +/* + * STREAM_0_SYNCHRONIZATION enum + */ + +typedef enum STREAM_0_SYNCHRONIZATION { +STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, +STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, +} STREAM_0_SYNCHRONIZATION; + +/* + * STREAM_1_SYNCHRONIZATION enum + */ + +typedef enum STREAM_1_SYNCHRONIZATION { +STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, +STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, +} STREAM_1_SYNCHRONIZATION; + +/* + * STREAM_2_SYNCHRONIZATION enum + */ + +typedef enum STREAM_2_SYNCHRONIZATION { +STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, +STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, +} STREAM_2_SYNCHRONIZATION; + +/* + * STREAM_3_SYNCHRONIZATION enum + */ + +typedef enum STREAM_3_SYNCHRONIZATION { +STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, +STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, +} STREAM_3_SYNCHRONIZATION; + +/* + * STREAM_4_SYNCHRONIZATION enum + */ + +typedef enum STREAM_4_SYNCHRONIZATION { +STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, +STREAM_4_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, +} STREAM_4_SYNCHRONIZATION; + +/* + * STREAM_5_SYNCHRONIZATION enum + */ + +typedef enum STREAM_5_SYNCHRONIZATION { +STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, +STREAM_5_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, +} STREAM_5_SYNCHRONIZATION; + +/* + * STREAM_6_SYNCHRONIZATION enum + */ + +typedef enum STREAM_6_SYNCHRONIZATION { +STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_6_SYNCHRONIZATION; + +/* + * STREAM_7_SYNCHRONIZATION enum + */ + +typedef enum STREAM_7_SYNCHRONIZATION { +STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_7_SYNCHRONIZATION; + +/* + * STREAM_8_SYNCHRONIZATION enum + */ + +typedef enum STREAM_8_SYNCHRONIZATION { +STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_8_SYNCHRONIZATION; + +/* + * STREAM_9_SYNCHRONIZATION enum + */ + +typedef enum STREAM_9_SYNCHRONIZATION { +STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_9_SYNCHRONIZATION; + +/* + * STREAM_10_SYNCHRONIZATION enum + */ + +typedef enum STREAM_10_SYNCHRONIZATION { +STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_10_SYNCHRONIZATION; + +/* + * STREAM_11_SYNCHRONIZATION enum + */ + +typedef enum STREAM_11_SYNCHRONIZATION { +STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_11_SYNCHRONIZATION; + +/* + * STREAM_12_SYNCHRONIZATION enum + */ + +typedef enum STREAM_12_SYNCHRONIZATION { +STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_12_SYNCHRONIZATION; + +/* + * STREAM_13_SYNCHRONIZATION enum + */ + +typedef enum STREAM_13_SYNCHRONIZATION { +STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_13_SYNCHRONIZATION; + +/* + * STREAM_14_SYNCHRONIZATION enum + */ + +typedef enum STREAM_14_SYNCHRONIZATION { +STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_14_SYNCHRONIZATION; + +/* + * STREAM_15_SYNCHRONIZATION enum + */ + +typedef enum STREAM_15_SYNCHRONIZATION { +STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, +STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, +} STREAM_15_SYNCHRONIZATION; + +/* + * CORB_READ_POINTER_RESET enum + */ + +typedef enum CORB_READ_POINTER_RESET { +CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0x00000000, +CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 0x00000001, +} CORB_READ_POINTER_RESET; + +/* + * AZ_CORB_SIZE enum + */ + +typedef enum AZ_CORB_SIZE { +AZ_CORB_SIZE_2ENTRIES_RESERVED = 0x00000000, +AZ_CORB_SIZE_16ENTRIES_RESERVED = 0x00000001, +AZ_CORB_SIZE_256ENTRIES = 0x00000002, +AZ_CORB_SIZE_RESERVED = 0x00000003, +} AZ_CORB_SIZE; + +/* + * AZ_RIRB_WRITE_POINTER_RESET enum + */ + +typedef enum AZ_RIRB_WRITE_POINTER_RESET { +AZ_RIRB_WRITE_POINTER_NOT_RESET = 0x00000000, +AZ_RIRB_WRITE_POINTER_DO_RESET = 0x00000001, +} AZ_RIRB_WRITE_POINTER_RESET; + +/* + * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum + */ + +typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL { +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000, +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001, +} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL; + +/* + * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum + */ + +typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL { +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000, +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001, +} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL; + +/* + * AZ_RIRB_SIZE enum + */ + +typedef enum AZ_RIRB_SIZE { +AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0x00000000, +AZ_RIRB_SIZE_16ENTRIES_RESERVED = 0x00000001, +AZ_RIRB_SIZE_256ENTRIES = 0x00000002, +AZ_RIRB_SIZE_UNDEFINED = 0x00000003, +} AZ_RIRB_SIZE; + +/* + * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum + */ + +typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID { +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0x00000000, +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 0x00000001, +} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID; + +/* + * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum + */ + +typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY { +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0x00000000, +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 0x00000001, +} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY; + +/* + * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum + */ + +typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE { +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0x00000000, +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 0x00000001, +} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE; + +/******************************************************* + * AZENDPOINT Enums + *******************************************************/ + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE { +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE { +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE { +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR { +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE { +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS { +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007, +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L { +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO { +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO { +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY { +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE { +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG { +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V { +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN { +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; + +/* + * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum + */ + +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE { +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0x00000000, +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 0x00000001, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE { +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE { +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT { +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE { +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE { +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE { +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE { +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE { +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE { +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE { +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE { +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; + +/* + * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum + */ + +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE { +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000, +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; + +/******************************************************* + * AZF0CONTROLLER Enums + *******************************************************/ + +/* + * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum + */ + +typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET { +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0x00000000, +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 0x00000001, +} AZALIA_SOFT_RESET_REFCLK_SOFT_RESET; + +/******************************************************* + * AZF0ROOT Enums + *******************************************************/ + +/* + * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum + */ + +typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY { +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0x00000000, +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 0x00000001, +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 0x00000002, +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 0x00000003, +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 0x00000004, +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 0x00000005, +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 0x00000006, +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 0x00000007, +} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY; + +/* + * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum + */ + +typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY { +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0x00000000, +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 0x00000001, +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 0x00000002, +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 0x00000003, +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 0x00000004, +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 0x00000005, +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 0x00000006, +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 0x00000007, +} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY; + +/******************************************************* + * AZINPUTENDPOINT Enums + *******************************************************/ + +/* + * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE { +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; + +/* + * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE { +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; + +/* + * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE { +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; + +/* + * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR { +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; + +/* + * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE { +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; + +/* + * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS { +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; + +/* + * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN { +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000, +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; + +/* + * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE { +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0x00000000, +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 0x00000001, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE; + +/* + * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE { +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000, +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; + +/* + * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE { +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 0x00000001, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE; + +/* + * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE { +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; + +/* + * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE { +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 0x00000001, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE; + +/* + * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE { +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; + +/* + * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE { +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 0x00000001, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE; + +/* + * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE { +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; + +/* + * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE { +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 0x00000001, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE; + +/* + * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum + */ + +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE { +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000, +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; + +/******************************************************* + * AZROOT Enums + *******************************************************/ + +/* + * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum + */ + +typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET { +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0x00000000, +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 0x00000001, +} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET; + +/******************************************************* + * DCCG Enums + *******************************************************/ + +/* + * ENABLE enum + */ + +typedef enum ENABLE { +DISABLE_THE_FEATURE = 0x00000000, +ENABLE_THE_FEATURE = 0x00000001, +} ENABLE; + +/* + * ENABLE_CLOCK enum + */ + +typedef enum ENABLE_CLOCK { +DISABLE_THE_CLOCK = 0x00000000, +ENABLE_THE_CLOCK = 0x00000001, +} ENABLE_CLOCK; + +/* + * FORCE_VBI enum + */ + +typedef enum FORCE_VBI { +FORCE_VBI_LOW = 0x00000000, +FORCE_VBI_HIGH = 0x00000001, +} FORCE_VBI; + +/* + * OVERRIDE_CGTT_SCLK enum + */ + +typedef enum OVERRIDE_CGTT_SCLK { +OVERRIDE_CGTT_SCLK_NOOP = 0x00000000, +SET_OVERRIDE_CGTT_SCLK = 0x00000001, +} OVERRIDE_CGTT_SCLK; + +/* + * CLEAR_SMU_INTR enum + */ + +typedef enum CLEAR_SMU_INTR { +SMU_INTR_STATUS_NOOP = 0x00000000, +SMU_INTR_STATUS_CLEAR = 0x00000001, +} CLEAR_SMU_INTR; + +/* + * STATIC_SCREEN_SMU_INTR enum + */ + +typedef enum STATIC_SCREEN_SMU_INTR { +STATIC_SCREEN_SMU_INTR_NOOP = 0x00000000, +SET_STATIC_SCREEN_SMU_INTR = 0x00000001, +} STATIC_SCREEN_SMU_INTR; + +/* + * JITTER_REMOVE_DISABLE enum + */ + +typedef enum JITTER_REMOVE_DISABLE { +ENABLE_JITTER_REMOVAL = 0x00000000, +DISABLE_JITTER_REMOVAL = 0x00000001, +} JITTER_REMOVE_DISABLE; + +/* + * DS_REF_SRC enum + */ + +typedef enum DS_REF_SRC { +DS_REF_IS_XTALIN = 0x00000000, +DS_REF_IS_EXT_GENLOCK = 0x00000001, +DS_REF_IS_PCIE = 0x00000002, +} DS_REF_SRC; + +/* + * DISABLE_CLOCK_GATING enum + */ + +typedef enum DISABLE_CLOCK_GATING { +CLOCK_GATING_ENABLED = 0x00000000, +CLOCK_GATING_DISABLED = 0x00000001, +} DISABLE_CLOCK_GATING; + +/* + * DISABLE_CLOCK_GATING_IN_DCO enum + */ + +typedef enum DISABLE_CLOCK_GATING_IN_DCO { +CLOCK_GATING_ENABLED_IN_DCO = 0x00000000, +CLOCK_GATING_DISABLED_IN_DCO = 0x00000001, +} DISABLE_CLOCK_GATING_IN_DCO; + +/* + * DCCG_DEEP_COLOR_CNTL enum + */ + +typedef enum DCCG_DEEP_COLOR_CNTL { +DCCG_DEEP_COLOR_DTO_DISABLE = 0x00000000, +DCCG_DEEP_COLOR_DTO_5_4_RATIO = 0x00000001, +DCCG_DEEP_COLOR_DTO_3_2_RATIO = 0x00000002, +DCCG_DEEP_COLOR_DTO_2_1_RATIO = 0x00000003, +} DCCG_DEEP_COLOR_CNTL; + +/* + * REFCLK_CLOCK_EN enum + */ + +typedef enum REFCLK_CLOCK_EN { +REFCLK_CLOCK_EN_XTALIN_CLK = 0x00000000, +REFCLK_CLOCK_EN_ALLOW_SRC_SEL = 0x00000001, +} REFCLK_CLOCK_EN; + +/* + * REFCLK_SRC_SEL enum + */ + +typedef enum REFCLK_SRC_SEL { +REFCLK_SRC_SEL_PCIE_REFCLK = 0x00000000, +REFCLK_SRC_SEL_CPL_REFCLK = 0x00000001, +} REFCLK_SRC_SEL; + +/* + * DPREFCLK_SRC_SEL enum + */ + +typedef enum DPREFCLK_SRC_SEL { +DPREFCLK_SRC_SEL_CK = 0x00000000, +DPREFCLK_SRC_SEL_P0PLL = 0x00000001, +DPREFCLK_SRC_SEL_P1PLL = 0x00000002, +DPREFCLK_SRC_SEL_P2PLL = 0x00000003, +DPREFCLK_SRC_SEL_P3PLL = 0x00000004, +} DPREFCLK_SRC_SEL; + +/* + * XTAL_REF_SEL enum + */ + +typedef enum XTAL_REF_SEL { +XTAL_REF_SEL_1X = 0x00000000, +XTAL_REF_SEL_2X = 0x00000001, +} XTAL_REF_SEL; + +/* + * XTAL_REF_CLOCK_SOURCE_SEL enum + */ + +typedef enum XTAL_REF_CLOCK_SOURCE_SEL { +XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0x00000000, +XTAL_REF_CLOCK_SOURCE_SEL_PPLL = 0x00000001, +} XTAL_REF_CLOCK_SOURCE_SEL; + +/* + * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum + */ + +typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL { +MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000, +MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 0x00000001, +} MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL; + +/* + * ALLOW_SR_ON_TRANS_REQ enum + */ + +typedef enum ALLOW_SR_ON_TRANS_REQ { +ALLOW_SR_ON_TRANS_REQ_ENABLE = 0x00000000, +ALLOW_SR_ON_TRANS_REQ_DISABLE = 0x00000001, +} ALLOW_SR_ON_TRANS_REQ; + +/* + * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum + */ + +typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL { +MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000, +MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 0x00000001, +} MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL; + +/* + * PIPE_PIXEL_RATE_SOURCE enum + */ + +typedef enum PIPE_PIXEL_RATE_SOURCE { +PIPE_PIXEL_RATE_SOURCE_P0PLL = 0x00000000, +PIPE_PIXEL_RATE_SOURCE_P1PLL = 0x00000001, +PIPE_PIXEL_RATE_SOURCE_P2PLL = 0x00000002, +} PIPE_PIXEL_RATE_SOURCE; + +/* + * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum + */ + +typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE { +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0x00000000, +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 0x00000001, +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 0x00000002, +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 0x00000003, +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE = 0x00000004, +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF = 0x00000005, +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG = 0x00000006, +} PIPE_PHYPLL_PIXEL_RATE_SOURCE; + +/* + * PIPE_PIXEL_RATE_PLL_SOURCE enum + */ + +typedef enum PIPE_PIXEL_RATE_PLL_SOURCE { +PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0x00000000, +PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 0x00000001, +} PIPE_PIXEL_RATE_PLL_SOURCE; + +/* + * DP_DTO_DS_DISABLE enum + */ + +typedef enum DP_DTO_DS_DISABLE { +DP_DTO_DESPREAD_DISABLE = 0x00000000, +DP_DTO_DESPREAD_ENABLE = 0x00000001, +} DP_DTO_DS_DISABLE; + +/* + * CRTC_ADD_PIXEL enum + */ + +typedef enum CRTC_ADD_PIXEL { +CRTC_ADD_PIXEL_NOOP = 0x00000000, +CRTC_ADD_PIXEL_FORCE = 0x00000001, +} CRTC_ADD_PIXEL; + +/* + * CRTC_DROP_PIXEL enum + */ + +typedef enum CRTC_DROP_PIXEL { +CRTC_DROP_PIXEL_NOOP = 0x00000000, +CRTC_DROP_PIXEL_FORCE = 0x00000001, +} CRTC_DROP_PIXEL; + +/* + * SYMCLK_FE_FORCE_EN enum + */ + +typedef enum SYMCLK_FE_FORCE_EN { +SYMCLK_FE_FORCE_EN_DISABLE = 0x00000000, +SYMCLK_FE_FORCE_EN_ENABLE = 0x00000001, +} SYMCLK_FE_FORCE_EN; + +/* + * SYMCLK_FE_FORCE_SRC enum + */ + +typedef enum SYMCLK_FE_FORCE_SRC { +SYMCLK_FE_FORCE_SRC_UNIPHYA = 0x00000000, +SYMCLK_FE_FORCE_SRC_UNIPHYB = 0x00000001, +SYMCLK_FE_FORCE_SRC_UNIPHYC = 0x00000002, +SYMCLK_FE_FORCE_SRC_UNIPHYD = 0x00000003, +SYMCLK_FE_FORCE_SRC_UNIPHYE = 0x00000004, +SYMCLK_FE_FORCE_SRC_UNIPHYF = 0x00000005, +SYMCLK_FE_FORCE_SRC_UNIPHYG = 0x00000006, +} SYMCLK_FE_FORCE_SRC; + +/* + * DPDBG_CLK_FORCE_EN enum + */ + +typedef enum DPDBG_CLK_FORCE_EN { +DPDBG_CLK_FORCE_EN_DISABLE = 0x00000000, +DPDBG_CLK_FORCE_EN_ENABLE = 0x00000001, +} DPDBG_CLK_FORCE_EN; + +/* + * DVOACLK_COARSE_SKEW_CNTL enum + */ + +typedef enum DVOACLK_COARSE_SKEW_CNTL { +DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000, +DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 0x00000001, +DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002, +DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003, +DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 0x00000004, +DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 0x00000005, +DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 0x00000006, +DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 0x00000007, +DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 0x00000008, +DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 0x00000009, +DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 0x0000000a, +DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 0x0000000b, +DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 0x0000000c, +DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 0x0000000d, +DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 0x0000000e, +DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 0x0000000f, +DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 0x00000010, +DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 0x00000011, +DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 0x00000012, +DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 0x00000013, +DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 0x00000014, +DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 0x00000015, +DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 0x00000016, +DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 0x00000017, +DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 0x00000018, +DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 0x00000019, +DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 0x0000001a, +DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 0x0000001b, +DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 0x0000001c, +DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 0x0000001d, +DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 0x0000001e, +} DVOACLK_COARSE_SKEW_CNTL; + +/* + * DVOACLK_FINE_SKEW_CNTL enum + */ + +typedef enum DVOACLK_FINE_SKEW_CNTL { +DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000, +DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 0x00000001, +DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002, +DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003, +DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 0x00000004, +DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 0x00000005, +DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 0x00000006, +DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 0x00000007, +} DVOACLK_FINE_SKEW_CNTL; + +/* + * DVOACLKD_IN_PHASE enum + */ + +typedef enum DVOACLKD_IN_PHASE { +DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000, +DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 0x00000001, +} DVOACLKD_IN_PHASE; + +/* + * DVOACLKC_IN_PHASE enum + */ + +typedef enum DVOACLKC_IN_PHASE { +DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000, +DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 0x00000001, +} DVOACLKC_IN_PHASE; + +/* + * DVOACLKC_MVP_IN_PHASE enum + */ + +typedef enum DVOACLKC_MVP_IN_PHASE { +DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000, +DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 0x00000001, +} DVOACLKC_MVP_IN_PHASE; + +/* + * DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum + */ + +typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE { +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0x00000000, +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 0x00000001, +} DVOACLKC_MVP_SKEW_PHASE_OVERRIDE; + +/* + * MVP_CLK_SRC_SEL enum + */ + +typedef enum MVP_CLK_SRC_SEL { +MVP_CLK_SRC_SEL_RSRV = 0x00000000, +MVP_CLK_SRC_SEL_IO_1 = 0x00000001, +MVP_CLK_SRC_SEL_IO_2 = 0x00000002, +MVP_CLK_SRC_SEL_REFCLK = 0x00000003, +} MVP_CLK_SRC_SEL; + +/* + * DCCG_AUDIO_DTO0_SOURCE_SEL enum + */ + +typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL { +DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0 = 0x00000000, +DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1 = 0x00000001, +DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2 = 0x00000002, +DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3 = 0x00000003, +DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4 = 0x00000004, +DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5 = 0x00000005, +DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 0x00000006, +} DCCG_AUDIO_DTO0_SOURCE_SEL; + +/* + * DCCG_AUDIO_DTO_SEL enum + */ + +typedef enum DCCG_AUDIO_DTO_SEL { +DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0x00000000, +DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 0x00000001, +DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 0x00000002, +} DCCG_AUDIO_DTO_SEL; + +/* + * DCCG_AUDIO_DTO2_SOURCE_SEL enum + */ + +typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL { +DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0x00000000, +DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1 = 0x00000001, +} DCCG_AUDIO_DTO2_SOURCE_SEL; + +/* + * DCCG_AUDIO_DTO_USE_512FBR_DTO enum + */ + +typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO { +DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0x00000000, +DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 0x00000001, +} DCCG_AUDIO_DTO_USE_512FBR_DTO; + +/* + * DCCG_DBG_EN enum + */ + +typedef enum DCCG_DBG_EN { +DCCG_DBG_EN_DISABLE = 0x00000000, +DCCG_DBG_EN_ENABLE = 0x00000001, +} DCCG_DBG_EN; + +/* + * DCCG_DBG_BLOCK_SEL enum + */ + +typedef enum DCCG_DBG_BLOCK_SEL { +DCCG_DBG_BLOCK_SEL_DCCG = 0x00000000, +DCCG_DBG_BLOCK_SEL_PMON = 0x00000001, +DCCG_DBG_BLOCK_SEL_PMON2 = 0x00000002, +} DCCG_DBG_BLOCK_SEL; + +/* + * DISPCLK_FREQ_RAMP_DONE enum + */ + +typedef enum DISPCLK_FREQ_RAMP_DONE { +DISPCLK_FREQ_RAMP_IN_PROGRESS = 0x00000000, +DISPCLK_FREQ_RAMP_COMPLETED = 0x00000001, +} DISPCLK_FREQ_RAMP_DONE; + +/* + * DCCG_FIFO_ERRDET_RESET enum + */ + +typedef enum DCCG_FIFO_ERRDET_RESET { +DCCG_FIFO_ERRDET_RESET_NOOP = 0x00000000, +DCCG_FIFO_ERRDET_RESET_FORCE = 0x00000001, +} DCCG_FIFO_ERRDET_RESET; + +/* + * DCCG_FIFO_ERRDET_STATE enum + */ + +typedef enum DCCG_FIFO_ERRDET_STATE { +DCCG_FIFO_ERRDET_STATE_DETECTION = 0x00000000, +DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0x00000001, +} DCCG_FIFO_ERRDET_STATE; + +/* + * DCCG_FIFO_ERRDET_OVR_EN enum + */ + +typedef enum DCCG_FIFO_ERRDET_OVR_EN { +DCCG_FIFO_ERRDET_OVR_DISABLE = 0x00000000, +DCCG_FIFO_ERRDET_OVR_ENABLE = 0x00000001, +} DCCG_FIFO_ERRDET_OVR_EN; + +/* + * DISPCLK_CHG_FWD_CORR_DISABLE enum + */ + +typedef enum DISPCLK_CHG_FWD_CORR_DISABLE { +DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0x00000000, +DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 0x00000001, +} DISPCLK_CHG_FWD_CORR_DISABLE; + +/* + * DC_MEM_GLOBAL_PWR_REQ_DIS enum + */ + +typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS { +DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0x00000000, +DC_MEM_GLOBAL_PWR_REQ_DISABLE = 0x00000001, +} DC_MEM_GLOBAL_PWR_REQ_DIS; + +/* + * DCCG_PERF_RUN enum + */ + +typedef enum DCCG_PERF_RUN { +DCCG_PERF_RUN_NOOP = 0x00000000, +DCCG_PERF_RUN_START = 0x00000001, +} DCCG_PERF_RUN; + +/* + * DCCG_PERF_MODE_VSYNC enum + */ + +typedef enum DCCG_PERF_MODE_VSYNC { +DCCG_PERF_MODE_VSYNC_NOOP = 0x00000000, +DCCG_PERF_MODE_VSYNC_START = 0x00000001, +} DCCG_PERF_MODE_VSYNC; + +/* + * DCCG_PERF_MODE_HSYNC enum + */ + +typedef enum DCCG_PERF_MODE_HSYNC { +DCCG_PERF_MODE_HSYNC_NOOP = 0x00000000, +DCCG_PERF_MODE_HSYNC_START = 0x00000001, +} DCCG_PERF_MODE_HSYNC; + +/* + * DCCG_PERF_CRTC_SELECT enum + */ + +typedef enum DCCG_PERF_CRTC_SELECT { +DCCG_PERF_SEL_CRTC0 = 0x00000000, +DCCG_PERF_SEL_CRTC1 = 0x00000001, +DCCG_PERF_SEL_CRTC2 = 0x00000002, +DCCG_PERF_SEL_CRTC3 = 0x00000003, +DCCG_PERF_SEL_CRTC4 = 0x00000004, +DCCG_PERF_SEL_CRTC5 = 0x00000005, +} DCCG_PERF_CRTC_SELECT; + +/* + * CLOCK_BRANCH_SOFT_RESET enum + */ + +typedef enum CLOCK_BRANCH_SOFT_RESET { +CLOCK_BRANCH_SOFT_RESET_NOOP = 0x00000000, +CLOCK_BRANCH_SOFT_RESET_FORCE = 0x00000001, +} CLOCK_BRANCH_SOFT_RESET; + +/* + * PLL_CFG_IF_SOFT_RESET enum + */ + +typedef enum PLL_CFG_IF_SOFT_RESET { +PLL_CFG_IF_SOFT_RESET_NOOP = 0x00000000, +PLL_CFG_IF_SOFT_RESET_FORCE = 0x00000001, +} PLL_CFG_IF_SOFT_RESET; + +/* + * DVO_ENABLE_RST enum + */ + +typedef enum DVO_ENABLE_RST { +DVO_ENABLE_RST_DISABLE = 0x00000000, +DVO_ENABLE_RST_ENABLE = 0x00000001, +} DVO_ENABLE_RST; + +/******************************************************* + * DCI Enums + *******************************************************/ + +/* + * LptNumPipes enum + */ + +typedef enum LptNumPipes { +LPT_NUM_PIPES_1CH = 0x00000000, +LPT_NUM_PIPES_2CH = 0x00000001, +LPT_NUM_PIPES_4CH = 0x00000002, +LPT_NUM_PIPES_8CH = 0x00000003, +} LptNumPipes; + +/* + * LptNumBanks enum + */ + +typedef enum LptNumBanks { +LPT_NUM_BANKS_2BANK = 0x00000000, +LPT_NUM_BANKS_4BANK = 0x00000001, +LPT_NUM_BANKS_8BANK = 0x00000002, +LPT_NUM_BANKS_16BANK = 0x00000003, +LPT_NUM_BANKS_32BANK = 0x00000004, +} LptNumBanks; + +/* + * OVERRIDE_CGTT_DCEFCLK enum + */ + +typedef enum OVERRIDE_CGTT_DCEFCLK { +OVERRIDE_CGTT_DCEFCLK_NOOP = 0x00000000, +SET_OVERRIDE_CGTT_DCEFCLK = 0x00000001, +} OVERRIDE_CGTT_DCEFCLK; + +/******************************************************* + * DCIO Enums + *******************************************************/ + +/* + * DCIO_DC_GENERICA_SEL enum + */ + +typedef enum DCIO_DC_GENERICA_SEL { +DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0x00000000, +DCIO_GENERICA_SEL_STEREOSYNC = 0x00000001, +DCIO_GENERICA_SEL_DACA_PIXCLK = 0x00000002, +DCIO_GENERICA_SEL_DACB_PIXCLK = 0x00000003, +DCIO_GENERICA_SEL_DVOA_CTL3 = 0x00000004, +DCIO_GENERICA_SEL_P1_PLLCLK = 0x00000005, +DCIO_GENERICA_SEL_P2_PLLCLK = 0x00000006, +DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 0x00000007, +DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 0x00000008, +DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 0x00000009, +DCIO_GENERICA_SEL_GENERICA_DCCG = 0x0000000a, +DCIO_GENERICA_SEL_SYNCEN = 0x0000000b, +DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK = 0x0000000c, +DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK = 0x0000000d, +DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK = 0x0000000e, +DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2 = 0x0000000f, +DCIO_GENERICA_SEL_GENERICA_DPRX = 0x00000010, +DCIO_GENERICA_SEL_GENERICB_DPRX = 0x00000011, +} DCIO_DC_GENERICA_SEL; + +/* + * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum + */ + +typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL { +DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x00000000, +DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x00000001, +DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x00000002, +DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x00000003, +DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x00000004, +DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x00000005, +DCIO_UNIPHYG_TEST_REFDIV_CLK = 0x00000006, +DCIO_UNIPHYLPA_TEST_REFDIV_CLK = 0x00000007, +DCIO_UNIPHYLPB_TEST_REFDIV_CLK = 0x00000008, +} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL; + +/* + * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum + */ + +typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL { +DCIO_UNIPHYA_FBDIV_CLK = 0x00000000, +DCIO_UNIPHYB_FBDIV_CLK = 0x00000001, +DCIO_UNIPHYC_FBDIV_CLK = 0x00000002, +DCIO_UNIPHYD_FBDIV_CLK = 0x00000003, +DCIO_UNIPHYE_FBDIV_CLK = 0x00000004, +DCIO_UNIPHYF_FBDIV_CLK = 0x00000005, +DCIO_UNIPHYG_FBDIV_CLK = 0x00000006, +DCIO_UNIPHYLPA_FBDIV_CLK = 0x00000007, +DCIO_UNIPHYLPB_FBDIV_CLK = 0x00000008, +} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL; + +/* + * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum + */ + +typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL { +DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x00000000, +DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x00000001, +DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x00000002, +DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x00000003, +DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x00000004, +DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x00000005, +DCIO_UNIPHYG_FBDIV_SSC_CLK = 0x00000006, +DCIO_UNIPHYLPA_FBDIV_SSC_CLK = 0x00000007, +DCIO_UNIPHYLPB_FBDIV_SSC_CLK = 0x00000008, +} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL; + +/* + * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum + */ + +typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL { +DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x00000000, +DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x00000001, +DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x00000002, +DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x00000003, +DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x00000004, +DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x00000005, +DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 0x00000006, +DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2 = 0x00000007, +DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2 = 0x00000008, +} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL; + +/* + * DCIO_DC_GENERICB_SEL enum + */ + +typedef enum DCIO_DC_GENERICB_SEL { +DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0x00000000, +DCIO_GENERICB_SEL_STEREOSYNC = 0x00000001, +DCIO_GENERICB_SEL_DACA_PIXCLK = 0x00000002, +DCIO_GENERICB_SEL_DACB_PIXCLK = 0x00000003, +DCIO_GENERICB_SEL_DVOA_CTL3 = 0x00000004, +DCIO_GENERICB_SEL_P1_PLLCLK = 0x00000005, +DCIO_GENERICB_SEL_P2_PLLCLK = 0x00000006, +DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 0x00000007, +DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 0x00000008, +DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 0x00000009, +DCIO_GENERICB_SEL_GENERICB_DCCG = 0x0000000a, +DCIO_GENERICB_SEL_SYNCEN = 0x0000000b, +DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK = 0x0000000c, +DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK = 0x0000000d, +DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK = 0x0000000e, +DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2 = 0x0000000f, +} DCIO_DC_GENERICB_SEL; + +/* + * DCIO_DC_PAD_EXTERN_SIG_SEL enum + */ + +typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL { +DCIO_DC_PAD_EXTERN_SIG_SEL_MVP = 0x00000000, +DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 0x00000001, +DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 0x00000002, +DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 0x00000003, +DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA = 0x00000004, +DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB = 0x00000005, +DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC = 0x00000006, +DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1 = 0x00000007, +DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2 = 0x00000008, +DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK = 0x00000009, +DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 0x0000000a, +DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK = 0x0000000b, +DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA = 0x0000000c, +DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1 = 0x0000000d, +DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0 = 0x0000000e, +DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL = 0x0000000f, +} DCIO_DC_PAD_EXTERN_SIG_SEL; + +/* + * DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS enum + */ + +typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS { +DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA = 0x00000000, +DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 0x00000001, +DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 0x00000002, +DCIO_MVP_PIXEL_SRC_STATUS_LB = 0x00000003, +} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS; + +/* + * DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL enum + */ + +typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL { +DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x00000000, +DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x00000001, +DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x00000002, +DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x00000003, +} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL; + +/* + * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum + */ + +typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL { +DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x00000000, +DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x00000001, +DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x00000002, +DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x00000003, +} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL; + +/* + * DCIO_DC_GPIO_VIP_DEBUG enum + */ + +typedef enum DCIO_DC_GPIO_VIP_DEBUG { +DCIO_DC_GPIO_VIP_DEBUG_NORMAL = 0x00000000, +DCIO_DC_GPIO_VIP_DEBUG_CG_BIG = 0x00000001, +} DCIO_DC_GPIO_VIP_DEBUG; + +/* + * DCIO_DC_GPIO_MACRO_DEBUG enum + */ + +typedef enum DCIO_DC_GPIO_MACRO_DEBUG { +DCIO_DC_GPIO_MACRO_DEBUG_NORMAL = 0x00000000, +DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF = 0x00000001, +DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 0x00000002, +DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 0x00000003, +} DCIO_DC_GPIO_MACRO_DEBUG; + +/* + * DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL enum + */ + +typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL { +DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0x00000000, +DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 0x00000001, +} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL; + +/* + * DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN enum + */ + +typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN { +DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS = 0x00000000, +DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE = 0x00000001, +} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN; + +/* + * DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE enum + */ + +typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE { +DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x00000000, +DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x00000001, +} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE; + +/* + * DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION enum + */ + +typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION { +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x00000000, +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x00000001, +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS = 0x00000002, +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS = 0x00000003, +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS = 0x00000004, +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS = 0x00000005, +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS = 0x00000006, +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS = 0x00000007, +} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION; + +/* + * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum + */ + +typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT { +DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x00000000, +DCIO_UNIPHY_CHANNEL_INVERTED = 0x00000001, +} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT; + +/* + * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum + */ + +typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK { +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x00000000, +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x00000001, +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x00000002, +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 0x00000003, +} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK; + +/* + * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum + */ + +typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE { +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x00000000, +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x00000001, +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x00000002, +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x00000003, +} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE; + +/* + * DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN enum + */ + +typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN { +DCIO_VIP_MUX_EN_DVO = 0x00000000, +DCIO_VIP_MUX_EN_VIP = 0x00000001, +} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN; + +/* + * DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN enum + */ + +typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN { +DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0x00000000, +DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 0x00000001, +} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN; + +/* + * DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN enum + */ + +typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN { +DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0x00000000, +DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 0x00000001, +} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN; + +/* + * DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN enum + */ + +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN { +DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE = 0x00000000, +DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE = 0x00000001, +} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN; + +/* + * DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE enum + */ + +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE { +DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0x00000000, +DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 0x00000001, +} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE; + +/* + * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL enum + */ + +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL { +DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0x00000000, +DCIO_LVTMA_SYNCEN_POL_INVERT = 0x00000001, +} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL; + +/* + * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON enum + */ + +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON { +DCIO_LVTMA_DIGON_OFF = 0x00000000, +DCIO_LVTMA_DIGON_ON = 0x00000001, +} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON; + +/* + * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL enum + */ + +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL { +DCIO_LVTMA_DIGON_POL_NON_INVERT = 0x00000000, +DCIO_LVTMA_DIGON_POL_INVERT = 0x00000001, +} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL; + +/* + * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON enum + */ + +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON { +DCIO_LVTMA_BLON_OFF = 0x00000000, +DCIO_LVTMA_BLON_ON = 0x00000001, +} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON; + +/* + * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL enum + */ + +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL { +DCIO_LVTMA_BLON_POL_NON_INVERT = 0x00000000, +DCIO_LVTMA_BLON_POL_INVERT = 0x00000001, +} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL; + +/* + * DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN enum + */ + +typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN { +DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0x00000000, +DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 0x00000001, +} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN; + +/* + * DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum + */ + +typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN { +DCIO_BL_PWM_FRACTIONAL_DISABLE = 0x00000000, +DCIO_BL_PWM_FRACTIONAL_ENABLE = 0x00000001, +} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN; + +/* + * DCIO_BL_PWM_CNTL_BL_PWM_EN enum + */ + +typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN { +DCIO_BL_PWM_DISABLE = 0x00000000, +DCIO_BL_PWM_ENABLE = 0x00000001, +} DCIO_BL_PWM_CNTL_BL_PWM_EN; + +/* + * DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT enum + */ + +typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT { +DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x00000000, +DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x00000001, +DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x00000002, +DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x00000003, +} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT; + +/* + * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum + */ + +typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE { +DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x00000000, +DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x00000001, +} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE; + +/* + * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN enum + */ + +typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN { +DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0x00000000, +DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 0x00000001, +} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN; + +/* + * DCIO_BL_PWM_GRP1_REG_LOCK enum + */ + +typedef enum DCIO_BL_PWM_GRP1_REG_LOCK { +DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x00000000, +DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x00000001, +} DCIO_BL_PWM_GRP1_REG_LOCK; + +/* + * DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum + */ + +typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START { +DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x00000000, +DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x00000001, +} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START; + +/* + * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum + */ + +typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL { +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0x00000000, +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 0x00000001, +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 0x00000002, +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 0x00000003, +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 0x00000004, +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 0x00000005, +} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL; + +/* + * DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum + */ + +typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN { +DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x00000000, +DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 0x00000001, +} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN; + +/* + * DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum + */ + +typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN { +DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x00000000, +DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x00000001, +} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; + +/* + * DCIO_GSL_SEL enum + */ + +typedef enum DCIO_GSL_SEL { +DCIO_GSL_SEL_GROUP_0 = 0x00000000, +DCIO_GSL_SEL_GROUP_1 = 0x00000001, +DCIO_GSL_SEL_GROUP_2 = 0x00000002, +} DCIO_GSL_SEL; + +/* + * DCIO_GENLK_CLK_GSL_MASK enum + */ + +typedef enum DCIO_GENLK_CLK_GSL_MASK { +DCIO_GENLK_CLK_GSL_MASK_NO = 0x00000000, +DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x00000001, +DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x00000002, +} DCIO_GENLK_CLK_GSL_MASK; + +/* + * DCIO_GENLK_VSYNC_GSL_MASK enum + */ + +typedef enum DCIO_GENLK_VSYNC_GSL_MASK { +DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x00000000, +DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x00000001, +DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x00000002, +} DCIO_GENLK_VSYNC_GSL_MASK; + +/* + * DCIO_SWAPLOCK_A_GSL_MASK enum + */ + +typedef enum DCIO_SWAPLOCK_A_GSL_MASK { +DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x00000000, +DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x00000001, +DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x00000002, +} DCIO_SWAPLOCK_A_GSL_MASK; + +/* + * DCIO_SWAPLOCK_B_GSL_MASK enum + */ + +typedef enum DCIO_SWAPLOCK_B_GSL_MASK { +DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x00000000, +DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x00000001, +DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x00000002, +} DCIO_SWAPLOCK_B_GSL_MASK; + +/* + * DCIO_GSL_VSYNC_SEL enum + */ + +typedef enum DCIO_GSL_VSYNC_SEL { +DCIO_GSL_VSYNC_SEL_PIPE0 = 0x00000000, +DCIO_GSL_VSYNC_SEL_PIPE1 = 0x00000001, +DCIO_GSL_VSYNC_SEL_PIPE2 = 0x00000002, +DCIO_GSL_VSYNC_SEL_PIPE3 = 0x00000003, +DCIO_GSL_VSYNC_SEL_PIPE4 = 0x00000004, +DCIO_GSL_VSYNC_SEL_PIPE5 = 0x00000005, +} DCIO_GSL_VSYNC_SEL; + +/* + * DCIO_GSL0_TIMING_SYNC_SEL enum + */ + +typedef enum DCIO_GSL0_TIMING_SYNC_SEL { +DCIO_GSL0_TIMING_SYNC_SEL_PIPE = 0x00000000, +DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x00000001, +DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 0x00000002, +DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A = 0x00000003, +DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B = 0x00000004, +} DCIO_GSL0_TIMING_SYNC_SEL; + +/* + * DCIO_GSL0_GLOBAL_UNLOCK_SEL enum + */ + +typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL { +DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION = 0x00000000, +DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x00000001, +DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x00000002, +DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x00000003, +DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x00000004, +} DCIO_GSL0_GLOBAL_UNLOCK_SEL; + +/* + * DCIO_GSL1_TIMING_SYNC_SEL enum + */ + +typedef enum DCIO_GSL1_TIMING_SYNC_SEL { +DCIO_GSL1_TIMING_SYNC_SEL_PIPE = 0x00000000, +DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x00000001, +DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 0x00000002, +DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A = 0x00000003, +DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B = 0x00000004, +} DCIO_GSL1_TIMING_SYNC_SEL; + +/* + * DCIO_GSL1_GLOBAL_UNLOCK_SEL enum + */ + +typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL { +DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION = 0x00000000, +DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x00000001, +DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x00000002, +DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x00000003, +DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x00000004, +} DCIO_GSL1_GLOBAL_UNLOCK_SEL; + +/* + * DCIO_GSL2_TIMING_SYNC_SEL enum + */ + +typedef enum DCIO_GSL2_TIMING_SYNC_SEL { +DCIO_GSL2_TIMING_SYNC_SEL_PIPE = 0x00000000, +DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x00000001, +DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 0x00000002, +DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A = 0x00000003, +DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B = 0x00000004, +} DCIO_GSL2_TIMING_SYNC_SEL; + +/* + * DCIO_GSL2_GLOBAL_UNLOCK_SEL enum + */ + +typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL { +DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION = 0x00000000, +DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x00000001, +DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x00000002, +DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x00000003, +DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x00000004, +} DCIO_GSL2_GLOBAL_UNLOCK_SEL; + +/* + * DCIO_DC_GPU_TIMER_START_POSITION enum + */ + +typedef enum DCIO_DC_GPU_TIMER_START_POSITION { +DCIO_GPU_TIMER_START_0_END_27 = 0x00000000, +DCIO_GPU_TIMER_START_1_END_28 = 0x00000001, +DCIO_GPU_TIMER_START_2_END_29 = 0x00000002, +DCIO_GPU_TIMER_START_3_END_30 = 0x00000003, +DCIO_GPU_TIMER_START_4_END_31 = 0x00000004, +DCIO_GPU_TIMER_START_6_END_33 = 0x00000005, +DCIO_GPU_TIMER_START_8_END_35 = 0x00000006, +DCIO_GPU_TIMER_START_10_END_37 = 0x00000007, +} DCIO_DC_GPU_TIMER_START_POSITION; + +/* + * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum + */ + +typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL { +DCIO_TEST_CLK_SEL_DISPCLK = 0x00000000, +DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x00000001, +DCIO_TEST_CLK_SEL_SCLK = 0x00000002, +} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL; + +/* + * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum + */ + +typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS { +DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x00000000, +DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x00000001, +} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS; + +/* + * DCIO_DCO_DCFE_EXT_VSYNC_MUX enum + */ + +typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX { +DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x00000000, +DCIO_EXT_VSYNC_MUX_CRTC0 = 0x00000001, +DCIO_EXT_VSYNC_MUX_CRTC1 = 0x00000002, +DCIO_EXT_VSYNC_MUX_CRTC2 = 0x00000003, +DCIO_EXT_VSYNC_MUX_CRTC3 = 0x00000004, +DCIO_EXT_VSYNC_MUX_CRTC4 = 0x00000005, +DCIO_EXT_VSYNC_MUX_CRTC5 = 0x00000006, +DCIO_EXT_VSYNC_MUX_GENERICB = 0x00000007, +} DCIO_DCO_DCFE_EXT_VSYNC_MUX; + +/* + * DCIO_DCO_EXT_VSYNC_MASK enum + */ + +typedef enum DCIO_DCO_EXT_VSYNC_MASK { +DCIO_EXT_VSYNC_MASK_NONE = 0x00000000, +DCIO_EXT_VSYNC_MASK_PIPE0 = 0x00000001, +DCIO_EXT_VSYNC_MASK_PIPE1 = 0x00000002, +DCIO_EXT_VSYNC_MASK_PIPE2 = 0x00000003, +DCIO_EXT_VSYNC_MASK_PIPE3 = 0x00000004, +DCIO_EXT_VSYNC_MASK_PIPE4 = 0x00000005, +DCIO_EXT_VSYNC_MASK_PIPE5 = 0x00000006, +DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x00000007, +} DCIO_DCO_EXT_VSYNC_MASK; + +/* + * DCIO_DSYNC_SOFT_RESET enum + */ + +typedef enum DCIO_DSYNC_SOFT_RESET { +DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x00000000, +DCIO_DSYNC_SOFT_RESET_ASSERT = 0x00000001, +} DCIO_DSYNC_SOFT_RESET; + +/* + * DCIO_DACA_SOFT_RESET enum + */ + +typedef enum DCIO_DACA_SOFT_RESET { +DCIO_DACA_SOFT_RESET_DEASSERT = 0x00000000, +DCIO_DACA_SOFT_RESET_ASSERT = 0x00000001, +} DCIO_DACA_SOFT_RESET; + +/* + * DCIO_DCRXPHY_SOFT_RESET enum + */ + +typedef enum DCIO_DCRXPHY_SOFT_RESET { +DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x00000000, +DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x00000001, +} DCIO_DCRXPHY_SOFT_RESET; + +/* + * DCIO_DPHY_LANE_SEL enum + */ + +typedef enum DCIO_DPHY_LANE_SEL { +DCIO_DPHY_LANE_SEL_LANE0 = 0x00000000, +DCIO_DPHY_LANE_SEL_LANE1 = 0x00000001, +DCIO_DPHY_LANE_SEL_LANE2 = 0x00000002, +DCIO_DPHY_LANE_SEL_LANE3 = 0x00000003, +} DCIO_DPHY_LANE_SEL; + +/* + * DCIO_DPCS_INTERRUPT_TYPE enum + */ + +typedef enum DCIO_DPCS_INTERRUPT_TYPE { +DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000, +DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 0x00000001, +} DCIO_DPCS_INTERRUPT_TYPE; + +/* + * DCIO_DPCS_INTERRUPT_MASK enum + */ + +typedef enum DCIO_DPCS_INTERRUPT_MASK { +DCIO_DPCS_INTERRUPT_DISABLE = 0x00000000, +DCIO_DPCS_INTERRUPT_ENABLE = 0x00000001, +} DCIO_DPCS_INTERRUPT_MASK; + +/* + * DCIO_DC_GPU_TIMER_READ_SELECT enum + */ + +typedef enum DCIO_DC_GPU_TIMER_READ_SELECT { +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x00000000, +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x00000001, +DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 0x00000002, +DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 0x00000003, +DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x00000004, +DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 0x00000005, +DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE = 0x00000006, +DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE = 0x00000007, +DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE = 0x00000008, +DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE = 0x00000009, +DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE = 0x0000000a, +DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE = 0x0000000b, +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0x0000000c, +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0x0000000d, +DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 0x0000000e, +DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 0x0000000f, +DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 0x00000010, +DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 0x00000011, +DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP = 0x00000012, +DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP = 0x00000013, +DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP = 0x00000014, +DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP = 0x00000015, +DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP = 0x00000016, +DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP = 0x00000017, +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x00000018, +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x00000019, +DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 0x0000001a, +DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 0x0000001b, +DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 0x0000001c, +DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 0x0000001d, +DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM = 0x0000001e, +DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM = 0x0000001f, +DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM = 0x00000020, +DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM = 0x00000021, +DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM = 0x00000022, +DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM = 0x00000023, +} DCIO_DC_GPU_TIMER_READ_SELECT; + +/* + * DCIO_IMPCAL_STEP_DELAY enum + */ + +typedef enum DCIO_IMPCAL_STEP_DELAY { +DCIO_IMPCAL_STEP_DELAY_1us = 0x00000000, +DCIO_IMPCAL_STEP_DELAY_2us = 0x00000001, +DCIO_IMPCAL_STEP_DELAY_3us = 0x00000002, +DCIO_IMPCAL_STEP_DELAY_4us = 0x00000003, +DCIO_IMPCAL_STEP_DELAY_5us = 0x00000004, +DCIO_IMPCAL_STEP_DELAY_6us = 0x00000005, +DCIO_IMPCAL_STEP_DELAY_7us = 0x00000006, +DCIO_IMPCAL_STEP_DELAY_8us = 0x00000007, +DCIO_IMPCAL_STEP_DELAY_9us = 0x00000008, +DCIO_IMPCAL_STEP_DELAY_10us = 0x00000009, +DCIO_IMPCAL_STEP_DELAY_11us = 0x0000000a, +DCIO_IMPCAL_STEP_DELAY_12us = 0x0000000b, +DCIO_IMPCAL_STEP_DELAY_13us = 0x0000000c, +DCIO_IMPCAL_STEP_DELAY_14us = 0x0000000d, +DCIO_IMPCAL_STEP_DELAY_15us = 0x0000000e, +DCIO_IMPCAL_STEP_DELAY_16us = 0x0000000f, +} DCIO_IMPCAL_STEP_DELAY; + +/* + * DCIO_UNIPHY_IMPCAL_SEL enum + */ + +typedef enum DCIO_UNIPHY_IMPCAL_SEL { +DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x00000000, +DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x00000001, +} DCIO_UNIPHY_IMPCAL_SEL; + +/* + * DCIO_DBG_ASYNC_BLOCK_SEL enum + */ + +typedef enum DCIO_DBG_ASYNC_BLOCK_SEL { +DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0x00000000, +DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 0x00000001, +DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 0x00000002, +DCIO_DBG_ASYNC_BLOCK_SEL_DCO = 0x00000003, +} DCIO_DBG_ASYNC_BLOCK_SEL; + +/* + * DCIO_DBG_ASYNC_4BIT_SEL enum + */ + +typedef enum DCIO_DBG_ASYNC_4BIT_SEL { +DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0x00000000, +DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 0x00000001, +DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 0x00000002, +DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 0x00000003, +DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 0x00000004, +DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 0x00000005, +DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 0x00000006, +DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 0x00000007, +} DCIO_DBG_ASYNC_4BIT_SEL; + +/******************************************************* + * AOUT Enums + *******************************************************/ + +/* + * AOUT_EN enum + */ + +typedef enum AOUT_EN { +AOUT_DISABLE = 0x00000000, +AOUT_ENABLE = 0x00000001, +} AOUT_EN; + +/* + * AOUT_FIFO_START_ADDR enum + */ + +typedef enum AOUT_FIFO_START_ADDR { +AOUT_FIFO_START_ADDR_2 = 0x00000000, +AOUT_FIFO_START_ADDR_3 = 0x00000001, +} AOUT_FIFO_START_ADDR; + +/* + * AOUT_CRC_TEST_EN enum + */ + +typedef enum AOUT_CRC_TEST_EN { +AOUT_CRC_DISABLE = 0x00000000, +AOUT_CRC_ENABLE = 0x00000001, +} AOUT_CRC_TEST_EN; + +/* + * AOUT_CRC_SOFT_RESET enum + */ + +typedef enum AOUT_CRC_SOFT_RESET { +AOUT_CRC_NO_RESET = 0x00000000, +AOUT_CRC_RESET = 0x00000001, +} AOUT_CRC_SOFT_RESET; + +/* + * AOUT_CRC_CONT_EN enum + */ + +typedef enum AOUT_CRC_CONT_EN { +AOUT_CRC_ONE_SHOT = 0x00000000, +AOUT_CRC_CONT = 0x00000001, +} AOUT_CRC_CONT_EN; + +/* + * I2S_WORD_SIZE enum + */ + +typedef enum I2S_WORD_SIZE { +I2S_WORD_SIZE_32 = 0x00000000, +I2S_WORD_SIZE_16 = 0x00000001, +} I2S_WORD_SIZE; + +/* + * I2S_SAMPLE_ALIGNMENT enum + */ + +typedef enum I2S_SAMPLE_ALIGNMENT { +I2S_SAMPLE_LEFT_ALIGNED = 0x00000000, +I2S_SAMPLE_RIGHT_ALIGNED = 0x00000001, +} I2S_SAMPLE_ALIGNMENT; + +/* + * I2S_SAMPLE_BIT_ORDER enum + */ + +typedef enum I2S_SAMPLE_BIT_ORDER { +I2S_SAMPLE_BIT_ORDER_MSB = 0x00000000, +I2S_SAMPLE_BIT_ORDER_LSB = 0x00000001, +} I2S_SAMPLE_BIT_ORDER; + +/* + * I2S_LRCLK_POLARITY enum + */ + +typedef enum I2S_LRCLK_POLARITY { +I2S_LRCLK_LOW_LEFT = 0x00000000, +I2S_LRCLK_HIGH_LEFT = 0x00000001, +} I2S_LRCLK_POLARITY; + +/* + * I2S_WORD_ALIGNMENT enum + */ + +typedef enum I2S_WORD_ALIGNMENT { +I2S_WORD_ALTERNATE_ALIGNMENT = 0x00000000, +I2S_WORD_I2S_ALIGNMENT = 0x00000001, +} I2S_WORD_ALIGNMENT; + +/* + * SPDIF_INVERT_EN enum + */ + +typedef enum SPDIF_INVERT_EN { +SPDIF_INVERT_DISABLE = 0x00000000, +SPDIF_INVERT_ENABLE = 0x00000001, +} SPDIF_INVERT_EN; + +/******************************************************* + * DCO Enums + *******************************************************/ + +/* + * DPDBG_EN enum + */ + +typedef enum DPDBG_EN { +DPDBG_DISABLE = 0x00000000, +DPDBG_ENABLE = 0x00000001, +} DPDBG_EN; + +/* + * DPDBG_INPUT_EN enum + */ + +typedef enum DPDBG_INPUT_EN { +DPDBG_INPUT_DISABLE = 0x00000000, +DPDBG_INPUT_ENABLE = 0x00000001, +} DPDBG_INPUT_EN; + +/* + * DPDBG_ERROR_DETECTION_MODE enum + */ + +typedef enum DPDBG_ERROR_DETECTION_MODE { +DPDBG_ERROR_DETECTION_MODE_CSC = 0x00000000, +DPDBG_ERROR_DETECTION_MODE_RS_ENCODING = 0x00000001, +} DPDBG_ERROR_DETECTION_MODE; + +/* + * DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK enum + */ + +typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK { +DPDBG_FIFO_OVERFLOW_INT_DISABLE = 0x00000000, +DPDBG_FIFO_OVERFLOW_INT_ENABLE = 0x00000001, +} DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK; + +/* + * DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE enum + */ + +typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE { +DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED = 0x00000000, +DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED = 0x00000001, +} DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE; + +/* + * DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK enum + */ + +typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK { +DPDBG_FIFO_OVERFLOW_INT_NO_ACK = 0x00000000, +DPDBG_FIFO_OVERFLOW_INT_CLEAR = 0x00000001, +} DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK; + +/* + * PM_ASSERT_RESET enum + */ + +typedef enum PM_ASSERT_RESET { +PM_ASSERT_RESET_0 = 0x00000000, +PM_ASSERT_RESET_1 = 0x00000001, +} PM_ASSERT_RESET; + +/* + * DAC_MUX_SELECT enum + */ + +typedef enum DAC_MUX_SELECT { +DAC_MUX_SELECT_DACA = 0x00000000, +DAC_MUX_SELECT_DACB = 0x00000001, +} DAC_MUX_SELECT; + +/* + * TMDS_DVO_MUX_SELECT enum + */ + +typedef enum TMDS_DVO_MUX_SELECT { +TMDS_DVO_MUX_SELECT_B = 0x00000000, +TMDS_DVO_MUX_SELECT_G = 0x00000001, +TMDS_DVO_MUX_SELECT_R = 0x00000002, +TMDS_DVO_MUX_SELECT_RESERVED = 0x00000003, +} TMDS_DVO_MUX_SELECT; + +/* + * DACA_SOFT_RESET enum + */ + +typedef enum DACA_SOFT_RESET { +DACA_SOFT_RESET_0 = 0x00000000, +DACA_SOFT_RESET_1 = 0x00000001, +} DACA_SOFT_RESET; + +/* + * I2S0_SPDIF0_SOFT_RESET enum + */ + +typedef enum I2S0_SPDIF0_SOFT_RESET { +I2S0_SPDIF0_SOFT_RESET_0 = 0x00000000, +I2S0_SPDIF0_SOFT_RESET_1 = 0x00000001, +} I2S0_SPDIF0_SOFT_RESET; + +/* + * I2S1_SOFT_RESET enum + */ + +typedef enum I2S1_SOFT_RESET { +I2S1_SOFT_RESET_0 = 0x00000000, +I2S1_SOFT_RESET_1 = 0x00000001, +} I2S1_SOFT_RESET; + +/* + * SPDIF1_SOFT_RESET enum + */ + +typedef enum SPDIF1_SOFT_RESET { +SPDIF1_SOFT_RESET_0 = 0x00000000, +SPDIF1_SOFT_RESET_1 = 0x00000001, +} SPDIF1_SOFT_RESET; + +/* + * DB_CLK_SOFT_RESET enum + */ + +typedef enum DB_CLK_SOFT_RESET { +DB_CLK_SOFT_RESET_0 = 0x00000000, +DB_CLK_SOFT_RESET_1 = 0x00000001, +} DB_CLK_SOFT_RESET; + +/* + * FMT0_SOFT_RESET enum + */ + +typedef enum FMT0_SOFT_RESET { +FMT0_SOFT_RESET_0 = 0x00000000, +FMT0_SOFT_RESET_1 = 0x00000001, +} FMT0_SOFT_RESET; + +/* + * FMT1_SOFT_RESET enum + */ + +typedef enum FMT1_SOFT_RESET { +FMT1_SOFT_RESET_0 = 0x00000000, +FMT1_SOFT_RESET_1 = 0x00000001, +} FMT1_SOFT_RESET; + +/* + * FMT2_SOFT_RESET enum + */ + +typedef enum FMT2_SOFT_RESET { +FMT2_SOFT_RESET_0 = 0x00000000, +FMT2_SOFT_RESET_1 = 0x00000001, +} FMT2_SOFT_RESET; + +/* + * FMT3_SOFT_RESET enum + */ + +typedef enum FMT3_SOFT_RESET { +FMT3_SOFT_RESET_0 = 0x00000000, +FMT3_SOFT_RESET_1 = 0x00000001, +} FMT3_SOFT_RESET; + +/* + * FMT4_SOFT_RESET enum + */ + +typedef enum FMT4_SOFT_RESET { +FMT4_SOFT_RESET_0 = 0x00000000, +FMT4_SOFT_RESET_1 = 0x00000001, +} FMT4_SOFT_RESET; + +/* + * FMT5_SOFT_RESET enum + */ + +typedef enum FMT5_SOFT_RESET { +FMT5_SOFT_RESET_0 = 0x00000000, +FMT5_SOFT_RESET_1 = 0x00000001, +} FMT5_SOFT_RESET; + +/* + * MVP_SOFT_RESET enum + */ + +typedef enum MVP_SOFT_RESET { +MVP_SOFT_RESET_0 = 0x00000000, +MVP_SOFT_RESET_1 = 0x00000001, +} MVP_SOFT_RESET; + +/* + * ABM_SOFT_RESET enum + */ + +typedef enum ABM_SOFT_RESET { +ABM_SOFT_RESET_0 = 0x00000000, +ABM_SOFT_RESET_1 = 0x00000001, +} ABM_SOFT_RESET; + +/* + * DVO_SOFT_RESET enum + */ + +typedef enum DVO_SOFT_RESET { +DVO_SOFT_RESET_0 = 0x00000000, +DVO_SOFT_RESET_1 = 0x00000001, +} DVO_SOFT_RESET; + +/* + * DIGA_FE_SOFT_RESET enum + */ + +typedef enum DIGA_FE_SOFT_RESET { +DIGA_FE_SOFT_RESET_0 = 0x00000000, +DIGA_FE_SOFT_RESET_1 = 0x00000001, +} DIGA_FE_SOFT_RESET; + +/* + * DIGA_BE_SOFT_RESET enum + */ + +typedef enum DIGA_BE_SOFT_RESET { +DIGA_BE_SOFT_RESET_0 = 0x00000000, +DIGA_BE_SOFT_RESET_1 = 0x00000001, +} DIGA_BE_SOFT_RESET; + +/* + * DIGB_FE_SOFT_RESET enum + */ + +typedef enum DIGB_FE_SOFT_RESET { +DIGB_FE_SOFT_RESET_0 = 0x00000000, +DIGB_FE_SOFT_RESET_1 = 0x00000001, +} DIGB_FE_SOFT_RESET; + +/* + * DIGB_BE_SOFT_RESET enum + */ + +typedef enum DIGB_BE_SOFT_RESET { +DIGB_BE_SOFT_RESET_0 = 0x00000000, +DIGB_BE_SOFT_RESET_1 = 0x00000001, +} DIGB_BE_SOFT_RESET; + +/* + * DIGC_FE_SOFT_RESET enum + */ + +typedef enum DIGC_FE_SOFT_RESET { +DIGC_FE_SOFT_RESET_0 = 0x00000000, +DIGC_FE_SOFT_RESET_1 = 0x00000001, +} DIGC_FE_SOFT_RESET; + +/* + * DIGC_BE_SOFT_RESET enum + */ + +typedef enum DIGC_BE_SOFT_RESET { +DIGC_BE_SOFT_RESET_0 = 0x00000000, +DIGC_BE_SOFT_RESET_1 = 0x00000001, +} DIGC_BE_SOFT_RESET; + +/* + * DIGD_FE_SOFT_RESET enum + */ + +typedef enum DIGD_FE_SOFT_RESET { +DIGD_FE_SOFT_RESET_0 = 0x00000000, +DIGD_FE_SOFT_RESET_1 = 0x00000001, +} DIGD_FE_SOFT_RESET; + +/* + * DIGD_BE_SOFT_RESET enum + */ + +typedef enum DIGD_BE_SOFT_RESET { +DIGD_BE_SOFT_RESET_0 = 0x00000000, +DIGD_BE_SOFT_RESET_1 = 0x00000001, +} DIGD_BE_SOFT_RESET; + +/* + * DIGE_FE_SOFT_RESET enum + */ + +typedef enum DIGE_FE_SOFT_RESET { +DIGE_FE_SOFT_RESET_0 = 0x00000000, +DIGE_FE_SOFT_RESET_1 = 0x00000001, +} DIGE_FE_SOFT_RESET; + +/* + * DIGE_BE_SOFT_RESET enum + */ + +typedef enum DIGE_BE_SOFT_RESET { +DIGE_BE_SOFT_RESET_0 = 0x00000000, +DIGE_BE_SOFT_RESET_1 = 0x00000001, +} DIGE_BE_SOFT_RESET; + +/* + * DIGF_FE_SOFT_RESET enum + */ + +typedef enum DIGF_FE_SOFT_RESET { +DIGF_FE_SOFT_RESET_0 = 0x00000000, +DIGF_FE_SOFT_RESET_1 = 0x00000001, +} DIGF_FE_SOFT_RESET; + +/* + * DIGF_BE_SOFT_RESET enum + */ + +typedef enum DIGF_BE_SOFT_RESET { +DIGF_BE_SOFT_RESET_0 = 0x00000000, +DIGF_BE_SOFT_RESET_1 = 0x00000001, +} DIGF_BE_SOFT_RESET; + +/* + * DIGG_FE_SOFT_RESET enum + */ + +typedef enum DIGG_FE_SOFT_RESET { +DIGG_FE_SOFT_RESET_0 = 0x00000000, +DIGG_FE_SOFT_RESET_1 = 0x00000001, +} DIGG_FE_SOFT_RESET; + +/* + * DIGG_BE_SOFT_RESET enum + */ + +typedef enum DIGG_BE_SOFT_RESET { +DIGG_BE_SOFT_RESET_0 = 0x00000000, +DIGG_BE_SOFT_RESET_1 = 0x00000001, +} DIGG_BE_SOFT_RESET; + +/* + * DPDBG_SOFT_RESET enum + */ + +typedef enum DPDBG_SOFT_RESET { +DPDBG_SOFT_RESET_0 = 0x00000000, +DPDBG_SOFT_RESET_1 = 0x00000001, +} DPDBG_SOFT_RESET; + +/* + * DIGLPA_FE_SOFT_RESET enum + */ + +typedef enum DIGLPA_FE_SOFT_RESET { +DIGLPA_FE_SOFT_RESET_0 = 0x00000000, +DIGLPA_FE_SOFT_RESET_1 = 0x00000001, +} DIGLPA_FE_SOFT_RESET; + +/* + * DIGLPA_BE_SOFT_RESET enum + */ + +typedef enum DIGLPA_BE_SOFT_RESET { +DIGLPA_BE_SOFT_RESET_0 = 0x00000000, +DIGLPA_BE_SOFT_RESET_1 = 0x00000001, +} DIGLPA_BE_SOFT_RESET; + +/* + * DIGLPB_FE_SOFT_RESET enum + */ + +typedef enum DIGLPB_FE_SOFT_RESET { +DIGLPB_FE_SOFT_RESET_0 = 0x00000000, +DIGLPB_FE_SOFT_RESET_1 = 0x00000001, +} DIGLPB_FE_SOFT_RESET; + +/* + * DIGLPB_BE_SOFT_RESET enum + */ + +typedef enum DIGLPB_BE_SOFT_RESET { +DIGLPB_BE_SOFT_RESET_0 = 0x00000000, +DIGLPB_BE_SOFT_RESET_1 = 0x00000001, +} DIGLPB_BE_SOFT_RESET; + +/* + * GENERICA_STEREOSYNC_SEL enum + */ + +typedef enum GENERICA_STEREOSYNC_SEL { +GENERICA_STEREOSYNC_SEL_D1 = 0x00000000, +GENERICA_STEREOSYNC_SEL_D2 = 0x00000001, +GENERICA_STEREOSYNC_SEL_D3 = 0x00000002, +GENERICA_STEREOSYNC_SEL_D4 = 0x00000003, +GENERICA_STEREOSYNC_SEL_D5 = 0x00000004, +GENERICA_STEREOSYNC_SEL_D6 = 0x00000005, +GENERICA_STEREOSYNC_SEL_RESERVED = 0x00000006, +} GENERICA_STEREOSYNC_SEL; + +/* + * GENERICB_STEREOSYNC_SEL enum + */ + +typedef enum GENERICB_STEREOSYNC_SEL { +GENERICB_STEREOSYNC_SEL_D1 = 0x00000000, +GENERICB_STEREOSYNC_SEL_D2 = 0x00000001, +GENERICB_STEREOSYNC_SEL_D3 = 0x00000002, +GENERICB_STEREOSYNC_SEL_D4 = 0x00000003, +GENERICB_STEREOSYNC_SEL_D5 = 0x00000004, +GENERICB_STEREOSYNC_SEL_D6 = 0x00000005, +GENERICB_STEREOSYNC_SEL_RESERVED = 0x00000006, +} GENERICB_STEREOSYNC_SEL; + +/* + * DCO_DBG_BLOCK_SEL enum + */ + +typedef enum DCO_DBG_BLOCK_SEL { +DCO_DBG_BLOCK_SEL_DCO = 0x00000000, +DCO_DBG_BLOCK_SEL_ABM = 0x00000001, +DCO_DBG_BLOCK_SEL_DVO = 0x00000002, +DCO_DBG_BLOCK_SEL_DAC = 0x00000003, +DCO_DBG_BLOCK_SEL_MVP = 0x00000004, +DCO_DBG_BLOCK_SEL_FMT0 = 0x00000005, +DCO_DBG_BLOCK_SEL_FMT1 = 0x00000006, +DCO_DBG_BLOCK_SEL_FMT2 = 0x00000007, +DCO_DBG_BLOCK_SEL_FMT3 = 0x00000008, +DCO_DBG_BLOCK_SEL_FMT4 = 0x00000009, +DCO_DBG_BLOCK_SEL_FMT5 = 0x0000000a, +DCO_DBG_BLOCK_SEL_DIGFE_A = 0x0000000b, +DCO_DBG_BLOCK_SEL_DIGFE_B = 0x0000000c, +DCO_DBG_BLOCK_SEL_DIGFE_C = 0x0000000d, +DCO_DBG_BLOCK_SEL_DIGFE_D = 0x0000000e, +DCO_DBG_BLOCK_SEL_DIGFE_E = 0x0000000f, +DCO_DBG_BLOCK_SEL_DIGFE_F = 0x00000010, +DCO_DBG_BLOCK_SEL_DIGFE_G = 0x00000011, +DCO_DBG_BLOCK_SEL_DIGA = 0x00000012, +DCO_DBG_BLOCK_SEL_DIGB = 0x00000013, +DCO_DBG_BLOCK_SEL_DIGC = 0x00000014, +DCO_DBG_BLOCK_SEL_DIGD = 0x00000015, +DCO_DBG_BLOCK_SEL_DIGE = 0x00000016, +DCO_DBG_BLOCK_SEL_DIGF = 0x00000017, +DCO_DBG_BLOCK_SEL_DIGG = 0x00000018, +DCO_DBG_BLOCK_SEL_DPFE_A = 0x00000019, +DCO_DBG_BLOCK_SEL_DPFE_B = 0x0000001a, +DCO_DBG_BLOCK_SEL_DPFE_C = 0x0000001b, +DCO_DBG_BLOCK_SEL_DPFE_D = 0x0000001c, +DCO_DBG_BLOCK_SEL_DPFE_E = 0x0000001d, +DCO_DBG_BLOCK_SEL_DPFE_F = 0x0000001e, +DCO_DBG_BLOCK_SEL_DPFE_G = 0x0000001f, +DCO_DBG_BLOCK_SEL_DPA = 0x00000020, +DCO_DBG_BLOCK_SEL_DPB = 0x00000021, +DCO_DBG_BLOCK_SEL_DPC = 0x00000022, +DCO_DBG_BLOCK_SEL_DPD = 0x00000023, +DCO_DBG_BLOCK_SEL_DPE = 0x00000024, +DCO_DBG_BLOCK_SEL_DPF = 0x00000025, +DCO_DBG_BLOCK_SEL_DPG = 0x00000026, +DCO_DBG_BLOCK_SEL_AUX0 = 0x00000027, +DCO_DBG_BLOCK_SEL_AUX1 = 0x00000028, +DCO_DBG_BLOCK_SEL_AUX2 = 0x00000029, +DCO_DBG_BLOCK_SEL_AUX3 = 0x0000002a, +DCO_DBG_BLOCK_SEL_AUX4 = 0x0000002b, +DCO_DBG_BLOCK_SEL_AUX5 = 0x0000002c, +DCO_DBG_BLOCK_SEL_PERFMON_DCO = 0x0000002d, +DCO_DBG_BLOCK_SEL_AUDIO_OUT = 0x0000002e, +DCO_DBG_BLOCK_SEL_DIGLPFEA = 0x0000002f, +DCO_DBG_BLOCK_SEL_DIGLPFEB = 0x00000030, +DCO_DBG_BLOCK_SEL_DIGLPA = 0x00000031, +DCO_DBG_BLOCK_SEL_DIGLPB = 0x00000032, +DCO_DBG_BLOCK_SEL_DPLPFEA = 0x00000033, +DCO_DBG_BLOCK_SEL_DPLPFEB = 0x00000034, +DCO_DBG_BLOCK_SEL_DPLPA = 0x00000035, +DCO_DBG_BLOCK_SEL_DPLPB = 0x00000036, +} DCO_DBG_BLOCK_SEL; + +/* + * DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE enum + */ + +typedef enum DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE { +DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0x00000000, +DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 0x00000001, +} DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE; + +/* + * FMT420_MEMORY_SOURCE_SEL enum + */ + +typedef enum FMT420_MEMORY_SOURCE_SEL { +FMT420_MEMORY_SOURCE_SEL_FMT0 = 0x00000000, +FMT420_MEMORY_SOURCE_SEL_FMT1 = 0x00000001, +FMT420_MEMORY_SOURCE_SEL_FMT2 = 0x00000002, +FMT420_MEMORY_SOURCE_SEL_FMT3 = 0x00000003, +FMT420_MEMORY_SOURCE_SEL_FMT4 = 0x00000004, +FMT420_MEMORY_SOURCE_SEL_FMT5 = 0x00000005, +FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED = 0x00000006, +} FMT420_MEMORY_SOURCE_SEL; + +/******************************************************* + * DOUT_I2C Enums + *******************************************************/ + +/* + * DOUT_I2C_CONTROL_GO enum + */ + +typedef enum DOUT_I2C_CONTROL_GO { +DOUT_I2C_CONTROL_STOP_TRANSFER = 0x00000000, +DOUT_I2C_CONTROL_START_TRANSFER = 0x00000001, +} DOUT_I2C_CONTROL_GO; + +/* + * DOUT_I2C_CONTROL_SOFT_RESET enum + */ + +typedef enum DOUT_I2C_CONTROL_SOFT_RESET { +DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x00000000, +DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 0x00000001, +} DOUT_I2C_CONTROL_SOFT_RESET; + +/* + * DOUT_I2C_CONTROL_SEND_RESET enum + */ + +typedef enum DOUT_I2C_CONTROL_SEND_RESET { +DOUT_I2C_CONTROL__NOT_SEND_RESET = 0x00000000, +DOUT_I2C_CONTROL__SEND_RESET = 0x00000001, +} DOUT_I2C_CONTROL_SEND_RESET; + +/* + * DOUT_I2C_CONTROL_SW_STATUS_RESET enum + */ + +typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET { +DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0x00000000, +DOUT_I2C_CONTROL_RESET_SW_STATUS = 0x00000001, +} DOUT_I2C_CONTROL_SW_STATUS_RESET; + +/* + * DOUT_I2C_CONTROL_DDC_SELECT enum + */ + +typedef enum DOUT_I2C_CONTROL_DDC_SELECT { +DOUT_I2C_CONTROL_SELECT_DDC1 = 0x00000000, +DOUT_I2C_CONTROL_SELECT_DDC2 = 0x00000001, +DOUT_I2C_CONTROL_SELECT_DDC3 = 0x00000002, +DOUT_I2C_CONTROL_SELECT_DDC4 = 0x00000003, +DOUT_I2C_CONTROL_SELECT_DDC5 = 0x00000004, +DOUT_I2C_CONTROL_SELECT_DDC6 = 0x00000005, +DOUT_I2C_CONTROL_SELECT_DDCVGA = 0x00000006, +} DOUT_I2C_CONTROL_DDC_SELECT; + +/* + * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum + */ + +typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT { +DOUT_I2C_CONTROL_TRANS0 = 0x00000000, +DOUT_I2C_CONTROL_TRANS0_TRANS1 = 0x00000001, +DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 0x00000002, +DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 0x00000003, +} DOUT_I2C_CONTROL_TRANSACTION_COUNT; + +/* + * DOUT_I2C_CONTROL_DBG_REF_SEL enum + */ + +typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL { +DOUT_I2C_CONTROL_NORMAL_DEBUG = 0x00000000, +DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 0x00000001, +} DOUT_I2C_CONTROL_DBG_REF_SEL; + +/* + * DOUT_I2C_ARBITRATION_SW_PRIORITY enum + */ + +typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY { +DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0x00000000, +DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 0x00000001, +DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x00000002, +DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x00000003, +} DOUT_I2C_ARBITRATION_SW_PRIORITY; + +/* + * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum + */ + +typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO { +DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0x00000000, +DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 0x00000001, +} DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO; + +/* + * DOUT_I2C_ARBITRATION_ABORT_XFER enum + */ + +typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER { +DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x00000000, +DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 0x00000001, +} DOUT_I2C_ARBITRATION_ABORT_XFER; + +/* + * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum + */ + +typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ { +DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x00000000, +DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 0x00000001, +} DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ; + +/* + * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum + */ + +typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG { +DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x00000000, +DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 0x00000001, +} DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG; + +/* + * DOUT_I2C_ACK enum + */ + +typedef enum DOUT_I2C_ACK { +DOUT_I2C_NO_ACK = 0x00000000, +DOUT_I2C_ACK_TO_CLEAN = 0x00000001, +} DOUT_I2C_ACK; + +/* + * DOUT_I2C_DDC_SPEED_THRESHOLD enum + */ + +typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD { +DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0x00000000, +DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 0x00000001, +DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 0x00000002, +DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 0x00000003, +} DOUT_I2C_DDC_SPEED_THRESHOLD; + +/* + * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum + */ + +typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN { +DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000, +DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 0x00000001, +} DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN; + +/* + * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum + */ + +typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL { +DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0x00000000, +DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 0x00000001, +} DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL; + +/* + * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum + */ + +typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE { +DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0x00000000, +DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 0x00000001, +} DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE; + +/* + * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum + */ + +typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN { +DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000, +DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 0x00000001, +} DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN; + +/* + * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum + */ + +typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK { +DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0x00000000, +DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 0x00000001, +} DOUT_I2C_TRANSACTION_STOP_ON_NACK; + +/* + * DOUT_I2C_DATA_INDEX_WRITE enum + */ + +typedef enum DOUT_I2C_DATA_INDEX_WRITE { +DOUT_I2C_DATA__NOT_INDEX_WRITE = 0x00000000, +DOUT_I2C_DATA__INDEX_WRITE = 0x00000001, +} DOUT_I2C_DATA_INDEX_WRITE; + +/* + * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum + */ + +typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET { +DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000000, +DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000001, +} DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET; + +/* + * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum + */ + +typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE { +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0x00000000, +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 0x00000001, +} DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE; + +/******************************************************* + * FBC Enums + *******************************************************/ + +/* + * FBC_IDLE_MASK_MASK_BITS enum + */ + +typedef enum FBC_IDLE_MASK_MASK_BITS { +FBC_IDLE_MASK_DISP_REG_UPDATE = 0x00000000, +FBC_IDLE_MASK_RESERVED1 = 0x00000001, +FBC_IDLE_MASK_FBC_GRPH_COMP_EN = 0x00000002, +FBC_IDLE_MASK_FBC_MIN_COMPRESSION = 0x00000003, +FBC_IDLE_MASK_FBC_ALPHA_COMP_EN = 0x00000004, +FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN = 0x00000005, +FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF = 0x00000006, +FBC_IDLE_MASK_RESERVED7 = 0x00000007, +FBC_IDLE_MASK_RESERVED8 = 0x00000008, +FBC_IDLE_MASK_RESERVED9 = 0x00000009, +FBC_IDLE_MASK_RESERVED10 = 0x0000000a, +FBC_IDLE_MASK_RESERVED11 = 0x0000000b, +FBC_IDLE_MASK_RESERVED12 = 0x0000000c, +FBC_IDLE_MASK_RESERVED13 = 0x0000000d, +FBC_IDLE_MASK_RESERVED14 = 0x0000000e, +FBC_IDLE_MASK_RESERVED15 = 0x0000000f, +FBC_IDLE_MASK_RESERVED16 = 0x00000010, +FBC_IDLE_MASK_RESERVED17 = 0x00000011, +FBC_IDLE_MASK_RESERVED18 = 0x00000012, +FBC_IDLE_MASK_RESERVED19 = 0x00000013, +FBC_IDLE_MASK_RESERVED20 = 0x00000014, +FBC_IDLE_MASK_RESERVED21 = 0x00000015, +FBC_IDLE_MASK_RESERVED22 = 0x00000016, +FBC_IDLE_MASK_RESERVED23 = 0x00000017, +FBC_IDLE_MASK_MC_HIT_REGION_0 = 0x00000018, +FBC_IDLE_MASK_MC_HIT_REGION_1 = 0x00000019, +FBC_IDLE_MASK_MC_HIT_REGION_2 = 0x0000001a, +FBC_IDLE_MASK_MC_HIT_REGION_3 = 0x0000001b, +FBC_IDLE_MASK_MC_WRITE = 0x0000001c, +FBC_IDLE_MASK_RESERVED29 = 0x0000001d, +FBC_IDLE_MASK_RESERVED30 = 0x0000001e, +FBC_IDLE_MASK_RESERVED31 = 0x0000001f, +} FBC_IDLE_MASK_MASK_BITS; + +/******************************************************* + * DPCSRX Enums + *******************************************************/ + +/* + * DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL enum + */ + +typedef enum DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL { +DPCSRX_BPHY_PCS_RX0_CLK = 0x00000000, +DPCSRX_BPHY_PCS_RX1_CLK = 0x00000001, +DPCSRX_BPHY_PCS_RX2_CLK = 0x00000002, +DPCSRX_BPHY_PCS_RX3_CLK = 0x00000003, +} DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL; + +/* + * DPCSRX_DBG_CFGCLK_SEL enum + */ + +typedef enum DPCSRX_DBG_CFGCLK_SEL { +DPCSRX_DBG_CFGCLK_SEL_DC_DPCS_INF = 0x00000000, +DPCSRX_DBG_CFGCLK_SEL_DPCS_BPHY_INF = 0x00000001, +DPCSRX_DBG_CFGCLK_SEL_CBUS_SLAVE = 0x00000002, +DPCSRX_DBG_CFGCLK_SEL_CBUS_MASTER = 0x00000003, +} DPCSRX_DBG_CFGCLK_SEL; + +/* + * DPCSRX_RX_SYMCLK_SEL enum + */ + +typedef enum DPCSRX_RX_SYMCLK_SEL { +DPCSRX_DBG_RX_SYMCLK_SEL_OUT0 = 0x00000000, +DPCSRX_DBG_RX_SYMCLK_SEL_OUT1 = 0x00000001, +DPCSRX_DBG_RX_SYMCLK_SEL_INT = 0x00000002, +} DPCSRX_RX_SYMCLK_SEL; + +/******************************************************* + * DPCSTX Enums + *******************************************************/ + +/* + * DPCSTX_DBG_CFGCLK_SEL enum + */ + +typedef enum DPCSTX_DBG_CFGCLK_SEL { +DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF = 0x00000000, +DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF = 0x00000001, +DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE = 0x00000002, +DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER = 0x00000003, +} DPCSTX_DBG_CFGCLK_SEL; + +/* + * DPCSTX_TX_SYMCLK_SEL enum + */ + +typedef enum DPCSTX_TX_SYMCLK_SEL { +DPCSTX_DBG_TX_SYMCLK_SEL_IN0 = 0x00000000, +DPCSTX_DBG_TX_SYMCLK_SEL_IN1 = 0x00000001, +DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR = 0x00000002, +} DPCSTX_TX_SYMCLK_SEL; + +/* + * DPCSTX_TX_SYMCLK_DIV2_SEL enum + */ + +typedef enum DPCSTX_TX_SYMCLK_DIV2_SEL { +DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0 = 0x00000000, +DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1 = 0x00000001, +DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2 = 0x00000002, +DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3 = 0x00000003, +DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD = 0x00000004, +DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT = 0x00000005, +} DPCSTX_TX_SYMCLK_DIV2_SEL; + +/******************************************************* + * CB Enums + *******************************************************/ + +/* + * SurfaceNumber enum + */ + +typedef enum SurfaceNumber { +NUMBER_UNORM = 0x00000000, +NUMBER_SNORM = 0x00000001, +NUMBER_USCALED = 0x00000002, +NUMBER_SSCALED = 0x00000003, +NUMBER_UINT = 0x00000004, +NUMBER_SINT = 0x00000005, +NUMBER_SRGB = 0x00000006, +NUMBER_FLOAT = 0x00000007, +} SurfaceNumber; + +/* + * SurfaceSwap enum + */ + +typedef enum SurfaceSwap { +SWAP_STD = 0x00000000, +SWAP_ALT = 0x00000001, +SWAP_STD_REV = 0x00000002, +SWAP_ALT_REV = 0x00000003, +} SurfaceSwap; + +/* + * CBMode enum + */ + +typedef enum CBMode { +CB_DISABLE = 0x00000000, +CB_NORMAL = 0x00000001, +CB_ELIMINATE_FAST_CLEAR = 0x00000002, +CB_RESOLVE = 0x00000003, +CB_DECOMPRESS = 0x00000004, +CB_FMASK_DECOMPRESS = 0x00000005, +CB_DCC_DECOMPRESS = 0x00000006, +} CBMode; + +/* + * RoundMode enum + */ + +typedef enum RoundMode { +ROUND_BY_HALF = 0x00000000, +ROUND_TRUNCATE = 0x00000001, +} RoundMode; + +/* + * SourceFormat enum + */ + +typedef enum SourceFormat { +EXPORT_4C_32BPC = 0x00000000, +EXPORT_4C_16BPC = 0x00000001, +EXPORT_2C_32BPC_GR = 0x00000002, +EXPORT_2C_32BPC_AR = 0x00000003, +} SourceFormat; + +/* + * BlendOp enum + */ + +typedef enum BlendOp { +BLEND_ZERO = 0x00000000, +BLEND_ONE = 0x00000001, +BLEND_SRC_COLOR = 0x00000002, +BLEND_ONE_MINUS_SRC_COLOR = 0x00000003, +BLEND_SRC_ALPHA = 0x00000004, +BLEND_ONE_MINUS_SRC_ALPHA = 0x00000005, +BLEND_DST_ALPHA = 0x00000006, +BLEND_ONE_MINUS_DST_ALPHA = 0x00000007, +BLEND_DST_COLOR = 0x00000008, +BLEND_ONE_MINUS_DST_COLOR = 0x00000009, +BLEND_SRC_ALPHA_SATURATE = 0x0000000a, +BLEND_BOTH_SRC_ALPHA = 0x0000000b, +BLEND_BOTH_INV_SRC_ALPHA = 0x0000000c, +BLEND_CONSTANT_COLOR = 0x0000000d, +BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0000000e, +BLEND_SRC1_COLOR = 0x0000000f, +BLEND_INV_SRC1_COLOR = 0x00000010, +BLEND_SRC1_ALPHA = 0x00000011, +BLEND_INV_SRC1_ALPHA = 0x00000012, +BLEND_CONSTANT_ALPHA = 0x00000013, +BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x00000014, +} BlendOp; + +/* + * CombFunc enum + */ + +typedef enum CombFunc { +COMB_DST_PLUS_SRC = 0x00000000, +COMB_SRC_MINUS_DST = 0x00000001, +COMB_MIN_DST_SRC = 0x00000002, +COMB_MAX_DST_SRC = 0x00000003, +COMB_DST_MINUS_SRC = 0x00000004, +} CombFunc; + +/* + * BlendOpt enum + */ + +typedef enum BlendOpt { +FORCE_OPT_AUTO = 0x00000000, +FORCE_OPT_DISABLE = 0x00000001, +FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x00000002, +FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x00000003, +FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x00000004, +FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x00000005, +FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x00000006, +FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x00000007, +} BlendOpt; + +/* + * CmaskCode enum + */ + +typedef enum CmaskCode { +CMASK_CLR00_F0 = 0x00000000, +CMASK_CLR00_F1 = 0x00000001, +CMASK_CLR00_F2 = 0x00000002, +CMASK_CLR00_FX = 0x00000003, +CMASK_CLR01_F0 = 0x00000004, +CMASK_CLR01_F1 = 0x00000005, +CMASK_CLR01_F2 = 0x00000006, +CMASK_CLR01_FX = 0x00000007, +CMASK_CLR10_F0 = 0x00000008, +CMASK_CLR10_F1 = 0x00000009, +CMASK_CLR10_F2 = 0x0000000a, +CMASK_CLR10_FX = 0x0000000b, +CMASK_CLR11_F0 = 0x0000000c, +CMASK_CLR11_F1 = 0x0000000d, +CMASK_CLR11_F2 = 0x0000000e, +CMASK_CLR11_FX = 0x0000000f, +} CmaskCode; + +/* + * CmaskAddr enum + */ + +typedef enum CmaskAddr { +CMASK_ADDR_TILED = 0x00000000, +CMASK_ADDR_LINEAR = 0x00000001, +CMASK_ADDR_COMPATIBLE = 0x00000002, +} CmaskAddr; + +/* + * MemArbMode enum + */ + +typedef enum MemArbMode { +MEM_ARB_MODE_FIXED = 0x00000000, +MEM_ARB_MODE_AGE = 0x00000001, +MEM_ARB_MODE_WEIGHT = 0x00000002, +MEM_ARB_MODE_BOTH = 0x00000003, +} MemArbMode; + +/* + * CBPerfSel enum + */ + +typedef enum CBPerfSel { +CB_PERF_SEL_NONE = 0x00000000, +CB_PERF_SEL_BUSY = 0x00000001, +CB_PERF_SEL_CORE_SCLK_VLD = 0x00000002, +CB_PERF_SEL_REG_SCLK0_VLD = 0x00000003, +CB_PERF_SEL_REG_SCLK1_VLD = 0x00000004, +CB_PERF_SEL_DRAWN_QUAD = 0x00000005, +CB_PERF_SEL_DRAWN_PIXEL = 0x00000006, +CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x00000007, +CB_PERF_SEL_DRAWN_TILE = 0x00000008, +CB_PERF_SEL_DB_CB_TILE_VALID_READY = 0x00000009, +CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0x0000000a, +CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 0x0000000b, +CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 0x0000000c, +CB_PERF_SEL_CM_FC_TILE_VALID_READY = 0x0000000d, +CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 0x0000000e, +CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 0x0000000f, +CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 0x00000010, +CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 0x00000011, +CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x00000012, +CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 0x00000013, +CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 0x00000014, +CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 0x00000015, +CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 0x00000016, +CB_PERF_SEL_LQUAD_NO_TILE = 0x00000017, +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 0x00000018, +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x00000019, +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x0000001a, +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x0000001b, +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x0000001c, +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x0000001d, +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR = 0x0000001e, +CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x0000001f, +CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x00000020, +CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK = 0x00000021, +CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x00000022, +CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x00000023, +CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 0x00000024, +CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 0x00000025, +CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 0x00000026, +CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 0x00000027, +CB_PERF_SEL_FOP_IN_VALID_READY = 0x00000028, +CB_PERF_SEL_FOP_IN_VALID_READYB = 0x00000029, +CB_PERF_SEL_FOP_IN_VALIDB_READY = 0x0000002a, +CB_PERF_SEL_FOP_IN_VALIDB_READYB = 0x0000002b, +CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 0x0000002c, +CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 0x0000002d, +CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 0x0000002e, +CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x0000002f, +CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 0x00000030, +CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 0x00000031, +CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 0x00000032, +CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 0x00000033, +CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 0x00000034, +CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 0x00000035, +CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 0x00000036, +CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 0x00000037, +CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x00000038, +CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x00000039, +CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x0000003a, +CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x0000003b, +CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x0000003c, +CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x0000003d, +CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x0000003e, +CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x0000003f, +CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 0x00000040, +CB_PERF_SEL_CM_CACHE_HIT = 0x00000041, +CB_PERF_SEL_CM_CACHE_TAG_MISS = 0x00000042, +CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 0x00000043, +CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 0x00000044, +CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000045, +CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000046, +CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000047, +CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 0x00000048, +CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 0x00000049, +CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 0x0000004a, +CB_PERF_SEL_CM_CACHE_STALL = 0x0000004b, +CB_PERF_SEL_CM_CACHE_FLUSH = 0x0000004c, +CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 0x0000004d, +CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 0x0000004e, +CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000004f, +CB_PERF_SEL_FC_CACHE_HIT = 0x00000050, +CB_PERF_SEL_FC_CACHE_TAG_MISS = 0x00000051, +CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 0x00000052, +CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 0x00000053, +CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000054, +CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000055, +CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000056, +CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 0x00000057, +CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 0x00000058, +CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 0x00000059, +CB_PERF_SEL_FC_CACHE_STALL = 0x0000005a, +CB_PERF_SEL_FC_CACHE_FLUSH = 0x0000005b, +CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 0x0000005c, +CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 0x0000005d, +CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000005e, +CB_PERF_SEL_CC_CACHE_HIT = 0x0000005f, +CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x00000060, +CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x00000061, +CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x00000062, +CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000063, +CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000064, +CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000065, +CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x00000066, +CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x00000067, +CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x00000068, +CB_PERF_SEL_CC_CACHE_STALL = 0x00000069, +CB_PERF_SEL_CC_CACHE_FLUSH = 0x0000006a, +CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x0000006b, +CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x0000006c, +CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000006d, +CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x0000006e, +CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 0x0000006f, +CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 0x00000070, +CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 0x00000071, +CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 0x00000072, +CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 0x00000073, +CB_PERF_SEL_CM_MC_WRITE_REQUEST = 0x00000074, +CB_PERF_SEL_FC_MC_WRITE_REQUEST = 0x00000075, +CB_PERF_SEL_CC_MC_WRITE_REQUEST = 0x00000076, +CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000077, +CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000078, +CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000079, +CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 0x0000007a, +CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 0x0000007b, +CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 0x0000007c, +CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 0x0000007d, +CB_PERF_SEL_CM_MC_READ_REQUEST = 0x0000007e, +CB_PERF_SEL_FC_MC_READ_REQUEST = 0x0000007f, +CB_PERF_SEL_CC_MC_READ_REQUEST = 0x00000080, +CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 0x00000081, +CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 0x00000082, +CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x00000083, +CB_PERF_SEL_CM_TQ_FULL = 0x00000084, +CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 0x00000085, +CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 0x00000086, +CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 0x00000087, +CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 0x00000088, +CB_PERF_SEL_FOP_FMASK_RAW_STALL = 0x00000089, +CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 0x0000008a, +CB_PERF_SEL_CC_SF_FULL = 0x0000008b, +CB_PERF_SEL_CC_RB_FULL = 0x0000008c, +CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 0x0000008d, +CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 0x0000008e, +CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 0x0000008f, +CB_PERF_SEL_EVENT = 0x00000090, +CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x00000091, +CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x00000092, +CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x00000093, +CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000094, +CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x00000095, +CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x00000096, +CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x00000097, +CB_PERF_SEL_CC_SURFACE_SYNC = 0x00000098, +CB_PERF_SEL_CMASK_READ_DATA_0xC = 0x00000099, +CB_PERF_SEL_CMASK_READ_DATA_0xD = 0x0000009a, +CB_PERF_SEL_CMASK_READ_DATA_0xE = 0x0000009b, +CB_PERF_SEL_CMASK_READ_DATA_0xF = 0x0000009c, +CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 0x0000009d, +CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 0x0000009e, +CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 0x0000009f, +CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 0x000000a0, +CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 0x000000a1, +CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0x000000a2, +CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 0x000000a3, +CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 0x000000a4, +CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 0x000000a5, +CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 0x000000a6, +CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 0x000000a7, +CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 0x000000a8, +CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 0x000000a9, +CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 0x000000aa, +CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 0x000000ab, +CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 0x000000ac, +CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 0x000000ad, +CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 0x000000ae, +CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 0x000000af, +CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 0x000000b0, +CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 0x000000b1, +CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 0x000000b2, +CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 0x000000b3, +CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 0x000000b4, +CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 0x000000b5, +CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 0x000000b6, +CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 0x000000b7, +CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 0x000000b8, +CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 0x000000b9, +CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 0x000000ba, +CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 0x000000bb, +CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 0x000000bc, +CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 0x000000bd, +CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 0x000000be, +CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 0x000000bf, +CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 0x000000c0, +CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 0x000000c1, +CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 0x000000c2, +CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 0x000000c3, +CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 0x000000c4, +CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 0x000000c5, +CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 0x000000c6, +CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 0x000000c7, +CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 0x000000c8, +CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 0x000000c9, +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 0x000000ca, +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 0x000000cb, +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 0x000000cc, +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 0x000000cd, +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 0x000000ce, +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 0x000000cf, +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 0x000000d0, +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 0x000000d1, +CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 0x000000d2, +CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 0x000000d3, +CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 0x000000d4, +CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 0x000000d5, +CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 0x000000d6, +CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 0x000000d7, +CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0x000000d8, +CB_PERF_SEL_DRAWN_BUSY = 0x000000d9, +CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 0x000000da, +CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 0x000000db, +CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 0x000000dc, +CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 0x000000dd, +CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED = 0x000000de, +CB_PERF_SEL_FC_SEQUENCER_CLEAR = 0x000000df, +CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 0x000000e0, +CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 0x000000e1, +CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE = 0x000000e2, +CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL = 0x000000e3, +CB_PERF_SEL_FC_DOC_IS_STALLED = 0x000000e4, +CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED = 0x000000e5, +CB_PERF_SEL_FC_DOC_MRTS_COMBINED = 0x000000e6, +CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS = 0x000000e7, +CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT = 0x000000e8, +CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS = 0x000000e9, +CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT = 0x000000ea, +CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL = 0x000000eb, +CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR = 0x000000ec, +CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS = 0x000000ed, +CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS = 0x000000ee, +CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS = 0x000000ef, +CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS = 0x000000f0, +CB_PERF_SEL_FC_DCC_CACHE_HIT = 0x000000f1, +CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS = 0x000000f2, +CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS = 0x000000f3, +CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL = 0x000000f4, +CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x000000f5, +CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x000000f6, +CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x000000f7, +CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL = 0x000000f8, +CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL = 0x000000f9, +CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL = 0x000000fa, +CB_PERF_SEL_FC_DCC_CACHE_STALL = 0x000000fb, +CB_PERF_SEL_FC_DCC_CACHE_FLUSH = 0x000000fc, +CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED = 0x000000fd, +CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED = 0x000000fe, +CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 0x000000ff, +CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT = 0x00000100, +CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST = 0x00000101, +CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT = 0x00000102, +CB_PERF_SEL_FC_MC_DCC_READ_REQUEST = 0x00000103, +CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT = 0x00000104, +CB_PERF_SEL_CC_DCC_RDREQ_STALL = 0x00000105, +CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN = 0x00000106, +CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT = 0x00000107, +CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN = 0x00000108, +CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT = 0x00000109, +CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR = 0x0000010a, +CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1 = 0x0000010b, +CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2 = 0x0000010c, +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x0000010d, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1 = 0x0000010e, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1 = 0x0000010f, +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2 = 0x00000110, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1 = 0x00000111, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000112, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000113, +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1 = 0x00000114, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2 = 0x00000115, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2 = 0x00000116, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2 = 0x00000117, +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000118, +CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1 = 0x00000119, +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1 = 0x0000011a, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2 = 0x0000011b, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3 = 0x0000011c, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4 = 0x0000011d, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1 = 0x0000011e, +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2 = 0x0000011f, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3 = 0x00000120, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4 = 0x00000121, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1 = 0x00000122, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2 = 0x00000123, +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3 = 0x00000124, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4 = 0x00000125, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1 = 0x00000126, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2 = 0x00000127, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3 = 0x00000128, +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1 = 0x00000129, +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2 = 0x0000012a, +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3 = 0x0000012b, +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4 = 0x0000012c, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1 = 0x0000012d, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2 = 0x0000012e, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3 = 0x0000012f, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4 = 0x00000130, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1 = 0x00000131, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2 = 0x00000132, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3 = 0x00000133, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4 = 0x00000134, +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1 = 0x00000135, +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2 = 0x00000136, +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3 = 0x00000137, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1 = 0x00000138, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1 = 0x00000139, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1 = 0x0000013a, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1 = 0x0000013b, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1 = 0x0000013c, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1 = 0x0000013d, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1 = 0x0000013e, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1 = 0x0000013f, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2 = 0x00000140, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2 = 0x00000141, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2 = 0x00000142, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2 = 0x00000143, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2 = 0x00000144, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2 = 0x00000145, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2 = 0x00000146, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1 = 0x00000147, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1 = 0x00000148, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1 = 0x00000149, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1 = 0x0000014a, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2 = 0x0000014b, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2 = 0x0000014c, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2 = 0x0000014d, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2 = 0x0000014e, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x0000014f, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000150, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000151, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000152, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000153, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000154, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000155, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1 = 0x00000156, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2 = 0x00000157, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3 = 0x00000158, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4 = 0x00000159, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5 = 0x0000015a, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6 = 0x0000015b, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0 = 0x0000015c, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1 = 0x0000015d, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1 = 0x0000015e, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2 = 0x0000015f, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3 = 0x00000160, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4 = 0x00000161, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5 = 0x00000162, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0 = 0x00000163, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1 = 0x00000164, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1 = 0x00000165, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1 = 0x00000166, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1 = 0x00000167, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1 = 0x00000168, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1 = 0x00000169, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1 = 0x0000016a, +CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1 = 0x0000016b, +CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1 = 0x0000016c, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2 = 0x0000016d, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2 = 0x0000016e, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2 = 0x0000016f, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2 = 0x00000170, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2 = 0x00000171, +CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2 = 0x00000172, +CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2 = 0x00000173, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1 = 0x00000174, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2 = 0x00000175, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3 = 0x00000176, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4 = 0x00000177, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5 = 0x00000178, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6 = 0x00000179, +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7 = 0x0000017a, +CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED = 0x0000017b, +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1 = 0x0000017c, +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1 = 0x0000017d, +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2 = 0x0000017e, +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3 = 0x0000017f, +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1 = 0x00000180, +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2 = 0x00000181, +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3 = 0x00000182, +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4 = 0x00000183, +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5 = 0x00000184, +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1 = 0x00000185, +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2 = 0x00000186, +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3 = 0x00000187, +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4 = 0x00000188, +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5 = 0x00000189, +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6 = 0x0000018a, +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7 = 0x0000018b, +CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 0x0000018c, +CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 0x0000018d, +CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 0x0000018e, +CB_PERF_SEL_RBP_SPLIT_MICROTILE = 0x0000018f, +CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK = 0x00000190, +CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK = 0x00000191, +CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING = 0x00000192, +CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS = 0x00000193, +CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD = 0x00000194, +} CBPerfSel; + +/* + * CBPerfOpFilterSel enum + */ + +typedef enum CBPerfOpFilterSel { +CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x00000000, +CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x00000001, +CB_PERF_OP_FILTER_SEL_RESOLVE = 0x00000002, +CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x00000003, +CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x00000004, +CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x00000005, +} CBPerfOpFilterSel; + +/* + * CBPerfClearFilterSel enum + */ + +typedef enum CBPerfClearFilterSel { +CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x00000000, +CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x00000001, +} CBPerfClearFilterSel; + +/******************************************************* + * TC Enums + *******************************************************/ + +/* + * TC_OP_MASKS enum + */ + +typedef enum TC_OP_MASKS { +TC_OP_MASK_FLUSH_DENROM = 0x00000008, +TC_OP_MASK_64 = 0x00000020, +TC_OP_MASK_NO_RTN = 0x00000040, +} TC_OP_MASKS; + +/* + * TC_OP enum + */ + +typedef enum TC_OP { +TC_OP_READ = 0x00000000, +TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001, +TC_OP_ATOMIC_FMIN_RTN_32 = 0x00000002, +TC_OP_ATOMIC_FMAX_RTN_32 = 0x00000003, +TC_OP_RESERVED_FOP_RTN_32_0 = 0x00000004, +TC_OP_RESERVED_FOP_RTN_32_1 = 0x00000005, +TC_OP_RESERVED_FOP_RTN_32_2 = 0x00000006, +TC_OP_ATOMIC_SWAP_RTN_32 = 0x00000007, +TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008, +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009, +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a, +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b, +TC_OP_PROBE_FILTER = 0x0000000c, +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0x0000000d, +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e, +TC_OP_ATOMIC_ADD_RTN_32 = 0x0000000f, +TC_OP_ATOMIC_SUB_RTN_32 = 0x00000010, +TC_OP_ATOMIC_SMIN_RTN_32 = 0x00000011, +TC_OP_ATOMIC_UMIN_RTN_32 = 0x00000012, +TC_OP_ATOMIC_SMAX_RTN_32 = 0x00000013, +TC_OP_ATOMIC_UMAX_RTN_32 = 0x00000014, +TC_OP_ATOMIC_AND_RTN_32 = 0x00000015, +TC_OP_ATOMIC_OR_RTN_32 = 0x00000016, +TC_OP_ATOMIC_XOR_RTN_32 = 0x00000017, +TC_OP_ATOMIC_INC_RTN_32 = 0x00000018, +TC_OP_ATOMIC_DEC_RTN_32 = 0x00000019, +TC_OP_WBINVL1_VOL = 0x0000001a, +TC_OP_WBINVL1_SD = 0x0000001b, +TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x0000001c, +TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x0000001d, +TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x0000001e, +TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x0000001f, +TC_OP_WRITE = 0x00000020, +TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021, +TC_OP_ATOMIC_FMIN_RTN_64 = 0x00000022, +TC_OP_ATOMIC_FMAX_RTN_64 = 0x00000023, +TC_OP_RESERVED_FOP_RTN_64_0 = 0x00000024, +TC_OP_RESERVED_FOP_RTN_64_1 = 0x00000025, +TC_OP_RESERVED_FOP_RTN_64_2 = 0x00000026, +TC_OP_ATOMIC_SWAP_RTN_64 = 0x00000027, +TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028, +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029, +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a, +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b, +TC_OP_WBINVL2_SD = 0x0000002c, +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x0000002d, +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x0000002e, +TC_OP_ATOMIC_ADD_RTN_64 = 0x0000002f, +TC_OP_ATOMIC_SUB_RTN_64 = 0x00000030, +TC_OP_ATOMIC_SMIN_RTN_64 = 0x00000031, +TC_OP_ATOMIC_UMIN_RTN_64 = 0x00000032, +TC_OP_ATOMIC_SMAX_RTN_64 = 0x00000033, +TC_OP_ATOMIC_UMAX_RTN_64 = 0x00000034, +TC_OP_ATOMIC_AND_RTN_64 = 0x00000035, +TC_OP_ATOMIC_OR_RTN_64 = 0x00000036, +TC_OP_ATOMIC_XOR_RTN_64 = 0x00000037, +TC_OP_ATOMIC_INC_RTN_64 = 0x00000038, +TC_OP_ATOMIC_DEC_RTN_64 = 0x00000039, +TC_OP_WBL2_NC = 0x0000003a, +TC_OP_WBL2_WC = 0x0000003b, +TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x0000003c, +TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x0000003d, +TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x0000003e, +TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x0000003f, +TC_OP_WBINVL1 = 0x00000040, +TC_OP_ATOMIC_FCMPSWAP_32 = 0x00000041, +TC_OP_ATOMIC_FMIN_32 = 0x00000042, +TC_OP_ATOMIC_FMAX_32 = 0x00000043, +TC_OP_RESERVED_FOP_32_0 = 0x00000044, +TC_OP_RESERVED_FOP_32_1 = 0x00000045, +TC_OP_RESERVED_FOP_32_2 = 0x00000046, +TC_OP_ATOMIC_SWAP_32 = 0x00000047, +TC_OP_ATOMIC_CMPSWAP_32 = 0x00000048, +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049, +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a, +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b, +TC_OP_INV_METADATA = 0x0000004c, +TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 0x0000004d, +TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x0000004e, +TC_OP_ATOMIC_ADD_32 = 0x0000004f, +TC_OP_ATOMIC_SUB_32 = 0x00000050, +TC_OP_ATOMIC_SMIN_32 = 0x00000051, +TC_OP_ATOMIC_UMIN_32 = 0x00000052, +TC_OP_ATOMIC_SMAX_32 = 0x00000053, +TC_OP_ATOMIC_UMAX_32 = 0x00000054, +TC_OP_ATOMIC_AND_32 = 0x00000055, +TC_OP_ATOMIC_OR_32 = 0x00000056, +TC_OP_ATOMIC_XOR_32 = 0x00000057, +TC_OP_ATOMIC_INC_32 = 0x00000058, +TC_OP_ATOMIC_DEC_32 = 0x00000059, +TC_OP_INVL2_NC = 0x0000005a, +TC_OP_NOP_RTN0 = 0x0000005b, +TC_OP_RESERVED_NON_FLOAT_32_1 = 0x0000005c, +TC_OP_RESERVED_NON_FLOAT_32_2 = 0x0000005d, +TC_OP_RESERVED_NON_FLOAT_32_3 = 0x0000005e, +TC_OP_RESERVED_NON_FLOAT_32_4 = 0x0000005f, +TC_OP_WBINVL2 = 0x00000060, +TC_OP_ATOMIC_FCMPSWAP_64 = 0x00000061, +TC_OP_ATOMIC_FMIN_64 = 0x00000062, +TC_OP_ATOMIC_FMAX_64 = 0x00000063, +TC_OP_RESERVED_FOP_64_0 = 0x00000064, +TC_OP_RESERVED_FOP_64_1 = 0x00000065, +TC_OP_RESERVED_FOP_64_2 = 0x00000066, +TC_OP_ATOMIC_SWAP_64 = 0x00000067, +TC_OP_ATOMIC_CMPSWAP_64 = 0x00000068, +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069, +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a, +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b, +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x0000006c, +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x0000006d, +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x0000006e, +TC_OP_ATOMIC_ADD_64 = 0x0000006f, +TC_OP_ATOMIC_SUB_64 = 0x00000070, +TC_OP_ATOMIC_SMIN_64 = 0x00000071, +TC_OP_ATOMIC_UMIN_64 = 0x00000072, +TC_OP_ATOMIC_SMAX_64 = 0x00000073, +TC_OP_ATOMIC_UMAX_64 = 0x00000074, +TC_OP_ATOMIC_AND_64 = 0x00000075, +TC_OP_ATOMIC_OR_64 = 0x00000076, +TC_OP_ATOMIC_XOR_64 = 0x00000077, +TC_OP_ATOMIC_INC_64 = 0x00000078, +TC_OP_ATOMIC_DEC_64 = 0x00000079, +TC_OP_WBINVL2_NC = 0x0000007a, +TC_OP_NOP_ACK = 0x0000007b, +TC_OP_RESERVED_NON_FLOAT_64_1 = 0x0000007c, +TC_OP_RESERVED_NON_FLOAT_64_2 = 0x0000007d, +TC_OP_RESERVED_NON_FLOAT_64_3 = 0x0000007e, +TC_OP_RESERVED_NON_FLOAT_64_4 = 0x0000007f, +} TC_OP; + +/* + * TC_CHUB_REQ_CREDITS_ENUM enum + */ + +typedef enum TC_CHUB_REQ_CREDITS_ENUM { +TC_CHUB_REQ_CREDITS = 0x00000010, +} TC_CHUB_REQ_CREDITS_ENUM; + +/* + * CHUB_TC_RET_CREDITS_ENUM enum + */ + +typedef enum CHUB_TC_RET_CREDITS_ENUM { +CHUB_TC_RET_CREDITS = 0x00000020, +} CHUB_TC_RET_CREDITS_ENUM; + +/* + * TC_NACKS enum + */ + +typedef enum TC_NACKS { +TC_NACK_NO_FAULT = 0x00000000, +TC_NACK_PAGE_FAULT = 0x00000001, +TC_NACK_PROTECTION_FAULT = 0x00000002, +TC_NACK_DATA_ERROR = 0x00000003, +} TC_NACKS; + +/* + * TC_EA_CID enum + */ + +typedef enum TC_EA_CID { +TC_EA_CID_RT = 0x00000000, +TC_EA_CID_FMASK = 0x00000001, +TC_EA_CID_DCC = 0x00000002, +TC_EA_CID_TCPMETA = 0x00000003, +TC_EA_CID_Z = 0x00000004, +TC_EA_CID_STENCIL = 0x00000005, +TC_EA_CID_HTILE = 0x00000006, +TC_EA_CID_MISC = 0x00000007, +TC_EA_CID_TCP = 0x00000008, +TC_EA_CID_SQC = 0x00000009, +TC_EA_CID_CPF = 0x0000000a, +TC_EA_CID_CPG = 0x0000000b, +TC_EA_CID_IA = 0x0000000c, +TC_EA_CID_WD = 0x0000000d, +TC_EA_CID_PA = 0x0000000e, +TC_EA_CID_UTCL2_TPI = 0x0000000f, +} TC_EA_CID; + +/******************************************************* + * SPI Enums + *******************************************************/ + +/* + * SPI_SAMPLE_CNTL enum + */ + +typedef enum SPI_SAMPLE_CNTL { +CENTROIDS_ONLY = 0x00000000, +CENTERS_ONLY = 0x00000001, +CENTROIDS_AND_CENTERS = 0x00000002, +UNDEF = 0x00000003, +} SPI_SAMPLE_CNTL; + +/* + * SPI_FOG_MODE enum + */ + +typedef enum SPI_FOG_MODE { +SPI_FOG_NONE = 0x00000000, +SPI_FOG_EXP = 0x00000001, +SPI_FOG_EXP2 = 0x00000002, +SPI_FOG_LINEAR = 0x00000003, +} SPI_FOG_MODE; + +/* + * SPI_PNT_SPRITE_OVERRIDE enum + */ + +typedef enum SPI_PNT_SPRITE_OVERRIDE { +SPI_PNT_SPRITE_SEL_0 = 0x00000000, +SPI_PNT_SPRITE_SEL_1 = 0x00000001, +SPI_PNT_SPRITE_SEL_S = 0x00000002, +SPI_PNT_SPRITE_SEL_T = 0x00000003, +SPI_PNT_SPRITE_SEL_NONE = 0x00000004, +} SPI_PNT_SPRITE_OVERRIDE; + +/* + * SPI_PERFCNT_SEL enum + */ + +typedef enum SPI_PERFCNT_SEL { +SPI_PERF_VS_WINDOW_VALID = 0x00000000, +SPI_PERF_VS_BUSY = 0x00000001, +SPI_PERF_VS_FIRST_WAVE = 0x00000002, +SPI_PERF_VS_LAST_WAVE = 0x00000003, +SPI_PERF_VS_LSHS_DEALLOC = 0x00000004, +SPI_PERF_VS_PC_STALL = 0x00000005, +SPI_PERF_VS_POS0_STALL = 0x00000006, +SPI_PERF_VS_POS1_STALL = 0x00000007, +SPI_PERF_VS_CRAWLER_STALL = 0x00000008, +SPI_PERF_VS_EVENT_WAVE = 0x00000009, +SPI_PERF_VS_WAVE = 0x0000000a, +SPI_PERF_VS_PERS_UPD_FULL0 = 0x0000000b, +SPI_PERF_VS_PERS_UPD_FULL1 = 0x0000000c, +SPI_PERF_VS_LATE_ALLOC_FULL = 0x0000000d, +SPI_PERF_VS_FIRST_SUBGRP = 0x0000000e, +SPI_PERF_VS_LAST_SUBGRP = 0x0000000f, +SPI_PERF_GS_WINDOW_VALID = 0x00000010, +SPI_PERF_GS_BUSY = 0x00000011, +SPI_PERF_GS_CRAWLER_STALL = 0x00000012, +SPI_PERF_GS_EVENT_WAVE = 0x00000013, +SPI_PERF_GS_WAVE = 0x00000014, +SPI_PERF_GS_PERS_UPD_FULL0 = 0x00000015, +SPI_PERF_GS_PERS_UPD_FULL1 = 0x00000016, +SPI_PERF_GS_FIRST_SUBGRP = 0x00000017, +SPI_PERF_GS_LAST_SUBGRP = 0x00000018, +SPI_PERF_ES_WINDOW_VALID = 0x00000019, +SPI_PERF_ES_BUSY = 0x0000001a, +SPI_PERF_ES_CRAWLER_STALL = 0x0000001b, +SPI_PERF_ES_FIRST_WAVE = 0x0000001c, +SPI_PERF_ES_LAST_WAVE = 0x0000001d, +SPI_PERF_ES_LSHS_DEALLOC = 0x0000001e, +SPI_PERF_ES_EVENT_WAVE = 0x0000001f, +SPI_PERF_ES_WAVE = 0x00000020, +SPI_PERF_ES_PERS_UPD_FULL0 = 0x00000021, +SPI_PERF_ES_PERS_UPD_FULL1 = 0x00000022, +SPI_PERF_ES_FIRST_SUBGRP = 0x00000023, +SPI_PERF_ES_LAST_SUBGRP = 0x00000024, +SPI_PERF_HS_WINDOW_VALID = 0x00000025, +SPI_PERF_HS_BUSY = 0x00000026, +SPI_PERF_HS_CRAWLER_STALL = 0x00000027, +SPI_PERF_HS_FIRST_WAVE = 0x00000028, +SPI_PERF_HS_LAST_WAVE = 0x00000029, +SPI_PERF_HS_LSHS_DEALLOC = 0x0000002a, +SPI_PERF_HS_EVENT_WAVE = 0x0000002b, +SPI_PERF_HS_WAVE = 0x0000002c, +SPI_PERF_HS_PERS_UPD_FULL0 = 0x0000002d, +SPI_PERF_HS_PERS_UPD_FULL1 = 0x0000002e, +SPI_PERF_LS_WINDOW_VALID = 0x0000002f, +SPI_PERF_LS_BUSY = 0x00000030, +SPI_PERF_LS_CRAWLER_STALL = 0x00000031, +SPI_PERF_LS_FIRST_WAVE = 0x00000032, +SPI_PERF_LS_LAST_WAVE = 0x00000033, +SPI_PERF_OFFCHIP_LDS_STALL_LS = 0x00000034, +SPI_PERF_LS_EVENT_WAVE = 0x00000035, +SPI_PERF_LS_WAVE = 0x00000036, +SPI_PERF_LS_PERS_UPD_FULL0 = 0x00000037, +SPI_PERF_LS_PERS_UPD_FULL1 = 0x00000038, +SPI_PERF_CSG_WINDOW_VALID = 0x00000039, +SPI_PERF_CSG_BUSY = 0x0000003a, +SPI_PERF_CSG_NUM_THREADGROUPS = 0x0000003b, +SPI_PERF_CSG_CRAWLER_STALL = 0x0000003c, +SPI_PERF_CSG_EVENT_WAVE = 0x0000003d, +SPI_PERF_CSG_WAVE = 0x0000003e, +SPI_PERF_CSN_WINDOW_VALID = 0x0000003f, +SPI_PERF_CSN_BUSY = 0x00000040, +SPI_PERF_CSN_NUM_THREADGROUPS = 0x00000041, +SPI_PERF_CSN_CRAWLER_STALL = 0x00000042, +SPI_PERF_CSN_EVENT_WAVE = 0x00000043, +SPI_PERF_CSN_WAVE = 0x00000044, +SPI_PERF_PS_CTL_WINDOW_VALID = 0x00000045, +SPI_PERF_PS_CTL_BUSY = 0x00000046, +SPI_PERF_PS_CTL_ACTIVE = 0x00000047, +SPI_PERF_PS_CTL_DEALLOC_BIN0 = 0x00000048, +SPI_PERF_PS_CTL_FPOS_BIN1_STALL = 0x00000049, +SPI_PERF_PS_CTL_EVENT_WAVE = 0x0000004a, +SPI_PERF_PS_CTL_WAVE = 0x0000004b, +SPI_PERF_PS_CTL_OPT_WAVE = 0x0000004c, +SPI_PERF_PS_CTL_PASS_BIN0 = 0x0000004d, +SPI_PERF_PS_CTL_PASS_BIN1 = 0x0000004e, +SPI_PERF_PS_CTL_FPOS_BIN2 = 0x0000004f, +SPI_PERF_PS_CTL_PRIM_BIN0 = 0x00000050, +SPI_PERF_PS_CTL_PRIM_BIN1 = 0x00000051, +SPI_PERF_PS_CTL_CNF_BIN2 = 0x00000052, +SPI_PERF_PS_CTL_CNF_BIN3 = 0x00000053, +SPI_PERF_PS_CTL_CRAWLER_STALL = 0x00000054, +SPI_PERF_PS_CTL_LDS_RES_FULL = 0x00000055, +SPI_PERF_PS_PERS_UPD_FULL0 = 0x00000056, +SPI_PERF_PS_PERS_UPD_FULL1 = 0x00000057, +SPI_PERF_PIX_ALLOC_PEND_CNT = 0x00000058, +SPI_PERF_PIX_ALLOC_SCB_STALL = 0x00000059, +SPI_PERF_PIX_ALLOC_DB0_STALL = 0x0000005a, +SPI_PERF_PIX_ALLOC_DB1_STALL = 0x0000005b, +SPI_PERF_PIX_ALLOC_DB2_STALL = 0x0000005c, +SPI_PERF_PIX_ALLOC_DB3_STALL = 0x0000005d, +SPI_PERF_LDS0_PC_VALID = 0x0000005e, +SPI_PERF_LDS1_PC_VALID = 0x0000005f, +SPI_PERF_RA_PIPE_REQ_BIN2 = 0x00000060, +SPI_PERF_RA_TASK_REQ_BIN3 = 0x00000061, +SPI_PERF_RA_WR_CTL_FULL = 0x00000062, +SPI_PERF_RA_REQ_NO_ALLOC = 0x00000063, +SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x00000064, +SPI_PERF_RA_REQ_NO_ALLOC_VS = 0x00000065, +SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x00000066, +SPI_PERF_RA_REQ_NO_ALLOC_ES = 0x00000067, +SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x00000068, +SPI_PERF_RA_REQ_NO_ALLOC_LS = 0x00000069, +SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x0000006a, +SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x0000006b, +SPI_PERF_RA_RES_STALL_PS = 0x0000006c, +SPI_PERF_RA_RES_STALL_VS = 0x0000006d, +SPI_PERF_RA_RES_STALL_GS = 0x0000006e, +SPI_PERF_RA_RES_STALL_ES = 0x0000006f, +SPI_PERF_RA_RES_STALL_HS = 0x00000070, +SPI_PERF_RA_RES_STALL_LS = 0x00000071, +SPI_PERF_RA_RES_STALL_CSG = 0x00000072, +SPI_PERF_RA_RES_STALL_CSN = 0x00000073, +SPI_PERF_RA_TMP_STALL_PS = 0x00000074, +SPI_PERF_RA_TMP_STALL_VS = 0x00000075, +SPI_PERF_RA_TMP_STALL_GS = 0x00000076, +SPI_PERF_RA_TMP_STALL_ES = 0x00000077, +SPI_PERF_RA_TMP_STALL_HS = 0x00000078, +SPI_PERF_RA_TMP_STALL_LS = 0x00000079, +SPI_PERF_RA_TMP_STALL_CSG = 0x0000007a, +SPI_PERF_RA_TMP_STALL_CSN = 0x0000007b, +SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x0000007c, +SPI_PERF_RA_WAVE_SIMD_FULL_VS = 0x0000007d, +SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x0000007e, +SPI_PERF_RA_WAVE_SIMD_FULL_ES = 0x0000007f, +SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x00000080, +SPI_PERF_RA_WAVE_SIMD_FULL_LS = 0x00000081, +SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x00000082, +SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x00000083, +SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x00000084, +SPI_PERF_RA_VGPR_SIMD_FULL_VS = 0x00000085, +SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x00000086, +SPI_PERF_RA_VGPR_SIMD_FULL_ES = 0x00000087, +SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x00000088, +SPI_PERF_RA_VGPR_SIMD_FULL_LS = 0x00000089, +SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x0000008a, +SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x0000008b, +SPI_PERF_RA_SGPR_SIMD_FULL_PS = 0x0000008c, +SPI_PERF_RA_SGPR_SIMD_FULL_VS = 0x0000008d, +SPI_PERF_RA_SGPR_SIMD_FULL_GS = 0x0000008e, +SPI_PERF_RA_SGPR_SIMD_FULL_ES = 0x0000008f, +SPI_PERF_RA_SGPR_SIMD_FULL_HS = 0x00000090, +SPI_PERF_RA_SGPR_SIMD_FULL_LS = 0x00000091, +SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 0x00000092, +SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 0x00000093, +SPI_PERF_RA_LDS_CU_FULL_PS = 0x00000094, +SPI_PERF_RA_LDS_CU_FULL_LS = 0x00000095, +SPI_PERF_RA_LDS_CU_FULL_ES = 0x00000096, +SPI_PERF_RA_LDS_CU_FULL_CSG = 0x00000097, +SPI_PERF_RA_LDS_CU_FULL_CSN = 0x00000098, +SPI_PERF_RA_BAR_CU_FULL_HS = 0x00000099, +SPI_PERF_RA_BAR_CU_FULL_CSG = 0x0000009a, +SPI_PERF_RA_BAR_CU_FULL_CSN = 0x0000009b, +SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x0000009c, +SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x0000009d, +SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x0000009e, +SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x0000009f, +SPI_PERF_RA_WVLIM_STALL_PS = 0x000000a0, +SPI_PERF_RA_WVLIM_STALL_VS = 0x000000a1, +SPI_PERF_RA_WVLIM_STALL_GS = 0x000000a2, +SPI_PERF_RA_WVLIM_STALL_ES = 0x000000a3, +SPI_PERF_RA_WVLIM_STALL_HS = 0x000000a4, +SPI_PERF_RA_WVLIM_STALL_LS = 0x000000a5, +SPI_PERF_RA_WVLIM_STALL_CSG = 0x000000a6, +SPI_PERF_RA_WVLIM_STALL_CSN = 0x000000a7, +SPI_PERF_RA_PS_LOCK_NA = 0x000000a8, +SPI_PERF_RA_VS_LOCK = 0x000000a9, +SPI_PERF_RA_GS_LOCK = 0x000000aa, +SPI_PERF_RA_ES_LOCK = 0x000000ab, +SPI_PERF_RA_HS_LOCK = 0x000000ac, +SPI_PERF_RA_LS_LOCK = 0x000000ad, +SPI_PERF_RA_CSG_LOCK = 0x000000ae, +SPI_PERF_RA_CSN_LOCK = 0x000000af, +SPI_PERF_RA_RSV_UPD = 0x000000b0, +SPI_PERF_EXP_ARB_COL_CNT = 0x000000b1, +SPI_PERF_EXP_ARB_PAR_CNT = 0x000000b2, +SPI_PERF_EXP_ARB_POS_CNT = 0x000000b3, +SPI_PERF_EXP_ARB_GDS_CNT = 0x000000b4, +SPI_PERF_CLKGATE_BUSY_STALL = 0x000000b5, +SPI_PERF_CLKGATE_ACTIVE_STALL = 0x000000b6, +SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 0x000000b7, +SPI_PERF_CLKGATE_CGTT_DYN_ON = 0x000000b8, +SPI_PERF_CLKGATE_CGTT_REG_ON = 0x000000b9, +SPI_PERF_NUM_VS_POS_EXPORTS = 0x000000ba, +SPI_PERF_NUM_VS_PARAM_EXPORTS = 0x000000bb, +SPI_PERF_NUM_PS_COL_EXPORTS = 0x000000bc, +SPI_PERF_ES_GRP_FIFO_FULL = 0x000000bd, +SPI_PERF_GS_GRP_FIFO_FULL = 0x000000be, +SPI_PERF_HS_GRP_FIFO_FULL = 0x000000bf, +SPI_PERF_LS_GRP_FIFO_FULL = 0x000000c0, +SPI_PERF_VS_ALLOC_CNT = 0x000000c1, +SPI_PERF_VS_LATE_ALLOC_ACCUM = 0x000000c2, +SPI_PERF_PC_ALLOC_CNT = 0x000000c3, +SPI_PERF_PC_ALLOC_ACCUM = 0x000000c4, +} SPI_PERFCNT_SEL; + +/* + * SPI_SHADER_FORMAT enum + */ + +typedef enum SPI_SHADER_FORMAT { +SPI_SHADER_NONE = 0x00000000, +SPI_SHADER_1COMP = 0x00000001, +SPI_SHADER_2COMP = 0x00000002, +SPI_SHADER_4COMPRESS = 0x00000003, +SPI_SHADER_4COMP = 0x00000004, +} SPI_SHADER_FORMAT; + +/* + * SPI_SHADER_EX_FORMAT enum + */ + +typedef enum SPI_SHADER_EX_FORMAT { +SPI_SHADER_ZERO = 0x00000000, +SPI_SHADER_32_R = 0x00000001, +SPI_SHADER_32_GR = 0x00000002, +SPI_SHADER_32_AR = 0x00000003, +SPI_SHADER_FP16_ABGR = 0x00000004, +SPI_SHADER_UNORM16_ABGR = 0x00000005, +SPI_SHADER_SNORM16_ABGR = 0x00000006, +SPI_SHADER_UINT16_ABGR = 0x00000007, +SPI_SHADER_SINT16_ABGR = 0x00000008, +SPI_SHADER_32_ABGR = 0x00000009, +} SPI_SHADER_EX_FORMAT; + +/* + * CLKGATE_SM_MODE enum + */ + +typedef enum CLKGATE_SM_MODE { +ON_SEQ = 0x00000000, +OFF_SEQ = 0x00000001, +PROG_SEQ = 0x00000002, +READ_SEQ = 0x00000003, +SM_MODE_RESERVED = 0x00000004, +} CLKGATE_SM_MODE; + +/* + * CLKGATE_BASE_MODE enum + */ + +typedef enum CLKGATE_BASE_MODE { +MULT_8 = 0x00000000, +MULT_16 = 0x00000001, +} CLKGATE_BASE_MODE; + +/******************************************************* + * SQ Enums + *******************************************************/ + +/* + * SQ_TEX_CLAMP enum + */ + +typedef enum SQ_TEX_CLAMP { +SQ_TEX_WRAP = 0x00000000, +SQ_TEX_MIRROR = 0x00000001, +SQ_TEX_CLAMP_LAST_TEXEL = 0x00000002, +SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x00000003, +SQ_TEX_CLAMP_HALF_BORDER = 0x00000004, +SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x00000005, +SQ_TEX_CLAMP_BORDER = 0x00000006, +SQ_TEX_MIRROR_ONCE_BORDER = 0x00000007, +} SQ_TEX_CLAMP; + +/* + * SQ_TEX_XY_FILTER enum + */ + +typedef enum SQ_TEX_XY_FILTER { +SQ_TEX_XY_FILTER_POINT = 0x00000000, +SQ_TEX_XY_FILTER_BILINEAR = 0x00000001, +SQ_TEX_XY_FILTER_ANISO_POINT = 0x00000002, +SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x00000003, +} SQ_TEX_XY_FILTER; + +/* + * SQ_TEX_Z_FILTER enum + */ + +typedef enum SQ_TEX_Z_FILTER { +SQ_TEX_Z_FILTER_NONE = 0x00000000, +SQ_TEX_Z_FILTER_POINT = 0x00000001, +SQ_TEX_Z_FILTER_LINEAR = 0x00000002, +} SQ_TEX_Z_FILTER; + +/* + * SQ_TEX_MIP_FILTER enum + */ + +typedef enum SQ_TEX_MIP_FILTER { +SQ_TEX_MIP_FILTER_NONE = 0x00000000, +SQ_TEX_MIP_FILTER_POINT = 0x00000001, +SQ_TEX_MIP_FILTER_LINEAR = 0x00000002, +SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 0x00000003, +} SQ_TEX_MIP_FILTER; + +/* + * SQ_TEX_ANISO_RATIO enum + */ + +typedef enum SQ_TEX_ANISO_RATIO { +SQ_TEX_ANISO_RATIO_1 = 0x00000000, +SQ_TEX_ANISO_RATIO_2 = 0x00000001, +SQ_TEX_ANISO_RATIO_4 = 0x00000002, +SQ_TEX_ANISO_RATIO_8 = 0x00000003, +SQ_TEX_ANISO_RATIO_16 = 0x00000004, +} SQ_TEX_ANISO_RATIO; + +/* + * SQ_TEX_DEPTH_COMPARE enum + */ + +typedef enum SQ_TEX_DEPTH_COMPARE { +SQ_TEX_DEPTH_COMPARE_NEVER = 0x00000000, +SQ_TEX_DEPTH_COMPARE_LESS = 0x00000001, +SQ_TEX_DEPTH_COMPARE_EQUAL = 0x00000002, +SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x00000003, +SQ_TEX_DEPTH_COMPARE_GREATER = 0x00000004, +SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x00000005, +SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x00000006, +SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x00000007, +} SQ_TEX_DEPTH_COMPARE; + +/* + * SQ_TEX_BORDER_COLOR enum + */ + +typedef enum SQ_TEX_BORDER_COLOR { +SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00000000, +SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x00000001, +SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x00000002, +SQ_TEX_BORDER_COLOR_REGISTER = 0x00000003, +} SQ_TEX_BORDER_COLOR; + +/* + * SQ_RSRC_BUF_TYPE enum + */ + +typedef enum SQ_RSRC_BUF_TYPE { +SQ_RSRC_BUF = 0x00000000, +SQ_RSRC_BUF_RSVD_1 = 0x00000001, +SQ_RSRC_BUF_RSVD_2 = 0x00000002, +SQ_RSRC_BUF_RSVD_3 = 0x00000003, +} SQ_RSRC_BUF_TYPE; + +/* + * SQ_RSRC_IMG_TYPE enum + */ + +typedef enum SQ_RSRC_IMG_TYPE { +SQ_RSRC_IMG_RSVD_0 = 0x00000000, +SQ_RSRC_IMG_RSVD_1 = 0x00000001, +SQ_RSRC_IMG_RSVD_2 = 0x00000002, +SQ_RSRC_IMG_RSVD_3 = 0x00000003, +SQ_RSRC_IMG_RSVD_4 = 0x00000004, +SQ_RSRC_IMG_RSVD_5 = 0x00000005, +SQ_RSRC_IMG_RSVD_6 = 0x00000006, +SQ_RSRC_IMG_RSVD_7 = 0x00000007, +SQ_RSRC_IMG_1D = 0x00000008, +SQ_RSRC_IMG_2D = 0x00000009, +SQ_RSRC_IMG_3D = 0x0000000a, +SQ_RSRC_IMG_CUBE = 0x0000000b, +SQ_RSRC_IMG_1D_ARRAY = 0x0000000c, +SQ_RSRC_IMG_2D_ARRAY = 0x0000000d, +SQ_RSRC_IMG_2D_MSAA = 0x0000000e, +SQ_RSRC_IMG_2D_MSAA_ARRAY = 0x0000000f, +} SQ_RSRC_IMG_TYPE; + +/* + * SQ_RSRC_FLAT_TYPE enum + */ + +typedef enum SQ_RSRC_FLAT_TYPE { +SQ_RSRC_FLAT_RSVD_0 = 0x00000000, +SQ_RSRC_FLAT = 0x00000001, +SQ_RSRC_FLAT_RSVD_2 = 0x00000002, +SQ_RSRC_FLAT_RSVD_3 = 0x00000003, +} SQ_RSRC_FLAT_TYPE; + +/* + * SQ_IMG_FILTER_TYPE enum + */ + +typedef enum SQ_IMG_FILTER_TYPE { +SQ_IMG_FILTER_MODE_BLEND = 0x00000000, +SQ_IMG_FILTER_MODE_MIN = 0x00000001, +SQ_IMG_FILTER_MODE_MAX = 0x00000002, +} SQ_IMG_FILTER_TYPE; + +/* + * SQ_SEL_XYZW01 enum + */ + +typedef enum SQ_SEL_XYZW01 { +SQ_SEL_0 = 0x00000000, +SQ_SEL_1 = 0x00000001, +SQ_SEL_RESERVED_0 = 0x00000002, +SQ_SEL_RESERVED_1 = 0x00000003, +SQ_SEL_X = 0x00000004, +SQ_SEL_Y = 0x00000005, +SQ_SEL_Z = 0x00000006, +SQ_SEL_W = 0x00000007, +} SQ_SEL_XYZW01; + +/* + * SQ_WAVE_TYPE enum + */ + +typedef enum SQ_WAVE_TYPE { +SQ_WAVE_TYPE_PS = 0x00000000, +SQ_WAVE_TYPE_VS = 0x00000001, +SQ_WAVE_TYPE_GS = 0x00000002, +SQ_WAVE_TYPE_ES = 0x00000003, +SQ_WAVE_TYPE_HS = 0x00000004, +SQ_WAVE_TYPE_LS = 0x00000005, +SQ_WAVE_TYPE_CS = 0x00000006, +SQ_WAVE_TYPE_PS1 = 0x00000007, +} SQ_WAVE_TYPE; + +/* + * SQ_THREAD_TRACE_TOKEN_TYPE enum + */ + +typedef enum SQ_THREAD_TRACE_TOKEN_TYPE { +SQ_THREAD_TRACE_TOKEN_MISC = 0x00000000, +SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 0x00000001, +SQ_THREAD_TRACE_TOKEN_REG = 0x00000002, +SQ_THREAD_TRACE_TOKEN_WAVE_START = 0x00000003, +SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC = 0x00000004, +SQ_THREAD_TRACE_TOKEN_REG_CSPRIV = 0x00000005, +SQ_THREAD_TRACE_TOKEN_WAVE_END = 0x00000006, +SQ_THREAD_TRACE_TOKEN_EVENT = 0x00000007, +SQ_THREAD_TRACE_TOKEN_EVENT_CS = 0x00000008, +SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 0x00000009, +SQ_THREAD_TRACE_TOKEN_INST = 0x0000000a, +SQ_THREAD_TRACE_TOKEN_INST_PC = 0x0000000b, +SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 0x0000000c, +SQ_THREAD_TRACE_TOKEN_ISSUE = 0x0000000d, +SQ_THREAD_TRACE_TOKEN_PERF = 0x0000000e, +SQ_THREAD_TRACE_TOKEN_REG_CS = 0x0000000f, +} SQ_THREAD_TRACE_TOKEN_TYPE; + +/* + * SQ_THREAD_TRACE_MISC_TOKEN_TYPE enum + */ + +typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE { +SQ_THREAD_TRACE_MISC_TOKEN_TIME = 0x00000000, +SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET = 0x00000001, +SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 0x00000002, +SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC = 0x00000003, +SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN = 0x00000004, +SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END = 0x00000005, +SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX = 0x00000006, +SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN = 0x00000007, +} SQ_THREAD_TRACE_MISC_TOKEN_TYPE; + +/* + * SQ_THREAD_TRACE_INST_TYPE enum + */ + +typedef enum SQ_THREAD_TRACE_INST_TYPE { +SQ_THREAD_TRACE_INST_TYPE_SMEM_RD = 0x00000000, +SQ_THREAD_TRACE_INST_TYPE_SALU_32 = 0x00000001, +SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 0x00000002, +SQ_THREAD_TRACE_INST_TYPE_VMEM_WR = 0x00000003, +SQ_THREAD_TRACE_INST_TYPE_FLAT_WR = 0x00000004, +SQ_THREAD_TRACE_INST_TYPE_VALU_32 = 0x00000005, +SQ_THREAD_TRACE_INST_TYPE_LDS = 0x00000006, +SQ_THREAD_TRACE_INST_TYPE_PC = 0x00000007, +SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 0x00000008, +SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 0x00000009, +SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 0x0000000a, +SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 0x0000000b, +SQ_THREAD_TRACE_INST_TYPE_JUMP = 0x0000000c, +SQ_THREAD_TRACE_INST_TYPE_NEXT = 0x0000000d, +SQ_THREAD_TRACE_INST_TYPE_FLAT_RD = 0x0000000e, +SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 0x0000000f, +SQ_THREAD_TRACE_INST_TYPE_SMEM_WR = 0x00000010, +SQ_THREAD_TRACE_INST_TYPE_SALU_64 = 0x00000011, +SQ_THREAD_TRACE_INST_TYPE_VALU_64 = 0x00000012, +SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY = 0x00000013, +SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY = 0x00000014, +SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY = 0x00000015, +SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY = 0x00000016, +SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY = 0x00000017, +SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY = 0x00000018, +SQ_THREAD_TRACE_INST_TYPE_FATAL_HALT = 0x00000019, +} SQ_THREAD_TRACE_INST_TYPE; + +/* + * SQ_THREAD_TRACE_REG_TYPE enum + */ + +typedef enum SQ_THREAD_TRACE_REG_TYPE { +SQ_THREAD_TRACE_REG_TYPE_EVENT = 0x00000000, +SQ_THREAD_TRACE_REG_TYPE_DRAW = 0x00000001, +SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 0x00000002, +SQ_THREAD_TRACE_REG_TYPE_USERDATA = 0x00000003, +SQ_THREAD_TRACE_REG_TYPE_MARKER = 0x00000004, +SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 0x00000005, +SQ_THREAD_TRACE_REG_TYPE_SHDEC = 0x00000006, +SQ_THREAD_TRACE_REG_TYPE_OTHER = 0x00000007, +} SQ_THREAD_TRACE_REG_TYPE; + +/* + * SQ_THREAD_TRACE_REG_OP enum + */ + +typedef enum SQ_THREAD_TRACE_REG_OP { +SQ_THREAD_TRACE_REG_OP_READ = 0x00000000, +SQ_THREAD_TRACE_REG_OP_WRITE = 0x00000001, +} SQ_THREAD_TRACE_REG_OP; + +/* + * SQ_THREAD_TRACE_MODE_SEL enum + */ + +typedef enum SQ_THREAD_TRACE_MODE_SEL { +SQ_THREAD_TRACE_MODE_OFF = 0x00000000, +SQ_THREAD_TRACE_MODE_ON = 0x00000001, +} SQ_THREAD_TRACE_MODE_SEL; + +/* + * SQ_THREAD_TRACE_CAPTURE_MODE enum + */ + +typedef enum SQ_THREAD_TRACE_CAPTURE_MODE { +SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0x00000000, +SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 0x00000001, +SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x00000002, +} SQ_THREAD_TRACE_CAPTURE_MODE; + +/* + * SQ_THREAD_TRACE_VM_ID_MASK enum + */ + +typedef enum SQ_THREAD_TRACE_VM_ID_MASK { +SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0x00000000, +SQ_THREAD_TRACE_VM_ID_MASK_ALL = 0x00000001, +SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x00000002, +} SQ_THREAD_TRACE_VM_ID_MASK; + +/* + * SQ_THREAD_TRACE_WAVE_MASK enum + */ + +typedef enum SQ_THREAD_TRACE_WAVE_MASK { +SQ_THREAD_TRACE_WAVE_MASK_NONE = 0x00000000, +SQ_THREAD_TRACE_WAVE_MASK_ALL = 0x00000001, +} SQ_THREAD_TRACE_WAVE_MASK; + +/* + * SQ_THREAD_TRACE_ISSUE enum + */ + +typedef enum SQ_THREAD_TRACE_ISSUE { +SQ_THREAD_TRACE_ISSUE_NULL = 0x00000000, +SQ_THREAD_TRACE_ISSUE_STALL = 0x00000001, +SQ_THREAD_TRACE_ISSUE_INST = 0x00000002, +SQ_THREAD_TRACE_ISSUE_IMMED = 0x00000003, +} SQ_THREAD_TRACE_ISSUE; + +/* + * SQ_THREAD_TRACE_ISSUE_MASK enum + */ + +typedef enum SQ_THREAD_TRACE_ISSUE_MASK { +SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0x00000000, +SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 0x00000001, +SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x00000002, +SQ_THREAD_TRACE_ISSUE_MASK_IMMED = 0x00000003, +} SQ_THREAD_TRACE_ISSUE_MASK; + +/* + * SQ_PERF_SEL enum + */ + +typedef enum SQ_PERF_SEL { +SQ_PERF_SEL_NONE = 0x00000000, +SQ_PERF_SEL_ACCUM_PREV = 0x00000001, +SQ_PERF_SEL_CYCLES = 0x00000002, +SQ_PERF_SEL_BUSY_CYCLES = 0x00000003, +SQ_PERF_SEL_WAVES = 0x00000004, +SQ_PERF_SEL_LEVEL_WAVES = 0x00000005, +SQ_PERF_SEL_WAVES_EQ_64 = 0x00000006, +SQ_PERF_SEL_WAVES_LT_64 = 0x00000007, +SQ_PERF_SEL_WAVES_LT_48 = 0x00000008, +SQ_PERF_SEL_WAVES_LT_32 = 0x00000009, +SQ_PERF_SEL_WAVES_LT_16 = 0x0000000a, +SQ_PERF_SEL_WAVES_CU = 0x0000000b, +SQ_PERF_SEL_LEVEL_WAVES_CU = 0x0000000c, +SQ_PERF_SEL_BUSY_CU_CYCLES = 0x0000000d, +SQ_PERF_SEL_ITEMS = 0x0000000e, +SQ_PERF_SEL_QUADS = 0x0000000f, +SQ_PERF_SEL_EVENTS = 0x00000010, +SQ_PERF_SEL_SURF_SYNCS = 0x00000011, +SQ_PERF_SEL_TTRACE_REQS = 0x00000012, +SQ_PERF_SEL_TTRACE_INFLIGHT_REQS = 0x00000013, +SQ_PERF_SEL_TTRACE_STALL = 0x00000014, +SQ_PERF_SEL_MSG_CNTR = 0x00000015, +SQ_PERF_SEL_MSG_PERF = 0x00000016, +SQ_PERF_SEL_MSG_GSCNT = 0x00000017, +SQ_PERF_SEL_MSG_INTERRUPT = 0x00000018, +SQ_PERF_SEL_INSTS = 0x00000019, +SQ_PERF_SEL_INSTS_VALU = 0x0000001a, +SQ_PERF_SEL_INSTS_VMEM_WR = 0x0000001b, +SQ_PERF_SEL_INSTS_VMEM_RD = 0x0000001c, +SQ_PERF_SEL_INSTS_VMEM = 0x0000001d, +SQ_PERF_SEL_INSTS_SALU = 0x0000001e, +SQ_PERF_SEL_INSTS_SMEM = 0x0000001f, +SQ_PERF_SEL_INSTS_FLAT = 0x00000020, +SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY = 0x00000021, +SQ_PERF_SEL_INSTS_LDS = 0x00000022, +SQ_PERF_SEL_INSTS_GDS = 0x00000023, +SQ_PERF_SEL_INSTS_EXP = 0x00000024, +SQ_PERF_SEL_INSTS_EXP_GDS = 0x00000025, +SQ_PERF_SEL_INSTS_BRANCH = 0x00000026, +SQ_PERF_SEL_INSTS_SENDMSG = 0x00000027, +SQ_PERF_SEL_INSTS_VSKIPPED = 0x00000028, +SQ_PERF_SEL_INST_LEVEL_VMEM = 0x00000029, +SQ_PERF_SEL_INST_LEVEL_SMEM = 0x0000002a, +SQ_PERF_SEL_INST_LEVEL_LDS = 0x0000002b, +SQ_PERF_SEL_INST_LEVEL_GDS = 0x0000002c, +SQ_PERF_SEL_INST_LEVEL_EXP = 0x0000002d, +SQ_PERF_SEL_WAVE_CYCLES = 0x0000002e, +SQ_PERF_SEL_WAVE_READY = 0x0000002f, +SQ_PERF_SEL_WAIT_CNT_VM = 0x00000030, +SQ_PERF_SEL_WAIT_CNT_LGKM = 0x00000031, +SQ_PERF_SEL_WAIT_CNT_EXP = 0x00000032, +SQ_PERF_SEL_WAIT_CNT_ANY = 0x00000033, +SQ_PERF_SEL_WAIT_BARRIER = 0x00000034, +SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x00000035, +SQ_PERF_SEL_WAIT_SLEEP = 0x00000036, +SQ_PERF_SEL_WAIT_SLEEP_XNACK = 0x00000037, +SQ_PERF_SEL_WAIT_OTHER = 0x00000038, +SQ_PERF_SEL_WAIT_ANY = 0x00000039, +SQ_PERF_SEL_WAIT_TTRACE = 0x0000003a, +SQ_PERF_SEL_WAIT_IFETCH = 0x0000003b, +SQ_PERF_SEL_WAIT_INST_ANY = 0x0000003c, +SQ_PERF_SEL_WAIT_INST_VMEM = 0x0000003d, +SQ_PERF_SEL_WAIT_INST_SCA = 0x0000003e, +SQ_PERF_SEL_WAIT_INST_LDS = 0x0000003f, +SQ_PERF_SEL_WAIT_INST_VALU = 0x00000040, +SQ_PERF_SEL_WAIT_INST_EXP_GDS = 0x00000041, +SQ_PERF_SEL_WAIT_INST_MISC = 0x00000042, +SQ_PERF_SEL_WAIT_INST_FLAT = 0x00000043, +SQ_PERF_SEL_ACTIVE_INST_ANY = 0x00000044, +SQ_PERF_SEL_ACTIVE_INST_VMEM = 0x00000045, +SQ_PERF_SEL_ACTIVE_INST_LDS = 0x00000046, +SQ_PERF_SEL_ACTIVE_INST_VALU = 0x00000047, +SQ_PERF_SEL_ACTIVE_INST_SCA = 0x00000048, +SQ_PERF_SEL_ACTIVE_INST_EXP_GDS = 0x00000049, +SQ_PERF_SEL_ACTIVE_INST_MISC = 0x0000004a, +SQ_PERF_SEL_ACTIVE_INST_FLAT = 0x0000004b, +SQ_PERF_SEL_INST_CYCLES_VMEM_WR = 0x0000004c, +SQ_PERF_SEL_INST_CYCLES_VMEM_RD = 0x0000004d, +SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR = 0x0000004e, +SQ_PERF_SEL_INST_CYCLES_VMEM_DATA = 0x0000004f, +SQ_PERF_SEL_INST_CYCLES_VMEM_CMD = 0x00000050, +SQ_PERF_SEL_INST_CYCLES_EXP = 0x00000051, +SQ_PERF_SEL_INST_CYCLES_GDS = 0x00000052, +SQ_PERF_SEL_INST_CYCLES_SMEM = 0x00000053, +SQ_PERF_SEL_INST_CYCLES_SALU = 0x00000054, +SQ_PERF_SEL_THREAD_CYCLES_VALU = 0x00000055, +SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX = 0x00000056, +SQ_PERF_SEL_IFETCH = 0x00000057, +SQ_PERF_SEL_IFETCH_LEVEL = 0x00000058, +SQ_PERF_SEL_CBRANCH_FORK = 0x00000059, +SQ_PERF_SEL_CBRANCH_FORK_SPLIT = 0x0000005a, +SQ_PERF_SEL_VALU_LDS_DIRECT_RD = 0x0000005b, +SQ_PERF_SEL_VALU_LDS_INTERP_OP = 0x0000005c, +SQ_PERF_SEL_LDS_BANK_CONFLICT = 0x0000005d, +SQ_PERF_SEL_LDS_ADDR_CONFLICT = 0x0000005e, +SQ_PERF_SEL_LDS_UNALIGNED_STALL = 0x0000005f, +SQ_PERF_SEL_LDS_MEM_VIOLATIONS = 0x00000060, +SQ_PERF_SEL_LDS_ATOMIC_RETURN = 0x00000061, +SQ_PERF_SEL_LDS_IDX_ACTIVE = 0x00000062, +SQ_PERF_SEL_VALU_DEP_STALL = 0x00000063, +SQ_PERF_SEL_VALU_STARVE = 0x00000064, +SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x00000065, +SQ_PERF_SEL_LDS_DATA_FIFO_FULL = 0x00000066, +SQ_PERF_SEL_LDS_CMD_FIFO_FULL = 0x00000067, +SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL = 0x00000068, +SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL = 0x00000069, +SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY = 0x0000006a, +SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL = 0x0000006b, +SQ_PERF_SEL_VALU_SRC_C_CONFLICT = 0x0000006c, +SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT = 0x0000006d, +SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT = 0x0000006e, +SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT = 0x0000006f, +SQ_PERF_SEL_LDS_SRC_CD_CONFLICT = 0x00000070, +SQ_PERF_SEL_SRC_CD_BUSY = 0x00000071, +SQ_PERF_SEL_PT_POWER_STALL = 0x00000072, +SQ_PERF_SEL_USER0 = 0x00000073, +SQ_PERF_SEL_USER1 = 0x00000074, +SQ_PERF_SEL_USER2 = 0x00000075, +SQ_PERF_SEL_USER3 = 0x00000076, +SQ_PERF_SEL_USER4 = 0x00000077, +SQ_PERF_SEL_USER5 = 0x00000078, +SQ_PERF_SEL_USER6 = 0x00000079, +SQ_PERF_SEL_USER7 = 0x0000007a, +SQ_PERF_SEL_USER8 = 0x0000007b, +SQ_PERF_SEL_USER9 = 0x0000007c, +SQ_PERF_SEL_USER10 = 0x0000007d, +SQ_PERF_SEL_USER11 = 0x0000007e, +SQ_PERF_SEL_USER12 = 0x0000007f, +SQ_PERF_SEL_USER13 = 0x00000080, +SQ_PERF_SEL_USER14 = 0x00000081, +SQ_PERF_SEL_USER15 = 0x00000082, +SQ_PERF_SEL_USER_LEVEL0 = 0x00000083, +SQ_PERF_SEL_USER_LEVEL1 = 0x00000084, +SQ_PERF_SEL_USER_LEVEL2 = 0x00000085, +SQ_PERF_SEL_USER_LEVEL3 = 0x00000086, +SQ_PERF_SEL_USER_LEVEL4 = 0x00000087, +SQ_PERF_SEL_USER_LEVEL5 = 0x00000088, +SQ_PERF_SEL_USER_LEVEL6 = 0x00000089, +SQ_PERF_SEL_USER_LEVEL7 = 0x0000008a, +SQ_PERF_SEL_USER_LEVEL8 = 0x0000008b, +SQ_PERF_SEL_USER_LEVEL9 = 0x0000008c, +SQ_PERF_SEL_USER_LEVEL10 = 0x0000008d, +SQ_PERF_SEL_USER_LEVEL11 = 0x0000008e, +SQ_PERF_SEL_USER_LEVEL12 = 0x0000008f, +SQ_PERF_SEL_USER_LEVEL13 = 0x00000090, +SQ_PERF_SEL_USER_LEVEL14 = 0x00000091, +SQ_PERF_SEL_USER_LEVEL15 = 0x00000092, +SQ_PERF_SEL_POWER_VALU = 0x00000093, +SQ_PERF_SEL_POWER_VALU0 = 0x00000094, +SQ_PERF_SEL_POWER_VALU1 = 0x00000095, +SQ_PERF_SEL_POWER_VALU2 = 0x00000096, +SQ_PERF_SEL_POWER_GPR_RD = 0x00000097, +SQ_PERF_SEL_POWER_GPR_WR = 0x00000098, +SQ_PERF_SEL_POWER_LDS_BUSY = 0x00000099, +SQ_PERF_SEL_POWER_ALU_BUSY = 0x0000009a, +SQ_PERF_SEL_POWER_TEX_BUSY = 0x0000009b, +SQ_PERF_SEL_ACCUM_PREV_HIRES = 0x0000009c, +SQ_PERF_SEL_WAVES_RESTORED = 0x0000009d, +SQ_PERF_SEL_WAVES_SAVED = 0x0000009e, +SQ_PERF_SEL_INSTS_SMEM_NORM = 0x0000009f, +SQ_PERF_SEL_ATC_INSTS_VMEM = 0x000000a0, +SQ_PERF_SEL_ATC_INST_LEVEL_VMEM = 0x000000a1, +SQ_PERF_SEL_ATC_XNACK_FIRST = 0x000000a2, +SQ_PERF_SEL_ATC_XNACK_ALL = 0x000000a3, +SQ_PERF_SEL_ATC_XNACK_FIFO_FULL = 0x000000a4, +SQ_PERF_SEL_ATC_INSTS_SMEM = 0x000000a5, +SQ_PERF_SEL_ATC_INST_LEVEL_SMEM = 0x000000a6, +SQ_PERF_SEL_IFETCH_XNACK = 0x000000a7, +SQ_PERF_SEL_TLB_SHOOTDOWN = 0x000000a8, +SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES = 0x000000a9, +SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY = 0x000000aa, +SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY = 0x000000ab, +SQ_PERF_SEL_INSTS_VMEM_REPLAY = 0x000000ac, +SQ_PERF_SEL_INSTS_SMEM_REPLAY = 0x000000ad, +SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY = 0x000000ae, +SQ_PERF_SEL_INSTS_FLAT_REPLAY = 0x000000af, +SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY = 0x000000b0, +SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY = 0x000000b1, +SQ_PERF_SEL_UTCL1_TRANSLATION_MISS = 0x000000b2, +SQ_PERF_SEL_UTCL1_PERMISSION_MISS = 0x000000b3, +SQ_PERF_SEL_UTCL1_REQUEST = 0x000000b4, +SQ_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 0x000000b5, +SQ_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 0x000000b6, +SQ_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 0x000000b7, +SQ_PERF_SEL_UTCL1_LFIFO_FULL = 0x000000b8, +SQ_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 0x000000b9, +SQ_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x000000ba, +SQ_PERF_SEL_DUMMY_END = 0x000000bb, +SQ_PERF_SEL_DUMMY_LAST = 0x000000ff, +SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 0x00000100, +SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0x00000101, +SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 0x00000102, +SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 0x00000103, +SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0x00000104, +SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 0x00000105, +SQC_PERF_SEL_TC_REQ = 0x00000106, +SQC_PERF_SEL_TC_INST_REQ = 0x00000107, +SQC_PERF_SEL_TC_DATA_READ_REQ = 0x00000108, +SQC_PERF_SEL_TC_DATA_WRITE_REQ = 0x00000109, +SQC_PERF_SEL_TC_DATA_ATOMIC_REQ = 0x0000010a, +SQC_PERF_SEL_TC_STALL = 0x0000010b, +SQC_PERF_SEL_TC_STARVE = 0x0000010c, +SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0x0000010d, +SQC_PERF_SEL_ICACHE_REQ = 0x0000010e, +SQC_PERF_SEL_ICACHE_HITS = 0x0000010f, +SQC_PERF_SEL_ICACHE_MISSES = 0x00000110, +SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0x00000111, +SQC_PERF_SEL_ICACHE_INVAL_INST = 0x00000112, +SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0x00000113, +SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0x00000114, +SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0x00000115, +SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0x00000116, +SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0x00000117, +SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000118, +SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 0x00000119, +SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0x0000011a, +SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0x0000011b, +SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 0x0000011c, +SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x0000011d, +SQC_PERF_SEL_ICACHE_PREFETCH_1 = 0x0000011e, +SQC_PERF_SEL_ICACHE_PREFETCH_2 = 0x0000011f, +SQC_PERF_SEL_ICACHE_PREFETCH_FILTERED = 0x00000120, +SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0x00000121, +SQC_PERF_SEL_DCACHE_REQ = 0x00000122, +SQC_PERF_SEL_DCACHE_HITS = 0x00000123, +SQC_PERF_SEL_DCACHE_MISSES = 0x00000124, +SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0x00000125, +SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 0x00000126, +SQC_PERF_SEL_DCACHE_MISS_EVICT_READ = 0x00000127, +SQC_PERF_SEL_DCACHE_WC_LRU_WRITE = 0x00000128, +SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE = 0x00000129, +SQC_PERF_SEL_DCACHE_ATOMIC = 0x0000012a, +SQC_PERF_SEL_DCACHE_VOLATILE = 0x0000012b, +SQC_PERF_SEL_DCACHE_INVAL_INST = 0x0000012c, +SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0x0000012d, +SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST = 0x0000012e, +SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC = 0x0000012f, +SQC_PERF_SEL_DCACHE_WB_INST = 0x00000130, +SQC_PERF_SEL_DCACHE_WB_ASYNC = 0x00000131, +SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST = 0x00000132, +SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC = 0x00000133, +SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0x00000134, +SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0x00000135, +SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0x00000136, +SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000137, +SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0x00000138, +SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT = 0x00000139, +SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED = 0x0000013a, +SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE = 0x0000013b, +SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT = 0x0000013c, +SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH = 0x0000013d, +SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE = 0x0000013e, +SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0x0000013f, +SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0x00000140, +SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 0x00000141, +SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x00000142, +SQC_PERF_SEL_DCACHE_REQ_READ_1 = 0x00000143, +SQC_PERF_SEL_DCACHE_REQ_READ_2 = 0x00000144, +SQC_PERF_SEL_DCACHE_REQ_READ_4 = 0x00000145, +SQC_PERF_SEL_DCACHE_REQ_READ_8 = 0x00000146, +SQC_PERF_SEL_DCACHE_REQ_READ_16 = 0x00000147, +SQC_PERF_SEL_DCACHE_REQ_TIME = 0x00000148, +SQC_PERF_SEL_DCACHE_REQ_WRITE_1 = 0x00000149, +SQC_PERF_SEL_DCACHE_REQ_WRITE_2 = 0x0000014a, +SQC_PERF_SEL_DCACHE_REQ_WRITE_4 = 0x0000014b, +SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 0x0000014c, +SQC_PERF_SEL_SQ_DCACHE_REQS = 0x0000014d, +SQC_PERF_SEL_DCACHE_FLAT_REQ = 0x0000014e, +SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 0x0000014f, +SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0x00000150, +SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0x00000151, +SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0x00000152, +SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0x00000153, +SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0x00000154, +SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS = 0x00000155, +SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS = 0x00000156, +SQC_PERF_SEL_ICACHE_GATCL1_REQUEST = 0x00000157, +SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX = 0x00000158, +SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT = 0x00000159, +SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL = 0x0000015a, +SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x0000015b, +SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS = 0x0000015c, +SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT = 0x0000015d, +SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL = 0x0000015e, +SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS = 0x0000015f, +SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS = 0x00000160, +SQC_PERF_SEL_DCACHE_GATCL1_REQUEST = 0x00000161, +SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX = 0x00000162, +SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT = 0x00000163, +SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL = 0x00000164, +SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x00000165, +SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS = 0x00000166, +SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT = 0x00000167, +SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL = 0x00000168, +SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS = 0x00000169, +SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL = 0x0000016a, +SQC_PERF_SEL_DUMMY_LAST = 0x0000016b, +} SQ_PERF_SEL; + +/* + * SQ_CAC_POWER_SEL enum + */ + +typedef enum SQ_CAC_POWER_SEL { +SQ_CAC_POWER_VALU = 0x00000000, +SQ_CAC_POWER_VALU0 = 0x00000001, +SQ_CAC_POWER_VALU1 = 0x00000002, +SQ_CAC_POWER_VALU2 = 0x00000003, +SQ_CAC_POWER_GPR_RD = 0x00000004, +SQ_CAC_POWER_GPR_WR = 0x00000005, +SQ_CAC_POWER_LDS_BUSY = 0x00000006, +SQ_CAC_POWER_ALU_BUSY = 0x00000007, +SQ_CAC_POWER_TEX_BUSY = 0x00000008, +} SQ_CAC_POWER_SEL; + +/* + * SQ_IND_CMD_CMD enum + */ + +typedef enum SQ_IND_CMD_CMD { +SQ_IND_CMD_CMD_NULL = 0x00000000, +SQ_IND_CMD_CMD_SETHALT = 0x00000001, +SQ_IND_CMD_CMD_SAVECTX = 0x00000002, +SQ_IND_CMD_CMD_KILL = 0x00000003, +SQ_IND_CMD_CMD_DEBUG = 0x00000004, +SQ_IND_CMD_CMD_TRAP = 0x00000005, +SQ_IND_CMD_CMD_SET_SPI_PRIO = 0x00000006, +SQ_IND_CMD_CMD_SETFATALHALT = 0x00000007, +} SQ_IND_CMD_CMD; + +/* + * SQ_IND_CMD_MODE enum + */ + +typedef enum SQ_IND_CMD_MODE { +SQ_IND_CMD_MODE_SINGLE = 0x00000000, +SQ_IND_CMD_MODE_BROADCAST = 0x00000001, +SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002, +SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003, +SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004, +} SQ_IND_CMD_MODE; + +/* + * SQ_EDC_INFO_SOURCE enum + */ + +typedef enum SQ_EDC_INFO_SOURCE { +SQ_EDC_INFO_SOURCE_INVALID = 0x00000000, +SQ_EDC_INFO_SOURCE_INST = 0x00000001, +SQ_EDC_INFO_SOURCE_SGPR = 0x00000002, +SQ_EDC_INFO_SOURCE_VGPR = 0x00000003, +SQ_EDC_INFO_SOURCE_LDS = 0x00000004, +SQ_EDC_INFO_SOURCE_GDS = 0x00000005, +SQ_EDC_INFO_SOURCE_TA = 0x00000006, +} SQ_EDC_INFO_SOURCE; + +/* + * SQ_ROUND_MODE enum + */ + +typedef enum SQ_ROUND_MODE { +SQ_ROUND_NEAREST_EVEN = 0x00000000, +SQ_ROUND_PLUS_INFINITY = 0x00000001, +SQ_ROUND_MINUS_INFINITY = 0x00000002, +SQ_ROUND_TO_ZERO = 0x00000003, +} SQ_ROUND_MODE; + +/* + * SQ_INTERRUPT_WORD_ENCODING enum + */ + +typedef enum SQ_INTERRUPT_WORD_ENCODING { +SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x00000000, +SQ_INTERRUPT_WORD_ENCODING_INST = 0x00000001, +SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x00000002, +} SQ_INTERRUPT_WORD_ENCODING; + +/* + * ENUM_SQ_EXPORT_RAT_INST enum + */ + +typedef enum ENUM_SQ_EXPORT_RAT_INST { +SQ_EXPORT_RAT_INST_NOP = 0x00000000, +SQ_EXPORT_RAT_INST_STORE_TYPED = 0x00000001, +SQ_EXPORT_RAT_INST_STORE_RAW = 0x00000002, +SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 0x00000003, +SQ_EXPORT_RAT_INST_CMPXCHG_INT = 0x00000004, +SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 0x00000005, +SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 0x00000006, +SQ_EXPORT_RAT_INST_ADD = 0x00000007, +SQ_EXPORT_RAT_INST_SUB = 0x00000008, +SQ_EXPORT_RAT_INST_RSUB = 0x00000009, +SQ_EXPORT_RAT_INST_MIN_INT = 0x0000000a, +SQ_EXPORT_RAT_INST_MIN_UINT = 0x0000000b, +SQ_EXPORT_RAT_INST_MAX_INT = 0x0000000c, +SQ_EXPORT_RAT_INST_MAX_UINT = 0x0000000d, +SQ_EXPORT_RAT_INST_AND = 0x0000000e, +SQ_EXPORT_RAT_INST_OR = 0x0000000f, +SQ_EXPORT_RAT_INST_XOR = 0x00000010, +SQ_EXPORT_RAT_INST_MSKOR = 0x00000011, +SQ_EXPORT_RAT_INST_INC_UINT = 0x00000012, +SQ_EXPORT_RAT_INST_DEC_UINT = 0x00000013, +SQ_EXPORT_RAT_INST_STORE_DWORD = 0x00000014, +SQ_EXPORT_RAT_INST_STORE_SHORT = 0x00000015, +SQ_EXPORT_RAT_INST_STORE_BYTE = 0x00000016, +SQ_EXPORT_RAT_INST_NOP_RTN = 0x00000020, +SQ_EXPORT_RAT_INST_XCHG_RTN = 0x00000022, +SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 0x00000023, +SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 0x00000024, +SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 0x00000025, +SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 0x00000026, +SQ_EXPORT_RAT_INST_ADD_RTN = 0x00000027, +SQ_EXPORT_RAT_INST_SUB_RTN = 0x00000028, +SQ_EXPORT_RAT_INST_RSUB_RTN = 0x00000029, +SQ_EXPORT_RAT_INST_MIN_INT_RTN = 0x0000002a, +SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 0x0000002b, +SQ_EXPORT_RAT_INST_MAX_INT_RTN = 0x0000002c, +SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 0x0000002d, +SQ_EXPORT_RAT_INST_AND_RTN = 0x0000002e, +SQ_EXPORT_RAT_INST_OR_RTN = 0x0000002f, +SQ_EXPORT_RAT_INST_XOR_RTN = 0x00000030, +SQ_EXPORT_RAT_INST_MSKOR_RTN = 0x00000031, +SQ_EXPORT_RAT_INST_INC_UINT_RTN = 0x00000032, +SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 0x00000033, +} ENUM_SQ_EXPORT_RAT_INST; + +/* + * SQ_IBUF_ST enum + */ + +typedef enum SQ_IBUF_ST { +SQ_IBUF_IB_IDLE = 0x00000000, +SQ_IBUF_IB_INI_WAIT_GNT = 0x00000001, +SQ_IBUF_IB_INI_WAIT_DRET = 0x00000002, +SQ_IBUF_IB_LE_4DW = 0x00000003, +SQ_IBUF_IB_WAIT_DRET = 0x00000004, +SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x00000005, +SQ_IBUF_IB_DRET = 0x00000006, +SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x00000007, +} SQ_IBUF_ST; + +/* + * SQ_INST_STR_ST enum + */ + +typedef enum SQ_INST_STR_ST { +SQ_INST_STR_IB_WAVE_NORML = 0x00000000, +SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x00000001, +SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x00000002, +SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x00000003, +SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 0x00000004, +SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 0x00000005, +SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x00000006, +SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x00000007, +} SQ_INST_STR_ST; + +/* + * SQ_WAVE_IB_ECC_ST enum + */ + +typedef enum SQ_WAVE_IB_ECC_ST { +SQ_WAVE_IB_ECC_CLEAN = 0x00000000, +SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x00000001, +SQ_WAVE_IB_ECC_ERR_HALT = 0x00000002, +SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x00000003, +} SQ_WAVE_IB_ECC_ST; + +/* + * SH_MEM_ADDRESS_MODE enum + */ + +typedef enum SH_MEM_ADDRESS_MODE { +SH_MEM_ADDRESS_MODE_64 = 0x00000000, +SH_MEM_ADDRESS_MODE_32 = 0x00000001, +} SH_MEM_ADDRESS_MODE; + +/* + * SH_MEM_ALIGNMENT_MODE enum + */ + +typedef enum SH_MEM_ALIGNMENT_MODE { +SH_MEM_ALIGNMENT_MODE_DWORD = 0x00000000, +SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x00000001, +SH_MEM_ALIGNMENT_MODE_STRICT = 0x00000002, +SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x00000003, +} SH_MEM_ALIGNMENT_MODE; + +/* + * SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX enum + */ + +typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX { +SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC = 0x00000018, +SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE = 0x00000019, +} SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX; + +/* + * SQ_LB_CTR_SEL_VALUES enum + */ + +typedef enum SQ_LB_CTR_SEL_VALUES { +SQ_LB_CTR_SEL_ALU_CYCLES = 0x00000000, +SQ_LB_CTR_SEL_ALU_STALLS = 0x00000001, +SQ_LB_CTR_SEL_TEX_CYCLES = 0x00000002, +SQ_LB_CTR_SEL_TEX_STALLS = 0x00000003, +SQ_LB_CTR_SEL_SALU_CYCLES = 0x00000004, +SQ_LB_CTR_SEL_SCALAR_STALLS = 0x00000005, +SQ_LB_CTR_SEL_SMEM_CYCLES = 0x00000006, +SQ_LB_CTR_SEL_ICACHE_STALLS = 0x00000007, +SQ_LB_CTR_SEL_DCACHE_STALLS = 0x00000008, +SQ_LB_CTR_SEL_RESERVED0 = 0x00000009, +SQ_LB_CTR_SEL_RESERVED1 = 0x0000000a, +SQ_LB_CTR_SEL_RESERVED2 = 0x0000000b, +SQ_LB_CTR_SEL_RESERVED3 = 0x0000000c, +SQ_LB_CTR_SEL_RESERVED4 = 0x0000000d, +SQ_LB_CTR_SEL_RESERVED5 = 0x0000000e, +SQ_LB_CTR_SEL_RESERVED6 = 0x0000000f, +} SQ_LB_CTR_SEL_VALUES; + +/* + * SQ_WAVE_TYPE value + */ + +#define SQ_WAVE_TYPE_PS0 0x00000000 + +/* + * SQIND_PARTITIONS value + */ + +#define SQIND_GLOBAL_REGS_OFFSET 0x00000000 +#define SQIND_GLOBAL_REGS_SIZE 0x00000008 +#define SQIND_LOCAL_REGS_OFFSET 0x00000008 +#define SQIND_LOCAL_REGS_SIZE 0x00000008 +#define SQIND_WAVE_HWREGS_OFFSET 0x00000010 +#define SQIND_WAVE_HWREGS_SIZE 0x000001f0 +#define SQIND_WAVE_SGPRS_OFFSET 0x00000200 +#define SQIND_WAVE_SGPRS_SIZE 0x00000200 +#define SQIND_WAVE_VGPRS_OFFSET 0x00000400 +#define SQIND_WAVE_VGPRS_SIZE 0x00000100 + +/* + * SQ_GFXDEC value + */ + +#define SQ_GFXDEC_BEGIN 0x0000a000 +#define SQ_GFXDEC_END 0x0000c000 +#define SQ_GFXDEC_STATE_ID_SHIFT 0x0000000a + +/* + * SQDEC value + */ + +#define SQDEC_BEGIN 0x00002300 +#define SQDEC_END 0x000023ff + +/* + * SQPERFSDEC value + */ + +#define SQPERFSDEC_BEGIN 0x0000d9c0 +#define SQPERFSDEC_END 0x0000da40 + +/* + * SQPERFDDEC value + */ + +#define SQPERFDDEC_BEGIN 0x0000d1c0 +#define SQPERFDDEC_END 0x0000d240 + +/* + * SQGFXUDEC value + */ + +#define SQGFXUDEC_BEGIN 0x0000c330 +#define SQGFXUDEC_END 0x0000c380 + +/* + * SQPWRDEC value + */ + +#define SQPWRDEC_BEGIN 0x0000f08c +#define SQPWRDEC_END 0x0000f094 + +/* + * SQ_DISPATCHER value + */ + +#define SQ_DISPATCHER_GFX_MIN 0x00000010 +#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x00000008 + +/* + * SQ_MAX value + */ + +#define SQ_MAX_PGM_SGPRS 0x00000068 +#define SQ_MAX_PGM_VGPRS 0x00000100 + +/* + * SQ_THREAD_TRACE_TIME_UNIT value + */ + +#define SQ_THREAD_TRACE_TIME_UNIT 0x00000004 + +/* + * SQ_EXCP_BITS value + */ + +#define SQ_EX_MODE_EXCP_VALU_BASE 0x00000000 +#define SQ_EX_MODE_EXCP_VALU_SIZE 0x00000007 +#define SQ_EX_MODE_EXCP_INVALID 0x00000000 +#define SQ_EX_MODE_EXCP_INPUT_DENORM 0x00000001 +#define SQ_EX_MODE_EXCP_DIV0 0x00000002 +#define SQ_EX_MODE_EXCP_OVERFLOW 0x00000003 +#define SQ_EX_MODE_EXCP_UNDERFLOW 0x00000004 +#define SQ_EX_MODE_EXCP_INEXACT 0x00000005 +#define SQ_EX_MODE_EXCP_INT_DIV0 0x00000006 +#define SQ_EX_MODE_EXCP_ADDR_WATCH0 0x00000007 +#define SQ_EX_MODE_EXCP_MEM_VIOL 0x00000008 + +/* + * SQ_EXCP_HI_BITS value + */ + +#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 0x00000000 +#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 0x00000001 +#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 0x00000002 + +/* + * HW_INSERTED_INST_ID value + */ + +#define INST_ID_PRIV_START 0x80000000 +#define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0 +#define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1 +#define INST_ID_HW_TRAP 0xfffffff2 +#define INST_ID_KILL_SEQ 0xfffffff3 +#define INST_ID_SPI_WREXEC 0xfffffff4 +#define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe + +/* + * SIMM16_WAITCNT_PARTITIONS value + */ + +#define SIMM16_WAITCNT_VM_CNT_START 0x00000000 +#define SIMM16_WAITCNT_VM_CNT_SIZE 0x00000004 +#define SIMM16_WAITCNT_EXP_CNT_START 0x00000004 +#define SIMM16_WAITCNT_EXP_CNT_SIZE 0x00000003 +#define SIMM16_WAITCNT_LGKM_CNT_START 0x00000008 +#define SIMM16_WAITCNT_LGKM_CNT_SIZE 0x00000004 +#define SIMM16_WAITCNT_VM_CNT_HI_START 0x0000000e +#define SIMM16_WAITCNT_VM_CNT_HI_SIZE 0x00000002 + +/* + * SQ_EDC_FUE_CNTL_BITS value + */ + +#define SQ_EDC_FUE_CNTL_SQ 0x00000000 +#define SQ_EDC_FUE_CNTL_LDS 0x00000001 +#define SQ_EDC_FUE_CNTL_SIMD0 0x00000002 +#define SQ_EDC_FUE_CNTL_SIMD1 0x00000003 +#define SQ_EDC_FUE_CNTL_SIMD2 0x00000004 +#define SQ_EDC_FUE_CNTL_SIMD3 0x00000005 +#define SQ_EDC_FUE_CNTL_TA 0x00000006 +#define SQ_EDC_FUE_CNTL_TD 0x00000007 +#define SQ_EDC_FUE_CNTL_TCP 0x00000008 + +/******************************************************* + * COMP Enums + *******************************************************/ + +/* + * CSDATA_TYPE enum + */ + +typedef enum CSDATA_TYPE { +CSDATA_TYPE_TG = 0x00000000, +CSDATA_TYPE_STATE = 0x00000001, +CSDATA_TYPE_EVENT = 0x00000002, +CSDATA_TYPE_PRIVATE = 0x00000003, +} CSDATA_TYPE; + +/* + * CSDATA_TYPE_WIDTH value + */ + +#define CSDATA_TYPE_WIDTH 0x00000002 + +/* + * CSDATA_ADDR_WIDTH value + */ + +#define CSDATA_ADDR_WIDTH 0x00000007 + +/* + * CSDATA_DATA_WIDTH value + */ + +#define CSDATA_DATA_WIDTH 0x00000020 + +/******************************************************* + * VGT Enums + *******************************************************/ + +/* + * VGT_OUT_PRIM_TYPE enum + */ + +typedef enum VGT_OUT_PRIM_TYPE { +VGT_OUT_POINT = 0x00000000, +VGT_OUT_LINE = 0x00000001, +VGT_OUT_TRI = 0x00000002, +VGT_OUT_RECT_V0 = 0x00000003, +VGT_OUT_RECT_V1 = 0x00000004, +VGT_OUT_RECT_V2 = 0x00000005, +VGT_OUT_RECT_V3 = 0x00000006, +VGT_OUT_2D_RECT = 0x00000007, +VGT_TE_QUAD = 0x00000008, +VGT_TE_PRIM_INDEX_LINE = 0x00000009, +VGT_TE_PRIM_INDEX_TRI = 0x0000000a, +VGT_TE_PRIM_INDEX_QUAD = 0x0000000b, +VGT_OUT_LINE_ADJ = 0x0000000c, +VGT_OUT_TRI_ADJ = 0x0000000d, +VGT_OUT_PATCH = 0x0000000e, +} VGT_OUT_PRIM_TYPE; + +/* + * VGT_DI_PRIM_TYPE enum + */ + +typedef enum VGT_DI_PRIM_TYPE { +DI_PT_NONE = 0x00000000, +DI_PT_POINTLIST = 0x00000001, +DI_PT_LINELIST = 0x00000002, +DI_PT_LINESTRIP = 0x00000003, +DI_PT_TRILIST = 0x00000004, +DI_PT_TRIFAN = 0x00000005, +DI_PT_TRISTRIP = 0x00000006, +DI_PT_2D_RECTANGLE = 0x00000007, +DI_PT_UNUSED_1 = 0x00000008, +DI_PT_PATCH = 0x00000009, +DI_PT_LINELIST_ADJ = 0x0000000a, +DI_PT_LINESTRIP_ADJ = 0x0000000b, +DI_PT_TRILIST_ADJ = 0x0000000c, +DI_PT_TRISTRIP_ADJ = 0x0000000d, +DI_PT_UNUSED_3 = 0x0000000e, +DI_PT_UNUSED_4 = 0x0000000f, +DI_PT_TRI_WITH_WFLAGS = 0x00000010, +DI_PT_RECTLIST = 0x00000011, +DI_PT_LINELOOP = 0x00000012, +DI_PT_QUADLIST = 0x00000013, +DI_PT_QUADSTRIP = 0x00000014, +DI_PT_POLYGON = 0x00000015, +} VGT_DI_PRIM_TYPE; + +/* + * VGT_DI_SOURCE_SELECT enum + */ + +typedef enum VGT_DI_SOURCE_SELECT { +DI_SRC_SEL_DMA = 0x00000000, +DI_SRC_SEL_IMMEDIATE = 0x00000001, +DI_SRC_SEL_AUTO_INDEX = 0x00000002, +DI_SRC_SEL_RESERVED = 0x00000003, +} VGT_DI_SOURCE_SELECT; + +/* + * VGT_DI_MAJOR_MODE_SELECT enum + */ + +typedef enum VGT_DI_MAJOR_MODE_SELECT { +DI_MAJOR_MODE_0 = 0x00000000, +DI_MAJOR_MODE_1 = 0x00000001, +} VGT_DI_MAJOR_MODE_SELECT; + +/* + * VGT_DI_INDEX_SIZE enum + */ + +typedef enum VGT_DI_INDEX_SIZE { +DI_INDEX_SIZE_16_BIT = 0x00000000, +DI_INDEX_SIZE_32_BIT = 0x00000001, +DI_INDEX_SIZE_8_BIT = 0x00000002, +} VGT_DI_INDEX_SIZE; + +/* + * VGT_EVENT_TYPE enum + */ + +typedef enum VGT_EVENT_TYPE { +Reserved_0x00 = 0x00000000, +SAMPLE_STREAMOUTSTATS1 = 0x00000001, +SAMPLE_STREAMOUTSTATS2 = 0x00000002, +SAMPLE_STREAMOUTSTATS3 = 0x00000003, +CACHE_FLUSH_TS = 0x00000004, +CONTEXT_DONE = 0x00000005, +CACHE_FLUSH = 0x00000006, +CS_PARTIAL_FLUSH = 0x00000007, +VGT_STREAMOUT_SYNC = 0x00000008, +Reserved_0x09 = 0x00000009, +VGT_STREAMOUT_RESET = 0x0000000a, +END_OF_PIPE_INCR_DE = 0x0000000b, +END_OF_PIPE_IB_END = 0x0000000c, +RST_PIX_CNT = 0x0000000d, +BREAK_BATCH = 0x0000000e, +VS_PARTIAL_FLUSH = 0x0000000f, +PS_PARTIAL_FLUSH = 0x00000010, +FLUSH_HS_OUTPUT = 0x00000011, +FLUSH_DFSM = 0x00000012, +RESET_TO_LOWEST_VGT = 0x00000013, +CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014, +ZPASS_DONE = 0x00000015, +CACHE_FLUSH_AND_INV_EVENT = 0x00000016, +PERFCOUNTER_START = 0x00000017, +PERFCOUNTER_STOP = 0x00000018, +PIPELINESTAT_START = 0x00000019, +PIPELINESTAT_STOP = 0x0000001a, +PERFCOUNTER_SAMPLE = 0x0000001b, +Available_0x1c = 0x0000001c, +Available_0x1d = 0x0000001d, +SAMPLE_PIPELINESTAT = 0x0000001e, +SO_VGTSTREAMOUT_FLUSH = 0x0000001f, +SAMPLE_STREAMOUTSTATS = 0x00000020, +RESET_VTX_CNT = 0x00000021, +BLOCK_CONTEXT_DONE = 0x00000022, +CS_CONTEXT_DONE = 0x00000023, +VGT_FLUSH = 0x00000024, +TGID_ROLLOVER = 0x00000025, +SQ_NON_EVENT = 0x00000026, +SC_SEND_DB_VPZ = 0x00000027, +BOTTOM_OF_PIPE_TS = 0x00000028, +FLUSH_SX_TS = 0x00000029, +DB_CACHE_FLUSH_AND_INV = 0x0000002a, +FLUSH_AND_INV_DB_DATA_TS = 0x0000002b, +FLUSH_AND_INV_DB_META = 0x0000002c, +FLUSH_AND_INV_CB_DATA_TS = 0x0000002d, +FLUSH_AND_INV_CB_META = 0x0000002e, +CS_DONE = 0x0000002f, +PS_DONE = 0x00000030, +FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000031, +SX_CB_RAT_ACK_REQUEST = 0x00000032, +THREAD_TRACE_START = 0x00000033, +THREAD_TRACE_STOP = 0x00000034, +THREAD_TRACE_MARKER = 0x00000035, +THREAD_TRACE_FLUSH = 0x00000036, +THREAD_TRACE_FINISH = 0x00000037, +PIXEL_PIPE_STAT_CONTROL = 0x00000038, +PIXEL_PIPE_STAT_DUMP = 0x00000039, +PIXEL_PIPE_STAT_RESET = 0x0000003a, +CONTEXT_SUSPEND = 0x0000003b, +OFFCHIP_HS_DEALLOC = 0x0000003c, +ENABLE_NGG_PIPELINE = 0x0000003d, +ENABLE_LEGACY_PIPELINE = 0x0000003e, +Reserved_0x3f = 0x0000003f, +} VGT_EVENT_TYPE; + +/* + * VGT_DMA_SWAP_MODE enum + */ + +typedef enum VGT_DMA_SWAP_MODE { +VGT_DMA_SWAP_NONE = 0x00000000, +VGT_DMA_SWAP_16_BIT = 0x00000001, +VGT_DMA_SWAP_32_BIT = 0x00000002, +VGT_DMA_SWAP_WORD = 0x00000003, +} VGT_DMA_SWAP_MODE; + +/* + * VGT_INDEX_TYPE_MODE enum + */ + +typedef enum VGT_INDEX_TYPE_MODE { +VGT_INDEX_16 = 0x00000000, +VGT_INDEX_32 = 0x00000001, +VGT_INDEX_8 = 0x00000002, +} VGT_INDEX_TYPE_MODE; + +/* + * VGT_DMA_BUF_TYPE enum + */ + +typedef enum VGT_DMA_BUF_TYPE { +VGT_DMA_BUF_MEM = 0x00000000, +VGT_DMA_BUF_RING = 0x00000001, +VGT_DMA_BUF_SETUP = 0x00000002, +VGT_DMA_PTR_UPDATE = 0x00000003, +} VGT_DMA_BUF_TYPE; + +/* + * VGT_OUTPATH_SELECT enum + */ + +typedef enum VGT_OUTPATH_SELECT { +VGT_OUTPATH_VTX_REUSE = 0x00000000, +VGT_OUTPATH_TESS_EN = 0x00000001, +VGT_OUTPATH_PASSTHRU = 0x00000002, +VGT_OUTPATH_GS_BLOCK = 0x00000003, +VGT_OUTPATH_HS_BLOCK = 0x00000004, +VGT_OUTPATH_PRIM_GEN = 0x00000005, +} VGT_OUTPATH_SELECT; + +/* + * VGT_GRP_PRIM_TYPE enum + */ + +typedef enum VGT_GRP_PRIM_TYPE { +VGT_GRP_3D_POINT = 0x00000000, +VGT_GRP_3D_LINE = 0x00000001, +VGT_GRP_3D_TRI = 0x00000002, +VGT_GRP_3D_RECT = 0x00000003, +VGT_GRP_3D_QUAD = 0x00000004, +VGT_GRP_2D_COPY_RECT_V0 = 0x00000005, +VGT_GRP_2D_COPY_RECT_V1 = 0x00000006, +VGT_GRP_2D_COPY_RECT_V2 = 0x00000007, +VGT_GRP_2D_COPY_RECT_V3 = 0x00000008, +VGT_GRP_2D_FILL_RECT = 0x00000009, +VGT_GRP_2D_LINE = 0x0000000a, +VGT_GRP_2D_TRI = 0x0000000b, +VGT_GRP_PRIM_INDEX_LINE = 0x0000000c, +VGT_GRP_PRIM_INDEX_TRI = 0x0000000d, +VGT_GRP_PRIM_INDEX_QUAD = 0x0000000e, +VGT_GRP_3D_LINE_ADJ = 0x0000000f, +VGT_GRP_3D_TRI_ADJ = 0x00000010, +VGT_GRP_3D_PATCH = 0x00000011, +VGT_GRP_2D_RECT = 0x00000012, +} VGT_GRP_PRIM_TYPE; + +/* + * VGT_GRP_PRIM_ORDER enum + */ + +typedef enum VGT_GRP_PRIM_ORDER { +VGT_GRP_LIST = 0x00000000, +VGT_GRP_STRIP = 0x00000001, +VGT_GRP_FAN = 0x00000002, +VGT_GRP_LOOP = 0x00000003, +VGT_GRP_POLYGON = 0x00000004, +} VGT_GRP_PRIM_ORDER; + +/* + * VGT_GROUP_CONV_SEL enum + */ + +typedef enum VGT_GROUP_CONV_SEL { +VGT_GRP_INDEX_16 = 0x00000000, +VGT_GRP_INDEX_32 = 0x00000001, +VGT_GRP_UINT_16 = 0x00000002, +VGT_GRP_UINT_32 = 0x00000003, +VGT_GRP_SINT_16 = 0x00000004, +VGT_GRP_SINT_32 = 0x00000005, +VGT_GRP_FLOAT_32 = 0x00000006, +VGT_GRP_AUTO_PRIM = 0x00000007, +VGT_GRP_FIX_1_23_TO_FLOAT = 0x00000008, +} VGT_GROUP_CONV_SEL; + +/* + * VGT_GS_MODE_TYPE enum + */ + +typedef enum VGT_GS_MODE_TYPE { +GS_OFF = 0x00000000, +GS_SCENARIO_A = 0x00000001, +GS_SCENARIO_B = 0x00000002, +GS_SCENARIO_G = 0x00000003, +GS_SCENARIO_C = 0x00000004, +SPRITE_EN = 0x00000005, +} VGT_GS_MODE_TYPE; + +/* + * VGT_GS_CUT_MODE enum + */ + +typedef enum VGT_GS_CUT_MODE { +GS_CUT_1024 = 0x00000000, +GS_CUT_512 = 0x00000001, +GS_CUT_256 = 0x00000002, +GS_CUT_128 = 0x00000003, +} VGT_GS_CUT_MODE; + +/* + * VGT_GS_OUTPRIM_TYPE enum + */ + +typedef enum VGT_GS_OUTPRIM_TYPE { +POINTLIST = 0x00000000, +LINESTRIP = 0x00000001, +TRISTRIP = 0x00000002, +RECTLIST = 0x00000003, +} VGT_GS_OUTPRIM_TYPE; + +/* + * VGT_CACHE_INVALID_MODE enum + */ + +typedef enum VGT_CACHE_INVALID_MODE { +VC_ONLY = 0x00000000, +TC_ONLY = 0x00000001, +VC_AND_TC = 0x00000002, +} VGT_CACHE_INVALID_MODE; + +/* + * VGT_TESS_TYPE enum + */ + +typedef enum VGT_TESS_TYPE { +TESS_ISOLINE = 0x00000000, +TESS_TRIANGLE = 0x00000001, +TESS_QUAD = 0x00000002, +} VGT_TESS_TYPE; + +/* + * VGT_TESS_PARTITION enum + */ + +typedef enum VGT_TESS_PARTITION { +PART_INTEGER = 0x00000000, +PART_POW2 = 0x00000001, +PART_FRAC_ODD = 0x00000002, +PART_FRAC_EVEN = 0x00000003, +} VGT_TESS_PARTITION; + +/* + * VGT_TESS_TOPOLOGY enum + */ + +typedef enum VGT_TESS_TOPOLOGY { +OUTPUT_POINT = 0x00000000, +OUTPUT_LINE = 0x00000001, +OUTPUT_TRIANGLE_CW = 0x00000002, +OUTPUT_TRIANGLE_CCW = 0x00000003, +} VGT_TESS_TOPOLOGY; + +/* + * VGT_RDREQ_POLICY enum + */ + +typedef enum VGT_RDREQ_POLICY { +VGT_POLICY_LRU = 0x00000000, +VGT_POLICY_STREAM = 0x00000001, +} VGT_RDREQ_POLICY; + +/* + * VGT_DIST_MODE enum + */ + +typedef enum VGT_DIST_MODE { +NO_DIST = 0x00000000, +PATCHES = 0x00000001, +DONUTS = 0x00000002, +TRAPEZOIDS = 0x00000003, +} VGT_DIST_MODE; + +/* + * VGT_STAGES_LS_EN enum + */ + +typedef enum VGT_STAGES_LS_EN { +LS_STAGE_OFF = 0x00000000, +LS_STAGE_ON = 0x00000001, +CS_STAGE_ON = 0x00000002, +RESERVED_LS = 0x00000003, +} VGT_STAGES_LS_EN; + +/* + * VGT_STAGES_HS_EN enum + */ + +typedef enum VGT_STAGES_HS_EN { +HS_STAGE_OFF = 0x00000000, +HS_STAGE_ON = 0x00000001, +} VGT_STAGES_HS_EN; + +/* + * VGT_STAGES_ES_EN enum + */ + +typedef enum VGT_STAGES_ES_EN { +ES_STAGE_OFF = 0x00000000, +ES_STAGE_DS = 0x00000001, +ES_STAGE_REAL = 0x00000002, +RESERVED_ES = 0x00000003, +} VGT_STAGES_ES_EN; + +/* + * VGT_STAGES_GS_EN enum + */ + +typedef enum VGT_STAGES_GS_EN { +GS_STAGE_OFF = 0x00000000, +GS_STAGE_ON = 0x00000001, +} VGT_STAGES_GS_EN; + +/* + * VGT_STAGES_VS_EN enum + */ + +typedef enum VGT_STAGES_VS_EN { +VS_STAGE_REAL = 0x00000000, +VS_STAGE_DS = 0x00000001, +VS_STAGE_COPY_SHADER = 0x00000002, +RESERVED_VS = 0x00000003, +} VGT_STAGES_VS_EN; + +/* + * VGT_PERFCOUNT_SELECT enum + */ + +typedef enum VGT_PERFCOUNT_SELECT { +vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0x00000000, +vgt_perf_VGT_SPI_ESVERT_VALID = 0x00000001, +vgt_perf_VGT_SPI_ESVERT_EOV = 0x00000002, +vgt_perf_VGT_SPI_ESVERT_STALLED = 0x00000003, +vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 0x00000004, +vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 0x00000005, +vgt_perf_VGT_SPI_ESVERT_STATIC = 0x00000006, +vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT = 0x00000007, +vgt_perf_VGT_SPI_ESTHREAD_SEND = 0x00000008, +vgt_perf_VGT_SPI_GSPRIM_VALID = 0x00000009, +vgt_perf_VGT_SPI_GSPRIM_EOV = 0x0000000a, +vgt_perf_VGT_SPI_GSPRIM_CONT = 0x0000000b, +vgt_perf_VGT_SPI_GSPRIM_STALLED = 0x0000000c, +vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 0x0000000d, +vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 0x0000000e, +vgt_perf_VGT_SPI_GSPRIM_STATIC = 0x0000000f, +vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 0x00000010, +vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT = 0x00000011, +vgt_perf_VGT_SPI_GSTHREAD_SEND = 0x00000012, +vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 0x00000013, +vgt_perf_VGT_SPI_VSVERT_SEND = 0x00000014, +vgt_perf_VGT_SPI_VSVERT_EOV = 0x00000015, +vgt_perf_VGT_SPI_VSVERT_STALLED = 0x00000016, +vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 0x00000017, +vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 0x00000018, +vgt_perf_VGT_SPI_VSVERT_STATIC = 0x00000019, +vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT = 0x0000001a, +vgt_perf_VGT_SPI_VSTHREAD_SEND = 0x0000001b, +vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 0x0000001c, +vgt_perf_VGT_PA_CLIPV_SEND = 0x0000001d, +vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 0x0000001e, +vgt_perf_VGT_PA_CLIPV_STALLED = 0x0000001f, +vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 0x00000020, +vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 0x00000021, +vgt_perf_VGT_PA_CLIPV_STATIC = 0x00000022, +vgt_perf_VGT_PA_CLIPP_SEND = 0x00000023, +vgt_perf_VGT_PA_CLIPP_EOP = 0x00000024, +vgt_perf_VGT_PA_CLIPP_IS_EVENT = 0x00000025, +vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 0x00000026, +vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 0x00000027, +vgt_perf_VGT_PA_CLIPP_STALLED = 0x00000028, +vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 0x00000029, +vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 0x0000002a, +vgt_perf_VGT_PA_CLIPP_STATIC = 0x0000002b, +vgt_perf_VGT_PA_CLIPS_SEND = 0x0000002c, +vgt_perf_VGT_PA_CLIPS_STALLED = 0x0000002d, +vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 0x0000002e, +vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 0x0000002f, +vgt_perf_VGT_PA_CLIPS_STATIC = 0x00000030, +vgt_perf_vsvert_ds_send = 0x00000031, +vgt_perf_vsvert_api_send = 0x00000032, +vgt_perf_hs_tif_stall = 0x00000033, +vgt_perf_hs_input_stall = 0x00000034, +vgt_perf_hs_interface_stall = 0x00000035, +vgt_perf_hs_tfm_stall = 0x00000036, +vgt_perf_te11_starved = 0x00000037, +vgt_perf_gs_event_stall = 0x00000038, +vgt_perf_vgt_pa_clipp_send_not_event = 0x00000039, +vgt_perf_vgt_pa_clipp_valid_prim = 0x0000003a, +vgt_perf_reused_es_indices = 0x0000003b, +vgt_perf_vs_cache_hits = 0x0000003c, +vgt_perf_gs_cache_hits = 0x0000003d, +vgt_perf_ds_cache_hits = 0x0000003e, +vgt_perf_total_cache_hits = 0x0000003f, +vgt_perf_vgt_busy = 0x00000040, +vgt_perf_vgt_gs_busy = 0x00000041, +vgt_perf_esvert_stalled_es_tbl = 0x00000042, +vgt_perf_esvert_stalled_gs_tbl = 0x00000043, +vgt_perf_esvert_stalled_gs_event = 0x00000044, +vgt_perf_esvert_stalled_gsprim = 0x00000045, +vgt_perf_gsprim_stalled_es_tbl = 0x00000046, +vgt_perf_gsprim_stalled_gs_tbl = 0x00000047, +vgt_perf_gsprim_stalled_gs_event = 0x00000048, +vgt_perf_gsprim_stalled_esvert = 0x00000049, +vgt_perf_esthread_stalled_es_rb_full = 0x0000004a, +vgt_perf_esthread_stalled_spi_bp = 0x0000004b, +vgt_perf_counters_avail_stalled = 0x0000004c, +vgt_perf_gs_rb_space_avail_stalled = 0x0000004d, +vgt_perf_gs_issue_rtr_stalled = 0x0000004e, +vgt_perf_gsthread_stalled = 0x0000004f, +vgt_perf_strmout_stalled = 0x00000050, +vgt_perf_wait_for_es_done_stalled = 0x00000051, +vgt_perf_cm_stalled_by_gog = 0x00000052, +vgt_perf_cm_reading_stalled = 0x00000053, +vgt_perf_cm_stalled_by_gsfetch_done = 0x00000054, +vgt_perf_gog_vs_tbl_stalled = 0x00000055, +vgt_perf_gog_out_indx_stalled = 0x00000056, +vgt_perf_gog_out_prim_stalled = 0x00000057, +vgt_perf_waveid_stalled = 0x00000058, +vgt_perf_gog_busy = 0x00000059, +vgt_perf_reused_vs_indices = 0x0000005a, +vgt_perf_sclk_reg_vld_event = 0x0000005b, +vgt_perf_vs_conflicting_indices = 0x0000005c, +vgt_perf_sclk_core_vld_event = 0x0000005d, +vgt_perf_hswave_stalled = 0x0000005e, +vgt_perf_sclk_gs_vld_event = 0x0000005f, +vgt_perf_VGT_SPI_LSVERT_VALID = 0x00000060, +vgt_perf_VGT_SPI_LSVERT_EOV = 0x00000061, +vgt_perf_VGT_SPI_LSVERT_STALLED = 0x00000062, +vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY = 0x00000063, +vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE = 0x00000064, +vgt_perf_VGT_SPI_LSVERT_STATIC = 0x00000065, +vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 0x00000066, +vgt_perf_VGT_SPI_LSWAVE_IS_EVENT = 0x00000067, +vgt_perf_VGT_SPI_LSWAVE_SEND = 0x00000068, +vgt_perf_VGT_SPI_HSVERT_VALID = 0x00000069, +vgt_perf_VGT_SPI_HSVERT_EOV = 0x0000006a, +vgt_perf_VGT_SPI_HSVERT_STALLED = 0x0000006b, +vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY = 0x0000006c, +vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE = 0x0000006d, +vgt_perf_VGT_SPI_HSVERT_STATIC = 0x0000006e, +vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 0x0000006f, +vgt_perf_VGT_SPI_HSWAVE_IS_EVENT = 0x00000070, +vgt_perf_VGT_SPI_HSWAVE_SEND = 0x00000071, +vgt_perf_ds_prims = 0x00000072, +vgt_perf_ds_RESERVED = 0x00000073, +vgt_perf_ls_thread_groups = 0x00000074, +vgt_perf_hs_thread_groups = 0x00000075, +vgt_perf_es_thread_groups = 0x00000076, +vgt_perf_vs_thread_groups = 0x00000077, +vgt_perf_ls_done_latency = 0x00000078, +vgt_perf_hs_done_latency = 0x00000079, +vgt_perf_es_done_latency = 0x0000007a, +vgt_perf_gs_done_latency = 0x0000007b, +vgt_perf_vgt_hs_busy = 0x0000007c, +vgt_perf_vgt_te11_busy = 0x0000007d, +vgt_perf_ls_flush = 0x0000007e, +vgt_perf_hs_flush = 0x0000007f, +vgt_perf_es_flush = 0x00000080, +vgt_perf_vgt_pa_clipp_eopg = 0x00000081, +vgt_perf_ls_done = 0x00000082, +vgt_perf_hs_done = 0x00000083, +vgt_perf_es_done = 0x00000084, +vgt_perf_gs_done = 0x00000085, +vgt_perf_vsfetch_done = 0x00000086, +vgt_perf_gs_done_received = 0x00000087, +vgt_perf_es_ring_high_water_mark = 0x00000088, +vgt_perf_gs_ring_high_water_mark = 0x00000089, +vgt_perf_vs_table_high_water_mark = 0x0000008a, +vgt_perf_hs_tgs_active_high_water_mark = 0x0000008b, +vgt_perf_pa_clipp_dealloc = 0x0000008c, +vgt_perf_cut_mem_flush_stalled = 0x0000008d, +vgt_perf_vsvert_work_received = 0x0000008e, +vgt_perf_vgt_pa_clipp_starved_after_work = 0x0000008f, +vgt_perf_te11_con_starved_after_work = 0x00000090, +vgt_perf_hs_waiting_on_ls_done_stall = 0x00000091, +vgt_spi_vsvert_valid = 0x00000092, +} VGT_PERFCOUNT_SELECT; + +/* + * IA_PERFCOUNT_SELECT enum + */ + +typedef enum IA_PERFCOUNT_SELECT { +ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE = 0x00000000, +ia_perf_dma_data_fifo_full = 0x00000001, +ia_perf_RESERVED1 = 0x00000002, +ia_perf_RESERVED2 = 0x00000003, +ia_perf_RESERVED3 = 0x00000004, +ia_perf_RESERVED4 = 0x00000005, +ia_perf_RESERVED5 = 0x00000006, +ia_perf_MC_LAT_BIN_0 = 0x00000007, +ia_perf_MC_LAT_BIN_1 = 0x00000008, +ia_perf_MC_LAT_BIN_2 = 0x00000009, +ia_perf_MC_LAT_BIN_3 = 0x0000000a, +ia_perf_MC_LAT_BIN_4 = 0x0000000b, +ia_perf_MC_LAT_BIN_5 = 0x0000000c, +ia_perf_MC_LAT_BIN_6 = 0x0000000d, +ia_perf_MC_LAT_BIN_7 = 0x0000000e, +ia_perf_ia_busy = 0x0000000f, +ia_perf_ia_sclk_reg_vld_event = 0x00000010, +ia_perf_RESERVED6 = 0x00000011, +ia_perf_ia_sclk_core_vld_event = 0x00000012, +ia_perf_RESERVED7 = 0x00000013, +ia_perf_ia_dma_return = 0x00000014, +ia_perf_ia_stalled = 0x00000015, +ia_perf_shift_starved_pipe0_event = 0x00000016, +ia_perf_shift_starved_pipe1_event = 0x00000017, +} IA_PERFCOUNT_SELECT; + +/* + * WD_PERFCOUNT_SELECT enum + */ + +typedef enum WD_PERFCOUNT_SELECT { +wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0x00000000, +wd_perf_RBIU_DR_FIFO_STARVED = 0x00000001, +wd_perf_RBIU_DR_FIFO_STALLED = 0x00000002, +wd_perf_RBIU_DI_FIFO_STARVED = 0x00000003, +wd_perf_RBIU_DI_FIFO_STALLED = 0x00000004, +wd_perf_wd_busy = 0x00000005, +wd_perf_wd_sclk_reg_vld_event = 0x00000006, +wd_perf_wd_sclk_input_vld_event = 0x00000007, +wd_perf_wd_sclk_core_vld_event = 0x00000008, +wd_perf_wd_stalled = 0x00000009, +wd_perf_inside_tf_bin_0 = 0x0000000a, +wd_perf_inside_tf_bin_1 = 0x0000000b, +wd_perf_inside_tf_bin_2 = 0x0000000c, +wd_perf_inside_tf_bin_3 = 0x0000000d, +wd_perf_inside_tf_bin_4 = 0x0000000e, +wd_perf_inside_tf_bin_5 = 0x0000000f, +wd_perf_inside_tf_bin_6 = 0x00000010, +wd_perf_inside_tf_bin_7 = 0x00000011, +wd_perf_inside_tf_bin_8 = 0x00000012, +wd_perf_tfreq_lat_bin_0 = 0x00000013, +wd_perf_tfreq_lat_bin_1 = 0x00000014, +wd_perf_tfreq_lat_bin_2 = 0x00000015, +wd_perf_tfreq_lat_bin_3 = 0x00000016, +wd_perf_tfreq_lat_bin_4 = 0x00000017, +wd_perf_tfreq_lat_bin_5 = 0x00000018, +wd_perf_tfreq_lat_bin_6 = 0x00000019, +wd_perf_tfreq_lat_bin_7 = 0x0000001a, +wd_starved_on_hs_done = 0x0000001b, +wd_perf_se0_hs_done_latency = 0x0000001c, +wd_perf_se1_hs_done_latency = 0x0000001d, +wd_perf_se2_hs_done_latency = 0x0000001e, +wd_perf_se3_hs_done_latency = 0x0000001f, +wd_perf_hs_done_se0 = 0x00000020, +wd_perf_hs_done_se1 = 0x00000021, +wd_perf_hs_done_se2 = 0x00000022, +wd_perf_hs_done_se3 = 0x00000023, +wd_perf_null_patches = 0x00000024, +} WD_PERFCOUNT_SELECT; + +/* + * WD_IA_DRAW_TYPE enum + */ + +typedef enum WD_IA_DRAW_TYPE { +WD_IA_DRAW_TYPE_DI_MM0 = 0x00000000, +WD_IA_DRAW_TYPE_REG_XFER = 0x00000001, +WD_IA_DRAW_TYPE_EVENT_INIT = 0x00000002, +WD_IA_DRAW_TYPE_EVENT_ADDR = 0x00000003, +WD_IA_DRAW_TYPE_MIN_INDX = 0x00000004, +WD_IA_DRAW_TYPE_MAX_INDX = 0x00000005, +WD_IA_DRAW_TYPE_INDX_OFF = 0x00000006, +WD_IA_DRAW_TYPE_IMM_DATA = 0x00000007, +} WD_IA_DRAW_TYPE; + +/* + * WD_IA_DRAW_REG_XFER enum + */ + +typedef enum WD_IA_DRAW_REG_XFER { +WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0x00000000, +WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 0x00000001, +} WD_IA_DRAW_REG_XFER; + +/* + * WD_IA_DRAW_SOURCE enum + */ + +typedef enum WD_IA_DRAW_SOURCE { +WD_IA_DRAW_SOURCE_DMA = 0x00000000, +WD_IA_DRAW_SOURCE_IMMD = 0x00000001, +WD_IA_DRAW_SOURCE_AUTO = 0x00000002, +WD_IA_DRAW_SOURCE_OPAQ = 0x00000003, +} WD_IA_DRAW_SOURCE; + +/* + * GS_THREADID_SIZE value + */ + +#define GSTHREADID_SIZE 0x00000002 + +/******************************************************* + * GB Enums + *******************************************************/ + +/* + * GB_EDC_DED_MODE enum + */ + +typedef enum GB_EDC_DED_MODE { +GB_EDC_DED_MODE_LOG = 0x00000000, +GB_EDC_DED_MODE_HALT = 0x00000001, +GB_EDC_DED_MODE_INT_HALT = 0x00000002, +} GB_EDC_DED_MODE; + +/* + * VALUE_GB_TILING_CONFIG_TABLE_SIZE value + */ + +#define GB_TILING_CONFIG_TABLE_SIZE 0x00000020 + +/* + * VALUE_GB_TILING_CONFIG_MACROTABLE_SIZE value + */ + +#define GB_TILING_CONFIG_MACROTABLE_SIZE 0x00000010 + +/******************************************************* + * TP Enums + *******************************************************/ + +/* + * TA_TC_ADDR_MODES enum + */ + +typedef enum TA_TC_ADDR_MODES { +TA_TC_ADDR_MODE_DEFAULT = 0x00000000, +TA_TC_ADDR_MODE_COMP0 = 0x00000001, +TA_TC_ADDR_MODE_COMP1 = 0x00000002, +TA_TC_ADDR_MODE_COMP2 = 0x00000003, +TA_TC_ADDR_MODE_COMP3 = 0x00000004, +TA_TC_ADDR_MODE_UNALIGNED = 0x00000005, +TA_TC_ADDR_MODE_BORDER_COLOR = 0x00000006, +} TA_TC_ADDR_MODES; + +/* + * TA_PERFCOUNT_SEL enum + */ + +typedef enum TA_PERFCOUNT_SEL { +TA_PERF_SEL_NULL = 0x00000000, +TA_PERF_SEL_sh_fifo_busy = 0x00000001, +TA_PERF_SEL_sh_fifo_cmd_busy = 0x00000002, +TA_PERF_SEL_sh_fifo_addr_busy = 0x00000003, +TA_PERF_SEL_sh_fifo_data_busy = 0x00000004, +TA_PERF_SEL_sh_fifo_data_sfifo_busy = 0x00000005, +TA_PERF_SEL_sh_fifo_data_tfifo_busy = 0x00000006, +TA_PERF_SEL_gradient_busy = 0x00000007, +TA_PERF_SEL_gradient_fifo_busy = 0x00000008, +TA_PERF_SEL_lod_busy = 0x00000009, +TA_PERF_SEL_lod_fifo_busy = 0x0000000a, +TA_PERF_SEL_addresser_busy = 0x0000000b, +TA_PERF_SEL_addresser_fifo_busy = 0x0000000c, +TA_PERF_SEL_aligner_busy = 0x0000000d, +TA_PERF_SEL_write_path_busy = 0x0000000e, +TA_PERF_SEL_ta_busy = 0x0000000f, +TA_PERF_SEL_sq_ta_cmd_cycles = 0x00000010, +TA_PERF_SEL_sp_ta_addr_cycles = 0x00000011, +TA_PERF_SEL_sp_ta_data_cycles = 0x00000012, +TA_PERF_SEL_ta_fa_data_state_cycles = 0x00000013, +TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 0x00000014, +TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 0x00000015, +TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles = 0x00000016, +TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles = 0x00000017, +TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles = 0x00000018, +TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles = 0x00000019, +TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles = 0x0000001a, +TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles = 0x0000001b, +TA_PERF_SEL_RESERVED_28 = 0x0000001c, +TA_PERF_SEL_RESERVED_29 = 0x0000001d, +TA_PERF_SEL_sh_fifo_addr_cycles = 0x0000001e, +TA_PERF_SEL_sh_fifo_data_cycles = 0x0000001f, +TA_PERF_SEL_total_wavefronts = 0x00000020, +TA_PERF_SEL_gradient_cycles = 0x00000021, +TA_PERF_SEL_walker_cycles = 0x00000022, +TA_PERF_SEL_aligner_cycles = 0x00000023, +TA_PERF_SEL_image_wavefronts = 0x00000024, +TA_PERF_SEL_image_read_wavefronts = 0x00000025, +TA_PERF_SEL_image_write_wavefronts = 0x00000026, +TA_PERF_SEL_image_atomic_wavefronts = 0x00000027, +TA_PERF_SEL_image_total_cycles = 0x00000028, +TA_PERF_SEL_RESERVED_41 = 0x00000029, +TA_PERF_SEL_RESERVED_42 = 0x0000002a, +TA_PERF_SEL_RESERVED_43 = 0x0000002b, +TA_PERF_SEL_buffer_wavefronts = 0x0000002c, +TA_PERF_SEL_buffer_read_wavefronts = 0x0000002d, +TA_PERF_SEL_buffer_write_wavefronts = 0x0000002e, +TA_PERF_SEL_buffer_atomic_wavefronts = 0x0000002f, +TA_PERF_SEL_buffer_coalescable_wavefronts = 0x00000030, +TA_PERF_SEL_buffer_total_cycles = 0x00000031, +TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles = 0x00000032, +TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles = 0x00000033, +TA_PERF_SEL_buffer_coalesced_read_cycles = 0x00000034, +TA_PERF_SEL_buffer_coalesced_write_cycles = 0x00000035, +TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x00000036, +TA_PERF_SEL_addr_stalled_by_td_cycles = 0x00000037, +TA_PERF_SEL_data_stalled_by_tc_cycles = 0x00000038, +TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 0x00000039, +TA_PERF_SEL_addresser_stalled_cycles = 0x0000003a, +TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 0x0000003b, +TA_PERF_SEL_aniso_stalled_cycles = 0x0000003c, +TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x0000003d, +TA_PERF_SEL_deriv_stalled_cycles = 0x0000003e, +TA_PERF_SEL_aniso_gt1_cycle_quads = 0x0000003f, +TA_PERF_SEL_color_1_cycle_pixels = 0x00000040, +TA_PERF_SEL_color_2_cycle_pixels = 0x00000041, +TA_PERF_SEL_color_3_cycle_pixels = 0x00000042, +TA_PERF_SEL_color_4_cycle_pixels = 0x00000043, +TA_PERF_SEL_mip_1_cycle_pixels = 0x00000044, +TA_PERF_SEL_mip_2_cycle_pixels = 0x00000045, +TA_PERF_SEL_vol_1_cycle_pixels = 0x00000046, +TA_PERF_SEL_vol_2_cycle_pixels = 0x00000047, +TA_PERF_SEL_bilin_point_1_cycle_pixels = 0x00000048, +TA_PERF_SEL_mipmap_lod_0_samples = 0x00000049, +TA_PERF_SEL_mipmap_lod_1_samples = 0x0000004a, +TA_PERF_SEL_mipmap_lod_2_samples = 0x0000004b, +TA_PERF_SEL_mipmap_lod_3_samples = 0x0000004c, +TA_PERF_SEL_mipmap_lod_4_samples = 0x0000004d, +TA_PERF_SEL_mipmap_lod_5_samples = 0x0000004e, +TA_PERF_SEL_mipmap_lod_6_samples = 0x0000004f, +TA_PERF_SEL_mipmap_lod_7_samples = 0x00000050, +TA_PERF_SEL_mipmap_lod_8_samples = 0x00000051, +TA_PERF_SEL_mipmap_lod_9_samples = 0x00000052, +TA_PERF_SEL_mipmap_lod_10_samples = 0x00000053, +TA_PERF_SEL_mipmap_lod_11_samples = 0x00000054, +TA_PERF_SEL_mipmap_lod_12_samples = 0x00000055, +TA_PERF_SEL_mipmap_lod_13_samples = 0x00000056, +TA_PERF_SEL_mipmap_lod_14_samples = 0x00000057, +TA_PERF_SEL_mipmap_invalid_samples = 0x00000058, +TA_PERF_SEL_aniso_1_cycle_quads = 0x00000059, +TA_PERF_SEL_aniso_2_cycle_quads = 0x0000005a, +TA_PERF_SEL_aniso_4_cycle_quads = 0x0000005b, +TA_PERF_SEL_aniso_6_cycle_quads = 0x0000005c, +TA_PERF_SEL_aniso_8_cycle_quads = 0x0000005d, +TA_PERF_SEL_aniso_10_cycle_quads = 0x0000005e, +TA_PERF_SEL_aniso_12_cycle_quads = 0x0000005f, +TA_PERF_SEL_aniso_14_cycle_quads = 0x00000060, +TA_PERF_SEL_aniso_16_cycle_quads = 0x00000061, +TA_PERF_SEL_write_path_input_cycles = 0x00000062, +TA_PERF_SEL_write_path_output_cycles = 0x00000063, +TA_PERF_SEL_flat_wavefronts = 0x00000064, +TA_PERF_SEL_flat_read_wavefronts = 0x00000065, +TA_PERF_SEL_flat_write_wavefronts = 0x00000066, +TA_PERF_SEL_flat_atomic_wavefronts = 0x00000067, +TA_PERF_SEL_flat_coalesceable_wavefronts = 0x00000068, +TA_PERF_SEL_reg_sclk_vld = 0x00000069, +TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x0000006a, +TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x0000006b, +TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 0x0000006c, +TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x0000006d, +TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x0000006e, +TA_PERF_SEL_xnack_on_phase0 = 0x0000006f, +TA_PERF_SEL_xnack_on_phase1 = 0x00000070, +TA_PERF_SEL_xnack_on_phase2 = 0x00000071, +TA_PERF_SEL_xnack_on_phase3 = 0x00000072, +TA_PERF_SEL_first_xnack_on_phase0 = 0x00000073, +TA_PERF_SEL_first_xnack_on_phase1 = 0x00000074, +TA_PERF_SEL_first_xnack_on_phase2 = 0x00000075, +TA_PERF_SEL_first_xnack_on_phase3 = 0x00000076, +} TA_PERFCOUNT_SEL; + +/* + * TD_PERFCOUNT_SEL enum + */ + +typedef enum TD_PERFCOUNT_SEL { +TD_PERF_SEL_none = 0x00000000, +TD_PERF_SEL_td_busy = 0x00000001, +TD_PERF_SEL_input_busy = 0x00000002, +TD_PERF_SEL_output_busy = 0x00000003, +TD_PERF_SEL_lerp_busy = 0x00000004, +TD_PERF_SEL_reg_sclk_vld = 0x00000005, +TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x00000006, +TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x00000007, +TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x00000008, +TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x00000009, +TD_PERF_SEL_tc_td_fifo_full = 0x0000000a, +TD_PERF_SEL_constant_state_full = 0x0000000b, +TD_PERF_SEL_sample_state_full = 0x0000000c, +TD_PERF_SEL_output_fifo_full = 0x0000000d, +TD_PERF_SEL_RESERVED_14 = 0x0000000e, +TD_PERF_SEL_tc_stall = 0x0000000f, +TD_PERF_SEL_pc_stall = 0x00000010, +TD_PERF_SEL_gds_stall = 0x00000011, +TD_PERF_SEL_RESERVED_18 = 0x00000012, +TD_PERF_SEL_RESERVED_19 = 0x00000013, +TD_PERF_SEL_gather4_wavefront = 0x00000014, +TD_PERF_SEL_gather4h_wavefront = 0x00000015, +TD_PERF_SEL_gather4h_packed_wavefront = 0x00000016, +TD_PERF_SEL_gather8h_packed_wavefront = 0x00000017, +TD_PERF_SEL_sample_c_wavefront = 0x00000018, +TD_PERF_SEL_load_wavefront = 0x00000019, +TD_PERF_SEL_atomic_wavefront = 0x0000001a, +TD_PERF_SEL_store_wavefront = 0x0000001b, +TD_PERF_SEL_ldfptr_wavefront = 0x0000001c, +TD_PERF_SEL_d16_en_wavefront = 0x0000001d, +TD_PERF_SEL_bypass_filter_wavefront = 0x0000001e, +TD_PERF_SEL_min_max_filter_wavefront = 0x0000001f, +TD_PERF_SEL_coalescable_wavefront = 0x00000020, +TD_PERF_SEL_coalesced_phase = 0x00000021, +TD_PERF_SEL_four_phase_wavefront = 0x00000022, +TD_PERF_SEL_eight_phase_wavefront = 0x00000023, +TD_PERF_SEL_sixteen_phase_wavefront = 0x00000024, +TD_PERF_SEL_four_phase_forward_wavefront = 0x00000025, +TD_PERF_SEL_write_ack_wavefront = 0x00000026, +TD_PERF_SEL_RESERVED_39 = 0x00000027, +TD_PERF_SEL_user_defined_border = 0x00000028, +TD_PERF_SEL_white_border = 0x00000029, +TD_PERF_SEL_opaque_black_border = 0x0000002a, +TD_PERF_SEL_RESERVED_43 = 0x0000002b, +TD_PERF_SEL_RESERVED_44 = 0x0000002c, +TD_PERF_SEL_nack = 0x0000002d, +TD_PERF_SEL_td_sp_traffic = 0x0000002e, +TD_PERF_SEL_consume_gds_traffic = 0x0000002f, +TD_PERF_SEL_addresscmd_poison = 0x00000030, +TD_PERF_SEL_data_poison = 0x00000031, +TD_PERF_SEL_start_cycle_0 = 0x00000032, +TD_PERF_SEL_start_cycle_1 = 0x00000033, +TD_PERF_SEL_start_cycle_2 = 0x00000034, +TD_PERF_SEL_start_cycle_3 = 0x00000035, +TD_PERF_SEL_null_cycle_output = 0x00000036, +TD_PERF_SEL_d16_data_packed = 0x00000037, +TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt = 0x00000038, +} TD_PERFCOUNT_SEL; + +/* + * TCP_PERFCOUNT_SELECT enum + */ + +typedef enum TCP_PERFCOUNT_SELECT { +TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0x00000000, +TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 0x00000001, +TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 0x00000002, +TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 0x00000003, +TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 0x00000004, +TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 0x00000005, +TCP_PERF_SEL_LOD_STALL_CYCLES = 0x00000006, +TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 0x00000007, +TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 0x00000008, +TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 0x00000009, +TCP_PERF_SEL_ALLOC_STALL_CYCLES = 0x0000000a, +TCP_PERF_SEL_LFIFO_STALL_CYCLES = 0x0000000b, +TCP_PERF_SEL_RFIFO_STALL_CYCLES = 0x0000000c, +TCP_PERF_SEL_TCR_RDRET_STALL = 0x0000000d, +TCP_PERF_SEL_WRITE_CONFLICT_STALL = 0x0000000e, +TCP_PERF_SEL_HOLE_READ_STALL = 0x0000000f, +TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 0x00000010, +TCP_PERF_SEL_PENDING_STALL_CYCLES = 0x00000011, +TCP_PERF_SEL_READFIFO_STALL_CYCLES = 0x00000012, +TCP_PERF_SEL_TCP_LATENCY = 0x00000013, +TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 0x00000014, +TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 0x00000015, +TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 0x00000016, +TCP_PERF_SEL_TCC_READ_REQ = 0x00000017, +TCP_PERF_SEL_TCC_WRITE_REQ = 0x00000018, +TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 0x00000019, +TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 0x0000001a, +TCP_PERF_SEL_TOTAL_LOCAL_READ = 0x0000001b, +TCP_PERF_SEL_TOTAL_GLOBAL_READ = 0x0000001c, +TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 0x0000001d, +TCP_PERF_SEL_TOTAL_GLOBAL_WRITE = 0x0000001e, +TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 0x0000001f, +TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 0x00000020, +TCP_PERF_SEL_TOTAL_WBINVL1 = 0x00000021, +TCP_PERF_SEL_IMG_READ_FMT_1 = 0x00000022, +TCP_PERF_SEL_IMG_READ_FMT_8 = 0x00000023, +TCP_PERF_SEL_IMG_READ_FMT_16 = 0x00000024, +TCP_PERF_SEL_IMG_READ_FMT_32 = 0x00000025, +TCP_PERF_SEL_IMG_READ_FMT_32_AS_8 = 0x00000026, +TCP_PERF_SEL_IMG_READ_FMT_32_AS_16 = 0x00000027, +TCP_PERF_SEL_IMG_READ_FMT_32_AS_128 = 0x00000028, +TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE = 0x00000029, +TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE = 0x0000002a, +TCP_PERF_SEL_IMG_READ_FMT_96 = 0x0000002b, +TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE = 0x0000002c, +TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE = 0x0000002d, +TCP_PERF_SEL_IMG_READ_FMT_BC1 = 0x0000002e, +TCP_PERF_SEL_IMG_READ_FMT_BC2 = 0x0000002f, +TCP_PERF_SEL_IMG_READ_FMT_BC3 = 0x00000030, +TCP_PERF_SEL_IMG_READ_FMT_BC4 = 0x00000031, +TCP_PERF_SEL_IMG_READ_FMT_BC5 = 0x00000032, +TCP_PERF_SEL_IMG_READ_FMT_BC6 = 0x00000033, +TCP_PERF_SEL_IMG_READ_FMT_BC7 = 0x00000034, +TCP_PERF_SEL_IMG_READ_FMT_I8 = 0x00000035, +TCP_PERF_SEL_IMG_READ_FMT_I16 = 0x00000036, +TCP_PERF_SEL_IMG_READ_FMT_I32 = 0x00000037, +TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8 = 0x00000038, +TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16 = 0x00000039, +TCP_PERF_SEL_IMG_READ_FMT_D8 = 0x0000003a, +TCP_PERF_SEL_IMG_READ_FMT_D16 = 0x0000003b, +TCP_PERF_SEL_IMG_READ_FMT_D32 = 0x0000003c, +TCP_PERF_SEL_IMG_WRITE_FMT_8 = 0x0000003d, +TCP_PERF_SEL_IMG_WRITE_FMT_16 = 0x0000003e, +TCP_PERF_SEL_IMG_WRITE_FMT_32 = 0x0000003f, +TCP_PERF_SEL_IMG_WRITE_FMT_64 = 0x00000040, +TCP_PERF_SEL_IMG_WRITE_FMT_128 = 0x00000041, +TCP_PERF_SEL_IMG_WRITE_FMT_D8 = 0x00000042, +TCP_PERF_SEL_IMG_WRITE_FMT_D16 = 0x00000043, +TCP_PERF_SEL_IMG_WRITE_FMT_D32 = 0x00000044, +TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32 = 0x00000045, +TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32 = 0x00000046, +TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64 = 0x00000047, +TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64 = 0x00000048, +TCP_PERF_SEL_BUF_READ_FMT_8 = 0x00000049, +TCP_PERF_SEL_BUF_READ_FMT_16 = 0x0000004a, +TCP_PERF_SEL_BUF_READ_FMT_32 = 0x0000004b, +TCP_PERF_SEL_BUF_WRITE_FMT_8 = 0x0000004c, +TCP_PERF_SEL_BUF_WRITE_FMT_16 = 0x0000004d, +TCP_PERF_SEL_BUF_WRITE_FMT_32 = 0x0000004e, +TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32 = 0x0000004f, +TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32 = 0x00000050, +TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64 = 0x00000051, +TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64 = 0x00000052, +TCP_PERF_SEL_ARR_LINEAR_GENERAL = 0x00000053, +TCP_PERF_SEL_ARR_LINEAR_ALIGNED = 0x00000054, +TCP_PERF_SEL_ARR_1D_THIN1 = 0x00000055, +TCP_PERF_SEL_ARR_1D_THICK = 0x00000056, +TCP_PERF_SEL_ARR_2D_THIN1 = 0x00000057, +TCP_PERF_SEL_ARR_2D_THICK = 0x00000058, +TCP_PERF_SEL_ARR_2D_XTHICK = 0x00000059, +TCP_PERF_SEL_ARR_3D_THIN1 = 0x0000005a, +TCP_PERF_SEL_ARR_3D_THICK = 0x0000005b, +TCP_PERF_SEL_ARR_3D_XTHICK = 0x0000005c, +TCP_PERF_SEL_DIM_1D = 0x0000005d, +TCP_PERF_SEL_DIM_2D = 0x0000005e, +TCP_PERF_SEL_DIM_3D = 0x0000005f, +TCP_PERF_SEL_DIM_1D_ARRAY = 0x00000060, +TCP_PERF_SEL_DIM_2D_ARRAY = 0x00000061, +TCP_PERF_SEL_DIM_2D_MSAA = 0x00000062, +TCP_PERF_SEL_DIM_2D_ARRAY_MSAA = 0x00000063, +TCP_PERF_SEL_DIM_CUBE_ARRAY = 0x00000064, +TCP_PERF_SEL_CP_TCP_INVALIDATE = 0x00000065, +TCP_PERF_SEL_TA_TCP_STATE_READ = 0x00000066, +TCP_PERF_SEL_TAGRAM0_REQ = 0x00000067, +TCP_PERF_SEL_TAGRAM1_REQ = 0x00000068, +TCP_PERF_SEL_TAGRAM2_REQ = 0x00000069, +TCP_PERF_SEL_TAGRAM3_REQ = 0x0000006a, +TCP_PERF_SEL_GATE_EN1 = 0x0000006b, +TCP_PERF_SEL_GATE_EN2 = 0x0000006c, +TCP_PERF_SEL_CORE_REG_SCLK_VLD = 0x0000006d, +TCP_PERF_SEL_TCC_REQ = 0x0000006e, +TCP_PERF_SEL_TCC_NON_READ_REQ = 0x0000006f, +TCP_PERF_SEL_TCC_BYPASS_READ_REQ = 0x00000070, +TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ = 0x00000071, +TCP_PERF_SEL_TCC_VOLATILE_READ_REQ = 0x00000072, +TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ = 0x00000073, +TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ = 0x00000074, +TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ = 0x00000075, +TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ = 0x00000076, +TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ = 0x00000077, +TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ = 0x00000078, +TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ = 0x00000079, +TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ = 0x0000007a, +TCP_PERF_SEL_TCC_ATOMIC_REQ = 0x0000007b, +TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ = 0x0000007c, +TCP_PERF_SEL_TCC_DATA_BUS_BUSY = 0x0000007d, +TCP_PERF_SEL_TOTAL_ACCESSES = 0x0000007e, +TCP_PERF_SEL_TOTAL_READ = 0x0000007f, +TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 0x00000080, +TCP_PERF_SEL_TOTAL_HIT_EVICT_READ = 0x00000081, +TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 0x00000082, +TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 0x00000083, +TCP_PERF_SEL_TOTAL_NON_READ = 0x00000084, +TCP_PERF_SEL_TOTAL_WRITE = 0x00000085, +TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 0x00000086, +TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 0x00000087, +TCP_PERF_SEL_TOTAL_WBINVL1_VOL = 0x00000088, +TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 0x00000089, +TCP_PERF_SEL_DISPLAY_MICROTILING = 0x0000008a, +TCP_PERF_SEL_THIN_MICROTILING = 0x0000008b, +TCP_PERF_SEL_DEPTH_MICROTILING = 0x0000008c, +TCP_PERF_SEL_ARR_PRT_THIN1 = 0x0000008d, +TCP_PERF_SEL_ARR_PRT_2D_THIN1 = 0x0000008e, +TCP_PERF_SEL_ARR_PRT_3D_THIN1 = 0x0000008f, +TCP_PERF_SEL_ARR_PRT_THICK = 0x00000090, +TCP_PERF_SEL_ARR_PRT_2D_THICK = 0x00000091, +TCP_PERF_SEL_ARR_PRT_3D_THICK = 0x00000092, +TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL = 0x00000093, +TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL = 0x00000094, +TCP_PERF_SEL_UNALIGNED = 0x00000095, +TCP_PERF_SEL_ROTATED_MICROTILING = 0x00000096, +TCP_PERF_SEL_THICK_MICROTILING = 0x00000097, +TCP_PERF_SEL_ATC = 0x00000098, +TCP_PERF_SEL_POWER_STALL = 0x00000099, +TCP_PERF_SEL_RESERVED_154 = 0x0000009a, +TCP_PERF_SEL_TCC_LRU_REQ = 0x0000009b, +TCP_PERF_SEL_TCC_STREAM_REQ = 0x0000009c, +TCP_PERF_SEL_TCC_NC_READ_REQ = 0x0000009d, +TCP_PERF_SEL_TCC_NC_WRITE_REQ = 0x0000009e, +TCP_PERF_SEL_TCC_NC_ATOMIC_REQ = 0x0000009f, +TCP_PERF_SEL_TCC_UC_READ_REQ = 0x000000a0, +TCP_PERF_SEL_TCC_UC_WRITE_REQ = 0x000000a1, +TCP_PERF_SEL_TCC_UC_ATOMIC_REQ = 0x000000a2, +TCP_PERF_SEL_TCC_CC_READ_REQ = 0x000000a3, +TCP_PERF_SEL_TCC_CC_WRITE_REQ = 0x000000a4, +TCP_PERF_SEL_TCC_CC_ATOMIC_REQ = 0x000000a5, +TCP_PERF_SEL_TCC_DCC_REQ = 0x000000a6, +TCP_PERF_SEL_TCC_PHYSICAL_REQ = 0x000000a7, +TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 0x000000a8, +TCP_PERF_SEL_VOLATILE = 0x000000a9, +TCP_PERF_SEL_TC_TA_XNACK_STALL = 0x000000aa, +TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL = 0x000000ab, +TCP_PERF_SEL_SHOOTDOWN = 0x000000ac, +TCP_PERF_SEL_UTCL1_TRANSLATION_MISS = 0x000000ad, +TCP_PERF_SEL_UTCL1_PERMISSION_MISS = 0x000000ae, +TCP_PERF_SEL_UTCL1_REQUEST = 0x000000af, +TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 0x000000b0, +TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 0x000000b1, +TCP_PERF_SEL_UTCL1_LFIFO_FULL = 0x000000b2, +TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 0x000000b3, +TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x000000b4, +TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT = 0x000000b5, +TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 0x000000b6, +TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB = 0x000000b7, +TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA = 0x000000b8, +TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1 = 0x000000b9, +TCP_PERF_SEL_IMG_READ_FMT_ETC2_R = 0x000000ba, +TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG = 0x000000bb, +TCP_PERF_SEL_IMG_READ_FMT_8_AS_32 = 0x000000bc, +TCP_PERF_SEL_IMG_READ_FMT_8_AS_64 = 0x000000bd, +TCP_PERF_SEL_IMG_READ_FMT_16_AS_64 = 0x000000be, +TCP_PERF_SEL_IMG_READ_FMT_16_AS_128 = 0x000000bf, +TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32 = 0x000000c0, +TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64 = 0x000000c1, +TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64 = 0x000000c2, +TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128 = 0x000000c3, +} TCP_PERFCOUNT_SELECT; + +/* + * TCP_CACHE_POLICIES enum + */ + +typedef enum TCP_CACHE_POLICIES { +TCP_CACHE_POLICY_MISS_LRU = 0x00000000, +TCP_CACHE_POLICY_MISS_EVICT = 0x00000001, +TCP_CACHE_POLICY_HIT_LRU = 0x00000002, +TCP_CACHE_POLICY_HIT_EVICT = 0x00000003, +} TCP_CACHE_POLICIES; + +/* + * TCP_CACHE_STORE_POLICIES enum + */ + +typedef enum TCP_CACHE_STORE_POLICIES { +TCP_CACHE_STORE_POLICY_WT_LRU = 0x00000000, +TCP_CACHE_STORE_POLICY_WT_EVICT = 0x00000001, +} TCP_CACHE_STORE_POLICIES; + +/* + * TCP_WATCH_MODES enum + */ + +typedef enum TCP_WATCH_MODES { +TCP_WATCH_MODE_READ = 0x00000000, +TCP_WATCH_MODE_NONREAD = 0x00000001, +TCP_WATCH_MODE_ATOMIC = 0x00000002, +TCP_WATCH_MODE_ALL = 0x00000003, +} TCP_WATCH_MODES; + +/* + * TCP_DSM_DATA_SEL enum + */ + +typedef enum TCP_DSM_DATA_SEL { +TCP_DSM_DISABLE = 0x00000000, +TCP_DSM_SEL0 = 0x00000001, +TCP_DSM_SEL1 = 0x00000002, +TCP_DSM_SEL_BOTH = 0x00000003, +} TCP_DSM_DATA_SEL; + +/* + * TCP_DSM_SINGLE_WRITE enum + */ + +typedef enum TCP_DSM_SINGLE_WRITE { +TCP_DSM_SINGLE_WRITE_DIS = 0x00000000, +TCP_DSM_SINGLE_WRITE_EN = 0x00000001, +} TCP_DSM_SINGLE_WRITE; + +/* + * TCP_DSM_INJECT_SEL enum + */ + +typedef enum TCP_DSM_INJECT_SEL { +TCP_DSM_INJECT_SEL0 = 0x00000000, +TCP_DSM_INJECT_SEL1 = 0x00000001, +TCP_DSM_INJECT_SEL2 = 0x00000002, +TCP_DSM_INJECT_SEL3 = 0x00000003, +} TCP_DSM_INJECT_SEL; + +/******************************************************* + * TCC Enums + *******************************************************/ + +/* + * TCC_PERF_SEL enum + */ + +typedef enum TCC_PERF_SEL { +TCC_PERF_SEL_NONE = 0x00000000, +TCC_PERF_SEL_CYCLE = 0x00000001, +TCC_PERF_SEL_BUSY = 0x00000002, +TCC_PERF_SEL_REQ = 0x00000003, +TCC_PERF_SEL_STREAMING_REQ = 0x00000004, +TCC_PERF_SEL_EXE_REQ = 0x00000005, +TCC_PERF_SEL_COMPRESSED_REQ = 0x00000006, +TCC_PERF_SEL_COMPRESSED_0_REQ = 0x00000007, +TCC_PERF_SEL_METADATA_REQ = 0x00000008, +TCC_PERF_SEL_NC_VIRTUAL_REQ = 0x00000009, +TCC_PERF_SEL_UC_VIRTUAL_REQ = 0x0000000a, +TCC_PERF_SEL_CC_PHYSICAL_REQ = 0x0000000b, +TCC_PERF_SEL_PROBE = 0x0000000c, +TCC_PERF_SEL_PROBE_ALL = 0x0000000d, +TCC_PERF_SEL_READ = 0x0000000e, +TCC_PERF_SEL_WRITE = 0x0000000f, +TCC_PERF_SEL_ATOMIC = 0x00000010, +TCC_PERF_SEL_HIT = 0x00000011, +TCC_PERF_SEL_SECTOR_HIT = 0x00000012, +TCC_PERF_SEL_MISS = 0x00000013, +TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0x00000014, +TCC_PERF_SEL_FULLY_WRITTEN_HIT = 0x00000015, +TCC_PERF_SEL_WRITEBACK = 0x00000016, +TCC_PERF_SEL_LATENCY_FIFO_FULL = 0x00000017, +TCC_PERF_SEL_SRC_FIFO_FULL = 0x00000018, +TCC_PERF_SEL_HOLE_FIFO_FULL = 0x00000019, +TCC_PERF_SEL_EA_WRREQ = 0x0000001a, +TCC_PERF_SEL_EA_WRREQ_64B = 0x0000001b, +TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 0x0000001c, +TCC_PERF_SEL_EA_WR_UNCACHED_32B = 0x0000001d, +TCC_PERF_SEL_EA_WRREQ_STALL = 0x0000001e, +TCC_PERF_SEL_EA_WRREQ_CREDIT_STALL = 0x0000001f, +TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 0x00000020, +TCC_PERF_SEL_EA_WRREQ_LEVEL = 0x00000021, +TCC_PERF_SEL_EA_ATOMIC = 0x00000022, +TCC_PERF_SEL_EA_ATOMIC_LEVEL = 0x00000023, +TCC_PERF_SEL_EA_RDREQ = 0x00000024, +TCC_PERF_SEL_EA_RDREQ_32B = 0x00000025, +TCC_PERF_SEL_EA_RD_UNCACHED_32B = 0x00000026, +TCC_PERF_SEL_EA_RD_MDC_32B = 0x00000027, +TCC_PERF_SEL_EA_RD_COMPRESSED_32B = 0x00000028, +TCC_PERF_SEL_EA_RDREQ_CREDIT_STALL = 0x00000029, +TCC_PERF_SEL_EA_RDREQ_LEVEL = 0x0000002a, +TCC_PERF_SEL_TAG_STALL = 0x0000002b, +TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x0000002c, +TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x0000002d, +TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 0x0000002e, +TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 0x0000002f, +TCC_PERF_SEL_TAG_PROBE_STALL = 0x00000030, +TCC_PERF_SEL_TAG_PROBE_FILTER_STALL = 0x00000031, +TCC_PERF_SEL_READ_RETURN_TIMEOUT = 0x00000032, +TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x00000033, +TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x00000034, +TCC_PERF_SEL_BUBBLE = 0x00000035, +TCC_PERF_SEL_RETURN_ACK = 0x00000036, +TCC_PERF_SEL_RETURN_DATA = 0x00000037, +TCC_PERF_SEL_RETURN_HOLE = 0x00000038, +TCC_PERF_SEL_RETURN_ACK_HOLE = 0x00000039, +TCC_PERF_SEL_IB_REQ = 0x0000003a, +TCC_PERF_SEL_IB_STALL = 0x0000003b, +TCC_PERF_SEL_IB_TAG_STALL = 0x0000003c, +TCC_PERF_SEL_IB_MDC_STALL = 0x0000003d, +TCC_PERF_SEL_TCA_LEVEL = 0x0000003e, +TCC_PERF_SEL_HOLE_LEVEL = 0x0000003f, +TCC_PERF_SEL_NORMAL_WRITEBACK = 0x00000040, +TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK = 0x00000041, +TCC_PERF_SEL_TC_OP_WBL2_WC_WRITEBACK = 0x00000042, +TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK = 0x00000043, +TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK = 0x00000044, +TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK = 0x00000045, +TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK = 0x00000046, +TCC_PERF_SEL_NORMAL_EVICT = 0x00000047, +TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT = 0x00000048, +TCC_PERF_SEL_TC_OP_WBL2_WC_EVICT = 0x00000049, +TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT = 0x0000004a, +TCC_PERF_SEL_TC_OP_WBINVL2_EVICT = 0x0000004b, +TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT = 0x0000004c, +TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT = 0x0000004d, +TCC_PERF_SEL_ALL_TC_OP_INV_EVICT = 0x0000004e, +TCC_PERF_SEL_PROBE_EVICT = 0x0000004f, +TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE = 0x00000050, +TCC_PERF_SEL_TC_OP_WBL2_WC_CYCLE = 0x00000051, +TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE = 0x00000052, +TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE = 0x00000053, +TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE = 0x00000054, +TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE = 0x00000055, +TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE = 0x00000056, +TCC_PERF_SEL_TC_OP_WBL2_NC_START = 0x00000057, +TCC_PERF_SEL_TC_OP_WBL2_WC_START = 0x00000058, +TCC_PERF_SEL_TC_OP_INVL2_NC_START = 0x00000059, +TCC_PERF_SEL_TC_OP_WBINVL2_START = 0x0000005a, +TCC_PERF_SEL_TC_OP_WBINVL2_NC_START = 0x0000005b, +TCC_PERF_SEL_TC_OP_WBINVL2_SD_START = 0x0000005c, +TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x0000005d, +TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH = 0x0000005e, +TCC_PERF_SEL_TC_OP_WBL2_WC_FINISH = 0x0000005f, +TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH = 0x00000060, +TCC_PERF_SEL_TC_OP_WBINVL2_FINISH = 0x00000061, +TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH = 0x00000062, +TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH = 0x00000063, +TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH = 0x00000064, +TCC_PERF_SEL_MDC_REQ = 0x00000065, +TCC_PERF_SEL_MDC_LEVEL = 0x00000066, +TCC_PERF_SEL_MDC_TAG_HIT = 0x00000067, +TCC_PERF_SEL_MDC_SECTOR_HIT = 0x00000068, +TCC_PERF_SEL_MDC_SECTOR_MISS = 0x00000069, +TCC_PERF_SEL_MDC_TAG_STALL = 0x0000006a, +TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 0x0000006b, +TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 0x0000006c, +TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 0x0000006d, +TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 0x0000006e, +TCC_PERF_SEL_PROBE_FILTER_DISABLED = 0x0000006f, +TCC_PERF_SEL_CLIENT0_REQ = 0x00000080, +TCC_PERF_SEL_CLIENT1_REQ = 0x00000081, +TCC_PERF_SEL_CLIENT2_REQ = 0x00000082, +TCC_PERF_SEL_CLIENT3_REQ = 0x00000083, +TCC_PERF_SEL_CLIENT4_REQ = 0x00000084, +TCC_PERF_SEL_CLIENT5_REQ = 0x00000085, +TCC_PERF_SEL_CLIENT6_REQ = 0x00000086, +TCC_PERF_SEL_CLIENT7_REQ = 0x00000087, +TCC_PERF_SEL_CLIENT8_REQ = 0x00000088, +TCC_PERF_SEL_CLIENT9_REQ = 0x00000089, +TCC_PERF_SEL_CLIENT10_REQ = 0x0000008a, +TCC_PERF_SEL_CLIENT11_REQ = 0x0000008b, +TCC_PERF_SEL_CLIENT12_REQ = 0x0000008c, +TCC_PERF_SEL_CLIENT13_REQ = 0x0000008d, +TCC_PERF_SEL_CLIENT14_REQ = 0x0000008e, +TCC_PERF_SEL_CLIENT15_REQ = 0x0000008f, +TCC_PERF_SEL_CLIENT16_REQ = 0x00000090, +TCC_PERF_SEL_CLIENT17_REQ = 0x00000091, +TCC_PERF_SEL_CLIENT18_REQ = 0x00000092, +TCC_PERF_SEL_CLIENT19_REQ = 0x00000093, +TCC_PERF_SEL_CLIENT20_REQ = 0x00000094, +TCC_PERF_SEL_CLIENT21_REQ = 0x00000095, +TCC_PERF_SEL_CLIENT22_REQ = 0x00000096, +TCC_PERF_SEL_CLIENT23_REQ = 0x00000097, +TCC_PERF_SEL_CLIENT24_REQ = 0x00000098, +TCC_PERF_SEL_CLIENT25_REQ = 0x00000099, +TCC_PERF_SEL_CLIENT26_REQ = 0x0000009a, +TCC_PERF_SEL_CLIENT27_REQ = 0x0000009b, +TCC_PERF_SEL_CLIENT28_REQ = 0x0000009c, +TCC_PERF_SEL_CLIENT29_REQ = 0x0000009d, +TCC_PERF_SEL_CLIENT30_REQ = 0x0000009e, +TCC_PERF_SEL_CLIENT31_REQ = 0x0000009f, +TCC_PERF_SEL_CLIENT32_REQ = 0x000000a0, +TCC_PERF_SEL_CLIENT33_REQ = 0x000000a1, +TCC_PERF_SEL_CLIENT34_REQ = 0x000000a2, +TCC_PERF_SEL_CLIENT35_REQ = 0x000000a3, +TCC_PERF_SEL_CLIENT36_REQ = 0x000000a4, +TCC_PERF_SEL_CLIENT37_REQ = 0x000000a5, +TCC_PERF_SEL_CLIENT38_REQ = 0x000000a6, +TCC_PERF_SEL_CLIENT39_REQ = 0x000000a7, +TCC_PERF_SEL_CLIENT40_REQ = 0x000000a8, +TCC_PERF_SEL_CLIENT41_REQ = 0x000000a9, +TCC_PERF_SEL_CLIENT42_REQ = 0x000000aa, +TCC_PERF_SEL_CLIENT43_REQ = 0x000000ab, +TCC_PERF_SEL_CLIENT44_REQ = 0x000000ac, +TCC_PERF_SEL_CLIENT45_REQ = 0x000000ad, +TCC_PERF_SEL_CLIENT46_REQ = 0x000000ae, +TCC_PERF_SEL_CLIENT47_REQ = 0x000000af, +TCC_PERF_SEL_CLIENT48_REQ = 0x000000b0, +TCC_PERF_SEL_CLIENT49_REQ = 0x000000b1, +TCC_PERF_SEL_CLIENT50_REQ = 0x000000b2, +TCC_PERF_SEL_CLIENT51_REQ = 0x000000b3, +TCC_PERF_SEL_CLIENT52_REQ = 0x000000b4, +TCC_PERF_SEL_CLIENT53_REQ = 0x000000b5, +TCC_PERF_SEL_CLIENT54_REQ = 0x000000b6, +TCC_PERF_SEL_CLIENT55_REQ = 0x000000b7, +TCC_PERF_SEL_CLIENT56_REQ = 0x000000b8, +TCC_PERF_SEL_CLIENT57_REQ = 0x000000b9, +TCC_PERF_SEL_CLIENT58_REQ = 0x000000ba, +TCC_PERF_SEL_CLIENT59_REQ = 0x000000bb, +TCC_PERF_SEL_CLIENT60_REQ = 0x000000bc, +TCC_PERF_SEL_CLIENT61_REQ = 0x000000bd, +TCC_PERF_SEL_CLIENT62_REQ = 0x000000be, +TCC_PERF_SEL_CLIENT63_REQ = 0x000000bf, +TCC_PERF_SEL_CLIENT64_REQ = 0x000000c0, +TCC_PERF_SEL_CLIENT65_REQ = 0x000000c1, +TCC_PERF_SEL_CLIENT66_REQ = 0x000000c2, +TCC_PERF_SEL_CLIENT67_REQ = 0x000000c3, +TCC_PERF_SEL_CLIENT68_REQ = 0x000000c4, +TCC_PERF_SEL_CLIENT69_REQ = 0x000000c5, +TCC_PERF_SEL_CLIENT70_REQ = 0x000000c6, +TCC_PERF_SEL_CLIENT71_REQ = 0x000000c7, +TCC_PERF_SEL_CLIENT72_REQ = 0x000000c8, +TCC_PERF_SEL_CLIENT73_REQ = 0x000000c9, +TCC_PERF_SEL_CLIENT74_REQ = 0x000000ca, +TCC_PERF_SEL_CLIENT75_REQ = 0x000000cb, +TCC_PERF_SEL_CLIENT76_REQ = 0x000000cc, +TCC_PERF_SEL_CLIENT77_REQ = 0x000000cd, +TCC_PERF_SEL_CLIENT78_REQ = 0x000000ce, +TCC_PERF_SEL_CLIENT79_REQ = 0x000000cf, +TCC_PERF_SEL_CLIENT80_REQ = 0x000000d0, +TCC_PERF_SEL_CLIENT81_REQ = 0x000000d1, +TCC_PERF_SEL_CLIENT82_REQ = 0x000000d2, +TCC_PERF_SEL_CLIENT83_REQ = 0x000000d3, +TCC_PERF_SEL_CLIENT84_REQ = 0x000000d4, +TCC_PERF_SEL_CLIENT85_REQ = 0x000000d5, +TCC_PERF_SEL_CLIENT86_REQ = 0x000000d6, +TCC_PERF_SEL_CLIENT87_REQ = 0x000000d7, +TCC_PERF_SEL_CLIENT88_REQ = 0x000000d8, +TCC_PERF_SEL_CLIENT89_REQ = 0x000000d9, +TCC_PERF_SEL_CLIENT90_REQ = 0x000000da, +TCC_PERF_SEL_CLIENT91_REQ = 0x000000db, +TCC_PERF_SEL_CLIENT92_REQ = 0x000000dc, +TCC_PERF_SEL_CLIENT93_REQ = 0x000000dd, +TCC_PERF_SEL_CLIENT94_REQ = 0x000000de, +TCC_PERF_SEL_CLIENT95_REQ = 0x000000df, +TCC_PERF_SEL_CLIENT96_REQ = 0x000000e0, +TCC_PERF_SEL_CLIENT97_REQ = 0x000000e1, +TCC_PERF_SEL_CLIENT98_REQ = 0x000000e2, +TCC_PERF_SEL_CLIENT99_REQ = 0x000000e3, +TCC_PERF_SEL_CLIENT100_REQ = 0x000000e4, +TCC_PERF_SEL_CLIENT101_REQ = 0x000000e5, +TCC_PERF_SEL_CLIENT102_REQ = 0x000000e6, +TCC_PERF_SEL_CLIENT103_REQ = 0x000000e7, +TCC_PERF_SEL_CLIENT104_REQ = 0x000000e8, +TCC_PERF_SEL_CLIENT105_REQ = 0x000000e9, +TCC_PERF_SEL_CLIENT106_REQ = 0x000000ea, +TCC_PERF_SEL_CLIENT107_REQ = 0x000000eb, +TCC_PERF_SEL_CLIENT108_REQ = 0x000000ec, +TCC_PERF_SEL_CLIENT109_REQ = 0x000000ed, +TCC_PERF_SEL_CLIENT110_REQ = 0x000000ee, +TCC_PERF_SEL_CLIENT111_REQ = 0x000000ef, +TCC_PERF_SEL_CLIENT112_REQ = 0x000000f0, +TCC_PERF_SEL_CLIENT113_REQ = 0x000000f1, +TCC_PERF_SEL_CLIENT114_REQ = 0x000000f2, +TCC_PERF_SEL_CLIENT115_REQ = 0x000000f3, +TCC_PERF_SEL_CLIENT116_REQ = 0x000000f4, +TCC_PERF_SEL_CLIENT117_REQ = 0x000000f5, +TCC_PERF_SEL_CLIENT118_REQ = 0x000000f6, +TCC_PERF_SEL_CLIENT119_REQ = 0x000000f7, +TCC_PERF_SEL_CLIENT120_REQ = 0x000000f8, +TCC_PERF_SEL_CLIENT121_REQ = 0x000000f9, +TCC_PERF_SEL_CLIENT122_REQ = 0x000000fa, +TCC_PERF_SEL_CLIENT123_REQ = 0x000000fb, +TCC_PERF_SEL_CLIENT124_REQ = 0x000000fc, +TCC_PERF_SEL_CLIENT125_REQ = 0x000000fd, +TCC_PERF_SEL_CLIENT126_REQ = 0x000000fe, +TCC_PERF_SEL_CLIENT127_REQ = 0x000000ff, +} TCC_PERF_SEL; + +/* + * TCA_PERF_SEL enum + */ + +typedef enum TCA_PERF_SEL { +TCA_PERF_SEL_NONE = 0x00000000, +TCA_PERF_SEL_CYCLE = 0x00000001, +TCA_PERF_SEL_BUSY = 0x00000002, +TCA_PERF_SEL_FORCED_HOLE_TCC0 = 0x00000003, +TCA_PERF_SEL_FORCED_HOLE_TCC1 = 0x00000004, +TCA_PERF_SEL_FORCED_HOLE_TCC2 = 0x00000005, +TCA_PERF_SEL_FORCED_HOLE_TCC3 = 0x00000006, +TCA_PERF_SEL_FORCED_HOLE_TCC4 = 0x00000007, +TCA_PERF_SEL_FORCED_HOLE_TCC5 = 0x00000008, +TCA_PERF_SEL_FORCED_HOLE_TCC6 = 0x00000009, +TCA_PERF_SEL_FORCED_HOLE_TCC7 = 0x0000000a, +TCA_PERF_SEL_REQ_TCC0 = 0x0000000b, +TCA_PERF_SEL_REQ_TCC1 = 0x0000000c, +TCA_PERF_SEL_REQ_TCC2 = 0x0000000d, +TCA_PERF_SEL_REQ_TCC3 = 0x0000000e, +TCA_PERF_SEL_REQ_TCC4 = 0x0000000f, +TCA_PERF_SEL_REQ_TCC5 = 0x00000010, +TCA_PERF_SEL_REQ_TCC6 = 0x00000011, +TCA_PERF_SEL_REQ_TCC7 = 0x00000012, +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 0x00000013, +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 0x00000014, +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 0x00000015, +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 0x00000016, +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 0x00000017, +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 0x00000018, +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 0x00000019, +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 0x0000001a, +TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 0x0000001b, +TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 0x0000001c, +TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 0x0000001d, +TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 0x0000001e, +TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 0x0000001f, +TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 0x00000020, +TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 0x00000021, +TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 0x00000022, +} TCA_PERF_SEL; + +/******************************************************* + * GRBM Enums + *******************************************************/ + +/* + * GRBM_PERF_SEL enum + */ + +typedef enum GRBM_PERF_SEL { +GRBM_PERF_SEL_COUNT = 0x00000000, +GRBM_PERF_SEL_USER_DEFINED = 0x00000001, +GRBM_PERF_SEL_GUI_ACTIVE = 0x00000002, +GRBM_PERF_SEL_CP_BUSY = 0x00000003, +GRBM_PERF_SEL_CP_COHER_BUSY = 0x00000004, +GRBM_PERF_SEL_CP_DMA_BUSY = 0x00000005, +GRBM_PERF_SEL_CB_BUSY = 0x00000006, +GRBM_PERF_SEL_DB_BUSY = 0x00000007, +GRBM_PERF_SEL_PA_BUSY = 0x00000008, +GRBM_PERF_SEL_SC_BUSY = 0x00000009, +GRBM_PERF_SEL_RESERVED_6 = 0x0000000a, +GRBM_PERF_SEL_SPI_BUSY = 0x0000000b, +GRBM_PERF_SEL_SX_BUSY = 0x0000000c, +GRBM_PERF_SEL_TA_BUSY = 0x0000000d, +GRBM_PERF_SEL_CB_CLEAN = 0x0000000e, +GRBM_PERF_SEL_DB_CLEAN = 0x0000000f, +GRBM_PERF_SEL_RESERVED_5 = 0x00000010, +GRBM_PERF_SEL_VGT_BUSY = 0x00000011, +GRBM_PERF_SEL_RESERVED_4 = 0x00000012, +GRBM_PERF_SEL_RESERVED_3 = 0x00000013, +GRBM_PERF_SEL_RESERVED_2 = 0x00000014, +GRBM_PERF_SEL_RESERVED_1 = 0x00000015, +GRBM_PERF_SEL_RESERVED_0 = 0x00000016, +GRBM_PERF_SEL_IA_BUSY = 0x00000017, +GRBM_PERF_SEL_IA_NO_DMA_BUSY = 0x00000018, +GRBM_PERF_SEL_GDS_BUSY = 0x00000019, +GRBM_PERF_SEL_BCI_BUSY = 0x0000001a, +GRBM_PERF_SEL_RLC_BUSY = 0x0000001b, +GRBM_PERF_SEL_TC_BUSY = 0x0000001c, +GRBM_PERF_SEL_CPG_BUSY = 0x0000001d, +GRBM_PERF_SEL_CPC_BUSY = 0x0000001e, +GRBM_PERF_SEL_CPF_BUSY = 0x0000001f, +GRBM_PERF_SEL_WD_BUSY = 0x00000020, +GRBM_PERF_SEL_WD_NO_DMA_BUSY = 0x00000021, +GRBM_PERF_SEL_UTCL2_BUSY = 0x00000022, +GRBM_PERF_SEL_EA_BUSY = 0x00000023, +GRBM_PERF_SEL_RMI_BUSY = 0x00000024, +GRBM_PERF_SEL_CPAXI_BUSY = 0x00000025, +} GRBM_PERF_SEL; + +/* + * GRBM_SE0_PERF_SEL enum + */ + +typedef enum GRBM_SE0_PERF_SEL { +GRBM_SE0_PERF_SEL_COUNT = 0x00000000, +GRBM_SE0_PERF_SEL_USER_DEFINED = 0x00000001, +GRBM_SE0_PERF_SEL_CB_BUSY = 0x00000002, +GRBM_SE0_PERF_SEL_DB_BUSY = 0x00000003, +GRBM_SE0_PERF_SEL_SC_BUSY = 0x00000004, +GRBM_SE0_PERF_SEL_RESERVED_1 = 0x00000005, +GRBM_SE0_PERF_SEL_SPI_BUSY = 0x00000006, +GRBM_SE0_PERF_SEL_SX_BUSY = 0x00000007, +GRBM_SE0_PERF_SEL_TA_BUSY = 0x00000008, +GRBM_SE0_PERF_SEL_CB_CLEAN = 0x00000009, +GRBM_SE0_PERF_SEL_DB_CLEAN = 0x0000000a, +GRBM_SE0_PERF_SEL_RESERVED_0 = 0x0000000b, +GRBM_SE0_PERF_SEL_PA_BUSY = 0x0000000c, +GRBM_SE0_PERF_SEL_VGT_BUSY = 0x0000000d, +GRBM_SE0_PERF_SEL_BCI_BUSY = 0x0000000e, +GRBM_SE0_PERF_SEL_RMI_BUSY = 0x0000000f, +} GRBM_SE0_PERF_SEL; + +/* + * GRBM_SE1_PERF_SEL enum + */ + +typedef enum GRBM_SE1_PERF_SEL { +GRBM_SE1_PERF_SEL_COUNT = 0x00000000, +GRBM_SE1_PERF_SEL_USER_DEFINED = 0x00000001, +GRBM_SE1_PERF_SEL_CB_BUSY = 0x00000002, +GRBM_SE1_PERF_SEL_DB_BUSY = 0x00000003, +GRBM_SE1_PERF_SEL_SC_BUSY = 0x00000004, +GRBM_SE1_PERF_SEL_RESERVED_1 = 0x00000005, +GRBM_SE1_PERF_SEL_SPI_BUSY = 0x00000006, +GRBM_SE1_PERF_SEL_SX_BUSY = 0x00000007, +GRBM_SE1_PERF_SEL_TA_BUSY = 0x00000008, +GRBM_SE1_PERF_SEL_CB_CLEAN = 0x00000009, +GRBM_SE1_PERF_SEL_DB_CLEAN = 0x0000000a, +GRBM_SE1_PERF_SEL_RESERVED_0 = 0x0000000b, +GRBM_SE1_PERF_SEL_PA_BUSY = 0x0000000c, +GRBM_SE1_PERF_SEL_VGT_BUSY = 0x0000000d, +GRBM_SE1_PERF_SEL_BCI_BUSY = 0x0000000e, +GRBM_SE1_PERF_SEL_RMI_BUSY = 0x0000000f, +} GRBM_SE1_PERF_SEL; + +/* + * GRBM_SE2_PERF_SEL enum + */ + +typedef enum GRBM_SE2_PERF_SEL { +GRBM_SE2_PERF_SEL_COUNT = 0x00000000, +GRBM_SE2_PERF_SEL_USER_DEFINED = 0x00000001, +GRBM_SE2_PERF_SEL_CB_BUSY = 0x00000002, +GRBM_SE2_PERF_SEL_DB_BUSY = 0x00000003, +GRBM_SE2_PERF_SEL_SC_BUSY = 0x00000004, +GRBM_SE2_PERF_SEL_RESERVED_1 = 0x00000005, +GRBM_SE2_PERF_SEL_SPI_BUSY = 0x00000006, +GRBM_SE2_PERF_SEL_SX_BUSY = 0x00000007, +GRBM_SE2_PERF_SEL_TA_BUSY = 0x00000008, +GRBM_SE2_PERF_SEL_CB_CLEAN = 0x00000009, +GRBM_SE2_PERF_SEL_DB_CLEAN = 0x0000000a, +GRBM_SE2_PERF_SEL_RESERVED_0 = 0x0000000b, +GRBM_SE2_PERF_SEL_PA_BUSY = 0x0000000c, +GRBM_SE2_PERF_SEL_VGT_BUSY = 0x0000000d, +GRBM_SE2_PERF_SEL_BCI_BUSY = 0x0000000e, +GRBM_SE2_PERF_SEL_RMI_BUSY = 0x0000000f, +} GRBM_SE2_PERF_SEL; + +/* + * GRBM_SE3_PERF_SEL enum + */ + +typedef enum GRBM_SE3_PERF_SEL { +GRBM_SE3_PERF_SEL_COUNT = 0x00000000, +GRBM_SE3_PERF_SEL_USER_DEFINED = 0x00000001, +GRBM_SE3_PERF_SEL_CB_BUSY = 0x00000002, +GRBM_SE3_PERF_SEL_DB_BUSY = 0x00000003, +GRBM_SE3_PERF_SEL_SC_BUSY = 0x00000004, +GRBM_SE3_PERF_SEL_RESERVED_1 = 0x00000005, +GRBM_SE3_PERF_SEL_SPI_BUSY = 0x00000006, +GRBM_SE3_PERF_SEL_SX_BUSY = 0x00000007, +GRBM_SE3_PERF_SEL_TA_BUSY = 0x00000008, +GRBM_SE3_PERF_SEL_CB_CLEAN = 0x00000009, +GRBM_SE3_PERF_SEL_DB_CLEAN = 0x0000000a, +GRBM_SE3_PERF_SEL_RESERVED_0 = 0x0000000b, +GRBM_SE3_PERF_SEL_PA_BUSY = 0x0000000c, +GRBM_SE3_PERF_SEL_VGT_BUSY = 0x0000000d, +GRBM_SE3_PERF_SEL_BCI_BUSY = 0x0000000e, +GRBM_SE3_PERF_SEL_RMI_BUSY = 0x0000000f, +} GRBM_SE3_PERF_SEL; + +/******************************************************* + * CP Enums + *******************************************************/ + +/* + * CP_RING_ID enum + */ + +typedef enum CP_RING_ID { +RINGID0 = 0x00000000, +RINGID1 = 0x00000001, +RINGID2 = 0x00000002, +RINGID3 = 0x00000003, +} CP_RING_ID; + +/* + * CP_PIPE_ID enum + */ + +typedef enum CP_PIPE_ID { +PIPE_ID0 = 0x00000000, +PIPE_ID1 = 0x00000001, +PIPE_ID2 = 0x00000002, +PIPE_ID3 = 0x00000003, +} CP_PIPE_ID; + +/* + * CP_ME_ID enum + */ + +typedef enum CP_ME_ID { +ME_ID0 = 0x00000000, +ME_ID1 = 0x00000001, +ME_ID2 = 0x00000002, +ME_ID3 = 0x00000003, +} CP_ME_ID; + +/* + * SPM_PERFMON_STATE enum + */ + +typedef enum SPM_PERFMON_STATE { +STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000, +STRM_PERFMON_STATE_START_COUNTING = 0x00000001, +STRM_PERFMON_STATE_STOP_COUNTING = 0x00000002, +STRM_PERFMON_STATE_RESERVED_3 = 0x00000003, +STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004, +STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005, +} SPM_PERFMON_STATE; + +/* + * CP_PERFMON_STATE enum + */ + +typedef enum CP_PERFMON_STATE { +CP_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000, +CP_PERFMON_STATE_START_COUNTING = 0x00000001, +CP_PERFMON_STATE_STOP_COUNTING = 0x00000002, +CP_PERFMON_STATE_RESERVED_3 = 0x00000003, +CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004, +CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005, +} CP_PERFMON_STATE; + +/* + * CP_PERFMON_ENABLE_MODE enum + */ + +typedef enum CP_PERFMON_ENABLE_MODE { +CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x00000000, +CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x00000001, +CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002, +CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003, +} CP_PERFMON_ENABLE_MODE; + +/* + * CPG_PERFCOUNT_SEL enum + */ + +typedef enum CPG_PERFCOUNT_SEL { +CPG_PERF_SEL_ALWAYS_COUNT = 0x00000000, +CPG_PERF_SEL_RBIU_FIFO_FULL = 0x00000001, +CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x00000002, +CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 0x00000003, +CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x00000004, +CPG_PERF_SEL_ME_PARSER_BUSY = 0x00000005, +CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x00000006, +CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x00000007, +CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x00000008, +CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x00000009, +CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0x0000000a, +CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0x0000000b, +CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0x0000000c, +CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0x0000000d, +CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0x0000000e, +CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0x0000000f, +CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x00000010, +CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x00000011, +CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x00000012, +CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x00000013, +CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x00000014, +CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x00000015, +CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x00000016, +CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x00000017, +CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x00000018, +CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x00000019, +CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x0000001a, +CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x0000001b, +CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x0000001c, +CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x0000001d, +CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x0000001e, +CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x0000001f, +CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x00000020, +CPG_PERF_SEL_REGISTER_CLK_VALID = 0x00000021, +CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 0x00000022, +CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 0x00000023, +CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x00000024, +CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x00000025, +CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x00000026, +CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x00000027, +CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 0x00000028, +CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x00000029, +CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x0000002a, +CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x0000002b, +CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x0000002c, +CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x0000002d, +CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x0000002e, +CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x0000002f, +CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000030, +} CPG_PERFCOUNT_SEL; + +/* + * CPF_PERFCOUNT_SEL enum + */ + +typedef enum CPF_PERFCOUNT_SEL { +CPF_PERF_SEL_ALWAYS_COUNT = 0x00000000, +CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x00000001, +CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x00000002, +CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x00000003, +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x00000004, +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x00000005, +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x00000006, +CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x00000007, +CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x00000008, +CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 0x00000009, +CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0x0000000a, +CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x0000000b, +CPF_PERF_SEL_GRBM_DWORDS_SENT = 0x0000000c, +CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0x0000000d, +CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0x0000000e, +CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 0x0000000f, +CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 0x00000010, +CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000011, +CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000012, +CPF_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000013, +CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000014, +} CPF_PERFCOUNT_SEL; + +/* + * CPC_PERFCOUNT_SEL enum + */ + +typedef enum CPC_PERFCOUNT_SEL { +CPC_PERF_SEL_ALWAYS_COUNT = 0x00000000, +CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000001, +CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x00000002, +CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 0x00000003, +CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 0x00000004, +CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x00000005, +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x00000006, +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x00000007, +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x00000008, +CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 0x00000009, +CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0x0000000a, +CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0x0000000b, +CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0x0000000c, +CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0x0000000d, +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0x0000000e, +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0x0000000f, +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x00000010, +CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 0x00000011, +CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 0x00000012, +CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x00000013, +CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x00000014, +CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x00000015, +CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000016, +CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000017, +CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000018, +} CPC_PERFCOUNT_SEL; + +/* + * CP_ALPHA_TAG_RAM_SEL enum + */ + +typedef enum CP_ALPHA_TAG_RAM_SEL { +CPG_TAG_RAM = 0x00000000, +CPC_TAG_RAM = 0x00000001, +CPF_TAG_RAM = 0x00000002, +RSV_TAG_RAM = 0x00000003, +} CP_ALPHA_TAG_RAM_SEL; + +/* + * SEM_RESPONSE value + */ + +#define SEM_ECC_ERROR 0x00000000 +#define SEM_TRANS_ERROR 0x00000001 +#define SEM_FAILED 0x00000002 +#define SEM_PASSED 0x00000003 + +/* + * IQ_RETRY_TYPE value + */ + +#define IQ_QUEUE_SLEEP 0x00000000 +#define IQ_OFFLOAD_RETRY 0x00000001 +#define IQ_SCH_WAVE_MSG 0x00000002 +#define IQ_SEM_REARM 0x00000003 +#define IQ_DEQUEUE_RETRY 0x00000004 + +/* + * IQ_INTR_TYPE value + */ + +#define IQ_INTR_TYPE_PQ 0x00000000 +#define IQ_INTR_TYPE_IB 0x00000001 +#define IQ_INTR_TYPE_MQD 0x00000002 + +/* + * VMID_SIZE value + */ + +#define VMID_SZ 0x00000004 + +/* + * CONFIG_SPACE value + */ + +#define CONFIG_SPACE_START 0x00002000 +#define CONFIG_SPACE_END 0x00009fff + +/* + * CONFIG_SPACE1 value + */ + +#define CONFIG_SPACE1_START 0x00002000 +#define CONFIG_SPACE1_END 0x00002bff + +/* + * CONFIG_SPACE2 value + */ + +#define CONFIG_SPACE2_START 0x00003000 +#define CONFIG_SPACE2_END 0x00009fff + +/* + * UCONFIG_SPACE value + */ + +#define UCONFIG_SPACE_START 0x0000c000 +#define UCONFIG_SPACE_END 0x0000ffff + +/* + * PERSISTENT_SPACE value + */ + +#define PERSISTENT_SPACE_START 0x00002c00 +#define PERSISTENT_SPACE_END 0x00002fff + +/* + * CONTEXT_SPACE value + */ + +#define CONTEXT_SPACE_START 0x0000a000 +#define CONTEXT_SPACE_END 0x0000bfff + +/******************************************************* + * SQ_UC Enums + *******************************************************/ + +/* + * VALUE_SQ_ENC_SOP1 value + */ + +#define SQ_ENC_SOP1_BITS 0xbe800000 +#define SQ_ENC_SOP1_MASK 0xff800000 +#define SQ_ENC_SOP1_FIELD 0x0000017d + +/* + * VALUE_SQ_ENC_SOPC value + */ + +#define SQ_ENC_SOPC_BITS 0xbf000000 +#define SQ_ENC_SOPC_MASK 0xff800000 +#define SQ_ENC_SOPC_FIELD 0x0000017e + +/* + * VALUE_SQ_ENC_SOPP value + */ + +#define SQ_ENC_SOPP_BITS 0xbf800000 +#define SQ_ENC_SOPP_MASK 0xff800000 +#define SQ_ENC_SOPP_FIELD 0x0000017f + +/* + * VALUE_SQ_ENC_SOPK value + */ + +#define SQ_ENC_SOPK_BITS 0xb0000000 +#define SQ_ENC_SOPK_MASK 0xf0000000 +#define SQ_ENC_SOPK_FIELD 0x0000000b + +/* + * VALUE_SQ_ENC_SOP2 value + */ + +#define SQ_ENC_SOP2_BITS 0x80000000 +#define SQ_ENC_SOP2_MASK 0xc0000000 +#define SQ_ENC_SOP2_FIELD 0x00000002 + +/* + * VALUE_SQ_ENC_SMEM value + */ + +#define SQ_ENC_SMEM_BITS 0xc0000000 +#define SQ_ENC_SMEM_MASK 0xfc000000 +#define SQ_ENC_SMEM_FIELD 0x00000030 + +/* + * VALUE_SQ_ENC_VOP1 value + */ + +#define SQ_ENC_VOP1_BITS 0x7e000000 +#define SQ_ENC_VOP1_MASK 0xfe000000 +#define SQ_ENC_VOP1_FIELD 0x0000003f + +/* + * VALUE_SQ_ENC_VOPC value + */ + +#define SQ_ENC_VOPC_BITS 0x7c000000 +#define SQ_ENC_VOPC_MASK 0xfe000000 +#define SQ_ENC_VOPC_FIELD 0x0000003e + +/* + * VALUE_SQ_ENC_VOP2 value + */ + +#define SQ_ENC_VOP2_BITS 0x00000000 +#define SQ_ENC_VOP2_MASK 0x80000000 +#define SQ_ENC_VOP2_FIELD 0x00000000 + +/* + * VALUE_SQ_ENC_VINTRP value + */ + +#define SQ_ENC_VINTRP_BITS 0xd4000000 +#define SQ_ENC_VINTRP_MASK 0xfc000000 +#define SQ_ENC_VINTRP_FIELD 0x00000035 + +/* + * VALUE_SQ_ENC_VOP3P value + */ + +#define SQ_ENC_VOP3P_BITS 0xd3800000 +#define SQ_ENC_VOP3P_MASK 0xff800000 +#define SQ_ENC_VOP3P_FIELD 0x000001a7 + +/* + * VALUE_SQ_ENC_VOP3 value + */ + +#define SQ_ENC_VOP3_BITS 0xd0000000 +#define SQ_ENC_VOP3_MASK 0xfc000000 +#define SQ_ENC_VOP3_FIELD 0x00000034 + +/* + * VALUE_SQ_ENC_DS value + */ + +#define SQ_ENC_DS_BITS 0xd8000000 +#define SQ_ENC_DS_MASK 0xfc000000 +#define SQ_ENC_DS_FIELD 0x00000036 + +/* + * VALUE_SQ_ENC_MUBUF value + */ + +#define SQ_ENC_MUBUF_BITS 0xe0000000 +#define SQ_ENC_MUBUF_MASK 0xfc000000 +#define SQ_ENC_MUBUF_FIELD 0x00000038 + +/* + * VALUE_SQ_ENC_MTBUF value + */ + +#define SQ_ENC_MTBUF_BITS 0xe8000000 +#define SQ_ENC_MTBUF_MASK 0xfc000000 +#define SQ_ENC_MTBUF_FIELD 0x0000003a + +/* + * VALUE_SQ_ENC_MIMG value + */ + +#define SQ_ENC_MIMG_BITS 0xf0000000 +#define SQ_ENC_MIMG_MASK 0xfc000000 +#define SQ_ENC_MIMG_FIELD 0x0000003c + +/* + * VALUE_SQ_ENC_EXP value + */ + +#define SQ_ENC_EXP_BITS 0xc4000000 +#define SQ_ENC_EXP_MASK 0xfc000000 +#define SQ_ENC_EXP_FIELD 0x00000031 + +/* + * VALUE_SQ_ENC_FLAT value + */ + +#define SQ_ENC_FLAT_BITS 0xdc000000 +#define SQ_ENC_FLAT_MASK 0xfc000000 +#define SQ_ENC_FLAT_FIELD 0x00000037 + +/* + * VALUE_SQ_V_OP3_INTRP_COUNT value + */ + +#define SQ_V_OP3_INTRP_COUNT 0x0000000c + +/* + * VALUE_SQ_SENDMSG_SYSTEM_SIZE value + */ + +#define SQ_SENDMSG_SYSTEM_SIZE 0x00000003 + +/* + * VALUE_SQ_HWREG_ID_SIZE value + */ + +#define SQ_HWREG_ID_SIZE 0x00000006 + +/* + * VALUE_SQ_V_OPC_COUNT value + */ + +#define SQ_V_OPC_COUNT 0x00000100 + +/* + * VALUE_SQ_NUM_VGPR value + */ + +#define SQ_NUM_VGPR 0x00000100 + +/* + * VALUE_SQ_WAITCNT_LGKM_SHIFT value + */ + +#define SQ_WAITCNT_LGKM_SHIFT 0x00000008 + +/* + * VALUE_SQ_HWREG_ID_SHIFT value + */ + +#define SQ_HWREG_ID_SHIFT 0x00000000 + +/* + * VALUE_SQ_EXP_NUM_POS value + */ + +#define SQ_EXP_NUM_POS 0x00000004 + +/* + * VALUE_SQ_XLATE_VOP3_TO_VOPC_OFFSET value + */ + +#define SQ_XLATE_VOP3_TO_VOPC_OFFSET 0x00000000 + +/* + * VALUE_SQ_V_OP3_2IN_OFFSET value + */ + +#define SQ_V_OP3_2IN_OFFSET 0x00000280 + +/* + * VALUE_SQ_XLATE_VOP3_TO_VOP2_OFFSET value + */ + +#define SQ_XLATE_VOP3_TO_VOP2_OFFSET 0x00000100 + +/* + * VALUE_SQ_EXP_NUM_MRT value + */ + +#define SQ_EXP_NUM_MRT 0x00000008 + +/* + * VALUE_SQ_NUM_TTMP value + */ + +#define SQ_NUM_TTMP 0x00000010 + +/* + * VALUE_SQ_SENDMSG_STREAMID_SHIFT value + */ + +#define SQ_SENDMSG_STREAMID_SHIFT 0x00000008 + +/* + * VALUE_SQ_V_OP1_COUNT value + */ + +#define SQ_V_OP1_COUNT 0x00000080 + +/* + * VALUE_SQ_WAITCNT_LGKM_SIZE value + */ + +#define SQ_WAITCNT_LGKM_SIZE 0x00000004 + +/* + * VALUE_SQ_XLATE_VOP3_TO_VOPC_COUNT value + */ + +#define SQ_XLATE_VOP3_TO_VOPC_COUNT 0x00000100 + +/* + * VALUE_SQ_SENDMSG_MSG_SHIFT value + */ + +#define SQ_SENDMSG_MSG_SHIFT 0x00000000 + +/* + * VALUE_SQ_V_OP3_3IN_OFFSET value + */ + +#define SQ_V_OP3_3IN_OFFSET 0x000001c0 + +/* + * VALUE_SQ_HWREG_OFFSET_SHIFT value + */ + +#define SQ_HWREG_OFFSET_SHIFT 0x00000006 + +/* + * VALUE_SQ_HWREG_SIZE_SHIFT value + */ + +#define SQ_HWREG_SIZE_SHIFT 0x0000000b + +/* + * VALUE_SQ_HWREG_OFFSET_SIZE value + */ + +#define SQ_HWREG_OFFSET_SIZE 0x00000005 + +/* + * VALUE_SQ_V_OP3_3IN_COUNT value + */ + +#define SQ_V_OP3_3IN_COUNT 0x000000b0 + +/* + * VALUE_SQ_SENDMSG_MSG_SIZE value + */ + +#define SQ_SENDMSG_MSG_SIZE 0x00000004 + +/* + * VALUE_SQ_XLATE_VOP3_TO_VOP1_COUNT value + */ + +#define SQ_XLATE_VOP3_TO_VOP1_COUNT 0x00000080 + +/* + * VALUE_SQ_EXP_NUM_GDS value + */ + +#define SQ_EXP_NUM_GDS 0x00000005 + +/* + * VALUE_SQ_V_OP2_COUNT value + */ + +#define SQ_V_OP2_COUNT 0x00000040 + +/* + * VALUE_SQ_SENDMSG_GSOP_SIZE value + */ + +#define SQ_SENDMSG_GSOP_SIZE 0x00000002 + +/* + * VALUE_SQ_WAITCNT_VM_SHIFT value + */ + +#define SQ_WAITCNT_VM_SHIFT 0x00000000 + +/* + * VALUE_SQ_XLATE_VOP3_TO_VOP3P_COUNT value + */ + +#define SQ_XLATE_VOP3_TO_VOP3P_COUNT 0x00000080 + +/* + * VALUE_SQ_V_OP3_2IN_COUNT value + */ + +#define SQ_V_OP3_2IN_COUNT 0x00000080 + +/* + * VALUE_SQ_SENDMSG_SYSTEM_SHIFT value + */ + +#define SQ_SENDMSG_SYSTEM_SHIFT 0x00000004 + +/* + * VALUE_SQ_WAITCNT_VM_SIZE value + */ + +#define SQ_WAITCNT_VM_SIZE 0x00000004 + +/* + * VALUE_SQ_XLATE_VOP3_TO_VOP3P_OFFSET value + */ + +#define SQ_XLATE_VOP3_TO_VOP3P_OFFSET 0x00000380 + +/* + * VALUE_SQ_WAITCNT_EXP_SHIFT value + */ + +#define SQ_WAITCNT_EXP_SHIFT 0x00000004 + +/* + * VALUE_SQ_XLATE_VOP3_TO_VOP2_COUNT value + */ + +#define SQ_XLATE_VOP3_TO_VOP2_COUNT 0x00000040 + +/* + * VALUE_SQ_EXP_NUM_PARAM value + */ + +#define SQ_EXP_NUM_PARAM 0x00000020 + +/* + * VALUE_SQ_HWREG_SIZE_SIZE value + */ + +#define SQ_HWREG_SIZE_SIZE 0x00000005 + +/* + * VALUE_SQ_WAITCNT_EXP_SIZE value + */ + +#define SQ_WAITCNT_EXP_SIZE 0x00000003 + +/* + * VALUE_SQ_V_OP3_INTRP_OFFSET value + */ + +#define SQ_V_OP3_INTRP_OFFSET 0x00000274 + +/* + * VALUE_SQ_SENDMSG_GSOP_SHIFT value + */ + +#define SQ_SENDMSG_GSOP_SHIFT 0x00000004 + +/* + * VALUE_SQ_XLATE_VOP3_TO_VINTRP_OFFSET value + */ + +#define SQ_XLATE_VOP3_TO_VINTRP_OFFSET 0x00000270 + +/* + * VALUE_SQ_NUM_ATTR value + */ + +#define SQ_NUM_ATTR 0x00000021 + +/* + * VALUE_SQ_NUM_SGPR value + */ + +#define SQ_NUM_SGPR 0x00000066 + +/* + * VALUE_SQ_SRC_VGPR_BIT value + */ + +#define SQ_SRC_VGPR_BIT 0x00000100 + +/* + * VALUE_SQ_V_INTRP_COUNT value + */ + +#define SQ_V_INTRP_COUNT 0x00000004 + +/* + * VALUE_SQ_SENDMSG_STREAMID_SIZE value + */ + +#define SQ_SENDMSG_STREAMID_SIZE 0x00000002 + +/* + * VALUE_SQ_V_OP3P_COUNT value + */ + +#define SQ_V_OP3P_COUNT 0x00000080 + +/* + * VALUE_SQ_XLATE_VOP3_TO_VOP1_OFFSET value + */ + +#define SQ_XLATE_VOP3_TO_VOP1_OFFSET 0x00000140 + +/* + * VALUE_SQ_XLATE_VOP3_TO_VINTRP_COUNT value + */ + +#define SQ_XLATE_VOP3_TO_VINTRP_COUNT 0x00000004 + +/* + * VALUE_SQ_SSRC_SPECIAL_DPP value + */ + +#define SQ_SRC_DPP 0x000000fa + +/* + * VALUE_SQ_OP_MTBUF value + */ + +#define SQ_TBUFFER_LOAD_FORMAT_X 0x00000000 +#define SQ_TBUFFER_LOAD_FORMAT_XY 0x00000001 +#define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x00000002 +#define SQ_TBUFFER_LOAD_FORMAT_XYZW 0x00000003 +#define SQ_TBUFFER_STORE_FORMAT_X 0x00000004 +#define SQ_TBUFFER_STORE_FORMAT_XY 0x00000005 +#define SQ_TBUFFER_STORE_FORMAT_XYZ 0x00000006 +#define SQ_TBUFFER_STORE_FORMAT_XYZW 0x00000007 +#define SQ_TBUFFER_LOAD_FORMAT_D16_X 0x00000008 +#define SQ_TBUFFER_LOAD_FORMAT_D16_XY 0x00000009 +#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ 0x0000000a +#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW 0x0000000b +#define SQ_TBUFFER_STORE_FORMAT_D16_X 0x0000000c +#define SQ_TBUFFER_STORE_FORMAT_D16_XY 0x0000000d +#define SQ_TBUFFER_STORE_FORMAT_D16_XYZ 0x0000000e +#define SQ_TBUFFER_STORE_FORMAT_D16_XYZW 0x0000000f + +/* + * VALUE_SQ_OP_FLAT_GLBL value + */ + +#define SQ_GLOBAL_LOAD_UBYTE 0x00000010 +#define SQ_GLOBAL_LOAD_SBYTE 0x00000011 +#define SQ_GLOBAL_LOAD_USHORT 0x00000012 +#define SQ_GLOBAL_LOAD_SSHORT 0x00000013 +#define SQ_GLOBAL_LOAD_DWORD 0x00000014 +#define SQ_GLOBAL_LOAD_DWORDX2 0x00000015 +#define SQ_GLOBAL_LOAD_DWORDX3 0x00000016 +#define SQ_GLOBAL_LOAD_DWORDX4 0x00000017 +#define SQ_GLOBAL_STORE_BYTE 0x00000018 +#define SQ_GLOBAL_STORE_SHORT 0x0000001a +#define SQ_GLOBAL_STORE_DWORD 0x0000001c +#define SQ_GLOBAL_STORE_DWORDX2 0x0000001d +#define SQ_GLOBAL_STORE_DWORDX3 0x0000001e +#define SQ_GLOBAL_STORE_DWORDX4 0x0000001f +#define SQ_GLOBAL_ATOMIC_SWAP 0x00000040 +#define SQ_GLOBAL_ATOMIC_CMPSWAP 0x00000041 +#define SQ_GLOBAL_ATOMIC_ADD 0x00000042 +#define SQ_GLOBAL_ATOMIC_SUB 0x00000043 +#define SQ_GLOBAL_ATOMIC_SMIN 0x00000044 +#define SQ_GLOBAL_ATOMIC_UMIN 0x00000045 +#define SQ_GLOBAL_ATOMIC_SMAX 0x00000046 +#define SQ_GLOBAL_ATOMIC_UMAX 0x00000047 +#define SQ_GLOBAL_ATOMIC_AND 0x00000048 +#define SQ_GLOBAL_ATOMIC_OR 0x00000049 +#define SQ_GLOBAL_ATOMIC_XOR 0x0000004a +#define SQ_GLOBAL_ATOMIC_INC 0x0000004b +#define SQ_GLOBAL_ATOMIC_DEC 0x0000004c +#define SQ_GLOBAL_ATOMIC_SWAP_X2 0x00000060 +#define SQ_GLOBAL_ATOMIC_CMPSWAP_X2 0x00000061 +#define SQ_GLOBAL_ATOMIC_ADD_X2 0x00000062 +#define SQ_GLOBAL_ATOMIC_SUB_X2 0x00000063 +#define SQ_GLOBAL_ATOMIC_SMIN_X2 0x00000064 +#define SQ_GLOBAL_ATOMIC_UMIN_X2 0x00000065 +#define SQ_GLOBAL_ATOMIC_SMAX_X2 0x00000066 +#define SQ_GLOBAL_ATOMIC_UMAX_X2 0x00000067 +#define SQ_GLOBAL_ATOMIC_AND_X2 0x00000068 +#define SQ_GLOBAL_ATOMIC_OR_X2 0x00000069 +#define SQ_GLOBAL_ATOMIC_XOR_X2 0x0000006a +#define SQ_GLOBAL_ATOMIC_INC_X2 0x0000006b +#define SQ_GLOBAL_ATOMIC_DEC_X2 0x0000006c + +/* + * VALUE_SQ_VGPR value + */ + +#define SQ_VGPR0 0x00000000 + +/* + * VALUE_SQ_OP_FLAT_SCRATCH value + */ + +#define SQ_SCRATCH_LOAD_UBYTE 0x00000010 +#define SQ_SCRATCH_LOAD_SBYTE 0x00000011 +#define SQ_SCRATCH_LOAD_USHORT 0x00000012 +#define SQ_SCRATCH_LOAD_SSHORT 0x00000013 +#define SQ_SCRATCH_LOAD_DWORD 0x00000014 +#define SQ_SCRATCH_LOAD_DWORDX2 0x00000015 +#define SQ_SCRATCH_LOAD_DWORDX3 0x00000016 +#define SQ_SCRATCH_LOAD_DWORDX4 0x00000017 +#define SQ_SCRATCH_STORE_BYTE 0x00000018 +#define SQ_SCRATCH_STORE_SHORT 0x0000001a +#define SQ_SCRATCH_STORE_DWORD 0x0000001c +#define SQ_SCRATCH_STORE_DWORDX2 0x0000001d +#define SQ_SCRATCH_STORE_DWORDX3 0x0000001e +#define SQ_SCRATCH_STORE_DWORDX4 0x0000001f + +/* + * VALUE_SQ_VCC value + */ + +#define SQ_VCC_ALL 0x00000000 + +/* + * VALUE_SQ_SSRC_0_63_INLINES value + */ + +#define SQ_SRC_0 0x00000080 +#define SQ_SRC_1_INT 0x00000081 +#define SQ_SRC_2_INT 0x00000082 +#define SQ_SRC_3_INT 0x00000083 +#define SQ_SRC_4_INT 0x00000084 +#define SQ_SRC_5_INT 0x00000085 +#define SQ_SRC_6_INT 0x00000086 +#define SQ_SRC_7_INT 0x00000087 +#define SQ_SRC_8_INT 0x00000088 +#define SQ_SRC_9_INT 0x00000089 +#define SQ_SRC_10_INT 0x0000008a +#define SQ_SRC_11_INT 0x0000008b +#define SQ_SRC_12_INT 0x0000008c +#define SQ_SRC_13_INT 0x0000008d +#define SQ_SRC_14_INT 0x0000008e +#define SQ_SRC_15_INT 0x0000008f +#define SQ_SRC_16_INT 0x00000090 +#define SQ_SRC_17_INT 0x00000091 +#define SQ_SRC_18_INT 0x00000092 +#define SQ_SRC_19_INT 0x00000093 +#define SQ_SRC_20_INT 0x00000094 +#define SQ_SRC_21_INT 0x00000095 +#define SQ_SRC_22_INT 0x00000096 +#define SQ_SRC_23_INT 0x00000097 +#define SQ_SRC_24_INT 0x00000098 +#define SQ_SRC_25_INT 0x00000099 +#define SQ_SRC_26_INT 0x0000009a +#define SQ_SRC_27_INT 0x0000009b +#define SQ_SRC_28_INT 0x0000009c +#define SQ_SRC_29_INT 0x0000009d +#define SQ_SRC_30_INT 0x0000009e +#define SQ_SRC_31_INT 0x0000009f +#define SQ_SRC_32_INT 0x000000a0 +#define SQ_SRC_33_INT 0x000000a1 +#define SQ_SRC_34_INT 0x000000a2 +#define SQ_SRC_35_INT 0x000000a3 +#define SQ_SRC_36_INT 0x000000a4 +#define SQ_SRC_37_INT 0x000000a5 +#define SQ_SRC_38_INT 0x000000a6 +#define SQ_SRC_39_INT 0x000000a7 +#define SQ_SRC_40_INT 0x000000a8 +#define SQ_SRC_41_INT 0x000000a9 +#define SQ_SRC_42_INT 0x000000aa +#define SQ_SRC_43_INT 0x000000ab +#define SQ_SRC_44_INT 0x000000ac +#define SQ_SRC_45_INT 0x000000ad +#define SQ_SRC_46_INT 0x000000ae +#define SQ_SRC_47_INT 0x000000af +#define SQ_SRC_48_INT 0x000000b0 +#define SQ_SRC_49_INT 0x000000b1 +#define SQ_SRC_50_INT 0x000000b2 +#define SQ_SRC_51_INT 0x000000b3 +#define SQ_SRC_52_INT 0x000000b4 +#define SQ_SRC_53_INT 0x000000b5 +#define SQ_SRC_54_INT 0x000000b6 +#define SQ_SRC_55_INT 0x000000b7 +#define SQ_SRC_56_INT 0x000000b8 +#define SQ_SRC_57_INT 0x000000b9 +#define SQ_SRC_58_INT 0x000000ba +#define SQ_SRC_59_INT 0x000000bb +#define SQ_SRC_60_INT 0x000000bc +#define SQ_SRC_61_INT 0x000000bd +#define SQ_SRC_62_INT 0x000000be +#define SQ_SRC_63_INT 0x000000bf + +/* + * VALUE_SQ_OP_MIMG value + */ + +#define SQ_IMAGE_LOAD 0x00000000 +#define SQ_IMAGE_LOAD_MIP 0x00000001 +#define SQ_IMAGE_LOAD_PCK 0x00000002 +#define SQ_IMAGE_LOAD_PCK_SGN 0x00000003 +#define SQ_IMAGE_LOAD_MIP_PCK 0x00000004 +#define SQ_IMAGE_LOAD_MIP_PCK_SGN 0x00000005 +#define SQ_IMAGE_STORE 0x00000008 +#define SQ_IMAGE_STORE_MIP 0x00000009 +#define SQ_IMAGE_STORE_PCK 0x0000000a +#define SQ_IMAGE_STORE_MIP_PCK 0x0000000b +#define SQ_IMAGE_GET_RESINFO 0x0000000e +#define SQ_IMAGE_ATOMIC_SWAP 0x00000010 +#define SQ_IMAGE_ATOMIC_CMPSWAP 0x00000011 +#define SQ_IMAGE_ATOMIC_ADD 0x00000012 +#define SQ_IMAGE_ATOMIC_SUB 0x00000013 +#define SQ_IMAGE_ATOMIC_SMIN 0x00000014 +#define SQ_IMAGE_ATOMIC_UMIN 0x00000015 +#define SQ_IMAGE_ATOMIC_SMAX 0x00000016 +#define SQ_IMAGE_ATOMIC_UMAX 0x00000017 +#define SQ_IMAGE_ATOMIC_AND 0x00000018 +#define SQ_IMAGE_ATOMIC_OR 0x00000019 +#define SQ_IMAGE_ATOMIC_XOR 0x0000001a +#define SQ_IMAGE_ATOMIC_INC 0x0000001b +#define SQ_IMAGE_ATOMIC_DEC 0x0000001c +#define SQ_IMAGE_SAMPLE 0x00000020 +#define SQ_IMAGE_SAMPLE_CL 0x00000021 +#define SQ_IMAGE_SAMPLE_D 0x00000022 +#define SQ_IMAGE_SAMPLE_D_CL 0x00000023 +#define SQ_IMAGE_SAMPLE_L 0x00000024 +#define SQ_IMAGE_SAMPLE_B 0x00000025 +#define SQ_IMAGE_SAMPLE_B_CL 0x00000026 +#define SQ_IMAGE_SAMPLE_LZ 0x00000027 +#define SQ_IMAGE_SAMPLE_C 0x00000028 +#define SQ_IMAGE_SAMPLE_C_CL 0x00000029 +#define SQ_IMAGE_SAMPLE_C_D 0x0000002a +#define SQ_IMAGE_SAMPLE_C_D_CL 0x0000002b +#define SQ_IMAGE_SAMPLE_C_L 0x0000002c +#define SQ_IMAGE_SAMPLE_C_B 0x0000002d +#define SQ_IMAGE_SAMPLE_C_B_CL 0x0000002e +#define SQ_IMAGE_SAMPLE_C_LZ 0x0000002f +#define SQ_IMAGE_SAMPLE_O 0x00000030 +#define SQ_IMAGE_SAMPLE_CL_O 0x00000031 +#define SQ_IMAGE_SAMPLE_D_O 0x00000032 +#define SQ_IMAGE_SAMPLE_D_CL_O 0x00000033 +#define SQ_IMAGE_SAMPLE_L_O 0x00000034 +#define SQ_IMAGE_SAMPLE_B_O 0x00000035 +#define SQ_IMAGE_SAMPLE_B_CL_O 0x00000036 +#define SQ_IMAGE_SAMPLE_LZ_O 0x00000037 +#define SQ_IMAGE_SAMPLE_C_O 0x00000038 +#define SQ_IMAGE_SAMPLE_C_CL_O 0x00000039 +#define SQ_IMAGE_SAMPLE_C_D_O 0x0000003a +#define SQ_IMAGE_SAMPLE_C_D_CL_O 0x0000003b +#define SQ_IMAGE_SAMPLE_C_L_O 0x0000003c +#define SQ_IMAGE_SAMPLE_C_B_O 0x0000003d +#define SQ_IMAGE_SAMPLE_C_B_CL_O 0x0000003e +#define SQ_IMAGE_SAMPLE_C_LZ_O 0x0000003f +#define SQ_IMAGE_GATHER4 0x00000040 +#define SQ_IMAGE_GATHER4_CL 0x00000041 +#define SQ_IMAGE_GATHER4H 0x00000042 +#define SQ_IMAGE_GATHER4_L 0x00000044 +#define SQ_IMAGE_GATHER4_B 0x00000045 +#define SQ_IMAGE_GATHER4_B_CL 0x00000046 +#define SQ_IMAGE_GATHER4_LZ 0x00000047 +#define SQ_IMAGE_GATHER4_C 0x00000048 +#define SQ_IMAGE_GATHER4_C_CL 0x00000049 +#define SQ_IMAGE_GATHER4H_PCK 0x0000004a +#define SQ_IMAGE_GATHER8H_PCK 0x0000004b +#define SQ_IMAGE_GATHER4_C_L 0x0000004c +#define SQ_IMAGE_GATHER4_C_B 0x0000004d +#define SQ_IMAGE_GATHER4_C_B_CL 0x0000004e +#define SQ_IMAGE_GATHER4_C_LZ 0x0000004f +#define SQ_IMAGE_GATHER4_O 0x00000050 +#define SQ_IMAGE_GATHER4_CL_O 0x00000051 +#define SQ_IMAGE_GATHER4_L_O 0x00000054 +#define SQ_IMAGE_GATHER4_B_O 0x00000055 +#define SQ_IMAGE_GATHER4_B_CL_O 0x00000056 +#define SQ_IMAGE_GATHER4_LZ_O 0x00000057 +#define SQ_IMAGE_GATHER4_C_O 0x00000058 +#define SQ_IMAGE_GATHER4_C_CL_O 0x00000059 +#define SQ_IMAGE_GATHER4_C_L_O 0x0000005c +#define SQ_IMAGE_GATHER4_C_B_O 0x0000005d +#define SQ_IMAGE_GATHER4_C_B_CL_O 0x0000005e +#define SQ_IMAGE_GATHER4_C_LZ_O 0x0000005f +#define SQ_IMAGE_GET_LOD 0x00000060 +#define SQ_IMAGE_SAMPLE_CD 0x00000068 +#define SQ_IMAGE_SAMPLE_CD_CL 0x00000069 +#define SQ_IMAGE_SAMPLE_C_CD 0x0000006a +#define SQ_IMAGE_SAMPLE_C_CD_CL 0x0000006b +#define SQ_IMAGE_SAMPLE_CD_O 0x0000006c +#define SQ_IMAGE_SAMPLE_CD_CL_O 0x0000006d +#define SQ_IMAGE_SAMPLE_C_CD_O 0x0000006e +#define SQ_IMAGE_SAMPLE_C_CD_CL_O 0x0000006f +#define SQ_IMAGE_RSRC256 0x0000007e +#define SQ_IMAGE_SAMPLER 0x0000007f + +/* + * VALUE_SQ_HW_REG value + */ + +#define SQ_HW_REG_MODE 0x00000001 +#define SQ_HW_REG_STATUS 0x00000002 +#define SQ_HW_REG_TRAPSTS 0x00000003 +#define SQ_HW_REG_HW_ID 0x00000004 +#define SQ_HW_REG_GPR_ALLOC 0x00000005 +#define SQ_HW_REG_LDS_ALLOC 0x00000006 +#define SQ_HW_REG_IB_STS 0x00000007 +#define SQ_HW_REG_PC_LO 0x00000008 +#define SQ_HW_REG_PC_HI 0x00000009 +#define SQ_HW_REG_INST_DW0 0x0000000a +#define SQ_HW_REG_INST_DW1 0x0000000b +#define SQ_HW_REG_IB_DBG0 0x0000000c +#define SQ_HW_REG_IB_DBG1 0x0000000d +#define SQ_HW_REG_FLUSH_IB 0x0000000e +#define SQ_HW_REG_SH_MEM_BASES 0x0000000f +#define SQ_HW_REG_SQ_SHADER_TBA_LO 0x00000010 +#define SQ_HW_REG_SQ_SHADER_TBA_HI 0x00000011 +#define SQ_HW_REG_SQ_SHADER_TMA_LO 0x00000012 +#define SQ_HW_REG_SQ_SHADER_TMA_HI 0x00000013 + +/* + * VALUE_SQ_OP_SOP1 value + */ + +#define SQ_S_MOV_B32 0x00000000 +#define SQ_S_MOV_B64 0x00000001 +#define SQ_S_CMOV_B32 0x00000002 +#define SQ_S_CMOV_B64 0x00000003 +#define SQ_S_NOT_B32 0x00000004 +#define SQ_S_NOT_B64 0x00000005 +#define SQ_S_WQM_B32 0x00000006 +#define SQ_S_WQM_B64 0x00000007 +#define SQ_S_BREV_B32 0x00000008 +#define SQ_S_BREV_B64 0x00000009 +#define SQ_S_BCNT0_I32_B32 0x0000000a +#define SQ_S_BCNT0_I32_B64 0x0000000b +#define SQ_S_BCNT1_I32_B32 0x0000000c +#define SQ_S_BCNT1_I32_B64 0x0000000d +#define SQ_S_FF0_I32_B32 0x0000000e +#define SQ_S_FF0_I32_B64 0x0000000f +#define SQ_S_FF1_I32_B32 0x00000010 +#define SQ_S_FF1_I32_B64 0x00000011 +#define SQ_S_FLBIT_I32_B32 0x00000012 +#define SQ_S_FLBIT_I32_B64 0x00000013 +#define SQ_S_FLBIT_I32 0x00000014 +#define SQ_S_FLBIT_I32_I64 0x00000015 +#define SQ_S_SEXT_I32_I8 0x00000016 +#define SQ_S_SEXT_I32_I16 0x00000017 +#define SQ_S_BITSET0_B32 0x00000018 +#define SQ_S_BITSET0_B64 0x00000019 +#define SQ_S_BITSET1_B32 0x0000001a +#define SQ_S_BITSET1_B64 0x0000001b +#define SQ_S_GETPC_B64 0x0000001c +#define SQ_S_SETPC_B64 0x0000001d +#define SQ_S_SWAPPC_B64 0x0000001e +#define SQ_S_RFE_B64 0x0000001f +#define SQ_S_AND_SAVEEXEC_B64 0x00000020 +#define SQ_S_OR_SAVEEXEC_B64 0x00000021 +#define SQ_S_XOR_SAVEEXEC_B64 0x00000022 +#define SQ_S_ANDN2_SAVEEXEC_B64 0x00000023 +#define SQ_S_ORN2_SAVEEXEC_B64 0x00000024 +#define SQ_S_NAND_SAVEEXEC_B64 0x00000025 +#define SQ_S_NOR_SAVEEXEC_B64 0x00000026 +#define SQ_S_XNOR_SAVEEXEC_B64 0x00000027 +#define SQ_S_QUADMASK_B32 0x00000028 +#define SQ_S_QUADMASK_B64 0x00000029 +#define SQ_S_MOVRELS_B32 0x0000002a +#define SQ_S_MOVRELS_B64 0x0000002b +#define SQ_S_MOVRELD_B32 0x0000002c +#define SQ_S_MOVRELD_B64 0x0000002d +#define SQ_S_CBRANCH_JOIN 0x0000002e +#define SQ_S_MOV_REGRD_B32 0x0000002f +#define SQ_S_ABS_I32 0x00000030 +#define SQ_S_MOV_FED_B32 0x00000031 +#define SQ_S_SET_GPR_IDX_IDX 0x00000032 +#define SQ_S_ANDN1_SAVEEXEC_B64 0x00000033 +#define SQ_S_ORN1_SAVEEXEC_B64 0x00000034 +#define SQ_S_ANDN1_WREXEC_B64 0x00000035 +#define SQ_S_ANDN2_WREXEC_B64 0x00000036 +#define SQ_S_BITREPLICATE_B64_B32 0x00000037 + +/* + * VALUE_SQ_CNT value + */ + +#define SQ_CNT1 0x00000000 +#define SQ_CNT2 0x00000001 +#define SQ_CNT3 0x00000002 +#define SQ_CNT4 0x00000003 + +/* + * VALUE_SQ_OP_VOP3 value + */ + +#define SQ_V_MAD_LEGACY_F32 0x000001c0 +#define SQ_V_MAD_F32 0x000001c1 +#define SQ_V_MAD_I32_I24 0x000001c2 +#define SQ_V_MAD_U32_U24 0x000001c3 +#define SQ_V_CUBEID_F32 0x000001c4 +#define SQ_V_CUBESC_F32 0x000001c5 +#define SQ_V_CUBETC_F32 0x000001c6 +#define SQ_V_CUBEMA_F32 0x000001c7 +#define SQ_V_BFE_U32 0x000001c8 +#define SQ_V_BFE_I32 0x000001c9 +#define SQ_V_BFI_B32 0x000001ca +#define SQ_V_FMA_F32 0x000001cb +#define SQ_V_FMA_F64 0x000001cc +#define SQ_V_LERP_U8 0x000001cd +#define SQ_V_ALIGNBIT_B32 0x000001ce +#define SQ_V_ALIGNBYTE_B32 0x000001cf +#define SQ_V_MIN3_F32 0x000001d0 +#define SQ_V_MIN3_I32 0x000001d1 +#define SQ_V_MIN3_U32 0x000001d2 +#define SQ_V_MAX3_F32 0x000001d3 +#define SQ_V_MAX3_I32 0x000001d4 +#define SQ_V_MAX3_U32 0x000001d5 +#define SQ_V_MED3_F32 0x000001d6 +#define SQ_V_MED3_I32 0x000001d7 +#define SQ_V_MED3_U32 0x000001d8 +#define SQ_V_SAD_U8 0x000001d9 +#define SQ_V_SAD_HI_U8 0x000001da +#define SQ_V_SAD_U16 0x000001db +#define SQ_V_SAD_U32 0x000001dc +#define SQ_V_CVT_PK_U8_F32 0x000001dd +#define SQ_V_DIV_FIXUP_F32 0x000001de +#define SQ_V_DIV_FIXUP_F64 0x000001df +#define SQ_V_DIV_SCALE_F32 0x000001e0 +#define SQ_V_DIV_SCALE_F64 0x000001e1 +#define SQ_V_DIV_FMAS_F32 0x000001e2 +#define SQ_V_DIV_FMAS_F64 0x000001e3 +#define SQ_V_MSAD_U8 0x000001e4 +#define SQ_V_QSAD_PK_U16_U8 0x000001e5 +#define SQ_V_MQSAD_PK_U16_U8 0x000001e6 +#define SQ_V_MQSAD_U32_U8 0x000001e7 +#define SQ_V_MAD_U64_U32 0x000001e8 +#define SQ_V_MAD_I64_I32 0x000001e9 +#define SQ_V_MAD_LEGACY_F16 0x000001ea +#define SQ_V_MAD_LEGACY_U16 0x000001eb +#define SQ_V_MAD_LEGACY_I16 0x000001ec +#define SQ_V_PERM_B32 0x000001ed +#define SQ_V_FMA_LEGACY_F16 0x000001ee +#define SQ_V_DIV_FIXUP_LEGACY_F16 0x000001ef +#define SQ_V_CVT_PKACCUM_U8_F32 0x000001f0 +#define SQ_V_MAD_U32_U16 0x000001f1 +#define SQ_V_MAD_I32_I16 0x000001f2 +#define SQ_V_XAD_U32 0x000001f3 +#define SQ_V_MIN3_F16 0x000001f4 +#define SQ_V_MIN3_I16 0x000001f5 +#define SQ_V_MIN3_U16 0x000001f6 +#define SQ_V_MAX3_F16 0x000001f7 +#define SQ_V_MAX3_I16 0x000001f8 +#define SQ_V_MAX3_U16 0x000001f9 +#define SQ_V_MED3_F16 0x000001fa +#define SQ_V_MED3_I16 0x000001fb +#define SQ_V_MED3_U16 0x000001fc +#define SQ_V_LSHL_ADD_U32 0x000001fd +#define SQ_V_ADD_LSHL_U32 0x000001fe +#define SQ_V_ADD3_U32 0x000001ff +#define SQ_V_LSHL_OR_B32 0x00000200 +#define SQ_V_AND_OR_B32 0x00000201 +#define SQ_V_OR3_B32 0x00000202 +#define SQ_V_MAD_F16 0x00000203 +#define SQ_V_MAD_U16 0x00000204 +#define SQ_V_MAD_I16 0x00000205 +#define SQ_V_FMA_F16 0x00000206 +#define SQ_V_DIV_FIXUP_F16 0x00000207 +#define SQ_V_INTERP_P1LL_F16 0x00000274 +#define SQ_V_INTERP_P1LV_F16 0x00000275 +#define SQ_V_INTERP_P2_LEGACY_F16 0x00000276 +#define SQ_V_INTERP_P2_F16 0x00000277 +#define SQ_V_ADD_F64 0x00000280 +#define SQ_V_MUL_F64 0x00000281 +#define SQ_V_MIN_F64 0x00000282 +#define SQ_V_MAX_F64 0x00000283 +#define SQ_V_LDEXP_F64 0x00000284 +#define SQ_V_MUL_LO_U32 0x00000285 +#define SQ_V_MUL_HI_U32 0x00000286 +#define SQ_V_MUL_HI_I32 0x00000287 +#define SQ_V_LDEXP_F32 0x00000288 +#define SQ_V_READLANE_B32 0x00000289 +#define SQ_V_WRITELANE_B32 0x0000028a +#define SQ_V_BCNT_U32_B32 0x0000028b +#define SQ_V_MBCNT_LO_U32_B32 0x0000028c +#define SQ_V_MBCNT_HI_U32_B32 0x0000028d +#define SQ_V_MAC_LEGACY_F32 0x0000028e +#define SQ_V_LSHLREV_B64 0x0000028f +#define SQ_V_LSHRREV_B64 0x00000290 +#define SQ_V_ASHRREV_I64 0x00000291 +#define SQ_V_TRIG_PREOP_F64 0x00000292 +#define SQ_V_BFM_B32 0x00000293 +#define SQ_V_CVT_PKNORM_I16_F32 0x00000294 +#define SQ_V_CVT_PKNORM_U16_F32 0x00000295 +#define SQ_V_CVT_PKRTZ_F16_F32 0x00000296 +#define SQ_V_CVT_PK_U16_U32 0x00000297 +#define SQ_V_CVT_PK_I16_I32 0x00000298 +#define SQ_V_CVT_PKNORM_I16_F16 0x00000299 +#define SQ_V_CVT_PKNORM_U16_F16 0x0000029a +#define SQ_V_READLANE_REGRD_B32 0x0000029b +#define SQ_V_ADD_I32 0x0000029c +#define SQ_V_SUB_I32 0x0000029d +#define SQ_V_ADD_I16 0x0000029e +#define SQ_V_SUB_I16 0x0000029f +#define SQ_V_PACK_B32_F16 0x000002a0 + +/* + * VALUE_SQ_SSRC_SPECIAL_LIT value + */ + +#define SQ_SRC_LITERAL 0x000000ff + +/* + * VALUE_SQ_DPP_CTRL value + */ + +#define SQ_DPP_QUAD_PERM 0x00000000 +#define SQ_DPP_ROW_SL1 0x00000101 +#define SQ_DPP_ROW_SL2 0x00000102 +#define SQ_DPP_ROW_SL3 0x00000103 +#define SQ_DPP_ROW_SL4 0x00000104 +#define SQ_DPP_ROW_SL5 0x00000105 +#define SQ_DPP_ROW_SL6 0x00000106 +#define SQ_DPP_ROW_SL7 0x00000107 +#define SQ_DPP_ROW_SL8 0x00000108 +#define SQ_DPP_ROW_SL9 0x00000109 +#define SQ_DPP_ROW_SL10 0x0000010a +#define SQ_DPP_ROW_SL11 0x0000010b +#define SQ_DPP_ROW_SL12 0x0000010c +#define SQ_DPP_ROW_SL13 0x0000010d +#define SQ_DPP_ROW_SL14 0x0000010e +#define SQ_DPP_ROW_SL15 0x0000010f +#define SQ_DPP_ROW_SR1 0x00000111 +#define SQ_DPP_ROW_SR2 0x00000112 +#define SQ_DPP_ROW_SR3 0x00000113 +#define SQ_DPP_ROW_SR4 0x00000114 +#define SQ_DPP_ROW_SR5 0x00000115 +#define SQ_DPP_ROW_SR6 0x00000116 +#define SQ_DPP_ROW_SR7 0x00000117 +#define SQ_DPP_ROW_SR8 0x00000118 +#define SQ_DPP_ROW_SR9 0x00000119 +#define SQ_DPP_ROW_SR10 0x0000011a +#define SQ_DPP_ROW_SR11 0x0000011b +#define SQ_DPP_ROW_SR12 0x0000011c +#define SQ_DPP_ROW_SR13 0x0000011d +#define SQ_DPP_ROW_SR14 0x0000011e +#define SQ_DPP_ROW_SR15 0x0000011f +#define SQ_DPP_ROW_RR1 0x00000121 +#define SQ_DPP_ROW_RR2 0x00000122 +#define SQ_DPP_ROW_RR3 0x00000123 +#define SQ_DPP_ROW_RR4 0x00000124 +#define SQ_DPP_ROW_RR5 0x00000125 +#define SQ_DPP_ROW_RR6 0x00000126 +#define SQ_DPP_ROW_RR7 0x00000127 +#define SQ_DPP_ROW_RR8 0x00000128 +#define SQ_DPP_ROW_RR9 0x00000129 +#define SQ_DPP_ROW_RR10 0x0000012a +#define SQ_DPP_ROW_RR11 0x0000012b +#define SQ_DPP_ROW_RR12 0x0000012c +#define SQ_DPP_ROW_RR13 0x0000012d +#define SQ_DPP_ROW_RR14 0x0000012e +#define SQ_DPP_ROW_RR15 0x0000012f +#define SQ_DPP_WF_SL1 0x00000130 +#define SQ_DPP_WF_RL1 0x00000134 +#define SQ_DPP_WF_SR1 0x00000138 +#define SQ_DPP_WF_RR1 0x0000013c +#define SQ_DPP_ROW_MIRROR 0x00000140 +#define SQ_DPP_ROW_HALF_MIRROR 0x00000141 +#define SQ_DPP_ROW_BCAST15 0x00000142 +#define SQ_DPP_ROW_BCAST31 0x00000143 + +/* + * VALUE_SQ_FLAT_SCRATCH_LOHI value + */ + +#define SQ_FLAT_SCRATCH_LO 0x00000066 +#define SQ_FLAT_SCRATCH_HI 0x00000067 + +/* + * VALUE_SQ_OP_VOP1 value + */ + +#define SQ_V_NOP 0x00000000 +#define SQ_V_MOV_B32 0x00000001 +#define SQ_V_READFIRSTLANE_B32 0x00000002 +#define SQ_V_CVT_I32_F64 0x00000003 +#define SQ_V_CVT_F64_I32 0x00000004 +#define SQ_V_CVT_F32_I32 0x00000005 +#define SQ_V_CVT_F32_U32 0x00000006 +#define SQ_V_CVT_U32_F32 0x00000007 +#define SQ_V_CVT_I32_F32 0x00000008 +#define SQ_V_MOV_FED_B32 0x00000009 +#define SQ_V_CVT_F16_F32 0x0000000a +#define SQ_V_CVT_F32_F16 0x0000000b +#define SQ_V_CVT_RPI_I32_F32 0x0000000c +#define SQ_V_CVT_FLR_I32_F32 0x0000000d +#define SQ_V_CVT_OFF_F32_I4 0x0000000e +#define SQ_V_CVT_F32_F64 0x0000000f +#define SQ_V_CVT_F64_F32 0x00000010 +#define SQ_V_CVT_F32_UBYTE0 0x00000011 +#define SQ_V_CVT_F32_UBYTE1 0x00000012 +#define SQ_V_CVT_F32_UBYTE2 0x00000013 +#define SQ_V_CVT_F32_UBYTE3 0x00000014 +#define SQ_V_CVT_U32_F64 0x00000015 +#define SQ_V_CVT_F64_U32 0x00000016 +#define SQ_V_TRUNC_F64 0x00000017 +#define SQ_V_CEIL_F64 0x00000018 +#define SQ_V_RNDNE_F64 0x00000019 +#define SQ_V_FLOOR_F64 0x0000001a +#define SQ_V_FRACT_F32 0x0000001b +#define SQ_V_TRUNC_F32 0x0000001c +#define SQ_V_CEIL_F32 0x0000001d +#define SQ_V_RNDNE_F32 0x0000001e +#define SQ_V_FLOOR_F32 0x0000001f +#define SQ_V_EXP_F32 0x00000020 +#define SQ_V_LOG_F32 0x00000021 +#define SQ_V_RCP_F32 0x00000022 +#define SQ_V_RCP_IFLAG_F32 0x00000023 +#define SQ_V_RSQ_F32 0x00000024 +#define SQ_V_RCP_F64 0x00000025 +#define SQ_V_RSQ_F64 0x00000026 +#define SQ_V_SQRT_F32 0x00000027 +#define SQ_V_SQRT_F64 0x00000028 +#define SQ_V_SIN_F32 0x00000029 +#define SQ_V_COS_F32 0x0000002a +#define SQ_V_NOT_B32 0x0000002b +#define SQ_V_BFREV_B32 0x0000002c +#define SQ_V_FFBH_U32 0x0000002d +#define SQ_V_FFBL_B32 0x0000002e +#define SQ_V_FFBH_I32 0x0000002f +#define SQ_V_FREXP_EXP_I32_F64 0x00000030 +#define SQ_V_FREXP_MANT_F64 0x00000031 +#define SQ_V_FRACT_F64 0x00000032 +#define SQ_V_FREXP_EXP_I32_F32 0x00000033 +#define SQ_V_FREXP_MANT_F32 0x00000034 +#define SQ_V_CLREXCP 0x00000035 +#define SQ_V_MOV_PRSV_B32 0x00000036 +#define SQ_V_CVT_F16_U16 0x00000039 +#define SQ_V_CVT_F16_I16 0x0000003a +#define SQ_V_CVT_U16_F16 0x0000003b +#define SQ_V_CVT_I16_F16 0x0000003c +#define SQ_V_RCP_F16 0x0000003d +#define SQ_V_SQRT_F16 0x0000003e +#define SQ_V_RSQ_F16 0x0000003f +#define SQ_V_LOG_F16 0x00000040 +#define SQ_V_EXP_F16 0x00000041 +#define SQ_V_FREXP_MANT_F16 0x00000042 +#define SQ_V_FREXP_EXP_I16_F16 0x00000043 +#define SQ_V_FLOOR_F16 0x00000044 +#define SQ_V_CEIL_F16 0x00000045 +#define SQ_V_TRUNC_F16 0x00000046 +#define SQ_V_RNDNE_F16 0x00000047 +#define SQ_V_FRACT_F16 0x00000048 +#define SQ_V_SIN_F16 0x00000049 +#define SQ_V_COS_F16 0x0000004a +#define SQ_V_EXP_LEGACY_F32 0x0000004b +#define SQ_V_LOG_LEGACY_F32 0x0000004c +#define SQ_V_CVT_NORM_I16_F16 0x0000004d +#define SQ_V_CVT_NORM_U16_F16 0x0000004e +#define SQ_V_SAT_PK_U8_I16 0x0000004f +#define SQ_V_WRITELANE_IMM32 0x00000050 +#define SQ_V_SWAP_B32 0x00000051 + +/* + * VALUE_SQ_OP_FLAT value + */ + +#define SQ_FLAT_LOAD_UBYTE 0x00000010 +#define SQ_FLAT_LOAD_SBYTE 0x00000011 +#define SQ_FLAT_LOAD_USHORT 0x00000012 +#define SQ_FLAT_LOAD_SSHORT 0x00000013 +#define SQ_FLAT_LOAD_DWORD 0x00000014 +#define SQ_FLAT_LOAD_DWORDX2 0x00000015 +#define SQ_FLAT_LOAD_DWORDX3 0x00000016 +#define SQ_FLAT_LOAD_DWORDX4 0x00000017 +#define SQ_FLAT_STORE_BYTE 0x00000018 +#define SQ_FLAT_STORE_SHORT 0x0000001a +#define SQ_FLAT_STORE_DWORD 0x0000001c +#define SQ_FLAT_STORE_DWORDX2 0x0000001d +#define SQ_FLAT_STORE_DWORDX3 0x0000001e +#define SQ_FLAT_STORE_DWORDX4 0x0000001f +#define SQ_FLAT_ATOMIC_SWAP 0x00000040 +#define SQ_FLAT_ATOMIC_CMPSWAP 0x00000041 +#define SQ_FLAT_ATOMIC_ADD 0x00000042 +#define SQ_FLAT_ATOMIC_SUB 0x00000043 +#define SQ_FLAT_ATOMIC_SMIN 0x00000044 +#define SQ_FLAT_ATOMIC_UMIN 0x00000045 +#define SQ_FLAT_ATOMIC_SMAX 0x00000046 +#define SQ_FLAT_ATOMIC_UMAX 0x00000047 +#define SQ_FLAT_ATOMIC_AND 0x00000048 +#define SQ_FLAT_ATOMIC_OR 0x00000049 +#define SQ_FLAT_ATOMIC_XOR 0x0000004a +#define SQ_FLAT_ATOMIC_INC 0x0000004b +#define SQ_FLAT_ATOMIC_DEC 0x0000004c +#define SQ_FLAT_ATOMIC_SWAP_X2 0x00000060 +#define SQ_FLAT_ATOMIC_CMPSWAP_X2 0x00000061 +#define SQ_FLAT_ATOMIC_ADD_X2 0x00000062 +#define SQ_FLAT_ATOMIC_SUB_X2 0x00000063 +#define SQ_FLAT_ATOMIC_SMIN_X2 0x00000064 +#define SQ_FLAT_ATOMIC_UMIN_X2 0x00000065 +#define SQ_FLAT_ATOMIC_SMAX_X2 0x00000066 +#define SQ_FLAT_ATOMIC_UMAX_X2 0x00000067 +#define SQ_FLAT_ATOMIC_AND_X2 0x00000068 +#define SQ_FLAT_ATOMIC_OR_X2 0x00000069 +#define SQ_FLAT_ATOMIC_XOR_X2 0x0000006a +#define SQ_FLAT_ATOMIC_INC_X2 0x0000006b +#define SQ_FLAT_ATOMIC_DEC_X2 0x0000006c + +/* + * VALUE_SQ_OP_DS value + */ + +#define SQ_DS_ADD_U32 0x00000000 +#define SQ_DS_SUB_U32 0x00000001 +#define SQ_DS_RSUB_U32 0x00000002 +#define SQ_DS_INC_U32 0x00000003 +#define SQ_DS_DEC_U32 0x00000004 +#define SQ_DS_MIN_I32 0x00000005 +#define SQ_DS_MAX_I32 0x00000006 +#define SQ_DS_MIN_U32 0x00000007 +#define SQ_DS_MAX_U32 0x00000008 +#define SQ_DS_AND_B32 0x00000009 +#define SQ_DS_OR_B32 0x0000000a +#define SQ_DS_XOR_B32 0x0000000b +#define SQ_DS_MSKOR_B32 0x0000000c +#define SQ_DS_WRITE_B32 0x0000000d +#define SQ_DS_WRITE2_B32 0x0000000e +#define SQ_DS_WRITE2ST64_B32 0x0000000f +#define SQ_DS_CMPST_B32 0x00000010 +#define SQ_DS_CMPST_F32 0x00000011 +#define SQ_DS_MIN_F32 0x00000012 +#define SQ_DS_MAX_F32 0x00000013 +#define SQ_DS_NOP 0x00000014 +#define SQ_DS_ADD_F32 0x00000015 +#define SQ_DS_WRITE_ADDTID_B32 0x0000001d +#define SQ_DS_WRITE_B8 0x0000001e +#define SQ_DS_WRITE_B16 0x0000001f +#define SQ_DS_ADD_RTN_U32 0x00000020 +#define SQ_DS_SUB_RTN_U32 0x00000021 +#define SQ_DS_RSUB_RTN_U32 0x00000022 +#define SQ_DS_INC_RTN_U32 0x00000023 +#define SQ_DS_DEC_RTN_U32 0x00000024 +#define SQ_DS_MIN_RTN_I32 0x00000025 +#define SQ_DS_MAX_RTN_I32 0x00000026 +#define SQ_DS_MIN_RTN_U32 0x00000027 +#define SQ_DS_MAX_RTN_U32 0x00000028 +#define SQ_DS_AND_RTN_B32 0x00000029 +#define SQ_DS_OR_RTN_B32 0x0000002a +#define SQ_DS_XOR_RTN_B32 0x0000002b +#define SQ_DS_MSKOR_RTN_B32 0x0000002c +#define SQ_DS_WRXCHG_RTN_B32 0x0000002d +#define SQ_DS_WRXCHG2_RTN_B32 0x0000002e +#define SQ_DS_WRXCHG2ST64_RTN_B32 0x0000002f +#define SQ_DS_CMPST_RTN_B32 0x00000030 +#define SQ_DS_CMPST_RTN_F32 0x00000031 +#define SQ_DS_MIN_RTN_F32 0x00000032 +#define SQ_DS_MAX_RTN_F32 0x00000033 +#define SQ_DS_WRAP_RTN_B32 0x00000034 +#define SQ_DS_ADD_RTN_F32 0x00000035 +#define SQ_DS_READ_B32 0x00000036 +#define SQ_DS_READ2_B32 0x00000037 +#define SQ_DS_READ2ST64_B32 0x00000038 +#define SQ_DS_READ_I8 0x00000039 +#define SQ_DS_READ_U8 0x0000003a +#define SQ_DS_READ_I16 0x0000003b +#define SQ_DS_READ_U16 0x0000003c +#define SQ_DS_SWIZZLE_B32 0x0000003d +#define SQ_DS_PERMUTE_B32 0x0000003e +#define SQ_DS_BPERMUTE_B32 0x0000003f +#define SQ_DS_ADD_U64 0x00000040 +#define SQ_DS_SUB_U64 0x00000041 +#define SQ_DS_RSUB_U64 0x00000042 +#define SQ_DS_INC_U64 0x00000043 +#define SQ_DS_DEC_U64 0x00000044 +#define SQ_DS_MIN_I64 0x00000045 +#define SQ_DS_MAX_I64 0x00000046 +#define SQ_DS_MIN_U64 0x00000047 +#define SQ_DS_MAX_U64 0x00000048 +#define SQ_DS_AND_B64 0x00000049 +#define SQ_DS_OR_B64 0x0000004a +#define SQ_DS_XOR_B64 0x0000004b +#define SQ_DS_MSKOR_B64 0x0000004c +#define SQ_DS_WRITE_B64 0x0000004d +#define SQ_DS_WRITE2_B64 0x0000004e +#define SQ_DS_WRITE2ST64_B64 0x0000004f +#define SQ_DS_CMPST_B64 0x00000050 +#define SQ_DS_CMPST_F64 0x00000051 +#define SQ_DS_MIN_F64 0x00000052 +#define SQ_DS_MAX_F64 0x00000053 +#define SQ_DS_ADD_RTN_U64 0x00000060 +#define SQ_DS_SUB_RTN_U64 0x00000061 +#define SQ_DS_RSUB_RTN_U64 0x00000062 +#define SQ_DS_INC_RTN_U64 0x00000063 +#define SQ_DS_DEC_RTN_U64 0x00000064 +#define SQ_DS_MIN_RTN_I64 0x00000065 +#define SQ_DS_MAX_RTN_I64 0x00000066 +#define SQ_DS_MIN_RTN_U64 0x00000067 +#define SQ_DS_MAX_RTN_U64 0x00000068 +#define SQ_DS_AND_RTN_B64 0x00000069 +#define SQ_DS_OR_RTN_B64 0x0000006a +#define SQ_DS_XOR_RTN_B64 0x0000006b +#define SQ_DS_MSKOR_RTN_B64 0x0000006c +#define SQ_DS_WRXCHG_RTN_B64 0x0000006d +#define SQ_DS_WRXCHG2_RTN_B64 0x0000006e +#define SQ_DS_WRXCHG2ST64_RTN_B64 0x0000006f +#define SQ_DS_CMPST_RTN_B64 0x00000070 +#define SQ_DS_CMPST_RTN_F64 0x00000071 +#define SQ_DS_MIN_RTN_F64 0x00000072 +#define SQ_DS_MAX_RTN_F64 0x00000073 +#define SQ_DS_READ_B64 0x00000076 +#define SQ_DS_READ2_B64 0x00000077 +#define SQ_DS_READ2ST64_B64 0x00000078 +#define SQ_DS_CONDXCHG32_RTN_B64 0x0000007e +#define SQ_DS_ADD_SRC2_U32 0x00000080 +#define SQ_DS_SUB_SRC2_U32 0x00000081 +#define SQ_DS_RSUB_SRC2_U32 0x00000082 +#define SQ_DS_INC_SRC2_U32 0x00000083 +#define SQ_DS_DEC_SRC2_U32 0x00000084 +#define SQ_DS_MIN_SRC2_I32 0x00000085 +#define SQ_DS_MAX_SRC2_I32 0x00000086 +#define SQ_DS_MIN_SRC2_U32 0x00000087 +#define SQ_DS_MAX_SRC2_U32 0x00000088 +#define SQ_DS_AND_SRC2_B32 0x00000089 +#define SQ_DS_OR_SRC2_B32 0x0000008a +#define SQ_DS_XOR_SRC2_B32 0x0000008b +#define SQ_DS_WRITE_SRC2_B32 0x0000008d +#define SQ_DS_MIN_SRC2_F32 0x00000092 +#define SQ_DS_MAX_SRC2_F32 0x00000093 +#define SQ_DS_ADD_SRC2_F32 0x00000095 +#define SQ_DS_GWS_SEMA_RELEASE_ALL 0x00000098 +#define SQ_DS_GWS_INIT 0x00000099 +#define SQ_DS_GWS_SEMA_V 0x0000009a +#define SQ_DS_GWS_SEMA_BR 0x0000009b +#define SQ_DS_GWS_SEMA_P 0x0000009c +#define SQ_DS_GWS_BARRIER 0x0000009d +#define SQ_DS_READ_ADDTID_B32 0x000000b6 +#define SQ_DS_CONSUME 0x000000bd +#define SQ_DS_APPEND 0x000000be +#define SQ_DS_ORDERED_COUNT 0x000000bf +#define SQ_DS_ADD_SRC2_U64 0x000000c0 +#define SQ_DS_SUB_SRC2_U64 0x000000c1 +#define SQ_DS_RSUB_SRC2_U64 0x000000c2 +#define SQ_DS_INC_SRC2_U64 0x000000c3 +#define SQ_DS_DEC_SRC2_U64 0x000000c4 +#define SQ_DS_MIN_SRC2_I64 0x000000c5 +#define SQ_DS_MAX_SRC2_I64 0x000000c6 +#define SQ_DS_MIN_SRC2_U64 0x000000c7 +#define SQ_DS_MAX_SRC2_U64 0x000000c8 +#define SQ_DS_AND_SRC2_B64 0x000000c9 +#define SQ_DS_OR_SRC2_B64 0x000000ca +#define SQ_DS_XOR_SRC2_B64 0x000000cb +#define SQ_DS_WRITE_SRC2_B64 0x000000cd +#define SQ_DS_MIN_SRC2_F64 0x000000d2 +#define SQ_DS_MAX_SRC2_F64 0x000000d3 +#define SQ_DS_WRITE_B96 0x000000de +#define SQ_DS_WRITE_B128 0x000000df +#define SQ_DS_CONDXCHG32_RTN_B128 0x000000fd +#define SQ_DS_READ_B96 0x000000fe +#define SQ_DS_READ_B128 0x000000ff + +/* + * VALUE_SQ_OP_SMEM value + */ + +#define SQ_S_LOAD_DWORD 0x00000000 +#define SQ_S_LOAD_DWORDX2 0x00000001 +#define SQ_S_LOAD_DWORDX4 0x00000002 +#define SQ_S_LOAD_DWORDX8 0x00000003 +#define SQ_S_LOAD_DWORDX16 0x00000004 +#define SQ_S_SCRATCH_LOAD_DWORD 0x00000005 +#define SQ_S_SCRATCH_LOAD_DWORDX2 0x00000006 +#define SQ_S_SCRATCH_LOAD_DWORDX4 0x00000007 +#define SQ_S_BUFFER_LOAD_DWORD 0x00000008 +#define SQ_S_BUFFER_LOAD_DWORDX2 0x00000009 +#define SQ_S_BUFFER_LOAD_DWORDX4 0x0000000a +#define SQ_S_BUFFER_LOAD_DWORDX8 0x0000000b +#define SQ_S_BUFFER_LOAD_DWORDX16 0x0000000c +#define SQ_S_STORE_DWORD 0x00000010 +#define SQ_S_STORE_DWORDX2 0x00000011 +#define SQ_S_STORE_DWORDX4 0x00000012 +#define SQ_S_SCRATCH_STORE_DWORD 0x00000015 +#define SQ_S_SCRATCH_STORE_DWORDX2 0x00000016 +#define SQ_S_SCRATCH_STORE_DWORDX4 0x00000017 +#define SQ_S_BUFFER_STORE_DWORD 0x00000018 +#define SQ_S_BUFFER_STORE_DWORDX2 0x00000019 +#define SQ_S_BUFFER_STORE_DWORDX4 0x0000001a +#define SQ_S_DCACHE_INV 0x00000020 +#define SQ_S_DCACHE_WB 0x00000021 +#define SQ_S_DCACHE_INV_VOL 0x00000022 +#define SQ_S_DCACHE_WB_VOL 0x00000023 +#define SQ_S_MEMTIME 0x00000024 +#define SQ_S_MEMREALTIME 0x00000025 +#define SQ_S_ATC_PROBE 0x00000026 +#define SQ_S_ATC_PROBE_BUFFER 0x00000027 +#define SQ_S_BUFFER_ATOMIC_SWAP 0x00000040 +#define SQ_S_BUFFER_ATOMIC_CMPSWAP 0x00000041 +#define SQ_S_BUFFER_ATOMIC_ADD 0x00000042 +#define SQ_S_BUFFER_ATOMIC_SUB 0x00000043 +#define SQ_S_BUFFER_ATOMIC_SMIN 0x00000044 +#define SQ_S_BUFFER_ATOMIC_UMIN 0x00000045 +#define SQ_S_BUFFER_ATOMIC_SMAX 0x00000046 +#define SQ_S_BUFFER_ATOMIC_UMAX 0x00000047 +#define SQ_S_BUFFER_ATOMIC_AND 0x00000048 +#define SQ_S_BUFFER_ATOMIC_OR 0x00000049 +#define SQ_S_BUFFER_ATOMIC_XOR 0x0000004a +#define SQ_S_BUFFER_ATOMIC_INC 0x0000004b +#define SQ_S_BUFFER_ATOMIC_DEC 0x0000004c +#define SQ_S_BUFFER_ATOMIC_SWAP_X2 0x00000060 +#define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2 0x00000061 +#define SQ_S_BUFFER_ATOMIC_ADD_X2 0x00000062 +#define SQ_S_BUFFER_ATOMIC_SUB_X2 0x00000063 +#define SQ_S_BUFFER_ATOMIC_SMIN_X2 0x00000064 +#define SQ_S_BUFFER_ATOMIC_UMIN_X2 0x00000065 +#define SQ_S_BUFFER_ATOMIC_SMAX_X2 0x00000066 +#define SQ_S_BUFFER_ATOMIC_UMAX_X2 0x00000067 +#define SQ_S_BUFFER_ATOMIC_AND_X2 0x00000068 +#define SQ_S_BUFFER_ATOMIC_OR_X2 0x00000069 +#define SQ_S_BUFFER_ATOMIC_XOR_X2 0x0000006a +#define SQ_S_BUFFER_ATOMIC_INC_X2 0x0000006b +#define SQ_S_BUFFER_ATOMIC_DEC_X2 0x0000006c +#define SQ_S_ATOMIC_SWAP 0x00000080 +#define SQ_S_ATOMIC_CMPSWAP 0x00000081 +#define SQ_S_ATOMIC_ADD 0x00000082 +#define SQ_S_ATOMIC_SUB 0x00000083 +#define SQ_S_ATOMIC_SMIN 0x00000084 +#define SQ_S_ATOMIC_UMIN 0x00000085 +#define SQ_S_ATOMIC_SMAX 0x00000086 +#define SQ_S_ATOMIC_UMAX 0x00000087 +#define SQ_S_ATOMIC_AND 0x00000088 +#define SQ_S_ATOMIC_OR 0x00000089 +#define SQ_S_ATOMIC_XOR 0x0000008a +#define SQ_S_ATOMIC_INC 0x0000008b +#define SQ_S_ATOMIC_DEC 0x0000008c +#define SQ_S_ATOMIC_SWAP_X2 0x000000a0 +#define SQ_S_ATOMIC_CMPSWAP_X2 0x000000a1 +#define SQ_S_ATOMIC_ADD_X2 0x000000a2 +#define SQ_S_ATOMIC_SUB_X2 0x000000a3 +#define SQ_S_ATOMIC_SMIN_X2 0x000000a4 +#define SQ_S_ATOMIC_UMIN_X2 0x000000a5 +#define SQ_S_ATOMIC_SMAX_X2 0x000000a6 +#define SQ_S_ATOMIC_UMAX_X2 0x000000a7 +#define SQ_S_ATOMIC_AND_X2 0x000000a8 +#define SQ_S_ATOMIC_OR_X2 0x000000a9 +#define SQ_S_ATOMIC_XOR_X2 0x000000aa +#define SQ_S_ATOMIC_INC_X2 0x000000ab +#define SQ_S_ATOMIC_DEC_X2 0x000000ac + +/* + * VALUE_SQ_OP_VOP2 value + */ + +#define SQ_V_CNDMASK_B32 0x00000000 +#define SQ_V_ADD_F32 0x00000001 +#define SQ_V_SUB_F32 0x00000002 +#define SQ_V_SUBREV_F32 0x00000003 +#define SQ_V_MUL_LEGACY_F32 0x00000004 +#define SQ_V_MUL_F32 0x00000005 +#define SQ_V_MUL_I32_I24 0x00000006 +#define SQ_V_MUL_HI_I32_I24 0x00000007 +#define SQ_V_MUL_U32_U24 0x00000008 +#define SQ_V_MUL_HI_U32_U24 0x00000009 +#define SQ_V_MIN_F32 0x0000000a +#define SQ_V_MAX_F32 0x0000000b +#define SQ_V_MIN_I32 0x0000000c +#define SQ_V_MAX_I32 0x0000000d +#define SQ_V_MIN_U32 0x0000000e +#define SQ_V_MAX_U32 0x0000000f +#define SQ_V_LSHRREV_B32 0x00000010 +#define SQ_V_ASHRREV_I32 0x00000011 +#define SQ_V_LSHLREV_B32 0x00000012 +#define SQ_V_AND_B32 0x00000013 +#define SQ_V_OR_B32 0x00000014 +#define SQ_V_XOR_B32 0x00000015 +#define SQ_V_MAC_F32 0x00000016 +#define SQ_V_MADMK_F32 0x00000017 +#define SQ_V_MADAK_F32 0x00000018 +#define SQ_V_ADD_CO_U32 0x00000019 +#define SQ_V_SUB_CO_U32 0x0000001a +#define SQ_V_SUBREV_CO_U32 0x0000001b +#define SQ_V_ADDC_CO_U32 0x0000001c +#define SQ_V_SUBB_CO_U32 0x0000001d +#define SQ_V_SUBBREV_CO_U32 0x0000001e +#define SQ_V_ADD_F16 0x0000001f +#define SQ_V_SUB_F16 0x00000020 +#define SQ_V_SUBREV_F16 0x00000021 +#define SQ_V_MUL_F16 0x00000022 +#define SQ_V_MAC_F16 0x00000023 +#define SQ_V_MADMK_F16 0x00000024 +#define SQ_V_MADAK_F16 0x00000025 +#define SQ_V_ADD_U16 0x00000026 +#define SQ_V_SUB_U16 0x00000027 +#define SQ_V_SUBREV_U16 0x00000028 +#define SQ_V_MUL_LO_U16 0x00000029 +#define SQ_V_LSHLREV_B16 0x0000002a +#define SQ_V_LSHRREV_B16 0x0000002b +#define SQ_V_ASHRREV_I16 0x0000002c +#define SQ_V_MAX_F16 0x0000002d +#define SQ_V_MIN_F16 0x0000002e +#define SQ_V_MAX_U16 0x0000002f +#define SQ_V_MAX_I16 0x00000030 +#define SQ_V_MIN_U16 0x00000031 +#define SQ_V_MIN_I16 0x00000032 +#define SQ_V_LDEXP_F16 0x00000033 +#define SQ_V_ADD_U32 0x00000034 +#define SQ_V_SUB_U32 0x00000035 +#define SQ_V_SUBREV_U32 0x00000036 + +/* + * VALUE_SQ_SYSMSG_OP value + */ + +#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x00000001 +#define SQ_SYSMSG_OP_REG_RD 0x00000002 +#define SQ_SYSMSG_OP_HOST_TRAP_ACK 0x00000003 +#define SQ_SYSMSG_OP_TTRACE_PC 0x00000004 +#define SQ_SYSMSG_OP_ILLEGAL_INST_INTERRUPT 0x00000005 +#define SQ_SYSMSG_OP_MEMVIOL_INTERRUPT 0x00000006 + +/* + * VALUE_SQ_SSRC_SPECIAL_VCCZ value + */ + +#define SQ_SRC_VCCZ 0x000000fb + +/* + * VALUE_SQ_CHAN value + */ + +#define SQ_CHAN_X 0x00000000 +#define SQ_CHAN_Y 0x00000001 +#define SQ_CHAN_Z 0x00000002 +#define SQ_CHAN_W 0x00000003 + +/* + * VALUE_SQ_OP_SOPK value + */ + +#define SQ_S_MOVK_I32 0x00000000 +#define SQ_S_CMOVK_I32 0x00000001 +#define SQ_S_CMPK_EQ_I32 0x00000002 +#define SQ_S_CMPK_LG_I32 0x00000003 +#define SQ_S_CMPK_GT_I32 0x00000004 +#define SQ_S_CMPK_GE_I32 0x00000005 +#define SQ_S_CMPK_LT_I32 0x00000006 +#define SQ_S_CMPK_LE_I32 0x00000007 +#define SQ_S_CMPK_EQ_U32 0x00000008 +#define SQ_S_CMPK_LG_U32 0x00000009 +#define SQ_S_CMPK_GT_U32 0x0000000a +#define SQ_S_CMPK_GE_U32 0x0000000b +#define SQ_S_CMPK_LT_U32 0x0000000c +#define SQ_S_CMPK_LE_U32 0x0000000d +#define SQ_S_ADDK_I32 0x0000000e +#define SQ_S_MULK_I32 0x0000000f +#define SQ_S_CBRANCH_I_FORK 0x00000010 +#define SQ_S_GETREG_B32 0x00000011 +#define SQ_S_SETREG_B32 0x00000012 +#define SQ_S_GETREG_REGRD_B32 0x00000013 +#define SQ_S_SETREG_IMM32_B32 0x00000014 +#define SQ_S_CALL_B64 0x00000015 + +/* + * VALUE_SQ_DPP_CTRL_L_1_15 value + */ + +#define SQ_L1 0x00000001 +#define SQ_L2 0x00000002 +#define SQ_L3 0x00000003 +#define SQ_L4 0x00000004 +#define SQ_L5 0x00000005 +#define SQ_L6 0x00000006 +#define SQ_L7 0x00000007 +#define SQ_L8 0x00000008 +#define SQ_L9 0x00000009 +#define SQ_L10 0x0000000a +#define SQ_L11 0x0000000b +#define SQ_L12 0x0000000c +#define SQ_L13 0x0000000d +#define SQ_L14 0x0000000e +#define SQ_L15 0x0000000f + +/* + * VALUE_SQ_SGPR value + */ + +#define SQ_SGPR0 0x00000000 + +/* + * VALUE_SQ_OP_VOP3P value + */ + +#define SQ_V_PK_MAD_I16 0x00000000 +#define SQ_V_PK_MUL_LO_U16 0x00000001 +#define SQ_V_PK_ADD_I16 0x00000002 +#define SQ_V_PK_SUB_I16 0x00000003 +#define SQ_V_PK_LSHLREV_B16 0x00000004 +#define SQ_V_PK_LSHRREV_B16 0x00000005 +#define SQ_V_PK_ASHRREV_I16 0x00000006 +#define SQ_V_PK_MAX_I16 0x00000007 +#define SQ_V_PK_MIN_I16 0x00000008 +#define SQ_V_PK_MAD_U16 0x00000009 +#define SQ_V_PK_ADD_U16 0x0000000a +#define SQ_V_PK_SUB_U16 0x0000000b +#define SQ_V_PK_MAX_U16 0x0000000c +#define SQ_V_PK_MIN_U16 0x0000000d +#define SQ_V_PK_MAD_F16 0x0000000e +#define SQ_V_PK_ADD_F16 0x0000000f +#define SQ_V_PK_MUL_F16 0x00000010 +#define SQ_V_PK_MIN_F16 0x00000011 +#define SQ_V_PK_MAX_F16 0x00000012 +#define SQ_V_MAD_MIX_F32 0x00000020 +#define SQ_V_MAD_MIXLO_F16 0x00000021 +#define SQ_V_MAD_MIXHI_F16 0x00000022 + +/* + * VALUE_SQ_OP_VINTRP value + */ + +#define SQ_V_INTERP_P1_F32 0x00000000 +#define SQ_V_INTERP_P2_F32 0x00000001 +#define SQ_V_INTERP_MOV_F32 0x00000002 + +/* + * VALUE_SQ_DPP_CTRL_R_1_15 value + */ + +#define SQ_R1 0x00000001 +#define SQ_R2 0x00000002 +#define SQ_R3 0x00000003 +#define SQ_R4 0x00000004 +#define SQ_R5 0x00000005 +#define SQ_R6 0x00000006 +#define SQ_R7 0x00000007 +#define SQ_R8 0x00000008 +#define SQ_R9 0x00000009 +#define SQ_R10 0x0000000a +#define SQ_R11 0x0000000b +#define SQ_R12 0x0000000c +#define SQ_R13 0x0000000d +#define SQ_R14 0x0000000e +#define SQ_R15 0x0000000f + +/* + * VALUE_SQ_OP_SOP2 value + */ + +#define SQ_S_ADD_U32 0x00000000 +#define SQ_S_SUB_U32 0x00000001 +#define SQ_S_ADD_I32 0x00000002 +#define SQ_S_SUB_I32 0x00000003 +#define SQ_S_ADDC_U32 0x00000004 +#define SQ_S_SUBB_U32 0x00000005 +#define SQ_S_MIN_I32 0x00000006 +#define SQ_S_MIN_U32 0x00000007 +#define SQ_S_MAX_I32 0x00000008 +#define SQ_S_MAX_U32 0x00000009 +#define SQ_S_CSELECT_B32 0x0000000a +#define SQ_S_CSELECT_B64 0x0000000b +#define SQ_S_AND_B32 0x0000000c +#define SQ_S_AND_B64 0x0000000d +#define SQ_S_OR_B32 0x0000000e +#define SQ_S_OR_B64 0x0000000f +#define SQ_S_XOR_B32 0x00000010 +#define SQ_S_XOR_B64 0x00000011 +#define SQ_S_ANDN2_B32 0x00000012 +#define SQ_S_ANDN2_B64 0x00000013 +#define SQ_S_ORN2_B32 0x00000014 +#define SQ_S_ORN2_B64 0x00000015 +#define SQ_S_NAND_B32 0x00000016 +#define SQ_S_NAND_B64 0x00000017 +#define SQ_S_NOR_B32 0x00000018 +#define SQ_S_NOR_B64 0x00000019 +#define SQ_S_XNOR_B32 0x0000001a +#define SQ_S_XNOR_B64 0x0000001b +#define SQ_S_LSHL_B32 0x0000001c +#define SQ_S_LSHL_B64 0x0000001d +#define SQ_S_LSHR_B32 0x0000001e +#define SQ_S_LSHR_B64 0x0000001f +#define SQ_S_ASHR_I32 0x00000020 +#define SQ_S_ASHR_I64 0x00000021 +#define SQ_S_BFM_B32 0x00000022 +#define SQ_S_BFM_B64 0x00000023 +#define SQ_S_MUL_I32 0x00000024 +#define SQ_S_BFE_U32 0x00000025 +#define SQ_S_BFE_I32 0x00000026 +#define SQ_S_BFE_U64 0x00000027 +#define SQ_S_BFE_I64 0x00000028 +#define SQ_S_CBRANCH_G_FORK 0x00000029 +#define SQ_S_ABSDIFF_I32 0x0000002a +#define SQ_S_RFE_RESTORE_B64 0x0000002b +#define SQ_S_MUL_HI_U32 0x0000002c +#define SQ_S_MUL_HI_I32 0x0000002d +#define SQ_S_LSHL1_ADD_U32 0x0000002e +#define SQ_S_LSHL2_ADD_U32 0x0000002f +#define SQ_S_LSHL3_ADD_U32 0x00000030 +#define SQ_S_LSHL4_ADD_U32 0x00000031 +#define SQ_S_PACK_LL_B32_B16 0x00000032 +#define SQ_S_PACK_LH_B32_B16 0x00000033 +#define SQ_S_PACK_HH_B32_B16 0x00000034 + +/* + * VALUE_SQ_SEG value + */ + +#define SQ_FLAT 0x00000000 +#define SQ_SCRATCH 0x00000001 +#define SQ_GLOBAL 0x00000002 + +/* + * VALUE_SQ_SDST_EXEC value + */ + +#define SQ_EXEC_LO 0x0000007e +#define SQ_EXEC_HI 0x0000007f + +/* + * VALUE_SQ_SSRC_SPECIAL_NOLIT value + */ + +#define SQ_SRC_64_INT 0x000000c0 +#define SQ_SRC_M_1_INT 0x000000c1 +#define SQ_SRC_M_2_INT 0x000000c2 +#define SQ_SRC_M_3_INT 0x000000c3 +#define SQ_SRC_M_4_INT 0x000000c4 +#define SQ_SRC_M_5_INT 0x000000c5 +#define SQ_SRC_M_6_INT 0x000000c6 +#define SQ_SRC_M_7_INT 0x000000c7 +#define SQ_SRC_M_8_INT 0x000000c8 +#define SQ_SRC_M_9_INT 0x000000c9 +#define SQ_SRC_M_10_INT 0x000000ca +#define SQ_SRC_M_11_INT 0x000000cb +#define SQ_SRC_M_12_INT 0x000000cc +#define SQ_SRC_M_13_INT 0x000000cd +#define SQ_SRC_M_14_INT 0x000000ce +#define SQ_SRC_M_15_INT 0x000000cf +#define SQ_SRC_M_16_INT 0x000000d0 +#define SQ_SRC_0_5 0x000000f0 +#define SQ_SRC_M_0_5 0x000000f1 +#define SQ_SRC_1 0x000000f2 +#define SQ_SRC_M_1 0x000000f3 +#define SQ_SRC_2 0x000000f4 +#define SQ_SRC_M_2 0x000000f5 +#define SQ_SRC_4 0x000000f6 +#define SQ_SRC_M_4 0x000000f7 +#define SQ_SRC_INV_2PI 0x000000f8 + +/* + * VALUE_SQ_VCC_LOHI value + */ + +#define SQ_VCC_LO 0x0000006a +#define SQ_VCC_HI 0x0000006b + +/* + * VALUE_SQ_TGT value + */ + +#define SQ_EXP_MRT0 0x00000000 +#define SQ_EXP_MRTZ 0x00000008 +#define SQ_EXP_NULL 0x00000009 +#define SQ_EXP_POS0 0x0000000c +#define SQ_EXP_PARAM0 0x00000020 + +/* + * VALUE_SQ_OP_SOPP value + */ + +#define SQ_S_NOP 0x00000000 +#define SQ_S_ENDPGM 0x00000001 +#define SQ_S_BRANCH 0x00000002 +#define SQ_S_WAKEUP 0x00000003 +#define SQ_S_CBRANCH_SCC0 0x00000004 +#define SQ_S_CBRANCH_SCC1 0x00000005 +#define SQ_S_CBRANCH_VCCZ 0x00000006 +#define SQ_S_CBRANCH_VCCNZ 0x00000007 +#define SQ_S_CBRANCH_EXECZ 0x00000008 +#define SQ_S_CBRANCH_EXECNZ 0x00000009 +#define SQ_S_BARRIER 0x0000000a +#define SQ_S_SETKILL 0x0000000b +#define SQ_S_WAITCNT 0x0000000c +#define SQ_S_SETHALT 0x0000000d +#define SQ_S_SLEEP 0x0000000e +#define SQ_S_SETPRIO 0x0000000f +#define SQ_S_SENDMSG 0x00000010 +#define SQ_S_SENDMSGHALT 0x00000011 +#define SQ_S_TRAP 0x00000012 +#define SQ_S_ICACHE_INV 0x00000013 +#define SQ_S_INCPERFLEVEL 0x00000014 +#define SQ_S_DECPERFLEVEL 0x00000015 +#define SQ_S_TTRACEDATA 0x00000016 +#define SQ_S_CBRANCH_CDBGSYS 0x00000017 +#define SQ_S_CBRANCH_CDBGUSER 0x00000018 +#define SQ_S_CBRANCH_CDBGSYS_OR_USER 0x00000019 +#define SQ_S_CBRANCH_CDBGSYS_AND_USER 0x0000001a +#define SQ_S_ENDPGM_SAVED 0x0000001b +#define SQ_S_SET_GPR_IDX_OFF 0x0000001c +#define SQ_S_SET_GPR_IDX_MODE 0x0000001d +#define SQ_S_ENDPGM_ORDERED_PS_DONE 0x0000001e + +/* + * VALUE_SQ_OP_EXP value + */ + +#define SQ_EXP 0x00000000 + +/* + * VALUE_SQ_SSRC_SPECIAL_POPS_EXITING_WAVE_ID value + */ + +#define SQ_SRC_POPS_EXITING_WAVE_ID 0x000000ef + +/* + * VALUE_SQ_XNACK_MASK_LOHI value + */ + +#define SQ_XNACK_MASK_LO 0x00000068 +#define SQ_XNACK_MASK_HI 0x00000069 + +/* + * VALUE_SQ_OMOD value + */ + +#define SQ_OMOD_OFF 0x00000000 +#define SQ_OMOD_M2 0x00000001 +#define SQ_OMOD_M4 0x00000002 +#define SQ_OMOD_D2 0x00000003 + +/* + * VALUE_SQ_SSRC_SPECIAL_EXECZ value + */ + +#define SQ_SRC_EXECZ 0x000000fc + +/* + * VALUE_SQ_COMPI value + */ + +#define SQ_F 0x00000000 +#define SQ_LT 0x00000001 +#define SQ_EQ 0x00000002 +#define SQ_LE 0x00000003 +#define SQ_GT 0x00000004 +#define SQ_NE 0x00000005 +#define SQ_GE 0x00000006 +#define SQ_T 0x00000007 + +/* + * VALUE_SQ_DPP_BOUND_CTRL value + */ + +#define SQ_DPP_BOUND_OFF 0x00000000 +#define SQ_DPP_BOUND_ZERO 0x00000001 + +/* + * VALUE_SQ_SDST_M0 value + */ + +#define SQ_M0 0x0000007c + +/* + * VALUE_SQ_MSG value + */ + +#define SQ_MSG_INTERRUPT 0x00000001 +#define SQ_MSG_GS 0x00000002 +#define SQ_MSG_GS_DONE 0x00000003 +#define SQ_MSG_SAVEWAVE 0x00000004 +#define SQ_MSG_STALL_WAVE_GEN 0x00000005 +#define SQ_MSG_HALT_WAVES 0x00000006 +#define SQ_MSG_ORDERED_PS_DONE 0x00000007 +#define SQ_MSG_EARLY_PRIM_DEALLOC 0x00000008 +#define SQ_MSG_GS_ALLOC_REQ 0x00000009 +#define SQ_MSG_SYSMSG 0x0000000f + +/* + * VALUE_SQ_PARAM value + */ + +#define SQ_PARAM_P10 0x00000000 +#define SQ_PARAM_P20 0x00000001 +#define SQ_PARAM_P0 0x00000002 + +/* + * VALUE_SQ_OPU_VOP3 value + */ + +#define SQ_V_OPC_OFFSET 0x00000000 +#define SQ_V_OP2_OFFSET 0x00000100 +#define SQ_V_OP1_OFFSET 0x00000140 +#define SQ_V_INTRP_OFFSET 0x00000270 +#define SQ_V_OP3P_OFFSET 0x00000380 + +/* + * VALUE_SQ_SSRC_SPECIAL_SDWA value + */ + +#define SQ_SRC_SDWA 0x000000f9 + +/* + * VALUE_SQ_SSRC_SPECIAL_APERTURE value + */ + +#define SQ_SRC_SHARED_BASE 0x000000eb +#define SQ_SRC_SHARED_LIMIT 0x000000ec +#define SQ_SRC_PRIVATE_BASE 0x000000ed +#define SQ_SRC_PRIVATE_LIMIT 0x000000ee + +/* + * VALUE_SQ_COMPF value + */ + +#define SQ_F 0x00000000 +#define SQ_LT 0x00000001 +#define SQ_EQ 0x00000002 +#define SQ_LE 0x00000003 +#define SQ_GT 0x00000004 +#define SQ_LG 0x00000005 +#define SQ_GE 0x00000006 +#define SQ_O 0x00000007 +#define SQ_U 0x00000008 +#define SQ_NGE 0x00000009 +#define SQ_NLG 0x0000000a +#define SQ_NGT 0x0000000b +#define SQ_NLE 0x0000000c +#define SQ_NEQ 0x0000000d +#define SQ_NLT 0x0000000e +#define SQ_TRU 0x0000000f + +/* + * VALUE_SQ_SDWA_UNUSED value + */ + +#define SQ_SDWA_UNUSED_PAD 0x00000000 +#define SQ_SDWA_UNUSED_SEXT 0x00000001 +#define SQ_SDWA_UNUSED_PRESERVE 0x00000002 + +/* + * VALUE_SQ_SSRC_SPECIAL_SCC value + */ + +#define SQ_SRC_SCC 0x000000fd + +/* + * VALUE_SQ_OP_VOPC value + */ + +#define SQ_V_CMP_CLASS_F32 0x00000010 +#define SQ_V_CMPX_CLASS_F32 0x00000011 +#define SQ_V_CMP_CLASS_F64 0x00000012 +#define SQ_V_CMPX_CLASS_F64 0x00000013 +#define SQ_V_CMP_CLASS_F16 0x00000014 +#define SQ_V_CMPX_CLASS_F16 0x00000015 +#define SQ_V_CMP_F_F16 0x00000020 +#define SQ_V_CMP_LT_F16 0x00000021 +#define SQ_V_CMP_EQ_F16 0x00000022 +#define SQ_V_CMP_LE_F16 0x00000023 +#define SQ_V_CMP_GT_F16 0x00000024 +#define SQ_V_CMP_LG_F16 0x00000025 +#define SQ_V_CMP_GE_F16 0x00000026 +#define SQ_V_CMP_O_F16 0x00000027 +#define SQ_V_CMP_U_F16 0x00000028 +#define SQ_V_CMP_NGE_F16 0x00000029 +#define SQ_V_CMP_NLG_F16 0x0000002a +#define SQ_V_CMP_NGT_F16 0x0000002b +#define SQ_V_CMP_NLE_F16 0x0000002c +#define SQ_V_CMP_NEQ_F16 0x0000002d +#define SQ_V_CMP_NLT_F16 0x0000002e +#define SQ_V_CMP_TRU_F16 0x0000002f +#define SQ_V_CMPX_F_F16 0x00000030 +#define SQ_V_CMPX_LT_F16 0x00000031 +#define SQ_V_CMPX_EQ_F16 0x00000032 +#define SQ_V_CMPX_LE_F16 0x00000033 +#define SQ_V_CMPX_GT_F16 0x00000034 +#define SQ_V_CMPX_LG_F16 0x00000035 +#define SQ_V_CMPX_GE_F16 0x00000036 +#define SQ_V_CMPX_O_F16 0x00000037 +#define SQ_V_CMPX_U_F16 0x00000038 +#define SQ_V_CMPX_NGE_F16 0x00000039 +#define SQ_V_CMPX_NLG_F16 0x0000003a +#define SQ_V_CMPX_NGT_F16 0x0000003b +#define SQ_V_CMPX_NLE_F16 0x0000003c +#define SQ_V_CMPX_NEQ_F16 0x0000003d +#define SQ_V_CMPX_NLT_F16 0x0000003e +#define SQ_V_CMPX_TRU_F16 0x0000003f +#define SQ_V_CMP_F_F32 0x00000040 +#define SQ_V_CMP_LT_F32 0x00000041 +#define SQ_V_CMP_EQ_F32 0x00000042 +#define SQ_V_CMP_LE_F32 0x00000043 +#define SQ_V_CMP_GT_F32 0x00000044 +#define SQ_V_CMP_LG_F32 0x00000045 +#define SQ_V_CMP_GE_F32 0x00000046 +#define SQ_V_CMP_O_F32 0x00000047 +#define SQ_V_CMP_U_F32 0x00000048 +#define SQ_V_CMP_NGE_F32 0x00000049 +#define SQ_V_CMP_NLG_F32 0x0000004a +#define SQ_V_CMP_NGT_F32 0x0000004b +#define SQ_V_CMP_NLE_F32 0x0000004c +#define SQ_V_CMP_NEQ_F32 0x0000004d +#define SQ_V_CMP_NLT_F32 0x0000004e +#define SQ_V_CMP_TRU_F32 0x0000004f +#define SQ_V_CMPX_F_F32 0x00000050 +#define SQ_V_CMPX_LT_F32 0x00000051 +#define SQ_V_CMPX_EQ_F32 0x00000052 +#define SQ_V_CMPX_LE_F32 0x00000053 +#define SQ_V_CMPX_GT_F32 0x00000054 +#define SQ_V_CMPX_LG_F32 0x00000055 +#define SQ_V_CMPX_GE_F32 0x00000056 +#define SQ_V_CMPX_O_F32 0x00000057 +#define SQ_V_CMPX_U_F32 0x00000058 +#define SQ_V_CMPX_NGE_F32 0x00000059 +#define SQ_V_CMPX_NLG_F32 0x0000005a +#define SQ_V_CMPX_NGT_F32 0x0000005b +#define SQ_V_CMPX_NLE_F32 0x0000005c +#define SQ_V_CMPX_NEQ_F32 0x0000005d +#define SQ_V_CMPX_NLT_F32 0x0000005e +#define SQ_V_CMPX_TRU_F32 0x0000005f +#define SQ_V_CMP_F_F64 0x00000060 +#define SQ_V_CMP_LT_F64 0x00000061 +#define SQ_V_CMP_EQ_F64 0x00000062 +#define SQ_V_CMP_LE_F64 0x00000063 +#define SQ_V_CMP_GT_F64 0x00000064 +#define SQ_V_CMP_LG_F64 0x00000065 +#define SQ_V_CMP_GE_F64 0x00000066 +#define SQ_V_CMP_O_F64 0x00000067 +#define SQ_V_CMP_U_F64 0x00000068 +#define SQ_V_CMP_NGE_F64 0x00000069 +#define SQ_V_CMP_NLG_F64 0x0000006a +#define SQ_V_CMP_NGT_F64 0x0000006b +#define SQ_V_CMP_NLE_F64 0x0000006c +#define SQ_V_CMP_NEQ_F64 0x0000006d +#define SQ_V_CMP_NLT_F64 0x0000006e +#define SQ_V_CMP_TRU_F64 0x0000006f +#define SQ_V_CMPX_F_F64 0x00000070 +#define SQ_V_CMPX_LT_F64 0x00000071 +#define SQ_V_CMPX_EQ_F64 0x00000072 +#define SQ_V_CMPX_LE_F64 0x00000073 +#define SQ_V_CMPX_GT_F64 0x00000074 +#define SQ_V_CMPX_LG_F64 0x00000075 +#define SQ_V_CMPX_GE_F64 0x00000076 +#define SQ_V_CMPX_O_F64 0x00000077 +#define SQ_V_CMPX_U_F64 0x00000078 +#define SQ_V_CMPX_NGE_F64 0x00000079 +#define SQ_V_CMPX_NLG_F64 0x0000007a +#define SQ_V_CMPX_NGT_F64 0x0000007b +#define SQ_V_CMPX_NLE_F64 0x0000007c +#define SQ_V_CMPX_NEQ_F64 0x0000007d +#define SQ_V_CMPX_NLT_F64 0x0000007e +#define SQ_V_CMPX_TRU_F64 0x0000007f +#define SQ_V_CMP_F_I16 0x000000a0 +#define SQ_V_CMP_LT_I16 0x000000a1 +#define SQ_V_CMP_EQ_I16 0x000000a2 +#define SQ_V_CMP_LE_I16 0x000000a3 +#define SQ_V_CMP_GT_I16 0x000000a4 +#define SQ_V_CMP_NE_I16 0x000000a5 +#define SQ_V_CMP_GE_I16 0x000000a6 +#define SQ_V_CMP_T_I16 0x000000a7 +#define SQ_V_CMP_F_U16 0x000000a8 +#define SQ_V_CMP_LT_U16 0x000000a9 +#define SQ_V_CMP_EQ_U16 0x000000aa +#define SQ_V_CMP_LE_U16 0x000000ab +#define SQ_V_CMP_GT_U16 0x000000ac +#define SQ_V_CMP_NE_U16 0x000000ad +#define SQ_V_CMP_GE_U16 0x000000ae +#define SQ_V_CMP_T_U16 0x000000af +#define SQ_V_CMPX_F_I16 0x000000b0 +#define SQ_V_CMPX_LT_I16 0x000000b1 +#define SQ_V_CMPX_EQ_I16 0x000000b2 +#define SQ_V_CMPX_LE_I16 0x000000b3 +#define SQ_V_CMPX_GT_I16 0x000000b4 +#define SQ_V_CMPX_NE_I16 0x000000b5 +#define SQ_V_CMPX_GE_I16 0x000000b6 +#define SQ_V_CMPX_T_I16 0x000000b7 +#define SQ_V_CMPX_F_U16 0x000000b8 +#define SQ_V_CMPX_LT_U16 0x000000b9 +#define SQ_V_CMPX_EQ_U16 0x000000ba +#define SQ_V_CMPX_LE_U16 0x000000bb +#define SQ_V_CMPX_GT_U16 0x000000bc +#define SQ_V_CMPX_NE_U16 0x000000bd +#define SQ_V_CMPX_GE_U16 0x000000be +#define SQ_V_CMPX_T_U16 0x000000bf +#define SQ_V_CMP_F_I32 0x000000c0 +#define SQ_V_CMP_LT_I32 0x000000c1 +#define SQ_V_CMP_EQ_I32 0x000000c2 +#define SQ_V_CMP_LE_I32 0x000000c3 +#define SQ_V_CMP_GT_I32 0x000000c4 +#define SQ_V_CMP_NE_I32 0x000000c5 +#define SQ_V_CMP_GE_I32 0x000000c6 +#define SQ_V_CMP_T_I32 0x000000c7 +#define SQ_V_CMP_F_U32 0x000000c8 +#define SQ_V_CMP_LT_U32 0x000000c9 +#define SQ_V_CMP_EQ_U32 0x000000ca +#define SQ_V_CMP_LE_U32 0x000000cb +#define SQ_V_CMP_GT_U32 0x000000cc +#define SQ_V_CMP_NE_U32 0x000000cd +#define SQ_V_CMP_GE_U32 0x000000ce +#define SQ_V_CMP_T_U32 0x000000cf +#define SQ_V_CMPX_F_I32 0x000000d0 +#define SQ_V_CMPX_LT_I32 0x000000d1 +#define SQ_V_CMPX_EQ_I32 0x000000d2 +#define SQ_V_CMPX_LE_I32 0x000000d3 +#define SQ_V_CMPX_GT_I32 0x000000d4 +#define SQ_V_CMPX_NE_I32 0x000000d5 +#define SQ_V_CMPX_GE_I32 0x000000d6 +#define SQ_V_CMPX_T_I32 0x000000d7 +#define SQ_V_CMPX_F_U32 0x000000d8 +#define SQ_V_CMPX_LT_U32 0x000000d9 +#define SQ_V_CMPX_EQ_U32 0x000000da +#define SQ_V_CMPX_LE_U32 0x000000db +#define SQ_V_CMPX_GT_U32 0x000000dc +#define SQ_V_CMPX_NE_U32 0x000000dd +#define SQ_V_CMPX_GE_U32 0x000000de +#define SQ_V_CMPX_T_U32 0x000000df +#define SQ_V_CMP_F_I64 0x000000e0 +#define SQ_V_CMP_LT_I64 0x000000e1 +#define SQ_V_CMP_EQ_I64 0x000000e2 +#define SQ_V_CMP_LE_I64 0x000000e3 +#define SQ_V_CMP_GT_I64 0x000000e4 +#define SQ_V_CMP_NE_I64 0x000000e5 +#define SQ_V_CMP_GE_I64 0x000000e6 +#define SQ_V_CMP_T_I64 0x000000e7 +#define SQ_V_CMP_F_U64 0x000000e8 +#define SQ_V_CMP_LT_U64 0x000000e9 +#define SQ_V_CMP_EQ_U64 0x000000ea +#define SQ_V_CMP_LE_U64 0x000000eb +#define SQ_V_CMP_GT_U64 0x000000ec +#define SQ_V_CMP_NE_U64 0x000000ed +#define SQ_V_CMP_GE_U64 0x000000ee +#define SQ_V_CMP_T_U64 0x000000ef +#define SQ_V_CMPX_F_I64 0x000000f0 +#define SQ_V_CMPX_LT_I64 0x000000f1 +#define SQ_V_CMPX_EQ_I64 0x000000f2 +#define SQ_V_CMPX_LE_I64 0x000000f3 +#define SQ_V_CMPX_GT_I64 0x000000f4 +#define SQ_V_CMPX_NE_I64 0x000000f5 +#define SQ_V_CMPX_GE_I64 0x000000f6 +#define SQ_V_CMPX_T_I64 0x000000f7 +#define SQ_V_CMPX_F_U64 0x000000f8 +#define SQ_V_CMPX_LT_U64 0x000000f9 +#define SQ_V_CMPX_EQ_U64 0x000000fa +#define SQ_V_CMPX_LE_U64 0x000000fb +#define SQ_V_CMPX_GT_U64 0x000000fc +#define SQ_V_CMPX_NE_U64 0x000000fd +#define SQ_V_CMPX_GE_U64 0x000000fe +#define SQ_V_CMPX_T_U64 0x000000ff + +/* + * VALUE_SQ_GS_OP value + */ + +#define SQ_GS_OP_NOP 0x00000000 +#define SQ_GS_OP_CUT 0x00000001 +#define SQ_GS_OP_EMIT 0x00000002 +#define SQ_GS_OP_EMIT_CUT 0x00000003 + +/* + * VALUE_SQ_SSRC_SPECIAL_LDS value + */ + +#define SQ_SRC_LDS_DIRECT 0x000000fe + +/* + * VALUE_SQ_ATTR value + */ + +#define SQ_ATTR0 0x00000000 + +/* + * VALUE_SQ_TGT_INTERNAL value + */ + +#define SQ_EXP_GDS0 0x00000018 + +/* + * VALUE_SQ_OP_SOPC value + */ + +#define SQ_S_CMP_EQ_I32 0x00000000 +#define SQ_S_CMP_LG_I32 0x00000001 +#define SQ_S_CMP_GT_I32 0x00000002 +#define SQ_S_CMP_GE_I32 0x00000003 +#define SQ_S_CMP_LT_I32 0x00000004 +#define SQ_S_CMP_LE_I32 0x00000005 +#define SQ_S_CMP_EQ_U32 0x00000006 +#define SQ_S_CMP_LG_U32 0x00000007 +#define SQ_S_CMP_GT_U32 0x00000008 +#define SQ_S_CMP_GE_U32 0x00000009 +#define SQ_S_CMP_LT_U32 0x0000000a +#define SQ_S_CMP_LE_U32 0x0000000b +#define SQ_S_BITCMP0_B32 0x0000000c +#define SQ_S_BITCMP1_B32 0x0000000d +#define SQ_S_BITCMP0_B64 0x0000000e +#define SQ_S_BITCMP1_B64 0x0000000f +#define SQ_S_SETVSKIP 0x00000010 +#define SQ_S_SET_GPR_IDX_ON 0x00000011 +#define SQ_S_CMP_EQ_U64 0x00000012 +#define SQ_S_CMP_LG_U64 0x00000013 + +/* + * VALUE_SQ_TRAP value + */ + +#define SQ_TTMP0 0x0000006c +#define SQ_TTMP1 0x0000006d +#define SQ_TTMP2 0x0000006e +#define SQ_TTMP3 0x0000006f +#define SQ_TTMP4 0x00000070 +#define SQ_TTMP5 0x00000071 +#define SQ_TTMP6 0x00000072 +#define SQ_TTMP7 0x00000073 +#define SQ_TTMP8 0x00000074 +#define SQ_TTMP9 0x00000075 +#define SQ_TTMP10 0x00000076 +#define SQ_TTMP11 0x00000077 +#define SQ_TTMP12 0x00000078 +#define SQ_TTMP13 0x00000079 +#define SQ_TTMP14 0x0000007a +#define SQ_TTMP15 0x0000007b + +/* + * VALUE_SQ_SRC_VGPR value + */ + +#define SQ_SRC_VGPR0 0x00000100 + +/* + * VALUE_SQ_OP_MUBUF value + */ + +#define SQ_BUFFER_LOAD_FORMAT_X 0x00000000 +#define SQ_BUFFER_LOAD_FORMAT_XY 0x00000001 +#define SQ_BUFFER_LOAD_FORMAT_XYZ 0x00000002 +#define SQ_BUFFER_LOAD_FORMAT_XYZW 0x00000003 +#define SQ_BUFFER_STORE_FORMAT_X 0x00000004 +#define SQ_BUFFER_STORE_FORMAT_XY 0x00000005 +#define SQ_BUFFER_STORE_FORMAT_XYZ 0x00000006 +#define SQ_BUFFER_STORE_FORMAT_XYZW 0x00000007 +#define SQ_BUFFER_LOAD_FORMAT_D16_X 0x00000008 +#define SQ_BUFFER_LOAD_FORMAT_D16_XY 0x00000009 +#define SQ_BUFFER_LOAD_FORMAT_D16_XYZ 0x0000000a +#define SQ_BUFFER_LOAD_FORMAT_D16_XYZW 0x0000000b +#define SQ_BUFFER_STORE_FORMAT_D16_X 0x0000000c +#define SQ_BUFFER_STORE_FORMAT_D16_XY 0x0000000d +#define SQ_BUFFER_STORE_FORMAT_D16_XYZ 0x0000000e +#define SQ_BUFFER_STORE_FORMAT_D16_XYZW 0x0000000f +#define SQ_BUFFER_LOAD_UBYTE 0x00000010 +#define SQ_BUFFER_LOAD_SBYTE 0x00000011 +#define SQ_BUFFER_LOAD_USHORT 0x00000012 +#define SQ_BUFFER_LOAD_SSHORT 0x00000013 +#define SQ_BUFFER_LOAD_DWORD 0x00000014 +#define SQ_BUFFER_LOAD_DWORDX2 0x00000015 +#define SQ_BUFFER_LOAD_DWORDX3 0x00000016 +#define SQ_BUFFER_LOAD_DWORDX4 0x00000017 +#define SQ_BUFFER_STORE_BYTE 0x00000018 +#define SQ_BUFFER_STORE_SHORT 0x0000001a +#define SQ_BUFFER_STORE_DWORD 0x0000001c +#define SQ_BUFFER_STORE_DWORDX2 0x0000001d +#define SQ_BUFFER_STORE_DWORDX3 0x0000001e +#define SQ_BUFFER_STORE_DWORDX4 0x0000001f +#define SQ_BUFFER_STORE_LDS_DWORD 0x0000003d +#define SQ_BUFFER_WBINVL1 0x0000003e +#define SQ_BUFFER_WBINVL1_VOL 0x0000003f +#define SQ_BUFFER_ATOMIC_SWAP 0x00000040 +#define SQ_BUFFER_ATOMIC_CMPSWAP 0x00000041 +#define SQ_BUFFER_ATOMIC_ADD 0x00000042 +#define SQ_BUFFER_ATOMIC_SUB 0x00000043 +#define SQ_BUFFER_ATOMIC_SMIN 0x00000044 +#define SQ_BUFFER_ATOMIC_UMIN 0x00000045 +#define SQ_BUFFER_ATOMIC_SMAX 0x00000046 +#define SQ_BUFFER_ATOMIC_UMAX 0x00000047 +#define SQ_BUFFER_ATOMIC_AND 0x00000048 +#define SQ_BUFFER_ATOMIC_OR 0x00000049 +#define SQ_BUFFER_ATOMIC_XOR 0x0000004a +#define SQ_BUFFER_ATOMIC_INC 0x0000004b +#define SQ_BUFFER_ATOMIC_DEC 0x0000004c +#define SQ_BUFFER_ATOMIC_SWAP_X2 0x00000060 +#define SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x00000061 +#define SQ_BUFFER_ATOMIC_ADD_X2 0x00000062 +#define SQ_BUFFER_ATOMIC_SUB_X2 0x00000063 +#define SQ_BUFFER_ATOMIC_SMIN_X2 0x00000064 +#define SQ_BUFFER_ATOMIC_UMIN_X2 0x00000065 +#define SQ_BUFFER_ATOMIC_SMAX_X2 0x00000066 +#define SQ_BUFFER_ATOMIC_UMAX_X2 0x00000067 +#define SQ_BUFFER_ATOMIC_AND_X2 0x00000068 +#define SQ_BUFFER_ATOMIC_OR_X2 0x00000069 +#define SQ_BUFFER_ATOMIC_XOR_X2 0x0000006a +#define SQ_BUFFER_ATOMIC_INC_X2 0x0000006b +#define SQ_BUFFER_ATOMIC_DEC_X2 0x0000006c + +/* + * VALUE_SQ_SDWA_SEL value + */ + +#define SQ_SDWA_BYTE_0 0x00000000 +#define SQ_SDWA_BYTE_1 0x00000001 +#define SQ_SDWA_BYTE_2 0x00000002 +#define SQ_SDWA_BYTE_3 0x00000003 +#define SQ_SDWA_WORD_0 0x00000004 +#define SQ_SDWA_WORD_1 0x00000005 +#define SQ_SDWA_DWORD 0x00000006 + +/******************************************************* + * SX Enums + *******************************************************/ + +/* + * SX_BLEND_OPT enum + */ + +typedef enum SX_BLEND_OPT { +BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0x00000000, +BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 0x00000001, +BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 0x00000002, +BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 0x00000003, +BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 0x00000004, +BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 0x00000005, +BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 0x00000006, +BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 0x00000007, +} SX_BLEND_OPT; + +/* + * SX_OPT_COMB_FCN enum + */ + +typedef enum SX_OPT_COMB_FCN { +OPT_COMB_NONE = 0x00000000, +OPT_COMB_ADD = 0x00000001, +OPT_COMB_SUBTRACT = 0x00000002, +OPT_COMB_MIN = 0x00000003, +OPT_COMB_MAX = 0x00000004, +OPT_COMB_REVSUBTRACT = 0x00000005, +OPT_COMB_BLEND_DISABLED = 0x00000006, +OPT_COMB_SAFE_ADD = 0x00000007, +} SX_OPT_COMB_FCN; + +/* + * SX_DOWNCONVERT_FORMAT enum + */ + +typedef enum SX_DOWNCONVERT_FORMAT { +SX_RT_EXPORT_NO_CONVERSION = 0x00000000, +SX_RT_EXPORT_32_R = 0x00000001, +SX_RT_EXPORT_32_A = 0x00000002, +SX_RT_EXPORT_10_11_11 = 0x00000003, +SX_RT_EXPORT_2_10_10_10 = 0x00000004, +SX_RT_EXPORT_8_8_8_8 = 0x00000005, +SX_RT_EXPORT_5_6_5 = 0x00000006, +SX_RT_EXPORT_1_5_5_5 = 0x00000007, +SX_RT_EXPORT_4_4_4_4 = 0x00000008, +SX_RT_EXPORT_16_16_GR = 0x00000009, +SX_RT_EXPORT_16_16_AR = 0x0000000a, +} SX_DOWNCONVERT_FORMAT; + +/* + * SX_PERFCOUNTER_VALS enum + */ + +typedef enum SX_PERFCOUNTER_VALS { +SX_PERF_SEL_PA_IDLE_CYCLES = 0x00000000, +SX_PERF_SEL_PA_REQ = 0x00000001, +SX_PERF_SEL_PA_POS = 0x00000002, +SX_PERF_SEL_CLOCK = 0x00000003, +SX_PERF_SEL_GATE_EN1 = 0x00000004, +SX_PERF_SEL_GATE_EN2 = 0x00000005, +SX_PERF_SEL_GATE_EN3 = 0x00000006, +SX_PERF_SEL_GATE_EN4 = 0x00000007, +SX_PERF_SEL_SH_POS_STARVE = 0x00000008, +SX_PERF_SEL_SH_COLOR_STARVE = 0x00000009, +SX_PERF_SEL_SH_POS_STALL = 0x0000000a, +SX_PERF_SEL_SH_COLOR_STALL = 0x0000000b, +SX_PERF_SEL_DB0_PIXELS = 0x0000000c, +SX_PERF_SEL_DB0_HALF_QUADS = 0x0000000d, +SX_PERF_SEL_DB0_PIXEL_STALL = 0x0000000e, +SX_PERF_SEL_DB0_PIXEL_IDLE = 0x0000000f, +SX_PERF_SEL_DB0_PRED_PIXELS = 0x00000010, +SX_PERF_SEL_DB1_PIXELS = 0x00000011, +SX_PERF_SEL_DB1_HALF_QUADS = 0x00000012, +SX_PERF_SEL_DB1_PIXEL_STALL = 0x00000013, +SX_PERF_SEL_DB1_PIXEL_IDLE = 0x00000014, +SX_PERF_SEL_DB1_PRED_PIXELS = 0x00000015, +SX_PERF_SEL_DB2_PIXELS = 0x00000016, +SX_PERF_SEL_DB2_HALF_QUADS = 0x00000017, +SX_PERF_SEL_DB2_PIXEL_STALL = 0x00000018, +SX_PERF_SEL_DB2_PIXEL_IDLE = 0x00000019, +SX_PERF_SEL_DB2_PRED_PIXELS = 0x0000001a, +SX_PERF_SEL_DB3_PIXELS = 0x0000001b, +SX_PERF_SEL_DB3_HALF_QUADS = 0x0000001c, +SX_PERF_SEL_DB3_PIXEL_STALL = 0x0000001d, +SX_PERF_SEL_DB3_PIXEL_IDLE = 0x0000001e, +SX_PERF_SEL_DB3_PRED_PIXELS = 0x0000001f, +SX_PERF_SEL_COL_BUSY = 0x00000020, +SX_PERF_SEL_POS_BUSY = 0x00000021, +SX_PERF_SEL_DB0_A2M_DISCARD_QUADS = 0x00000022, +SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS = 0x00000023, +SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST = 0x00000024, +SX_PERF_SEL_DB0_MRT0_DISCARD_SRC = 0x00000025, +SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS = 0x00000026, +SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS = 0x00000027, +SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS = 0x00000028, +SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST = 0x00000029, +SX_PERF_SEL_DB0_MRT1_DISCARD_SRC = 0x0000002a, +SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS = 0x0000002b, +SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS = 0x0000002c, +SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS = 0x0000002d, +SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST = 0x0000002e, +SX_PERF_SEL_DB0_MRT2_DISCARD_SRC = 0x0000002f, +SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS = 0x00000030, +SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS = 0x00000031, +SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS = 0x00000032, +SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST = 0x00000033, +SX_PERF_SEL_DB0_MRT3_DISCARD_SRC = 0x00000034, +SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS = 0x00000035, +SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS = 0x00000036, +SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS = 0x00000037, +SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST = 0x00000038, +SX_PERF_SEL_DB0_MRT4_DISCARD_SRC = 0x00000039, +SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS = 0x0000003a, +SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS = 0x0000003b, +SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS = 0x0000003c, +SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST = 0x0000003d, +SX_PERF_SEL_DB0_MRT5_DISCARD_SRC = 0x0000003e, +SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS = 0x0000003f, +SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS = 0x00000040, +SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS = 0x00000041, +SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST = 0x00000042, +SX_PERF_SEL_DB0_MRT6_DISCARD_SRC = 0x00000043, +SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS = 0x00000044, +SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS = 0x00000045, +SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS = 0x00000046, +SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST = 0x00000047, +SX_PERF_SEL_DB0_MRT7_DISCARD_SRC = 0x00000048, +SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS = 0x00000049, +SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS = 0x0000004a, +SX_PERF_SEL_DB1_A2M_DISCARD_QUADS = 0x0000004b, +SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS = 0x0000004c, +SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST = 0x0000004d, +SX_PERF_SEL_DB1_MRT0_DISCARD_SRC = 0x0000004e, +SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS = 0x0000004f, +SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS = 0x00000050, +SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS = 0x00000051, +SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST = 0x00000052, +SX_PERF_SEL_DB1_MRT1_DISCARD_SRC = 0x00000053, +SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS = 0x00000054, +SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS = 0x00000055, +SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS = 0x00000056, +SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST = 0x00000057, +SX_PERF_SEL_DB1_MRT2_DISCARD_SRC = 0x00000058, +SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS = 0x00000059, +SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS = 0x0000005a, +SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS = 0x0000005b, +SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST = 0x0000005c, +SX_PERF_SEL_DB1_MRT3_DISCARD_SRC = 0x0000005d, +SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS = 0x0000005e, +SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS = 0x0000005f, +SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS = 0x00000060, +SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST = 0x00000061, +SX_PERF_SEL_DB1_MRT4_DISCARD_SRC = 0x00000062, +SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS = 0x00000063, +SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS = 0x00000064, +SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS = 0x00000065, +SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST = 0x00000066, +SX_PERF_SEL_DB1_MRT5_DISCARD_SRC = 0x00000067, +SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS = 0x00000068, +SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS = 0x00000069, +SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS = 0x0000006a, +SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST = 0x0000006b, +SX_PERF_SEL_DB1_MRT6_DISCARD_SRC = 0x0000006c, +SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS = 0x0000006d, +SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS = 0x0000006e, +SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS = 0x0000006f, +SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST = 0x00000070, +SX_PERF_SEL_DB1_MRT7_DISCARD_SRC = 0x00000071, +SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS = 0x00000072, +SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS = 0x00000073, +SX_PERF_SEL_DB2_A2M_DISCARD_QUADS = 0x00000074, +SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS = 0x00000075, +SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST = 0x00000076, +SX_PERF_SEL_DB2_MRT0_DISCARD_SRC = 0x00000077, +SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS = 0x00000078, +SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS = 0x00000079, +SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS = 0x0000007a, +SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST = 0x0000007b, +SX_PERF_SEL_DB2_MRT1_DISCARD_SRC = 0x0000007c, +SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS = 0x0000007d, +SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS = 0x0000007e, +SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS = 0x0000007f, +SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST = 0x00000080, +SX_PERF_SEL_DB2_MRT2_DISCARD_SRC = 0x00000081, +SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS = 0x00000082, +SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS = 0x00000083, +SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS = 0x00000084, +SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST = 0x00000085, +SX_PERF_SEL_DB2_MRT3_DISCARD_SRC = 0x00000086, +SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS = 0x00000087, +SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS = 0x00000088, +SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS = 0x00000089, +SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST = 0x0000008a, +SX_PERF_SEL_DB2_MRT4_DISCARD_SRC = 0x0000008b, +SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS = 0x0000008c, +SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS = 0x0000008d, +SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS = 0x0000008e, +SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST = 0x0000008f, +SX_PERF_SEL_DB2_MRT5_DISCARD_SRC = 0x00000090, +SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS = 0x00000091, +SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS = 0x00000092, +SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS = 0x00000093, +SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST = 0x00000094, +SX_PERF_SEL_DB2_MRT6_DISCARD_SRC = 0x00000095, +SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS = 0x00000096, +SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS = 0x00000097, +SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS = 0x00000098, +SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST = 0x00000099, +SX_PERF_SEL_DB2_MRT7_DISCARD_SRC = 0x0000009a, +SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS = 0x0000009b, +SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS = 0x0000009c, +SX_PERF_SEL_DB3_A2M_DISCARD_QUADS = 0x0000009d, +SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS = 0x0000009e, +SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST = 0x0000009f, +SX_PERF_SEL_DB3_MRT0_DISCARD_SRC = 0x000000a0, +SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS = 0x000000a1, +SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS = 0x000000a2, +SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS = 0x000000a3, +SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST = 0x000000a4, +SX_PERF_SEL_DB3_MRT1_DISCARD_SRC = 0x000000a5, +SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS = 0x000000a6, +SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS = 0x000000a7, +SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS = 0x000000a8, +SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST = 0x000000a9, +SX_PERF_SEL_DB3_MRT2_DISCARD_SRC = 0x000000aa, +SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS = 0x000000ab, +SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS = 0x000000ac, +SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS = 0x000000ad, +SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST = 0x000000ae, +SX_PERF_SEL_DB3_MRT3_DISCARD_SRC = 0x000000af, +SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS = 0x000000b0, +SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS = 0x000000b1, +SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS = 0x000000b2, +SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST = 0x000000b3, +SX_PERF_SEL_DB3_MRT4_DISCARD_SRC = 0x000000b4, +SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS = 0x000000b5, +SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS = 0x000000b6, +SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS = 0x000000b7, +SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST = 0x000000b8, +SX_PERF_SEL_DB3_MRT5_DISCARD_SRC = 0x000000b9, +SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS = 0x000000ba, +SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS = 0x000000bb, +SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS = 0x000000bc, +SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST = 0x000000bd, +SX_PERF_SEL_DB3_MRT6_DISCARD_SRC = 0x000000be, +SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS = 0x000000bf, +SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS = 0x000000c0, +SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS = 0x000000c1, +SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST = 0x000000c2, +SX_PERF_SEL_DB3_MRT7_DISCARD_SRC = 0x000000c3, +SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS = 0x000000c4, +SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS = 0x000000c5, +} SX_PERFCOUNTER_VALS; + +/******************************************************* + * DB Enums + *******************************************************/ + +/* + * ForceControl enum + */ + +typedef enum ForceControl { +FORCE_OFF = 0x00000000, +FORCE_ENABLE = 0x00000001, +FORCE_DISABLE = 0x00000002, +FORCE_RESERVED = 0x00000003, +} ForceControl; + +/* + * ZSamplePosition enum + */ + +typedef enum ZSamplePosition { +Z_SAMPLE_CENTER = 0x00000000, +Z_SAMPLE_CENTROID = 0x00000001, +} ZSamplePosition; + +/* + * ZOrder enum + */ + +typedef enum ZOrder { +LATE_Z = 0x00000000, +EARLY_Z_THEN_LATE_Z = 0x00000001, +RE_Z = 0x00000002, +EARLY_Z_THEN_RE_Z = 0x00000003, +} ZOrder; + +/* + * ZpassControl enum + */ + +typedef enum ZpassControl { +ZPASS_DISABLE = 0x00000000, +ZPASS_SAMPLES = 0x00000001, +ZPASS_PIXELS = 0x00000002, +} ZpassControl; + +/* + * ZModeForce enum + */ + +typedef enum ZModeForce { +NO_FORCE = 0x00000000, +FORCE_EARLY_Z = 0x00000001, +FORCE_LATE_Z = 0x00000002, +FORCE_RE_Z = 0x00000003, +} ZModeForce; + +/* + * ZLimitSumm enum + */ + +typedef enum ZLimitSumm { +FORCE_SUMM_OFF = 0x00000000, +FORCE_SUMM_MINZ = 0x00000001, +FORCE_SUMM_MAXZ = 0x00000002, +FORCE_SUMM_BOTH = 0x00000003, +} ZLimitSumm; + +/* + * CompareFrag enum + */ + +typedef enum CompareFrag { +FRAG_NEVER = 0x00000000, +FRAG_LESS = 0x00000001, +FRAG_EQUAL = 0x00000002, +FRAG_LEQUAL = 0x00000003, +FRAG_GREATER = 0x00000004, +FRAG_NOTEQUAL = 0x00000005, +FRAG_GEQUAL = 0x00000006, +FRAG_ALWAYS = 0x00000007, +} CompareFrag; + +/* + * StencilOp enum + */ + +typedef enum StencilOp { +STENCIL_KEEP = 0x00000000, +STENCIL_ZERO = 0x00000001, +STENCIL_ONES = 0x00000002, +STENCIL_REPLACE_TEST = 0x00000003, +STENCIL_REPLACE_OP = 0x00000004, +STENCIL_ADD_CLAMP = 0x00000005, +STENCIL_SUB_CLAMP = 0x00000006, +STENCIL_INVERT = 0x00000007, +STENCIL_ADD_WRAP = 0x00000008, +STENCIL_SUB_WRAP = 0x00000009, +STENCIL_AND = 0x0000000a, +STENCIL_OR = 0x0000000b, +STENCIL_XOR = 0x0000000c, +STENCIL_NAND = 0x0000000d, +STENCIL_NOR = 0x0000000e, +STENCIL_XNOR = 0x0000000f, +} StencilOp; + +/* + * ConservativeZExport enum + */ + +typedef enum ConservativeZExport { +EXPORT_ANY_Z = 0x00000000, +EXPORT_LESS_THAN_Z = 0x00000001, +EXPORT_GREATER_THAN_Z = 0x00000002, +EXPORT_RESERVED = 0x00000003, +} ConservativeZExport; + +/* + * DbPSLControl enum + */ + +typedef enum DbPSLControl { +PSLC_AUTO = 0x00000000, +PSLC_ON_HANG_ONLY = 0x00000001, +PSLC_ASAP = 0x00000002, +PSLC_COUNTDOWN = 0x00000003, +} DbPSLControl; + +/* + * DbPRTFaultBehavior enum + */ + +typedef enum DbPRTFaultBehavior { +FAULT_ZERO = 0x00000000, +FAULT_ONE = 0x00000001, +FAULT_FAIL = 0x00000002, +FAULT_PASS = 0x00000003, +} DbPRTFaultBehavior; + +/* + * PerfCounter_Vals enum + */ + +typedef enum PerfCounter_Vals { +DB_PERF_SEL_SC_DB_tile_sends = 0x00000000, +DB_PERF_SEL_SC_DB_tile_busy = 0x00000001, +DB_PERF_SEL_SC_DB_tile_stalls = 0x00000002, +DB_PERF_SEL_SC_DB_tile_events = 0x00000003, +DB_PERF_SEL_SC_DB_tile_tiles = 0x00000004, +DB_PERF_SEL_SC_DB_tile_covered = 0x00000005, +DB_PERF_SEL_hiz_tc_read_starved = 0x00000006, +DB_PERF_SEL_hiz_tc_write_stall = 0x00000007, +DB_PERF_SEL_hiz_qtiles_culled = 0x00000008, +DB_PERF_SEL_his_qtiles_culled = 0x00000009, +DB_PERF_SEL_DB_SC_tile_sends = 0x0000000a, +DB_PERF_SEL_DB_SC_tile_busy = 0x0000000b, +DB_PERF_SEL_DB_SC_tile_stalls = 0x0000000c, +DB_PERF_SEL_DB_SC_tile_df_stalls = 0x0000000d, +DB_PERF_SEL_DB_SC_tile_tiles = 0x0000000e, +DB_PERF_SEL_DB_SC_tile_culled = 0x0000000f, +DB_PERF_SEL_DB_SC_tile_hier_kill = 0x00000010, +DB_PERF_SEL_DB_SC_tile_fast_ops = 0x00000011, +DB_PERF_SEL_DB_SC_tile_no_ops = 0x00000012, +DB_PERF_SEL_DB_SC_tile_tile_rate = 0x00000013, +DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x00000014, +DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x00000015, +DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x00000016, +DB_PERF_SEL_SC_DB_quad_sends = 0x00000017, +DB_PERF_SEL_SC_DB_quad_busy = 0x00000018, +DB_PERF_SEL_SC_DB_quad_squads = 0x00000019, +DB_PERF_SEL_SC_DB_quad_tiles = 0x0000001a, +DB_PERF_SEL_SC_DB_quad_pixels = 0x0000001b, +DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x0000001c, +DB_PERF_SEL_DB_SC_quad_sends = 0x0000001d, +DB_PERF_SEL_DB_SC_quad_busy = 0x0000001e, +DB_PERF_SEL_DB_SC_quad_stalls = 0x0000001f, +DB_PERF_SEL_DB_SC_quad_tiles = 0x00000020, +DB_PERF_SEL_DB_SC_quad_lit_quad = 0x00000021, +DB_PERF_SEL_DB_CB_tile_sends = 0x00000022, +DB_PERF_SEL_DB_CB_tile_busy = 0x00000023, +DB_PERF_SEL_DB_CB_tile_stalls = 0x00000024, +DB_PERF_SEL_SX_DB_quad_sends = 0x00000025, +DB_PERF_SEL_SX_DB_quad_busy = 0x00000026, +DB_PERF_SEL_SX_DB_quad_stalls = 0x00000027, +DB_PERF_SEL_SX_DB_quad_quads = 0x00000028, +DB_PERF_SEL_SX_DB_quad_pixels = 0x00000029, +DB_PERF_SEL_SX_DB_quad_exports = 0x0000002a, +DB_PERF_SEL_SH_quads_outstanding_sum = 0x0000002b, +DB_PERF_SEL_DB_CB_lquad_sends = 0x0000002c, +DB_PERF_SEL_DB_CB_lquad_busy = 0x0000002d, +DB_PERF_SEL_DB_CB_lquad_stalls = 0x0000002e, +DB_PERF_SEL_DB_CB_lquad_quads = 0x0000002f, +DB_PERF_SEL_tile_rd_sends = 0x00000030, +DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x00000031, +DB_PERF_SEL_quad_rd_sends = 0x00000032, +DB_PERF_SEL_quad_rd_busy = 0x00000033, +DB_PERF_SEL_quad_rd_mi_stall = 0x00000034, +DB_PERF_SEL_quad_rd_rw_collision = 0x00000035, +DB_PERF_SEL_quad_rd_tag_stall = 0x00000036, +DB_PERF_SEL_quad_rd_32byte_reqs = 0x00000037, +DB_PERF_SEL_quad_rd_panic = 0x00000038, +DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x00000039, +DB_PERF_SEL_quad_rdret_sends = 0x0000003a, +DB_PERF_SEL_quad_rdret_busy = 0x0000003b, +DB_PERF_SEL_tile_wr_sends = 0x0000003c, +DB_PERF_SEL_tile_wr_acks = 0x0000003d, +DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x0000003e, +DB_PERF_SEL_quad_wr_sends = 0x0000003f, +DB_PERF_SEL_quad_wr_busy = 0x00000040, +DB_PERF_SEL_quad_wr_mi_stall = 0x00000041, +DB_PERF_SEL_quad_wr_coherency_stall = 0x00000042, +DB_PERF_SEL_quad_wr_acks = 0x00000043, +DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x00000044, +DB_PERF_SEL_Tile_Cache_misses = 0x00000045, +DB_PERF_SEL_Tile_Cache_hits = 0x00000046, +DB_PERF_SEL_Tile_Cache_flushes = 0x00000047, +DB_PERF_SEL_Tile_Cache_surface_stall = 0x00000048, +DB_PERF_SEL_Tile_Cache_starves = 0x00000049, +DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x0000004a, +DB_PERF_SEL_tcp_dispatcher_reads = 0x0000004b, +DB_PERF_SEL_tcp_prefetcher_reads = 0x0000004c, +DB_PERF_SEL_tcp_preloader_reads = 0x0000004d, +DB_PERF_SEL_tcp_dispatcher_flushes = 0x0000004e, +DB_PERF_SEL_tcp_prefetcher_flushes = 0x0000004f, +DB_PERF_SEL_tcp_preloader_flushes = 0x00000050, +DB_PERF_SEL_Depth_Tile_Cache_sends = 0x00000051, +DB_PERF_SEL_Depth_Tile_Cache_busy = 0x00000052, +DB_PERF_SEL_Depth_Tile_Cache_starves = 0x00000053, +DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x00000054, +DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x00000055, +DB_PERF_SEL_Depth_Tile_Cache_misses = 0x00000056, +DB_PERF_SEL_Depth_Tile_Cache_hits = 0x00000057, +DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x00000058, +DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x00000059, +DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x0000005a, +DB_PERF_SEL_Depth_Tile_Cache_event = 0x0000005b, +DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x0000005c, +DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x0000005d, +DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x0000005e, +DB_PERF_SEL_Stencil_Cache_misses = 0x0000005f, +DB_PERF_SEL_Stencil_Cache_hits = 0x00000060, +DB_PERF_SEL_Stencil_Cache_flushes = 0x00000061, +DB_PERF_SEL_Stencil_Cache_starves = 0x00000062, +DB_PERF_SEL_Stencil_Cache_frees = 0x00000063, +DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x00000064, +DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x00000065, +DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x00000066, +DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x00000067, +DB_PERF_SEL_Z_Cache_pmask_misses = 0x00000068, +DB_PERF_SEL_Z_Cache_pmask_hits = 0x00000069, +DB_PERF_SEL_Z_Cache_pmask_flushes = 0x0000006a, +DB_PERF_SEL_Z_Cache_pmask_starves = 0x0000006b, +DB_PERF_SEL_Z_Cache_frees = 0x0000006c, +DB_PERF_SEL_Plane_Cache_misses = 0x0000006d, +DB_PERF_SEL_Plane_Cache_hits = 0x0000006e, +DB_PERF_SEL_Plane_Cache_flushes = 0x0000006f, +DB_PERF_SEL_Plane_Cache_starves = 0x00000070, +DB_PERF_SEL_Plane_Cache_frees = 0x00000071, +DB_PERF_SEL_flush_expanded_stencil = 0x00000072, +DB_PERF_SEL_flush_compressed_stencil = 0x00000073, +DB_PERF_SEL_flush_single_stencil = 0x00000074, +DB_PERF_SEL_planes_flushed = 0x00000075, +DB_PERF_SEL_flush_1plane = 0x00000076, +DB_PERF_SEL_flush_2plane = 0x00000077, +DB_PERF_SEL_flush_3plane = 0x00000078, +DB_PERF_SEL_flush_4plane = 0x00000079, +DB_PERF_SEL_flush_5plane = 0x0000007a, +DB_PERF_SEL_flush_6plane = 0x0000007b, +DB_PERF_SEL_flush_7plane = 0x0000007c, +DB_PERF_SEL_flush_8plane = 0x0000007d, +DB_PERF_SEL_flush_9plane = 0x0000007e, +DB_PERF_SEL_flush_10plane = 0x0000007f, +DB_PERF_SEL_flush_11plane = 0x00000080, +DB_PERF_SEL_flush_12plane = 0x00000081, +DB_PERF_SEL_flush_13plane = 0x00000082, +DB_PERF_SEL_flush_14plane = 0x00000083, +DB_PERF_SEL_flush_15plane = 0x00000084, +DB_PERF_SEL_flush_16plane = 0x00000085, +DB_PERF_SEL_flush_expanded_z = 0x00000086, +DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x00000087, +DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x00000088, +DB_PERF_SEL_dk_tile_sends = 0x00000089, +DB_PERF_SEL_dk_tile_busy = 0x0000008a, +DB_PERF_SEL_dk_tile_quad_starves = 0x0000008b, +DB_PERF_SEL_dk_tile_stalls = 0x0000008c, +DB_PERF_SEL_dk_squad_sends = 0x0000008d, +DB_PERF_SEL_dk_squad_busy = 0x0000008e, +DB_PERF_SEL_dk_squad_stalls = 0x0000008f, +DB_PERF_SEL_Op_Pipe_Busy = 0x00000090, +DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x00000091, +DB_PERF_SEL_qc_busy = 0x00000092, +DB_PERF_SEL_qc_xfc = 0x00000093, +DB_PERF_SEL_qc_conflicts = 0x00000094, +DB_PERF_SEL_qc_full_stall = 0x00000095, +DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x00000096, +DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x00000097, +DB_PERF_SEL_tsc_insert_summarize_stall = 0x00000098, +DB_PERF_SEL_tl_busy = 0x00000099, +DB_PERF_SEL_tl_dtc_read_starved = 0x0000009a, +DB_PERF_SEL_tl_z_fetch_stall = 0x0000009b, +DB_PERF_SEL_tl_stencil_stall = 0x0000009c, +DB_PERF_SEL_tl_z_decompress_stall = 0x0000009d, +DB_PERF_SEL_tl_stencil_locked_stall = 0x0000009e, +DB_PERF_SEL_tl_events = 0x0000009f, +DB_PERF_SEL_tl_summarize_squads = 0x000000a0, +DB_PERF_SEL_tl_flush_expand_squads = 0x000000a1, +DB_PERF_SEL_tl_expand_squads = 0x000000a2, +DB_PERF_SEL_tl_preZ_squads = 0x000000a3, +DB_PERF_SEL_tl_postZ_squads = 0x000000a4, +DB_PERF_SEL_tl_preZ_noop_squads = 0x000000a5, +DB_PERF_SEL_tl_postZ_noop_squads = 0x000000a6, +DB_PERF_SEL_tl_tile_ops = 0x000000a7, +DB_PERF_SEL_tl_in_xfc = 0x000000a8, +DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0x000000a9, +DB_PERF_SEL_tl_in_fast_z_stall = 0x000000aa, +DB_PERF_SEL_tl_out_xfc = 0x000000ab, +DB_PERF_SEL_tl_out_squads = 0x000000ac, +DB_PERF_SEL_zf_plane_multicycle = 0x000000ad, +DB_PERF_SEL_PostZ_Samples_passing_Z = 0x000000ae, +DB_PERF_SEL_PostZ_Samples_failing_Z = 0x000000af, +DB_PERF_SEL_PostZ_Samples_failing_S = 0x000000b0, +DB_PERF_SEL_PreZ_Samples_passing_Z = 0x000000b1, +DB_PERF_SEL_PreZ_Samples_failing_Z = 0x000000b2, +DB_PERF_SEL_PreZ_Samples_failing_S = 0x000000b3, +DB_PERF_SEL_ts_tc_update_stall = 0x000000b4, +DB_PERF_SEL_sc_kick_start = 0x000000b5, +DB_PERF_SEL_sc_kick_end = 0x000000b6, +DB_PERF_SEL_clock_reg_active = 0x000000b7, +DB_PERF_SEL_clock_main_active = 0x000000b8, +DB_PERF_SEL_clock_mem_export_active = 0x000000b9, +DB_PERF_SEL_esr_ps_out_busy = 0x000000ba, +DB_PERF_SEL_esr_ps_lqf_busy = 0x000000bb, +DB_PERF_SEL_esr_ps_lqf_stall = 0x000000bc, +DB_PERF_SEL_etr_out_send = 0x000000bd, +DB_PERF_SEL_etr_out_busy = 0x000000be, +DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0x000000bf, +DB_PERF_SEL_etr_out_cb_tile_stall = 0x000000c0, +DB_PERF_SEL_etr_out_esr_stall = 0x000000c1, +DB_PERF_SEL_esr_ps_sqq_busy = 0x000000c2, +DB_PERF_SEL_esr_ps_sqq_stall = 0x000000c3, +DB_PERF_SEL_esr_eot_fwd_busy = 0x000000c4, +DB_PERF_SEL_esr_eot_fwd_holding_squad = 0x000000c5, +DB_PERF_SEL_esr_eot_fwd_forward = 0x000000c6, +DB_PERF_SEL_esr_sqq_zi_busy = 0x000000c7, +DB_PERF_SEL_esr_sqq_zi_stall = 0x000000c8, +DB_PERF_SEL_postzl_sq_pt_busy = 0x000000c9, +DB_PERF_SEL_postzl_sq_pt_stall = 0x000000ca, +DB_PERF_SEL_postzl_se_busy = 0x000000cb, +DB_PERF_SEL_postzl_se_stall = 0x000000cc, +DB_PERF_SEL_postzl_partial_launch = 0x000000cd, +DB_PERF_SEL_postzl_full_launch = 0x000000ce, +DB_PERF_SEL_postzl_partial_waiting = 0x000000cf, +DB_PERF_SEL_postzl_tile_mem_stall = 0x000000d0, +DB_PERF_SEL_postzl_tile_init_stall = 0x000000d1, +DB_PEFF_SEL_prezl_tile_mem_stall = 0x000000d2, +DB_PERF_SEL_prezl_tile_init_stall = 0x000000d3, +DB_PERF_SEL_dtt_sm_clash_stall = 0x000000d4, +DB_PERF_SEL_dtt_sm_slot_stall = 0x000000d5, +DB_PERF_SEL_dtt_sm_miss_stall = 0x000000d6, +DB_PERF_SEL_mi_rdreq_busy = 0x000000d7, +DB_PERF_SEL_mi_rdreq_stall = 0x000000d8, +DB_PERF_SEL_mi_wrreq_busy = 0x000000d9, +DB_PERF_SEL_mi_wrreq_stall = 0x000000da, +DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0x000000db, +DB_PERF_SEL_dkg_tile_rate_tile = 0x000000dc, +DB_PERF_SEL_prezl_src_in_sends = 0x000000dd, +DB_PERF_SEL_prezl_src_in_stall = 0x000000de, +DB_PERF_SEL_prezl_src_in_squads = 0x000000df, +DB_PERF_SEL_prezl_src_in_squads_unrolled = 0x000000e0, +DB_PERF_SEL_prezl_src_in_tile_rate = 0x000000e1, +DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0x000000e2, +DB_PERF_SEL_prezl_src_out_stall = 0x000000e3, +DB_PERF_SEL_postzl_src_in_sends = 0x000000e4, +DB_PERF_SEL_postzl_src_in_stall = 0x000000e5, +DB_PERF_SEL_postzl_src_in_squads = 0x000000e6, +DB_PERF_SEL_postzl_src_in_squads_unrolled = 0x000000e7, +DB_PERF_SEL_postzl_src_in_tile_rate = 0x000000e8, +DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0x000000e9, +DB_PERF_SEL_postzl_src_out_stall = 0x000000ea, +DB_PERF_SEL_esr_ps_src_in_sends = 0x000000eb, +DB_PERF_SEL_esr_ps_src_in_stall = 0x000000ec, +DB_PERF_SEL_esr_ps_src_in_squads = 0x000000ed, +DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0x000000ee, +DB_PERF_SEL_esr_ps_src_in_tile_rate = 0x000000ef, +DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0x000000f0, +DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 0x000000f1, +DB_PERF_SEL_esr_ps_src_out_stall = 0x000000f2, +DB_PERF_SEL_depth_bounds_qtiles_culled = 0x000000f3, +DB_PERF_SEL_PreZ_Samples_failing_DB = 0x000000f4, +DB_PERF_SEL_PostZ_Samples_failing_DB = 0x000000f5, +DB_PERF_SEL_flush_compressed = 0x000000f6, +DB_PERF_SEL_flush_plane_le4 = 0x000000f7, +DB_PERF_SEL_tiles_z_fully_summarized = 0x000000f8, +DB_PERF_SEL_tiles_stencil_fully_summarized = 0x000000f9, +DB_PERF_SEL_tiles_z_clear_on_expclear = 0x000000fa, +DB_PERF_SEL_tiles_s_clear_on_expclear = 0x000000fb, +DB_PERF_SEL_tiles_decomp_on_expclear = 0x000000fc, +DB_PERF_SEL_tiles_compressed_to_decompressed = 0x000000fd, +DB_PERF_SEL_Op_Pipe_Prez_Busy = 0x000000fe, +DB_PERF_SEL_Op_Pipe_Postz_Busy = 0x000000ff, +DB_PERF_SEL_di_dt_stall = 0x00000100, +DB_PERF_SEL_DB_SC_quad_double_quad = 0x00000101, +DB_PERF_SEL_SX_DB_quad_export_quads = 0x00000102, +DB_PERF_SEL_SX_DB_quad_double_format = 0x00000103, +DB_PERF_SEL_SX_DB_quad_fast_format = 0x00000104, +DB_PERF_SEL_SX_DB_quad_slow_format = 0x00000105, +DB_PERF_SEL_DB_CB_lquad_export_quads = 0x00000106, +DB_PERF_SEL_DB_CB_lquad_double_format = 0x00000107, +DB_PERF_SEL_DB_CB_lquad_fast_format = 0x00000108, +DB_PERF_SEL_DB_CB_lquad_slow_format = 0x00000109, +DB_PERF_SEL_CB_DB_rdreq_sends = 0x0000010a, +DB_PERF_SEL_CB_DB_rdreq_prt_sends = 0x0000010b, +DB_PERF_SEL_CB_DB_wrreq_sends = 0x0000010c, +DB_PERF_SEL_CB_DB_wrreq_prt_sends = 0x0000010d, +DB_PERF_SEL_DB_CB_rdret_ack = 0x0000010e, +DB_PERF_SEL_DB_CB_rdret_nack = 0x0000010f, +DB_PERF_SEL_DB_CB_wrret_ack = 0x00000110, +DB_PERF_SEL_DB_CB_wrret_nack = 0x00000111, +DB_PERF_SEL_DFSM_squads_in = 0x00000112, +DB_PERF_SEL_DFSM_full_cleared_squads_out = 0x00000113, +DB_PERF_SEL_DFSM_quads_in = 0x00000114, +DB_PERF_SEL_DFSM_fully_cleared_quads_out = 0x00000115, +DB_PERF_SEL_DFSM_lit_pixels_in = 0x00000116, +DB_PERF_SEL_DFSM_fully_cleared_pixels_out = 0x00000117, +DB_PERF_SEL_DFSM_lit_samples_in = 0x00000118, +DB_PERF_SEL_DFSM_lit_samples_out = 0x00000119, +DB_PERF_SEL_DFSM_cycles_above_watermark = 0x0000011a, +DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream = 0x0000011b, +DB_PERF_SEL_DFSM_stalled_by_downstream = 0x0000011c, +DB_PERF_SEL_DFSM_evicted_squads_above_watermark = 0x0000011d, +DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow = 0x0000011e, +DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO = 0x0000011f, +DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark = 0x00000120, +} PerfCounter_Vals; + +/* + * RingCounterControl enum + */ + +typedef enum RingCounterControl { +COUNTER_RING_SPLIT = 0x00000000, +COUNTER_RING_0 = 0x00000001, +COUNTER_RING_1 = 0x00000002, +} RingCounterControl; + +/* + * DbMemArbWatermarks enum + */ + +typedef enum DbMemArbWatermarks { +TRANSFERRED_64_BYTES = 0x00000000, +TRANSFERRED_128_BYTES = 0x00000001, +TRANSFERRED_256_BYTES = 0x00000002, +TRANSFERRED_512_BYTES = 0x00000003, +TRANSFERRED_1024_BYTES = 0x00000004, +TRANSFERRED_2048_BYTES = 0x00000005, +TRANSFERRED_4096_BYTES = 0x00000006, +TRANSFERRED_8192_BYTES = 0x00000007, +} DbMemArbWatermarks; + +/* + * DFSMFlushEvents enum + */ + +typedef enum DFSMFlushEvents { +DB_FLUSH_AND_INV_DB_DATA_TS = 0x00000000, +DB_FLUSH_AND_INV_DB_META = 0x00000001, +DB_CACHE_FLUSH = 0x00000002, +DB_CACHE_FLUSH_TS = 0x00000003, +DB_CACHE_FLUSH_AND_INV_EVENT = 0x00000004, +DB_CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000005, +} DFSMFlushEvents; + +/* + * PixelPipeCounterId enum + */ + +typedef enum PixelPipeCounterId { +PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x00000000, +PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x00000001, +PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x00000002, +PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x00000003, +PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x00000004, +PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x00000005, +PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x00000006, +PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x00000007, +} PixelPipeCounterId; + +/* + * PixelPipeStride enum + */ + +typedef enum PixelPipeStride { +PIXEL_PIPE_STRIDE_32_BITS = 0x00000000, +PIXEL_PIPE_STRIDE_64_BITS = 0x00000001, +PIXEL_PIPE_STRIDE_128_BITS = 0x00000002, +PIXEL_PIPE_STRIDE_256_BITS = 0x00000003, +} PixelPipeStride; + +/******************************************************* + * TA Enums + *******************************************************/ + +/* + * TEX_BORDER_COLOR_TYPE enum + */ + +typedef enum TEX_BORDER_COLOR_TYPE { +TEX_BorderColor_TransparentBlack = 0x00000000, +TEX_BorderColor_OpaqueBlack = 0x00000001, +TEX_BorderColor_OpaqueWhite = 0x00000002, +TEX_BorderColor_Register = 0x00000003, +} TEX_BORDER_COLOR_TYPE; + +/* + * TEX_CHROMA_KEY enum + */ + +typedef enum TEX_CHROMA_KEY { +TEX_ChromaKey_Disabled = 0x00000000, +TEX_ChromaKey_Kill = 0x00000001, +TEX_ChromaKey_Blend = 0x00000002, +TEX_ChromaKey_RESERVED_3 = 0x00000003, +} TEX_CHROMA_KEY; + +/* + * TEX_CLAMP enum + */ + +typedef enum TEX_CLAMP { +TEX_Clamp_Repeat = 0x00000000, +TEX_Clamp_Mirror = 0x00000001, +TEX_Clamp_ClampToLast = 0x00000002, +TEX_Clamp_MirrorOnceToLast = 0x00000003, +TEX_Clamp_ClampHalfToBorder = 0x00000004, +TEX_Clamp_MirrorOnceHalfToBorder = 0x00000005, +TEX_Clamp_ClampToBorder = 0x00000006, +TEX_Clamp_MirrorOnceToBorder = 0x00000007, +} TEX_CLAMP; + +/* + * TEX_COORD_TYPE enum + */ + +typedef enum TEX_COORD_TYPE { +TEX_CoordType_Unnormalized = 0x00000000, +TEX_CoordType_Normalized = 0x00000001, +} TEX_COORD_TYPE; + +/* + * TEX_DEPTH_COMPARE_FUNCTION enum + */ + +typedef enum TEX_DEPTH_COMPARE_FUNCTION { +TEX_DepthCompareFunction_Never = 0x00000000, +TEX_DepthCompareFunction_Less = 0x00000001, +TEX_DepthCompareFunction_Equal = 0x00000002, +TEX_DepthCompareFunction_LessEqual = 0x00000003, +TEX_DepthCompareFunction_Greater = 0x00000004, +TEX_DepthCompareFunction_NotEqual = 0x00000005, +TEX_DepthCompareFunction_GreaterEqual = 0x00000006, +TEX_DepthCompareFunction_Always = 0x00000007, +} TEX_DEPTH_COMPARE_FUNCTION; + +/* + * TEX_DIM enum + */ + +typedef enum TEX_DIM { +TEX_Dim_1D = 0x00000000, +TEX_Dim_2D = 0x00000001, +TEX_Dim_3D = 0x00000002, +TEX_Dim_CubeMap = 0x00000003, +TEX_Dim_1DArray = 0x00000004, +TEX_Dim_2DArray = 0x00000005, +TEX_Dim_2D_MSAA = 0x00000006, +TEX_Dim_2DArray_MSAA = 0x00000007, +} TEX_DIM; + +/* + * TEX_FORMAT_COMP enum + */ + +typedef enum TEX_FORMAT_COMP { +TEX_FormatComp_Unsigned = 0x00000000, +TEX_FormatComp_Signed = 0x00000001, +TEX_FormatComp_UnsignedBiased = 0x00000002, +TEX_FormatComp_RESERVED_3 = 0x00000003, +} TEX_FORMAT_COMP; + +/* + * TEX_MAX_ANISO_RATIO enum + */ + +typedef enum TEX_MAX_ANISO_RATIO { +TEX_MaxAnisoRatio_1to1 = 0x00000000, +TEX_MaxAnisoRatio_2to1 = 0x00000001, +TEX_MaxAnisoRatio_4to1 = 0x00000002, +TEX_MaxAnisoRatio_8to1 = 0x00000003, +TEX_MaxAnisoRatio_16to1 = 0x00000004, +TEX_MaxAnisoRatio_RESERVED_5 = 0x00000005, +TEX_MaxAnisoRatio_RESERVED_6 = 0x00000006, +TEX_MaxAnisoRatio_RESERVED_7 = 0x00000007, +} TEX_MAX_ANISO_RATIO; + +/* + * TEX_MIP_FILTER enum + */ + +typedef enum TEX_MIP_FILTER { +TEX_MipFilter_None = 0x00000000, +TEX_MipFilter_Point = 0x00000001, +TEX_MipFilter_Linear = 0x00000002, +TEX_MipFilter_Point_Aniso_Adj = 0x00000003, +} TEX_MIP_FILTER; + +/* + * TEX_REQUEST_SIZE enum + */ + +typedef enum TEX_REQUEST_SIZE { +TEX_RequestSize_32B = 0x00000000, +TEX_RequestSize_64B = 0x00000001, +TEX_RequestSize_128B = 0x00000002, +TEX_RequestSize_2X64B = 0x00000003, +} TEX_REQUEST_SIZE; + +/* + * TEX_SAMPLER_TYPE enum + */ + +typedef enum TEX_SAMPLER_TYPE { +TEX_SamplerType_Invalid = 0x00000000, +TEX_SamplerType_Valid = 0x00000001, +} TEX_SAMPLER_TYPE; + +/* + * TEX_XY_FILTER enum + */ + +typedef enum TEX_XY_FILTER { +TEX_XYFilter_Point = 0x00000000, +TEX_XYFilter_Linear = 0x00000001, +TEX_XYFilter_AnisoPoint = 0x00000002, +TEX_XYFilter_AnisoLinear = 0x00000003, +} TEX_XY_FILTER; + +/* + * TEX_Z_FILTER enum + */ + +typedef enum TEX_Z_FILTER { +TEX_ZFilter_None = 0x00000000, +TEX_ZFilter_Point = 0x00000001, +TEX_ZFilter_Linear = 0x00000002, +TEX_ZFilter_RESERVED_3 = 0x00000003, +} TEX_Z_FILTER; + +/* + * VTX_CLAMP enum + */ + +typedef enum VTX_CLAMP { +VTX_Clamp_ClampToZero = 0x00000000, +VTX_Clamp_ClampToNAN = 0x00000001, +} VTX_CLAMP; + +/* + * VTX_FETCH_TYPE enum + */ + +typedef enum VTX_FETCH_TYPE { +VTX_FetchType_VertexData = 0x00000000, +VTX_FetchType_InstanceData = 0x00000001, +VTX_FetchType_NoIndexOffset = 0x00000002, +VTX_FetchType_RESERVED_3 = 0x00000003, +} VTX_FETCH_TYPE; + +/* + * VTX_FORMAT_COMP_ALL enum + */ + +typedef enum VTX_FORMAT_COMP_ALL { +VTX_FormatCompAll_Unsigned = 0x00000000, +VTX_FormatCompAll_Signed = 0x00000001, +} VTX_FORMAT_COMP_ALL; + +/* + * VTX_MEM_REQUEST_SIZE enum + */ + +typedef enum VTX_MEM_REQUEST_SIZE { +VTX_MemRequestSize_32B = 0x00000000, +VTX_MemRequestSize_64B = 0x00000001, +} VTX_MEM_REQUEST_SIZE; + +/* + * TVX_DATA_FORMAT enum + */ + +typedef enum TVX_DATA_FORMAT { +TVX_FMT_INVALID = 0x00000000, +TVX_FMT_8 = 0x00000001, +TVX_FMT_4_4 = 0x00000002, +TVX_FMT_3_3_2 = 0x00000003, +TVX_FMT_RESERVED_4 = 0x00000004, +TVX_FMT_16 = 0x00000005, +TVX_FMT_16_FLOAT = 0x00000006, +TVX_FMT_8_8 = 0x00000007, +TVX_FMT_5_6_5 = 0x00000008, +TVX_FMT_6_5_5 = 0x00000009, +TVX_FMT_1_5_5_5 = 0x0000000a, +TVX_FMT_4_4_4_4 = 0x0000000b, +TVX_FMT_5_5_5_1 = 0x0000000c, +TVX_FMT_32 = 0x0000000d, +TVX_FMT_32_FLOAT = 0x0000000e, +TVX_FMT_16_16 = 0x0000000f, +TVX_FMT_16_16_FLOAT = 0x00000010, +TVX_FMT_8_24 = 0x00000011, +TVX_FMT_8_24_FLOAT = 0x00000012, +TVX_FMT_24_8 = 0x00000013, +TVX_FMT_24_8_FLOAT = 0x00000014, +TVX_FMT_10_11_11 = 0x00000015, +TVX_FMT_10_11_11_FLOAT = 0x00000016, +TVX_FMT_11_11_10 = 0x00000017, +TVX_FMT_11_11_10_FLOAT = 0x00000018, +TVX_FMT_2_10_10_10 = 0x00000019, +TVX_FMT_8_8_8_8 = 0x0000001a, +TVX_FMT_10_10_10_2 = 0x0000001b, +TVX_FMT_X24_8_32_FLOAT = 0x0000001c, +TVX_FMT_32_32 = 0x0000001d, +TVX_FMT_32_32_FLOAT = 0x0000001e, +TVX_FMT_16_16_16_16 = 0x0000001f, +TVX_FMT_16_16_16_16_FLOAT = 0x00000020, +TVX_FMT_RESERVED_33 = 0x00000021, +TVX_FMT_32_32_32_32 = 0x00000022, +TVX_FMT_32_32_32_32_FLOAT = 0x00000023, +TVX_FMT_RESERVED_36 = 0x00000024, +TVX_FMT_1 = 0x00000025, +TVX_FMT_1_REVERSED = 0x00000026, +TVX_FMT_GB_GR = 0x00000027, +TVX_FMT_BG_RG = 0x00000028, +TVX_FMT_32_AS_8 = 0x00000029, +TVX_FMT_32_AS_8_8 = 0x0000002a, +TVX_FMT_5_9_9_9_SHAREDEXP = 0x0000002b, +TVX_FMT_8_8_8 = 0x0000002c, +TVX_FMT_16_16_16 = 0x0000002d, +TVX_FMT_16_16_16_FLOAT = 0x0000002e, +TVX_FMT_32_32_32 = 0x0000002f, +TVX_FMT_32_32_32_FLOAT = 0x00000030, +TVX_FMT_BC1 = 0x00000031, +TVX_FMT_BC2 = 0x00000032, +TVX_FMT_BC3 = 0x00000033, +TVX_FMT_BC4 = 0x00000034, +TVX_FMT_BC5 = 0x00000035, +TVX_FMT_APC0 = 0x00000036, +TVX_FMT_APC1 = 0x00000037, +TVX_FMT_APC2 = 0x00000038, +TVX_FMT_APC3 = 0x00000039, +TVX_FMT_APC4 = 0x0000003a, +TVX_FMT_APC5 = 0x0000003b, +TVX_FMT_APC6 = 0x0000003c, +TVX_FMT_APC7 = 0x0000003d, +TVX_FMT_CTX1 = 0x0000003e, +TVX_FMT_RESERVED_63 = 0x0000003f, +} TVX_DATA_FORMAT; + +/* + * TVX_DST_SEL enum + */ + +typedef enum TVX_DST_SEL { +TVX_DstSel_X = 0x00000000, +TVX_DstSel_Y = 0x00000001, +TVX_DstSel_Z = 0x00000002, +TVX_DstSel_W = 0x00000003, +TVX_DstSel_0f = 0x00000004, +TVX_DstSel_1f = 0x00000005, +TVX_DstSel_RESERVED_6 = 0x00000006, +TVX_DstSel_Mask = 0x00000007, +} TVX_DST_SEL; + +/* + * TVX_ENDIAN_SWAP enum + */ + +typedef enum TVX_ENDIAN_SWAP { +TVX_EndianSwap_None = 0x00000000, +TVX_EndianSwap_8in16 = 0x00000001, +TVX_EndianSwap_8in32 = 0x00000002, +TVX_EndianSwap_8in64 = 0x00000003, +} TVX_ENDIAN_SWAP; + +/* + * TVX_INST enum + */ + +typedef enum TVX_INST { +TVX_Inst_NormalVertexFetch = 0x00000000, +TVX_Inst_SemanticVertexFetch = 0x00000001, +TVX_Inst_RESERVED_2 = 0x00000002, +TVX_Inst_LD = 0x00000003, +TVX_Inst_GetTextureResInfo = 0x00000004, +TVX_Inst_GetNumberOfSamples = 0x00000005, +TVX_Inst_GetLOD = 0x00000006, +TVX_Inst_GetGradientsH = 0x00000007, +TVX_Inst_GetGradientsV = 0x00000008, +TVX_Inst_SetTextureOffsets = 0x00000009, +TVX_Inst_KeepGradients = 0x0000000a, +TVX_Inst_SetGradientsH = 0x0000000b, +TVX_Inst_SetGradientsV = 0x0000000c, +TVX_Inst_Pass = 0x0000000d, +TVX_Inst_GetBufferResInfo = 0x0000000e, +TVX_Inst_RESERVED_15 = 0x0000000f, +TVX_Inst_Sample = 0x00000010, +TVX_Inst_Sample_L = 0x00000011, +TVX_Inst_Sample_LB = 0x00000012, +TVX_Inst_Sample_LZ = 0x00000013, +TVX_Inst_Sample_G = 0x00000014, +TVX_Inst_Gather4 = 0x00000015, +TVX_Inst_Sample_G_LB = 0x00000016, +TVX_Inst_Gather4_O = 0x00000017, +TVX_Inst_Sample_C = 0x00000018, +TVX_Inst_Sample_C_L = 0x00000019, +TVX_Inst_Sample_C_LB = 0x0000001a, +TVX_Inst_Sample_C_LZ = 0x0000001b, +TVX_Inst_Sample_C_G = 0x0000001c, +TVX_Inst_Gather4_C = 0x0000001d, +TVX_Inst_Sample_C_G_LB = 0x0000001e, +TVX_Inst_Gather4_C_O = 0x0000001f, +} TVX_INST; + +/* + * TVX_NUM_FORMAT_ALL enum + */ + +typedef enum TVX_NUM_FORMAT_ALL { +TVX_NumFormatAll_Norm = 0x00000000, +TVX_NumFormatAll_Int = 0x00000001, +TVX_NumFormatAll_Scaled = 0x00000002, +TVX_NumFormatAll_RESERVED_3 = 0x00000003, +} TVX_NUM_FORMAT_ALL; + +/* + * TVX_SRC_SEL enum + */ + +typedef enum TVX_SRC_SEL { +TVX_SrcSel_X = 0x00000000, +TVX_SrcSel_Y = 0x00000001, +TVX_SrcSel_Z = 0x00000002, +TVX_SrcSel_W = 0x00000003, +TVX_SrcSel_0f = 0x00000004, +TVX_SrcSel_1f = 0x00000005, +} TVX_SRC_SEL; + +/* + * TVX_SRF_MODE_ALL enum + */ + +typedef enum TVX_SRF_MODE_ALL { +TVX_SRFModeAll_ZCMO = 0x00000000, +TVX_SRFModeAll_NZ = 0x00000001, +} TVX_SRF_MODE_ALL; + +/* + * TVX_TYPE enum + */ + +typedef enum TVX_TYPE { +TVX_Type_InvalidTextureResource = 0x00000000, +TVX_Type_InvalidVertexBuffer = 0x00000001, +TVX_Type_ValidTextureResource = 0x00000002, +TVX_Type_ValidVertexBuffer = 0x00000003, +} TVX_TYPE; + +/******************************************************* + * PA Enums + *******************************************************/ + +/* + * SU_PERFCNT_SEL enum + */ + +typedef enum SU_PERFCNT_SEL { +PERF_PAPC_PASX_REQ = 0x00000000, +PERF_PAPC_PASX_DISABLE_PIPE = 0x00000001, +PERF_PAPC_PASX_FIRST_VECTOR = 0x00000002, +PERF_PAPC_PASX_SECOND_VECTOR = 0x00000003, +PERF_PAPC_PASX_FIRST_DEAD = 0x00000004, +PERF_PAPC_PASX_SECOND_DEAD = 0x00000005, +PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x00000006, +PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x00000007, +PERF_PAPC_PA_INPUT_PRIM = 0x00000008, +PERF_PAPC_PA_INPUT_NULL_PRIM = 0x00000009, +PERF_PAPC_PA_INPUT_EVENT_FLAG = 0x0000000a, +PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0x0000000b, +PERF_PAPC_PA_INPUT_END_OF_PACKET = 0x0000000c, +PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0x0000000d, +PERF_PAPC_CLPR_CULL_PRIM = 0x0000000e, +PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0x0000000f, +PERF_PAPC_CLPR_VV_CULL_PRIM = 0x00000010, +PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x00000011, +PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x00000012, +PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x00000013, +PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x00000014, +PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x00000015, +PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x00000016, +PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x00000017, +PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x00000018, +PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x00000019, +PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x0000001a, +PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x0000001b, +PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x0000001c, +PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x0000001d, +PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x0000001e, +PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x0000001f, +PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x00000020, +PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x00000021, +PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x00000022, +PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x00000023, +PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x00000024, +PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x00000025, +PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x00000026, +PERF_PAPC_CLSM_NULL_PRIM = 0x00000027, +PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x00000028, +PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x00000029, +PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x0000002a, +PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x0000002b, +PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x0000002c, +PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x0000002d, +PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x0000002e, +PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x0000002f, +PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x00000030, +PERF_PAPC_SU_INPUT_PRIM = 0x00000031, +PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x00000032, +PERF_PAPC_SU_INPUT_NULL_PRIM = 0x00000033, +PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x00000034, +PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x00000035, +PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x00000036, +PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x00000037, +PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x00000038, +PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x00000039, +PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x0000003a, +PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x0000003b, +PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x0000003c, +PERF_PAPC_SU_OUTPUT_PRIM = 0x0000003d, +PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x0000003e, +PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x0000003f, +PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x00000040, +PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x00000041, +PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x00000042, +PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x00000043, +PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x00000044, +PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x00000045, +PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x00000046, +PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x00000047, +PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x00000048, +PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x00000049, +PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x0000004a, +PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x0000004b, +PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x0000004c, +PERF_PAPC_PASX_REQ_IDLE = 0x0000004d, +PERF_PAPC_PASX_REQ_BUSY = 0x0000004e, +PERF_PAPC_PASX_REQ_STALLED = 0x0000004f, +PERF_PAPC_PASX_REC_IDLE = 0x00000050, +PERF_PAPC_PASX_REC_BUSY = 0x00000051, +PERF_PAPC_PASX_REC_STARVED_SX = 0x00000052, +PERF_PAPC_PASX_REC_STALLED = 0x00000053, +PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x00000054, +PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x00000055, +PERF_PAPC_CCGSM_IDLE = 0x00000056, +PERF_PAPC_CCGSM_BUSY = 0x00000057, +PERF_PAPC_CCGSM_STALLED = 0x00000058, +PERF_PAPC_CLPRIM_IDLE = 0x00000059, +PERF_PAPC_CLPRIM_BUSY = 0x0000005a, +PERF_PAPC_CLPRIM_STALLED = 0x0000005b, +PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x0000005c, +PERF_PAPC_CLIPSM_IDLE = 0x0000005d, +PERF_PAPC_CLIPSM_BUSY = 0x0000005e, +PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x0000005f, +PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x00000060, +PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x00000061, +PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x00000062, +PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x00000063, +PERF_PAPC_CLIPGA_IDLE = 0x00000064, +PERF_PAPC_CLIPGA_BUSY = 0x00000065, +PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x00000066, +PERF_PAPC_CLIPGA_STALLED = 0x00000067, +PERF_PAPC_CLIP_IDLE = 0x00000068, +PERF_PAPC_CLIP_BUSY = 0x00000069, +PERF_PAPC_SU_IDLE = 0x0000006a, +PERF_PAPC_SU_BUSY = 0x0000006b, +PERF_PAPC_SU_STARVED_CLIP = 0x0000006c, +PERF_PAPC_SU_STALLED_SC = 0x0000006d, +PERF_PAPC_CL_DYN_SCLK_VLD = 0x0000006e, +PERF_PAPC_SU_DYN_SCLK_VLD = 0x0000006f, +PERF_PAPC_PA_REG_SCLK_VLD = 0x00000070, +PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x00000071, +PERF_PAPC_PASX_SE0_REQ = 0x00000072, +PERF_PAPC_PASX_SE1_REQ = 0x00000073, +PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x00000074, +PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x00000075, +PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x00000076, +PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x00000077, +PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x00000078, +PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x00000079, +PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x0000007a, +PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x0000007b, +PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x0000007c, +PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x0000007d, +PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x0000007e, +PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x0000007f, +PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x00000080, +PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x00000081, +PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x00000082, +PERF_PAPC_SU_SE0_STALLED_SC = 0x00000083, +PERF_PAPC_SU_SE1_STALLED_SC = 0x00000084, +PERF_PAPC_SU_SE01_STALLED_SC = 0x00000085, +PERF_PAPC_CLSM_CLIPPING_PRIM = 0x00000086, +PERF_PAPC_SU_CULLED_PRIM = 0x00000087, +PERF_PAPC_SU_OUTPUT_EOPG = 0x00000088, +PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x00000089, +PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x0000008a, +PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x0000008b, +PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x0000008c, +PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x0000008d, +PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x0000008e, +PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 0x0000008f, +PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 0x00000090, +PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 0x00000091, +PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 0x00000092, +PERF_PAPC_SU_SE0_OUTPUT_EOPG = 0x00000093, +PERF_PAPC_SU_SE1_OUTPUT_EOPG = 0x00000094, +PERF_PAPC_SU_SE2_OUTPUT_EOPG = 0x00000095, +PERF_PAPC_SU_SE3_OUTPUT_EOPG = 0x00000096, +PERF_PAPC_SU_SE2_STALLED_SC = 0x00000097, +PERF_PAPC_SU_SE3_STALLED_SC = 0x00000098, +} SU_PERFCNT_SEL; + +/* + * SC_PERFCNT_SEL enum + */ + +typedef enum SC_PERFCNT_SEL { +SC_SRPS_WINDOW_VALID = 0x00000000, +SC_PSSW_WINDOW_VALID = 0x00000001, +SC_TPQZ_WINDOW_VALID = 0x00000002, +SC_QZQP_WINDOW_VALID = 0x00000003, +SC_TRPK_WINDOW_VALID = 0x00000004, +SC_SRPS_WINDOW_VALID_BUSY = 0x00000005, +SC_PSSW_WINDOW_VALID_BUSY = 0x00000006, +SC_TPQZ_WINDOW_VALID_BUSY = 0x00000007, +SC_QZQP_WINDOW_VALID_BUSY = 0x00000008, +SC_TRPK_WINDOW_VALID_BUSY = 0x00000009, +SC_STARVED_BY_PA = 0x0000000a, +SC_STALLED_BY_PRIMFIFO = 0x0000000b, +SC_STALLED_BY_DB_TILE = 0x0000000c, +SC_STARVED_BY_DB_TILE = 0x0000000d, +SC_STALLED_BY_TILEORDERFIFO = 0x0000000e, +SC_STALLED_BY_TILEFIFO = 0x0000000f, +SC_STALLED_BY_DB_QUAD = 0x00000010, +SC_STARVED_BY_DB_QUAD = 0x00000011, +SC_STALLED_BY_QUADFIFO = 0x00000012, +SC_STALLED_BY_BCI = 0x00000013, +SC_STALLED_BY_SPI = 0x00000014, +SC_SCISSOR_DISCARD = 0x00000015, +SC_BB_DISCARD = 0x00000016, +SC_SUPERTILE_COUNT = 0x00000017, +SC_SUPERTILE_PER_PRIM_H0 = 0x00000018, +SC_SUPERTILE_PER_PRIM_H1 = 0x00000019, +SC_SUPERTILE_PER_PRIM_H2 = 0x0000001a, +SC_SUPERTILE_PER_PRIM_H3 = 0x0000001b, +SC_SUPERTILE_PER_PRIM_H4 = 0x0000001c, +SC_SUPERTILE_PER_PRIM_H5 = 0x0000001d, +SC_SUPERTILE_PER_PRIM_H6 = 0x0000001e, +SC_SUPERTILE_PER_PRIM_H7 = 0x0000001f, +SC_SUPERTILE_PER_PRIM_H8 = 0x00000020, +SC_SUPERTILE_PER_PRIM_H9 = 0x00000021, +SC_SUPERTILE_PER_PRIM_H10 = 0x00000022, +SC_SUPERTILE_PER_PRIM_H11 = 0x00000023, +SC_SUPERTILE_PER_PRIM_H12 = 0x00000024, +SC_SUPERTILE_PER_PRIM_H13 = 0x00000025, +SC_SUPERTILE_PER_PRIM_H14 = 0x00000026, +SC_SUPERTILE_PER_PRIM_H15 = 0x00000027, +SC_SUPERTILE_PER_PRIM_H16 = 0x00000028, +SC_TILE_PER_PRIM_H0 = 0x00000029, +SC_TILE_PER_PRIM_H1 = 0x0000002a, +SC_TILE_PER_PRIM_H2 = 0x0000002b, +SC_TILE_PER_PRIM_H3 = 0x0000002c, +SC_TILE_PER_PRIM_H4 = 0x0000002d, +SC_TILE_PER_PRIM_H5 = 0x0000002e, +SC_TILE_PER_PRIM_H6 = 0x0000002f, +SC_TILE_PER_PRIM_H7 = 0x00000030, +SC_TILE_PER_PRIM_H8 = 0x00000031, +SC_TILE_PER_PRIM_H9 = 0x00000032, +SC_TILE_PER_PRIM_H10 = 0x00000033, +SC_TILE_PER_PRIM_H11 = 0x00000034, +SC_TILE_PER_PRIM_H12 = 0x00000035, +SC_TILE_PER_PRIM_H13 = 0x00000036, +SC_TILE_PER_PRIM_H14 = 0x00000037, +SC_TILE_PER_PRIM_H15 = 0x00000038, +SC_TILE_PER_PRIM_H16 = 0x00000039, +SC_TILE_PER_SUPERTILE_H0 = 0x0000003a, +SC_TILE_PER_SUPERTILE_H1 = 0x0000003b, +SC_TILE_PER_SUPERTILE_H2 = 0x0000003c, +SC_TILE_PER_SUPERTILE_H3 = 0x0000003d, +SC_TILE_PER_SUPERTILE_H4 = 0x0000003e, +SC_TILE_PER_SUPERTILE_H5 = 0x0000003f, +SC_TILE_PER_SUPERTILE_H6 = 0x00000040, +SC_TILE_PER_SUPERTILE_H7 = 0x00000041, +SC_TILE_PER_SUPERTILE_H8 = 0x00000042, +SC_TILE_PER_SUPERTILE_H9 = 0x00000043, +SC_TILE_PER_SUPERTILE_H10 = 0x00000044, +SC_TILE_PER_SUPERTILE_H11 = 0x00000045, +SC_TILE_PER_SUPERTILE_H12 = 0x00000046, +SC_TILE_PER_SUPERTILE_H13 = 0x00000047, +SC_TILE_PER_SUPERTILE_H14 = 0x00000048, +SC_TILE_PER_SUPERTILE_H15 = 0x00000049, +SC_TILE_PER_SUPERTILE_H16 = 0x0000004a, +SC_TILE_PICKED_H1 = 0x0000004b, +SC_TILE_PICKED_H2 = 0x0000004c, +SC_TILE_PICKED_H3 = 0x0000004d, +SC_TILE_PICKED_H4 = 0x0000004e, +SC_QZ0_MULTI_GPU_TILE_DISCARD = 0x0000004f, +SC_QZ1_MULTI_GPU_TILE_DISCARD = 0x00000050, +SC_QZ2_MULTI_GPU_TILE_DISCARD = 0x00000051, +SC_QZ3_MULTI_GPU_TILE_DISCARD = 0x00000052, +SC_QZ0_TILE_COUNT = 0x00000053, +SC_QZ1_TILE_COUNT = 0x00000054, +SC_QZ2_TILE_COUNT = 0x00000055, +SC_QZ3_TILE_COUNT = 0x00000056, +SC_QZ0_TILE_COVERED_COUNT = 0x00000057, +SC_QZ1_TILE_COVERED_COUNT = 0x00000058, +SC_QZ2_TILE_COVERED_COUNT = 0x00000059, +SC_QZ3_TILE_COVERED_COUNT = 0x0000005a, +SC_QZ0_TILE_NOT_COVERED_COUNT = 0x0000005b, +SC_QZ1_TILE_NOT_COVERED_COUNT = 0x0000005c, +SC_QZ2_TILE_NOT_COVERED_COUNT = 0x0000005d, +SC_QZ3_TILE_NOT_COVERED_COUNT = 0x0000005e, +SC_QZ0_QUAD_PER_TILE_H0 = 0x0000005f, +SC_QZ0_QUAD_PER_TILE_H1 = 0x00000060, +SC_QZ0_QUAD_PER_TILE_H2 = 0x00000061, +SC_QZ0_QUAD_PER_TILE_H3 = 0x00000062, +SC_QZ0_QUAD_PER_TILE_H4 = 0x00000063, +SC_QZ0_QUAD_PER_TILE_H5 = 0x00000064, +SC_QZ0_QUAD_PER_TILE_H6 = 0x00000065, +SC_QZ0_QUAD_PER_TILE_H7 = 0x00000066, +SC_QZ0_QUAD_PER_TILE_H8 = 0x00000067, +SC_QZ0_QUAD_PER_TILE_H9 = 0x00000068, +SC_QZ0_QUAD_PER_TILE_H10 = 0x00000069, +SC_QZ0_QUAD_PER_TILE_H11 = 0x0000006a, +SC_QZ0_QUAD_PER_TILE_H12 = 0x0000006b, +SC_QZ0_QUAD_PER_TILE_H13 = 0x0000006c, +SC_QZ0_QUAD_PER_TILE_H14 = 0x0000006d, +SC_QZ0_QUAD_PER_TILE_H15 = 0x0000006e, +SC_QZ0_QUAD_PER_TILE_H16 = 0x0000006f, +SC_QZ1_QUAD_PER_TILE_H0 = 0x00000070, +SC_QZ1_QUAD_PER_TILE_H1 = 0x00000071, +SC_QZ1_QUAD_PER_TILE_H2 = 0x00000072, +SC_QZ1_QUAD_PER_TILE_H3 = 0x00000073, +SC_QZ1_QUAD_PER_TILE_H4 = 0x00000074, +SC_QZ1_QUAD_PER_TILE_H5 = 0x00000075, +SC_QZ1_QUAD_PER_TILE_H6 = 0x00000076, +SC_QZ1_QUAD_PER_TILE_H7 = 0x00000077, +SC_QZ1_QUAD_PER_TILE_H8 = 0x00000078, +SC_QZ1_QUAD_PER_TILE_H9 = 0x00000079, +SC_QZ1_QUAD_PER_TILE_H10 = 0x0000007a, +SC_QZ1_QUAD_PER_TILE_H11 = 0x0000007b, +SC_QZ1_QUAD_PER_TILE_H12 = 0x0000007c, +SC_QZ1_QUAD_PER_TILE_H13 = 0x0000007d, +SC_QZ1_QUAD_PER_TILE_H14 = 0x0000007e, +SC_QZ1_QUAD_PER_TILE_H15 = 0x0000007f, +SC_QZ1_QUAD_PER_TILE_H16 = 0x00000080, +SC_QZ2_QUAD_PER_TILE_H0 = 0x00000081, +SC_QZ2_QUAD_PER_TILE_H1 = 0x00000082, +SC_QZ2_QUAD_PER_TILE_H2 = 0x00000083, +SC_QZ2_QUAD_PER_TILE_H3 = 0x00000084, +SC_QZ2_QUAD_PER_TILE_H4 = 0x00000085, +SC_QZ2_QUAD_PER_TILE_H5 = 0x00000086, +SC_QZ2_QUAD_PER_TILE_H6 = 0x00000087, +SC_QZ2_QUAD_PER_TILE_H7 = 0x00000088, +SC_QZ2_QUAD_PER_TILE_H8 = 0x00000089, +SC_QZ2_QUAD_PER_TILE_H9 = 0x0000008a, +SC_QZ2_QUAD_PER_TILE_H10 = 0x0000008b, +SC_QZ2_QUAD_PER_TILE_H11 = 0x0000008c, +SC_QZ2_QUAD_PER_TILE_H12 = 0x0000008d, +SC_QZ2_QUAD_PER_TILE_H13 = 0x0000008e, +SC_QZ2_QUAD_PER_TILE_H14 = 0x0000008f, +SC_QZ2_QUAD_PER_TILE_H15 = 0x00000090, +SC_QZ2_QUAD_PER_TILE_H16 = 0x00000091, +SC_QZ3_QUAD_PER_TILE_H0 = 0x00000092, +SC_QZ3_QUAD_PER_TILE_H1 = 0x00000093, +SC_QZ3_QUAD_PER_TILE_H2 = 0x00000094, +SC_QZ3_QUAD_PER_TILE_H3 = 0x00000095, +SC_QZ3_QUAD_PER_TILE_H4 = 0x00000096, +SC_QZ3_QUAD_PER_TILE_H5 = 0x00000097, +SC_QZ3_QUAD_PER_TILE_H6 = 0x00000098, +SC_QZ3_QUAD_PER_TILE_H7 = 0x00000099, +SC_QZ3_QUAD_PER_TILE_H8 = 0x0000009a, +SC_QZ3_QUAD_PER_TILE_H9 = 0x0000009b, +SC_QZ3_QUAD_PER_TILE_H10 = 0x0000009c, +SC_QZ3_QUAD_PER_TILE_H11 = 0x0000009d, +SC_QZ3_QUAD_PER_TILE_H12 = 0x0000009e, +SC_QZ3_QUAD_PER_TILE_H13 = 0x0000009f, +SC_QZ3_QUAD_PER_TILE_H14 = 0x000000a0, +SC_QZ3_QUAD_PER_TILE_H15 = 0x000000a1, +SC_QZ3_QUAD_PER_TILE_H16 = 0x000000a2, +SC_QZ0_QUAD_COUNT = 0x000000a3, +SC_QZ1_QUAD_COUNT = 0x000000a4, +SC_QZ2_QUAD_COUNT = 0x000000a5, +SC_QZ3_QUAD_COUNT = 0x000000a6, +SC_P0_HIZ_TILE_COUNT = 0x000000a7, +SC_P1_HIZ_TILE_COUNT = 0x000000a8, +SC_P2_HIZ_TILE_COUNT = 0x000000a9, +SC_P3_HIZ_TILE_COUNT = 0x000000aa, +SC_P0_HIZ_QUAD_PER_TILE_H0 = 0x000000ab, +SC_P0_HIZ_QUAD_PER_TILE_H1 = 0x000000ac, +SC_P0_HIZ_QUAD_PER_TILE_H2 = 0x000000ad, +SC_P0_HIZ_QUAD_PER_TILE_H3 = 0x000000ae, +SC_P0_HIZ_QUAD_PER_TILE_H4 = 0x000000af, +SC_P0_HIZ_QUAD_PER_TILE_H5 = 0x000000b0, +SC_P0_HIZ_QUAD_PER_TILE_H6 = 0x000000b1, +SC_P0_HIZ_QUAD_PER_TILE_H7 = 0x000000b2, +SC_P0_HIZ_QUAD_PER_TILE_H8 = 0x000000b3, +SC_P0_HIZ_QUAD_PER_TILE_H9 = 0x000000b4, +SC_P0_HIZ_QUAD_PER_TILE_H10 = 0x000000b5, +SC_P0_HIZ_QUAD_PER_TILE_H11 = 0x000000b6, +SC_P0_HIZ_QUAD_PER_TILE_H12 = 0x000000b7, +SC_P0_HIZ_QUAD_PER_TILE_H13 = 0x000000b8, +SC_P0_HIZ_QUAD_PER_TILE_H14 = 0x000000b9, +SC_P0_HIZ_QUAD_PER_TILE_H15 = 0x000000ba, +SC_P0_HIZ_QUAD_PER_TILE_H16 = 0x000000bb, +SC_P1_HIZ_QUAD_PER_TILE_H0 = 0x000000bc, +SC_P1_HIZ_QUAD_PER_TILE_H1 = 0x000000bd, +SC_P1_HIZ_QUAD_PER_TILE_H2 = 0x000000be, +SC_P1_HIZ_QUAD_PER_TILE_H3 = 0x000000bf, +SC_P1_HIZ_QUAD_PER_TILE_H4 = 0x000000c0, +SC_P1_HIZ_QUAD_PER_TILE_H5 = 0x000000c1, +SC_P1_HIZ_QUAD_PER_TILE_H6 = 0x000000c2, +SC_P1_HIZ_QUAD_PER_TILE_H7 = 0x000000c3, +SC_P1_HIZ_QUAD_PER_TILE_H8 = 0x000000c4, +SC_P1_HIZ_QUAD_PER_TILE_H9 = 0x000000c5, +SC_P1_HIZ_QUAD_PER_TILE_H10 = 0x000000c6, +SC_P1_HIZ_QUAD_PER_TILE_H11 = 0x000000c7, +SC_P1_HIZ_QUAD_PER_TILE_H12 = 0x000000c8, +SC_P1_HIZ_QUAD_PER_TILE_H13 = 0x000000c9, +SC_P1_HIZ_QUAD_PER_TILE_H14 = 0x000000ca, +SC_P1_HIZ_QUAD_PER_TILE_H15 = 0x000000cb, +SC_P1_HIZ_QUAD_PER_TILE_H16 = 0x000000cc, +SC_P2_HIZ_QUAD_PER_TILE_H0 = 0x000000cd, +SC_P2_HIZ_QUAD_PER_TILE_H1 = 0x000000ce, +SC_P2_HIZ_QUAD_PER_TILE_H2 = 0x000000cf, +SC_P2_HIZ_QUAD_PER_TILE_H3 = 0x000000d0, +SC_P2_HIZ_QUAD_PER_TILE_H4 = 0x000000d1, +SC_P2_HIZ_QUAD_PER_TILE_H5 = 0x000000d2, +SC_P2_HIZ_QUAD_PER_TILE_H6 = 0x000000d3, +SC_P2_HIZ_QUAD_PER_TILE_H7 = 0x000000d4, +SC_P2_HIZ_QUAD_PER_TILE_H8 = 0x000000d5, +SC_P2_HIZ_QUAD_PER_TILE_H9 = 0x000000d6, +SC_P2_HIZ_QUAD_PER_TILE_H10 = 0x000000d7, +SC_P2_HIZ_QUAD_PER_TILE_H11 = 0x000000d8, +SC_P2_HIZ_QUAD_PER_TILE_H12 = 0x000000d9, +SC_P2_HIZ_QUAD_PER_TILE_H13 = 0x000000da, +SC_P2_HIZ_QUAD_PER_TILE_H14 = 0x000000db, +SC_P2_HIZ_QUAD_PER_TILE_H15 = 0x000000dc, +SC_P2_HIZ_QUAD_PER_TILE_H16 = 0x000000dd, +SC_P3_HIZ_QUAD_PER_TILE_H0 = 0x000000de, +SC_P3_HIZ_QUAD_PER_TILE_H1 = 0x000000df, +SC_P3_HIZ_QUAD_PER_TILE_H2 = 0x000000e0, +SC_P3_HIZ_QUAD_PER_TILE_H3 = 0x000000e1, +SC_P3_HIZ_QUAD_PER_TILE_H4 = 0x000000e2, +SC_P3_HIZ_QUAD_PER_TILE_H5 = 0x000000e3, +SC_P3_HIZ_QUAD_PER_TILE_H6 = 0x000000e4, +SC_P3_HIZ_QUAD_PER_TILE_H7 = 0x000000e5, +SC_P3_HIZ_QUAD_PER_TILE_H8 = 0x000000e6, +SC_P3_HIZ_QUAD_PER_TILE_H9 = 0x000000e7, +SC_P3_HIZ_QUAD_PER_TILE_H10 = 0x000000e8, +SC_P3_HIZ_QUAD_PER_TILE_H11 = 0x000000e9, +SC_P3_HIZ_QUAD_PER_TILE_H12 = 0x000000ea, +SC_P3_HIZ_QUAD_PER_TILE_H13 = 0x000000eb, +SC_P3_HIZ_QUAD_PER_TILE_H14 = 0x000000ec, +SC_P3_HIZ_QUAD_PER_TILE_H15 = 0x000000ed, +SC_P3_HIZ_QUAD_PER_TILE_H16 = 0x000000ee, +SC_P0_HIZ_QUAD_COUNT = 0x000000ef, +SC_P1_HIZ_QUAD_COUNT = 0x000000f0, +SC_P2_HIZ_QUAD_COUNT = 0x000000f1, +SC_P3_HIZ_QUAD_COUNT = 0x000000f2, +SC_P0_DETAIL_QUAD_COUNT = 0x000000f3, +SC_P1_DETAIL_QUAD_COUNT = 0x000000f4, +SC_P2_DETAIL_QUAD_COUNT = 0x000000f5, +SC_P3_DETAIL_QUAD_COUNT = 0x000000f6, +SC_P0_DETAIL_QUAD_WITH_1_PIX = 0x000000f7, +SC_P0_DETAIL_QUAD_WITH_2_PIX = 0x000000f8, +SC_P0_DETAIL_QUAD_WITH_3_PIX = 0x000000f9, +SC_P0_DETAIL_QUAD_WITH_4_PIX = 0x000000fa, +SC_P1_DETAIL_QUAD_WITH_1_PIX = 0x000000fb, +SC_P1_DETAIL_QUAD_WITH_2_PIX = 0x000000fc, +SC_P1_DETAIL_QUAD_WITH_3_PIX = 0x000000fd, +SC_P1_DETAIL_QUAD_WITH_4_PIX = 0x000000fe, +SC_P2_DETAIL_QUAD_WITH_1_PIX = 0x000000ff, +SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x00000100, +SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x00000101, +SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x00000102, +SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x00000103, +SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x00000104, +SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x00000105, +SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x00000106, +SC_EARLYZ_QUAD_COUNT = 0x00000107, +SC_EARLYZ_QUAD_WITH_1_PIX = 0x00000108, +SC_EARLYZ_QUAD_WITH_2_PIX = 0x00000109, +SC_EARLYZ_QUAD_WITH_3_PIX = 0x0000010a, +SC_EARLYZ_QUAD_WITH_4_PIX = 0x0000010b, +SC_PKR_QUAD_PER_ROW_H1 = 0x0000010c, +SC_PKR_QUAD_PER_ROW_H2 = 0x0000010d, +SC_PKR_4X2_QUAD_SPLIT = 0x0000010e, +SC_PKR_4X2_FILL_QUAD = 0x0000010f, +SC_PKR_END_OF_VECTOR = 0x00000110, +SC_PKR_CONTROL_XFER = 0x00000111, +SC_PKR_DBHANG_FORCE_EOV = 0x00000112, +SC_REG_SCLK_BUSY = 0x00000113, +SC_GRP0_DYN_SCLK_BUSY = 0x00000114, +SC_GRP1_DYN_SCLK_BUSY = 0x00000115, +SC_GRP2_DYN_SCLK_BUSY = 0x00000116, +SC_GRP3_DYN_SCLK_BUSY = 0x00000117, +SC_GRP4_DYN_SCLK_BUSY = 0x00000118, +SC_PA0_SC_DATA_FIFO_RD = 0x00000119, +SC_PA0_SC_DATA_FIFO_WE = 0x0000011a, +SC_PA1_SC_DATA_FIFO_RD = 0x0000011b, +SC_PA1_SC_DATA_FIFO_WE = 0x0000011c, +SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x0000011d, +SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000011e, +SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000011f, +SC_PS_ARB_STALLED_FROM_BELOW = 0x00000120, +SC_PS_ARB_STARVED_FROM_ABOVE = 0x00000121, +SC_PS_ARB_SC_BUSY = 0x00000122, +SC_PS_ARB_PA_SC_BUSY = 0x00000123, +SC_PA2_SC_DATA_FIFO_RD = 0x00000124, +SC_PA2_SC_DATA_FIFO_WE = 0x00000125, +SC_PA3_SC_DATA_FIFO_RD = 0x00000126, +SC_PA3_SC_DATA_FIFO_WE = 0x00000127, +SC_PA_SC_DEALLOC_0_0_WE = 0x00000128, +SC_PA_SC_DEALLOC_0_1_WE = 0x00000129, +SC_PA_SC_DEALLOC_1_0_WE = 0x0000012a, +SC_PA_SC_DEALLOC_1_1_WE = 0x0000012b, +SC_PA_SC_DEALLOC_2_0_WE = 0x0000012c, +SC_PA_SC_DEALLOC_2_1_WE = 0x0000012d, +SC_PA_SC_DEALLOC_3_0_WE = 0x0000012e, +SC_PA_SC_DEALLOC_3_1_WE = 0x0000012f, +SC_PA0_SC_EOP_WE = 0x00000130, +SC_PA0_SC_EOPG_WE = 0x00000131, +SC_PA0_SC_EVENT_WE = 0x00000132, +SC_PA1_SC_EOP_WE = 0x00000133, +SC_PA1_SC_EOPG_WE = 0x00000134, +SC_PA1_SC_EVENT_WE = 0x00000135, +SC_PA2_SC_EOP_WE = 0x00000136, +SC_PA2_SC_EOPG_WE = 0x00000137, +SC_PA2_SC_EVENT_WE = 0x00000138, +SC_PA3_SC_EOP_WE = 0x00000139, +SC_PA3_SC_EOPG_WE = 0x0000013a, +SC_PA3_SC_EVENT_WE = 0x0000013b, +SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x0000013c, +SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 0x0000013d, +SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 0x0000013e, +SC_PS_ARB_EOP_POP_SYNC_POP = 0x0000013f, +SC_PS_ARB_EVENT_SYNC_POP = 0x00000140, +SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 0x00000141, +SC_PA0_SC_FPOV_WE = 0x00000142, +SC_PA1_SC_FPOV_WE = 0x00000143, +SC_PA2_SC_FPOV_WE = 0x00000144, +SC_PA3_SC_FPOV_WE = 0x00000145, +SC_PA0_SC_LPOV_WE = 0x00000146, +SC_PA1_SC_LPOV_WE = 0x00000147, +SC_PA2_SC_LPOV_WE = 0x00000148, +SC_PA3_SC_LPOV_WE = 0x00000149, +SC_SC_SPI_DEALLOC_0_0 = 0x0000014a, +SC_SC_SPI_DEALLOC_0_1 = 0x0000014b, +SC_SC_SPI_DEALLOC_0_2 = 0x0000014c, +SC_SC_SPI_DEALLOC_1_0 = 0x0000014d, +SC_SC_SPI_DEALLOC_1_1 = 0x0000014e, +SC_SC_SPI_DEALLOC_1_2 = 0x0000014f, +SC_SC_SPI_DEALLOC_2_0 = 0x00000150, +SC_SC_SPI_DEALLOC_2_1 = 0x00000151, +SC_SC_SPI_DEALLOC_2_2 = 0x00000152, +SC_SC_SPI_DEALLOC_3_0 = 0x00000153, +SC_SC_SPI_DEALLOC_3_1 = 0x00000154, +SC_SC_SPI_DEALLOC_3_2 = 0x00000155, +SC_SC_SPI_FPOV_0 = 0x00000156, +SC_SC_SPI_FPOV_1 = 0x00000157, +SC_SC_SPI_FPOV_2 = 0x00000158, +SC_SC_SPI_FPOV_3 = 0x00000159, +SC_SC_SPI_EVENT = 0x0000015a, +SC_PS_TS_EVENT_FIFO_PUSH = 0x0000015b, +SC_PS_TS_EVENT_FIFO_POP = 0x0000015c, +SC_PS_CTX_DONE_FIFO_PUSH = 0x0000015d, +SC_PS_CTX_DONE_FIFO_POP = 0x0000015e, +SC_MULTICYCLE_BUBBLE_FREEZE = 0x0000015f, +SC_EOP_SYNC_WINDOW = 0x00000160, +SC_PA0_SC_NULL_WE = 0x00000161, +SC_PA0_SC_NULL_DEALLOC_WE = 0x00000162, +SC_PA0_SC_DATA_FIFO_EOPG_RD = 0x00000163, +SC_PA0_SC_DATA_FIFO_EOP_RD = 0x00000164, +SC_PA0_SC_DEALLOC_0_RD = 0x00000165, +SC_PA0_SC_DEALLOC_1_RD = 0x00000166, +SC_PA1_SC_DATA_FIFO_EOPG_RD = 0x00000167, +SC_PA1_SC_DATA_FIFO_EOP_RD = 0x00000168, +SC_PA1_SC_DEALLOC_0_RD = 0x00000169, +SC_PA1_SC_DEALLOC_1_RD = 0x0000016a, +SC_PA1_SC_NULL_WE = 0x0000016b, +SC_PA1_SC_NULL_DEALLOC_WE = 0x0000016c, +SC_PA2_SC_DATA_FIFO_EOPG_RD = 0x0000016d, +SC_PA2_SC_DATA_FIFO_EOP_RD = 0x0000016e, +SC_PA2_SC_DEALLOC_0_RD = 0x0000016f, +SC_PA2_SC_DEALLOC_1_RD = 0x00000170, +SC_PA2_SC_NULL_WE = 0x00000171, +SC_PA2_SC_NULL_DEALLOC_WE = 0x00000172, +SC_PA3_SC_DATA_FIFO_EOPG_RD = 0x00000173, +SC_PA3_SC_DATA_FIFO_EOP_RD = 0x00000174, +SC_PA3_SC_DEALLOC_0_RD = 0x00000175, +SC_PA3_SC_DEALLOC_1_RD = 0x00000176, +SC_PA3_SC_NULL_WE = 0x00000177, +SC_PA3_SC_NULL_DEALLOC_WE = 0x00000178, +SC_PS_PA0_SC_FIFO_EMPTY = 0x00000179, +SC_PS_PA0_SC_FIFO_FULL = 0x0000017a, +SC_PA0_PS_DATA_SEND = 0x0000017b, +SC_PS_PA1_SC_FIFO_EMPTY = 0x0000017c, +SC_PS_PA1_SC_FIFO_FULL = 0x0000017d, +SC_PA1_PS_DATA_SEND = 0x0000017e, +SC_PS_PA2_SC_FIFO_EMPTY = 0x0000017f, +SC_PS_PA2_SC_FIFO_FULL = 0x00000180, +SC_PA2_PS_DATA_SEND = 0x00000181, +SC_PS_PA3_SC_FIFO_EMPTY = 0x00000182, +SC_PS_PA3_SC_FIFO_FULL = 0x00000183, +SC_PA3_PS_DATA_SEND = 0x00000184, +SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000185, +SC_BUSY_CNT_NOT_ZERO = 0x00000186, +SC_BM_BUSY = 0x00000187, +SC_BACKEND_BUSY = 0x00000188, +SC_SCF_SCB_INTERFACE_BUSY = 0x00000189, +SC_SCB_BUSY = 0x0000018a, +SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 0x0000018b, +SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 0x0000018c, +SC_PBB_BIN_HIST_NUM_PRIMS = 0x0000018d, +SC_PBB_BATCH_HIST_NUM_PRIMS = 0x0000018e, +SC_PBB_BIN_HIST_NUM_CONTEXTS = 0x0000018f, +SC_PBB_BATCH_HIST_NUM_CONTEXTS = 0x00000190, +SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 0x00000191, +SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 0x00000192, +SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 0x00000193, +SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 0x00000194, +SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 0x00000195, +SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 0x00000196, +SC_PBB_BUSY = 0x00000197, +SC_PBB_BUSY_AND_RTR = 0x00000198, +SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 0x00000199, +SC_PBB_NUM_BINS = 0x0000019a, +SC_PBB_END_OF_BIN = 0x0000019b, +SC_PBB_END_OF_BATCH = 0x0000019c, +SC_PBB_PRIMBIN_PROCESSED = 0x0000019d, +SC_PBB_PRIM_ADDED_TO_BATCH = 0x0000019e, +SC_PBB_NONBINNED_PRIM = 0x0000019f, +SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 0x000001a0, +SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 0x000001a1, +SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 0x000001a2, +SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 0x000001a3, +SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 0x000001a4, +SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 0x000001a5, +SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 0x000001a6, +SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 0x000001a7, +SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 0x000001a8, +SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 0x000001a9, +SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 0x000001aa, +SC_POPS_INTRA_WAVE_OVERLAPS = 0x000001ab, +SC_POPS_FORCE_EOV = 0x000001ac, +SC_PKR_QUAD_OVERLAP_NOT_FOUND_IN_WAVE_TABLE = 0x000001ad, +SC_PKR_QUAD_OVERLAP_FOUND_IN_WAVE_TABLE = 0x000001ae, +} SC_PERFCNT_SEL; + +/* + * SePairXsel enum + */ + +typedef enum SePairXsel { +RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x00000000, +RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x00000001, +RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x00000002, +RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x00000003, +RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE = 0x00000004, +} SePairXsel; + +/* + * SePairYsel enum + */ + +typedef enum SePairYsel { +RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x00000000, +RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x00000001, +RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x00000002, +RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x00000003, +RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE = 0x00000004, +} SePairYsel; + +/* + * SePairMap enum + */ + +typedef enum SePairMap { +RASTER_CONFIG_SE_PAIR_MAP_0 = 0x00000000, +RASTER_CONFIG_SE_PAIR_MAP_1 = 0x00000001, +RASTER_CONFIG_SE_PAIR_MAP_2 = 0x00000002, +RASTER_CONFIG_SE_PAIR_MAP_3 = 0x00000003, +} SePairMap; + +/* + * SeXsel enum + */ + +typedef enum SeXsel { +RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x00000000, +RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x00000001, +RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x00000002, +RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x00000003, +RASTER_CONFIG_SE_XSEL_128_WIDE_TILE = 0x00000004, +} SeXsel; + +/* + * SeYsel enum + */ + +typedef enum SeYsel { +RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x00000000, +RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x00000001, +RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x00000002, +RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x00000003, +RASTER_CONFIG_SE_YSEL_128_WIDE_TILE = 0x00000004, +} SeYsel; + +/* + * SeMap enum + */ + +typedef enum SeMap { +RASTER_CONFIG_SE_MAP_0 = 0x00000000, +RASTER_CONFIG_SE_MAP_1 = 0x00000001, +RASTER_CONFIG_SE_MAP_2 = 0x00000002, +RASTER_CONFIG_SE_MAP_3 = 0x00000003, +} SeMap; + +/* + * ScXsel enum + */ + +typedef enum ScXsel { +RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x00000000, +RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x00000001, +RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x00000002, +RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x00000003, +} ScXsel; + +/* + * ScYsel enum + */ + +typedef enum ScYsel { +RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x00000000, +RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x00000001, +RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x00000002, +RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x00000003, +} ScYsel; + +/* + * ScMap enum + */ + +typedef enum ScMap { +RASTER_CONFIG_SC_MAP_0 = 0x00000000, +RASTER_CONFIG_SC_MAP_1 = 0x00000001, +RASTER_CONFIG_SC_MAP_2 = 0x00000002, +RASTER_CONFIG_SC_MAP_3 = 0x00000003, +} ScMap; + +/* + * PkrXsel2 enum + */ + +typedef enum PkrXsel2 { +RASTER_CONFIG_PKR_XSEL2_0 = 0x00000000, +RASTER_CONFIG_PKR_XSEL2_1 = 0x00000001, +RASTER_CONFIG_PKR_XSEL2_2 = 0x00000002, +RASTER_CONFIG_PKR_XSEL2_3 = 0x00000003, +} PkrXsel2; + +/* + * PkrXsel enum + */ + +typedef enum PkrXsel { +RASTER_CONFIG_PKR_XSEL_0 = 0x00000000, +RASTER_CONFIG_PKR_XSEL_1 = 0x00000001, +RASTER_CONFIG_PKR_XSEL_2 = 0x00000002, +RASTER_CONFIG_PKR_XSEL_3 = 0x00000003, +} PkrXsel; + +/* + * PkrYsel enum + */ + +typedef enum PkrYsel { +RASTER_CONFIG_PKR_YSEL_0 = 0x00000000, +RASTER_CONFIG_PKR_YSEL_1 = 0x00000001, +RASTER_CONFIG_PKR_YSEL_2 = 0x00000002, +RASTER_CONFIG_PKR_YSEL_3 = 0x00000003, +} PkrYsel; + +/* + * PkrMap enum + */ + +typedef enum PkrMap { +RASTER_CONFIG_PKR_MAP_0 = 0x00000000, +RASTER_CONFIG_PKR_MAP_1 = 0x00000001, +RASTER_CONFIG_PKR_MAP_2 = 0x00000002, +RASTER_CONFIG_PKR_MAP_3 = 0x00000003, +} PkrMap; + +/* + * RbXsel enum + */ + +typedef enum RbXsel { +RASTER_CONFIG_RB_XSEL_0 = 0x00000000, +RASTER_CONFIG_RB_XSEL_1 = 0x00000001, +} RbXsel; + +/* + * RbYsel enum + */ + +typedef enum RbYsel { +RASTER_CONFIG_RB_YSEL_0 = 0x00000000, +RASTER_CONFIG_RB_YSEL_1 = 0x00000001, +} RbYsel; + +/* + * RbXsel2 enum + */ + +typedef enum RbXsel2 { +RASTER_CONFIG_RB_XSEL2_0 = 0x00000000, +RASTER_CONFIG_RB_XSEL2_1 = 0x00000001, +RASTER_CONFIG_RB_XSEL2_2 = 0x00000002, +RASTER_CONFIG_RB_XSEL2_3 = 0x00000003, +} RbXsel2; + +/* + * RbMap enum + */ + +typedef enum RbMap { +RASTER_CONFIG_RB_MAP_0 = 0x00000000, +RASTER_CONFIG_RB_MAP_1 = 0x00000001, +RASTER_CONFIG_RB_MAP_2 = 0x00000002, +RASTER_CONFIG_RB_MAP_3 = 0x00000003, +} RbMap; + +/* + * BinningMode enum + */ + +typedef enum BinningMode { +BINNING_ALLOWED = 0x00000000, +FORCE_BINNING_ON = 0x00000001, +DISABLE_BINNING_USE_NEW_SC = 0x00000002, +DISABLE_BINNING_USE_LEGACY_SC = 0x00000003, +} BinningMode; + +/* + * BinEventCntl enum + */ + +typedef enum BinEventCntl { +BINNER_BREAK_BATCH = 0x00000000, +BINNER_PIPELINE = 0x00000001, +BINNER_DROP_ASSERT = 0x00000002, +} BinEventCntl; + +/* + * CovToShaderSel enum + */ + +typedef enum CovToShaderSel { +INPUT_COVERAGE = 0x00000000, +INPUT_INNER_COVERAGE = 0x00000001, +INPUT_DEPTH_COVERAGE = 0x00000002, +RAW = 0x00000003, +} CovToShaderSel; + +/******************************************************* + * RMI Enums + *******************************************************/ + +/* + * RMIPerfSel enum + */ + +typedef enum RMIPerfSel { +RMI_PERF_SEL_NONE = 0x00000000, +RMI_PERF_SEL_BUSY = 0x00000001, +RMI_PERF_SEL_REG_CLK_VLD = 0x00000002, +RMI_PERF_SEL_DYN_CLK_CMN_VLD = 0x00000003, +RMI_PERF_SEL_DYN_CLK_RB_VLD = 0x00000004, +RMI_PERF_SEL_DYN_CLK_PERF_VLD = 0x00000005, +RMI_PERF_SEL_PERF_WINDOW = 0x00000006, +RMI_PERF_SEL_EVENT_SEND = 0x00000007, +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0 = 0x00000008, +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1 = 0x00000009, +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2 = 0x0000000a, +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3 = 0x0000000b, +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4 = 0x0000000c, +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5 = 0x0000000d, +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6 = 0x0000000e, +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7 = 0x0000000f, +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8 = 0x00000010, +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9 = 0x00000011, +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10 = 0x00000012, +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11 = 0x00000013, +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12 = 0x00000014, +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13 = 0x00000015, +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14 = 0x00000016, +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15 = 0x00000017, +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL = 0x00000018, +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0 = 0x00000019, +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1 = 0x0000001a, +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2 = 0x0000001b, +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3 = 0x0000001c, +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4 = 0x0000001d, +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5 = 0x0000001e, +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6 = 0x0000001f, +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7 = 0x00000020, +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8 = 0x00000021, +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9 = 0x00000022, +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10 = 0x00000023, +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11 = 0x00000024, +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12 = 0x00000025, +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13 = 0x00000026, +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14 = 0x00000027, +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15 = 0x00000028, +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL = 0x00000029, +RMI_PERF_SEL_UTCL1_TRANSLATION_MISS = 0x0000002a, +RMI_PERF_SEL_UTCL1_PERMISSION_MISS = 0x0000002b, +RMI_PERF_SEL_UTCL1_REQUEST = 0x0000002c, +RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 0x0000002d, +RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 0x0000002e, +RMI_PERF_SEL_UTCL1_LFIFO_FULL = 0x0000002f, +RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 0x00000030, +RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x00000031, +RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 0x00000032, +RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL = 0x00000033, +RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS = 0x00000034, +RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 0x00000035, +RMI_PERF_SEL_RB_RMI_WRREQ_BUSY = 0x00000036, +RMI_PERF_SEL_RB_RMI_WRREQ_CID0 = 0x00000037, +RMI_PERF_SEL_RB_RMI_WRREQ_CID1 = 0x00000038, +RMI_PERF_SEL_RB_RMI_WRREQ_CID2 = 0x00000039, +RMI_PERF_SEL_RB_RMI_WRREQ_CID3 = 0x0000003a, +RMI_PERF_SEL_RB_RMI_WRREQ_CID4 = 0x0000003b, +RMI_PERF_SEL_RB_RMI_WRREQ_CID5 = 0x0000003c, +RMI_PERF_SEL_RB_RMI_WRREQ_CID6 = 0x0000003d, +RMI_PERF_SEL_RB_RMI_WRREQ_CID7 = 0x0000003e, +RMI_PERF_SEL_RB_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID = 0x0000003f, +RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000040, +RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 0x00000041, +RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY = 0x00000042, +RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID = 0x00000043, +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0 = 0x00000044, +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1 = 0x00000045, +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2 = 0x00000046, +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3 = 0x00000047, +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4 = 0x00000048, +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5 = 0x00000049, +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6 = 0x0000004a, +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7 = 0x0000004b, +RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0 = 0x0000004c, +RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1 = 0x0000004d, +RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2 = 0x0000004e, +RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3 = 0x0000004f, +RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID = 0x00000050, +RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 0x00000051, +RMI_PERF_SEL_RB_RMI_RDREQ_BUSY = 0x00000052, +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0 = 0x00000053, +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1 = 0x00000054, +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2 = 0x00000055, +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3 = 0x00000056, +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4 = 0x00000057, +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5 = 0x00000058, +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6 = 0x00000059, +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7 = 0x0000005a, +RMI_PERF_SEL_RB_RMI_RDREQ_CID0 = 0x0000005b, +RMI_PERF_SEL_RB_RMI_RDREQ_CID1 = 0x0000005c, +RMI_PERF_SEL_RB_RMI_RDREQ_CID2 = 0x0000005d, +RMI_PERF_SEL_RB_RMI_RDREQ_CID3 = 0x0000005e, +RMI_PERF_SEL_RB_RMI_RDREQ_CID4 = 0x0000005f, +RMI_PERF_SEL_RB_RMI_RDREQ_CID5 = 0x00000060, +RMI_PERF_SEL_RB_RMI_RDREQ_CID6 = 0x00000061, +RMI_PERF_SEL_RB_RMI_RDREQ_CID7 = 0x00000062, +RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 0x00000063, +RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000064, +RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 0x00000065, +RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY = 0x00000066, +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 0x00000067, +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0 = 0x00000068, +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1 = 0x00000069, +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2 = 0x0000006a, +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3 = 0x0000006b, +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4 = 0x0000006c, +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5 = 0x0000006d, +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6 = 0x0000006e, +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7 = 0x0000006f, +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 0x00000070, +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 0x00000071, +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 0x00000072, +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 0x00000073, +RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID = 0x00000074, +RMI_PERF_SEL_RMI_TC_REQ_BUSY = 0x00000075, +RMI_PERF_SEL_RMI_TC_WRREQ_CID0 = 0x00000076, +RMI_PERF_SEL_RMI_TC_WRREQ_CID1 = 0x00000077, +RMI_PERF_SEL_RMI_TC_WRREQ_CID2 = 0x00000078, +RMI_PERF_SEL_RMI_TC_WRREQ_CID3 = 0x00000079, +RMI_PERF_SEL_RMI_TC_WRREQ_CID4 = 0x0000007a, +RMI_PERF_SEL_RMI_TC_WRREQ_CID5 = 0x0000007b, +RMI_PERF_SEL_RMI_TC_WRREQ_CID6 = 0x0000007c, +RMI_PERF_SEL_RMI_TC_WRREQ_CID7 = 0x0000007d, +RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 0x0000007e, +RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID = 0x0000007f, +RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID = 0x00000080, +RMI_PERF_SEL_RMI_TC_RDREQ_CID0 = 0x00000081, +RMI_PERF_SEL_RMI_TC_RDREQ_CID1 = 0x00000082, +RMI_PERF_SEL_RMI_TC_RDREQ_CID2 = 0x00000083, +RMI_PERF_SEL_RMI_TC_RDREQ_CID3 = 0x00000084, +RMI_PERF_SEL_RMI_TC_RDREQ_CID4 = 0x00000085, +RMI_PERF_SEL_RMI_TC_RDREQ_CID5 = 0x00000086, +RMI_PERF_SEL_RMI_TC_RDREQ_CID6 = 0x00000087, +RMI_PERF_SEL_RMI_TC_RDREQ_CID7 = 0x00000088, +RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 0x00000089, +RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID = 0x0000008a, +RMI_PERF_SEL_UTCL1_BUSY = 0x0000008b, +RMI_PERF_SEL_RMI_UTC_REQ = 0x0000008c, +RMI_PERF_SEL_RMI_UTC_BUSY = 0x0000008d, +RMI_PERF_SEL_UTCL1_UTCL2_REQ = 0x0000008e, +RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY = 0x0000008f, +RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT = 0x00000090, +RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT = 0x00000091, +RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT = 0x00000092, +RMI_PERF_SEL_XNACK_FIFO_NUM_USED = 0x00000093, +RMI_PERF_SEL_LAT_FIFO_NUM_USED = 0x00000094, +RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ = 0x00000095, +RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ = 0x00000096, +RMI_PERF_SEL_XNACK_FIFO_FULL = 0x00000097, +RMI_PERF_SEL_XNACK_FIFO_BUSY = 0x00000098, +RMI_PERF_SEL_LAT_FIFO_FULL = 0x00000099, +RMI_PERF_SEL_SKID_FIFO_DEPTH = 0x0000009a, +RMI_PERF_SEL_TCIW_INFLIGHT_COUNT = 0x0000009b, +RMI_PERF_SEL_PRT_FIFO_NUM_USED = 0x0000009c, +RMI_PERF_SEL_PRT_FIFO_REQ = 0x0000009d, +RMI_PERF_SEL_PRT_FIFO_BUSY = 0x0000009e, +RMI_PERF_SEL_TCIW_REQ = 0x0000009f, +RMI_PERF_SEL_TCIW_BUSY = 0x000000a0, +RMI_PERF_SEL_SKID_FIFO_REQ = 0x000000a1, +RMI_PERF_SEL_SKID_FIFO_BUSY = 0x000000a2, +RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0 = 0x000000a3, +RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1 = 0x000000a4, +RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2 = 0x000000a5, +RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3 = 0x000000a6, +RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR = 0x000000a7, +RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR = 0x000000a8, +RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB = 0x000000a9, +RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB = 0x000000aa, +RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 0x000000ab, +RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 0x000000ac, +RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 0x000000ad, +RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 0x000000ae, +RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR = 0x000000af, +RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR = 0x000000b0, +RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB = 0x000000b1, +RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB = 0x000000b2, +RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR = 0x000000b3, +RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR = 0x000000b4, +RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB = 0x000000b5, +RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB = 0x000000b6, +RMI_PERF_SEL_POP_DEMUX_RTS_RTR = 0x000000b7, +RMI_PERF_SEL_POP_DEMUX_RTSB_RTR = 0x000000b8, +RMI_PERF_SEL_POP_DEMUX_RTS_RTRB = 0x000000b9, +RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB = 0x000000ba, +RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR = 0x000000bb, +RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR = 0x000000bc, +RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB = 0x000000bd, +RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB = 0x000000be, +RMI_PERF_SEL_UTC_POP_RTS_RTR = 0x000000bf, +RMI_PERF_SEL_UTC_POP_RTSB_RTR = 0x000000c0, +RMI_PERF_SEL_UTC_POP_RTS_RTRB = 0x000000c1, +RMI_PERF_SEL_UTC_POP_RTSB_RTRB = 0x000000c2, +RMI_PERF_SEL_POP_XNACK_RTS_RTR = 0x000000c3, +RMI_PERF_SEL_POP_XNACK_RTSB_RTR = 0x000000c4, +RMI_PERF_SEL_POP_XNACK_RTS_RTRB = 0x000000c5, +RMI_PERF_SEL_POP_XNACK_RTSB_RTRB = 0x000000c6, +RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR = 0x000000c7, +RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR = 0x000000c8, +RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB = 0x000000c9, +RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB = 0x000000ca, +RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR = 0x000000cb, +RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR = 0x000000cc, +RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB = 0x000000cd, +RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB = 0x000000ce, +RMI_PERF_SEL_SKID_FIFO_IN_RTS = 0x000000cf, +RMI_PERF_SEL_SKID_FIFO_IN_RTSB = 0x000000d0, +RMI_PERF_SEL_SKID_FIFO_OUT_RTS = 0x000000d1, +RMI_PERF_SEL_SKID_FIFO_OUT_RTSB = 0x000000d2, +RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR = 0x000000d3, +RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR = 0x000000d4, +RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR = 0x000000d5, +RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR = 0x000000d6, +RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR = 0x000000d7, +RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR = 0x000000d8, +RMI_PERF_SEL_REORDER_FIFO_REQ = 0x000000d9, +RMI_PERF_SEL_REORDER_FIFO_BUSY = 0x000000da, +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID = 0x000000db, +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0 = 0x000000dc, +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1 = 0x000000dd, +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2 = 0x000000de, +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3 = 0x000000df, +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4 = 0x000000e0, +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5 = 0x000000e1, +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6 = 0x000000e2, +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7 = 0x000000e3, +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0 = 0x000000e4, +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1 = 0x000000e5, +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2 = 0x000000e6, +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3 = 0x000000e7, +} RMIPerfSel; + +/******************************************************* + * IH Enums + *******************************************************/ + +/* + * IH_PERF_SEL enum + */ + +typedef enum IH_PERF_SEL { +IH_PERF_SEL_CYCLE = 0x00000000, +IH_PERF_SEL_IDLE = 0x00000001, +IH_PERF_SEL_INPUT_IDLE = 0x00000002, +IH_PERF_SEL_BUFFER_IDLE = 0x00000003, +IH_PERF_SEL_RB0_FULL = 0x00000004, +IH_PERF_SEL_RB0_OVERFLOW = 0x00000005, +IH_PERF_SEL_RB0_WPTR_WRITEBACK = 0x00000006, +IH_PERF_SEL_RB0_WPTR_WRAP = 0x00000007, +IH_PERF_SEL_RB0_RPTR_WRAP = 0x00000008, +IH_PERF_SEL_MC_WR_IDLE = 0x00000009, +IH_PERF_SEL_MC_WR_COUNT = 0x0000000a, +IH_PERF_SEL_MC_WR_STALL = 0x0000000b, +IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x0000000c, +IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x0000000d, +IH_PERF_SEL_BIF_LINE0_RISING = 0x0000000e, +IH_PERF_SEL_BIF_LINE0_FALLING = 0x0000000f, +IH_PERF_SEL_RB1_FULL = 0x00000010, +IH_PERF_SEL_RB1_OVERFLOW = 0x00000011, +Reserved18 = 0x00000012, +IH_PERF_SEL_RB1_WPTR_WRAP = 0x00000013, +IH_PERF_SEL_RB1_RPTR_WRAP = 0x00000014, +IH_PERF_SEL_RB2_FULL = 0x00000015, +IH_PERF_SEL_RB2_OVERFLOW = 0x00000016, +Reserved23 = 0x00000017, +IH_PERF_SEL_RB2_WPTR_WRAP = 0x00000018, +IH_PERF_SEL_RB2_RPTR_WRAP = 0x00000019, +Reserved26 = 0x0000001a, +Reserved27 = 0x0000001b, +Reserved28 = 0x0000001c, +Reserved29 = 0x0000001d, +IH_PERF_SEL_RB0_FULL_VF0 = 0x0000001e, +IH_PERF_SEL_RB0_FULL_VF1 = 0x0000001f, +IH_PERF_SEL_RB0_FULL_VF2 = 0x00000020, +IH_PERF_SEL_RB0_FULL_VF3 = 0x00000021, +IH_PERF_SEL_RB0_FULL_VF4 = 0x00000022, +IH_PERF_SEL_RB0_FULL_VF5 = 0x00000023, +IH_PERF_SEL_RB0_FULL_VF6 = 0x00000024, +IH_PERF_SEL_RB0_FULL_VF7 = 0x00000025, +IH_PERF_SEL_RB0_FULL_VF8 = 0x00000026, +IH_PERF_SEL_RB0_FULL_VF9 = 0x00000027, +IH_PERF_SEL_RB0_FULL_VF10 = 0x00000028, +IH_PERF_SEL_RB0_FULL_VF11 = 0x00000029, +IH_PERF_SEL_RB0_FULL_VF12 = 0x0000002a, +IH_PERF_SEL_RB0_FULL_VF13 = 0x0000002b, +IH_PERF_SEL_RB0_FULL_VF14 = 0x0000002c, +IH_PERF_SEL_RB0_FULL_VF15 = 0x0000002d, +IH_PERF_SEL_RB0_OVERFLOW_VF0 = 0x0000002e, +IH_PERF_SEL_RB0_OVERFLOW_VF1 = 0x0000002f, +IH_PERF_SEL_RB0_OVERFLOW_VF2 = 0x00000030, +IH_PERF_SEL_RB0_OVERFLOW_VF3 = 0x00000031, +IH_PERF_SEL_RB0_OVERFLOW_VF4 = 0x00000032, +IH_PERF_SEL_RB0_OVERFLOW_VF5 = 0x00000033, +IH_PERF_SEL_RB0_OVERFLOW_VF6 = 0x00000034, +IH_PERF_SEL_RB0_OVERFLOW_VF7 = 0x00000035, +IH_PERF_SEL_RB0_OVERFLOW_VF8 = 0x00000036, +IH_PERF_SEL_RB0_OVERFLOW_VF9 = 0x00000037, +IH_PERF_SEL_RB0_OVERFLOW_VF10 = 0x00000038, +IH_PERF_SEL_RB0_OVERFLOW_VF11 = 0x00000039, +IH_PERF_SEL_RB0_OVERFLOW_VF12 = 0x0000003a, +IH_PERF_SEL_RB0_OVERFLOW_VF13 = 0x0000003b, +IH_PERF_SEL_RB0_OVERFLOW_VF14 = 0x0000003c, +IH_PERF_SEL_RB0_OVERFLOW_VF15 = 0x0000003d, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 0x0000003e, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 0x0000003f, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 0x00000040, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 0x00000041, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 0x00000042, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 0x00000043, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 0x00000044, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 0x00000045, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 0x00000046, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 0x00000047, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 0x00000048, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 0x00000049, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 0x0000004a, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 0x0000004b, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 0x0000004c, +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 0x0000004d, +IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 0x0000004e, +IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 0x0000004f, +IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 0x00000050, +IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 0x00000051, +IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 0x00000052, +IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 0x00000053, +IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 0x00000054, +IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 0x00000055, +IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 0x00000056, +IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 0x00000057, +IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 0x00000058, +IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 0x00000059, +IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 0x0000005a, +IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 0x0000005b, +IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 0x0000005c, +IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 0x0000005d, +IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 0x0000005e, +IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 0x0000005f, +IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 0x00000060, +IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 0x00000061, +IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 0x00000062, +IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 0x00000063, +IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 0x00000064, +IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 0x00000065, +IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 0x00000066, +IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 0x00000067, +IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 0x00000068, +IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 0x00000069, +IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 0x0000006a, +IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 0x0000006b, +IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 0x0000006c, +IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 0x0000006d, +IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 0x0000006e, +IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 0x0000006f, +IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 0x00000070, +IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 0x00000071, +IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 0x00000072, +IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 0x00000073, +IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 0x00000074, +IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 0x00000075, +IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 0x00000076, +IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 0x00000077, +IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 0x00000078, +IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 0x00000079, +IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 0x0000007a, +IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 0x0000007b, +IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 0x0000007c, +IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 0x0000007d, +IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 0x0000007e, +IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 0x0000007f, +IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 0x00000080, +IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 0x00000081, +IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 0x00000082, +IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 0x00000083, +IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 0x00000084, +IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 0x00000085, +IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 0x00000086, +IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 0x00000087, +IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 0x00000088, +IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 0x00000089, +IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 0x0000008a, +IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 0x0000008b, +IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 0x0000008c, +IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 0x0000008d, +Reserved142 = 0x0000008e, +Reserved143 = 0x0000008f, +Reserved144 = 0x00000090, +Reserved145 = 0x00000091, +Reserved146 = 0x00000092, +Reserved147 = 0x00000093, +Reserved148 = 0x00000094, +Reserved149 = 0x00000095, +IH_PERF_SEL_CLIENT0_INT = 0x00000096, +IH_PERF_SEL_CLIENT1_INT = 0x00000097, +IH_PERF_SEL_CLIENT2_INT = 0x00000098, +IH_PERF_SEL_CLIENT3_INT = 0x00000099, +IH_PERF_SEL_CLIENT4_INT = 0x0000009a, +IH_PERF_SEL_CLIENT5_INT = 0x0000009b, +IH_PERF_SEL_CLIENT6_INT = 0x0000009c, +IH_PERF_SEL_CLIENT7_INT = 0x0000009d, +IH_PERF_SEL_CLIENT8_INT = 0x0000009e, +IH_PERF_SEL_CLIENT9_INT = 0x0000009f, +IH_PERF_SEL_CLIENT10_INT = 0x000000a0, +IH_PERF_SEL_CLIENT11_INT = 0x000000a1, +IH_PERF_SEL_CLIENT12_INT = 0x000000a2, +IH_PERF_SEL_CLIENT13_INT = 0x000000a3, +IH_PERF_SEL_CLIENT14_INT = 0x000000a4, +IH_PERF_SEL_CLIENT15_INT = 0x000000a5, +IH_PERF_SEL_CLIENT16_INT = 0x000000a6, +IH_PERF_SEL_CLIENT17_INT = 0x000000a7, +IH_PERF_SEL_CLIENT18_INT = 0x000000a8, +IH_PERF_SEL_CLIENT19_INT = 0x000000a9, +IH_PERF_SEL_CLIENT20_INT = 0x000000aa, +IH_PERF_SEL_CLIENT21_INT = 0x000000ab, +IH_PERF_SEL_CLIENT22_INT = 0x000000ac, +IH_PERF_SEL_CLIENT23_INT = 0x000000ad, +IH_PERF_SEL_CLIENT24_INT = 0x000000ae, +IH_PERF_SEL_CLIENT25_INT = 0x000000af, +IH_PERF_SEL_CLIENT26_INT = 0x000000b0, +IH_PERF_SEL_CLIENT27_INT = 0x000000b1, +IH_PERF_SEL_CLIENT28_INT = 0x000000b2, +IH_PERF_SEL_CLIENT29_INT = 0x000000b3, +IH_PERF_SEL_CLIENT30_INT = 0x000000b4, +IH_PERF_SEL_CLIENT31_INT = 0x000000b5, +Reserved182 = 0x000000b6, +Reserved183 = 0x000000b7, +Reserved184 = 0x000000b8, +Reserved185 = 0x000000b9, +Reserved186 = 0x000000ba, +Reserved187 = 0x000000bb, +Reserved188 = 0x000000bc, +Reserved189 = 0x000000bd, +Reserved190 = 0x000000be, +Reserved191 = 0x000000bf, +Reserved192 = 0x000000c0, +Reserved193 = 0x000000c1, +Reserved194 = 0x000000c2, +Reserved195 = 0x000000c3, +Reserved196 = 0x000000c4, +Reserved197 = 0x000000c5, +Reserved198 = 0x000000c6, +Reserved199 = 0x000000c7, +Reserved200 = 0x000000c8, +Reserved201 = 0x000000c9, +Reserved202 = 0x000000ca, +Reserved203 = 0x000000cb, +Reserved204 = 0x000000cc, +Reserved205 = 0x000000cd, +Reserved206 = 0x000000ce, +Reserved207 = 0x000000cf, +Reserved208 = 0x000000d0, +Reserved209 = 0x000000d1, +Reserved210 = 0x000000d2, +Reserved211 = 0x000000d3, +Reserved212 = 0x000000d4, +Reserved213 = 0x000000d5, +Reserved214 = 0x000000d6, +Reserved215 = 0x000000d7, +Reserved216 = 0x000000d8, +Reserved217 = 0x000000d9, +Reserved218 = 0x000000da, +Reserved219 = 0x000000db, +IH_PERF_SEL_RB1_FULL_VF0 = 0x000000dc, +IH_PERF_SEL_RB1_FULL_VF1 = 0x000000dd, +IH_PERF_SEL_RB1_FULL_VF2 = 0x000000de, +IH_PERF_SEL_RB1_FULL_VF3 = 0x000000df, +IH_PERF_SEL_RB1_FULL_VF4 = 0x000000e0, +IH_PERF_SEL_RB1_FULL_VF5 = 0x000000e1, +IH_PERF_SEL_RB1_FULL_VF6 = 0x000000e2, +IH_PERF_SEL_RB1_FULL_VF7 = 0x000000e3, +IH_PERF_SEL_RB1_FULL_VF8 = 0x000000e4, +IH_PERF_SEL_RB1_FULL_VF9 = 0x000000e5, +IH_PERF_SEL_RB1_FULL_VF10 = 0x000000e6, +IH_PERF_SEL_RB1_FULL_VF11 = 0x000000e7, +IH_PERF_SEL_RB1_FULL_VF12 = 0x000000e8, +IH_PERF_SEL_RB1_FULL_VF13 = 0x000000e9, +IH_PERF_SEL_RB1_FULL_VF14 = 0x000000ea, +IH_PERF_SEL_RB1_FULL_VF15 = 0x000000eb, +IH_PERF_SEL_RB1_OVERFLOW_VF0 = 0x000000ec, +IH_PERF_SEL_RB1_OVERFLOW_VF1 = 0x000000ed, +IH_PERF_SEL_RB1_OVERFLOW_VF2 = 0x000000ee, +IH_PERF_SEL_RB1_OVERFLOW_VF3 = 0x000000ef, +IH_PERF_SEL_RB1_OVERFLOW_VF4 = 0x000000f0, +IH_PERF_SEL_RB1_OVERFLOW_VF5 = 0x000000f1, +IH_PERF_SEL_RB1_OVERFLOW_VF6 = 0x000000f2, +IH_PERF_SEL_RB1_OVERFLOW_VF7 = 0x000000f3, +IH_PERF_SEL_RB1_OVERFLOW_VF8 = 0x000000f4, +IH_PERF_SEL_RB1_OVERFLOW_VF9 = 0x000000f5, +IH_PERF_SEL_RB1_OVERFLOW_VF10 = 0x000000f6, +IH_PERF_SEL_RB1_OVERFLOW_VF11 = 0x000000f7, +IH_PERF_SEL_RB1_OVERFLOW_VF12 = 0x000000f8, +IH_PERF_SEL_RB1_OVERFLOW_VF13 = 0x000000f9, +IH_PERF_SEL_RB1_OVERFLOW_VF14 = 0x000000fa, +IH_PERF_SEL_RB1_OVERFLOW_VF15 = 0x000000fb, +Reserved252 = 0x000000fc, +Reserved253 = 0x000000fd, +Reserved254 = 0x000000fe, +Reserved255 = 0x000000ff, +Reserved256 = 0x00000100, +Reserved257 = 0x00000101, +Reserved258 = 0x00000102, +Reserved259 = 0x00000103, +Reserved260 = 0x00000104, +Reserved261 = 0x00000105, +Reserved262 = 0x00000106, +Reserved263 = 0x00000107, +Reserved264 = 0x00000108, +Reserved265 = 0x00000109, +Reserved266 = 0x0000010a, +Reserved267 = 0x0000010b, +IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 0x0000010c, +IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 0x0000010d, +IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 0x0000010e, +IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 0x0000010f, +IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 0x00000110, +IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 0x00000111, +IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 0x00000112, +IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 0x00000113, +IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 0x00000114, +IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 0x00000115, +IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 0x00000116, +IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 0x00000117, +IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 0x00000118, +IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 0x00000119, +IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 0x0000011a, +IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 0x0000011b, +IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 0x0000011c, +IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 0x0000011d, +IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 0x0000011e, +IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 0x0000011f, +IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 0x00000120, +IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 0x00000121, +IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 0x00000122, +IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 0x00000123, +IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 0x00000124, +IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 0x00000125, +IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 0x00000126, +IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 0x00000127, +IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 0x00000128, +IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 0x00000129, +IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 0x0000012a, +IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 0x0000012b, +Reserved300 = 0x0000012c, +Reserved301 = 0x0000012d, +Reserved302 = 0x0000012e, +Reserved303 = 0x0000012f, +Reserved304 = 0x00000130, +Reserved305 = 0x00000131, +Reserved306 = 0x00000132, +Reserved307 = 0x00000133, +Reserved308 = 0x00000134, +Reserved309 = 0x00000135, +Reserved310 = 0x00000136, +Reserved311 = 0x00000137, +Reserved312 = 0x00000138, +Reserved313 = 0x00000139, +Reserved314 = 0x0000013a, +Reserved315 = 0x0000013b, +Reserved316 = 0x0000013c, +Reserved317 = 0x0000013d, +Reserved318 = 0x0000013e, +Reserved319 = 0x0000013f, +Reserved320 = 0x00000140, +Reserved321 = 0x00000141, +Reserved322 = 0x00000142, +Reserved323 = 0x00000143, +Reserved324 = 0x00000144, +Reserved325 = 0x00000145, +Reserved326 = 0x00000146, +Reserved327 = 0x00000147, +Reserved328 = 0x00000148, +Reserved329 = 0x00000149, +Reserved330 = 0x0000014a, +Reserved331 = 0x0000014b, +IH_PERF_SEL_RB2_FULL_VF0 = 0x0000014c, +IH_PERF_SEL_RB2_FULL_VF1 = 0x0000014d, +IH_PERF_SEL_RB2_FULL_VF2 = 0x0000014e, +IH_PERF_SEL_RB2_FULL_VF3 = 0x0000014f, +IH_PERF_SEL_RB2_FULL_VF4 = 0x00000150, +IH_PERF_SEL_RB2_FULL_VF5 = 0x00000151, +IH_PERF_SEL_RB2_FULL_VF6 = 0x00000152, +IH_PERF_SEL_RB2_FULL_VF7 = 0x00000153, +IH_PERF_SEL_RB2_FULL_VF8 = 0x00000154, +IH_PERF_SEL_RB2_FULL_VF9 = 0x00000155, +IH_PERF_SEL_RB2_FULL_VF10 = 0x00000156, +IH_PERF_SEL_RB2_FULL_VF11 = 0x00000157, +IH_PERF_SEL_RB2_FULL_VF12 = 0x00000158, +IH_PERF_SEL_RB2_FULL_VF13 = 0x00000159, +IH_PERF_SEL_RB2_FULL_VF14 = 0x0000015a, +IH_PERF_SEL_RB2_FULL_VF15 = 0x0000015b, +IH_PERF_SEL_RB2_OVERFLOW_VF0 = 0x0000015c, +IH_PERF_SEL_RB2_OVERFLOW_VF1 = 0x0000015d, +IH_PERF_SEL_RB2_OVERFLOW_VF2 = 0x0000015e, +IH_PERF_SEL_RB2_OVERFLOW_VF3 = 0x0000015f, +IH_PERF_SEL_RB2_OVERFLOW_VF4 = 0x00000160, +IH_PERF_SEL_RB2_OVERFLOW_VF5 = 0x00000161, +IH_PERF_SEL_RB2_OVERFLOW_VF6 = 0x00000162, +IH_PERF_SEL_RB2_OVERFLOW_VF7 = 0x00000163, +IH_PERF_SEL_RB2_OVERFLOW_VF8 = 0x00000164, +IH_PERF_SEL_RB2_OVERFLOW_VF9 = 0x00000165, +IH_PERF_SEL_RB2_OVERFLOW_VF10 = 0x00000166, +IH_PERF_SEL_RB2_OVERFLOW_VF11 = 0x00000167, +IH_PERF_SEL_RB2_OVERFLOW_VF12 = 0x00000168, +IH_PERF_SEL_RB2_OVERFLOW_VF13 = 0x00000169, +IH_PERF_SEL_RB2_OVERFLOW_VF14 = 0x0000016a, +IH_PERF_SEL_RB2_OVERFLOW_VF15 = 0x0000016b, +Reserved364 = 0x0000016c, +Reserved365 = 0x0000016d, +Reserved366 = 0x0000016e, +Reserved367 = 0x0000016f, +Reserved368 = 0x00000170, +Reserved369 = 0x00000171, +Reserved370 = 0x00000172, +Reserved371 = 0x00000173, +Reserved372 = 0x00000174, +Reserved373 = 0x00000175, +Reserved374 = 0x00000176, +Reserved375 = 0x00000177, +Reserved376 = 0x00000178, +Reserved377 = 0x00000179, +Reserved378 = 0x0000017a, +Reserved379 = 0x0000017b, +IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 0x0000017c, +IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 0x0000017d, +IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 0x0000017e, +IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 0x0000017f, +IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 0x00000180, +IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 0x00000181, +IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 0x00000182, +IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 0x00000183, +IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 0x00000184, +IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 0x00000185, +IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 0x00000186, +IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 0x00000187, +IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 0x00000188, +IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 0x00000189, +IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 0x0000018a, +IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 0x0000018b, +IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 0x0000018c, +IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 0x0000018d, +IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 0x0000018e, +IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 0x0000018f, +IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 0x00000190, +IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 0x00000191, +IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 0x00000192, +IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 0x00000193, +IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 0x00000194, +IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 0x00000195, +IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 0x00000196, +IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 0x00000197, +IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 0x00000198, +IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 0x00000199, +IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 0x0000019a, +IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 0x0000019b, +Reserved412 = 0x0000019c, +Reserved413 = 0x0000019d, +Reserved414 = 0x0000019e, +Reserved415 = 0x0000019f, +Reserved416 = 0x000001a0, +Reserved417 = 0x000001a1, +Reserved418 = 0x000001a2, +Reserved419 = 0x000001a3, +Reserved420 = 0x000001a4, +Reserved421 = 0x000001a5, +Reserved422 = 0x000001a6, +Reserved423 = 0x000001a7, +Reserved424 = 0x000001a8, +Reserved425 = 0x000001a9, +Reserved426 = 0x000001aa, +Reserved427 = 0x000001ab, +Reserved428 = 0x000001ac, +Reserved429 = 0x000001ad, +Reserved430 = 0x000001ae, +Reserved431 = 0x000001af, +Reserved432 = 0x000001b0, +Reserved433 = 0x000001b1, +Reserved434 = 0x000001b2, +Reserved435 = 0x000001b3, +Reserved436 = 0x000001b4, +Reserved437 = 0x000001b5, +Reserved438 = 0x000001b6, +Reserved439 = 0x000001b7, +Reserved440 = 0x000001b8, +Reserved441 = 0x000001b9, +Reserved442 = 0x000001ba, +Reserved443 = 0x000001bb, +Reserved444 = 0x000001bc, +Reserved445 = 0x000001bd, +Reserved446 = 0x000001be, +Reserved447 = 0x000001bf, +Reserved448 = 0x000001c0, +Reserved449 = 0x000001c1, +Reserved450 = 0x000001c2, +Reserved451 = 0x000001c3, +Reserved452 = 0x000001c4, +Reserved453 = 0x000001c5, +Reserved454 = 0x000001c6, +Reserved455 = 0x000001c7, +Reserved456 = 0x000001c8, +Reserved457 = 0x000001c9, +Reserved458 = 0x000001ca, +Reserved459 = 0x000001cb, +Reserved460 = 0x000001cc, +Reserved461 = 0x000001cd, +Reserved462 = 0x000001ce, +Reserved463 = 0x000001cf, +Reserved464 = 0x000001d0, +Reserved465 = 0x000001d1, +Reserved466 = 0x000001d2, +Reserved467 = 0x000001d3, +Reserved468 = 0x000001d4, +Reserved469 = 0x000001d5, +Reserved470 = 0x000001d6, +Reserved471 = 0x000001d7, +Reserved472 = 0x000001d8, +Reserved473 = 0x000001d9, +Reserved474 = 0x000001da, +Reserved475 = 0x000001db, +Reserved476 = 0x000001dc, +Reserved477 = 0x000001dd, +Reserved478 = 0x000001de, +Reserved479 = 0x000001df, +Reserved480 = 0x000001e0, +Reserved481 = 0x000001e1, +Reserved482 = 0x000001e2, +Reserved483 = 0x000001e3, +Reserved484 = 0x000001e4, +Reserved485 = 0x000001e5, +Reserved486 = 0x000001e6, +Reserved487 = 0x000001e7, +Reserved488 = 0x000001e8, +Reserved489 = 0x000001e9, +Reserved490 = 0x000001ea, +Reserved491 = 0x000001eb, +Reserved492 = 0x000001ec, +Reserved493 = 0x000001ed, +Reserved494 = 0x000001ee, +Reserved495 = 0x000001ef, +Reserved496 = 0x000001f0, +Reserved497 = 0x000001f1, +Reserved498 = 0x000001f2, +Reserved499 = 0x000001f3, +Reserved500 = 0x000001f4, +Reserved501 = 0x000001f5, +Reserved502 = 0x000001f6, +Reserved503 = 0x000001f7, +Reserved504 = 0x000001f8, +Reserved505 = 0x000001f9, +Reserved506 = 0x000001fa, +Reserved507 = 0x000001fb, +Reserved508 = 0x000001fc, +Reserved509 = 0x000001fd, +Reserved510 = 0x000001fe, +Reserved511 = 0x000001ff, +} IH_PERF_SEL; + +/******************************************************* + * SEM Enums + *******************************************************/ + +/* + * SEM_PERF_SEL enum + */ + +typedef enum SEM_PERF_SEL { +SEM_PERF_SEL_CYCLE = 0x00000000, +SEM_PERF_SEL_IDLE = 0x00000001, +SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 0x00000002, +SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 0x00000003, +SEM_PERF_SEL_UVD_REQ_SIGNAL = 0x00000004, +SEM_PERF_SEL_VCE0_REQ_SIGNAL = 0x00000005, +SEM_PERF_SEL_ACP_REQ_SIGNAL = 0x00000006, +SEM_PERF_SEL_ISP_REQ_SIGNAL = 0x00000007, +SEM_PERF_SEL_VCE1_REQ_SIGNAL = 0x00000008, +SEM_PERF_SEL_VP8_REQ_SIGNAL = 0x00000009, +SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 0x0000000a, +SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 0x0000000b, +SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 0x0000000c, +SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 0x0000000d, +SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 0x0000000e, +SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 0x0000000f, +SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 0x00000010, +SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 0x00000011, +SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 0x00000012, +SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 0x00000013, +SEM_PERF_SEL_SDMA0_REQ_WAIT = 0x00000014, +SEM_PERF_SEL_SDMA1_REQ_WAIT = 0x00000015, +SEM_PERF_SEL_UVD_REQ_WAIT = 0x00000016, +SEM_PERF_SEL_VCE0_REQ_WAIT = 0x00000017, +SEM_PERF_SEL_ACP_REQ_WAIT = 0x00000018, +SEM_PERF_SEL_ISP_REQ_WAIT = 0x00000019, +SEM_PERF_SEL_VCE1_REQ_WAIT = 0x0000001a, +SEM_PERF_SEL_VP8_REQ_WAIT = 0x0000001b, +SEM_PERF_SEL_CPG_E0_REQ_WAIT = 0x0000001c, +SEM_PERF_SEL_CPG_E1_REQ_WAIT = 0x0000001d, +SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 0x0000001e, +SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 0x0000001f, +SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 0x00000020, +SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 0x00000021, +SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 0x00000022, +SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 0x00000023, +SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 0x00000024, +SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 0x00000025, +SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 0x00000026, +SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 0x00000027, +SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 0x00000028, +SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 0x00000029, +SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 0x0000002a, +SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 0x0000002b, +SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 0x0000002c, +SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 0x0000002d, +SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 0x0000002e, +SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 0x0000002f, +SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 0x00000030, +SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 0x00000031, +SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 0x00000032, +SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 0x00000033, +SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 0x00000034, +SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 0x00000035, +SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 0x00000036, +SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 0x00000037, +SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 0x00000038, +SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 0x00000039, +SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 0x0000003a, +SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 0x0000003b, +SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 0x0000003c, +SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 0x0000003d, +SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 0x0000003e, +SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 0x0000003f, +SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 0x00000040, +SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 0x00000041, +SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 0x00000042, +SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 0x00000043, +SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 0x00000044, +SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 0x00000045, +SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 0x00000046, +SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 0x00000047, +SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 0x00000048, +SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 0x00000049, +SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 0x0000004a, +SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 0x0000004b, +SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 0x0000004c, +SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 0x0000004d, +SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 0x0000004e, +SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 0x0000004f, +SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 0x00000050, +SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 0x00000051, +SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 0x00000052, +SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 0x00000053, +SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 0x00000054, +SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 0x00000055, +SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 0x00000056, +SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 0x00000057, +SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 0x00000058, +SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 0x00000059, +SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 0x0000005a, +SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 0x0000005b, +SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 0x0000005c, +SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 0x0000005d, +SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 0x0000005e, +SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 0x0000005f, +SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 0x00000060, +SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 0x00000061, +SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 0x00000062, +SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 0x00000063, +SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 0x00000064, +SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 0x00000065, +SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 0x00000066, +SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 0x00000067, +SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 0x00000068, +SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 0x00000069, +SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 0x0000006a, +SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 0x0000006b, +SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 0x0000006c, +SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 0x0000006d, +SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 0x0000006e, +SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 0x0000006f, +SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 0x00000070, +SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 0x00000071, +SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 0x00000072, +SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 0x00000073, +SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 0x00000074, +SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 0x00000075, +SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 0x00000076, +SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 0x00000077, +SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 0x00000078, +SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 0x00000079, +SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 0x0000007a, +SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 0x0000007b, +SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 0x0000007c, +SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 0x0000007d, +SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 0x0000007e, +SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 0x0000007f, +SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 0x00000080, +SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 0x00000081, +SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 0x00000082, +SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 0x00000083, +SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 0x00000084, +SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 0x00000085, +SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 0x00000086, +SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 0x00000087, +SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 0x00000088, +SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 0x00000089, +SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 0x0000008a, +SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 0x0000008b, +SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 0x0000008c, +SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 0x0000008d, +SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 0x0000008e, +SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 0x0000008f, +SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 0x00000090, +SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 0x00000091, +SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 0x00000092, +SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 0x00000093, +SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 0x00000094, +SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 0x00000095, +SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 0x00000096, +SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 0x00000097, +SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 0x00000098, +SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 0x00000099, +SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 0x0000009a, +SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 0x0000009b, +SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 0x0000009c, +SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 0x0000009d, +SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 0x0000009e, +SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 0x0000009f, +SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 0x000000a0, +SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 0x000000a1, +SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 0x000000a2, +SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 0x000000a3, +SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 0x000000a4, +SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 0x000000a5, +SEM_PERF_SEL_MC_RD_REQ = 0x000000a6, +SEM_PERF_SEL_MC_RD_RET = 0x000000a7, +SEM_PERF_SEL_MC_WR_REQ = 0x000000a8, +SEM_PERF_SEL_MC_WR_RET = 0x000000a9, +SEM_PERF_SEL_ATC_REQ = 0x000000aa, +SEM_PERF_SEL_ATC_RET = 0x000000ab, +SEM_PERF_SEL_ATC_XNACK = 0x000000ac, +SEM_PERF_SEL_ATC_INVALIDATION = 0x000000ad, +} SEM_PERF_SEL; + +/******************************************************* + * SDMA Enums + *******************************************************/ + +/* + * SDMA_PERF_SEL enum + */ + +typedef enum SDMA_PERF_SEL { +SDMA_PERF_SEL_CYCLE = 0x00000000, +SDMA_PERF_SEL_IDLE = 0x00000001, +SDMA_PERF_SEL_REG_IDLE = 0x00000002, +SDMA_PERF_SEL_RB_EMPTY = 0x00000003, +SDMA_PERF_SEL_RB_FULL = 0x00000004, +SDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005, +SDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006, +SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007, +SDMA_PERF_SEL_RB_RPTR_WB = 0x00000008, +SDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009, +SDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a, +SDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b, +SDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c, +SDMA_PERF_SEL_EX_IDLE = 0x0000000d, +SDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e, +SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f, +SDMA_PERF_SEL_MC_WR_IDLE = 0x00000010, +SDMA_PERF_SEL_MC_WR_COUNT = 0x00000011, +SDMA_PERF_SEL_MC_RD_IDLE = 0x00000012, +SDMA_PERF_SEL_MC_RD_COUNT = 0x00000013, +SDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014, +SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015, +SDMA_PERF_SEL_SEM_IDLE = 0x00000018, +SDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019, +SDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a, +SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b, +SDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c, +SDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d, +SDMA_PERF_SEL_INT_IDLE = 0x0000001e, +SDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f, +SDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020, +SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021, +SDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022, +SDMA_PERF_SEL_NUM_PACKET = 0x00000023, +SDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025, +SDMA_PERF_SEL_CE_WR_IDLE = 0x00000026, +SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027, +SDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028, +SDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029, +SDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a, +SDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b, +SDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e, +SDMA_PERF_SEL_CE_INFO_FULL = 0x00000031, +SDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032, +SDMA_PERF_SEL_CE_RD_STALL = 0x00000033, +SDMA_PERF_SEL_CE_WR_STALL = 0x00000034, +SDMA_PERF_SEL_GFX_SELECT = 0x00000035, +SDMA_PERF_SEL_RLC0_SELECT = 0x00000036, +SDMA_PERF_SEL_RLC1_SELECT = 0x00000037, +SDMA_PERF_SEL_PAGE_SELECT = 0x00000038, +SDMA_PERF_SEL_CTX_CHANGE = 0x00000039, +SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x0000003a, +SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x0000003b, +SDMA_PERF_SEL_DOORBELL = 0x0000003c, +SDMA_PERF_SEL_RD_BA_RTR = 0x0000003d, +SDMA_PERF_SEL_WR_BA_RTR = 0x0000003e, +SDMA_PERF_SEL_F32_L1_WR_VLD = 0x0000003f, +SDMA_PERF_SEL_CE_L1_WR_VLD = 0x00000040, +SDMA_PERF_SEL_CE_L1_STALL = 0x00000041, +SDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 0x00000042, +SDMA_PERF_SEL_SDMA_INVACK_FLUSH = 0x00000043, +SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 0x00000044, +SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 0x00000045, +SDMA_PERF_SEL_ATCL2_RET_XNACK = 0x00000046, +SDMA_PERF_SEL_ATCL2_RET_ACK = 0x00000047, +SDMA_PERF_SEL_ATCL2_FREE = 0x00000048, +SDMA_PERF_SEL_SDMA_ATCL2_SEND = 0x00000049, +SDMA_PERF_SEL_DMA_L1_WR_SEND = 0x0000004a, +SDMA_PERF_SEL_DMA_L1_RD_SEND = 0x0000004b, +SDMA_PERF_SEL_DMA_MC_WR_SEND = 0x0000004c, +SDMA_PERF_SEL_DMA_MC_RD_SEND = 0x0000004d, +SDMA_PERF_SEL_L1_WR_FIFO_IDLE = 0x0000004e, +SDMA_PERF_SEL_L1_RD_FIFO_IDLE = 0x0000004f, +SDMA_PERF_SEL_L1_WRL2_IDLE = 0x00000050, +SDMA_PERF_SEL_L1_RDL2_IDLE = 0x00000051, +SDMA_PERF_SEL_L1_WRMC_IDLE = 0x00000052, +SDMA_PERF_SEL_L1_RDMC_IDLE = 0x00000053, +SDMA_PERF_SEL_L1_WR_INV_IDLE = 0x00000054, +SDMA_PERF_SEL_L1_RD_INV_IDLE = 0x00000055, +SDMA_PERF_SEL_L1_WR_INV_EN = 0x00000056, +SDMA_PERF_SEL_L1_RD_INV_EN = 0x00000057, +SDMA_PERF_SEL_L1_WR_WAIT_INVADR = 0x00000058, +SDMA_PERF_SEL_L1_RD_WAIT_INVADR = 0x00000059, +SDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 0x0000005a, +SDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 0x0000005b, +SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 0x0000005c, +SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 0x0000005d, +SDMA_PERF_SEL_L1_INV_MIDDLE = 0x0000005e, +SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER = 0x000000fe, +SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER = 0x000000ff, +} SDMA_PERF_SEL; + +/******************************************************* + * SMUIO Enums + *******************************************************/ + +/* + * ROM_SIGNATURE value + */ + +#define ROM_SIGNATURE 0x0000aa55 + +/******************************************************* + * XDMA_CMN Enums + *******************************************************/ + +/* + * ENUM_XDMA_LOCAL_SW_MODE enum + */ + +typedef enum ENUM_XDMA_LOCAL_SW_MODE { +XDMA_LOCAL_SW_MODE_SW_256B_D = 0x00000002, +XDMA_LOCAL_SW_MODE_SW_64KB_D = 0x0000000a, +XDMA_LOCAL_SW_MODE_SW_64KB_D_X = 0x0000001a, +} ENUM_XDMA_LOCAL_SW_MODE; + +/******************************************************* + * XDMA_SLV Enums + *******************************************************/ + +/* + * ENUM_XDMA_SLV_ALPHA_POSITION enum + */ + +typedef enum ENUM_XDMA_SLV_ALPHA_POSITION { +XDMA_SLV_ALPHA_POSITION_7_0 = 0x00000000, +XDMA_SLV_ALPHA_POSITION_15_8 = 0x00000001, +XDMA_SLV_ALPHA_POSITION_23_16 = 0x00000002, +XDMA_SLV_ALPHA_POSITION_31_24 = 0x00000003, +} ENUM_XDMA_SLV_ALPHA_POSITION; + +/******************************************************* + * XDMA_MSTR Enums + *******************************************************/ + +/* + * ENUM_XDMA_MSTR_ALPHA_POSITION enum + */ + +typedef enum ENUM_XDMA_MSTR_ALPHA_POSITION { +XDMA_MSTR_ALPHA_POSITION_7_0 = 0x00000000, +XDMA_MSTR_ALPHA_POSITION_15_8 = 0x00000001, +XDMA_MSTR_ALPHA_POSITION_23_16 = 0x00000002, +XDMA_MSTR_ALPHA_POSITION_31_24 = 0x00000003, +} ENUM_XDMA_MSTR_ALPHA_POSITION; + +/* + * ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL enum + */ + +typedef enum ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL { +XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE0 = 0x00000000, +XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE1 = 0x00000001, +XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE2 = 0x00000002, +XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE3 = 0x00000003, +XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE4 = 0x00000004, +XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE5 = 0x00000005, +} ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL; + + +#endif /*_vega10_ENUM_HEADER*/ + diff --git a/extra/amdpci/overlay/gc_9_4_3.h b/extra/amdpci/overlay/gc_9_4_3.h new file mode 100644 index 0000000000..c937e68a48 --- /dev/null +++ b/extra/amdpci/overlay/gc_9_4_3.h @@ -0,0 +1,7 @@ +// From MQD struct +#define regCOMPUTE_CURRENT_LOGIC_XCC_ID 0x0e25 +#define regCOMPUTE_CURRENT_LOGIC_XCC_ID_BASE_IDX 0 +// Mask is probably not full register, doesn't matter though +#define COMPUTE_CURRENT_LOGIC_XCC_ID__CURRENT_LOGIC_XCC_ID__SHIFT 0x0 +#define COMPUTE_CURRENT_LOGIC_XCC_ID__CURRENT_LOGIC_XCC_ID_MASK 0xFFFFFFFFL + diff --git a/extra/hip_gpu_driver/soc15d.h b/extra/hip_gpu_driver/soc15d.h new file mode 100644 index 0000000000..b9cbeb389e --- /dev/null +++ b/extra/hip_gpu_driver/soc15d.h @@ -0,0 +1,444 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef SOC15_H +#define SOC15_H + +#define GFX9_NUM_GFX_RINGS 1 +#define GFX9_NUM_COMPUTE_RINGS 8 + +/* + * PM4 + */ +#define PACKET_TYPE0 0 +#define PACKET_TYPE1 1 +#define PACKET_TYPE2 2 +#define PACKET_TYPE3 3 + +#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) +#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) +#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) +#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) +#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ + ((reg) & 0xFFFF) | \ + ((n) & 0x3FFF) << 16) +#define CP_PACKET2 0x80000000 +#define PACKET2_PAD_SHIFT 0 +#define PACKET2_PAD_MASK (0x3fffffff << 0) + +#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) + +#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ + (((op) & 0xFF) << 8) | \ + ((n) & 0x3FFF) << 16) + +#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) + +#define PACKETJ_CONDITION_CHECK0 0 +#define PACKETJ_CONDITION_CHECK1 1 +#define PACKETJ_CONDITION_CHECK2 2 +#define PACKETJ_CONDITION_CHECK3 3 +#define PACKETJ_CONDITION_CHECK4 4 +#define PACKETJ_CONDITION_CHECK5 5 +#define PACKETJ_CONDITION_CHECK6 6 +#define PACKETJ_CONDITION_CHECK7 7 + +#define PACKETJ_TYPE0 0 +#define PACKETJ_TYPE1 1 +#define PACKETJ_TYPE2 2 +#define PACKETJ_TYPE3 3 +#define PACKETJ_TYPE4 4 +#define PACKETJ_TYPE5 5 +#define PACKETJ_TYPE6 6 +#define PACKETJ_TYPE7 7 + +#define PACKETJ(reg, r, cond, type) ((reg & 0x3FFFF) | \ + ((r & 0x3F) << 18) | \ + ((cond & 0xF) << 24) | \ + ((type & 0xF) << 28)) + +#define CP_PACKETJ_NOP 0x60000000 +#define CP_PACKETJ_GET_REG(x) ((x) & 0x3FFFF) +#define CP_PACKETJ_GET_RES(x) (((x) >> 18) & 0x3F) +#define CP_PACKETJ_GET_COND(x) (((x) >> 24) & 0xF) +#define CP_PACKETJ_GET_TYPE(x) (((x) >> 28) & 0xF) + +/* Packet 3 types */ +#define PACKET3_NOP 0x10 +#define PACKET3_SET_BASE 0x11 +#define PACKET3_BASE_INDEX(x) ((x) << 0) +#define CE_PARTITION_BASE 3 +#define PACKET3_CLEAR_STATE 0x12 +#define PACKET3_INDEX_BUFFER_SIZE 0x13 +#define PACKET3_DISPATCH_DIRECT 0x15 +#define PACKET3_DISPATCH_INDIRECT 0x16 +#define PACKET3_ATOMIC_GDS 0x1D +#define PACKET3_ATOMIC_MEM 0x1E +#define PACKET3_OCCLUSION_QUERY 0x1F +#define PACKET3_SET_PREDICATION 0x20 +#define PACKET3_REG_RMW 0x21 +#define PACKET3_COND_EXEC 0x22 +#define PACKET3_PRED_EXEC 0x23 +#define PACKET3_DRAW_INDIRECT 0x24 +#define PACKET3_DRAW_INDEX_INDIRECT 0x25 +#define PACKET3_INDEX_BASE 0x26 +#define PACKET3_DRAW_INDEX_2 0x27 +#define PACKET3_CONTEXT_CONTROL 0x28 +#define PACKET3_INDEX_TYPE 0x2A +#define PACKET3_DRAW_INDIRECT_MULTI 0x2C +#define PACKET3_DRAW_INDEX_AUTO 0x2D +#define PACKET3_NUM_INSTANCES 0x2F +#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 +#define PACKET3_INDIRECT_BUFFER_CONST 0x33 +#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 +#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 +#define PACKET3_DRAW_PREAMBLE 0x36 +#define PACKET3_WRITE_DATA 0x37 +#define WRITE_DATA_DST_SEL(x) ((x) << 8) + /* 0 - register + * 1 - memory (sync - via GRBM) + * 2 - gl2 + * 3 - gds + * 4 - reserved + * 5 - memory (async - direct) + */ +#define WR_ONE_ADDR (1 << 16) +#define WR_CONFIRM (1 << 20) +#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) + /* 0 - LRU + * 1 - Stream + */ +#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) + /* 0 - me + * 1 - pfp + * 2 - ce + */ +#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 +#define PACKET3_MEM_SEMAPHORE 0x39 +# define PACKET3_SEM_USE_MAILBOX (0x1 << 16) +# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ +# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) +# define PACKET3_SEM_SEL_WAIT (0x7 << 29) +#define PACKET3_WAIT_REG_MEM 0x3C +#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) + /* 0 - always + * 1 - < + * 2 - <= + * 3 - == + * 4 - != + * 5 - >= + * 6 - > + */ +#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) + /* 0 - reg + * 1 - mem + */ +#define WAIT_REG_MEM_OPERATION(x) ((x) << 6) + /* 0 - wait_reg_mem + * 1 - wr_wait_wr_reg + */ +#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) + /* 0 - me + * 1 - pfp + */ +#define PACKET3_INDIRECT_BUFFER 0x3F +#define INDIRECT_BUFFER_VALID (1 << 23) +#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) + /* 0 - LRU + * 1 - Stream + * 2 - Bypass + */ +#define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) +#define INDIRECT_BUFFER_PRE_RESUME(x) ((x) << 30) +#define PACKET3_COPY_DATA 0x40 +#define PACKET3_PFP_SYNC_ME 0x42 +#define PACKET3_COND_WRITE 0x45 +#define PACKET3_EVENT_WRITE 0x46 +#define EVENT_TYPE(x) ((x) << 0) +#define EVENT_INDEX(x) ((x) << 8) + /* 0 - any non-TS event + * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* + * 2 - SAMPLE_PIPELINESTAT + * 3 - SAMPLE_STREAMOUTSTAT* + * 4 - *S_PARTIAL_FLUSH + */ +#define PACKET3_RELEASE_MEM 0x49 +#define EVENT_TYPE(x) ((x) << 0) +#define EVENT_INDEX(x) ((x) << 8) +#define EOP_TCL1_VOL_ACTION_EN (1 << 12) +#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ +#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ +#define EOP_TCL1_ACTION_EN (1 << 16) +#define EOP_TC_ACTION_EN (1 << 17) /* L2 */ +#define EOP_TC_NC_ACTION_EN (1 << 19) +#define EOP_TC_MD_ACTION_EN (1 << 21) /* L2 metadata */ +#define EOP_EXEC (1 << 28) /* For Trailing Fence */ + +#define DATA_SEL(x) ((x) << 29) + /* 0 - discard + * 1 - send low 32bit data + * 2 - send 64bit data + * 3 - send 64bit GPU counter value + * 4 - send 64bit sys counter value + */ +#define INT_SEL(x) ((x) << 24) + /* 0 - none + * 1 - interrupt only (DATA_SEL = 0) + * 2 - interrupt when data write is confirmed + */ +#define DST_SEL(x) ((x) << 16) + /* 0 - MC + * 1 - TC/L2 + */ + + + +#define PACKET3_PREAMBLE_CNTL 0x4A +# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) +# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) +#define PACKET3_DMA_DATA 0x50 +/* 1. header + * 2. CONTROL + * 3. SRC_ADDR_LO or DATA [31:0] + * 4. SRC_ADDR_HI [31:0] + * 5. DST_ADDR_LO [31:0] + * 6. DST_ADDR_HI [7:0] + * 7. COMMAND [30:21] | BYTE_COUNT [20:0] + */ +/* CONTROL */ +# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) + /* 0 - ME + * 1 - PFP + */ +# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) + /* 0 - LRU + * 1 - Stream + */ +# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) + /* 0 - DST_ADDR using DAS + * 1 - GDS + * 3 - DST_ADDR using L2 + */ +# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) + /* 0 - LRU + * 1 - Stream + */ +# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) + /* 0 - SRC_ADDR using SAS + * 1 - GDS + * 2 - DATA + * 3 - SRC_ADDR using L2 + */ +# define PACKET3_DMA_DATA_CP_SYNC (1 << 31) +/* COMMAND */ +# define PACKET3_DMA_DATA_CMD_SAS (1 << 26) + /* 0 - memory + * 1 - register + */ +# define PACKET3_DMA_DATA_CMD_DAS (1 << 27) + /* 0 - memory + * 1 - register + */ +# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) +# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) +# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) +#define PACKET3_ACQUIRE_MEM 0x58 +/* 1. HEADER + * 2. COHER_CNTL [30:0] + * 2.1 ENGINE_SEL [31:31] + * 3. COHER_SIZE [31:0] + * 4. COHER_SIZE_HI [7:0] + * 5. COHER_BASE_LO [31:0] + * 6. COHER_BASE_HI [23:0] + * 7. POLL_INTERVAL [15:0] + */ +/* COHER_CNTL fields for CP_COHER_CNTL */ +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA(x) ((x) << 3) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WC_ACTION_ENA(x) ((x) << 4) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_INV_METADATA_ACTION_ENA(x) ((x) << 5) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_VOL_ACTION_ENA(x) ((x) << 15) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(x) ((x) << 18) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(x) ((x) << 22) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(x) ((x) << 23) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_CB_ACTION_ENA(x) ((x) << 25) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_DB_ACTION_ENA(x) ((x) << 26) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(x) ((x) << 27) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_VOL_ACTION_ENA(x) ((x) << 28) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(x) ((x) << 29) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_WB_ACTION_ENA(x) ((x) << 30) +#define PACKET3_REWIND 0x59 +#define PACKET3_LOAD_UCONFIG_REG 0x5E +#define PACKET3_LOAD_SH_REG 0x5F +#define PACKET3_LOAD_CONFIG_REG 0x60 +#define PACKET3_LOAD_CONTEXT_REG 0x61 +#define PACKET3_SET_CONFIG_REG 0x68 +#define PACKET3_SET_CONFIG_REG_START 0x00002000 +#define PACKET3_SET_CONFIG_REG_END 0x00002c00 +#define PACKET3_SET_CONTEXT_REG 0x69 +#define PACKET3_SET_CONTEXT_REG_START 0x0000a000 +#define PACKET3_SET_CONTEXT_REG_END 0x0000a400 +#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 +#define PACKET3_SET_SH_REG 0x76 +#define PACKET3_SET_SH_REG_START 0x00002c00 +#define PACKET3_SET_SH_REG_END 0x00003000 +#define PACKET3_SET_SH_REG_OFFSET 0x77 +#define PACKET3_SET_QUEUE_REG 0x78 +#define PACKET3_SET_UCONFIG_REG 0x79 +#define PACKET3_SET_UCONFIG_REG_START 0x0000c000 +#define PACKET3_SET_UCONFIG_REG_END 0x0000c400 +#define PACKET3_SET_UCONFIG_REG_INDEX_TYPE (2 << 28) +#define PACKET3_SCRATCH_RAM_WRITE 0x7D +#define PACKET3_SCRATCH_RAM_READ 0x7E +#define PACKET3_LOAD_CONST_RAM 0x80 +#define PACKET3_WRITE_CONST_RAM 0x81 +#define PACKET3_DUMP_CONST_RAM 0x83 +#define PACKET3_INCREMENT_CE_COUNTER 0x84 +#define PACKET3_INCREMENT_DE_COUNTER 0x85 +#define PACKET3_WAIT_ON_CE_COUNTER 0x86 +#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 +#define PACKET3_SWITCH_BUFFER 0x8B +#define PACKET3_FRAME_CONTROL 0x90 +# define FRAME_TMZ (1 << 0) +# define FRAME_CMD(x) ((x) << 28) + /* + * x=0: tmz_begin + * x=1: tmz_end + */ + +#define PACKET3_INVALIDATE_TLBS 0x98 +# define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0) +# define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4) +# define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5) +# define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x) ((x) << 29) +#define PACKET3_SET_RESOURCES 0xA0 +/* 1. header + * 2. CONTROL + * 3. QUEUE_MASK_LO [31:0] + * 4. QUEUE_MASK_HI [31:0] + * 5. GWS_MASK_LO [31:0] + * 6. GWS_MASK_HI [31:0] + * 7. OAC_MASK [15:0] + * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0] + */ +# define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) +# define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) +# define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) +#define PACKET3_MAP_QUEUES 0xA2 +/* 1. header + * 2. CONTROL + * 3. CONTROL2 + * 4. MQD_ADDR_LO [31:0] + * 5. MQD_ADDR_HI [31:0] + * 6. WPTR_ADDR_LO [31:0] + * 7. WPTR_ADDR_HI [31:0] + */ +/* CONTROL */ +# define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) +# define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) +# define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13) +# define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16) +# define PACKET3_MAP_QUEUES_ME(x) ((x) << 18) +# define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) +# define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) +# define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) +# define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) +/* CONTROL2 */ +# define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) +# define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) +#define PACKET3_UNMAP_QUEUES 0xA3 +/* 1. header + * 2. CONTROL + * 3. CONTROL2 + * 4. CONTROL3 + * 5. CONTROL4 + * 6. CONTROL5 + */ +/* CONTROL */ +# define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) + /* 0 - PREEMPT_QUEUES + * 1 - RESET_QUEUES + * 2 - DISABLE_PROCESS_QUEUES + * 3 - PREEMPT_QUEUES_NO_UNMAP + */ +# define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) +# define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) +# define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) +/* CONTROL2a */ +# define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) +/* CONTROL2b */ +# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) +/* CONTROL3a */ +# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) +/* CONTROL3b */ +# define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) +/* CONTROL4 */ +# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) +/* CONTROL5 */ +# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) +#define PACKET3_QUERY_STATUS 0xA4 +/* 1. header + * 2. CONTROL + * 3. CONTROL2 + * 4. ADDR_LO [31:0] + * 5. ADDR_HI [31:0] + * 6. DATA_LO [31:0] + * 7. DATA_HI [31:0] + */ +/* CONTROL */ +# define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) +# define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) +# define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) +/* CONTROL2a */ +# define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) +/* CONTROL2b */ +# define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) +# define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) + +#define PACKET3_RUN_CLEANER_SHADER 0xD2 +/* 1. header + * 2. RESERVED [31:0] + */ + +#define VCE_CMD_NO_OP 0x00000000 +#define VCE_CMD_END 0x00000001 +#define VCE_CMD_IB 0x00000002 +#define VCE_CMD_FENCE 0x00000003 +#define VCE_CMD_TRAP 0x00000004 +#define VCE_CMD_IB_AUTO 0x00000005 +#define VCE_CMD_SEMAPHORE 0x00000006 + +#define VCE_CMD_IB_VM 0x00000102 +#define VCE_CMD_WAIT_GE 0x00000106 +#define VCE_CMD_UPDATE_PTB 0x00000107 +#define VCE_CMD_FLUSH_TLB 0x00000108 +#define VCE_CMD_REG_WRITE 0x00000109 +#define VCE_CMD_REG_WAIT 0x0000010a + +#define HEVC_ENC_CMD_NO_OP 0x00000000 +#define HEVC_ENC_CMD_END 0x00000001 +#define HEVC_ENC_CMD_FENCE 0x00000003 +#define HEVC_ENC_CMD_TRAP 0x00000004 +#define HEVC_ENC_CMD_IB_VM 0x00000102 +#define HEVC_ENC_CMD_REG_WRITE 0x00000109 +#define HEVC_ENC_CMD_REG_WAIT 0x0000010a + +#endif diff --git a/extra/hip_gpu_driver/vega10_sdma_pkt_open.h b/extra/hip_gpu_driver/vega10_sdma_pkt_open.h new file mode 100644 index 0000000000..8de4ccce5e --- /dev/null +++ b/extra/hip_gpu_driver/vega10_sdma_pkt_open.h @@ -0,0 +1,3335 @@ +/* + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __VEGA10_SDMA_PKT_OPEN_H_ +#define __VEGA10_SDMA_PKT_OPEN_H_ + +#define SDMA_OP_NOP 0 +#define SDMA_OP_COPY 1 +#define SDMA_OP_WRITE 2 +#define SDMA_OP_INDIRECT 4 +#define SDMA_OP_FENCE 5 +#define SDMA_OP_TRAP 6 +#define SDMA_OP_SEM 7 +#define SDMA_OP_POLL_REGMEM 8 +#define SDMA_OP_COND_EXE 9 +#define SDMA_OP_ATOMIC 10 +#define SDMA_OP_CONST_FILL 11 +#define SDMA_OP_PTEPDE 12 +#define SDMA_OP_TIMESTAMP 13 +#define SDMA_OP_SRBM_WRITE 14 +#define SDMA_OP_PRE_EXE 15 +#define SDMA_OP_DUMMY_TRAP 16 +#define SDMA_SUBOP_TIMESTAMP_SET 0 +#define SDMA_SUBOP_TIMESTAMP_GET 1 +#define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL 2 +#define SDMA_SUBOP_COPY_LINEAR 0 +#define SDMA_SUBOP_COPY_LINEAR_SUB_WIND 4 +#define SDMA_SUBOP_COPY_TILED 1 +#define SDMA_SUBOP_COPY_TILED_SUB_WIND 5 +#define SDMA_SUBOP_COPY_T2T_SUB_WIND 6 +#define SDMA_SUBOP_COPY_SOA 3 +#define SDMA_SUBOP_COPY_DIRTY_PAGE 7 +#define SDMA_SUBOP_COPY_LINEAR_PHY 8 +#define SDMA_SUBOP_WRITE_LINEAR 0 +#define SDMA_SUBOP_WRITE_TILED 1 +#define SDMA_SUBOP_PTEPDE_GEN 0 +#define SDMA_SUBOP_PTEPDE_COPY 1 +#define SDMA_SUBOP_PTEPDE_RMW 2 +#define SDMA_SUBOP_PTEPDE_COPY_BACKWARDS 3 +#define SDMA_SUBOP_DATA_FILL_MULTI 1 +#define SDMA_SUBOP_POLL_REG_WRITE_MEM 1 +#define SDMA_SUBOP_POLL_DBIT_WRITE_MEM 2 +#define SDMA_SUBOP_POLL_MEM_VERIFY 3 +#define HEADER_AGENT_DISPATCH 4 +#define HEADER_BARRIER 5 +#define SDMA_OP_AQL_COPY 0 +#define SDMA_OP_AQL_BARRIER_OR 0 + +/*define for op field*/ +#define SDMA_PKT_HEADER_op_offset 0 +#define SDMA_PKT_HEADER_op_mask 0x000000FF +#define SDMA_PKT_HEADER_op_shift 0 +#define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_HEADER_sub_op_offset 0 +#define SDMA_PKT_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_HEADER_sub_op_shift 8 +#define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_shift) + + +/* +** Definitions for SDMA_PKT_COPY_LINEAR packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift) + +/*define for encrypt field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift 16 +#define SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift) + +/*define for broadcast field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift 27 +#define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1 +#define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF +#define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0 +#define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift) + +/*define for PARAMETER word*/ +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_COPY_DIRTY_PAGE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift) + +/*define for all field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift 31 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset 1 +#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask 0x003FFFFF +#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask) << SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift) + +/*define for PARAMETER word*/ +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift 16 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift) + +/*define for dst_gcc field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift 19 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift) + +/*define for dst_sys field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift 20 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift) + +/*define for dst_snoop field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift 22 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift) + +/*define for dst_gpa field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift 23 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift 24 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift) + +/*define for src_sys field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift 28 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift) + +/*define for src_snoop field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift 30 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift) + +/*define for src_gpa field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift 31 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset 3 +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset 4 +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset 5 +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset 6 +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_COPY_PHYSICAL_LINEAR packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset 1 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask 0x003FFFFF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift) + +/*define for PARAMETER word*/ +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift 16 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift) + +/*define for dst_gcc field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift 19 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift) + +/*define for dst_sys field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift 20 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift) + +/*define for dst_log field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift 21 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift) + +/*define for dst_snoop field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift 22 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift) + +/*define for dst_gpa field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift 23 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift 24 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift) + +/*define for src_gcc field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift 27 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift) + +/*define for src_sys field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift 28 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift) + +/*define for src_snoop field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift 30 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift) + +/*define for src_gpa field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift 31 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift) + +/*define for encrypt field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask 0x00000001 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift 16 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift) + +/*define for broadcast field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift 27 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x003FFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift) + +/*define for PARAMETER word*/ +/*define for dst2_sw field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift 8 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift) + +/*define for dst1_sw field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift 16 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift 24 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST1_ADDR_LO word*/ +/*define for dst1_addr_31_0 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift) + +/*define for DST1_ADDR_HI word*/ +/*define for dst1_addr_63_32 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift) + +/*define for DST2_ADDR_LO word*/ +/*define for dst2_addr_31_0 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift) + +/*define for DST2_ADDR_HI word*/ +/*define for dst2_addr_63_32 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift) + +/*define for elementsize field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift 29 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for src_x field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift) + +/*define for src_y field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift) + +/*define for DW_4 word*/ +/*define for src_z field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x000007FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift) + +/*define for src_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x0007FFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift 13 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift) + +/*define for DW_5 word*/ +/*define for src_slice_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_8 word*/ +/*define for dst_x field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift) + +/*define for dst_y field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift) + +/*define for DW_9 word*/ +/*define for dst_z field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x000007FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift) + +/*define for dst_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x0007FFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift 13 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift) + +/*define for DW_10 word*/ +/*define for dst_slice_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift) + +/*define for DW_11 word*/ +/*define for rect_x field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift) + +/*define for rect_y field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift) + +/*define for DW_12 word*/ +/*define for rect_z field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x000007FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift) + +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift 24 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift) + + +/* +** Definitions for SDMA_PKT_COPY_TILED packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_TILED_HEADER_op_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_HEADER_op_shift 0 +#define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift) + +/*define for encrypt field*/ +#define SDMA_PKT_COPY_TILED_HEADER_encrypt_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_encrypt_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_HEADER_encrypt_shift 16 +#define SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_encrypt_mask) << SDMA_PKT_COPY_TILED_HEADER_encrypt_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_TILED_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_HEADER_tmz_shift) + +/*define for mip_max field*/ +#define SDMA_PKT_COPY_TILED_HEADER_mip_max_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_mip_max_mask 0x0000000F +#define SDMA_PKT_COPY_TILED_HEADER_mip_max_shift 20 +#define SDMA_PKT_COPY_TILED_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_mip_max_mask) << SDMA_PKT_COPY_TILED_HEADER_mip_max_shift) + +/*define for detile field*/ +#define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_HEADER_detile_shift 31 +#define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift) + +/*define for TILED_ADDR_LO word*/ +/*define for tiled_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1 +#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift) + +/*define for TILED_ADDR_HI word*/ +/*define for tiled_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2 +#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for width field*/ +#define SDMA_PKT_COPY_TILED_DW_3_width_offset 3 +#define SDMA_PKT_COPY_TILED_DW_3_width_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_DW_3_width_shift 0 +#define SDMA_PKT_COPY_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_width_mask) << SDMA_PKT_COPY_TILED_DW_3_width_shift) + +/*define for DW_4 word*/ +/*define for height field*/ +#define SDMA_PKT_COPY_TILED_DW_4_height_offset 4 +#define SDMA_PKT_COPY_TILED_DW_4_height_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_DW_4_height_shift 0 +#define SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_height_mask) << SDMA_PKT_COPY_TILED_DW_4_height_shift) + +/*define for depth field*/ +#define SDMA_PKT_COPY_TILED_DW_4_depth_offset 4 +#define SDMA_PKT_COPY_TILED_DW_4_depth_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_DW_4_depth_shift 16 +#define SDMA_PKT_COPY_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_DW_4_depth_shift) + +/*define for DW_5 word*/ +/*define for element_size field*/ +#define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0 +#define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift) + +/*define for swizzle_mode field*/ +#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask 0x0000001F +#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift 3 +#define SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift) + +/*define for dimension field*/ +#define SDMA_PKT_COPY_TILED_DW_5_dimension_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_dimension_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_DW_5_dimension_shift 9 +#define SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_dimension_mask) << SDMA_PKT_COPY_TILED_DW_5_dimension_shift) + +/*define for epitch field*/ +#define SDMA_PKT_COPY_TILED_DW_5_epitch_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_epitch_mask 0x0000FFFF +#define SDMA_PKT_COPY_TILED_DW_5_epitch_shift 16 +#define SDMA_PKT_COPY_TILED_DW_5_EPITCH(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_epitch_mask) << SDMA_PKT_COPY_TILED_DW_5_epitch_shift) + +/*define for DW_6 word*/ +/*define for x field*/ +#define SDMA_PKT_COPY_TILED_DW_6_x_offset 6 +#define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_DW_6_x_shift 0 +#define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift) + +/*define for y field*/ +#define SDMA_PKT_COPY_TILED_DW_6_y_offset 6 +#define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_DW_6_y_shift 16 +#define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift) + +/*define for DW_7 word*/ +/*define for z field*/ +#define SDMA_PKT_COPY_TILED_DW_7_z_offset 7 +#define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_DW_7_z_shift 0 +#define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7 +#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift 16 +#define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift) + +/*define for tile_sw field*/ +#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7 +#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift 24 +#define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift) + +/*define for LINEAR_PITCH word*/ +/*define for linear_pitch field*/ +#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10 +#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF +#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0 +#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift) + +/*define for LINEAR_SLICE_PITCH word*/ +/*define for linear_slice_pitch field*/ +#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 11 +#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 +#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_TILED_COUNT_count_offset 12 +#define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x000FFFFF +#define SDMA_PKT_COPY_TILED_COUNT_count_shift 0 +#define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift) + +/*define for encrypt field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask 0x00000001 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift 16 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift) + +/*define for mip_max field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask 0x0000000F +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift 20 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift) + +/*define for videocopy field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x00000001 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift 26 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift) + +/*define for broadcast field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x00000001 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift 27 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift) + +/*define for TILED_ADDR_LO_0 word*/ +/*define for tiled_addr0_31_0 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift) + +/*define for TILED_ADDR_HI_0 word*/ +/*define for tiled_addr0_63_32 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift) + +/*define for TILED_ADDR_LO_1 word*/ +/*define for tiled_addr1_31_0 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift) + +/*define for TILED_ADDR_HI_1 word*/ +/*define for tiled_addr1_63_32 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift) + +/*define for DW_5 word*/ +/*define for width field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset 5 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask 0x00003FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift) + +/*define for DW_6 word*/ +/*define for height field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset 6 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask 0x00003FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift) + +/*define for depth field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset 6 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask 0x000007FF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift 16 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift) + +/*define for DW_7 word*/ +/*define for element_size field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift) + +/*define for swizzle_mode field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask 0x0000001F +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift 3 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift) + +/*define for dimension field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift 9 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift) + +/*define for epitch field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask 0x0000FFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift 16 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_EPITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift) + +/*define for DW_8 word*/ +/*define for x field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift) + +/*define for y field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift 16 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift) + +/*define for DW_9 word*/ +/*define for z field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x000007FF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift) + +/*define for DW_10 word*/ +/*define for dst2_sw field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift 16 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift) + +/*define for tile_sw field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift 24 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift) + +/*define for LINEAR_PITCH word*/ +/*define for linear_pitch field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift) + +/*define for LINEAR_SLICE_PITCH word*/ +/*define for linear_slice_pitch field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 14 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 15 +#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x000FFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_COPY_T2T packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_T2T_HEADER_op_offset 0 +#define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_T2T_HEADER_op_shift 0 +#define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_T2T_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_T2T_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_T2T_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_T2T_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_tmz_mask) << SDMA_PKT_COPY_T2T_HEADER_tmz_shift) + +/*define for mip_max field*/ +#define SDMA_PKT_COPY_T2T_HEADER_mip_max_offset 0 +#define SDMA_PKT_COPY_T2T_HEADER_mip_max_mask 0x0000000F +#define SDMA_PKT_COPY_T2T_HEADER_mip_max_shift 20 +#define SDMA_PKT_COPY_T2T_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_mip_max_mask) << SDMA_PKT_COPY_T2T_HEADER_mip_max_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1 +#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2 +#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for src_x field*/ +#define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3 +#define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 0 +#define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift) + +/*define for src_y field*/ +#define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3 +#define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_3_src_y_shift 16 +#define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift) + +/*define for DW_4 word*/ +/*define for src_z field*/ +#define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4 +#define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x000007FF +#define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 0 +#define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift) + +/*define for src_width field*/ +#define SDMA_PKT_COPY_T2T_DW_4_src_width_offset 4 +#define SDMA_PKT_COPY_T2T_DW_4_src_width_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_4_src_width_shift 16 +#define SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_DW_4_src_width_shift) + +/*define for DW_5 word*/ +/*define for src_height field*/ +#define SDMA_PKT_COPY_T2T_DW_5_src_height_offset 5 +#define SDMA_PKT_COPY_T2T_DW_5_src_height_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_5_src_height_shift 0 +#define SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_DW_5_src_height_shift) + +/*define for src_depth field*/ +#define SDMA_PKT_COPY_T2T_DW_5_src_depth_offset 5 +#define SDMA_PKT_COPY_T2T_DW_5_src_depth_mask 0x000007FF +#define SDMA_PKT_COPY_T2T_DW_5_src_depth_shift 16 +#define SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_DW_5_src_depth_shift) + +/*define for DW_6 word*/ +/*define for src_element_size field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 0 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift) + +/*define for src_swizzle_mode field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask 0x0000001F +#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift 3 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift) + +/*define for src_dimension field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift 9 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask) << SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift) + +/*define for src_epitch field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_epitch_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask 0x0000FFFF +#define SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift 16 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_EPITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask) << SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7 +#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8 +#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_9 word*/ +/*define for dst_x field*/ +#define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9 +#define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 0 +#define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift) + +/*define for dst_y field*/ +#define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9 +#define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift 16 +#define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift) + +/*define for DW_10 word*/ +/*define for dst_z field*/ +#define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10 +#define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x000007FF +#define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 0 +#define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift) + +/*define for dst_width field*/ +#define SDMA_PKT_COPY_T2T_DW_10_dst_width_offset 10 +#define SDMA_PKT_COPY_T2T_DW_10_dst_width_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_10_dst_width_shift 16 +#define SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_width_shift) + +/*define for DW_11 word*/ +/*define for dst_height field*/ +#define SDMA_PKT_COPY_T2T_DW_11_dst_height_offset 11 +#define SDMA_PKT_COPY_T2T_DW_11_dst_height_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_11_dst_height_shift 0 +#define SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_height_shift) + +/*define for dst_depth field*/ +#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset 11 +#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask 0x000007FF +#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift 16 +#define SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift) + +/*define for DW_12 word*/ +/*define for dst_element_size field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift 0 +#define SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift) + +/*define for dst_swizzle_mode field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask 0x0000001F +#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift 3 +#define SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift) + +/*define for dst_dimension field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift 9 +#define SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift) + +/*define for dst_epitch field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask 0x0000FFFF +#define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift 16 +#define SDMA_PKT_COPY_T2T_DW_12_DST_EPITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift) + +/*define for DW_13 word*/ +/*define for rect_x field*/ +#define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13 +#define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 0 +#define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift) + +/*define for rect_y field*/ +#define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13 +#define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift 16 +#define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift) + +/*define for DW_14 word*/ +/*define for rect_z field*/ +#define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14 +#define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x000007FF +#define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 0 +#define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift) + +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14 +#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift 16 +#define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14 +#define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift 24 +#define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift) + + +/* +** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift) + +/*define for mip_max field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask 0x0000000F +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift 20 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift) + +/*define for mip_id field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask 0x0000000F +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift 24 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_ID(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift) + +/*define for detile field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift 31 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift) + +/*define for TILED_ADDR_LO word*/ +/*define for tiled_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1 +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift) + +/*define for TILED_ADDR_HI word*/ +/*define for tiled_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2 +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for tiled_x field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift) + +/*define for tiled_y field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift) + +/*define for DW_4 word*/ +/*define for tiled_z field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift) + +/*define for width field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset 4 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift) + +/*define for DW_5 word*/ +/*define for height field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset 5 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift) + +/*define for depth field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset 5 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift) + +/*define for DW_6 word*/ +/*define for element_size field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift) + +/*define for swizzle_mode field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask 0x0000001F +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift 3 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift) + +/*define for dimension field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift 9 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift) + +/*define for epitch field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask 0x0000FFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_EPITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift) + +/*define for DW_9 word*/ +/*define for linear_x field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift) + +/*define for linear_y field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift) + +/*define for DW_10 word*/ +/*define for linear_z field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift) + +/*define for linear_pitch field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift) + +/*define for DW_11 word*/ +/*define for linear_slice_pitch field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift) + +/*define for DW_12 word*/ +/*define for rect_x field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift) + +/*define for rect_y field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift) + +/*define for DW_13 word*/ +/*define for rect_z field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift) + +/*define for tile_sw field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift 24 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift) + + +/* +** Definitions for SDMA_PKT_COPY_STRUCT packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask) << SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift) + +/*define for detile field*/ +#define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x00000001 +#define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift 31 +#define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift) + +/*define for SB_ADDR_LO word*/ +/*define for sb_addr_31_0 field*/ +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1 +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 0 +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift) + +/*define for SB_ADDR_HI word*/ +/*define for sb_addr_63_32 field*/ +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2 +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 0 +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift) + +/*define for START_INDEX word*/ +/*define for start_index field*/ +#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3 +#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 0 +#define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4 +#define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 0 +#define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift) + +/*define for DW_5 word*/ +/*define for stride field*/ +#define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5 +#define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF +#define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 0 +#define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5 +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift 16 +#define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift) + +/*define for struct_sw field*/ +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5 +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x00000003 +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift 24 +#define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6 +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7 +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_WRITE_UNTILED packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF +#define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift 8 +#define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift) + +/*define for encrypt field*/ +#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask 0x00000001 +#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift 16 +#define SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift) + +/*define for tmz field*/ +#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift 18 +#define SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1 +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2 +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for count field*/ +#define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3 +#define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x000FFFFF +#define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 0 +#define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) + +/*define for sw field*/ +#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3 +#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x00000003 +#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift 24 +#define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift) + +/*define for DATA0 word*/ +/*define for data0 field*/ +#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4 +#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 0 +#define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift) + + +/* +** Definitions for SDMA_PKT_WRITE_TILED packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0 +#define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF +#define SDMA_PKT_WRITE_TILED_HEADER_op_shift 0 +#define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0 +#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift 8 +#define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift) + +/*define for encrypt field*/ +#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset 0 +#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask 0x00000001 +#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift 16 +#define SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift) + +/*define for tmz field*/ +#define SDMA_PKT_WRITE_TILED_HEADER_tmz_offset 0 +#define SDMA_PKT_WRITE_TILED_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_WRITE_TILED_HEADER_tmz_shift 18 +#define SDMA_PKT_WRITE_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_TILED_HEADER_tmz_shift) + +/*define for mip_max field*/ +#define SDMA_PKT_WRITE_TILED_HEADER_mip_max_offset 0 +#define SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask 0x0000000F +#define SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift 20 +#define SDMA_PKT_WRITE_TILED_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask) << SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1 +#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2 +#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for width field*/ +#define SDMA_PKT_WRITE_TILED_DW_3_width_offset 3 +#define SDMA_PKT_WRITE_TILED_DW_3_width_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_DW_3_width_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_DW_3_width_shift) + +/*define for DW_4 word*/ +/*define for height field*/ +#define SDMA_PKT_WRITE_TILED_DW_4_height_offset 4 +#define SDMA_PKT_WRITE_TILED_DW_4_height_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_DW_4_height_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_DW_4_height_shift) + +/*define for depth field*/ +#define SDMA_PKT_WRITE_TILED_DW_4_depth_offset 4 +#define SDMA_PKT_WRITE_TILED_DW_4_depth_mask 0x000007FF +#define SDMA_PKT_WRITE_TILED_DW_4_depth_shift 16 +#define SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_DW_4_depth_shift) + +/*define for DW_5 word*/ +/*define for element_size field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x00000007 +#define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift) + +/*define for swizzle_mode field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask 0x0000001F +#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift 3 +#define SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift) + +/*define for dimension field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_dimension_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_dimension_mask 0x00000003 +#define SDMA_PKT_WRITE_TILED_DW_5_dimension_shift 9 +#define SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_dimension_mask) << SDMA_PKT_WRITE_TILED_DW_5_dimension_shift) + +/*define for epitch field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_epitch_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_epitch_mask 0x0000FFFF +#define SDMA_PKT_WRITE_TILED_DW_5_epitch_shift 16 +#define SDMA_PKT_WRITE_TILED_DW_5_EPITCH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_epitch_mask) << SDMA_PKT_WRITE_TILED_DW_5_epitch_shift) + +/*define for DW_6 word*/ +/*define for x field*/ +#define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6 +#define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_DW_6_x_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift) + +/*define for y field*/ +#define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6 +#define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_DW_6_y_shift 16 +#define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift) + +/*define for DW_7 word*/ +/*define for z field*/ +#define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7 +#define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x000007FF +#define SDMA_PKT_WRITE_TILED_DW_7_z_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift) + +/*define for sw field*/ +#define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7 +#define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x00000003 +#define SDMA_PKT_WRITE_TILED_DW_7_sw_shift 24 +#define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8 +#define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x000FFFFF +#define SDMA_PKT_WRITE_TILED_COUNT_count_shift 0 +#define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift) + +/*define for DATA0 word*/ +/*define for data0 field*/ +#define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9 +#define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 0 +#define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift) + + +/* +** Definitions for SDMA_PKT_PTEPDE_COPY packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_PTEPDE_COPY_HEADER_op_offset 0 +#define SDMA_PKT_PTEPDE_COPY_HEADER_op_mask 0x000000FF +#define SDMA_PKT_PTEPDE_COPY_HEADER_op_shift 0 +#define SDMA_PKT_PTEPDE_COPY_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset 0 +#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift 8 +#define SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift) + +/*define for ptepde_op field*/ +#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset 0 +#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask 0x00000001 +#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift 31 +#define SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset 1 +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset 2 +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset 3 +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset 4 +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for MASK_DW0 word*/ +/*define for mask_dw0 field*/ +#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset 5 +#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift 0 +#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift) + +/*define for MASK_DW1 word*/ +/*define for mask_dw1 field*/ +#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset 6 +#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift 0 +#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_PTEPDE_COPY_COUNT_count_offset 7 +#define SDMA_PKT_PTEPDE_COPY_COUNT_count_mask 0x0007FFFF +#define SDMA_PKT_PTEPDE_COPY_COUNT_count_shift 0 +#define SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_count_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_PTEPDE_COPY_BACKWARDS packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask 0x000000FF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift 8 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift) + +/*define for pte_size field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask 0x00000003 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift 28 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift) + +/*define for direction field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask 0x00000001 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift 30 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift) + +/*define for ptepde_op field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask 0x00000001 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift 31 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset 1 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset 2 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset 3 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset 4 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for MASK_BIT_FOR_DW word*/ +/*define for mask_first_xfer field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset 5 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask 0x000000FF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift) + +/*define for mask_last_xfer field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset 5 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask 0x000000FF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift 8 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift) + +/*define for COUNT_IN_32B_XFER word*/ +/*define for count field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset 6 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask 0x0001FFFF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift) + + +/* +** Definitions for SDMA_PKT_PTEPDE_RMW packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_op_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_op_mask 0x000000FF +#define SDMA_PKT_PTEPDE_RMW_HEADER_op_shift 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift 8 +#define SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift) + +/*define for gcc field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask 0x00000001 +#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift 19 +#define SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift) + +/*define for sys field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask 0x00000001 +#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift 20 +#define SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift) + +/*define for snp field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask 0x00000001 +#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift 22 +#define SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift) + +/*define for gpa field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask 0x00000001 +#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift 23 +#define SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift) + +/*define for MASK_LO word*/ +/*define for mask_31_0 field*/ +#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset 3 +#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift 0 +#define SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask) << SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift) + +/*define for MASK_HI word*/ +/*define for mask_63_32 field*/ +#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset 4 +#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift 0 +#define SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask) << SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift) + +/*define for VALUE_LO word*/ +/*define for value_31_0 field*/ +#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset 5 +#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift 0 +#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift) + +/*define for VALUE_HI word*/ +/*define for value_63_32 field*/ +#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset 6 +#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift 0 +#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift) + + +/* +** Definitions for SDMA_PKT_WRITE_INCR packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0 +#define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF +#define SDMA_PKT_WRITE_INCR_HEADER_op_shift 0 +#define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0 +#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift 8 +#define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1 +#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2 +#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for MASK_DW0 word*/ +/*define for mask_dw0 field*/ +#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3 +#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 0 +#define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift) + +/*define for MASK_DW1 word*/ +/*define for mask_dw1 field*/ +#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4 +#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 0 +#define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift) + +/*define for INIT_DW0 word*/ +/*define for init_dw0 field*/ +#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5 +#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 0 +#define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift) + +/*define for INIT_DW1 word*/ +/*define for init_dw1 field*/ +#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6 +#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 0 +#define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift) + +/*define for INCR_DW0 word*/ +/*define for incr_dw0 field*/ +#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7 +#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 0 +#define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift) + +/*define for INCR_DW1 word*/ +/*define for incr_dw1 field*/ +#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8 +#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 0 +#define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9 +#define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF +#define SDMA_PKT_WRITE_INCR_COUNT_count_shift 0 +#define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_INDIRECT packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_INDIRECT_HEADER_op_offset 0 +#define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF +#define SDMA_PKT_INDIRECT_HEADER_op_shift 0 +#define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0 +#define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_INDIRECT_HEADER_sub_op_shift 8 +#define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift) + +/*define for vmid field*/ +#define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0 +#define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F +#define SDMA_PKT_INDIRECT_HEADER_vmid_shift 16 +#define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift) + +/*define for BASE_LO word*/ +/*define for ib_base_31_0 field*/ +#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1 +#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 0 +#define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift) + +/*define for BASE_HI word*/ +/*define for ib_base_63_32 field*/ +#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2 +#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 0 +#define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift) + +/*define for IB_SIZE word*/ +/*define for ib_size field*/ +#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3 +#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF +#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 0 +#define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift) + +/*define for CSA_ADDR_LO word*/ +/*define for csa_addr_31_0 field*/ +#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4 +#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 0 +#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift) + +/*define for CSA_ADDR_HI word*/ +/*define for csa_addr_63_32 field*/ +#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5 +#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 0 +#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_SEMAPHORE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_SEMAPHORE_HEADER_op_shift 0 +#define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift 8 +#define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift) + +/*define for write_one field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x00000001 +#define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift 29 +#define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift) + +/*define for signal field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x00000001 +#define SDMA_PKT_SEMAPHORE_HEADER_signal_shift 30 +#define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift) + +/*define for mailbox field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x00000001 +#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift 31 +#define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_FENCE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_FENCE_HEADER_op_offset 0 +#define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_FENCE_HEADER_op_shift 0 +#define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_FENCE_HEADER_sub_op_offset 0 +#define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_FENCE_HEADER_sub_op_shift 8 +#define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift) + +/*define for DATA word*/ +/*define for data field*/ +#define SDMA_PKT_FENCE_DATA_data_offset 3 +#define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF +#define SDMA_PKT_FENCE_DATA_data_shift 0 +#define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift) + + +/* +** Definitions for SDMA_PKT_SRBM_WRITE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0 +#define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 0 +#define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0 +#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift 8 +#define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift) + +/*define for byte_en field*/ +#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0 +#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F +#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift 28 +#define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift) + +/*define for ADDR word*/ +/*define for addr field*/ +#define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1 +#define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0003FFFF +#define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 0 +#define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift) + +/*define for DATA word*/ +/*define for data field*/ +#define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2 +#define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF +#define SDMA_PKT_SRBM_WRITE_DATA_data_shift 0 +#define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift) + + +/* +** Definitions for SDMA_PKT_PRE_EXE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_PRE_EXE_HEADER_op_offset 0 +#define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_PRE_EXE_HEADER_op_shift 0 +#define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0 +#define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift 8 +#define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift) + +/*define for dev_sel field*/ +#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0 +#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF +#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift 16 +#define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift) + +/*define for EXEC_COUNT word*/ +/*define for exec_count field*/ +#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1 +#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF +#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 0 +#define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift) + + +/* +** Definitions for SDMA_PKT_COND_EXE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COND_EXE_HEADER_op_offset 0 +#define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COND_EXE_HEADER_op_shift 0 +#define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0 +#define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COND_EXE_HEADER_sub_op_shift 8 +#define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift) + +/*define for REFERENCE word*/ +/*define for reference field*/ +#define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3 +#define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF +#define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 0 +#define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift) + +/*define for EXEC_COUNT word*/ +/*define for exec_count field*/ +#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4 +#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF +#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 0 +#define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift) + + +/* +** Definitions for SDMA_PKT_CONSTANT_FILL packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF +#define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift 8 +#define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift) + +/*define for sw field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x00000003 +#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift 16 +#define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift) + +/*define for fillsize field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x00000003 +#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift 30 +#define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1 +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2 +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DATA word*/ +/*define for src_data_31_0 field*/ +#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3 +#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 0 +#define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4 +#define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x003FFFFF +#define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 0 +#define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_DATA_FILL_MULTI packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset 0 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask 0x000000FF +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift 0 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset 0 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift 8 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift) + +/*define for memlog_clr field*/ +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset 0 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask 0x00000001 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift 31 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift) + +/*define for BYTE_STRIDE word*/ +/*define for byte_stride field*/ +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset 1 +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask 0xFFFFFFFF +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift 0 +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift) + +/*define for DMA_COUNT word*/ +/*define for dma_count field*/ +#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset 2 +#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask 0xFFFFFFFF +#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift 0 +#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask) << SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset 3 +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset 4 +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for BYTE_COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset 5 +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask 0x03FFFFFF +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift 0 +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_POLL_REGMEM packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF +#define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift 8 +#define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift) + +/*define for hdp_flush field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x00000001 +#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift 26 +#define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift) + +/*define for func field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x00000007 +#define SDMA_PKT_POLL_REGMEM_HEADER_func_shift 28 +#define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift) + +/*define for mem_poll field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x00000001 +#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift 31 +#define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift) + +/*define for VALUE word*/ +/*define for value field*/ +#define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3 +#define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 0 +#define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift) + +/*define for MASK word*/ +/*define for mask field*/ +#define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4 +#define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 0 +#define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift) + +/*define for DW5 word*/ +/*define for interval field*/ +#define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5 +#define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF +#define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 0 +#define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) + +/*define for retry_count field*/ +#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5 +#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF +#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift 16 +#define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift) + + +/* +** Definitions for SDMA_PKT_POLL_REG_WRITE_MEM packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset 0 +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask 0x000000FF +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift 0 +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset 0 +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift 8 +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift) + +/*define for SRC_ADDR word*/ +/*define for addr_31_2 field*/ +#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset 1 +#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask 0x3FFFFFFF +#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift 2 +#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift) + +/*define for DST_ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 2 +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 3 +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_POLL_DBIT_WRITE_MEM packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask 0x000000FF +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift 8 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift) + +/*define for ea field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask 0x00000003 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift 16 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift) + +/*define for DST_ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) + +/*define for START_PAGE word*/ +/*define for addr_31_4 field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset 3 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask 0x0FFFFFFF +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift 4 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift) + +/*define for PAGE_NUM word*/ +/*define for page_num_31_0 field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset 4 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift) + + +/* +** Definitions for SDMA_PKT_POLL_MEM_VERIFY packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset 0 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask 0x000000FF +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset 0 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift 8 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift) + +/*define for mode field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset 0 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask 0x00000001 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift 31 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift) + +/*define for PATTERN word*/ +/*define for pattern field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset 1 +#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask) << SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift) + +/*define for CMP0_ADDR_START_LO word*/ +/*define for cmp0_start_31_0 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset 2 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift) + +/*define for CMP0_ADDR_START_HI word*/ +/*define for cmp0_start_63_32 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset 3 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift) + +/*define for CMP0_ADDR_END_LO word*/ +/*define for cmp1_end_31_0 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset 4 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift) + +/*define for CMP0_ADDR_END_HI word*/ +/*define for cmp1_end_63_32 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset 5 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift) + +/*define for CMP1_ADDR_START_LO word*/ +/*define for cmp1_start_31_0 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset 6 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift) + +/*define for CMP1_ADDR_START_HI word*/ +/*define for cmp1_start_63_32 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset 7 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift) + +/*define for CMP1_ADDR_END_LO word*/ +/*define for cmp1_end_31_0 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset 8 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift) + +/*define for CMP1_ADDR_END_HI word*/ +/*define for cmp1_end_63_32 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset 9 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift) + +/*define for REC_ADDR_LO word*/ +/*define for rec_31_0 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset 10 +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift) + +/*define for REC_ADDR_HI word*/ +/*define for rec_63_32 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset 11 +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift) + +/*define for RESERVED word*/ +/*define for reserved field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset 12 +#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift) + + +/* +** Definitions for SDMA_PKT_ATOMIC packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_ATOMIC_HEADER_op_offset 0 +#define SDMA_PKT_ATOMIC_HEADER_op_mask 0x000000FF +#define SDMA_PKT_ATOMIC_HEADER_op_shift 0 +#define SDMA_PKT_ATOMIC_HEADER_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift) + +/*define for loop field*/ +#define SDMA_PKT_ATOMIC_HEADER_loop_offset 0 +#define SDMA_PKT_ATOMIC_HEADER_loop_mask 0x00000001 +#define SDMA_PKT_ATOMIC_HEADER_loop_shift 16 +#define SDMA_PKT_ATOMIC_HEADER_LOOP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift) + +/*define for tmz field*/ +#define SDMA_PKT_ATOMIC_HEADER_tmz_offset 0 +#define SDMA_PKT_ATOMIC_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_ATOMIC_HEADER_tmz_shift 18 +#define SDMA_PKT_ATOMIC_HEADER_TMZ(x) (((x) & SDMA_PKT_ATOMIC_HEADER_tmz_mask) << SDMA_PKT_ATOMIC_HEADER_tmz_shift) + +/*define for atomic_op field*/ +#define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0 +#define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask 0x0000007F +#define SDMA_PKT_ATOMIC_HEADER_atomic_op_shift 25 +#define SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift) + +/*define for SRC_DATA_LO word*/ +/*define for src_data_31_0 field*/ +#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset 3 +#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift 0 +#define SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift) + +/*define for SRC_DATA_HI word*/ +/*define for src_data_63_32 field*/ +#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset 4 +#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift 0 +#define SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift) + +/*define for CMP_DATA_LO word*/ +/*define for cmp_data_31_0 field*/ +#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset 5 +#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift 0 +#define SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift) + +/*define for CMP_DATA_HI word*/ +/*define for cmp_data_63_32 field*/ +#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset 6 +#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift 0 +#define SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift) + +/*define for LOOP_INTERVAL word*/ +/*define for loop_interval field*/ +#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset 7 +#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask 0x00001FFF +#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift 0 +#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x) (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift) + + +/* +** Definitions for SDMA_PKT_TIMESTAMP_SET packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0 +#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 0 +#define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0 +#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift 8 +#define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift) + +/*define for INIT_DATA_LO word*/ +/*define for init_data_31_0 field*/ +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1 +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 0 +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift) + +/*define for INIT_DATA_HI word*/ +/*define for init_data_63_32 field*/ +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2 +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 0 +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift) + + +/* +** Definitions for SDMA_PKT_TIMESTAMP_GET packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 0 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift 8 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift) + +/*define for WRITE_ADDR_LO word*/ +/*define for write_addr_31_3 field*/ +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1 +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift 3 +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift) + +/*define for WRITE_ADDR_HI word*/ +/*define for write_addr_63_32 field*/ +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2 +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 0 +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift 8 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift) + +/*define for WRITE_ADDR_LO word*/ +/*define for write_addr_31_3 field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift 3 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift) + +/*define for WRITE_ADDR_HI word*/ +/*define for write_addr_63_32 field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_TRAP packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_TRAP_HEADER_op_offset 0 +#define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF +#define SDMA_PKT_TRAP_HEADER_op_shift 0 +#define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_TRAP_HEADER_sub_op_offset 0 +#define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_TRAP_HEADER_sub_op_shift 8 +#define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift) + +/*define for INT_CONTEXT word*/ +/*define for int_context field*/ +#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1 +#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF +#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 0 +#define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift) + + +/* +** Definitions for SDMA_PKT_DUMMY_TRAP packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_DUMMY_TRAP_HEADER_op_offset 0 +#define SDMA_PKT_DUMMY_TRAP_HEADER_op_mask 0x000000FF +#define SDMA_PKT_DUMMY_TRAP_HEADER_op_shift 0 +#define SDMA_PKT_DUMMY_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset 0 +#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift 8 +#define SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift) + +/*define for INT_CONTEXT word*/ +/*define for int_context field*/ +#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset 1 +#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF +#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift 0 +#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift) + + +/* +** Definitions for SDMA_PKT_NOP packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_NOP_HEADER_op_offset 0 +#define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF +#define SDMA_PKT_NOP_HEADER_op_shift 0 +#define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_NOP_HEADER_sub_op_offset 0 +#define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_NOP_HEADER_sub_op_shift 8 +#define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift) + +/*define for count field*/ +#define SDMA_PKT_NOP_HEADER_count_offset 0 +#define SDMA_PKT_NOP_HEADER_count_mask 0x00003FFF +#define SDMA_PKT_NOP_HEADER_count_shift 16 +#define SDMA_PKT_NOP_HEADER_COUNT(x) (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift) + +/*define for DATA0 word*/ +/*define for data0 field*/ +#define SDMA_PKT_NOP_DATA0_data0_offset 1 +#define SDMA_PKT_NOP_DATA0_data0_mask 0xFFFFFFFF +#define SDMA_PKT_NOP_DATA0_data0_shift 0 +#define SDMA_PKT_NOP_DATA0_DATA0(x) (((x) & SDMA_PKT_NOP_DATA0_data0_mask) << SDMA_PKT_NOP_DATA0_data0_shift) + + +/* +** Definitions for SDMA_AQL_PKT_HEADER packet +*/ + +/*define for HEADER word*/ +/*define for format field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_format_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_format_mask 0x000000FF +#define SDMA_AQL_PKT_HEADER_HEADER_format_shift 0 +#define SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_format_mask) << SDMA_AQL_PKT_HEADER_HEADER_format_shift) + +/*define for barrier field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_barrier_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_barrier_mask 0x00000001 +#define SDMA_AQL_PKT_HEADER_HEADER_barrier_shift 8 +#define SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_barrier_mask) << SDMA_AQL_PKT_HEADER_HEADER_barrier_shift) + +/*define for acquire_fence_scope field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask 0x00000003 +#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift 9 +#define SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift) + +/*define for release_fence_scope field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask 0x00000003 +#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift 11 +#define SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift) + +/*define for reserved field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_reserved_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_reserved_mask 0x00000007 +#define SDMA_AQL_PKT_HEADER_HEADER_reserved_shift 13 +#define SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_reserved_mask) << SDMA_AQL_PKT_HEADER_HEADER_reserved_shift) + +/*define for op field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_op_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_op_mask 0x0000000F +#define SDMA_AQL_PKT_HEADER_HEADER_op_shift 16 +#define SDMA_AQL_PKT_HEADER_HEADER_OP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_op_mask) << SDMA_AQL_PKT_HEADER_HEADER_op_shift) + +/*define for subop field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_subop_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_subop_mask 0x00000007 +#define SDMA_AQL_PKT_HEADER_HEADER_subop_shift 20 +#define SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_subop_mask) << SDMA_AQL_PKT_HEADER_HEADER_subop_shift) + + +/* +** Definitions for SDMA_AQL_PKT_COPY_LINEAR packet +*/ + +/*define for HEADER word*/ +/*define for format field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask 0x000000FF +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift) + +/*define for barrier field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask 0x00000001 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift 8 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift) + +/*define for acquire_fence_scope field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask 0x00000003 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift 9 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift) + +/*define for release_fence_scope field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask 0x00000003 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift 11 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift) + +/*define for reserved field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask 0x00000007 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift 13 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift) + +/*define for op field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask 0x0000000F +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift 16 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift) + +/*define for subop field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask 0x00000007 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift 20 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift) + +/*define for RESERVED_DW1 word*/ +/*define for reserved_dw1 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset 1 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift) + +/*define for RETURN_ADDR_LO word*/ +/*define for return_addr_31_0 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset 2 +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift) + +/*define for RETURN_ADDR_HI word*/ +/*define for return_addr_63_32 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset 3 +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset 4 +#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift) + +/*define for PARAMETER word*/ +/*define for dst_sw field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 5 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) + +/*define for src_sw field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 5 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 6 +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 7 +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 8 +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 9 +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for RESERVED_DW10 word*/ +/*define for reserved_dw10 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset 10 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift) + +/*define for RESERVED_DW11 word*/ +/*define for reserved_dw11 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset 11 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift) + +/*define for RESERVED_DW12 word*/ +/*define for reserved_dw12 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset 12 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift) + +/*define for RESERVED_DW13 word*/ +/*define for reserved_dw13 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset 13 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift) + +/*define for COMPLETION_SIGNAL_LO word*/ +/*define for completion_signal_31_0 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) + +/*define for COMPLETION_SIGNAL_HI word*/ +/*define for completion_signal_63_32 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) + + +/* +** Definitions for SDMA_AQL_PKT_BARRIER_OR packet +*/ + +/*define for HEADER word*/ +/*define for format field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask 0x000000FF +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift) + +/*define for barrier field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask 0x00000001 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift 8 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift) + +/*define for acquire_fence_scope field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask 0x00000003 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift 9 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift) + +/*define for release_fence_scope field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask 0x00000003 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift 11 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift) + +/*define for reserved field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask 0x00000007 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift 13 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift) + +/*define for op field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask 0x0000000F +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift 16 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift) + +/*define for subop field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask 0x00000007 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift 20 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift) + +/*define for RESERVED_DW1 word*/ +/*define for reserved_dw1 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset 1 +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift) + +/*define for DEPENDENT_ADDR_0_LO word*/ +/*define for dependent_addr_0_31_0 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset 2 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift) + +/*define for DEPENDENT_ADDR_0_HI word*/ +/*define for dependent_addr_0_63_32 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset 3 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift) + +/*define for DEPENDENT_ADDR_1_LO word*/ +/*define for dependent_addr_1_31_0 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset 4 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift) + +/*define for DEPENDENT_ADDR_1_HI word*/ +/*define for dependent_addr_1_63_32 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset 5 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift) + +/*define for DEPENDENT_ADDR_2_LO word*/ +/*define for dependent_addr_2_31_0 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset 6 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift) + +/*define for DEPENDENT_ADDR_2_HI word*/ +/*define for dependent_addr_2_63_32 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset 7 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift) + +/*define for DEPENDENT_ADDR_3_LO word*/ +/*define for dependent_addr_3_31_0 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset 8 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift) + +/*define for DEPENDENT_ADDR_3_HI word*/ +/*define for dependent_addr_3_63_32 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset 9 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift) + +/*define for DEPENDENT_ADDR_4_LO word*/ +/*define for dependent_addr_4_31_0 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset 10 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift) + +/*define for DEPENDENT_ADDR_4_HI word*/ +/*define for dependent_addr_4_63_32 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset 11 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift) + +/*define for RESERVED_DW12 word*/ +/*define for reserved_dw12 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset 12 +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift) + +/*define for RESERVED_DW13 word*/ +/*define for reserved_dw13 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset 13 +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift) + +/*define for COMPLETION_SIGNAL_LO word*/ +/*define for completion_signal_31_0 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) + +/*define for COMPLETION_SIGNAL_HI word*/ +/*define for completion_signal_63_32 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) + + +#endif /* __SDMA_PKT_OPEN_H_ */ diff --git a/tinygrad/runtime/autogen/am/gc_9_4_3.py b/tinygrad/runtime/autogen/am/gc_9_4_3.py new file mode 100644 index 0000000000..7b77d7e4f3 --- /dev/null +++ b/tinygrad/runtime/autogen/am/gc_9_4_3.py @@ -0,0 +1,66438 @@ +# mypy: ignore-errors +# -*- coding: utf-8 -*- +# +# TARGET arch is: [] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes + + + + +_gc_9_4_3_OFFSET_HEADER = True # macro +regGRBM_CNTL = 0x0000 # macro +regGRBM_CNTL_BASE_IDX = 0 # macro +regGRBM_SKEW_CNTL = 0x0001 # macro +regGRBM_SKEW_CNTL_BASE_IDX = 0 # macro +regGRBM_STATUS2 = 0x0002 # macro +regGRBM_STATUS2_BASE_IDX = 0 # macro +regGRBM_PWR_CNTL = 0x0003 # macro +regGRBM_PWR_CNTL_BASE_IDX = 0 # macro +regGRBM_STATUS = 0x0004 # macro +regGRBM_STATUS_BASE_IDX = 0 # macro +regGRBM_STATUS_SE0 = 0x0005 # macro +regGRBM_STATUS_SE0_BASE_IDX = 0 # macro +regGRBM_STATUS_SE1 = 0x0006 # macro +regGRBM_STATUS_SE1_BASE_IDX = 0 # macro +regGRBM_SOFT_RESET = 0x0008 # macro +regGRBM_SOFT_RESET_BASE_IDX = 0 # macro +regGRBM_GFX_CLKEN_CNTL = 0x000c # macro +regGRBM_GFX_CLKEN_CNTL_BASE_IDX = 0 # macro +regGRBM_WAIT_IDLE_CLOCKS = 0x000d # macro +regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX = 0 # macro +regGRBM_STATUS_SE2 = 0x000e # macro +regGRBM_STATUS_SE2_BASE_IDX = 0 # macro +regGRBM_STATUS_SE3 = 0x000f # macro +regGRBM_STATUS_SE3_BASE_IDX = 0 # macro +regGRBM_READ_ERROR = 0x0016 # macro +regGRBM_READ_ERROR_BASE_IDX = 0 # macro +regGRBM_READ_ERROR2 = 0x0017 # macro +regGRBM_READ_ERROR2_BASE_IDX = 0 # macro +regGRBM_INT_CNTL = 0x0018 # macro +regGRBM_INT_CNTL_BASE_IDX = 0 # macro +regGRBM_TRAP_OP = 0x0019 # macro +regGRBM_TRAP_OP_BASE_IDX = 0 # macro +regGRBM_TRAP_ADDR = 0x001a # macro +regGRBM_TRAP_ADDR_BASE_IDX = 0 # macro +regGRBM_TRAP_ADDR_MSK = 0x001b # macro +regGRBM_TRAP_ADDR_MSK_BASE_IDX = 0 # macro +regGRBM_TRAP_WD = 0x001c # macro +regGRBM_TRAP_WD_BASE_IDX = 0 # macro +regGRBM_TRAP_WD_MSK = 0x001d # macro +regGRBM_TRAP_WD_MSK_BASE_IDX = 0 # macro +regGRBM_WRITE_ERROR = 0x001f # macro +regGRBM_WRITE_ERROR_BASE_IDX = 0 # macro +regGRBM_IOV_ERROR = 0x0020 # macro +regGRBM_IOV_ERROR_BASE_IDX = 0 # macro +regGRBM_CHIP_REVISION = 0x0021 # macro +regGRBM_CHIP_REVISION_BASE_IDX = 0 # macro +regGRBM_GFX_CNTL = 0x0022 # macro +regGRBM_GFX_CNTL_BASE_IDX = 0 # macro +regGRBM_RSMU_CFG = 0x0023 # macro +regGRBM_RSMU_CFG_BASE_IDX = 0 # macro +regGRBM_IH_CREDIT = 0x0024 # macro +regGRBM_IH_CREDIT_BASE_IDX = 0 # macro +regGRBM_PWR_CNTL2 = 0x0025 # macro +regGRBM_PWR_CNTL2_BASE_IDX = 0 # macro +regGRBM_UTCL2_INVAL_RANGE_START = 0x0026 # macro +regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX = 0 # macro +regGRBM_UTCL2_INVAL_RANGE_END = 0x0027 # macro +regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX = 0 # macro +regGRBM_RSMU_READ_ERROR = 0x0028 # macro +regGRBM_RSMU_READ_ERROR_BASE_IDX = 0 # macro +regGRBM_CHICKEN_BITS = 0x0029 # macro +regGRBM_CHICKEN_BITS_BASE_IDX = 0 # macro +regGRBM_FENCE_RANGE0 = 0x002a # macro +regGRBM_FENCE_RANGE0_BASE_IDX = 0 # macro +regGRBM_FENCE_RANGE1 = 0x002b # macro +regGRBM_FENCE_RANGE1_BASE_IDX = 0 # macro +regGRBM_IOV_READ_ERROR = 0x002c # macro +regGRBM_IOV_READ_ERROR_BASE_IDX = 0 # macro +regGRBM_NOWHERE = 0x003f # macro +regGRBM_NOWHERE_BASE_IDX = 0 # macro +regGRBM_SCRATCH_REG0 = 0x0040 # macro +regGRBM_SCRATCH_REG0_BASE_IDX = 0 # macro +regGRBM_SCRATCH_REG1 = 0x0041 # macro +regGRBM_SCRATCH_REG1_BASE_IDX = 0 # macro +regGRBM_SCRATCH_REG2 = 0x0042 # macro +regGRBM_SCRATCH_REG2_BASE_IDX = 0 # macro +regGRBM_SCRATCH_REG3 = 0x0043 # macro +regGRBM_SCRATCH_REG3_BASE_IDX = 0 # macro +regGRBM_SCRATCH_REG4 = 0x0044 # macro +regGRBM_SCRATCH_REG4_BASE_IDX = 0 # macro +regGRBM_SCRATCH_REG5 = 0x0045 # macro +regGRBM_SCRATCH_REG5_BASE_IDX = 0 # macro +regGRBM_SCRATCH_REG6 = 0x0046 # macro +regGRBM_SCRATCH_REG6_BASE_IDX = 0 # macro +regGRBM_SCRATCH_REG7 = 0x0047 # macro +regGRBM_SCRATCH_REG7_BASE_IDX = 0 # macro +regVIOLATION_DATA_ASYNC_VF_PROG = 0x0048 # macro +regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX = 0 # macro +regCP_CPC_DEBUG_CNTL = 0x0080 # macro +regCP_CPC_DEBUG_CNTL_BASE_IDX = 0 # macro +regCP_CPF_DEBUG_CNTL = 0x0082 # macro +regCP_CPF_DEBUG_CNTL_BASE_IDX = 0 # macro +regCP_CPC_STATUS = 0x0084 # macro +regCP_CPC_STATUS_BASE_IDX = 0 # macro +regCP_CPC_BUSY_STAT = 0x0085 # macro +regCP_CPC_BUSY_STAT_BASE_IDX = 0 # macro +regCP_CPC_STALLED_STAT1 = 0x0086 # macro +regCP_CPC_STALLED_STAT1_BASE_IDX = 0 # macro +regCP_CPF_STATUS = 0x0087 # macro +regCP_CPF_STATUS_BASE_IDX = 0 # macro +regCP_CPF_BUSY_STAT = 0x0088 # macro +regCP_CPF_BUSY_STAT_BASE_IDX = 0 # macro +regCP_CPF_STALLED_STAT1 = 0x0089 # macro +regCP_CPF_STALLED_STAT1_BASE_IDX = 0 # macro +regCP_CPC_GRBM_FREE_COUNT = 0x008b # macro +regCP_CPC_GRBM_FREE_COUNT_BASE_IDX = 0 # macro +regCP_CPC_PRIV_VIOLATION_ADDR = 0x008c # macro +regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX = 0 # macro +regCP_MEC_CNTL = 0x008d # macro +regCP_MEC_CNTL_BASE_IDX = 0 # macro +regCP_MEC_ME1_HEADER_DUMP = 0x008e # macro +regCP_MEC_ME1_HEADER_DUMP_BASE_IDX = 0 # macro +regCP_MEC_ME2_HEADER_DUMP = 0x008f # macro +regCP_MEC_ME2_HEADER_DUMP_BASE_IDX = 0 # macro +regCP_CPC_SCRATCH_INDEX = 0x0090 # macro +regCP_CPC_SCRATCH_INDEX_BASE_IDX = 0 # macro +regCP_CPC_SCRATCH_DATA = 0x0091 # macro +regCP_CPC_SCRATCH_DATA_BASE_IDX = 0 # macro +regCP_CPF_GRBM_FREE_COUNT = 0x0092 # macro +regCP_CPF_GRBM_FREE_COUNT_BASE_IDX = 0 # macro +regCP_CPC_HALT_HYST_COUNT = 0x00a7 # macro +regCP_CPC_HALT_HYST_COUNT_BASE_IDX = 0 # macro +regCP_CE_COMPARE_COUNT = 0x00c0 # macro +regCP_CE_COMPARE_COUNT_BASE_IDX = 0 # macro +regCP_CE_DE_COUNT = 0x00c1 # macro +regCP_CE_DE_COUNT_BASE_IDX = 0 # macro +regCP_DE_CE_COUNT = 0x00c2 # macro +regCP_DE_CE_COUNT_BASE_IDX = 0 # macro +regCP_DE_LAST_INVAL_COUNT = 0x00c3 # macro +regCP_DE_LAST_INVAL_COUNT_BASE_IDX = 0 # macro +regCP_DE_DE_COUNT = 0x00c4 # macro +regCP_DE_DE_COUNT_BASE_IDX = 0 # macro +regCP_STALLED_STAT3 = 0x019c # macro +regCP_STALLED_STAT3_BASE_IDX = 0 # macro +regCP_STALLED_STAT1 = 0x019d # macro +regCP_STALLED_STAT1_BASE_IDX = 0 # macro +regCP_STALLED_STAT2 = 0x019e # macro +regCP_STALLED_STAT2_BASE_IDX = 0 # macro +regCP_BUSY_STAT = 0x019f # macro +regCP_BUSY_STAT_BASE_IDX = 0 # macro +regCP_STAT = 0x01a0 # macro +regCP_STAT_BASE_IDX = 0 # macro +regCP_ME_HEADER_DUMP = 0x01a1 # macro +regCP_ME_HEADER_DUMP_BASE_IDX = 0 # macro +regCP_PFP_HEADER_DUMP = 0x01a2 # macro +regCP_PFP_HEADER_DUMP_BASE_IDX = 0 # macro +regCP_GRBM_FREE_COUNT = 0x01a3 # macro +regCP_GRBM_FREE_COUNT_BASE_IDX = 0 # macro +regCP_CE_HEADER_DUMP = 0x01a4 # macro +regCP_CE_HEADER_DUMP_BASE_IDX = 0 # macro +regCP_PFP_INSTR_PNTR = 0x01a5 # macro +regCP_PFP_INSTR_PNTR_BASE_IDX = 0 # macro +regCP_ME_INSTR_PNTR = 0x01a6 # macro +regCP_ME_INSTR_PNTR_BASE_IDX = 0 # macro +regCP_CE_INSTR_PNTR = 0x01a7 # macro +regCP_CE_INSTR_PNTR_BASE_IDX = 0 # macro +regCP_MEC1_INSTR_PNTR = 0x01a8 # macro +regCP_MEC1_INSTR_PNTR_BASE_IDX = 0 # macro +regCP_MEC2_INSTR_PNTR = 0x01a9 # macro +regCP_MEC2_INSTR_PNTR_BASE_IDX = 0 # macro +regCP_CSF_STAT = 0x01b4 # macro +regCP_CSF_STAT_BASE_IDX = 0 # macro +regCP_ME_CNTL = 0x01b6 # macro +regCP_ME_CNTL_BASE_IDX = 0 # macro +regCP_CNTX_STAT = 0x01b8 # macro +regCP_CNTX_STAT_BASE_IDX = 0 # macro +regCP_ME_PREEMPTION = 0x01b9 # macro +regCP_ME_PREEMPTION_BASE_IDX = 0 # macro +regCP_ROQ_THRESHOLDS = 0x01bc # macro +regCP_ROQ_THRESHOLDS_BASE_IDX = 0 # macro +regCP_MEQ_STQ_THRESHOLD = 0x01bd # macro +regCP_MEQ_STQ_THRESHOLD_BASE_IDX = 0 # macro +regCP_RB2_RPTR = 0x01be # macro +regCP_RB2_RPTR_BASE_IDX = 0 # macro +regCP_RB1_RPTR = 0x01bf # macro +regCP_RB1_RPTR_BASE_IDX = 0 # macro +regCP_RB0_RPTR = 0x01c0 # macro +regCP_RB0_RPTR_BASE_IDX = 0 # macro +regCP_RB_RPTR = 0x01c0 # macro +regCP_RB_RPTR_BASE_IDX = 0 # macro +regCP_RB_WPTR_DELAY = 0x01c1 # macro +regCP_RB_WPTR_DELAY_BASE_IDX = 0 # macro +regCP_RB_WPTR_POLL_CNTL = 0x01c2 # macro +regCP_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +regCP_ROQ1_THRESHOLDS = 0x01d5 # macro +regCP_ROQ1_THRESHOLDS_BASE_IDX = 0 # macro +regCP_ROQ2_THRESHOLDS = 0x01d6 # macro +regCP_ROQ2_THRESHOLDS_BASE_IDX = 0 # macro +regCP_STQ_THRESHOLDS = 0x01d7 # macro +regCP_STQ_THRESHOLDS_BASE_IDX = 0 # macro +regCP_QUEUE_THRESHOLDS = 0x01d8 # macro +regCP_QUEUE_THRESHOLDS_BASE_IDX = 0 # macro +regCP_MEQ_THRESHOLDS = 0x01d9 # macro +regCP_MEQ_THRESHOLDS_BASE_IDX = 0 # macro +regCP_ROQ_AVAIL = 0x01da # macro +regCP_ROQ_AVAIL_BASE_IDX = 0 # macro +regCP_STQ_AVAIL = 0x01db # macro +regCP_STQ_AVAIL_BASE_IDX = 0 # macro +regCP_ROQ2_AVAIL = 0x01dc # macro +regCP_ROQ2_AVAIL_BASE_IDX = 0 # macro +regCP_MEQ_AVAIL = 0x01dd # macro +regCP_MEQ_AVAIL_BASE_IDX = 0 # macro +regCP_CMD_INDEX = 0x01de # macro +regCP_CMD_INDEX_BASE_IDX = 0 # macro +regCP_CMD_DATA = 0x01df # macro +regCP_CMD_DATA_BASE_IDX = 0 # macro +regCP_ROQ_RB_STAT = 0x01e0 # macro +regCP_ROQ_RB_STAT_BASE_IDX = 0 # macro +regCP_ROQ_IB1_STAT = 0x01e1 # macro +regCP_ROQ_IB1_STAT_BASE_IDX = 0 # macro +regCP_ROQ_IB2_STAT = 0x01e2 # macro +regCP_ROQ_IB2_STAT_BASE_IDX = 0 # macro +regCP_STQ_STAT = 0x01e3 # macro +regCP_STQ_STAT_BASE_IDX = 0 # macro +regCP_STQ_WR_STAT = 0x01e4 # macro +regCP_STQ_WR_STAT_BASE_IDX = 0 # macro +regCP_MEQ_STAT = 0x01e5 # macro +regCP_MEQ_STAT_BASE_IDX = 0 # macro +regCP_CEQ1_AVAIL = 0x01e6 # macro +regCP_CEQ1_AVAIL_BASE_IDX = 0 # macro +regCP_CEQ2_AVAIL = 0x01e7 # macro +regCP_CEQ2_AVAIL_BASE_IDX = 0 # macro +regCP_CE_ROQ_RB_STAT = 0x01e8 # macro +regCP_CE_ROQ_RB_STAT_BASE_IDX = 0 # macro +regCP_CE_ROQ_IB1_STAT = 0x01e9 # macro +regCP_CE_ROQ_IB1_STAT_BASE_IDX = 0 # macro +regCP_CE_ROQ_IB2_STAT = 0x01ea # macro +regCP_CE_ROQ_IB2_STAT_BASE_IDX = 0 # macro +regCP_INT_STAT_DEBUG = 0x01f7 # macro +regCP_INT_STAT_DEBUG_BASE_IDX = 0 # macro +regCP_DEBUG_CNTL = 0x01f8 # macro +regCP_DEBUG_CNTL_BASE_IDX = 0 # macro +regCP_PRIV_VIOLATION_ADDR = 0x01fa # macro +regCP_PRIV_VIOLATION_ADDR_BASE_IDX = 0 # macro +regVGT_VTX_VECT_EJECT_REG = 0x022c # macro +regVGT_VTX_VECT_EJECT_REG_BASE_IDX = 0 # macro +regVGT_DMA_DATA_FIFO_DEPTH = 0x022d # macro +regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX = 0 # macro +regVGT_DMA_REQ_FIFO_DEPTH = 0x022e # macro +regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX = 0 # macro +regVGT_DRAW_INIT_FIFO_DEPTH = 0x022f # macro +regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX = 0 # macro +regVGT_LAST_COPY_STATE = 0x0230 # macro +regVGT_LAST_COPY_STATE_BASE_IDX = 0 # macro +regVGT_CACHE_INVALIDATION = 0x0231 # macro +regVGT_CACHE_INVALIDATION_BASE_IDX = 0 # macro +regVGT_RESET_DEBUG = 0x0232 # macro +regVGT_RESET_DEBUG_BASE_IDX = 0 # macro +regVGT_STRMOUT_DELAY = 0x0233 # macro +regVGT_STRMOUT_DELAY_BASE_IDX = 0 # macro +regVGT_FIFO_DEPTHS = 0x0234 # macro +regVGT_FIFO_DEPTHS_BASE_IDX = 0 # macro +regVGT_GS_VERTEX_REUSE = 0x0235 # macro +regVGT_GS_VERTEX_REUSE_BASE_IDX = 0 # macro +regVGT_MC_LAT_CNTL = 0x0236 # macro +regVGT_MC_LAT_CNTL_BASE_IDX = 0 # macro +regIA_CNTL_STATUS = 0x0237 # macro +regIA_CNTL_STATUS_BASE_IDX = 0 # macro +regVGT_CNTL_STATUS = 0x023c # macro +regVGT_CNTL_STATUS_BASE_IDX = 0 # macro +regWD_CNTL_STATUS = 0x023f # macro +regWD_CNTL_STATUS_BASE_IDX = 0 # macro +regCC_GC_PRIM_CONFIG = 0x0240 # macro +regCC_GC_PRIM_CONFIG_BASE_IDX = 0 # macro +regGC_USER_PRIM_CONFIG = 0x0241 # macro +regGC_USER_PRIM_CONFIG_BASE_IDX = 0 # macro +regWD_QOS = 0x0242 # macro +regWD_QOS_BASE_IDX = 0 # macro +regWD_UTCL1_CNTL = 0x0243 # macro +regWD_UTCL1_CNTL_BASE_IDX = 0 # macro +regWD_UTCL1_STATUS = 0x0244 # macro +regWD_UTCL1_STATUS_BASE_IDX = 0 # macro +regIA_UTCL1_CNTL = 0x0246 # macro +regIA_UTCL1_CNTL_BASE_IDX = 0 # macro +regIA_UTCL1_STATUS = 0x0247 # macro +regIA_UTCL1_STATUS_BASE_IDX = 0 # macro +regVGT_SYS_CONFIG = 0x0263 # macro +regVGT_SYS_CONFIG_BASE_IDX = 0 # macro +regVGT_VS_MAX_WAVE_ID = 0x0268 # macro +regVGT_VS_MAX_WAVE_ID_BASE_IDX = 0 # macro +regVGT_GS_MAX_WAVE_ID = 0x0269 # macro +regVGT_GS_MAX_WAVE_ID_BASE_IDX = 0 # macro +regGFX_PIPE_CONTROL = 0x026d # macro +regGFX_PIPE_CONTROL_BASE_IDX = 0 # macro +regCC_GC_SHADER_ARRAY_CONFIG = 0x026f # macro +regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX = 0 # macro +regGC_USER_SHADER_ARRAY_CONFIG = 0x0270 # macro +regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX = 0 # macro +regVGT_DMA_PRIMITIVE_TYPE = 0x0271 # macro +regVGT_DMA_PRIMITIVE_TYPE_BASE_IDX = 0 # macro +regVGT_DMA_CONTROL = 0x0272 # macro +regVGT_DMA_CONTROL_BASE_IDX = 0 # macro +regVGT_DMA_LS_HS_CONFIG = 0x0273 # macro +regVGT_DMA_LS_HS_CONFIG_BASE_IDX = 0 # macro +regWD_BUF_RESOURCE_1 = 0x0276 # macro +regWD_BUF_RESOURCE_1_BASE_IDX = 0 # macro +regWD_BUF_RESOURCE_2 = 0x0277 # macro +regWD_BUF_RESOURCE_2_BASE_IDX = 0 # macro +regPA_CL_CNTL_STATUS = 0x0284 # macro +regPA_CL_CNTL_STATUS_BASE_IDX = 0 # macro +regPA_CL_ENHANCE = 0x0285 # macro +regPA_CL_ENHANCE_BASE_IDX = 0 # macro +regPA_CL_RESET_DEBUG = 0x0286 # macro +regPA_CL_RESET_DEBUG_BASE_IDX = 0 # macro +regPA_SU_CNTL_STATUS = 0x0294 # macro +regPA_SU_CNTL_STATUS_BASE_IDX = 0 # macro +regPA_SC_FIFO_DEPTH_CNTL = 0x0295 # macro +regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX = 0 # macro +regPA_SC_P3D_TRAP_SCREEN_HV_LOCK = 0x02c0 # macro +regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX = 0 # macro +regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK = 0x02c1 # macro +regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX = 0 # macro +regPA_SC_TRAP_SCREEN_HV_LOCK = 0x02c2 # macro +regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX = 0 # macro +regPA_SC_FORCE_EOV_MAX_CNTS = 0x02c9 # macro +regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX = 0 # macro +regPA_SC_BINNER_EVENT_CNTL_0 = 0x02cc # macro +regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX = 0 # macro +regPA_SC_BINNER_EVENT_CNTL_1 = 0x02cd # macro +regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX = 0 # macro +regPA_SC_BINNER_EVENT_CNTL_2 = 0x02ce # macro +regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX = 0 # macro +regPA_SC_BINNER_EVENT_CNTL_3 = 0x02cf # macro +regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX = 0 # macro +regPA_SC_BINNER_TIMEOUT_COUNTER = 0x02d0 # macro +regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX = 0 # macro +regPA_SC_BINNER_PERF_CNTL_0 = 0x02d1 # macro +regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX = 0 # macro +regPA_SC_BINNER_PERF_CNTL_1 = 0x02d2 # macro +regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX = 0 # macro +regPA_SC_BINNER_PERF_CNTL_2 = 0x02d3 # macro +regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX = 0 # macro +regPA_SC_BINNER_PERF_CNTL_3 = 0x02d4 # macro +regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX = 0 # macro +regPA_SC_ENHANCE_2 = 0x02dc # macro +regPA_SC_ENHANCE_2_BASE_IDX = 0 # macro +regPA_SC_FIFO_SIZE = 0x02f3 # macro +regPA_SC_FIFO_SIZE_BASE_IDX = 0 # macro +regPA_SC_IF_FIFO_SIZE = 0x02f5 # macro +regPA_SC_IF_FIFO_SIZE_BASE_IDX = 0 # macro +regPA_SC_PKR_WAVE_TABLE_CNTL = 0x02f8 # macro +regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX = 0 # macro +regPA_UTCL1_CNTL1 = 0x02f9 # macro +regPA_UTCL1_CNTL1_BASE_IDX = 0 # macro +regPA_UTCL1_CNTL2 = 0x02fa # macro +regPA_UTCL1_CNTL2_BASE_IDX = 0 # macro +regPA_SIDEBAND_REQUEST_DELAYS = 0x02fb # macro +regPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX = 0 # macro +regPA_SC_ENHANCE = 0x02fc # macro +regPA_SC_ENHANCE_BASE_IDX = 0 # macro +regPA_SC_ENHANCE_1 = 0x02fd # macro +regPA_SC_ENHANCE_1_BASE_IDX = 0 # macro +regPA_SC_DSM_CNTL = 0x02fe # macro +regPA_SC_DSM_CNTL_BASE_IDX = 0 # macro +regPA_SC_TILE_STEERING_CREST_OVERRIDE = 0x02ff # macro +regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX = 0 # macro +regSQ_CONFIG = 0x0300 # macro +regSQ_CONFIG_BASE_IDX = 0 # macro +regSQC_CONFIG = 0x0301 # macro +regSQC_CONFIG_BASE_IDX = 0 # macro +regLDS_CONFIG = 0x0302 # macro +regLDS_CONFIG_BASE_IDX = 0 # macro +regSQ_RANDOM_WAVE_PRI = 0x0303 # macro +regSQ_RANDOM_WAVE_PRI_BASE_IDX = 0 # macro +regSQ_REG_CREDITS = 0x0304 # macro +regSQ_REG_CREDITS_BASE_IDX = 0 # macro +regSQ_FIFO_SIZES = 0x0305 # macro +regSQ_FIFO_SIZES_BASE_IDX = 0 # macro +regSQ_DSM_CNTL = 0x0306 # macro +regSQ_DSM_CNTL_BASE_IDX = 0 # macro +regSQ_DSM_CNTL2 = 0x0307 # macro +regSQ_DSM_CNTL2_BASE_IDX = 0 # macro +regSQ_RUNTIME_CONFIG = 0x0308 # macro +regSQ_RUNTIME_CONFIG_BASE_IDX = 0 # macro +regSQ_DEBUG_STS_GLOBAL = 0x0309 # macro +regSQ_DEBUG_STS_GLOBAL_BASE_IDX = 0 # macro +regSH_MEM_BASES = 0x030a # macro +regSH_MEM_BASES_BASE_IDX = 0 # macro +regSQ_TIMEOUT_CONFIG = 0x030b # macro +regSQ_TIMEOUT_CONFIG_BASE_IDX = 0 # macro +regSQ_TIMEOUT_STATUS = 0x030c # macro +regSQ_TIMEOUT_STATUS_BASE_IDX = 0 # macro +regSH_MEM_CONFIG = 0x030d # macro +regSH_MEM_CONFIG_BASE_IDX = 0 # macro +regSP_MFMA_PORTD_RD_CONFIG = 0x030e # macro +regSP_MFMA_PORTD_RD_CONFIG_BASE_IDX = 0 # macro +regSH_CAC_CONFIG = 0x030f # macro +regSH_CAC_CONFIG_BASE_IDX = 0 # macro +regSQ_DEBUG_STS_GLOBAL2 = 0x0310 # macro +regSQ_DEBUG_STS_GLOBAL2_BASE_IDX = 0 # macro +regSQ_DEBUG_STS_GLOBAL3 = 0x0311 # macro +regSQ_DEBUG_STS_GLOBAL3_BASE_IDX = 0 # macro +regCC_GC_SHADER_RATE_CONFIG = 0x0312 # macro +regCC_GC_SHADER_RATE_CONFIG_BASE_IDX = 0 # macro +regGC_USER_SHADER_RATE_CONFIG = 0x0313 # macro +regGC_USER_SHADER_RATE_CONFIG_BASE_IDX = 0 # macro +regSQ_INTERRUPT_AUTO_MASK = 0x0314 # macro +regSQ_INTERRUPT_AUTO_MASK_BASE_IDX = 0 # macro +regSQ_INTERRUPT_MSG_CTRL = 0x0315 # macro +regSQ_INTERRUPT_MSG_CTRL_BASE_IDX = 0 # macro +regSQ_DEBUG_PERFCOUNT_TRAP = 0x0316 # macro +regSQ_DEBUG_PERFCOUNT_TRAP_BASE_IDX = 0 # macro +regSQ_UTCL1_CNTL1 = 0x0317 # macro +regSQ_UTCL1_CNTL1_BASE_IDX = 0 # macro +regSQ_UTCL1_CNTL2 = 0x0318 # macro +regSQ_UTCL1_CNTL2_BASE_IDX = 0 # macro +regSQ_UTCL1_STATUS = 0x0319 # macro +regSQ_UTCL1_STATUS_BASE_IDX = 0 # macro +regSQ_FED_INTERRUPT_STATUS = 0x031a # macro +regSQ_FED_INTERRUPT_STATUS_BASE_IDX = 0 # macro +regSQ_CGTS_CONFIG = 0x031b # macro +regSQ_CGTS_CONFIG_BASE_IDX = 0 # macro +regSQ_SHADER_TBA_LO = 0x031c # macro +regSQ_SHADER_TBA_LO_BASE_IDX = 0 # macro +regSQ_SHADER_TBA_HI = 0x031d # macro +regSQ_SHADER_TBA_HI_BASE_IDX = 0 # macro +regSQ_SHADER_TMA_LO = 0x031e # macro +regSQ_SHADER_TMA_LO_BASE_IDX = 0 # macro +regSQ_SHADER_TMA_HI = 0x031f # macro +regSQ_SHADER_TMA_HI_BASE_IDX = 0 # macro +regSQC_DSM_CNTL = 0x0320 # macro +regSQC_DSM_CNTL_BASE_IDX = 0 # macro +regSQC_DSM_CNTLA = 0x0321 # macro +regSQC_DSM_CNTLA_BASE_IDX = 0 # macro +regSQC_DSM_CNTLB = 0x0322 # macro +regSQC_DSM_CNTLB_BASE_IDX = 0 # macro +regSQC_DSM_CNTL2 = 0x0325 # macro +regSQC_DSM_CNTL2_BASE_IDX = 0 # macro +regSQC_DSM_CNTL2A = 0x0326 # macro +regSQC_DSM_CNTL2A_BASE_IDX = 0 # macro +regSQC_DSM_CNTL2B = 0x0327 # macro +regSQC_DSM_CNTL2B_BASE_IDX = 0 # macro +regSQC_DSM_CNTL2E = 0x032a # macro +regSQC_DSM_CNTL2E_BASE_IDX = 0 # macro +regSQC_EDC_FUE_CNTL = 0x032b # macro +regSQC_EDC_FUE_CNTL_BASE_IDX = 0 # macro +regSQC_EDC_CNT2 = 0x032c # macro +regSQC_EDC_CNT2_BASE_IDX = 0 # macro +regSQC_EDC_CNT3 = 0x032d # macro +regSQC_EDC_CNT3_BASE_IDX = 0 # macro +regSQC_EDC_PARITY_CNT3 = 0x032e # macro +regSQC_EDC_PARITY_CNT3_BASE_IDX = 0 # macro +regSQ_DEBUG = 0x0332 # macro +regSQ_DEBUG_BASE_IDX = 0 # macro +regSQ_PERF_SNAPSHOT_CTRL = 0x0334 # macro +regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX = 0 # macro +regSQ_DEBUG_FOR_INTERNAL_CTRL = 0x0335 # macro +regSQ_DEBUG_FOR_INTERNAL_CTRL_BASE_IDX = 0 # macro +regSQ_REG_TIMESTAMP = 0x0374 # macro +regSQ_REG_TIMESTAMP_BASE_IDX = 0 # macro +regSQ_CMD_TIMESTAMP = 0x0375 # macro +regSQ_CMD_TIMESTAMP_BASE_IDX = 0 # macro +regSQ_HOSTTRAP_STATUS = 0x0376 # macro +regSQ_HOSTTRAP_STATUS_BASE_IDX = 0 # macro +regSQ_IND_INDEX = 0x0378 # macro +regSQ_IND_INDEX_BASE_IDX = 0 # macro +regSQ_IND_DATA = 0x0379 # macro +regSQ_IND_DATA_BASE_IDX = 0 # macro +regSQ_CONFIG1 = 0x037a # macro +regSQ_CONFIG1_BASE_IDX = 0 # macro +regSQ_CMD = 0x037b # macro +regSQ_CMD_BASE_IDX = 0 # macro +regSQ_TIME_HI = 0x037c # macro +regSQ_TIME_HI_BASE_IDX = 0 # macro +regSQ_TIME_LO = 0x037d # macro +regSQ_TIME_LO_BASE_IDX = 0 # macro +regSQ_DS_0 = 0x037f # macro +regSQ_DS_0_BASE_IDX = 0 # macro +regSQ_DS_1 = 0x037f # macro +regSQ_DS_1_BASE_IDX = 0 # macro +regSQ_EXP_0 = 0x037f # macro +regSQ_EXP_0_BASE_IDX = 0 # macro +regSQ_EXP_1 = 0x037f # macro +regSQ_EXP_1_BASE_IDX = 0 # macro +regSQ_FLAT_0 = 0x037f # macro +regSQ_FLAT_0_BASE_IDX = 0 # macro +regSQ_FLAT_1 = 0x037f # macro +regSQ_FLAT_1_BASE_IDX = 0 # macro +regSQ_GLBL_0 = 0x037f # macro +regSQ_GLBL_0_BASE_IDX = 0 # macro +regSQ_GLBL_1 = 0x037f # macro +regSQ_GLBL_1_BASE_IDX = 0 # macro +regSQ_INST = 0x037f # macro +regSQ_INST_BASE_IDX = 0 # macro +regSQ_MIMG_0 = 0x037f # macro +regSQ_MIMG_0_BASE_IDX = 0 # macro +regSQ_MIMG_1 = 0x037f # macro +regSQ_MIMG_1_BASE_IDX = 0 # macro +regSQ_MTBUF_0 = 0x037f # macro +regSQ_MTBUF_0_BASE_IDX = 0 # macro +regSQ_MTBUF_1 = 0x037f # macro +regSQ_MTBUF_1_BASE_IDX = 0 # macro +regSQ_MUBUF_0 = 0x037f # macro +regSQ_MUBUF_0_BASE_IDX = 0 # macro +regSQ_MUBUF_1 = 0x037f # macro +regSQ_MUBUF_1_BASE_IDX = 0 # macro +regSQ_SCRATCH_0 = 0x037f # macro +regSQ_SCRATCH_0_BASE_IDX = 0 # macro +regSQ_SCRATCH_1 = 0x037f # macro +regSQ_SCRATCH_1_BASE_IDX = 0 # macro +regSQ_SMEM_0 = 0x037f # macro +regSQ_SMEM_0_BASE_IDX = 0 # macro +regSQ_SMEM_1 = 0x037f # macro +regSQ_SMEM_1_BASE_IDX = 0 # macro +regSQ_SOP1 = 0x037f # macro +regSQ_SOP1_BASE_IDX = 0 # macro +regSQ_SOP2 = 0x037f # macro +regSQ_SOP2_BASE_IDX = 0 # macro +regSQ_SOPC = 0x037f # macro +regSQ_SOPC_BASE_IDX = 0 # macro +regSQ_SOPK = 0x037f # macro +regSQ_SOPK_BASE_IDX = 0 # macro +regSQ_SOPP = 0x037f # macro +regSQ_SOPP_BASE_IDX = 0 # macro +regSQ_VINTRP = 0x037f # macro +regSQ_VINTRP_BASE_IDX = 0 # macro +regSQ_VOP1 = 0x037f # macro +regSQ_VOP1_BASE_IDX = 0 # macro +regSQ_VOP2 = 0x037f # macro +regSQ_VOP2_BASE_IDX = 0 # macro +regSQ_VOP3P_0 = 0x037f # macro +regSQ_VOP3P_0_BASE_IDX = 0 # macro +regSQ_VOP3P_1 = 0x037f # macro +regSQ_VOP3P_1_BASE_IDX = 0 # macro +regSQ_VOP3P_MFMA_0 = 0x037f # macro +regSQ_VOP3P_MFMA_0_BASE_IDX = 0 # macro +regSQ_VOP3P_MFMA_1 = 0x037f # macro +regSQ_VOP3P_MFMA_1_BASE_IDX = 0 # macro +regSQ_VOP3_0 = 0x037f # macro +regSQ_VOP3_0_BASE_IDX = 0 # macro +regSQ_VOP3_0_SDST_ENC = 0x037f # macro +regSQ_VOP3_0_SDST_ENC_BASE_IDX = 0 # macro +regSQ_VOP3_1 = 0x037f # macro +regSQ_VOP3_1_BASE_IDX = 0 # macro +regSQ_VOPC = 0x037f # macro +regSQ_VOPC_BASE_IDX = 0 # macro +regSQ_VOP_DPP = 0x037f # macro +regSQ_VOP_DPP_BASE_IDX = 0 # macro +regSQ_VOP_SDWA = 0x037f # macro +regSQ_VOP_SDWA_BASE_IDX = 0 # macro +regSQ_VOP_SDWA_SDST_ENC = 0x037f # macro +regSQ_VOP_SDWA_SDST_ENC_BASE_IDX = 0 # macro +regSQ_LB_CTR_CTRL = 0x0398 # macro +regSQ_LB_CTR_CTRL_BASE_IDX = 0 # macro +regSQ_LB_DATA0 = 0x0399 # macro +regSQ_LB_DATA0_BASE_IDX = 0 # macro +regSQ_LB_DATA1 = 0x039a # macro +regSQ_LB_DATA1_BASE_IDX = 0 # macro +regSQ_LB_DATA2 = 0x039b # macro +regSQ_LB_DATA2_BASE_IDX = 0 # macro +regSQ_LB_DATA3 = 0x039c # macro +regSQ_LB_DATA3_BASE_IDX = 0 # macro +regSQ_LB_CTR_SEL = 0x039d # macro +regSQ_LB_CTR_SEL_BASE_IDX = 0 # macro +regSQ_LB_CTR0_CU = 0x039e # macro +regSQ_LB_CTR0_CU_BASE_IDX = 0 # macro +regSQ_LB_CTR1_CU = 0x039f # macro +regSQ_LB_CTR1_CU_BASE_IDX = 0 # macro +regSQ_LB_CTR2_CU = 0x03a0 # macro +regSQ_LB_CTR2_CU_BASE_IDX = 0 # macro +regSQ_LB_CTR3_CU = 0x03a1 # macro +regSQ_LB_CTR3_CU_BASE_IDX = 0 # macro +regSQC_EDC_CNT = 0x03a2 # macro +regSQC_EDC_CNT_BASE_IDX = 0 # macro +regSQ_EDC_SEC_CNT = 0x03a3 # macro +regSQ_EDC_SEC_CNT_BASE_IDX = 0 # macro +regSQ_EDC_DED_CNT = 0x03a4 # macro +regSQ_EDC_DED_CNT_BASE_IDX = 0 # macro +regSQ_EDC_INFO = 0x03a5 # macro +regSQ_EDC_INFO_BASE_IDX = 0 # macro +regSQ_EDC_CNT = 0x03a6 # macro +regSQ_EDC_CNT_BASE_IDX = 0 # macro +regSQ_EDC_FUE_CNTL = 0x03a7 # macro +regSQ_EDC_FUE_CNTL_BASE_IDX = 0 # macro +regSQ_THREAD_TRACE_WORD_CMN = 0x03b0 # macro +regSQ_THREAD_TRACE_WORD_CMN_BASE_IDX = 0 # macro +regSQ_THREAD_TRACE_WORD_EVENT = 0x03b0 # macro +regSQ_THREAD_TRACE_WORD_EVENT_BASE_IDX = 0 # macro +regSQ_THREAD_TRACE_WORD_INST = 0x03b0 # macro +regSQ_THREAD_TRACE_WORD_INST_BASE_IDX = 0 # macro +regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 = 0x03b0 # macro +regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_BASE_IDX = 0 # macro +regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 = 0x03b0 # macro +regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_BASE_IDX = 0 # macro +regSQ_THREAD_TRACE_WORD_ISSUE = 0x03b0 # macro +regSQ_THREAD_TRACE_WORD_ISSUE_BASE_IDX = 0 # macro +regSQ_THREAD_TRACE_WORD_MISC = 0x03b0 # macro +regSQ_THREAD_TRACE_WORD_MISC_BASE_IDX = 0 # macro +regSQ_THREAD_TRACE_WORD_PERF_1_OF_2 = 0x03b0 # macro +regSQ_THREAD_TRACE_WORD_PERF_1_OF_2_BASE_IDX = 0 # macro +regSQ_THREAD_TRACE_WORD_REG_1_OF_2 = 0x03b0 # macro +regSQ_THREAD_TRACE_WORD_REG_1_OF_2_BASE_IDX = 0 # macro +regSQ_THREAD_TRACE_WORD_REG_2_OF_2 = 0x03b0 # macro +regSQ_THREAD_TRACE_WORD_REG_2_OF_2_BASE_IDX = 0 # macro +regSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 = 0x03b0 # macro +regSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_BASE_IDX = 0 # macro +regSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 = 0x03b0 # macro +regSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_BASE_IDX = 0 # macro +regSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 = 0x03b0 # macro +regSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_BASE_IDX = 0 # macro +regSQ_THREAD_TRACE_WORD_WAVE = 0x03b0 # macro +regSQ_THREAD_TRACE_WORD_WAVE_BASE_IDX = 0 # macro +regSQ_THREAD_TRACE_WORD_WAVE_START = 0x03b0 # macro +regSQ_THREAD_TRACE_WORD_WAVE_START_BASE_IDX = 0 # macro +regSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 = 0x03b1 # macro +regSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_BASE_IDX = 0 # macro +regSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 = 0x03b1 # macro +regSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_BASE_IDX = 0 # macro +regSQ_THREAD_TRACE_WORD_PERF_2_OF_2 = 0x03b1 # macro +regSQ_THREAD_TRACE_WORD_PERF_2_OF_2_BASE_IDX = 0 # macro +regSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 = 0x03b1 # macro +regSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_BASE_IDX = 0 # macro +regSQ_WREXEC_EXEC_HI = 0x03b1 # macro +regSQ_WREXEC_EXEC_HI_BASE_IDX = 0 # macro +regSQ_WREXEC_EXEC_LO = 0x03b1 # macro +regSQ_WREXEC_EXEC_LO_BASE_IDX = 0 # macro +regSQ_BUF_RSRC_WORD0 = 0x03c0 # macro +regSQ_BUF_RSRC_WORD0_BASE_IDX = 0 # macro +regSQ_BUF_RSRC_WORD1 = 0x03c1 # macro +regSQ_BUF_RSRC_WORD1_BASE_IDX = 0 # macro +regSQ_BUF_RSRC_WORD2 = 0x03c2 # macro +regSQ_BUF_RSRC_WORD2_BASE_IDX = 0 # macro +regSQ_BUF_RSRC_WORD3 = 0x03c3 # macro +regSQ_BUF_RSRC_WORD3_BASE_IDX = 0 # macro +regSQ_IMG_RSRC_WORD0 = 0x03c4 # macro +regSQ_IMG_RSRC_WORD0_BASE_IDX = 0 # macro +regSQ_IMG_RSRC_WORD1 = 0x03c5 # macro +regSQ_IMG_RSRC_WORD1_BASE_IDX = 0 # macro +regSQ_IMG_RSRC_WORD2 = 0x03c6 # macro +regSQ_IMG_RSRC_WORD2_BASE_IDX = 0 # macro +regSQ_IMG_RSRC_WORD3 = 0x03c7 # macro +regSQ_IMG_RSRC_WORD3_BASE_IDX = 0 # macro +regSQ_IMG_RSRC_WORD4 = 0x03c8 # macro +regSQ_IMG_RSRC_WORD4_BASE_IDX = 0 # macro +regSQ_IMG_RSRC_WORD5 = 0x03c9 # macro +regSQ_IMG_RSRC_WORD5_BASE_IDX = 0 # macro +regSQ_IMG_RSRC_WORD6 = 0x03ca # macro +regSQ_IMG_RSRC_WORD6_BASE_IDX = 0 # macro +regSQ_IMG_RSRC_WORD7 = 0x03cb # macro +regSQ_IMG_RSRC_WORD7_BASE_IDX = 0 # macro +regSQ_IMG_SAMP_WORD0 = 0x03cc # macro +regSQ_IMG_SAMP_WORD0_BASE_IDX = 0 # macro +regSQ_IMG_SAMP_WORD1 = 0x03cd # macro +regSQ_IMG_SAMP_WORD1_BASE_IDX = 0 # macro +regSQ_IMG_SAMP_WORD2 = 0x03ce # macro +regSQ_IMG_SAMP_WORD2_BASE_IDX = 0 # macro +regSQ_IMG_SAMP_WORD3 = 0x03cf # macro +regSQ_IMG_SAMP_WORD3_BASE_IDX = 0 # macro +regSQ_FLAT_SCRATCH_WORD0 = 0x03d0 # macro +regSQ_FLAT_SCRATCH_WORD0_BASE_IDX = 0 # macro +regSQ_FLAT_SCRATCH_WORD1 = 0x03d1 # macro +regSQ_FLAT_SCRATCH_WORD1_BASE_IDX = 0 # macro +regSQ_M0_GPR_IDX_WORD = 0x03d2 # macro +regSQ_M0_GPR_IDX_WORD_BASE_IDX = 0 # macro +regSQC_ICACHE_UTCL1_CNTL1 = 0x03d3 # macro +regSQC_ICACHE_UTCL1_CNTL1_BASE_IDX = 0 # macro +regSQC_ICACHE_UTCL1_CNTL2 = 0x03d4 # macro +regSQC_ICACHE_UTCL1_CNTL2_BASE_IDX = 0 # macro +regSQC_DCACHE_UTCL1_CNTL1 = 0x03d5 # macro +regSQC_DCACHE_UTCL1_CNTL1_BASE_IDX = 0 # macro +regSQC_DCACHE_UTCL1_CNTL2 = 0x03d6 # macro +regSQC_DCACHE_UTCL1_CNTL2_BASE_IDX = 0 # macro +regSQC_ICACHE_UTCL1_STATUS = 0x03d7 # macro +regSQC_ICACHE_UTCL1_STATUS_BASE_IDX = 0 # macro +regSQC_DCACHE_UTCL1_STATUS = 0x03d8 # macro +regSQC_DCACHE_UTCL1_STATUS_BASE_IDX = 0 # macro +regSQC_UE_EDC_LO = 0x03d9 # macro +regSQC_UE_EDC_LO_BASE_IDX = 0 # macro +regSQC_UE_EDC_HI = 0x03da # macro +regSQC_UE_EDC_HI_BASE_IDX = 0 # macro +regSQC_CE_EDC_LO = 0x03db # macro +regSQC_CE_EDC_LO_BASE_IDX = 0 # macro +regSQC_CE_EDC_HI = 0x03dc # macro +regSQC_CE_EDC_HI_BASE_IDX = 0 # macro +regSQ_UE_ERR_STATUS_LO = 0x03dd # macro +regSQ_UE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regSQ_UE_ERR_STATUS_HI = 0x03de # macro +regSQ_UE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regSQ_CE_ERR_STATUS_LO = 0x03df # macro +regSQ_CE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regSQ_CE_ERR_STATUS_HI = 0x03e0 # macro +regSQ_CE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regLDS_UE_ERR_STATUS_LO = 0x03e1 # macro +regLDS_UE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regLDS_UE_ERR_STATUS_HI = 0x03e2 # macro +regLDS_UE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regLDS_CE_ERR_STATUS_LO = 0x03e3 # macro +regLDS_CE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regLDS_CE_ERR_STATUS_HI = 0x03e4 # macro +regLDS_CE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regSP0_UE_ERR_STATUS_LO = 0x03e5 # macro +regSP0_UE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regSP0_UE_ERR_STATUS_HI = 0x03e6 # macro +regSP0_UE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regSP0_CE_ERR_STATUS_LO = 0x03e7 # macro +regSP0_CE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regSP0_CE_ERR_STATUS_HI = 0x03e8 # macro +regSP0_CE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regSP1_UE_ERR_STATUS_LO = 0x03e9 # macro +regSP1_UE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regSP1_UE_ERR_STATUS_HI = 0x03ea # macro +regSP1_UE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regSP1_CE_ERR_STATUS_LO = 0x03eb # macro +regSP1_CE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regSP1_CE_ERR_STATUS_HI = 0x03ec # macro +regSP1_CE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regSX_DEBUG_BUSY = 0x0414 # macro +regSX_DEBUG_BUSY_BASE_IDX = 0 # macro +regSX_DEBUG_1 = 0x0419 # macro +regSX_DEBUG_1_BASE_IDX = 0 # macro +regSPI_PS_MAX_WAVE_ID = 0x043a # macro +regSPI_PS_MAX_WAVE_ID_BASE_IDX = 0 # macro +regSPI_START_PHASE = 0x043b # macro +regSPI_START_PHASE_BASE_IDX = 0 # macro +regSPI_GFX_CNTL = 0x043c # macro +regSPI_GFX_CNTL_BASE_IDX = 0 # macro +regSPI_DEBUG_READ = 0x0442 # macro +regSPI_DEBUG_READ_BASE_IDX = 0 # macro +regSPI_DSM_CNTL = 0x0443 # macro +regSPI_DSM_CNTL_BASE_IDX = 0 # macro +regSPI_DSM_CNTL2 = 0x0444 # macro +regSPI_DSM_CNTL2_BASE_IDX = 0 # macro +regSPI_EDC_CNT = 0x0445 # macro +regSPI_EDC_CNT_BASE_IDX = 0 # macro +regSPI_UE_ERR_STATUS_LO = 0x0446 # macro +regSPI_UE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regSPI_UE_ERR_STATUS_HI = 0x0447 # macro +regSPI_UE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regSPI_CE_ERR_STATUS_LO = 0x0448 # macro +regSPI_CE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regSPI_CE_ERR_STATUS_HI = 0x0449 # macro +regSPI_CE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regSPI_DEBUG_BUSY = 0x0450 # macro +regSPI_DEBUG_BUSY_BASE_IDX = 0 # macro +regSPI_CONFIG_PS_CU_EN = 0x0452 # macro +regSPI_CONFIG_PS_CU_EN_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_CNTL = 0x04aa # macro +regSPI_WF_LIFETIME_CNTL_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_LIMIT_0 = 0x04ab # macro +regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_LIMIT_1 = 0x04ac # macro +regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_LIMIT_2 = 0x04ad # macro +regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_LIMIT_3 = 0x04ae # macro +regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_LIMIT_4 = 0x04af # macro +regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_LIMIT_5 = 0x04b0 # macro +regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_LIMIT_6 = 0x04b1 # macro +regSPI_WF_LIFETIME_LIMIT_6_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_LIMIT_7 = 0x04b2 # macro +regSPI_WF_LIFETIME_LIMIT_7_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_LIMIT_8 = 0x04b3 # macro +regSPI_WF_LIFETIME_LIMIT_8_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_LIMIT_9 = 0x04b4 # macro +regSPI_WF_LIFETIME_LIMIT_9_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_0 = 0x04b5 # macro +regSPI_WF_LIFETIME_STATUS_0_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_1 = 0x04b6 # macro +regSPI_WF_LIFETIME_STATUS_1_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_2 = 0x04b7 # macro +regSPI_WF_LIFETIME_STATUS_2_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_3 = 0x04b8 # macro +regSPI_WF_LIFETIME_STATUS_3_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_4 = 0x04b9 # macro +regSPI_WF_LIFETIME_STATUS_4_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_5 = 0x04ba # macro +regSPI_WF_LIFETIME_STATUS_5_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_6 = 0x04bb # macro +regSPI_WF_LIFETIME_STATUS_6_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_7 = 0x04bc # macro +regSPI_WF_LIFETIME_STATUS_7_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_8 = 0x04bd # macro +regSPI_WF_LIFETIME_STATUS_8_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_9 = 0x04be # macro +regSPI_WF_LIFETIME_STATUS_9_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_10 = 0x04bf # macro +regSPI_WF_LIFETIME_STATUS_10_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_11 = 0x04c0 # macro +regSPI_WF_LIFETIME_STATUS_11_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_12 = 0x04c1 # macro +regSPI_WF_LIFETIME_STATUS_12_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_13 = 0x04c2 # macro +regSPI_WF_LIFETIME_STATUS_13_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_14 = 0x04c3 # macro +regSPI_WF_LIFETIME_STATUS_14_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_15 = 0x04c4 # macro +regSPI_WF_LIFETIME_STATUS_15_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_16 = 0x04c5 # macro +regSPI_WF_LIFETIME_STATUS_16_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_17 = 0x04c6 # macro +regSPI_WF_LIFETIME_STATUS_17_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_18 = 0x04c7 # macro +regSPI_WF_LIFETIME_STATUS_18_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_19 = 0x04c8 # macro +regSPI_WF_LIFETIME_STATUS_19_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_STATUS_20 = 0x04c9 # macro +regSPI_WF_LIFETIME_STATUS_20_BASE_IDX = 0 # macro +regSPI_WF_LIFETIME_DEBUG = 0x04ca # macro +regSPI_WF_LIFETIME_DEBUG_BASE_IDX = 0 # macro +regSPI_LB_CTR_CTRL = 0x04d4 # macro +regSPI_LB_CTR_CTRL_BASE_IDX = 0 # macro +regSPI_LB_CU_MASK = 0x04d5 # macro +regSPI_LB_CU_MASK_BASE_IDX = 0 # macro +regSPI_LB_DATA_REG = 0x04d6 # macro +regSPI_LB_DATA_REG_BASE_IDX = 0 # macro +regSPI_PG_ENABLE_STATIC_CU_MASK = 0x04d7 # macro +regSPI_PG_ENABLE_STATIC_CU_MASK_BASE_IDX = 0 # macro +regSPI_GDS_CREDITS = 0x04d8 # macro +regSPI_GDS_CREDITS_BASE_IDX = 0 # macro +regSPI_SX_EXPORT_BUFFER_SIZES = 0x04d9 # macro +regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX = 0 # macro +regSPI_SX_SCOREBOARD_BUFFER_SIZES = 0x04da # macro +regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX = 0 # macro +regSPI_CSQ_WF_ACTIVE_STATUS = 0x04db # macro +regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX = 0 # macro +regSPI_CSQ_WF_ACTIVE_COUNT_0 = 0x04dc # macro +regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX = 0 # macro +regSPI_CSQ_WF_ACTIVE_COUNT_1 = 0x04dd # macro +regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX = 0 # macro +regSPI_CSQ_WF_ACTIVE_COUNT_2 = 0x04de # macro +regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX = 0 # macro +regSPI_CSQ_WF_ACTIVE_COUNT_3 = 0x04df # macro +regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX = 0 # macro +regSPI_CSQ_WF_ACTIVE_COUNT_4 = 0x04e0 # macro +regSPI_CSQ_WF_ACTIVE_COUNT_4_BASE_IDX = 0 # macro +regSPI_CSQ_WF_ACTIVE_COUNT_5 = 0x04e1 # macro +regSPI_CSQ_WF_ACTIVE_COUNT_5_BASE_IDX = 0 # macro +regSPI_CSQ_WF_ACTIVE_COUNT_6 = 0x04e2 # macro +regSPI_CSQ_WF_ACTIVE_COUNT_6_BASE_IDX = 0 # macro +regSPI_CSQ_WF_ACTIVE_COUNT_7 = 0x04e3 # macro +regSPI_CSQ_WF_ACTIVE_COUNT_7_BASE_IDX = 0 # macro +regSPI_LB_DATA_WAVES = 0x04e4 # macro +regSPI_LB_DATA_WAVES_BASE_IDX = 0 # macro +regSPI_LB_DATA_PERCU_WAVE_HSGS = 0x04e5 # macro +regSPI_LB_DATA_PERCU_WAVE_HSGS_BASE_IDX = 0 # macro +regSPI_LB_DATA_PERCU_WAVE_VSPS = 0x04e6 # macro +regSPI_LB_DATA_PERCU_WAVE_VSPS_BASE_IDX = 0 # macro +regSPI_LB_DATA_PERCU_WAVE_CS = 0x04e7 # macro +regSPI_LB_DATA_PERCU_WAVE_CS_BASE_IDX = 0 # macro +regSPIS_DEBUG_READ = 0x04ea # macro +regSPIS_DEBUG_READ_BASE_IDX = 0 # macro +regBCI_DEBUG_READ = 0x04eb # macro +regBCI_DEBUG_READ_BASE_IDX = 0 # macro +regSPI_P0_TRAP_SCREEN_PSBA_LO = 0x04ec # macro +regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX = 0 # macro +regSPI_P0_TRAP_SCREEN_PSBA_HI = 0x04ed # macro +regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX = 0 # macro +regSPI_P0_TRAP_SCREEN_PSMA_LO = 0x04ee # macro +regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX = 0 # macro +regSPI_P0_TRAP_SCREEN_PSMA_HI = 0x04ef # macro +regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX = 0 # macro +regSPI_P0_TRAP_SCREEN_GPR_MIN = 0x04f0 # macro +regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX = 0 # macro +regSPI_P1_TRAP_SCREEN_PSBA_LO = 0x04f1 # macro +regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX = 0 # macro +regSPI_P1_TRAP_SCREEN_PSBA_HI = 0x04f2 # macro +regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX = 0 # macro +regSPI_P1_TRAP_SCREEN_PSMA_LO = 0x04f3 # macro +regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX = 0 # macro +regSPI_P1_TRAP_SCREEN_PSMA_HI = 0x04f4 # macro +regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX = 0 # macro +regSPI_P1_TRAP_SCREEN_GPR_MIN = 0x04f5 # macro +regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX = 0 # macro +regTD_CNTL = 0x0525 # macro +regTD_CNTL_BASE_IDX = 0 # macro +regTD_STATUS = 0x0526 # macro +regTD_STATUS_BASE_IDX = 0 # macro +regTD_POWER_CNTL = 0x052a # macro +regTD_POWER_CNTL_BASE_IDX = 0 # macro +regTD_UE_EDC_LO = 0x052b # macro +regTD_UE_EDC_LO_BASE_IDX = 0 # macro +regTD_UE_EDC_HI = 0x052c # macro +regTD_UE_EDC_HI_BASE_IDX = 0 # macro +regTD_CE_EDC_LO = 0x052d # macro +regTD_CE_EDC_LO_BASE_IDX = 0 # macro +regTD_CE_EDC_HI = 0x052e # macro +regTD_CE_EDC_HI_BASE_IDX = 0 # macro +regTD_DSM_CNTL = 0x052f # macro +regTD_DSM_CNTL_BASE_IDX = 0 # macro +regTD_DSM_CNTL2 = 0x0530 # macro +regTD_DSM_CNTL2_BASE_IDX = 0 # macro +regTD_SCRATCH = 0x0533 # macro +regTD_SCRATCH_BASE_IDX = 0 # macro +regTA_POWER_CNTL = 0x0540 # macro +regTA_POWER_CNTL_BASE_IDX = 0 # macro +regTA_CNTL = 0x0541 # macro +regTA_CNTL_BASE_IDX = 0 # macro +regTA_CNTL_AUX = 0x0542 # macro +regTA_CNTL_AUX_BASE_IDX = 0 # macro +regTA_FEATURE_CNTL = 0x0543 # macro +regTA_FEATURE_CNTL_BASE_IDX = 0 # macro +regTA_STATUS = 0x0548 # macro +regTA_STATUS_BASE_IDX = 0 # macro +regTA_SCRATCH = 0x0564 # macro +regTA_SCRATCH_BASE_IDX = 0 # macro +regTA_DSM_CNTL = 0x0584 # macro +regTA_DSM_CNTL_BASE_IDX = 0 # macro +regTA_DSM_CNTL2 = 0x0585 # macro +regTA_DSM_CNTL2_BASE_IDX = 0 # macro +regTA_UE_EDC_LO = 0x0587 # macro +regTA_UE_EDC_LO_BASE_IDX = 0 # macro +regTA_UE_EDC_HI = 0x0588 # macro +regTA_UE_EDC_HI_BASE_IDX = 0 # macro +regTA_CE_EDC_LO = 0x0589 # macro +regTA_CE_EDC_LO_BASE_IDX = 0 # macro +regTA_CE_EDC_HI = 0x058a # macro +regTA_CE_EDC_HI_BASE_IDX = 0 # macro +regGDS_CONFIG = 0x05c0 # macro +regGDS_CONFIG_BASE_IDX = 0 # macro +regGDS_CNTL_STATUS = 0x05c1 # macro +regGDS_CNTL_STATUS_BASE_IDX = 0 # macro +regGDS_ENHANCE2 = 0x05c2 # macro +regGDS_ENHANCE2_BASE_IDX = 0 # macro +regGDS_PROTECTION_FAULT = 0x05c3 # macro +regGDS_PROTECTION_FAULT_BASE_IDX = 0 # macro +regGDS_VM_PROTECTION_FAULT = 0x05c4 # macro +regGDS_VM_PROTECTION_FAULT_BASE_IDX = 0 # macro +regGDS_EDC_CNT = 0x05c5 # macro +regGDS_EDC_CNT_BASE_IDX = 0 # macro +regGDS_EDC_GRBM_CNT = 0x05c6 # macro +regGDS_EDC_GRBM_CNT_BASE_IDX = 0 # macro +regGDS_EDC_OA_DED = 0x05c7 # macro +regGDS_EDC_OA_DED_BASE_IDX = 0 # macro +regGDS_DSM_CNTL = 0x05ca # macro +regGDS_DSM_CNTL_BASE_IDX = 0 # macro +regGDS_EDC_OA_PHY_CNT = 0x05cb # macro +regGDS_EDC_OA_PHY_CNT_BASE_IDX = 0 # macro +regGDS_EDC_OA_PIPE_CNT = 0x05cc # macro +regGDS_EDC_OA_PIPE_CNT_BASE_IDX = 0 # macro +regGDS_DSM_CNTL2 = 0x05cd # macro +regGDS_DSM_CNTL2_BASE_IDX = 0 # macro +regGDS_WD_GDS_CSB = 0x05ce # macro +regGDS_WD_GDS_CSB_BASE_IDX = 0 # macro +regGDS_UE_ERR_STATUS_LO = 0x05cf # macro +regGDS_UE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regGDS_UE_ERR_STATUS_HI = 0x05d0 # macro +regGDS_UE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regGDS_CE_ERR_STATUS_LO = 0x05d1 # macro +regGDS_CE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regGDS_CE_ERR_STATUS_HI = 0x05d2 # macro +regGDS_CE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regDB_DEBUG = 0x060c # macro +regDB_DEBUG_BASE_IDX = 0 # macro +regDB_DEBUG2 = 0x060d # macro +regDB_DEBUG2_BASE_IDX = 0 # macro +regDB_DEBUG3 = 0x060e # macro +regDB_DEBUG3_BASE_IDX = 0 # macro +regDB_DEBUG4 = 0x060f # macro +regDB_DEBUG4_BASE_IDX = 0 # macro +regDB_CREDIT_LIMIT = 0x0614 # macro +regDB_CREDIT_LIMIT_BASE_IDX = 0 # macro +regDB_WATERMARKS = 0x0615 # macro +regDB_WATERMARKS_BASE_IDX = 0 # macro +regDB_SUBTILE_CONTROL = 0x0616 # macro +regDB_SUBTILE_CONTROL_BASE_IDX = 0 # macro +regDB_FREE_CACHELINES = 0x0617 # macro +regDB_FREE_CACHELINES_BASE_IDX = 0 # macro +regDB_FIFO_DEPTH1 = 0x0618 # macro +regDB_FIFO_DEPTH1_BASE_IDX = 0 # macro +regDB_FIFO_DEPTH2 = 0x0619 # macro +regDB_FIFO_DEPTH2_BASE_IDX = 0 # macro +regDB_EXCEPTION_CONTROL = 0x061a # macro +regDB_EXCEPTION_CONTROL_BASE_IDX = 0 # macro +regDB_RING_CONTROL = 0x061b # macro +regDB_RING_CONTROL_BASE_IDX = 0 # macro +regDB_MEM_ARB_WATERMARKS = 0x061c # macro +regDB_MEM_ARB_WATERMARKS_BASE_IDX = 0 # macro +regDB_RMI_CACHE_POLICY = 0x061e # macro +regDB_RMI_CACHE_POLICY_BASE_IDX = 0 # macro +regDB_DFSM_CONFIG = 0x0630 # macro +regDB_DFSM_CONFIG_BASE_IDX = 0 # macro +regDB_DFSM_WATERMARK = 0x0631 # macro +regDB_DFSM_WATERMARK_BASE_IDX = 0 # macro +regDB_DFSM_TILES_IN_FLIGHT = 0x0632 # macro +regDB_DFSM_TILES_IN_FLIGHT_BASE_IDX = 0 # macro +regDB_DFSM_PRIMS_IN_FLIGHT = 0x0633 # macro +regDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX = 0 # macro +regDB_DFSM_WATCHDOG = 0x0634 # macro +regDB_DFSM_WATCHDOG_BASE_IDX = 0 # macro +regDB_DFSM_FLUSH_ENABLE = 0x0635 # macro +regDB_DFSM_FLUSH_ENABLE_BASE_IDX = 0 # macro +regDB_DFSM_FLUSH_AUX_EVENT = 0x0636 # macro +regDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX = 0 # macro +regCC_RB_REDUNDANCY = 0x063c # macro +regCC_RB_REDUNDANCY_BASE_IDX = 0 # macro +regCC_RB_BACKEND_DISABLE = 0x063d # macro +regCC_RB_BACKEND_DISABLE_BASE_IDX = 0 # macro +regGB_ADDR_CONFIG = 0x063e # macro +regGB_ADDR_CONFIG_BASE_IDX = 0 # macro +regGB_BACKEND_MAP = 0x063f # macro +regGB_BACKEND_MAP_BASE_IDX = 0 # macro +regGB_GPU_ID = 0x0640 # macro +regGB_GPU_ID_BASE_IDX = 0 # macro +regCC_RB_DAISY_CHAIN = 0x0641 # macro +regCC_RB_DAISY_CHAIN_BASE_IDX = 0 # macro +regGB_ADDR_CONFIG_READ = 0x0642 # macro +regGB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro +regGB_TILE_MODE0 = 0x0644 # macro +regGB_TILE_MODE0_BASE_IDX = 0 # macro +regGB_TILE_MODE1 = 0x0645 # macro +regGB_TILE_MODE1_BASE_IDX = 0 # macro +regGB_TILE_MODE2 = 0x0646 # macro +regGB_TILE_MODE2_BASE_IDX = 0 # macro +regGB_TILE_MODE3 = 0x0647 # macro +regGB_TILE_MODE3_BASE_IDX = 0 # macro +regGB_TILE_MODE4 = 0x0648 # macro +regGB_TILE_MODE4_BASE_IDX = 0 # macro +regGB_TILE_MODE5 = 0x0649 # macro +regGB_TILE_MODE5_BASE_IDX = 0 # macro +regGB_TILE_MODE6 = 0x064a # macro +regGB_TILE_MODE6_BASE_IDX = 0 # macro +regGB_TILE_MODE7 = 0x064b # macro +regGB_TILE_MODE7_BASE_IDX = 0 # macro +regGB_TILE_MODE8 = 0x064c # macro +regGB_TILE_MODE8_BASE_IDX = 0 # macro +regGB_TILE_MODE9 = 0x064d # macro +regGB_TILE_MODE9_BASE_IDX = 0 # macro +regGB_TILE_MODE10 = 0x064e # macro +regGB_TILE_MODE10_BASE_IDX = 0 # macro +regGB_TILE_MODE11 = 0x064f # macro +regGB_TILE_MODE11_BASE_IDX = 0 # macro +regGB_TILE_MODE12 = 0x0650 # macro +regGB_TILE_MODE12_BASE_IDX = 0 # macro +regGB_TILE_MODE13 = 0x0651 # macro +regGB_TILE_MODE13_BASE_IDX = 0 # macro +regGB_TILE_MODE14 = 0x0652 # macro +regGB_TILE_MODE14_BASE_IDX = 0 # macro +regGB_TILE_MODE15 = 0x0653 # macro +regGB_TILE_MODE15_BASE_IDX = 0 # macro +regGB_TILE_MODE16 = 0x0654 # macro +regGB_TILE_MODE16_BASE_IDX = 0 # macro +regGB_TILE_MODE17 = 0x0655 # macro +regGB_TILE_MODE17_BASE_IDX = 0 # macro +regGB_TILE_MODE18 = 0x0656 # macro +regGB_TILE_MODE18_BASE_IDX = 0 # macro +regGB_TILE_MODE19 = 0x0657 # macro +regGB_TILE_MODE19_BASE_IDX = 0 # macro +regGB_TILE_MODE20 = 0x0658 # macro +regGB_TILE_MODE20_BASE_IDX = 0 # macro +regGB_TILE_MODE21 = 0x0659 # macro +regGB_TILE_MODE21_BASE_IDX = 0 # macro +regGB_TILE_MODE22 = 0x065a # macro +regGB_TILE_MODE22_BASE_IDX = 0 # macro +regGB_TILE_MODE23 = 0x065b # macro +regGB_TILE_MODE23_BASE_IDX = 0 # macro +regGB_TILE_MODE24 = 0x065c # macro +regGB_TILE_MODE24_BASE_IDX = 0 # macro +regGB_TILE_MODE25 = 0x065d # macro +regGB_TILE_MODE25_BASE_IDX = 0 # macro +regGB_TILE_MODE26 = 0x065e # macro +regGB_TILE_MODE26_BASE_IDX = 0 # macro +regGB_TILE_MODE27 = 0x065f # macro +regGB_TILE_MODE27_BASE_IDX = 0 # macro +regGB_TILE_MODE28 = 0x0660 # macro +regGB_TILE_MODE28_BASE_IDX = 0 # macro +regGB_TILE_MODE29 = 0x0661 # macro +regGB_TILE_MODE29_BASE_IDX = 0 # macro +regGB_TILE_MODE30 = 0x0662 # macro +regGB_TILE_MODE30_BASE_IDX = 0 # macro +regGB_TILE_MODE31 = 0x0663 # macro +regGB_TILE_MODE31_BASE_IDX = 0 # macro +regGB_MACROTILE_MODE0 = 0x0664 # macro +regGB_MACROTILE_MODE0_BASE_IDX = 0 # macro +regGB_MACROTILE_MODE1 = 0x0665 # macro +regGB_MACROTILE_MODE1_BASE_IDX = 0 # macro +regGB_MACROTILE_MODE2 = 0x0666 # macro +regGB_MACROTILE_MODE2_BASE_IDX = 0 # macro +regGB_MACROTILE_MODE3 = 0x0667 # macro +regGB_MACROTILE_MODE3_BASE_IDX = 0 # macro +regGB_MACROTILE_MODE4 = 0x0668 # macro +regGB_MACROTILE_MODE4_BASE_IDX = 0 # macro +regGB_MACROTILE_MODE5 = 0x0669 # macro +regGB_MACROTILE_MODE5_BASE_IDX = 0 # macro +regGB_MACROTILE_MODE6 = 0x066a # macro +regGB_MACROTILE_MODE6_BASE_IDX = 0 # macro +regGB_MACROTILE_MODE7 = 0x066b # macro +regGB_MACROTILE_MODE7_BASE_IDX = 0 # macro +regGB_MACROTILE_MODE8 = 0x066c # macro +regGB_MACROTILE_MODE8_BASE_IDX = 0 # macro +regGB_MACROTILE_MODE9 = 0x066d # macro +regGB_MACROTILE_MODE9_BASE_IDX = 0 # macro +regGB_MACROTILE_MODE10 = 0x066e # macro +regGB_MACROTILE_MODE10_BASE_IDX = 0 # macro +regGB_MACROTILE_MODE11 = 0x066f # macro +regGB_MACROTILE_MODE11_BASE_IDX = 0 # macro +regGB_MACROTILE_MODE12 = 0x0670 # macro +regGB_MACROTILE_MODE12_BASE_IDX = 0 # macro +regGB_MACROTILE_MODE13 = 0x0671 # macro +regGB_MACROTILE_MODE13_BASE_IDX = 0 # macro +regGB_MACROTILE_MODE14 = 0x0672 # macro +regGB_MACROTILE_MODE14_BASE_IDX = 0 # macro +regGB_MACROTILE_MODE15 = 0x0673 # macro +regGB_MACROTILE_MODE15_BASE_IDX = 0 # macro +regCB_HW_CONTROL = 0x0680 # macro +regCB_HW_CONTROL_BASE_IDX = 0 # macro +regCB_HW_CONTROL_1 = 0x0681 # macro +regCB_HW_CONTROL_1_BASE_IDX = 0 # macro +regCB_HW_CONTROL_2 = 0x0682 # macro +regCB_HW_CONTROL_2_BASE_IDX = 0 # macro +regCB_HW_CONTROL_3 = 0x0683 # macro +regCB_HW_CONTROL_3_BASE_IDX = 0 # macro +regCB_HW_MEM_ARBITER_RD = 0x0686 # macro +regCB_HW_MEM_ARBITER_RD_BASE_IDX = 0 # macro +regCB_HW_MEM_ARBITER_WR = 0x0687 # macro +regCB_HW_MEM_ARBITER_WR_BASE_IDX = 0 # macro +regCB_DCC_CONFIG = 0x0688 # macro +regCB_DCC_CONFIG_BASE_IDX = 0 # macro +regGC_USER_RB_REDUNDANCY = 0x06de # macro +regGC_USER_RB_REDUNDANCY_BASE_IDX = 0 # macro +regGC_USER_RB_BACKEND_DISABLE = 0x06df # macro +regGC_USER_RB_BACKEND_DISABLE_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_CLI2GRP_MAP0 = 0x0a00 # macro +regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_CLI2GRP_MAP1 = 0x0a01 # macro +regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_CLI2GRP_MAP0 = 0x0a02 # macro +regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_CLI2GRP_MAP1 = 0x0a03 # macro +regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_GRP2VC_MAP = 0x0a04 # macro +regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_GRP2VC_MAP = 0x0a05 # macro +regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_LAZY = 0x0a06 # macro +regGCEA_DRAM_RD_LAZY_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_LAZY = 0x0a07 # macro +regGCEA_DRAM_WR_LAZY_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_CAM_CNTL = 0x0a08 # macro +regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_CAM_CNTL = 0x0a09 # macro +regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX = 0 # macro +regGCEA_DRAM_PAGE_BURST = 0x0a0a # macro +regGCEA_DRAM_PAGE_BURST_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_PRI_AGE = 0x0a0b # macro +regGCEA_DRAM_RD_PRI_AGE_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_PRI_AGE = 0x0a0c # macro +regGCEA_DRAM_WR_PRI_AGE_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_PRI_QUEUING = 0x0a0d # macro +regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_PRI_QUEUING = 0x0a0e # macro +regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_PRI_FIXED = 0x0a0f # macro +regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_PRI_FIXED = 0x0a10 # macro +regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_PRI_URGENCY = 0x0a11 # macro +regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_PRI_URGENCY = 0x0a12 # macro +regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_PRI_QUANT_PRI1 = 0x0a13 # macro +regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_PRI_QUANT_PRI2 = 0x0a14 # macro +regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX = 0 # macro +regGCEA_DRAM_RD_PRI_QUANT_PRI3 = 0x0a15 # macro +regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_PRI_QUANT_PRI1 = 0x0a16 # macro +regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_PRI_QUANT_PRI2 = 0x0a17 # macro +regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX = 0 # macro +regGCEA_DRAM_WR_PRI_QUANT_PRI3 = 0x0a18 # macro +regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX = 0 # macro +regGCEA_IO_RD_CLI2GRP_MAP0 = 0x0ad5 # macro +regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX = 0 # macro +regGCEA_IO_RD_CLI2GRP_MAP1 = 0x0ad6 # macro +regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX = 0 # macro +regGCEA_IO_WR_CLI2GRP_MAP0 = 0x0ad7 # macro +regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX = 0 # macro +regGCEA_IO_WR_CLI2GRP_MAP1 = 0x0ad8 # macro +regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX = 0 # macro +regGCEA_IO_RD_COMBINE_FLUSH = 0x0ad9 # macro +regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX = 0 # macro +regGCEA_IO_WR_COMBINE_FLUSH = 0x0ada # macro +regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX = 0 # macro +regGCEA_IO_GROUP_BURST = 0x0adb # macro +regGCEA_IO_GROUP_BURST_BASE_IDX = 0 # macro +regGCEA_IO_RD_PRI_AGE = 0x0adc # macro +regGCEA_IO_RD_PRI_AGE_BASE_IDX = 0 # macro +regGCEA_IO_WR_PRI_AGE = 0x0add # macro +regGCEA_IO_WR_PRI_AGE_BASE_IDX = 0 # macro +regGCEA_IO_RD_PRI_QUEUING = 0x0ade # macro +regGCEA_IO_RD_PRI_QUEUING_BASE_IDX = 0 # macro +regGCEA_IO_WR_PRI_QUEUING = 0x0adf # macro +regGCEA_IO_WR_PRI_QUEUING_BASE_IDX = 0 # macro +regGCEA_IO_RD_PRI_FIXED = 0x0ae0 # macro +regGCEA_IO_RD_PRI_FIXED_BASE_IDX = 0 # macro +regGCEA_IO_WR_PRI_FIXED = 0x0ae1 # macro +regGCEA_IO_WR_PRI_FIXED_BASE_IDX = 0 # macro +regGCEA_IO_RD_PRI_URGENCY = 0x0ae2 # macro +regGCEA_IO_RD_PRI_URGENCY_BASE_IDX = 0 # macro +regGCEA_IO_WR_PRI_URGENCY = 0x0ae3 # macro +regGCEA_IO_WR_PRI_URGENCY_BASE_IDX = 0 # macro +regGCEA_IO_RD_PRI_URGENCY_MASKING = 0x0ae4 # macro +regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX = 0 # macro +regGCEA_IO_WR_PRI_URGENCY_MASKING = 0x0ae5 # macro +regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX = 0 # macro +regGCEA_IO_RD_PRI_QUANT_PRI1 = 0x0ae6 # macro +regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX = 0 # macro +regGCEA_IO_RD_PRI_QUANT_PRI2 = 0x0ae7 # macro +regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX = 0 # macro +regGCEA_IO_RD_PRI_QUANT_PRI3 = 0x0ae8 # macro +regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX = 0 # macro +regGCEA_IO_WR_PRI_QUANT_PRI1 = 0x0ae9 # macro +regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX = 0 # macro +regGCEA_IO_WR_PRI_QUANT_PRI2 = 0x0aea # macro +regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX = 0 # macro +regGCEA_IO_WR_PRI_QUANT_PRI3 = 0x0aeb # macro +regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX = 0 # macro +regGCEA_SDP_ARB_DRAM = 0x0aec # macro +regGCEA_SDP_ARB_DRAM_BASE_IDX = 0 # macro +regGCEA_SDP_ARB_FINAL = 0x0aee # macro +regGCEA_SDP_ARB_FINAL_BASE_IDX = 0 # macro +regGCEA_SDP_DRAM_PRIORITY = 0x0aef # macro +regGCEA_SDP_DRAM_PRIORITY_BASE_IDX = 0 # macro +regGCEA_SDP_IO_PRIORITY = 0x0af1 # macro +regGCEA_SDP_IO_PRIORITY_BASE_IDX = 0 # macro +regGCEA_SDP_CREDITS = 0x0af2 # macro +regGCEA_SDP_CREDITS_BASE_IDX = 0 # macro +regGCEA_SDP_TAG_RESERVE0 = 0x0af3 # macro +regGCEA_SDP_TAG_RESERVE0_BASE_IDX = 0 # macro +regGCEA_SDP_TAG_RESERVE1 = 0x0af4 # macro +regGCEA_SDP_TAG_RESERVE1_BASE_IDX = 0 # macro +regGCEA_SDP_VCC_RESERVE0 = 0x0af5 # macro +regGCEA_SDP_VCC_RESERVE0_BASE_IDX = 0 # macro +regGCEA_SDP_VCC_RESERVE1 = 0x0af6 # macro +regGCEA_SDP_VCC_RESERVE1_BASE_IDX = 0 # macro +regGCEA_SDP_VCD_RESERVE0 = 0x0af7 # macro +regGCEA_SDP_VCD_RESERVE0_BASE_IDX = 0 # macro +regGCEA_SDP_VCD_RESERVE1 = 0x0af8 # macro +regGCEA_SDP_VCD_RESERVE1_BASE_IDX = 0 # macro +regGCEA_SDP_REQ_CNTL = 0x0af9 # macro +regGCEA_SDP_REQ_CNTL_BASE_IDX = 0 # macro +regGCEA_MISC = 0x0afa # macro +regGCEA_MISC_BASE_IDX = 0 # macro +regGCEA_LATENCY_SAMPLING = 0x0afb # macro +regGCEA_LATENCY_SAMPLING_BASE_IDX = 0 # macro +regGCEA_PERFCOUNTER_LO = 0x0afc # macro +regGCEA_PERFCOUNTER_LO_BASE_IDX = 0 # macro +regGCEA_PERFCOUNTER_HI = 0x0afd # macro +regGCEA_PERFCOUNTER_HI_BASE_IDX = 0 # macro +regGCEA_PERFCOUNTER0_CFG = 0x0afe # macro +regGCEA_PERFCOUNTER0_CFG_BASE_IDX = 0 # macro +regGCEA_PERFCOUNTER1_CFG = 0x0aff # macro +regGCEA_PERFCOUNTER1_CFG_BASE_IDX = 0 # macro +regGCEA_PERFCOUNTER_RSLT_CNTL = 0x0700 # macro +regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 0 # macro +regGCEA_MAM_CTRL = 0x0701 # macro +regGCEA_MAM_CTRL_BASE_IDX = 0 # macro +regGCEA_MAM_CTRL2 = 0x0702 # macro +regGCEA_MAM_CTRL2_BASE_IDX = 0 # macro +regGCEA_UE_ERR_STATUS_LO = 0x0706 # macro +regGCEA_UE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regGCEA_UE_ERR_STATUS_HI = 0x0707 # macro +regGCEA_UE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regGCEA_DSM_CNTL = 0x0708 # macro +regGCEA_DSM_CNTL_BASE_IDX = 0 # macro +regGCEA_DSM_CNTLA = 0x0709 # macro +regGCEA_DSM_CNTLA_BASE_IDX = 0 # macro +regGCEA_DSM_CNTLB = 0x070a # macro +regGCEA_DSM_CNTLB_BASE_IDX = 0 # macro +regGCEA_DSM_CNTL2 = 0x070b # macro +regGCEA_DSM_CNTL2_BASE_IDX = 0 # macro +regGCEA_DSM_CNTL2A = 0x070c # macro +regGCEA_DSM_CNTL2A_BASE_IDX = 0 # macro +regGCEA_DSM_CNTL2B = 0x070d # macro +regGCEA_DSM_CNTL2B_BASE_IDX = 0 # macro +regGCEA_TCC_XBR_CREDITS = 0x070e # macro +regGCEA_TCC_XBR_CREDITS_BASE_IDX = 0 # macro +regGCEA_TCC_XBR_MAXBURST = 0x070f # macro +regGCEA_TCC_XBR_MAXBURST_BASE_IDX = 0 # macro +regGCEA_PROBE_CNTL = 0x0710 # macro +regGCEA_PROBE_CNTL_BASE_IDX = 0 # macro +regGCEA_PROBE_MAP = 0x0711 # macro +regGCEA_PROBE_MAP_BASE_IDX = 0 # macro +regGCEA_ERR_STATUS = 0x0712 # macro +regGCEA_ERR_STATUS_BASE_IDX = 0 # macro +regGCEA_MISC2 = 0x0713 # macro +regGCEA_MISC2_BASE_IDX = 0 # macro +regGCEA_SDP_BACKDOOR_CMDCREDITS0 = 0x0715 # macro +regGCEA_SDP_BACKDOOR_CMDCREDITS0_BASE_IDX = 0 # macro +regGCEA_SDP_BACKDOOR_CMDCREDITS1 = 0x0716 # macro +regGCEA_SDP_BACKDOOR_CMDCREDITS1_BASE_IDX = 0 # macro +regGCEA_SDP_BACKDOOR_DATACREDITS0 = 0x0717 # macro +regGCEA_SDP_BACKDOOR_DATACREDITS0_BASE_IDX = 0 # macro +regGCEA_SDP_BACKDOOR_DATACREDITS1 = 0x0718 # macro +regGCEA_SDP_BACKDOOR_DATACREDITS1_BASE_IDX = 0 # macro +regGCEA_SDP_BACKDOOR_MISCCREDITS = 0x0719 # macro +regGCEA_SDP_BACKDOOR_MISCCREDITS_BASE_IDX = 0 # macro +regGCEA_CE_ERR_STATUS_LO = 0x071b # macro +regGCEA_CE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regGCEA_CE_ERR_STATUS_HI = 0x071d # macro +regGCEA_CE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regGCEA_SDP_ENABLE = 0x071f # macro +regGCEA_SDP_ENABLE_BASE_IDX = 0 # macro +regGCEA_ICG_CTRL = 0x50c4 # macro +regGCEA_ICG_CTRL_BASE_IDX = 1 # macro +regRMI_GENERAL_CNTL = 0x0780 # macro +regRMI_GENERAL_CNTL_BASE_IDX = 0 # macro +regRMI_GENERAL_CNTL1 = 0x0781 # macro +regRMI_GENERAL_CNTL1_BASE_IDX = 0 # macro +regRMI_GENERAL_STATUS = 0x0782 # macro +regRMI_GENERAL_STATUS_BASE_IDX = 0 # macro +regRMI_SUBBLOCK_STATUS0 = 0x0783 # macro +regRMI_SUBBLOCK_STATUS0_BASE_IDX = 0 # macro +regRMI_SUBBLOCK_STATUS1 = 0x0784 # macro +regRMI_SUBBLOCK_STATUS1_BASE_IDX = 0 # macro +regRMI_SUBBLOCK_STATUS2 = 0x0785 # macro +regRMI_SUBBLOCK_STATUS2_BASE_IDX = 0 # macro +regRMI_SUBBLOCK_STATUS3 = 0x0786 # macro +regRMI_SUBBLOCK_STATUS3_BASE_IDX = 0 # macro +regRMI_XBAR_CONFIG = 0x0787 # macro +regRMI_XBAR_CONFIG_BASE_IDX = 0 # macro +regRMI_PROBE_POP_LOGIC_CNTL = 0x0788 # macro +regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX = 0 # macro +regRMI_UTC_XNACK_N_MISC_CNTL = 0x0789 # macro +regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX = 0 # macro +regRMI_DEMUX_CNTL = 0x078a # macro +regRMI_DEMUX_CNTL_BASE_IDX = 0 # macro +regRMI_UTCL1_CNTL1 = 0x078b # macro +regRMI_UTCL1_CNTL1_BASE_IDX = 0 # macro +regRMI_UTCL1_CNTL2 = 0x078c # macro +regRMI_UTCL1_CNTL2_BASE_IDX = 0 # macro +regRMI_UTC_UNIT_CONFIG = 0x078d # macro +regRMI_UTC_UNIT_CONFIG_BASE_IDX = 0 # macro +regRMI_TCIW_FORMATTER0_CNTL = 0x078e # macro +regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX = 0 # macro +regRMI_TCIW_FORMATTER1_CNTL = 0x078f # macro +regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX = 0 # macro +regRMI_SCOREBOARD_CNTL = 0x0790 # macro +regRMI_SCOREBOARD_CNTL_BASE_IDX = 0 # macro +regRMI_SCOREBOARD_STATUS0 = 0x0791 # macro +regRMI_SCOREBOARD_STATUS0_BASE_IDX = 0 # macro +regRMI_SCOREBOARD_STATUS1 = 0x0792 # macro +regRMI_SCOREBOARD_STATUS1_BASE_IDX = 0 # macro +regRMI_SCOREBOARD_STATUS2 = 0x0793 # macro +regRMI_SCOREBOARD_STATUS2_BASE_IDX = 0 # macro +regRMI_XBAR_ARBITER_CONFIG = 0x0794 # macro +regRMI_XBAR_ARBITER_CONFIG_BASE_IDX = 0 # macro +regRMI_XBAR_ARBITER_CONFIG_1 = 0x0795 # macro +regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX = 0 # macro +regRMI_CLOCK_CNTRL = 0x0796 # macro +regRMI_CLOCK_CNTRL_BASE_IDX = 0 # macro +regRMI_UTCL1_STATUS = 0x0797 # macro +regRMI_UTCL1_STATUS_BASE_IDX = 0 # macro +regRMI_XNACK_DEBUG = 0x079d # macro +regRMI_XNACK_DEBUG_BASE_IDX = 0 # macro +regRMI_SPARE = 0x079e # macro +regRMI_SPARE_BASE_IDX = 0 # macro +regRMI_SPARE_1 = 0x079f # macro +regRMI_SPARE_1_BASE_IDX = 0 # macro +regRMI_SPARE_2 = 0x07a0 # macro +regRMI_SPARE_2_BASE_IDX = 0 # macro +regATC_L2_CNTL = 0x0800 # macro +regATC_L2_CNTL_BASE_IDX = 0 # macro +regATC_L2_CNTL2 = 0x0801 # macro +regATC_L2_CNTL2_BASE_IDX = 0 # macro +regATC_L2_CACHE_DATA0 = 0x0804 # macro +regATC_L2_CACHE_DATA0_BASE_IDX = 0 # macro +regATC_L2_CACHE_DATA1 = 0x0805 # macro +regATC_L2_CACHE_DATA1_BASE_IDX = 0 # macro +regATC_L2_CACHE_DATA2 = 0x0806 # macro +regATC_L2_CACHE_DATA2_BASE_IDX = 0 # macro +regATC_L2_CACHE_DATA3 = 0x0807 # macro +regATC_L2_CACHE_DATA3_BASE_IDX = 0 # macro +regATC_L2_CNTL3 = 0x0808 # macro +regATC_L2_CNTL3_BASE_IDX = 0 # macro +regATC_L2_STATUS = 0x0809 # macro +regATC_L2_STATUS_BASE_IDX = 0 # macro +regATC_L2_STATUS2 = 0x080a # macro +regATC_L2_STATUS2_BASE_IDX = 0 # macro +regATC_L2_MISC_CG = 0x080b # macro +regATC_L2_MISC_CG_BASE_IDX = 0 # macro +regATC_L2_MEM_POWER_LS = 0x080c # macro +regATC_L2_MEM_POWER_LS_BASE_IDX = 0 # macro +regATC_L2_CGTT_CLK_CTRL = 0x080d # macro +regATC_L2_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regATC_L2_CACHE_4K_DSM_INDEX = 0x080f # macro +regATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX = 0 # macro +regATC_L2_CACHE_32K_DSM_INDEX = 0x0810 # macro +regATC_L2_CACHE_32K_DSM_INDEX_BASE_IDX = 0 # macro +regATC_L2_CACHE_2M_DSM_INDEX = 0x0811 # macro +regATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX = 0 # macro +regATC_L2_CACHE_4K_DSM_CNTL = 0x0812 # macro +regATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX = 0 # macro +regATC_L2_CACHE_32K_DSM_CNTL = 0x0813 # macro +regATC_L2_CACHE_32K_DSM_CNTL_BASE_IDX = 0 # macro +regATC_L2_CACHE_2M_DSM_CNTL = 0x0814 # macro +regATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX = 0 # macro +regATC_L2_CNTL4 = 0x0815 # macro +regATC_L2_CNTL4_BASE_IDX = 0 # macro +regATC_L2_MM_GROUP_RT_CLASSES = 0x0816 # macro +regATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX = 0 # macro +regATC_L2_UE_ERR_STATUS_LO = 0x081a # macro +regATC_L2_UE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regATC_L2_UE_ERR_STATUS_HI = 0x081b # macro +regATC_L2_UE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regATC_L2_CE_ERR_STATUS_LO = 0x081c # macro +regATC_L2_CE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regATC_L2_CE_ERR_STATUS_HI = 0x081d # macro +regATC_L2_CE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regVM_L2_CNTL = 0x0820 # macro +regVM_L2_CNTL_BASE_IDX = 0 # macro +regVM_L2_CNTL2 = 0x0821 # macro +regVM_L2_CNTL2_BASE_IDX = 0 # macro +regVM_L2_CNTL3 = 0x0822 # macro +regVM_L2_CNTL3_BASE_IDX = 0 # macro +regVM_L2_STATUS = 0x0823 # macro +regVM_L2_STATUS_BASE_IDX = 0 # macro +regVM_DUMMY_PAGE_FAULT_CNTL = 0x0824 # macro +regVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX = 0 # macro +regVM_DUMMY_PAGE_FAULT_ADDR_LO32 = 0x0825 # macro +regVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX = 0 # macro +regVM_DUMMY_PAGE_FAULT_ADDR_HI32 = 0x0826 # macro +regVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX = 0 # macro +regVM_L2_PROTECTION_FAULT_CNTL = 0x0827 # macro +regVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX = 0 # macro +regVM_L2_PROTECTION_FAULT_CNTL2 = 0x0828 # macro +regVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX = 0 # macro +regVM_L2_PROTECTION_FAULT_MM_CNTL3 = 0x0829 # macro +regVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX = 0 # macro +regVM_L2_PROTECTION_FAULT_MM_CNTL4 = 0x082a # macro +regVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX = 0 # macro +regVM_L2_PROTECTION_FAULT_STATUS = 0x082b # macro +regVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX = 0 # macro +regVM_L2_PROTECTION_FAULT_ADDR_LO32 = 0x082c # macro +regVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX = 0 # macro +regVM_L2_PROTECTION_FAULT_ADDR_HI32 = 0x082d # macro +regVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX = 0 # macro +regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 = 0x082e # macro +regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX = 0 # macro +regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 = 0x082f # macro +regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX = 0 # macro +regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 = 0x0831 # macro +regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX = 0 # macro +regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 = 0x0832 # macro +regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX = 0 # macro +regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 = 0x0833 # macro +regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX = 0 # macro +regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 = 0x0834 # macro +regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX = 0 # macro +regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 = 0x0835 # macro +regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX = 0 # macro +regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 = 0x0836 # macro +regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX = 0 # macro +regVM_L2_CNTL4 = 0x0837 # macro +regVM_L2_CNTL4_BASE_IDX = 0 # macro +regVM_L2_CNTL5 = 0x0838 # macro +regVM_L2_CNTL5_BASE_IDX = 0 # macro +regVM_L2_MM_GROUP_RT_CLASSES = 0x0839 # macro +regVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX = 0 # macro +regVM_L2_BANK_SELECT_RESERVED_CID = 0x083a # macro +regVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX = 0 # macro +regVM_L2_BANK_SELECT_RESERVED_CID2 = 0x083b # macro +regVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX = 0 # macro +regVM_L2_CACHE_PARITY_CNTL = 0x083c # macro +regVM_L2_CACHE_PARITY_CNTL_BASE_IDX = 0 # macro +regVM_L2_CGTT_CLK_CTRL = 0x083d # macro +regVM_L2_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regVM_L2_CGTT_BUSY_CTRL = 0x083e # macro +regVM_L2_CGTT_BUSY_CTRL_BASE_IDX = 0 # macro +regVML2_MEM_ECC_INDEX = 0x0842 # macro +regVML2_MEM_ECC_INDEX_BASE_IDX = 0 # macro +regVML2_WALKER_MEM_ECC_INDEX = 0x0843 # macro +regVML2_WALKER_MEM_ECC_INDEX_BASE_IDX = 0 # macro +regUTCL2_MEM_ECC_INDEX = 0x0844 # macro +regUTCL2_MEM_ECC_INDEX_BASE_IDX = 0 # macro +regVML2_MEM_ECC_CNTL = 0x0845 # macro +regVML2_MEM_ECC_CNTL_BASE_IDX = 0 # macro +regVML2_WALKER_MEM_ECC_CNTL = 0x0846 # macro +regVML2_WALKER_MEM_ECC_CNTL_BASE_IDX = 0 # macro +regUTCL2_MEM_ECC_CNTL = 0x0847 # macro +regUTCL2_MEM_ECC_CNTL_BASE_IDX = 0 # macro +regVML2_MEM_ECC_STATUS = 0x0848 # macro +regVML2_MEM_ECC_STATUS_BASE_IDX = 0 # macro +regVML2_WALKER_MEM_ECC_STATUS = 0x0849 # macro +regVML2_WALKER_MEM_ECC_STATUS_BASE_IDX = 0 # macro +regUTCL2_MEM_ECC_STATUS = 0x084a # macro +regUTCL2_MEM_ECC_STATUS_BASE_IDX = 0 # macro +regUTCL2_EDC_MODE = 0x084b # macro +regUTCL2_EDC_MODE_BASE_IDX = 0 # macro +regUTCL2_EDC_CONFIG = 0x084c # macro +regUTCL2_EDC_CONFIG_BASE_IDX = 0 # macro +regVML2_UE_ERR_STATUS_LO = 0x084d # macro +regVML2_UE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regVML2_WALKER_UE_ERR_STATUS_LO = 0x084e # macro +regVML2_WALKER_UE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regUTCL2_UE_ERR_STATUS_LO = 0x084f # macro +regUTCL2_UE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regVML2_UE_ERR_STATUS_HI = 0x0850 # macro +regVML2_UE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regVML2_WALKER_UE_ERR_STATUS_HI = 0x0851 # macro +regVML2_WALKER_UE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regUTCL2_UE_ERR_STATUS_HI = 0x0852 # macro +regUTCL2_UE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regVML2_CE_ERR_STATUS_LO = 0x0853 # macro +regVML2_CE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regVML2_WALKER_CE_ERR_STATUS_LO = 0x0854 # macro +regVML2_WALKER_CE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regUTCL2_CE_ERR_STATUS_LO = 0x0855 # macro +regUTCL2_CE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regVML2_CE_ERR_STATUS_HI = 0x0856 # macro +regVML2_CE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regVML2_WALKER_CE_ERR_STATUS_HI = 0x0857 # macro +regVML2_WALKER_CE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regUTCL2_CE_ERR_STATUS_HI = 0x0858 # macro +regUTCL2_CE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regVM_CONTEXT0_CNTL = 0x0860 # macro +regVM_CONTEXT0_CNTL_BASE_IDX = 0 # macro +regVM_CONTEXT1_CNTL = 0x0861 # macro +regVM_CONTEXT1_CNTL_BASE_IDX = 0 # macro +regVM_CONTEXT2_CNTL = 0x0862 # macro +regVM_CONTEXT2_CNTL_BASE_IDX = 0 # macro +regVM_CONTEXT3_CNTL = 0x0863 # macro +regVM_CONTEXT3_CNTL_BASE_IDX = 0 # macro +regVM_CONTEXT4_CNTL = 0x0864 # macro +regVM_CONTEXT4_CNTL_BASE_IDX = 0 # macro +regVM_CONTEXT5_CNTL = 0x0865 # macro +regVM_CONTEXT5_CNTL_BASE_IDX = 0 # macro +regVM_CONTEXT6_CNTL = 0x0866 # macro +regVM_CONTEXT6_CNTL_BASE_IDX = 0 # macro +regVM_CONTEXT7_CNTL = 0x0867 # macro +regVM_CONTEXT7_CNTL_BASE_IDX = 0 # macro +regVM_CONTEXT8_CNTL = 0x0868 # macro +regVM_CONTEXT8_CNTL_BASE_IDX = 0 # macro +regVM_CONTEXT9_CNTL = 0x0869 # macro +regVM_CONTEXT9_CNTL_BASE_IDX = 0 # macro +regVM_CONTEXT10_CNTL = 0x086a # macro +regVM_CONTEXT10_CNTL_BASE_IDX = 0 # macro +regVM_CONTEXT11_CNTL = 0x086b # macro +regVM_CONTEXT11_CNTL_BASE_IDX = 0 # macro +regVM_CONTEXT12_CNTL = 0x086c # macro +regVM_CONTEXT12_CNTL_BASE_IDX = 0 # macro +regVM_CONTEXT13_CNTL = 0x086d # macro +regVM_CONTEXT13_CNTL_BASE_IDX = 0 # macro +regVM_CONTEXT14_CNTL = 0x086e # macro +regVM_CONTEXT14_CNTL_BASE_IDX = 0 # macro +regVM_CONTEXT15_CNTL = 0x086f # macro +regVM_CONTEXT15_CNTL_BASE_IDX = 0 # macro +regVM_CONTEXTS_DISABLE = 0x0870 # macro +regVM_CONTEXTS_DISABLE_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG0_SEM = 0x0871 # macro +regVM_INVALIDATE_ENG0_SEM_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG1_SEM = 0x0872 # macro +regVM_INVALIDATE_ENG1_SEM_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG2_SEM = 0x0873 # macro +regVM_INVALIDATE_ENG2_SEM_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG3_SEM = 0x0874 # macro +regVM_INVALIDATE_ENG3_SEM_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG4_SEM = 0x0875 # macro +regVM_INVALIDATE_ENG4_SEM_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG5_SEM = 0x0876 # macro +regVM_INVALIDATE_ENG5_SEM_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG6_SEM = 0x0877 # macro +regVM_INVALIDATE_ENG6_SEM_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG7_SEM = 0x0878 # macro +regVM_INVALIDATE_ENG7_SEM_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG8_SEM = 0x0879 # macro +regVM_INVALIDATE_ENG8_SEM_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG9_SEM = 0x087a # macro +regVM_INVALIDATE_ENG9_SEM_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG10_SEM = 0x087b # macro +regVM_INVALIDATE_ENG10_SEM_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG11_SEM = 0x087c # macro +regVM_INVALIDATE_ENG11_SEM_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG12_SEM = 0x087d # macro +regVM_INVALIDATE_ENG12_SEM_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG13_SEM = 0x087e # macro +regVM_INVALIDATE_ENG13_SEM_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG14_SEM = 0x087f # macro +regVM_INVALIDATE_ENG14_SEM_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG15_SEM = 0x0880 # macro +regVM_INVALIDATE_ENG15_SEM_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG16_SEM = 0x0881 # macro +regVM_INVALIDATE_ENG16_SEM_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG17_SEM = 0x0882 # macro +regVM_INVALIDATE_ENG17_SEM_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG0_REQ = 0x0883 # macro +regVM_INVALIDATE_ENG0_REQ_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG1_REQ = 0x0884 # macro +regVM_INVALIDATE_ENG1_REQ_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG2_REQ = 0x0885 # macro +regVM_INVALIDATE_ENG2_REQ_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG3_REQ = 0x0886 # macro +regVM_INVALIDATE_ENG3_REQ_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG4_REQ = 0x0887 # macro +regVM_INVALIDATE_ENG4_REQ_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG5_REQ = 0x0888 # macro +regVM_INVALIDATE_ENG5_REQ_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG6_REQ = 0x0889 # macro +regVM_INVALIDATE_ENG6_REQ_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG7_REQ = 0x088a # macro +regVM_INVALIDATE_ENG7_REQ_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG8_REQ = 0x088b # macro +regVM_INVALIDATE_ENG8_REQ_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG9_REQ = 0x088c # macro +regVM_INVALIDATE_ENG9_REQ_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG10_REQ = 0x088d # macro +regVM_INVALIDATE_ENG10_REQ_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG11_REQ = 0x088e # macro +regVM_INVALIDATE_ENG11_REQ_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG12_REQ = 0x088f # macro +regVM_INVALIDATE_ENG12_REQ_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG13_REQ = 0x0890 # macro +regVM_INVALIDATE_ENG13_REQ_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG14_REQ = 0x0891 # macro +regVM_INVALIDATE_ENG14_REQ_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG15_REQ = 0x0892 # macro +regVM_INVALIDATE_ENG15_REQ_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG16_REQ = 0x0893 # macro +regVM_INVALIDATE_ENG16_REQ_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG17_REQ = 0x0894 # macro +regVM_INVALIDATE_ENG17_REQ_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG0_ACK = 0x0895 # macro +regVM_INVALIDATE_ENG0_ACK_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG1_ACK = 0x0896 # macro +regVM_INVALIDATE_ENG1_ACK_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG2_ACK = 0x0897 # macro +regVM_INVALIDATE_ENG2_ACK_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG3_ACK = 0x0898 # macro +regVM_INVALIDATE_ENG3_ACK_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG4_ACK = 0x0899 # macro +regVM_INVALIDATE_ENG4_ACK_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG5_ACK = 0x089a # macro +regVM_INVALIDATE_ENG5_ACK_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG6_ACK = 0x089b # macro +regVM_INVALIDATE_ENG6_ACK_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG7_ACK = 0x089c # macro +regVM_INVALIDATE_ENG7_ACK_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG8_ACK = 0x089d # macro +regVM_INVALIDATE_ENG8_ACK_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG9_ACK = 0x089e # macro +regVM_INVALIDATE_ENG9_ACK_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG10_ACK = 0x089f # macro +regVM_INVALIDATE_ENG10_ACK_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG11_ACK = 0x08a0 # macro +regVM_INVALIDATE_ENG11_ACK_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG12_ACK = 0x08a1 # macro +regVM_INVALIDATE_ENG12_ACK_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG13_ACK = 0x08a2 # macro +regVM_INVALIDATE_ENG13_ACK_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG14_ACK = 0x08a3 # macro +regVM_INVALIDATE_ENG14_ACK_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG15_ACK = 0x08a4 # macro +regVM_INVALIDATE_ENG15_ACK_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG16_ACK = 0x08a5 # macro +regVM_INVALIDATE_ENG16_ACK_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG17_ACK = 0x08a6 # macro +regVM_INVALIDATE_ENG17_ACK_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 = 0x08a7 # macro +regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 = 0x08a8 # macro +regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 = 0x08a9 # macro +regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 = 0x08aa # macro +regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 = 0x08ab # macro +regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 = 0x08ac # macro +regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 = 0x08ad # macro +regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 = 0x08ae # macro +regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 = 0x08af # macro +regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 = 0x08b0 # macro +regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 = 0x08b1 # macro +regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 = 0x08b2 # macro +regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 = 0x08b3 # macro +regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 = 0x08b4 # macro +regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 = 0x08b5 # macro +regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 = 0x08b6 # macro +regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 = 0x08b7 # macro +regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 = 0x08b8 # macro +regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 = 0x08b9 # macro +regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 = 0x08ba # macro +regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 = 0x08bb # macro +regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 = 0x08bc # macro +regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 = 0x08bd # macro +regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 = 0x08be # macro +regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 = 0x08bf # macro +regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 = 0x08c0 # macro +regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 = 0x08c1 # macro +regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 = 0x08c2 # macro +regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 = 0x08c3 # macro +regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 = 0x08c4 # macro +regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 = 0x08c5 # macro +regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 = 0x08c6 # macro +regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 = 0x08c7 # macro +regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 = 0x08c8 # macro +regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 = 0x08c9 # macro +regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 = 0x08ca # macro +regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 = 0x08cb # macro +regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 = 0x08cc # macro +regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 = 0x08cd # macro +regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 = 0x08ce # macro +regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 = 0x08cf # macro +regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 = 0x08d0 # macro +regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 = 0x08d1 # macro +regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 = 0x08d2 # macro +regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 = 0x08d3 # macro +regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 = 0x08d4 # macro +regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 = 0x08d5 # macro +regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 = 0x08d6 # macro +regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 = 0x08d7 # macro +regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 = 0x08d8 # macro +regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 = 0x08d9 # macro +regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 = 0x08da # macro +regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 = 0x08db # macro +regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 = 0x08dc # macro +regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 = 0x08dd # macro +regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 = 0x08de # macro +regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 = 0x08df # macro +regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 = 0x08e0 # macro +regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 = 0x08e1 # macro +regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 = 0x08e2 # macro +regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 = 0x08e3 # macro +regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 = 0x08e4 # macro +regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 = 0x08e5 # macro +regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 = 0x08e6 # macro +regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 = 0x08e7 # macro +regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 = 0x08e8 # macro +regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 = 0x08e9 # macro +regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 = 0x08ea # macro +regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 = 0x08eb # macro +regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 = 0x08ec # macro +regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 = 0x08ed # macro +regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 = 0x08ee # macro +regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 = 0x08ef # macro +regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 = 0x08f0 # macro +regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 = 0x08f1 # macro +regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 = 0x08f2 # macro +regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 = 0x08f3 # macro +regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 = 0x08f4 # macro +regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 = 0x08f5 # macro +regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 = 0x08f6 # macro +regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 = 0x08f7 # macro +regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 = 0x08f8 # macro +regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 = 0x08f9 # macro +regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 = 0x08fa # macro +regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 = 0x08fb # macro +regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 = 0x08fc # macro +regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 = 0x08fd # macro +regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 = 0x08fe # macro +regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 = 0x08ff # macro +regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 = 0x0900 # macro +regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 = 0x0901 # macro +regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 = 0x0902 # macro +regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 = 0x0903 # macro +regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 = 0x0904 # macro +regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 = 0x0905 # macro +regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 = 0x0906 # macro +regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 = 0x0907 # macro +regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 = 0x0908 # macro +regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 = 0x0909 # macro +regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 = 0x090a # macro +regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 = 0x090b # macro +regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 = 0x090c # macro +regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 = 0x090d # macro +regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 = 0x090e # macro +regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 = 0x090f # macro +regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 = 0x0910 # macro +regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 = 0x0911 # macro +regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 = 0x0912 # macro +regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 = 0x0913 # macro +regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 = 0x0914 # macro +regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 = 0x0915 # macro +regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 = 0x0916 # macro +regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 = 0x0917 # macro +regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 = 0x0918 # macro +regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 = 0x0919 # macro +regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 = 0x091a # macro +regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 = 0x091b # macro +regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 = 0x091c # macro +regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 = 0x091d # macro +regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 = 0x091e # macro +regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 = 0x091f # macro +regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 = 0x0920 # macro +regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 = 0x0921 # macro +regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 = 0x0922 # macro +regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 = 0x0923 # macro +regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 = 0x0924 # macro +regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 = 0x0925 # macro +regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 = 0x0926 # macro +regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 = 0x0927 # macro +regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 = 0x0928 # macro +regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 = 0x0929 # macro +regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 = 0x092a # macro +regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMC_VM_NB_MMIOBASE = 0x0940 # macro +regMC_VM_NB_MMIOBASE_BASE_IDX = 0 # macro +regMC_VM_NB_MMIOLIMIT = 0x0941 # macro +regMC_VM_NB_MMIOLIMIT_BASE_IDX = 0 # macro +regMC_VM_NB_PCI_CTRL = 0x0942 # macro +regMC_VM_NB_PCI_CTRL_BASE_IDX = 0 # macro +regMC_VM_NB_PCI_ARB = 0x0943 # macro +regMC_VM_NB_PCI_ARB_BASE_IDX = 0 # macro +regMC_VM_NB_TOP_OF_DRAM_SLOT1 = 0x0944 # macro +regMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX = 0 # macro +regMC_VM_NB_LOWER_TOP_OF_DRAM2 = 0x0945 # macro +regMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX = 0 # macro +regMC_VM_NB_UPPER_TOP_OF_DRAM2 = 0x0946 # macro +regMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX = 0 # macro +regMC_VM_FB_OFFSET = 0x0947 # macro +regMC_VM_FB_OFFSET_BASE_IDX = 0 # macro +regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0x0948 # macro +regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX = 0 # macro +regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x0949 # macro +regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX = 0 # macro +regMC_VM_STEERING = 0x094a # macro +regMC_VM_STEERING_BASE_IDX = 0 # macro +regMC_SHARED_VIRT_RESET_REQ = 0x094b # macro +regMC_SHARED_VIRT_RESET_REQ_BASE_IDX = 0 # macro +regMC_MEM_POWER_LS = 0x094c # macro +regMC_MEM_POWER_LS_BASE_IDX = 0 # macro +regMC_VM_CACHEABLE_DRAM_ADDRESS_START = 0x094d # macro +regMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX = 0 # macro +regMC_VM_CACHEABLE_DRAM_ADDRESS_END = 0x094e # macro +regMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX = 0 # macro +regMC_VM_APT_CNTL = 0x0951 # macro +regMC_VM_APT_CNTL_BASE_IDX = 0 # macro +regMC_VM_LOCAL_HBM_ADDRESS_START = 0x0952 # macro +regMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX = 0 # macro +regMC_VM_LOCAL_HBM_ADDRESS_END = 0x0953 # macro +regMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX = 0 # macro +regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL = 0x0954 # macro +regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX = 0 # macro +regUTCL2_CGTT_CLK_CTRL = 0x0955 # macro +regUTCL2_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regMC_VM_XGMI_LFB_CNTL = 0x0957 # macro +regMC_VM_XGMI_LFB_CNTL_BASE_IDX = 0 # macro +regMC_VM_XGMI_LFB_SIZE = 0x0958 # macro +regMC_VM_XGMI_LFB_SIZE_BASE_IDX = 0 # macro +regMC_VM_CACHEABLE_DRAM_CNTL = 0x0959 # macro +regMC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX = 0 # macro +regMC_VM_HOST_MAPPING = 0x095a # macro +regMC_VM_HOST_MAPPING_BASE_IDX = 0 # macro +regMC_VM_FB_LOCATION_BASE = 0x095c # macro +regMC_VM_FB_LOCATION_BASE_BASE_IDX = 0 # macro +regMC_VM_FB_LOCATION_TOP = 0x095d # macro +regMC_VM_FB_LOCATION_TOP_BASE_IDX = 0 # macro +regMC_VM_AGP_TOP = 0x095e # macro +regMC_VM_AGP_TOP_BASE_IDX = 0 # macro +regMC_VM_AGP_BOT = 0x095f # macro +regMC_VM_AGP_BOT_BASE_IDX = 0 # macro +regMC_VM_AGP_BASE = 0x0960 # macro +regMC_VM_AGP_BASE_BASE_IDX = 0 # macro +regMC_VM_SYSTEM_APERTURE_LOW_ADDR = 0x0961 # macro +regMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX = 0 # macro +regMC_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x0962 # macro +regMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX = 0 # macro +regMC_VM_MX_L1_TLB_CNTL = 0x0963 # macro +regMC_VM_MX_L1_TLB_CNTL_BASE_IDX = 0 # macro +regL2TLB_TLB0_STATUS = 0x096d # macro +regL2TLB_TLB0_STATUS_BASE_IDX = 0 # macro +regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO = 0x096f # macro +regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX = 0 # macro +regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI = 0x0970 # macro +regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX = 0 # macro +regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO = 0x0971 # macro +regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX = 0 # macro +regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI = 0x0972 # macro +regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX = 0 # macro +regTCP_INVALIDATE = 0x0b00 # macro +regTCP_INVALIDATE_BASE_IDX = 0 # macro +regTCP_STATUS = 0x0b01 # macro +regTCP_STATUS_BASE_IDX = 0 # macro +regTCP_CNTL = 0x0b02 # macro +regTCP_CNTL_BASE_IDX = 0 # macro +regTCP_CHAN_STEER_0 = 0x0b03 # macro +regTCP_CHAN_STEER_0_BASE_IDX = 0 # macro +regTCP_CHAN_STEER_1 = 0x0b04 # macro +regTCP_CHAN_STEER_1_BASE_IDX = 0 # macro +regTCP_ADDR_CONFIG = 0x0b05 # macro +regTCP_ADDR_CONFIG_BASE_IDX = 0 # macro +regTCP_CREDIT = 0x0b06 # macro +regTCP_CREDIT_BASE_IDX = 0 # macro +regTCP_BUFFER_ADDR_HASH_CNTL = 0x0b16 # macro +regTCP_BUFFER_ADDR_HASH_CNTL_BASE_IDX = 0 # macro +regTC_CFG_L1_LOAD_POLICY0 = 0x0b1a # macro +regTC_CFG_L1_LOAD_POLICY0_BASE_IDX = 0 # macro +regTC_CFG_L1_LOAD_POLICY1 = 0x0b1b # macro +regTC_CFG_L1_LOAD_POLICY1_BASE_IDX = 0 # macro +regTC_CFG_L1_STORE_POLICY = 0x0b1c # macro +regTC_CFG_L1_STORE_POLICY_BASE_IDX = 0 # macro +regTC_CFG_L2_LOAD_POLICY0 = 0x0b1d # macro +regTC_CFG_L2_LOAD_POLICY0_BASE_IDX = 0 # macro +regTC_CFG_L2_LOAD_POLICY1 = 0x0b1e # macro +regTC_CFG_L2_LOAD_POLICY1_BASE_IDX = 0 # macro +regTC_CFG_L2_STORE_POLICY0 = 0x0b1f # macro +regTC_CFG_L2_STORE_POLICY0_BASE_IDX = 0 # macro +regTC_CFG_L2_STORE_POLICY1 = 0x0b20 # macro +regTC_CFG_L2_STORE_POLICY1_BASE_IDX = 0 # macro +regTC_CFG_L2_ATOMIC_POLICY = 0x0b21 # macro +regTC_CFG_L2_ATOMIC_POLICY_BASE_IDX = 0 # macro +regTC_CFG_L1_VOLATILE = 0x0b22 # macro +regTC_CFG_L1_VOLATILE_BASE_IDX = 0 # macro +regTC_CFG_L2_VOLATILE = 0x0b23 # macro +regTC_CFG_L2_VOLATILE_BASE_IDX = 0 # macro +regTCP_UE_EDC_HI_REG = 0x0b54 # macro +regTCP_UE_EDC_HI_REG_BASE_IDX = 0 # macro +regTCP_UE_EDC_LO_REG = 0x0b55 # macro +regTCP_UE_EDC_LO_REG_BASE_IDX = 0 # macro +regTCP_CE_EDC_HI_REG = 0x0b56 # macro +regTCP_CE_EDC_HI_REG_BASE_IDX = 0 # macro +regTCP_CE_EDC_LO_REG = 0x0b57 # macro +regTCP_CE_EDC_LO_REG_BASE_IDX = 0 # macro +regTCI_UE_EDC_HI_REG = 0x0b58 # macro +regTCI_UE_EDC_HI_REG_BASE_IDX = 0 # macro +regTCI_UE_EDC_LO_REG = 0x0b59 # macro +regTCI_UE_EDC_LO_REG_BASE_IDX = 0 # macro +regTCI_CE_EDC_HI_REG = 0x0b5a # macro +regTCI_CE_EDC_HI_REG_BASE_IDX = 0 # macro +regTCI_CE_EDC_LO_REG = 0x0b5b # macro +regTCI_CE_EDC_LO_REG_BASE_IDX = 0 # macro +regTCI_MISC = 0x0b5c # macro +regTCI_MISC_BASE_IDX = 0 # macro +regTCI_CNTL_3 = 0x0b5d # macro +regTCI_CNTL_3_BASE_IDX = 0 # macro +regTCI_DSM_CNTL = 0x0b5e # macro +regTCI_DSM_CNTL_BASE_IDX = 0 # macro +regTCI_DSM_CNTL2 = 0x0b5f # macro +regTCI_DSM_CNTL2_BASE_IDX = 0 # macro +regTCI_STATUS = 0x0b61 # macro +regTCI_STATUS_BASE_IDX = 0 # macro +regTCI_CNTL_1 = 0x0b62 # macro +regTCI_CNTL_1_BASE_IDX = 0 # macro +regTCI_CNTL_2 = 0x0b63 # macro +regTCI_CNTL_2_BASE_IDX = 0 # macro +regTCC_CTRL = 0x0b80 # macro +regTCC_CTRL_BASE_IDX = 0 # macro +regTCC_CTRL2 = 0x0b81 # macro +regTCC_CTRL2_BASE_IDX = 0 # macro +regTCC_DSM_CNTL = 0x0b86 # macro +regTCC_DSM_CNTL_BASE_IDX = 0 # macro +regTCC_DSM_CNTLA = 0x0b87 # macro +regTCC_DSM_CNTLA_BASE_IDX = 0 # macro +regTCC_DSM_CNTL2 = 0x0b88 # macro +regTCC_DSM_CNTL2_BASE_IDX = 0 # macro +regTCC_DSM_CNTL2A = 0x0b89 # macro +regTCC_DSM_CNTL2A_BASE_IDX = 0 # macro +regTCC_DSM_CNTL2B = 0x0b8a # macro +regTCC_DSM_CNTL2B_BASE_IDX = 0 # macro +regTCC_WBINVL2 = 0x0b8b # macro +regTCC_WBINVL2_BASE_IDX = 0 # macro +regTCC_SOFT_RESET = 0x0b8c # macro +regTCC_SOFT_RESET_BASE_IDX = 0 # macro +regTCC_DSM_CNTL3 = 0x0b8e # macro +regTCC_DSM_CNTL3_BASE_IDX = 0 # macro +regTCA_CTRL = 0x0bc0 # macro +regTCA_CTRL_BASE_IDX = 0 # macro +regTCA_BURST_MASK = 0x0bc1 # macro +regTCA_BURST_MASK_BASE_IDX = 0 # macro +regTCA_BURST_CTRL = 0x0bc2 # macro +regTCA_BURST_CTRL_BASE_IDX = 0 # macro +regTCA_DSM_CNTL = 0x0bc3 # macro +regTCA_DSM_CNTL_BASE_IDX = 0 # macro +regTCA_DSM_CNTL2 = 0x0bc4 # macro +regTCA_DSM_CNTL2_BASE_IDX = 0 # macro +regTCX_CTRL = 0x0bc6 # macro +regTCX_CTRL_BASE_IDX = 0 # macro +regTCX_DSM_CNTL = 0x0bc7 # macro +regTCX_DSM_CNTL_BASE_IDX = 0 # macro +regTCX_DSM_CNTL2 = 0x0bc8 # macro +regTCX_DSM_CNTL2_BASE_IDX = 0 # macro +regTCA_UE_ERR_STATUS_LO = 0x0bc9 # macro +regTCA_UE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regTCA_UE_ERR_STATUS_HI = 0x0bca # macro +regTCA_UE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regTCX_UE_ERR_STATUS_LO = 0x0bcb # macro +regTCX_UE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regTCX_UE_ERR_STATUS_HI = 0x0bcc # macro +regTCX_UE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regTCX_CE_ERR_STATUS_LO = 0x0bcd # macro +regTCX_CE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regTCX_CE_ERR_STATUS_HI = 0x0bce # macro +regTCX_CE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regTCC_UE_ERR_STATUS_LO = 0x0bcf # macro +regTCC_UE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regTCC_UE_ERR_STATUS_HI = 0x0bd0 # macro +regTCC_UE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regTCC_CE_ERR_STATUS_LO = 0x0bd1 # macro +regTCC_CE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regTCC_CE_ERR_STATUS_HI = 0x0bd2 # macro +regTCC_CE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC3_PS = 0x0c07 # macro +regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_LO_PS = 0x0c08 # macro +regSPI_SHADER_PGM_LO_PS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_HI_PS = 0x0c09 # macro +regSPI_SHADER_PGM_HI_PS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC1_PS = 0x0c0a # macro +regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC2_PS = 0x0c0b # macro +regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_0 = 0x0c0c # macro +regSPI_SHADER_USER_DATA_PS_0_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_1 = 0x0c0d # macro +regSPI_SHADER_USER_DATA_PS_1_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_2 = 0x0c0e # macro +regSPI_SHADER_USER_DATA_PS_2_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_3 = 0x0c0f # macro +regSPI_SHADER_USER_DATA_PS_3_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_4 = 0x0c10 # macro +regSPI_SHADER_USER_DATA_PS_4_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_5 = 0x0c11 # macro +regSPI_SHADER_USER_DATA_PS_5_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_6 = 0x0c12 # macro +regSPI_SHADER_USER_DATA_PS_6_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_7 = 0x0c13 # macro +regSPI_SHADER_USER_DATA_PS_7_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_8 = 0x0c14 # macro +regSPI_SHADER_USER_DATA_PS_8_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_9 = 0x0c15 # macro +regSPI_SHADER_USER_DATA_PS_9_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_10 = 0x0c16 # macro +regSPI_SHADER_USER_DATA_PS_10_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_11 = 0x0c17 # macro +regSPI_SHADER_USER_DATA_PS_11_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_12 = 0x0c18 # macro +regSPI_SHADER_USER_DATA_PS_12_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_13 = 0x0c19 # macro +regSPI_SHADER_USER_DATA_PS_13_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_14 = 0x0c1a # macro +regSPI_SHADER_USER_DATA_PS_14_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_15 = 0x0c1b # macro +regSPI_SHADER_USER_DATA_PS_15_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_16 = 0x0c1c # macro +regSPI_SHADER_USER_DATA_PS_16_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_17 = 0x0c1d # macro +regSPI_SHADER_USER_DATA_PS_17_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_18 = 0x0c1e # macro +regSPI_SHADER_USER_DATA_PS_18_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_19 = 0x0c1f # macro +regSPI_SHADER_USER_DATA_PS_19_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_20 = 0x0c20 # macro +regSPI_SHADER_USER_DATA_PS_20_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_21 = 0x0c21 # macro +regSPI_SHADER_USER_DATA_PS_21_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_22 = 0x0c22 # macro +regSPI_SHADER_USER_DATA_PS_22_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_23 = 0x0c23 # macro +regSPI_SHADER_USER_DATA_PS_23_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_24 = 0x0c24 # macro +regSPI_SHADER_USER_DATA_PS_24_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_25 = 0x0c25 # macro +regSPI_SHADER_USER_DATA_PS_25_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_26 = 0x0c26 # macro +regSPI_SHADER_USER_DATA_PS_26_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_27 = 0x0c27 # macro +regSPI_SHADER_USER_DATA_PS_27_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_28 = 0x0c28 # macro +regSPI_SHADER_USER_DATA_PS_28_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_29 = 0x0c29 # macro +regSPI_SHADER_USER_DATA_PS_29_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_30 = 0x0c2a # macro +regSPI_SHADER_USER_DATA_PS_30_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_PS_31 = 0x0c2b # macro +regSPI_SHADER_USER_DATA_PS_31_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC3_VS = 0x0c46 # macro +regSPI_SHADER_PGM_RSRC3_VS_BASE_IDX = 0 # macro +regSPI_SHADER_LATE_ALLOC_VS = 0x0c47 # macro +regSPI_SHADER_LATE_ALLOC_VS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_LO_VS = 0x0c48 # macro +regSPI_SHADER_PGM_LO_VS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_HI_VS = 0x0c49 # macro +regSPI_SHADER_PGM_HI_VS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC1_VS = 0x0c4a # macro +regSPI_SHADER_PGM_RSRC1_VS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC2_VS = 0x0c4b # macro +regSPI_SHADER_PGM_RSRC2_VS_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_0 = 0x0c4c # macro +regSPI_SHADER_USER_DATA_VS_0_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_1 = 0x0c4d # macro +regSPI_SHADER_USER_DATA_VS_1_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_2 = 0x0c4e # macro +regSPI_SHADER_USER_DATA_VS_2_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_3 = 0x0c4f # macro +regSPI_SHADER_USER_DATA_VS_3_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_4 = 0x0c50 # macro +regSPI_SHADER_USER_DATA_VS_4_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_5 = 0x0c51 # macro +regSPI_SHADER_USER_DATA_VS_5_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_6 = 0x0c52 # macro +regSPI_SHADER_USER_DATA_VS_6_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_7 = 0x0c53 # macro +regSPI_SHADER_USER_DATA_VS_7_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_8 = 0x0c54 # macro +regSPI_SHADER_USER_DATA_VS_8_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_9 = 0x0c55 # macro +regSPI_SHADER_USER_DATA_VS_9_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_10 = 0x0c56 # macro +regSPI_SHADER_USER_DATA_VS_10_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_11 = 0x0c57 # macro +regSPI_SHADER_USER_DATA_VS_11_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_12 = 0x0c58 # macro +regSPI_SHADER_USER_DATA_VS_12_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_13 = 0x0c59 # macro +regSPI_SHADER_USER_DATA_VS_13_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_14 = 0x0c5a # macro +regSPI_SHADER_USER_DATA_VS_14_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_15 = 0x0c5b # macro +regSPI_SHADER_USER_DATA_VS_15_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_16 = 0x0c5c # macro +regSPI_SHADER_USER_DATA_VS_16_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_17 = 0x0c5d # macro +regSPI_SHADER_USER_DATA_VS_17_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_18 = 0x0c5e # macro +regSPI_SHADER_USER_DATA_VS_18_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_19 = 0x0c5f # macro +regSPI_SHADER_USER_DATA_VS_19_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_20 = 0x0c60 # macro +regSPI_SHADER_USER_DATA_VS_20_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_21 = 0x0c61 # macro +regSPI_SHADER_USER_DATA_VS_21_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_22 = 0x0c62 # macro +regSPI_SHADER_USER_DATA_VS_22_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_23 = 0x0c63 # macro +regSPI_SHADER_USER_DATA_VS_23_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_24 = 0x0c64 # macro +regSPI_SHADER_USER_DATA_VS_24_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_25 = 0x0c65 # macro +regSPI_SHADER_USER_DATA_VS_25_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_26 = 0x0c66 # macro +regSPI_SHADER_USER_DATA_VS_26_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_27 = 0x0c67 # macro +regSPI_SHADER_USER_DATA_VS_27_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_28 = 0x0c68 # macro +regSPI_SHADER_USER_DATA_VS_28_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_29 = 0x0c69 # macro +regSPI_SHADER_USER_DATA_VS_29_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_30 = 0x0c6a # macro +regSPI_SHADER_USER_DATA_VS_30_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_VS_31 = 0x0c6b # macro +regSPI_SHADER_USER_DATA_VS_31_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC2_GS_VS = 0x0c7c # macro +regSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC4_GS = 0x0c81 # macro +regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ADDR_LO_GS = 0x0c82 # macro +regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ADDR_HI_GS = 0x0c83 # macro +regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_LO_ES = 0x0c84 # macro +regSPI_SHADER_PGM_LO_ES_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_HI_ES = 0x0c85 # macro +regSPI_SHADER_PGM_HI_ES_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC3_GS = 0x0c87 # macro +regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_LO_GS = 0x0c88 # macro +regSPI_SHADER_PGM_LO_GS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_HI_GS = 0x0c89 # macro +regSPI_SHADER_PGM_HI_GS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC1_GS = 0x0c8a # macro +regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC2_GS = 0x0c8b # macro +regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_0 = 0x0ccc # macro +regSPI_SHADER_USER_DATA_ES_0_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_1 = 0x0ccd # macro +regSPI_SHADER_USER_DATA_ES_1_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_2 = 0x0cce # macro +regSPI_SHADER_USER_DATA_ES_2_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_3 = 0x0ccf # macro +regSPI_SHADER_USER_DATA_ES_3_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_4 = 0x0cd0 # macro +regSPI_SHADER_USER_DATA_ES_4_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_5 = 0x0cd1 # macro +regSPI_SHADER_USER_DATA_ES_5_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_6 = 0x0cd2 # macro +regSPI_SHADER_USER_DATA_ES_6_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_7 = 0x0cd3 # macro +regSPI_SHADER_USER_DATA_ES_7_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_8 = 0x0cd4 # macro +regSPI_SHADER_USER_DATA_ES_8_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_9 = 0x0cd5 # macro +regSPI_SHADER_USER_DATA_ES_9_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_10 = 0x0cd6 # macro +regSPI_SHADER_USER_DATA_ES_10_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_11 = 0x0cd7 # macro +regSPI_SHADER_USER_DATA_ES_11_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_12 = 0x0cd8 # macro +regSPI_SHADER_USER_DATA_ES_12_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_13 = 0x0cd9 # macro +regSPI_SHADER_USER_DATA_ES_13_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_14 = 0x0cda # macro +regSPI_SHADER_USER_DATA_ES_14_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_15 = 0x0cdb # macro +regSPI_SHADER_USER_DATA_ES_15_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_16 = 0x0cdc # macro +regSPI_SHADER_USER_DATA_ES_16_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_17 = 0x0cdd # macro +regSPI_SHADER_USER_DATA_ES_17_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_18 = 0x0cde # macro +regSPI_SHADER_USER_DATA_ES_18_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_19 = 0x0cdf # macro +regSPI_SHADER_USER_DATA_ES_19_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_20 = 0x0ce0 # macro +regSPI_SHADER_USER_DATA_ES_20_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_21 = 0x0ce1 # macro +regSPI_SHADER_USER_DATA_ES_21_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_22 = 0x0ce2 # macro +regSPI_SHADER_USER_DATA_ES_22_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_23 = 0x0ce3 # macro +regSPI_SHADER_USER_DATA_ES_23_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_24 = 0x0ce4 # macro +regSPI_SHADER_USER_DATA_ES_24_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_25 = 0x0ce5 # macro +regSPI_SHADER_USER_DATA_ES_25_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_26 = 0x0ce6 # macro +regSPI_SHADER_USER_DATA_ES_26_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_27 = 0x0ce7 # macro +regSPI_SHADER_USER_DATA_ES_27_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_28 = 0x0ce8 # macro +regSPI_SHADER_USER_DATA_ES_28_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_29 = 0x0ce9 # macro +regSPI_SHADER_USER_DATA_ES_29_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_30 = 0x0cea # macro +regSPI_SHADER_USER_DATA_ES_30_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ES_31 = 0x0ceb # macro +regSPI_SHADER_USER_DATA_ES_31_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC4_HS = 0x0d01 # macro +regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ADDR_LO_HS = 0x0d02 # macro +regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_ADDR_HI_HS = 0x0d03 # macro +regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_LO_LS = 0x0d04 # macro +regSPI_SHADER_PGM_LO_LS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_HI_LS = 0x0d05 # macro +regSPI_SHADER_PGM_HI_LS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC3_HS = 0x0d07 # macro +regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_LO_HS = 0x0d08 # macro +regSPI_SHADER_PGM_LO_HS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_HI_HS = 0x0d09 # macro +regSPI_SHADER_PGM_HI_HS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC1_HS = 0x0d0a # macro +regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX = 0 # macro +regSPI_SHADER_PGM_RSRC2_HS = 0x0d0b # macro +regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_0 = 0x0d0c # macro +regSPI_SHADER_USER_DATA_LS_0_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_1 = 0x0d0d # macro +regSPI_SHADER_USER_DATA_LS_1_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_2 = 0x0d0e # macro +regSPI_SHADER_USER_DATA_LS_2_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_3 = 0x0d0f # macro +regSPI_SHADER_USER_DATA_LS_3_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_4 = 0x0d10 # macro +regSPI_SHADER_USER_DATA_LS_4_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_5 = 0x0d11 # macro +regSPI_SHADER_USER_DATA_LS_5_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_6 = 0x0d12 # macro +regSPI_SHADER_USER_DATA_LS_6_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_7 = 0x0d13 # macro +regSPI_SHADER_USER_DATA_LS_7_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_8 = 0x0d14 # macro +regSPI_SHADER_USER_DATA_LS_8_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_9 = 0x0d15 # macro +regSPI_SHADER_USER_DATA_LS_9_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_10 = 0x0d16 # macro +regSPI_SHADER_USER_DATA_LS_10_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_11 = 0x0d17 # macro +regSPI_SHADER_USER_DATA_LS_11_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_12 = 0x0d18 # macro +regSPI_SHADER_USER_DATA_LS_12_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_13 = 0x0d19 # macro +regSPI_SHADER_USER_DATA_LS_13_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_14 = 0x0d1a # macro +regSPI_SHADER_USER_DATA_LS_14_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_15 = 0x0d1b # macro +regSPI_SHADER_USER_DATA_LS_15_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_16 = 0x0d1c # macro +regSPI_SHADER_USER_DATA_LS_16_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_17 = 0x0d1d # macro +regSPI_SHADER_USER_DATA_LS_17_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_18 = 0x0d1e # macro +regSPI_SHADER_USER_DATA_LS_18_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_19 = 0x0d1f # macro +regSPI_SHADER_USER_DATA_LS_19_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_20 = 0x0d20 # macro +regSPI_SHADER_USER_DATA_LS_20_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_21 = 0x0d21 # macro +regSPI_SHADER_USER_DATA_LS_21_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_22 = 0x0d22 # macro +regSPI_SHADER_USER_DATA_LS_22_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_23 = 0x0d23 # macro +regSPI_SHADER_USER_DATA_LS_23_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_24 = 0x0d24 # macro +regSPI_SHADER_USER_DATA_LS_24_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_25 = 0x0d25 # macro +regSPI_SHADER_USER_DATA_LS_25_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_26 = 0x0d26 # macro +regSPI_SHADER_USER_DATA_LS_26_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_27 = 0x0d27 # macro +regSPI_SHADER_USER_DATA_LS_27_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_28 = 0x0d28 # macro +regSPI_SHADER_USER_DATA_LS_28_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_29 = 0x0d29 # macro +regSPI_SHADER_USER_DATA_LS_29_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_30 = 0x0d2a # macro +regSPI_SHADER_USER_DATA_LS_30_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_LS_31 = 0x0d2b # macro +regSPI_SHADER_USER_DATA_LS_31_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_0 = 0x0d4c # macro +regSPI_SHADER_USER_DATA_COMMON_0_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_1 = 0x0d4d # macro +regSPI_SHADER_USER_DATA_COMMON_1_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_2 = 0x0d4e # macro +regSPI_SHADER_USER_DATA_COMMON_2_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_3 = 0x0d4f # macro +regSPI_SHADER_USER_DATA_COMMON_3_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_4 = 0x0d50 # macro +regSPI_SHADER_USER_DATA_COMMON_4_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_5 = 0x0d51 # macro +regSPI_SHADER_USER_DATA_COMMON_5_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_6 = 0x0d52 # macro +regSPI_SHADER_USER_DATA_COMMON_6_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_7 = 0x0d53 # macro +regSPI_SHADER_USER_DATA_COMMON_7_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_8 = 0x0d54 # macro +regSPI_SHADER_USER_DATA_COMMON_8_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_9 = 0x0d55 # macro +regSPI_SHADER_USER_DATA_COMMON_9_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_10 = 0x0d56 # macro +regSPI_SHADER_USER_DATA_COMMON_10_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_11 = 0x0d57 # macro +regSPI_SHADER_USER_DATA_COMMON_11_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_12 = 0x0d58 # macro +regSPI_SHADER_USER_DATA_COMMON_12_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_13 = 0x0d59 # macro +regSPI_SHADER_USER_DATA_COMMON_13_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_14 = 0x0d5a # macro +regSPI_SHADER_USER_DATA_COMMON_14_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_15 = 0x0d5b # macro +regSPI_SHADER_USER_DATA_COMMON_15_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_16 = 0x0d5c # macro +regSPI_SHADER_USER_DATA_COMMON_16_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_17 = 0x0d5d # macro +regSPI_SHADER_USER_DATA_COMMON_17_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_18 = 0x0d5e # macro +regSPI_SHADER_USER_DATA_COMMON_18_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_19 = 0x0d5f # macro +regSPI_SHADER_USER_DATA_COMMON_19_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_20 = 0x0d60 # macro +regSPI_SHADER_USER_DATA_COMMON_20_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_21 = 0x0d61 # macro +regSPI_SHADER_USER_DATA_COMMON_21_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_22 = 0x0d62 # macro +regSPI_SHADER_USER_DATA_COMMON_22_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_23 = 0x0d63 # macro +regSPI_SHADER_USER_DATA_COMMON_23_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_24 = 0x0d64 # macro +regSPI_SHADER_USER_DATA_COMMON_24_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_25 = 0x0d65 # macro +regSPI_SHADER_USER_DATA_COMMON_25_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_26 = 0x0d66 # macro +regSPI_SHADER_USER_DATA_COMMON_26_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_27 = 0x0d67 # macro +regSPI_SHADER_USER_DATA_COMMON_27_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_28 = 0x0d68 # macro +regSPI_SHADER_USER_DATA_COMMON_28_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_29 = 0x0d69 # macro +regSPI_SHADER_USER_DATA_COMMON_29_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_30 = 0x0d6a # macro +regSPI_SHADER_USER_DATA_COMMON_30_BASE_IDX = 0 # macro +regSPI_SHADER_USER_DATA_COMMON_31 = 0x0d6b # macro +regSPI_SHADER_USER_DATA_COMMON_31_BASE_IDX = 0 # macro +regCOMPUTE_DISPATCH_INITIATOR = 0x0e00 # macro +regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX = 0 # macro +regCOMPUTE_DIM_X = 0x0e01 # macro +regCOMPUTE_DIM_X_BASE_IDX = 0 # macro +regCOMPUTE_DIM_Y = 0x0e02 # macro +regCOMPUTE_DIM_Y_BASE_IDX = 0 # macro +regCOMPUTE_DIM_Z = 0x0e03 # macro +regCOMPUTE_DIM_Z_BASE_IDX = 0 # macro +regCOMPUTE_START_X = 0x0e04 # macro +regCOMPUTE_START_X_BASE_IDX = 0 # macro +regCOMPUTE_START_Y = 0x0e05 # macro +regCOMPUTE_START_Y_BASE_IDX = 0 # macro +regCOMPUTE_START_Z = 0x0e06 # macro +regCOMPUTE_START_Z_BASE_IDX = 0 # macro +regCOMPUTE_NUM_THREAD_X = 0x0e07 # macro +regCOMPUTE_NUM_THREAD_X_BASE_IDX = 0 # macro +regCOMPUTE_NUM_THREAD_Y = 0x0e08 # macro +regCOMPUTE_NUM_THREAD_Y_BASE_IDX = 0 # macro +regCOMPUTE_NUM_THREAD_Z = 0x0e09 # macro +regCOMPUTE_NUM_THREAD_Z_BASE_IDX = 0 # macro +regCOMPUTE_PIPELINESTAT_ENABLE = 0x0e0a # macro +regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX = 0 # macro +regCOMPUTE_PERFCOUNT_ENABLE = 0x0e0b # macro +regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX = 0 # macro +regCOMPUTE_PGM_LO = 0x0e0c # macro +regCOMPUTE_PGM_LO_BASE_IDX = 0 # macro +regCOMPUTE_PGM_HI = 0x0e0d # macro +regCOMPUTE_PGM_HI_BASE_IDX = 0 # macro +regCOMPUTE_DISPATCH_PKT_ADDR_LO = 0x0e0e # macro +regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX = 0 # macro +regCOMPUTE_DISPATCH_PKT_ADDR_HI = 0x0e0f # macro +regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX = 0 # macro +regCOMPUTE_DISPATCH_SCRATCH_BASE_LO = 0x0e10 # macro +regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX = 0 # macro +regCOMPUTE_DISPATCH_SCRATCH_BASE_HI = 0x0e11 # macro +regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX = 0 # macro +regCOMPUTE_PGM_RSRC1 = 0x0e12 # macro +regCOMPUTE_PGM_RSRC1_BASE_IDX = 0 # macro +regCOMPUTE_PGM_RSRC2 = 0x0e13 # macro +regCOMPUTE_PGM_RSRC2_BASE_IDX = 0 # macro +regCOMPUTE_VMID = 0x0e14 # macro +regCOMPUTE_VMID_BASE_IDX = 0 # macro +regCOMPUTE_RESOURCE_LIMITS = 0x0e15 # macro +regCOMPUTE_RESOURCE_LIMITS_BASE_IDX = 0 # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE0 = 0x0e16 # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX = 0 # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE1 = 0x0e17 # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX = 0 # macro +regCOMPUTE_TMPRING_SIZE = 0x0e18 # macro +regCOMPUTE_TMPRING_SIZE_BASE_IDX = 0 # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE2 = 0x0e19 # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX = 0 # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE3 = 0x0e1a # macro +regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX = 0 # macro +regCOMPUTE_RESTART_X = 0x0e1b # macro +regCOMPUTE_RESTART_X_BASE_IDX = 0 # macro +regCOMPUTE_RESTART_Y = 0x0e1c # macro +regCOMPUTE_RESTART_Y_BASE_IDX = 0 # macro +regCOMPUTE_RESTART_Z = 0x0e1d # macro +regCOMPUTE_RESTART_Z_BASE_IDX = 0 # macro +regCOMPUTE_THREAD_TRACE_ENABLE = 0x0e1e # macro +regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX = 0 # macro +regCOMPUTE_MISC_RESERVED = 0x0e1f # macro +regCOMPUTE_MISC_RESERVED_BASE_IDX = 0 # macro +regCOMPUTE_DISPATCH_ID = 0x0e20 # macro +regCOMPUTE_DISPATCH_ID_BASE_IDX = 0 # macro +regCOMPUTE_THREADGROUP_ID = 0x0e21 # macro +regCOMPUTE_THREADGROUP_ID_BASE_IDX = 0 # macro +regCOMPUTE_RELAUNCH = 0x0e22 # macro +regCOMPUTE_RELAUNCH_BASE_IDX = 0 # macro +regCOMPUTE_WAVE_RESTORE_ADDR_LO = 0x0e23 # macro +regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX = 0 # macro +regCOMPUTE_WAVE_RESTORE_ADDR_HI = 0x0e24 # macro +regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX = 0 # macro +regCOMPUTE_TG_CHUNK_SIZE = 0x0e27 # macro +regCOMPUTE_TG_CHUNK_SIZE_BASE_IDX = 0 # macro +regCOMPUTE_SHADER_CHKSUM = 0x0e2c # macro +regCOMPUTE_SHADER_CHKSUM_BASE_IDX = 0 # macro +regCOMPUTE_PGM_RSRC3 = 0x0e2d # macro +regCOMPUTE_PGM_RSRC3_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_0 = 0x0e40 # macro +regCOMPUTE_USER_DATA_0_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_1 = 0x0e41 # macro +regCOMPUTE_USER_DATA_1_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_2 = 0x0e42 # macro +regCOMPUTE_USER_DATA_2_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_3 = 0x0e43 # macro +regCOMPUTE_USER_DATA_3_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_4 = 0x0e44 # macro +regCOMPUTE_USER_DATA_4_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_5 = 0x0e45 # macro +regCOMPUTE_USER_DATA_5_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_6 = 0x0e46 # macro +regCOMPUTE_USER_DATA_6_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_7 = 0x0e47 # macro +regCOMPUTE_USER_DATA_7_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_8 = 0x0e48 # macro +regCOMPUTE_USER_DATA_8_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_9 = 0x0e49 # macro +regCOMPUTE_USER_DATA_9_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_10 = 0x0e4a # macro +regCOMPUTE_USER_DATA_10_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_11 = 0x0e4b # macro +regCOMPUTE_USER_DATA_11_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_12 = 0x0e4c # macro +regCOMPUTE_USER_DATA_12_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_13 = 0x0e4d # macro +regCOMPUTE_USER_DATA_13_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_14 = 0x0e4e # macro +regCOMPUTE_USER_DATA_14_BASE_IDX = 0 # macro +regCOMPUTE_USER_DATA_15 = 0x0e4f # macro +regCOMPUTE_USER_DATA_15_BASE_IDX = 0 # macro +regCOMPUTE_DISPATCH_END = 0x0e7e # macro +regCOMPUTE_DISPATCH_END_BASE_IDX = 0 # macro +regCOMPUTE_NOWHERE = 0x0e7f # macro +regCOMPUTE_NOWHERE_BASE_IDX = 0 # macro +regCP_DFY_CNTL = 0x1020 # macro +regCP_DFY_CNTL_BASE_IDX = 0 # macro +regCP_DFY_STAT = 0x1021 # macro +regCP_DFY_STAT_BASE_IDX = 0 # macro +regCP_DFY_ADDR_HI = 0x1022 # macro +regCP_DFY_ADDR_HI_BASE_IDX = 0 # macro +regCP_DFY_ADDR_LO = 0x1023 # macro +regCP_DFY_ADDR_LO_BASE_IDX = 0 # macro +regCP_DFY_DATA_0 = 0x1024 # macro +regCP_DFY_DATA_0_BASE_IDX = 0 # macro +regCP_DFY_DATA_1 = 0x1025 # macro +regCP_DFY_DATA_1_BASE_IDX = 0 # macro +regCP_DFY_DATA_2 = 0x1026 # macro +regCP_DFY_DATA_2_BASE_IDX = 0 # macro +regCP_DFY_DATA_3 = 0x1027 # macro +regCP_DFY_DATA_3_BASE_IDX = 0 # macro +regCP_DFY_DATA_4 = 0x1028 # macro +regCP_DFY_DATA_4_BASE_IDX = 0 # macro +regCP_DFY_DATA_5 = 0x1029 # macro +regCP_DFY_DATA_5_BASE_IDX = 0 # macro +regCP_DFY_DATA_6 = 0x102a # macro +regCP_DFY_DATA_6_BASE_IDX = 0 # macro +regCP_DFY_DATA_7 = 0x102b # macro +regCP_DFY_DATA_7_BASE_IDX = 0 # macro +regCP_DFY_DATA_8 = 0x102c # macro +regCP_DFY_DATA_8_BASE_IDX = 0 # macro +regCP_DFY_DATA_9 = 0x102d # macro +regCP_DFY_DATA_9_BASE_IDX = 0 # macro +regCP_DFY_DATA_10 = 0x102e # macro +regCP_DFY_DATA_10_BASE_IDX = 0 # macro +regCP_DFY_DATA_11 = 0x102f # macro +regCP_DFY_DATA_11_BASE_IDX = 0 # macro +regCP_DFY_DATA_12 = 0x1030 # macro +regCP_DFY_DATA_12_BASE_IDX = 0 # macro +regCP_DFY_DATA_13 = 0x1031 # macro +regCP_DFY_DATA_13_BASE_IDX = 0 # macro +regCP_DFY_DATA_14 = 0x1032 # macro +regCP_DFY_DATA_14_BASE_IDX = 0 # macro +regCP_DFY_DATA_15 = 0x1033 # macro +regCP_DFY_DATA_15_BASE_IDX = 0 # macro +regCP_DFY_CMD = 0x1034 # macro +regCP_DFY_CMD_BASE_IDX = 0 # macro +regCP_EOPQ_WAIT_TIME = 0x1035 # macro +regCP_EOPQ_WAIT_TIME_BASE_IDX = 0 # macro +regCP_CPC_MGCG_SYNC_CNTL = 0x1036 # macro +regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX = 0 # macro +regCPC_INT_INFO = 0x1037 # macro +regCPC_INT_INFO_BASE_IDX = 0 # macro +regCP_VIRT_STATUS = 0x1038 # macro +regCP_VIRT_STATUS_BASE_IDX = 0 # macro +regCPC_INT_ADDR = 0x1039 # macro +regCPC_INT_ADDR_BASE_IDX = 0 # macro +regCPC_INT_PASID = 0x103a # macro +regCPC_INT_PASID_BASE_IDX = 0 # macro +regCP_GFX_ERROR = 0x103b # macro +regCP_GFX_ERROR_BASE_IDX = 0 # macro +regCPG_UTCL1_CNTL = 0x103c # macro +regCPG_UTCL1_CNTL_BASE_IDX = 0 # macro +regCPC_UTCL1_CNTL = 0x103d # macro +regCPC_UTCL1_CNTL_BASE_IDX = 0 # macro +regCPF_UTCL1_CNTL = 0x103e # macro +regCPF_UTCL1_CNTL_BASE_IDX = 0 # macro +regCP_AQL_SMM_STATUS = 0x103f # macro +regCP_AQL_SMM_STATUS_BASE_IDX = 0 # macro +regCP_RB0_BASE = 0x1040 # macro +regCP_RB0_BASE_BASE_IDX = 0 # macro +regCP_RB_BASE = 0x1040 # macro +regCP_RB_BASE_BASE_IDX = 0 # macro +regCP_RB0_CNTL = 0x1041 # macro +regCP_RB0_CNTL_BASE_IDX = 0 # macro +regCP_RB_CNTL = 0x1041 # macro +regCP_RB_CNTL_BASE_IDX = 0 # macro +regCP_RB_RPTR_WR = 0x1042 # macro +regCP_RB_RPTR_WR_BASE_IDX = 0 # macro +regCP_RB0_RPTR_ADDR = 0x1043 # macro +regCP_RB0_RPTR_ADDR_BASE_IDX = 0 # macro +regCP_RB_RPTR_ADDR = 0x1043 # macro +regCP_RB_RPTR_ADDR_BASE_IDX = 0 # macro +regCP_RB0_RPTR_ADDR_HI = 0x1044 # macro +regCP_RB0_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regCP_RB_RPTR_ADDR_HI = 0x1044 # macro +regCP_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regCP_RB0_BUFSZ_MASK = 0x1045 # macro +regCP_RB0_BUFSZ_MASK_BASE_IDX = 0 # macro +regCP_RB_BUFSZ_MASK = 0x1045 # macro +regCP_RB_BUFSZ_MASK_BASE_IDX = 0 # macro +regCP_RB_WPTR_POLL_ADDR_LO = 0x1046 # macro +regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +regCP_RB_WPTR_POLL_ADDR_HI = 0x1047 # macro +regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +regGC_PRIV_MODE = 0x1048 # macro +regGC_PRIV_MODE_BASE_IDX = 0 # macro +regCP_INT_CNTL = 0x1049 # macro +regCP_INT_CNTL_BASE_IDX = 0 # macro +regCP_INT_STATUS = 0x104a # macro +regCP_INT_STATUS_BASE_IDX = 0 # macro +regCP_DEVICE_ID = 0x104b # macro +regCP_DEVICE_ID_BASE_IDX = 0 # macro +regCP_ME0_PIPE_PRIORITY_CNTS = 0x104c # macro +regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro +regCP_RING_PRIORITY_CNTS = 0x104c # macro +regCP_RING_PRIORITY_CNTS_BASE_IDX = 0 # macro +regCP_ME0_PIPE0_PRIORITY = 0x104d # macro +regCP_ME0_PIPE0_PRIORITY_BASE_IDX = 0 # macro +regCP_RING0_PRIORITY = 0x104d # macro +regCP_RING0_PRIORITY_BASE_IDX = 0 # macro +regCP_ME0_PIPE1_PRIORITY = 0x104e # macro +regCP_ME0_PIPE1_PRIORITY_BASE_IDX = 0 # macro +regCP_RING1_PRIORITY = 0x104e # macro +regCP_RING1_PRIORITY_BASE_IDX = 0 # macro +regCP_ME0_PIPE2_PRIORITY = 0x104f # macro +regCP_ME0_PIPE2_PRIORITY_BASE_IDX = 0 # macro +regCP_RING2_PRIORITY = 0x104f # macro +regCP_RING2_PRIORITY_BASE_IDX = 0 # macro +regCP_FATAL_ERROR = 0x1050 # macro +regCP_FATAL_ERROR_BASE_IDX = 0 # macro +regCP_RB_VMID = 0x1051 # macro +regCP_RB_VMID_BASE_IDX = 0 # macro +regCP_ME0_PIPE0_VMID = 0x1052 # macro +regCP_ME0_PIPE0_VMID_BASE_IDX = 0 # macro +regCP_ME0_PIPE1_VMID = 0x1053 # macro +regCP_ME0_PIPE1_VMID_BASE_IDX = 0 # macro +regCP_RB0_WPTR = 0x1054 # macro +regCP_RB0_WPTR_BASE_IDX = 0 # macro +regCP_RB_WPTR = 0x1054 # macro +regCP_RB_WPTR_BASE_IDX = 0 # macro +regCP_RB0_WPTR_HI = 0x1055 # macro +regCP_RB0_WPTR_HI_BASE_IDX = 0 # macro +regCP_RB_WPTR_HI = 0x1055 # macro +regCP_RB_WPTR_HI_BASE_IDX = 0 # macro +regCP_RB1_WPTR = 0x1056 # macro +regCP_RB1_WPTR_BASE_IDX = 0 # macro +regCP_RB1_WPTR_HI = 0x1057 # macro +regCP_RB1_WPTR_HI_BASE_IDX = 0 # macro +regCP_RB2_WPTR = 0x1058 # macro +regCP_RB2_WPTR_BASE_IDX = 0 # macro +regCP_RB_DOORBELL_CONTROL = 0x1059 # macro +regCP_RB_DOORBELL_CONTROL_BASE_IDX = 0 # macro +regCP_RB_DOORBELL_RANGE_LOWER = 0x105a # macro +regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX = 0 # macro +regCP_RB_DOORBELL_RANGE_UPPER = 0x105b # macro +regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX = 0 # macro +regCP_MEC_DOORBELL_RANGE_LOWER = 0x105c # macro +regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX = 0 # macro +regCP_MEC_DOORBELL_RANGE_UPPER = 0x105d # macro +regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX = 0 # macro +regCPG_UTCL1_ERROR = 0x105e # macro +regCPG_UTCL1_ERROR_BASE_IDX = 0 # macro +regCPC_UTCL1_ERROR = 0x105f # macro +regCPC_UTCL1_ERROR_BASE_IDX = 0 # macro +regCP_RB1_BASE = 0x1060 # macro +regCP_RB1_BASE_BASE_IDX = 0 # macro +regCP_RB1_CNTL = 0x1061 # macro +regCP_RB1_CNTL_BASE_IDX = 0 # macro +regCP_RB1_RPTR_ADDR = 0x1062 # macro +regCP_RB1_RPTR_ADDR_BASE_IDX = 0 # macro +regCP_RB1_RPTR_ADDR_HI = 0x1063 # macro +regCP_RB1_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regCP_RB2_BASE = 0x1065 # macro +regCP_RB2_BASE_BASE_IDX = 0 # macro +regCP_RB2_CNTL = 0x1066 # macro +regCP_RB2_CNTL_BASE_IDX = 0 # macro +regCP_RB2_RPTR_ADDR = 0x1067 # macro +regCP_RB2_RPTR_ADDR_BASE_IDX = 0 # macro +regCP_RB2_RPTR_ADDR_HI = 0x1068 # macro +regCP_RB2_RPTR_ADDR_HI_BASE_IDX = 0 # macro +regCP_RB0_ACTIVE = 0x1069 # macro +regCP_RB0_ACTIVE_BASE_IDX = 0 # macro +regCP_RB_ACTIVE = 0x1069 # macro +regCP_RB_ACTIVE_BASE_IDX = 0 # macro +regCP_INT_CNTL_RING0 = 0x106a # macro +regCP_INT_CNTL_RING0_BASE_IDX = 0 # macro +regCP_INT_CNTL_RING1 = 0x106b # macro +regCP_INT_CNTL_RING1_BASE_IDX = 0 # macro +regCP_INT_CNTL_RING2 = 0x106c # macro +regCP_INT_CNTL_RING2_BASE_IDX = 0 # macro +regCP_INT_STATUS_RING0 = 0x106d # macro +regCP_INT_STATUS_RING0_BASE_IDX = 0 # macro +regCP_INT_STATUS_RING1 = 0x106e # macro +regCP_INT_STATUS_RING1_BASE_IDX = 0 # macro +regCP_INT_STATUS_RING2 = 0x106f # macro +regCP_INT_STATUS_RING2_BASE_IDX = 0 # macro +regCP_ME_F32_INTERRUPT = 0x1073 # macro +regCP_ME_F32_INTERRUPT_BASE_IDX = 0 # macro +regCP_PFP_F32_INTERRUPT = 0x1074 # macro +regCP_PFP_F32_INTERRUPT_BASE_IDX = 0 # macro +regCP_CE_F32_INTERRUPT = 0x1075 # macro +regCP_CE_F32_INTERRUPT_BASE_IDX = 0 # macro +regCP_MEC1_F32_INTERRUPT = 0x1076 # macro +regCP_MEC1_F32_INTERRUPT_BASE_IDX = 0 # macro +regCP_MEC2_F32_INTERRUPT = 0x1077 # macro +regCP_MEC2_F32_INTERRUPT_BASE_IDX = 0 # macro +regCP_PWR_CNTL = 0x1078 # macro +regCP_PWR_CNTL_BASE_IDX = 0 # macro +regCP_MEM_SLP_CNTL = 0x1079 # macro +regCP_MEM_SLP_CNTL_BASE_IDX = 0 # macro +regCP_ECC_DMA_FIRST_OCCURRENCE = 0x107a # macro +regCP_ECC_DMA_FIRST_OCCURRENCE_BASE_IDX = 0 # macro +regCP_ECC_FIRSTOCCURRENCE = 0x107a # macro +regCP_ECC_FIRSTOCCURRENCE_BASE_IDX = 0 # macro +regCP_ECC_FIRSTOCCURRENCE_RING0 = 0x107b # macro +regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX = 0 # macro +regCP_ECC_FIRSTOCCURRENCE_RING1 = 0x107c # macro +regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX = 0 # macro +regCP_ECC_FIRSTOCCURRENCE_RING2 = 0x107d # macro +regCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX = 0 # macro +regGB_EDC_MODE = 0x107e # macro +regGB_EDC_MODE_BASE_IDX = 0 # macro +regCP_DEBUG = 0x107f # macro +regCP_DEBUG_BASE_IDX = 0 # macro +regCP_CPF_DEBUG = 0x1080 # macro +regCP_CPF_DEBUG_BASE_IDX = 0 # macro +regCP_CPC_DEBUG = 0x1081 # macro +regCP_CPC_DEBUG_BASE_IDX = 0 # macro +regCP_CPC_DEBUG_2 = 0x1082 # macro +regCP_CPC_DEBUG_2_BASE_IDX = 0 # macro +regCP_PQ_WPTR_POLL_CNTL = 0x1083 # macro +regCP_PQ_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +regCP_PQ_WPTR_POLL_CNTL1 = 0x1084 # macro +regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX = 0 # macro +regCP_ME1_PIPE0_INT_CNTL = 0x1085 # macro +regCP_ME1_PIPE0_INT_CNTL_BASE_IDX = 0 # macro +regCP_ME1_PIPE1_INT_CNTL = 0x1086 # macro +regCP_ME1_PIPE1_INT_CNTL_BASE_IDX = 0 # macro +regCP_ME1_PIPE2_INT_CNTL = 0x1087 # macro +regCP_ME1_PIPE2_INT_CNTL_BASE_IDX = 0 # macro +regCP_ME1_PIPE3_INT_CNTL = 0x1088 # macro +regCP_ME1_PIPE3_INT_CNTL_BASE_IDX = 0 # macro +regCP_ME2_PIPE0_INT_CNTL = 0x1089 # macro +regCP_ME2_PIPE0_INT_CNTL_BASE_IDX = 0 # macro +regCP_ME2_PIPE1_INT_CNTL = 0x108a # macro +regCP_ME2_PIPE1_INT_CNTL_BASE_IDX = 0 # macro +regCP_ME2_PIPE2_INT_CNTL = 0x108b # macro +regCP_ME2_PIPE2_INT_CNTL_BASE_IDX = 0 # macro +regCP_ME2_PIPE3_INT_CNTL = 0x108c # macro +regCP_ME2_PIPE3_INT_CNTL_BASE_IDX = 0 # macro +regCP_ME1_PIPE0_INT_STATUS = 0x108d # macro +regCP_ME1_PIPE0_INT_STATUS_BASE_IDX = 0 # macro +regCP_ME1_PIPE1_INT_STATUS = 0x108e # macro +regCP_ME1_PIPE1_INT_STATUS_BASE_IDX = 0 # macro +regCP_ME1_PIPE2_INT_STATUS = 0x108f # macro +regCP_ME1_PIPE2_INT_STATUS_BASE_IDX = 0 # macro +regCP_ME1_PIPE3_INT_STATUS = 0x1090 # macro +regCP_ME1_PIPE3_INT_STATUS_BASE_IDX = 0 # macro +regCP_ME2_PIPE0_INT_STATUS = 0x1091 # macro +regCP_ME2_PIPE0_INT_STATUS_BASE_IDX = 0 # macro +regCP_ME2_PIPE1_INT_STATUS = 0x1092 # macro +regCP_ME2_PIPE1_INT_STATUS_BASE_IDX = 0 # macro +regCP_ME2_PIPE2_INT_STATUS = 0x1093 # macro +regCP_ME2_PIPE2_INT_STATUS_BASE_IDX = 0 # macro +regCP_ME2_PIPE3_INT_STATUS = 0x1094 # macro +regCP_ME2_PIPE3_INT_STATUS_BASE_IDX = 0 # macro +regCP_ME1_INT_STAT_DEBUG = 0x1095 # macro +regCP_ME1_INT_STAT_DEBUG_BASE_IDX = 0 # macro +regCP_ME2_INT_STAT_DEBUG = 0x1096 # macro +regCP_ME2_INT_STAT_DEBUG_BASE_IDX = 0 # macro +regCC_GC_EDC_CONFIG = 0x1098 # macro +regCC_GC_EDC_CONFIG_BASE_IDX = 0 # macro +regCP_ME1_PIPE_PRIORITY_CNTS = 0x1099 # macro +regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro +regCP_ME1_PIPE0_PRIORITY = 0x109a # macro +regCP_ME1_PIPE0_PRIORITY_BASE_IDX = 0 # macro +regCP_ME1_PIPE1_PRIORITY = 0x109b # macro +regCP_ME1_PIPE1_PRIORITY_BASE_IDX = 0 # macro +regCP_ME1_PIPE2_PRIORITY = 0x109c # macro +regCP_ME1_PIPE2_PRIORITY_BASE_IDX = 0 # macro +regCP_ME1_PIPE3_PRIORITY = 0x109d # macro +regCP_ME1_PIPE3_PRIORITY_BASE_IDX = 0 # macro +regCP_ME2_PIPE_PRIORITY_CNTS = 0x109e # macro +regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro +regCP_ME2_PIPE0_PRIORITY = 0x109f # macro +regCP_ME2_PIPE0_PRIORITY_BASE_IDX = 0 # macro +regCP_ME2_PIPE1_PRIORITY = 0x10a0 # macro +regCP_ME2_PIPE1_PRIORITY_BASE_IDX = 0 # macro +regCP_ME2_PIPE2_PRIORITY = 0x10a1 # macro +regCP_ME2_PIPE2_PRIORITY_BASE_IDX = 0 # macro +regCP_ME2_PIPE3_PRIORITY = 0x10a2 # macro +regCP_ME2_PIPE3_PRIORITY_BASE_IDX = 0 # macro +regCP_CE_PRGRM_CNTR_START = 0x10a3 # macro +regCP_CE_PRGRM_CNTR_START_BASE_IDX = 0 # macro +regCP_PFP_PRGRM_CNTR_START = 0x10a4 # macro +regCP_PFP_PRGRM_CNTR_START_BASE_IDX = 0 # macro +regCP_ME_PRGRM_CNTR_START = 0x10a5 # macro +regCP_ME_PRGRM_CNTR_START_BASE_IDX = 0 # macro +regCP_MEC1_PRGRM_CNTR_START = 0x10a6 # macro +regCP_MEC1_PRGRM_CNTR_START_BASE_IDX = 0 # macro +regCP_MEC2_PRGRM_CNTR_START = 0x10a7 # macro +regCP_MEC2_PRGRM_CNTR_START_BASE_IDX = 0 # macro +regCP_CE_INTR_ROUTINE_START = 0x10a8 # macro +regCP_CE_INTR_ROUTINE_START_BASE_IDX = 0 # macro +regCP_PFP_INTR_ROUTINE_START = 0x10a9 # macro +regCP_PFP_INTR_ROUTINE_START_BASE_IDX = 0 # macro +regCP_ME_INTR_ROUTINE_START = 0x10aa # macro +regCP_ME_INTR_ROUTINE_START_BASE_IDX = 0 # macro +regCP_MEC1_INTR_ROUTINE_START = 0x10ab # macro +regCP_MEC1_INTR_ROUTINE_START_BASE_IDX = 0 # macro +regCP_MEC2_INTR_ROUTINE_START = 0x10ac # macro +regCP_MEC2_INTR_ROUTINE_START_BASE_IDX = 0 # macro +regCP_CONTEXT_CNTL = 0x10ad # macro +regCP_CONTEXT_CNTL_BASE_IDX = 0 # macro +regCP_MAX_CONTEXT = 0x10ae # macro +regCP_MAX_CONTEXT_BASE_IDX = 0 # macro +regCP_IQ_WAIT_TIME1 = 0x10af # macro +regCP_IQ_WAIT_TIME1_BASE_IDX = 0 # macro +regCP_IQ_WAIT_TIME2 = 0x10b0 # macro +regCP_IQ_WAIT_TIME2_BASE_IDX = 0 # macro +regCP_RB0_BASE_HI = 0x10b1 # macro +regCP_RB0_BASE_HI_BASE_IDX = 0 # macro +regCP_RB1_BASE_HI = 0x10b2 # macro +regCP_RB1_BASE_HI_BASE_IDX = 0 # macro +regCP_VMID_RESET = 0x10b3 # macro +regCP_VMID_RESET_BASE_IDX = 0 # macro +regCPC_INT_CNTL = 0x10b4 # macro +regCPC_INT_CNTL_BASE_IDX = 0 # macro +regCPC_INT_STATUS = 0x10b5 # macro +regCPC_INT_STATUS_BASE_IDX = 0 # macro +regCP_VMID_PREEMPT = 0x10b6 # macro +regCP_VMID_PREEMPT_BASE_IDX = 0 # macro +regCPC_INT_CNTX_ID = 0x10b7 # macro +regCPC_INT_CNTX_ID_BASE_IDX = 0 # macro +regCP_PQ_STATUS = 0x10b8 # macro +regCP_PQ_STATUS_BASE_IDX = 0 # macro +regCP_CPC_IC_BASE_LO = 0x10b9 # macro +regCP_CPC_IC_BASE_LO_BASE_IDX = 0 # macro +regCP_CPC_IC_BASE_HI = 0x10ba # macro +regCP_CPC_IC_BASE_HI_BASE_IDX = 0 # macro +regCP_CPC_IC_BASE_CNTL = 0x10bb # macro +regCP_CPC_IC_BASE_CNTL_BASE_IDX = 0 # macro +regCP_CPC_IC_OP_CNTL = 0x10bc # macro +regCP_CPC_IC_OP_CNTL_BASE_IDX = 0 # macro +regCP_MEC1_F32_INT_DIS = 0x10bd # macro +regCP_MEC1_F32_INT_DIS_BASE_IDX = 0 # macro +regCP_MEC2_F32_INT_DIS = 0x10be # macro +regCP_MEC2_F32_INT_DIS_BASE_IDX = 0 # macro +regCP_VMID_STATUS = 0x10bf # macro +regCP_VMID_STATUS_BASE_IDX = 0 # macro +regCPC_UE_ERR_STATUS_LO = 0x10e0 # macro +regCPC_UE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regCPC_UE_ERR_STATUS_HI = 0x10e1 # macro +regCPC_UE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regCPC_CE_ERR_STATUS_LO = 0x10e2 # macro +regCPC_CE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regCPC_CE_ERR_STATUS_HI = 0x10e3 # macro +regCPC_CE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regCPF_UE_ERR_STATUS_LO = 0x10e4 # macro +regCPF_UE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regCPF_UE_ERR_STATUS_HI = 0x10e5 # macro +regCPF_UE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regCPF_CE_ERR_STATUS_LO = 0x10e6 # macro +regCPF_CE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regCPF_CE_ERR_STATUS_HI = 0x10e7 # macro +regCPF_CE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regCPG_UE_ERR_STATUS_LO = 0x10e8 # macro +regCPG_UE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regCPG_UE_ERR_STATUS_HI = 0x10e9 # macro +regCPG_UE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regCPG_CE_ERR_STATUS_LO = 0x10ea # macro +regCPG_CE_ERR_STATUS_LO_BASE_IDX = 0 # macro +regCPG_CE_ERR_STATUS_HI = 0x10eb # macro +regCPG_CE_ERR_STATUS_HI_BASE_IDX = 0 # macro +regCP_RB_DOORBELL_CONTROL_SCH_0 = 0x1180 # macro +regCP_RB_DOORBELL_CONTROL_SCH_0_BASE_IDX = 0 # macro +regCP_RB_DOORBELL_CONTROL_SCH_1 = 0x1181 # macro +regCP_RB_DOORBELL_CONTROL_SCH_1_BASE_IDX = 0 # macro +regCP_RB_DOORBELL_CONTROL_SCH_2 = 0x1182 # macro +regCP_RB_DOORBELL_CONTROL_SCH_2_BASE_IDX = 0 # macro +regCP_RB_DOORBELL_CONTROL_SCH_3 = 0x1183 # macro +regCP_RB_DOORBELL_CONTROL_SCH_3_BASE_IDX = 0 # macro +regCP_RB_DOORBELL_CONTROL_SCH_4 = 0x1184 # macro +regCP_RB_DOORBELL_CONTROL_SCH_4_BASE_IDX = 0 # macro +regCP_RB_DOORBELL_CONTROL_SCH_5 = 0x1185 # macro +regCP_RB_DOORBELL_CONTROL_SCH_5_BASE_IDX = 0 # macro +regCP_RB_DOORBELL_CONTROL_SCH_6 = 0x1186 # macro +regCP_RB_DOORBELL_CONTROL_SCH_6_BASE_IDX = 0 # macro +regCP_RB_DOORBELL_CONTROL_SCH_7 = 0x1187 # macro +regCP_RB_DOORBELL_CONTROL_SCH_7_BASE_IDX = 0 # macro +regCP_RB_DOORBELL_CLEAR = 0x1188 # macro +regCP_RB_DOORBELL_CLEAR_BASE_IDX = 0 # macro +regCP_CPF_DSM_CNTL = 0x1194 # macro +regCP_CPF_DSM_CNTL_BASE_IDX = 0 # macro +regCP_CPG_DSM_CNTL = 0x1195 # macro +regCP_CPG_DSM_CNTL_BASE_IDX = 0 # macro +regCP_CPC_DSM_CNTL = 0x1196 # macro +regCP_CPC_DSM_CNTL_BASE_IDX = 0 # macro +regCP_CPF_DSM_CNTL2 = 0x1197 # macro +regCP_CPF_DSM_CNTL2_BASE_IDX = 0 # macro +regCP_CPG_DSM_CNTL2 = 0x1198 # macro +regCP_CPG_DSM_CNTL2_BASE_IDX = 0 # macro +regCP_CPC_DSM_CNTL2 = 0x1199 # macro +regCP_CPC_DSM_CNTL2_BASE_IDX = 0 # macro +regCP_CPF_DSM_CNTL2A = 0x119a # macro +regCP_CPF_DSM_CNTL2A_BASE_IDX = 0 # macro +regCP_CPG_DSM_CNTL2A = 0x119b # macro +regCP_CPG_DSM_CNTL2A_BASE_IDX = 0 # macro +regCP_CPC_DSM_CNTL2A = 0x119c # macro +regCP_CPC_DSM_CNTL2A_BASE_IDX = 0 # macro +regCP_EDC_FUE_CNTL = 0x119d # macro +regCP_EDC_FUE_CNTL_BASE_IDX = 0 # macro +regCP_GFX_MQD_CONTROL = 0x11a0 # macro +regCP_GFX_MQD_CONTROL_BASE_IDX = 0 # macro +regCP_GFX_MQD_BASE_ADDR = 0x11a1 # macro +regCP_GFX_MQD_BASE_ADDR_BASE_IDX = 0 # macro +regCP_GFX_MQD_BASE_ADDR_HI = 0x11a2 # macro +regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX = 0 # macro +regCP_RB_STATUS = 0x11a3 # macro +regCP_RB_STATUS_BASE_IDX = 0 # macro +regCPG_UTCL1_STATUS = 0x11b4 # macro +regCPG_UTCL1_STATUS_BASE_IDX = 0 # macro +regCPC_UTCL1_STATUS = 0x11b5 # macro +regCPC_UTCL1_STATUS_BASE_IDX = 0 # macro +regCPF_UTCL1_STATUS = 0x11b6 # macro +regCPF_UTCL1_STATUS_BASE_IDX = 0 # macro +regCP_SD_CNTL = 0x11b7 # macro +regCP_SD_CNTL_BASE_IDX = 0 # macro +regCP_SOFT_RESET_CNTL = 0x11b9 # macro +regCP_SOFT_RESET_CNTL_BASE_IDX = 0 # macro +regCP_CPC_GFX_CNTL = 0x11ba # macro +regCP_CPC_GFX_CNTL_BASE_IDX = 0 # macro +regSPI_ARB_PRIORITY = 0x11c0 # macro +regSPI_ARB_PRIORITY_BASE_IDX = 0 # macro +regSPI_ARB_CYCLES_0 = 0x11c1 # macro +regSPI_ARB_CYCLES_0_BASE_IDX = 0 # macro +regSPI_ARB_CYCLES_1 = 0x11c2 # macro +regSPI_ARB_CYCLES_1_BASE_IDX = 0 # macro +regSPI_CDBG_SYS_GFX = 0x11c3 # macro +regSPI_CDBG_SYS_GFX_BASE_IDX = 0 # macro +regSPI_CDBG_SYS_HP3D = 0x11c4 # macro +regSPI_CDBG_SYS_HP3D_BASE_IDX = 0 # macro +regSPI_CDBG_SYS_CS0 = 0x11c5 # macro +regSPI_CDBG_SYS_CS0_BASE_IDX = 0 # macro +regSPI_CDBG_SYS_CS1 = 0x11c6 # macro +regSPI_CDBG_SYS_CS1_BASE_IDX = 0 # macro +regSPI_WCL_PIPE_PERCENT_GFX = 0x11c7 # macro +regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX = 0 # macro +regSPI_WCL_PIPE_PERCENT_HP3D = 0x11c8 # macro +regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX = 0 # macro +regSPI_WCL_PIPE_PERCENT_CS0 = 0x11c9 # macro +regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX = 0 # macro +regSPI_WCL_PIPE_PERCENT_CS1 = 0x11ca # macro +regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX = 0 # macro +regSPI_WCL_PIPE_PERCENT_CS2 = 0x11cb # macro +regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX = 0 # macro +regSPI_WCL_PIPE_PERCENT_CS3 = 0x11cc # macro +regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX = 0 # macro +regSPI_WCL_PIPE_PERCENT_CS4 = 0x11cd # macro +regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX = 0 # macro +regSPI_WCL_PIPE_PERCENT_CS5 = 0x11ce # macro +regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX = 0 # macro +regSPI_WCL_PIPE_PERCENT_CS6 = 0x11cf # macro +regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX = 0 # macro +regSPI_WCL_PIPE_PERCENT_CS7 = 0x11d0 # macro +regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX = 0 # macro +regSPI_GDBG_WAVE_CNTL = 0x11d1 # macro +regSPI_GDBG_WAVE_CNTL_BASE_IDX = 0 # macro +regSPI_GDBG_TRAP_CONFIG = 0x11d2 # macro +regSPI_GDBG_TRAP_CONFIG_BASE_IDX = 0 # macro +regSPI_GDBG_PER_VMID_CNTL = 0x11d3 # macro +regSPI_GDBG_PER_VMID_CNTL_BASE_IDX = 0 # macro +regSPI_GDBG_WAVE_CNTL3 = 0x11d5 # macro +regSPI_GDBG_WAVE_CNTL3_BASE_IDX = 0 # macro +regSPI_SCRATCH_ADDR_CHECK = 0x11d8 # macro +regSPI_SCRATCH_ADDR_CHECK_BASE_IDX = 0 # macro +regSPI_SCRATCH_ADDR_STATUS = 0x11d9 # macro +regSPI_SCRATCH_ADDR_STATUS_BASE_IDX = 0 # macro +regSPI_RESET_DEBUG = 0x11da # macro +regSPI_RESET_DEBUG_BASE_IDX = 0 # macro +regSPI_COMPUTE_QUEUE_RESET = 0x11db # macro +regSPI_COMPUTE_QUEUE_RESET_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_CU_0 = 0x11dc # macro +regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_CU_1 = 0x11dd # macro +regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_CU_2 = 0x11de # macro +regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_CU_3 = 0x11df # macro +regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_CU_4 = 0x11e0 # macro +regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_CU_5 = 0x11e1 # macro +regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_CU_6 = 0x11e2 # macro +regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_CU_7 = 0x11e3 # macro +regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_CU_8 = 0x11e4 # macro +regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_CU_9 = 0x11e5 # macro +regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_EN_CU_0 = 0x11e6 # macro +regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_EN_CU_1 = 0x11e7 # macro +regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_EN_CU_2 = 0x11e8 # macro +regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_EN_CU_3 = 0x11e9 # macro +regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_EN_CU_4 = 0x11ea # macro +regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_EN_CU_5 = 0x11eb # macro +regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_EN_CU_6 = 0x11ec # macro +regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_EN_CU_7 = 0x11ed # macro +regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_EN_CU_8 = 0x11ee # macro +regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_EN_CU_9 = 0x11ef # macro +regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_CU_10 = 0x11f0 # macro +regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_CU_11 = 0x11f1 # macro +regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_EN_CU_10 = 0x11f2 # macro +regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_EN_CU_11 = 0x11f3 # macro +regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_CU_12 = 0x11f4 # macro +regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_CU_13 = 0x11f5 # macro +regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_CU_14 = 0x11f6 # macro +regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_CU_15 = 0x11f7 # macro +regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_EN_CU_12 = 0x11f8 # macro +regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_EN_CU_13 = 0x11f9 # macro +regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_EN_CU_14 = 0x11fa # macro +regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX = 0 # macro +regSPI_RESOURCE_RESERVE_EN_CU_15 = 0x11fb # macro +regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX = 0 # macro +regSPI_COMPUTE_WF_CTX_SAVE = 0x11fc # macro +regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX = 0 # macro +regSPI_ARB_CNTL_0 = 0x11fd # macro +regSPI_ARB_CNTL_0_BASE_IDX = 0 # macro +regCP_HQD_GFX_CONTROL = 0x123e # macro +regCP_HQD_GFX_CONTROL_BASE_IDX = 0 # macro +regCP_HQD_GFX_STATUS = 0x123f # macro +regCP_HQD_GFX_STATUS_BASE_IDX = 0 # macro +regCP_HPD_ROQ_OFFSETS = 0x1240 # macro +regCP_HPD_ROQ_OFFSETS_BASE_IDX = 0 # macro +regCP_HPD_STATUS0 = 0x1241 # macro +regCP_HPD_STATUS0_BASE_IDX = 0 # macro +regCP_HPD_UTCL1_CNTL = 0x1242 # macro +regCP_HPD_UTCL1_CNTL_BASE_IDX = 0 # macro +regCP_HPD_UTCL1_ERROR = 0x1243 # macro +regCP_HPD_UTCL1_ERROR_BASE_IDX = 0 # macro +regCP_HPD_UTCL1_ERROR_ADDR = 0x1244 # macro +regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX = 0 # macro +regCP_MQD_BASE_ADDR = 0x1245 # macro +regCP_MQD_BASE_ADDR_BASE_IDX = 0 # macro +regCP_MQD_BASE_ADDR_HI = 0x1246 # macro +regCP_MQD_BASE_ADDR_HI_BASE_IDX = 0 # macro +regCP_HQD_ACTIVE = 0x1247 # macro +regCP_HQD_ACTIVE_BASE_IDX = 0 # macro +regCP_HQD_VMID = 0x1248 # macro +regCP_HQD_VMID_BASE_IDX = 0 # macro +regCP_HQD_PERSISTENT_STATE = 0x1249 # macro +regCP_HQD_PERSISTENT_STATE_BASE_IDX = 0 # macro +regCP_HQD_PIPE_PRIORITY = 0x124a # macro +regCP_HQD_PIPE_PRIORITY_BASE_IDX = 0 # macro +regCP_HQD_QUEUE_PRIORITY = 0x124b # macro +regCP_HQD_QUEUE_PRIORITY_BASE_IDX = 0 # macro +regCP_HQD_QUANTUM = 0x124c # macro +regCP_HQD_QUANTUM_BASE_IDX = 0 # macro +regCP_HQD_PQ_BASE = 0x124d # macro +regCP_HQD_PQ_BASE_BASE_IDX = 0 # macro +regCP_HQD_PQ_BASE_HI = 0x124e # macro +regCP_HQD_PQ_BASE_HI_BASE_IDX = 0 # macro +regCP_HQD_PQ_RPTR = 0x124f # macro +regCP_HQD_PQ_RPTR_BASE_IDX = 0 # macro +regCP_HQD_PQ_RPTR_REPORT_ADDR = 0x1250 # macro +regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX = 0 # macro +regCP_HQD_PQ_RPTR_REPORT_ADDR_HI = 0x1251 # macro +regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX = 0 # macro +regCP_HQD_PQ_WPTR_POLL_ADDR = 0x1252 # macro +regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX = 0 # macro +regCP_HQD_PQ_WPTR_POLL_ADDR_HI = 0x1253 # macro +regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +regCP_HQD_PQ_DOORBELL_CONTROL = 0x1254 # macro +regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX = 0 # macro +regCP_HQD_PQ_CONTROL = 0x1256 # macro +regCP_HQD_PQ_CONTROL_BASE_IDX = 0 # macro +regCP_HQD_IB_BASE_ADDR = 0x1257 # macro +regCP_HQD_IB_BASE_ADDR_BASE_IDX = 0 # macro +regCP_HQD_IB_BASE_ADDR_HI = 0x1258 # macro +regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX = 0 # macro +regCP_HQD_IB_RPTR = 0x1259 # macro +regCP_HQD_IB_RPTR_BASE_IDX = 0 # macro +regCP_HQD_IB_CONTROL = 0x125a # macro +regCP_HQD_IB_CONTROL_BASE_IDX = 0 # macro +regCP_HQD_IQ_TIMER = 0x125b # macro +regCP_HQD_IQ_TIMER_BASE_IDX = 0 # macro +regCP_HQD_IQ_RPTR = 0x125c # macro +regCP_HQD_IQ_RPTR_BASE_IDX = 0 # macro +regCP_HQD_DEQUEUE_REQUEST = 0x125d # macro +regCP_HQD_DEQUEUE_REQUEST_BASE_IDX = 0 # macro +regCP_HQD_DMA_OFFLOAD = 0x125e # macro +regCP_HQD_DMA_OFFLOAD_BASE_IDX = 0 # macro +regCP_HQD_OFFLOAD = 0x125e # macro +regCP_HQD_OFFLOAD_BASE_IDX = 0 # macro +regCP_HQD_SEMA_CMD = 0x125f # macro +regCP_HQD_SEMA_CMD_BASE_IDX = 0 # macro +regCP_HQD_MSG_TYPE = 0x1260 # macro +regCP_HQD_MSG_TYPE_BASE_IDX = 0 # macro +regCP_HQD_ATOMIC0_PREOP_LO = 0x1261 # macro +regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX = 0 # macro +regCP_HQD_ATOMIC0_PREOP_HI = 0x1262 # macro +regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX = 0 # macro +regCP_HQD_ATOMIC1_PREOP_LO = 0x1263 # macro +regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX = 0 # macro +regCP_HQD_ATOMIC1_PREOP_HI = 0x1264 # macro +regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX = 0 # macro +regCP_HQD_HQ_SCHEDULER0 = 0x1265 # macro +regCP_HQD_HQ_SCHEDULER0_BASE_IDX = 0 # macro +regCP_HQD_HQ_STATUS0 = 0x1265 # macro +regCP_HQD_HQ_STATUS0_BASE_IDX = 0 # macro +regCP_HQD_HQ_CONTROL0 = 0x1266 # macro +regCP_HQD_HQ_CONTROL0_BASE_IDX = 0 # macro +regCP_HQD_HQ_SCHEDULER1 = 0x1266 # macro +regCP_HQD_HQ_SCHEDULER1_BASE_IDX = 0 # macro +regCP_MQD_CONTROL = 0x1267 # macro +regCP_MQD_CONTROL_BASE_IDX = 0 # macro +regCP_HQD_HQ_STATUS1 = 0x1268 # macro +regCP_HQD_HQ_STATUS1_BASE_IDX = 0 # macro +regCP_HQD_HQ_CONTROL1 = 0x1269 # macro +regCP_HQD_HQ_CONTROL1_BASE_IDX = 0 # macro +regCP_HQD_EOP_BASE_ADDR = 0x126a # macro +regCP_HQD_EOP_BASE_ADDR_BASE_IDX = 0 # macro +regCP_HQD_EOP_BASE_ADDR_HI = 0x126b # macro +regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX = 0 # macro +regCP_HQD_EOP_CONTROL = 0x126c # macro +regCP_HQD_EOP_CONTROL_BASE_IDX = 0 # macro +regCP_HQD_EOP_RPTR = 0x126d # macro +regCP_HQD_EOP_RPTR_BASE_IDX = 0 # macro +regCP_HQD_EOP_WPTR = 0x126e # macro +regCP_HQD_EOP_WPTR_BASE_IDX = 0 # macro +regCP_HQD_EOP_EVENTS = 0x126f # macro +regCP_HQD_EOP_EVENTS_BASE_IDX = 0 # macro +regCP_HQD_CTX_SAVE_BASE_ADDR_LO = 0x1270 # macro +regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX = 0 # macro +regCP_HQD_CTX_SAVE_BASE_ADDR_HI = 0x1271 # macro +regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX = 0 # macro +regCP_HQD_CTX_SAVE_CONTROL = 0x1272 # macro +regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX = 0 # macro +regCP_HQD_CNTL_STACK_OFFSET = 0x1273 # macro +regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro +regCP_HQD_CNTL_STACK_SIZE = 0x1274 # macro +regCP_HQD_CNTL_STACK_SIZE_BASE_IDX = 0 # macro +regCP_HQD_WG_STATE_OFFSET = 0x1275 # macro +regCP_HQD_WG_STATE_OFFSET_BASE_IDX = 0 # macro +regCP_HQD_CTX_SAVE_SIZE = 0x1276 # macro +regCP_HQD_CTX_SAVE_SIZE_BASE_IDX = 0 # macro +regCP_HQD_GDS_RESOURCE_STATE = 0x1277 # macro +regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX = 0 # macro +regCP_HQD_ERROR = 0x1278 # macro +regCP_HQD_ERROR_BASE_IDX = 0 # macro +regCP_HQD_EOP_WPTR_MEM = 0x1279 # macro +regCP_HQD_EOP_WPTR_MEM_BASE_IDX = 0 # macro +regCP_HQD_AQL_CONTROL = 0x127a # macro +regCP_HQD_AQL_CONTROL_BASE_IDX = 0 # macro +regCP_HQD_PQ_WPTR_LO = 0x127b # macro +regCP_HQD_PQ_WPTR_LO_BASE_IDX = 0 # macro +regCP_HQD_PQ_WPTR_HI = 0x127c # macro +regCP_HQD_PQ_WPTR_HI_BASE_IDX = 0 # macro +regCP_HQD_AQL_CONTROL_1 = 0x127d # macro +regCP_HQD_AQL_CONTROL_1_BASE_IDX = 0 # macro +regCP_HQD_AQL_DISPATCH_ID = 0x127e # macro +regCP_HQD_AQL_DISPATCH_ID_BASE_IDX = 0 # macro +regCP_HQD_AQL_DISPATCH_ID_HI = 0x127f # macro +regCP_HQD_AQL_DISPATCH_ID_HI_BASE_IDX = 0 # macro +regTCP_WATCH0_ADDR_H = 0x12a0 # macro +regTCP_WATCH0_ADDR_H_BASE_IDX = 0 # macro +regTCP_WATCH0_ADDR_L = 0x12a1 # macro +regTCP_WATCH0_ADDR_L_BASE_IDX = 0 # macro +regTCP_WATCH0_CNTL = 0x12a2 # macro +regTCP_WATCH0_CNTL_BASE_IDX = 0 # macro +regTCP_WATCH1_ADDR_H = 0x12a3 # macro +regTCP_WATCH1_ADDR_H_BASE_IDX = 0 # macro +regTCP_WATCH1_ADDR_L = 0x12a4 # macro +regTCP_WATCH1_ADDR_L_BASE_IDX = 0 # macro +regTCP_WATCH1_CNTL = 0x12a5 # macro +regTCP_WATCH1_CNTL_BASE_IDX = 0 # macro +regTCP_WATCH2_ADDR_H = 0x12a6 # macro +regTCP_WATCH2_ADDR_H_BASE_IDX = 0 # macro +regTCP_WATCH2_ADDR_L = 0x12a7 # macro +regTCP_WATCH2_ADDR_L_BASE_IDX = 0 # macro +regTCP_WATCH2_CNTL = 0x12a8 # macro +regTCP_WATCH2_CNTL_BASE_IDX = 0 # macro +regTCP_WATCH3_ADDR_H = 0x12a9 # macro +regTCP_WATCH3_ADDR_H_BASE_IDX = 0 # macro +regTCP_WATCH3_ADDR_L = 0x12aa # macro +regTCP_WATCH3_ADDR_L_BASE_IDX = 0 # macro +regTCP_WATCH3_CNTL = 0x12ab # macro +regTCP_WATCH3_CNTL_BASE_IDX = 0 # macro +regTCP_GATCL1_CNTL = 0x12b0 # macro +regTCP_GATCL1_CNTL_BASE_IDX = 0 # macro +regTCP_ATC_EDC_GATCL1_CNT = 0x12b1 # macro +regTCP_ATC_EDC_GATCL1_CNT_BASE_IDX = 0 # macro +regTCP_GATCL1_DSM_CNTL = 0x12b2 # macro +regTCP_GATCL1_DSM_CNTL_BASE_IDX = 0 # macro +regTCP_DSM_CNTL = 0x12b3 # macro +regTCP_DSM_CNTL_BASE_IDX = 0 # macro +regTCP_CNTL2 = 0x12b4 # macro +regTCP_CNTL2_BASE_IDX = 0 # macro +regTCP_UTCL1_CNTL1 = 0x12b5 # macro +regTCP_UTCL1_CNTL1_BASE_IDX = 0 # macro +regTCP_UTCL1_CNTL2 = 0x12b6 # macro +regTCP_UTCL1_CNTL2_BASE_IDX = 0 # macro +regTCP_UTCL1_STATUS = 0x12b7 # macro +regTCP_UTCL1_STATUS_BASE_IDX = 0 # macro +regTCP_DSM_CNTL2 = 0x12b8 # macro +regTCP_DSM_CNTL2_BASE_IDX = 0 # macro +regTCP_PERFCOUNTER_FILTER = 0x12b9 # macro +regTCP_PERFCOUNTER_FILTER_BASE_IDX = 0 # macro +regTCP_PERFCOUNTER_FILTER_EN = 0x12ba # macro +regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX = 0 # macro +regGDS_VMID0_BASE = 0x1300 # macro +regGDS_VMID0_BASE_BASE_IDX = 0 # macro +regGDS_VMID0_SIZE = 0x1301 # macro +regGDS_VMID0_SIZE_BASE_IDX = 0 # macro +regGDS_VMID1_BASE = 0x1302 # macro +regGDS_VMID1_BASE_BASE_IDX = 0 # macro +regGDS_VMID1_SIZE = 0x1303 # macro +regGDS_VMID1_SIZE_BASE_IDX = 0 # macro +regGDS_VMID2_BASE = 0x1304 # macro +regGDS_VMID2_BASE_BASE_IDX = 0 # macro +regGDS_VMID2_SIZE = 0x1305 # macro +regGDS_VMID2_SIZE_BASE_IDX = 0 # macro +regGDS_VMID3_BASE = 0x1306 # macro +regGDS_VMID3_BASE_BASE_IDX = 0 # macro +regGDS_VMID3_SIZE = 0x1307 # macro +regGDS_VMID3_SIZE_BASE_IDX = 0 # macro +regGDS_VMID4_BASE = 0x1308 # macro +regGDS_VMID4_BASE_BASE_IDX = 0 # macro +regGDS_VMID4_SIZE = 0x1309 # macro +regGDS_VMID4_SIZE_BASE_IDX = 0 # macro +regGDS_VMID5_BASE = 0x130a # macro +regGDS_VMID5_BASE_BASE_IDX = 0 # macro +regGDS_VMID5_SIZE = 0x130b # macro +regGDS_VMID5_SIZE_BASE_IDX = 0 # macro +regGDS_VMID6_BASE = 0x130c # macro +regGDS_VMID6_BASE_BASE_IDX = 0 # macro +regGDS_VMID6_SIZE = 0x130d # macro +regGDS_VMID6_SIZE_BASE_IDX = 0 # macro +regGDS_VMID7_BASE = 0x130e # macro +regGDS_VMID7_BASE_BASE_IDX = 0 # macro +regGDS_VMID7_SIZE = 0x130f # macro +regGDS_VMID7_SIZE_BASE_IDX = 0 # macro +regGDS_VMID8_BASE = 0x1310 # macro +regGDS_VMID8_BASE_BASE_IDX = 0 # macro +regGDS_VMID8_SIZE = 0x1311 # macro +regGDS_VMID8_SIZE_BASE_IDX = 0 # macro +regGDS_VMID9_BASE = 0x1312 # macro +regGDS_VMID9_BASE_BASE_IDX = 0 # macro +regGDS_VMID9_SIZE = 0x1313 # macro +regGDS_VMID9_SIZE_BASE_IDX = 0 # macro +regGDS_VMID10_BASE = 0x1314 # macro +regGDS_VMID10_BASE_BASE_IDX = 0 # macro +regGDS_VMID10_SIZE = 0x1315 # macro +regGDS_VMID10_SIZE_BASE_IDX = 0 # macro +regGDS_VMID11_BASE = 0x1316 # macro +regGDS_VMID11_BASE_BASE_IDX = 0 # macro +regGDS_VMID11_SIZE = 0x1317 # macro +regGDS_VMID11_SIZE_BASE_IDX = 0 # macro +regGDS_VMID12_BASE = 0x1318 # macro +regGDS_VMID12_BASE_BASE_IDX = 0 # macro +regGDS_VMID12_SIZE = 0x1319 # macro +regGDS_VMID12_SIZE_BASE_IDX = 0 # macro +regGDS_VMID13_BASE = 0x131a # macro +regGDS_VMID13_BASE_BASE_IDX = 0 # macro +regGDS_VMID13_SIZE = 0x131b # macro +regGDS_VMID13_SIZE_BASE_IDX = 0 # macro +regGDS_VMID14_BASE = 0x131c # macro +regGDS_VMID14_BASE_BASE_IDX = 0 # macro +regGDS_VMID14_SIZE = 0x131d # macro +regGDS_VMID14_SIZE_BASE_IDX = 0 # macro +regGDS_VMID15_BASE = 0x131e # macro +regGDS_VMID15_BASE_BASE_IDX = 0 # macro +regGDS_VMID15_SIZE = 0x131f # macro +regGDS_VMID15_SIZE_BASE_IDX = 0 # macro +regGDS_GWS_VMID0 = 0x1320 # macro +regGDS_GWS_VMID0_BASE_IDX = 0 # macro +regGDS_GWS_VMID1 = 0x1321 # macro +regGDS_GWS_VMID1_BASE_IDX = 0 # macro +regGDS_GWS_VMID2 = 0x1322 # macro +regGDS_GWS_VMID2_BASE_IDX = 0 # macro +regGDS_GWS_VMID3 = 0x1323 # macro +regGDS_GWS_VMID3_BASE_IDX = 0 # macro +regGDS_GWS_VMID4 = 0x1324 # macro +regGDS_GWS_VMID4_BASE_IDX = 0 # macro +regGDS_GWS_VMID5 = 0x1325 # macro +regGDS_GWS_VMID5_BASE_IDX = 0 # macro +regGDS_GWS_VMID6 = 0x1326 # macro +regGDS_GWS_VMID6_BASE_IDX = 0 # macro +regGDS_GWS_VMID7 = 0x1327 # macro +regGDS_GWS_VMID7_BASE_IDX = 0 # macro +regGDS_GWS_VMID8 = 0x1328 # macro +regGDS_GWS_VMID8_BASE_IDX = 0 # macro +regGDS_GWS_VMID9 = 0x1329 # macro +regGDS_GWS_VMID9_BASE_IDX = 0 # macro +regGDS_GWS_VMID10 = 0x132a # macro +regGDS_GWS_VMID10_BASE_IDX = 0 # macro +regGDS_GWS_VMID11 = 0x132b # macro +regGDS_GWS_VMID11_BASE_IDX = 0 # macro +regGDS_GWS_VMID12 = 0x132c # macro +regGDS_GWS_VMID12_BASE_IDX = 0 # macro +regGDS_GWS_VMID13 = 0x132d # macro +regGDS_GWS_VMID13_BASE_IDX = 0 # macro +regGDS_GWS_VMID14 = 0x132e # macro +regGDS_GWS_VMID14_BASE_IDX = 0 # macro +regGDS_GWS_VMID15 = 0x132f # macro +regGDS_GWS_VMID15_BASE_IDX = 0 # macro +regGDS_OA_VMID0 = 0x1330 # macro +regGDS_OA_VMID0_BASE_IDX = 0 # macro +regGDS_OA_VMID1 = 0x1331 # macro +regGDS_OA_VMID1_BASE_IDX = 0 # macro +regGDS_OA_VMID2 = 0x1332 # macro +regGDS_OA_VMID2_BASE_IDX = 0 # macro +regGDS_OA_VMID3 = 0x1333 # macro +regGDS_OA_VMID3_BASE_IDX = 0 # macro +regGDS_OA_VMID4 = 0x1334 # macro +regGDS_OA_VMID4_BASE_IDX = 0 # macro +regGDS_OA_VMID5 = 0x1335 # macro +regGDS_OA_VMID5_BASE_IDX = 0 # macro +regGDS_OA_VMID6 = 0x1336 # macro +regGDS_OA_VMID6_BASE_IDX = 0 # macro +regGDS_OA_VMID7 = 0x1337 # macro +regGDS_OA_VMID7_BASE_IDX = 0 # macro +regGDS_OA_VMID8 = 0x1338 # macro +regGDS_OA_VMID8_BASE_IDX = 0 # macro +regGDS_OA_VMID9 = 0x1339 # macro +regGDS_OA_VMID9_BASE_IDX = 0 # macro +regGDS_OA_VMID10 = 0x133a # macro +regGDS_OA_VMID10_BASE_IDX = 0 # macro +regGDS_OA_VMID11 = 0x133b # macro +regGDS_OA_VMID11_BASE_IDX = 0 # macro +regGDS_OA_VMID12 = 0x133c # macro +regGDS_OA_VMID12_BASE_IDX = 0 # macro +regGDS_OA_VMID13 = 0x133d # macro +regGDS_OA_VMID13_BASE_IDX = 0 # macro +regGDS_OA_VMID14 = 0x133e # macro +regGDS_OA_VMID14_BASE_IDX = 0 # macro +regGDS_OA_VMID15 = 0x133f # macro +regGDS_OA_VMID15_BASE_IDX = 0 # macro +regGDS_GWS_RESET0 = 0x1344 # macro +regGDS_GWS_RESET0_BASE_IDX = 0 # macro +regGDS_GWS_RESET1 = 0x1345 # macro +regGDS_GWS_RESET1_BASE_IDX = 0 # macro +regGDS_GWS_RESOURCE_RESET = 0x1346 # macro +regGDS_GWS_RESOURCE_RESET_BASE_IDX = 0 # macro +regGDS_COMPUTE_MAX_WAVE_ID = 0x1348 # macro +regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX = 0 # macro +regGDS_OA_RESET_MASK = 0x1349 # macro +regGDS_OA_RESET_MASK_BASE_IDX = 0 # macro +regGDS_OA_RESET = 0x134a # macro +regGDS_OA_RESET_BASE_IDX = 0 # macro +regGDS_ENHANCE = 0x134b # macro +regGDS_ENHANCE_BASE_IDX = 0 # macro +regGDS_OA_CGPG_RESTORE = 0x134c # macro +regGDS_OA_CGPG_RESTORE_BASE_IDX = 0 # macro +regGDS_CS_CTXSW_STATUS = 0x134d # macro +regGDS_CS_CTXSW_STATUS_BASE_IDX = 0 # macro +regGDS_CS_CTXSW_CNT0 = 0x134e # macro +regGDS_CS_CTXSW_CNT0_BASE_IDX = 0 # macro +regGDS_CS_CTXSW_CNT1 = 0x134f # macro +regGDS_CS_CTXSW_CNT1_BASE_IDX = 0 # macro +regGDS_CS_CTXSW_CNT2 = 0x1350 # macro +regGDS_CS_CTXSW_CNT2_BASE_IDX = 0 # macro +regGDS_CS_CTXSW_CNT3 = 0x1351 # macro +regGDS_CS_CTXSW_CNT3_BASE_IDX = 0 # macro +regGDS_GFX_CTXSW_STATUS = 0x1352 # macro +regGDS_GFX_CTXSW_STATUS_BASE_IDX = 0 # macro +regGDS_VS_CTXSW_CNT0 = 0x1353 # macro +regGDS_VS_CTXSW_CNT0_BASE_IDX = 0 # macro +regGDS_VS_CTXSW_CNT1 = 0x1354 # macro +regGDS_VS_CTXSW_CNT1_BASE_IDX = 0 # macro +regGDS_VS_CTXSW_CNT2 = 0x1355 # macro +regGDS_VS_CTXSW_CNT2_BASE_IDX = 0 # macro +regGDS_VS_CTXSW_CNT3 = 0x1356 # macro +regGDS_VS_CTXSW_CNT3_BASE_IDX = 0 # macro +regGDS_PS0_CTXSW_CNT0 = 0x1357 # macro +regGDS_PS0_CTXSW_CNT0_BASE_IDX = 0 # macro +regGDS_PS0_CTXSW_CNT1 = 0x1358 # macro +regGDS_PS0_CTXSW_CNT1_BASE_IDX = 0 # macro +regGDS_PS0_CTXSW_CNT2 = 0x1359 # macro +regGDS_PS0_CTXSW_CNT2_BASE_IDX = 0 # macro +regGDS_PS0_CTXSW_CNT3 = 0x135a # macro +regGDS_PS0_CTXSW_CNT3_BASE_IDX = 0 # macro +regGDS_PS1_CTXSW_CNT0 = 0x135b # macro +regGDS_PS1_CTXSW_CNT0_BASE_IDX = 0 # macro +regGDS_PS1_CTXSW_CNT1 = 0x135c # macro +regGDS_PS1_CTXSW_CNT1_BASE_IDX = 0 # macro +regGDS_PS1_CTXSW_CNT2 = 0x135d # macro +regGDS_PS1_CTXSW_CNT2_BASE_IDX = 0 # macro +regGDS_PS1_CTXSW_CNT3 = 0x135e # macro +regGDS_PS1_CTXSW_CNT3_BASE_IDX = 0 # macro +regGDS_PS2_CTXSW_CNT0 = 0x135f # macro +regGDS_PS2_CTXSW_CNT0_BASE_IDX = 0 # macro +regGDS_PS2_CTXSW_CNT1 = 0x1360 # macro +regGDS_PS2_CTXSW_CNT1_BASE_IDX = 0 # macro +regGDS_PS2_CTXSW_CNT2 = 0x1361 # macro +regGDS_PS2_CTXSW_CNT2_BASE_IDX = 0 # macro +regGDS_PS2_CTXSW_CNT3 = 0x1362 # macro +regGDS_PS2_CTXSW_CNT3_BASE_IDX = 0 # macro +regGDS_PS3_CTXSW_CNT0 = 0x1363 # macro +regGDS_PS3_CTXSW_CNT0_BASE_IDX = 0 # macro +regGDS_PS3_CTXSW_CNT1 = 0x1364 # macro +regGDS_PS3_CTXSW_CNT1_BASE_IDX = 0 # macro +regGDS_PS3_CTXSW_CNT2 = 0x1365 # macro +regGDS_PS3_CTXSW_CNT2_BASE_IDX = 0 # macro +regGDS_PS3_CTXSW_CNT3 = 0x1366 # macro +regGDS_PS3_CTXSW_CNT3_BASE_IDX = 0 # macro +regGDS_PS4_CTXSW_CNT0 = 0x1367 # macro +regGDS_PS4_CTXSW_CNT0_BASE_IDX = 0 # macro +regGDS_PS4_CTXSW_CNT1 = 0x1368 # macro +regGDS_PS4_CTXSW_CNT1_BASE_IDX = 0 # macro +regGDS_PS4_CTXSW_CNT2 = 0x1369 # macro +regGDS_PS4_CTXSW_CNT2_BASE_IDX = 0 # macro +regGDS_PS4_CTXSW_CNT3 = 0x136a # macro +regGDS_PS4_CTXSW_CNT3_BASE_IDX = 0 # macro +regGDS_PS5_CTXSW_CNT0 = 0x136b # macro +regGDS_PS5_CTXSW_CNT0_BASE_IDX = 0 # macro +regGDS_PS5_CTXSW_CNT1 = 0x136c # macro +regGDS_PS5_CTXSW_CNT1_BASE_IDX = 0 # macro +regGDS_PS5_CTXSW_CNT2 = 0x136d # macro +regGDS_PS5_CTXSW_CNT2_BASE_IDX = 0 # macro +regGDS_PS5_CTXSW_CNT3 = 0x136e # macro +regGDS_PS5_CTXSW_CNT3_BASE_IDX = 0 # macro +regGDS_PS6_CTXSW_CNT0 = 0x136f # macro +regGDS_PS6_CTXSW_CNT0_BASE_IDX = 0 # macro +regGDS_PS6_CTXSW_CNT1 = 0x1370 # macro +regGDS_PS6_CTXSW_CNT1_BASE_IDX = 0 # macro +regGDS_PS6_CTXSW_CNT2 = 0x1371 # macro +regGDS_PS6_CTXSW_CNT2_BASE_IDX = 0 # macro +regGDS_PS6_CTXSW_CNT3 = 0x1372 # macro +regGDS_PS6_CTXSW_CNT3_BASE_IDX = 0 # macro +regGDS_PS7_CTXSW_CNT0 = 0x1373 # macro +regGDS_PS7_CTXSW_CNT0_BASE_IDX = 0 # macro +regGDS_PS7_CTXSW_CNT1 = 0x1374 # macro +regGDS_PS7_CTXSW_CNT1_BASE_IDX = 0 # macro +regGDS_PS7_CTXSW_CNT2 = 0x1375 # macro +regGDS_PS7_CTXSW_CNT2_BASE_IDX = 0 # macro +regGDS_PS7_CTXSW_CNT3 = 0x1376 # macro +regGDS_PS7_CTXSW_CNT3_BASE_IDX = 0 # macro +regGDS_GS_CTXSW_CNT0 = 0x1377 # macro +regGDS_GS_CTXSW_CNT0_BASE_IDX = 0 # macro +regGDS_GS_CTXSW_CNT1 = 0x1378 # macro +regGDS_GS_CTXSW_CNT1_BASE_IDX = 0 # macro +regGDS_GS_CTXSW_CNT2 = 0x1379 # macro +regGDS_GS_CTXSW_CNT2_BASE_IDX = 0 # macro +regGDS_GS_CTXSW_CNT3 = 0x137a # macro +regGDS_GS_CTXSW_CNT3_BASE_IDX = 0 # macro +regRAS_SIGNATURE_CONTROL = 0x1380 # macro +regRAS_SIGNATURE_CONTROL_BASE_IDX = 0 # macro +regRAS_SIGNATURE_MASK = 0x1381 # macro +regRAS_SIGNATURE_MASK_BASE_IDX = 0 # macro +regRAS_SX_SIGNATURE0 = 0x1382 # macro +regRAS_SX_SIGNATURE0_BASE_IDX = 0 # macro +regRAS_SX_SIGNATURE1 = 0x1383 # macro +regRAS_SX_SIGNATURE1_BASE_IDX = 0 # macro +regRAS_SX_SIGNATURE2 = 0x1384 # macro +regRAS_SX_SIGNATURE2_BASE_IDX = 0 # macro +regRAS_SX_SIGNATURE3 = 0x1385 # macro +regRAS_SX_SIGNATURE3_BASE_IDX = 0 # macro +regRAS_DB_SIGNATURE0 = 0x138b # macro +regRAS_DB_SIGNATURE0_BASE_IDX = 0 # macro +regRAS_PA_SIGNATURE0 = 0x138c # macro +regRAS_PA_SIGNATURE0_BASE_IDX = 0 # macro +regRAS_VGT_SIGNATURE0 = 0x138d # macro +regRAS_VGT_SIGNATURE0_BASE_IDX = 0 # macro +regRAS_SQ_SIGNATURE0 = 0x138e # macro +regRAS_SQ_SIGNATURE0_BASE_IDX = 0 # macro +regRAS_SC_SIGNATURE0 = 0x138f # macro +regRAS_SC_SIGNATURE0_BASE_IDX = 0 # macro +regRAS_SC_SIGNATURE1 = 0x1390 # macro +regRAS_SC_SIGNATURE1_BASE_IDX = 0 # macro +regRAS_SC_SIGNATURE2 = 0x1391 # macro +regRAS_SC_SIGNATURE2_BASE_IDX = 0 # macro +regRAS_SC_SIGNATURE3 = 0x1392 # macro +regRAS_SC_SIGNATURE3_BASE_IDX = 0 # macro +regRAS_SC_SIGNATURE4 = 0x1393 # macro +regRAS_SC_SIGNATURE4_BASE_IDX = 0 # macro +regRAS_SC_SIGNATURE5 = 0x1394 # macro +regRAS_SC_SIGNATURE5_BASE_IDX = 0 # macro +regRAS_SC_SIGNATURE6 = 0x1395 # macro +regRAS_SC_SIGNATURE6_BASE_IDX = 0 # macro +regRAS_SC_SIGNATURE7 = 0x1396 # macro +regRAS_SC_SIGNATURE7_BASE_IDX = 0 # macro +regRAS_IA_SIGNATURE0 = 0x1397 # macro +regRAS_IA_SIGNATURE0_BASE_IDX = 0 # macro +regRAS_IA_SIGNATURE1 = 0x1398 # macro +regRAS_IA_SIGNATURE1_BASE_IDX = 0 # macro +regRAS_SPI_SIGNATURE0 = 0x1399 # macro +regRAS_SPI_SIGNATURE0_BASE_IDX = 0 # macro +regRAS_SPI_SIGNATURE1 = 0x139a # macro +regRAS_SPI_SIGNATURE1_BASE_IDX = 0 # macro +regRAS_TA_SIGNATURE0 = 0x139b # macro +regRAS_TA_SIGNATURE0_BASE_IDX = 0 # macro +regRAS_TD_SIGNATURE0 = 0x139c # macro +regRAS_TD_SIGNATURE0_BASE_IDX = 0 # macro +regRAS_CB_SIGNATURE0 = 0x139d # macro +regRAS_CB_SIGNATURE0_BASE_IDX = 0 # macro +regRAS_BCI_SIGNATURE0 = 0x139e # macro +regRAS_BCI_SIGNATURE0_BASE_IDX = 0 # macro +regRAS_BCI_SIGNATURE1 = 0x139f # macro +regRAS_BCI_SIGNATURE1_BASE_IDX = 0 # macro +regRAS_TA_SIGNATURE1 = 0x13a0 # macro +regRAS_TA_SIGNATURE1_BASE_IDX = 0 # macro +regDB_RENDER_CONTROL = 0x0000 # macro +regDB_RENDER_CONTROL_BASE_IDX = 1 # macro +regDB_COUNT_CONTROL = 0x0001 # macro +regDB_COUNT_CONTROL_BASE_IDX = 1 # macro +regDB_DEPTH_VIEW = 0x0002 # macro +regDB_DEPTH_VIEW_BASE_IDX = 1 # macro +regDB_RENDER_OVERRIDE = 0x0003 # macro +regDB_RENDER_OVERRIDE_BASE_IDX = 1 # macro +regDB_RENDER_OVERRIDE2 = 0x0004 # macro +regDB_RENDER_OVERRIDE2_BASE_IDX = 1 # macro +regDB_HTILE_DATA_BASE = 0x0005 # macro +regDB_HTILE_DATA_BASE_BASE_IDX = 1 # macro +regDB_HTILE_DATA_BASE_HI = 0x0006 # macro +regDB_HTILE_DATA_BASE_HI_BASE_IDX = 1 # macro +regDB_DEPTH_SIZE = 0x0007 # macro +regDB_DEPTH_SIZE_BASE_IDX = 1 # macro +regDB_DEPTH_BOUNDS_MIN = 0x0008 # macro +regDB_DEPTH_BOUNDS_MIN_BASE_IDX = 1 # macro +regDB_DEPTH_BOUNDS_MAX = 0x0009 # macro +regDB_DEPTH_BOUNDS_MAX_BASE_IDX = 1 # macro +regDB_STENCIL_CLEAR = 0x000a # macro +regDB_STENCIL_CLEAR_BASE_IDX = 1 # macro +regDB_DEPTH_CLEAR = 0x000b # macro +regDB_DEPTH_CLEAR_BASE_IDX = 1 # macro +regPA_SC_SCREEN_SCISSOR_TL = 0x000c # macro +regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX = 1 # macro +regPA_SC_SCREEN_SCISSOR_BR = 0x000d # macro +regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX = 1 # macro +regDB_Z_INFO = 0x000e # macro +regDB_Z_INFO_BASE_IDX = 1 # macro +regDB_STENCIL_INFO = 0x000f # macro +regDB_STENCIL_INFO_BASE_IDX = 1 # macro +regDB_Z_READ_BASE = 0x0010 # macro +regDB_Z_READ_BASE_BASE_IDX = 1 # macro +regDB_Z_READ_BASE_HI = 0x0011 # macro +regDB_Z_READ_BASE_HI_BASE_IDX = 1 # macro +regDB_STENCIL_READ_BASE = 0x0012 # macro +regDB_STENCIL_READ_BASE_BASE_IDX = 1 # macro +regDB_STENCIL_READ_BASE_HI = 0x0013 # macro +regDB_STENCIL_READ_BASE_HI_BASE_IDX = 1 # macro +regDB_Z_WRITE_BASE = 0x0014 # macro +regDB_Z_WRITE_BASE_BASE_IDX = 1 # macro +regDB_Z_WRITE_BASE_HI = 0x0015 # macro +regDB_Z_WRITE_BASE_HI_BASE_IDX = 1 # macro +regDB_STENCIL_WRITE_BASE = 0x0016 # macro +regDB_STENCIL_WRITE_BASE_BASE_IDX = 1 # macro +regDB_STENCIL_WRITE_BASE_HI = 0x0017 # macro +regDB_STENCIL_WRITE_BASE_HI_BASE_IDX = 1 # macro +regDB_DFSM_CONTROL = 0x0018 # macro +regDB_DFSM_CONTROL_BASE_IDX = 1 # macro +regDB_Z_INFO2 = 0x001a # macro +regDB_Z_INFO2_BASE_IDX = 1 # macro +regDB_STENCIL_INFO2 = 0x001b # macro +regDB_STENCIL_INFO2_BASE_IDX = 1 # macro +regCOHER_DEST_BASE_HI_0 = 0x007a # macro +regCOHER_DEST_BASE_HI_0_BASE_IDX = 1 # macro +regCOHER_DEST_BASE_HI_1 = 0x007b # macro +regCOHER_DEST_BASE_HI_1_BASE_IDX = 1 # macro +regCOHER_DEST_BASE_HI_2 = 0x007c # macro +regCOHER_DEST_BASE_HI_2_BASE_IDX = 1 # macro +regCOHER_DEST_BASE_HI_3 = 0x007d # macro +regCOHER_DEST_BASE_HI_3_BASE_IDX = 1 # macro +regCOHER_DEST_BASE_2 = 0x007e # macro +regCOHER_DEST_BASE_2_BASE_IDX = 1 # macro +regCOHER_DEST_BASE_3 = 0x007f # macro +regCOHER_DEST_BASE_3_BASE_IDX = 1 # macro +regPA_SC_WINDOW_OFFSET = 0x0080 # macro +regPA_SC_WINDOW_OFFSET_BASE_IDX = 1 # macro +regPA_SC_WINDOW_SCISSOR_TL = 0x0081 # macro +regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX = 1 # macro +regPA_SC_WINDOW_SCISSOR_BR = 0x0082 # macro +regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX = 1 # macro +regPA_SC_CLIPRECT_RULE = 0x0083 # macro +regPA_SC_CLIPRECT_RULE_BASE_IDX = 1 # macro +regPA_SC_CLIPRECT_0_TL = 0x0084 # macro +regPA_SC_CLIPRECT_0_TL_BASE_IDX = 1 # macro +regPA_SC_CLIPRECT_0_BR = 0x0085 # macro +regPA_SC_CLIPRECT_0_BR_BASE_IDX = 1 # macro +regPA_SC_CLIPRECT_1_TL = 0x0086 # macro +regPA_SC_CLIPRECT_1_TL_BASE_IDX = 1 # macro +regPA_SC_CLIPRECT_1_BR = 0x0087 # macro +regPA_SC_CLIPRECT_1_BR_BASE_IDX = 1 # macro +regPA_SC_CLIPRECT_2_TL = 0x0088 # macro +regPA_SC_CLIPRECT_2_TL_BASE_IDX = 1 # macro +regPA_SC_CLIPRECT_2_BR = 0x0089 # macro +regPA_SC_CLIPRECT_2_BR_BASE_IDX = 1 # macro +regPA_SC_CLIPRECT_3_TL = 0x008a # macro +regPA_SC_CLIPRECT_3_TL_BASE_IDX = 1 # macro +regPA_SC_CLIPRECT_3_BR = 0x008b # macro +regPA_SC_CLIPRECT_3_BR_BASE_IDX = 1 # macro +regPA_SC_EDGERULE = 0x008c # macro +regPA_SC_EDGERULE_BASE_IDX = 1 # macro +regPA_SU_HARDWARE_SCREEN_OFFSET = 0x008d # macro +regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX = 1 # macro +regCB_TARGET_MASK = 0x008e # macro +regCB_TARGET_MASK_BASE_IDX = 1 # macro +regCB_SHADER_MASK = 0x008f # macro +regCB_SHADER_MASK_BASE_IDX = 1 # macro +regPA_SC_GENERIC_SCISSOR_TL = 0x0090 # macro +regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX = 1 # macro +regPA_SC_GENERIC_SCISSOR_BR = 0x0091 # macro +regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX = 1 # macro +regCOHER_DEST_BASE_0 = 0x0092 # macro +regCOHER_DEST_BASE_0_BASE_IDX = 1 # macro +regCOHER_DEST_BASE_1 = 0x0093 # macro +regCOHER_DEST_BASE_1_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_0_TL = 0x0094 # macro +regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_0_BR = 0x0095 # macro +regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_1_TL = 0x0096 # macro +regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_1_BR = 0x0097 # macro +regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_2_TL = 0x0098 # macro +regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_2_BR = 0x0099 # macro +regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_3_TL = 0x009a # macro +regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_3_BR = 0x009b # macro +regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_4_TL = 0x009c # macro +regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_4_BR = 0x009d # macro +regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_5_TL = 0x009e # macro +regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_5_BR = 0x009f # macro +regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_6_TL = 0x00a0 # macro +regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_6_BR = 0x00a1 # macro +regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_7_TL = 0x00a2 # macro +regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_7_BR = 0x00a3 # macro +regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_8_TL = 0x00a4 # macro +regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_8_BR = 0x00a5 # macro +regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_9_TL = 0x00a6 # macro +regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_9_BR = 0x00a7 # macro +regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_10_TL = 0x00a8 # macro +regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_10_BR = 0x00a9 # macro +regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_11_TL = 0x00aa # macro +regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_11_BR = 0x00ab # macro +regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_12_TL = 0x00ac # macro +regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_12_BR = 0x00ad # macro +regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_13_TL = 0x00ae # macro +regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_13_BR = 0x00af # macro +regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_14_TL = 0x00b0 # macro +regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_14_BR = 0x00b1 # macro +regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_15_TL = 0x00b2 # macro +regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX = 1 # macro +regPA_SC_VPORT_SCISSOR_15_BR = 0x00b3 # macro +regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_0 = 0x00b4 # macro +regPA_SC_VPORT_ZMIN_0_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_0 = 0x00b5 # macro +regPA_SC_VPORT_ZMAX_0_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_1 = 0x00b6 # macro +regPA_SC_VPORT_ZMIN_1_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_1 = 0x00b7 # macro +regPA_SC_VPORT_ZMAX_1_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_2 = 0x00b8 # macro +regPA_SC_VPORT_ZMIN_2_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_2 = 0x00b9 # macro +regPA_SC_VPORT_ZMAX_2_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_3 = 0x00ba # macro +regPA_SC_VPORT_ZMIN_3_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_3 = 0x00bb # macro +regPA_SC_VPORT_ZMAX_3_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_4 = 0x00bc # macro +regPA_SC_VPORT_ZMIN_4_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_4 = 0x00bd # macro +regPA_SC_VPORT_ZMAX_4_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_5 = 0x00be # macro +regPA_SC_VPORT_ZMIN_5_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_5 = 0x00bf # macro +regPA_SC_VPORT_ZMAX_5_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_6 = 0x00c0 # macro +regPA_SC_VPORT_ZMIN_6_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_6 = 0x00c1 # macro +regPA_SC_VPORT_ZMAX_6_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_7 = 0x00c2 # macro +regPA_SC_VPORT_ZMIN_7_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_7 = 0x00c3 # macro +regPA_SC_VPORT_ZMAX_7_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_8 = 0x00c4 # macro +regPA_SC_VPORT_ZMIN_8_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_8 = 0x00c5 # macro +regPA_SC_VPORT_ZMAX_8_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_9 = 0x00c6 # macro +regPA_SC_VPORT_ZMIN_9_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_9 = 0x00c7 # macro +regPA_SC_VPORT_ZMAX_9_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_10 = 0x00c8 # macro +regPA_SC_VPORT_ZMIN_10_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_10 = 0x00c9 # macro +regPA_SC_VPORT_ZMAX_10_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_11 = 0x00ca # macro +regPA_SC_VPORT_ZMIN_11_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_11 = 0x00cb # macro +regPA_SC_VPORT_ZMAX_11_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_12 = 0x00cc # macro +regPA_SC_VPORT_ZMIN_12_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_12 = 0x00cd # macro +regPA_SC_VPORT_ZMAX_12_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_13 = 0x00ce # macro +regPA_SC_VPORT_ZMIN_13_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_13 = 0x00cf # macro +regPA_SC_VPORT_ZMAX_13_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_14 = 0x00d0 # macro +regPA_SC_VPORT_ZMIN_14_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_14 = 0x00d1 # macro +regPA_SC_VPORT_ZMAX_14_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMIN_15 = 0x00d2 # macro +regPA_SC_VPORT_ZMIN_15_BASE_IDX = 1 # macro +regPA_SC_VPORT_ZMAX_15 = 0x00d3 # macro +regPA_SC_VPORT_ZMAX_15_BASE_IDX = 1 # macro +regPA_SC_RASTER_CONFIG = 0x00d4 # macro +regPA_SC_RASTER_CONFIG_BASE_IDX = 1 # macro +regPA_SC_RASTER_CONFIG_1 = 0x00d5 # macro +regPA_SC_RASTER_CONFIG_1_BASE_IDX = 1 # macro +regPA_SC_SCREEN_EXTENT_CONTROL = 0x00d6 # macro +regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX = 1 # macro +regPA_SC_TILE_STEERING_OVERRIDE = 0x00d7 # macro +regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX = 1 # macro +regCP_PERFMON_CNTX_CNTL = 0x00d8 # macro +regCP_PERFMON_CNTX_CNTL_BASE_IDX = 1 # macro +regCP_PIPEID = 0x00d9 # macro +regCP_PIPEID_BASE_IDX = 1 # macro +regCP_RINGID = 0x00d9 # macro +regCP_RINGID_BASE_IDX = 1 # macro +regCP_VMID = 0x00da # macro +regCP_VMID_BASE_IDX = 1 # macro +regPA_SC_RIGHT_VERT_GRID = 0x00e8 # macro +regPA_SC_RIGHT_VERT_GRID_BASE_IDX = 1 # macro +regPA_SC_LEFT_VERT_GRID = 0x00e9 # macro +regPA_SC_LEFT_VERT_GRID_BASE_IDX = 1 # macro +regPA_SC_HORIZ_GRID = 0x00ea # macro +regPA_SC_HORIZ_GRID_BASE_IDX = 1 # macro +regVGT_MULTI_PRIM_IB_RESET_INDX = 0x0103 # macro +regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX = 1 # macro +regCB_BLEND_RED = 0x0105 # macro +regCB_BLEND_RED_BASE_IDX = 1 # macro +regCB_BLEND_GREEN = 0x0106 # macro +regCB_BLEND_GREEN_BASE_IDX = 1 # macro +regCB_BLEND_BLUE = 0x0107 # macro +regCB_BLEND_BLUE_BASE_IDX = 1 # macro +regCB_BLEND_ALPHA = 0x0108 # macro +regCB_BLEND_ALPHA_BASE_IDX = 1 # macro +regCB_DCC_CONTROL = 0x0109 # macro +regCB_DCC_CONTROL_BASE_IDX = 1 # macro +regDB_STENCIL_CONTROL = 0x010b # macro +regDB_STENCIL_CONTROL_BASE_IDX = 1 # macro +regDB_STENCILREFMASK = 0x010c # macro +regDB_STENCILREFMASK_BASE_IDX = 1 # macro +regDB_STENCILREFMASK_BF = 0x010d # macro +regDB_STENCILREFMASK_BF_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE = 0x010f # macro +regPA_CL_VPORT_XSCALE_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET = 0x0110 # macro +regPA_CL_VPORT_XOFFSET_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE = 0x0111 # macro +regPA_CL_VPORT_YSCALE_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET = 0x0112 # macro +regPA_CL_VPORT_YOFFSET_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE = 0x0113 # macro +regPA_CL_VPORT_ZSCALE_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET = 0x0114 # macro +regPA_CL_VPORT_ZOFFSET_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_1 = 0x0115 # macro +regPA_CL_VPORT_XSCALE_1_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_1 = 0x0116 # macro +regPA_CL_VPORT_XOFFSET_1_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_1 = 0x0117 # macro +regPA_CL_VPORT_YSCALE_1_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_1 = 0x0118 # macro +regPA_CL_VPORT_YOFFSET_1_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_1 = 0x0119 # macro +regPA_CL_VPORT_ZSCALE_1_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_1 = 0x011a # macro +regPA_CL_VPORT_ZOFFSET_1_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_2 = 0x011b # macro +regPA_CL_VPORT_XSCALE_2_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_2 = 0x011c # macro +regPA_CL_VPORT_XOFFSET_2_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_2 = 0x011d # macro +regPA_CL_VPORT_YSCALE_2_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_2 = 0x011e # macro +regPA_CL_VPORT_YOFFSET_2_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_2 = 0x011f # macro +regPA_CL_VPORT_ZSCALE_2_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_2 = 0x0120 # macro +regPA_CL_VPORT_ZOFFSET_2_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_3 = 0x0121 # macro +regPA_CL_VPORT_XSCALE_3_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_3 = 0x0122 # macro +regPA_CL_VPORT_XOFFSET_3_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_3 = 0x0123 # macro +regPA_CL_VPORT_YSCALE_3_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_3 = 0x0124 # macro +regPA_CL_VPORT_YOFFSET_3_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_3 = 0x0125 # macro +regPA_CL_VPORT_ZSCALE_3_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_3 = 0x0126 # macro +regPA_CL_VPORT_ZOFFSET_3_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_4 = 0x0127 # macro +regPA_CL_VPORT_XSCALE_4_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_4 = 0x0128 # macro +regPA_CL_VPORT_XOFFSET_4_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_4 = 0x0129 # macro +regPA_CL_VPORT_YSCALE_4_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_4 = 0x012a # macro +regPA_CL_VPORT_YOFFSET_4_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_4 = 0x012b # macro +regPA_CL_VPORT_ZSCALE_4_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_4 = 0x012c # macro +regPA_CL_VPORT_ZOFFSET_4_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_5 = 0x012d # macro +regPA_CL_VPORT_XSCALE_5_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_5 = 0x012e # macro +regPA_CL_VPORT_XOFFSET_5_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_5 = 0x012f # macro +regPA_CL_VPORT_YSCALE_5_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_5 = 0x0130 # macro +regPA_CL_VPORT_YOFFSET_5_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_5 = 0x0131 # macro +regPA_CL_VPORT_ZSCALE_5_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_5 = 0x0132 # macro +regPA_CL_VPORT_ZOFFSET_5_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_6 = 0x0133 # macro +regPA_CL_VPORT_XSCALE_6_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_6 = 0x0134 # macro +regPA_CL_VPORT_XOFFSET_6_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_6 = 0x0135 # macro +regPA_CL_VPORT_YSCALE_6_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_6 = 0x0136 # macro +regPA_CL_VPORT_YOFFSET_6_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_6 = 0x0137 # macro +regPA_CL_VPORT_ZSCALE_6_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_6 = 0x0138 # macro +regPA_CL_VPORT_ZOFFSET_6_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_7 = 0x0139 # macro +regPA_CL_VPORT_XSCALE_7_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_7 = 0x013a # macro +regPA_CL_VPORT_XOFFSET_7_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_7 = 0x013b # macro +regPA_CL_VPORT_YSCALE_7_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_7 = 0x013c # macro +regPA_CL_VPORT_YOFFSET_7_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_7 = 0x013d # macro +regPA_CL_VPORT_ZSCALE_7_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_7 = 0x013e # macro +regPA_CL_VPORT_ZOFFSET_7_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_8 = 0x013f # macro +regPA_CL_VPORT_XSCALE_8_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_8 = 0x0140 # macro +regPA_CL_VPORT_XOFFSET_8_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_8 = 0x0141 # macro +regPA_CL_VPORT_YSCALE_8_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_8 = 0x0142 # macro +regPA_CL_VPORT_YOFFSET_8_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_8 = 0x0143 # macro +regPA_CL_VPORT_ZSCALE_8_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_8 = 0x0144 # macro +regPA_CL_VPORT_ZOFFSET_8_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_9 = 0x0145 # macro +regPA_CL_VPORT_XSCALE_9_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_9 = 0x0146 # macro +regPA_CL_VPORT_XOFFSET_9_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_9 = 0x0147 # macro +regPA_CL_VPORT_YSCALE_9_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_9 = 0x0148 # macro +regPA_CL_VPORT_YOFFSET_9_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_9 = 0x0149 # macro +regPA_CL_VPORT_ZSCALE_9_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_9 = 0x014a # macro +regPA_CL_VPORT_ZOFFSET_9_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_10 = 0x014b # macro +regPA_CL_VPORT_XSCALE_10_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_10 = 0x014c # macro +regPA_CL_VPORT_XOFFSET_10_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_10 = 0x014d # macro +regPA_CL_VPORT_YSCALE_10_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_10 = 0x014e # macro +regPA_CL_VPORT_YOFFSET_10_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_10 = 0x014f # macro +regPA_CL_VPORT_ZSCALE_10_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_10 = 0x0150 # macro +regPA_CL_VPORT_ZOFFSET_10_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_11 = 0x0151 # macro +regPA_CL_VPORT_XSCALE_11_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_11 = 0x0152 # macro +regPA_CL_VPORT_XOFFSET_11_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_11 = 0x0153 # macro +regPA_CL_VPORT_YSCALE_11_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_11 = 0x0154 # macro +regPA_CL_VPORT_YOFFSET_11_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_11 = 0x0155 # macro +regPA_CL_VPORT_ZSCALE_11_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_11 = 0x0156 # macro +regPA_CL_VPORT_ZOFFSET_11_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_12 = 0x0157 # macro +regPA_CL_VPORT_XSCALE_12_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_12 = 0x0158 # macro +regPA_CL_VPORT_XOFFSET_12_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_12 = 0x0159 # macro +regPA_CL_VPORT_YSCALE_12_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_12 = 0x015a # macro +regPA_CL_VPORT_YOFFSET_12_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_12 = 0x015b # macro +regPA_CL_VPORT_ZSCALE_12_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_12 = 0x015c # macro +regPA_CL_VPORT_ZOFFSET_12_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_13 = 0x015d # macro +regPA_CL_VPORT_XSCALE_13_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_13 = 0x015e # macro +regPA_CL_VPORT_XOFFSET_13_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_13 = 0x015f # macro +regPA_CL_VPORT_YSCALE_13_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_13 = 0x0160 # macro +regPA_CL_VPORT_YOFFSET_13_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_13 = 0x0161 # macro +regPA_CL_VPORT_ZSCALE_13_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_13 = 0x0162 # macro +regPA_CL_VPORT_ZOFFSET_13_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_14 = 0x0163 # macro +regPA_CL_VPORT_XSCALE_14_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_14 = 0x0164 # macro +regPA_CL_VPORT_XOFFSET_14_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_14 = 0x0165 # macro +regPA_CL_VPORT_YSCALE_14_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_14 = 0x0166 # macro +regPA_CL_VPORT_YOFFSET_14_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_14 = 0x0167 # macro +regPA_CL_VPORT_ZSCALE_14_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_14 = 0x0168 # macro +regPA_CL_VPORT_ZOFFSET_14_BASE_IDX = 1 # macro +regPA_CL_VPORT_XSCALE_15 = 0x0169 # macro +regPA_CL_VPORT_XSCALE_15_BASE_IDX = 1 # macro +regPA_CL_VPORT_XOFFSET_15 = 0x016a # macro +regPA_CL_VPORT_XOFFSET_15_BASE_IDX = 1 # macro +regPA_CL_VPORT_YSCALE_15 = 0x016b # macro +regPA_CL_VPORT_YSCALE_15_BASE_IDX = 1 # macro +regPA_CL_VPORT_YOFFSET_15 = 0x016c # macro +regPA_CL_VPORT_YOFFSET_15_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZSCALE_15 = 0x016d # macro +regPA_CL_VPORT_ZSCALE_15_BASE_IDX = 1 # macro +regPA_CL_VPORT_ZOFFSET_15 = 0x016e # macro +regPA_CL_VPORT_ZOFFSET_15_BASE_IDX = 1 # macro +regPA_CL_UCP_0_X = 0x016f # macro +regPA_CL_UCP_0_X_BASE_IDX = 1 # macro +regPA_CL_UCP_0_Y = 0x0170 # macro +regPA_CL_UCP_0_Y_BASE_IDX = 1 # macro +regPA_CL_UCP_0_Z = 0x0171 # macro +regPA_CL_UCP_0_Z_BASE_IDX = 1 # macro +regPA_CL_UCP_0_W = 0x0172 # macro +regPA_CL_UCP_0_W_BASE_IDX = 1 # macro +regPA_CL_UCP_1_X = 0x0173 # macro +regPA_CL_UCP_1_X_BASE_IDX = 1 # macro +regPA_CL_UCP_1_Y = 0x0174 # macro +regPA_CL_UCP_1_Y_BASE_IDX = 1 # macro +regPA_CL_UCP_1_Z = 0x0175 # macro +regPA_CL_UCP_1_Z_BASE_IDX = 1 # macro +regPA_CL_UCP_1_W = 0x0176 # macro +regPA_CL_UCP_1_W_BASE_IDX = 1 # macro +regPA_CL_UCP_2_X = 0x0177 # macro +regPA_CL_UCP_2_X_BASE_IDX = 1 # macro +regPA_CL_UCP_2_Y = 0x0178 # macro +regPA_CL_UCP_2_Y_BASE_IDX = 1 # macro +regPA_CL_UCP_2_Z = 0x0179 # macro +regPA_CL_UCP_2_Z_BASE_IDX = 1 # macro +regPA_CL_UCP_2_W = 0x017a # macro +regPA_CL_UCP_2_W_BASE_IDX = 1 # macro +regPA_CL_UCP_3_X = 0x017b # macro +regPA_CL_UCP_3_X_BASE_IDX = 1 # macro +regPA_CL_UCP_3_Y = 0x017c # macro +regPA_CL_UCP_3_Y_BASE_IDX = 1 # macro +regPA_CL_UCP_3_Z = 0x017d # macro +regPA_CL_UCP_3_Z_BASE_IDX = 1 # macro +regPA_CL_UCP_3_W = 0x017e # macro +regPA_CL_UCP_3_W_BASE_IDX = 1 # macro +regPA_CL_UCP_4_X = 0x017f # macro +regPA_CL_UCP_4_X_BASE_IDX = 1 # macro +regPA_CL_UCP_4_Y = 0x0180 # macro +regPA_CL_UCP_4_Y_BASE_IDX = 1 # macro +regPA_CL_UCP_4_Z = 0x0181 # macro +regPA_CL_UCP_4_Z_BASE_IDX = 1 # macro +regPA_CL_UCP_4_W = 0x0182 # macro +regPA_CL_UCP_4_W_BASE_IDX = 1 # macro +regPA_CL_UCP_5_X = 0x0183 # macro +regPA_CL_UCP_5_X_BASE_IDX = 1 # macro +regPA_CL_UCP_5_Y = 0x0184 # macro +regPA_CL_UCP_5_Y_BASE_IDX = 1 # macro +regPA_CL_UCP_5_Z = 0x0185 # macro +regPA_CL_UCP_5_Z_BASE_IDX = 1 # macro +regPA_CL_UCP_5_W = 0x0186 # macro +regPA_CL_UCP_5_W_BASE_IDX = 1 # macro +regPA_CL_PROG_NEAR_CLIP_Z = 0x0187 # macro +regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_0 = 0x0191 # macro +regSPI_PS_INPUT_CNTL_0_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_1 = 0x0192 # macro +regSPI_PS_INPUT_CNTL_1_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_2 = 0x0193 # macro +regSPI_PS_INPUT_CNTL_2_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_3 = 0x0194 # macro +regSPI_PS_INPUT_CNTL_3_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_4 = 0x0195 # macro +regSPI_PS_INPUT_CNTL_4_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_5 = 0x0196 # macro +regSPI_PS_INPUT_CNTL_5_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_6 = 0x0197 # macro +regSPI_PS_INPUT_CNTL_6_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_7 = 0x0198 # macro +regSPI_PS_INPUT_CNTL_7_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_8 = 0x0199 # macro +regSPI_PS_INPUT_CNTL_8_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_9 = 0x019a # macro +regSPI_PS_INPUT_CNTL_9_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_10 = 0x019b # macro +regSPI_PS_INPUT_CNTL_10_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_11 = 0x019c # macro +regSPI_PS_INPUT_CNTL_11_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_12 = 0x019d # macro +regSPI_PS_INPUT_CNTL_12_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_13 = 0x019e # macro +regSPI_PS_INPUT_CNTL_13_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_14 = 0x019f # macro +regSPI_PS_INPUT_CNTL_14_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_15 = 0x01a0 # macro +regSPI_PS_INPUT_CNTL_15_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_16 = 0x01a1 # macro +regSPI_PS_INPUT_CNTL_16_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_17 = 0x01a2 # macro +regSPI_PS_INPUT_CNTL_17_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_18 = 0x01a3 # macro +regSPI_PS_INPUT_CNTL_18_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_19 = 0x01a4 # macro +regSPI_PS_INPUT_CNTL_19_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_20 = 0x01a5 # macro +regSPI_PS_INPUT_CNTL_20_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_21 = 0x01a6 # macro +regSPI_PS_INPUT_CNTL_21_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_22 = 0x01a7 # macro +regSPI_PS_INPUT_CNTL_22_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_23 = 0x01a8 # macro +regSPI_PS_INPUT_CNTL_23_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_24 = 0x01a9 # macro +regSPI_PS_INPUT_CNTL_24_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_25 = 0x01aa # macro +regSPI_PS_INPUT_CNTL_25_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_26 = 0x01ab # macro +regSPI_PS_INPUT_CNTL_26_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_27 = 0x01ac # macro +regSPI_PS_INPUT_CNTL_27_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_28 = 0x01ad # macro +regSPI_PS_INPUT_CNTL_28_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_29 = 0x01ae # macro +regSPI_PS_INPUT_CNTL_29_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_30 = 0x01af # macro +regSPI_PS_INPUT_CNTL_30_BASE_IDX = 1 # macro +regSPI_PS_INPUT_CNTL_31 = 0x01b0 # macro +regSPI_PS_INPUT_CNTL_31_BASE_IDX = 1 # macro +regSPI_VS_OUT_CONFIG = 0x01b1 # macro +regSPI_VS_OUT_CONFIG_BASE_IDX = 1 # macro +regSPI_PS_INPUT_ENA = 0x01b3 # macro +regSPI_PS_INPUT_ENA_BASE_IDX = 1 # macro +regSPI_PS_INPUT_ADDR = 0x01b4 # macro +regSPI_PS_INPUT_ADDR_BASE_IDX = 1 # macro +regSPI_INTERP_CONTROL_0 = 0x01b5 # macro +regSPI_INTERP_CONTROL_0_BASE_IDX = 1 # macro +regSPI_PS_IN_CONTROL = 0x01b6 # macro +regSPI_PS_IN_CONTROL_BASE_IDX = 1 # macro +regSPI_BARYC_CNTL = 0x01b8 # macro +regSPI_BARYC_CNTL_BASE_IDX = 1 # macro +regSPI_TMPRING_SIZE = 0x01ba # macro +regSPI_TMPRING_SIZE_BASE_IDX = 1 # macro +regSPI_SHADER_POS_FORMAT = 0x01c3 # macro +regSPI_SHADER_POS_FORMAT_BASE_IDX = 1 # macro +regSPI_SHADER_Z_FORMAT = 0x01c4 # macro +regSPI_SHADER_Z_FORMAT_BASE_IDX = 1 # macro +regSPI_SHADER_COL_FORMAT = 0x01c5 # macro +regSPI_SHADER_COL_FORMAT_BASE_IDX = 1 # macro +regCB_BLEND0_CONTROL = 0x01e0 # macro +regCB_BLEND0_CONTROL_BASE_IDX = 1 # macro +regCB_BLEND1_CONTROL = 0x01e1 # macro +regCB_BLEND1_CONTROL_BASE_IDX = 1 # macro +regCB_BLEND2_CONTROL = 0x01e2 # macro +regCB_BLEND2_CONTROL_BASE_IDX = 1 # macro +regCB_BLEND3_CONTROL = 0x01e3 # macro +regCB_BLEND3_CONTROL_BASE_IDX = 1 # macro +regCB_BLEND4_CONTROL = 0x01e4 # macro +regCB_BLEND4_CONTROL_BASE_IDX = 1 # macro +regCB_BLEND5_CONTROL = 0x01e5 # macro +regCB_BLEND5_CONTROL_BASE_IDX = 1 # macro +regCB_BLEND6_CONTROL = 0x01e6 # macro +regCB_BLEND6_CONTROL_BASE_IDX = 1 # macro +regCB_BLEND7_CONTROL = 0x01e7 # macro +regCB_BLEND7_CONTROL_BASE_IDX = 1 # macro +regCB_MRT0_EPITCH = 0x01e8 # macro +regCB_MRT0_EPITCH_BASE_IDX = 1 # macro +regCB_MRT1_EPITCH = 0x01e9 # macro +regCB_MRT1_EPITCH_BASE_IDX = 1 # macro +regCB_MRT2_EPITCH = 0x01ea # macro +regCB_MRT2_EPITCH_BASE_IDX = 1 # macro +regCB_MRT3_EPITCH = 0x01eb # macro +regCB_MRT3_EPITCH_BASE_IDX = 1 # macro +regCB_MRT4_EPITCH = 0x01ec # macro +regCB_MRT4_EPITCH_BASE_IDX = 1 # macro +regCB_MRT5_EPITCH = 0x01ed # macro +regCB_MRT5_EPITCH_BASE_IDX = 1 # macro +regCB_MRT6_EPITCH = 0x01ee # macro +regCB_MRT6_EPITCH_BASE_IDX = 1 # macro +regCB_MRT7_EPITCH = 0x01ef # macro +regCB_MRT7_EPITCH_BASE_IDX = 1 # macro +regCS_COPY_STATE = 0x01f3 # macro +regCS_COPY_STATE_BASE_IDX = 1 # macro +regGFX_COPY_STATE = 0x01f4 # macro +regGFX_COPY_STATE_BASE_IDX = 1 # macro +regPA_CL_POINT_X_RAD = 0x01f5 # macro +regPA_CL_POINT_X_RAD_BASE_IDX = 1 # macro +regPA_CL_POINT_Y_RAD = 0x01f6 # macro +regPA_CL_POINT_Y_RAD_BASE_IDX = 1 # macro +regPA_CL_POINT_SIZE = 0x01f7 # macro +regPA_CL_POINT_SIZE_BASE_IDX = 1 # macro +regPA_CL_POINT_CULL_RAD = 0x01f8 # macro +regPA_CL_POINT_CULL_RAD_BASE_IDX = 1 # macro +regVGT_DMA_BASE_HI = 0x01f9 # macro +regVGT_DMA_BASE_HI_BASE_IDX = 1 # macro +regVGT_DMA_BASE = 0x01fa # macro +regVGT_DMA_BASE_BASE_IDX = 1 # macro +regVGT_DRAW_INITIATOR = 0x01fc # macro +regVGT_DRAW_INITIATOR_BASE_IDX = 1 # macro +regVGT_IMMED_DATA = 0x01fd # macro +regVGT_IMMED_DATA_BASE_IDX = 1 # macro +regVGT_EVENT_ADDRESS_REG = 0x01fe # macro +regVGT_EVENT_ADDRESS_REG_BASE_IDX = 1 # macro +regDB_DEPTH_CONTROL = 0x0200 # macro +regDB_DEPTH_CONTROL_BASE_IDX = 1 # macro +regDB_EQAA = 0x0201 # macro +regDB_EQAA_BASE_IDX = 1 # macro +regCB_COLOR_CONTROL = 0x0202 # macro +regCB_COLOR_CONTROL_BASE_IDX = 1 # macro +regDB_SHADER_CONTROL = 0x0203 # macro +regDB_SHADER_CONTROL_BASE_IDX = 1 # macro +regPA_CL_CLIP_CNTL = 0x0204 # macro +regPA_CL_CLIP_CNTL_BASE_IDX = 1 # macro +regPA_SU_SC_MODE_CNTL = 0x0205 # macro +regPA_SU_SC_MODE_CNTL_BASE_IDX = 1 # macro +regPA_CL_VTE_CNTL = 0x0206 # macro +regPA_CL_VTE_CNTL_BASE_IDX = 1 # macro +regPA_CL_VS_OUT_CNTL = 0x0207 # macro +regPA_CL_VS_OUT_CNTL_BASE_IDX = 1 # macro +regPA_CL_NANINF_CNTL = 0x0208 # macro +regPA_CL_NANINF_CNTL_BASE_IDX = 1 # macro +regPA_SU_LINE_STIPPLE_CNTL = 0x0209 # macro +regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX = 1 # macro +regPA_SU_LINE_STIPPLE_SCALE = 0x020a # macro +regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX = 1 # macro +regPA_SU_PRIM_FILTER_CNTL = 0x020b # macro +regPA_SU_PRIM_FILTER_CNTL_BASE_IDX = 1 # macro +regPA_SU_SMALL_PRIM_FILTER_CNTL = 0x020c # macro +regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX = 1 # macro +regPA_CL_OBJPRIM_ID_CNTL = 0x020d # macro +regPA_CL_OBJPRIM_ID_CNTL_BASE_IDX = 1 # macro +regPA_CL_NGG_CNTL = 0x020e # macro +regPA_CL_NGG_CNTL_BASE_IDX = 1 # macro +regPA_SU_OVER_RASTERIZATION_CNTL = 0x020f # macro +regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX = 1 # macro +regPA_STEREO_CNTL = 0x0210 # macro +regPA_STEREO_CNTL_BASE_IDX = 1 # macro +regPA_SU_POINT_SIZE = 0x0280 # macro +regPA_SU_POINT_SIZE_BASE_IDX = 1 # macro +regPA_SU_POINT_MINMAX = 0x0281 # macro +regPA_SU_POINT_MINMAX_BASE_IDX = 1 # macro +regPA_SU_LINE_CNTL = 0x0282 # macro +regPA_SU_LINE_CNTL_BASE_IDX = 1 # macro +regPA_SC_LINE_STIPPLE = 0x0283 # macro +regPA_SC_LINE_STIPPLE_BASE_IDX = 1 # macro +regVGT_OUTPUT_PATH_CNTL = 0x0284 # macro +regVGT_OUTPUT_PATH_CNTL_BASE_IDX = 1 # macro +regVGT_HOS_CNTL = 0x0285 # macro +regVGT_HOS_CNTL_BASE_IDX = 1 # macro +regVGT_HOS_MAX_TESS_LEVEL = 0x0286 # macro +regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX = 1 # macro +regVGT_HOS_MIN_TESS_LEVEL = 0x0287 # macro +regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX = 1 # macro +regVGT_HOS_REUSE_DEPTH = 0x0288 # macro +regVGT_HOS_REUSE_DEPTH_BASE_IDX = 1 # macro +regVGT_GROUP_PRIM_TYPE = 0x0289 # macro +regVGT_GROUP_PRIM_TYPE_BASE_IDX = 1 # macro +regVGT_GROUP_FIRST_DECR = 0x028a # macro +regVGT_GROUP_FIRST_DECR_BASE_IDX = 1 # macro +regVGT_GROUP_DECR = 0x028b # macro +regVGT_GROUP_DECR_BASE_IDX = 1 # macro +regVGT_GROUP_VECT_0_CNTL = 0x028c # macro +regVGT_GROUP_VECT_0_CNTL_BASE_IDX = 1 # macro +regVGT_GROUP_VECT_1_CNTL = 0x028d # macro +regVGT_GROUP_VECT_1_CNTL_BASE_IDX = 1 # macro +regVGT_GROUP_VECT_0_FMT_CNTL = 0x028e # macro +regVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX = 1 # macro +regVGT_GROUP_VECT_1_FMT_CNTL = 0x028f # macro +regVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX = 1 # macro +regVGT_GS_MODE = 0x0290 # macro +regVGT_GS_MODE_BASE_IDX = 1 # macro +regVGT_GS_ONCHIP_CNTL = 0x0291 # macro +regVGT_GS_ONCHIP_CNTL_BASE_IDX = 1 # macro +regPA_SC_MODE_CNTL_0 = 0x0292 # macro +regPA_SC_MODE_CNTL_0_BASE_IDX = 1 # macro +regPA_SC_MODE_CNTL_1 = 0x0293 # macro +regPA_SC_MODE_CNTL_1_BASE_IDX = 1 # macro +regVGT_ENHANCE = 0x0294 # macro +regVGT_ENHANCE_BASE_IDX = 1 # macro +regVGT_GS_PER_ES = 0x0295 # macro +regVGT_GS_PER_ES_BASE_IDX = 1 # macro +regVGT_ES_PER_GS = 0x0296 # macro +regVGT_ES_PER_GS_BASE_IDX = 1 # macro +regVGT_GS_PER_VS = 0x0297 # macro +regVGT_GS_PER_VS_BASE_IDX = 1 # macro +regVGT_GSVS_RING_OFFSET_1 = 0x0298 # macro +regVGT_GSVS_RING_OFFSET_1_BASE_IDX = 1 # macro +regVGT_GSVS_RING_OFFSET_2 = 0x0299 # macro +regVGT_GSVS_RING_OFFSET_2_BASE_IDX = 1 # macro +regVGT_GSVS_RING_OFFSET_3 = 0x029a # macro +regVGT_GSVS_RING_OFFSET_3_BASE_IDX = 1 # macro +regVGT_GS_OUT_PRIM_TYPE = 0x029b # macro +regVGT_GS_OUT_PRIM_TYPE_BASE_IDX = 1 # macro +regIA_ENHANCE = 0x029c # macro +regIA_ENHANCE_BASE_IDX = 1 # macro +regVGT_DMA_SIZE = 0x029d # macro +regVGT_DMA_SIZE_BASE_IDX = 1 # macro +regVGT_DMA_MAX_SIZE = 0x029e # macro +regVGT_DMA_MAX_SIZE_BASE_IDX = 1 # macro +regVGT_DMA_INDEX_TYPE = 0x029f # macro +regVGT_DMA_INDEX_TYPE_BASE_IDX = 1 # macro +regWD_ENHANCE = 0x02a0 # macro +regWD_ENHANCE_BASE_IDX = 1 # macro +regVGT_PRIMITIVEID_EN = 0x02a1 # macro +regVGT_PRIMITIVEID_EN_BASE_IDX = 1 # macro +regVGT_DMA_NUM_INSTANCES = 0x02a2 # macro +regVGT_DMA_NUM_INSTANCES_BASE_IDX = 1 # macro +regVGT_PRIMITIVEID_RESET = 0x02a3 # macro +regVGT_PRIMITIVEID_RESET_BASE_IDX = 1 # macro +regVGT_EVENT_INITIATOR = 0x02a4 # macro +regVGT_EVENT_INITIATOR_BASE_IDX = 1 # macro +regVGT_GS_MAX_PRIMS_PER_SUBGROUP = 0x02a5 # macro +regVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX = 1 # macro +regVGT_DRAW_PAYLOAD_CNTL = 0x02a6 # macro +regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX = 1 # macro +regVGT_INSTANCE_STEP_RATE_0 = 0x02a8 # macro +regVGT_INSTANCE_STEP_RATE_0_BASE_IDX = 1 # macro +regVGT_INSTANCE_STEP_RATE_1 = 0x02a9 # macro +regVGT_INSTANCE_STEP_RATE_1_BASE_IDX = 1 # macro +regIA_MULTI_VGT_PARAM_BC = 0x02aa # macro +regIA_MULTI_VGT_PARAM_BC_BASE_IDX = 1 # macro +regVGT_ESGS_RING_ITEMSIZE = 0x02ab # macro +regVGT_ESGS_RING_ITEMSIZE_BASE_IDX = 1 # macro +regVGT_GSVS_RING_ITEMSIZE = 0x02ac # macro +regVGT_GSVS_RING_ITEMSIZE_BASE_IDX = 1 # macro +regVGT_REUSE_OFF = 0x02ad # macro +regVGT_REUSE_OFF_BASE_IDX = 1 # macro +regVGT_VTX_CNT_EN = 0x02ae # macro +regVGT_VTX_CNT_EN_BASE_IDX = 1 # macro +regDB_HTILE_SURFACE = 0x02af # macro +regDB_HTILE_SURFACE_BASE_IDX = 1 # macro +regDB_SRESULTS_COMPARE_STATE0 = 0x02b0 # macro +regDB_SRESULTS_COMPARE_STATE0_BASE_IDX = 1 # macro +regDB_SRESULTS_COMPARE_STATE1 = 0x02b1 # macro +regDB_SRESULTS_COMPARE_STATE1_BASE_IDX = 1 # macro +regDB_PRELOAD_CONTROL = 0x02b2 # macro +regDB_PRELOAD_CONTROL_BASE_IDX = 1 # macro +regVGT_STRMOUT_BUFFER_SIZE_0 = 0x02b4 # macro +regVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX = 1 # macro +regVGT_STRMOUT_VTX_STRIDE_0 = 0x02b5 # macro +regVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX = 1 # macro +regVGT_STRMOUT_BUFFER_OFFSET_0 = 0x02b7 # macro +regVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX = 1 # macro +regVGT_STRMOUT_BUFFER_SIZE_1 = 0x02b8 # macro +regVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX = 1 # macro +regVGT_STRMOUT_VTX_STRIDE_1 = 0x02b9 # macro +regVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX = 1 # macro +regVGT_STRMOUT_BUFFER_OFFSET_1 = 0x02bb # macro +regVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX = 1 # macro +regVGT_STRMOUT_BUFFER_SIZE_2 = 0x02bc # macro +regVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX = 1 # macro +regVGT_STRMOUT_VTX_STRIDE_2 = 0x02bd # macro +regVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX = 1 # macro +regVGT_STRMOUT_BUFFER_OFFSET_2 = 0x02bf # macro +regVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX = 1 # macro +regVGT_STRMOUT_BUFFER_SIZE_3 = 0x02c0 # macro +regVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX = 1 # macro +regVGT_STRMOUT_VTX_STRIDE_3 = 0x02c1 # macro +regVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX = 1 # macro +regVGT_STRMOUT_BUFFER_OFFSET_3 = 0x02c3 # macro +regVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX = 1 # macro +regVGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x02ca # macro +regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX = 1 # macro +regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x02cb # macro +regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX = 1 # macro +regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x02cc # macro +regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX = 1 # macro +regVGT_GS_MAX_VERT_OUT = 0x02ce # macro +regVGT_GS_MAX_VERT_OUT_BASE_IDX = 1 # macro +regVGT_TESS_DISTRIBUTION = 0x02d4 # macro +regVGT_TESS_DISTRIBUTION_BASE_IDX = 1 # macro +regVGT_SHADER_STAGES_EN = 0x02d5 # macro +regVGT_SHADER_STAGES_EN_BASE_IDX = 1 # macro +regVGT_LS_HS_CONFIG = 0x02d6 # macro +regVGT_LS_HS_CONFIG_BASE_IDX = 1 # macro +regVGT_GS_VERT_ITEMSIZE = 0x02d7 # macro +regVGT_GS_VERT_ITEMSIZE_BASE_IDX = 1 # macro +regVGT_GS_VERT_ITEMSIZE_1 = 0x02d8 # macro +regVGT_GS_VERT_ITEMSIZE_1_BASE_IDX = 1 # macro +regVGT_GS_VERT_ITEMSIZE_2 = 0x02d9 # macro +regVGT_GS_VERT_ITEMSIZE_2_BASE_IDX = 1 # macro +regVGT_GS_VERT_ITEMSIZE_3 = 0x02da # macro +regVGT_GS_VERT_ITEMSIZE_3_BASE_IDX = 1 # macro +regVGT_TF_PARAM = 0x02db # macro +regVGT_TF_PARAM_BASE_IDX = 1 # macro +regDB_ALPHA_TO_MASK = 0x02dc # macro +regDB_ALPHA_TO_MASK_BASE_IDX = 1 # macro +regVGT_DISPATCH_DRAW_INDEX = 0x02dd # macro +regVGT_DISPATCH_DRAW_INDEX_BASE_IDX = 1 # macro +regPA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x02de # macro +regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX = 1 # macro +regPA_SU_POLY_OFFSET_CLAMP = 0x02df # macro +regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX = 1 # macro +regPA_SU_POLY_OFFSET_FRONT_SCALE = 0x02e0 # macro +regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX = 1 # macro +regPA_SU_POLY_OFFSET_FRONT_OFFSET = 0x02e1 # macro +regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX = 1 # macro +regPA_SU_POLY_OFFSET_BACK_SCALE = 0x02e2 # macro +regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX = 1 # macro +regPA_SU_POLY_OFFSET_BACK_OFFSET = 0x02e3 # macro +regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX = 1 # macro +regVGT_GS_INSTANCE_CNT = 0x02e4 # macro +regVGT_GS_INSTANCE_CNT_BASE_IDX = 1 # macro +regVGT_STRMOUT_CONFIG = 0x02e5 # macro +regVGT_STRMOUT_CONFIG_BASE_IDX = 1 # macro +regVGT_STRMOUT_BUFFER_CONFIG = 0x02e6 # macro +regVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX = 1 # macro +regVGT_DMA_EVENT_INITIATOR = 0x02e7 # macro +regVGT_DMA_EVENT_INITIATOR_BASE_IDX = 1 # macro +regPA_SC_CENTROID_PRIORITY_0 = 0x02f5 # macro +regPA_SC_CENTROID_PRIORITY_0_BASE_IDX = 1 # macro +regPA_SC_CENTROID_PRIORITY_1 = 0x02f6 # macro +regPA_SC_CENTROID_PRIORITY_1_BASE_IDX = 1 # macro +regPA_SC_LINE_CNTL = 0x02f7 # macro +regPA_SC_LINE_CNTL_BASE_IDX = 1 # macro +regPA_SC_AA_CONFIG = 0x02f8 # macro +regPA_SC_AA_CONFIG_BASE_IDX = 1 # macro +regPA_SU_VTX_CNTL = 0x02f9 # macro +regPA_SU_VTX_CNTL_BASE_IDX = 1 # macro +regPA_CL_GB_VERT_CLIP_ADJ = 0x02fa # macro +regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX = 1 # macro +regPA_CL_GB_VERT_DISC_ADJ = 0x02fb # macro +regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX = 1 # macro +regPA_CL_GB_HORZ_CLIP_ADJ = 0x02fc # macro +regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX = 1 # macro +regPA_CL_GB_HORZ_DISC_ADJ = 0x02fd # macro +regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 = 0x02fe # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 = 0x02ff # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 = 0x0300 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 = 0x0301 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 = 0x0302 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 = 0x0303 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 = 0x0304 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 = 0x0305 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 = 0x0306 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 = 0x0307 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 = 0x0308 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 = 0x0309 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 = 0x030a # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 = 0x030b # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 = 0x030c # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX = 1 # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 = 0x030d # macro +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX = 1 # macro +regPA_SC_AA_MASK_X0Y0_X1Y0 = 0x030e # macro +regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX = 1 # macro +regPA_SC_AA_MASK_X0Y1_X1Y1 = 0x030f # macro +regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX = 1 # macro +regPA_SC_SHADER_CONTROL = 0x0310 # macro +regPA_SC_SHADER_CONTROL_BASE_IDX = 1 # macro +regPA_SC_BINNER_CNTL_0 = 0x0311 # macro +regPA_SC_BINNER_CNTL_0_BASE_IDX = 1 # macro +regPA_SC_BINNER_CNTL_1 = 0x0312 # macro +regPA_SC_BINNER_CNTL_1_BASE_IDX = 1 # macro +regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL = 0x0313 # macro +regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX = 1 # macro +regPA_SC_NGG_MODE_CNTL = 0x0314 # macro +regPA_SC_NGG_MODE_CNTL_BASE_IDX = 1 # macro +regVGT_VERTEX_REUSE_BLOCK_CNTL = 0x0316 # macro +regVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX = 1 # macro +regVGT_OUT_DEALLOC_CNTL = 0x0317 # macro +regVGT_OUT_DEALLOC_CNTL_BASE_IDX = 1 # macro +regCB_COLOR0_BASE = 0x0318 # macro +regCB_COLOR0_BASE_BASE_IDX = 1 # macro +regCB_COLOR0_BASE_EXT = 0x0319 # macro +regCB_COLOR0_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR0_ATTRIB2 = 0x031a # macro +regCB_COLOR0_ATTRIB2_BASE_IDX = 1 # macro +regCB_COLOR0_VIEW = 0x031b # macro +regCB_COLOR0_VIEW_BASE_IDX = 1 # macro +regCB_COLOR0_INFO = 0x031c # macro +regCB_COLOR0_INFO_BASE_IDX = 1 # macro +regCB_COLOR0_ATTRIB = 0x031d # macro +regCB_COLOR0_ATTRIB_BASE_IDX = 1 # macro +regCB_COLOR0_DCC_CONTROL = 0x031e # macro +regCB_COLOR0_DCC_CONTROL_BASE_IDX = 1 # macro +regCB_COLOR0_CMASK = 0x031f # macro +regCB_COLOR0_CMASK_BASE_IDX = 1 # macro +regCB_COLOR0_CMASK_BASE_EXT = 0x0320 # macro +regCB_COLOR0_CMASK_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR0_FMASK = 0x0321 # macro +regCB_COLOR0_FMASK_BASE_IDX = 1 # macro +regCB_COLOR0_FMASK_BASE_EXT = 0x0322 # macro +regCB_COLOR0_FMASK_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR0_CLEAR_WORD0 = 0x0323 # macro +regCB_COLOR0_CLEAR_WORD0_BASE_IDX = 1 # macro +regCB_COLOR0_CLEAR_WORD1 = 0x0324 # macro +regCB_COLOR0_CLEAR_WORD1_BASE_IDX = 1 # macro +regCB_COLOR0_DCC_BASE = 0x0325 # macro +regCB_COLOR0_DCC_BASE_BASE_IDX = 1 # macro +regCB_COLOR0_DCC_BASE_EXT = 0x0326 # macro +regCB_COLOR0_DCC_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR1_BASE = 0x0327 # macro +regCB_COLOR1_BASE_BASE_IDX = 1 # macro +regCB_COLOR1_BASE_EXT = 0x0328 # macro +regCB_COLOR1_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR1_ATTRIB2 = 0x0329 # macro +regCB_COLOR1_ATTRIB2_BASE_IDX = 1 # macro +regCB_COLOR1_VIEW = 0x032a # macro +regCB_COLOR1_VIEW_BASE_IDX = 1 # macro +regCB_COLOR1_INFO = 0x032b # macro +regCB_COLOR1_INFO_BASE_IDX = 1 # macro +regCB_COLOR1_ATTRIB = 0x032c # macro +regCB_COLOR1_ATTRIB_BASE_IDX = 1 # macro +regCB_COLOR1_DCC_CONTROL = 0x032d # macro +regCB_COLOR1_DCC_CONTROL_BASE_IDX = 1 # macro +regCB_COLOR1_CMASK = 0x032e # macro +regCB_COLOR1_CMASK_BASE_IDX = 1 # macro +regCB_COLOR1_CMASK_BASE_EXT = 0x032f # macro +regCB_COLOR1_CMASK_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR1_FMASK = 0x0330 # macro +regCB_COLOR1_FMASK_BASE_IDX = 1 # macro +regCB_COLOR1_FMASK_BASE_EXT = 0x0331 # macro +regCB_COLOR1_FMASK_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR1_CLEAR_WORD0 = 0x0332 # macro +regCB_COLOR1_CLEAR_WORD0_BASE_IDX = 1 # macro +regCB_COLOR1_CLEAR_WORD1 = 0x0333 # macro +regCB_COLOR1_CLEAR_WORD1_BASE_IDX = 1 # macro +regCB_COLOR1_DCC_BASE = 0x0334 # macro +regCB_COLOR1_DCC_BASE_BASE_IDX = 1 # macro +regCB_COLOR1_DCC_BASE_EXT = 0x0335 # macro +regCB_COLOR1_DCC_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR2_BASE = 0x0336 # macro +regCB_COLOR2_BASE_BASE_IDX = 1 # macro +regCB_COLOR2_BASE_EXT = 0x0337 # macro +regCB_COLOR2_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR2_ATTRIB2 = 0x0338 # macro +regCB_COLOR2_ATTRIB2_BASE_IDX = 1 # macro +regCB_COLOR2_VIEW = 0x0339 # macro +regCB_COLOR2_VIEW_BASE_IDX = 1 # macro +regCB_COLOR2_INFO = 0x033a # macro +regCB_COLOR2_INFO_BASE_IDX = 1 # macro +regCB_COLOR2_ATTRIB = 0x033b # macro +regCB_COLOR2_ATTRIB_BASE_IDX = 1 # macro +regCB_COLOR2_DCC_CONTROL = 0x033c # macro +regCB_COLOR2_DCC_CONTROL_BASE_IDX = 1 # macro +regCB_COLOR2_CMASK = 0x033d # macro +regCB_COLOR2_CMASK_BASE_IDX = 1 # macro +regCB_COLOR2_CMASK_BASE_EXT = 0x033e # macro +regCB_COLOR2_CMASK_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR2_FMASK = 0x033f # macro +regCB_COLOR2_FMASK_BASE_IDX = 1 # macro +regCB_COLOR2_FMASK_BASE_EXT = 0x0340 # macro +regCB_COLOR2_FMASK_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR2_CLEAR_WORD0 = 0x0341 # macro +regCB_COLOR2_CLEAR_WORD0_BASE_IDX = 1 # macro +regCB_COLOR2_CLEAR_WORD1 = 0x0342 # macro +regCB_COLOR2_CLEAR_WORD1_BASE_IDX = 1 # macro +regCB_COLOR2_DCC_BASE = 0x0343 # macro +regCB_COLOR2_DCC_BASE_BASE_IDX = 1 # macro +regCB_COLOR2_DCC_BASE_EXT = 0x0344 # macro +regCB_COLOR2_DCC_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR3_BASE = 0x0345 # macro +regCB_COLOR3_BASE_BASE_IDX = 1 # macro +regCB_COLOR3_BASE_EXT = 0x0346 # macro +regCB_COLOR3_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR3_ATTRIB2 = 0x0347 # macro +regCB_COLOR3_ATTRIB2_BASE_IDX = 1 # macro +regCB_COLOR3_VIEW = 0x0348 # macro +regCB_COLOR3_VIEW_BASE_IDX = 1 # macro +regCB_COLOR3_INFO = 0x0349 # macro +regCB_COLOR3_INFO_BASE_IDX = 1 # macro +regCB_COLOR3_ATTRIB = 0x034a # macro +regCB_COLOR3_ATTRIB_BASE_IDX = 1 # macro +regCB_COLOR3_DCC_CONTROL = 0x034b # macro +regCB_COLOR3_DCC_CONTROL_BASE_IDX = 1 # macro +regCB_COLOR3_CMASK = 0x034c # macro +regCB_COLOR3_CMASK_BASE_IDX = 1 # macro +regCB_COLOR3_CMASK_BASE_EXT = 0x034d # macro +regCB_COLOR3_CMASK_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR3_FMASK = 0x034e # macro +regCB_COLOR3_FMASK_BASE_IDX = 1 # macro +regCB_COLOR3_FMASK_BASE_EXT = 0x034f # macro +regCB_COLOR3_FMASK_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR3_CLEAR_WORD0 = 0x0350 # macro +regCB_COLOR3_CLEAR_WORD0_BASE_IDX = 1 # macro +regCB_COLOR3_CLEAR_WORD1 = 0x0351 # macro +regCB_COLOR3_CLEAR_WORD1_BASE_IDX = 1 # macro +regCB_COLOR3_DCC_BASE = 0x0352 # macro +regCB_COLOR3_DCC_BASE_BASE_IDX = 1 # macro +regCB_COLOR3_DCC_BASE_EXT = 0x0353 # macro +regCB_COLOR3_DCC_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR4_BASE = 0x0354 # macro +regCB_COLOR4_BASE_BASE_IDX = 1 # macro +regCB_COLOR4_BASE_EXT = 0x0355 # macro +regCB_COLOR4_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR4_ATTRIB2 = 0x0356 # macro +regCB_COLOR4_ATTRIB2_BASE_IDX = 1 # macro +regCB_COLOR4_VIEW = 0x0357 # macro +regCB_COLOR4_VIEW_BASE_IDX = 1 # macro +regCB_COLOR4_INFO = 0x0358 # macro +regCB_COLOR4_INFO_BASE_IDX = 1 # macro +regCB_COLOR4_ATTRIB = 0x0359 # macro +regCB_COLOR4_ATTRIB_BASE_IDX = 1 # macro +regCB_COLOR4_DCC_CONTROL = 0x035a # macro +regCB_COLOR4_DCC_CONTROL_BASE_IDX = 1 # macro +regCB_COLOR4_CMASK = 0x035b # macro +regCB_COLOR4_CMASK_BASE_IDX = 1 # macro +regCB_COLOR4_CMASK_BASE_EXT = 0x035c # macro +regCB_COLOR4_CMASK_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR4_FMASK = 0x035d # macro +regCB_COLOR4_FMASK_BASE_IDX = 1 # macro +regCB_COLOR4_FMASK_BASE_EXT = 0x035e # macro +regCB_COLOR4_FMASK_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR4_CLEAR_WORD0 = 0x035f # macro +regCB_COLOR4_CLEAR_WORD0_BASE_IDX = 1 # macro +regCB_COLOR4_CLEAR_WORD1 = 0x0360 # macro +regCB_COLOR4_CLEAR_WORD1_BASE_IDX = 1 # macro +regCB_COLOR4_DCC_BASE = 0x0361 # macro +regCB_COLOR4_DCC_BASE_BASE_IDX = 1 # macro +regCB_COLOR4_DCC_BASE_EXT = 0x0362 # macro +regCB_COLOR4_DCC_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR5_BASE = 0x0363 # macro +regCB_COLOR5_BASE_BASE_IDX = 1 # macro +regCB_COLOR5_BASE_EXT = 0x0364 # macro +regCB_COLOR5_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR5_ATTRIB2 = 0x0365 # macro +regCB_COLOR5_ATTRIB2_BASE_IDX = 1 # macro +regCB_COLOR5_VIEW = 0x0366 # macro +regCB_COLOR5_VIEW_BASE_IDX = 1 # macro +regCB_COLOR5_INFO = 0x0367 # macro +regCB_COLOR5_INFO_BASE_IDX = 1 # macro +regCB_COLOR5_ATTRIB = 0x0368 # macro +regCB_COLOR5_ATTRIB_BASE_IDX = 1 # macro +regCB_COLOR5_DCC_CONTROL = 0x0369 # macro +regCB_COLOR5_DCC_CONTROL_BASE_IDX = 1 # macro +regCB_COLOR5_CMASK = 0x036a # macro +regCB_COLOR5_CMASK_BASE_IDX = 1 # macro +regCB_COLOR5_CMASK_BASE_EXT = 0x036b # macro +regCB_COLOR5_CMASK_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR5_FMASK = 0x036c # macro +regCB_COLOR5_FMASK_BASE_IDX = 1 # macro +regCB_COLOR5_FMASK_BASE_EXT = 0x036d # macro +regCB_COLOR5_FMASK_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR5_CLEAR_WORD0 = 0x036e # macro +regCB_COLOR5_CLEAR_WORD0_BASE_IDX = 1 # macro +regCB_COLOR5_CLEAR_WORD1 = 0x036f # macro +regCB_COLOR5_CLEAR_WORD1_BASE_IDX = 1 # macro +regCB_COLOR5_DCC_BASE = 0x0370 # macro +regCB_COLOR5_DCC_BASE_BASE_IDX = 1 # macro +regCB_COLOR5_DCC_BASE_EXT = 0x0371 # macro +regCB_COLOR5_DCC_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR6_BASE = 0x0372 # macro +regCB_COLOR6_BASE_BASE_IDX = 1 # macro +regCB_COLOR6_BASE_EXT = 0x0373 # macro +regCB_COLOR6_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR6_ATTRIB2 = 0x0374 # macro +regCB_COLOR6_ATTRIB2_BASE_IDX = 1 # macro +regCB_COLOR6_VIEW = 0x0375 # macro +regCB_COLOR6_VIEW_BASE_IDX = 1 # macro +regCB_COLOR6_INFO = 0x0376 # macro +regCB_COLOR6_INFO_BASE_IDX = 1 # macro +regCB_COLOR6_ATTRIB = 0x0377 # macro +regCB_COLOR6_ATTRIB_BASE_IDX = 1 # macro +regCB_COLOR6_DCC_CONTROL = 0x0378 # macro +regCB_COLOR6_DCC_CONTROL_BASE_IDX = 1 # macro +regCB_COLOR6_CMASK = 0x0379 # macro +regCB_COLOR6_CMASK_BASE_IDX = 1 # macro +regCB_COLOR6_CMASK_BASE_EXT = 0x037a # macro +regCB_COLOR6_CMASK_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR6_FMASK = 0x037b # macro +regCB_COLOR6_FMASK_BASE_IDX = 1 # macro +regCB_COLOR6_FMASK_BASE_EXT = 0x037c # macro +regCB_COLOR6_FMASK_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR6_CLEAR_WORD0 = 0x037d # macro +regCB_COLOR6_CLEAR_WORD0_BASE_IDX = 1 # macro +regCB_COLOR6_CLEAR_WORD1 = 0x037e # macro +regCB_COLOR6_CLEAR_WORD1_BASE_IDX = 1 # macro +regCB_COLOR6_DCC_BASE = 0x037f # macro +regCB_COLOR6_DCC_BASE_BASE_IDX = 1 # macro +regCB_COLOR6_DCC_BASE_EXT = 0x0380 # macro +regCB_COLOR6_DCC_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR7_BASE = 0x0381 # macro +regCB_COLOR7_BASE_BASE_IDX = 1 # macro +regCB_COLOR7_BASE_EXT = 0x0382 # macro +regCB_COLOR7_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR7_ATTRIB2 = 0x0383 # macro +regCB_COLOR7_ATTRIB2_BASE_IDX = 1 # macro +regCB_COLOR7_VIEW = 0x0384 # macro +regCB_COLOR7_VIEW_BASE_IDX = 1 # macro +regCB_COLOR7_INFO = 0x0385 # macro +regCB_COLOR7_INFO_BASE_IDX = 1 # macro +regCB_COLOR7_ATTRIB = 0x0386 # macro +regCB_COLOR7_ATTRIB_BASE_IDX = 1 # macro +regCB_COLOR7_DCC_CONTROL = 0x0387 # macro +regCB_COLOR7_DCC_CONTROL_BASE_IDX = 1 # macro +regCB_COLOR7_CMASK = 0x0388 # macro +regCB_COLOR7_CMASK_BASE_IDX = 1 # macro +regCB_COLOR7_CMASK_BASE_EXT = 0x0389 # macro +regCB_COLOR7_CMASK_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR7_FMASK = 0x038a # macro +regCB_COLOR7_FMASK_BASE_IDX = 1 # macro +regCB_COLOR7_FMASK_BASE_EXT = 0x038b # macro +regCB_COLOR7_FMASK_BASE_EXT_BASE_IDX = 1 # macro +regCB_COLOR7_CLEAR_WORD0 = 0x038c # macro +regCB_COLOR7_CLEAR_WORD0_BASE_IDX = 1 # macro +regCB_COLOR7_CLEAR_WORD1 = 0x038d # macro +regCB_COLOR7_CLEAR_WORD1_BASE_IDX = 1 # macro +regCB_COLOR7_DCC_BASE = 0x038e # macro +regCB_COLOR7_DCC_BASE_BASE_IDX = 1 # macro +regCB_COLOR7_DCC_BASE_EXT = 0x038f # macro +regCB_COLOR7_DCC_BASE_EXT_BASE_IDX = 1 # macro +regCP_EOP_DONE_ADDR_LO = 0x2000 # macro +regCP_EOP_DONE_ADDR_LO_BASE_IDX = 1 # macro +regCP_EOP_DONE_ADDR_HI = 0x2001 # macro +regCP_EOP_DONE_ADDR_HI_BASE_IDX = 1 # macro +regCP_EOP_DONE_DATA_LO = 0x2002 # macro +regCP_EOP_DONE_DATA_LO_BASE_IDX = 1 # macro +regCP_EOP_DONE_DATA_HI = 0x2003 # macro +regCP_EOP_DONE_DATA_HI_BASE_IDX = 1 # macro +regCP_EOP_LAST_FENCE_LO = 0x2004 # macro +regCP_EOP_LAST_FENCE_LO_BASE_IDX = 1 # macro +regCP_EOP_LAST_FENCE_HI = 0x2005 # macro +regCP_EOP_LAST_FENCE_HI_BASE_IDX = 1 # macro +regCP_STREAM_OUT_ADDR_LO = 0x2006 # macro +regCP_STREAM_OUT_ADDR_LO_BASE_IDX = 1 # macro +regCP_STREAM_OUT_ADDR_HI = 0x2007 # macro +regCP_STREAM_OUT_ADDR_HI_BASE_IDX = 1 # macro +regCP_NUM_PRIM_WRITTEN_COUNT0_LO = 0x2008 # macro +regCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX = 1 # macro +regCP_NUM_PRIM_WRITTEN_COUNT0_HI = 0x2009 # macro +regCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX = 1 # macro +regCP_NUM_PRIM_NEEDED_COUNT0_LO = 0x200a # macro +regCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX = 1 # macro +regCP_NUM_PRIM_NEEDED_COUNT0_HI = 0x200b # macro +regCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX = 1 # macro +regCP_NUM_PRIM_WRITTEN_COUNT1_LO = 0x200c # macro +regCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX = 1 # macro +regCP_NUM_PRIM_WRITTEN_COUNT1_HI = 0x200d # macro +regCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX = 1 # macro +regCP_NUM_PRIM_NEEDED_COUNT1_LO = 0x200e # macro +regCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX = 1 # macro +regCP_NUM_PRIM_NEEDED_COUNT1_HI = 0x200f # macro +regCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX = 1 # macro +regCP_NUM_PRIM_WRITTEN_COUNT2_LO = 0x2010 # macro +regCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX = 1 # macro +regCP_NUM_PRIM_WRITTEN_COUNT2_HI = 0x2011 # macro +regCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX = 1 # macro +regCP_NUM_PRIM_NEEDED_COUNT2_LO = 0x2012 # macro +regCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX = 1 # macro +regCP_NUM_PRIM_NEEDED_COUNT2_HI = 0x2013 # macro +regCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX = 1 # macro +regCP_NUM_PRIM_WRITTEN_COUNT3_LO = 0x2014 # macro +regCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX = 1 # macro +regCP_NUM_PRIM_WRITTEN_COUNT3_HI = 0x2015 # macro +regCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX = 1 # macro +regCP_NUM_PRIM_NEEDED_COUNT3_LO = 0x2016 # macro +regCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX = 1 # macro +regCP_NUM_PRIM_NEEDED_COUNT3_HI = 0x2017 # macro +regCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX = 1 # macro +regCP_PIPE_STATS_ADDR_LO = 0x2018 # macro +regCP_PIPE_STATS_ADDR_LO_BASE_IDX = 1 # macro +regCP_PIPE_STATS_ADDR_HI = 0x2019 # macro +regCP_PIPE_STATS_ADDR_HI_BASE_IDX = 1 # macro +regCP_VGT_IAVERT_COUNT_LO = 0x201a # macro +regCP_VGT_IAVERT_COUNT_LO_BASE_IDX = 1 # macro +regCP_VGT_IAVERT_COUNT_HI = 0x201b # macro +regCP_VGT_IAVERT_COUNT_HI_BASE_IDX = 1 # macro +regCP_VGT_IAPRIM_COUNT_LO = 0x201c # macro +regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX = 1 # macro +regCP_VGT_IAPRIM_COUNT_HI = 0x201d # macro +regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX = 1 # macro +regCP_VGT_GSPRIM_COUNT_LO = 0x201e # macro +regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX = 1 # macro +regCP_VGT_GSPRIM_COUNT_HI = 0x201f # macro +regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX = 1 # macro +regCP_VGT_VSINVOC_COUNT_LO = 0x2020 # macro +regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX = 1 # macro +regCP_VGT_VSINVOC_COUNT_HI = 0x2021 # macro +regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX = 1 # macro +regCP_VGT_GSINVOC_COUNT_LO = 0x2022 # macro +regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX = 1 # macro +regCP_VGT_GSINVOC_COUNT_HI = 0x2023 # macro +regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX = 1 # macro +regCP_VGT_HSINVOC_COUNT_LO = 0x2024 # macro +regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX = 1 # macro +regCP_VGT_HSINVOC_COUNT_HI = 0x2025 # macro +regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX = 1 # macro +regCP_VGT_DSINVOC_COUNT_LO = 0x2026 # macro +regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX = 1 # macro +regCP_VGT_DSINVOC_COUNT_HI = 0x2027 # macro +regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX = 1 # macro +regCP_PA_CINVOC_COUNT_LO = 0x2028 # macro +regCP_PA_CINVOC_COUNT_LO_BASE_IDX = 1 # macro +regCP_PA_CINVOC_COUNT_HI = 0x2029 # macro +regCP_PA_CINVOC_COUNT_HI_BASE_IDX = 1 # macro +regCP_PA_CPRIM_COUNT_LO = 0x202a # macro +regCP_PA_CPRIM_COUNT_LO_BASE_IDX = 1 # macro +regCP_PA_CPRIM_COUNT_HI = 0x202b # macro +regCP_PA_CPRIM_COUNT_HI_BASE_IDX = 1 # macro +regCP_SC_PSINVOC_COUNT0_LO = 0x202c # macro +regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX = 1 # macro +regCP_SC_PSINVOC_COUNT0_HI = 0x202d # macro +regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX = 1 # macro +regCP_SC_PSINVOC_COUNT1_LO = 0x202e # macro +regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX = 1 # macro +regCP_SC_PSINVOC_COUNT1_HI = 0x202f # macro +regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX = 1 # macro +regCP_VGT_CSINVOC_COUNT_LO = 0x2030 # macro +regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX = 1 # macro +regCP_VGT_CSINVOC_COUNT_HI = 0x2031 # macro +regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX = 1 # macro +regCP_PIPE_STATS_CONTROL = 0x203d # macro +regCP_PIPE_STATS_CONTROL_BASE_IDX = 1 # macro +regCP_STREAM_OUT_CONTROL = 0x203e # macro +regCP_STREAM_OUT_CONTROL_BASE_IDX = 1 # macro +regCP_STRMOUT_CNTL = 0x203f # macro +regCP_STRMOUT_CNTL_BASE_IDX = 1 # macro +regSCRATCH_REG0 = 0x2040 # macro +regSCRATCH_REG0_BASE_IDX = 1 # macro +regSCRATCH_REG1 = 0x2041 # macro +regSCRATCH_REG1_BASE_IDX = 1 # macro +regSCRATCH_REG2 = 0x2042 # macro +regSCRATCH_REG2_BASE_IDX = 1 # macro +regSCRATCH_REG3 = 0x2043 # macro +regSCRATCH_REG3_BASE_IDX = 1 # macro +regSCRATCH_REG4 = 0x2044 # macro +regSCRATCH_REG4_BASE_IDX = 1 # macro +regSCRATCH_REG5 = 0x2045 # macro +regSCRATCH_REG5_BASE_IDX = 1 # macro +regSCRATCH_REG6 = 0x2046 # macro +regSCRATCH_REG6_BASE_IDX = 1 # macro +regSCRATCH_REG7 = 0x2047 # macro +regSCRATCH_REG7_BASE_IDX = 1 # macro +regCP_APPEND_DATA_HI = 0x204c # macro +regCP_APPEND_DATA_HI_BASE_IDX = 1 # macro +regCP_APPEND_LAST_CS_FENCE_HI = 0x204d # macro +regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX = 1 # macro +regCP_APPEND_LAST_PS_FENCE_HI = 0x204e # macro +regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX = 1 # macro +regSCRATCH_UMSK = 0x2050 # macro +regSCRATCH_UMSK_BASE_IDX = 1 # macro +regSCRATCH_ADDR = 0x2051 # macro +regSCRATCH_ADDR_BASE_IDX = 1 # macro +regCP_PFP_ATOMIC_PREOP_LO = 0x2052 # macro +regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro +regCP_PFP_ATOMIC_PREOP_HI = 0x2053 # macro +regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro +regCP_PFP_GDS_ATOMIC0_PREOP_LO = 0x2054 # macro +regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro +regCP_PFP_GDS_ATOMIC0_PREOP_HI = 0x2055 # macro +regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro +regCP_PFP_GDS_ATOMIC1_PREOP_LO = 0x2056 # macro +regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro +regCP_PFP_GDS_ATOMIC1_PREOP_HI = 0x2057 # macro +regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro +regCP_APPEND_ADDR_LO = 0x2058 # macro +regCP_APPEND_ADDR_LO_BASE_IDX = 1 # macro +regCP_APPEND_ADDR_HI = 0x2059 # macro +regCP_APPEND_ADDR_HI_BASE_IDX = 1 # macro +regCP_APPEND_DATA_LO = 0x205a # macro +regCP_APPEND_DATA_LO_BASE_IDX = 1 # macro +regCP_APPEND_LAST_CS_FENCE_LO = 0x205b # macro +regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX = 1 # macro +regCP_APPEND_LAST_PS_FENCE_LO = 0x205c # macro +regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX = 1 # macro +regCP_ATOMIC_PREOP_LO = 0x205d # macro +regCP_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro +regCP_ME_ATOMIC_PREOP_LO = 0x205d # macro +regCP_ME_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro +regCP_ATOMIC_PREOP_HI = 0x205e # macro +regCP_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro +regCP_ME_ATOMIC_PREOP_HI = 0x205e # macro +regCP_ME_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro +regCP_GDS_ATOMIC0_PREOP_LO = 0x205f # macro +regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro +regCP_ME_GDS_ATOMIC0_PREOP_LO = 0x205f # macro +regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro +regCP_GDS_ATOMIC0_PREOP_HI = 0x2060 # macro +regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro +regCP_ME_GDS_ATOMIC0_PREOP_HI = 0x2060 # macro +regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro +regCP_GDS_ATOMIC1_PREOP_LO = 0x2061 # macro +regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro +regCP_ME_GDS_ATOMIC1_PREOP_LO = 0x2061 # macro +regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro +regCP_GDS_ATOMIC1_PREOP_HI = 0x2062 # macro +regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro +regCP_ME_GDS_ATOMIC1_PREOP_HI = 0x2062 # macro +regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro +regCP_ME_MC_WADDR_LO = 0x2069 # macro +regCP_ME_MC_WADDR_LO_BASE_IDX = 1 # macro +regCP_ME_MC_WADDR_HI = 0x206a # macro +regCP_ME_MC_WADDR_HI_BASE_IDX = 1 # macro +regCP_ME_MC_WDATA_LO = 0x206b # macro +regCP_ME_MC_WDATA_LO_BASE_IDX = 1 # macro +regCP_ME_MC_WDATA_HI = 0x206c # macro +regCP_ME_MC_WDATA_HI_BASE_IDX = 1 # macro +regCP_ME_MC_RADDR_LO = 0x206d # macro +regCP_ME_MC_RADDR_LO_BASE_IDX = 1 # macro +regCP_ME_MC_RADDR_HI = 0x206e # macro +regCP_ME_MC_RADDR_HI_BASE_IDX = 1 # macro +regCP_SEM_WAIT_TIMER = 0x206f # macro +regCP_SEM_WAIT_TIMER_BASE_IDX = 1 # macro +regCP_SIG_SEM_ADDR_LO = 0x2070 # macro +regCP_SIG_SEM_ADDR_LO_BASE_IDX = 1 # macro +regCP_SIG_SEM_ADDR_HI = 0x2071 # macro +regCP_SIG_SEM_ADDR_HI_BASE_IDX = 1 # macro +regCP_WAIT_REG_MEM_TIMEOUT = 0x2074 # macro +regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX = 1 # macro +regCP_WAIT_SEM_ADDR_LO = 0x2075 # macro +regCP_WAIT_SEM_ADDR_LO_BASE_IDX = 1 # macro +regCP_WAIT_SEM_ADDR_HI = 0x2076 # macro +regCP_WAIT_SEM_ADDR_HI_BASE_IDX = 1 # macro +regCP_DMA_PFP_CONTROL = 0x2077 # macro +regCP_DMA_PFP_CONTROL_BASE_IDX = 1 # macro +regCP_DMA_ME_CONTROL = 0x2078 # macro +regCP_DMA_ME_CONTROL_BASE_IDX = 1 # macro +regCP_COHER_BASE_HI = 0x2079 # macro +regCP_COHER_BASE_HI_BASE_IDX = 1 # macro +regCP_COHER_START_DELAY = 0x207b # macro +regCP_COHER_START_DELAY_BASE_IDX = 1 # macro +regCP_COHER_CNTL = 0x207c # macro +regCP_COHER_CNTL_BASE_IDX = 1 # macro +regCP_COHER_SIZE = 0x207d # macro +regCP_COHER_SIZE_BASE_IDX = 1 # macro +regCP_COHER_BASE = 0x207e # macro +regCP_COHER_BASE_BASE_IDX = 1 # macro +regCP_COHER_STATUS = 0x207f # macro +regCP_COHER_STATUS_BASE_IDX = 1 # macro +regCP_DMA_ME_SRC_ADDR = 0x2080 # macro +regCP_DMA_ME_SRC_ADDR_BASE_IDX = 1 # macro +regCP_DMA_ME_SRC_ADDR_HI = 0x2081 # macro +regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX = 1 # macro +regCP_DMA_ME_DST_ADDR = 0x2082 # macro +regCP_DMA_ME_DST_ADDR_BASE_IDX = 1 # macro +regCP_DMA_ME_DST_ADDR_HI = 0x2083 # macro +regCP_DMA_ME_DST_ADDR_HI_BASE_IDX = 1 # macro +regCP_DMA_ME_COMMAND = 0x2084 # macro +regCP_DMA_ME_COMMAND_BASE_IDX = 1 # macro +regCP_DMA_PFP_SRC_ADDR = 0x2085 # macro +regCP_DMA_PFP_SRC_ADDR_BASE_IDX = 1 # macro +regCP_DMA_PFP_SRC_ADDR_HI = 0x2086 # macro +regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX = 1 # macro +regCP_DMA_PFP_DST_ADDR = 0x2087 # macro +regCP_DMA_PFP_DST_ADDR_BASE_IDX = 1 # macro +regCP_DMA_PFP_DST_ADDR_HI = 0x2088 # macro +regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX = 1 # macro +regCP_DMA_PFP_COMMAND = 0x2089 # macro +regCP_DMA_PFP_COMMAND_BASE_IDX = 1 # macro +regCP_DMA_CNTL = 0x208a # macro +regCP_DMA_CNTL_BASE_IDX = 1 # macro +regCP_DMA_READ_TAGS = 0x208b # macro +regCP_DMA_READ_TAGS_BASE_IDX = 1 # macro +regCP_COHER_SIZE_HI = 0x208c # macro +regCP_COHER_SIZE_HI_BASE_IDX = 1 # macro +regCP_PFP_IB_CONTROL = 0x208d # macro +regCP_PFP_IB_CONTROL_BASE_IDX = 1 # macro +regCP_PFP_LOAD_CONTROL = 0x208e # macro +regCP_PFP_LOAD_CONTROL_BASE_IDX = 1 # macro +regCP_SCRATCH_INDEX = 0x208f # macro +regCP_SCRATCH_INDEX_BASE_IDX = 1 # macro +regCP_SCRATCH_DATA = 0x2090 # macro +regCP_SCRATCH_DATA_BASE_IDX = 1 # macro +regCP_RB_OFFSET = 0x2091 # macro +regCP_RB_OFFSET_BASE_IDX = 1 # macro +regCP_IB1_OFFSET = 0x2092 # macro +regCP_IB1_OFFSET_BASE_IDX = 1 # macro +regCP_IB2_OFFSET = 0x2093 # macro +regCP_IB2_OFFSET_BASE_IDX = 1 # macro +regCP_IB1_PREAMBLE_BEGIN = 0x2094 # macro +regCP_IB1_PREAMBLE_BEGIN_BASE_IDX = 1 # macro +regCP_IB1_PREAMBLE_END = 0x2095 # macro +regCP_IB1_PREAMBLE_END_BASE_IDX = 1 # macro +regCP_IB2_PREAMBLE_BEGIN = 0x2096 # macro +regCP_IB2_PREAMBLE_BEGIN_BASE_IDX = 1 # macro +regCP_IB2_PREAMBLE_END = 0x2097 # macro +regCP_IB2_PREAMBLE_END_BASE_IDX = 1 # macro +regCP_CE_IB1_OFFSET = 0x2098 # macro +regCP_CE_IB1_OFFSET_BASE_IDX = 1 # macro +regCP_CE_IB2_OFFSET = 0x2099 # macro +regCP_CE_IB2_OFFSET_BASE_IDX = 1 # macro +regCP_CE_COUNTER = 0x209a # macro +regCP_CE_COUNTER_BASE_IDX = 1 # macro +regCP_CE_RB_OFFSET = 0x209b # macro +regCP_CE_RB_OFFSET_BASE_IDX = 1 # macro +regCP_CE_INIT_CMD_BUFSZ = 0x20bd # macro +regCP_CE_INIT_CMD_BUFSZ_BASE_IDX = 1 # macro +regCP_CE_IB1_CMD_BUFSZ = 0x20be # macro +regCP_CE_IB1_CMD_BUFSZ_BASE_IDX = 1 # macro +regCP_CE_IB2_CMD_BUFSZ = 0x20bf # macro +regCP_CE_IB2_CMD_BUFSZ_BASE_IDX = 1 # macro +regCP_IB1_CMD_BUFSZ = 0x20c0 # macro +regCP_IB1_CMD_BUFSZ_BASE_IDX = 1 # macro +regCP_IB2_CMD_BUFSZ = 0x20c1 # macro +regCP_IB2_CMD_BUFSZ_BASE_IDX = 1 # macro +regCP_ST_CMD_BUFSZ = 0x20c2 # macro +regCP_ST_CMD_BUFSZ_BASE_IDX = 1 # macro +regCP_CE_INIT_BASE_LO = 0x20c3 # macro +regCP_CE_INIT_BASE_LO_BASE_IDX = 1 # macro +regCP_CE_INIT_BASE_HI = 0x20c4 # macro +regCP_CE_INIT_BASE_HI_BASE_IDX = 1 # macro +regCP_CE_INIT_BUFSZ = 0x20c5 # macro +regCP_CE_INIT_BUFSZ_BASE_IDX = 1 # macro +regCP_CE_IB1_BASE_LO = 0x20c6 # macro +regCP_CE_IB1_BASE_LO_BASE_IDX = 1 # macro +regCP_CE_IB1_BASE_HI = 0x20c7 # macro +regCP_CE_IB1_BASE_HI_BASE_IDX = 1 # macro +regCP_CE_IB1_BUFSZ = 0x20c8 # macro +regCP_CE_IB1_BUFSZ_BASE_IDX = 1 # macro +regCP_CE_IB2_BASE_LO = 0x20c9 # macro +regCP_CE_IB2_BASE_LO_BASE_IDX = 1 # macro +regCP_CE_IB2_BASE_HI = 0x20ca # macro +regCP_CE_IB2_BASE_HI_BASE_IDX = 1 # macro +regCP_CE_IB2_BUFSZ = 0x20cb # macro +regCP_CE_IB2_BUFSZ_BASE_IDX = 1 # macro +regCP_IB1_BASE_LO = 0x20cc # macro +regCP_IB1_BASE_LO_BASE_IDX = 1 # macro +regCP_IB1_BASE_HI = 0x20cd # macro +regCP_IB1_BASE_HI_BASE_IDX = 1 # macro +regCP_IB1_BUFSZ = 0x20ce # macro +regCP_IB1_BUFSZ_BASE_IDX = 1 # macro +regCP_IB2_BASE_LO = 0x20cf # macro +regCP_IB2_BASE_LO_BASE_IDX = 1 # macro +regCP_IB2_BASE_HI = 0x20d0 # macro +regCP_IB2_BASE_HI_BASE_IDX = 1 # macro +regCP_IB2_BUFSZ = 0x20d1 # macro +regCP_IB2_BUFSZ_BASE_IDX = 1 # macro +regCP_ST_BASE_LO = 0x20d2 # macro +regCP_ST_BASE_LO_BASE_IDX = 1 # macro +regCP_ST_BASE_HI = 0x20d3 # macro +regCP_ST_BASE_HI_BASE_IDX = 1 # macro +regCP_ST_BUFSZ = 0x20d4 # macro +regCP_ST_BUFSZ_BASE_IDX = 1 # macro +regCP_EOP_DONE_EVENT_CNTL = 0x20d5 # macro +regCP_EOP_DONE_EVENT_CNTL_BASE_IDX = 1 # macro +regCP_EOP_DONE_DATA_CNTL = 0x20d6 # macro +regCP_EOP_DONE_DATA_CNTL_BASE_IDX = 1 # macro +regCP_EOP_DONE_CNTX_ID = 0x20d7 # macro +regCP_EOP_DONE_CNTX_ID_BASE_IDX = 1 # macro +regCP_PFP_COMPLETION_STATUS = 0x20ec # macro +regCP_PFP_COMPLETION_STATUS_BASE_IDX = 1 # macro +regCP_CE_COMPLETION_STATUS = 0x20ed # macro +regCP_CE_COMPLETION_STATUS_BASE_IDX = 1 # macro +regCP_PRED_NOT_VISIBLE = 0x20ee # macro +regCP_PRED_NOT_VISIBLE_BASE_IDX = 1 # macro +regCP_PFP_METADATA_BASE_ADDR = 0x20f0 # macro +regCP_PFP_METADATA_BASE_ADDR_BASE_IDX = 1 # macro +regCP_PFP_METADATA_BASE_ADDR_HI = 0x20f1 # macro +regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX = 1 # macro +regCP_CE_METADATA_BASE_ADDR = 0x20f2 # macro +regCP_CE_METADATA_BASE_ADDR_BASE_IDX = 1 # macro +regCP_CE_METADATA_BASE_ADDR_HI = 0x20f3 # macro +regCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX = 1 # macro +regCP_DRAW_INDX_INDR_ADDR = 0x20f4 # macro +regCP_DRAW_INDX_INDR_ADDR_BASE_IDX = 1 # macro +regCP_DRAW_INDX_INDR_ADDR_HI = 0x20f5 # macro +regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX = 1 # macro +regCP_DISPATCH_INDR_ADDR = 0x20f6 # macro +regCP_DISPATCH_INDR_ADDR_BASE_IDX = 1 # macro +regCP_DISPATCH_INDR_ADDR_HI = 0x20f7 # macro +regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX = 1 # macro +regCP_INDEX_BASE_ADDR = 0x20f8 # macro +regCP_INDEX_BASE_ADDR_BASE_IDX = 1 # macro +regCP_INDEX_BASE_ADDR_HI = 0x20f9 # macro +regCP_INDEX_BASE_ADDR_HI_BASE_IDX = 1 # macro +regCP_INDEX_TYPE = 0x20fa # macro +regCP_INDEX_TYPE_BASE_IDX = 1 # macro +regCP_GDS_BKUP_ADDR = 0x20fb # macro +regCP_GDS_BKUP_ADDR_BASE_IDX = 1 # macro +regCP_GDS_BKUP_ADDR_HI = 0x20fc # macro +regCP_GDS_BKUP_ADDR_HI_BASE_IDX = 1 # macro +regCP_SAMPLE_STATUS = 0x20fd # macro +regCP_SAMPLE_STATUS_BASE_IDX = 1 # macro +regCP_ME_COHER_CNTL = 0x20fe # macro +regCP_ME_COHER_CNTL_BASE_IDX = 1 # macro +regCP_ME_COHER_SIZE = 0x20ff # macro +regCP_ME_COHER_SIZE_BASE_IDX = 1 # macro +regCP_ME_COHER_SIZE_HI = 0x2100 # macro +regCP_ME_COHER_SIZE_HI_BASE_IDX = 1 # macro +regCP_ME_COHER_BASE = 0x2101 # macro +regCP_ME_COHER_BASE_BASE_IDX = 1 # macro +regCP_ME_COHER_BASE_HI = 0x2102 # macro +regCP_ME_COHER_BASE_HI_BASE_IDX = 1 # macro +regCP_ME_COHER_STATUS = 0x2103 # macro +regCP_ME_COHER_STATUS_BASE_IDX = 1 # macro +regRLC_GPM_PERF_COUNT_0 = 0x2140 # macro +regRLC_GPM_PERF_COUNT_0_BASE_IDX = 1 # macro +regRLC_GPM_PERF_COUNT_1 = 0x2141 # macro +regRLC_GPM_PERF_COUNT_1_BASE_IDX = 1 # macro +regGRBM_GFX_INDEX = 0x2200 # macro +regGRBM_GFX_INDEX_BASE_IDX = 1 # macro +regVGT_GSVS_RING_SIZE = 0x2241 # macro +regVGT_GSVS_RING_SIZE_BASE_IDX = 1 # macro +regVGT_PRIMITIVE_TYPE = 0x2242 # macro +regVGT_PRIMITIVE_TYPE_BASE_IDX = 1 # macro +regVGT_INDEX_TYPE = 0x2243 # macro +regVGT_INDEX_TYPE_BASE_IDX = 1 # macro +regVGT_STRMOUT_BUFFER_FILLED_SIZE_0 = 0x2244 # macro +regVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX = 1 # macro +regVGT_STRMOUT_BUFFER_FILLED_SIZE_1 = 0x2245 # macro +regVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX = 1 # macro +regVGT_STRMOUT_BUFFER_FILLED_SIZE_2 = 0x2246 # macro +regVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX = 1 # macro +regVGT_STRMOUT_BUFFER_FILLED_SIZE_3 = 0x2247 # macro +regVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX = 1 # macro +regVGT_MAX_VTX_INDX = 0x2248 # macro +regVGT_MAX_VTX_INDX_BASE_IDX = 1 # macro +regVGT_MIN_VTX_INDX = 0x2249 # macro +regVGT_MIN_VTX_INDX_BASE_IDX = 1 # macro +regVGT_INDX_OFFSET = 0x224a # macro +regVGT_INDX_OFFSET_BASE_IDX = 1 # macro +regVGT_MULTI_PRIM_IB_RESET_EN = 0x224b # macro +regVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX = 1 # macro +regVGT_NUM_INDICES = 0x224c # macro +regVGT_NUM_INDICES_BASE_IDX = 1 # macro +regVGT_NUM_INSTANCES = 0x224d # macro +regVGT_NUM_INSTANCES_BASE_IDX = 1 # macro +regVGT_TF_RING_SIZE = 0x224e # macro +regVGT_TF_RING_SIZE_BASE_IDX = 1 # macro +regVGT_HS_OFFCHIP_PARAM = 0x224f # macro +regVGT_HS_OFFCHIP_PARAM_BASE_IDX = 1 # macro +regVGT_TF_MEMORY_BASE = 0x2250 # macro +regVGT_TF_MEMORY_BASE_BASE_IDX = 1 # macro +regVGT_TF_MEMORY_BASE_HI = 0x2251 # macro +regVGT_TF_MEMORY_BASE_HI_BASE_IDX = 1 # macro +regWD_POS_BUF_BASE = 0x2252 # macro +regWD_POS_BUF_BASE_BASE_IDX = 1 # macro +regWD_POS_BUF_BASE_HI = 0x2253 # macro +regWD_POS_BUF_BASE_HI_BASE_IDX = 1 # macro +regWD_CNTL_SB_BUF_BASE = 0x2254 # macro +regWD_CNTL_SB_BUF_BASE_BASE_IDX = 1 # macro +regWD_CNTL_SB_BUF_BASE_HI = 0x2255 # macro +regWD_CNTL_SB_BUF_BASE_HI_BASE_IDX = 1 # macro +regWD_INDEX_BUF_BASE = 0x2256 # macro +regWD_INDEX_BUF_BASE_BASE_IDX = 1 # macro +regWD_INDEX_BUF_BASE_HI = 0x2257 # macro +regWD_INDEX_BUF_BASE_HI_BASE_IDX = 1 # macro +regIA_MULTI_VGT_PARAM = 0x2258 # macro +regIA_MULTI_VGT_PARAM_BASE_IDX = 1 # macro +regVGT_INSTANCE_BASE_ID = 0x225a # macro +regVGT_INSTANCE_BASE_ID_BASE_IDX = 1 # macro +regPA_SU_LINE_STIPPLE_VALUE = 0x2280 # macro +regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX = 1 # macro +regPA_SC_LINE_STIPPLE_STATE = 0x2281 # macro +regPA_SC_LINE_STIPPLE_STATE_BASE_IDX = 1 # macro +regPA_SC_SCREEN_EXTENT_MIN_0 = 0x2284 # macro +regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX = 1 # macro +regPA_SC_SCREEN_EXTENT_MAX_0 = 0x2285 # macro +regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX = 1 # macro +regPA_SC_SCREEN_EXTENT_MIN_1 = 0x2286 # macro +regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX = 1 # macro +regPA_SC_SCREEN_EXTENT_MAX_1 = 0x228b # macro +regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX = 1 # macro +regPA_SC_P3D_TRAP_SCREEN_HV_EN = 0x22a0 # macro +regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro +regPA_SC_P3D_TRAP_SCREEN_H = 0x22a1 # macro +regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX = 1 # macro +regPA_SC_P3D_TRAP_SCREEN_V = 0x22a2 # macro +regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX = 1 # macro +regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE = 0x22a3 # macro +regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro +regPA_SC_P3D_TRAP_SCREEN_COUNT = 0x22a4 # macro +regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro +regPA_SC_HP3D_TRAP_SCREEN_HV_EN = 0x22a8 # macro +regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro +regPA_SC_HP3D_TRAP_SCREEN_H = 0x22a9 # macro +regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX = 1 # macro +regPA_SC_HP3D_TRAP_SCREEN_V = 0x22aa # macro +regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX = 1 # macro +regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE = 0x22ab # macro +regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro +regPA_SC_HP3D_TRAP_SCREEN_COUNT = 0x22ac # macro +regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro +regPA_SC_TRAP_SCREEN_HV_EN = 0x22b0 # macro +regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro +regPA_SC_TRAP_SCREEN_H = 0x22b1 # macro +regPA_SC_TRAP_SCREEN_H_BASE_IDX = 1 # macro +regPA_SC_TRAP_SCREEN_V = 0x22b2 # macro +regPA_SC_TRAP_SCREEN_V_BASE_IDX = 1 # macro +regPA_SC_TRAP_SCREEN_OCCURRENCE = 0x22b3 # macro +regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro +regPA_SC_TRAP_SCREEN_COUNT = 0x22b4 # macro +regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro +regPA_STATE_STEREO_X = 0x22b5 # macro +regPA_STATE_STEREO_X_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_BASE = 0x2330 # macro +regSQ_THREAD_TRACE_BASE_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_SIZE = 0x2331 # macro +regSQ_THREAD_TRACE_SIZE_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_MASK = 0x2332 # macro +regSQ_THREAD_TRACE_MASK_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_TOKEN_MASK = 0x2333 # macro +regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_PERF_MASK = 0x2334 # macro +regSQ_THREAD_TRACE_PERF_MASK_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_CTRL = 0x2335 # macro +regSQ_THREAD_TRACE_CTRL_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_MODE = 0x2336 # macro +regSQ_THREAD_TRACE_MODE_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_BASE2 = 0x2337 # macro +regSQ_THREAD_TRACE_BASE2_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_TOKEN_MASK2 = 0x2338 # macro +regSQ_THREAD_TRACE_TOKEN_MASK2_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_WPTR = 0x2339 # macro +regSQ_THREAD_TRACE_WPTR_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_STATUS = 0x233a # macro +regSQ_THREAD_TRACE_STATUS_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_HIWATER = 0x233b # macro +regSQ_THREAD_TRACE_HIWATER_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_CNTR = 0x233c # macro +regSQ_THREAD_TRACE_CNTR_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_USERDATA_0 = 0x2340 # macro +regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_USERDATA_1 = 0x2341 # macro +regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_USERDATA_2 = 0x2342 # macro +regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX = 1 # macro +regSQ_THREAD_TRACE_USERDATA_3 = 0x2343 # macro +regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX = 1 # macro +regSQC_CACHES = 0x2348 # macro +regSQC_CACHES_BASE_IDX = 1 # macro +regSQC_WRITEBACK = 0x2349 # macro +regSQC_WRITEBACK_BASE_IDX = 1 # macro +regDB_OCCLUSION_COUNT0_LOW = 0x23c0 # macro +regDB_OCCLUSION_COUNT0_LOW_BASE_IDX = 1 # macro +regDB_OCCLUSION_COUNT0_HI = 0x23c1 # macro +regDB_OCCLUSION_COUNT0_HI_BASE_IDX = 1 # macro +regDB_OCCLUSION_COUNT1_LOW = 0x23c2 # macro +regDB_OCCLUSION_COUNT1_LOW_BASE_IDX = 1 # macro +regDB_OCCLUSION_COUNT1_HI = 0x23c3 # macro +regDB_OCCLUSION_COUNT1_HI_BASE_IDX = 1 # macro +regDB_OCCLUSION_COUNT2_LOW = 0x23c4 # macro +regDB_OCCLUSION_COUNT2_LOW_BASE_IDX = 1 # macro +regDB_OCCLUSION_COUNT2_HI = 0x23c5 # macro +regDB_OCCLUSION_COUNT2_HI_BASE_IDX = 1 # macro +regDB_OCCLUSION_COUNT3_LOW = 0x23c6 # macro +regDB_OCCLUSION_COUNT3_LOW_BASE_IDX = 1 # macro +regDB_OCCLUSION_COUNT3_HI = 0x23c7 # macro +regDB_OCCLUSION_COUNT3_HI_BASE_IDX = 1 # macro +regDB_ZPASS_COUNT_LOW = 0x23fe # macro +regDB_ZPASS_COUNT_LOW_BASE_IDX = 1 # macro +regDB_ZPASS_COUNT_HI = 0x23ff # macro +regDB_ZPASS_COUNT_HI_BASE_IDX = 1 # macro +regGDS_RD_ADDR = 0x2400 # macro +regGDS_RD_ADDR_BASE_IDX = 1 # macro +regGDS_RD_DATA = 0x2401 # macro +regGDS_RD_DATA_BASE_IDX = 1 # macro +regGDS_RD_BURST_ADDR = 0x2402 # macro +regGDS_RD_BURST_ADDR_BASE_IDX = 1 # macro +regGDS_RD_BURST_COUNT = 0x2403 # macro +regGDS_RD_BURST_COUNT_BASE_IDX = 1 # macro +regGDS_RD_BURST_DATA = 0x2404 # macro +regGDS_RD_BURST_DATA_BASE_IDX = 1 # macro +regGDS_WR_ADDR = 0x2405 # macro +regGDS_WR_ADDR_BASE_IDX = 1 # macro +regGDS_WR_DATA = 0x2406 # macro +regGDS_WR_DATA_BASE_IDX = 1 # macro +regGDS_WR_BURST_ADDR = 0x2407 # macro +regGDS_WR_BURST_ADDR_BASE_IDX = 1 # macro +regGDS_WR_BURST_DATA = 0x2408 # macro +regGDS_WR_BURST_DATA_BASE_IDX = 1 # macro +regGDS_WRITE_COMPLETE = 0x2409 # macro +regGDS_WRITE_COMPLETE_BASE_IDX = 1 # macro +regGDS_ATOM_CNTL = 0x240a # macro +regGDS_ATOM_CNTL_BASE_IDX = 1 # macro +regGDS_ATOM_COMPLETE = 0x240b # macro +regGDS_ATOM_COMPLETE_BASE_IDX = 1 # macro +regGDS_ATOM_BASE = 0x240c # macro +regGDS_ATOM_BASE_BASE_IDX = 1 # macro +regGDS_ATOM_SIZE = 0x240d # macro +regGDS_ATOM_SIZE_BASE_IDX = 1 # macro +regGDS_ATOM_OFFSET0 = 0x240e # macro +regGDS_ATOM_OFFSET0_BASE_IDX = 1 # macro +regGDS_ATOM_OFFSET1 = 0x240f # macro +regGDS_ATOM_OFFSET1_BASE_IDX = 1 # macro +regGDS_ATOM_DST = 0x2410 # macro +regGDS_ATOM_DST_BASE_IDX = 1 # macro +regGDS_ATOM_OP = 0x2411 # macro +regGDS_ATOM_OP_BASE_IDX = 1 # macro +regGDS_ATOM_SRC0 = 0x2412 # macro +regGDS_ATOM_SRC0_BASE_IDX = 1 # macro +regGDS_ATOM_SRC0_U = 0x2413 # macro +regGDS_ATOM_SRC0_U_BASE_IDX = 1 # macro +regGDS_ATOM_SRC1 = 0x2414 # macro +regGDS_ATOM_SRC1_BASE_IDX = 1 # macro +regGDS_ATOM_SRC1_U = 0x2415 # macro +regGDS_ATOM_SRC1_U_BASE_IDX = 1 # macro +regGDS_ATOM_READ0 = 0x2416 # macro +regGDS_ATOM_READ0_BASE_IDX = 1 # macro +regGDS_ATOM_READ0_U = 0x2417 # macro +regGDS_ATOM_READ0_U_BASE_IDX = 1 # macro +regGDS_ATOM_READ1 = 0x2418 # macro +regGDS_ATOM_READ1_BASE_IDX = 1 # macro +regGDS_ATOM_READ1_U = 0x2419 # macro +regGDS_ATOM_READ1_U_BASE_IDX = 1 # macro +regGDS_GWS_RESOURCE_CNTL = 0x241a # macro +regGDS_GWS_RESOURCE_CNTL_BASE_IDX = 1 # macro +regGDS_GWS_RESOURCE = 0x241b # macro +regGDS_GWS_RESOURCE_BASE_IDX = 1 # macro +regGDS_GWS_RESOURCE_CNT = 0x241c # macro +regGDS_GWS_RESOURCE_CNT_BASE_IDX = 1 # macro +regGDS_OA_CNTL = 0x241d # macro +regGDS_OA_CNTL_BASE_IDX = 1 # macro +regGDS_OA_COUNTER = 0x241e # macro +regGDS_OA_COUNTER_BASE_IDX = 1 # macro +regGDS_OA_ADDRESS = 0x241f # macro +regGDS_OA_ADDRESS_BASE_IDX = 1 # macro +regGDS_OA_INCDEC = 0x2420 # macro +regGDS_OA_INCDEC_BASE_IDX = 1 # macro +regGDS_OA_RING_SIZE = 0x2421 # macro +regGDS_OA_RING_SIZE_BASE_IDX = 1 # macro +regSPI_CONFIG_CNTL = 0x2440 # macro +regSPI_CONFIG_CNTL_BASE_IDX = 1 # macro +regSPI_CONFIG_CNTL_1 = 0x2441 # macro +regSPI_CONFIG_CNTL_1_BASE_IDX = 1 # macro +regSPI_CONFIG_CNTL_2 = 0x2442 # macro +regSPI_CONFIG_CNTL_2_BASE_IDX = 1 # macro +regSPI_WAVE_LIMIT_CNTL = 0x2443 # macro +regSPI_WAVE_LIMIT_CNTL_BASE_IDX = 1 # macro +regGC_CANE_ERR_STATUS = 0x2f4d # macro +regGC_CANE_ERR_STATUS_BASE_IDX = 1 # macro +regGC_CANE_UE_ERR_STATUS_LO = 0x2f4e # macro +regGC_CANE_UE_ERR_STATUS_LO_BASE_IDX = 1 # macro +regGC_CANE_UE_ERR_STATUS_HI = 0x2f4f # macro +regGC_CANE_UE_ERR_STATUS_HI_BASE_IDX = 1 # macro +regGC_CANE_CE_ERR_STATUS_LO = 0x2f50 # macro +regGC_CANE_CE_ERR_STATUS_LO_BASE_IDX = 1 # macro +regGC_CANE_CE_ERR_STATUS_HI = 0x2f51 # macro +regGC_CANE_CE_ERR_STATUS_HI_BASE_IDX = 1 # macro +regCPG_PERFCOUNTER1_LO = 0x3000 # macro +regCPG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regCPG_PERFCOUNTER1_HI = 0x3001 # macro +regCPG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regCPG_PERFCOUNTER0_LO = 0x3002 # macro +regCPG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regCPG_PERFCOUNTER0_HI = 0x3003 # macro +regCPG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regCPC_PERFCOUNTER1_LO = 0x3004 # macro +regCPC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regCPC_PERFCOUNTER1_HI = 0x3005 # macro +regCPC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regCPC_PERFCOUNTER0_LO = 0x3006 # macro +regCPC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regCPC_PERFCOUNTER0_HI = 0x3007 # macro +regCPC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regCPF_PERFCOUNTER1_LO = 0x3008 # macro +regCPF_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regCPF_PERFCOUNTER1_HI = 0x3009 # macro +regCPF_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regCPF_PERFCOUNTER0_LO = 0x300a # macro +regCPF_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regCPF_PERFCOUNTER0_HI = 0x300b # macro +regCPF_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regCPF_LATENCY_STATS_DATA = 0x300c # macro +regCPF_LATENCY_STATS_DATA_BASE_IDX = 1 # macro +regCPG_LATENCY_STATS_DATA = 0x300d # macro +regCPG_LATENCY_STATS_DATA_BASE_IDX = 1 # macro +regCPC_LATENCY_STATS_DATA = 0x300e # macro +regCPC_LATENCY_STATS_DATA_BASE_IDX = 1 # macro +regGRBM_PERFCOUNTER0_LO = 0x3040 # macro +regGRBM_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regGRBM_PERFCOUNTER0_HI = 0x3041 # macro +regGRBM_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regGRBM_PERFCOUNTER1_LO = 0x3043 # macro +regGRBM_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regGRBM_PERFCOUNTER1_HI = 0x3044 # macro +regGRBM_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regGRBM_SE0_PERFCOUNTER_LO = 0x3045 # macro +regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX = 1 # macro +regGRBM_SE0_PERFCOUNTER_HI = 0x3046 # macro +regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX = 1 # macro +regGRBM_SE1_PERFCOUNTER_LO = 0x3047 # macro +regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX = 1 # macro +regGRBM_SE1_PERFCOUNTER_HI = 0x3048 # macro +regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX = 1 # macro +regGRBM_SE2_PERFCOUNTER_LO = 0x3049 # macro +regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX = 1 # macro +regGRBM_SE2_PERFCOUNTER_HI = 0x304a # macro +regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX = 1 # macro +regGRBM_SE3_PERFCOUNTER_LO = 0x304b # macro +regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX = 1 # macro +regGRBM_SE3_PERFCOUNTER_HI = 0x304c # macro +regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX = 1 # macro +regWD_PERFCOUNTER0_LO = 0x3080 # macro +regWD_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regWD_PERFCOUNTER0_HI = 0x3081 # macro +regWD_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regWD_PERFCOUNTER1_LO = 0x3082 # macro +regWD_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regWD_PERFCOUNTER1_HI = 0x3083 # macro +regWD_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regWD_PERFCOUNTER2_LO = 0x3084 # macro +regWD_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regWD_PERFCOUNTER2_HI = 0x3085 # macro +regWD_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regWD_PERFCOUNTER3_LO = 0x3086 # macro +regWD_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regWD_PERFCOUNTER3_HI = 0x3087 # macro +regWD_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regIA_PERFCOUNTER0_LO = 0x3088 # macro +regIA_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regIA_PERFCOUNTER0_HI = 0x3089 # macro +regIA_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regIA_PERFCOUNTER1_LO = 0x308a # macro +regIA_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regIA_PERFCOUNTER1_HI = 0x308b # macro +regIA_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regIA_PERFCOUNTER2_LO = 0x308c # macro +regIA_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regIA_PERFCOUNTER2_HI = 0x308d # macro +regIA_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regIA_PERFCOUNTER3_LO = 0x308e # macro +regIA_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regIA_PERFCOUNTER3_HI = 0x308f # macro +regIA_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regVGT_PERFCOUNTER0_LO = 0x3090 # macro +regVGT_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regVGT_PERFCOUNTER0_HI = 0x3091 # macro +regVGT_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regVGT_PERFCOUNTER1_LO = 0x3092 # macro +regVGT_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regVGT_PERFCOUNTER1_HI = 0x3093 # macro +regVGT_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regVGT_PERFCOUNTER2_LO = 0x3094 # macro +regVGT_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regVGT_PERFCOUNTER2_HI = 0x3095 # macro +regVGT_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regVGT_PERFCOUNTER3_LO = 0x3096 # macro +regVGT_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regVGT_PERFCOUNTER3_HI = 0x3097 # macro +regVGT_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER0_LO = 0x3100 # macro +regPA_SU_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER0_HI = 0x3101 # macro +regPA_SU_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER1_LO = 0x3102 # macro +regPA_SU_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER1_HI = 0x3103 # macro +regPA_SU_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER2_LO = 0x3104 # macro +regPA_SU_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER2_HI = 0x3105 # macro +regPA_SU_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER3_LO = 0x3106 # macro +regPA_SU_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER3_HI = 0x3107 # macro +regPA_SU_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER0_LO = 0x3140 # macro +regPA_SC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER0_HI = 0x3141 # macro +regPA_SC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER1_LO = 0x3142 # macro +regPA_SC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER1_HI = 0x3143 # macro +regPA_SC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER2_LO = 0x3144 # macro +regPA_SC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER2_HI = 0x3145 # macro +regPA_SC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER3_LO = 0x3146 # macro +regPA_SC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER3_HI = 0x3147 # macro +regPA_SC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER4_LO = 0x3148 # macro +regPA_SC_PERFCOUNTER4_LO_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER4_HI = 0x3149 # macro +regPA_SC_PERFCOUNTER4_HI_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER5_LO = 0x314a # macro +regPA_SC_PERFCOUNTER5_LO_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER5_HI = 0x314b # macro +regPA_SC_PERFCOUNTER5_HI_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER6_LO = 0x314c # macro +regPA_SC_PERFCOUNTER6_LO_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER6_HI = 0x314d # macro +regPA_SC_PERFCOUNTER6_HI_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER7_LO = 0x314e # macro +regPA_SC_PERFCOUNTER7_LO_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER7_HI = 0x314f # macro +regPA_SC_PERFCOUNTER7_HI_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER0_HI = 0x3180 # macro +regSPI_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER0_LO = 0x3181 # macro +regSPI_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER1_HI = 0x3182 # macro +regSPI_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER1_LO = 0x3183 # macro +regSPI_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER2_HI = 0x3184 # macro +regSPI_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER2_LO = 0x3185 # macro +regSPI_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER3_HI = 0x3186 # macro +regSPI_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER3_LO = 0x3187 # macro +regSPI_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER4_HI = 0x3188 # macro +regSPI_PERFCOUNTER4_HI_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER4_LO = 0x3189 # macro +regSPI_PERFCOUNTER4_LO_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER5_HI = 0x318a # macro +regSPI_PERFCOUNTER5_HI_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER5_LO = 0x318b # macro +regSPI_PERFCOUNTER5_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER0_LO = 0x31c0 # macro +regSQ_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER0_HI = 0x31c1 # macro +regSQ_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER1_LO = 0x31c2 # macro +regSQ_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER1_HI = 0x31c3 # macro +regSQ_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER2_LO = 0x31c4 # macro +regSQ_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER2_HI = 0x31c5 # macro +regSQ_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER3_LO = 0x31c6 # macro +regSQ_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER3_HI = 0x31c7 # macro +regSQ_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER4_LO = 0x31c8 # macro +regSQ_PERFCOUNTER4_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER4_HI = 0x31c9 # macro +regSQ_PERFCOUNTER4_HI_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER5_LO = 0x31ca # macro +regSQ_PERFCOUNTER5_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER5_HI = 0x31cb # macro +regSQ_PERFCOUNTER5_HI_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER6_LO = 0x31cc # macro +regSQ_PERFCOUNTER6_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER6_HI = 0x31cd # macro +regSQ_PERFCOUNTER6_HI_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER7_LO = 0x31ce # macro +regSQ_PERFCOUNTER7_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER7_HI = 0x31cf # macro +regSQ_PERFCOUNTER7_HI_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER8_LO = 0x31d0 # macro +regSQ_PERFCOUNTER8_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER8_HI = 0x31d1 # macro +regSQ_PERFCOUNTER8_HI_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER9_LO = 0x31d2 # macro +regSQ_PERFCOUNTER9_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER9_HI = 0x31d3 # macro +regSQ_PERFCOUNTER9_HI_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER10_LO = 0x31d4 # macro +regSQ_PERFCOUNTER10_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER10_HI = 0x31d5 # macro +regSQ_PERFCOUNTER10_HI_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER11_LO = 0x31d6 # macro +regSQ_PERFCOUNTER11_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER11_HI = 0x31d7 # macro +regSQ_PERFCOUNTER11_HI_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER12_LO = 0x31d8 # macro +regSQ_PERFCOUNTER12_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER12_HI = 0x31d9 # macro +regSQ_PERFCOUNTER12_HI_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER13_LO = 0x31da # macro +regSQ_PERFCOUNTER13_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER13_HI = 0x31db # macro +regSQ_PERFCOUNTER13_HI_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER14_LO = 0x31dc # macro +regSQ_PERFCOUNTER14_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER14_HI = 0x31dd # macro +regSQ_PERFCOUNTER14_HI_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER15_LO = 0x31de # macro +regSQ_PERFCOUNTER15_LO_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER15_HI = 0x31df # macro +regSQ_PERFCOUNTER15_HI_BASE_IDX = 1 # macro +regSX_PERFCOUNTER0_LO = 0x3240 # macro +regSX_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regSX_PERFCOUNTER0_HI = 0x3241 # macro +regSX_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regSX_PERFCOUNTER1_LO = 0x3242 # macro +regSX_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regSX_PERFCOUNTER1_HI = 0x3243 # macro +regSX_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regSX_PERFCOUNTER2_LO = 0x3244 # macro +regSX_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regSX_PERFCOUNTER2_HI = 0x3245 # macro +regSX_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regSX_PERFCOUNTER3_LO = 0x3246 # macro +regSX_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regSX_PERFCOUNTER3_HI = 0x3247 # macro +regSX_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER0_LO = 0x3280 # macro +regGDS_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER0_HI = 0x3281 # macro +regGDS_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER1_LO = 0x3282 # macro +regGDS_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER1_HI = 0x3283 # macro +regGDS_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER2_LO = 0x3284 # macro +regGDS_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER2_HI = 0x3285 # macro +regGDS_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER3_LO = 0x3286 # macro +regGDS_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER3_HI = 0x3287 # macro +regGDS_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regTA_PERFCOUNTER0_LO = 0x32c0 # macro +regTA_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regTA_PERFCOUNTER0_HI = 0x32c1 # macro +regTA_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regTA_PERFCOUNTER1_LO = 0x32c2 # macro +regTA_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regTA_PERFCOUNTER1_HI = 0x32c3 # macro +regTA_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regTD_PERFCOUNTER0_LO = 0x3300 # macro +regTD_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regTD_PERFCOUNTER0_HI = 0x3301 # macro +regTD_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regTD_PERFCOUNTER1_LO = 0x3302 # macro +regTD_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regTD_PERFCOUNTER1_HI = 0x3303 # macro +regTD_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER0_LO = 0x3340 # macro +regTCP_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER0_HI = 0x3341 # macro +regTCP_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER1_LO = 0x3342 # macro +regTCP_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER1_HI = 0x3343 # macro +regTCP_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER2_LO = 0x3344 # macro +regTCP_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER2_HI = 0x3345 # macro +regTCP_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER3_LO = 0x3346 # macro +regTCP_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER3_HI = 0x3347 # macro +regTCP_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regTCC_PERFCOUNTER0_LO = 0x3380 # macro +regTCC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regTCC_PERFCOUNTER0_HI = 0x3381 # macro +regTCC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regTCC_PERFCOUNTER1_LO = 0x3382 # macro +regTCC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regTCC_PERFCOUNTER1_HI = 0x3383 # macro +regTCC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regTCC_PERFCOUNTER2_LO = 0x3384 # macro +regTCC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regTCC_PERFCOUNTER2_HI = 0x3385 # macro +regTCC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regTCC_PERFCOUNTER3_LO = 0x3386 # macro +regTCC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regTCC_PERFCOUNTER3_HI = 0x3387 # macro +regTCC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regTCA_PERFCOUNTER0_LO = 0x3390 # macro +regTCA_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regTCA_PERFCOUNTER0_HI = 0x3391 # macro +regTCA_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regTCA_PERFCOUNTER1_LO = 0x3392 # macro +regTCA_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regTCA_PERFCOUNTER1_HI = 0x3393 # macro +regTCA_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regTCA_PERFCOUNTER2_LO = 0x3394 # macro +regTCA_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regTCA_PERFCOUNTER2_HI = 0x3395 # macro +regTCA_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regTCA_PERFCOUNTER3_LO = 0x3396 # macro +regTCA_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regTCA_PERFCOUNTER3_HI = 0x3397 # macro +regTCA_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regCB_PERFCOUNTER0_LO = 0x3406 # macro +regCB_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regCB_PERFCOUNTER0_HI = 0x3407 # macro +regCB_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regCB_PERFCOUNTER1_LO = 0x3408 # macro +regCB_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regCB_PERFCOUNTER1_HI = 0x3409 # macro +regCB_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regCB_PERFCOUNTER2_LO = 0x340a # macro +regCB_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regCB_PERFCOUNTER2_HI = 0x340b # macro +regCB_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regCB_PERFCOUNTER3_LO = 0x340c # macro +regCB_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regCB_PERFCOUNTER3_HI = 0x340d # macro +regCB_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regDB_PERFCOUNTER0_LO = 0x3440 # macro +regDB_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regDB_PERFCOUNTER0_HI = 0x3441 # macro +regDB_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regDB_PERFCOUNTER1_LO = 0x3442 # macro +regDB_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regDB_PERFCOUNTER1_HI = 0x3443 # macro +regDB_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regDB_PERFCOUNTER2_LO = 0x3444 # macro +regDB_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regDB_PERFCOUNTER2_HI = 0x3445 # macro +regDB_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regDB_PERFCOUNTER3_LO = 0x3446 # macro +regDB_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regDB_PERFCOUNTER3_HI = 0x3447 # macro +regDB_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regRLC_PERFCOUNTER0_LO = 0x3480 # macro +regRLC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regRLC_PERFCOUNTER0_HI = 0x3481 # macro +regRLC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regRLC_PERFCOUNTER1_LO = 0x3482 # macro +regRLC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regRLC_PERFCOUNTER1_HI = 0x3483 # macro +regRLC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER0_LO = 0x34c0 # macro +regRMI_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER0_HI = 0x34c1 # macro +regRMI_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER1_LO = 0x34c2 # macro +regRMI_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER1_HI = 0x34c3 # macro +regRMI_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER2_LO = 0x34c4 # macro +regRMI_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER2_HI = 0x34c5 # macro +regRMI_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER3_LO = 0x34c6 # macro +regRMI_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER3_HI = 0x34c7 # macro +regRMI_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +regATC_L2_PERFCOUNTER_LO = 0x3500 # macro +regATC_L2_PERFCOUNTER_LO_BASE_IDX = 1 # macro +regATC_L2_PERFCOUNTER_HI = 0x3501 # macro +regATC_L2_PERFCOUNTER_HI_BASE_IDX = 1 # macro +regMC_VM_L2_PERFCOUNTER_LO = 0x3502 # macro +regMC_VM_L2_PERFCOUNTER_LO_BASE_IDX = 1 # macro +regMC_VM_L2_PERFCOUNTER_HI = 0x3503 # macro +regMC_VM_L2_PERFCOUNTER_HI_BASE_IDX = 1 # macro +regL2TLB_PERFCOUNTER_LO = 0x3512 # macro +regL2TLB_PERFCOUNTER_LO_BASE_IDX = 1 # macro +regL2TLB_PERFCOUNTER_HI = 0x3513 # macro +regL2TLB_PERFCOUNTER_HI_BASE_IDX = 1 # macro +regCPG_PERFCOUNTER1_SELECT = 0x3800 # macro +regCPG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regCPG_PERFCOUNTER0_SELECT1 = 0x3801 # macro +regCPG_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regCPG_PERFCOUNTER0_SELECT = 0x3802 # macro +regCPG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regCPC_PERFCOUNTER1_SELECT = 0x3803 # macro +regCPC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regCPC_PERFCOUNTER0_SELECT1 = 0x3804 # macro +regCPC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regCPF_PERFCOUNTER1_SELECT = 0x3805 # macro +regCPF_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regCPF_PERFCOUNTER0_SELECT1 = 0x3806 # macro +regCPF_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regCPF_PERFCOUNTER0_SELECT = 0x3807 # macro +regCPF_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regCP_PERFMON_CNTL = 0x3808 # macro +regCP_PERFMON_CNTL_BASE_IDX = 1 # macro +regCPC_PERFCOUNTER0_SELECT = 0x3809 # macro +regCPC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regCPF_TC_PERF_COUNTER_WINDOW_SELECT = 0x380a # macro +regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro +regCPG_TC_PERF_COUNTER_WINDOW_SELECT = 0x380b # macro +regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro +regCPF_LATENCY_STATS_SELECT = 0x380c # macro +regCPF_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro +regCPG_LATENCY_STATS_SELECT = 0x380d # macro +regCPG_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro +regCPC_LATENCY_STATS_SELECT = 0x380e # macro +regCPC_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro +regCP_DRAW_OBJECT = 0x3810 # macro +regCP_DRAW_OBJECT_BASE_IDX = 1 # macro +regCP_DRAW_OBJECT_COUNTER = 0x3811 # macro +regCP_DRAW_OBJECT_COUNTER_BASE_IDX = 1 # macro +regCP_DRAW_WINDOW_MASK_HI = 0x3812 # macro +regCP_DRAW_WINDOW_MASK_HI_BASE_IDX = 1 # macro +regCP_DRAW_WINDOW_HI = 0x3813 # macro +regCP_DRAW_WINDOW_HI_BASE_IDX = 1 # macro +regCP_DRAW_WINDOW_LO = 0x3814 # macro +regCP_DRAW_WINDOW_LO_BASE_IDX = 1 # macro +regCP_DRAW_WINDOW_CNTL = 0x3815 # macro +regCP_DRAW_WINDOW_CNTL_BASE_IDX = 1 # macro +regGRBM_PERFCOUNTER0_SELECT = 0x3840 # macro +regGRBM_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regGRBM_PERFCOUNTER1_SELECT = 0x3841 # macro +regGRBM_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regGRBM_SE0_PERFCOUNTER_SELECT = 0x3842 # macro +regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro +regGRBM_SE1_PERFCOUNTER_SELECT = 0x3843 # macro +regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro +regGRBM_SE2_PERFCOUNTER_SELECT = 0x3844 # macro +regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro +regGRBM_SE3_PERFCOUNTER_SELECT = 0x3845 # macro +regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro +regWD_PERFCOUNTER0_SELECT = 0x3880 # macro +regWD_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regWD_PERFCOUNTER1_SELECT = 0x3881 # macro +regWD_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regWD_PERFCOUNTER2_SELECT = 0x3882 # macro +regWD_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regWD_PERFCOUNTER3_SELECT = 0x3883 # macro +regWD_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regIA_PERFCOUNTER0_SELECT = 0x3884 # macro +regIA_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regIA_PERFCOUNTER1_SELECT = 0x3885 # macro +regIA_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regIA_PERFCOUNTER2_SELECT = 0x3886 # macro +regIA_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regIA_PERFCOUNTER3_SELECT = 0x3887 # macro +regIA_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regIA_PERFCOUNTER0_SELECT1 = 0x3888 # macro +regIA_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regVGT_PERFCOUNTER0_SELECT = 0x388c # macro +regVGT_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regVGT_PERFCOUNTER1_SELECT = 0x388d # macro +regVGT_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regVGT_PERFCOUNTER2_SELECT = 0x388e # macro +regVGT_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regVGT_PERFCOUNTER3_SELECT = 0x388f # macro +regVGT_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regVGT_PERFCOUNTER0_SELECT1 = 0x3890 # macro +regVGT_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regVGT_PERFCOUNTER1_SELECT1 = 0x3891 # macro +regVGT_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regVGT_PERFCOUNTER_SEID_MASK = 0x3894 # macro +regVGT_PERFCOUNTER_SEID_MASK_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER0_SELECT = 0x3900 # macro +regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER0_SELECT1 = 0x3901 # macro +regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER1_SELECT = 0x3902 # macro +regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER1_SELECT1 = 0x3903 # macro +regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER2_SELECT = 0x3904 # macro +regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regPA_SU_PERFCOUNTER3_SELECT = 0x3905 # macro +regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER0_SELECT = 0x3940 # macro +regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER0_SELECT1 = 0x3941 # macro +regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER1_SELECT = 0x3942 # macro +regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER2_SELECT = 0x3943 # macro +regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER3_SELECT = 0x3944 # macro +regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER4_SELECT = 0x3945 # macro +regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER5_SELECT = 0x3946 # macro +regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER6_SELECT = 0x3947 # macro +regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro +regPA_SC_PERFCOUNTER7_SELECT = 0x3948 # macro +regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER0_SELECT = 0x3980 # macro +regSPI_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER1_SELECT = 0x3981 # macro +regSPI_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER2_SELECT = 0x3982 # macro +regSPI_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER3_SELECT = 0x3983 # macro +regSPI_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER0_SELECT1 = 0x3984 # macro +regSPI_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER1_SELECT1 = 0x3985 # macro +regSPI_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER2_SELECT1 = 0x3986 # macro +regSPI_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER3_SELECT1 = 0x3987 # macro +regSPI_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER4_SELECT = 0x3988 # macro +regSPI_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER5_SELECT = 0x3989 # macro +regSPI_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro +regSPI_PERFCOUNTER_BINS = 0x398a # macro +regSPI_PERFCOUNTER_BINS_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER0_SELECT = 0x39c0 # macro +regSQ_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER1_SELECT = 0x39c1 # macro +regSQ_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER2_SELECT = 0x39c2 # macro +regSQ_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER3_SELECT = 0x39c3 # macro +regSQ_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER4_SELECT = 0x39c4 # macro +regSQ_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER5_SELECT = 0x39c5 # macro +regSQ_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER6_SELECT = 0x39c6 # macro +regSQ_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER7_SELECT = 0x39c7 # macro +regSQ_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER8_SELECT = 0x39c8 # macro +regSQ_PERFCOUNTER8_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER9_SELECT = 0x39c9 # macro +regSQ_PERFCOUNTER9_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER10_SELECT = 0x39ca # macro +regSQ_PERFCOUNTER10_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER11_SELECT = 0x39cb # macro +regSQ_PERFCOUNTER11_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER12_SELECT = 0x39cc # macro +regSQ_PERFCOUNTER12_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER13_SELECT = 0x39cd # macro +regSQ_PERFCOUNTER13_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER14_SELECT = 0x39ce # macro +regSQ_PERFCOUNTER14_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER15_SELECT = 0x39cf # macro +regSQ_PERFCOUNTER15_SELECT_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER_CTRL = 0x39e0 # macro +regSQ_PERFCOUNTER_CTRL_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER_MASK = 0x39e1 # macro +regSQ_PERFCOUNTER_MASK_BASE_IDX = 1 # macro +regSQ_PERFCOUNTER_CTRL2 = 0x39e2 # macro +regSQ_PERFCOUNTER_CTRL2_BASE_IDX = 1 # macro +regSX_PERFCOUNTER0_SELECT = 0x3a40 # macro +regSX_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regSX_PERFCOUNTER1_SELECT = 0x3a41 # macro +regSX_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regSX_PERFCOUNTER2_SELECT = 0x3a42 # macro +regSX_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regSX_PERFCOUNTER3_SELECT = 0x3a43 # macro +regSX_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regSX_PERFCOUNTER0_SELECT1 = 0x3a44 # macro +regSX_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regSX_PERFCOUNTER1_SELECT1 = 0x3a45 # macro +regSX_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER0_SELECT = 0x3a80 # macro +regGDS_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER1_SELECT = 0x3a81 # macro +regGDS_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER2_SELECT = 0x3a82 # macro +regGDS_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER3_SELECT = 0x3a83 # macro +regGDS_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regGDS_PERFCOUNTER0_SELECT1 = 0x3a84 # macro +regGDS_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regTA_PERFCOUNTER0_SELECT = 0x3ac0 # macro +regTA_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regTA_PERFCOUNTER0_SELECT1 = 0x3ac1 # macro +regTA_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regTA_PERFCOUNTER1_SELECT = 0x3ac2 # macro +regTA_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regTD_PERFCOUNTER0_SELECT = 0x3b00 # macro +regTD_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regTD_PERFCOUNTER0_SELECT1 = 0x3b01 # macro +regTD_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regTD_PERFCOUNTER1_SELECT = 0x3b02 # macro +regTD_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER0_SELECT = 0x3b40 # macro +regTCP_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER0_SELECT1 = 0x3b41 # macro +regTCP_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER1_SELECT = 0x3b42 # macro +regTCP_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER1_SELECT1 = 0x3b43 # macro +regTCP_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER2_SELECT = 0x3b44 # macro +regTCP_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regTCP_PERFCOUNTER3_SELECT = 0x3b45 # macro +regTCP_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regTCC_PERFCOUNTER0_SELECT = 0x3b80 # macro +regTCC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regTCC_PERFCOUNTER0_SELECT1 = 0x3b81 # macro +regTCC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regTCC_PERFCOUNTER1_SELECT = 0x3b82 # macro +regTCC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regTCC_PERFCOUNTER1_SELECT1 = 0x3b83 # macro +regTCC_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regTCC_PERFCOUNTER2_SELECT = 0x3b84 # macro +regTCC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regTCC_PERFCOUNTER3_SELECT = 0x3b85 # macro +regTCC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regTCA_PERFCOUNTER0_SELECT = 0x3b90 # macro +regTCA_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regTCA_PERFCOUNTER0_SELECT1 = 0x3b91 # macro +regTCA_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regTCA_PERFCOUNTER1_SELECT = 0x3b92 # macro +regTCA_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regTCA_PERFCOUNTER1_SELECT1 = 0x3b93 # macro +regTCA_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regTCA_PERFCOUNTER2_SELECT = 0x3b94 # macro +regTCA_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regTCA_PERFCOUNTER3_SELECT = 0x3b95 # macro +regTCA_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regCB_PERFCOUNTER_FILTER = 0x3c00 # macro +regCB_PERFCOUNTER_FILTER_BASE_IDX = 1 # macro +regCB_PERFCOUNTER0_SELECT = 0x3c01 # macro +regCB_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regCB_PERFCOUNTER0_SELECT1 = 0x3c02 # macro +regCB_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regCB_PERFCOUNTER1_SELECT = 0x3c03 # macro +regCB_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regCB_PERFCOUNTER2_SELECT = 0x3c04 # macro +regCB_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regCB_PERFCOUNTER3_SELECT = 0x3c05 # macro +regCB_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regDB_PERFCOUNTER0_SELECT = 0x3c40 # macro +regDB_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regDB_PERFCOUNTER0_SELECT1 = 0x3c41 # macro +regDB_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regDB_PERFCOUNTER1_SELECT = 0x3c42 # macro +regDB_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regDB_PERFCOUNTER1_SELECT1 = 0x3c43 # macro +regDB_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +regDB_PERFCOUNTER2_SELECT = 0x3c44 # macro +regDB_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regDB_PERFCOUNTER3_SELECT = 0x3c46 # macro +regDB_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regRLC_SPM_PERFMON_CNTL = 0x3c80 # macro +regRLC_SPM_PERFMON_CNTL_BASE_IDX = 1 # macro +regRLC_SPM_PERFMON_RING_BASE_LO = 0x3c81 # macro +regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX = 1 # macro +regRLC_SPM_PERFMON_RING_BASE_HI = 0x3c82 # macro +regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX = 1 # macro +regRLC_SPM_PERFMON_RING_SIZE = 0x3c83 # macro +regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX = 1 # macro +regRLC_SPM_PERFMON_SEGMENT_SIZE = 0x3c84 # macro +regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX = 1 # macro +regRLC_SPM_SE_MUXSEL_ADDR = 0x3c85 # macro +regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX = 1 # macro +regRLC_SPM_SE_MUXSEL_DATA = 0x3c86 # macro +regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX = 1 # macro +regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY = 0x3c87 # macro +regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_BASE_IDX = 1 # macro +regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY = 0x3c88 # macro +regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_BASE_IDX = 1 # macro +regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY = 0x3c89 # macro +regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_BASE_IDX = 1 # macro +regRLC_SPM_CB_PERFMON_SAMPLE_DELAY = 0x3c8a # macro +regRLC_SPM_CB_PERFMON_SAMPLE_DELAY_BASE_IDX = 1 # macro +regRLC_SPM_DB_PERFMON_SAMPLE_DELAY = 0x3c8b # macro +regRLC_SPM_DB_PERFMON_SAMPLE_DELAY_BASE_IDX = 1 # macro +regRLC_SPM_PA_PERFMON_SAMPLE_DELAY = 0x3c8c # macro +regRLC_SPM_PA_PERFMON_SAMPLE_DELAY_BASE_IDX = 1 # macro +regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY = 0x3c8d # macro +regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_BASE_IDX = 1 # macro +regRLC_SPM_IA_PERFMON_SAMPLE_DELAY = 0x3c8e # macro +regRLC_SPM_IA_PERFMON_SAMPLE_DELAY_BASE_IDX = 1 # macro +regRLC_SPM_SC_PERFMON_SAMPLE_DELAY = 0x3c90 # macro +regRLC_SPM_SC_PERFMON_SAMPLE_DELAY_BASE_IDX = 1 # macro +regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY = 0x3c91 # macro +regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_BASE_IDX = 1 # macro +regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY = 0x3c92 # macro +regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_BASE_IDX = 1 # macro +regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY = 0x3c93 # macro +regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_BASE_IDX = 1 # macro +regRLC_SPM_TA_PERFMON_SAMPLE_DELAY = 0x3c94 # macro +regRLC_SPM_TA_PERFMON_SAMPLE_DELAY_BASE_IDX = 1 # macro +regRLC_SPM_TD_PERFMON_SAMPLE_DELAY = 0x3c95 # macro +regRLC_SPM_TD_PERFMON_SAMPLE_DELAY_BASE_IDX = 1 # macro +regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY = 0x3c96 # macro +regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_BASE_IDX = 1 # macro +regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY = 0x3c97 # macro +regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_BASE_IDX = 1 # macro +regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY = 0x3c98 # macro +regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_BASE_IDX = 1 # macro +regRLC_SPM_SX_PERFMON_SAMPLE_DELAY = 0x3c9a # macro +regRLC_SPM_SX_PERFMON_SAMPLE_DELAY_BASE_IDX = 1 # macro +regRLC_SPM_GLOBAL_MUXSEL_ADDR = 0x3c9b # macro +regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX = 1 # macro +regRLC_SPM_GLOBAL_MUXSEL_DATA = 0x3c9c # macro +regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX = 1 # macro +regRLC_SPM_RING_RDPTR = 0x3c9d # macro +regRLC_SPM_RING_RDPTR_BASE_IDX = 1 # macro +regRLC_SPM_SEGMENT_THRESHOLD = 0x3c9e # macro +regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX = 1 # macro +regRLC_SPM_RMI_PERFMON_SAMPLE_DELAY = 0x3ca3 # macro +regRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_BASE_IDX = 1 # macro +regRLC_SPM_PERFMON_SAMPLE_DELAY_MAX = 0x3ca4 # macro +regRLC_SPM_PERFMON_SAMPLE_DELAY_MAX_BASE_IDX = 1 # macro +regRLC_PERFMON_CNTL = 0x3cc0 # macro +regRLC_PERFMON_CNTL_BASE_IDX = 1 # macro +regRLC_PERFCOUNTER0_SELECT = 0x3cc1 # macro +regRLC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regRLC_PERFCOUNTER1_SELECT = 0x3cc2 # macro +regRLC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regRLC_GPU_IOV_PERF_CNT_CNTL = 0x3cc3 # macro +regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX = 1 # macro +regRLC_GPU_IOV_PERF_CNT_WR_ADDR = 0x3cc4 # macro +regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX = 1 # macro +regRLC_GPU_IOV_PERF_CNT_WR_DATA = 0x3cc5 # macro +regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX = 1 # macro +regRLC_GPU_IOV_PERF_CNT_RD_ADDR = 0x3cc6 # macro +regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX = 1 # macro +regRLC_GPU_IOV_PERF_CNT_RD_DATA = 0x3cc7 # macro +regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER0_SELECT = 0x3d00 # macro +regRMI_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER0_SELECT1 = 0x3d01 # macro +regRMI_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER1_SELECT = 0x3d02 # macro +regRMI_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER2_SELECT = 0x3d03 # macro +regRMI_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER2_SELECT1 = 0x3d04 # macro +regRMI_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +regRMI_PERFCOUNTER3_SELECT = 0x3d05 # macro +regRMI_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +regRMI_PERF_COUNTER_CNTL = 0x3d06 # macro +regRMI_PERF_COUNTER_CNTL_BASE_IDX = 1 # macro +regATC_L2_PERFCOUNTER0_CFG = 0x3d40 # macro +regATC_L2_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro +regATC_L2_PERFCOUNTER1_CFG = 0x3d41 # macro +regATC_L2_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro +regATC_L2_PERFCOUNTER_RSLT_CNTL = 0x3d42 # macro +regATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro +regMC_VM_L2_PERFCOUNTER0_CFG = 0x3d46 # macro +regMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro +regMC_VM_L2_PERFCOUNTER1_CFG = 0x3d47 # macro +regMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro +regMC_VM_L2_PERFCOUNTER2_CFG = 0x3d48 # macro +regMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX = 1 # macro +regMC_VM_L2_PERFCOUNTER3_CFG = 0x3d49 # macro +regMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX = 1 # macro +regMC_VM_L2_PERFCOUNTER4_CFG = 0x3d4a # macro +regMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX = 1 # macro +regMC_VM_L2_PERFCOUNTER5_CFG = 0x3d4b # macro +regMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX = 1 # macro +regMC_VM_L2_PERFCOUNTER6_CFG = 0x3d4c # macro +regMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX = 1 # macro +regMC_VM_L2_PERFCOUNTER7_CFG = 0x3d4d # macro +regMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX = 1 # macro +regMC_VM_L2_PERFCOUNTER_RSLT_CNTL = 0x3d56 # macro +regMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro +regL2TLB_PERFCOUNTER0_CFG = 0x3d5e # macro +regL2TLB_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro +regL2TLB_PERFCOUNTER1_CFG = 0x3d5f # macro +regL2TLB_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro +regL2TLB_PERFCOUNTER2_CFG = 0x3d60 # macro +regL2TLB_PERFCOUNTER2_CFG_BASE_IDX = 1 # macro +regL2TLB_PERFCOUNTER3_CFG = 0x3d61 # macro +regL2TLB_PERFCOUNTER3_CFG_BASE_IDX = 1 # macro +regL2TLB_PERFCOUNTER_RSLT_CNTL = 0x3d62 # macro +regL2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro +regGDFLL_EDC_HYSTERESIS_CNTL = 0x481b # macro +regGDFLL_EDC_HYSTERESIS_CNTL_BASE_IDX = 1 # macro +regGDFLL_EDC_HYSTERESIS_STAT = 0x481c # macro +regGDFLL_EDC_HYSTERESIS_STAT_BASE_IDX = 1 # macro +regRLC_CNTL = 0x4c00 # macro +regRLC_CNTL_BASE_IDX = 1 # macro +regRLC_CGCG_CGLS_CTRL_2 = 0x4c03 # macro +regRLC_CGCG_CGLS_CTRL_2_BASE_IDX = 1 # macro +regRLC_STAT = 0x4c04 # macro +regRLC_STAT_BASE_IDX = 1 # macro +regRLC_SAFE_MODE = 0x4c05 # macro +regRLC_SAFE_MODE_BASE_IDX = 1 # macro +regRLC_MEM_SLP_CNTL = 0x4c06 # macro +regRLC_MEM_SLP_CNTL_BASE_IDX = 1 # macro +regSMU_RLC_RESPONSE = 0x4c07 # macro +regSMU_RLC_RESPONSE_BASE_IDX = 1 # macro +regRLC_RLCV_SAFE_MODE = 0x4c08 # macro +regRLC_RLCV_SAFE_MODE_BASE_IDX = 1 # macro +regRLC_SMU_SAFE_MODE = 0x4c09 # macro +regRLC_SMU_SAFE_MODE_BASE_IDX = 1 # macro +regRLC_RLCV_COMMAND = 0x4c0a # macro +regRLC_RLCV_COMMAND_BASE_IDX = 1 # macro +regRLC_REFCLOCK_TIMESTAMP_LSB = 0x4c0c # macro +regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX = 1 # macro +regRLC_REFCLOCK_TIMESTAMP_MSB = 0x4c0d # macro +regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX = 1 # macro +regRLC_GPM_TIMER_INT_0 = 0x4c0e # macro +regRLC_GPM_TIMER_INT_0_BASE_IDX = 1 # macro +regRLC_GPM_TIMER_INT_1 = 0x4c0f # macro +regRLC_GPM_TIMER_INT_1_BASE_IDX = 1 # macro +regRLC_GPM_TIMER_INT_2 = 0x4c10 # macro +regRLC_GPM_TIMER_INT_2_BASE_IDX = 1 # macro +regRLC_GPM_TIMER_CTRL = 0x4c11 # macro +regRLC_GPM_TIMER_CTRL_BASE_IDX = 1 # macro +regRLC_LB_CNTR_MAX = 0x4c12 # macro +regRLC_LB_CNTR_MAX_BASE_IDX = 1 # macro +regRLC_GPM_TIMER_STAT = 0x4c13 # macro +regRLC_GPM_TIMER_STAT_BASE_IDX = 1 # macro +regRLC_GPM_TIMER_INT_3 = 0x4c15 # macro +regRLC_GPM_TIMER_INT_3_BASE_IDX = 1 # macro +regRLC_SERDES_WR_NONCU_MASTER_MASK_1 = 0x4c16 # macro +regRLC_SERDES_WR_NONCU_MASTER_MASK_1_BASE_IDX = 1 # macro +regRLC_SERDES_NONCU_MASTER_BUSY_1 = 0x4c17 # macro +regRLC_SERDES_NONCU_MASTER_BUSY_1_BASE_IDX = 1 # macro +regRLC_INT_STAT = 0x4c18 # macro +regRLC_INT_STAT_BASE_IDX = 1 # macro +regRLC_LB_CNTL = 0x4c19 # macro +regRLC_LB_CNTL_BASE_IDX = 1 # macro +regRLC_MGCG_CTRL = 0x4c1a # macro +regRLC_MGCG_CTRL_BASE_IDX = 1 # macro +regRLC_LB_CNTR_INIT = 0x4c1b # macro +regRLC_LB_CNTR_INIT_BASE_IDX = 1 # macro +regRLC_LOAD_BALANCE_CNTR = 0x4c1c # macro +regRLC_LOAD_BALANCE_CNTR_BASE_IDX = 1 # macro +regRLC_JUMP_TABLE_RESTORE = 0x4c1e # macro +regRLC_JUMP_TABLE_RESTORE_BASE_IDX = 1 # macro +regRLC_PG_DELAY_2 = 0x4c1f # macro +regRLC_PG_DELAY_2_BASE_IDX = 1 # macro +regRLC_GPU_CLOCK_COUNT_LSB = 0x4c24 # macro +regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX = 1 # macro +regRLC_GPU_CLOCK_COUNT_MSB = 0x4c25 # macro +regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX = 1 # macro +regRLC_CAPTURE_GPU_CLOCK_COUNT = 0x4c26 # macro +regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX = 1 # macro +regRLC_UCODE_CNTL = 0x4c27 # macro +regRLC_UCODE_CNTL_BASE_IDX = 1 # macro +regRLC_GPM_THREAD_RESET = 0x4c28 # macro +regRLC_GPM_THREAD_RESET_BASE_IDX = 1 # macro +regRLC_GPM_CP_DMA_COMPLETE_T0 = 0x4c29 # macro +regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX = 1 # macro +regRLC_GPM_CP_DMA_COMPLETE_T1 = 0x4c2a # macro +regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX = 1 # macro +regRLC_FIREWALL_VIOLATION = 0x4c2b # macro +regRLC_FIREWALL_VIOLATION_BASE_IDX = 1 # macro +regRLC_CLK_COUNT_GFXCLK_LSB = 0x4c30 # macro +regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX = 1 # macro +regRLC_CLK_COUNT_GFXCLK_MSB = 0x4c31 # macro +regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX = 1 # macro +regRLC_CLK_COUNT_REFCLK_LSB = 0x4c32 # macro +regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX = 1 # macro +regRLC_CLK_COUNT_REFCLK_MSB = 0x4c33 # macro +regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX = 1 # macro +regRLC_CLK_COUNT_CTRL = 0x4c34 # macro +regRLC_CLK_COUNT_CTRL_BASE_IDX = 1 # macro +regRLC_CLK_COUNT_STAT = 0x4c35 # macro +regRLC_CLK_COUNT_STAT_BASE_IDX = 1 # macro +regRLC_GPM_STAT = 0x4c40 # macro +regRLC_GPM_STAT_BASE_IDX = 1 # macro +regRLC_GPU_CLOCK_32_RES_SEL = 0x4c41 # macro +regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX = 1 # macro +regRLC_GPU_CLOCK_32 = 0x4c42 # macro +regRLC_GPU_CLOCK_32_BASE_IDX = 1 # macro +regRLC_PG_CNTL = 0x4c43 # macro +regRLC_PG_CNTL_BASE_IDX = 1 # macro +regRLC_GPM_THREAD_PRIORITY = 0x4c44 # macro +regRLC_GPM_THREAD_PRIORITY_BASE_IDX = 1 # macro +regRLC_GPM_THREAD_ENABLE = 0x4c45 # macro +regRLC_GPM_THREAD_ENABLE_BASE_IDX = 1 # macro +regRLC_CGTT_MGCG_OVERRIDE = 0x4c48 # macro +regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX = 1 # macro +regRLC_CGCG_CGLS_CTRL = 0x4c49 # macro +regRLC_CGCG_CGLS_CTRL_BASE_IDX = 1 # macro +regRLC_CGCG_RAMP_CTRL = 0x4c4a # macro +regRLC_CGCG_RAMP_CTRL_BASE_IDX = 1 # macro +regRLC_DYN_PG_STATUS = 0x4c4b # macro +regRLC_DYN_PG_STATUS_BASE_IDX = 1 # macro +regRLC_DYN_PG_REQUEST = 0x4c4c # macro +regRLC_DYN_PG_REQUEST_BASE_IDX = 1 # macro +regRLC_PG_DELAY = 0x4c4d # macro +regRLC_PG_DELAY_BASE_IDX = 1 # macro +regRLC_CU_STATUS = 0x4c4e # macro +regRLC_CU_STATUS_BASE_IDX = 1 # macro +regRLC_LB_INIT_CU_MASK = 0x4c4f # macro +regRLC_LB_INIT_CU_MASK_BASE_IDX = 1 # macro +regRLC_LB_ALWAYS_ACTIVE_CU_MASK = 0x4c50 # macro +regRLC_LB_ALWAYS_ACTIVE_CU_MASK_BASE_IDX = 1 # macro +regRLC_LB_PARAMS = 0x4c51 # macro +regRLC_LB_PARAMS_BASE_IDX = 1 # macro +regRLC_THREAD1_DELAY = 0x4c52 # macro +regRLC_THREAD1_DELAY_BASE_IDX = 1 # macro +regRLC_PG_ALWAYS_ON_CU_MASK = 0x4c53 # macro +regRLC_PG_ALWAYS_ON_CU_MASK_BASE_IDX = 1 # macro +regRLC_MAX_PG_CU = 0x4c54 # macro +regRLC_MAX_PG_CU_BASE_IDX = 1 # macro +regRLC_AUTO_PG_CTRL = 0x4c55 # macro +regRLC_AUTO_PG_CTRL_BASE_IDX = 1 # macro +regRLC_SMU_GRBM_REG_SAVE_CTRL = 0x4c56 # macro +regRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX = 1 # macro +regRLC_SERDES_RD_PENDING = 0x4c58 # macro +regRLC_SERDES_RD_PENDING_BASE_IDX = 1 # macro +regRLC_SERDES_RD_MASTER_INDEX = 0x4c59 # macro +regRLC_SERDES_RD_MASTER_INDEX_BASE_IDX = 1 # macro +regRLC_SERDES_RD_DATA_0 = 0x4c5a # macro +regRLC_SERDES_RD_DATA_0_BASE_IDX = 1 # macro +regRLC_SERDES_RD_DATA_1 = 0x4c5b # macro +regRLC_SERDES_RD_DATA_1_BASE_IDX = 1 # macro +regRLC_SERDES_RD_DATA_2 = 0x4c5c # macro +regRLC_SERDES_RD_DATA_2_BASE_IDX = 1 # macro +regRLC_SERDES_WR_CU_MASTER_MASK = 0x4c5d # macro +regRLC_SERDES_WR_CU_MASTER_MASK_BASE_IDX = 1 # macro +regRLC_SERDES_WR_NONCU_MASTER_MASK = 0x4c5e # macro +regRLC_SERDES_WR_NONCU_MASTER_MASK_BASE_IDX = 1 # macro +regRLC_SERDES_WR_CTRL = 0x4c5f # macro +regRLC_SERDES_WR_CTRL_BASE_IDX = 1 # macro +regRLC_SERDES_WR_DATA = 0x4c60 # macro +regRLC_SERDES_WR_DATA_BASE_IDX = 1 # macro +regRLC_SERDES_CU_MASTER_BUSY = 0x4c61 # macro +regRLC_SERDES_CU_MASTER_BUSY_BASE_IDX = 1 # macro +regRLC_SERDES_NONCU_MASTER_BUSY = 0x4c62 # macro +regRLC_SERDES_NONCU_MASTER_BUSY_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_0 = 0x4c63 # macro +regRLC_GPM_GENERAL_0_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_1 = 0x4c64 # macro +regRLC_GPM_GENERAL_1_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_2 = 0x4c65 # macro +regRLC_GPM_GENERAL_2_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_3 = 0x4c66 # macro +regRLC_GPM_GENERAL_3_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_4 = 0x4c67 # macro +regRLC_GPM_GENERAL_4_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_5 = 0x4c68 # macro +regRLC_GPM_GENERAL_5_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_6 = 0x4c69 # macro +regRLC_GPM_GENERAL_6_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_7 = 0x4c6a # macro +regRLC_GPM_GENERAL_7_BASE_IDX = 1 # macro +regRLC_GPM_SCRATCH_ADDR = 0x4c6c # macro +regRLC_GPM_SCRATCH_ADDR_BASE_IDX = 1 # macro +regRLC_GPM_SCRATCH_DATA = 0x4c6d # macro +regRLC_GPM_SCRATCH_DATA_BASE_IDX = 1 # macro +regRLC_STATIC_PG_STATUS = 0x4c6e # macro +regRLC_STATIC_PG_STATUS_BASE_IDX = 1 # macro +regRLC_SPM_MC_CNTL = 0x4c71 # macro +regRLC_SPM_MC_CNTL_BASE_IDX = 1 # macro +regRLC_SPM_INT_CNTL = 0x4c72 # macro +regRLC_SPM_INT_CNTL_BASE_IDX = 1 # macro +regRLC_SPM_INT_STATUS = 0x4c73 # macro +regRLC_SPM_INT_STATUS_BASE_IDX = 1 # macro +regRLC_SMU_MESSAGE = 0x4c76 # macro +regRLC_SMU_MESSAGE_BASE_IDX = 1 # macro +regRLC_GPM_LOG_SIZE = 0x4c77 # macro +regRLC_GPM_LOG_SIZE_BASE_IDX = 1 # macro +regRLC_PG_DELAY_3 = 0x4c78 # macro +regRLC_PG_DELAY_3_BASE_IDX = 1 # macro +regRLC_GPR_REG1 = 0x4c79 # macro +regRLC_GPR_REG1_BASE_IDX = 1 # macro +regRLC_GPR_REG2 = 0x4c7a # macro +regRLC_GPR_REG2_BASE_IDX = 1 # macro +regRLC_GPM_LOG_CONT = 0x4c7b # macro +regRLC_GPM_LOG_CONT_BASE_IDX = 1 # macro +regRLC_GPM_INT_DISABLE_TH0 = 0x4c7c # macro +regRLC_GPM_INT_DISABLE_TH0_BASE_IDX = 1 # macro +regRLC_GPM_INT_FORCE_TH0 = 0x4c7e # macro +regRLC_GPM_INT_FORCE_TH0_BASE_IDX = 1 # macro +regRLC_GPM_INT_FORCE_TH1 = 0x4c7f # macro +regRLC_GPM_INT_FORCE_TH1_BASE_IDX = 1 # macro +regRLC_SRM_CNTL = 0x4c80 # macro +regRLC_SRM_CNTL_BASE_IDX = 1 # macro +regRLC_SRM_ARAM_ADDR = 0x4c83 # macro +regRLC_SRM_ARAM_ADDR_BASE_IDX = 1 # macro +regRLC_SRM_ARAM_DATA = 0x4c84 # macro +regRLC_SRM_ARAM_DATA_BASE_IDX = 1 # macro +regRLC_SRM_DRAM_ADDR = 0x4c85 # macro +regRLC_SRM_DRAM_ADDR_BASE_IDX = 1 # macro +regRLC_SRM_DRAM_DATA = 0x4c86 # macro +regRLC_SRM_DRAM_DATA_BASE_IDX = 1 # macro +regRLC_SRM_GPM_COMMAND = 0x4c87 # macro +regRLC_SRM_GPM_COMMAND_BASE_IDX = 1 # macro +regRLC_SRM_GPM_COMMAND_STATUS = 0x4c88 # macro +regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX = 1 # macro +regRLC_SRM_RLCV_COMMAND = 0x4c89 # macro +regRLC_SRM_RLCV_COMMAND_BASE_IDX = 1 # macro +regRLC_SRM_RLCV_COMMAND_STATUS = 0x4c8a # macro +regRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_ADDR_0 = 0x4c8b # macro +regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_ADDR_1 = 0x4c8c # macro +regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_ADDR_2 = 0x4c8d # macro +regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_ADDR_3 = 0x4c8e # macro +regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_ADDR_4 = 0x4c8f # macro +regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_ADDR_5 = 0x4c90 # macro +regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_ADDR_6 = 0x4c91 # macro +regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_ADDR_7 = 0x4c92 # macro +regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_DATA_0 = 0x4c93 # macro +regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_DATA_1 = 0x4c94 # macro +regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_DATA_2 = 0x4c95 # macro +regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_DATA_3 = 0x4c96 # macro +regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_DATA_4 = 0x4c97 # macro +regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_DATA_5 = 0x4c98 # macro +regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_DATA_6 = 0x4c99 # macro +regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX = 1 # macro +regRLC_SRM_INDEX_CNTL_DATA_7 = 0x4c9a # macro +regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX = 1 # macro +regRLC_SRM_STAT = 0x4c9b # macro +regRLC_SRM_STAT_BASE_IDX = 1 # macro +regRLC_SRM_GPM_ABORT = 0x4c9c # macro +regRLC_SRM_GPM_ABORT_BASE_IDX = 1 # macro +regRLC_CSIB_ADDR_LO = 0x4ca2 # macro +regRLC_CSIB_ADDR_LO_BASE_IDX = 1 # macro +regRLC_CSIB_ADDR_HI = 0x4ca3 # macro +regRLC_CSIB_ADDR_HI_BASE_IDX = 1 # macro +regRLC_CSIB_LENGTH = 0x4ca4 # macro +regRLC_CSIB_LENGTH_BASE_IDX = 1 # macro +regRLC_SMU_COMMAND = 0x4ca9 # macro +regRLC_SMU_COMMAND_BASE_IDX = 1 # macro +regRLC_CP_SCHEDULERS = 0x4caa # macro +regRLC_CP_SCHEDULERS_BASE_IDX = 1 # macro +regRLC_SMU_ARGUMENT_1 = 0x4cab # macro +regRLC_SMU_ARGUMENT_1_BASE_IDX = 1 # macro +regRLC_SMU_ARGUMENT_2 = 0x4cac # macro +regRLC_SMU_ARGUMENT_2_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_8 = 0x4cad # macro +regRLC_GPM_GENERAL_8_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_9 = 0x4cae # macro +regRLC_GPM_GENERAL_9_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_10 = 0x4caf # macro +regRLC_GPM_GENERAL_10_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_11 = 0x4cb0 # macro +regRLC_GPM_GENERAL_11_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_12 = 0x4cb1 # macro +regRLC_GPM_GENERAL_12_BASE_IDX = 1 # macro +regRLC_GPM_UTCL1_CNTL_0 = 0x4cb2 # macro +regRLC_GPM_UTCL1_CNTL_0_BASE_IDX = 1 # macro +regRLC_GPM_UTCL1_CNTL_1 = 0x4cb3 # macro +regRLC_GPM_UTCL1_CNTL_1_BASE_IDX = 1 # macro +regRLC_GPM_UTCL1_CNTL_2 = 0x4cb4 # macro +regRLC_GPM_UTCL1_CNTL_2_BASE_IDX = 1 # macro +regRLC_SPM_UTCL1_CNTL = 0x4cb5 # macro +regRLC_SPM_UTCL1_CNTL_BASE_IDX = 1 # macro +regRLC_UTCL1_STATUS_2 = 0x4cb6 # macro +regRLC_UTCL1_STATUS_2_BASE_IDX = 1 # macro +regRLC_LB_THR_CONFIG_2 = 0x4cb8 # macro +regRLC_LB_THR_CONFIG_2_BASE_IDX = 1 # macro +regRLC_LB_THR_CONFIG_3 = 0x4cb9 # macro +regRLC_LB_THR_CONFIG_3_BASE_IDX = 1 # macro +regRLC_LB_THR_CONFIG_4 = 0x4cba # macro +regRLC_LB_THR_CONFIG_4_BASE_IDX = 1 # macro +regRLC_SPM_UTCL1_ERROR_1 = 0x4cbc # macro +regRLC_SPM_UTCL1_ERROR_1_BASE_IDX = 1 # macro +regRLC_SPM_UTCL1_ERROR_2 = 0x4cbd # macro +regRLC_SPM_UTCL1_ERROR_2_BASE_IDX = 1 # macro +regRLC_GPM_UTCL1_TH0_ERROR_1 = 0x4cbe # macro +regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX = 1 # macro +regRLC_LB_THR_CONFIG_1 = 0x4cbf # macro +regRLC_LB_THR_CONFIG_1_BASE_IDX = 1 # macro +regRLC_GPM_UTCL1_TH0_ERROR_2 = 0x4cc0 # macro +regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX = 1 # macro +regRLC_GPM_UTCL1_TH1_ERROR_1 = 0x4cc1 # macro +regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX = 1 # macro +regRLC_GPM_UTCL1_TH1_ERROR_2 = 0x4cc2 # macro +regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX = 1 # macro +regRLC_GPM_UTCL1_TH2_ERROR_1 = 0x4cc3 # macro +regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX = 1 # macro +regRLC_GPM_UTCL1_TH2_ERROR_2 = 0x4cc4 # macro +regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX = 1 # macro +regRLC_SEMAPHORE_0 = 0x4cc7 # macro +regRLC_SEMAPHORE_0_BASE_IDX = 1 # macro +regRLC_SEMAPHORE_1 = 0x4cc8 # macro +regRLC_SEMAPHORE_1_BASE_IDX = 1 # macro +regRLC_CP_EOF_INT = 0x4cca # macro +regRLC_CP_EOF_INT_BASE_IDX = 1 # macro +regRLC_CP_EOF_INT_CNT = 0x4ccb # macro +regRLC_CP_EOF_INT_CNT_BASE_IDX = 1 # macro +regRLC_SPARE_INT = 0x4ccc # macro +regRLC_SPARE_INT_BASE_IDX = 1 # macro +regRLC_PREWALKER_UTCL1_CNTL = 0x4ccd # macro +regRLC_PREWALKER_UTCL1_CNTL_BASE_IDX = 1 # macro +regRLC_PREWALKER_UTCL1_TRIG = 0x4cce # macro +regRLC_PREWALKER_UTCL1_TRIG_BASE_IDX = 1 # macro +regRLC_PREWALKER_UTCL1_ADDR_LSB = 0x4ccf # macro +regRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX = 1 # macro +regRLC_PREWALKER_UTCL1_ADDR_MSB = 0x4cd0 # macro +regRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX = 1 # macro +regRLC_PREWALKER_UTCL1_SIZE_LSB = 0x4cd1 # macro +regRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX = 1 # macro +regRLC_PREWALKER_UTCL1_SIZE_MSB = 0x4cd2 # macro +regRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX = 1 # macro +regRLC_DSM_TRIG = 0x4cd3 # macro +regRLC_DSM_TRIG_BASE_IDX = 1 # macro +regRLC_UTCL1_STATUS = 0x4cd4 # macro +regRLC_UTCL1_STATUS_BASE_IDX = 1 # macro +regRLC_R2I_CNTL_0 = 0x4cd5 # macro +regRLC_R2I_CNTL_0_BASE_IDX = 1 # macro +regRLC_R2I_CNTL_1 = 0x4cd6 # macro +regRLC_R2I_CNTL_1_BASE_IDX = 1 # macro +regRLC_R2I_CNTL_2 = 0x4cd7 # macro +regRLC_R2I_CNTL_2_BASE_IDX = 1 # macro +regRLC_R2I_CNTL_3 = 0x4cd8 # macro +regRLC_R2I_CNTL_3_BASE_IDX = 1 # macro +regRLC_UTCL2_CNTL = 0x4cd9 # macro +regRLC_UTCL2_CNTL_BASE_IDX = 1 # macro +regRLC_LBPW_CU_STAT = 0x4cda # macro +regRLC_LBPW_CU_STAT_BASE_IDX = 1 # macro +regRLC_DS_CNTL = 0x4cdb # macro +regRLC_DS_CNTL_BASE_IDX = 1 # macro +regRLC_GPM_INT_STAT_TH0 = 0x4cdc # macro +regRLC_GPM_INT_STAT_TH0_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_13 = 0x4cdd # macro +regRLC_GPM_GENERAL_13_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_14 = 0x4cde # macro +regRLC_GPM_GENERAL_14_BASE_IDX = 1 # macro +regRLC_GPM_GENERAL_15 = 0x4cdf # macro +regRLC_GPM_GENERAL_15_BASE_IDX = 1 # macro +regRLC_SPARE_INT_1 = 0x4ce0 # macro +regRLC_SPARE_INT_1_BASE_IDX = 1 # macro +regRLC_RLCV_SPARE_INT_1 = 0x4ce1 # macro +regRLC_RLCV_SPARE_INT_1_BASE_IDX = 1 # macro +regRLC_SEMAPHORE_2 = 0x4ce3 # macro +regRLC_SEMAPHORE_2_BASE_IDX = 1 # macro +regRLC_SEMAPHORE_3 = 0x4ce4 # macro +regRLC_SEMAPHORE_3_BASE_IDX = 1 # macro +regRLC_SMU_ARGUMENT_3 = 0x4ce5 # macro +regRLC_SMU_ARGUMENT_3_BASE_IDX = 1 # macro +regRLC_SMU_ARGUMENT_4 = 0x4ce6 # macro +regRLC_SMU_ARGUMENT_4_BASE_IDX = 1 # macro +regRLC_GPU_CLOCK_COUNT_LSB_1 = 0x4ce8 # macro +regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX = 1 # macro +regRLC_GPU_CLOCK_COUNT_MSB_1 = 0x4ce9 # macro +regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX = 1 # macro +regRLC_CAPTURE_GPU_CLOCK_COUNT_1 = 0x4cea # macro +regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX = 1 # macro +regRLC_GPU_CLOCK_COUNT_LSB_2 = 0x4ceb # macro +regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX = 1 # macro +regRLC_GPU_CLOCK_COUNT_MSB_2 = 0x4cec # macro +regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX = 1 # macro +regRLC_CAPTURE_GPU_CLOCK_COUNT_2 = 0x4cef # macro +regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX = 1 # macro +regRLC_CPG_STAT_INVAL = 0x4d09 # macro +regRLC_CPG_STAT_INVAL_BASE_IDX = 1 # macro +regRLC_UE_ERR_STATUS_LOW = 0x4d40 # macro +regRLC_UE_ERR_STATUS_LOW_BASE_IDX = 1 # macro +regRLC_UE_ERR_STATUS_HIGH = 0x4d41 # macro +regRLC_UE_ERR_STATUS_HIGH_BASE_IDX = 1 # macro +regRLC_DSM_CNTL = 0x4d42 # macro +regRLC_DSM_CNTL_BASE_IDX = 1 # macro +regRLC_DSM_CNTLA = 0x4d43 # macro +regRLC_DSM_CNTLA_BASE_IDX = 1 # macro +regRLC_DSM_CNTL2 = 0x4d44 # macro +regRLC_DSM_CNTL2_BASE_IDX = 1 # macro +regRLC_DSM_CNTL2A = 0x4d45 # macro +regRLC_DSM_CNTL2A_BASE_IDX = 1 # macro +regRLC_CE_ERR_STATUS_LOW = 0x4d49 # macro +regRLC_CE_ERR_STATUS_LOW_BASE_IDX = 1 # macro +regRLC_CE_ERR_STATUS_HIGH = 0x4d4a # macro +regRLC_CE_ERR_STATUS_HIGH_BASE_IDX = 1 # macro +regRLC_RLCV_SPARE_INT = 0x4f30 # macro +regRLC_RLCV_SPARE_INT_BASE_IDX = 1 # macro +regRLC_SMU_CLK_REQ = 0x4f97 # macro +regRLC_SMU_CLK_REQ_BASE_IDX = 1 # macro +regCGTS_SM_CTRL_REG = 0x5000 # macro +regCGTS_SM_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_RD_CTRL_REG = 0x5001 # macro +regCGTS_RD_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_RD_REG = 0x5002 # macro +regCGTS_RD_REG_BASE_IDX = 1 # macro +regCGTS_TCC_DISABLE = 0x5003 # macro +regCGTS_TCC_DISABLE_BASE_IDX = 1 # macro +regCGTS_USER_TCC_DISABLE = 0x5004 # macro +regCGTS_USER_TCC_DISABLE_BASE_IDX = 1 # macro +regCGTS_CU0_SP0_CTRL_REG = 0x5008 # macro +regCGTS_CU0_SP0_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU0_LDS_SQ_CTRL_REG = 0x5009 # macro +regCGTS_CU0_LDS_SQ_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU0_TA_SQC_CTRL_REG = 0x500a # macro +regCGTS_CU0_TA_SQC_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU0_SP1_CTRL_REG = 0x500b # macro +regCGTS_CU0_SP1_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU0_TD_TCP_CTRL_REG = 0x500c # macro +regCGTS_CU0_TD_TCP_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU1_SP0_CTRL_REG = 0x500d # macro +regCGTS_CU1_SP0_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU1_LDS_SQ_CTRL_REG = 0x500e # macro +regCGTS_CU1_LDS_SQ_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU1_TA_SQC_CTRL_REG = 0x500f # macro +regCGTS_CU1_TA_SQC_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU1_SP1_CTRL_REG = 0x5010 # macro +regCGTS_CU1_SP1_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU1_TD_TCP_CTRL_REG = 0x5011 # macro +regCGTS_CU1_TD_TCP_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU2_SP0_CTRL_REG = 0x5012 # macro +regCGTS_CU2_SP0_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU2_LDS_SQ_CTRL_REG = 0x5013 # macro +regCGTS_CU2_LDS_SQ_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU2_TA_SQC_CTRL_REG = 0x5014 # macro +regCGTS_CU2_TA_SQC_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU2_SP1_CTRL_REG = 0x5015 # macro +regCGTS_CU2_SP1_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU2_TD_TCP_CTRL_REG = 0x5016 # macro +regCGTS_CU2_TD_TCP_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU3_SP0_CTRL_REG = 0x5017 # macro +regCGTS_CU3_SP0_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU3_LDS_SQ_CTRL_REG = 0x5018 # macro +regCGTS_CU3_LDS_SQ_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU3_TA_SQC_CTRL_REG = 0x5019 # macro +regCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU3_SP1_CTRL_REG = 0x501a # macro +regCGTS_CU3_SP1_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU3_TD_TCP_CTRL_REG = 0x501b # macro +regCGTS_CU3_TD_TCP_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU4_SP0_CTRL_REG = 0x501c # macro +regCGTS_CU4_SP0_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU4_LDS_SQ_CTRL_REG = 0x501d # macro +regCGTS_CU4_LDS_SQ_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU4_TA_SQC_CTRL_REG = 0x501e # macro +regCGTS_CU4_TA_SQC_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU4_SP1_CTRL_REG = 0x501f # macro +regCGTS_CU4_SP1_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU4_TD_TCP_CTRL_REG = 0x5020 # macro +regCGTS_CU4_TD_TCP_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU5_SP0_CTRL_REG = 0x5021 # macro +regCGTS_CU5_SP0_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU5_LDS_SQ_CTRL_REG = 0x5022 # macro +regCGTS_CU5_LDS_SQ_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU5_TA_SQC_CTRL_REG = 0x5023 # macro +regCGTS_CU5_TA_SQC_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU5_SP1_CTRL_REG = 0x5024 # macro +regCGTS_CU5_SP1_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU5_TD_TCP_CTRL_REG = 0x5025 # macro +regCGTS_CU5_TD_TCP_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU6_SP0_CTRL_REG = 0x5026 # macro +regCGTS_CU6_SP0_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU6_LDS_SQ_CTRL_REG = 0x5027 # macro +regCGTS_CU6_LDS_SQ_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU6_TA_SQC_CTRL_REG = 0x5028 # macro +regCGTS_CU6_TA_SQC_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU6_SP1_CTRL_REG = 0x5029 # macro +regCGTS_CU6_SP1_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU6_TD_TCP_CTRL_REG = 0x502a # macro +regCGTS_CU6_TD_TCP_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU7_SP0_CTRL_REG = 0x502b # macro +regCGTS_CU7_SP0_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU7_LDS_SQ_CTRL_REG = 0x502c # macro +regCGTS_CU7_LDS_SQ_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU7_TA_SQC_CTRL_REG = 0x502d # macro +regCGTS_CU7_TA_SQC_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU7_SP1_CTRL_REG = 0x502e # macro +regCGTS_CU7_SP1_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU7_TD_TCP_CTRL_REG = 0x502f # macro +regCGTS_CU7_TD_TCP_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU8_SP0_CTRL_REG = 0x5030 # macro +regCGTS_CU8_SP0_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU8_LDS_SQ_CTRL_REG = 0x5031 # macro +regCGTS_CU8_LDS_SQ_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU8_TA_SQC_CTRL_REG = 0x5032 # macro +regCGTS_CU8_TA_SQC_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU8_SP1_CTRL_REG = 0x5033 # macro +regCGTS_CU8_SP1_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU8_TD_TCP_CTRL_REG = 0x5034 # macro +regCGTS_CU8_TD_TCP_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU9_SP0_CTRL_REG = 0x5035 # macro +regCGTS_CU9_SP0_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU9_LDS_SQ_CTRL_REG = 0x5036 # macro +regCGTS_CU9_LDS_SQ_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU9_TA_SQC_CTRL_REG = 0x5037 # macro +regCGTS_CU9_TA_SQC_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU9_SP1_CTRL_REG = 0x5038 # macro +regCGTS_CU9_SP1_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU9_TD_TCP_CTRL_REG = 0x5039 # macro +regCGTS_CU9_TD_TCP_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU10_SP0_CTRL_REG = 0x503a # macro +regCGTS_CU10_SP0_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU10_LDS_SQ_CTRL_REG = 0x503b # macro +regCGTS_CU10_LDS_SQ_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU10_TA_SQC_CTRL_REG = 0x503c # macro +regCGTS_CU10_TA_SQC_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU10_SP1_CTRL_REG = 0x503d # macro +regCGTS_CU10_SP1_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU10_TD_TCP_CTRL_REG = 0x503e # macro +regCGTS_CU10_TD_TCP_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU11_SP0_CTRL_REG = 0x503f # macro +regCGTS_CU11_SP0_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU11_LDS_SQ_CTRL_REG = 0x5040 # macro +regCGTS_CU11_LDS_SQ_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU11_TA_SQC_CTRL_REG = 0x5041 # macro +regCGTS_CU11_TA_SQC_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU11_SP1_CTRL_REG = 0x5042 # macro +regCGTS_CU11_SP1_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU11_TD_TCP_CTRL_REG = 0x5043 # macro +regCGTS_CU11_TD_TCP_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU12_SP0_CTRL_REG = 0x5044 # macro +regCGTS_CU12_SP0_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU12_LDS_SQ_CTRL_REG = 0x5045 # macro +regCGTS_CU12_LDS_SQ_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU12_TA_SQC_CTRL_REG = 0x5046 # macro +regCGTS_CU12_TA_SQC_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU12_SP1_CTRL_REG = 0x5047 # macro +regCGTS_CU12_SP1_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU12_TD_TCP_CTRL_REG = 0x5048 # macro +regCGTS_CU12_TD_TCP_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU13_SP0_CTRL_REG = 0x5049 # macro +regCGTS_CU13_SP0_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU13_LDS_SQ_CTRL_REG = 0x504a # macro +regCGTS_CU13_LDS_SQ_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU13_TA_SQC_CTRL_REG = 0x504b # macro +regCGTS_CU13_TA_SQC_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU13_SP1_CTRL_REG = 0x504c # macro +regCGTS_CU13_SP1_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU13_TD_TCP_CTRL_REG = 0x504d # macro +regCGTS_CU13_TD_TCP_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU14_SP0_CTRL_REG = 0x504e # macro +regCGTS_CU14_SP0_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU14_LDS_SQ_CTRL_REG = 0x504f # macro +regCGTS_CU14_LDS_SQ_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU14_TA_SQC_CTRL_REG = 0x5050 # macro +regCGTS_CU14_TA_SQC_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU14_SP1_CTRL_REG = 0x5051 # macro +regCGTS_CU14_SP1_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU14_TD_TCP_CTRL_REG = 0x5052 # macro +regCGTS_CU14_TD_TCP_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU15_SP0_CTRL_REG = 0x5053 # macro +regCGTS_CU15_SP0_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU15_LDS_SQ_CTRL_REG = 0x5054 # macro +regCGTS_CU15_LDS_SQ_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU15_TA_SQC_CTRL_REG = 0x5055 # macro +regCGTS_CU15_TA_SQC_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU15_SP1_CTRL_REG = 0x5056 # macro +regCGTS_CU15_SP1_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU15_TD_TCP_CTRL_REG = 0x5057 # macro +regCGTS_CU15_TD_TCP_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU0_TCPI_CTRL_REG = 0x5058 # macro +regCGTS_CU0_TCPI_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU1_TCPI_CTRL_REG = 0x5059 # macro +regCGTS_CU1_TCPI_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU2_TCPI_CTRL_REG = 0x505a # macro +regCGTS_CU2_TCPI_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU3_TCPI_CTRL_REG = 0x505b # macro +regCGTS_CU3_TCPI_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU4_TCPI_CTRL_REG = 0x505c # macro +regCGTS_CU4_TCPI_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU5_TCPI_CTRL_REG = 0x505d # macro +regCGTS_CU5_TCPI_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU6_TCPI_CTRL_REG = 0x505e # macro +regCGTS_CU6_TCPI_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU7_TCPI_CTRL_REG = 0x505f # macro +regCGTS_CU7_TCPI_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU8_TCPI_CTRL_REG = 0x5060 # macro +regCGTS_CU8_TCPI_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU9_TCPI_CTRL_REG = 0x5061 # macro +regCGTS_CU9_TCPI_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU10_TCPI_CTRL_REG = 0x5062 # macro +regCGTS_CU10_TCPI_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU11_TCPI_CTRL_REG = 0x5063 # macro +regCGTS_CU11_TCPI_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU12_TCPI_CTRL_REG = 0x5064 # macro +regCGTS_CU12_TCPI_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU13_TCPI_CTRL_REG = 0x5065 # macro +regCGTS_CU13_TCPI_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU14_TCPI_CTRL_REG = 0x5066 # macro +regCGTS_CU14_TCPI_CTRL_REG_BASE_IDX = 1 # macro +regCGTS_CU15_TCPI_CTRL_REG = 0x5067 # macro +regCGTS_CU15_TCPI_CTRL_REG_BASE_IDX = 1 # macro +regCGTT_SPI_PS_CLK_CTRL = 0x507d # macro +regCGTT_SPI_PS_CLK_CTRL_BASE_IDX = 1 # macro +regCGTT_SPIS_CLK_CTRL = 0x507e # macro +regCGTT_SPIS_CLK_CTRL_BASE_IDX = 1 # macro +regCGTX_SPI_DEBUG_CLK_CTRL = 0x507f # macro +regCGTX_SPI_DEBUG_CLK_CTRL_BASE_IDX = 1 # macro +regCGTT_SPI_CLK_CTRL = 0x5080 # macro +regCGTT_SPI_CLK_CTRL_BASE_IDX = 1 # macro +regCGTT_PC_CLK_CTRL = 0x5081 # macro +regCGTT_PC_CLK_CTRL_BASE_IDX = 1 # macro +regCGTT_BCI_CLK_CTRL = 0x5082 # macro +regCGTT_BCI_CLK_CTRL_BASE_IDX = 1 # macro +regCGTT_VGT_CLK_CTRL = 0x5084 # macro +regCGTT_VGT_CLK_CTRL_BASE_IDX = 1 # macro +regCGTT_IA_CLK_CTRL = 0x5085 # macro +regCGTT_IA_CLK_CTRL_BASE_IDX = 1 # macro +regCGTT_WD_CLK_CTRL = 0x5086 # macro +regCGTT_WD_CLK_CTRL_BASE_IDX = 1 # macro +regCGTT_PA_CLK_CTRL = 0x5088 # macro +regCGTT_PA_CLK_CTRL_BASE_IDX = 1 # macro +regCGTT_SC_CLK_CTRL0 = 0x5089 # macro +regCGTT_SC_CLK_CTRL0_BASE_IDX = 1 # macro +regCGTT_SC_CLK_CTRL1 = 0x508a # macro +regCGTT_SC_CLK_CTRL1_BASE_IDX = 1 # macro +regCGTT_SC_CLK_CTRL2 = 0x508b # macro +regCGTT_SC_CLK_CTRL2_BASE_IDX = 1 # macro +regCGTT_SQ_CLK_CTRL = 0x508c # macro +regCGTT_SQ_CLK_CTRL_BASE_IDX = 1 # macro +regCGTT_SQG_CLK_CTRL = 0x508d # macro +regCGTT_SQG_CLK_CTRL_BASE_IDX = 1 # macro +regSQ_ALU_CLK_CTRL = 0x508e # macro +regSQ_ALU_CLK_CTRL_BASE_IDX = 1 # macro +regSQ_TEX_CLK_CTRL = 0x508f # macro +regSQ_TEX_CLK_CTRL_BASE_IDX = 1 # macro +regSQ_LDS_CLK_CTRL = 0x5090 # macro +regSQ_LDS_CLK_CTRL_BASE_IDX = 1 # macro +regSQ_POWER_THROTTLE = 0x5091 # macro +regSQ_POWER_THROTTLE_BASE_IDX = 1 # macro +regSQ_POWER_THROTTLE2 = 0x5092 # macro +regSQ_POWER_THROTTLE2_BASE_IDX = 1 # macro +regTD_CGTT_CTRL = 0x509c # macro +regTD_CGTT_CTRL_BASE_IDX = 1 # macro +regTA_CGTT_CTRL = 0x509d # macro +regTA_CGTT_CTRL_BASE_IDX = 1 # macro +regCGTT_TCPI_CLK_CTRL = 0x509e # macro +regCGTT_TCPI_CLK_CTRL_BASE_IDX = 1 # macro +regTCX_CGTT_SCLK_CTRL = 0x50a3 # macro +regTCX_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro +regDB_CGTT_CLK_CTRL_0 = 0x50a4 # macro +regDB_CGTT_CLK_CTRL_0_BASE_IDX = 1 # macro +regCB_CGTT_SCLK_CTRL = 0x50a8 # macro +regCB_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro +regTCC_CGTT_SCLK_CTRL = 0x50ac # macro +regTCC_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro +regTCC_CGTT_SCLK_CTRL2 = 0x50ad # macro +regTCC_CGTT_SCLK_CTRL2_BASE_IDX = 1 # macro +regTCC_CGTT_SCLK_CTRL3 = 0x50ae # macro +regTCC_CGTT_SCLK_CTRL3_BASE_IDX = 1 # macro +regTCA_CGTT_SCLK_CTRL = 0x50af # macro +regTCA_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro +regCGTT_CP_CLK_CTRL = 0x50b0 # macro +regCGTT_CP_CLK_CTRL_BASE_IDX = 1 # macro +regCGTT_CPC_CLK_CTRL = 0x50b2 # macro +regCGTT_CPC_CLK_CTRL_BASE_IDX = 1 # macro +regCGTT_RLC_CLK_CTRL = 0x50b5 # macro +regCGTT_RLC_CLK_CTRL_BASE_IDX = 1 # macro +regRLC_GFX_RM_CNTL = 0x50b6 # macro +regRLC_GFX_RM_CNTL_BASE_IDX = 1 # macro +regRMI_CGTT_SCLK_CTRL = 0x50c0 # macro +regRMI_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro +regCGTT_TCPF_CLK_CTRL = 0x50c1 # macro +regCGTT_TCPF_CLK_CTRL_BASE_IDX = 1 # macro +regCP_HYP_PFP_UCODE_ADDR = 0x5814 # macro +regCP_HYP_PFP_UCODE_ADDR_BASE_IDX = 1 # macro +regCP_PFP_UCODE_ADDR = 0x5814 # macro +regCP_PFP_UCODE_ADDR_BASE_IDX = 1 # macro +regCP_HYP_PFP_UCODE_DATA = 0x5815 # macro +regCP_HYP_PFP_UCODE_DATA_BASE_IDX = 1 # macro +regCP_PFP_UCODE_DATA = 0x5815 # macro +regCP_PFP_UCODE_DATA_BASE_IDX = 1 # macro +regCP_HYP_ME_UCODE_ADDR = 0x5816 # macro +regCP_HYP_ME_UCODE_ADDR_BASE_IDX = 1 # macro +regCP_ME_RAM_RADDR = 0x5816 # macro +regCP_ME_RAM_RADDR_BASE_IDX = 1 # macro +regCP_ME_RAM_WADDR = 0x5816 # macro +regCP_ME_RAM_WADDR_BASE_IDX = 1 # macro +regCP_HYP_ME_UCODE_DATA = 0x5817 # macro +regCP_HYP_ME_UCODE_DATA_BASE_IDX = 1 # macro +regCP_ME_RAM_DATA = 0x5817 # macro +regCP_ME_RAM_DATA_BASE_IDX = 1 # macro +regCP_CE_UCODE_ADDR = 0x5818 # macro +regCP_CE_UCODE_ADDR_BASE_IDX = 1 # macro +regCP_HYP_CE_UCODE_ADDR = 0x5818 # macro +regCP_HYP_CE_UCODE_ADDR_BASE_IDX = 1 # macro +regCP_CE_UCODE_DATA = 0x5819 # macro +regCP_CE_UCODE_DATA_BASE_IDX = 1 # macro +regCP_HYP_CE_UCODE_DATA = 0x5819 # macro +regCP_HYP_CE_UCODE_DATA_BASE_IDX = 1 # macro +regCP_HYP_MEC1_UCODE_ADDR = 0x581a # macro +regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX = 1 # macro +regCP_MEC_ME1_UCODE_ADDR = 0x581a # macro +regCP_MEC_ME1_UCODE_ADDR_BASE_IDX = 1 # macro +regCP_HYP_MEC1_UCODE_DATA = 0x581b # macro +regCP_HYP_MEC1_UCODE_DATA_BASE_IDX = 1 # macro +regCP_MEC_ME1_UCODE_DATA = 0x581b # macro +regCP_MEC_ME1_UCODE_DATA_BASE_IDX = 1 # macro +regCP_HYP_MEC2_UCODE_ADDR = 0x581c # macro +regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX = 1 # macro +regCP_MEC_ME2_UCODE_ADDR = 0x581c # macro +regCP_MEC_ME2_UCODE_ADDR_BASE_IDX = 1 # macro +regCP_HYP_MEC2_UCODE_DATA = 0x581d # macro +regCP_HYP_MEC2_UCODE_DATA_BASE_IDX = 1 # macro +regCP_MEC_ME2_UCODE_DATA = 0x581d # macro +regCP_MEC_ME2_UCODE_DATA_BASE_IDX = 1 # macro +regCP_HYP_PFP_UCODE_CHKSUM = 0x581e # macro +regCP_HYP_PFP_UCODE_CHKSUM_BASE_IDX = 1 # macro +regCP_HYP_CE_UCODE_CHKSUM = 0x581f # macro +regCP_HYP_CE_UCODE_CHKSUM_BASE_IDX = 1 # macro +regCP_HYP_ME_UCODE_CHKSUM = 0x5820 # macro +regCP_HYP_ME_UCODE_CHKSUM_BASE_IDX = 1 # macro +regCP_HYP_MEC_ME1_UCODE_CHKSUM = 0x5821 # macro +regCP_HYP_MEC_ME1_UCODE_CHKSUM_BASE_IDX = 1 # macro +regCP_HYP_MEC_ME2_UCODE_CHKSUM = 0x5822 # macro +regCP_HYP_MEC_ME2_UCODE_CHKSUM_BASE_IDX = 1 # macro +regCP_HYP_XCP_CTL = 0x5828 # macro +regCP_HYP_XCP_CTL_BASE_IDX = 1 # macro +regRLC_GPM_UCODE_ADDR = 0x583c # macro +regRLC_GPM_UCODE_ADDR_BASE_IDX = 1 # macro +regRLC_GPM_UCODE_DATA = 0x583d # macro +regRLC_GPM_UCODE_DATA_BASE_IDX = 1 # macro +regGRBM_GFX_INDEX_SR_SELECT = 0x5a00 # macro +regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX = 1 # macro +regGRBM_GFX_INDEX_SR_DATA = 0x5a01 # macro +regGRBM_GFX_INDEX_SR_DATA_BASE_IDX = 1 # macro +regGRBM_GFX_CNTL_SR_SELECT = 0x5a02 # macro +regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX = 1 # macro +regGRBM_GFX_CNTL_SR_DATA = 0x5a03 # macro +regGRBM_GFX_CNTL_SR_DATA_BASE_IDX = 1 # macro +regGRBM_MCM_ADDR = 0x5a07 # macro +regGRBM_MCM_ADDR_BASE_IDX = 1 # macro +regRLC_GPU_IOV_VF_ENABLE = 0x5b00 # macro +regRLC_GPU_IOV_VF_ENABLE_BASE_IDX = 1 # macro +regRLC_GPU_IOV_CFG_REG6 = 0x5b06 # macro +regRLC_GPU_IOV_CFG_REG6_BASE_IDX = 1 # macro +regRLC_GPU_IOV_CFG_REG8 = 0x5b20 # macro +regRLC_GPU_IOV_CFG_REG8_BASE_IDX = 1 # macro +regRLC_RLCV_TIMER_INT_0 = 0x5b25 # macro +regRLC_RLCV_TIMER_INT_0_BASE_IDX = 1 # macro +regRLC_RLCV_TIMER_CTRL = 0x5b26 # macro +regRLC_RLCV_TIMER_CTRL_BASE_IDX = 1 # macro +regRLC_RLCV_TIMER_STAT = 0x5b27 # macro +regRLC_RLCV_TIMER_STAT_BASE_IDX = 1 # macro +regRLC_GPU_IOV_VF_DOORBELL_STATUS = 0x5b2a # macro +regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET = 0x5b2b # macro +regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX = 1 # macro +regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR = 0x5b2c # macro +regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX = 1 # macro +regRLC_GPU_IOV_VF_MASK = 0x5b2d # macro +regRLC_GPU_IOV_VF_MASK_BASE_IDX = 1 # macro +regRLC_HYP_SEMAPHORE_0 = 0x5b2e # macro +regRLC_HYP_SEMAPHORE_0_BASE_IDX = 1 # macro +regRLC_HYP_SEMAPHORE_1 = 0x5b2f # macro +regRLC_HYP_SEMAPHORE_1_BASE_IDX = 1 # macro +regRLC_CLK_CNTL = 0x5b31 # macro +regRLC_CLK_CNTL_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SCH_BLOCK = 0x5b34 # macro +regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX = 1 # macro +regRLC_GPU_IOV_CFG_REG1 = 0x5b35 # macro +regRLC_GPU_IOV_CFG_REG1_BASE_IDX = 1 # macro +regRLC_GPU_IOV_CFG_REG2 = 0x5b36 # macro +regRLC_GPU_IOV_CFG_REG2_BASE_IDX = 1 # macro +regRLC_GPU_IOV_VM_BUSY_STATUS = 0x5b37 # macro +regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SCH_0 = 0x5b38 # macro +regRLC_GPU_IOV_SCH_0_BASE_IDX = 1 # macro +regRLC_GPU_IOV_ACTIVE_FCN_ID = 0x5b39 # macro +regRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SCH_3 = 0x5b3a # macro +regRLC_GPU_IOV_SCH_3_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SCH_1 = 0x5b3b # macro +regRLC_GPU_IOV_SCH_1_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SCH_2 = 0x5b3c # macro +regRLC_GPU_IOV_SCH_2_BASE_IDX = 1 # macro +regRLC_GPU_IOV_INT_STAT = 0x5b3f # macro +regRLC_GPU_IOV_INT_STAT_BASE_IDX = 1 # macro +regRLC_RLCV_TIMER_INT_1 = 0x5b40 # macro +regRLC_RLCV_TIMER_INT_1_BASE_IDX = 1 # macro +regRLC_GPU_IOV_UCODE_ADDR = 0x5b42 # macro +regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX = 1 # macro +regRLC_GPU_IOV_UCODE_DATA = 0x5b43 # macro +regRLC_GPU_IOV_UCODE_DATA_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SCRATCH_ADDR = 0x5b44 # macro +regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SCRATCH_DATA = 0x5b45 # macro +regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX = 1 # macro +regRLC_GPU_IOV_F32_CNTL = 0x5b46 # macro +regRLC_GPU_IOV_F32_CNTL_BASE_IDX = 1 # macro +regRLC_GPU_IOV_F32_RESET = 0x5b47 # macro +regRLC_GPU_IOV_F32_RESET_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA0_STATUS = 0x5b48 # macro +regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA1_STATUS = 0x5b49 # macro +regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SMU_RESPONSE = 0x5b4a # macro +regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX = 1 # macro +regRLC_GPU_IOV_VIRT_RESET_REQ = 0x5b4c # macro +regRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX = 1 # macro +regRLC_GPU_IOV_RLC_RESPONSE = 0x5b4d # macro +regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX = 1 # macro +regRLC_GPU_IOV_INT_DISABLE = 0x5b4e # macro +regRLC_GPU_IOV_INT_DISABLE_BASE_IDX = 1 # macro +regRLC_GPU_IOV_INT_FORCE = 0x5b4f # macro +regRLC_GPU_IOV_INT_FORCE_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA0_BUSY_STATUS = 0x5b50 # macro +regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA1_BUSY_STATUS = 0x5b51 # macro +regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX = 1 # macro +regRLC_HYP_SEMAPHORE_2 = 0x5b52 # macro +regRLC_HYP_SEMAPHORE_2_BASE_IDX = 1 # macro +regRLC_HYP_SEMAPHORE_3 = 0x5b53 # macro +regRLC_HYP_SEMAPHORE_3_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA2_STATUS = 0x5b54 # macro +regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA3_STATUS = 0x5b55 # macro +regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA4_STATUS = 0x5b56 # macro +regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA5_STATUS = 0x5b57 # macro +regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA6_STATUS = 0x5b58 # macro +regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA7_STATUS = 0x5b59 # macro +regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA2_BUSY_STATUS = 0x5b5a # macro +regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA3_BUSY_STATUS = 0x5b5b # macro +regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA4_BUSY_STATUS = 0x5b5c # macro +regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA5_BUSY_STATUS = 0x5b5d # macro +regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA6_BUSY_STATUS = 0x5b5e # macro +regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX = 1 # macro +regRLC_GPU_IOV_SDMA7_BUSY_STATUS = 0x5b5f # macro +regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX = 1 # macro +regMC_VM_FB_SIZE_OFFSET_VF0 = 0x5a80 # macro +regMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX = 1 # macro +regMC_VM_FB_SIZE_OFFSET_VF1 = 0x5a81 # macro +regMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX = 1 # macro +regMC_VM_FB_SIZE_OFFSET_VF2 = 0x5a82 # macro +regMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX = 1 # macro +regMC_VM_FB_SIZE_OFFSET_VF3 = 0x5a83 # macro +regMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX = 1 # macro +regMC_VM_FB_SIZE_OFFSET_VF4 = 0x5a84 # macro +regMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX = 1 # macro +regMC_VM_FB_SIZE_OFFSET_VF5 = 0x5a85 # macro +regMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX = 1 # macro +regMC_VM_FB_SIZE_OFFSET_VF6 = 0x5a86 # macro +regMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX = 1 # macro +regMC_VM_FB_SIZE_OFFSET_VF7 = 0x5a87 # macro +regMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX = 1 # macro +regMC_VM_FB_SIZE_OFFSET_VF8 = 0x5a88 # macro +regMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX = 1 # macro +regMC_VM_FB_SIZE_OFFSET_VF9 = 0x5a89 # macro +regMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX = 1 # macro +regMC_VM_FB_SIZE_OFFSET_VF10 = 0x5a8a # macro +regMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX = 1 # macro +regMC_VM_FB_SIZE_OFFSET_VF11 = 0x5a8b # macro +regMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX = 1 # macro +regMC_VM_FB_SIZE_OFFSET_VF12 = 0x5a8c # macro +regMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX = 1 # macro +regMC_VM_FB_SIZE_OFFSET_VF13 = 0x5a8d # macro +regMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX = 1 # macro +regMC_VM_FB_SIZE_OFFSET_VF14 = 0x5a8e # macro +regMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX = 1 # macro +regMC_VM_FB_SIZE_OFFSET_VF15 = 0x5a8f # macro +regMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX = 1 # macro +regVM_IOMMU_MMIO_CNTRL_1 = 0x5a90 # macro +regVM_IOMMU_MMIO_CNTRL_1_BASE_IDX = 1 # macro +regMC_VM_MARC_BASE_LO_0 = 0x5a91 # macro +regMC_VM_MARC_BASE_LO_0_BASE_IDX = 1 # macro +regMC_VM_MARC_BASE_LO_1 = 0x5a92 # macro +regMC_VM_MARC_BASE_LO_1_BASE_IDX = 1 # macro +regMC_VM_MARC_BASE_LO_2 = 0x5a93 # macro +regMC_VM_MARC_BASE_LO_2_BASE_IDX = 1 # macro +regMC_VM_MARC_BASE_LO_3 = 0x5a94 # macro +regMC_VM_MARC_BASE_LO_3_BASE_IDX = 1 # macro +regMC_VM_MARC_BASE_HI_0 = 0x5a95 # macro +regMC_VM_MARC_BASE_HI_0_BASE_IDX = 1 # macro +regMC_VM_MARC_BASE_HI_1 = 0x5a96 # macro +regMC_VM_MARC_BASE_HI_1_BASE_IDX = 1 # macro +regMC_VM_MARC_BASE_HI_2 = 0x5a97 # macro +regMC_VM_MARC_BASE_HI_2_BASE_IDX = 1 # macro +regMC_VM_MARC_BASE_HI_3 = 0x5a98 # macro +regMC_VM_MARC_BASE_HI_3_BASE_IDX = 1 # macro +regMC_VM_MARC_RELOC_LO_0 = 0x5a99 # macro +regMC_VM_MARC_RELOC_LO_0_BASE_IDX = 1 # macro +regMC_VM_MARC_RELOC_LO_1 = 0x5a9a # macro +regMC_VM_MARC_RELOC_LO_1_BASE_IDX = 1 # macro +regMC_VM_MARC_RELOC_LO_2 = 0x5a9b # macro +regMC_VM_MARC_RELOC_LO_2_BASE_IDX = 1 # macro +regMC_VM_MARC_RELOC_LO_3 = 0x5a9c # macro +regMC_VM_MARC_RELOC_LO_3_BASE_IDX = 1 # macro +regMC_VM_MARC_RELOC_HI_0 = 0x5a9d # macro +regMC_VM_MARC_RELOC_HI_0_BASE_IDX = 1 # macro +regMC_VM_MARC_RELOC_HI_1 = 0x5a9e # macro +regMC_VM_MARC_RELOC_HI_1_BASE_IDX = 1 # macro +regMC_VM_MARC_RELOC_HI_2 = 0x5a9f # macro +regMC_VM_MARC_RELOC_HI_2_BASE_IDX = 1 # macro +regMC_VM_MARC_RELOC_HI_3 = 0x5aa0 # macro +regMC_VM_MARC_RELOC_HI_3_BASE_IDX = 1 # macro +regMC_VM_MARC_LEN_LO_0 = 0x5aa1 # macro +regMC_VM_MARC_LEN_LO_0_BASE_IDX = 1 # macro +regMC_VM_MARC_LEN_LO_1 = 0x5aa2 # macro +regMC_VM_MARC_LEN_LO_1_BASE_IDX = 1 # macro +regMC_VM_MARC_LEN_LO_2 = 0x5aa3 # macro +regMC_VM_MARC_LEN_LO_2_BASE_IDX = 1 # macro +regMC_VM_MARC_LEN_LO_3 = 0x5aa4 # macro +regMC_VM_MARC_LEN_LO_3_BASE_IDX = 1 # macro +regMC_VM_MARC_LEN_HI_0 = 0x5aa5 # macro +regMC_VM_MARC_LEN_HI_0_BASE_IDX = 1 # macro +regMC_VM_MARC_LEN_HI_1 = 0x5aa6 # macro +regMC_VM_MARC_LEN_HI_1_BASE_IDX = 1 # macro +regMC_VM_MARC_LEN_HI_2 = 0x5aa7 # macro +regMC_VM_MARC_LEN_HI_2_BASE_IDX = 1 # macro +regMC_VM_MARC_LEN_HI_3 = 0x5aa8 # macro +regMC_VM_MARC_LEN_HI_3_BASE_IDX = 1 # macro +regVM_IOMMU_CONTROL_REGISTER = 0x5aa9 # macro +regVM_IOMMU_CONTROL_REGISTER_BASE_IDX = 1 # macro +regVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER = 0x5aaa # macro +regVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX = 1 # macro +regVM_PCIE_ATS_CNTL = 0x5aab # macro +regVM_PCIE_ATS_CNTL_BASE_IDX = 1 # macro +regVM_PCIE_ATS_CNTL_VF_0 = 0x5aac # macro +regVM_PCIE_ATS_CNTL_VF_0_BASE_IDX = 1 # macro +regVM_PCIE_ATS_CNTL_VF_1 = 0x5aad # macro +regVM_PCIE_ATS_CNTL_VF_1_BASE_IDX = 1 # macro +regVM_PCIE_ATS_CNTL_VF_2 = 0x5aae # macro +regVM_PCIE_ATS_CNTL_VF_2_BASE_IDX = 1 # macro +regVM_PCIE_ATS_CNTL_VF_3 = 0x5aaf # macro +regVM_PCIE_ATS_CNTL_VF_3_BASE_IDX = 1 # macro +regVM_PCIE_ATS_CNTL_VF_4 = 0x5ab0 # macro +regVM_PCIE_ATS_CNTL_VF_4_BASE_IDX = 1 # macro +regVM_PCIE_ATS_CNTL_VF_5 = 0x5ab1 # macro +regVM_PCIE_ATS_CNTL_VF_5_BASE_IDX = 1 # macro +regVM_PCIE_ATS_CNTL_VF_6 = 0x5ab2 # macro +regVM_PCIE_ATS_CNTL_VF_6_BASE_IDX = 1 # macro +regVM_PCIE_ATS_CNTL_VF_7 = 0x5ab3 # macro +regVM_PCIE_ATS_CNTL_VF_7_BASE_IDX = 1 # macro +regVM_PCIE_ATS_CNTL_VF_8 = 0x5ab4 # macro +regVM_PCIE_ATS_CNTL_VF_8_BASE_IDX = 1 # macro +regVM_PCIE_ATS_CNTL_VF_9 = 0x5ab5 # macro +regVM_PCIE_ATS_CNTL_VF_9_BASE_IDX = 1 # macro +regVM_PCIE_ATS_CNTL_VF_10 = 0x5ab6 # macro +regVM_PCIE_ATS_CNTL_VF_10_BASE_IDX = 1 # macro +regVM_PCIE_ATS_CNTL_VF_11 = 0x5ab7 # macro +regVM_PCIE_ATS_CNTL_VF_11_BASE_IDX = 1 # macro +regVM_PCIE_ATS_CNTL_VF_12 = 0x5ab8 # macro +regVM_PCIE_ATS_CNTL_VF_12_BASE_IDX = 1 # macro +regVM_PCIE_ATS_CNTL_VF_13 = 0x5ab9 # macro +regVM_PCIE_ATS_CNTL_VF_13_BASE_IDX = 1 # macro +regVM_PCIE_ATS_CNTL_VF_14 = 0x5aba # macro +regVM_PCIE_ATS_CNTL_VF_14_BASE_IDX = 1 # macro +regVM_PCIE_ATS_CNTL_VF_15 = 0x5abb # macro +regVM_PCIE_ATS_CNTL_VF_15_BASE_IDX = 1 # macro +regMC_SHARED_ACTIVE_FCN_ID = 0x5abc # macro +regMC_SHARED_ACTIVE_FCN_ID_BASE_IDX = 1 # macro +regMC_VM_XGMI_GPUIOV_ENABLE = 0x5abd # macro +regMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX = 1 # macro +regCPG_PSP_DEBUG = 0x5c30 # macro +regCPG_PSP_DEBUG_BASE_IDX = 1 # macro +regCPC_PSP_DEBUG = 0x5c31 # macro +regCPC_PSP_DEBUG_BASE_IDX = 1 # macro +regCP_PSP_XCP_CTL = 0x5c34 # macro +regCP_PSP_XCP_CTL_BASE_IDX = 1 # macro +regGRBM_SEC_CNTL = 0x5e0b # macro +regGRBM_SEC_CNTL_BASE_IDX = 1 # macro +regGRBM_IOV_ERROR_FIFO_DATA = 0x5e12 # macro +regGRBM_IOV_ERROR_FIFO_DATA_BASE_IDX = 1 # macro +regGRBM_DSM_BYPASS = 0x5e13 # macro +regGRBM_DSM_BYPASS_BASE_IDX = 1 # macro +regGRBM_CAM_INDEX = 0x5e16 # macro +regGRBM_CAM_INDEX_BASE_IDX = 1 # macro +regGRBM_HYP_CAM_INDEX = 0x5e16 # macro +regGRBM_HYP_CAM_INDEX_BASE_IDX = 1 # macro +regGRBM_CAM_DATA = 0x5e17 # macro +regGRBM_CAM_DATA_BASE_IDX = 1 # macro +regGRBM_HYP_CAM_DATA = 0x5e17 # macro +regGRBM_HYP_CAM_DATA_BASE_IDX = 1 # macro +regRLC_FWL_FIRST_VIOL_ADDR = 0x5f37 # macro +regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX = 1 # macro +ixSQ_DEBUG_STS_LOCAL = 0x0008 # macro +ixSQ_DEBUG_CTRL_LOCAL = 0x0009 # macro +ixSQ_WAVE_VALID_AND_IDLE = 0x000a # macro +ixSQ_WAVE_MODE = 0x0011 # macro +ixSQ_WAVE_STATUS = 0x0012 # macro +ixSQ_WAVE_TRAPSTS = 0x0013 # macro +ixSQ_WAVE_HW_ID = 0x0014 # macro +ixSQ_WAVE_GPR_ALLOC = 0x0015 # macro +ixSQ_WAVE_LDS_ALLOC = 0x0016 # macro +ixSQ_WAVE_IB_STS = 0x0017 # macro +ixSQ_WAVE_PC_LO = 0x0018 # macro +ixSQ_WAVE_PC_HI = 0x0019 # macro +ixSQ_WAVE_INST_DW0 = 0x001a # macro +ixSQ_WAVE_INST_DW1 = 0x001b # macro +ixSQ_WAVE_IB_DBG0 = 0x001c # macro +ixSQ_WAVE_IB_DBG1 = 0x001d # macro +ixSQ_WAVE_FLUSH_IB = 0x001e # macro +ixSQ_WAVE_TTMP0 = 0x026c # macro +ixSQ_WAVE_TTMP1 = 0x026d # macro +ixSQ_WAVE_TTMP2 = 0x026e # macro +ixSQ_WAVE_TTMP3 = 0x026f # macro +ixSQ_WAVE_TTMP4 = 0x0270 # macro +ixSQ_WAVE_TTMP5 = 0x0271 # macro +ixSQ_WAVE_TTMP6 = 0x0272 # macro +ixSQ_WAVE_TTMP7 = 0x0273 # macro +ixSQ_WAVE_TTMP8 = 0x0274 # macro +ixSQ_WAVE_TTMP9 = 0x0275 # macro +ixSQ_WAVE_TTMP10 = 0x0276 # macro +ixSQ_WAVE_TTMP11 = 0x0277 # macro +ixSQ_WAVE_TTMP12 = 0x0278 # macro +ixSQ_WAVE_TTMP13 = 0x0279 # macro +ixSQ_WAVE_TTMP14 = 0x027a # macro +ixSQ_WAVE_TTMP15 = 0x027b # macro +ixSQ_WAVE_M0 = 0x027c # macro +ixSQ_WAVE_EXEC_LO = 0x027e # macro +ixSQ_WAVE_EXEC_HI = 0x027f # macro +ixSQ_INTERRUPT_WORD_AUTO_CTXID = 0x20c0 # macro +ixSQ_INTERRUPT_WORD_AUTO_HI = 0x20c0 # macro +ixSQ_INTERRUPT_WORD_AUTO_LO = 0x20c0 # macro +ixSQ_INTERRUPT_WORD_CMN_CTXID = 0x20c0 # macro +ixSQ_INTERRUPT_WORD_CMN_HI = 0x20c0 # macro +ixSQ_INTERRUPT_WORD_WAVE_CTXID = 0x20c0 # macro +ixSQ_INTERRUPT_WORD_WAVE_HI = 0x20c0 # macro +ixSQ_INTERRUPT_WORD_WAVE_LO = 0x20c0 # macro +_gc_9_4_3_SH_MASK_HEADER = True # macro +GRBM_CNTL__READ_TIMEOUT__SHIFT = 0x0 # macro +GRBM_CNTL__REPORT_LAST_RDERR__SHIFT = 0x1f # macro +GRBM_CNTL__READ_TIMEOUT_MASK = 0x000000FF # macro +GRBM_CNTL__REPORT_LAST_RDERR_MASK = 0x80000000 # macro +GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT = 0x0 # macro +GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT = 0x6 # macro +GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK = 0x0000003F # macro +GRBM_SKEW_CNTL__SKEW_COUNT_MASK = 0x00000FC0 # macro +GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT = 0x0 # macro +GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT = 0x4 # macro +GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT = 0x5 # macro +GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT = 0x6 # macro +GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT = 0x7 # macro +GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT = 0x8 # macro +GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT = 0x9 # macro +GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT = 0xa # macro +GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT = 0xb # macro +GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT = 0xc # macro +GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT = 0xd # macro +GRBM_STATUS2__RLC_RQ_PENDING__SHIFT = 0xe # macro +GRBM_STATUS2__UTCL2_BUSY__SHIFT = 0xf # macro +GRBM_STATUS2__EA_BUSY__SHIFT = 0x10 # macro +GRBM_STATUS2__RMI_BUSY__SHIFT = 0x11 # macro +GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT = 0x12 # macro +GRBM_STATUS2__CPF_RQ_PENDING__SHIFT = 0x13 # macro +GRBM_STATUS2__EA_LINK_BUSY__SHIFT = 0x14 # macro +GRBM_STATUS2__CANE_BUSY__SHIFT = 0x15 # macro +GRBM_STATUS2__CANE_LINK_BUSY__SHIFT = 0x16 # macro +GRBM_STATUS2__RLC_BUSY__SHIFT = 0x18 # macro +GRBM_STATUS2__TC_BUSY__SHIFT = 0x19 # macro +GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT = 0x1a # macro +GRBM_STATUS2__CPF_BUSY__SHIFT = 0x1c # macro +GRBM_STATUS2__CPC_BUSY__SHIFT = 0x1d # macro +GRBM_STATUS2__CPG_BUSY__SHIFT = 0x1e # macro +GRBM_STATUS2__CPAXI_BUSY__SHIFT = 0x1f # macro +GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK = 0x0000000F # macro +GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK = 0x00000010 # macro +GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK = 0x00000020 # macro +GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK = 0x00000040 # macro +GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK = 0x00000080 # macro +GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK = 0x00000100 # macro +GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK = 0x00000200 # macro +GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK = 0x00000400 # macro +GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK = 0x00000800 # macro +GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK = 0x00001000 # macro +GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK = 0x00002000 # macro +GRBM_STATUS2__RLC_RQ_PENDING_MASK = 0x00004000 # macro +GRBM_STATUS2__UTCL2_BUSY_MASK = 0x00008000 # macro +GRBM_STATUS2__EA_BUSY_MASK = 0x00010000 # macro +GRBM_STATUS2__RMI_BUSY_MASK = 0x00020000 # macro +GRBM_STATUS2__UTCL2_RQ_PENDING_MASK = 0x00040000 # macro +GRBM_STATUS2__CPF_RQ_PENDING_MASK = 0x00080000 # macro +GRBM_STATUS2__EA_LINK_BUSY_MASK = 0x00100000 # macro +GRBM_STATUS2__CANE_BUSY_MASK = 0x00200000 # macro +GRBM_STATUS2__CANE_LINK_BUSY_MASK = 0x00400000 # macro +GRBM_STATUS2__RLC_BUSY_MASK = 0x01000000 # macro +GRBM_STATUS2__TC_BUSY_MASK = 0x02000000 # macro +GRBM_STATUS2__TCC_CC_RESIDENT_MASK = 0x04000000 # macro +GRBM_STATUS2__CPF_BUSY_MASK = 0x10000000 # macro +GRBM_STATUS2__CPC_BUSY_MASK = 0x20000000 # macro +GRBM_STATUS2__CPG_BUSY_MASK = 0x40000000 # macro +GRBM_STATUS2__CPAXI_BUSY_MASK = 0x80000000 # macro +GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT = 0x0 # macro +GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT = 0x2 # macro +GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT = 0x4 # macro +GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT = 0x6 # macro +GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT = 0xe # macro +GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT = 0xf # macro +GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK = 0x00000003 # macro +GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK = 0x0000000C # macro +GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK = 0x00000030 # macro +GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK = 0x000000C0 # macro +GRBM_PWR_CNTL__GFX_REQ_EN_MASK = 0x00004000 # macro +GRBM_PWR_CNTL__ALL_REQ_EN_MASK = 0x00008000 # macro +GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT = 0x0 # macro +GRBM_STATUS__RSMU_RQ_PENDING__SHIFT = 0x5 # macro +GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT = 0x7 # macro +GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT = 0x8 # macro +GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT = 0x9 # macro +GRBM_STATUS__DB_CLEAN__SHIFT = 0xc # macro +GRBM_STATUS__CB_CLEAN__SHIFT = 0xd # macro +GRBM_STATUS__TA_BUSY__SHIFT = 0xe # macro +GRBM_STATUS__GDS_BUSY__SHIFT = 0xf # macro +GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT = 0x10 # macro +GRBM_STATUS__VGT_BUSY__SHIFT = 0x11 # macro +GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT = 0x12 # macro +GRBM_STATUS__IA_BUSY__SHIFT = 0x13 # macro +GRBM_STATUS__SX_BUSY__SHIFT = 0x14 # macro +GRBM_STATUS__WD_BUSY__SHIFT = 0x15 # macro +GRBM_STATUS__SPI_BUSY__SHIFT = 0x16 # macro +GRBM_STATUS__BCI_BUSY__SHIFT = 0x17 # macro +GRBM_STATUS__SC_BUSY__SHIFT = 0x18 # macro +GRBM_STATUS__PA_BUSY__SHIFT = 0x19 # macro +GRBM_STATUS__DB_BUSY__SHIFT = 0x1a # macro +GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT = 0x1c # macro +GRBM_STATUS__CP_BUSY__SHIFT = 0x1d # macro +GRBM_STATUS__CB_BUSY__SHIFT = 0x1e # macro +GRBM_STATUS__GUI_ACTIVE__SHIFT = 0x1f # macro +GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK = 0x0000000F # macro +GRBM_STATUS__RSMU_RQ_PENDING_MASK = 0x00000020 # macro +GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK = 0x00000080 # macro +GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK = 0x00000100 # macro +GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK = 0x00000200 # macro +GRBM_STATUS__DB_CLEAN_MASK = 0x00001000 # macro +GRBM_STATUS__CB_CLEAN_MASK = 0x00002000 # macro +GRBM_STATUS__TA_BUSY_MASK = 0x00004000 # macro +GRBM_STATUS__GDS_BUSY_MASK = 0x00008000 # macro +GRBM_STATUS__WD_BUSY_NO_DMA_MASK = 0x00010000 # macro +GRBM_STATUS__VGT_BUSY_MASK = 0x00020000 # macro +GRBM_STATUS__IA_BUSY_NO_DMA_MASK = 0x00040000 # macro +GRBM_STATUS__IA_BUSY_MASK = 0x00080000 # macro +GRBM_STATUS__SX_BUSY_MASK = 0x00100000 # macro +GRBM_STATUS__WD_BUSY_MASK = 0x00200000 # macro +GRBM_STATUS__SPI_BUSY_MASK = 0x00400000 # macro +GRBM_STATUS__BCI_BUSY_MASK = 0x00800000 # macro +GRBM_STATUS__SC_BUSY_MASK = 0x01000000 # macro +GRBM_STATUS__PA_BUSY_MASK = 0x02000000 # macro +GRBM_STATUS__DB_BUSY_MASK = 0x04000000 # macro +GRBM_STATUS__CP_COHERENCY_BUSY_MASK = 0x10000000 # macro +GRBM_STATUS__CP_BUSY_MASK = 0x20000000 # macro +GRBM_STATUS__CB_BUSY_MASK = 0x40000000 # macro +GRBM_STATUS__GUI_ACTIVE_MASK = 0x80000000 # macro +GRBM_STATUS_SE0__DB_CLEAN__SHIFT = 0x1 # macro +GRBM_STATUS_SE0__CB_CLEAN__SHIFT = 0x2 # macro +GRBM_STATUS_SE0__RMI_BUSY__SHIFT = 0x15 # macro +GRBM_STATUS_SE0__BCI_BUSY__SHIFT = 0x16 # macro +GRBM_STATUS_SE0__VGT_BUSY__SHIFT = 0x17 # macro +GRBM_STATUS_SE0__PA_BUSY__SHIFT = 0x18 # macro +GRBM_STATUS_SE0__TA_BUSY__SHIFT = 0x19 # macro +GRBM_STATUS_SE0__SX_BUSY__SHIFT = 0x1a # macro +GRBM_STATUS_SE0__SPI_BUSY__SHIFT = 0x1b # macro +GRBM_STATUS_SE0__SC_BUSY__SHIFT = 0x1d # macro +GRBM_STATUS_SE0__DB_BUSY__SHIFT = 0x1e # macro +GRBM_STATUS_SE0__CB_BUSY__SHIFT = 0x1f # macro +GRBM_STATUS_SE0__DB_CLEAN_MASK = 0x00000002 # macro +GRBM_STATUS_SE0__CB_CLEAN_MASK = 0x00000004 # macro +GRBM_STATUS_SE0__RMI_BUSY_MASK = 0x00200000 # macro +GRBM_STATUS_SE0__BCI_BUSY_MASK = 0x00400000 # macro +GRBM_STATUS_SE0__VGT_BUSY_MASK = 0x00800000 # macro +GRBM_STATUS_SE0__PA_BUSY_MASK = 0x01000000 # macro +GRBM_STATUS_SE0__TA_BUSY_MASK = 0x02000000 # macro +GRBM_STATUS_SE0__SX_BUSY_MASK = 0x04000000 # macro +GRBM_STATUS_SE0__SPI_BUSY_MASK = 0x08000000 # macro +GRBM_STATUS_SE0__SC_BUSY_MASK = 0x20000000 # macro +GRBM_STATUS_SE0__DB_BUSY_MASK = 0x40000000 # macro +GRBM_STATUS_SE0__CB_BUSY_MASK = 0x80000000 # macro +GRBM_STATUS_SE1__DB_CLEAN__SHIFT = 0x1 # macro +GRBM_STATUS_SE1__CB_CLEAN__SHIFT = 0x2 # macro +GRBM_STATUS_SE1__RMI_BUSY__SHIFT = 0x15 # macro +GRBM_STATUS_SE1__BCI_BUSY__SHIFT = 0x16 # macro +GRBM_STATUS_SE1__VGT_BUSY__SHIFT = 0x17 # macro +GRBM_STATUS_SE1__PA_BUSY__SHIFT = 0x18 # macro +GRBM_STATUS_SE1__TA_BUSY__SHIFT = 0x19 # macro +GRBM_STATUS_SE1__SX_BUSY__SHIFT = 0x1a # macro +GRBM_STATUS_SE1__SPI_BUSY__SHIFT = 0x1b # macro +GRBM_STATUS_SE1__SC_BUSY__SHIFT = 0x1d # macro +GRBM_STATUS_SE1__DB_BUSY__SHIFT = 0x1e # macro +GRBM_STATUS_SE1__CB_BUSY__SHIFT = 0x1f # macro +GRBM_STATUS_SE1__DB_CLEAN_MASK = 0x00000002 # macro +GRBM_STATUS_SE1__CB_CLEAN_MASK = 0x00000004 # macro +GRBM_STATUS_SE1__RMI_BUSY_MASK = 0x00200000 # macro +GRBM_STATUS_SE1__BCI_BUSY_MASK = 0x00400000 # macro +GRBM_STATUS_SE1__VGT_BUSY_MASK = 0x00800000 # macro +GRBM_STATUS_SE1__PA_BUSY_MASK = 0x01000000 # macro +GRBM_STATUS_SE1__TA_BUSY_MASK = 0x02000000 # macro +GRBM_STATUS_SE1__SX_BUSY_MASK = 0x04000000 # macro +GRBM_STATUS_SE1__SPI_BUSY_MASK = 0x08000000 # macro +GRBM_STATUS_SE1__SC_BUSY_MASK = 0x20000000 # macro +GRBM_STATUS_SE1__DB_BUSY_MASK = 0x40000000 # macro +GRBM_STATUS_SE1__CB_BUSY_MASK = 0x80000000 # macro +GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT = 0x0 # macro +GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT = 0x2 # macro +GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT = 0x10 # macro +GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT = 0x11 # macro +GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT = 0x12 # macro +GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT = 0x13 # macro +GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT = 0x14 # macro +GRBM_SOFT_RESET__SOFT_RESET_CANE__SHIFT = 0x15 # macro +GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT = 0x16 # macro +GRBM_SOFT_RESET__SOFT_RESET_UTCL2__SHIFT = 0x17 # macro +GRBM_SOFT_RESET__SOFT_RESET_CP_MASK = 0x00000001 # macro +GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK = 0x00000004 # macro +GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK = 0x00010000 # macro +GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK = 0x00020000 # macro +GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK = 0x00040000 # macro +GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK = 0x00080000 # macro +GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK = 0x00100000 # macro +GRBM_SOFT_RESET__SOFT_RESET_CANE_MASK = 0x00200000 # macro +GRBM_SOFT_RESET__SOFT_RESET_EA_MASK = 0x00400000 # macro +GRBM_SOFT_RESET__SOFT_RESET_UTCL2_MASK = 0x00800000 # macro +GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT = 0x0 # macro +GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT = 0x8 # macro +GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK = 0x0000000F # macro +GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK = 0x00001F00 # macro +GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT = 0x0 # macro +GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK = 0x000000FF # macro +GRBM_STATUS_SE2__DB_CLEAN__SHIFT = 0x1 # macro +GRBM_STATUS_SE2__CB_CLEAN__SHIFT = 0x2 # macro +GRBM_STATUS_SE2__RMI_BUSY__SHIFT = 0x15 # macro +GRBM_STATUS_SE2__BCI_BUSY__SHIFT = 0x16 # macro +GRBM_STATUS_SE2__VGT_BUSY__SHIFT = 0x17 # macro +GRBM_STATUS_SE2__PA_BUSY__SHIFT = 0x18 # macro +GRBM_STATUS_SE2__TA_BUSY__SHIFT = 0x19 # macro +GRBM_STATUS_SE2__SX_BUSY__SHIFT = 0x1a # macro +GRBM_STATUS_SE2__SPI_BUSY__SHIFT = 0x1b # macro +GRBM_STATUS_SE2__SC_BUSY__SHIFT = 0x1d # macro +GRBM_STATUS_SE2__DB_BUSY__SHIFT = 0x1e # macro +GRBM_STATUS_SE2__CB_BUSY__SHIFT = 0x1f # macro +GRBM_STATUS_SE2__DB_CLEAN_MASK = 0x00000002 # macro +GRBM_STATUS_SE2__CB_CLEAN_MASK = 0x00000004 # macro +GRBM_STATUS_SE2__RMI_BUSY_MASK = 0x00200000 # macro +GRBM_STATUS_SE2__BCI_BUSY_MASK = 0x00400000 # macro +GRBM_STATUS_SE2__VGT_BUSY_MASK = 0x00800000 # macro +GRBM_STATUS_SE2__PA_BUSY_MASK = 0x01000000 # macro +GRBM_STATUS_SE2__TA_BUSY_MASK = 0x02000000 # macro +GRBM_STATUS_SE2__SX_BUSY_MASK = 0x04000000 # macro +GRBM_STATUS_SE2__SPI_BUSY_MASK = 0x08000000 # macro +GRBM_STATUS_SE2__SC_BUSY_MASK = 0x20000000 # macro +GRBM_STATUS_SE2__DB_BUSY_MASK = 0x40000000 # macro +GRBM_STATUS_SE2__CB_BUSY_MASK = 0x80000000 # macro +GRBM_STATUS_SE3__DB_CLEAN__SHIFT = 0x1 # macro +GRBM_STATUS_SE3__CB_CLEAN__SHIFT = 0x2 # macro +GRBM_STATUS_SE3__RMI_BUSY__SHIFT = 0x15 # macro +GRBM_STATUS_SE3__BCI_BUSY__SHIFT = 0x16 # macro +GRBM_STATUS_SE3__VGT_BUSY__SHIFT = 0x17 # macro +GRBM_STATUS_SE3__PA_BUSY__SHIFT = 0x18 # macro +GRBM_STATUS_SE3__TA_BUSY__SHIFT = 0x19 # macro +GRBM_STATUS_SE3__SX_BUSY__SHIFT = 0x1a # macro +GRBM_STATUS_SE3__SPI_BUSY__SHIFT = 0x1b # macro +GRBM_STATUS_SE3__SC_BUSY__SHIFT = 0x1d # macro +GRBM_STATUS_SE3__DB_BUSY__SHIFT = 0x1e # macro +GRBM_STATUS_SE3__CB_BUSY__SHIFT = 0x1f # macro +GRBM_STATUS_SE3__DB_CLEAN_MASK = 0x00000002 # macro +GRBM_STATUS_SE3__CB_CLEAN_MASK = 0x00000004 # macro +GRBM_STATUS_SE3__RMI_BUSY_MASK = 0x00200000 # macro +GRBM_STATUS_SE3__BCI_BUSY_MASK = 0x00400000 # macro +GRBM_STATUS_SE3__VGT_BUSY_MASK = 0x00800000 # macro +GRBM_STATUS_SE3__PA_BUSY_MASK = 0x01000000 # macro +GRBM_STATUS_SE3__TA_BUSY_MASK = 0x02000000 # macro +GRBM_STATUS_SE3__SX_BUSY_MASK = 0x04000000 # macro +GRBM_STATUS_SE3__SPI_BUSY_MASK = 0x08000000 # macro +GRBM_STATUS_SE3__SC_BUSY_MASK = 0x20000000 # macro +GRBM_STATUS_SE3__DB_BUSY_MASK = 0x40000000 # macro +GRBM_STATUS_SE3__CB_BUSY_MASK = 0x80000000 # macro +GRBM_READ_ERROR__READ_ADDRESS__SHIFT = 0x2 # macro +GRBM_READ_ERROR__READ_PIPEID__SHIFT = 0x14 # macro +GRBM_READ_ERROR__READ_MEID__SHIFT = 0x16 # macro +GRBM_READ_ERROR__READ_ERROR__SHIFT = 0x1f # macro +GRBM_READ_ERROR__READ_ADDRESS_MASK = 0x0003FFFC # macro +GRBM_READ_ERROR__READ_PIPEID_MASK = 0x00300000 # macro +GRBM_READ_ERROR__READ_MEID_MASK = 0x00C00000 # macro +GRBM_READ_ERROR__READ_ERROR_MASK = 0x80000000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT = 0x10 # macro +GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT = 0x11 # macro +GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT = 0x12 # macro +GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT = 0x13 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT = 0x14 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT = 0x15 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT = 0x16 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT = 0x17 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT = 0x18 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT = 0x19 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT = 0x1a # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT = 0x1b # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT = 0x1c # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT = 0x1d # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT = 0x1e # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT = 0x1f # macro +GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK = 0x00010000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK = 0x00020000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK = 0x00040000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK = 0x00080000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK = 0x00100000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK = 0x00200000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK = 0x00400000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK = 0x00800000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK = 0x01000000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK = 0x02000000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK = 0x04000000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK = 0x08000000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK = 0x10000000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK = 0x20000000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK = 0x40000000 # macro +GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK = 0x80000000 # macro +GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT = 0x0 # macro +GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT = 0x13 # macro +GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK = 0x00000001 # macro +GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK = 0x00080000 # macro +GRBM_TRAP_OP__RW__SHIFT = 0x0 # macro +GRBM_TRAP_OP__RW_MASK = 0x00000001 # macro +GRBM_TRAP_ADDR__DATA__SHIFT = 0x0 # macro +GRBM_TRAP_ADDR__DATA_MASK = 0x0003FFFF # macro +GRBM_TRAP_ADDR_MSK__DATA__SHIFT = 0x0 # macro +GRBM_TRAP_ADDR_MSK__DATA_MASK = 0x0003FFFF # macro +GRBM_TRAP_WD__DATA__SHIFT = 0x0 # macro +GRBM_TRAP_WD__DATA_MASK = 0xFFFFFFFF # macro +GRBM_TRAP_WD_MSK__DATA__SHIFT = 0x0 # macro +GRBM_TRAP_WD_MSK__DATA_MASK = 0xFFFFFFFF # macro +GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT = 0x0 # macro +GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT = 0x1 # macro +GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT = 0x2 # macro +GRBM_WRITE_ERROR__WRITE_VFID__SHIFT = 0x5 # macro +GRBM_WRITE_ERROR__WRITE_VF__SHIFT = 0xc # macro +GRBM_WRITE_ERROR__WRITE_VMID__SHIFT = 0xd # macro +GRBM_WRITE_ERROR__TMZ__SHIFT = 0x11 # macro +GRBM_WRITE_ERROR__CP_SECURE_WR_ILLEGAL__SHIFT = 0x12 # macro +GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT = 0x14 # macro +GRBM_WRITE_ERROR__WRITE_MEID__SHIFT = 0x16 # macro +GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT = 0x1f # macro +GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK = 0x00000001 # macro +GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK = 0x00000002 # macro +GRBM_WRITE_ERROR__WRITE_SSRCID_MASK = 0x0000001C # macro +GRBM_WRITE_ERROR__WRITE_VFID_MASK = 0x000001E0 # macro +GRBM_WRITE_ERROR__WRITE_VF_MASK = 0x00001000 # macro +GRBM_WRITE_ERROR__WRITE_VMID_MASK = 0x0001E000 # macro +GRBM_WRITE_ERROR__TMZ_MASK = 0x00020000 # macro +GRBM_WRITE_ERROR__CP_SECURE_WR_ILLEGAL_MASK = 0x00040000 # macro +GRBM_WRITE_ERROR__WRITE_PIPEID_MASK = 0x00300000 # macro +GRBM_WRITE_ERROR__WRITE_MEID_MASK = 0x00C00000 # macro +GRBM_WRITE_ERROR__WRITE_ERROR_MASK = 0x80000000 # macro +GRBM_IOV_ERROR__IOV_ADDR__SHIFT = 0x2 # macro +GRBM_IOV_ERROR__IOV_VFID__SHIFT = 0x14 # macro +GRBM_IOV_ERROR__IOV_VF__SHIFT = 0x1a # macro +GRBM_IOV_ERROR__IOV_OP__SHIFT = 0x1b # macro +GRBM_IOV_ERROR__IOV_ERROR__SHIFT = 0x1f # macro +GRBM_IOV_ERROR__IOV_ADDR_MASK = 0x000FFFFC # macro +GRBM_IOV_ERROR__IOV_VFID_MASK = 0x03F00000 # macro +GRBM_IOV_ERROR__IOV_VF_MASK = 0x04000000 # macro +GRBM_IOV_ERROR__IOV_OP_MASK = 0x08000000 # macro +GRBM_IOV_ERROR__IOV_ERROR_MASK = 0x80000000 # macro +GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT = 0x0 # macro +GRBM_CHIP_REVISION__CHIP_REVISION_MASK = 0x000000FF # macro +GRBM_GFX_CNTL__PIPEID__SHIFT = 0x0 # macro +GRBM_GFX_CNTL__MEID__SHIFT = 0x2 # macro +GRBM_GFX_CNTL__VMID__SHIFT = 0x4 # macro +GRBM_GFX_CNTL__QUEUEID__SHIFT = 0x8 # macro +GRBM_GFX_CNTL__PIPEID_MASK = 0x00000003 # macro +GRBM_GFX_CNTL__MEID_MASK = 0x0000000C # macro +GRBM_GFX_CNTL__VMID_MASK = 0x000000F0 # macro +GRBM_GFX_CNTL__QUEUEID_MASK = 0x00000700 # macro +GRBM_RSMU_CFG__APERTURE_ID__SHIFT = 0x0 # macro +GRBM_RSMU_CFG__QOS__SHIFT = 0xc # macro +GRBM_RSMU_CFG__POSTED_WR__SHIFT = 0x10 # macro +GRBM_RSMU_CFG__DEBUG_MASK__SHIFT = 0x11 # macro +GRBM_RSMU_CFG__APERTURE_ID_MASK = 0x00000FFF # macro +GRBM_RSMU_CFG__QOS_MASK = 0x0000F000 # macro +GRBM_RSMU_CFG__POSTED_WR_MASK = 0x00010000 # macro +GRBM_RSMU_CFG__DEBUG_MASK_MASK = 0x00020000 # macro +GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT = 0x0 # macro +GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT = 0x10 # macro +GRBM_IH_CREDIT__CREDIT_VALUE_MASK = 0x00000003 # macro +GRBM_IH_CREDIT__IH_CLIENT_ID_MASK = 0x00FF0000 # macro +GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT = 0x10 # macro +GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT = 0x14 # macro +GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK = 0x00010000 # macro +GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK = 0x00100000 # macro +GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT = 0x0 # macro +GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK = 0x0003FFFF # macro +GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT = 0x0 # macro +GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK = 0x0003FFFF # macro +GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT = 0x2 # macro +GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT = 0x14 # macro +GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT = 0x15 # macro +GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT = 0x1b # macro +GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT = 0x1f # macro +GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK = 0x000FFFFC # macro +GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK = 0x00100000 # macro +GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK = 0x07E00000 # macro +GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK = 0x08000000 # macro +GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK = 0x80000000 # macro +GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT = 0x0 # macro +GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK = 0x00000001 # macro +GRBM_FENCE_RANGE0__START__SHIFT = 0x0 # macro +GRBM_FENCE_RANGE0__END__SHIFT = 0x10 # macro +GRBM_FENCE_RANGE0__START_MASK = 0x0000FFFF # macro +GRBM_FENCE_RANGE0__END_MASK = 0xFFFF0000 # macro +GRBM_FENCE_RANGE1__START__SHIFT = 0x0 # macro +GRBM_FENCE_RANGE1__END__SHIFT = 0x10 # macro +GRBM_FENCE_RANGE1__START_MASK = 0x0000FFFF # macro +GRBM_FENCE_RANGE1__END_MASK = 0xFFFF0000 # macro +GRBM_IOV_READ_ERROR__IOV_ADDR__SHIFT = 0x2 # macro +GRBM_IOV_READ_ERROR__IOV_VFID__SHIFT = 0x14 # macro +GRBM_IOV_READ_ERROR__IOV_VF__SHIFT = 0x1a # macro +GRBM_IOV_READ_ERROR__IOV_OP__SHIFT = 0x1b # macro +GRBM_IOV_READ_ERROR__IOV_ERROR__SHIFT = 0x1f # macro +GRBM_IOV_READ_ERROR__IOV_ADDR_MASK = 0x000FFFFC # macro +GRBM_IOV_READ_ERROR__IOV_VFID_MASK = 0x03F00000 # macro +GRBM_IOV_READ_ERROR__IOV_VF_MASK = 0x04000000 # macro +GRBM_IOV_READ_ERROR__IOV_OP_MASK = 0x08000000 # macro +GRBM_IOV_READ_ERROR__IOV_ERROR_MASK = 0x80000000 # macro +GRBM_NOWHERE__DATA__SHIFT = 0x0 # macro +GRBM_NOWHERE__DATA_MASK = 0xFFFFFFFF # macro +GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT = 0x0 # macro +GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK = 0xFFFFFFFF # macro +GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT = 0x0 # macro +GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK = 0xFFFFFFFF # macro +GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT = 0x0 # macro +GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK = 0xFFFFFFFF # macro +GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT = 0x0 # macro +GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK = 0xFFFFFFFF # macro +GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT = 0x0 # macro +GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK = 0xFFFFFFFF # macro +GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT = 0x0 # macro +GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK = 0xFFFFFFFF # macro +GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT = 0x0 # macro +GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK = 0xFFFFFFFF # macro +GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT = 0x0 # macro +GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK = 0xFFFFFFFF # macro +VIOLATION_DATA_ASYNC_VF_PROG__SSRCID__SHIFT = 0x0 # macro +VIOLATION_DATA_ASYNC_VF_PROG__VFID__SHIFT = 0x4 # macro +VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR__SHIFT = 0x1f # macro +VIOLATION_DATA_ASYNC_VF_PROG__SSRCID_MASK = 0x0000000F # macro +VIOLATION_DATA_ASYNC_VF_PROG__VFID_MASK = 0x000003F0 # macro +VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR_MASK = 0x80000000 # macro +CP_CPC_DEBUG_CNTL__DEBUG_INDX__SHIFT = 0x0 # macro +CP_CPC_DEBUG_CNTL__DEBUG_BUS_DC_GD_SEL__SHIFT = 0x8 # macro +CP_CPC_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS__SHIFT = 0x10 # macro +CP_CPC_DEBUG_CNTL__DEBUG_BUS_FLOP_EN__SHIFT = 0x1f # macro +CP_CPC_DEBUG_CNTL__DEBUG_INDX_MASK = 0x0000007F # macro +CP_CPC_DEBUG_CNTL__DEBUG_BUS_DC_GD_SEL_MASK = 0x00000700 # macro +CP_CPC_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS_MASK = 0x003F0000 # macro +CP_CPC_DEBUG_CNTL__DEBUG_BUS_FLOP_EN_MASK = 0x80000000 # macro +CP_CPF_DEBUG_CNTL__DEBUG_INDX__SHIFT = 0x0 # macro +CP_CPF_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS__SHIFT = 0x10 # macro +CP_CPF_DEBUG_CNTL__DEBUG_BUS_FLOP_EN__SHIFT = 0x1f # macro +CP_CPF_DEBUG_CNTL__DEBUG_INDX_MASK = 0x0000007F # macro +CP_CPF_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS_MASK = 0x003F0000 # macro +CP_CPF_DEBUG_CNTL__DEBUG_BUS_FLOP_EN_MASK = 0x80000000 # macro +CP_CPC_STATUS__MEC1_BUSY__SHIFT = 0x0 # macro +CP_CPC_STATUS__MEC2_BUSY__SHIFT = 0x1 # macro +CP_CPC_STATUS__DC0_BUSY__SHIFT = 0x2 # macro +CP_CPC_STATUS__DC1_BUSY__SHIFT = 0x3 # macro +CP_CPC_STATUS__RCIU1_BUSY__SHIFT = 0x4 # macro +CP_CPC_STATUS__RCIU2_BUSY__SHIFT = 0x5 # macro +CP_CPC_STATUS__ROQ1_BUSY__SHIFT = 0x6 # macro +CP_CPC_STATUS__ROQ2_BUSY__SHIFT = 0x7 # macro +CP_CPC_STATUS__TCIU_BUSY__SHIFT = 0xa # macro +CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT = 0xb # macro +CP_CPC_STATUS__QU_BUSY__SHIFT = 0xc # macro +CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT = 0xd # macro +CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT = 0xe # macro +CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT = 0x1d # macro +CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT = 0x1e # macro +CP_CPC_STATUS__CPC_BUSY__SHIFT = 0x1f # macro +CP_CPC_STATUS__MEC1_BUSY_MASK = 0x00000001 # macro +CP_CPC_STATUS__MEC2_BUSY_MASK = 0x00000002 # macro +CP_CPC_STATUS__DC0_BUSY_MASK = 0x00000004 # macro +CP_CPC_STATUS__DC1_BUSY_MASK = 0x00000008 # macro +CP_CPC_STATUS__RCIU1_BUSY_MASK = 0x00000010 # macro +CP_CPC_STATUS__RCIU2_BUSY_MASK = 0x00000020 # macro +CP_CPC_STATUS__ROQ1_BUSY_MASK = 0x00000040 # macro +CP_CPC_STATUS__ROQ2_BUSY_MASK = 0x00000080 # macro +CP_CPC_STATUS__TCIU_BUSY_MASK = 0x00000400 # macro +CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK = 0x00000800 # macro +CP_CPC_STATUS__QU_BUSY_MASK = 0x00001000 # macro +CP_CPC_STATUS__UTCL2IU_BUSY_MASK = 0x00002000 # macro +CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK = 0x00004000 # macro +CP_CPC_STATUS__CPG_CPC_BUSY_MASK = 0x20000000 # macro +CP_CPC_STATUS__CPF_CPC_BUSY_MASK = 0x40000000 # macro +CP_CPC_STATUS__CPC_BUSY_MASK = 0x80000000 # macro +CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT = 0x0 # macro +CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT = 0x1 # macro +CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT = 0x2 # macro +CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT = 0x3 # macro +CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT = 0x4 # macro +CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT = 0x5 # macro +CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT = 0x6 # macro +CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT = 0x7 # macro +CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT = 0x8 # macro +CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT = 0x9 # macro +CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT = 0xa # macro +CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT = 0xb # macro +CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT = 0xc # macro +CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT = 0xd # macro +CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT = 0x10 # macro +CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT = 0x11 # macro +CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT = 0x12 # macro +CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT = 0x13 # macro +CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT = 0x14 # macro +CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT = 0x15 # macro +CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT = 0x16 # macro +CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT = 0x17 # macro +CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT = 0x18 # macro +CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT = 0x19 # macro +CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT = 0x1a # macro +CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT = 0x1b # macro +CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT = 0x1c # macro +CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT = 0x1d # macro +CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK = 0x00000001 # macro +CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK = 0x00000002 # macro +CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK = 0x00000004 # macro +CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK = 0x00000008 # macro +CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK = 0x00000010 # macro +CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK = 0x00000020 # macro +CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK = 0x00000040 # macro +CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK = 0x00000080 # macro +CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK = 0x00000100 # macro +CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK = 0x00000200 # macro +CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK = 0x00000400 # macro +CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK = 0x00000800 # macro +CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK = 0x00001000 # macro +CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK = 0x00002000 # macro +CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK = 0x00010000 # macro +CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK = 0x00020000 # macro +CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK = 0x00040000 # macro +CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK = 0x00080000 # macro +CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK = 0x00100000 # macro +CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK = 0x00200000 # macro +CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK = 0x00400000 # macro +CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK = 0x00800000 # macro +CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK = 0x01000000 # macro +CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK = 0x02000000 # macro +CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK = 0x04000000 # macro +CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK = 0x08000000 # macro +CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK = 0x10000000 # macro +CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK = 0x20000000 # macro +CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT = 0x3 # macro +CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT = 0x4 # macro +CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT = 0x6 # macro +CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT = 0x8 # macro +CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT = 0x9 # macro +CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT = 0xa # macro +CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT = 0xd # macro +CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT = 0x10 # macro +CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT = 0x11 # macro +CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT = 0x12 # macro +CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT = 0x15 # macro +CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT = 0x16 # macro +CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT = 0x17 # macro +CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT = 0x18 # macro +CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK = 0x00000008 # macro +CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK = 0x00000010 # macro +CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK = 0x00000040 # macro +CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK = 0x00000100 # macro +CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK = 0x00000200 # macro +CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK = 0x00000400 # macro +CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK = 0x00002000 # macro +CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK = 0x00010000 # macro +CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK = 0x00020000 # macro +CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK = 0x00040000 # macro +CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK = 0x00200000 # macro +CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK = 0x00400000 # macro +CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK = 0x00800000 # macro +CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK = 0x01000000 # macro +CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT = 0x0 # macro +CP_CPF_STATUS__CSF_BUSY__SHIFT = 0x1 # macro +CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT = 0x4 # macro +CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT = 0x5 # macro +CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT = 0x6 # macro +CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT = 0x7 # macro +CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT = 0x8 # macro +CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT = 0x9 # macro +CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT = 0xa # macro +CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT = 0xb # macro +CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT = 0xc # macro +CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT = 0xd # macro +CP_CPF_STATUS__TCIU_BUSY__SHIFT = 0xe # macro +CP_CPF_STATUS__HQD_BUSY__SHIFT = 0xf # macro +CP_CPF_STATUS__PRT_BUSY__SHIFT = 0x10 # macro +CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT = 0x11 # macro +CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT = 0x1a # macro +CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT = 0x1b # macro +CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT = 0x1c # macro +CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT = 0x1e # macro +CP_CPF_STATUS__CPF_BUSY__SHIFT = 0x1f # macro +CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK = 0x00000001 # macro +CP_CPF_STATUS__CSF_BUSY_MASK = 0x00000002 # macro +CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK = 0x00000010 # macro +CP_CPF_STATUS__ROQ_RING_BUSY_MASK = 0x00000020 # macro +CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK = 0x00000040 # macro +CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK = 0x00000080 # macro +CP_CPF_STATUS__ROQ_STATE_BUSY_MASK = 0x00000100 # macro +CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK = 0x00000200 # macro +CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK = 0x00000400 # macro +CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK = 0x00000800 # macro +CP_CPF_STATUS__SEMAPHORE_BUSY_MASK = 0x00001000 # macro +CP_CPF_STATUS__INTERRUPT_BUSY_MASK = 0x00002000 # macro +CP_CPF_STATUS__TCIU_BUSY_MASK = 0x00004000 # macro +CP_CPF_STATUS__HQD_BUSY_MASK = 0x00008000 # macro +CP_CPF_STATUS__PRT_BUSY_MASK = 0x00010000 # macro +CP_CPF_STATUS__UTCL2IU_BUSY_MASK = 0x00020000 # macro +CP_CPF_STATUS__CPF_GFX_BUSY_MASK = 0x04000000 # macro +CP_CPF_STATUS__CPF_CMP_BUSY_MASK = 0x08000000 # macro +CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK = 0x30000000 # macro +CP_CPF_STATUS__CPC_CPF_BUSY_MASK = 0x40000000 # macro +CP_CPF_STATUS__CPF_BUSY_MASK = 0x80000000 # macro +CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT = 0x0 # macro +CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT = 0x1 # macro +CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT = 0x2 # macro +CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT = 0x3 # macro +CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT = 0x4 # macro +CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT = 0x5 # macro +CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT = 0x6 # macro +CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT = 0x7 # macro +CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT = 0x8 # macro +CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT = 0x9 # macro +CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT = 0xb # macro +CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT = 0xc # macro +CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT = 0xd # macro +CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT = 0xe # macro +CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT = 0xf # macro +CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT = 0x10 # macro +CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT = 0x11 # macro +CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT = 0x12 # macro +CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT = 0x13 # macro +CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT = 0x14 # macro +CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT = 0x15 # macro +CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT = 0x16 # macro +CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT = 0x17 # macro +CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT = 0x18 # macro +CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT = 0x19 # macro +CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT = 0x1a # macro +CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT = 0x1b # macro +CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT = 0x1c # macro +CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT = 0x1d # macro +CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT = 0x1e # macro +CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT = 0x1f # macro +CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK = 0x00000001 # macro +CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK = 0x00000002 # macro +CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK = 0x00000004 # macro +CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK = 0x00000008 # macro +CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK = 0x00000010 # macro +CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK = 0x00000020 # macro +CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK = 0x00000040 # macro +CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK = 0x00000080 # macro +CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK = 0x00000100 # macro +CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK = 0x00000200 # macro +CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK = 0x00000800 # macro +CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK = 0x00001000 # macro +CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK = 0x00002000 # macro +CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK = 0x00004000 # macro +CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK = 0x00008000 # macro +CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK = 0x00010000 # macro +CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK = 0x00020000 # macro +CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK = 0x00040000 # macro +CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK = 0x00080000 # macro +CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK = 0x00100000 # macro +CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK = 0x00200000 # macro +CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK = 0x00400000 # macro +CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK = 0x00800000 # macro +CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK = 0x01000000 # macro +CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK = 0x02000000 # macro +CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK = 0x04000000 # macro +CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK = 0x08000000 # macro +CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK = 0x10000000 # macro +CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK = 0x20000000 # macro +CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK = 0x40000000 # macro +CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK = 0x80000000 # macro +CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT = 0x0 # macro +CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT = 0x1 # macro +CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT = 0x2 # macro +CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT = 0x3 # macro +CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT = 0x5 # macro +CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT = 0x6 # macro +CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT = 0x7 # macro +CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT = 0x8 # macro +CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT = 0x9 # macro +CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT = 0xa # macro +CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT = 0xb # macro +CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK = 0x00000001 # macro +CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK = 0x00000002 # macro +CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK = 0x00000004 # macro +CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK = 0x00000008 # macro +CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK = 0x00000020 # macro +CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK = 0x00000040 # macro +CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK = 0x00000080 # macro +CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK = 0x00000100 # macro +CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK = 0x00000200 # macro +CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK = 0x00000400 # macro +CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK = 0x00000800 # macro +CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT = 0x0 # macro +CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK = 0x0000003F # macro +CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_STATUS__SHIFT = 0x0 # macro +CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_OP__SHIFT = 0x1 # macro +CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT = 0x2 # macro +CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_APERTURE_ID__SHIFT = 0x14 # macro +CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_STATUS_MASK = 0x00000001 # macro +CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_OP_MASK = 0x00000002 # macro +CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK = 0x000FFFFC # macro +CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_APERTURE_ID_MASK = 0xFFF00000 # macro +CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT = 0x4 # macro +CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT = 0x10 # macro +CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT = 0x11 # macro +CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT = 0x12 # macro +CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT = 0x13 # macro +CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT = 0x14 # macro +CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT = 0x15 # macro +CP_MEC_CNTL__MEC_ME2_HALT__SHIFT = 0x1c # macro +CP_MEC_CNTL__MEC_ME2_STEP__SHIFT = 0x1d # macro +CP_MEC_CNTL__MEC_ME1_HALT__SHIFT = 0x1e # macro +CP_MEC_CNTL__MEC_ME1_STEP__SHIFT = 0x1f # macro +CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK = 0x00000010 # macro +CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK = 0x00010000 # macro +CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK = 0x00020000 # macro +CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK = 0x00040000 # macro +CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK = 0x00080000 # macro +CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK = 0x00100000 # macro +CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK = 0x00200000 # macro +CP_MEC_CNTL__MEC_ME2_HALT_MASK = 0x10000000 # macro +CP_MEC_CNTL__MEC_ME2_STEP_MASK = 0x20000000 # macro +CP_MEC_CNTL__MEC_ME1_HALT_MASK = 0x40000000 # macro +CP_MEC_CNTL__MEC_ME1_STEP_MASK = 0x80000000 # macro +CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT = 0x0 # macro +CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK = 0xFFFFFFFF # macro +CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT = 0x0 # macro +CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK = 0xFFFFFFFF # macro +CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT = 0x0 # macro +CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK = 0x000003FF # macro +CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT = 0x0 # macro +CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK = 0xFFFFFFFF # macro +CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT = 0x0 # macro +CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK = 0x00000007 # macro +CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT = 0x0 # macro +CP_CPC_HALT_HYST_COUNT__COUNT_MASK = 0x0000000F # macro +CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT = 0x0 # macro +CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK = 0xFFFFFFFF # macro +CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT = 0x0 # macro +CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK = 0xFFFFFFFF # macro +CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT = 0x0 # macro +CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK = 0xFFFFFFFF # macro +CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT = 0x0 # macro +CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK = 0xFFFFFFFF # macro +CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT = 0x0 # macro +CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK = 0xFFFFFFFF # macro +CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT = 0x0 # macro +CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT = 0x1 # macro +CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT = 0x2 # macro +CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT = 0x3 # macro +CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT = 0x4 # macro +CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT = 0x5 # macro +CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT = 0x6 # macro +CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT = 0x7 # macro +CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT = 0xa # macro +CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT = 0xb # macro +CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT = 0xc # macro +CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT = 0xd # macro +CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT = 0xe # macro +CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT = 0xf # macro +CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT = 0x10 # macro +CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT = 0x11 # macro +CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT = 0x12 # macro +CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT = 0x13 # macro +CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT = 0x14 # macro +CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK = 0x00000001 # macro +CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK = 0x00000002 # macro +CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK = 0x00000004 # macro +CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK = 0x00000008 # macro +CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK = 0x00000010 # macro +CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK = 0x00000020 # macro +CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK = 0x00000040 # macro +CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK = 0x00000080 # macro +CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK = 0x00000400 # macro +CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK = 0x00000800 # macro +CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK = 0x00001000 # macro +CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK = 0x00002000 # macro +CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK = 0x00004000 # macro +CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK = 0x00008000 # macro +CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK = 0x00010000 # macro +CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK = 0x00020000 # macro +CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK = 0x00040000 # macro +CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK = 0x00080000 # macro +CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK = 0x00100000 # macro +CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT = 0x0 # macro +CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT = 0x2 # macro +CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT = 0x4 # macro +CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT = 0xa # macro +CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT = 0xb # macro +CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT = 0xc # macro +CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT = 0xd # macro +CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT = 0xe # macro +CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT = 0xf # macro +CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT = 0x17 # macro +CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT = 0x18 # macro +CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT = 0x19 # macro +CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT = 0x1a # macro +CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT = 0x1b # macro +CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT = 0x1c # macro +CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT = 0x1d # macro +CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK = 0x00000001 # macro +CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK = 0x00000004 # macro +CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK = 0x00000010 # macro +CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK = 0x00000400 # macro +CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK = 0x00000800 # macro +CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK = 0x00001000 # macro +CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK = 0x00002000 # macro +CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK = 0x00004000 # macro +CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK = 0x00008000 # macro +CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK = 0x00800000 # macro +CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK = 0x01000000 # macro +CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK = 0x02000000 # macro +CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK = 0x04000000 # macro +CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK = 0x08000000 # macro +CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK = 0x10000000 # macro +CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK = 0x20000000 # macro +CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT = 0x0 # macro +CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT = 0x1 # macro +CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT = 0x2 # macro +CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT = 0x4 # macro +CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT = 0x5 # macro +CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT = 0x8 # macro +CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT = 0x9 # macro +CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT = 0xa # macro +CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT = 0xb # macro +CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT = 0xc # macro +CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT = 0xd # macro +CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT = 0xe # macro +CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT = 0xf # macro +CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT = 0x10 # macro +CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT = 0x11 # macro +CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT = 0x12 # macro +CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT = 0x13 # macro +CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT = 0x14 # macro +CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT = 0x15 # macro +CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT = 0x16 # macro +CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT = 0x17 # macro +CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT = 0x18 # macro +CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT = 0x19 # macro +CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT = 0x1a # macro +CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT = 0x1b # macro +CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT = 0x1c # macro +CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT = 0x1d # macro +CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT = 0x1e # macro +CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT = 0x1f # macro +CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK = 0x00000001 # macro +CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK = 0x00000002 # macro +CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK = 0x00000004 # macro +CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK = 0x00000010 # macro +CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK = 0x00000020 # macro +CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK = 0x00000100 # macro +CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK = 0x00000200 # macro +CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK = 0x00000400 # macro +CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK = 0x00000800 # macro +CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK = 0x00001000 # macro +CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK = 0x00002000 # macro +CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK = 0x00004000 # macro +CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK = 0x00008000 # macro +CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK = 0x00010000 # macro +CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK = 0x00020000 # macro +CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK = 0x00040000 # macro +CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK = 0x00080000 # macro +CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK = 0x00100000 # macro +CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK = 0x00200000 # macro +CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK = 0x00400000 # macro +CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK = 0x00800000 # macro +CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK = 0x01000000 # macro +CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK = 0x02000000 # macro +CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK = 0x04000000 # macro +CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK = 0x08000000 # macro +CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK = 0x10000000 # macro +CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK = 0x20000000 # macro +CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK = 0x40000000 # macro +CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK = 0x80000000 # macro +CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT = 0x0 # macro +CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT = 0x6 # macro +CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT = 0x7 # macro +CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT = 0x8 # macro +CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT = 0x9 # macro +CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT = 0xa # macro +CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT = 0xc # macro +CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT = 0xd # macro +CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT = 0xe # macro +CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT = 0xf # macro +CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT = 0x11 # macro +CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT = 0x12 # macro +CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT = 0x13 # macro +CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT = 0x14 # macro +CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT = 0x15 # macro +CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT = 0x16 # macro +CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK = 0x00000001 # macro +CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK = 0x00000040 # macro +CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK = 0x00000080 # macro +CP_BUSY_STAT__ME_PARSING_PACKETS_MASK = 0x00000100 # macro +CP_BUSY_STAT__RCIU_PFP_BUSY_MASK = 0x00000200 # macro +CP_BUSY_STAT__RCIU_ME_BUSY_MASK = 0x00000400 # macro +CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK = 0x00001000 # macro +CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK = 0x00002000 # macro +CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK = 0x00004000 # macro +CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK = 0x00008000 # macro +CP_BUSY_STAT__ME_PARSER_BUSY_MASK = 0x00020000 # macro +CP_BUSY_STAT__EOP_DONE_BUSY_MASK = 0x00040000 # macro +CP_BUSY_STAT__STRM_OUT_BUSY_MASK = 0x00080000 # macro +CP_BUSY_STAT__PIPE_STATS_BUSY_MASK = 0x00100000 # macro +CP_BUSY_STAT__RCIU_CE_BUSY_MASK = 0x00200000 # macro +CP_BUSY_STAT__CE_PARSING_PACKETS_MASK = 0x00400000 # macro +CP_STAT__ROQ_RING_BUSY__SHIFT = 0x9 # macro +CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT = 0xa # macro +CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT = 0xb # macro +CP_STAT__ROQ_STATE_BUSY__SHIFT = 0xc # macro +CP_STAT__DC_BUSY__SHIFT = 0xd # macro +CP_STAT__UTCL2IU_BUSY__SHIFT = 0xe # macro +CP_STAT__PFP_BUSY__SHIFT = 0xf # macro +CP_STAT__MEQ_BUSY__SHIFT = 0x10 # macro +CP_STAT__ME_BUSY__SHIFT = 0x11 # macro +CP_STAT__QUERY_BUSY__SHIFT = 0x12 # macro +CP_STAT__SEMAPHORE_BUSY__SHIFT = 0x13 # macro +CP_STAT__INTERRUPT_BUSY__SHIFT = 0x14 # macro +CP_STAT__SURFACE_SYNC_BUSY__SHIFT = 0x15 # macro +CP_STAT__DMA_BUSY__SHIFT = 0x16 # macro +CP_STAT__RCIU_BUSY__SHIFT = 0x17 # macro +CP_STAT__SCRATCH_RAM_BUSY__SHIFT = 0x18 # macro +CP_STAT__CE_BUSY__SHIFT = 0x1a # macro +CP_STAT__TCIU_BUSY__SHIFT = 0x1b # macro +CP_STAT__ROQ_CE_RING_BUSY__SHIFT = 0x1c # macro +CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT = 0x1d # macro +CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT = 0x1e # macro +CP_STAT__CP_BUSY__SHIFT = 0x1f # macro +CP_STAT__ROQ_RING_BUSY_MASK = 0x00000200 # macro +CP_STAT__ROQ_INDIRECT1_BUSY_MASK = 0x00000400 # macro +CP_STAT__ROQ_INDIRECT2_BUSY_MASK = 0x00000800 # macro +CP_STAT__ROQ_STATE_BUSY_MASK = 0x00001000 # macro +CP_STAT__DC_BUSY_MASK = 0x00002000 # macro +CP_STAT__UTCL2IU_BUSY_MASK = 0x00004000 # macro +CP_STAT__PFP_BUSY_MASK = 0x00008000 # macro +CP_STAT__MEQ_BUSY_MASK = 0x00010000 # macro +CP_STAT__ME_BUSY_MASK = 0x00020000 # macro +CP_STAT__QUERY_BUSY_MASK = 0x00040000 # macro +CP_STAT__SEMAPHORE_BUSY_MASK = 0x00080000 # macro +CP_STAT__INTERRUPT_BUSY_MASK = 0x00100000 # macro +CP_STAT__SURFACE_SYNC_BUSY_MASK = 0x00200000 # macro +CP_STAT__DMA_BUSY_MASK = 0x00400000 # macro +CP_STAT__RCIU_BUSY_MASK = 0x00800000 # macro +CP_STAT__SCRATCH_RAM_BUSY_MASK = 0x01000000 # macro +CP_STAT__CE_BUSY_MASK = 0x04000000 # macro +CP_STAT__TCIU_BUSY_MASK = 0x08000000 # macro +CP_STAT__ROQ_CE_RING_BUSY_MASK = 0x10000000 # macro +CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK = 0x20000000 # macro +CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK = 0x40000000 # macro +CP_STAT__CP_BUSY_MASK = 0x80000000 # macro +CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT = 0x0 # macro +CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK = 0xFFFFFFFF # macro +CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT = 0x0 # macro +CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK = 0xFFFFFFFF # macro +CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT = 0x0 # macro +CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT = 0x8 # macro +CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT = 0x10 # macro +CP_GRBM_FREE_COUNT__FREE_COUNT_MASK = 0x0000003F # macro +CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK = 0x00003F00 # macro +CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK = 0x003F0000 # macro +CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT = 0x0 # macro +CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK = 0xFFFFFFFF # macro +CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT = 0x0 # macro +CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK = 0x0000FFFF # macro +CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT = 0x0 # macro +CP_ME_INSTR_PNTR__INSTR_PNTR_MASK = 0x0000FFFF # macro +CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT = 0x0 # macro +CP_CE_INSTR_PNTR__INSTR_PNTR_MASK = 0x0000FFFF # macro +CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT = 0x0 # macro +CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK = 0x0000FFFF # macro +CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT = 0x0 # macro +CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK = 0x0000FFFF # macro +CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT = 0x8 # macro +CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK = 0x0001FF00 # macro +CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT = 0x4 # macro +CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT = 0x6 # macro +CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT = 0x8 # macro +CP_ME_CNTL__CE_PIPE0_RESET__SHIFT = 0x10 # macro +CP_ME_CNTL__CE_PIPE1_RESET__SHIFT = 0x11 # macro +CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT = 0x12 # macro +CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT = 0x13 # macro +CP_ME_CNTL__ME_PIPE0_RESET__SHIFT = 0x14 # macro +CP_ME_CNTL__ME_PIPE1_RESET__SHIFT = 0x15 # macro +CP_ME_CNTL__CE_HALT__SHIFT = 0x18 # macro +CP_ME_CNTL__CE_STEP__SHIFT = 0x19 # macro +CP_ME_CNTL__PFP_HALT__SHIFT = 0x1a # macro +CP_ME_CNTL__PFP_STEP__SHIFT = 0x1b # macro +CP_ME_CNTL__ME_HALT__SHIFT = 0x1c # macro +CP_ME_CNTL__ME_STEP__SHIFT = 0x1d # macro +CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK = 0x00000010 # macro +CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK = 0x00000040 # macro +CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK = 0x00000100 # macro +CP_ME_CNTL__CE_PIPE0_RESET_MASK = 0x00010000 # macro +CP_ME_CNTL__CE_PIPE1_RESET_MASK = 0x00020000 # macro +CP_ME_CNTL__PFP_PIPE0_RESET_MASK = 0x00040000 # macro +CP_ME_CNTL__PFP_PIPE1_RESET_MASK = 0x00080000 # macro +CP_ME_CNTL__ME_PIPE0_RESET_MASK = 0x00100000 # macro +CP_ME_CNTL__ME_PIPE1_RESET_MASK = 0x00200000 # macro +CP_ME_CNTL__CE_HALT_MASK = 0x01000000 # macro +CP_ME_CNTL__CE_STEP_MASK = 0x02000000 # macro +CP_ME_CNTL__PFP_HALT_MASK = 0x04000000 # macro +CP_ME_CNTL__PFP_STEP_MASK = 0x08000000 # macro +CP_ME_CNTL__ME_HALT_MASK = 0x10000000 # macro +CP_ME_CNTL__ME_STEP_MASK = 0x20000000 # macro +CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT = 0x0 # macro +CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT = 0x8 # macro +CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT = 0x14 # macro +CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT = 0x1c # macro +CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK = 0x000000FF # macro +CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK = 0x00000700 # macro +CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK = 0x0FF00000 # macro +CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK = 0x70000000 # macro +CP_ME_PREEMPTION__OBSOLETE__SHIFT = 0x0 # macro +CP_ME_PREEMPTION__OBSOLETE_MASK = 0x00000001 # macro +CP_ROQ_THRESHOLDS__IB1_START__SHIFT = 0x0 # macro +CP_ROQ_THRESHOLDS__IB2_START__SHIFT = 0x8 # macro +CP_ROQ_THRESHOLDS__IB1_START_MASK = 0x000000FF # macro +CP_ROQ_THRESHOLDS__IB2_START_MASK = 0x0000FF00 # macro +CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT = 0x0 # macro +CP_MEQ_STQ_THRESHOLD__STQ_START_MASK = 0x000000FF # macro +CP_RB2_RPTR__RB_RPTR__SHIFT = 0x0 # macro +CP_RB2_RPTR__RB_RPTR_MASK = 0x000FFFFF # macro +CP_RB1_RPTR__RB_RPTR__SHIFT = 0x0 # macro +CP_RB1_RPTR__RB_RPTR_MASK = 0x000FFFFF # macro +CP_RB0_RPTR__RB_RPTR__SHIFT = 0x0 # macro +CP_RB0_RPTR__RB_RPTR_MASK = 0x000FFFFF # macro +CP_RB_RPTR__RB_RPTR__SHIFT = 0x0 # macro +CP_RB_RPTR__RB_RPTR_MASK = 0x000FFFFF # macro +CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT = 0x0 # macro +CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT = 0x1c # macro +CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK = 0x0FFFFFFF # macro +CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK = 0xF0000000 # macro +CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT = 0x0 # macro +CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT = 0x10 # macro +CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK = 0x0000FFFF # macro +CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK = 0xFFFF0000 # macro +CP_ROQ1_THRESHOLDS__RB1_START__SHIFT = 0x0 # macro +CP_ROQ1_THRESHOLDS__RB2_START__SHIFT = 0x8 # macro +CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT = 0x10 # macro +CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT = 0x18 # macro +CP_ROQ1_THRESHOLDS__RB1_START_MASK = 0x000000FF # macro +CP_ROQ1_THRESHOLDS__RB2_START_MASK = 0x0000FF00 # macro +CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK = 0x00FF0000 # macro +CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK = 0xFF000000 # macro +CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT = 0x0 # macro +CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT = 0x8 # macro +CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT = 0x10 # macro +CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT = 0x18 # macro +CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK = 0x000000FF # macro +CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK = 0x0000FF00 # macro +CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK = 0x00FF0000 # macro +CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK = 0xFF000000 # macro +CP_STQ_THRESHOLDS__STQ0_START__SHIFT = 0x0 # macro +CP_STQ_THRESHOLDS__STQ1_START__SHIFT = 0x8 # macro +CP_STQ_THRESHOLDS__STQ2_START__SHIFT = 0x10 # macro +CP_STQ_THRESHOLDS__STQ0_START_MASK = 0x000000FF # macro +CP_STQ_THRESHOLDS__STQ1_START_MASK = 0x0000FF00 # macro +CP_STQ_THRESHOLDS__STQ2_START_MASK = 0x00FF0000 # macro +CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT = 0x0 # macro +CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT = 0x8 # macro +CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK = 0x0000003F # macro +CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK = 0x00003F00 # macro +CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT = 0x0 # macro +CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT = 0x8 # macro +CP_MEQ_THRESHOLDS__MEQ1_START_MASK = 0x000000FF # macro +CP_MEQ_THRESHOLDS__MEQ2_START_MASK = 0x0000FF00 # macro +CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT = 0x0 # macro +CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT = 0x10 # macro +CP_ROQ_AVAIL__ROQ_CNT_RING_MASK = 0x000007FF # macro +CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK = 0x07FF0000 # macro +CP_STQ_AVAIL__STQ_CNT__SHIFT = 0x0 # macro +CP_STQ_AVAIL__STQ_CNT_MASK = 0x000001FF # macro +CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT = 0x0 # macro +CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK = 0x000007FF # macro +CP_MEQ_AVAIL__MEQ_CNT__SHIFT = 0x0 # macro +CP_MEQ_AVAIL__MEQ_CNT_MASK = 0x000003FF # macro +CP_CMD_INDEX__CMD_INDEX__SHIFT = 0x0 # macro +CP_CMD_INDEX__CMD_ME_SEL__SHIFT = 0xc # macro +CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT = 0x10 # macro +CP_CMD_INDEX__CMD_INDEX_MASK = 0x000007FF # macro +CP_CMD_INDEX__CMD_ME_SEL_MASK = 0x00003000 # macro +CP_CMD_INDEX__CMD_QUEUE_SEL_MASK = 0x00070000 # macro +CP_CMD_DATA__CMD_DATA__SHIFT = 0x0 # macro +CP_CMD_DATA__CMD_DATA_MASK = 0xFFFFFFFF # macro +CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT = 0x0 # macro +CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT = 0x10 # macro +CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK = 0x000003FF # macro +CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK = 0x03FF0000 # macro +CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT = 0x0 # macro +CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT = 0x10 # macro +CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK = 0x000003FF # macro +CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK = 0x03FF0000 # macro +CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT = 0x0 # macro +CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT = 0x10 # macro +CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK = 0x000003FF # macro +CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK = 0x03FF0000 # macro +CP_STQ_STAT__STQ_RPTR__SHIFT = 0x0 # macro +CP_STQ_STAT__STQ_RPTR_MASK = 0x000003FF # macro +CP_STQ_WR_STAT__STQ_WPTR__SHIFT = 0x0 # macro +CP_STQ_WR_STAT__STQ_WPTR_MASK = 0x000003FF # macro +CP_MEQ_STAT__MEQ_RPTR__SHIFT = 0x0 # macro +CP_MEQ_STAT__MEQ_WPTR__SHIFT = 0x10 # macro +CP_MEQ_STAT__MEQ_RPTR_MASK = 0x000003FF # macro +CP_MEQ_STAT__MEQ_WPTR_MASK = 0x03FF0000 # macro +CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT = 0x0 # macro +CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT = 0x10 # macro +CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK = 0x000007FF # macro +CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK = 0x07FF0000 # macro +CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT = 0x0 # macro +CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK = 0x000007FF # macro +CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT = 0x0 # macro +CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT = 0x10 # macro +CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK = 0x000003FF # macro +CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK = 0x03FF0000 # macro +CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT = 0x0 # macro +CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT = 0x10 # macro +CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK = 0x000003FF # macro +CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK = 0x03FF0000 # macro +CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT = 0x0 # macro +CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT = 0x10 # macro +CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK = 0x000003FF # macro +CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK = 0x03FF0000 # macro +CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT = 0xb # macro +CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT = 0xe # macro +CP_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT = 0x10 # macro +CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT = 0x11 # macro +CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT = 0x12 # macro +CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT = 0x13 # macro +CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT = 0x14 # macro +CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT = 0x15 # macro +CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT = 0x16 # macro +CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT = 0x17 # macro +CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT = 0x18 # macro +CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT = 0x1a # macro +CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT = 0x1b # macro +CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT = 0x1d # macro +CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT = 0x1e # macro +CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT = 0x1f # macro +CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK = 0x00000800 # macro +CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK = 0x00004000 # macro +CP_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK = 0x00010000 # macro +CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK = 0x00020000 # macro +CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK = 0x00040000 # macro +CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK = 0x00080000 # macro +CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK = 0x00100000 # macro +CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK = 0x00200000 # macro +CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK = 0x00400000 # macro +CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK = 0x00800000 # macro +CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK = 0x01000000 # macro +CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK = 0x04000000 # macro +CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK = 0x08000000 # macro +CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK = 0x20000000 # macro +CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK = 0x40000000 # macro +CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK = 0x80000000 # macro +CP_DEBUG_CNTL__DEBUG_INDX__SHIFT = 0x0 # macro +CP_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS__SHIFT = 0x10 # macro +CP_DEBUG_CNTL__DEBUG_BUS_FLOP_EN__SHIFT = 0x1f # macro +CP_DEBUG_CNTL__DEBUG_INDX_MASK = 0x0000007F # macro +CP_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS_MASK = 0x003F0000 # macro +CP_DEBUG_CNTL__DEBUG_BUS_FLOP_EN_MASK = 0x80000000 # macro +CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT = 0x0 # macro +CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK = 0x0000FFFF # macro +VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT = 0x0 # macro +VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK = 0x0000007F # macro +VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT = 0x0 # macro +VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT = 0x9 # macro +VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK = 0x000001FF # macro +VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK = 0x0007FE00 # macro +VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT = 0x0 # macro +VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK = 0x0000003F # macro +VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT = 0x0 # macro +VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK = 0x0000003F # macro +VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT = 0x0 # macro +VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT = 0x10 # macro +VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK = 0x00000007 # macro +VGT_LAST_COPY_STATE__DST_STATE_ID_MASK = 0x00070000 # macro +VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT = 0x0 # macro +VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT = 0x4 # macro +VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT = 0x5 # macro +VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT = 0x6 # macro +VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT = 0x9 # macro +VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT = 0xb # macro +VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT = 0xc # macro +VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT = 0xd # macro +VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT = 0x10 # macro +VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT = 0x15 # macro +VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT = 0x16 # macro +VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT = 0x19 # macro +VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT = 0x1c # macro +VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT = 0x1d # macro +VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK = 0x00000003 # macro +VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK = 0x00000010 # macro +VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK = 0x00000020 # macro +VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK = 0x000000C0 # macro +VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK = 0x00000200 # macro +VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK = 0x00000800 # macro +VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK = 0x00001000 # macro +VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK = 0x00002000 # macro +VGT_CACHE_INVALIDATION__ES_LIMIT_MASK = 0x001F0000 # macro +VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK = 0x00200000 # macro +VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK = 0x01C00000 # macro +VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK = 0x0E000000 # macro +VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK = 0x10000000 # macro +VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK = 0x20000000 # macro +VGT_RESET_DEBUG__GS_DISABLE__SHIFT = 0x0 # macro +VGT_RESET_DEBUG__TESS_DISABLE__SHIFT = 0x1 # macro +VGT_RESET_DEBUG__WD_DISABLE__SHIFT = 0x2 # macro +VGT_RESET_DEBUG__GS_DISABLE_MASK = 0x00000001 # macro +VGT_RESET_DEBUG__TESS_DISABLE_MASK = 0x00000002 # macro +VGT_RESET_DEBUG__WD_DISABLE_MASK = 0x00000004 # macro +VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT = 0x0 # macro +VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT = 0x8 # macro +VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT = 0xb # macro +VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT = 0xe # macro +VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT = 0x11 # macro +VGT_STRMOUT_DELAY__SKIP_DELAY_MASK = 0x000000FF # macro +VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK = 0x00000700 # macro +VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK = 0x00003800 # macro +VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK = 0x0001C000 # macro +VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK = 0x000E0000 # macro +VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT = 0x0 # macro +VGT_FIFO_DEPTHS__RESERVED_0__SHIFT = 0x7 # macro +VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT = 0x8 # macro +VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT = 0x16 # macro +VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK = 0x0000007F # macro +VGT_FIFO_DEPTHS__RESERVED_0_MASK = 0x00000080 # macro +VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK = 0x003FFF00 # macro +VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK = 0x0FC00000 # macro +VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT = 0x0 # macro +VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK = 0x0000001F # macro +VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT = 0x0 # macro +VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK = 0x0000000F # macro +IA_CNTL_STATUS__IA_BUSY__SHIFT = 0x0 # macro +IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT = 0x1 # macro +IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT = 0x2 # macro +IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT = 0x3 # macro +IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT = 0x4 # macro +IA_CNTL_STATUS__IA_BUSY_MASK = 0x00000001 # macro +IA_CNTL_STATUS__IA_DMA_BUSY_MASK = 0x00000002 # macro +IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK = 0x00000004 # macro +IA_CNTL_STATUS__IA_GRP_BUSY_MASK = 0x00000008 # macro +IA_CNTL_STATUS__IA_ADC_BUSY_MASK = 0x00000010 # macro +VGT_CNTL_STATUS__VGT_BUSY__SHIFT = 0x0 # macro +VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT = 0x1 # macro +VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT = 0x2 # macro +VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT = 0x3 # macro +VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT = 0x4 # macro +VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT = 0x5 # macro +VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT = 0x6 # macro +VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT = 0x7 # macro +VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT = 0x8 # macro +VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT = 0x9 # macro +VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT = 0xa # macro +VGT_CNTL_STATUS__VGT_BUSY_MASK = 0x00000001 # macro +VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK = 0x00000002 # macro +VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK = 0x00000004 # macro +VGT_CNTL_STATUS__VGT_PT_BUSY_MASK = 0x00000008 # macro +VGT_CNTL_STATUS__VGT_TE_BUSY_MASK = 0x00000010 # macro +VGT_CNTL_STATUS__VGT_VR_BUSY_MASK = 0x00000020 # macro +VGT_CNTL_STATUS__VGT_PI_BUSY_MASK = 0x00000040 # macro +VGT_CNTL_STATUS__VGT_GS_BUSY_MASK = 0x00000080 # macro +VGT_CNTL_STATUS__VGT_HS_BUSY_MASK = 0x00000100 # macro +VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK = 0x00000200 # macro +VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK = 0x00000400 # macro +WD_CNTL_STATUS__WD_BUSY__SHIFT = 0x0 # macro +WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT = 0x1 # macro +WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT = 0x2 # macro +WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT = 0x3 # macro +WD_CNTL_STATUS__WD_BUSY_MASK = 0x00000001 # macro +WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK = 0x00000002 # macro +WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK = 0x00000004 # macro +WD_CNTL_STATUS__WD_ADC_BUSY_MASK = 0x00000008 # macro +CC_GC_PRIM_CONFIG__WRITE_DIS__SHIFT = 0x0 # macro +CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT = 0x10 # macro +CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT = 0x18 # macro +CC_GC_PRIM_CONFIG__WRITE_DIS_MASK = 0x00000001 # macro +CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK = 0x00030000 # macro +CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK = 0x0F000000 # macro +GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT = 0x10 # macro +GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT = 0x18 # macro +GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK = 0x00030000 # macro +GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK = 0x0F000000 # macro +WD_QOS__DRAW_STALL__SHIFT = 0x0 # macro +WD_QOS__DRAW_STALL_MASK = 0x00000001 # macro +WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT = 0x0 # macro +WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT = 0x17 # macro +WD_UTCL1_CNTL__DROP_MODE__SHIFT = 0x18 # macro +WD_UTCL1_CNTL__BYPASS__SHIFT = 0x19 # macro +WD_UTCL1_CNTL__INVALIDATE__SHIFT = 0x1a # macro +WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT = 0x1b # macro +WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT = 0x1c # macro +WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT = 0x1d # macro +WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK = 0x000FFFFF # macro +WD_UTCL1_CNTL__VMID_RESET_MODE_MASK = 0x00800000 # macro +WD_UTCL1_CNTL__DROP_MODE_MASK = 0x01000000 # macro +WD_UTCL1_CNTL__BYPASS_MASK = 0x02000000 # macro +WD_UTCL1_CNTL__INVALIDATE_MASK = 0x04000000 # macro +WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK = 0x08000000 # macro +WD_UTCL1_CNTL__FORCE_SNOOP_MASK = 0x10000000 # macro +WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK = 0x20000000 # macro +WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT = 0x0 # macro +WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT = 0x1 # macro +WD_UTCL1_STATUS__PRT_DETECTED__SHIFT = 0x2 # macro +WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT = 0x8 # macro +WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT = 0x10 # macro +WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT = 0x18 # macro +WD_UTCL1_STATUS__FAULT_DETECTED_MASK = 0x00000001 # macro +WD_UTCL1_STATUS__RETRY_DETECTED_MASK = 0x00000002 # macro +WD_UTCL1_STATUS__PRT_DETECTED_MASK = 0x00000004 # macro +WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK = 0x00003F00 # macro +WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK = 0x003F0000 # macro +WD_UTCL1_STATUS__PRT_UTCL1ID_MASK = 0x3F000000 # macro +IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT = 0x0 # macro +IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT = 0x17 # macro +IA_UTCL1_CNTL__DROP_MODE__SHIFT = 0x18 # macro +IA_UTCL1_CNTL__BYPASS__SHIFT = 0x19 # macro +IA_UTCL1_CNTL__INVALIDATE__SHIFT = 0x1a # macro +IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT = 0x1b # macro +IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT = 0x1c # macro +IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT = 0x1d # macro +IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK = 0x000FFFFF # macro +IA_UTCL1_CNTL__VMID_RESET_MODE_MASK = 0x00800000 # macro +IA_UTCL1_CNTL__DROP_MODE_MASK = 0x01000000 # macro +IA_UTCL1_CNTL__BYPASS_MASK = 0x02000000 # macro +IA_UTCL1_CNTL__INVALIDATE_MASK = 0x04000000 # macro +IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK = 0x08000000 # macro +IA_UTCL1_CNTL__FORCE_SNOOP_MASK = 0x10000000 # macro +IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK = 0x20000000 # macro +IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT = 0x0 # macro +IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT = 0x1 # macro +IA_UTCL1_STATUS__PRT_DETECTED__SHIFT = 0x2 # macro +IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT = 0x8 # macro +IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT = 0x10 # macro +IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT = 0x18 # macro +IA_UTCL1_STATUS__FAULT_DETECTED_MASK = 0x00000001 # macro +IA_UTCL1_STATUS__RETRY_DETECTED_MASK = 0x00000002 # macro +IA_UTCL1_STATUS__PRT_DETECTED_MASK = 0x00000004 # macro +IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK = 0x00003F00 # macro +IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK = 0x003F0000 # macro +IA_UTCL1_STATUS__PRT_UTCL1ID_MASK = 0x3F000000 # macro +VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT = 0x0 # macro +VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT = 0x1 # macro +VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT = 0x7 # macro +VGT_SYS_CONFIG__DUAL_CORE_EN_MASK = 0x00000001 # macro +VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK = 0x0000007E # macro +VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK = 0x00000080 # macro +VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT = 0x0 # macro +VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK = 0x00000FFF # macro +VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT = 0x0 # macro +VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK = 0x00000FFF # macro +GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT = 0x0 # macro +GFX_PIPE_CONTROL__RESERVED__SHIFT = 0xd # macro +GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT = 0x10 # macro +GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK = 0x00001FFF # macro +GFX_PIPE_CONTROL__RESERVED_MASK = 0x0000E000 # macro +GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK = 0x00010000 # macro +CC_GC_SHADER_ARRAY_CONFIG__WRITE_DIS__SHIFT = 0x0 # macro +CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT = 0x10 # macro +CC_GC_SHADER_ARRAY_CONFIG__WRITE_DIS_MASK = 0x00000001 # macro +CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK = 0xFFFF0000 # macro +GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT = 0x10 # macro +GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK = 0xFFFF0000 # macro +VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT = 0x0 # macro +VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK = 0x0000003F # macro +VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT = 0x0 # macro +VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT = 0x11 # macro +VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT = 0x13 # macro +VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT = 0x14 # macro +VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT = 0x15 # macro +VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT = 0x16 # macro +VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT = 0x17 # macro +VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK = 0x0000FFFF # macro +VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK = 0x00020000 # macro +VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK = 0x00080000 # macro +VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK = 0x00100000 # macro +VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK = 0x00200000 # macro +VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK = 0x00400000 # macro +VGT_DMA_CONTROL__HW_USE_ONLY_MASK = 0x00800000 # macro +VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT = 0x8 # macro +VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK = 0x00003F00 # macro +WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT = 0x0 # macro +WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT = 0x10 # macro +WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK = 0x0000FFFF # macro +WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK = 0xFFFF0000 # macro +WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT = 0x0 # macro +WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT = 0xf # macro +WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT = 0x10 # macro +WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK = 0x00001FFF # macro +WD_BUF_RESOURCE_2__ADDR_MODE_MASK = 0x00008000 # macro +WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK = 0xFFFF0000 # macro +PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT = 0x0 # macro +PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT = 0x1 # macro +PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT = 0x2 # macro +PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK = 0x00000001 # macro +PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK = 0x00000002 # macro +PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK = 0x00000004 # macro +PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT = 0x0 # macro +PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT = 0x1 # macro +PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT = 0x3 # macro +PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT = 0x4 # macro +PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT = 0x5 # macro +PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT = 0x6 # macro +PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT = 0x7 # macro +PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT = 0x8 # macro +PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT = 0x9 # macro +PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT = 0xb # macro +PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT = 0xc # macro +PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT = 0xe # macro +PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT = 0x11 # macro +PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT__SHIFT = 0x12 # macro +PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET__SHIFT = 0x13 # macro +PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT = 0x14 # macro +PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT = 0x15 # macro +PA_CL_ENHANCE__ECO_SPARE3__SHIFT = 0x1c # macro +PA_CL_ENHANCE__ECO_SPARE2__SHIFT = 0x1d # macro +PA_CL_ENHANCE__ECO_SPARE1__SHIFT = 0x1e # macro +PA_CL_ENHANCE__ECO_SPARE0__SHIFT = 0x1f # macro +PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK = 0x00000001 # macro +PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK = 0x00000006 # macro +PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK = 0x00000008 # macro +PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK = 0x00000010 # macro +PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK = 0x00000020 # macro +PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK = 0x00000040 # macro +PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK = 0x00000080 # macro +PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK = 0x00000100 # macro +PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK = 0x00000600 # macro +PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK = 0x00000800 # macro +PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK = 0x00003000 # macro +PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK = 0x0001C000 # macro +PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK = 0x00020000 # macro +PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT_MASK = 0x00040000 # macro +PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET_MASK = 0x00080000 # macro +PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK = 0x00100000 # macro +PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK = 0x00200000 # macro +PA_CL_ENHANCE__ECO_SPARE3_MASK = 0x10000000 # macro +PA_CL_ENHANCE__ECO_SPARE2_MASK = 0x20000000 # macro +PA_CL_ENHANCE__ECO_SPARE1_MASK = 0x40000000 # macro +PA_CL_ENHANCE__ECO_SPARE0_MASK = 0x80000000 # macro +PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT = 0x0 # macro +PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK = 0x00000001 # macro +PA_SU_CNTL_STATUS__SU_BUSY__SHIFT = 0x1f # macro +PA_SU_CNTL_STATUS__SU_BUSY_MASK = 0x80000000 # macro +PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT = 0x0 # macro +PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK = 0x000003FF # macro +PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT = 0x0 # macro +PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK = 0x00000001 # macro +PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT = 0x0 # macro +PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK = 0x00000001 # macro +PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT = 0x0 # macro +PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK = 0x00000001 # macro +PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT = 0x0 # macro +PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT = 0x10 # macro +PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK = 0x0000FFFF # macro +PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK = 0xFFFF0000 # macro +PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT = 0x0 # macro +PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT = 0x2 # macro +PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT = 0x4 # macro +PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT = 0x6 # macro +PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT = 0x8 # macro +PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT = 0xa # macro +PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT = 0xc # macro +PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT = 0xe # macro +PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT = 0x10 # macro +PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT = 0x12 # macro +PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT = 0x14 # macro +PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT = 0x16 # macro +PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT = 0x18 # macro +PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT = 0x1a # macro +PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT = 0x1c # macro +PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT = 0x1e # macro +PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK = 0x00000003 # macro +PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK = 0x0000000C # macro +PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK = 0x00000030 # macro +PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK = 0x000000C0 # macro +PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK = 0x00000300 # macro +PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK = 0x00000C00 # macro +PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK = 0x00003000 # macro +PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK = 0x0000C000 # macro +PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK = 0x00030000 # macro +PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK = 0x000C0000 # macro +PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK = 0x00300000 # macro +PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK = 0x00C00000 # macro +PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK = 0x03000000 # macro +PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK = 0x0C000000 # macro +PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK = 0x30000000 # macro +PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK = 0xC0000000 # macro +PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT = 0x0 # macro +PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT = 0x2 # macro +PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT = 0x4 # macro +PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT = 0x6 # macro +PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT = 0x8 # macro +PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT = 0xa # macro +PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT = 0xc # macro +PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT = 0xe # macro +PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT = 0x10 # macro +PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT = 0x12 # macro +PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT = 0x14 # macro +PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT = 0x16 # macro +PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT = 0x18 # macro +PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT = 0x1a # macro +PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT = 0x1c # macro +PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT = 0x1e # macro +PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK = 0x00000003 # macro +PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK = 0x0000000C # macro +PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK = 0x00000030 # macro +PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK = 0x000000C0 # macro +PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK = 0x00000300 # macro +PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK = 0x00000C00 # macro +PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK = 0x00003000 # macro +PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK = 0x0000C000 # macro +PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK = 0x00030000 # macro +PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK = 0x000C0000 # macro +PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK = 0x00300000 # macro +PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK = 0x00C00000 # macro +PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK = 0x03000000 # macro +PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK = 0x0C000000 # macro +PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK = 0x30000000 # macro +PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK = 0xC0000000 # macro +PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT = 0x0 # macro +PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT = 0x2 # macro +PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT = 0x4 # macro +PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT = 0x6 # macro +PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT = 0x8 # macro +PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT = 0xa # macro +PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT = 0xc # macro +PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT = 0xe # macro +PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT = 0x10 # macro +PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT = 0x12 # macro +PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT = 0x14 # macro +PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT = 0x16 # macro +PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT = 0x18 # macro +PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT = 0x1a # macro +PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT = 0x1c # macro +PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT = 0x1e # macro +PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK = 0x00000003 # macro +PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK = 0x0000000C # macro +PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK = 0x00000030 # macro +PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK = 0x000000C0 # macro +PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK = 0x00000300 # macro +PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK = 0x00000C00 # macro +PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK = 0x00003000 # macro +PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK = 0x0000C000 # macro +PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK = 0x00030000 # macro +PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK = 0x000C0000 # macro +PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK = 0x00300000 # macro +PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK = 0x00C00000 # macro +PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK = 0x03000000 # macro +PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK = 0x0C000000 # macro +PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK = 0x30000000 # macro +PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK = 0xC0000000 # macro +PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT = 0x0 # macro +PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT = 0x2 # macro +PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT = 0x4 # macro +PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT = 0x6 # macro +PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT = 0x8 # macro +PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT = 0xa # macro +PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT = 0xc # macro +PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT = 0xe # macro +PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT = 0x10 # macro +PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT = 0x12 # macro +PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT = 0x14 # macro +PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT = 0x16 # macro +PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT = 0x18 # macro +PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT = 0x1a # macro +PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT = 0x1c # macro +PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT = 0x1e # macro +PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK = 0x00000003 # macro +PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK = 0x0000000C # macro +PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK = 0x00000030 # macro +PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK = 0x000000C0 # macro +PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK = 0x00000300 # macro +PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK = 0x00000C00 # macro +PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK = 0x00003000 # macro +PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK = 0x0000C000 # macro +PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK = 0x00030000 # macro +PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK = 0x000C0000 # macro +PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK = 0x00300000 # macro +PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK = 0x00C00000 # macro +PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK = 0x03000000 # macro +PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK = 0x0C000000 # macro +PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK = 0x30000000 # macro +PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK = 0xC0000000 # macro +PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT = 0x0 # macro +PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK = 0xFFFFFFFF # macro +PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT = 0x0 # macro +PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT = 0xa # macro +PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT = 0x14 # macro +PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT = 0x17 # macro +PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK = 0x000003FF # macro +PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK = 0x000FFC00 # macro +PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK = 0x00700000 # macro +PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK = 0x03800000 # macro +PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT = 0x0 # macro +PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT = 0x5 # macro +PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT = 0xa # macro +PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK = 0x0000001F # macro +PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK = 0x000003E0 # macro +PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK = 0x03FFFC00 # macro +PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT = 0x0 # macro +PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT = 0xb # macro +PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK = 0x000007FF # macro +PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK = 0x003FF800 # macro +PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT = 0x0 # macro +PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK = 0xFFFFFFFF # macro +PA_SC_ENHANCE_2__RESERVED_0__SHIFT = 0x0 # macro +PA_SC_ENHANCE_2__RESERVED_1__SHIFT = 0x1 # macro +PA_SC_ENHANCE_2__RESERVED_2__SHIFT = 0x2 # macro +PA_SC_ENHANCE_2__RESERVED_3__SHIFT = 0x3 # macro +PA_SC_ENHANCE_2__RESERVED_4__SHIFT = 0x4 # macro +PA_SC_ENHANCE_2__RESERVED_5__SHIFT = 0x5 # macro +PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN__SHIFT = 0x6 # macro +PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PIPELINE_PRIMID__SHIFT = 0x7 # macro +PA_SC_ENHANCE_2__RSVD__SHIFT = 0x8 # macro +PA_SC_ENHANCE_2__RESERVED_0_MASK = 0x00000001 # macro +PA_SC_ENHANCE_2__RESERVED_1_MASK = 0x00000002 # macro +PA_SC_ENHANCE_2__RESERVED_2_MASK = 0x00000004 # macro +PA_SC_ENHANCE_2__RESERVED_3_MASK = 0x00000008 # macro +PA_SC_ENHANCE_2__RESERVED_4_MASK = 0x00000010 # macro +PA_SC_ENHANCE_2__RESERVED_5_MASK = 0x00000020 # macro +PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN_MASK = 0x00000040 # macro +PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PIPELINE_PRIMID_MASK = 0x00000080 # macro +PA_SC_ENHANCE_2__RSVD_MASK = 0xFFFFFF00 # macro +PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT = 0x0 # macro +PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT = 0x6 # macro +PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT = 0xf # macro +PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT = 0x15 # macro +PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK = 0x0000003F # macro +PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK = 0x00007FC0 # macro +PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK = 0x001F8000 # macro +PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK = 0xFFE00000 # macro +PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT = 0x0 # macro +PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT = 0x6 # macro +PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT = 0xc # macro +PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT = 0x12 # macro +PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK = 0x0000003F # macro +PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK = 0x00000FC0 # macro +PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK = 0x0003F000 # macro +PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK = 0x00FC0000 # macro +PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT = 0x0 # macro +PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK = 0x0000003F # macro +PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT = 0x0 # macro +PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT = 0x1 # macro +PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT = 0x2 # macro +PA_UTCL1_CNTL1__RESP_MODE__SHIFT = 0x3 # macro +PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT = 0x5 # macro +PA_UTCL1_CNTL1__CLIENTID__SHIFT = 0x7 # macro +PA_UTCL1_CNTL1__SPARE__SHIFT = 0x10 # macro +PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT = 0x11 # macro +PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT = 0x12 # macro +PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT = 0x13 # macro +PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT = 0x17 # macro +PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT = 0x18 # macro +PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT = 0x19 # macro +PA_UTCL1_CNTL1__FORCE_MISS__SHIFT = 0x1a # macro +PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT = 0x1b # macro +PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT = 0x1c # macro +PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT = 0x1e # macro +PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK = 0x00000001 # macro +PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK = 0x00000002 # macro +PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK = 0x00000004 # macro +PA_UTCL1_CNTL1__RESP_MODE_MASK = 0x00000018 # macro +PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK = 0x00000060 # macro +PA_UTCL1_CNTL1__CLIENTID_MASK = 0x0000FF80 # macro +PA_UTCL1_CNTL1__SPARE_MASK = 0x00010000 # macro +PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK = 0x00020000 # macro +PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK = 0x00040000 # macro +PA_UTCL1_CNTL1__REG_INV_VMID_MASK = 0x00780000 # macro +PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK = 0x00800000 # macro +PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK = 0x01000000 # macro +PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK = 0x02000000 # macro +PA_UTCL1_CNTL1__FORCE_MISS_MASK = 0x04000000 # macro +PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK = 0x08000000 # macro +PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK = 0x30000000 # macro +PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK = 0xC0000000 # macro +PA_UTCL1_CNTL2__SPARE1__SHIFT = 0x0 # macro +PA_UTCL1_CNTL2__SPARE2__SHIFT = 0x8 # macro +PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT = 0x9 # macro +PA_UTCL1_CNTL2__LINE_VALID__SHIFT = 0xa # macro +PA_UTCL1_CNTL2__SPARE3__SHIFT = 0xb # macro +PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT = 0xc # macro +PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT = 0xd # macro +PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT = 0xe # macro +PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT = 0xf # macro +PA_UTCL1_CNTL2__SPARE4__SHIFT = 0x10 # macro +PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT = 0x12 # macro +PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT = 0x13 # macro +PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT = 0x14 # macro +PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT = 0x15 # macro +PA_UTCL1_CNTL2__SPARE5__SHIFT = 0x19 # macro +PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT = 0x1a # macro +PA_UTCL1_CNTL2__RESERVED__SHIFT = 0x1b # macro +PA_UTCL1_CNTL2__SPARE1_MASK = 0x000000FF # macro +PA_UTCL1_CNTL2__SPARE2_MASK = 0x00000100 # macro +PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK = 0x00000200 # macro +PA_UTCL1_CNTL2__LINE_VALID_MASK = 0x00000400 # macro +PA_UTCL1_CNTL2__SPARE3_MASK = 0x00000800 # macro +PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK = 0x00001000 # macro +PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK = 0x00002000 # macro +PA_UTCL1_CNTL2__FORCE_SNOOP_MASK = 0x00004000 # macro +PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK = 0x00008000 # macro +PA_UTCL1_CNTL2__SPARE4_MASK = 0x00030000 # macro +PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK = 0x00040000 # macro +PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK = 0x00080000 # macro +PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK = 0x00100000 # macro +PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK = 0x01E00000 # macro +PA_UTCL1_CNTL2__SPARE5_MASK = 0x02000000 # macro +PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK = 0x04000000 # macro +PA_UTCL1_CNTL2__RESERVED_MASK = 0xF8000000 # macro +PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT = 0x0 # macro +PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT = 0x10 # macro +PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK = 0x0000FFFF # macro +PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK = 0xFFFF0000 # macro +PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT = 0x0 # macro +PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT = 0x1 # macro +PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT = 0x2 # macro +PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT = 0x3 # macro +PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT = 0x4 # macro +PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT = 0x5 # macro +PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT = 0x6 # macro +PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT = 0x7 # macro +PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT = 0x8 # macro +PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT = 0x9 # macro +PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT = 0xa # macro +PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT = 0xb # macro +PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT = 0xc # macro +PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT = 0xd # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT = 0xe # macro +PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT = 0xf # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT = 0x10 # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT = 0x11 # macro +PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT = 0x12 # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT = 0x13 # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT = 0x14 # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT = 0x15 # macro +PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT = 0x16 # macro +PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT = 0x17 # macro +PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT = 0x18 # macro +PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT = 0x19 # macro +PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT = 0x1a # macro +PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT = 0x1b # macro +PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT = 0x1c # macro +PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT = 0x1d # macro +PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK = 0x00000001 # macro +PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK = 0x00000002 # macro +PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK = 0x00000004 # macro +PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK = 0x00000008 # macro +PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK = 0x00000010 # macro +PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK = 0x00000020 # macro +PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK = 0x00000040 # macro +PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK = 0x00000080 # macro +PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK = 0x00000100 # macro +PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK = 0x00000200 # macro +PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK = 0x00000400 # macro +PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK = 0x00000800 # macro +PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK = 0x00001000 # macro +PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK = 0x00002000 # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK = 0x00004000 # macro +PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK = 0x00008000 # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK = 0x00010000 # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK = 0x00020000 # macro +PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK = 0x00040000 # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK = 0x00080000 # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK = 0x00100000 # macro +PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK = 0x00200000 # macro +PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK = 0x00400000 # macro +PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK = 0x00800000 # macro +PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK = 0x01000000 # macro +PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK = 0x02000000 # macro +PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK = 0x04000000 # macro +PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK = 0x08000000 # macro +PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK = 0x10000000 # macro +PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK = 0x20000000 # macro +PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT = 0x0 # macro +PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT = 0x1 # macro +PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT = 0x3 # macro +PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT = 0x4 # macro +PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT = 0x5 # macro +PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT = 0x6 # macro +PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT = 0x7 # macro +PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT = 0x8 # macro +PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT = 0x9 # macro +PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT = 0xa # macro +PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT = 0xb # macro +PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK__SHIFT = 0xc # macro +PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT = 0xd # macro +PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT = 0xe # macro +PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT = 0xf # macro +PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT = 0x10 # macro +PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT = 0x11 # macro +PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT = 0x12 # macro +PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT = 0x13 # macro +PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT = 0x14 # macro +PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT = 0x15 # macro +PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT = 0x16 # macro +PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT = 0x17 # macro +PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT = 0x18 # macro +PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT = 0x19 # macro +PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT = 0x1a # macro +PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT = 0x1b # macro +PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT = 0x1c # macro +PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT = 0x1d # macro +PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT = 0x1e # macro +PA_SC_ENHANCE_1__RSVD__SHIFT = 0x1f # macro +PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK = 0x00000001 # macro +PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK = 0x00000006 # macro +PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK = 0x00000008 # macro +PA_SC_ENHANCE_1__BYPASS_PBB_MASK = 0x00000010 # macro +PA_SC_ENHANCE_1__ECO_SPARE0_MASK = 0x00000020 # macro +PA_SC_ENHANCE_1__ECO_SPARE1_MASK = 0x00000040 # macro +PA_SC_ENHANCE_1__ECO_SPARE2_MASK = 0x00000080 # macro +PA_SC_ENHANCE_1__ECO_SPARE3_MASK = 0x00000100 # macro +PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK = 0x00000200 # macro +PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK = 0x00000400 # macro +PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK = 0x00000800 # macro +PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK_MASK = 0x00001000 # macro +PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK = 0x00002000 # macro +PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK = 0x00004000 # macro +PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK = 0x00008000 # macro +PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK = 0x00010000 # macro +PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK = 0x00020000 # macro +PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK = 0x00040000 # macro +PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK = 0x00080000 # macro +PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK = 0x00100000 # macro +PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK = 0x00200000 # macro +PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK = 0x00400000 # macro +PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK = 0x00800000 # macro +PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK = 0x01000000 # macro +PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK = 0x02000000 # macro +PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK = 0x04000000 # macro +PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK = 0x08000000 # macro +PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK = 0x10000000 # macro +PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK = 0x20000000 # macro +PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK = 0x40000000 # macro +PA_SC_ENHANCE_1__RSVD_MASK = 0x80000000 # macro +PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT = 0x0 # macro +PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT = 0x1 # macro +PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK = 0x00000001 # macro +PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK = 0x00000002 # macro +PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT = 0x0 # macro +PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT = 0x1 # macro +PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT = 0x5 # macro +PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK = 0x00000001 # macro +PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK = 0x00000006 # macro +PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK = 0x00000060 # macro +SQ_CONFIG__DISABLE_BARRIER_WAITCNT__SHIFT = 0x0 # macro +SQ_CONFIG__DISABLE_REPEATER_FGCG_CLOCK_GATING__SHIFT = 0x1 # macro +SQ_CONFIG__DISABLE_SPIPRIO_OVER_USERPRIO__SHIFT = 0x2 # macro +SQ_CONFIG__OVERRIDE_SP_MAI_ALU_BUSY__SHIFT = 0x3 # macro +SQ_CONFIG__DISABLE_RAM_CLOCK_GATING__SHIFT = 0x4 # macro +SQ_CONFIG__DISABLE_MAI_CO_EXEC__SHIFT = 0x5 # macro +SQ_CONFIG__OVERRIDE_MAI_ALU_BUSY__SHIFT = 0x6 # macro +SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT = 0x7 # macro +SQ_CONFIG__DEBUG_EN__SHIFT = 0x8 # macro +SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT = 0x9 # macro +SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT = 0xa # macro +SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT = 0xb # macro +SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT = 0xc # macro +SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT = 0xd # macro +SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT = 0xe # macro +SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT = 0xf # macro +SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT = 0x10 # macro +SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT = 0x11 # macro +SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT = 0x12 # macro +SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT = 0x13 # macro +SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT = 0x15 # macro +SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT = 0x1c # macro +SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT = 0x1d # macro +SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT = 0x1e # macro +SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT = 0x1f # macro +SQ_CONFIG__DISABLE_BARRIER_WAITCNT_MASK = 0x00000001 # macro +SQ_CONFIG__DISABLE_REPEATER_FGCG_CLOCK_GATING_MASK = 0x00000002 # macro +SQ_CONFIG__DISABLE_SPIPRIO_OVER_USERPRIO_MASK = 0x00000004 # macro +SQ_CONFIG__OVERRIDE_SP_MAI_ALU_BUSY_MASK = 0x00000008 # macro +SQ_CONFIG__DISABLE_RAM_CLOCK_GATING_MASK = 0x00000010 # macro +SQ_CONFIG__DISABLE_MAI_CO_EXEC_MASK = 0x00000020 # macro +SQ_CONFIG__OVERRIDE_MAI_ALU_BUSY_MASK = 0x00000040 # macro +SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK = 0x00000080 # macro +SQ_CONFIG__DEBUG_EN_MASK = 0x00000100 # macro +SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK = 0x00000200 # macro +SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK = 0x00000400 # macro +SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK = 0x00000800 # macro +SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK = 0x00001000 # macro +SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK = 0x00002000 # macro +SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK = 0x00004000 # macro +SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK = 0x00008000 # macro +SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK = 0x00010000 # macro +SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK = 0x00020000 # macro +SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK = 0x00040000 # macro +SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK = 0x00180000 # macro +SQ_CONFIG__REPLAY_SLEEP_CNT_MASK = 0x0FE00000 # macro +SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK = 0x10000000 # macro +SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK = 0x20000000 # macro +SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK = 0x40000000 # macro +SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK = 0x80000000 # macro +SQC_CONFIG__INST_CACHE_SIZE__SHIFT = 0x0 # macro +SQC_CONFIG__DATA_CACHE_SIZE__SHIFT = 0x2 # macro +SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT = 0x4 # macro +SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT = 0x6 # macro +SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT = 0x7 # macro +SQC_CONFIG__FORCE_IN_ORDER__SHIFT = 0x8 # macro +SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT = 0x9 # macro +SQC_CONFIG__IDENTITY_HASH_SET__SHIFT = 0xa # macro +SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT = 0xb # macro +SQC_CONFIG__EVICT_LRU__SHIFT = 0xc # macro +SQC_CONFIG__FORCE_2_BANK__SHIFT = 0xe # macro +SQC_CONFIG__FORCE_1_BANK__SHIFT = 0xf # macro +SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT = 0x10 # macro +SQC_CONFIG__INST_PRF_COUNT__SHIFT = 0x18 # macro +SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT = 0x1d # macro +SQC_CONFIG__DISABLE_PREFETCH_CROSS_4K_BOUNDARY_CHECK__SHIFT = 0x1e # macro +SQC_CONFIG__MEM_LS_DISABLE__SHIFT = 0x1f # macro +SQC_CONFIG__INST_CACHE_SIZE_MASK = 0x00000003 # macro +SQC_CONFIG__DATA_CACHE_SIZE_MASK = 0x0000000C # macro +SQC_CONFIG__MISS_FIFO_DEPTH_MASK = 0x00000030 # macro +SQC_CONFIG__HIT_FIFO_DEPTH_MASK = 0x00000040 # macro +SQC_CONFIG__FORCE_ALWAYS_MISS_MASK = 0x00000080 # macro +SQC_CONFIG__FORCE_IN_ORDER_MASK = 0x00000100 # macro +SQC_CONFIG__IDENTITY_HASH_BANK_MASK = 0x00000200 # macro +SQC_CONFIG__IDENTITY_HASH_SET_MASK = 0x00000400 # macro +SQC_CONFIG__PER_VMID_INV_DISABLE_MASK = 0x00000800 # macro +SQC_CONFIG__EVICT_LRU_MASK = 0x00003000 # macro +SQC_CONFIG__FORCE_2_BANK_MASK = 0x00004000 # macro +SQC_CONFIG__FORCE_1_BANK_MASK = 0x00008000 # macro +SQC_CONFIG__LS_DISABLE_CLOCKS_MASK = 0x00FF0000 # macro +SQC_CONFIG__INST_PRF_COUNT_MASK = 0x1F000000 # macro +SQC_CONFIG__INST_PRF_FILTER_DIS_MASK = 0x20000000 # macro +SQC_CONFIG__DISABLE_PREFETCH_CROSS_4K_BOUNDARY_CHECK_MASK = 0x40000000 # macro +SQC_CONFIG__MEM_LS_DISABLE_MASK = 0x80000000 # macro +LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT = 0x0 # macro +LDS_CONFIG__TMZ_VIOLATION_REPORTING__SHIFT = 0x1 # macro +LDS_CONFIG__DISABLE_RAM_CLOCK_GATING__SHIFT = 0x2 # macro +LDS_CONFIG__DISABLE_IDXCLK_MGCG__SHIFT = 0x3 # macro +LDS_CONFIG__DISABLE_MEMCLK_MGCG__SHIFT = 0x4 # macro +LDS_CONFIG__DISABLE_ATTRCLK_MGCG__SHIFT = 0x5 # macro +LDS_CONFIG__DISABLE_ATODFPCLK_MGCG__SHIFT = 0x6 # macro +LDS_CONFIG__DISABLE_PHASE_FGCG__SHIFT = 0x7 # macro +LDS_CONFIG__DISABLE_LDS_SP_READ_FGCG__SHIFT = 0x8 # macro +LDS_CONFIG__DISABLE_SP_DATA_CLOCK_GATING__SHIFT = 0x9 # macro +LDS_CONFIG__DISABLE_TD_DATA_CLOCK_GATING__SHIFT = 0xa # macro +LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK = 0x00000001 # macro +LDS_CONFIG__TMZ_VIOLATION_REPORTING_MASK = 0x00000002 # macro +LDS_CONFIG__DISABLE_RAM_CLOCK_GATING_MASK = 0x00000004 # macro +LDS_CONFIG__DISABLE_IDXCLK_MGCG_MASK = 0x00000008 # macro +LDS_CONFIG__DISABLE_MEMCLK_MGCG_MASK = 0x00000010 # macro +LDS_CONFIG__DISABLE_ATTRCLK_MGCG_MASK = 0x00000020 # macro +LDS_CONFIG__DISABLE_ATODFPCLK_MGCG_MASK = 0x00000040 # macro +LDS_CONFIG__DISABLE_PHASE_FGCG_MASK = 0x00000080 # macro +LDS_CONFIG__DISABLE_LDS_SP_READ_FGCG_MASK = 0x00000100 # macro +LDS_CONFIG__DISABLE_SP_DATA_CLOCK_GATING_MASK = 0x00000200 # macro +LDS_CONFIG__DISABLE_TD_DATA_CLOCK_GATING_MASK = 0x00000400 # macro +SQ_RANDOM_WAVE_PRI__RET__SHIFT = 0x0 # macro +SQ_RANDOM_WAVE_PRI__RUI__SHIFT = 0x7 # macro +SQ_RANDOM_WAVE_PRI__RNG__SHIFT = 0xa # macro +SQ_RANDOM_WAVE_PRI__RET_MASK = 0x0000007F # macro +SQ_RANDOM_WAVE_PRI__RUI_MASK = 0x00000380 # macro +SQ_RANDOM_WAVE_PRI__RNG_MASK = 0x007FFC00 # macro +SQ_REG_CREDITS__SRBM_CREDITS__SHIFT = 0x0 # macro +SQ_REG_CREDITS__CMD_CREDITS__SHIFT = 0x8 # macro +SQ_REG_CREDITS__REG_BUSY__SHIFT = 0x1c # macro +SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT = 0x1d # macro +SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT = 0x1e # macro +SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT = 0x1f # macro +SQ_REG_CREDITS__SRBM_CREDITS_MASK = 0x0000003F # macro +SQ_REG_CREDITS__CMD_CREDITS_MASK = 0x00000F00 # macro +SQ_REG_CREDITS__REG_BUSY_MASK = 0x10000000 # macro +SQ_REG_CREDITS__SRBM_OVERFLOW_MASK = 0x20000000 # macro +SQ_REG_CREDITS__IMMED_OVERFLOW_MASK = 0x40000000 # macro +SQ_REG_CREDITS__CMD_OVERFLOW_MASK = 0x80000000 # macro +SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT = 0x0 # macro +SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT = 0x8 # macro +SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT = 0x10 # macro +SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT = 0x12 # macro +SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK = 0x0000000F # macro +SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK = 0x00000F00 # macro +SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK = 0x00030000 # macro +SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK = 0x000C0000 # macro +SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT = 0x0 # macro +SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT = 0x1 # macro +SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT = 0x2 # macro +SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT = 0x3 # macro +SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT = 0x8 # macro +SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT = 0x9 # macro +SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT = 0xa # macro +SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT = 0x10 # macro +SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT = 0x11 # macro +SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT = 0x12 # macro +SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT = 0x13 # macro +SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT = 0x14 # macro +SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT = 0x15 # macro +SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT = 0x18 # macro +SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT = 0x19 # macro +SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT = 0x1a # macro +SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK = 0x00000001 # macro +SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK = 0x00000002 # macro +SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK = 0x00000004 # macro +SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK = 0x00000008 # macro +SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK = 0x00000100 # macro +SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK = 0x00000200 # macro +SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK = 0x00000400 # macro +SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK = 0x00010000 # macro +SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK = 0x00020000 # macro +SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK = 0x00040000 # macro +SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK = 0x00080000 # macro +SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK = 0x00100000 # macro +SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK = 0x00200000 # macro +SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK = 0x01000000 # macro +SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK = 0x02000000 # macro +SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK = 0x04000000 # macro +SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT = 0x6 # macro +SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT = 0x8 # macro +SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT = 0xb # macro +SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT = 0xe # macro +SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT = 0x14 # macro +SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT = 0x1a # macro +SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK = 0x000000C0 # macro +SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK = 0x00000100 # macro +SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK = 0x000FC000 # macro +SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK = 0x03F00000 # macro +SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK = 0xFC000000 # macro +SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT = 0x0 # macro +SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK = 0x00000001 # macro +SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT = 0x0 # macro +SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT = 0x1 # macro +SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT = 0x4 # macro +SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT = 0x10 # macro +SQ_DEBUG_STS_GLOBAL__BUSY_MASK = 0x00000001 # macro +SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK = 0x00000002 # macro +SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK = 0x0000FFF0 # macro +SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK = 0x0FFF0000 # macro +SH_MEM_BASES__PRIVATE_BASE__SHIFT = 0x0 # macro +SH_MEM_BASES__SHARED_BASE__SHIFT = 0x10 # macro +SH_MEM_BASES__PRIVATE_BASE_MASK = 0x0000FFFF # macro +SH_MEM_BASES__SHARED_BASE_MASK = 0xFFFF0000 # macro +SQ_TIMEOUT_CONFIG__PERIOD_SEL__SHIFT = 0x0 # macro +SQ_TIMEOUT_CONFIG__TIMEOUT_FATAL_DISABLE__SHIFT = 0x6 # macro +SQ_TIMEOUT_CONFIG__TIMER_LONGER_SEL__SHIFT = 0x7 # macro +SQ_TIMEOUT_CONFIG__TIMEOUT_CONDITIONS_MASK__SHIFT = 0x8 # macro +SQ_TIMEOUT_CONFIG__PERIOD_SEL_MASK = 0x0000003F # macro +SQ_TIMEOUT_CONFIG__TIMEOUT_FATAL_DISABLE_MASK = 0x00000040 # macro +SQ_TIMEOUT_CONFIG__TIMER_LONGER_SEL_MASK = 0x00000080 # macro +SQ_TIMEOUT_CONFIG__TIMEOUT_CONDITIONS_MASK_MASK = 0x07FFFF00 # macro +SQ_TIMEOUT_STATUS__WAVE_TIMEOUT__SHIFT = 0x0 # macro +SQ_TIMEOUT_STATUS__WAVE_TIMEOUT_MASK = 0xFFFFFFFF # macro +SH_MEM_CONFIG__ADDRESS_MODE__SHIFT = 0x0 # macro +SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT = 0x3 # macro +SH_MEM_CONFIG__F8_MODE__SHIFT = 0x8 # macro +SH_MEM_CONFIG__RETRY_DISABLE__SHIFT = 0xc # macro +SH_MEM_CONFIG__PRIVATE_NV__SHIFT = 0xd # macro +SH_MEM_CONFIG__ADDRESS_MODE_MASK = 0x00000001 # macro +SH_MEM_CONFIG__ALIGNMENT_MODE_MASK = 0x00000018 # macro +SH_MEM_CONFIG__F8_MODE_MASK = 0x00000100 # macro +SH_MEM_CONFIG__RETRY_DISABLE_MASK = 0x00001000 # macro +SH_MEM_CONFIG__PRIVATE_NV_MASK = 0x00002000 # macro +SP_MFMA_PORTD_RD_CONFIG__SET__SHIFT = 0x0 # macro +SP_MFMA_PORTD_RD_CONFIG__TYPE__SHIFT = 0x1 # macro +SP_MFMA_PORTD_RD_CONFIG__LAST_PASS__SHIFT = 0x4 # macro +SP_MFMA_PORTD_RD_CONFIG__PORTD_PATTERN__SHIFT = 0x9 # macro +SP_MFMA_PORTD_RD_CONFIG__SET_MASK = 0x00000001 # macro +SP_MFMA_PORTD_RD_CONFIG__TYPE_MASK = 0x0000000E # macro +SP_MFMA_PORTD_RD_CONFIG__LAST_PASS_MASK = 0x000001F0 # macro +SP_MFMA_PORTD_RD_CONFIG__PORTD_PATTERN_MASK = 0x1FFFFE00 # macro +SH_CAC_CONFIG__SQG_UTCL1_REPEATER_FGCG_DISABLE__SHIFT = 0x0 # macro +SH_CAC_CONFIG__SQC_UTCL1_REPEATER_FGCG_DISABLE__SHIFT = 0x1 # macro +SH_CAC_CONFIG__SPI_SQ_CMD_REPEATER_FGCG_DISABLE__SHIFT = 0x2 # macro +SH_CAC_CONFIG__SQ_MSG_REPEATER_FGCG_DISABLE__SHIFT = 0x3 # macro +SH_CAC_CONFIG__SQC_TC_REPEATER_FGCG_DISABLE__SHIFT = 0x4 # macro +SH_CAC_CONFIG__SQC_SQ_REPEATER_FGCG_DISABLE__SHIFT = 0x5 # macro +SH_CAC_CONFIG__SQG_TC_REPEATER_FGCG_DISABLE__SHIFT = 0x6 # macro +SH_CAC_CONFIG__SQC_DISABLE_RAM_CLOCK_GATING__SHIFT = 0x8 # macro +SH_CAC_CONFIG__SQG_DISABLE_RAM_CLOCK_GATING__SHIFT = 0x9 # macro +SH_CAC_CONFIG__SQC_MGCG_CLOCK_OFF_DELAY_CNT__SHIFT = 0x10 # macro +SH_CAC_CONFIG__SQC_MGCG_DISABLE__SHIFT = 0x14 # macro +SH_CAC_CONFIG__SQC_TC_REQ_CLKEN_CHICKENBIT__SHIFT = 0x1c # macro +SH_CAC_CONFIG__SQC_ICACHE_CTRL_MGCG_DISABLE__SHIFT = 0x1d # macro +SH_CAC_CONFIG__SQC_DCACHE_CTRL_MGCG_DISABLE__SHIFT = 0x1e # macro +SH_CAC_CONFIG__SQC_DISABLE_UTCL1_FGCG_PADDR__SHIFT = 0x1f # macro +SH_CAC_CONFIG__SQG_UTCL1_REPEATER_FGCG_DISABLE_MASK = 0x00000001 # macro +SH_CAC_CONFIG__SQC_UTCL1_REPEATER_FGCG_DISABLE_MASK = 0x00000002 # macro +SH_CAC_CONFIG__SPI_SQ_CMD_REPEATER_FGCG_DISABLE_MASK = 0x00000004 # macro +SH_CAC_CONFIG__SQ_MSG_REPEATER_FGCG_DISABLE_MASK = 0x00000008 # macro +SH_CAC_CONFIG__SQC_TC_REPEATER_FGCG_DISABLE_MASK = 0x00000010 # macro +SH_CAC_CONFIG__SQC_SQ_REPEATER_FGCG_DISABLE_MASK = 0x00000020 # macro +SH_CAC_CONFIG__SQG_TC_REPEATER_FGCG_DISABLE_MASK = 0x00000040 # macro +SH_CAC_CONFIG__SQC_DISABLE_RAM_CLOCK_GATING_MASK = 0x00000100 # macro +SH_CAC_CONFIG__SQG_DISABLE_RAM_CLOCK_GATING_MASK = 0x00000200 # macro +SH_CAC_CONFIG__SQC_MGCG_CLOCK_OFF_DELAY_CNT_MASK = 0x000F0000 # macro +SH_CAC_CONFIG__SQC_MGCG_DISABLE_MASK = 0x0FF00000 # macro +SH_CAC_CONFIG__SQC_TC_REQ_CLKEN_CHICKENBIT_MASK = 0x10000000 # macro +SH_CAC_CONFIG__SQC_ICACHE_CTRL_MGCG_DISABLE_MASK = 0x20000000 # macro +SH_CAC_CONFIG__SQC_DCACHE_CTRL_MGCG_DISABLE_MASK = 0x40000000 # macro +SH_CAC_CONFIG__SQC_DISABLE_UTCL1_FGCG_PADDR_MASK = 0x80000000 # macro +SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT = 0x0 # macro +SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT = 0x8 # macro +SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT = 0x10 # macro +SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT = 0x18 # macro +SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK = 0x000000FF # macro +SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK = 0x0000FF00 # macro +SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK = 0x00FF0000 # macro +SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK = 0xFF000000 # macro +SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT = 0x0 # macro +SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT = 0x4 # macro +SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK = 0x0000000F # macro +SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK = 0x000003F0 # macro +CC_GC_SHADER_RATE_CONFIG__WRITE_DIS__SHIFT = 0x0 # macro +CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT = 0x1 # macro +CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT = 0x3 # macro +CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT = 0x4 # macro +CC_GC_SHADER_RATE_CONFIG__WRITE_DIS_MASK = 0x00000001 # macro +CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK = 0x00000006 # macro +CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK = 0x00000008 # macro +CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK = 0x00000010 # macro +GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT = 0x1 # macro +GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT = 0x3 # macro +GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT = 0x4 # macro +GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK = 0x00000006 # macro +GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK = 0x00000008 # macro +GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK = 0x00000010 # macro +SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT = 0x0 # macro +SQ_INTERRUPT_AUTO_MASK__MASK_MASK = 0x00FFFFFF # macro +SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT = 0x0 # macro +SQ_INTERRUPT_MSG_CTRL__STALL_MASK = 0x00000001 # macro +SQ_DEBUG_PERFCOUNT_TRAP__ENABLE__SHIFT = 0x0 # macro +SQ_DEBUG_PERFCOUNT_TRAP__COUNTER__SHIFT = 0x1 # macro +SQ_DEBUG_PERFCOUNT_TRAP__LIMIT__SHIFT = 0x4 # macro +SQ_DEBUG_PERFCOUNT_TRAP__ENABLE_MASK = 0x00000001 # macro +SQ_DEBUG_PERFCOUNT_TRAP__COUNTER_MASK = 0x0000000E # macro +SQ_DEBUG_PERFCOUNT_TRAP__LIMIT_MASK = 0x0FFFFFF0 # macro +SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT = 0x0 # macro +SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT = 0x1 # macro +SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT = 0x2 # macro +SQ_UTCL1_CNTL1__RESP_MODE__SHIFT = 0x3 # macro +SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT = 0x5 # macro +SQ_UTCL1_CNTL1__CLIENTID__SHIFT = 0x7 # macro +SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT = 0x10 # macro +SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT = 0x11 # macro +SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT = 0x12 # macro +SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT = 0x13 # macro +SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT = 0x17 # macro +SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT = 0x18 # macro +SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT = 0x19 # macro +SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT = 0x1a # macro +SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT = 0x1b # macro +SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT = 0x1c # macro +SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT = 0x1e # macro +SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK = 0x00000001 # macro +SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK = 0x00000002 # macro +SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK = 0x00000004 # macro +SQ_UTCL1_CNTL1__RESP_MODE_MASK = 0x00000018 # macro +SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK = 0x00000060 # macro +SQ_UTCL1_CNTL1__CLIENTID_MASK = 0x0000FF80 # macro +SQ_UTCL1_CNTL1__USERVM_DIS_MASK = 0x00010000 # macro +SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK = 0x00020000 # macro +SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK = 0x00040000 # macro +SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK = 0x00780000 # macro +SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK = 0x00800000 # macro +SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK = 0x01000000 # macro +SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK = 0x02000000 # macro +SQ_UTCL1_CNTL1__FORCE_MISS_MASK = 0x04000000 # macro +SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK = 0x08000000 # macro +SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK = 0x30000000 # macro +SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK = 0xC0000000 # macro +SQ_UTCL1_CNTL2__SPARE__SHIFT = 0x0 # macro +SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT = 0x8 # macro +SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT = 0x9 # macro +SQ_UTCL1_CNTL2__LINE_VALID__SHIFT = 0xa # macro +SQ_UTCL1_CNTL2__DIS_EDC__SHIFT = 0xb # macro +SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT = 0xc # macro +SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT = 0xd # macro +SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT = 0xe # macro +SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT = 0xf # macro +SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT = 0x10 # macro +SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT = 0x1a # macro +SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT = 0x1c # macro +SQ_UTCL1_CNTL2__SPARE_MASK = 0x000000FF # macro +SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK = 0x00000100 # macro +SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK = 0x00000200 # macro +SQ_UTCL1_CNTL2__LINE_VALID_MASK = 0x00000400 # macro +SQ_UTCL1_CNTL2__DIS_EDC_MASK = 0x00000800 # macro +SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK = 0x00001000 # macro +SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK = 0x00002000 # macro +SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK = 0x00004000 # macro +SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK = 0x00008000 # macro +SQ_UTCL1_CNTL2__RETRY_TIMER_MASK = 0x007F0000 # macro +SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK = 0x04000000 # macro +SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK = 0xF0000000 # macro +SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT = 0x0 # macro +SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT = 0x1 # macro +SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT = 0x2 # macro +SQ_UTCL1_STATUS__RESERVED__SHIFT = 0x3 # macro +SQ_UTCL1_STATUS__UNUSED__SHIFT = 0x10 # macro +SQ_UTCL1_STATUS__FAULT_DETECTED_MASK = 0x00000001 # macro +SQ_UTCL1_STATUS__RETRY_DETECTED_MASK = 0x00000002 # macro +SQ_UTCL1_STATUS__PRT_DETECTED_MASK = 0x00000004 # macro +SQ_UTCL1_STATUS__RESERVED_MASK = 0x0000FFF8 # macro +SQ_UTCL1_STATUS__UNUSED_MASK = 0xFFFF0000 # macro +SQ_FED_INTERRUPT_STATUS__INTERRUPT_STATUS__SHIFT = 0x0 # macro +SQ_FED_INTERRUPT_STATUS__INTERRUPT_SIMD_ID__SHIFT = 0x2 # macro +SQ_FED_INTERRUPT_STATUS__INTERRUPT_WAVE_ID__SHIFT = 0x4 # macro +SQ_FED_INTERRUPT_STATUS__INTERRUPT_CU_ID__SHIFT = 0x8 # macro +SQ_FED_INTERRUPT_STATUS__INTERRUPT_VM_ID__SHIFT = 0xc # macro +SQ_FED_INTERRUPT_STATUS__TO_RSMU_DISABLE__SHIFT = 0x10 # macro +SQ_FED_INTERRUPT_STATUS__TO_IH_DISABLE__SHIFT = 0x11 # macro +SQ_FED_INTERRUPT_STATUS__FED_HALT_DISABLE__SHIFT = 0x12 # macro +SQ_FED_INTERRUPT_STATUS__INTERRUPT_STATUS_MASK = 0x00000001 # macro +SQ_FED_INTERRUPT_STATUS__INTERRUPT_SIMD_ID_MASK = 0x0000000C # macro +SQ_FED_INTERRUPT_STATUS__INTERRUPT_WAVE_ID_MASK = 0x000000F0 # macro +SQ_FED_INTERRUPT_STATUS__INTERRUPT_CU_ID_MASK = 0x00000F00 # macro +SQ_FED_INTERRUPT_STATUS__INTERRUPT_VM_ID_MASK = 0x0000F000 # macro +SQ_FED_INTERRUPT_STATUS__TO_RSMU_DISABLE_MASK = 0x00010000 # macro +SQ_FED_INTERRUPT_STATUS__TO_IH_DISABLE_MASK = 0x00020000 # macro +SQ_FED_INTERRUPT_STATUS__FED_HALT_DISABLE_MASK = 0x00040000 # macro +SQ_CGTS_CONFIG__DGEMM_EXTRA_BUSY_PASS__SHIFT = 0x0 # macro +SQ_CGTS_CONFIG__XDL_EXTRA_BUSY_PASS__SHIFT = 0x4 # macro +SQ_CGTS_CONFIG__VALU_EXTRA_BUSY_PASS__SHIFT = 0x8 # macro +SQ_CGTS_CONFIG__DLOP_EXTRA_BUSY_PASS__SHIFT = 0xc # macro +SQ_CGTS_CONFIG__XDL_EXTRA_GAP_PASS__SHIFT = 0x10 # macro +SQ_CGTS_CONFIG__DGEMM_EXTRA_GAP_PASS__SHIFT = 0x12 # macro +SQ_CGTS_CONFIG__DLOP_EXTRA_GAP_PASS__SHIFT = 0x14 # macro +SQ_CGTS_CONFIG__DGEMM_EXTRA_BUSY_PASS_MASK = 0x0000000F # macro +SQ_CGTS_CONFIG__XDL_EXTRA_BUSY_PASS_MASK = 0x000000F0 # macro +SQ_CGTS_CONFIG__VALU_EXTRA_BUSY_PASS_MASK = 0x00000F00 # macro +SQ_CGTS_CONFIG__DLOP_EXTRA_BUSY_PASS_MASK = 0x0000F000 # macro +SQ_CGTS_CONFIG__XDL_EXTRA_GAP_PASS_MASK = 0x00030000 # macro +SQ_CGTS_CONFIG__DGEMM_EXTRA_GAP_PASS_MASK = 0x000C0000 # macro +SQ_CGTS_CONFIG__DLOP_EXTRA_GAP_PASS_MASK = 0x00300000 # macro +SQ_SHADER_TBA_LO__ADDR_LO__SHIFT = 0x0 # macro +SQ_SHADER_TBA_LO__ADDR_LO_MASK = 0xFFFFFFFF # macro +SQ_SHADER_TBA_HI__ADDR_HI__SHIFT = 0x0 # macro +SQ_SHADER_TBA_HI__ADDR_HI_MASK = 0x000000FF # macro +SQ_SHADER_TMA_LO__ADDR_LO__SHIFT = 0x0 # macro +SQ_SHADER_TMA_LO__ADDR_LO_MASK = 0xFFFFFFFF # macro +SQ_SHADER_TMA_HI__ADDR_HI__SHIFT = 0x0 # macro +SQ_SHADER_TMA_HI__ADDR_HI_MASK = 0x000000FF # macro +SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT = 0x0 # macro +SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT = 0x2 # macro +SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT = 0x3 # macro +SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT = 0x5 # macro +SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT = 0x6 # macro +SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT = 0x8 # macro +SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT = 0x9 # macro +SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT = 0xb # macro +SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT = 0xc # macro +SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT = 0xe # macro +SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT = 0xf # macro +SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT = 0x11 # macro +SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT = 0x12 # macro +SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT = 0x14 # macro +SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT = 0x15 # macro +SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT = 0x17 # macro +SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT = 0x18 # macro +SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT = 0x1a # macro +SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK = 0x00000003 # macro +SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK = 0x00000004 # macro +SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK = 0x00000018 # macro +SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK = 0x00000020 # macro +SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK = 0x000000C0 # macro +SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK = 0x00000100 # macro +SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK = 0x00000600 # macro +SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK = 0x00000800 # macro +SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK = 0x00003000 # macro +SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK = 0x00004000 # macro +SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK = 0x00018000 # macro +SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK = 0x00020000 # macro +SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK = 0x000C0000 # macro +SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK = 0x00100000 # macro +SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK = 0x00600000 # macro +SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK = 0x00800000 # macro +SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK = 0x03000000 # macro +SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK = 0x04000000 # macro +SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT = 0x0 # macro +SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT = 0x2 # macro +SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT = 0x3 # macro +SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT = 0x5 # macro +SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT = 0x6 # macro +SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT = 0x8 # macro +SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT = 0x9 # macro +SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT = 0xb # macro +SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT = 0xc # macro +SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT = 0xe # macro +SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT = 0xf # macro +SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT = 0x11 # macro +SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT = 0x12 # macro +SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT = 0x14 # macro +SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT = 0x15 # macro +SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT = 0x17 # macro +SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT = 0x18 # macro +SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT = 0x1a # macro +SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK = 0x00000003 # macro +SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK = 0x00000004 # macro +SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK = 0x00000018 # macro +SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK = 0x00000020 # macro +SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK = 0x000000C0 # macro +SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK = 0x00000100 # macro +SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK = 0x00000600 # macro +SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK = 0x00000800 # macro +SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK = 0x00003000 # macro +SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK = 0x00004000 # macro +SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK = 0x00018000 # macro +SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK = 0x00020000 # macro +SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK = 0x000C0000 # macro +SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK = 0x00100000 # macro +SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK = 0x00600000 # macro +SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK = 0x00800000 # macro +SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK = 0x03000000 # macro +SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK = 0x04000000 # macro +SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT = 0x0 # macro +SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT = 0x2 # macro +SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT = 0x3 # macro +SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT = 0x5 # macro +SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT = 0x6 # macro +SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT = 0x8 # macro +SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT = 0x9 # macro +SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT = 0xb # macro +SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT = 0xc # macro +SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT = 0xe # macro +SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT = 0xf # macro +SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT = 0x11 # macro +SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT = 0x12 # macro +SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT = 0x14 # macro +SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT = 0x15 # macro +SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT = 0x17 # macro +SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT = 0x18 # macro +SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT = 0x1a # macro +SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK = 0x00000003 # macro +SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK = 0x00000004 # macro +SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK = 0x00000018 # macro +SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK = 0x00000020 # macro +SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK = 0x000000C0 # macro +SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK = 0x00000100 # macro +SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK = 0x00000600 # macro +SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK = 0x00000800 # macro +SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK = 0x00003000 # macro +SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK = 0x00004000 # macro +SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK = 0x00018000 # macro +SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK = 0x00020000 # macro +SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK = 0x000C0000 # macro +SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK = 0x00100000 # macro +SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK = 0x00600000 # macro +SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK = 0x00800000 # macro +SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK = 0x03000000 # macro +SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK = 0x04000000 # macro +SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT = 0x6 # macro +SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT = 0x8 # macro +SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT = 0xb # macro +SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT = 0xc # macro +SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT = 0xe # macro +SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT = 0xf # macro +SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT = 0x11 # macro +SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT = 0x12 # macro +SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT = 0x14 # macro +SQC_DSM_CNTL2__INJECT_DELAY__SHIFT = 0x1a # macro +SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK = 0x000000C0 # macro +SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK = 0x00000100 # macro +SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK = 0x00003000 # macro +SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK = 0x00004000 # macro +SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK = 0x00018000 # macro +SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK = 0x00020000 # macro +SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK = 0x000C0000 # macro +SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK = 0x00100000 # macro +SQC_DSM_CNTL2__INJECT_DELAY_MASK = 0xFC000000 # macro +SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT = 0x6 # macro +SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT = 0x8 # macro +SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT = 0xb # macro +SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT = 0xc # macro +SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT = 0xe # macro +SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT = 0xf # macro +SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT = 0x11 # macro +SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT = 0x12 # macro +SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT = 0x14 # macro +SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x15 # macro +SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT = 0x17 # macro +SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x18 # macro +SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT = 0x1a # macro +SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK = 0x000000C0 # macro +SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK = 0x00000100 # macro +SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK = 0x00003000 # macro +SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK = 0x00004000 # macro +SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK = 0x00018000 # macro +SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK = 0x00020000 # macro +SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK = 0x000C0000 # macro +SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK = 0x00100000 # macro +SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK = 0x00600000 # macro +SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK = 0x00800000 # macro +SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK = 0x03000000 # macro +SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK = 0x04000000 # macro +SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT = 0x6 # macro +SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT = 0x8 # macro +SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT = 0xb # macro +SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT = 0xc # macro +SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT = 0xe # macro +SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT = 0xf # macro +SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT = 0x11 # macro +SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT = 0x12 # macro +SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT = 0x14 # macro +SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x15 # macro +SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT = 0x17 # macro +SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x18 # macro +SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT = 0x1a # macro +SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK = 0x000000C0 # macro +SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK = 0x00000100 # macro +SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK = 0x00003000 # macro +SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK = 0x00004000 # macro +SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK = 0x00018000 # macro +SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK = 0x00020000 # macro +SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK = 0x000C0000 # macro +SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK = 0x00100000 # macro +SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK = 0x00600000 # macro +SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK = 0x00800000 # macro +SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK = 0x03000000 # macro +SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK = 0x04000000 # macro +SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT = 0x0 # macro +SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT = 0x10 # macro +SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK = 0x0000FFFF # macro +SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK = 0xFFFF0000 # macro +SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT = 0x0 # macro +SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT = 0x2 # macro +SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT = 0x4 # macro +SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT = 0x6 # macro +SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT = 0x8 # macro +SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT = 0xa # macro +SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT = 0xc # macro +SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT = 0xe # macro +SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT = 0x10 # macro +SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT = 0x12 # macro +SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SEC_COUNT__SHIFT = 0x14 # macro +SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_DED_COUNT__SHIFT = 0x16 # macro +SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK = 0x00000003 # macro +SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK = 0x0000000C # macro +SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK = 0x00000030 # macro +SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK = 0x000000C0 # macro +SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK = 0x00000300 # macro +SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK = 0x00000C00 # macro +SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK = 0x00003000 # macro +SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK = 0x0000C000 # macro +SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK = 0x00030000 # macro +SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK = 0x000C0000 # macro +SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SEC_COUNT_MASK = 0x00300000 # macro +SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_DED_COUNT_MASK = 0x00C00000 # macro +SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT = 0x0 # macro +SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT = 0x2 # macro +SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT = 0x4 # macro +SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT = 0x6 # macro +SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT = 0x8 # macro +SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT = 0xa # macro +SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT = 0xc # macro +SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT = 0xe # macro +SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SEC_COUNT__SHIFT = 0x10 # macro +SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_DED_COUNT__SHIFT = 0x12 # macro +SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK = 0x00000003 # macro +SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK = 0x0000000C # macro +SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK = 0x00000030 # macro +SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK = 0x000000C0 # macro +SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK = 0x00000300 # macro +SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK = 0x00000C00 # macro +SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK = 0x00003000 # macro +SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK = 0x0000C000 # macro +SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SEC_COUNT_MASK = 0x00030000 # macro +SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_DED_COUNT_MASK = 0x000C0000 # macro +SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT__SHIFT = 0x0 # macro +SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT__SHIFT = 0x2 # macro +SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_SEC_COUNT__SHIFT = 0x4 # macro +SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_DED_COUNT__SHIFT = 0x6 # macro +SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_SEC_COUNT__SHIFT = 0x8 # macro +SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_DED_COUNT__SHIFT = 0xa # macro +SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_SEC_COUNT__SHIFT = 0xc # macro +SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_DED_COUNT__SHIFT = 0xe # macro +SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT__SHIFT = 0x10 # macro +SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT__SHIFT = 0x12 # macro +SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT__SHIFT = 0x14 # macro +SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_DED_COUNT__SHIFT = 0x16 # macro +SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_SEC_COUNT__SHIFT = 0x18 # macro +SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_DED_COUNT__SHIFT = 0x1a # macro +SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_SEC_COUNT__SHIFT = 0x1c # macro +SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_DED_COUNT__SHIFT = 0x1e # macro +SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT_MASK = 0x00000003 # macro +SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT_MASK = 0x0000000C # macro +SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_SEC_COUNT_MASK = 0x00000030 # macro +SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_DED_COUNT_MASK = 0x000000C0 # macro +SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_SEC_COUNT_MASK = 0x00000300 # macro +SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_DED_COUNT_MASK = 0x00000C00 # macro +SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_SEC_COUNT_MASK = 0x00003000 # macro +SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_DED_COUNT_MASK = 0x0000C000 # macro +SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT_MASK = 0x00030000 # macro +SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT_MASK = 0x000C0000 # macro +SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT_MASK = 0x00300000 # macro +SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_DED_COUNT_MASK = 0x00C00000 # macro +SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_SEC_COUNT_MASK = 0x03000000 # macro +SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_DED_COUNT_MASK = 0x0C000000 # macro +SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_SEC_COUNT_MASK = 0x30000000 # macro +SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_DED_COUNT_MASK = 0xC0000000 # macro +SQ_DEBUG__SINGLE_MEMOP__SHIFT = 0x0 # macro +SQ_DEBUG__SINGLE_ALU_OP__SHIFT = 0x1 # macro +SQ_DEBUG__SINGLE_MEMOP_MASK = 0x00000001 # macro +SQ_DEBUG__SINGLE_ALU_OP_MASK = 0x00000002 # macro +SQ_PERF_SNAPSHOT_CTRL__COUNT_INTVAL__SHIFT = 0x0 # macro +SQ_PERF_SNAPSHOT_CTRL__COUNT_SEL__SHIFT = 0x5 # macro +SQ_PERF_SNAPSHOT_CTRL__VMID_MASK__SHIFT = 0x6 # macro +SQ_PERF_SNAPSHOT_CTRL__ENABLE__SHIFT = 0x16 # macro +SQ_PERF_SNAPSHOT_CTRL__TEST_MODE__SHIFT = 0x17 # macro +SQ_PERF_SNAPSHOT_CTRL__COUNT_INTVAL_MASK = 0x0000001F # macro +SQ_PERF_SNAPSHOT_CTRL__COUNT_SEL_MASK = 0x00000020 # macro +SQ_PERF_SNAPSHOT_CTRL__VMID_MASK_MASK = 0x003FFFC0 # macro +SQ_PERF_SNAPSHOT_CTRL__ENABLE_MASK = 0x00400000 # macro +SQ_PERF_SNAPSHOT_CTRL__TEST_MODE_MASK = 0x00800000 # macro +SQ_DEBUG_FOR_INTERNAL_CTRL__FLAG_WR_ADDR_MATCH_FLAT_SCRATCH__SHIFT = 0x0 # macro +SQ_DEBUG_FOR_INTERNAL_CTRL__FLAG_RD_FLAT_SCRATCH_RETURN_ZERO__SHIFT = 0x1 # macro +SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_FLAT_SCRATCH_WRITE_PROTECT__SHIFT = 0x2 # macro +SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_FLAT_SCRATCH_READ_PROTECT__SHIFT = 0x3 # macro +SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_SNAPSHOT_TRAP_ON_BARRIER__SHIFT = 0x4 # macro +SQ_DEBUG_FOR_INTERNAL_CTRL__ENABLE_DED_TRIGGER_HALT__SHIFT = 0x5 # macro +SQ_DEBUG_FOR_INTERNAL_CTRL__FLAG_WR_ADDR_MATCH_FLAT_SCRATCH_MASK = 0x00000001 # macro +SQ_DEBUG_FOR_INTERNAL_CTRL__FLAG_RD_FLAT_SCRATCH_RETURN_ZERO_MASK = 0x00000002 # macro +SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_FLAT_SCRATCH_WRITE_PROTECT_MASK = 0x00000004 # macro +SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_FLAT_SCRATCH_READ_PROTECT_MASK = 0x00000008 # macro +SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_SNAPSHOT_TRAP_ON_BARRIER_MASK = 0x00000010 # macro +SQ_DEBUG_FOR_INTERNAL_CTRL__ENABLE_DED_TRIGGER_HALT_MASK = 0x00000020 # macro +SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT = 0x0 # macro +SQ_REG_TIMESTAMP__TIMESTAMP_MASK = 0x000000FF # macro +SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT = 0x0 # macro +SQ_CMD_TIMESTAMP__TIMESTAMP_MASK = 0x000000FF # macro +SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT__SHIFT = 0x0 # macro +SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE__SHIFT = 0x8 # macro +SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT_MASK = 0x000000FF # macro +SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE_MASK = 0x00000100 # macro +SQ_IND_INDEX__WAVE_ID__SHIFT = 0x0 # macro +SQ_IND_INDEX__SIMD_ID__SHIFT = 0x4 # macro +SQ_IND_INDEX__THREAD_ID__SHIFT = 0x6 # macro +SQ_IND_INDEX__AUTO_INCR__SHIFT = 0xc # macro +SQ_IND_INDEX__FORCE_READ__SHIFT = 0xd # macro +SQ_IND_INDEX__READ_TIMEOUT__SHIFT = 0xe # macro +SQ_IND_INDEX__UNINDEXED__SHIFT = 0xf # macro +SQ_IND_INDEX__INDEX__SHIFT = 0x10 # macro +SQ_IND_INDEX__WAVE_ID_MASK = 0x0000000F # macro +SQ_IND_INDEX__SIMD_ID_MASK = 0x00000030 # macro +SQ_IND_INDEX__THREAD_ID_MASK = 0x00000FC0 # macro +SQ_IND_INDEX__AUTO_INCR_MASK = 0x00001000 # macro +SQ_IND_INDEX__FORCE_READ_MASK = 0x00002000 # macro +SQ_IND_INDEX__READ_TIMEOUT_MASK = 0x00004000 # macro +SQ_IND_INDEX__UNINDEXED_MASK = 0x00008000 # macro +SQ_IND_INDEX__INDEX_MASK = 0xFFFF0000 # macro +SQ_IND_DATA__DATA__SHIFT = 0x0 # macro +SQ_IND_DATA__DATA_MASK = 0xFFFFFFFF # macro +SQ_CONFIG1__DISABLE_XDL_PORTD_CO_EXEC__SHIFT = 0x0 # macro +SQ_CONFIG1__DISABLE_MGCG_ON_IBUF__SHIFT = 0x1 # macro +SQ_CONFIG1__DISABLE_MGCG_ON_PERF__SHIFT = 0x2 # macro +SQ_CONFIG1__DISABLE_MGCG_ON_EXP__SHIFT = 0x3 # macro +SQ_CONFIG1__DISABLE_MGCG_ON_SCA__SHIFT = 0x4 # macro +SQ_CONFIG1__DISABLE_MGCG_ON_SREG__SHIFT = 0x5 # macro +SQ_CONFIG1__DISABLE_MGCG_ON_VDEC__SHIFT = 0x6 # macro +SQ_CONFIG1__EXTRA_DGEMM_PROTECT_EN__SHIFT = 0x7 # macro +SQ_CONFIG1__DISABLE_VALU_COEXEC__SHIFT = 0x8 # macro +SQ_CONFIG1__DISABLE_WAVE_VALU_COEXEC__SHIFT = 0x9 # macro +SQ_CONFIG1__VGPR_ARB_PLUS1__SHIFT = 0xa # macro +SQ_CONFIG1__DISABLE_VGPR_COLLAPSE__SHIFT = 0xb # macro +SQ_CONFIG1__DISABLE_XNACK_CHECK_IN_RETRY_DISABLE__SHIFT = 0xc # macro +SQ_CONFIG1__DISABLE_BARRIER_ADDR_WATCH__SHIFT = 0xd # macro +SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_WAIT__SHIFT = 0xe # macro +SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_BACKOFF__SHIFT = 0xf # macro +SQ_CONFIG1__EXPAND_SP_CMD_FGCG__SHIFT = 0x10 # macro +SQ_CONFIG1__EXPAND_SP_EXPORT_FGCG__SHIFT = 0x11 # macro +SQ_CONFIG1__DISABLE_MGCG_ON_PERF_SNAP__SHIFT = 0x12 # macro +SQ_CONFIG1__DISABLE_VALU_COEXEC_MODE_AUTO_CLEAN__SHIFT = 0x13 # macro +SQ_CONFIG1__SP_CORE1_MGCG_OVERRIDE__SHIFT = 0x14 # macro +SQ_CONFIG1__SP_CORE4_MGCG_OVERRIDE__SHIFT = 0x15 # macro +SQ_CONFIG1__SP_CORE5_MGCG_OVERRIDE__SHIFT = 0x16 # macro +SQ_CONFIG1__DISABLE_SP_VGPR_COLLAPSE__SHIFT = 0x17 # macro +SQ_CONFIG1__SP_FGCG_REP_OVERRIDE__SHIFT = 0x18 # macro +SQ_CONFIG1__DPMACC_MGCG_OVERRIDE__SHIFT = 0x19 # macro +SQ_CONFIG1__XDLMACC_MGCG_OVERRIDE__SHIFT = 0x1a # macro +SQ_CONFIG1__TRANSMACC_MGCG_OVERRIDE__SHIFT = 0x1b # macro +SQ_CONFIG1__SPMACC_MGCG_OVERRIDE__SHIFT = 0x1c # macro +SQ_CONFIG1__DPMACC_DGEMM2X_MGCG_OVERRIDE__SHIFT = 0x1d # macro +SQ_CONFIG1__DISABLE_SP_VGPR_READ_SKIP__SHIFT = 0x1e # macro +SQ_CONFIG1__SP_SRC_1ST_BUFFER_MGCG_OVERRIDE__SHIFT = 0x1f # macro +SQ_CONFIG1__DISABLE_XDL_PORTD_CO_EXEC_MASK = 0x00000001 # macro +SQ_CONFIG1__DISABLE_MGCG_ON_IBUF_MASK = 0x00000002 # macro +SQ_CONFIG1__DISABLE_MGCG_ON_PERF_MASK = 0x00000004 # macro +SQ_CONFIG1__DISABLE_MGCG_ON_EXP_MASK = 0x00000008 # macro +SQ_CONFIG1__DISABLE_MGCG_ON_SCA_MASK = 0x00000010 # macro +SQ_CONFIG1__DISABLE_MGCG_ON_SREG_MASK = 0x00000020 # macro +SQ_CONFIG1__DISABLE_MGCG_ON_VDEC_MASK = 0x00000040 # macro +SQ_CONFIG1__EXTRA_DGEMM_PROTECT_EN_MASK = 0x00000080 # macro +SQ_CONFIG1__DISABLE_VALU_COEXEC_MASK = 0x00000100 # macro +SQ_CONFIG1__DISABLE_WAVE_VALU_COEXEC_MASK = 0x00000200 # macro +SQ_CONFIG1__VGPR_ARB_PLUS1_MASK = 0x00000400 # macro +SQ_CONFIG1__DISABLE_VGPR_COLLAPSE_MASK = 0x00000800 # macro +SQ_CONFIG1__DISABLE_XNACK_CHECK_IN_RETRY_DISABLE_MASK = 0x00001000 # macro +SQ_CONFIG1__DISABLE_BARRIER_ADDR_WATCH_MASK = 0x00002000 # macro +SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_WAIT_MASK = 0x00004000 # macro +SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_BACKOFF_MASK = 0x00008000 # macro +SQ_CONFIG1__EXPAND_SP_CMD_FGCG_MASK = 0x00010000 # macro +SQ_CONFIG1__EXPAND_SP_EXPORT_FGCG_MASK = 0x00020000 # macro +SQ_CONFIG1__DISABLE_MGCG_ON_PERF_SNAP_MASK = 0x00040000 # macro +SQ_CONFIG1__DISABLE_VALU_COEXEC_MODE_AUTO_CLEAN_MASK = 0x00080000 # macro +SQ_CONFIG1__SP_CORE1_MGCG_OVERRIDE_MASK = 0x00100000 # macro +SQ_CONFIG1__SP_CORE4_MGCG_OVERRIDE_MASK = 0x00200000 # macro +SQ_CONFIG1__SP_CORE5_MGCG_OVERRIDE_MASK = 0x00400000 # macro +SQ_CONFIG1__DISABLE_SP_VGPR_COLLAPSE_MASK = 0x00800000 # macro +SQ_CONFIG1__SP_FGCG_REP_OVERRIDE_MASK = 0x01000000 # macro +SQ_CONFIG1__DPMACC_MGCG_OVERRIDE_MASK = 0x02000000 # macro +SQ_CONFIG1__XDLMACC_MGCG_OVERRIDE_MASK = 0x04000000 # macro +SQ_CONFIG1__TRANSMACC_MGCG_OVERRIDE_MASK = 0x08000000 # macro +SQ_CONFIG1__SPMACC_MGCG_OVERRIDE_MASK = 0x10000000 # macro +SQ_CONFIG1__DPMACC_DGEMM2X_MGCG_OVERRIDE_MASK = 0x20000000 # macro +SQ_CONFIG1__DISABLE_SP_VGPR_READ_SKIP_MASK = 0x40000000 # macro +SQ_CONFIG1__SP_SRC_1ST_BUFFER_MGCG_OVERRIDE_MASK = 0x80000000 # macro +SQ_CMD__CMD__SHIFT = 0x0 # macro +SQ_CMD__MODE__SHIFT = 0x4 # macro +SQ_CMD__CHECK_VMID__SHIFT = 0x7 # macro +SQ_CMD__DATA__SHIFT = 0x8 # macro +SQ_CMD__WAVE_ID__SHIFT = 0x10 # macro +SQ_CMD__SIMD_ID__SHIFT = 0x14 # macro +SQ_CMD__QUEUE_ID__SHIFT = 0x18 # macro +SQ_CMD__VM_ID__SHIFT = 0x1c # macro +SQ_CMD__CMD_MASK = 0x00000007 # macro +SQ_CMD__MODE_MASK = 0x00000070 # macro +SQ_CMD__CHECK_VMID_MASK = 0x00000080 # macro +SQ_CMD__DATA_MASK = 0x00000F00 # macro +SQ_CMD__WAVE_ID_MASK = 0x000F0000 # macro +SQ_CMD__SIMD_ID_MASK = 0x00300000 # macro +SQ_CMD__QUEUE_ID_MASK = 0x07000000 # macro +SQ_CMD__VM_ID_MASK = 0xF0000000 # macro +SQ_TIME_HI__TIME__SHIFT = 0x0 # macro +SQ_TIME_HI__TIME_MASK = 0xFFFFFFFF # macro +SQ_TIME_LO__TIME__SHIFT = 0x0 # macro +SQ_TIME_LO__TIME_MASK = 0xFFFFFFFF # macro +SQ_DS_0__OFFSET0__SHIFT = 0x0 # macro +SQ_DS_0__OFFSET1__SHIFT = 0x8 # macro +SQ_DS_0__GDS__SHIFT = 0x10 # macro +SQ_DS_0__OP__SHIFT = 0x11 # macro +SQ_DS_0__ACC__SHIFT = 0x19 # macro +SQ_DS_0__ENCODING__SHIFT = 0x1a # macro +SQ_DS_0__OFFSET0_MASK = 0x000000FF # macro +SQ_DS_0__OFFSET1_MASK = 0x0000FF00 # macro +SQ_DS_0__GDS_MASK = 0x00010000 # macro +SQ_DS_0__OP_MASK = 0x01FE0000 # macro +SQ_DS_0__ACC_MASK = 0x02000000 # macro +SQ_DS_0__ENCODING_MASK = 0xFC000000 # macro +SQ_DS_1__ADDR__SHIFT = 0x0 # macro +SQ_DS_1__DATA0__SHIFT = 0x8 # macro +SQ_DS_1__DATA1__SHIFT = 0x10 # macro +SQ_DS_1__VDST__SHIFT = 0x18 # macro +SQ_DS_1__ADDR_MASK = 0x000000FF # macro +SQ_DS_1__DATA0_MASK = 0x0000FF00 # macro +SQ_DS_1__DATA1_MASK = 0x00FF0000 # macro +SQ_DS_1__VDST_MASK = 0xFF000000 # macro +SQ_EXP_0__EN__SHIFT = 0x0 # macro +SQ_EXP_0__TGT__SHIFT = 0x4 # macro +SQ_EXP_0__COMPR__SHIFT = 0xa # macro +SQ_EXP_0__DONE__SHIFT = 0xb # macro +SQ_EXP_0__VM__SHIFT = 0xc # macro +SQ_EXP_0__ENCODING__SHIFT = 0x1a # macro +SQ_EXP_0__EN_MASK = 0x0000000F # macro +SQ_EXP_0__TGT_MASK = 0x000003F0 # macro +SQ_EXP_0__COMPR_MASK = 0x00000400 # macro +SQ_EXP_0__DONE_MASK = 0x00000800 # macro +SQ_EXP_0__VM_MASK = 0x00001000 # macro +SQ_EXP_0__ENCODING_MASK = 0xFC000000 # macro +SQ_EXP_1__VSRC0__SHIFT = 0x0 # macro +SQ_EXP_1__VSRC1__SHIFT = 0x8 # macro +SQ_EXP_1__VSRC2__SHIFT = 0x10 # macro +SQ_EXP_1__VSRC3__SHIFT = 0x18 # macro +SQ_EXP_1__VSRC0_MASK = 0x000000FF # macro +SQ_EXP_1__VSRC1_MASK = 0x0000FF00 # macro +SQ_EXP_1__VSRC2_MASK = 0x00FF0000 # macro +SQ_EXP_1__VSRC3_MASK = 0xFF000000 # macro +SQ_FLAT_0__OFFSET__SHIFT = 0x0 # macro +SQ_FLAT_0__SVE__SHIFT = 0xd # macro +SQ_FLAT_0__SEG__SHIFT = 0xe # macro +SQ_FLAT_0__SC0__SHIFT = 0x10 # macro +SQ_FLAT_0__NT__SHIFT = 0x11 # macro +SQ_FLAT_0__OP__SHIFT = 0x12 # macro +SQ_FLAT_0__SC1__SHIFT = 0x19 # macro +SQ_FLAT_0__ENCODING__SHIFT = 0x1a # macro +SQ_FLAT_0__OFFSET_MASK = 0x00000FFF # macro +SQ_FLAT_0__SVE_MASK = 0x00002000 # macro +SQ_FLAT_0__SEG_MASK = 0x0000C000 # macro +SQ_FLAT_0__SC0_MASK = 0x00010000 # macro +SQ_FLAT_0__NT_MASK = 0x00020000 # macro +SQ_FLAT_0__OP_MASK = 0x01FC0000 # macro +SQ_FLAT_0__SC1_MASK = 0x02000000 # macro +SQ_FLAT_0__ENCODING_MASK = 0xFC000000 # macro +SQ_FLAT_1__ADDR__SHIFT = 0x0 # macro +SQ_FLAT_1__DATA__SHIFT = 0x8 # macro +SQ_FLAT_1__SADDR__SHIFT = 0x10 # macro +SQ_FLAT_1__ACC__SHIFT = 0x17 # macro +SQ_FLAT_1__VDST__SHIFT = 0x18 # macro +SQ_FLAT_1__ADDR_MASK = 0x000000FF # macro +SQ_FLAT_1__DATA_MASK = 0x0000FF00 # macro +SQ_FLAT_1__SADDR_MASK = 0x007F0000 # macro +SQ_FLAT_1__ACC_MASK = 0x00800000 # macro +SQ_FLAT_1__VDST_MASK = 0xFF000000 # macro +SQ_GLBL_0__OFFSET__SHIFT = 0x0 # macro +SQ_GLBL_0__SVE__SHIFT = 0xd # macro +SQ_GLBL_0__SEG__SHIFT = 0xe # macro +SQ_GLBL_0__SC0__SHIFT = 0x10 # macro +SQ_GLBL_0__NT__SHIFT = 0x11 # macro +SQ_GLBL_0__OP__SHIFT = 0x12 # macro +SQ_GLBL_0__SC1__SHIFT = 0x19 # macro +SQ_GLBL_0__ENCODING__SHIFT = 0x1a # macro +SQ_GLBL_0__OFFSET_MASK = 0x00001FFF # macro +SQ_GLBL_0__SVE_MASK = 0x00002000 # macro +SQ_GLBL_0__SEG_MASK = 0x0000C000 # macro +SQ_GLBL_0__SC0_MASK = 0x00010000 # macro +SQ_GLBL_0__NT_MASK = 0x00020000 # macro +SQ_GLBL_0__OP_MASK = 0x01FC0000 # macro +SQ_GLBL_0__SC1_MASK = 0x02000000 # macro +SQ_GLBL_0__ENCODING_MASK = 0xFC000000 # macro +SQ_GLBL_1__ADDR__SHIFT = 0x0 # macro +SQ_GLBL_1__DATA__SHIFT = 0x8 # macro +SQ_GLBL_1__SADDR__SHIFT = 0x10 # macro +SQ_GLBL_1__ACC__SHIFT = 0x17 # macro +SQ_GLBL_1__VDST__SHIFT = 0x18 # macro +SQ_GLBL_1__ADDR_MASK = 0x000000FF # macro +SQ_GLBL_1__DATA_MASK = 0x0000FF00 # macro +SQ_GLBL_1__SADDR_MASK = 0x007F0000 # macro +SQ_GLBL_1__ACC_MASK = 0x00800000 # macro +SQ_GLBL_1__VDST_MASK = 0xFF000000 # macro +SQ_INST__ENCODING__SHIFT = 0x0 # macro +SQ_INST__ENCODING_MASK = 0xFFFFFFFF # macro +SQ_MIMG_0__OPM__SHIFT = 0x0 # macro +SQ_MIMG_0__SC1__SHIFT = 0x7 # macro +SQ_MIMG_0__DMASK__SHIFT = 0x8 # macro +SQ_MIMG_0__UNORM__SHIFT = 0xc # macro +SQ_MIMG_0__SC0__SHIFT = 0xd # macro +SQ_MIMG_0__DA__SHIFT = 0xe # macro +SQ_MIMG_0__A16__SHIFT = 0xf # macro +SQ_MIMG_0__ACC__SHIFT = 0x10 # macro +SQ_MIMG_0__LWE__SHIFT = 0x11 # macro +SQ_MIMG_0__OP__SHIFT = 0x12 # macro +SQ_MIMG_0__NT__SHIFT = 0x19 # macro +SQ_MIMG_0__ENCODING__SHIFT = 0x1a # macro +SQ_MIMG_0__OPM_MASK = 0x00000001 # macro +SQ_MIMG_0__SC1_MASK = 0x00000080 # macro +SQ_MIMG_0__DMASK_MASK = 0x00000F00 # macro +SQ_MIMG_0__UNORM_MASK = 0x00001000 # macro +SQ_MIMG_0__SC0_MASK = 0x00002000 # macro +SQ_MIMG_0__DA_MASK = 0x00004000 # macro +SQ_MIMG_0__A16_MASK = 0x00008000 # macro +SQ_MIMG_0__ACC_MASK = 0x00010000 # macro +SQ_MIMG_0__LWE_MASK = 0x00020000 # macro +SQ_MIMG_0__OP_MASK = 0x01FC0000 # macro +SQ_MIMG_0__NT_MASK = 0x02000000 # macro +SQ_MIMG_0__ENCODING_MASK = 0xFC000000 # macro +SQ_MIMG_1__VADDR__SHIFT = 0x0 # macro +SQ_MIMG_1__VDATA__SHIFT = 0x8 # macro +SQ_MIMG_1__SRSRC__SHIFT = 0x10 # macro +SQ_MIMG_1__SSAMP__SHIFT = 0x15 # macro +SQ_MIMG_1__D16__SHIFT = 0x1f # macro +SQ_MIMG_1__VADDR_MASK = 0x000000FF # macro +SQ_MIMG_1__VDATA_MASK = 0x0000FF00 # macro +SQ_MIMG_1__SRSRC_MASK = 0x001F0000 # macro +SQ_MIMG_1__SSAMP_MASK = 0x03E00000 # macro +SQ_MIMG_1__D16_MASK = 0x80000000 # macro +SQ_MTBUF_0__OFFSET__SHIFT = 0x0 # macro +SQ_MTBUF_0__OFFEN__SHIFT = 0xc # macro +SQ_MTBUF_0__IDXEN__SHIFT = 0xd # macro +SQ_MTBUF_0__SC0__SHIFT = 0xe # macro +SQ_MTBUF_0__OP__SHIFT = 0xf # macro +SQ_MTBUF_0__DFMT__SHIFT = 0x13 # macro +SQ_MTBUF_0__NFMT__SHIFT = 0x17 # macro +SQ_MTBUF_0__ENCODING__SHIFT = 0x1a # macro +SQ_MTBUF_0__OFFSET_MASK = 0x00000FFF # macro +SQ_MTBUF_0__OFFEN_MASK = 0x00001000 # macro +SQ_MTBUF_0__IDXEN_MASK = 0x00002000 # macro +SQ_MTBUF_0__SC0_MASK = 0x00004000 # macro +SQ_MTBUF_0__OP_MASK = 0x00078000 # macro +SQ_MTBUF_0__DFMT_MASK = 0x00780000 # macro +SQ_MTBUF_0__NFMT_MASK = 0x03800000 # macro +SQ_MTBUF_0__ENCODING_MASK = 0xFC000000 # macro +SQ_MTBUF_1__VADDR__SHIFT = 0x0 # macro +SQ_MTBUF_1__VDATA__SHIFT = 0x8 # macro +SQ_MTBUF_1__SRSRC__SHIFT = 0x10 # macro +SQ_MTBUF_1__SC1__SHIFT = 0x15 # macro +SQ_MTBUF_1__NT__SHIFT = 0x16 # macro +SQ_MTBUF_1__ACC__SHIFT = 0x17 # macro +SQ_MTBUF_1__SOFFSET__SHIFT = 0x18 # macro +SQ_MTBUF_1__VADDR_MASK = 0x000000FF # macro +SQ_MTBUF_1__VDATA_MASK = 0x0000FF00 # macro +SQ_MTBUF_1__SRSRC_MASK = 0x001F0000 # macro +SQ_MTBUF_1__SC1_MASK = 0x00200000 # macro +SQ_MTBUF_1__NT_MASK = 0x00400000 # macro +SQ_MTBUF_1__ACC_MASK = 0x00800000 # macro +SQ_MTBUF_1__SOFFSET_MASK = 0xFF000000 # macro +SQ_MUBUF_0__OFFSET__SHIFT = 0x0 # macro +SQ_MUBUF_0__OFFEN__SHIFT = 0xc # macro +SQ_MUBUF_0__IDXEN__SHIFT = 0xd # macro +SQ_MUBUF_0__SC0__SHIFT = 0xe # macro +SQ_MUBUF_0__SC1__SHIFT = 0xf # macro +SQ_MUBUF_0__LDS__SHIFT = 0x10 # macro +SQ_MUBUF_0__NT__SHIFT = 0x11 # macro +SQ_MUBUF_0__OP__SHIFT = 0x12 # macro +SQ_MUBUF_0__ENCODING__SHIFT = 0x1a # macro +SQ_MUBUF_0__OFFSET_MASK = 0x00000FFF # macro +SQ_MUBUF_0__OFFEN_MASK = 0x00001000 # macro +SQ_MUBUF_0__IDXEN_MASK = 0x00002000 # macro +SQ_MUBUF_0__SC0_MASK = 0x00004000 # macro +SQ_MUBUF_0__SC1_MASK = 0x00008000 # macro +SQ_MUBUF_0__LDS_MASK = 0x00010000 # macro +SQ_MUBUF_0__NT_MASK = 0x00020000 # macro +SQ_MUBUF_0__OP_MASK = 0x01FC0000 # macro +SQ_MUBUF_0__ENCODING_MASK = 0xFC000000 # macro +SQ_MUBUF_1__VADDR__SHIFT = 0x0 # macro +SQ_MUBUF_1__VDATA__SHIFT = 0x8 # macro +SQ_MUBUF_1__SRSRC__SHIFT = 0x10 # macro +SQ_MUBUF_1__ACC__SHIFT = 0x17 # macro +SQ_MUBUF_1__SOFFSET__SHIFT = 0x18 # macro +SQ_MUBUF_1__VADDR_MASK = 0x000000FF # macro +SQ_MUBUF_1__VDATA_MASK = 0x0000FF00 # macro +SQ_MUBUF_1__SRSRC_MASK = 0x001F0000 # macro +SQ_MUBUF_1__ACC_MASK = 0x00800000 # macro +SQ_MUBUF_1__SOFFSET_MASK = 0xFF000000 # macro +SQ_SCRATCH_0__OFFSET__SHIFT = 0x0 # macro +SQ_SCRATCH_0__SVE__SHIFT = 0xd # macro +SQ_SCRATCH_0__SEG__SHIFT = 0xe # macro +SQ_SCRATCH_0__SC0__SHIFT = 0x10 # macro +SQ_SCRATCH_0__NT__SHIFT = 0x11 # macro +SQ_SCRATCH_0__OP__SHIFT = 0x12 # macro +SQ_SCRATCH_0__SC1__SHIFT = 0x19 # macro +SQ_SCRATCH_0__ENCODING__SHIFT = 0x1a # macro +SQ_SCRATCH_0__OFFSET_MASK = 0x00001FFF # macro +SQ_SCRATCH_0__SVE_MASK = 0x00002000 # macro +SQ_SCRATCH_0__SEG_MASK = 0x0000C000 # macro +SQ_SCRATCH_0__SC0_MASK = 0x00010000 # macro +SQ_SCRATCH_0__NT_MASK = 0x00020000 # macro +SQ_SCRATCH_0__OP_MASK = 0x01FC0000 # macro +SQ_SCRATCH_0__SC1_MASK = 0x02000000 # macro +SQ_SCRATCH_0__ENCODING_MASK = 0xFC000000 # macro +SQ_SCRATCH_1__ADDR__SHIFT = 0x0 # macro +SQ_SCRATCH_1__DATA__SHIFT = 0x8 # macro +SQ_SCRATCH_1__SADDR__SHIFT = 0x10 # macro +SQ_SCRATCH_1__ACC__SHIFT = 0x17 # macro +SQ_SCRATCH_1__VDST__SHIFT = 0x18 # macro +SQ_SCRATCH_1__ADDR_MASK = 0x000000FF # macro +SQ_SCRATCH_1__DATA_MASK = 0x0000FF00 # macro +SQ_SCRATCH_1__SADDR_MASK = 0x007F0000 # macro +SQ_SCRATCH_1__ACC_MASK = 0x00800000 # macro +SQ_SCRATCH_1__VDST_MASK = 0xFF000000 # macro +SQ_SMEM_0__SBASE__SHIFT = 0x0 # macro +SQ_SMEM_0__SDATA__SHIFT = 0x6 # macro +SQ_SMEM_0__SOFFSET_EN__SHIFT = 0xe # macro +SQ_SMEM_0__NV__SHIFT = 0xf # macro +SQ_SMEM_0__GLC__SHIFT = 0x10 # macro +SQ_SMEM_0__IMM__SHIFT = 0x11 # macro +SQ_SMEM_0__OP__SHIFT = 0x12 # macro +SQ_SMEM_0__ENCODING__SHIFT = 0x1a # macro +SQ_SMEM_0__SBASE_MASK = 0x0000003F # macro +SQ_SMEM_0__SDATA_MASK = 0x00001FC0 # macro +SQ_SMEM_0__SOFFSET_EN_MASK = 0x00004000 # macro +SQ_SMEM_0__NV_MASK = 0x00008000 # macro +SQ_SMEM_0__GLC_MASK = 0x00010000 # macro +SQ_SMEM_0__IMM_MASK = 0x00020000 # macro +SQ_SMEM_0__OP_MASK = 0x03FC0000 # macro +SQ_SMEM_0__ENCODING_MASK = 0xFC000000 # macro +SQ_SMEM_1__OFFSET__SHIFT = 0x0 # macro +SQ_SMEM_1__SOFFSET__SHIFT = 0x19 # macro +SQ_SMEM_1__OFFSET_MASK = 0x001FFFFF # macro +SQ_SMEM_1__SOFFSET_MASK = 0xFE000000 # macro +SQ_SOP1__SSRC0__SHIFT = 0x0 # macro +SQ_SOP1__OP__SHIFT = 0x8 # macro +SQ_SOP1__SDST__SHIFT = 0x10 # macro +SQ_SOP1__ENCODING__SHIFT = 0x17 # macro +SQ_SOP1__SSRC0_MASK = 0x000000FF # macro +SQ_SOP1__OP_MASK = 0x0000FF00 # macro +SQ_SOP1__SDST_MASK = 0x007F0000 # macro +SQ_SOP1__ENCODING_MASK = 0xFF800000 # macro +SQ_SOP2__SSRC0__SHIFT = 0x0 # macro +SQ_SOP2__SSRC1__SHIFT = 0x8 # macro +SQ_SOP2__SDST__SHIFT = 0x10 # macro +SQ_SOP2__OP__SHIFT = 0x17 # macro +SQ_SOP2__ENCODING__SHIFT = 0x1e # macro +SQ_SOP2__SSRC0_MASK = 0x000000FF # macro +SQ_SOP2__SSRC1_MASK = 0x0000FF00 # macro +SQ_SOP2__SDST_MASK = 0x007F0000 # macro +SQ_SOP2__OP_MASK = 0x3F800000 # macro +SQ_SOP2__ENCODING_MASK = 0xC0000000 # macro +SQ_SOPC__SSRC0__SHIFT = 0x0 # macro +SQ_SOPC__SSRC1__SHIFT = 0x8 # macro +SQ_SOPC__OP__SHIFT = 0x10 # macro +SQ_SOPC__ENCODING__SHIFT = 0x17 # macro +SQ_SOPC__SSRC0_MASK = 0x000000FF # macro +SQ_SOPC__SSRC1_MASK = 0x0000FF00 # macro +SQ_SOPC__OP_MASK = 0x007F0000 # macro +SQ_SOPC__ENCODING_MASK = 0xFF800000 # macro +SQ_SOPK__SIMM16__SHIFT = 0x0 # macro +SQ_SOPK__SDST__SHIFT = 0x10 # macro +SQ_SOPK__OP__SHIFT = 0x17 # macro +SQ_SOPK__ENCODING__SHIFT = 0x1c # macro +SQ_SOPK__SIMM16_MASK = 0x0000FFFF # macro +SQ_SOPK__SDST_MASK = 0x007F0000 # macro +SQ_SOPK__OP_MASK = 0x0F800000 # macro +SQ_SOPK__ENCODING_MASK = 0xF0000000 # macro +SQ_SOPP__SIMM16__SHIFT = 0x0 # macro +SQ_SOPP__OP__SHIFT = 0x10 # macro +SQ_SOPP__ENCODING__SHIFT = 0x17 # macro +SQ_SOPP__SIMM16_MASK = 0x0000FFFF # macro +SQ_SOPP__OP_MASK = 0x007F0000 # macro +SQ_SOPP__ENCODING_MASK = 0xFF800000 # macro +SQ_VINTRP__VSRC__SHIFT = 0x0 # macro +SQ_VINTRP__ATTRCHAN__SHIFT = 0x8 # macro +SQ_VINTRP__ATTR__SHIFT = 0xa # macro +SQ_VINTRP__OP__SHIFT = 0x10 # macro +SQ_VINTRP__VDST__SHIFT = 0x12 # macro +SQ_VINTRP__ENCODING__SHIFT = 0x1a # macro +SQ_VINTRP__VSRC_MASK = 0x000000FF # macro +SQ_VINTRP__ATTRCHAN_MASK = 0x00000300 # macro +SQ_VINTRP__ATTR_MASK = 0x0000FC00 # macro +SQ_VINTRP__OP_MASK = 0x00030000 # macro +SQ_VINTRP__VDST_MASK = 0x03FC0000 # macro +SQ_VINTRP__ENCODING_MASK = 0xFC000000 # macro +SQ_VOP1__SRC0__SHIFT = 0x0 # macro +SQ_VOP1__OP__SHIFT = 0x9 # macro +SQ_VOP1__VDST__SHIFT = 0x11 # macro +SQ_VOP1__ENCODING__SHIFT = 0x19 # macro +SQ_VOP1__SRC0_MASK = 0x000001FF # macro +SQ_VOP1__OP_MASK = 0x0001FE00 # macro +SQ_VOP1__VDST_MASK = 0x01FE0000 # macro +SQ_VOP1__ENCODING_MASK = 0xFE000000 # macro +SQ_VOP2__SRC0__SHIFT = 0x0 # macro +SQ_VOP2__VSRC1__SHIFT = 0x9 # macro +SQ_VOP2__VDST__SHIFT = 0x11 # macro +SQ_VOP2__OP__SHIFT = 0x19 # macro +SQ_VOP2__ENCODING__SHIFT = 0x1f # macro +SQ_VOP2__SRC0_MASK = 0x000001FF # macro +SQ_VOP2__VSRC1_MASK = 0x0001FE00 # macro +SQ_VOP2__VDST_MASK = 0x01FE0000 # macro +SQ_VOP2__OP_MASK = 0x7E000000 # macro +SQ_VOP2__ENCODING_MASK = 0x80000000 # macro +SQ_VOP3P_0__VDST__SHIFT = 0x0 # macro +SQ_VOP3P_0__NEG_HI__SHIFT = 0x8 # macro +SQ_VOP3P_0__OP_SEL__SHIFT = 0xb # macro +SQ_VOP3P_0__OP_SEL_HI_2__SHIFT = 0xe # macro +SQ_VOP3P_0__CLAMP__SHIFT = 0xf # macro +SQ_VOP3P_0__OP__SHIFT = 0x10 # macro +SQ_VOP3P_0__ENCODING__SHIFT = 0x17 # macro +SQ_VOP3P_0__VDST_MASK = 0x000000FF # macro +SQ_VOP3P_0__NEG_HI_MASK = 0x00000700 # macro +SQ_VOP3P_0__OP_SEL_MASK = 0x00003800 # macro +SQ_VOP3P_0__OP_SEL_HI_2_MASK = 0x00004000 # macro +SQ_VOP3P_0__CLAMP_MASK = 0x00008000 # macro +SQ_VOP3P_0__OP_MASK = 0x007F0000 # macro +SQ_VOP3P_0__ENCODING_MASK = 0xFF800000 # macro +SQ_VOP3P_1__SRC0__SHIFT = 0x0 # macro +SQ_VOP3P_1__SRC1__SHIFT = 0x9 # macro +SQ_VOP3P_1__SRC2__SHIFT = 0x12 # macro +SQ_VOP3P_1__OP_SEL_HI__SHIFT = 0x1b # macro +SQ_VOP3P_1__NEG__SHIFT = 0x1d # macro +SQ_VOP3P_1__SRC0_MASK = 0x000001FF # macro +SQ_VOP3P_1__SRC1_MASK = 0x0003FE00 # macro +SQ_VOP3P_1__SRC2_MASK = 0x07FC0000 # macro +SQ_VOP3P_1__OP_SEL_HI_MASK = 0x18000000 # macro +SQ_VOP3P_1__NEG_MASK = 0xE0000000 # macro +SQ_VOP3P_MFMA_0__VDST__SHIFT = 0x0 # macro +SQ_VOP3P_MFMA_0__CBSZ__SHIFT = 0x8 # macro +SQ_VOP3P_MFMA_0__ABID__SHIFT = 0xb # macro +SQ_VOP3P_MFMA_0__ACC_CD__SHIFT = 0xf # macro +SQ_VOP3P_MFMA_0__OP__SHIFT = 0x10 # macro +SQ_VOP3P_MFMA_0__ENCODING__SHIFT = 0x17 # macro +SQ_VOP3P_MFMA_0__VDST_MASK = 0x000000FF # macro +SQ_VOP3P_MFMA_0__CBSZ_MASK = 0x00000700 # macro +SQ_VOP3P_MFMA_0__ABID_MASK = 0x00007800 # macro +SQ_VOP3P_MFMA_0__ACC_CD_MASK = 0x00008000 # macro +SQ_VOP3P_MFMA_0__OP_MASK = 0x007F0000 # macro +SQ_VOP3P_MFMA_0__ENCODING_MASK = 0xFF800000 # macro +SQ_VOP3P_MFMA_1__SRC0__SHIFT = 0x0 # macro +SQ_VOP3P_MFMA_1__SRC1__SHIFT = 0x9 # macro +SQ_VOP3P_MFMA_1__SRC2__SHIFT = 0x12 # macro +SQ_VOP3P_MFMA_1__ACC__SHIFT = 0x1b # macro +SQ_VOP3P_MFMA_1__BLGP__SHIFT = 0x1d # macro +SQ_VOP3P_MFMA_1__SRC0_MASK = 0x000001FF # macro +SQ_VOP3P_MFMA_1__SRC1_MASK = 0x0003FE00 # macro +SQ_VOP3P_MFMA_1__SRC2_MASK = 0x07FC0000 # macro +SQ_VOP3P_MFMA_1__ACC_MASK = 0x18000000 # macro +SQ_VOP3P_MFMA_1__BLGP_MASK = 0xE0000000 # macro +SQ_VOP3_0__VDST__SHIFT = 0x0 # macro +SQ_VOP3_0__ABS__SHIFT = 0x8 # macro +SQ_VOP3_0__OP_SEL__SHIFT = 0xb # macro +SQ_VOP3_0__CLAMP__SHIFT = 0xf # macro +SQ_VOP3_0__OP__SHIFT = 0x10 # macro +SQ_VOP3_0__ENCODING__SHIFT = 0x1a # macro +SQ_VOP3_0__VDST_MASK = 0x000000FF # macro +SQ_VOP3_0__ABS_MASK = 0x00000700 # macro +SQ_VOP3_0__OP_SEL_MASK = 0x00007800 # macro +SQ_VOP3_0__CLAMP_MASK = 0x00008000 # macro +SQ_VOP3_0__OP_MASK = 0x03FF0000 # macro +SQ_VOP3_0__ENCODING_MASK = 0xFC000000 # macro +SQ_VOP3_0_SDST_ENC__VDST__SHIFT = 0x0 # macro +SQ_VOP3_0_SDST_ENC__SDST__SHIFT = 0x8 # macro +SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT = 0xf # macro +SQ_VOP3_0_SDST_ENC__OP__SHIFT = 0x10 # macro +SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT = 0x1a # macro +SQ_VOP3_0_SDST_ENC__VDST_MASK = 0x000000FF # macro +SQ_VOP3_0_SDST_ENC__SDST_MASK = 0x00007F00 # macro +SQ_VOP3_0_SDST_ENC__CLAMP_MASK = 0x00008000 # macro +SQ_VOP3_0_SDST_ENC__OP_MASK = 0x03FF0000 # macro +SQ_VOP3_0_SDST_ENC__ENCODING_MASK = 0xFC000000 # macro +SQ_VOP3_1__SRC0__SHIFT = 0x0 # macro +SQ_VOP3_1__SRC1__SHIFT = 0x9 # macro +SQ_VOP3_1__SRC2__SHIFT = 0x12 # macro +SQ_VOP3_1__OMOD__SHIFT = 0x1b # macro +SQ_VOP3_1__NEG__SHIFT = 0x1d # macro +SQ_VOP3_1__SRC0_MASK = 0x000001FF # macro +SQ_VOP3_1__SRC1_MASK = 0x0003FE00 # macro +SQ_VOP3_1__SRC2_MASK = 0x07FC0000 # macro +SQ_VOP3_1__OMOD_MASK = 0x18000000 # macro +SQ_VOP3_1__NEG_MASK = 0xE0000000 # macro +SQ_VOPC__SRC0__SHIFT = 0x0 # macro +SQ_VOPC__VSRC1__SHIFT = 0x9 # macro +SQ_VOPC__OP__SHIFT = 0x11 # macro +SQ_VOPC__ENCODING__SHIFT = 0x19 # macro +SQ_VOPC__SRC0_MASK = 0x000001FF # macro +SQ_VOPC__VSRC1_MASK = 0x0001FE00 # macro +SQ_VOPC__OP_MASK = 0x01FE0000 # macro +SQ_VOPC__ENCODING_MASK = 0xFE000000 # macro +SQ_VOP_DPP__SRC0__SHIFT = 0x0 # macro +SQ_VOP_DPP__DPP_CTRL__SHIFT = 0x8 # macro +SQ_VOP_DPP__BOUND_CTRL__SHIFT = 0x13 # macro +SQ_VOP_DPP__SRC0_NEG__SHIFT = 0x14 # macro +SQ_VOP_DPP__SRC0_ABS__SHIFT = 0x15 # macro +SQ_VOP_DPP__SRC1_NEG__SHIFT = 0x16 # macro +SQ_VOP_DPP__SRC1_ABS__SHIFT = 0x17 # macro +SQ_VOP_DPP__BANK_MASK__SHIFT = 0x18 # macro +SQ_VOP_DPP__ROW_MASK__SHIFT = 0x1c # macro +SQ_VOP_DPP__SRC0_MASK = 0x000000FF # macro +SQ_VOP_DPP__DPP_CTRL_MASK = 0x0001FF00 # macro +SQ_VOP_DPP__BOUND_CTRL_MASK = 0x00080000 # macro +SQ_VOP_DPP__SRC0_NEG_MASK = 0x00100000 # macro +SQ_VOP_DPP__SRC0_ABS_MASK = 0x00200000 # macro +SQ_VOP_DPP__SRC1_NEG_MASK = 0x00400000 # macro +SQ_VOP_DPP__SRC1_ABS_MASK = 0x00800000 # macro +SQ_VOP_DPP__BANK_MASK_MASK = 0x0F000000 # macro +SQ_VOP_DPP__ROW_MASK_MASK = 0xF0000000 # macro +SQ_VOP_SDWA__SRC0__SHIFT = 0x0 # macro +SQ_VOP_SDWA__DST_SEL__SHIFT = 0x8 # macro +SQ_VOP_SDWA__DST_UNUSED__SHIFT = 0xb # macro +SQ_VOP_SDWA__CLAMP__SHIFT = 0xd # macro +SQ_VOP_SDWA__OMOD__SHIFT = 0xe # macro +SQ_VOP_SDWA__SRC0_SEL__SHIFT = 0x10 # macro +SQ_VOP_SDWA__SRC0_SEXT__SHIFT = 0x13 # macro +SQ_VOP_SDWA__SRC0_NEG__SHIFT = 0x14 # macro +SQ_VOP_SDWA__SRC0_ABS__SHIFT = 0x15 # macro +SQ_VOP_SDWA__S0__SHIFT = 0x17 # macro +SQ_VOP_SDWA__SRC1_SEL__SHIFT = 0x18 # macro +SQ_VOP_SDWA__SRC1_SEXT__SHIFT = 0x1b # macro +SQ_VOP_SDWA__SRC1_NEG__SHIFT = 0x1c # macro +SQ_VOP_SDWA__SRC1_ABS__SHIFT = 0x1d # macro +SQ_VOP_SDWA__S1__SHIFT = 0x1f # macro +SQ_VOP_SDWA__SRC0_MASK = 0x000000FF # macro +SQ_VOP_SDWA__DST_SEL_MASK = 0x00000700 # macro +SQ_VOP_SDWA__DST_UNUSED_MASK = 0x00001800 # macro +SQ_VOP_SDWA__CLAMP_MASK = 0x00002000 # macro +SQ_VOP_SDWA__OMOD_MASK = 0x0000C000 # macro +SQ_VOP_SDWA__SRC0_SEL_MASK = 0x00070000 # macro +SQ_VOP_SDWA__SRC0_SEXT_MASK = 0x00080000 # macro +SQ_VOP_SDWA__SRC0_NEG_MASK = 0x00100000 # macro +SQ_VOP_SDWA__SRC0_ABS_MASK = 0x00200000 # macro +SQ_VOP_SDWA__S0_MASK = 0x00800000 # macro +SQ_VOP_SDWA__SRC1_SEL_MASK = 0x07000000 # macro +SQ_VOP_SDWA__SRC1_SEXT_MASK = 0x08000000 # macro +SQ_VOP_SDWA__SRC1_NEG_MASK = 0x10000000 # macro +SQ_VOP_SDWA__SRC1_ABS_MASK = 0x20000000 # macro +SQ_VOP_SDWA__S1_MASK = 0x80000000 # macro +SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT = 0x0 # macro +SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT = 0x8 # macro +SQ_VOP_SDWA_SDST_ENC__SD__SHIFT = 0xf # macro +SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT = 0x10 # macro +SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT = 0x13 # macro +SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT = 0x14 # macro +SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT = 0x15 # macro +SQ_VOP_SDWA_SDST_ENC__S0__SHIFT = 0x17 # macro +SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT = 0x18 # macro +SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT = 0x1b # macro +SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT = 0x1c # macro +SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT = 0x1d # macro +SQ_VOP_SDWA_SDST_ENC__S1__SHIFT = 0x1f # macro +SQ_VOP_SDWA_SDST_ENC__SRC0_MASK = 0x000000FF # macro +SQ_VOP_SDWA_SDST_ENC__SDST_MASK = 0x00007F00 # macro +SQ_VOP_SDWA_SDST_ENC__SD_MASK = 0x00008000 # macro +SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK = 0x00070000 # macro +SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK = 0x00080000 # macro +SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK = 0x00100000 # macro +SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK = 0x00200000 # macro +SQ_VOP_SDWA_SDST_ENC__S0_MASK = 0x00800000 # macro +SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK = 0x07000000 # macro +SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK = 0x08000000 # macro +SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK = 0x10000000 # macro +SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK = 0x20000000 # macro +SQ_VOP_SDWA_SDST_ENC__S1_MASK = 0x80000000 # macro +SQ_LB_CTR_CTRL__START__SHIFT = 0x0 # macro +SQ_LB_CTR_CTRL__LOAD__SHIFT = 0x1 # macro +SQ_LB_CTR_CTRL__CLEAR__SHIFT = 0x2 # macro +SQ_LB_CTR_CTRL__START_MASK = 0x00000001 # macro +SQ_LB_CTR_CTRL__LOAD_MASK = 0x00000002 # macro +SQ_LB_CTR_CTRL__CLEAR_MASK = 0x00000004 # macro +SQ_LB_DATA0__DATA__SHIFT = 0x0 # macro +SQ_LB_DATA0__DATA_MASK = 0xFFFFFFFF # macro +SQ_LB_DATA1__DATA__SHIFT = 0x0 # macro +SQ_LB_DATA1__DATA_MASK = 0xFFFFFFFF # macro +SQ_LB_DATA2__DATA__SHIFT = 0x0 # macro +SQ_LB_DATA2__DATA_MASK = 0xFFFFFFFF # macro +SQ_LB_DATA3__DATA__SHIFT = 0x0 # macro +SQ_LB_DATA3__DATA_MASK = 0xFFFFFFFF # macro +SQ_LB_CTR_SEL__SEL0__SHIFT = 0x0 # macro +SQ_LB_CTR_SEL__SEL1__SHIFT = 0x4 # macro +SQ_LB_CTR_SEL__SEL2__SHIFT = 0x8 # macro +SQ_LB_CTR_SEL__SEL3__SHIFT = 0xc # macro +SQ_LB_CTR_SEL__SEL0_MASK = 0x0000000F # macro +SQ_LB_CTR_SEL__SEL1_MASK = 0x000000F0 # macro +SQ_LB_CTR_SEL__SEL2_MASK = 0x00000F00 # macro +SQ_LB_CTR_SEL__SEL3_MASK = 0x0000F000 # macro +SQ_LB_CTR0_CU__SH0_MASK__SHIFT = 0x0 # macro +SQ_LB_CTR0_CU__SH1_MASK__SHIFT = 0x10 # macro +SQ_LB_CTR0_CU__SH0_MASK_MASK = 0x0000FFFF # macro +SQ_LB_CTR0_CU__SH1_MASK_MASK = 0xFFFF0000 # macro +SQ_LB_CTR1_CU__SH0_MASK__SHIFT = 0x0 # macro +SQ_LB_CTR1_CU__SH1_MASK__SHIFT = 0x10 # macro +SQ_LB_CTR1_CU__SH0_MASK_MASK = 0x0000FFFF # macro +SQ_LB_CTR1_CU__SH1_MASK_MASK = 0xFFFF0000 # macro +SQ_LB_CTR2_CU__SH0_MASK__SHIFT = 0x0 # macro +SQ_LB_CTR2_CU__SH1_MASK__SHIFT = 0x10 # macro +SQ_LB_CTR2_CU__SH0_MASK_MASK = 0x0000FFFF # macro +SQ_LB_CTR2_CU__SH1_MASK_MASK = 0xFFFF0000 # macro +SQ_LB_CTR3_CU__SH0_MASK__SHIFT = 0x0 # macro +SQ_LB_CTR3_CU__SH1_MASK__SHIFT = 0x10 # macro +SQ_LB_CTR3_CU__SH0_MASK_MASK = 0x0000FFFF # macro +SQ_LB_CTR3_CU__SH1_MASK_MASK = 0xFFFF0000 # macro +SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT = 0x0 # macro +SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT = 0x2 # macro +SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT = 0x4 # macro +SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT = 0x6 # macro +SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT = 0x8 # macro +SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT = 0xa # macro +SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT = 0xc # macro +SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT = 0xe # macro +SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT = 0x10 # macro +SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT = 0x12 # macro +SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT = 0x14 # macro +SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT = 0x16 # macro +SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT = 0x18 # macro +SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT = 0x1a # macro +SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT = 0x1c # macro +SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT = 0x1e # macro +SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK = 0x00000003 # macro +SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK = 0x0000000C # macro +SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK = 0x00000030 # macro +SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK = 0x000000C0 # macro +SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK = 0x00000300 # macro +SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK = 0x00000C00 # macro +SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK = 0x00003000 # macro +SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK = 0x0000C000 # macro +SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK = 0x00030000 # macro +SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK = 0x000C0000 # macro +SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK = 0x00300000 # macro +SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK = 0x00C00000 # macro +SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK = 0x03000000 # macro +SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK = 0x0C000000 # macro +SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK = 0x30000000 # macro +SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK = 0xC0000000 # macro +SQ_EDC_SEC_CNT__LDS_SEC__SHIFT = 0x0 # macro +SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT = 0x8 # macro +SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT = 0x10 # macro +SQ_EDC_SEC_CNT__LDS_SEC_MASK = 0x000000FF # macro +SQ_EDC_SEC_CNT__SGPR_SEC_MASK = 0x0000FF00 # macro +SQ_EDC_SEC_CNT__VGPR_SEC_MASK = 0x00FF0000 # macro +SQ_EDC_DED_CNT__LDS_DED__SHIFT = 0x0 # macro +SQ_EDC_DED_CNT__SGPR_DED__SHIFT = 0x8 # macro +SQ_EDC_DED_CNT__VGPR_DED__SHIFT = 0x10 # macro +SQ_EDC_DED_CNT__LDS_DED_MASK = 0x000000FF # macro +SQ_EDC_DED_CNT__SGPR_DED_MASK = 0x0000FF00 # macro +SQ_EDC_DED_CNT__VGPR_DED_MASK = 0x00FF0000 # macro +SQ_EDC_INFO__WAVE_ID__SHIFT = 0x0 # macro +SQ_EDC_INFO__SIMD_ID__SHIFT = 0x4 # macro +SQ_EDC_INFO__SOURCE__SHIFT = 0x6 # macro +SQ_EDC_INFO__VM_ID__SHIFT = 0x9 # macro +SQ_EDC_INFO__WAVE_ID_MASK = 0x0000000F # macro +SQ_EDC_INFO__SIMD_ID_MASK = 0x00000030 # macro +SQ_EDC_INFO__SOURCE_MASK = 0x000001C0 # macro +SQ_EDC_INFO__VM_ID_MASK = 0x00001E00 # macro +SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT = 0x0 # macro +SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT = 0x2 # macro +SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT = 0x4 # macro +SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT = 0x6 # macro +SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT = 0x8 # macro +SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT = 0xa # macro +SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT = 0xc # macro +SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT = 0xe # macro +SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT = 0x10 # macro +SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT = 0x12 # macro +SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT = 0x14 # macro +SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT = 0x16 # macro +SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT = 0x18 # macro +SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT = 0x1a # macro +SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK = 0x00000003 # macro +SQ_EDC_CNT__LDS_D_DED_COUNT_MASK = 0x0000000C # macro +SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK = 0x00000030 # macro +SQ_EDC_CNT__LDS_I_DED_COUNT_MASK = 0x000000C0 # macro +SQ_EDC_CNT__SGPR_SEC_COUNT_MASK = 0x00000300 # macro +SQ_EDC_CNT__SGPR_DED_COUNT_MASK = 0x00000C00 # macro +SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK = 0x00003000 # macro +SQ_EDC_CNT__VGPR0_DED_COUNT_MASK = 0x0000C000 # macro +SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK = 0x00030000 # macro +SQ_EDC_CNT__VGPR1_DED_COUNT_MASK = 0x000C0000 # macro +SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK = 0x00300000 # macro +SQ_EDC_CNT__VGPR2_DED_COUNT_MASK = 0x00C00000 # macro +SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK = 0x03000000 # macro +SQ_EDC_CNT__VGPR3_DED_COUNT_MASK = 0x0C000000 # macro +SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT = 0x0 # macro +SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT = 0x10 # macro +SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK = 0x0000FFFF # macro +SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK = 0xFFFF0000 # macro +SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT = 0x4 # macro +SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK = 0x000F # macro +SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK = 0x0010 # macro +SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT = 0x4 # macro +SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT = 0x5 # macro +SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT = 0x6 # macro +SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT = 0xa # macro +SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK = 0x000F # macro +SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK = 0x0010 # macro +SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK = 0x0020 # macro +SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK = 0x01C0 # macro +SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK = 0xFC00 # macro +SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT = 0x4 # macro +SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT = 0x5 # macro +SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT = 0x9 # macro +SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT = 0xb # macro +SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK = 0x000F # macro +SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK = 0x0010 # macro +SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK = 0x01E0 # macro +SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK = 0x0600 # macro +SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK = 0xF800 # macro +SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT = 0x4 # macro +SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT = 0x5 # macro +SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT = 0x9 # macro +SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT = 0xf # macro +SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT = 0x10 # macro +SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK = 0x0000000F # macro +SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK = 0x00000010 # macro +SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK = 0x000001E0 # macro +SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK = 0x00000600 # macro +SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK = 0x00008000 # macro +SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK = 0xFFFF0000 # macro +SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT = 0x4 # macro +SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__PRIV__SHIFT = 0x5 # macro +SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT = 0x6 # macro +SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT = 0xa # macro +SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT = 0xe # macro +SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT = 0x10 # macro +SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK = 0x0000000F # macro +SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK = 0x00000010 # macro +SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__PRIV_MASK = 0x00000020 # macro +SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK = 0x000003C0 # macro +SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK = 0x00003C00 # macro +SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK = 0x0000C000 # macro +SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK = 0xFFFF0000 # macro +SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT = 0x4 # macro +SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT = 0x5 # macro +SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT = 0x8 # macro +SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT = 0xa # macro +SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT = 0xc # macro +SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT = 0xe # macro +SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT = 0x10 # macro +SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT = 0x12 # macro +SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT = 0x14 # macro +SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT = 0x16 # macro +SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT = 0x18 # macro +SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT = 0x1a # macro +SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK = 0x0000000F # macro +SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK = 0x00000010 # macro +SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK = 0x00000060 # macro +SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK = 0x00000300 # macro +SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK = 0x00000C00 # macro +SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK = 0x00003000 # macro +SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK = 0x0000C000 # macro +SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK = 0x00030000 # macro +SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK = 0x000C0000 # macro +SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK = 0x00300000 # macro +SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK = 0x00C00000 # macro +SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK = 0x03000000 # macro +SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK = 0x0C000000 # macro +SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT = 0x4 # macro +SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT = 0xc # macro +SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT = 0xd # macro +SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK = 0x000F # macro +SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK = 0x0FF0 # macro +SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK = 0x1000 # macro +SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK = 0xE000 # macro +SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT = 0x4 # macro +SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT = 0x5 # macro +SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT = 0x6 # macro +SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT = 0xa # macro +SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT = 0xc # macro +SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT = 0x19 # macro +SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK = 0x0000000F # macro +SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK = 0x00000010 # macro +SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK = 0x00000020 # macro +SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK = 0x000003C0 # macro +SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK = 0x00000C00 # macro +SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK = 0x01FFF000 # macro +SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK = 0xFE000000 # macro +SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT = 0x4 # macro +SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT = 0x5 # macro +SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT = 0x7 # macro +SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT = 0x9 # macro +SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT = 0xa # macro +SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT = 0xe # macro +SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT = 0xf # macro +SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT = 0x10 # macro +SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK = 0x0000000F # macro +SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK = 0x00000010 # macro +SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK = 0x00000060 # macro +SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK = 0x00000180 # macro +SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK = 0x00000200 # macro +SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK = 0x00001C00 # macro +SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK = 0x00004000 # macro +SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK = 0x00008000 # macro +SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK = 0xFFFF0000 # macro +SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK = 0xFFFFFFFF # macro +SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT = 0x4 # macro +SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT = 0x5 # macro +SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT = 0x7 # macro +SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT = 0x9 # macro +SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT = 0x10 # macro +SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK = 0x0000000F # macro +SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK = 0x00000010 # macro +SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK = 0x00000060 # macro +SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK = 0x00000180 # macro +SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK = 0x0000FE00 # macro +SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK = 0xFFFF0000 # macro +SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK = 0x0000FFFF # macro +SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT = 0x10 # macro +SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK = 0x0000000F # macro +SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK = 0xFFFF0000 # macro +SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT = 0x4 # macro +SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT = 0x5 # macro +SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT = 0x6 # macro +SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT = 0xa # macro +SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT = 0xe # macro +SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK = 0x000F # macro +SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK = 0x0010 # macro +SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK = 0x0020 # macro +SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK = 0x03C0 # macro +SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK = 0x3C00 # macro +SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK = 0xC000 # macro +SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT = 0x4 # macro +SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT = 0x5 # macro +SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT = 0x6 # macro +SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT = 0xa # macro +SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT = 0xe # macro +SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT = 0x10 # macro +SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT = 0x15 # macro +SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT = 0x16 # macro +SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT = 0x1d # macro +SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK = 0x0000000F # macro +SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK = 0x00000010 # macro +SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK = 0x00000020 # macro +SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK = 0x000003C0 # macro +SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK = 0x00003C00 # macro +SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK = 0x0000C000 # macro +SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK = 0x001F0000 # macro +SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK = 0x00200000 # macro +SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK = 0x1FC00000 # macro +SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK = 0xE0000000 # macro +SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK = 0x00FFFFFF # macro +SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK = 0xFFFF # macro +SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT = 0x6 # macro +SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT = 0x13 # macro +SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK = 0x0000003F # macro +SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK = 0x0007FFC0 # macro +SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK = 0xFFF80000 # macro +SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK = 0xFFFFFFFF # macro +SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT = 0x0 # macro +SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT = 0x1a # macro +SQ_WREXEC_EXEC_HI__ATC__SHIFT = 0x1b # macro +SQ_WREXEC_EXEC_HI__MTYPE__SHIFT = 0x1c # macro +SQ_WREXEC_EXEC_HI__MSB__SHIFT = 0x1f # macro +SQ_WREXEC_EXEC_HI__ADDR_HI_MASK = 0x0000FFFF # macro +SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK = 0x04000000 # macro +SQ_WREXEC_EXEC_HI__ATC_MASK = 0x08000000 # macro +SQ_WREXEC_EXEC_HI__MTYPE_MASK = 0x70000000 # macro +SQ_WREXEC_EXEC_HI__MSB_MASK = 0x80000000 # macro +SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT = 0x0 # macro +SQ_WREXEC_EXEC_LO__ADDR_LO_MASK = 0xFFFFFFFF # macro +SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT = 0x0 # macro +SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK = 0xFFFFFFFF # macro +SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT = 0x0 # macro +SQ_BUF_RSRC_WORD1__STRIDE__SHIFT = 0x10 # macro +SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT = 0x1e # macro +SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT = 0x1f # macro +SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK = 0x0000FFFF # macro +SQ_BUF_RSRC_WORD1__STRIDE_MASK = 0x3FFF0000 # macro +SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK = 0x40000000 # macro +SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK = 0x80000000 # macro +SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT = 0x0 # macro +SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK = 0xFFFFFFFF # macro +SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT = 0x0 # macro +SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT = 0x3 # macro +SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT = 0x6 # macro +SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT = 0x9 # macro +SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT = 0xc # macro +SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT = 0xf # macro +SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT = 0x13 # macro +SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT = 0x14 # macro +SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT = 0x15 # macro +SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT = 0x17 # macro +SQ_BUF_RSRC_WORD3__NV__SHIFT = 0x1b # macro +SQ_BUF_RSRC_WORD3__TYPE__SHIFT = 0x1e # macro +SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK = 0x00000007 # macro +SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK = 0x00000038 # macro +SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK = 0x000001C0 # macro +SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK = 0x00000E00 # macro +SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK = 0x00007000 # macro +SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK = 0x00078000 # macro +SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK = 0x00080000 # macro +SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK = 0x00100000 # macro +SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK = 0x00600000 # macro +SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK = 0x00800000 # macro +SQ_BUF_RSRC_WORD3__NV_MASK = 0x08000000 # macro +SQ_BUF_RSRC_WORD3__TYPE_MASK = 0xC0000000 # macro +SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT = 0x0 # macro +SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK = 0xFFFFFFFF # macro +SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT = 0x0 # macro +SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT = 0x8 # macro +SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT = 0x14 # macro +SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT = 0x1a # macro +SQ_IMG_RSRC_WORD1__NV__SHIFT = 0x1e # macro +SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT = 0x1f # macro +SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK = 0x000000FF # macro +SQ_IMG_RSRC_WORD1__MIN_LOD_MASK = 0x000FFF00 # macro +SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK = 0x03F00000 # macro +SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK = 0x3C000000 # macro +SQ_IMG_RSRC_WORD1__NV_MASK = 0x40000000 # macro +SQ_IMG_RSRC_WORD1__META_DIRECT_MASK = 0x80000000 # macro +SQ_IMG_RSRC_WORD2__WIDTH__SHIFT = 0x0 # macro +SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT = 0xe # macro +SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT = 0x1c # macro +SQ_IMG_RSRC_WORD2__WIDTH_MASK = 0x00003FFF # macro +SQ_IMG_RSRC_WORD2__HEIGHT_MASK = 0x0FFFC000 # macro +SQ_IMG_RSRC_WORD2__PERF_MOD_MASK = 0x70000000 # macro +SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT = 0x0 # macro +SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT = 0x3 # macro +SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT = 0x6 # macro +SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT = 0x9 # macro +SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT = 0xc # macro +SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT = 0x10 # macro +SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT = 0x14 # macro +SQ_IMG_RSRC_WORD3__TYPE__SHIFT = 0x1c # macro +SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK = 0x00000007 # macro +SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK = 0x00000038 # macro +SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK = 0x000001C0 # macro +SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK = 0x00000E00 # macro +SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK = 0x0000F000 # macro +SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK = 0x000F0000 # macro +SQ_IMG_RSRC_WORD3__SW_MODE_MASK = 0x01F00000 # macro +SQ_IMG_RSRC_WORD3__TYPE_MASK = 0xF0000000 # macro +SQ_IMG_RSRC_WORD4__DEPTH__SHIFT = 0x0 # macro +SQ_IMG_RSRC_WORD4__PITCH__SHIFT = 0xd # macro +SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT = 0x1d # macro +SQ_IMG_RSRC_WORD4__DEPTH_MASK = 0x00001FFF # macro +SQ_IMG_RSRC_WORD4__PITCH_MASK = 0x1FFFE000 # macro +SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK = 0xE0000000 # macro +SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT = 0x0 # macro +SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT = 0xd # macro +SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT = 0x11 # macro +SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT = 0x19 # macro +SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT = 0x1a # macro +SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT = 0x1b # macro +SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT = 0x1c # macro +SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK = 0x00001FFF # macro +SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK = 0x0001E000 # macro +SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK = 0x01FE0000 # macro +SQ_IMG_RSRC_WORD5__META_LINEAR_MASK = 0x02000000 # macro +SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK = 0x04000000 # macro +SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK = 0x08000000 # macro +SQ_IMG_RSRC_WORD5__MAX_MIP_MASK = 0xF0000000 # macro +SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT = 0x0 # macro +SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT = 0xc # macro +SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT = 0x14 # macro +SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT = 0x15 # macro +SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT = 0x16 # macro +SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT = 0x17 # macro +SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT = 0x18 # macro +SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT = 0x1c # macro +SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK = 0x00000FFF # macro +SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK = 0x000FF000 # macro +SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK = 0x00100000 # macro +SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK = 0x00200000 # macro +SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK = 0x00400000 # macro +SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK = 0x00800000 # macro +SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK = 0x0F000000 # macro +SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK = 0xF0000000 # macro +SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT = 0x0 # macro +SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK = 0xFFFFFFFF # macro +SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT = 0x0 # macro +SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT = 0x3 # macro +SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT = 0x6 # macro +SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT = 0x9 # macro +SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT = 0xc # macro +SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT = 0xf # macro +SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT = 0x10 # macro +SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT = 0x13 # macro +SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT = 0x14 # macro +SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT = 0x15 # macro +SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT = 0x1b # macro +SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT = 0x1c # macro +SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT = 0x1d # macro +SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT = 0x1f # macro +SQ_IMG_SAMP_WORD0__CLAMP_X_MASK = 0x00000007 # macro +SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK = 0x00000038 # macro +SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK = 0x000001C0 # macro +SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK = 0x00000E00 # macro +SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK = 0x00007000 # macro +SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK = 0x00008000 # macro +SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK = 0x00070000 # macro +SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK = 0x00080000 # macro +SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK = 0x00100000 # macro +SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK = 0x07E00000 # macro +SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK = 0x08000000 # macro +SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK = 0x10000000 # macro +SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK = 0x60000000 # macro +SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK = 0x80000000 # macro +SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT = 0x0 # macro +SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT = 0xc # macro +SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT = 0x18 # macro +SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT = 0x1c # macro +SQ_IMG_SAMP_WORD1__MIN_LOD_MASK = 0x00000FFF # macro +SQ_IMG_SAMP_WORD1__MAX_LOD_MASK = 0x00FFF000 # macro +SQ_IMG_SAMP_WORD1__PERF_MIP_MASK = 0x0F000000 # macro +SQ_IMG_SAMP_WORD1__PERF_Z_MASK = 0xF0000000 # macro +SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT = 0x0 # macro +SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT = 0xe # macro +SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT = 0x14 # macro +SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT = 0x16 # macro +SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT = 0x18 # macro +SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT = 0x1a # macro +SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT = 0x1c # macro +SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT = 0x1d # macro +SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT = 0x1e # macro +SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT = 0x1f # macro +SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK = 0x00003FFF # macro +SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK = 0x000FC000 # macro +SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK = 0x00300000 # macro +SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK = 0x00C00000 # macro +SQ_IMG_SAMP_WORD2__Z_FILTER_MASK = 0x03000000 # macro +SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK = 0x0C000000 # macro +SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK = 0x10000000 # macro +SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK = 0x20000000 # macro +SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK = 0x40000000 # macro +SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK = 0x80000000 # macro +SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT = 0x0 # macro +SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT = 0xc # macro +SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT = 0x1e # macro +SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK = 0x00000FFF # macro +SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK = 0x00001000 # macro +SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK = 0xC0000000 # macro +SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT = 0x0 # macro +SQ_FLAT_SCRATCH_WORD0__SIZE_MASK = 0x0007FFFF # macro +SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT = 0x0 # macro +SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK = 0x00FFFFFF # macro +SQ_M0_GPR_IDX_WORD__INDEX__SHIFT = 0x0 # macro +SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT = 0xc # macro +SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT = 0xd # macro +SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT = 0xe # macro +SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT = 0xf # macro +SQ_M0_GPR_IDX_WORD__INDEX_MASK = 0x000000FF # macro +SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK = 0x00001000 # macro +SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK = 0x00002000 # macro +SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK = 0x00004000 # macro +SQ_M0_GPR_IDX_WORD__VDST_REL_MASK = 0x00008000 # macro +SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT = 0x0 # macro +SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT = 0x1 # macro +SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT = 0x2 # macro +SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT = 0x3 # macro +SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT = 0x5 # macro +SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT = 0x7 # macro +SQC_ICACHE_UTCL1_CNTL1__RESERVED__SHIFT = 0x10 # macro +SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT = 0x11 # macro +SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT = 0x12 # macro +SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT = 0x13 # macro +SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT = 0x17 # macro +SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT = 0x18 # macro +SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT = 0x19 # macro +SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT = 0x1a # macro +SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT = 0x1b # macro +SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT = 0x1c # macro +SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT = 0x1e # macro +SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK = 0x00000001 # macro +SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK = 0x00000002 # macro +SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK = 0x00000004 # macro +SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK = 0x00000018 # macro +SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK = 0x00000060 # macro +SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK = 0x0000FF80 # macro +SQC_ICACHE_UTCL1_CNTL1__RESERVED_MASK = 0x00010000 # macro +SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK = 0x00020000 # macro +SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK = 0x00040000 # macro +SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK = 0x00780000 # macro +SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK = 0x00800000 # macro +SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK = 0x01000000 # macro +SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK = 0x02000000 # macro +SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK = 0x04000000 # macro +SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK = 0x08000000 # macro +SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK = 0x30000000 # macro +SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK = 0xC0000000 # macro +SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT = 0x0 # macro +SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT = 0x8 # macro +SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT = 0x9 # macro +SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT = 0xa # macro +SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT = 0xb # macro +SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT = 0xc # macro +SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT = 0xd # macro +SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT = 0xe # macro +SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT = 0xf # macro +SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT = 0x10 # macro +SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT = 0x12 # macro +SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT = 0x13 # macro +SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT = 0x14 # macro +SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT = 0x15 # macro +SQC_ICACHE_UTCL1_CNTL2__RESERVED__SHIFT = 0x19 # macro +SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT = 0x1a # macro +SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK = 0x000000FF # macro +SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK = 0x00000100 # macro +SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK = 0x00000200 # macro +SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK = 0x00000400 # macro +SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK = 0x00000800 # macro +SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK = 0x00001000 # macro +SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK = 0x00002000 # macro +SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK = 0x00004000 # macro +SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK = 0x00008000 # macro +SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK = 0x00030000 # macro +SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK = 0x00040000 # macro +SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK = 0x00080000 # macro +SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK = 0x00100000 # macro +SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK = 0x01E00000 # macro +SQC_ICACHE_UTCL1_CNTL2__RESERVED_MASK = 0x02000000 # macro +SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK = 0x04000000 # macro +SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT = 0x0 # macro +SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT = 0x1 # macro +SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT = 0x2 # macro +SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT = 0x3 # macro +SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT = 0x5 # macro +SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT = 0x7 # macro +SQC_DCACHE_UTCL1_CNTL1__RESERVED__SHIFT = 0x10 # macro +SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT = 0x11 # macro +SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT = 0x12 # macro +SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT = 0x13 # macro +SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT = 0x17 # macro +SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT = 0x18 # macro +SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT = 0x19 # macro +SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT = 0x1a # macro +SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT = 0x1b # macro +SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT = 0x1c # macro +SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT = 0x1e # macro +SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK = 0x00000001 # macro +SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK = 0x00000002 # macro +SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK = 0x00000004 # macro +SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK = 0x00000018 # macro +SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK = 0x00000060 # macro +SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK = 0x0000FF80 # macro +SQC_DCACHE_UTCL1_CNTL1__RESERVED_MASK = 0x00010000 # macro +SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK = 0x00020000 # macro +SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK = 0x00040000 # macro +SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK = 0x00780000 # macro +SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK = 0x00800000 # macro +SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK = 0x01000000 # macro +SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK = 0x02000000 # macro +SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK = 0x04000000 # macro +SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK = 0x08000000 # macro +SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK = 0x30000000 # macro +SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK = 0xC0000000 # macro +SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT = 0x0 # macro +SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT = 0x8 # macro +SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT = 0x9 # macro +SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT = 0xa # macro +SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT = 0xb # macro +SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT = 0xc # macro +SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT = 0xd # macro +SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT = 0xe # macro +SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT = 0xf # macro +SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT = 0x10 # macro +SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT = 0x12 # macro +SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT = 0x13 # macro +SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT = 0x14 # macro +SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT = 0x15 # macro +SQC_DCACHE_UTCL1_CNTL2__RESERVED__SHIFT = 0x19 # macro +SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT = 0x1a # macro +SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK = 0x000000FF # macro +SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK = 0x00000100 # macro +SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK = 0x00000200 # macro +SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK = 0x00000400 # macro +SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK = 0x00000800 # macro +SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK = 0x00001000 # macro +SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK = 0x00002000 # macro +SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK = 0x00004000 # macro +SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK = 0x00008000 # macro +SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK = 0x00030000 # macro +SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK = 0x00040000 # macro +SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK = 0x00080000 # macro +SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK = 0x00100000 # macro +SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK = 0x01E00000 # macro +SQC_DCACHE_UTCL1_CNTL2__RESERVED_MASK = 0x02000000 # macro +SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK = 0x04000000 # macro +SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT = 0x0 # macro +SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT = 0x1 # macro +SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT = 0x2 # macro +SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK = 0x00000001 # macro +SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK = 0x00000002 # macro +SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK = 0x00000004 # macro +SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT = 0x0 # macro +SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT = 0x1 # macro +SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT = 0x2 # macro +SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK = 0x00000001 # macro +SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK = 0x00000002 # macro +SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK = 0x00000004 # macro +SQC_UE_EDC_LO__STATUS_VALID_FLAG__SHIFT = 0x0 # macro +SQC_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT = 0x1 # macro +SQC_UE_EDC_LO__ADDRESS__SHIFT = 0x2 # macro +SQC_UE_EDC_LO__MEM_ID__SHIFT = 0x18 # macro +SQC_UE_EDC_LO__STATUS_VALID_FLAG_MASK = 0x00000001 # macro +SQC_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK = 0x00000002 # macro +SQC_UE_EDC_LO__ADDRESS_MASK = 0x00FFFFFC # macro +SQC_UE_EDC_LO__MEM_ID_MASK = 0xFF000000 # macro +SQC_UE_EDC_HI__ECC__SHIFT = 0x0 # macro +SQC_UE_EDC_HI__PARITY__SHIFT = 0x1 # macro +SQC_UE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +SQC_UE_EDC_HI__ERR_INFO__SHIFT = 0x3 # macro +SQC_UE_EDC_HI__UE_CNT__SHIFT = 0x17 # macro +SQC_UE_EDC_HI__FED_CNT__SHIFT = 0x1a # macro +SQC_UE_EDC_HI__ECC_MASK = 0x00000001 # macro +SQC_UE_EDC_HI__PARITY_MASK = 0x00000002 # macro +SQC_UE_EDC_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +SQC_UE_EDC_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +SQC_UE_EDC_HI__UE_CNT_MASK = 0x03800000 # macro +SQC_UE_EDC_HI__FED_CNT_MASK = 0x1C000000 # macro +SQC_CE_EDC_LO__STATUS_VALID_FLAG__SHIFT = 0x0 # macro +SQC_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT = 0x1 # macro +SQC_CE_EDC_LO__ADDRESS__SHIFT = 0x2 # macro +SQC_CE_EDC_LO__MEM_ID__SHIFT = 0x18 # macro +SQC_CE_EDC_LO__STATUS_VALID_FLAG_MASK = 0x00000001 # macro +SQC_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK = 0x00000002 # macro +SQC_CE_EDC_LO__ADDRESS_MASK = 0x00FFFFFC # macro +SQC_CE_EDC_LO__MEM_ID_MASK = 0xFF000000 # macro +SQC_CE_EDC_HI__ECC__SHIFT = 0x0 # macro +SQC_CE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +SQC_CE_EDC_HI__ERR_INFO__SHIFT = 0x3 # macro +SQC_CE_EDC_HI__CE_CNT__SHIFT = 0x17 # macro +SQC_CE_EDC_HI__POSION__SHIFT = 0x1a # macro +SQC_CE_EDC_HI__ECC_MASK = 0x00000001 # macro +SQC_CE_EDC_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +SQC_CE_EDC_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +SQC_CE_EDC_HI__CE_CNT_MASK = 0x03800000 # macro +SQC_CE_EDC_HI__POSION_MASK = 0x04000000 # macro +SQ_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +SQ_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +SQ_UE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +SQ_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +SQ_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +SQ_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +SQ_UE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +SQ_UE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +SQ_UE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +SQ_UE_ERR_STATUS_HI__PARITY__SHIFT = 0x1 # macro +SQ_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +SQ_UE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +SQ_UE_ERR_STATUS_HI__UE_CNT__SHIFT = 0x17 # macro +SQ_UE_ERR_STATUS_HI__FED_CNT__SHIFT = 0x1a # macro +SQ_UE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1d # macro +SQ_UE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +SQ_UE_ERR_STATUS_HI__PARITY_MASK = 0x00000002 # macro +SQ_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +SQ_UE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +SQ_UE_ERR_STATUS_HI__UE_CNT_MASK = 0x03800000 # macro +SQ_UE_ERR_STATUS_HI__FED_CNT_MASK = 0x1C000000 # macro +SQ_UE_ERR_STATUS_HI__RESERVED_MASK = 0xE0000000 # macro +SQ_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +SQ_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +SQ_CE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +SQ_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +SQ_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +SQ_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +SQ_CE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +SQ_CE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +SQ_CE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +SQ_CE_ERR_STATUS_HI__OTHER__SHIFT = 0x1 # macro +SQ_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +SQ_CE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +SQ_CE_ERR_STATUS_HI__CE_CNT__SHIFT = 0x17 # macro +SQ_CE_ERR_STATUS_HI__POISON__SHIFT = 0x1a # macro +SQ_CE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1b # macro +SQ_CE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +SQ_CE_ERR_STATUS_HI__OTHER_MASK = 0x00000002 # macro +SQ_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +SQ_CE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +SQ_CE_ERR_STATUS_HI__CE_CNT_MASK = 0x03800000 # macro +SQ_CE_ERR_STATUS_HI__POISON_MASK = 0x04000000 # macro +SQ_CE_ERR_STATUS_HI__RESERVED_MASK = 0xF8000000 # macro +LDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +LDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +LDS_UE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +LDS_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +LDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +LDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +LDS_UE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +LDS_UE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +LDS_UE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +LDS_UE_ERR_STATUS_HI__PARITY__SHIFT = 0x1 # macro +LDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +LDS_UE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +LDS_UE_ERR_STATUS_HI__UE_CNT__SHIFT = 0x17 # macro +LDS_UE_ERR_STATUS_HI__FED_CNT__SHIFT = 0x1a # macro +LDS_UE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1d # macro +LDS_UE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +LDS_UE_ERR_STATUS_HI__PARITY_MASK = 0x00000002 # macro +LDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +LDS_UE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +LDS_UE_ERR_STATUS_HI__UE_CNT_MASK = 0x03800000 # macro +LDS_UE_ERR_STATUS_HI__FED_CNT_MASK = 0x1C000000 # macro +LDS_UE_ERR_STATUS_HI__RESERVED_MASK = 0xE0000000 # macro +LDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +LDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +LDS_CE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +LDS_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +LDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +LDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +LDS_CE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +LDS_CE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +LDS_CE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +LDS_CE_ERR_STATUS_HI__OTHER__SHIFT = 0x1 # macro +LDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +LDS_CE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +LDS_CE_ERR_STATUS_HI__CE_CNT__SHIFT = 0x17 # macro +LDS_CE_ERR_STATUS_HI__POISON__SHIFT = 0x1a # macro +LDS_CE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1b # macro +LDS_CE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +LDS_CE_ERR_STATUS_HI__OTHER_MASK = 0x00000002 # macro +LDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +LDS_CE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +LDS_CE_ERR_STATUS_HI__CE_CNT_MASK = 0x03800000 # macro +LDS_CE_ERR_STATUS_HI__POISON_MASK = 0x04000000 # macro +LDS_CE_ERR_STATUS_HI__RESERVED_MASK = 0xF8000000 # macro +SP0_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +SP0_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +SP0_UE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +SP0_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +SP0_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +SP0_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +SP0_UE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +SP0_UE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +SP0_UE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +SP0_UE_ERR_STATUS_HI__PARITY__SHIFT = 0x1 # macro +SP0_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +SP0_UE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +SP0_UE_ERR_STATUS_HI__UE_CNT__SHIFT = 0x17 # macro +SP0_UE_ERR_STATUS_HI__FED_CNT__SHIFT = 0x1a # macro +SP0_UE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1d # macro +SP0_UE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +SP0_UE_ERR_STATUS_HI__PARITY_MASK = 0x00000002 # macro +SP0_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +SP0_UE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +SP0_UE_ERR_STATUS_HI__UE_CNT_MASK = 0x03800000 # macro +SP0_UE_ERR_STATUS_HI__FED_CNT_MASK = 0x1C000000 # macro +SP0_UE_ERR_STATUS_HI__RESERVED_MASK = 0xE0000000 # macro +SP0_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +SP0_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +SP0_CE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +SP0_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +SP0_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +SP0_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +SP0_CE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +SP0_CE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +SP0_CE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +SP0_CE_ERR_STATUS_HI__OTHER__SHIFT = 0x1 # macro +SP0_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +SP0_CE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +SP0_CE_ERR_STATUS_HI__CE_CNT__SHIFT = 0x17 # macro +SP0_CE_ERR_STATUS_HI__POISON__SHIFT = 0x1a # macro +SP0_CE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1b # macro +SP0_CE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +SP0_CE_ERR_STATUS_HI__OTHER_MASK = 0x00000002 # macro +SP0_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +SP0_CE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +SP0_CE_ERR_STATUS_HI__CE_CNT_MASK = 0x03800000 # macro +SP0_CE_ERR_STATUS_HI__POISON_MASK = 0x04000000 # macro +SP0_CE_ERR_STATUS_HI__RESERVED_MASK = 0xF8000000 # macro +SP1_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +SP1_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +SP1_UE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +SP1_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +SP1_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +SP1_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +SP1_UE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +SP1_UE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +SP1_UE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +SP1_UE_ERR_STATUS_HI__PARITY__SHIFT = 0x1 # macro +SP1_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +SP1_UE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +SP1_UE_ERR_STATUS_HI__UE_CNT__SHIFT = 0x17 # macro +SP1_UE_ERR_STATUS_HI__FED_CNT__SHIFT = 0x1a # macro +SP1_UE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1d # macro +SP1_UE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +SP1_UE_ERR_STATUS_HI__PARITY_MASK = 0x00000002 # macro +SP1_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +SP1_UE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +SP1_UE_ERR_STATUS_HI__UE_CNT_MASK = 0x03800000 # macro +SP1_UE_ERR_STATUS_HI__FED_CNT_MASK = 0x1C000000 # macro +SP1_UE_ERR_STATUS_HI__RESERVED_MASK = 0xE0000000 # macro +SP1_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +SP1_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +SP1_CE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +SP1_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +SP1_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +SP1_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +SP1_CE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +SP1_CE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +SP1_CE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +SP1_CE_ERR_STATUS_HI__OTHER__SHIFT = 0x1 # macro +SP1_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +SP1_CE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +SP1_CE_ERR_STATUS_HI__CE_CNT__SHIFT = 0x17 # macro +SP1_CE_ERR_STATUS_HI__POISON__SHIFT = 0x1a # macro +SP1_CE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1b # macro +SP1_CE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +SP1_CE_ERR_STATUS_HI__OTHER_MASK = 0x00000002 # macro +SP1_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +SP1_CE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +SP1_CE_ERR_STATUS_HI__CE_CNT_MASK = 0x03800000 # macro +SP1_CE_ERR_STATUS_HI__POISON_MASK = 0x04000000 # macro +SP1_CE_ERR_STATUS_HI__RESERVED_MASK = 0xF8000000 # macro +SX_DEBUG_BUSY__RESERVED__SHIFT = 0x0 # macro +SX_DEBUG_BUSY__PCCMD_VALID__SHIFT = 0x1b # macro +SX_DEBUG_BUSY__VDATA1_VALID__SHIFT = 0x1c # macro +SX_DEBUG_BUSY__VDATA0_VALID__SHIFT = 0x1d # macro +SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT = 0x1e # macro +SX_DEBUG_BUSY__PCDATA_VALID__SHIFT = 0x1f # macro +SX_DEBUG_BUSY__RESERVED_MASK = 0x07FFFFFF # macro +SX_DEBUG_BUSY__PCCMD_VALID_MASK = 0x08000000 # macro +SX_DEBUG_BUSY__VDATA1_VALID_MASK = 0x10000000 # macro +SX_DEBUG_BUSY__VDATA0_VALID_MASK = 0x20000000 # macro +SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK = 0x40000000 # macro +SX_DEBUG_BUSY__PCDATA_VALID_MASK = 0x80000000 # macro +SX_DEBUG_1__RESERVED__SHIFT = 0x0 # macro +SX_DEBUG_1__DISABLE_REP_FGCG__SHIFT = 0xd # macro +SX_DEBUG_1__RESERVED_MASK = 0x00001FFF # macro +SX_DEBUG_1__DISABLE_REP_FGCG_MASK = 0x00002000 # macro +SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT = 0x0 # macro +SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT = 0x10 # macro +SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK = 0x00000FFF # macro +SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK = 0x03FF0000 # macro +SPI_START_PHASE__VGPR_START_PHASE__SHIFT = 0x0 # macro +SPI_START_PHASE__SGPR_START_PHASE__SHIFT = 0x2 # macro +SPI_START_PHASE__WAVE_START_PHASE__SHIFT = 0x4 # macro +SPI_START_PHASE__SPI_TD_GAP__SHIFT = 0x6 # macro +SPI_START_PHASE__VGPR_START_PHASE_MASK = 0x00000003 # macro +SPI_START_PHASE__SGPR_START_PHASE_MASK = 0x0000000C # macro +SPI_START_PHASE__WAVE_START_PHASE_MASK = 0x00000030 # macro +SPI_START_PHASE__SPI_TD_GAP_MASK = 0x000003C0 # macro +SPI_GFX_CNTL__RESET_COUNTS__SHIFT = 0x0 # macro +SPI_GFX_CNTL__RESET_COUNTS_MASK = 0x00000001 # macro +SPI_DEBUG_READ__DATA__SHIFT = 0x0 # macro +SPI_DEBUG_READ__DATA_MASK = 0xFFFFFFFF # macro +SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT = 0x0 # macro +SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT = 0x2 # macro +SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_DSM_IRRITATOR_DATA__SHIFT = 0x3 # macro +SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_ENABLE_SINGLE_WRITE__SHIFT = 0x5 # macro +SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_DSM_IRRITATOR_DATA__SHIFT = 0x6 # macro +SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_ENABLE_SINGLE_WRITE__SHIFT = 0x8 # macro +SPI_DSM_CNTL__RESERVED__SHIFT = 0x9 # macro +SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_DSM_IRRITATOR_DATA__SHIFT = 0xc # macro +SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_ENABLE_SINGLE_WRITE__SHIFT = 0xe # macro +SPI_DSM_CNTL__UNUSED__SHIFT = 0xf # macro +SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK = 0x00000003 # macro +SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK = 0x00000004 # macro +SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_DSM_IRRITATOR_DATA_MASK = 0x00000018 # macro +SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_ENABLE_SINGLE_WRITE_MASK = 0x00000020 # macro +SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_DSM_IRRITATOR_DATA_MASK = 0x000000C0 # macro +SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_ENABLE_SINGLE_WRITE_MASK = 0x00000100 # macro +SPI_DSM_CNTL__RESERVED_MASK = 0x00000E00 # macro +SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_DSM_IRRITATOR_DATA_MASK = 0x00003000 # macro +SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_ENABLE_SINGLE_WRITE_MASK = 0x00004000 # macro +SPI_DSM_CNTL__UNUSED_MASK = 0xFFFF8000 # macro +SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT = 0x4 # macro +SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_ENABLE_ERROR_INJECT__SHIFT = 0xa # macro +SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_SELECT_INJECT_DELAY__SHIFT = 0xc # macro +SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_ENABLE_ERROR_INJECT__SHIFT = 0xd # macro +SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_SELECT_INJECT_DELAY__SHIFT = 0xf # macro +SPI_DSM_CNTL2__RESERVED__SHIFT = 0x10 # macro +SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_ENABLE_ERROR_INJECT__SHIFT = 0x13 # macro +SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_SELECT_INJECT_DELAY__SHIFT = 0x15 # macro +SPI_DSM_CNTL2__UNUSED__SHIFT = 0x16 # macro +SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK = 0x000003F0 # macro +SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_ENABLE_ERROR_INJECT_MASK = 0x00000C00 # macro +SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_SELECT_INJECT_DELAY_MASK = 0x00001000 # macro +SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_ENABLE_ERROR_INJECT_MASK = 0x00006000 # macro +SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_SELECT_INJECT_DELAY_MASK = 0x00008000 # macro +SPI_DSM_CNTL2__RESERVED_MASK = 0x00070000 # macro +SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_ENABLE_ERROR_INJECT_MASK = 0x00180000 # macro +SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_SELECT_INJECT_DELAY_MASK = 0x00200000 # macro +SPI_DSM_CNTL2__UNUSED_MASK = 0xFFC00000 # macro +SPI_EDC_CNT__SPI_SR_MEM_SEC_COUNT__SHIFT = 0x0 # macro +SPI_EDC_CNT__SPI_SR_MEM_DED_COUNT__SHIFT = 0x2 # macro +SPI_EDC_CNT__SPI_GDS_EXPREQ_SEC_COUNT__SHIFT = 0x4 # macro +SPI_EDC_CNT__SPI_GDS_EXPREQ_DED_COUNT__SHIFT = 0x6 # macro +SPI_EDC_CNT__SPI_WB_GRANT_30_SEC_COUNT__SHIFT = 0x8 # macro +SPI_EDC_CNT__SPI_WB_GRANT_30_DED_COUNT__SHIFT = 0xa # macro +SPI_EDC_CNT__RESERVED__SHIFT = 0xc # macro +SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT__SHIFT = 0x10 # macro +SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT__SHIFT = 0x12 # macro +SPI_EDC_CNT__UNUSED__SHIFT = 0x14 # macro +SPI_EDC_CNT__SPI_SR_MEM_SEC_COUNT_MASK = 0x00000003 # macro +SPI_EDC_CNT__SPI_SR_MEM_DED_COUNT_MASK = 0x0000000C # macro +SPI_EDC_CNT__SPI_GDS_EXPREQ_SEC_COUNT_MASK = 0x00000030 # macro +SPI_EDC_CNT__SPI_GDS_EXPREQ_DED_COUNT_MASK = 0x000000C0 # macro +SPI_EDC_CNT__SPI_WB_GRANT_30_SEC_COUNT_MASK = 0x00000300 # macro +SPI_EDC_CNT__SPI_WB_GRANT_30_DED_COUNT_MASK = 0x00000C00 # macro +SPI_EDC_CNT__RESERVED_MASK = 0x0000F000 # macro +SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT_MASK = 0x00030000 # macro +SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT_MASK = 0x000C0000 # macro +SPI_EDC_CNT__UNUSED_MASK = 0xFFF00000 # macro +SPI_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +SPI_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +SPI_UE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +SPI_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +SPI_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +SPI_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +SPI_UE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +SPI_UE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +SPI_UE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +SPI_UE_ERR_STATUS_HI__PARITY__SHIFT = 0x1 # macro +SPI_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +SPI_UE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +SPI_UE_ERR_STATUS_HI__UE_CNT__SHIFT = 0x17 # macro +SPI_UE_ERR_STATUS_HI__FED_CNT__SHIFT = 0x1a # macro +SPI_UE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1d # macro +SPI_UE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +SPI_UE_ERR_STATUS_HI__PARITY_MASK = 0x00000002 # macro +SPI_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +SPI_UE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +SPI_UE_ERR_STATUS_HI__UE_CNT_MASK = 0x03800000 # macro +SPI_UE_ERR_STATUS_HI__FED_CNT_MASK = 0x1C000000 # macro +SPI_UE_ERR_STATUS_HI__RESERVED_MASK = 0xE0000000 # macro +SPI_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +SPI_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +SPI_CE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +SPI_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +SPI_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +SPI_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +SPI_CE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +SPI_CE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +SPI_CE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +SPI_CE_ERR_STATUS_HI__OTHER__SHIFT = 0x1 # macro +SPI_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +SPI_CE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +SPI_CE_ERR_STATUS_HI__CE_CNT__SHIFT = 0x17 # macro +SPI_CE_ERR_STATUS_HI__POISON__SHIFT = 0x1a # macro +SPI_CE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1b # macro +SPI_CE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +SPI_CE_ERR_STATUS_HI__OTHER_MASK = 0x00000002 # macro +SPI_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +SPI_CE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +SPI_CE_ERR_STATUS_HI__CE_CNT_MASK = 0x03800000 # macro +SPI_CE_ERR_STATUS_HI__POISON_MASK = 0x04000000 # macro +SPI_CE_ERR_STATUS_HI__RESERVED_MASK = 0xF8000000 # macro +SPI_DEBUG_BUSY__HS_BUSY__SHIFT = 0x0 # macro +SPI_DEBUG_BUSY__GS_BUSY__SHIFT = 0x1 # macro +SPI_DEBUG_BUSY__VS_BUSY__SHIFT = 0x2 # macro +SPI_DEBUG_BUSY__PS0_BUSY__SHIFT = 0x3 # macro +SPI_DEBUG_BUSY__PS1_BUSY__SHIFT = 0x4 # macro +SPI_DEBUG_BUSY__CSG_BUSY__SHIFT = 0x5 # macro +SPI_DEBUG_BUSY__CS0_BUSY__SHIFT = 0x6 # macro +SPI_DEBUG_BUSY__CS1_BUSY__SHIFT = 0x7 # macro +SPI_DEBUG_BUSY__CS2_BUSY__SHIFT = 0x8 # macro +SPI_DEBUG_BUSY__CS3_BUSY__SHIFT = 0x9 # macro +SPI_DEBUG_BUSY__CS4_BUSY__SHIFT = 0xa # macro +SPI_DEBUG_BUSY__CS5_BUSY__SHIFT = 0xb # macro +SPI_DEBUG_BUSY__CS6_BUSY__SHIFT = 0xc # macro +SPI_DEBUG_BUSY__CS7_BUSY__SHIFT = 0xd # macro +SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT = 0xe # macro +SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT = 0xf # macro +SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT = 0x10 # macro +SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT = 0x11 # macro +SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT = 0x12 # macro +SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT = 0x13 # macro +SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT = 0x14 # macro +SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT = 0x15 # macro +SPI_DEBUG_BUSY__HS_BUSY_MASK = 0x00000001 # macro +SPI_DEBUG_BUSY__GS_BUSY_MASK = 0x00000002 # macro +SPI_DEBUG_BUSY__VS_BUSY_MASK = 0x00000004 # macro +SPI_DEBUG_BUSY__PS0_BUSY_MASK = 0x00000008 # macro +SPI_DEBUG_BUSY__PS1_BUSY_MASK = 0x00000010 # macro +SPI_DEBUG_BUSY__CSG_BUSY_MASK = 0x00000020 # macro +SPI_DEBUG_BUSY__CS0_BUSY_MASK = 0x00000040 # macro +SPI_DEBUG_BUSY__CS1_BUSY_MASK = 0x00000080 # macro +SPI_DEBUG_BUSY__CS2_BUSY_MASK = 0x00000100 # macro +SPI_DEBUG_BUSY__CS3_BUSY_MASK = 0x00000200 # macro +SPI_DEBUG_BUSY__CS4_BUSY_MASK = 0x00000400 # macro +SPI_DEBUG_BUSY__CS5_BUSY_MASK = 0x00000800 # macro +SPI_DEBUG_BUSY__CS6_BUSY_MASK = 0x00001000 # macro +SPI_DEBUG_BUSY__CS7_BUSY_MASK = 0x00002000 # macro +SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK = 0x00004000 # macro +SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK = 0x00008000 # macro +SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK = 0x00010000 # macro +SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK = 0x00020000 # macro +SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK = 0x00040000 # macro +SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK = 0x00080000 # macro +SPI_DEBUG_BUSY__GRBM_BUSY_MASK = 0x00100000 # macro +SPI_DEBUG_BUSY__SPIS_BUSY_MASK = 0x00200000 # macro +SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT = 0x0 # macro +SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT = 0x1 # macro +SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT = 0x10 # macro +SPI_CONFIG_PS_CU_EN__ENABLE_MASK = 0x00000001 # macro +SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK = 0x0000FFFE # macro +SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK = 0xFFFF0000 # macro +SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_CNTL__EN__SHIFT = 0x4 # macro +SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK = 0x0000000F # macro +SPI_WF_LIFETIME_CNTL__EN_MASK = 0x00000010 # macro +SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK = 0x80000000 # macro +SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT = 0x0 # macro +SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT = 0x1f # macro +SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK = 0x7FFFFFFF # macro +SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK = 0x80000000 # macro +SPI_LB_CTR_CTRL__LOAD__SHIFT = 0x0 # macro +SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT = 0x1 # macro +SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT = 0x3 # macro +SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT = 0x4 # macro +SPI_LB_CTR_CTRL__LOAD_MASK = 0x00000001 # macro +SPI_LB_CTR_CTRL__WAVES_SELECT_MASK = 0x00000006 # macro +SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK = 0x00000008 # macro +SPI_LB_CTR_CTRL__RESET_COUNTS_MASK = 0x00000010 # macro +SPI_LB_CU_MASK__CU_MASK__SHIFT = 0x0 # macro +SPI_LB_CU_MASK__CU_MASK_MASK = 0xFFFF # macro +SPI_LB_DATA_REG__CNT_DATA__SHIFT = 0x0 # macro +SPI_LB_DATA_REG__CNT_DATA_MASK = 0xFFFFFFFF # macro +SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT = 0x0 # macro +SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK = 0xFFFF # macro +SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT = 0x0 # macro +SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT = 0x8 # macro +SPI_GDS_CREDITS__UNUSED__SHIFT = 0x10 # macro +SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK = 0x000000FF # macro +SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK = 0x0000FF00 # macro +SPI_GDS_CREDITS__UNUSED_MASK = 0xFFFF0000 # macro +SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT = 0x0 # macro +SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT = 0x10 # macro +SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK = 0x0000FFFF # macro +SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK = 0xFFFF0000 # macro +SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT = 0x0 # macro +SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT = 0x10 # macro +SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK = 0x0000FFFF # macro +SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK = 0xFFFF0000 # macro +SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT = 0x0 # macro +SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK = 0xFFFFFFFF # macro +SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT = 0x0 # macro +SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT = 0x10 # macro +SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK = 0x000001FF # macro +SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK = 0x01FF0000 # macro +SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT = 0x0 # macro +SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT = 0x10 # macro +SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK = 0x000001FF # macro +SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK = 0x01FF0000 # macro +SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT = 0x0 # macro +SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT = 0x10 # macro +SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK = 0x000001FF # macro +SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK = 0x01FF0000 # macro +SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT = 0x0 # macro +SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT = 0x10 # macro +SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK = 0x000001FF # macro +SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK = 0x01FF0000 # macro +SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT = 0x0 # macro +SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT = 0x10 # macro +SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK = 0x000001FF # macro +SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK = 0x01FF0000 # macro +SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT = 0x0 # macro +SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT = 0x10 # macro +SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK = 0x000001FF # macro +SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK = 0x01FF0000 # macro +SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT = 0x0 # macro +SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT = 0x10 # macro +SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK = 0x000001FF # macro +SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK = 0x01FF0000 # macro +SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT = 0x0 # macro +SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT = 0x10 # macro +SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK = 0x000001FF # macro +SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK = 0x01FF0000 # macro +SPI_LB_DATA_WAVES__COUNT0__SHIFT = 0x0 # macro +SPI_LB_DATA_WAVES__COUNT1__SHIFT = 0x10 # macro +SPI_LB_DATA_WAVES__COUNT0_MASK = 0x0000FFFF # macro +SPI_LB_DATA_WAVES__COUNT1_MASK = 0xFFFF0000 # macro +SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT = 0x0 # macro +SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT = 0x10 # macro +SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK = 0x0000FFFF # macro +SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK = 0xFFFF0000 # macro +SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT = 0x0 # macro +SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT = 0x10 # macro +SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK = 0x0000FFFF # macro +SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK = 0xFFFF0000 # macro +SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT = 0x0 # macro +SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK = 0xFFFF # macro +SPIS_DEBUG_READ__DATA__SHIFT = 0x0 # macro +SPIS_DEBUG_READ__DATA_MASK = 0xFFFFFFFF # macro +BCI_DEBUG_READ__DATA__SHIFT = 0x0 # macro +BCI_DEBUG_READ__DATA_MASK = 0xFFFFFF # macro +SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT = 0x0 # macro +SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT = 0x0 # macro +SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK = 0xFF # macro +SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT = 0x0 # macro +SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT = 0x0 # macro +SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK = 0xFF # macro +SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT = 0x0 # macro +SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT = 0x6 # macro +SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK = 0x003F # macro +SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK = 0x03C0 # macro +SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT = 0x0 # macro +SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT = 0x0 # macro +SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK = 0xFF # macro +SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT = 0x0 # macro +SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT = 0x0 # macro +SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK = 0xFF # macro +SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT = 0x0 # macro +SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT = 0x6 # macro +SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK = 0x003F # macro +SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK = 0x03C0 # macro +TD_CNTL__SYNC_PHASE_SH__SHIFT = 0x0 # macro +TD_CNTL__TD_IN_CAC_CHICKENBITS__SHIFT = 0x2 # macro +TD_CNTL__TD_OUT_CAC_CHICKENBITS__SHIFT = 0x6 # macro +TD_CNTL__EXTEND_LDS_STALL__SHIFT = 0x9 # macro +TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT = 0xb # macro +TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT = 0x14 # macro +TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT = 0x15 # macro +TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT = 0x17 # macro +TD_CNTL__SRAM_FGCG_TD_KCLARR_LG__SHIFT = 0x1b # macro +TD_CNTL__RFGCG_CHICKEN__SHIFT = 0x1c # macro +TD_CNTL__SYNC_PHASE_SH_MASK = 0x00000003 # macro +TD_CNTL__TD_IN_CAC_CHICKENBITS_MASK = 0x0000000C # macro +TD_CNTL__TD_OUT_CAC_CHICKENBITS_MASK = 0x000000C0 # macro +TD_CNTL__EXTEND_LDS_STALL_MASK = 0x00000600 # macro +TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK = 0x00001800 # macro +TD_CNTL__DISABLE_POWER_THROTTLE_MASK = 0x00100000 # macro +TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK = 0x00200000 # macro +TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK = 0x00800000 # macro +TD_CNTL__SRAM_FGCG_TD_KCLARR_LG_MASK = 0x08000000 # macro +TD_CNTL__RFGCG_CHICKEN_MASK = 0x70000000 # macro +TD_STATUS__BUSY__SHIFT = 0x1f # macro +TD_STATUS__BUSY_MASK = 0x80000000 # macro +TD_POWER_CNTL__MGCG_OUTPUTSTAGE__SHIFT = 0x1 # macro +TD_POWER_CNTL__MID0_THREAD_DATA__SHIFT = 0x2 # macro +TD_POWER_CNTL__MID2_ACCUM_DATA__SHIFT = 0x3 # macro +TD_POWER_CNTL__MGCG_OUTPUTSTAGE_MASK = 0x00000002 # macro +TD_POWER_CNTL__MID0_THREAD_DATA_MASK = 0x00000004 # macro +TD_POWER_CNTL__MID2_ACCUM_DATA_MASK = 0x00000008 # macro +TD_UE_EDC_LO__STATUS_VALID_FLAG__SHIFT = 0x0 # macro +TD_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT = 0x1 # macro +TD_UE_EDC_LO__ADDRESS__SHIFT = 0x2 # macro +TD_UE_EDC_LO__MEM_ID__SHIFT = 0x18 # macro +TD_UE_EDC_LO__STATUS_VALID_FLAG_MASK = 0x00000001 # macro +TD_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK = 0x00000002 # macro +TD_UE_EDC_LO__ADDRESS_MASK = 0x00FFFFFC # macro +TD_UE_EDC_LO__MEM_ID_MASK = 0xFF000000 # macro +TD_UE_EDC_HI__ECC__SHIFT = 0x0 # macro +TD_UE_EDC_HI__PARITY__SHIFT = 0x1 # macro +TD_UE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +TD_UE_EDC_HI__ERR_INFO__SHIFT = 0x3 # macro +TD_UE_EDC_HI__UE_CNT__SHIFT = 0x17 # macro +TD_UE_EDC_HI__FED_CNT__SHIFT = 0x1a # macro +TD_UE_EDC_HI__ECC_MASK = 0x00000001 # macro +TD_UE_EDC_HI__PARITY_MASK = 0x00000002 # macro +TD_UE_EDC_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +TD_UE_EDC_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +TD_UE_EDC_HI__UE_CNT_MASK = 0x03800000 # macro +TD_UE_EDC_HI__FED_CNT_MASK = 0x1C000000 # macro +TD_CE_EDC_LO__STATUS_VALID_FLAG__SHIFT = 0x0 # macro +TD_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT = 0x1 # macro +TD_CE_EDC_LO__ADDRESS__SHIFT = 0x2 # macro +TD_CE_EDC_LO__MEM_ID__SHIFT = 0x18 # macro +TD_CE_EDC_LO__STATUS_VALID_FLAG_MASK = 0x00000001 # macro +TD_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK = 0x00000002 # macro +TD_CE_EDC_LO__ADDRESS_MASK = 0x00FFFFFC # macro +TD_CE_EDC_LO__MEM_ID_MASK = 0xFF000000 # macro +TD_CE_EDC_HI__ECC__SHIFT = 0x0 # macro +TD_CE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +TD_CE_EDC_HI__ERR_INFO__SHIFT = 0x3 # macro +TD_CE_EDC_HI__CE_CNT__SHIFT = 0x17 # macro +TD_CE_EDC_HI__POISON__SHIFT = 0x1a # macro +TD_CE_EDC_HI__ECC_MASK = 0x00000001 # macro +TD_CE_EDC_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +TD_CE_EDC_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +TD_CE_EDC_HI__CE_CNT_MASK = 0x03800000 # macro +TD_CE_EDC_HI__POISON_MASK = 0x04000000 # macro +TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT = 0x0 # macro +TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT = 0x2 # macro +TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT = 0x3 # macro +TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT = 0x5 # macro +TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT = 0x6 # macro +TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT = 0x8 # macro +TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK = 0x00000003 # macro +TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK = 0x00000004 # macro +TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK = 0x00000018 # macro +TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK = 0x00000020 # macro +TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK = 0x000000C0 # macro +TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK = 0x00000100 # macro +TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT = 0x6 # macro +TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT = 0x8 # macro +TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT = 0x1a # macro +TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK = 0x000000C0 # macro +TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK = 0x00000100 # macro +TD_DSM_CNTL2__TD_INJECT_DELAY_MASK = 0xFC000000 # macro +TD_SCRATCH__SCRATCH__SHIFT = 0x0 # macro +TD_SCRATCH__SCRATCH_MASK = 0xFFFFFFFF # macro +TA_POWER_CNTL__INPUT_CLK_EN_MODE__SHIFT = 0x0 # macro +TA_POWER_CNTL__LOD_CLK_EN_MODE__SHIFT = 0x1 # macro +TA_POWER_CNTL__WDP_CLK_EN_MODE__SHIFT = 0x2 # macro +TA_POWER_CNTL__INPUT_CLK_EN_MODE_MASK = 0x00000001 # macro +TA_POWER_CNTL__LOD_CLK_EN_MODE_MASK = 0x00000002 # macro +TA_POWER_CNTL__WDP_CLK_EN_MODE_MASK = 0x00000004 # macro +TA_CNTL__FX_XNACK_CREDIT__SHIFT = 0x0 # macro +TA_CNTL__SQ_XNACK_CREDIT__SHIFT = 0x9 # macro +TA_CNTL__TC_DATA_CREDIT__SHIFT = 0xd # macro +TA_CNTL__ALIGNER_CREDIT__SHIFT = 0x10 # macro +TA_CNTL__TD_FIFO_CREDIT__SHIFT = 0x16 # macro +TA_CNTL__FX_XNACK_CREDIT_MASK = 0x0000007F # macro +TA_CNTL__SQ_XNACK_CREDIT_MASK = 0x00001E00 # macro +TA_CNTL__TC_DATA_CREDIT_MASK = 0x0000E000 # macro +TA_CNTL__ALIGNER_CREDIT_MASK = 0x001F0000 # macro +TA_CNTL__TD_FIFO_CREDIT_MASK = 0xFFC00000 # macro +TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT = 0x0 # macro +TA_CNTL_AUX__RESERVED__SHIFT = 0x1 # macro +TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT = 0x5 # macro +TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT = 0x7 # macro +TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT = 0x14 # macro +TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT = 0x15 # macro +TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT = 0x16 # macro +TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT = 0x17 # macro +TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT = 0x18 # macro +TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT = 0x19 # macro +TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT = 0x1a # macro +TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK = 0x00000001 # macro +TA_CNTL_AUX__RESERVED_MASK = 0x0000000E # macro +TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK = 0x00000020 # macro +TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK = 0x00000080 # macro +TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK = 0x00100000 # macro +TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK = 0x00200000 # macro +TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK = 0x00400000 # macro +TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK = 0x00800000 # macro +TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK = 0x01000000 # macro +TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK = 0x02000000 # macro +TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK = 0x04000000 # macro +TA_FEATURE_CNTL__ATOMIC_COALESCING_EN__SHIFT = 0x4 # macro +TA_FEATURE_CNTL__TA_ACFIFO_CHICKEN__SHIFT = 0xb # macro +TA_FEATURE_CNTL__TA_CAC_CHICKEN__SHIFT = 0xc # macro +TA_FEATURE_CNTL__AFIFO_SPLIT_CHICKEN__SHIFT = 0xd # macro +TA_FEATURE_CNTL__TA_DXFIFO_CHICKEN__SHIFT = 0xe # macro +TA_FEATURE_CNTL__ATOMIC_COALESCING_EN_MASK = 0x00000030 # macro +TA_FEATURE_CNTL__TA_ACFIFO_CHICKEN_MASK = 0x00000800 # macro +TA_FEATURE_CNTL__TA_CAC_CHICKEN_MASK = 0x00001000 # macro +TA_FEATURE_CNTL__AFIFO_SPLIT_CHICKEN_MASK = 0x00002000 # macro +TA_FEATURE_CNTL__TA_DXFIFO_CHICKEN_MASK = 0x00004000 # macro +TA_STATUS__FG_PFIFO_EMPTYB__SHIFT = 0xc # macro +TA_STATUS__FL_PFIFO_EMPTYB__SHIFT = 0x10 # macro +TA_STATUS__FA_PFIFO_EMPTYB__SHIFT = 0x14 # macro +TA_STATUS__IN_BUSY__SHIFT = 0x18 # macro +TA_STATUS__FG_BUSY__SHIFT = 0x19 # macro +TA_STATUS__TA_BUSY__SHIFT = 0x1c # macro +TA_STATUS__FA_BUSY__SHIFT = 0x1d # macro +TA_STATUS__AL_BUSY__SHIFT = 0x1e # macro +TA_STATUS__BUSY__SHIFT = 0x1f # macro +TA_STATUS__FG_PFIFO_EMPTYB_MASK = 0x00001000 # macro +TA_STATUS__FL_PFIFO_EMPTYB_MASK = 0x00010000 # macro +TA_STATUS__FA_PFIFO_EMPTYB_MASK = 0x00100000 # macro +TA_STATUS__IN_BUSY_MASK = 0x01000000 # macro +TA_STATUS__FG_BUSY_MASK = 0x02000000 # macro +TA_STATUS__TA_BUSY_MASK = 0x10000000 # macro +TA_STATUS__FA_BUSY_MASK = 0x20000000 # macro +TA_STATUS__AL_BUSY_MASK = 0x40000000 # macro +TA_STATUS__BUSY_MASK = 0x80000000 # macro +TA_SCRATCH__SCRATCH__SHIFT = 0x0 # macro +TA_SCRATCH__SCRATCH_MASK = 0xFFFFFFFF # macro +TA_DSM_CNTL__TA_FS_DFIFO_DSM_IRRITATOR_DATA__SHIFT = 0x0 # macro +TA_DSM_CNTL__TA_FS_DFIFO_ENABLE_SINGLE_WRITE__SHIFT = 0x2 # macro +TA_DSM_CNTL__TA_FX_LFIFO_DSM_IRRITATOR_DATA__SHIFT = 0x9 # macro +TA_DSM_CNTL__TA_FX_LFIFO_ENABLE_SINGLE_WRITE__SHIFT = 0xb # macro +TA_DSM_CNTL__TA_FS_CFIFO_DSM_IRRITATOR_DATA__SHIFT = 0xc # macro +TA_DSM_CNTL__TA_FS_CFIFO_ENABLE_SINGLE_WRITE__SHIFT = 0xe # macro +TA_DSM_CNTL__TA_FS_AFIFO_LO_DSM_IRRITATOR_DATA__SHIFT = 0xf # macro +TA_DSM_CNTL__TA_FS_AFIFO_LO_ENABLE_SINGLE_WRITE__SHIFT = 0x11 # macro +TA_DSM_CNTL__TA_FS_AFIFO_HI_DSM_IRRITATOR_DATA__SHIFT = 0x12 # macro +TA_DSM_CNTL__TA_FS_AFIFO_HI_ENABLE_SINGLE_WRITE__SHIFT = 0x14 # macro +TA_DSM_CNTL__TA_FS_DFIFO_DSM_IRRITATOR_DATA_MASK = 0x00000003 # macro +TA_DSM_CNTL__TA_FS_DFIFO_ENABLE_SINGLE_WRITE_MASK = 0x00000004 # macro +TA_DSM_CNTL__TA_FX_LFIFO_DSM_IRRITATOR_DATA_MASK = 0x00000600 # macro +TA_DSM_CNTL__TA_FX_LFIFO_ENABLE_SINGLE_WRITE_MASK = 0x00000800 # macro +TA_DSM_CNTL__TA_FS_CFIFO_DSM_IRRITATOR_DATA_MASK = 0x00003000 # macro +TA_DSM_CNTL__TA_FS_CFIFO_ENABLE_SINGLE_WRITE_MASK = 0x00004000 # macro +TA_DSM_CNTL__TA_FS_AFIFO_LO_DSM_IRRITATOR_DATA_MASK = 0x00018000 # macro +TA_DSM_CNTL__TA_FS_AFIFO_LO_ENABLE_SINGLE_WRITE_MASK = 0x00020000 # macro +TA_DSM_CNTL__TA_FS_AFIFO_HI_DSM_IRRITATOR_DATA_MASK = 0x000C0000 # macro +TA_DSM_CNTL__TA_FS_AFIFO_HI_ENABLE_SINGLE_WRITE_MASK = 0x00100000 # macro +TA_DSM_CNTL2__TA_FS_DFIFO_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +TA_DSM_CNTL2__TA_FS_DFIFO_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +TA_DSM_CNTL2__TA_FX_LFIFO_ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +TA_DSM_CNTL2__TA_FX_LFIFO_SELECT_INJECT_DELAY__SHIFT = 0xb # macro +TA_DSM_CNTL2__TA_FS_CFIFO_ENABLE_ERROR_INJECT__SHIFT = 0xc # macro +TA_DSM_CNTL2__TA_FS_CFIFO_SELECT_INJECT_DELAY__SHIFT = 0xe # macro +TA_DSM_CNTL2__TA_FS_AFIFO_LO_ENABLE_ERROR_INJECT__SHIFT = 0xf # macro +TA_DSM_CNTL2__TA_FS_AFIFO_LO_SELECT_INJECT_DELAY__SHIFT = 0x11 # macro +TA_DSM_CNTL2__TA_FS_AFIFO_HI_ENABLE_ERROR_INJECT__SHIFT = 0x12 # macro +TA_DSM_CNTL2__TA_FS_AFIFO_HI_SELECT_INJECT_DELAY__SHIFT = 0x14 # macro +TA_DSM_CNTL2__TA_INJECT_DELAY__SHIFT = 0x1a # macro +TA_DSM_CNTL2__TA_FS_DFIFO_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +TA_DSM_CNTL2__TA_FS_DFIFO_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +TA_DSM_CNTL2__TA_FX_LFIFO_ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +TA_DSM_CNTL2__TA_FX_LFIFO_SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +TA_DSM_CNTL2__TA_FS_CFIFO_ENABLE_ERROR_INJECT_MASK = 0x00003000 # macro +TA_DSM_CNTL2__TA_FS_CFIFO_SELECT_INJECT_DELAY_MASK = 0x00004000 # macro +TA_DSM_CNTL2__TA_FS_AFIFO_LO_ENABLE_ERROR_INJECT_MASK = 0x00018000 # macro +TA_DSM_CNTL2__TA_FS_AFIFO_LO_SELECT_INJECT_DELAY_MASK = 0x00020000 # macro +TA_DSM_CNTL2__TA_FS_AFIFO_HI_ENABLE_ERROR_INJECT_MASK = 0x000C0000 # macro +TA_DSM_CNTL2__TA_FS_AFIFO_HI_SELECT_INJECT_DELAY_MASK = 0x00100000 # macro +TA_DSM_CNTL2__TA_INJECT_DELAY_MASK = 0xFC000000 # macro +TA_UE_EDC_LO__STATUS_VALID_FLAG__SHIFT = 0x0 # macro +TA_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT = 0x1 # macro +TA_UE_EDC_LO__ADDRESS__SHIFT = 0x2 # macro +TA_UE_EDC_LO__MEM_ID__SHIFT = 0x18 # macro +TA_UE_EDC_LO__STATUS_VALID_FLAG_MASK = 0x00000001 # macro +TA_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK = 0x00000002 # macro +TA_UE_EDC_LO__ADDRESS_MASK = 0x00FFFFFC # macro +TA_UE_EDC_LO__MEM_ID_MASK = 0xFF000000 # macro +TA_UE_EDC_HI__ECC__SHIFT = 0x0 # macro +TA_UE_EDC_HI__PARITY__SHIFT = 0x1 # macro +TA_UE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +TA_UE_EDC_HI__ERR_INFO__SHIFT = 0x3 # macro +TA_UE_EDC_HI__UE_CNT__SHIFT = 0x17 # macro +TA_UE_EDC_HI__FED_CNT__SHIFT = 0x1a # macro +TA_UE_EDC_HI__ECC_MASK = 0x00000001 # macro +TA_UE_EDC_HI__PARITY_MASK = 0x00000002 # macro +TA_UE_EDC_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +TA_UE_EDC_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +TA_UE_EDC_HI__UE_CNT_MASK = 0x03800000 # macro +TA_UE_EDC_HI__FED_CNT_MASK = 0x1C000000 # macro +TA_CE_EDC_LO__STATUS_VALID_FLAG__SHIFT = 0x0 # macro +TA_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT = 0x1 # macro +TA_CE_EDC_LO__ADDRESS__SHIFT = 0x2 # macro +TA_CE_EDC_LO__MEM_ID__SHIFT = 0x18 # macro +TA_CE_EDC_LO__STATUS_VALID_FLAG_MASK = 0x00000001 # macro +TA_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK = 0x00000002 # macro +TA_CE_EDC_LO__ADDRESS_MASK = 0x00FFFFFC # macro +TA_CE_EDC_LO__MEM_ID_MASK = 0xFF000000 # macro +TA_CE_EDC_HI__ECC__SHIFT = 0x0 # macro +TA_CE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +TA_CE_EDC_HI__ERR_INFO__SHIFT = 0x3 # macro +TA_CE_EDC_HI__CE_CNT__SHIFT = 0x17 # macro +TA_CE_EDC_HI__POISON__SHIFT = 0x1a # macro +TA_CE_EDC_HI__ECC_MASK = 0x00000001 # macro +TA_CE_EDC_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +TA_CE_EDC_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +TA_CE_EDC_HI__CE_CNT_MASK = 0x03800000 # macro +TA_CE_EDC_HI__POISON_MASK = 0x04000000 # macro +GDS_CONFIG__WRITE_DIS__SHIFT = 0x0 # macro +GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT = 0x1 # macro +GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT = 0x3 # macro +GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT = 0x5 # macro +GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT = 0x7 # macro +GDS_CONFIG__SH4_GPR_PHASE_SEL__SHIFT = 0x9 # macro +GDS_CONFIG__SH5_GPR_PHASE_SEL__SHIFT = 0xb # macro +GDS_CONFIG__SH6_GPR_PHASE_SEL__SHIFT = 0xd # macro +GDS_CONFIG__SH7_GPR_PHASE_SEL__SHIFT = 0xf # macro +GDS_CONFIG__WRITE_DIS_MASK = 0x00000001 # macro +GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK = 0x00000006 # macro +GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK = 0x00000018 # macro +GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK = 0x00000060 # macro +GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK = 0x00000180 # macro +GDS_CONFIG__SH4_GPR_PHASE_SEL_MASK = 0x00000600 # macro +GDS_CONFIG__SH5_GPR_PHASE_SEL_MASK = 0x00001800 # macro +GDS_CONFIG__SH6_GPR_PHASE_SEL_MASK = 0x00006000 # macro +GDS_CONFIG__SH7_GPR_PHASE_SEL_MASK = 0x00018000 # macro +GDS_CNTL_STATUS__GDS_BUSY__SHIFT = 0x0 # macro +GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT = 0x1 # macro +GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT = 0x2 # macro +GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT = 0x3 # macro +GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT = 0x4 # macro +GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT = 0x5 # macro +GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT = 0x6 # macro +GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT = 0x7 # macro +GDS_CNTL_STATUS__DS_BUSY__SHIFT = 0x8 # macro +GDS_CNTL_STATUS__GWS_BUSY__SHIFT = 0x9 # macro +GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT = 0xa # macro +GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT = 0xb # macro +GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT = 0xc # macro +GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT = 0xd # macro +GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT = 0xe # macro +GDS_CNTL_STATUS__CREDIT_BUSY4__SHIFT = 0xf # macro +GDS_CNTL_STATUS__CREDIT_BUSY5__SHIFT = 0x10 # macro +GDS_CNTL_STATUS__CREDIT_BUSY6__SHIFT = 0x11 # macro +GDS_CNTL_STATUS__CREDIT_BUSY7__SHIFT = 0x12 # macro +GDS_CNTL_STATUS__GDS_BUSY_MASK = 0x00000001 # macro +GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK = 0x00000002 # macro +GDS_CNTL_STATUS__ORD_APP_BUSY_MASK = 0x00000004 # macro +GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK = 0x00000008 # macro +GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK = 0x00000010 # macro +GDS_CNTL_STATUS__DS_WR_CLAMP_MASK = 0x00000020 # macro +GDS_CNTL_STATUS__DS_RD_CLAMP_MASK = 0x00000040 # macro +GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK = 0x00000080 # macro +GDS_CNTL_STATUS__DS_BUSY_MASK = 0x00000100 # macro +GDS_CNTL_STATUS__GWS_BUSY_MASK = 0x00000200 # macro +GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK = 0x00000400 # macro +GDS_CNTL_STATUS__CREDIT_BUSY0_MASK = 0x00000800 # macro +GDS_CNTL_STATUS__CREDIT_BUSY1_MASK = 0x00001000 # macro +GDS_CNTL_STATUS__CREDIT_BUSY2_MASK = 0x00002000 # macro +GDS_CNTL_STATUS__CREDIT_BUSY3_MASK = 0x00004000 # macro +GDS_CNTL_STATUS__CREDIT_BUSY4_MASK = 0x00008000 # macro +GDS_CNTL_STATUS__CREDIT_BUSY5_MASK = 0x00010000 # macro +GDS_CNTL_STATUS__CREDIT_BUSY6_MASK = 0x00020000 # macro +GDS_CNTL_STATUS__CREDIT_BUSY7_MASK = 0x00040000 # macro +GDS_ENHANCE2__MISC__SHIFT = 0x0 # macro +GDS_ENHANCE2__GDS_TD_INTERFACES_FGCG_OVERRIDE__SHIFT = 0x10 # macro +GDS_ENHANCE2__GDS_PHY_CMD_RAM_FGCG_OVERRIDE__SHIFT = 0x11 # macro +GDS_ENHANCE2__GDS_FED_IN_PROPAGATE__SHIFT = 0x12 # macro +GDS_ENHANCE2__UNUSED__SHIFT = 0x13 # macro +GDS_ENHANCE2__MISC_MASK = 0x0000FFFF # macro +GDS_ENHANCE2__GDS_TD_INTERFACES_FGCG_OVERRIDE_MASK = 0x00010000 # macro +GDS_ENHANCE2__GDS_PHY_CMD_RAM_FGCG_OVERRIDE_MASK = 0x00020000 # macro +GDS_ENHANCE2__GDS_FED_IN_PROPAGATE_MASK = 0x00040000 # macro +GDS_ENHANCE2__UNUSED_MASK = 0xFFF80000 # macro +GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT = 0x0 # macro +GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT = 0x1 # macro +GDS_PROTECTION_FAULT__GRBM__SHIFT = 0x2 # macro +GDS_PROTECTION_FAULT__SH_ID__SHIFT = 0x3 # macro +GDS_PROTECTION_FAULT__CU_ID__SHIFT = 0x6 # macro +GDS_PROTECTION_FAULT__SIMD_ID__SHIFT = 0xa # macro +GDS_PROTECTION_FAULT__WAVE_ID__SHIFT = 0xc # macro +GDS_PROTECTION_FAULT__ADDRESS__SHIFT = 0x10 # macro +GDS_PROTECTION_FAULT__WRITE_DIS_MASK = 0x00000001 # macro +GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK = 0x00000002 # macro +GDS_PROTECTION_FAULT__GRBM_MASK = 0x00000004 # macro +GDS_PROTECTION_FAULT__SH_ID_MASK = 0x00000038 # macro +GDS_PROTECTION_FAULT__CU_ID_MASK = 0x000003C0 # macro +GDS_PROTECTION_FAULT__SIMD_ID_MASK = 0x00000C00 # macro +GDS_PROTECTION_FAULT__WAVE_ID_MASK = 0x0000F000 # macro +GDS_PROTECTION_FAULT__ADDRESS_MASK = 0xFFFF0000 # macro +GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT = 0x0 # macro +GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT = 0x1 # macro +GDS_VM_PROTECTION_FAULT__GWS__SHIFT = 0x2 # macro +GDS_VM_PROTECTION_FAULT__OA__SHIFT = 0x3 # macro +GDS_VM_PROTECTION_FAULT__GRBM__SHIFT = 0x4 # macro +GDS_VM_PROTECTION_FAULT__TMZ__SHIFT = 0x5 # macro +GDS_VM_PROTECTION_FAULT__VMID__SHIFT = 0x8 # macro +GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT = 0x10 # macro +GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK = 0x00000001 # macro +GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK = 0x00000002 # macro +GDS_VM_PROTECTION_FAULT__GWS_MASK = 0x00000004 # macro +GDS_VM_PROTECTION_FAULT__OA_MASK = 0x00000008 # macro +GDS_VM_PROTECTION_FAULT__GRBM_MASK = 0x00000010 # macro +GDS_VM_PROTECTION_FAULT__TMZ_MASK = 0x00000020 # macro +GDS_VM_PROTECTION_FAULT__VMID_MASK = 0x00000F00 # macro +GDS_VM_PROTECTION_FAULT__ADDRESS_MASK = 0xFFFF0000 # macro +GDS_EDC_CNT__GDS_MEM_DED__SHIFT = 0x0 # macro +GDS_EDC_CNT__GDS_MEM_SEC__SHIFT = 0x4 # macro +GDS_EDC_CNT__UNUSED__SHIFT = 0x6 # macro +GDS_EDC_CNT__GDS_MEM_DED_MASK = 0x00000003 # macro +GDS_EDC_CNT__GDS_MEM_SEC_MASK = 0x00000030 # macro +GDS_EDC_CNT__UNUSED_MASK = 0xFFFFFFC0 # macro +GDS_EDC_GRBM_CNT__DED__SHIFT = 0x0 # macro +GDS_EDC_GRBM_CNT__SEC__SHIFT = 0x2 # macro +GDS_EDC_GRBM_CNT__UNUSED__SHIFT = 0x4 # macro +GDS_EDC_GRBM_CNT__DED_MASK = 0x00000003 # macro +GDS_EDC_GRBM_CNT__SEC_MASK = 0x0000000C # macro +GDS_EDC_GRBM_CNT__UNUSED_MASK = 0xFFFFFFF0 # macro +GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT = 0x0 # macro +GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT = 0x1 # macro +GDS_EDC_OA_DED__ME0_CS_DED__SHIFT = 0x2 # macro +GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT = 0x3 # macro +GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT = 0x4 # macro +GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT = 0x5 # macro +GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT = 0x6 # macro +GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT = 0x7 # macro +GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT = 0x8 # macro +GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT = 0x9 # macro +GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT = 0xa # macro +GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT = 0xb # macro +GDS_EDC_OA_DED__UNUSED1__SHIFT = 0xc # macro +GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK = 0x00000001 # macro +GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK = 0x00000002 # macro +GDS_EDC_OA_DED__ME0_CS_DED_MASK = 0x00000004 # macro +GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK = 0x00000008 # macro +GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK = 0x00000010 # macro +GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK = 0x00000020 # macro +GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK = 0x00000040 # macro +GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK = 0x00000080 # macro +GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK = 0x00000100 # macro +GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK = 0x00000200 # macro +GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK = 0x00000400 # macro +GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK = 0x00000800 # macro +GDS_EDC_OA_DED__UNUSED1_MASK = 0xFFFFF000 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT = 0x0 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT = 0x1 # macro +GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT = 0x2 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT = 0x3 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT = 0x4 # macro +GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT = 0x5 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT = 0x6 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT = 0x7 # macro +GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT = 0x8 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT = 0x9 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT = 0xa # macro +GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT = 0xb # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT = 0xc # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT = 0xd # macro +GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT = 0xe # macro +GDS_DSM_CNTL__UNUSED__SHIFT = 0xf # macro +GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK = 0x00000001 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK = 0x00000002 # macro +GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK = 0x00000004 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK = 0x00000008 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK = 0x00000010 # macro +GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK = 0x00000020 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK = 0x00000040 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK = 0x00000080 # macro +GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK = 0x00000100 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK = 0x00000200 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK = 0x00000400 # macro +GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK = 0x00000800 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK = 0x00001000 # macro +GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK = 0x00002000 # macro +GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK = 0x00004000 # macro +GDS_DSM_CNTL__UNUSED_MASK = 0xFFFF8000 # macro +GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT = 0x0 # macro +GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT = 0x2 # macro +GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT = 0x4 # macro +GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT = 0x6 # macro +GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SEC__SHIFT = 0x8 # macro +GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_DED__SHIFT = 0xa # macro +GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT = 0xc # macro +GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK = 0x00000003 # macro +GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK = 0x0000000C # macro +GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK = 0x00000030 # macro +GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK = 0x000000C0 # macro +GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SEC_MASK = 0x00000300 # macro +GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_DED_MASK = 0x00000C00 # macro +GDS_EDC_OA_PHY_CNT__UNUSED1_MASK = 0xFFFFF000 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT = 0x0 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT = 0x2 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT = 0x4 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT = 0x6 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT = 0x8 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT = 0xa # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT = 0xc # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT = 0xe # macro +GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT = 0x10 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK = 0x00000003 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK = 0x0000000C # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK = 0x00000030 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK = 0x000000C0 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK = 0x00000300 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK = 0x00000C00 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK = 0x00003000 # macro +GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK = 0x0000C000 # macro +GDS_EDC_OA_PIPE_CNT__UNUSED_MASK = 0xFFFF0000 # macro +GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x6 # macro +GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT = 0x8 # macro +GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT = 0xb # macro +GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT = 0xc # macro +GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT = 0xe # macro +GDS_DSM_CNTL2__UNUSED__SHIFT = 0xf # macro +GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT = 0x1a # macro +GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK = 0x000000C0 # macro +GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK = 0x00000100 # macro +GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK = 0x00003000 # macro +GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK = 0x00004000 # macro +GDS_DSM_CNTL2__UNUSED_MASK = 0x03FF8000 # macro +GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK = 0xFC000000 # macro +GDS_WD_GDS_CSB__COUNTER__SHIFT = 0x0 # macro +GDS_WD_GDS_CSB__UNUSED__SHIFT = 0xd # macro +GDS_WD_GDS_CSB__COUNTER_MASK = 0x00001FFF # macro +GDS_WD_GDS_CSB__UNUSED_MASK = 0xFFFFE000 # macro +GDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +GDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +GDS_UE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +GDS_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +GDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +GDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +GDS_UE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +GDS_UE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +GDS_UE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +GDS_UE_ERR_STATUS_HI__PARITY__SHIFT = 0x1 # macro +GDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +GDS_UE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +GDS_UE_ERR_STATUS_HI__UE_CNT__SHIFT = 0x17 # macro +GDS_UE_ERR_STATUS_HI__FED_CNT__SHIFT = 0x1a # macro +GDS_UE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1d # macro +GDS_UE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +GDS_UE_ERR_STATUS_HI__PARITY_MASK = 0x00000002 # macro +GDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +GDS_UE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +GDS_UE_ERR_STATUS_HI__UE_CNT_MASK = 0x03800000 # macro +GDS_UE_ERR_STATUS_HI__FED_CNT_MASK = 0x1C000000 # macro +GDS_UE_ERR_STATUS_HI__RESERVED_MASK = 0xE0000000 # macro +GDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +GDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +GDS_CE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +GDS_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +GDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +GDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +GDS_CE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +GDS_CE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +GDS_CE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +GDS_CE_ERR_STATUS_HI__OTHER__SHIFT = 0x1 # macro +GDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +GDS_CE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +GDS_CE_ERR_STATUS_HI__CE_CNT__SHIFT = 0x17 # macro +GDS_CE_ERR_STATUS_HI__POISON__SHIFT = 0x1a # macro +GDS_CE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1b # macro +GDS_CE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +GDS_CE_ERR_STATUS_HI__OTHER_MASK = 0x00000002 # macro +GDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +GDS_CE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +GDS_CE_ERR_STATUS_HI__CE_CNT_MASK = 0x03800000 # macro +GDS_CE_ERR_STATUS_HI__POISON_MASK = 0x04000000 # macro +GDS_CE_ERR_STATUS_HI__RESERVED_MASK = 0xF8000000 # macro +DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT = 0x0 # macro +DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT = 0x1 # macro +DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT = 0x2 # macro +DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT = 0x3 # macro +DB_DEBUG__FORCE_Z_MODE__SHIFT = 0x4 # macro +DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT = 0x6 # macro +DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT = 0x7 # macro +DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT = 0x8 # macro +DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT = 0xa # macro +DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT = 0xc # macro +DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT = 0xe # macro +DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT = 0xf # macro +DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT = 0x10 # macro +DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT = 0x11 # macro +DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT = 0x12 # macro +DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT = 0x13 # macro +DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT = 0x15 # macro +DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT = 0x16 # macro +DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT = 0x17 # macro +DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT = 0x18 # macro +DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT = 0x1c # macro +DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT = 0x1d # macro +DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT = 0x1e # macro +DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT = 0x1f # macro +DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK = 0x00000001 # macro +DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK = 0x00000002 # macro +DB_DEBUG__FETCH_FULL_Z_TILE_MASK = 0x00000004 # macro +DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK = 0x00000008 # macro +DB_DEBUG__FORCE_Z_MODE_MASK = 0x00000030 # macro +DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK = 0x00000040 # macro +DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK = 0x00000080 # macro +DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK = 0x00000300 # macro +DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK = 0x00000C00 # macro +DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK = 0x00003000 # macro +DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK = 0x00004000 # macro +DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK = 0x00008000 # macro +DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK = 0x00010000 # macro +DB_DEBUG__DISABLE_SUMM_SQUADS_MASK = 0x00020000 # macro +DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK = 0x00040000 # macro +DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK = 0x00180000 # macro +DB_DEBUG__NEVER_FREE_Z_ONLY_MASK = 0x00200000 # macro +DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK = 0x00400000 # macro +DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK = 0x00800000 # macro +DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK = 0x0F000000 # macro +DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK = 0x10000000 # macro +DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK = 0x20000000 # macro +DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK = 0x40000000 # macro +DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK = 0x80000000 # macro +DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT = 0x0 # macro +DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT = 0x1 # macro +DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT = 0x2 # macro +DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT = 0x3 # macro +DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT = 0x4 # macro +DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT = 0x5 # macro +DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT = 0x6 # macro +DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT = 0x7 # macro +DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT = 0x8 # macro +DB_DEBUG2__CLK_OFF_DELAY__SHIFT = 0x9 # macro +DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT = 0xe # macro +DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT = 0xf # macro +DB_DEBUG2__RESERVED__SHIFT = 0x10 # macro +DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT = 0x11 # macro +DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT = 0x12 # macro +DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT = 0x13 # macro +DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID__SHIFT = 0x1a # macro +DB_DEBUG2__DISABLE_VR_PS_INVOKE__SHIFT = 0x1b # macro +DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT = 0x1c # macro +DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT = 0x1d # macro +DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT = 0x1e # macro +DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT = 0x1f # macro +DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK = 0x00000001 # macro +DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK = 0x00000002 # macro +DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK = 0x00000004 # macro +DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK = 0x00000008 # macro +DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK = 0x00000010 # macro +DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK = 0x00000020 # macro +DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK = 0x00000040 # macro +DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK = 0x00000080 # macro +DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK = 0x00000100 # macro +DB_DEBUG2__CLK_OFF_DELAY_MASK = 0x00003E00 # macro +DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK = 0x00004000 # macro +DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK = 0x00008000 # macro +DB_DEBUG2__RESERVED_MASK = 0x00010000 # macro +DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK = 0x00020000 # macro +DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK = 0x00040000 # macro +DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK = 0x00080000 # macro +DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID_MASK = 0x04000000 # macro +DB_DEBUG2__DISABLE_VR_PS_INVOKE_MASK = 0x08000000 # macro +DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK = 0x10000000 # macro +DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK = 0x20000000 # macro +DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK = 0x40000000 # macro +DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK = 0x80000000 # macro +DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT = 0x0 # macro +DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT = 0x1 # macro +DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT = 0x2 # macro +DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT = 0x3 # macro +DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT = 0x4 # macro +DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT = 0x5 # macro +DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT = 0x6 # macro +DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT = 0x7 # macro +DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT = 0x8 # macro +DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT = 0x9 # macro +DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT = 0xa # macro +DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT = 0xb # macro +DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT = 0xc # macro +DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT = 0xd # macro +DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT = 0xe # macro +DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT = 0xf # macro +DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT = 0x10 # macro +DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT = 0x11 # macro +DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT = 0x12 # macro +DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT = 0x13 # macro +DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT = 0x14 # macro +DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT = 0x15 # macro +DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT = 0x16 # macro +DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT = 0x17 # macro +DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT = 0x18 # macro +DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT = 0x19 # macro +DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT = 0x1a # macro +DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT = 0x1b # macro +DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT = 0x1c # macro +DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT = 0x1d # macro +DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT = 0x1e # macro +DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT = 0x1f # macro +DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK = 0x00000001 # macro +DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK = 0x00000002 # macro +DB_DEBUG3__FORCE_DB_IS_GOOD_MASK = 0x00000004 # macro +DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK = 0x00000008 # macro +DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK = 0x00000010 # macro +DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK = 0x00000020 # macro +DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK = 0x00000040 # macro +DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK = 0x00000080 # macro +DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK = 0x00000100 # macro +DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK = 0x00000200 # macro +DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK = 0x00000400 # macro +DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK = 0x00000800 # macro +DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK = 0x00001000 # macro +DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK = 0x00002000 # macro +DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK = 0x00004000 # macro +DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK = 0x00008000 # macro +DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK = 0x00010000 # macro +DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK = 0x00020000 # macro +DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK = 0x00040000 # macro +DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK = 0x00080000 # macro +DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK = 0x00100000 # macro +DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK = 0x00200000 # macro +DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK = 0x00400000 # macro +DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK = 0x00800000 # macro +DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK = 0x01000000 # macro +DB_DEBUG3__DISABLE_DI_DT_STALL_MASK = 0x02000000 # macro +DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK = 0x04000000 # macro +DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK = 0x08000000 # macro +DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK = 0x10000000 # macro +DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK = 0x20000000 # macro +DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK = 0x40000000 # macro +DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK = 0x80000000 # macro +DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT = 0x0 # macro +DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT = 0x1 # macro +DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT = 0x2 # macro +DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT = 0x3 # macro +DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT = 0x4 # macro +DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT = 0x5 # macro +DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT = 0x6 # macro +DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT = 0x7 # macro +DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT = 0x8 # macro +DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT = 0x9 # macro +DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT = 0xa # macro +DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT = 0xb # macro +DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT = 0xc # macro +DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT = 0xd # macro +DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT = 0xe # macro +DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT = 0xf # macro +DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT = 0x10 # macro +DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT = 0x11 # macro +DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT = 0x12 # macro +DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT = 0x13 # macro +DB_DEBUG4__DISABLE_8PPC_OBJPRIMID_WHEN_NO_SHADER_EXPORTS__SHIFT = 0x1e # macro +DB_DEBUG4__FULL_TILE_CACHE_EVICT_ON_HALF_FULL__SHIFT = 0x1f # macro +DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK = 0x00000001 # macro +DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK = 0x00000002 # macro +DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK = 0x00000004 # macro +DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK = 0x00000008 # macro +DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK = 0x00000010 # macro +DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK = 0x00000020 # macro +DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK = 0x00000040 # macro +DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK = 0x00000080 # macro +DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK = 0x00000100 # macro +DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK = 0x00000200 # macro +DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK = 0x00000400 # macro +DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK = 0x00000800 # macro +DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK = 0x00001000 # macro +DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK = 0x00002000 # macro +DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK = 0x00004000 # macro +DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK = 0x00008000 # macro +DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK = 0x00010000 # macro +DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK = 0x00020000 # macro +DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK = 0x00040000 # macro +DB_DEBUG4__DB_EXTRA_DEBUG4_MASK = 0x3FF80000 # macro +DB_DEBUG4__DISABLE_8PPC_OBJPRIMID_WHEN_NO_SHADER_EXPORTS_MASK = 0x40000000 # macro +DB_DEBUG4__FULL_TILE_CACHE_EVICT_ON_HALF_FULL_MASK = 0x80000000 # macro +DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT = 0x0 # macro +DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT = 0x5 # macro +DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT = 0xa # macro +DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT = 0x18 # macro +DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK = 0x0000001F # macro +DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK = 0x000003E0 # macro +DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK = 0x00001C00 # macro +DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK = 0x7F000000 # macro +DB_WATERMARKS__DEPTH_FREE__SHIFT = 0x0 # macro +DB_WATERMARKS__DEPTH_FLUSH__SHIFT = 0x5 # macro +DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT = 0xb # macro +DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT = 0xf # macro +DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT = 0x14 # macro +DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT = 0x1e # macro +DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT = 0x1f # macro +DB_WATERMARKS__DEPTH_FREE_MASK = 0x0000001F # macro +DB_WATERMARKS__DEPTH_FLUSH_MASK = 0x000007E0 # macro +DB_WATERMARKS__FORCE_SUMMARIZE_MASK = 0x00007800 # macro +DB_WATERMARKS__DEPTH_PENDING_FREE_MASK = 0x000F8000 # macro +DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK = 0x0FF00000 # macro +DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK = 0x40000000 # macro +DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK = 0x80000000 # macro +DB_SUBTILE_CONTROL__MSAA1_X__SHIFT = 0x0 # macro +DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT = 0x2 # macro +DB_SUBTILE_CONTROL__MSAA2_X__SHIFT = 0x4 # macro +DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT = 0x6 # macro +DB_SUBTILE_CONTROL__MSAA4_X__SHIFT = 0x8 # macro +DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT = 0xa # macro +DB_SUBTILE_CONTROL__MSAA8_X__SHIFT = 0xc # macro +DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT = 0xe # macro +DB_SUBTILE_CONTROL__MSAA16_X__SHIFT = 0x10 # macro +DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT = 0x12 # macro +DB_SUBTILE_CONTROL__MSAA1_X_MASK = 0x00000003 # macro +DB_SUBTILE_CONTROL__MSAA1_Y_MASK = 0x0000000C # macro +DB_SUBTILE_CONTROL__MSAA2_X_MASK = 0x00000030 # macro +DB_SUBTILE_CONTROL__MSAA2_Y_MASK = 0x000000C0 # macro +DB_SUBTILE_CONTROL__MSAA4_X_MASK = 0x00000300 # macro +DB_SUBTILE_CONTROL__MSAA4_Y_MASK = 0x00000C00 # macro +DB_SUBTILE_CONTROL__MSAA8_X_MASK = 0x00003000 # macro +DB_SUBTILE_CONTROL__MSAA8_Y_MASK = 0x0000C000 # macro +DB_SUBTILE_CONTROL__MSAA16_X_MASK = 0x00030000 # macro +DB_SUBTILE_CONTROL__MSAA16_Y_MASK = 0x000C0000 # macro +DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT = 0x0 # macro +DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT = 0x7 # macro +DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT = 0xe # macro +DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT = 0x14 # macro +DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT = 0x18 # macro +DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK = 0x0000007F # macro +DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK = 0x00003F80 # macro +DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK = 0x000FC000 # macro +DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK = 0x00F00000 # macro +DB_FREE_CACHELINES__QUAD_READ_REQS_MASK = 0xFF000000 # macro +DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT = 0x0 # macro +DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT = 0x5 # macro +DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT = 0xa # macro +DB_FIFO_DEPTH1__QC_DEPTH__SHIFT = 0x10 # macro +DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT = 0x15 # macro +DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK = 0x0000001F # macro +DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK = 0x000003E0 # macro +DB_FIFO_DEPTH1__MCC_DEPTH_MASK = 0x0000FC00 # macro +DB_FIFO_DEPTH1__QC_DEPTH_MASK = 0x001F0000 # macro +DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK = 0x1FE00000 # macro +DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT = 0x0 # macro +DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT = 0x8 # macro +DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT = 0xf # macro +DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT = 0x19 # macro +DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK = 0x000000FF # macro +DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK = 0x00007F00 # macro +DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK = 0x01FF8000 # macro +DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK = 0xFE000000 # macro +DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT = 0x0 # macro +DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT = 0x1 # macro +DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT = 0x2 # macro +DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK = 0x00000001 # macro +DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK = 0x00000002 # macro +DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK = 0x00000004 # macro +DB_RING_CONTROL__COUNTER_CONTROL__SHIFT = 0x0 # macro +DB_RING_CONTROL__COUNTER_CONTROL_MASK = 0x00000003 # macro +DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT = 0x0 # macro +DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT = 0x8 # macro +DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT = 0x10 # macro +DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT = 0x18 # macro +DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK = 0x00000007 # macro +DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK = 0x00000700 # macro +DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK = 0x00070000 # macro +DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK = 0x07000000 # macro +DB_RMI_CACHE_POLICY__Z_RD__SHIFT = 0x0 # macro +DB_RMI_CACHE_POLICY__S_RD__SHIFT = 0x1 # macro +DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT = 0x2 # macro +DB_RMI_CACHE_POLICY__Z_WR__SHIFT = 0x8 # macro +DB_RMI_CACHE_POLICY__S_WR__SHIFT = 0x9 # macro +DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT = 0xa # macro +DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT = 0xb # macro +DB_RMI_CACHE_POLICY__CC_RD__SHIFT = 0x10 # macro +DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT = 0x11 # macro +DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT = 0x12 # macro +DB_RMI_CACHE_POLICY__DCC_RD__SHIFT = 0x13 # macro +DB_RMI_CACHE_POLICY__CC_WR__SHIFT = 0x18 # macro +DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT = 0x19 # macro +DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT = 0x1a # macro +DB_RMI_CACHE_POLICY__DCC_WR__SHIFT = 0x1b # macro +DB_RMI_CACHE_POLICY__Z_RD_MASK = 0x00000001 # macro +DB_RMI_CACHE_POLICY__S_RD_MASK = 0x00000002 # macro +DB_RMI_CACHE_POLICY__HTILE_RD_MASK = 0x00000004 # macro +DB_RMI_CACHE_POLICY__Z_WR_MASK = 0x00000100 # macro +DB_RMI_CACHE_POLICY__S_WR_MASK = 0x00000200 # macro +DB_RMI_CACHE_POLICY__HTILE_WR_MASK = 0x00000400 # macro +DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK = 0x00000800 # macro +DB_RMI_CACHE_POLICY__CC_RD_MASK = 0x00010000 # macro +DB_RMI_CACHE_POLICY__FMASK_RD_MASK = 0x00020000 # macro +DB_RMI_CACHE_POLICY__CMASK_RD_MASK = 0x00040000 # macro +DB_RMI_CACHE_POLICY__DCC_RD_MASK = 0x00080000 # macro +DB_RMI_CACHE_POLICY__CC_WR_MASK = 0x01000000 # macro +DB_RMI_CACHE_POLICY__FMASK_WR_MASK = 0x02000000 # macro +DB_RMI_CACHE_POLICY__CMASK_WR_MASK = 0x04000000 # macro +DB_RMI_CACHE_POLICY__DCC_WR_MASK = 0x08000000 # macro +DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT = 0x0 # macro +DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT = 0x1 # macro +DB_DFSM_CONFIG__DISABLE_POPS__SHIFT = 0x2 # macro +DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT = 0x3 # macro +DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT = 0x8 # macro +DB_DFSM_CONFIG__BYPASS_DFSM_MASK = 0x00000001 # macro +DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK = 0x00000002 # macro +DB_DFSM_CONFIG__DISABLE_POPS_MASK = 0x00000004 # macro +DB_DFSM_CONFIG__FORCE_FLUSH_MASK = 0x00000008 # macro +DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK = 0x00007F00 # macro +DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT = 0x0 # macro +DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT = 0x10 # macro +DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK = 0x0000FFFF # macro +DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK = 0xFFFF0000 # macro +DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT = 0x0 # macro +DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT = 0x10 # macro +DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK = 0x0000FFFF # macro +DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK = 0xFFFF0000 # macro +DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT = 0x0 # macro +DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT = 0x10 # macro +DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK = 0x0000FFFF # macro +DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK = 0xFFFF0000 # macro +DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT = 0x0 # macro +DB_DFSM_WATCHDOG__TIMER_TARGET_MASK = 0xFFFFFFFF # macro +DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT = 0x0 # macro +DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT = 0x18 # macro +DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT = 0x1c # macro +DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK = 0x000003FF # macro +DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK = 0x0F000000 # macro +DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK = 0xF0000000 # macro +DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT = 0x0 # macro +DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT = 0x8 # macro +DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT = 0x10 # macro +DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT = 0x18 # macro +DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK = 0x000000FF # macro +DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK = 0x0000FF00 # macro +DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK = 0x00FF0000 # macro +DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK = 0xFF000000 # macro +CC_RB_REDUNDANCY__WRITE_DIS__SHIFT = 0x0 # macro +CC_RB_REDUNDANCY__FAILED_RB0__SHIFT = 0x8 # macro +CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT = 0xc # macro +CC_RB_REDUNDANCY__FAILED_RB1__SHIFT = 0x10 # macro +CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT = 0x14 # macro +CC_RB_REDUNDANCY__WRITE_DIS_MASK = 0x00000001 # macro +CC_RB_REDUNDANCY__FAILED_RB0_MASK = 0x00000F00 # macro +CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK = 0x00001000 # macro +CC_RB_REDUNDANCY__FAILED_RB1_MASK = 0x000F0000 # macro +CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK = 0x00100000 # macro +CC_RB_BACKEND_DISABLE__WRITE_DIS__SHIFT = 0x0 # macro +CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT = 0x10 # macro +CC_RB_BACKEND_DISABLE__WRITE_DIS_MASK = 0x00000001 # macro +CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK = 0x00FF0000 # macro +GB_ADDR_CONFIG__NUM_PIPES__SHIFT = 0x0 # macro +GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT = 0x3 # macro +GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT = 0x6 # macro +GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT = 0x8 # macro +GB_ADDR_CONFIG__NUM_BANKS__SHIFT = 0xc # macro +GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT = 0x10 # macro +GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT = 0x13 # macro +GB_ADDR_CONFIG__NUM_GPUS__SHIFT = 0x15 # macro +GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT = 0x18 # macro +GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT = 0x1a # macro +GB_ADDR_CONFIG__ROW_SIZE__SHIFT = 0x1c # macro +GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT = 0x1e # macro +GB_ADDR_CONFIG__SE_ENABLE__SHIFT = 0x1f # macro +GB_ADDR_CONFIG__NUM_PIPES_MASK = 0x00000007 # macro +GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK = 0x00000038 # macro +GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK = 0x000000C0 # macro +GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK = 0x00000700 # macro +GB_ADDR_CONFIG__NUM_BANKS_MASK = 0x00007000 # macro +GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK = 0x00070000 # macro +GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK = 0x00180000 # macro +GB_ADDR_CONFIG__NUM_GPUS_MASK = 0x00E00000 # macro +GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK = 0x03000000 # macro +GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK = 0x0C000000 # macro +GB_ADDR_CONFIG__ROW_SIZE_MASK = 0x30000000 # macro +GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK = 0x40000000 # macro +GB_ADDR_CONFIG__SE_ENABLE_MASK = 0x80000000 # macro +GB_BACKEND_MAP__BACKEND_MAP__SHIFT = 0x0 # macro +GB_BACKEND_MAP__BACKEND_MAP_MASK = 0xFFFFFFFF # macro +GB_GPU_ID__GPU_ID__SHIFT = 0x0 # macro +GB_GPU_ID__GPU_ID_MASK = 0x0000000F # macro +CC_RB_DAISY_CHAIN__RB_0__SHIFT = 0x0 # macro +CC_RB_DAISY_CHAIN__RB_1__SHIFT = 0x4 # macro +CC_RB_DAISY_CHAIN__RB_2__SHIFT = 0x8 # macro +CC_RB_DAISY_CHAIN__RB_3__SHIFT = 0xc # macro +CC_RB_DAISY_CHAIN__RB_4__SHIFT = 0x10 # macro +CC_RB_DAISY_CHAIN__RB_5__SHIFT = 0x14 # macro +CC_RB_DAISY_CHAIN__RB_6__SHIFT = 0x18 # macro +CC_RB_DAISY_CHAIN__RB_7__SHIFT = 0x1c # macro +CC_RB_DAISY_CHAIN__RB_0_MASK = 0x0000000F # macro +CC_RB_DAISY_CHAIN__RB_1_MASK = 0x000000F0 # macro +CC_RB_DAISY_CHAIN__RB_2_MASK = 0x00000F00 # macro +CC_RB_DAISY_CHAIN__RB_3_MASK = 0x0000F000 # macro +CC_RB_DAISY_CHAIN__RB_4_MASK = 0x000F0000 # macro +CC_RB_DAISY_CHAIN__RB_5_MASK = 0x00F00000 # macro +CC_RB_DAISY_CHAIN__RB_6_MASK = 0x0F000000 # macro +CC_RB_DAISY_CHAIN__RB_7_MASK = 0xF0000000 # macro +GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT = 0x0 # macro +GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT = 0x3 # macro +GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT = 0x6 # macro +GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT = 0x8 # macro +GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT = 0xc # macro +GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT = 0x10 # macro +GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT = 0x13 # macro +GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT = 0x15 # macro +GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT = 0x18 # macro +GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT = 0x1a # macro +GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT = 0x1c # macro +GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT = 0x1e # macro +GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT = 0x1f # macro +GB_ADDR_CONFIG_READ__NUM_PIPES_MASK = 0x00000007 # macro +GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK = 0x00000038 # macro +GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK = 0x000000C0 # macro +GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK = 0x00000700 # macro +GB_ADDR_CONFIG_READ__NUM_BANKS_MASK = 0x00007000 # macro +GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK = 0x00070000 # macro +GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK = 0x00180000 # macro +GB_ADDR_CONFIG_READ__NUM_GPUS_MASK = 0x00E00000 # macro +GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK = 0x03000000 # macro +GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK = 0x0C000000 # macro +GB_ADDR_CONFIG_READ__ROW_SIZE_MASK = 0x30000000 # macro +GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK = 0x40000000 # macro +GB_ADDR_CONFIG_READ__SE_ENABLE_MASK = 0x80000000 # macro +GB_TILE_MODE0__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE0__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE0__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE0__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE0__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE0__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE0__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE1__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE1__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE1__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE1__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE1__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE1__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE1__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE2__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE2__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE2__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE2__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE2__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE2__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE2__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE3__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE3__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE3__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE3__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE3__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE3__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE3__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE4__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE4__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE4__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE4__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE4__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE4__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE4__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE5__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE5__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE5__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE5__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE5__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE5__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE5__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE6__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE6__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE6__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE6__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE6__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE6__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE6__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE7__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE7__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE7__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE7__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE7__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE7__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE7__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE8__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE8__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE8__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE8__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE8__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE8__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE8__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE9__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE9__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE9__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE9__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE9__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE9__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE9__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE10__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE10__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE10__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE10__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE10__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE10__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE10__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE11__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE11__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE11__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE11__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE11__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE11__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE11__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE12__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE12__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE12__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE12__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE12__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE12__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE12__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE13__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE13__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE13__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE13__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE13__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE13__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE13__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE14__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE14__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE14__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE14__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE14__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE14__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE14__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE15__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE15__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE15__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE15__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE15__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE15__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE15__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE16__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE16__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE16__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE16__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE16__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE16__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE16__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE17__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE17__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE17__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE17__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE17__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE17__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE17__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE18__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE18__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE18__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE18__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE18__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE18__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE18__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE19__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE19__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE19__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE19__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE19__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE19__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE19__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE20__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE20__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE20__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE20__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE20__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE20__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE20__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE21__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE21__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE21__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE21__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE21__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE21__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE21__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE22__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE22__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE22__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE22__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE22__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE22__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE22__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE23__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE23__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE23__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE23__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE23__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE23__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE23__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE24__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE24__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE24__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE24__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE24__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE24__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE24__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE25__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE25__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE25__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE25__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE25__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE25__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE25__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE26__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE26__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE26__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE26__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE26__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE26__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE26__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE27__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE27__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE27__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE27__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE27__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE27__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE27__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE28__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE28__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE28__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE28__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE28__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE28__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE28__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE29__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE29__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE29__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE29__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE29__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE29__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE29__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE30__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE30__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE30__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE30__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE30__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE30__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE30__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_TILE_MODE31__ARRAY_MODE__SHIFT = 0x2 # macro +GB_TILE_MODE31__PIPE_CONFIG__SHIFT = 0x6 # macro +GB_TILE_MODE31__TILE_SPLIT__SHIFT = 0xb # macro +GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT = 0x16 # macro +GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT = 0x19 # macro +GB_TILE_MODE31__ARRAY_MODE_MASK = 0x0000003C # macro +GB_TILE_MODE31__PIPE_CONFIG_MASK = 0x000007C0 # macro +GB_TILE_MODE31__TILE_SPLIT_MASK = 0x00003800 # macro +GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK = 0x01C00000 # macro +GB_TILE_MODE31__SAMPLE_SPLIT_MASK = 0x06000000 # macro +GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT = 0x0 # macro +GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT = 0x2 # macro +GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT = 0x4 # macro +GB_MACROTILE_MODE0__NUM_BANKS__SHIFT = 0x6 # macro +GB_MACROTILE_MODE0__BANK_WIDTH_MASK = 0x00000003 # macro +GB_MACROTILE_MODE0__BANK_HEIGHT_MASK = 0x0000000C # macro +GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK = 0x00000030 # macro +GB_MACROTILE_MODE0__NUM_BANKS_MASK = 0x000000C0 # macro +GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT = 0x0 # macro +GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT = 0x2 # macro +GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT = 0x4 # macro +GB_MACROTILE_MODE1__NUM_BANKS__SHIFT = 0x6 # macro +GB_MACROTILE_MODE1__BANK_WIDTH_MASK = 0x00000003 # macro +GB_MACROTILE_MODE1__BANK_HEIGHT_MASK = 0x0000000C # macro +GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK = 0x00000030 # macro +GB_MACROTILE_MODE1__NUM_BANKS_MASK = 0x000000C0 # macro +GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT = 0x0 # macro +GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT = 0x2 # macro +GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT = 0x4 # macro +GB_MACROTILE_MODE2__NUM_BANKS__SHIFT = 0x6 # macro +GB_MACROTILE_MODE2__BANK_WIDTH_MASK = 0x00000003 # macro +GB_MACROTILE_MODE2__BANK_HEIGHT_MASK = 0x0000000C # macro +GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK = 0x00000030 # macro +GB_MACROTILE_MODE2__NUM_BANKS_MASK = 0x000000C0 # macro +GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT = 0x0 # macro +GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT = 0x2 # macro +GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT = 0x4 # macro +GB_MACROTILE_MODE3__NUM_BANKS__SHIFT = 0x6 # macro +GB_MACROTILE_MODE3__BANK_WIDTH_MASK = 0x00000003 # macro +GB_MACROTILE_MODE3__BANK_HEIGHT_MASK = 0x0000000C # macro +GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK = 0x00000030 # macro +GB_MACROTILE_MODE3__NUM_BANKS_MASK = 0x000000C0 # macro +GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT = 0x0 # macro +GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT = 0x2 # macro +GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT = 0x4 # macro +GB_MACROTILE_MODE4__NUM_BANKS__SHIFT = 0x6 # macro +GB_MACROTILE_MODE4__BANK_WIDTH_MASK = 0x00000003 # macro +GB_MACROTILE_MODE4__BANK_HEIGHT_MASK = 0x0000000C # macro +GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK = 0x00000030 # macro +GB_MACROTILE_MODE4__NUM_BANKS_MASK = 0x000000C0 # macro +GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT = 0x0 # macro +GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT = 0x2 # macro +GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT = 0x4 # macro +GB_MACROTILE_MODE5__NUM_BANKS__SHIFT = 0x6 # macro +GB_MACROTILE_MODE5__BANK_WIDTH_MASK = 0x00000003 # macro +GB_MACROTILE_MODE5__BANK_HEIGHT_MASK = 0x0000000C # macro +GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK = 0x00000030 # macro +GB_MACROTILE_MODE5__NUM_BANKS_MASK = 0x000000C0 # macro +GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT = 0x0 # macro +GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT = 0x2 # macro +GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT = 0x4 # macro +GB_MACROTILE_MODE6__NUM_BANKS__SHIFT = 0x6 # macro +GB_MACROTILE_MODE6__BANK_WIDTH_MASK = 0x00000003 # macro +GB_MACROTILE_MODE6__BANK_HEIGHT_MASK = 0x0000000C # macro +GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK = 0x00000030 # macro +GB_MACROTILE_MODE6__NUM_BANKS_MASK = 0x000000C0 # macro +GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT = 0x0 # macro +GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT = 0x2 # macro +GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT = 0x4 # macro +GB_MACROTILE_MODE7__NUM_BANKS__SHIFT = 0x6 # macro +GB_MACROTILE_MODE7__BANK_WIDTH_MASK = 0x00000003 # macro +GB_MACROTILE_MODE7__BANK_HEIGHT_MASK = 0x0000000C # macro +GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK = 0x00000030 # macro +GB_MACROTILE_MODE7__NUM_BANKS_MASK = 0x000000C0 # macro +GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT = 0x0 # macro +GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT = 0x2 # macro +GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT = 0x4 # macro +GB_MACROTILE_MODE8__NUM_BANKS__SHIFT = 0x6 # macro +GB_MACROTILE_MODE8__BANK_WIDTH_MASK = 0x00000003 # macro +GB_MACROTILE_MODE8__BANK_HEIGHT_MASK = 0x0000000C # macro +GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK = 0x00000030 # macro +GB_MACROTILE_MODE8__NUM_BANKS_MASK = 0x000000C0 # macro +GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT = 0x0 # macro +GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT = 0x2 # macro +GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT = 0x4 # macro +GB_MACROTILE_MODE9__NUM_BANKS__SHIFT = 0x6 # macro +GB_MACROTILE_MODE9__BANK_WIDTH_MASK = 0x00000003 # macro +GB_MACROTILE_MODE9__BANK_HEIGHT_MASK = 0x0000000C # macro +GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK = 0x00000030 # macro +GB_MACROTILE_MODE9__NUM_BANKS_MASK = 0x000000C0 # macro +GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT = 0x0 # macro +GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT = 0x2 # macro +GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT = 0x4 # macro +GB_MACROTILE_MODE10__NUM_BANKS__SHIFT = 0x6 # macro +GB_MACROTILE_MODE10__BANK_WIDTH_MASK = 0x00000003 # macro +GB_MACROTILE_MODE10__BANK_HEIGHT_MASK = 0x0000000C # macro +GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK = 0x00000030 # macro +GB_MACROTILE_MODE10__NUM_BANKS_MASK = 0x000000C0 # macro +GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT = 0x0 # macro +GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT = 0x2 # macro +GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT = 0x4 # macro +GB_MACROTILE_MODE11__NUM_BANKS__SHIFT = 0x6 # macro +GB_MACROTILE_MODE11__BANK_WIDTH_MASK = 0x00000003 # macro +GB_MACROTILE_MODE11__BANK_HEIGHT_MASK = 0x0000000C # macro +GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK = 0x00000030 # macro +GB_MACROTILE_MODE11__NUM_BANKS_MASK = 0x000000C0 # macro +GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT = 0x0 # macro +GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT = 0x2 # macro +GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT = 0x4 # macro +GB_MACROTILE_MODE12__NUM_BANKS__SHIFT = 0x6 # macro +GB_MACROTILE_MODE12__BANK_WIDTH_MASK = 0x00000003 # macro +GB_MACROTILE_MODE12__BANK_HEIGHT_MASK = 0x0000000C # macro +GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK = 0x00000030 # macro +GB_MACROTILE_MODE12__NUM_BANKS_MASK = 0x000000C0 # macro +GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT = 0x0 # macro +GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT = 0x2 # macro +GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT = 0x4 # macro +GB_MACROTILE_MODE13__NUM_BANKS__SHIFT = 0x6 # macro +GB_MACROTILE_MODE13__BANK_WIDTH_MASK = 0x00000003 # macro +GB_MACROTILE_MODE13__BANK_HEIGHT_MASK = 0x0000000C # macro +GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK = 0x00000030 # macro +GB_MACROTILE_MODE13__NUM_BANKS_MASK = 0x000000C0 # macro +GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT = 0x0 # macro +GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT = 0x2 # macro +GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT = 0x4 # macro +GB_MACROTILE_MODE14__NUM_BANKS__SHIFT = 0x6 # macro +GB_MACROTILE_MODE14__BANK_WIDTH_MASK = 0x00000003 # macro +GB_MACROTILE_MODE14__BANK_HEIGHT_MASK = 0x0000000C # macro +GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK = 0x00000030 # macro +GB_MACROTILE_MODE14__NUM_BANKS_MASK = 0x000000C0 # macro +GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT = 0x0 # macro +GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT = 0x2 # macro +GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT = 0x4 # macro +GB_MACROTILE_MODE15__NUM_BANKS__SHIFT = 0x6 # macro +GB_MACROTILE_MODE15__BANK_WIDTH_MASK = 0x00000003 # macro +GB_MACROTILE_MODE15__BANK_HEIGHT_MASK = 0x0000000C # macro +GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK = 0x00000030 # macro +GB_MACROTILE_MODE15__NUM_BANKS_MASK = 0x000000C0 # macro +CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT = 0x0 # macro +CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT = 0x6 # macro +CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT = 0xc # macro +CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT = 0x10 # macro +CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT = 0x12 # macro +CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT = 0x13 # macro +CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT = 0x14 # macro +CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT = 0x15 # macro +CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT = 0x16 # macro +CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT = 0x17 # macro +CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT = 0x18 # macro +CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT = 0x19 # macro +CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT = 0x1a # macro +CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT = 0x1b # macro +CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT = 0x1c # macro +CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT = 0x1d # macro +CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT = 0x1e # macro +CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT = 0x1f # macro +CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK = 0x0000000F # macro +CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK = 0x000003C0 # macro +CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK = 0x0000F000 # macro +CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK = 0x00010000 # macro +CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK = 0x00040000 # macro +CB_HW_CONTROL__FORCE_NEEDS_DST_MASK = 0x00080000 # macro +CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK = 0x00100000 # macro +CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK = 0x00200000 # macro +CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK = 0x00400000 # macro +CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK = 0x00800000 # macro +CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK = 0x01000000 # macro +CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK = 0x02000000 # macro +CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK = 0x04000000 # macro +CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK = 0x08000000 # macro +CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK = 0x10000000 # macro +CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK = 0x20000000 # macro +CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK = 0x40000000 # macro +CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK = 0x80000000 # macro +CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT = 0x0 # macro +CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT = 0x5 # macro +CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT = 0xb # macro +CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT = 0x11 # macro +CB_HW_CONTROL_1__RMI_CREDITS__SHIFT = 0x1a # macro +CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK = 0x0000001F # macro +CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK = 0x000007E0 # macro +CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK = 0x0001F800 # macro +CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK = 0x03FE0000 # macro +CB_HW_CONTROL_1__RMI_CREDITS_MASK = 0xFC000000 # macro +CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT = 0x0 # macro +CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT = 0x8 # macro +CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT = 0xf # macro +CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT = 0x18 # macro +CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT = 0x1c # macro +CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK = 0x000000FF # macro +CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK = 0x00007F00 # macro +CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK = 0x007F8000 # macro +CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK = 0x0F000000 # macro +CB_HW_CONTROL_2__CHICKEN_BITS_MASK = 0xF0000000 # macro +CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT = 0x0 # macro +CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT = 0x1 # macro +CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT = 0x2 # macro +CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT = 0x3 # macro +CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT = 0x4 # macro +CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT = 0x5 # macro +CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT = 0x6 # macro +CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT = 0x7 # macro +CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT = 0x8 # macro +CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT = 0x9 # macro +CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT = 0xa # macro +CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT = 0xb # macro +CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT = 0xc # macro +CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT = 0xd # macro +CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT = 0xe # macro +CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT = 0xf # macro +CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT = 0x10 # macro +CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT = 0x11 # macro +CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT = 0x12 # macro +CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT = 0x13 # macro +CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT = 0x14 # macro +CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT = 0x15 # macro +CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT = 0x16 # macro +CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT = 0x17 # macro +CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT = 0x18 # macro +CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT = 0x19 # macro +CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT = 0x1a # macro +CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT = 0x1b # macro +CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS__SHIFT = 0x1c # macro +CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK = 0x00000001 # macro +CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK = 0x00000002 # macro +CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK = 0x00000004 # macro +CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK = 0x00000008 # macro +CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK = 0x00000010 # macro +CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK = 0x00000020 # macro +CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK = 0x00000040 # macro +CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK = 0x00000080 # macro +CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK = 0x00000100 # macro +CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK = 0x00000200 # macro +CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK = 0x00000400 # macro +CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK = 0x00000800 # macro +CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK = 0x00001000 # macro +CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK = 0x00002000 # macro +CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK = 0x00004000 # macro +CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK = 0x00008000 # macro +CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK = 0x00010000 # macro +CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK = 0x00020000 # macro +CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK = 0x00040000 # macro +CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK = 0x00080000 # macro +CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK = 0x00100000 # macro +CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK = 0x00200000 # macro +CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK = 0x00400000 # macro +CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK = 0x00800000 # macro +CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK = 0x01000000 # macro +CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK = 0x02000000 # macro +CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK = 0x04000000 # macro +CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK = 0x08000000 # macro +CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS_MASK = 0x30000000 # macro +CB_HW_MEM_ARBITER_RD__MODE__SHIFT = 0x0 # macro +CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT = 0x2 # macro +CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT = 0x6 # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT = 0xa # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT = 0xc # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT = 0xe # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT = 0x10 # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT = 0x12 # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT = 0x14 # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT = 0x16 # macro +CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT = 0x17 # macro +CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT = 0x1a # macro +CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT = 0x1d # macro +CB_HW_MEM_ARBITER_RD__MODE_MASK = 0x00000003 # macro +CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK = 0x0000003C # macro +CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK = 0x000003C0 # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK = 0x00000C00 # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK = 0x00003000 # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK = 0x0000C000 # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK = 0x00030000 # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK = 0x000C0000 # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK = 0x00300000 # macro +CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK = 0x00400000 # macro +CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK = 0x03800000 # macro +CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK = 0x1C000000 # macro +CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK = 0x20000000 # macro +CB_HW_MEM_ARBITER_WR__MODE__SHIFT = 0x0 # macro +CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT = 0x2 # macro +CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT = 0x6 # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT = 0xa # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT = 0xc # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT = 0xe # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT = 0x10 # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT = 0x12 # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT = 0x14 # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT = 0x16 # macro +CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT = 0x17 # macro +CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT = 0x1a # macro +CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT = 0x1d # macro +CB_HW_MEM_ARBITER_WR__MODE_MASK = 0x00000003 # macro +CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK = 0x0000003C # macro +CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK = 0x000003C0 # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK = 0x00000C00 # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK = 0x00003000 # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK = 0x0000C000 # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK = 0x00030000 # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK = 0x000C0000 # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK = 0x00300000 # macro +CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK = 0x00400000 # macro +CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK = 0x03800000 # macro +CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK = 0x1C000000 # macro +CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK = 0x20000000 # macro +CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT = 0x0 # macro +CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT = 0x5 # macro +CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT = 0x6 # macro +CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE__SHIFT = 0x7 # macro +CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT = 0x8 # macro +CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT = 0x10 # macro +CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT = 0x18 # macro +CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT = 0x1c # macro +CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK = 0x0000001F # macro +CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK = 0x00000020 # macro +CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK = 0x00000040 # macro +CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE_MASK = 0x00000080 # macro +CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK = 0x0000FF00 # macro +CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK = 0x007F0000 # macro +CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK = 0x0F000000 # macro +CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK = 0xF0000000 # macro +GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT = 0x8 # macro +GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT = 0xc # macro +GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT = 0x10 # macro +GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT = 0x14 # macro +GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK = 0x00000F00 # macro +GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK = 0x00001000 # macro +GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK = 0x000F0000 # macro +GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK = 0x00100000 # macro +GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT = 0x10 # macro +GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK = 0x00FF0000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT = 0x0 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT = 0x2 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT = 0x4 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT = 0x6 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT = 0x8 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT = 0xa # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT = 0xc # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT = 0xe # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT = 0x10 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT = 0x12 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT = 0x14 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT = 0x16 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT = 0x18 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT = 0x1a # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT = 0x1c # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT = 0x1e # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK = 0x00000003 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK = 0x0000000C # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK = 0x00000030 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK = 0x000000C0 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK = 0x00000300 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK = 0x00000C00 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK = 0x00003000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK = 0x0000C000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK = 0x00030000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK = 0x000C0000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK = 0x00300000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK = 0x00C00000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK = 0x03000000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK = 0x0C000000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK = 0x30000000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK = 0xC0000000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT = 0x0 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT = 0x2 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT = 0x4 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT = 0x6 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT = 0x8 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT = 0xa # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT = 0xc # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT = 0xe # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT = 0x10 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT = 0x12 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT = 0x14 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT = 0x16 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT = 0x18 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT = 0x1a # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT = 0x1c # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT = 0x1e # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK = 0x00000003 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK = 0x0000000C # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK = 0x00000030 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK = 0x000000C0 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK = 0x00000300 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK = 0x00000C00 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK = 0x00003000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK = 0x0000C000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK = 0x00030000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK = 0x000C0000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK = 0x00300000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK = 0x00C00000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK = 0x03000000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK = 0x0C000000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK = 0x30000000 # macro +GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK = 0xC0000000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT = 0x0 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT = 0x2 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT = 0x4 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT = 0x6 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT = 0x8 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT = 0xa # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT = 0xc # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT = 0xe # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT = 0x10 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT = 0x12 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT = 0x14 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT = 0x16 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT = 0x18 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT = 0x1a # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT = 0x1c # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT = 0x1e # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK = 0x00000003 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK = 0x0000000C # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK = 0x00000030 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK = 0x000000C0 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK = 0x00000300 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK = 0x00000C00 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK = 0x00003000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK = 0x0000C000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK = 0x00030000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK = 0x000C0000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK = 0x00300000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK = 0x00C00000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK = 0x03000000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK = 0x0C000000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK = 0x30000000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK = 0xC0000000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT = 0x0 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT = 0x2 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT = 0x4 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT = 0x6 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT = 0x8 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT = 0xa # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT = 0xc # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT = 0xe # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT = 0x10 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT = 0x12 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT = 0x14 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT = 0x16 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT = 0x18 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT = 0x1a # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT = 0x1c # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT = 0x1e # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK = 0x00000003 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK = 0x0000000C # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK = 0x00000030 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK = 0x000000C0 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK = 0x00000300 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK = 0x00000C00 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK = 0x00003000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK = 0x0000C000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK = 0x00030000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK = 0x000C0000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK = 0x00300000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK = 0x00C00000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK = 0x03000000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK = 0x0C000000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK = 0x30000000 # macro +GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK = 0xC0000000 # macro +GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT = 0x0 # macro +GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT = 0x3 # macro +GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT = 0x6 # macro +GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT = 0x9 # macro +GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK = 0x00000007 # macro +GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK = 0x00000038 # macro +GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK = 0x000001C0 # macro +GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK = 0x00000E00 # macro +GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT = 0x0 # macro +GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT = 0x3 # macro +GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT = 0x6 # macro +GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT = 0x9 # macro +GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK = 0x00000007 # macro +GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK = 0x00000038 # macro +GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK = 0x000001C0 # macro +GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK = 0x00000E00 # macro +GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT = 0x0 # macro +GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT = 0x3 # macro +GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT = 0x6 # macro +GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT = 0x9 # macro +GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT = 0xc # macro +GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT = 0x14 # macro +GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT = 0x1b # macro +GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK = 0x00000007 # macro +GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK = 0x00000038 # macro +GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK = 0x000001C0 # macro +GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK = 0x00000E00 # macro +GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK = 0x0003F000 # macro +GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK = 0x07F00000 # macro +GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK = 0x78000000 # macro +GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT = 0x0 # macro +GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT = 0x3 # macro +GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT = 0x6 # macro +GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT = 0x9 # macro +GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT = 0xc # macro +GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT = 0x14 # macro +GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT = 0x1b # macro +GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK = 0x00000007 # macro +GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK = 0x00000038 # macro +GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK = 0x000001C0 # macro +GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK = 0x00000E00 # macro +GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK = 0x0003F000 # macro +GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK = 0x07F00000 # macro +GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK = 0x78000000 # macro +GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT = 0x0 # macro +GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT = 0x4 # macro +GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT = 0x8 # macro +GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT = 0xc # macro +GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT = 0x10 # macro +GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT = 0x13 # macro +GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT = 0x16 # macro +GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT = 0x19 # macro +GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT = 0x1c # macro +GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK = 0x0000000F # macro +GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK = 0x000000F0 # macro +GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK = 0x00000F00 # macro +GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK = 0x0000F000 # macro +GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK = 0x00070000 # macro +GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK = 0x00380000 # macro +GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK = 0x01C00000 # macro +GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK = 0x0E000000 # macro +GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK = 0x10000000 # macro +GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT = 0x0 # macro +GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT = 0x4 # macro +GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT = 0x8 # macro +GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT = 0xc # macro +GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT = 0x10 # macro +GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT = 0x13 # macro +GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT = 0x16 # macro +GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT = 0x19 # macro +GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT = 0x1c # macro +GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK = 0x0000000F # macro +GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK = 0x000000F0 # macro +GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK = 0x00000F00 # macro +GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK = 0x0000F000 # macro +GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK = 0x00070000 # macro +GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK = 0x00380000 # macro +GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK = 0x01C00000 # macro +GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK = 0x0E000000 # macro +GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK = 0x10000000 # macro +GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT = 0x0 # macro +GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT = 0x8 # macro +GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT = 0x10 # macro +GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT = 0x18 # macro +GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK = 0x000000FF # macro +GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK = 0x0000FF00 # macro +GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK = 0x00FF0000 # macro +GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK = 0xFF000000 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT = 0x0 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT = 0x3 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT = 0x6 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT = 0x9 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT = 0xc # macro +GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT = 0xf # macro +GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT = 0x12 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT = 0x15 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK = 0x00000007 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK = 0x00000038 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK = 0x000001C0 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK = 0x00000E00 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK = 0x00007000 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK = 0x00038000 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK = 0x001C0000 # macro +GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK = 0x00E00000 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT = 0x0 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT = 0x3 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT = 0x6 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT = 0x9 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT = 0xc # macro +GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT = 0xf # macro +GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT = 0x12 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT = 0x15 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK = 0x00000007 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK = 0x00000038 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK = 0x000001C0 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK = 0x00000E00 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK = 0x00007000 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK = 0x00038000 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK = 0x001C0000 # macro +GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK = 0x00E00000 # macro +GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT = 0xc # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT = 0xd # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT = 0xe # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT = 0xf # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK = 0x00001000 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK = 0x00002000 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK = 0x00004000 # macro +GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK = 0x00008000 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT = 0xc # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT = 0xd # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT = 0xe # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT = 0xf # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK = 0x00001000 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK = 0x00002000 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK = 0x00004000 # macro +GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK = 0x00008000 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT = 0x0 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT = 0x2 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT = 0x4 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT = 0x6 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT = 0x8 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT = 0xa # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT = 0xc # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT = 0xe # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT = 0x10 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT = 0x12 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT = 0x14 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT = 0x16 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT = 0x18 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT = 0x1a # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT = 0x1c # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT = 0x1e # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK = 0x00000003 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK = 0x0000000C # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK = 0x00000030 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK = 0x000000C0 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK = 0x00000300 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK = 0x00000C00 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK = 0x00003000 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK = 0x0000C000 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK = 0x00030000 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK = 0x000C0000 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK = 0x00300000 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK = 0x00C00000 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK = 0x03000000 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK = 0x0C000000 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK = 0x30000000 # macro +GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK = 0xC0000000 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT = 0x0 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT = 0x2 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT = 0x4 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT = 0x6 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT = 0x8 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT = 0xa # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT = 0xc # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT = 0xe # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT = 0x10 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT = 0x12 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT = 0x14 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT = 0x16 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT = 0x18 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT = 0x1a # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT = 0x1c # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT = 0x1e # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK = 0x00000003 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK = 0x0000000C # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK = 0x00000030 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK = 0x000000C0 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK = 0x00000300 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK = 0x00000C00 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK = 0x00003000 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK = 0x0000C000 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK = 0x00030000 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK = 0x000C0000 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK = 0x00300000 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK = 0x00C00000 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK = 0x03000000 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK = 0x0C000000 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK = 0x30000000 # macro +GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK = 0xC0000000 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT = 0x0 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT = 0x2 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT = 0x4 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT = 0x6 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT = 0x8 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT = 0xa # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT = 0xc # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT = 0xe # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT = 0x10 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT = 0x12 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT = 0x14 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT = 0x16 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT = 0x18 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT = 0x1a # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT = 0x1c # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT = 0x1e # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK = 0x00000003 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK = 0x0000000C # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK = 0x00000030 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK = 0x000000C0 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK = 0x00000300 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK = 0x00000C00 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK = 0x00003000 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK = 0x0000C000 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK = 0x00030000 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK = 0x000C0000 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK = 0x00300000 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK = 0x00C00000 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK = 0x03000000 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK = 0x0C000000 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK = 0x30000000 # macro +GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK = 0xC0000000 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT = 0x0 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT = 0x2 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT = 0x4 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT = 0x6 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT = 0x8 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT = 0xa # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT = 0xc # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT = 0xe # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT = 0x10 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT = 0x12 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT = 0x14 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT = 0x16 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT = 0x18 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT = 0x1a # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT = 0x1c # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT = 0x1e # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK = 0x00000003 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK = 0x0000000C # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK = 0x00000030 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK = 0x000000C0 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK = 0x00000300 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK = 0x00000C00 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK = 0x00003000 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK = 0x0000C000 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK = 0x00030000 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK = 0x000C0000 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK = 0x00300000 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK = 0x00C00000 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK = 0x03000000 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK = 0x0C000000 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK = 0x30000000 # macro +GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK = 0xC0000000 # macro +GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT = 0x0 # macro +GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT = 0x4 # macro +GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT = 0x8 # macro +GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT = 0xc # macro +GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT = 0x10 # macro +GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK = 0x0000000F # macro +GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK = 0x000000F0 # macro +GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK = 0x00000F00 # macro +GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK = 0x0000F000 # macro +GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK = 0x00030000 # macro +GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT = 0x0 # macro +GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT = 0x4 # macro +GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT = 0x8 # macro +GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT = 0xc # macro +GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT = 0x10 # macro +GCEA_IO_WR_COMBINE_FLUSH__DISABLE_MAM_CHAINING__SHIFT = 0x12 # macro +GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK = 0x0000000F # macro +GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK = 0x000000F0 # macro +GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK = 0x00000F00 # macro +GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK = 0x0000F000 # macro +GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK = 0x00030000 # macro +GCEA_IO_WR_COMBINE_FLUSH__DISABLE_MAM_CHAINING_MASK = 0x00040000 # macro +GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT = 0x0 # macro +GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT = 0x8 # macro +GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT = 0x10 # macro +GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT = 0x18 # macro +GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK = 0x000000FF # macro +GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK = 0x0000FF00 # macro +GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK = 0x00FF0000 # macro +GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK = 0xFF000000 # macro +GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT = 0x0 # macro +GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT = 0x3 # macro +GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT = 0x6 # macro +GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT = 0x9 # macro +GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT = 0xc # macro +GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT = 0xf # macro +GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT = 0x12 # macro +GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT = 0x15 # macro +GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK = 0x00000007 # macro +GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK = 0x00000038 # macro +GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK = 0x000001C0 # macro +GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK = 0x00000E00 # macro +GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK = 0x00007000 # macro +GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK = 0x00038000 # macro +GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK = 0x001C0000 # macro +GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK = 0x00E00000 # macro +GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT = 0x0 # macro +GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT = 0x3 # macro +GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT = 0x6 # macro +GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT = 0x9 # macro +GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT = 0xc # macro +GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT = 0xf # macro +GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT = 0x12 # macro +GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT = 0x15 # macro +GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK = 0x00000007 # macro +GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK = 0x00000038 # macro +GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK = 0x000001C0 # macro +GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK = 0x00000E00 # macro +GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK = 0x00007000 # macro +GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK = 0x00038000 # macro +GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK = 0x001C0000 # macro +GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK = 0x00E00000 # macro +GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT = 0xc # macro +GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT = 0xd # macro +GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT = 0xe # macro +GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT = 0xf # macro +GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK = 0x00001000 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK = 0x00002000 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK = 0x00004000 # macro +GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK = 0x00008000 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT = 0x0 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT = 0x3 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT = 0x6 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT = 0x9 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT = 0xc # macro +GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT = 0xd # macro +GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT = 0xe # macro +GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT = 0xf # macro +GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK = 0x00000007 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK = 0x00000038 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK = 0x000001C0 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK = 0x00000E00 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK = 0x00001000 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK = 0x00002000 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK = 0x00004000 # macro +GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK = 0x00008000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT = 0x0 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT = 0x1 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT = 0x2 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT = 0x3 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT = 0x4 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT = 0x5 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT = 0x6 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT = 0x7 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT = 0x8 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT = 0x9 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT = 0xa # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT = 0xb # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT = 0xc # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT = 0xd # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT = 0xe # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT = 0xf # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT = 0x10 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT = 0x11 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT = 0x12 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT = 0x13 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT = 0x14 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT = 0x15 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT = 0x16 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT = 0x17 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT = 0x18 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT = 0x19 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT = 0x1a # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT = 0x1b # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT = 0x1c # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT = 0x1d # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT = 0x1e # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT = 0x1f # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK = 0x00000001 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK = 0x00000002 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK = 0x00000004 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK = 0x00000008 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK = 0x00000010 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK = 0x00000020 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK = 0x00000040 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK = 0x00000080 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK = 0x00000100 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK = 0x00000200 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK = 0x00000400 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK = 0x00000800 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK = 0x00001000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK = 0x00002000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK = 0x00004000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK = 0x00008000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK = 0x00010000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK = 0x00020000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK = 0x00040000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK = 0x00080000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK = 0x00100000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK = 0x00200000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK = 0x00400000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK = 0x00800000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK = 0x01000000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK = 0x02000000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK = 0x04000000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK = 0x08000000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK = 0x10000000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK = 0x20000000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK = 0x40000000 # macro +GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK = 0x80000000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT = 0x0 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT = 0x1 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT = 0x2 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT = 0x3 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT = 0x4 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT = 0x5 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT = 0x6 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT = 0x7 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT = 0x8 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT = 0x9 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT = 0xa # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT = 0xb # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT = 0xc # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT = 0xd # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT = 0xe # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT = 0xf # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT = 0x10 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT = 0x11 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT = 0x12 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT = 0x13 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT = 0x14 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT = 0x15 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT = 0x16 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT = 0x17 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT = 0x18 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT = 0x19 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT = 0x1a # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT = 0x1b # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT = 0x1c # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT = 0x1d # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT = 0x1e # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT = 0x1f # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK = 0x00000001 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK = 0x00000002 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK = 0x00000004 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK = 0x00000008 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK = 0x00000010 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK = 0x00000020 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK = 0x00000040 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK = 0x00000080 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK = 0x00000100 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK = 0x00000200 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK = 0x00000400 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK = 0x00000800 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK = 0x00001000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK = 0x00002000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK = 0x00004000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK = 0x00008000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK = 0x00010000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK = 0x00020000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK = 0x00040000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK = 0x00080000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK = 0x00100000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK = 0x00200000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK = 0x00400000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK = 0x00800000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK = 0x01000000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK = 0x02000000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK = 0x04000000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK = 0x08000000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK = 0x10000000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK = 0x20000000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK = 0x40000000 # macro +GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK = 0x80000000 # macro +GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT = 0x0 # macro +GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT = 0x10 # macro +GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT = 0x18 # macro +GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK = 0x000000FF # macro +GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK = 0x0000FF00 # macro +GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK = 0x00FF0000 # macro +GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK = 0xFF000000 # macro +GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT = 0x0 # macro +GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT = 0x8 # macro +GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT = 0x10 # macro +GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT = 0x11 # macro +GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT = 0x12 # macro +GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT = 0x13 # macro +GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT = 0x14 # macro +GCEA_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT = 0x15 # macro +GCEA_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING__SHIFT = 0x16 # macro +GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK = 0x0000007F # macro +GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK = 0x00007F00 # macro +GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK = 0x00010000 # macro +GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK = 0x00020000 # macro +GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK = 0x00040000 # macro +GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK = 0x00080000 # macro +GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK = 0x00100000 # macro +GCEA_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK = 0x00200000 # macro +GCEA_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING_MASK = 0x00400000 # macro +GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT = 0x0 # macro +GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT = 0x5 # macro +GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT = 0xa # macro +GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT = 0xf # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC0__SHIFT = 0x11 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC1__SHIFT = 0x12 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC2__SHIFT = 0x13 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC3__SHIFT = 0x14 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC4__SHIFT = 0x15 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC5__SHIFT = 0x16 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC6__SHIFT = 0x17 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC7__SHIFT = 0x18 # macro +GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT = 0x19 # macro +GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT = 0x1a # macro +GCEA_SDP_ARB_FINAL__DRAM_BURST_STRETCH__SHIFT = 0x1b # macro +GCEA_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT = 0x1c # macro +GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK = 0x0000001F # macro +GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK = 0x000003E0 # macro +GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK = 0x00007C00 # macro +GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK = 0x00018000 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC0_MASK = 0x00020000 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC1_MASK = 0x00040000 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC2_MASK = 0x00080000 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC3_MASK = 0x00100000 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC4_MASK = 0x00200000 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC5_MASK = 0x00400000 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC6_MASK = 0x00800000 # macro +GCEA_SDP_ARB_FINAL__RDONLY_VC7_MASK = 0x01000000 # macro +GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK = 0x02000000 # macro +GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK = 0x04000000 # macro +GCEA_SDP_ARB_FINAL__DRAM_BURST_STRETCH_MASK = 0x08000000 # macro +GCEA_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK = 0x10000000 # macro +GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT = 0x0 # macro +GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT = 0x4 # macro +GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT = 0x8 # macro +GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT = 0xc # macro +GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT = 0x10 # macro +GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT = 0x14 # macro +GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT = 0x18 # macro +GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT = 0x1c # macro +GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK = 0x0000000F # macro +GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK = 0x000000F0 # macro +GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK = 0x00000F00 # macro +GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK = 0x0000F000 # macro +GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK = 0x000F0000 # macro +GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK = 0x00F00000 # macro +GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK = 0x0F000000 # macro +GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK = 0xF0000000 # macro +GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT = 0x0 # macro +GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT = 0x4 # macro +GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT = 0x8 # macro +GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT = 0xc # macro +GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT = 0x10 # macro +GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT = 0x14 # macro +GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT = 0x18 # macro +GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT = 0x1c # macro +GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK = 0x0000000F # macro +GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK = 0x000000F0 # macro +GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK = 0x00000F00 # macro +GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK = 0x0000F000 # macro +GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK = 0x000F0000 # macro +GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK = 0x00F00000 # macro +GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK = 0x0F000000 # macro +GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK = 0xF0000000 # macro +GCEA_SDP_CREDITS__TAG_LIMIT__SHIFT = 0x0 # macro +GCEA_SDP_CREDITS__WR_RESP_CREDITS__SHIFT = 0x8 # macro +GCEA_SDP_CREDITS__RD_RESP_CREDITS__SHIFT = 0x10 # macro +GCEA_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT = 0x18 # macro +GCEA_SDP_CREDITS__TAG_LIMIT_MASK = 0x000000FF # macro +GCEA_SDP_CREDITS__WR_RESP_CREDITS_MASK = 0x00007F00 # macro +GCEA_SDP_CREDITS__RD_RESP_CREDITS_MASK = 0x007F0000 # macro +GCEA_SDP_CREDITS__PRB_REQ_CREDITS_MASK = 0x3F000000 # macro +GCEA_SDP_TAG_RESERVE0__VC0__SHIFT = 0x0 # macro +GCEA_SDP_TAG_RESERVE0__VC1__SHIFT = 0x8 # macro +GCEA_SDP_TAG_RESERVE0__VC2__SHIFT = 0x10 # macro +GCEA_SDP_TAG_RESERVE0__VC3__SHIFT = 0x18 # macro +GCEA_SDP_TAG_RESERVE0__VC0_MASK = 0x000000FF # macro +GCEA_SDP_TAG_RESERVE0__VC1_MASK = 0x0000FF00 # macro +GCEA_SDP_TAG_RESERVE0__VC2_MASK = 0x00FF0000 # macro +GCEA_SDP_TAG_RESERVE0__VC3_MASK = 0xFF000000 # macro +GCEA_SDP_TAG_RESERVE1__VC4__SHIFT = 0x0 # macro +GCEA_SDP_TAG_RESERVE1__VC5__SHIFT = 0x8 # macro +GCEA_SDP_TAG_RESERVE1__VC6__SHIFT = 0x10 # macro +GCEA_SDP_TAG_RESERVE1__VC7__SHIFT = 0x18 # macro +GCEA_SDP_TAG_RESERVE1__VC4_MASK = 0x000000FF # macro +GCEA_SDP_TAG_RESERVE1__VC5_MASK = 0x0000FF00 # macro +GCEA_SDP_TAG_RESERVE1__VC6_MASK = 0x00FF0000 # macro +GCEA_SDP_TAG_RESERVE1__VC7_MASK = 0xFF000000 # macro +GCEA_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT = 0x0 # macro +GCEA_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT = 0x6 # macro +GCEA_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT = 0xc # macro +GCEA_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT = 0x12 # macro +GCEA_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT = 0x18 # macro +GCEA_SDP_VCC_RESERVE0__VC0_CREDITS_MASK = 0x0000003F # macro +GCEA_SDP_VCC_RESERVE0__VC1_CREDITS_MASK = 0x00000FC0 # macro +GCEA_SDP_VCC_RESERVE0__VC2_CREDITS_MASK = 0x0003F000 # macro +GCEA_SDP_VCC_RESERVE0__VC3_CREDITS_MASK = 0x00FC0000 # macro +GCEA_SDP_VCC_RESERVE0__VC4_CREDITS_MASK = 0x3F000000 # macro +GCEA_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT = 0x0 # macro +GCEA_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT = 0x6 # macro +GCEA_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT = 0xc # macro +GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT = 0x1f # macro +GCEA_SDP_VCC_RESERVE1__VC5_CREDITS_MASK = 0x0000003F # macro +GCEA_SDP_VCC_RESERVE1__VC6_CREDITS_MASK = 0x00000FC0 # macro +GCEA_SDP_VCC_RESERVE1__VC7_CREDITS_MASK = 0x0003F000 # macro +GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK = 0x80000000 # macro +GCEA_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT = 0x0 # macro +GCEA_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT = 0x6 # macro +GCEA_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT = 0xc # macro +GCEA_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT = 0x12 # macro +GCEA_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT = 0x18 # macro +GCEA_SDP_VCD_RESERVE0__VC0_CREDITS_MASK = 0x0000003F # macro +GCEA_SDP_VCD_RESERVE0__VC1_CREDITS_MASK = 0x00000FC0 # macro +GCEA_SDP_VCD_RESERVE0__VC2_CREDITS_MASK = 0x0003F000 # macro +GCEA_SDP_VCD_RESERVE0__VC3_CREDITS_MASK = 0x00FC0000 # macro +GCEA_SDP_VCD_RESERVE0__VC4_CREDITS_MASK = 0x3F000000 # macro +GCEA_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT = 0x0 # macro +GCEA_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT = 0x6 # macro +GCEA_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT = 0xc # macro +GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT = 0x1f # macro +GCEA_SDP_VCD_RESERVE1__VC5_CREDITS_MASK = 0x0000003F # macro +GCEA_SDP_VCD_RESERVE1__VC6_CREDITS_MASK = 0x00000FC0 # macro +GCEA_SDP_VCD_RESERVE1__VC7_CREDITS_MASK = 0x0003F000 # macro +GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK = 0x80000000 # macro +GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT = 0x0 # macro +GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT = 0x1 # macro +GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT = 0x2 # macro +GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT = 0x3 # macro +GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT = 0x4 # macro +GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT = 0x5 # macro +GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT = 0x6 # macro +GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT = 0x8 # macro +GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT = 0xa # macro +GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK = 0x00000001 # macro +GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK = 0x00000002 # macro +GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK = 0x00000004 # macro +GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK = 0x00000008 # macro +GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK = 0x00000010 # macro +GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK = 0x00000020 # macro +GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK = 0x000000C0 # macro +GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK = 0x00000300 # macro +GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK = 0x00000C00 # macro +GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT = 0x0 # macro +GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT = 0x1 # macro +GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT = 0x2 # macro +GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT = 0x3 # macro +GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT = 0x4 # macro +GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT = 0x5 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT = 0x6 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT = 0x7 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT = 0x8 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT = 0x9 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT = 0xa # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT = 0xb # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT = 0xc # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT = 0xd # macro +GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT = 0xe # macro +GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT = 0xf # macro +GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT = 0x11 # macro +GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT = 0x13 # macro +GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT = 0x15 # macro +GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT = 0x1a # macro +GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT = 0x1b # macro +GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT = 0x1c # macro +GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT = 0x1d # macro +GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT = 0x1e # macro +GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT = 0x1f # macro +GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK = 0x00000001 # macro +GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK = 0x00000002 # macro +GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK = 0x00000004 # macro +GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK = 0x00000008 # macro +GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK = 0x00000010 # macro +GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK = 0x00000020 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK = 0x00000040 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK = 0x00000080 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK = 0x00000100 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK = 0x00000200 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK = 0x00000400 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK = 0x00000800 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK = 0x00001000 # macro +GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK = 0x00002000 # macro +GCEA_MISC__EARLY_SDP_ORIGDATA_MASK = 0x00004000 # macro +GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK = 0x00018000 # macro +GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK = 0x00060000 # macro +GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK = 0x00180000 # macro +GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK = 0x03E00000 # macro +GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK = 0x04000000 # macro +GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK = 0x08000000 # macro +GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK = 0x10000000 # macro +GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK = 0x20000000 # macro +GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK = 0x40000000 # macro +GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK = 0x80000000 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT = 0x0 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT = 0x1 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT = 0x2 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT = 0x3 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT = 0x4 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT = 0x5 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT = 0x6 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT = 0x7 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT = 0x8 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT = 0x9 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT = 0xa # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT = 0xb # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT = 0xc # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT = 0xd # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT = 0xe # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT = 0x16 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK = 0x00000001 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK = 0x00000002 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK = 0x00000004 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK = 0x00000008 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK = 0x00000010 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK = 0x00000020 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK = 0x00000040 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK = 0x00000080 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK = 0x00000100 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK = 0x00000200 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK = 0x00000400 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK = 0x00000800 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK = 0x00001000 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK = 0x00002000 # macro +GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK = 0x003FC000 # macro +GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK = 0x3FC00000 # macro +GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +GCEA_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +GCEA_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +GCEA_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +GCEA_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x0000000F # macro +GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +GCEA_MAM_CTRL__ADRAM_MODE__SHIFT = 0x0 # macro +GCEA_MAM_CTRL__ADRAM_COALESCE_DISABLE__SHIFT = 0x2 # macro +GCEA_MAM_CTRL__ARAM_FLUSH_CNTR_THRESHOLD__SHIFT = 0x3 # macro +GCEA_MAM_CTRL__ARAM_FLUSH_CNTR_DISABLE__SHIFT = 0x6 # macro +GCEA_MAM_CTRL__ARAM_FORCE_FLUSH__SHIFT = 0x7 # macro +GCEA_MAM_CTRL__ALOG_MODE1_FILTER1_THRESHOLD__SHIFT = 0x8 # macro +GCEA_MAM_CTRL__ALOG_MODE1_FILTER2_BYPASS__SHIFT = 0xb # macro +GCEA_MAM_CTRL__ALOG_ACTIVE__SHIFT = 0xc # macro +GCEA_MAM_CTRL__SDP_PRIORITY__SHIFT = 0xd # macro +GCEA_MAM_CTRL__CLIENT_ID__SHIFT = 0x11 # macro +GCEA_MAM_CTRL__MAM_DISABLE__SHIFT = 0x16 # macro +GCEA_MAM_CTRL__ARAM_FLUSH_RB_SIZE__SHIFT = 0x17 # macro +GCEA_MAM_CTRL__ALOG_MODE__SHIFT = 0x1b # macro +GCEA_MAM_CTRL__ALOG_MODE2_LOCK_WINDOW__SHIFT = 0x1c # macro +GCEA_MAM_CTRL__ALOG_TRACK_2M_SEGMENT__SHIFT = 0x1f # macro +GCEA_MAM_CTRL__ADRAM_MODE_MASK = 0x00000003 # macro +GCEA_MAM_CTRL__ADRAM_COALESCE_DISABLE_MASK = 0x00000004 # macro +GCEA_MAM_CTRL__ARAM_FLUSH_CNTR_THRESHOLD_MASK = 0x00000038 # macro +GCEA_MAM_CTRL__ARAM_FLUSH_CNTR_DISABLE_MASK = 0x00000040 # macro +GCEA_MAM_CTRL__ARAM_FORCE_FLUSH_MASK = 0x00000080 # macro +GCEA_MAM_CTRL__ALOG_MODE1_FILTER1_THRESHOLD_MASK = 0x00000700 # macro +GCEA_MAM_CTRL__ALOG_MODE1_FILTER2_BYPASS_MASK = 0x00000800 # macro +GCEA_MAM_CTRL__ALOG_ACTIVE_MASK = 0x00001000 # macro +GCEA_MAM_CTRL__SDP_PRIORITY_MASK = 0x0001E000 # macro +GCEA_MAM_CTRL__CLIENT_ID_MASK = 0x003E0000 # macro +GCEA_MAM_CTRL__MAM_DISABLE_MASK = 0x00400000 # macro +GCEA_MAM_CTRL__ARAM_FLUSH_RB_SIZE_MASK = 0x07800000 # macro +GCEA_MAM_CTRL__ALOG_MODE_MASK = 0x08000000 # macro +GCEA_MAM_CTRL__ALOG_MODE2_LOCK_WINDOW_MASK = 0x70000000 # macro +GCEA_MAM_CTRL__ALOG_TRACK_2M_SEGMENT_MASK = 0x80000000 # macro +GCEA_MAM_CTRL2__ALOG_MODE2_INTR_THRESHOLD__SHIFT = 0x0 # macro +GCEA_MAM_CTRL2__ALOG_SPACE_EN__SHIFT = 0x2 # macro +GCEA_MAM_CTRL2__ARAM_FLUSH_SNOOP_EN__SHIFT = 0x5 # macro +GCEA_MAM_CTRL2__ARAM_FLUSH_NOALLOC__SHIFT = 0x6 # macro +GCEA_MAM_CTRL2__RESERVED_FIELD__SHIFT = 0x7 # macro +GCEA_MAM_CTRL2__ADDR_HI__SHIFT = 0x18 # macro +GCEA_MAM_CTRL2__ALOG_MODE2_INTR_THRESHOLD_MASK = 0x00000003 # macro +GCEA_MAM_CTRL2__ALOG_SPACE_EN_MASK = 0x0000001C # macro +GCEA_MAM_CTRL2__ARAM_FLUSH_SNOOP_EN_MASK = 0x00000020 # macro +GCEA_MAM_CTRL2__ARAM_FLUSH_NOALLOC_MASK = 0x00000040 # macro +GCEA_MAM_CTRL2__RESERVED_FIELD_MASK = 0x00FFFF80 # macro +GCEA_MAM_CTRL2__ADDR_HI_MASK = 0xFF000000 # macro +GCEA_UE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT = 0x0 # macro +GCEA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +GCEA_UE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +GCEA_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +GCEA_UE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK = 0x00000001 # macro +GCEA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +GCEA_UE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +GCEA_UE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +GCEA_UE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +GCEA_UE_ERR_STATUS_HI__PARITY__SHIFT = 0x1 # macro +GCEA_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +GCEA_UE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +GCEA_UE_ERR_STATUS_HI__UE_CNT__SHIFT = 0x17 # macro +GCEA_UE_ERR_STATUS_HI__FED_CNT__SHIFT = 0x1a # macro +GCEA_UE_ERR_STATUS_HI__RESERVED_FIELD__SHIFT = 0x1d # macro +GCEA_UE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +GCEA_UE_ERR_STATUS_HI__PARITY_MASK = 0x00000002 # macro +GCEA_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +GCEA_UE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +GCEA_UE_ERR_STATUS_HI__UE_CNT_MASK = 0x03800000 # macro +GCEA_UE_ERR_STATUS_HI__FED_CNT_MASK = 0x1C000000 # macro +GCEA_UE_ERR_STATUS_HI__RESERVED_FIELD_MASK = 0xE0000000 # macro +GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT = 0x0 # macro +GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x2 # macro +GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT = 0x3 # macro +GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x5 # macro +GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT = 0x6 # macro +GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x8 # macro +GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT = 0x9 # macro +GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT = 0xb # macro +GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT = 0xc # macro +GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT = 0xe # macro +GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT = 0xf # macro +GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x11 # macro +GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT = 0x12 # macro +GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x14 # macro +GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT = 0x15 # macro +GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x17 # macro +GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK = 0x00000003 # macro +GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK = 0x00000004 # macro +GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK = 0x00000018 # macro +GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK = 0x00000020 # macro +GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK = 0x000000C0 # macro +GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK = 0x00000100 # macro +GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK = 0x00000600 # macro +GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK = 0x00000800 # macro +GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK = 0x00003000 # macro +GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK = 0x00004000 # macro +GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK = 0x00018000 # macro +GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK = 0x00020000 # macro +GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK = 0x000C0000 # macro +GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK = 0x00100000 # macro +GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK = 0x00600000 # macro +GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK = 0x00800000 # macro +GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT = 0x0 # macro +GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x2 # macro +GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT = 0x3 # macro +GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x5 # macro +GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT = 0x6 # macro +GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x8 # macro +GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT = 0x9 # macro +GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT = 0xb # macro +GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT = 0xc # macro +GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT = 0xe # macro +GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT = 0xf # macro +GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x11 # macro +GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT = 0x12 # macro +GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x14 # macro +GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK = 0x00000003 # macro +GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK = 0x00000004 # macro +GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK = 0x00000018 # macro +GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK = 0x00000020 # macro +GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK = 0x000000C0 # macro +GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK = 0x00000100 # macro +GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK = 0x00000600 # macro +GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK = 0x00000800 # macro +GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK = 0x00003000 # macro +GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK = 0x00004000 # macro +GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK = 0x00018000 # macro +GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK = 0x00020000 # macro +GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK = 0x000C0000 # macro +GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK = 0x00100000 # macro +GCEA_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA__SHIFT = 0x0 # macro +GCEA_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE__SHIFT = 0x2 # macro +GCEA_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA__SHIFT = 0x3 # macro +GCEA_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE__SHIFT = 0x5 # macro +GCEA_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA__SHIFT = 0x6 # macro +GCEA_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE__SHIFT = 0x8 # macro +GCEA_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA__SHIFT = 0x9 # macro +GCEA_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE__SHIFT = 0xb # macro +GCEA_DSM_CNTLB__MAM_A0MEM_DSM_IRRITATOR_DATA__SHIFT = 0xc # macro +GCEA_DSM_CNTLB__MAM_A0MEM_ENABLE_SINGLE_WRITE__SHIFT = 0xe # macro +GCEA_DSM_CNTLB__MAM_A1MEM_DSM_IRRITATOR_DATA__SHIFT = 0xf # macro +GCEA_DSM_CNTLB__MAM_A1MEM_ENABLE_SINGLE_WRITE__SHIFT = 0x11 # macro +GCEA_DSM_CNTLB__MAM_A2MEM_DSM_IRRITATOR_DATA__SHIFT = 0x12 # macro +GCEA_DSM_CNTLB__MAM_A2MEM_ENABLE_SINGLE_WRITE__SHIFT = 0x14 # macro +GCEA_DSM_CNTLB__MAM_A3MEM_DSM_IRRITATOR_DATA__SHIFT = 0x15 # macro +GCEA_DSM_CNTLB__MAM_A3MEM_ENABLE_SINGLE_WRITE__SHIFT = 0x17 # macro +GCEA_DSM_CNTLB__MAM_AFMEM_DSM_IRRITATOR_DATA__SHIFT = 0x18 # macro +GCEA_DSM_CNTLB__MAM_AFMEM_ENABLE_SINGLE_WRITE__SHIFT = 0x1a # macro +GCEA_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA_MASK = 0x00000003 # macro +GCEA_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE_MASK = 0x00000004 # macro +GCEA_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA_MASK = 0x00000018 # macro +GCEA_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE_MASK = 0x00000020 # macro +GCEA_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA_MASK = 0x000000C0 # macro +GCEA_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE_MASK = 0x00000100 # macro +GCEA_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA_MASK = 0x00000600 # macro +GCEA_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE_MASK = 0x00000800 # macro +GCEA_DSM_CNTLB__MAM_A0MEM_DSM_IRRITATOR_DATA_MASK = 0x00003000 # macro +GCEA_DSM_CNTLB__MAM_A0MEM_ENABLE_SINGLE_WRITE_MASK = 0x00004000 # macro +GCEA_DSM_CNTLB__MAM_A1MEM_DSM_IRRITATOR_DATA_MASK = 0x00018000 # macro +GCEA_DSM_CNTLB__MAM_A1MEM_ENABLE_SINGLE_WRITE_MASK = 0x00020000 # macro +GCEA_DSM_CNTLB__MAM_A2MEM_DSM_IRRITATOR_DATA_MASK = 0x000C0000 # macro +GCEA_DSM_CNTLB__MAM_A2MEM_ENABLE_SINGLE_WRITE_MASK = 0x00100000 # macro +GCEA_DSM_CNTLB__MAM_A3MEM_DSM_IRRITATOR_DATA_MASK = 0x00600000 # macro +GCEA_DSM_CNTLB__MAM_A3MEM_ENABLE_SINGLE_WRITE_MASK = 0x00800000 # macro +GCEA_DSM_CNTLB__MAM_AFMEM_DSM_IRRITATOR_DATA_MASK = 0x03000000 # macro +GCEA_DSM_CNTLB__MAM_AFMEM_ENABLE_SINGLE_WRITE_MASK = 0x04000000 # macro +GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT = 0x6 # macro +GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT = 0x8 # macro +GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT = 0xb # macro +GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT = 0xc # macro +GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT = 0xe # macro +GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT = 0xf # macro +GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT = 0x11 # macro +GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT = 0x12 # macro +GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT = 0x14 # macro +GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT = 0x15 # macro +GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT = 0x17 # macro +GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT = 0x1a # macro +GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK = 0x000000C0 # macro +GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK = 0x00000100 # macro +GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK = 0x00003000 # macro +GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK = 0x00004000 # macro +GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK = 0x00018000 # macro +GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK = 0x00020000 # macro +GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK = 0x000C0000 # macro +GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK = 0x00100000 # macro +GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK = 0x00600000 # macro +GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK = 0x00800000 # macro +GCEA_DSM_CNTL2__INJECT_DELAY_MASK = 0xFC000000 # macro +GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT = 0x6 # macro +GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT = 0x8 # macro +GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT = 0xb # macro +GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT = 0xc # macro +GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT = 0xe # macro +GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT = 0xf # macro +GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT = 0x11 # macro +GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT = 0x12 # macro +GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT = 0x14 # macro +GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK = 0x000000C0 # macro +GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK = 0x00000100 # macro +GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK = 0x00003000 # macro +GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK = 0x00004000 # macro +GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK = 0x00018000 # macro +GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK = 0x00020000 # macro +GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK = 0x000C0000 # macro +GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK = 0x00100000 # macro +GCEA_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +GCEA_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +GCEA_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +GCEA_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +GCEA_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT__SHIFT = 0x6 # macro +GCEA_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY__SHIFT = 0x8 # macro +GCEA_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +GCEA_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY__SHIFT = 0xb # macro +GCEA_DSM_CNTL2B__MAM_A0MEM_ENABLE_ERROR_INJECT__SHIFT = 0xc # macro +GCEA_DSM_CNTL2B__MAM_A0MEM_SELECT_INJECT_DELAY__SHIFT = 0xe # macro +GCEA_DSM_CNTL2B__MAM_A1MEM_ENABLE_ERROR_INJECT__SHIFT = 0xf # macro +GCEA_DSM_CNTL2B__MAM_A1MEM_SELECT_INJECT_DELAY__SHIFT = 0x11 # macro +GCEA_DSM_CNTL2B__MAM_A2MEM_ENABLE_ERROR_INJECT__SHIFT = 0x12 # macro +GCEA_DSM_CNTL2B__MAM_A2MEM_SELECT_INJECT_DELAY__SHIFT = 0x14 # macro +GCEA_DSM_CNTL2B__MAM_A3MEM_ENABLE_ERROR_INJECT__SHIFT = 0x15 # macro +GCEA_DSM_CNTL2B__MAM_A3MEM_SELECT_INJECT_DELAY__SHIFT = 0x17 # macro +GCEA_DSM_CNTL2B__MAM_AFMEM_ENABLE_ERROR_INJECT__SHIFT = 0x18 # macro +GCEA_DSM_CNTL2B__MAM_AFMEM_SELECT_INJECT_DELAY__SHIFT = 0x1a # macro +GCEA_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +GCEA_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +GCEA_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +GCEA_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +GCEA_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT_MASK = 0x000000C0 # macro +GCEA_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY_MASK = 0x00000100 # macro +GCEA_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +GCEA_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +GCEA_DSM_CNTL2B__MAM_A0MEM_ENABLE_ERROR_INJECT_MASK = 0x00003000 # macro +GCEA_DSM_CNTL2B__MAM_A0MEM_SELECT_INJECT_DELAY_MASK = 0x00004000 # macro +GCEA_DSM_CNTL2B__MAM_A1MEM_ENABLE_ERROR_INJECT_MASK = 0x00018000 # macro +GCEA_DSM_CNTL2B__MAM_A1MEM_SELECT_INJECT_DELAY_MASK = 0x00020000 # macro +GCEA_DSM_CNTL2B__MAM_A2MEM_ENABLE_ERROR_INJECT_MASK = 0x000C0000 # macro +GCEA_DSM_CNTL2B__MAM_A2MEM_SELECT_INJECT_DELAY_MASK = 0x00100000 # macro +GCEA_DSM_CNTL2B__MAM_A3MEM_ENABLE_ERROR_INJECT_MASK = 0x00600000 # macro +GCEA_DSM_CNTL2B__MAM_A3MEM_SELECT_INJECT_DELAY_MASK = 0x00800000 # macro +GCEA_DSM_CNTL2B__MAM_AFMEM_ENABLE_ERROR_INJECT_MASK = 0x03000000 # macro +GCEA_DSM_CNTL2B__MAM_AFMEM_SELECT_INJECT_DELAY_MASK = 0x04000000 # macro +GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT = 0x0 # macro +GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT = 0x6 # macro +GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT__SHIFT = 0x8 # macro +GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE__SHIFT = 0xe # macro +GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT = 0x10 # macro +GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT = 0x16 # macro +GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT__SHIFT = 0x18 # macro +GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE__SHIFT = 0x1e # macro +GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT_MASK = 0x0000003F # macro +GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE_MASK = 0x000000C0 # macro +GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT_MASK = 0x00003F00 # macro +GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE_MASK = 0x0000C000 # macro +GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT_MASK = 0x003F0000 # macro +GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE_MASK = 0x00C00000 # macro +GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT_MASK = 0x3F000000 # macro +GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE_MASK = 0xC0000000 # macro +GCEA_TCC_XBR_MAXBURST__DRAM_RD__SHIFT = 0x0 # macro +GCEA_TCC_XBR_MAXBURST__IO_RD__SHIFT = 0x4 # macro +GCEA_TCC_XBR_MAXBURST__DRAM_WR__SHIFT = 0x8 # macro +GCEA_TCC_XBR_MAXBURST__IO_WR__SHIFT = 0xc # macro +GCEA_TCC_XBR_MAXBURST__DRAM_RD_MASK = 0x0000000F # macro +GCEA_TCC_XBR_MAXBURST__IO_RD_MASK = 0x000000F0 # macro +GCEA_TCC_XBR_MAXBURST__DRAM_WR_MASK = 0x00000F00 # macro +GCEA_TCC_XBR_MAXBURST__IO_WR_MASK = 0x0000F000 # macro +GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT = 0x0 # macro +GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT = 0x5 # macro +GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK = 0x0000001F # macro +GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK = 0x00000020 # macro +GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC__SHIFT = 0x0 # macro +GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC__SHIFT = 0x1 # macro +GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC__SHIFT = 0x2 # macro +GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC__SHIFT = 0x3 # macro +GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC__SHIFT = 0x4 # macro +GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC__SHIFT = 0x5 # macro +GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC__SHIFT = 0x6 # macro +GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC__SHIFT = 0x7 # macro +GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC__SHIFT = 0x8 # macro +GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC__SHIFT = 0x9 # macro +GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC__SHIFT = 0xa # macro +GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC__SHIFT = 0xb # macro +GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC__SHIFT = 0xc # macro +GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC__SHIFT = 0xd # macro +GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC__SHIFT = 0xe # macro +GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC__SHIFT = 0xf # macro +GCEA_PROBE_MAP__INTLV_SIZE__SHIFT = 0x10 # macro +GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC_MASK = 0x00000001 # macro +GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC_MASK = 0x00000002 # macro +GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC_MASK = 0x00000004 # macro +GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC_MASK = 0x00000008 # macro +GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC_MASK = 0x00000010 # macro +GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC_MASK = 0x00000020 # macro +GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC_MASK = 0x00000040 # macro +GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC_MASK = 0x00000080 # macro +GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC_MASK = 0x00000100 # macro +GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC_MASK = 0x00000200 # macro +GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC_MASK = 0x00000400 # macro +GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC_MASK = 0x00000800 # macro +GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC_MASK = 0x00001000 # macro +GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC_MASK = 0x00002000 # macro +GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC_MASK = 0x00004000 # macro +GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC_MASK = 0x00008000 # macro +GCEA_PROBE_MAP__INTLV_SIZE_MASK = 0x00030000 # macro +GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT = 0x0 # macro +GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT = 0x4 # macro +GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT = 0x8 # macro +GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT = 0xa # macro +GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT = 0xb # macro +GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT = 0xc # macro +GCEA_ERR_STATUS__FUE_FLAG__SHIFT = 0xd # macro +GCEA_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT = 0xe # macro +GCEA_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT = 0xf # macro +GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT = 0x10 # macro +GCEA_ERR_STATUS__LEVEL_INTERRUPT__SHIFT = 0x11 # macro +GCEA_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT = 0x12 # macro +GCEA_ERR_STATUS__FUE_FLAG_CLIENT__SHIFT = 0x13 # macro +GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK = 0x0000000F # macro +GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK = 0x000000F0 # macro +GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK = 0x00000300 # macro +GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK = 0x00000400 # macro +GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK = 0x00000800 # macro +GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK = 0x00001000 # macro +GCEA_ERR_STATUS__FUE_FLAG_MASK = 0x00002000 # macro +GCEA_ERR_STATUS__IGNORE_RDRSP_FED_MASK = 0x00004000 # macro +GCEA_ERR_STATUS__INTERRUPT_ON_FATAL_MASK = 0x00008000 # macro +GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK = 0x00010000 # macro +GCEA_ERR_STATUS__LEVEL_INTERRUPT_MASK = 0x00020000 # macro +GCEA_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK = 0x00040000 # macro +GCEA_ERR_STATUS__FUE_FLAG_CLIENT_MASK = 0x00080000 # macro +GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT = 0x0 # macro +GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT = 0x1 # macro +GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT = 0x2 # macro +GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT = 0x7 # macro +GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT = 0xc # macro +GCEA_MISC2__BLOCK_REQUESTS__SHIFT = 0xd # macro +GCEA_MISC2__REQUESTS_BLOCKED__SHIFT = 0xe # macro +GCEA_MISC2__FGCLKEN_OVERRIDE__SHIFT = 0xf # macro +GCEA_MISC2__DRAM_RD_THROTTLE__SHIFT = 0x10 # macro +GCEA_MISC2__DRAM_WR_THROTTLE__SHIFT = 0x11 # macro +GCEA_MISC2__GMI_RD_THROTTLE__SHIFT = 0x12 # macro +GCEA_MISC2__GMI_WR_THROTTLE__SHIFT = 0x13 # macro +GCEA_MISC2__CONTAIN_ILLEGAL_OP__SHIFT = 0x14 # macro +GCEA_MISC2__REPORT_ILLEGAL_OP__SHIFT = 0x15 # macro +GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK = 0x00000001 # macro +GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK = 0x00000002 # macro +GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK = 0x0000007C # macro +GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK = 0x00000F80 # macro +GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK = 0x00001000 # macro +GCEA_MISC2__BLOCK_REQUESTS_MASK = 0x00002000 # macro +GCEA_MISC2__REQUESTS_BLOCKED_MASK = 0x00004000 # macro +GCEA_MISC2__FGCLKEN_OVERRIDE_MASK = 0x00008000 # macro +GCEA_MISC2__DRAM_RD_THROTTLE_MASK = 0x00010000 # macro +GCEA_MISC2__DRAM_WR_THROTTLE_MASK = 0x00020000 # macro +GCEA_MISC2__GMI_RD_THROTTLE_MASK = 0x00040000 # macro +GCEA_MISC2__GMI_WR_THROTTLE_MASK = 0x00080000 # macro +GCEA_MISC2__CONTAIN_ILLEGAL_OP_MASK = 0x00100000 # macro +GCEA_MISC2__REPORT_ILLEGAL_OP_MASK = 0x00200000 # macro +GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED__SHIFT = 0x0 # macro +GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED__SHIFT = 0x7 # macro +GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED__SHIFT = 0xe # macro +GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED__SHIFT = 0x15 # macro +GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED__SHIFT = 0x1c # macro +GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED_MASK = 0x0000007F # macro +GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED_MASK = 0x00003F80 # macro +GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED_MASK = 0x001FC000 # macro +GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED_MASK = 0x0FE00000 # macro +GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED_MASK = 0xF0000000 # macro +GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED__SHIFT = 0x0 # macro +GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED__SHIFT = 0x3 # macro +GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED__SHIFT = 0xa # macro +GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED__SHIFT = 0x11 # macro +GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED__SHIFT = 0x18 # macro +GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED_MASK = 0x00000007 # macro +GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED_MASK = 0x000003F8 # macro +GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED_MASK = 0x0001FC00 # macro +GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED_MASK = 0x00FE0000 # macro +GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED_MASK = 0x7F000000 # macro +GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED__SHIFT = 0x0 # macro +GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED__SHIFT = 0x7 # macro +GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED__SHIFT = 0xe # macro +GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED__SHIFT = 0x15 # macro +GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED__SHIFT = 0x1c # macro +GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED_MASK = 0x0000007F # macro +GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED_MASK = 0x00003F80 # macro +GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED_MASK = 0x001FC000 # macro +GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED_MASK = 0x0FE00000 # macro +GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED_MASK = 0xF0000000 # macro +GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED__SHIFT = 0x0 # macro +GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED__SHIFT = 0x3 # macro +GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED__SHIFT = 0xa # macro +GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED__SHIFT = 0x11 # macro +GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED__SHIFT = 0x18 # macro +GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED_MASK = 0x00000007 # macro +GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED_MASK = 0x000003F8 # macro +GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED_MASK = 0x0001FC00 # macro +GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED_MASK = 0x00FE0000 # macro +GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED_MASK = 0x7F000000 # macro +GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT = 0x0 # macro +GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT = 0x8 # macro +GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED__SHIFT = 0x10 # macro +GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED__SHIFT = 0x17 # macro +GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK = 0x000000FF # macro +GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK = 0x0000FF00 # macro +GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED_MASK = 0x007F0000 # macro +GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED_MASK = 0x3F800000 # macro +GCEA_CE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT = 0x0 # macro +GCEA_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +GCEA_CE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +GCEA_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +GCEA_CE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK = 0x00000001 # macro +GCEA_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +GCEA_CE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +GCEA_CE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +GCEA_CE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD0__SHIFT = 0x1 # macro +GCEA_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +GCEA_CE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +GCEA_CE_ERR_STATUS_HI__CE_CNT__SHIFT = 0x17 # macro +GCEA_CE_ERR_STATUS_HI__POISON__SHIFT = 0x1a # macro +GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD1__SHIFT = 0x1b # macro +GCEA_CE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD0_MASK = 0x00000002 # macro +GCEA_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +GCEA_CE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +GCEA_CE_ERR_STATUS_HI__CE_CNT_MASK = 0x03800000 # macro +GCEA_CE_ERR_STATUS_HI__POISON_MASK = 0x04000000 # macro +GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD1_MASK = 0xF8000000 # macro +GCEA_SDP_ENABLE__ENABLE__SHIFT = 0x0 # macro +GCEA_SDP_ENABLE__ENABLE_MASK = 0x00000001 # macro +GCEA_ICG_CTRL__SOFT_OVERRIDE_RETURN__SHIFT = 0x0 # macro +GCEA_ICG_CTRL__SOFT_OVERRIDE_READ__SHIFT = 0x1 # macro +GCEA_ICG_CTRL__SOFT_OVERRIDE_WRITE__SHIFT = 0x2 # macro +GCEA_ICG_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT = 0x3 # macro +GCEA_ICG_CTRL__SOFT_OVERRIDE_RETURN_MASK = 0x00000001 # macro +GCEA_ICG_CTRL__SOFT_OVERRIDE_READ_MASK = 0x00000002 # macro +GCEA_ICG_CTRL__SOFT_OVERRIDE_WRITE_MASK = 0x00000004 # macro +GCEA_ICG_CTRL__SOFT_OVERRIDE_REGISTER_MASK = 0x00000008 # macro +RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT = 0x0 # macro +RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT = 0x1 # macro +RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT = 0x11 # macro +RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT = 0x13 # macro +RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT = 0x14 # macro +RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT = 0x15 # macro +RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT = 0x19 # macro +RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT = 0x1a # macro +RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT = 0x1b # macro +RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT = 0x1c # macro +RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT = 0x1d # macro +RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT = 0x1e # macro +RMI_GENERAL_CNTL__BURST_DISABLE_MASK = 0x00000001 # macro +RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK = 0x0001FFFE # macro +RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK = 0x00060000 # macro +RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK = 0x00080000 # macro +RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK = 0x00100000 # macro +RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK = 0x01E00000 # macro +RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK = 0x02000000 # macro +RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK = 0x04000000 # macro +RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK = 0x08000000 # macro +RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK = 0x10000000 # macro +RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK = 0x20000000 # macro +RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK = 0x40000000 # macro +RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT = 0x0 # macro +RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT = 0x4 # macro +RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT = 0x6 # macro +RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT = 0x8 # macro +RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT = 0x9 # macro +RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT = 0xa # macro +RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT = 0xb # macro +RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT = 0xc # macro +RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK = 0x0000000F # macro +RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK = 0x00000030 # macro +RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK = 0x000000C0 # macro +RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK = 0x00000100 # macro +RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK = 0x00000200 # macro +RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK = 0x00000400 # macro +RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK = 0x00000800 # macro +RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK = 0x00001000 # macro +RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT = 0x0 # macro +RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT = 0x1 # macro +RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT = 0x2 # macro +RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT = 0x3 # macro +RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT = 0x4 # macro +RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT = 0x5 # macro +RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT = 0x6 # macro +RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT = 0x7 # macro +RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT = 0x8 # macro +RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT = 0x9 # macro +RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT = 0xa # macro +RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT = 0xb # macro +RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT = 0xc # macro +RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT = 0xd # macro +RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT = 0xe # macro +RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT = 0xf # macro +RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT = 0x10 # macro +RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT = 0x11 # macro +RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT = 0x12 # macro +RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT = 0x13 # macro +RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT = 0x14 # macro +RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT = 0x15 # macro +RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT = 0x1d # macro +RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT = 0x1e # macro +RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT = 0x1f # macro +RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK = 0x00000001 # macro +RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK = 0x00000002 # macro +RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK = 0x00000004 # macro +RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK = 0x00000008 # macro +RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK = 0x00000010 # macro +RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK = 0x00000020 # macro +RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK = 0x00000040 # macro +RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK = 0x00000080 # macro +RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK = 0x00000100 # macro +RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK = 0x00000200 # macro +RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK = 0x00000400 # macro +RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK = 0x00000800 # macro +RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK = 0x00001000 # macro +RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK = 0x00002000 # macro +RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK = 0x00004000 # macro +RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK = 0x00008000 # macro +RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK = 0x00010000 # macro +RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK = 0x00020000 # macro +RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK = 0x00040000 # macro +RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK = 0x00080000 # macro +RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK = 0x00100000 # macro +RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK = 0x1FE00000 # macro +RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK = 0x20000000 # macro +RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK = 0x40000000 # macro +RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK = 0x80000000 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT = 0x0 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT = 0x7 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT = 0x8 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT = 0x9 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT = 0x10 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT = 0x11 # macro +RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT = 0x12 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK = 0x0000007F # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK = 0x00000080 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK = 0x00000100 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK = 0x0000FE00 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK = 0x00010000 # macro +RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK = 0x00020000 # macro +RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK = 0x0FFC0000 # macro +RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT = 0x0 # macro +RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT = 0xa # macro +RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT = 0x14 # macro +RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK = 0x000003FF # macro +RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK = 0x000FFC00 # macro +RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK = 0x3FF00000 # macro +RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT = 0x0 # macro +RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT = 0x9 # macro +RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK = 0x000001FF # macro +RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK = 0x0003FE00 # macro +RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT = 0x0 # macro +RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT = 0xa # macro +RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK = 0x000003FF # macro +RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK = 0x000FFC00 # macro +RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT = 0x0 # macro +RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT = 0x2 # macro +RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT = 0x6 # macro +RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT = 0x7 # macro +RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT = 0x8 # macro +RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT = 0xc # macro +RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT = 0xd # macro +RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT = 0xe # macro +RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK = 0x00000003 # macro +RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK = 0x0000003C # macro +RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK = 0x00000040 # macro +RMI_XBAR_CONFIG__ARBITER_DIS_MASK = 0x00000080 # macro +RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK = 0x00000F00 # macro +RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK = 0x00001000 # macro +RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK = 0x00002000 # macro +RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK = 0x00004000 # macro +RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT = 0x0 # macro +RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT = 0x7 # macro +RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT = 0x8 # macro +RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT = 0xa # macro +RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT = 0x11 # macro +RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK = 0x0000007F # macro +RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK = 0x00000080 # macro +RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK = 0x00000300 # macro +RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK = 0x0001FC00 # macro +RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK = 0x00020000 # macro +RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT = 0x0 # macro +RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT = 0x8 # macro +RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT = 0xc # macro +RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT = 0xd # macro +RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK = 0x000000FF # macro +RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK = 0x00000F00 # macro +RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK = 0x00001000 # macro +RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK = 0x00002000 # macro +RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT = 0x0 # macro +RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT = 0x1 # macro +RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT = 0x4 # macro +RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT = 0x6 # macro +RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT = 0xe # macro +RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT = 0x10 # macro +RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT = 0x11 # macro +RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT = 0x14 # macro +RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT = 0x16 # macro +RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT = 0x1e # macro +RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK = 0x00000001 # macro +RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK = 0x00000002 # macro +RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK = 0x00000030 # macro +RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK = 0x00003FC0 # macro +RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK = 0x0000C000 # macro +RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK = 0x00010000 # macro +RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK = 0x00020000 # macro +RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK = 0x00300000 # macro +RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK = 0x3FC00000 # macro +RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK = 0xC0000000 # macro +RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT = 0x0 # macro +RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT = 0x1 # macro +RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT = 0x2 # macro +RMI_UTCL1_CNTL1__RESP_MODE__SHIFT = 0x3 # macro +RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT = 0x5 # macro +RMI_UTCL1_CNTL1__CLIENTID__SHIFT = 0x7 # macro +RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT = 0x10 # macro +RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT = 0x11 # macro +RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT = 0x12 # macro +RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT = 0x13 # macro +RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT = 0x17 # macro +RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT = 0x18 # macro +RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT = 0x19 # macro +RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT = 0x1a # macro +RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT = 0x1b # macro +RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT = 0x1c # macro +RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT = 0x1e # macro +RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK = 0x00000001 # macro +RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK = 0x00000002 # macro +RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK = 0x00000004 # macro +RMI_UTCL1_CNTL1__RESP_MODE_MASK = 0x00000018 # macro +RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK = 0x00000060 # macro +RMI_UTCL1_CNTL1__CLIENTID_MASK = 0x0000FF80 # macro +RMI_UTCL1_CNTL1__USERVM_DIS_MASK = 0x00010000 # macro +RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK = 0x00020000 # macro +RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK = 0x00040000 # macro +RMI_UTCL1_CNTL1__REG_INV_VMID_MASK = 0x00780000 # macro +RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK = 0x00800000 # macro +RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK = 0x01000000 # macro +RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK = 0x02000000 # macro +RMI_UTCL1_CNTL1__FORCE_MISS_MASK = 0x04000000 # macro +RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK = 0x08000000 # macro +RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK = 0x30000000 # macro +RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK = 0xC0000000 # macro +RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT = 0x0 # macro +RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT = 0x9 # macro +RMI_UTCL1_CNTL2__LINE_VALID__SHIFT = 0xa # macro +RMI_UTCL1_CNTL2__DIS_EDC__SHIFT = 0xb # macro +RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT = 0xc # macro +RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT = 0xd # macro +RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT = 0xe # macro +RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT = 0xf # macro +RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT = 0x10 # macro +RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT = 0x12 # macro +RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT = 0x13 # macro +RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT = 0x14 # macro +RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT = 0x15 # macro +RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT = 0x19 # macro +RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT = 0x1a # macro +RMI_UTCL1_CNTL2__UTC_SPARE_MASK = 0x000000FF # macro +RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK = 0x00000200 # macro +RMI_UTCL1_CNTL2__LINE_VALID_MASK = 0x00000400 # macro +RMI_UTCL1_CNTL2__DIS_EDC_MASK = 0x00000800 # macro +RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK = 0x00001000 # macro +RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK = 0x00002000 # macro +RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK = 0x00004000 # macro +RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK = 0x00008000 # macro +RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK = 0x00030000 # macro +RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK = 0x00040000 # macro +RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK = 0x00080000 # macro +RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK = 0x00100000 # macro +RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK = 0x01E00000 # macro +RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK = 0x02000000 # macro +RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK = 0x04000000 # macro +RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN__SHIFT = 0x0 # macro +RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN_MASK = 0x0000FFFF # macro +RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT = 0x0 # macro +RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT = 0x1 # macro +RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT = 0x9 # macro +RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT = 0x13 # macro +RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT = 0x1b # macro +RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT = 0x1c # macro +RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT = 0x1d # macro +RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT = 0x1e # macro +RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT = 0x1f # macro +RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK = 0x00000001 # macro +RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK = 0x000001FE # macro +RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK = 0x0007FE00 # macro +RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK = 0x07F80000 # macro +RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK = 0x08000000 # macro +RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK = 0x10000000 # macro +RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK = 0x20000000 # macro +RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK = 0x40000000 # macro +RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK = 0x80000000 # macro +RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT = 0x0 # macro +RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT = 0x1 # macro +RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT = 0x9 # macro +RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT = 0x13 # macro +RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT = 0x1b # macro +RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT = 0x1c # macro +RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT = 0x1d # macro +RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT = 0x1e # macro +RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT = 0x1f # macro +RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK = 0x00000001 # macro +RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK = 0x000001FE # macro +RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK = 0x0007FE00 # macro +RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK = 0x07F80000 # macro +RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK = 0x08000000 # macro +RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK = 0x10000000 # macro +RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK = 0x20000000 # macro +RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK = 0x40000000 # macro +RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK = 0x80000000 # macro +RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT = 0x0 # macro +RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT = 0x1 # macro +RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT = 0x2 # macro +RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT = 0x3 # macro +RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT = 0x4 # macro +RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT = 0x5 # macro +RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT = 0x6 # macro +RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT = 0x7 # macro +RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT = 0x8 # macro +RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT = 0x9 # macro +RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK = 0x00000001 # macro +RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK = 0x00000002 # macro +RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK = 0x00000004 # macro +RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK = 0x00000008 # macro +RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK = 0x00000010 # macro +RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK = 0x00000020 # macro +RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK = 0x00000040 # macro +RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK = 0x00000080 # macro +RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK = 0x00000100 # macro +RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK = 0x001FFE00 # macro +RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT = 0x0 # macro +RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT = 0x1 # macro +RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT = 0x2 # macro +RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT = 0x12 # macro +RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT = 0x13 # macro +RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT = 0x14 # macro +RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT = 0x15 # macro +RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK = 0x00000001 # macro +RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK = 0x00000002 # macro +RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK = 0x0003FFFC # macro +RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK = 0x00040000 # macro +RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK = 0x00080000 # macro +RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK = 0x00100000 # macro +RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK = 0x00200000 # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT = 0x0 # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT = 0xc # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT = 0xd # macro +RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT = 0xe # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT = 0xf # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT = 0x1b # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT = 0x1c # macro +RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT = 0x1d # macro +RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT = 0x1e # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK = 0x00000FFF # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK = 0x00001000 # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK = 0x00002000 # macro +RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK = 0x00004000 # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK = 0x07FF8000 # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK = 0x08000000 # macro +RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK = 0x10000000 # macro +RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK = 0x20000000 # macro +RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK = 0x40000000 # macro +RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT = 0x0 # macro +RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT = 0xc # macro +RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT = 0xd # macro +RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT = 0x19 # macro +RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT = 0x1a # macro +RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT = 0x1b # macro +RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT = 0x1c # macro +RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT = 0x1d # macro +RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT = 0x1e # macro +RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT = 0x1f # macro +RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK = 0x00000FFF # macro +RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK = 0x00001000 # macro +RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK = 0x01FFE000 # macro +RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK = 0x02000000 # macro +RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK = 0x04000000 # macro +RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK = 0x08000000 # macro +RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK = 0x10000000 # macro +RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK = 0x20000000 # macro +RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK = 0x40000000 # macro +RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK = 0x80000000 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT = 0x0 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT = 0x2 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT = 0x3 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT = 0x4 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT = 0x6 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT = 0x8 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT = 0x10 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT = 0x12 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT = 0x13 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT = 0x14 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT = 0x16 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT = 0x18 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK = 0x00000003 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK = 0x00000004 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK = 0x00000008 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK = 0x00000010 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK = 0x000000C0 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK = 0x0000FF00 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK = 0x00030000 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK = 0x00040000 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK = 0x00080000 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK = 0x00100000 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK = 0x00C00000 # macro +RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK = 0xFF000000 # macro +RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT = 0x0 # macro +RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT = 0x8 # macro +RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT = 0x10 # macro +RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT = 0x18 # macro +RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK = 0x000000FF # macro +RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK = 0x0000FF00 # macro +RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK = 0x00FF0000 # macro +RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK = 0xFF000000 # macro +RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT = 0x0 # macro +RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT = 0x5 # macro +RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT = 0xa # macro +RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT = 0xf # macro +RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT = 0x14 # macro +RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT = 0x19 # macro +RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK = 0x0000001F # macro +RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK = 0x000003E0 # macro +RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK = 0x00007C00 # macro +RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK = 0x000F8000 # macro +RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK = 0x01F00000 # macro +RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK = 0x3E000000 # macro +RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT = 0x0 # macro +RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT = 0x1 # macro +RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT = 0x2 # macro +RMI_UTCL1_STATUS__FAULT_DETECTED_MASK = 0x00000001 # macro +RMI_UTCL1_STATUS__RETRY_DETECTED_MASK = 0x00000002 # macro +RMI_UTCL1_STATUS__PRT_DETECTED_MASK = 0x00000004 # macro +RMI_XNACK_DEBUG__XNACK_PER_VMID__SHIFT = 0x0 # macro +RMI_XNACK_DEBUG__XNACK_PER_VMID_MASK = 0x0000FFFF # macro +RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT = 0x0 # macro +RMI_SPARE__SPARE_BIT_1__SHIFT = 0x1 # macro +RMI_SPARE__SPARE_BIT_2__SHIFT = 0x2 # macro +RMI_SPARE__SPARE_BIT_3__SHIFT = 0x3 # macro +RMI_SPARE__SPARE_BIT_4__SHIFT = 0x4 # macro +RMI_SPARE__SPARE_BIT_5__SHIFT = 0x5 # macro +RMI_SPARE__SPARE_BIT_6__SHIFT = 0x6 # macro +RMI_SPARE__SPARE_BIT_7__SHIFT = 0x7 # macro +RMI_SPARE__SPARE_BIT_8_0__SHIFT = 0x8 # macro +RMI_SPARE__SPARE_BIT_16_0__SHIFT = 0x10 # macro +RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK = 0x00000001 # macro +RMI_SPARE__SPARE_BIT_1_MASK = 0x00000002 # macro +RMI_SPARE__SPARE_BIT_2_MASK = 0x00000004 # macro +RMI_SPARE__SPARE_BIT_3_MASK = 0x00000008 # macro +RMI_SPARE__SPARE_BIT_4_MASK = 0x00000010 # macro +RMI_SPARE__SPARE_BIT_5_MASK = 0x00000020 # macro +RMI_SPARE__SPARE_BIT_6_MASK = 0x00000040 # macro +RMI_SPARE__SPARE_BIT_7_MASK = 0x00000080 # macro +RMI_SPARE__SPARE_BIT_8_0_MASK = 0x0000FF00 # macro +RMI_SPARE__SPARE_BIT_16_0_MASK = 0xFFFF0000 # macro +RMI_SPARE_1__SPARE_BIT_8__SHIFT = 0x0 # macro +RMI_SPARE_1__SPARE_BIT_9__SHIFT = 0x1 # macro +RMI_SPARE_1__SPARE_BIT_10__SHIFT = 0x2 # macro +RMI_SPARE_1__SPARE_BIT_11__SHIFT = 0x3 # macro +RMI_SPARE_1__SPARE_BIT_12__SHIFT = 0x4 # macro +RMI_SPARE_1__SPARE_BIT_13__SHIFT = 0x5 # macro +RMI_SPARE_1__SPARE_BIT_14__SHIFT = 0x6 # macro +RMI_SPARE_1__SPARE_BIT_15__SHIFT = 0x7 # macro +RMI_SPARE_1__SPARE_BIT_8_1__SHIFT = 0x8 # macro +RMI_SPARE_1__SPARE_BIT_16_1__SHIFT = 0x10 # macro +RMI_SPARE_1__SPARE_BIT_8_MASK = 0x00000001 # macro +RMI_SPARE_1__SPARE_BIT_9_MASK = 0x00000002 # macro +RMI_SPARE_1__SPARE_BIT_10_MASK = 0x00000004 # macro +RMI_SPARE_1__SPARE_BIT_11_MASK = 0x00000008 # macro +RMI_SPARE_1__SPARE_BIT_12_MASK = 0x00000010 # macro +RMI_SPARE_1__SPARE_BIT_13_MASK = 0x00000020 # macro +RMI_SPARE_1__SPARE_BIT_14_MASK = 0x00000040 # macro +RMI_SPARE_1__SPARE_BIT_15_MASK = 0x00000080 # macro +RMI_SPARE_1__SPARE_BIT_8_1_MASK = 0x0000FF00 # macro +RMI_SPARE_1__SPARE_BIT_16_1_MASK = 0xFFFF0000 # macro +RMI_SPARE_2__SPARE_BIT_16__SHIFT = 0x0 # macro +RMI_SPARE_2__SPARE_BIT_17__SHIFT = 0x1 # macro +RMI_SPARE_2__SPARE_BIT_18__SHIFT = 0x2 # macro +RMI_SPARE_2__SPARE_BIT_19__SHIFT = 0x3 # macro +RMI_SPARE_2__SPARE_BIT_20__SHIFT = 0x4 # macro +RMI_SPARE_2__SPARE_BIT_21__SHIFT = 0x5 # macro +RMI_SPARE_2__SPARE_BIT_22__SHIFT = 0x6 # macro +RMI_SPARE_2__SPARE_BIT_23__SHIFT = 0x7 # macro +RMI_SPARE_2__SPARE_BIT_4_0__SHIFT = 0x8 # macro +RMI_SPARE_2__SPARE_BIT_4_1__SHIFT = 0xc # macro +RMI_SPARE_2__SPARE_BIT_8_2__SHIFT = 0x10 # macro +RMI_SPARE_2__SPARE_BIT_8_3__SHIFT = 0x18 # macro +RMI_SPARE_2__SPARE_BIT_16_MASK = 0x00000001 # macro +RMI_SPARE_2__SPARE_BIT_17_MASK = 0x00000002 # macro +RMI_SPARE_2__SPARE_BIT_18_MASK = 0x00000004 # macro +RMI_SPARE_2__SPARE_BIT_19_MASK = 0x00000008 # macro +RMI_SPARE_2__SPARE_BIT_20_MASK = 0x00000010 # macro +RMI_SPARE_2__SPARE_BIT_21_MASK = 0x00000020 # macro +RMI_SPARE_2__SPARE_BIT_22_MASK = 0x00000040 # macro +RMI_SPARE_2__SPARE_BIT_23_MASK = 0x00000080 # macro +RMI_SPARE_2__SPARE_BIT_4_0_MASK = 0x00000F00 # macro +RMI_SPARE_2__SPARE_BIT_4_1_MASK = 0x0000F000 # macro +RMI_SPARE_2__SPARE_BIT_8_2_MASK = 0x00FF0000 # macro +RMI_SPARE_2__SPARE_BIT_8_3_MASK = 0xFF000000 # macro +ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT = 0x0 # macro +ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT = 0x3 # macro +ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT = 0x6 # macro +ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT = 0x7 # macro +ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT = 0x8 # macro +ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT = 0xb # macro +ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT = 0xe # macro +ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT = 0xf # macro +ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT = 0x10 # macro +ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT = 0x13 # macro +ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT = 0x14 # macro +ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT = 0x16 # macro +ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK = 0x00000003 # macro +ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK = 0x00000018 # macro +ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK = 0x00000040 # macro +ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK = 0x00000080 # macro +ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK = 0x00000300 # macro +ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK = 0x00001800 # macro +ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK = 0x00004000 # macro +ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK = 0x00008000 # macro +ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK = 0x00070000 # macro +ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK = 0x00080000 # macro +ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK = 0x00300000 # macro +ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK = 0x0FC00000 # macro +ATC_L2_CNTL2__BANK_SELECT__SHIFT = 0x0 # macro +ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT = 0x6 # macro +ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT = 0x9 # macro +ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT = 0xb # macro +ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT = 0xc # macro +ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT = 0xf # macro +ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT = 0x12 # macro +ATC_L2_CNTL2__BANK_SELECT_MASK = 0x0000003F # macro +ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK = 0x000001C0 # macro +ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK = 0x00000600 # macro +ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK = 0x00000800 # macro +ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK = 0x00007000 # macro +ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK = 0x00038000 # macro +ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK = 0x00FC0000 # macro +ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT = 0x0 # macro +ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT = 0x1 # macro +ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT = 0x2 # macro +ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT = 0x17 # macro +ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK = 0x00000001 # macro +ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK = 0x00000002 # macro +ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK = 0x007FFFFC # macro +ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK = 0x07800000 # macro +ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT = 0x0 # macro +ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK = 0xFFFFFFFF # macro +ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT = 0x0 # macro +ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK = 0xFFFFFFFF # macro +ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS__SHIFT = 0x0 # macro +ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS_MASK = 0xFFFFFFFF # macro +ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE__SHIFT = 0x6 # macro +ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE__SHIFT = 0xc # macro +ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT = 0x12 # macro +ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT = 0x15 # macro +ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT = 0x1b # macro +ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT = 0x1e # macro +ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE_MASK = 0x0000003F # macro +ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE_MASK = 0x00000FC0 # macro +ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE_MASK = 0x0003F000 # macro +ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK = 0x001C0000 # macro +ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK = 0x07E00000 # macro +ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK = 0x38000000 # macro +ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK = 0x40000000 # macro +ATC_L2_STATUS__BUSY__SHIFT = 0x0 # macro +ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS__SHIFT = 0x1 # macro +ATC_L2_STATUS__BUSY_MASK = 0x00000001 # macro +ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS_MASK = 0x00000002 # macro +ATC_L2_STATUS2__UCE_MEM_ADDR__SHIFT = 0x0 # macro +ATC_L2_STATUS2__UCE_MEM_INST__SHIFT = 0xc # macro +ATC_L2_STATUS2__UCE_SRT_CACHE__SHIFT = 0x14 # macro +ATC_L2_STATUS2__UCE__SHIFT = 0x15 # macro +ATC_L2_STATUS2__UCE_MEM_ADDR_MASK = 0x00000FFF # macro +ATC_L2_STATUS2__UCE_MEM_INST_MASK = 0x000FF000 # macro +ATC_L2_STATUS2__UCE_SRT_CACHE_MASK = 0x00100000 # macro +ATC_L2_STATUS2__UCE_MASK = 0x00200000 # macro +ATC_L2_MISC_CG__OFFDLY__SHIFT = 0x6 # macro +ATC_L2_MISC_CG__ENABLE__SHIFT = 0x12 # macro +ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT = 0x13 # macro +ATC_L2_MISC_CG__OFFDLY_MASK = 0x00000FC0 # macro +ATC_L2_MISC_CG__ENABLE_MASK = 0x00040000 # macro +ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK = 0x00080000 # macro +ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT = 0x0 # macro +ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT = 0x6 # macro +ATC_L2_MEM_POWER_LS__LS_SETUP_MASK = 0x0000003F # macro +ATC_L2_MEM_POWER_LS__LS_HOLD_MASK = 0x00000FC0 # macro +ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT = 0xf # macro +ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT = 0x10 # macro +ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT = 0x18 # macro +ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK = 0x00008000 # macro +ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK = 0x00FF0000 # macro +ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK = 0xFF000000 # macro +ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT = 0x0 # macro +ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK = 0x000000FF # macro +ATC_L2_CACHE_32K_DSM_INDEX__INDEX__SHIFT = 0x0 # macro +ATC_L2_CACHE_32K_DSM_INDEX__INDEX_MASK = 0x000000FF # macro +ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT = 0x0 # macro +ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK = 0x000000FF # macro +ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT = 0x0 # macro +ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT = 0x6 # macro +ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT = 0x8 # macro +ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT = 0xb # macro +ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT = 0xc # macro +ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT = 0xd # macro +ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT = 0xf # macro +ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT = 0x11 # macro +ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK = 0x0000003F # macro +ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK = 0x000000C0 # macro +ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK = 0x00000100 # macro +ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK = 0x00001000 # macro +ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK = 0x00006000 # macro +ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK = 0x00018000 # macro +ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK = 0x00020000 # macro +ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY__SHIFT = 0x0 # macro +ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT = 0x6 # macro +ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT = 0x8 # macro +ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT = 0xb # macro +ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS__SHIFT = 0xc # macro +ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT__SHIFT = 0xd # macro +ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT__SHIFT = 0xf # macro +ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE__SHIFT = 0x11 # macro +ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY_MASK = 0x0000003F # macro +ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK = 0x000000C0 # macro +ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK = 0x00000100 # macro +ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS_MASK = 0x00001000 # macro +ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT_MASK = 0x00006000 # macro +ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT_MASK = 0x00018000 # macro +ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE_MASK = 0x00020000 # macro +ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT = 0x0 # macro +ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT = 0x6 # macro +ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT = 0x8 # macro +ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT = 0xb # macro +ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT = 0xc # macro +ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT = 0xd # macro +ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT = 0xf # macro +ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT = 0x11 # macro +ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK = 0x0000003F # macro +ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK = 0x000000C0 # macro +ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK = 0x00000100 # macro +ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK = 0x00001000 # macro +ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK = 0x00006000 # macro +ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK = 0x00018000 # macro +ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK = 0x00020000 # macro +ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT = 0x0 # macro +ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT = 0xa # macro +ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK = 0x000003FF # macro +ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK = 0x000FFC00 # macro +ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT = 0x0 # macro +ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK = 0xFFFFFFFF # macro +ATC_L2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +ATC_L2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +ATC_L2_UE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +ATC_L2_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +ATC_L2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +ATC_L2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +ATC_L2_UE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +ATC_L2_UE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +ATC_L2_UE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +ATC_L2_UE_ERR_STATUS_HI__PARITY__SHIFT = 0x1 # macro +ATC_L2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +ATC_L2_UE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +ATC_L2_UE_ERR_STATUS_HI__UE_CNT__SHIFT = 0x17 # macro +ATC_L2_UE_ERR_STATUS_HI__FED_CNT__SHIFT = 0x1a # macro +ATC_L2_UE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1d # macro +ATC_L2_UE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +ATC_L2_UE_ERR_STATUS_HI__PARITY_MASK = 0x00000002 # macro +ATC_L2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +ATC_L2_UE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +ATC_L2_UE_ERR_STATUS_HI__UE_CNT_MASK = 0x03800000 # macro +ATC_L2_UE_ERR_STATUS_HI__FED_CNT_MASK = 0x1C000000 # macro +ATC_L2_UE_ERR_STATUS_HI__RESERVED_MASK = 0x60000000 # macro +ATC_L2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +ATC_L2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +ATC_L2_CE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +ATC_L2_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +ATC_L2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +ATC_L2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +ATC_L2_CE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +ATC_L2_CE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +ATC_L2_CE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +ATC_L2_CE_ERR_STATUS_HI__OTHER__SHIFT = 0x1 # macro +ATC_L2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +ATC_L2_CE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +ATC_L2_CE_ERR_STATUS_HI__CE_CNT__SHIFT = 0x17 # macro +ATC_L2_CE_ERR_STATUS_HI__POISON__SHIFT = 0x1a # macro +ATC_L2_CE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1b # macro +ATC_L2_CE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +ATC_L2_CE_ERR_STATUS_HI__OTHER_MASK = 0x00000002 # macro +ATC_L2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +ATC_L2_CE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +ATC_L2_CE_ERR_STATUS_HI__CE_CNT_MASK = 0x03800000 # macro +ATC_L2_CE_ERR_STATUS_HI__POISON_MASK = 0x04000000 # macro +ATC_L2_CE_ERR_STATUS_HI__RESERVED_MASK = 0xF8000000 # macro +VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT = 0x0 # macro +VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT = 0x1 # macro +VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT = 0x2 # macro +VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT = 0x4 # macro +VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT = 0x8 # macro +VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT = 0x9 # macro +VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT = 0xa # macro +VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT = 0xb # macro +VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT = 0xc # macro +VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT = 0xf # macro +VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT = 0x12 # macro +VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT = 0x13 # macro +VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT = 0x15 # macro +VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT = 0x1a # macro +VM_L2_CNTL__ENABLE_L2_CACHE_MASK = 0x00000001 # macro +VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK = 0x00000002 # macro +VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK = 0x0000000C # macro +VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK = 0x00000030 # macro +VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK = 0x00000100 # macro +VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK = 0x00000200 # macro +VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK = 0x00000400 # macro +VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK = 0x00000800 # macro +VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK = 0x00007000 # macro +VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK = 0x00038000 # macro +VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK = 0x00040000 # macro +VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK = 0x00180000 # macro +VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK = 0x03E00000 # macro +VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK = 0x0C000000 # macro +VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT = 0x0 # macro +VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT = 0x1 # macro +VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT = 0x15 # macro +VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT = 0x16 # macro +VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT = 0x17 # macro +VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT = 0x1a # macro +VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT = 0x1c # macro +VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK = 0x00000001 # macro +VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK = 0x00000002 # macro +VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK = 0x00200000 # macro +VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK = 0x00400000 # macro +VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK = 0x03800000 # macro +VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK = 0x0C000000 # macro +VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK = 0x70000000 # macro +VM_L2_CNTL3__BANK_SELECT__SHIFT = 0x0 # macro +VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT = 0x6 # macro +VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT = 0x8 # macro +VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0xf # macro +VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT = 0x14 # macro +VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT = 0x15 # macro +VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT = 0x18 # macro +VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT = 0x1c # macro +VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT = 0x1d # macro +VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT = 0x1e # macro +VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT = 0x1f # macro +VM_L2_CNTL3__BANK_SELECT_MASK = 0x0000003F # macro +VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK = 0x000000C0 # macro +VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK = 0x00001F00 # macro +VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000F8000 # macro +VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK = 0x00100000 # macro +VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK = 0x00E00000 # macro +VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK = 0x0F000000 # macro +VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK = 0x10000000 # macro +VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK = 0x20000000 # macro +VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK = 0x40000000 # macro +VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK = 0x80000000 # macro +VM_L2_STATUS__L2_BUSY__SHIFT = 0x0 # macro +VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT = 0x1 # macro +VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT = 0x11 # macro +VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT = 0x12 # macro +VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT = 0x13 # macro +VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT = 0x14 # macro +VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT = 0x15 # macro +VM_L2_STATUS__L2_BUSY_MASK = 0x00000001 # macro +VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK = 0x0001FFFE # macro +VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK = 0x00020000 # macro +VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK = 0x00040000 # macro +VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK = 0x00080000 # macro +VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK = 0x00100000 # macro +VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK = 0x00200000 # macro +VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT = 0x0 # macro +VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT = 0x1 # macro +VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT = 0x2 # macro +VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK = 0x00000001 # macro +VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK = 0x00000002 # macro +VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK = 0x000000FC # macro +VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT = 0x0 # macro +VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK = 0xFFFFFFFF # macro +VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT = 0x0 # macro +VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK = 0x0000000F # macro +VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x0 # macro +VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT = 0x1 # macro +VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x2 # macro +VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x3 # macro +VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x4 # macro +VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x5 # macro +VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x6 # macro +VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x7 # macro +VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x8 # macro +VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x9 # macro +VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xb # macro +VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT = 0xd # macro +VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT = 0x1d # macro +VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT = 0x1e # macro +VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT = 0x1f # macro +VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00000001 # macro +VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK = 0x00000002 # macro +VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000004 # macro +VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000008 # macro +VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000010 # macro +VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000020 # macro +VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000040 # macro +VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000080 # macro +VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000100 # macro +VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000200 # macro +VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000800 # macro +VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK = 0x1FFFE000 # macro +VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK = 0x20000000 # macro +VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK = 0x40000000 # macro +VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK = 0x80000000 # macro +VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT = 0x0 # macro +VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT = 0x10 # macro +VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT = 0x11 # macro +VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT = 0x12 # macro +VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT = 0x13 # macro +VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK = 0x0000FFFF # macro +VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK = 0x00010000 # macro +VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK = 0x00020000 # macro +VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK = 0x00040000 # macro +VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK = 0x00080000 # macro +VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT = 0x0 # macro +VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK = 0xFFFFFFFF # macro +VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT = 0x0 # macro +VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK = 0xFFFFFFFF # macro +VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT = 0x0 # macro +VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT = 0x1 # macro +VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT = 0x4 # macro +VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT = 0x8 # macro +VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT = 0x9 # macro +VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT = 0x12 # macro +VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT = 0x13 # macro +VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT = 0x14 # macro +VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT = 0x18 # macro +VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT = 0x19 # macro +VM_L2_PROTECTION_FAULT_STATUS__UCE__SHIFT = 0x1d # macro +VM_L2_PROTECTION_FAULT_STATUS__FED__SHIFT = 0x1e # macro +VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK = 0x00000001 # macro +VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK = 0x0000000E # macro +VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK = 0x000000F0 # macro +VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK = 0x00000100 # macro +VM_L2_PROTECTION_FAULT_STATUS__CID_MASK = 0x0003FE00 # macro +VM_L2_PROTECTION_FAULT_STATUS__RW_MASK = 0x00040000 # macro +VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK = 0x00080000 # macro +VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK = 0x00F00000 # macro +VM_L2_PROTECTION_FAULT_STATUS__VF_MASK = 0x01000000 # macro +VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK = 0x1E000000 # macro +VM_L2_PROTECTION_FAULT_STATUS__UCE_MASK = 0x20000000 # macro +VM_L2_PROTECTION_FAULT_STATUS__FED_MASK = 0x40000000 # macro +VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT = 0x0 # macro +VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK = 0xFFFFFFFF # macro +VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT = 0x0 # macro +VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK = 0x0000000F # macro +VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT = 0x0 # macro +VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK = 0xFFFFFFFF # macro +VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT = 0x0 # macro +VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK = 0x0000000F # macro +VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT = 0x0 # macro +VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK = 0xFFFFFFFF # macro +VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT = 0x0 # macro +VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK = 0x0000000F # macro +VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT = 0x0 # macro +VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT = 0x6 # macro +VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT = 0x7 # macro +VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT = 0x8 # macro +VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT = 0x12 # macro +VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT = 0x1c # macro +VM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT = 0x1d # macro +VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT = 0x1e # macro +VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK = 0x0000003F # macro +VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK = 0x00000040 # macro +VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK = 0x00000080 # macro +VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK = 0x0003FF00 # macro +VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK = 0x0FFC0000 # macro +VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK = 0x10000000 # macro +VM_L2_CNTL4__GC_CH_FGCG_OFF_MASK = 0x20000000 # macro +VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK = 0x40000000 # macro +VM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT = 0x0 # macro +VM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT = 0x1 # macro +VM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK = 0x00000001 # macro +VM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK = 0x00000002 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT = 0x0 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT = 0x1 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT = 0x2 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT = 0x3 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT = 0x4 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT = 0x5 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT = 0x6 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT = 0x7 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT = 0x8 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT = 0x9 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT = 0xa # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT = 0xb # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT = 0xc # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT = 0xd # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT = 0xe # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT = 0xf # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT = 0x10 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT = 0x11 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT = 0x12 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT = 0x13 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT = 0x14 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT = 0x15 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT = 0x16 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT = 0x17 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT = 0x18 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT = 0x19 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT = 0x1a # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT = 0x1b # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT = 0x1c # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT = 0x1d # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT = 0x1e # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT = 0x1f # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK = 0x00000001 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK = 0x00000002 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK = 0x00000004 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK = 0x00000008 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK = 0x00000010 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK = 0x00000020 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK = 0x00000040 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK = 0x00000080 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK = 0x00000100 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK = 0x00000200 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK = 0x00000400 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK = 0x00000800 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK = 0x00001000 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK = 0x00002000 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK = 0x00004000 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK = 0x00008000 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK = 0x00010000 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK = 0x00020000 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK = 0x00040000 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK = 0x00080000 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK = 0x00100000 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK = 0x00200000 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK = 0x00400000 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK = 0x00800000 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK = 0x01000000 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK = 0x02000000 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK = 0x04000000 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK = 0x08000000 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK = 0x10000000 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK = 0x20000000 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK = 0x40000000 # macro +VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK = 0x80000000 # macro +VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT = 0x0 # macro +VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT = 0xa # macro +VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT = 0x14 # macro +VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT = 0x18 # macro +VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT = 0x19 # macro +VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK = 0x000001FF # macro +VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK = 0x0007FC00 # macro +VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK = 0x00100000 # macro +VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK = 0x01000000 # macro +VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK = 0x02000000 # macro +VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT = 0x0 # macro +VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT = 0xa # macro +VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT = 0x14 # macro +VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT = 0x18 # macro +VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT = 0x19 # macro +VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK = 0x000001FF # macro +VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK = 0x0007FC00 # macro +VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK = 0x00100000 # macro +VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK = 0x01000000 # macro +VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK = 0x02000000 # macro +VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT = 0x0 # macro +VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT = 0x1 # macro +VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT = 0x2 # macro +VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT = 0x3 # macro +VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT = 0x4 # macro +VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT = 0x5 # macro +VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT = 0x6 # macro +VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT = 0x9 # macro +VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT = 0xc # macro +VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK = 0x00000001 # macro +VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK = 0x00000002 # macro +VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK = 0x00000004 # macro +VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK = 0x00000008 # macro +VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK = 0x00000010 # macro +VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK = 0x00000020 # macro +VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK = 0x000001C0 # macro +VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK = 0x00000E00 # macro +VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK = 0x0000F000 # macro +VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT = 0xf # macro +VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT = 0x10 # macro +VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT = 0x18 # macro +VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK = 0x00008000 # macro +VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK = 0x00FF0000 # macro +VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK = 0xFF000000 # macro +VM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT = 0x0 # macro +VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT = 0x4 # macro +VM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK = 0x0000000F # macro +VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK = 0x00000010 # macro +VML2_MEM_ECC_INDEX__INDEX__SHIFT = 0x0 # macro +VML2_MEM_ECC_INDEX__INDEX_MASK = 0x000000FF # macro +VML2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT = 0x0 # macro +VML2_WALKER_MEM_ECC_INDEX__INDEX_MASK = 0x000000FF # macro +UTCL2_MEM_ECC_INDEX__INDEX__SHIFT = 0x0 # macro +UTCL2_MEM_ECC_INDEX__INDEX_MASK = 0x000000FF # macro +VML2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT = 0x0 # macro +VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT = 0x6 # macro +VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT = 0x8 # macro +VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT = 0xb # macro +VML2_MEM_ECC_CNTL__SEC_COUNT__SHIFT = 0xc # macro +VML2_MEM_ECC_CNTL__DED_COUNT__SHIFT = 0xe # macro +VML2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT = 0x10 # macro +VML2_MEM_ECC_CNTL__TEST_FUE__SHIFT = 0x11 # macro +VML2_MEM_ECC_CNTL__INJECT_DELAY_MASK = 0x0000003F # macro +VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK = 0x000000C0 # macro +VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK = 0x00000100 # macro +VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +VML2_MEM_ECC_CNTL__SEC_COUNT_MASK = 0x00003000 # macro +VML2_MEM_ECC_CNTL__DED_COUNT_MASK = 0x0000C000 # macro +VML2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK = 0x00010000 # macro +VML2_MEM_ECC_CNTL__TEST_FUE_MASK = 0x00020000 # macro +VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY__SHIFT = 0x0 # macro +VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT = 0x6 # macro +VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT = 0x8 # macro +VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT = 0xb # macro +VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT__SHIFT = 0xc # macro +VML2_WALKER_MEM_ECC_CNTL__DED_COUNT__SHIFT = 0xe # macro +VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT = 0x10 # macro +VML2_WALKER_MEM_ECC_CNTL__TEST_FUE__SHIFT = 0x11 # macro +VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY_MASK = 0x0000003F # macro +VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK = 0x000000C0 # macro +VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK = 0x00000100 # macro +VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT_MASK = 0x00003000 # macro +VML2_WALKER_MEM_ECC_CNTL__DED_COUNT_MASK = 0x0000C000 # macro +VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS_MASK = 0x00010000 # macro +VML2_WALKER_MEM_ECC_CNTL__TEST_FUE_MASK = 0x00020000 # macro +UTCL2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT = 0x0 # macro +UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT = 0x6 # macro +UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT = 0x8 # macro +UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT = 0xb # macro +UTCL2_MEM_ECC_CNTL__SEC_COUNT__SHIFT = 0xc # macro +UTCL2_MEM_ECC_CNTL__DED_COUNT__SHIFT = 0xe # macro +UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT = 0x10 # macro +UTCL2_MEM_ECC_CNTL__TEST_FUE__SHIFT = 0x11 # macro +UTCL2_MEM_ECC_CNTL__INJECT_DELAY_MASK = 0x0000003F # macro +UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK = 0x000000C0 # macro +UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK = 0x00000100 # macro +UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +UTCL2_MEM_ECC_CNTL__SEC_COUNT_MASK = 0x00003000 # macro +UTCL2_MEM_ECC_CNTL__DED_COUNT_MASK = 0x0000C000 # macro +UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK = 0x00010000 # macro +UTCL2_MEM_ECC_CNTL__TEST_FUE_MASK = 0x00020000 # macro +VML2_MEM_ECC_STATUS__UCE__SHIFT = 0x0 # macro +VML2_MEM_ECC_STATUS__FED__SHIFT = 0x1 # macro +VML2_MEM_ECC_STATUS__UCE_MASK = 0x00000001 # macro +VML2_MEM_ECC_STATUS__FED_MASK = 0x00000002 # macro +VML2_WALKER_MEM_ECC_STATUS__UCE__SHIFT = 0x0 # macro +VML2_WALKER_MEM_ECC_STATUS__FED__SHIFT = 0x1 # macro +VML2_WALKER_MEM_ECC_STATUS__UCE_MASK = 0x00000001 # macro +VML2_WALKER_MEM_ECC_STATUS__FED_MASK = 0x00000002 # macro +UTCL2_MEM_ECC_STATUS__UCE__SHIFT = 0x0 # macro +UTCL2_MEM_ECC_STATUS__FED__SHIFT = 0x1 # macro +UTCL2_MEM_ECC_STATUS__UCE_MASK = 0x00000001 # macro +UTCL2_MEM_ECC_STATUS__FED_MASK = 0x00000002 # macro +UTCL2_EDC_MODE__FORCE_SEC_ON_DED__SHIFT = 0xf # macro +UTCL2_EDC_MODE__COUNT_FED_OUT__SHIFT = 0x10 # macro +UTCL2_EDC_MODE__GATE_FUE__SHIFT = 0x11 # macro +UTCL2_EDC_MODE__DED_MODE__SHIFT = 0x14 # macro +UTCL2_EDC_MODE__PROP_FED__SHIFT = 0x1d # macro +UTCL2_EDC_MODE__BYPASS__SHIFT = 0x1f # macro +UTCL2_EDC_MODE__FORCE_SEC_ON_DED_MASK = 0x00008000 # macro +UTCL2_EDC_MODE__COUNT_FED_OUT_MASK = 0x00010000 # macro +UTCL2_EDC_MODE__GATE_FUE_MASK = 0x00020000 # macro +UTCL2_EDC_MODE__DED_MODE_MASK = 0x00300000 # macro +UTCL2_EDC_MODE__PROP_FED_MASK = 0x20000000 # macro +UTCL2_EDC_MODE__BYPASS_MASK = 0x80000000 # macro +UTCL2_EDC_CONFIG__WRITE_DIS__SHIFT = 0x0 # macro +UTCL2_EDC_CONFIG__DIS_EDC__SHIFT = 0x1 # macro +UTCL2_EDC_CONFIG__WRITE_DIS_MASK = 0x00000001 # macro +UTCL2_EDC_CONFIG__DIS_EDC_MASK = 0x00000002 # macro +VML2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +VML2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +VML2_UE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +VML2_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +VML2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +VML2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +VML2_UE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +VML2_UE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +VML2_WALKER_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +VML2_WALKER_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +VML2_WALKER_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +VML2_WALKER_UE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +UTCL2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +UTCL2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +UTCL2_UE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +UTCL2_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +UTCL2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +UTCL2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +UTCL2_UE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +UTCL2_UE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +VML2_UE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +VML2_UE_ERR_STATUS_HI__PARITY__SHIFT = 0x1 # macro +VML2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +VML2_UE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +VML2_UE_ERR_STATUS_HI__UE_CNT__SHIFT = 0x17 # macro +VML2_UE_ERR_STATUS_HI__FED_CNT__SHIFT = 0x1a # macro +VML2_UE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1d # macro +VML2_UE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +VML2_UE_ERR_STATUS_HI__PARITY_MASK = 0x00000002 # macro +VML2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +VML2_UE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +VML2_UE_ERR_STATUS_HI__UE_CNT_MASK = 0x03800000 # macro +VML2_UE_ERR_STATUS_HI__FED_CNT_MASK = 0x1C000000 # macro +VML2_UE_ERR_STATUS_HI__RESERVED_MASK = 0xE0000000 # macro +VML2_WALKER_UE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +VML2_WALKER_UE_ERR_STATUS_HI__PARITY__SHIFT = 0x1 # macro +VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +VML2_WALKER_UE_ERR_STATUS_HI__UE_CNT__SHIFT = 0x17 # macro +VML2_WALKER_UE_ERR_STATUS_HI__FED_CNT__SHIFT = 0x1a # macro +VML2_WALKER_UE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1d # macro +VML2_WALKER_UE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +VML2_WALKER_UE_ERR_STATUS_HI__PARITY_MASK = 0x00000002 # macro +VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +VML2_WALKER_UE_ERR_STATUS_HI__UE_CNT_MASK = 0x03800000 # macro +VML2_WALKER_UE_ERR_STATUS_HI__FED_CNT_MASK = 0x1C000000 # macro +VML2_WALKER_UE_ERR_STATUS_HI__RESERVED_MASK = 0xE0000000 # macro +UTCL2_UE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +UTCL2_UE_ERR_STATUS_HI__PARITY__SHIFT = 0x1 # macro +UTCL2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +UTCL2_UE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +UTCL2_UE_ERR_STATUS_HI__UE_CNT__SHIFT = 0x17 # macro +UTCL2_UE_ERR_STATUS_HI__FED_CNT__SHIFT = 0x1a # macro +UTCL2_UE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1d # macro +UTCL2_UE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +UTCL2_UE_ERR_STATUS_HI__PARITY_MASK = 0x00000002 # macro +UTCL2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +UTCL2_UE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +UTCL2_UE_ERR_STATUS_HI__UE_CNT_MASK = 0x03800000 # macro +UTCL2_UE_ERR_STATUS_HI__FED_CNT_MASK = 0x1C000000 # macro +UTCL2_UE_ERR_STATUS_HI__RESERVED_MASK = 0xE0000000 # macro +VML2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +VML2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +VML2_CE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +VML2_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +VML2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +VML2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +VML2_CE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +VML2_CE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +VML2_WALKER_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +VML2_WALKER_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +VML2_WALKER_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +VML2_WALKER_CE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +UTCL2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +UTCL2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +UTCL2_CE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +UTCL2_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +UTCL2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +UTCL2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +UTCL2_CE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +UTCL2_CE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +VML2_CE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +VML2_CE_ERR_STATUS_HI__OTHER__SHIFT = 0x1 # macro +VML2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +VML2_CE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +VML2_CE_ERR_STATUS_HI__CE_CNT__SHIFT = 0x17 # macro +VML2_CE_ERR_STATUS_HI__POISON__SHIFT = 0x1a # macro +VML2_CE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1b # macro +VML2_CE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +VML2_CE_ERR_STATUS_HI__OTHER_MASK = 0x00000002 # macro +VML2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +VML2_CE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +VML2_CE_ERR_STATUS_HI__CE_CNT_MASK = 0x03800000 # macro +VML2_CE_ERR_STATUS_HI__POISON_MASK = 0x04000000 # macro +VML2_CE_ERR_STATUS_HI__RESERVED_MASK = 0xF8000000 # macro +VML2_WALKER_CE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +VML2_WALKER_CE_ERR_STATUS_HI__OTHER__SHIFT = 0x1 # macro +VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +VML2_WALKER_CE_ERR_STATUS_HI__CE_CNT__SHIFT = 0x17 # macro +VML2_WALKER_CE_ERR_STATUS_HI__POISON__SHIFT = 0x1a # macro +VML2_WALKER_CE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1b # macro +VML2_WALKER_CE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +VML2_WALKER_CE_ERR_STATUS_HI__OTHER_MASK = 0x00000002 # macro +VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +VML2_WALKER_CE_ERR_STATUS_HI__CE_CNT_MASK = 0x03800000 # macro +VML2_WALKER_CE_ERR_STATUS_HI__POISON_MASK = 0x04000000 # macro +VML2_WALKER_CE_ERR_STATUS_HI__RESERVED_MASK = 0xF8000000 # macro +UTCL2_CE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +UTCL2_CE_ERR_STATUS_HI__OTHER__SHIFT = 0x1 # macro +UTCL2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +UTCL2_CE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +UTCL2_CE_ERR_STATUS_HI__CE_CNT__SHIFT = 0x17 # macro +UTCL2_CE_ERR_STATUS_HI__POISON__SHIFT = 0x1a # macro +UTCL2_CE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1b # macro +UTCL2_CE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +UTCL2_CE_ERR_STATUS_HI__OTHER_MASK = 0x00000002 # macro +UTCL2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +UTCL2_CE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +UTCL2_CE_ERR_STATUS_HI__CE_CNT_MASK = 0x03800000 # macro +UTCL2_CE_ERR_STATUS_HI__POISON_MASK = 0x04000000 # macro +UTCL2_CE_ERR_STATUS_HI__RESERVED_MASK = 0xF8000000 # macro +VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT = 0x0 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT = 0x1 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT = 0x2 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT = 0x3 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT = 0x4 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT = 0x5 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT = 0x6 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT = 0x7 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT = 0x8 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT = 0x9 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT = 0xa # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT = 0xb # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT = 0xc # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT = 0xd # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT = 0xe # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT = 0xf # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK = 0x00000001 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK = 0x00000002 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK = 0x00000004 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK = 0x00000008 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK = 0x00000010 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK = 0x00000020 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK = 0x00000040 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK = 0x00000080 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK = 0x00000100 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK = 0x00000200 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK = 0x00000400 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK = 0x00000800 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK = 0x00001000 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK = 0x00002000 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK = 0x00004000 # macro +VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK = 0x00008000 # macro +VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT = 0x12 # macro +VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x13 # macro +VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x14 # macro +VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x15 # macro +VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT = 0x16 # macro +VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x17 # macro +VM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT = 0x18 # macro +VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK = 0x00030000 # macro +VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK = 0x00040000 # macro +VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK = 0x00080000 # macro +VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK = 0x00100000 # macro +VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK = 0x00200000 # macro +VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK = 0x00400000 # macro +VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00800000 # macro +VM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK = 0x01000000 # macro +VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT = 0x12 # macro +VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x13 # macro +VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x14 # macro +VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x15 # macro +VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT = 0x16 # macro +VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x17 # macro +VM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT = 0x18 # macro +VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK = 0x00030000 # macro +VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK = 0x00040000 # macro +VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK = 0x00080000 # macro +VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK = 0x00100000 # macro +VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK = 0x00200000 # macro +VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK = 0x00400000 # macro +VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00800000 # macro +VM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK = 0x01000000 # macro +VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT = 0x12 # macro +VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x13 # macro +VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x14 # macro +VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x15 # macro +VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT = 0x16 # macro +VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x17 # macro +VM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT = 0x18 # macro +VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK = 0x00030000 # macro +VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK = 0x00040000 # macro +VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK = 0x00080000 # macro +VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK = 0x00100000 # macro +VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK = 0x00200000 # macro +VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK = 0x00400000 # macro +VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00800000 # macro +VM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK = 0x01000000 # macro +VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT = 0x12 # macro +VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x13 # macro +VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x14 # macro +VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x15 # macro +VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT = 0x16 # macro +VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x17 # macro +VM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT = 0x18 # macro +VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK = 0x00030000 # macro +VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK = 0x00040000 # macro +VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK = 0x00080000 # macro +VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK = 0x00100000 # macro +VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK = 0x00200000 # macro +VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK = 0x00400000 # macro +VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00800000 # macro +VM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK = 0x01000000 # macro +VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT = 0x12 # macro +VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x13 # macro +VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x14 # macro +VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x15 # macro +VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT = 0x16 # macro +VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x17 # macro +VM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT = 0x18 # macro +VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK = 0x00030000 # macro +VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK = 0x00040000 # macro +VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK = 0x00080000 # macro +VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK = 0x00100000 # macro +VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK = 0x00200000 # macro +VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK = 0x00400000 # macro +VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00800000 # macro +VM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK = 0x01000000 # macro +VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT = 0x12 # macro +VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x13 # macro +VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x14 # macro +VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x15 # macro +VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT = 0x16 # macro +VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x17 # macro +VM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT = 0x18 # macro +VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK = 0x00030000 # macro +VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK = 0x00040000 # macro +VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK = 0x00080000 # macro +VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK = 0x00100000 # macro +VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK = 0x00200000 # macro +VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK = 0x00400000 # macro +VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00800000 # macro +VM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK = 0x01000000 # macro +VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT = 0x12 # macro +VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x13 # macro +VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x14 # macro +VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x15 # macro +VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT = 0x16 # macro +VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x17 # macro +VM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT = 0x18 # macro +VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK = 0x00030000 # macro +VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK = 0x00040000 # macro +VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK = 0x00080000 # macro +VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK = 0x00100000 # macro +VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK = 0x00200000 # macro +VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK = 0x00400000 # macro +VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00800000 # macro +VM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK = 0x01000000 # macro +VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT = 0x12 # macro +VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x13 # macro +VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x14 # macro +VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x15 # macro +VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT = 0x16 # macro +VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x17 # macro +VM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT = 0x18 # macro +VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK = 0x00030000 # macro +VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK = 0x00040000 # macro +VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK = 0x00080000 # macro +VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK = 0x00100000 # macro +VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK = 0x00200000 # macro +VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK = 0x00400000 # macro +VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00800000 # macro +VM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK = 0x01000000 # macro +VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT = 0x12 # macro +VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x13 # macro +VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x14 # macro +VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x15 # macro +VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT = 0x16 # macro +VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x17 # macro +VM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT = 0x18 # macro +VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK = 0x00030000 # macro +VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK = 0x00040000 # macro +VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK = 0x00080000 # macro +VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK = 0x00100000 # macro +VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK = 0x00200000 # macro +VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK = 0x00400000 # macro +VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00800000 # macro +VM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK = 0x01000000 # macro +VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT = 0x12 # macro +VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x13 # macro +VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x14 # macro +VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x15 # macro +VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT = 0x16 # macro +VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x17 # macro +VM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT = 0x18 # macro +VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK = 0x00030000 # macro +VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK = 0x00040000 # macro +VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK = 0x00080000 # macro +VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK = 0x00100000 # macro +VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK = 0x00200000 # macro +VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK = 0x00400000 # macro +VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00800000 # macro +VM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK = 0x01000000 # macro +VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT = 0x12 # macro +VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x13 # macro +VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x14 # macro +VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x15 # macro +VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT = 0x16 # macro +VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x17 # macro +VM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT = 0x18 # macro +VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK = 0x00030000 # macro +VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK = 0x00040000 # macro +VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK = 0x00080000 # macro +VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK = 0x00100000 # macro +VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK = 0x00200000 # macro +VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK = 0x00400000 # macro +VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00800000 # macro +VM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK = 0x01000000 # macro +VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT = 0x12 # macro +VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x13 # macro +VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x14 # macro +VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x15 # macro +VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT = 0x16 # macro +VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x17 # macro +VM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT = 0x18 # macro +VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK = 0x00030000 # macro +VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK = 0x00040000 # macro +VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK = 0x00080000 # macro +VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK = 0x00100000 # macro +VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK = 0x00200000 # macro +VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK = 0x00400000 # macro +VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00800000 # macro +VM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK = 0x01000000 # macro +VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT = 0x12 # macro +VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x13 # macro +VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x14 # macro +VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x15 # macro +VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT = 0x16 # macro +VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x17 # macro +VM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT = 0x18 # macro +VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK = 0x00030000 # macro +VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK = 0x00040000 # macro +VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK = 0x00080000 # macro +VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK = 0x00100000 # macro +VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK = 0x00200000 # macro +VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK = 0x00400000 # macro +VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00800000 # macro +VM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK = 0x01000000 # macro +VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT = 0x12 # macro +VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x13 # macro +VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x14 # macro +VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x15 # macro +VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT = 0x16 # macro +VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x17 # macro +VM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT = 0x18 # macro +VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK = 0x00030000 # macro +VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK = 0x00040000 # macro +VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK = 0x00080000 # macro +VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK = 0x00100000 # macro +VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK = 0x00200000 # macro +VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK = 0x00400000 # macro +VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00800000 # macro +VM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK = 0x01000000 # macro +VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT = 0x12 # macro +VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x13 # macro +VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x14 # macro +VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x15 # macro +VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT = 0x16 # macro +VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x17 # macro +VM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT = 0x18 # macro +VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK = 0x00030000 # macro +VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK = 0x00040000 # macro +VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK = 0x00080000 # macro +VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK = 0x00100000 # macro +VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK = 0x00200000 # macro +VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK = 0x00400000 # macro +VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00800000 # macro +VM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK = 0x01000000 # macro +VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT = 0x12 # macro +VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x13 # macro +VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x14 # macro +VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x15 # macro +VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT = 0x16 # macro +VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x17 # macro +VM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT = 0x18 # macro +VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK = 0x00030000 # macro +VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK = 0x00040000 # macro +VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK = 0x00080000 # macro +VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK = 0x00100000 # macro +VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK = 0x00200000 # macro +VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK = 0x00400000 # macro +VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00800000 # macro +VM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK = 0x01000000 # macro +VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT = 0x12 # macro +VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x13 # macro +VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x14 # macro +VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x15 # macro +VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT = 0x16 # macro +VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x17 # macro +VM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT = 0x18 # macro +VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK = 0x00030000 # macro +VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK = 0x00040000 # macro +VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK = 0x00080000 # macro +VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK = 0x00100000 # macro +VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK = 0x00200000 # macro +VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK = 0x00400000 # macro +VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00800000 # macro +VM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK = 0x01000000 # macro +VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT = 0x12 # macro +VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x13 # macro +VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x14 # macro +VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x15 # macro +VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT = 0x16 # macro +VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x17 # macro +VM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT = 0x18 # macro +VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK = 0x00030000 # macro +VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK = 0x00040000 # macro +VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK = 0x00080000 # macro +VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK = 0x00100000 # macro +VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK = 0x00200000 # macro +VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK = 0x00400000 # macro +VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00800000 # macro +VM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK = 0x01000000 # macro +VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK = 0x00010000 # macro +VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK = 0x00010000 # macro +VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK = 0x00010000 # macro +VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK = 0x00010000 # macro +VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK = 0x00010000 # macro +VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK = 0x00010000 # macro +VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK = 0x00010000 # macro +VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK = 0x00010000 # macro +VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK = 0x00010000 # macro +VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK = 0x00010000 # macro +VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK = 0x00010000 # macro +VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK = 0x00010000 # macro +VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK = 0x00010000 # macro +VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK = 0x00010000 # macro +VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK = 0x00010000 # macro +VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK = 0x00010000 # macro +VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK = 0x00010000 # macro +VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT = 0x10 # macro +VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK = 0x00010000 # macro +VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT = 0x0 # macro +MC_VM_NB_MMIOBASE__MMIOBASE_MASK = 0xFFFFFFFF # macro +MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT = 0x0 # macro +MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK = 0xFFFFFFFF # macro +MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT = 0x17 # macro +MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK = 0x00800000 # macro +MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT = 0x3 # macro +MC_VM_NB_PCI_ARB__VGA_HOLE_MASK = 0x00000008 # macro +MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT = 0x17 # macro +MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK = 0xFF800000 # macro +MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT = 0x0 # macro +MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT = 0x17 # macro +MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK = 0x00000001 # macro +MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK = 0xFF800000 # macro +MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT = 0x0 # macro +MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK = 0x0000FFFF # macro +MC_VM_FB_OFFSET__FB_OFFSET__SHIFT = 0x0 # macro +MC_VM_FB_OFFSET__FB_OFFSET_MASK = 0x00FFFFFF # macro +MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT = 0x0 # macro +MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK = 0xFFFFFFFF # macro +MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT = 0x0 # macro +MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK = 0x0000000F # macro +MC_VM_STEERING__DEFAULT_STEERING__SHIFT = 0x0 # macro +MC_VM_STEERING__DEFAULT_STEERING_MASK = 0x00000003 # macro +MC_SHARED_VIRT_RESET_REQ__VF__SHIFT = 0x0 # macro +MC_SHARED_VIRT_RESET_REQ__PF__SHIFT = 0x1f # macro +MC_SHARED_VIRT_RESET_REQ__VF_MASK = 0x0000FFFF # macro +MC_SHARED_VIRT_RESET_REQ__PF_MASK = 0x80000000 # macro +MC_MEM_POWER_LS__LS_SETUP__SHIFT = 0x0 # macro +MC_MEM_POWER_LS__LS_HOLD__SHIFT = 0x6 # macro +MC_MEM_POWER_LS__LS_SETUP_MASK = 0x0000003F # macro +MC_MEM_POWER_LS__LS_HOLD_MASK = 0x00000FC0 # macro +MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT = 0x0 # macro +MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK = 0x00FFFFFF # macro +MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT = 0x0 # macro +MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK = 0x00FFFFFF # macro +MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT = 0x0 # macro +MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT = 0x1 # macro +MC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT = 0x2 # macro +MC_VM_APT_CNTL__PERMS_GRANTED__SHIFT = 0x3 # macro +MC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT = 0x4 # macro +MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK = 0x00000001 # macro +MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK = 0x00000002 # macro +MC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK = 0x00000004 # macro +MC_VM_APT_CNTL__PERMS_GRANTED_MASK = 0x00000008 # macro +MC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK = 0x00000030 # macro +MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT = 0x0 # macro +MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK = 0x00FFFFFF # macro +MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT = 0x0 # macro +MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK = 0x00FFFFFF # macro +MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT = 0x0 # macro +MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK = 0x00000001 # macro +UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT = 0xc # macro +UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT = 0xf # macro +UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT = 0x10 # macro +UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT = 0x18 # macro +UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK = 0x00007000 # macro +UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK = 0x00008000 # macro +UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK = 0x00FF0000 # macro +UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK = 0xFF000000 # macro +MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT = 0x0 # macro +MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT = 0x4 # macro +MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK = 0x0000000F # macro +MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK = 0x000000F0 # macro +MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT = 0x0 # macro +MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK = 0x0001FFFF # macro +MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT = 0x0 # macro +MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK = 0x00000001 # macro +MC_VM_HOST_MAPPING__MODE__SHIFT = 0x0 # macro +MC_VM_HOST_MAPPING__MODE_MASK = 0x00000001 # macro +MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT = 0x0 # macro +MC_VM_FB_LOCATION_BASE__FB_BASE_MASK = 0x00FFFFFF # macro +MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT = 0x0 # macro +MC_VM_FB_LOCATION_TOP__FB_TOP_MASK = 0x00FFFFFF # macro +MC_VM_AGP_TOP__AGP_TOP__SHIFT = 0x0 # macro +MC_VM_AGP_TOP__AGP_TOP_MASK = 0x00FFFFFF # macro +MC_VM_AGP_BOT__AGP_BOT__SHIFT = 0x0 # macro +MC_VM_AGP_BOT__AGP_BOT_MASK = 0x00FFFFFF # macro +MC_VM_AGP_BASE__AGP_BASE__SHIFT = 0x0 # macro +MC_VM_AGP_BASE__AGP_BASE_MASK = 0x00FFFFFF # macro +MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT = 0x0 # macro +MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK = 0x3FFFFFFF # macro +MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT = 0x0 # macro +MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK = 0x3FFFFFFF # macro +MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT = 0x0 # macro +MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT = 0x3 # macro +MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT = 0x5 # macro +MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT = 0x6 # macro +MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT = 0x7 # macro +MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT = 0xb # macro +MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT = 0xd # macro +MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK = 0x00000001 # macro +MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK = 0x00000018 # macro +MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK = 0x00000020 # macro +MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK = 0x00000040 # macro +MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK = 0x00000780 # macro +MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK = 0x00001800 # macro +MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK = 0x00002000 # macro +L2TLB_TLB0_STATUS__BUSY__SHIFT = 0x0 # macro +L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT = 0x1 # macro +L2TLB_TLB0_STATUS__BUSY_MASK = 0x00000001 # macro +L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK = 0x00000002 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT = 0x0 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK = 0xFFFFFFFF # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT = 0x0 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT = 0x4 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT = 0x9 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT = 0xd # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT = 0xe # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT = 0x10 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT = 0x11 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT = 0x12 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT = 0x13 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT = 0x1f # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK = 0x0000000F # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK = 0x000000F0 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK = 0x00001E00 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK = 0x00002000 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK = 0x0000C000 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK = 0x00010000 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK = 0x00020000 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK = 0x00040000 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK = 0x0FF80000 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK = 0x80000000 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT = 0x0 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK = 0xFFFFFFFF # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT = 0x0 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT = 0x4 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT = 0x7 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT = 0xd # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT = 0xe # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT = 0xf # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT = 0x10 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT = 0x11 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT = 0x12 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT = 0x14 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT = 0x15 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT = 0x16 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT = 0x1f # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK = 0x0000000F # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK = 0x00000070 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK = 0x00001F80 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK = 0x00002000 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK = 0x00004000 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK = 0x00008000 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK = 0x00010000 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK = 0x00020000 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK = 0x000C0000 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK = 0x00100000 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK = 0x00200000 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK = 0x00C00000 # macro +UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK = 0x80000000 # macro +TCP_INVALIDATE__START__SHIFT = 0x0 # macro +TCP_INVALIDATE__START_MASK = 0x00000001 # macro +TCP_STATUS__TCP_BUSY__SHIFT = 0x0 # macro +TCP_STATUS__INPUT_BUSY__SHIFT = 0x1 # macro +TCP_STATUS__ADRS_BUSY__SHIFT = 0x2 # macro +TCP_STATUS__TAGRAMS_BUSY__SHIFT = 0x3 # macro +TCP_STATUS__CNTRL_BUSY__SHIFT = 0x4 # macro +TCP_STATUS__LFIFO_BUSY__SHIFT = 0x5 # macro +TCP_STATUS__READ_BUSY__SHIFT = 0x6 # macro +TCP_STATUS__FORMAT_BUSY__SHIFT = 0x7 # macro +TCP_STATUS__VM_BUSY__SHIFT = 0x8 # macro +TCP_STATUS__TCP_BUSY_MASK = 0x00000001 # macro +TCP_STATUS__INPUT_BUSY_MASK = 0x00000002 # macro +TCP_STATUS__ADRS_BUSY_MASK = 0x00000004 # macro +TCP_STATUS__TAGRAMS_BUSY_MASK = 0x00000008 # macro +TCP_STATUS__CNTRL_BUSY_MASK = 0x00000010 # macro +TCP_STATUS__LFIFO_BUSY_MASK = 0x00000020 # macro +TCP_STATUS__READ_BUSY_MASK = 0x00000040 # macro +TCP_STATUS__FORMAT_BUSY_MASK = 0x00000080 # macro +TCP_STATUS__VM_BUSY_MASK = 0x00000100 # macro +TCP_CNTL__FORCE_HIT__SHIFT = 0x0 # macro +TCP_CNTL__FORCE_MISS__SHIFT = 0x1 # macro +TCP_CNTL__L1_SIZE__SHIFT = 0x2 # macro +TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT = 0x4 # macro +TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT = 0x5 # macro +TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT = 0xf # macro +TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT = 0x16 # macro +TCP_CNTL__DISABLE_Z_MAP__SHIFT = 0x1c # macro +TCP_CNTL__FORCE_HIT_MASK = 0x00000001 # macro +TCP_CNTL__FORCE_MISS_MASK = 0x00000002 # macro +TCP_CNTL__L1_SIZE_MASK = 0x0000000C # macro +TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK = 0x00000010 # macro +TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK = 0x00000020 # macro +TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK = 0x001F8000 # macro +TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK = 0x0FC00000 # macro +TCP_CNTL__DISABLE_Z_MAP_MASK = 0x10000000 # macro +TCP_CHAN_STEER_0__CHAN0__SHIFT = 0x0 # macro +TCP_CHAN_STEER_0__CHAN1__SHIFT = 0x4 # macro +TCP_CHAN_STEER_0__CHAN2__SHIFT = 0x8 # macro +TCP_CHAN_STEER_0__CHAN3__SHIFT = 0xc # macro +TCP_CHAN_STEER_0__CHAN4__SHIFT = 0x10 # macro +TCP_CHAN_STEER_0__CHAN5__SHIFT = 0x14 # macro +TCP_CHAN_STEER_0__CHAN6__SHIFT = 0x18 # macro +TCP_CHAN_STEER_0__CHAN7__SHIFT = 0x1c # macro +TCP_CHAN_STEER_0__CHAN0_MASK = 0x0000000F # macro +TCP_CHAN_STEER_0__CHAN1_MASK = 0x000000F0 # macro +TCP_CHAN_STEER_0__CHAN2_MASK = 0x00000F00 # macro +TCP_CHAN_STEER_0__CHAN3_MASK = 0x0000F000 # macro +TCP_CHAN_STEER_0__CHAN4_MASK = 0x000F0000 # macro +TCP_CHAN_STEER_0__CHAN5_MASK = 0x00F00000 # macro +TCP_CHAN_STEER_0__CHAN6_MASK = 0x0F000000 # macro +TCP_CHAN_STEER_0__CHAN7_MASK = 0xF0000000 # macro +TCP_CHAN_STEER_1__CHAN8__SHIFT = 0x0 # macro +TCP_CHAN_STEER_1__CHAN9__SHIFT = 0x4 # macro +TCP_CHAN_STEER_1__CHANA__SHIFT = 0x8 # macro +TCP_CHAN_STEER_1__CHANB__SHIFT = 0xc # macro +TCP_CHAN_STEER_1__CHANC__SHIFT = 0x10 # macro +TCP_CHAN_STEER_1__CHAND__SHIFT = 0x14 # macro +TCP_CHAN_STEER_1__CHANE__SHIFT = 0x18 # macro +TCP_CHAN_STEER_1__CHANF__SHIFT = 0x1c # macro +TCP_CHAN_STEER_1__CHAN8_MASK = 0x0000000F # macro +TCP_CHAN_STEER_1__CHAN9_MASK = 0x000000F0 # macro +TCP_CHAN_STEER_1__CHANA_MASK = 0x00000F00 # macro +TCP_CHAN_STEER_1__CHANB_MASK = 0x0000F000 # macro +TCP_CHAN_STEER_1__CHANC_MASK = 0x000F0000 # macro +TCP_CHAN_STEER_1__CHAND_MASK = 0x00F00000 # macro +TCP_CHAN_STEER_1__CHANE_MASK = 0x0F000000 # macro +TCP_CHAN_STEER_1__CHANF_MASK = 0xF0000000 # macro +TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT = 0x0 # macro +TCP_ADDR_CONFIG__ENABLE64KHASH__SHIFT = 0xb # macro +TCP_ADDR_CONFIG__ENABLE2MHASH__SHIFT = 0xc # macro +TCP_ADDR_CONFIG__ENABLE1GHASH__SHIFT = 0xd # macro +TCP_ADDR_CONFIG__ENABLE1THASH__SHIFT = 0xe # macro +TCP_ADDR_CONFIG__ENABLE4KHASH__SHIFT = 0xf # macro +TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK = 0x0000001F # macro +TCP_ADDR_CONFIG__ENABLE64KHASH_MASK = 0x00000800 # macro +TCP_ADDR_CONFIG__ENABLE2MHASH_MASK = 0x00001000 # macro +TCP_ADDR_CONFIG__ENABLE1GHASH_MASK = 0x00002000 # macro +TCP_ADDR_CONFIG__ENABLE1THASH_MASK = 0x00004000 # macro +TCP_ADDR_CONFIG__ENABLE4KHASH_MASK = 0x00008000 # macro +TCP_CREDIT__LFIFO_CREDIT__SHIFT = 0x0 # macro +TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT = 0x10 # macro +TCP_CREDIT__TD_CREDIT__SHIFT = 0x1d # macro +TCP_CREDIT__LFIFO_CREDIT_MASK = 0x000007FF # macro +TCP_CREDIT__REQ_FIFO_CREDIT_MASK = 0x007F0000 # macro +TCP_CREDIT__TD_CREDIT_MASK = 0xE0000000 # macro +TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT = 0x0 # macro +TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT = 0x8 # macro +TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT = 0x10 # macro +TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT = 0x18 # macro +TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK = 0x00000007 # macro +TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK = 0x00000700 # macro +TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK = 0x00070000 # macro +TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK = 0x07000000 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT = 0x0 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT = 0x2 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT = 0x4 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT = 0x6 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT = 0x8 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT = 0xa # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT = 0xc # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT = 0xe # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT = 0x10 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT = 0x12 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT = 0x14 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT = 0x16 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT = 0x18 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT = 0x1a # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT = 0x1c # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT = 0x1e # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK = 0x00000003 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK = 0x0000000C # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK = 0x00000030 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK = 0x000000C0 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK = 0x00000300 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK = 0x00000C00 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK = 0x00003000 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK = 0x0000C000 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK = 0x00030000 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK = 0x000C0000 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK = 0x00300000 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK = 0x00C00000 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK = 0x03000000 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK = 0x0C000000 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK = 0x30000000 # macro +TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK = 0xC0000000 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT = 0x0 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT = 0x2 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT = 0x4 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT = 0x6 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT = 0x8 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT = 0xa # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT = 0xc # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT = 0xe # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT = 0x10 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT = 0x12 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT = 0x14 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT = 0x16 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT = 0x18 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT = 0x1a # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT = 0x1c # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT = 0x1e # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK = 0x00000003 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK = 0x0000000C # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK = 0x00000030 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK = 0x000000C0 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK = 0x00000300 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK = 0x00000C00 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK = 0x00003000 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK = 0x0000C000 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK = 0x00030000 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK = 0x000C0000 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK = 0x00300000 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK = 0x00C00000 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK = 0x03000000 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK = 0x0C000000 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK = 0x30000000 # macro +TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK = 0xC0000000 # macro +TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT = 0x0 # macro +TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT = 0x1 # macro +TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT = 0x2 # macro +TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT = 0x3 # macro +TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT = 0x4 # macro +TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT = 0x5 # macro +TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT = 0x6 # macro +TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT = 0x7 # macro +TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT = 0x8 # macro +TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT = 0x9 # macro +TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT = 0xa # macro +TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT = 0xb # macro +TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT = 0xc # macro +TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT = 0xd # macro +TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT = 0xe # macro +TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT = 0xf # macro +TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT = 0x10 # macro +TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT = 0x11 # macro +TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT = 0x12 # macro +TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT = 0x13 # macro +TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT = 0x14 # macro +TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT = 0x15 # macro +TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT = 0x16 # macro +TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT = 0x17 # macro +TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT = 0x18 # macro +TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT = 0x19 # macro +TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT = 0x1a # macro +TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT = 0x1b # macro +TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT = 0x1c # macro +TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT = 0x1d # macro +TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT = 0x1e # macro +TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT = 0x1f # macro +TC_CFG_L1_STORE_POLICY__POLICY_0_MASK = 0x00000001 # macro +TC_CFG_L1_STORE_POLICY__POLICY_1_MASK = 0x00000002 # macro +TC_CFG_L1_STORE_POLICY__POLICY_2_MASK = 0x00000004 # macro +TC_CFG_L1_STORE_POLICY__POLICY_3_MASK = 0x00000008 # macro +TC_CFG_L1_STORE_POLICY__POLICY_4_MASK = 0x00000010 # macro +TC_CFG_L1_STORE_POLICY__POLICY_5_MASK = 0x00000020 # macro +TC_CFG_L1_STORE_POLICY__POLICY_6_MASK = 0x00000040 # macro +TC_CFG_L1_STORE_POLICY__POLICY_7_MASK = 0x00000080 # macro +TC_CFG_L1_STORE_POLICY__POLICY_8_MASK = 0x00000100 # macro +TC_CFG_L1_STORE_POLICY__POLICY_9_MASK = 0x00000200 # macro +TC_CFG_L1_STORE_POLICY__POLICY_10_MASK = 0x00000400 # macro +TC_CFG_L1_STORE_POLICY__POLICY_11_MASK = 0x00000800 # macro +TC_CFG_L1_STORE_POLICY__POLICY_12_MASK = 0x00001000 # macro +TC_CFG_L1_STORE_POLICY__POLICY_13_MASK = 0x00002000 # macro +TC_CFG_L1_STORE_POLICY__POLICY_14_MASK = 0x00004000 # macro +TC_CFG_L1_STORE_POLICY__POLICY_15_MASK = 0x00008000 # macro +TC_CFG_L1_STORE_POLICY__POLICY_16_MASK = 0x00010000 # macro +TC_CFG_L1_STORE_POLICY__POLICY_17_MASK = 0x00020000 # macro +TC_CFG_L1_STORE_POLICY__POLICY_18_MASK = 0x00040000 # macro +TC_CFG_L1_STORE_POLICY__POLICY_19_MASK = 0x00080000 # macro +TC_CFG_L1_STORE_POLICY__POLICY_20_MASK = 0x00100000 # macro +TC_CFG_L1_STORE_POLICY__POLICY_21_MASK = 0x00200000 # macro +TC_CFG_L1_STORE_POLICY__POLICY_22_MASK = 0x00400000 # macro +TC_CFG_L1_STORE_POLICY__POLICY_23_MASK = 0x00800000 # macro +TC_CFG_L1_STORE_POLICY__POLICY_24_MASK = 0x01000000 # macro +TC_CFG_L1_STORE_POLICY__POLICY_25_MASK = 0x02000000 # macro +TC_CFG_L1_STORE_POLICY__POLICY_26_MASK = 0x04000000 # macro +TC_CFG_L1_STORE_POLICY__POLICY_27_MASK = 0x08000000 # macro +TC_CFG_L1_STORE_POLICY__POLICY_28_MASK = 0x10000000 # macro +TC_CFG_L1_STORE_POLICY__POLICY_29_MASK = 0x20000000 # macro +TC_CFG_L1_STORE_POLICY__POLICY_30_MASK = 0x40000000 # macro +TC_CFG_L1_STORE_POLICY__POLICY_31_MASK = 0x80000000 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT = 0x0 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT = 0x2 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT = 0x4 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT = 0x6 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT = 0x8 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT = 0xa # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT = 0xc # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT = 0xe # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT = 0x10 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT = 0x12 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT = 0x14 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT = 0x16 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT = 0x18 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT = 0x1a # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT = 0x1c # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT = 0x1e # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK = 0x00000003 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK = 0x0000000C # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK = 0x00000030 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK = 0x000000C0 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK = 0x00000300 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK = 0x00000C00 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK = 0x00003000 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK = 0x0000C000 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK = 0x00030000 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK = 0x000C0000 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK = 0x00300000 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK = 0x00C00000 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK = 0x03000000 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK = 0x0C000000 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK = 0x30000000 # macro +TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK = 0xC0000000 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT = 0x0 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT = 0x2 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT = 0x4 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT = 0x6 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT = 0x8 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT = 0xa # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT = 0xc # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT = 0xe # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT = 0x10 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT = 0x12 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT = 0x14 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT = 0x16 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT = 0x18 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT = 0x1a # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT = 0x1c # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT = 0x1e # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK = 0x00000003 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK = 0x0000000C # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK = 0x00000030 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK = 0x000000C0 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK = 0x00000300 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK = 0x00000C00 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK = 0x00003000 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK = 0x0000C000 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK = 0x00030000 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK = 0x000C0000 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK = 0x00300000 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK = 0x00C00000 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK = 0x03000000 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK = 0x0C000000 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK = 0x30000000 # macro +TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK = 0xC0000000 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT = 0x0 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT = 0x2 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT = 0x4 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT = 0x6 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT = 0x8 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT = 0xa # macro +TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT = 0xc # macro +TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT = 0xe # macro +TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT = 0x10 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT = 0x12 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT = 0x14 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT = 0x16 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT = 0x18 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT = 0x1a # macro +TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT = 0x1c # macro +TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT = 0x1e # macro +TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK = 0x00000003 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK = 0x0000000C # macro +TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK = 0x00000030 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK = 0x000000C0 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK = 0x00000300 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK = 0x00000C00 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK = 0x00003000 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK = 0x0000C000 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK = 0x00030000 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK = 0x000C0000 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK = 0x00300000 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK = 0x00C00000 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK = 0x03000000 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK = 0x0C000000 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK = 0x30000000 # macro +TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK = 0xC0000000 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT = 0x0 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT = 0x2 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT = 0x4 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT = 0x6 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT = 0x8 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT = 0xa # macro +TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT = 0xc # macro +TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT = 0xe # macro +TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT = 0x10 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT = 0x12 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT = 0x14 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT = 0x16 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT = 0x18 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT = 0x1a # macro +TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT = 0x1c # macro +TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT = 0x1e # macro +TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK = 0x00000003 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK = 0x0000000C # macro +TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK = 0x00000030 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK = 0x000000C0 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK = 0x00000300 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK = 0x00000C00 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK = 0x00003000 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK = 0x0000C000 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK = 0x00030000 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK = 0x000C0000 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK = 0x00300000 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK = 0x00C00000 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK = 0x03000000 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK = 0x0C000000 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK = 0x30000000 # macro +TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK = 0xC0000000 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT = 0x0 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT = 0x2 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT = 0x4 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT = 0x6 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT = 0x8 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT = 0xa # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT = 0xc # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT = 0xe # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT = 0x10 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT = 0x12 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT = 0x14 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT = 0x16 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT = 0x18 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT = 0x1a # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT = 0x1c # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT = 0x1e # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK = 0x00000003 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK = 0x0000000C # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK = 0x00000030 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK = 0x000000C0 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK = 0x00000300 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK = 0x00000C00 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK = 0x00003000 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK = 0x0000C000 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK = 0x00030000 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK = 0x000C0000 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK = 0x00300000 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK = 0x00C00000 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK = 0x03000000 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK = 0x0C000000 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK = 0x30000000 # macro +TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK = 0xC0000000 # macro +TC_CFG_L1_VOLATILE__VOL__SHIFT = 0x0 # macro +TC_CFG_L1_VOLATILE__VOL_MASK = 0x0000000F # macro +TC_CFG_L2_VOLATILE__VOL__SHIFT = 0x0 # macro +TC_CFG_L2_VOLATILE__VOL_MASK = 0x0000000F # macro +TCP_UE_EDC_HI_REG__ECC__SHIFT = 0x0 # macro +TCP_UE_EDC_HI_REG__PARITY__SHIFT = 0x1 # macro +TCP_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +TCP_UE_EDC_HI_REG__ERR_INFO__SHIFT = 0x3 # macro +TCP_UE_EDC_HI_REG__UE_CNT__SHIFT = 0x17 # macro +TCP_UE_EDC_HI_REG__FED_CNT__SHIFT = 0x1a # macro +TCP_UE_EDC_HI_REG__RESERVED__SHIFT = 0x1d # macro +TCP_UE_EDC_HI_REG__ECC_MASK = 0x00000001 # macro +TCP_UE_EDC_HI_REG__PARITY_MASK = 0x00000002 # macro +TCP_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +TCP_UE_EDC_HI_REG__ERR_INFO_MASK = 0x007FFFF8 # macro +TCP_UE_EDC_HI_REG__UE_CNT_MASK = 0x03800000 # macro +TCP_UE_EDC_HI_REG__FED_CNT_MASK = 0x1C000000 # macro +TCP_UE_EDC_HI_REG__RESERVED_MASK = 0xE0000000 # macro +TCP_UE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT = 0x0 # macro +TCP_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT = 0x1 # macro +TCP_UE_EDC_LO_REG__ADDRESS__SHIFT = 0x2 # macro +TCP_UE_EDC_LO_REG__MEM_ID__SHIFT = 0x18 # macro +TCP_UE_EDC_LO_REG__STATUS_VALID_FLAG_MASK = 0x00000001 # macro +TCP_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK = 0x00000002 # macro +TCP_UE_EDC_LO_REG__ADDRESS_MASK = 0x00FFFFFC # macro +TCP_UE_EDC_LO_REG__MEM_ID_MASK = 0xFF000000 # macro +TCP_CE_EDC_HI_REG__ECC__SHIFT = 0x0 # macro +TCP_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +TCP_CE_EDC_HI_REG__ERR_INFO__SHIFT = 0x3 # macro +TCP_CE_EDC_HI_REG__CE_CNT__SHIFT = 0x17 # macro +TCP_CE_EDC_HI_REG__POISON__SHIFT = 0x1a # macro +TCP_CE_EDC_HI_REG__RESERVED__SHIFT = 0x1b # macro +TCP_CE_EDC_HI_REG__ECC_MASK = 0x00000001 # macro +TCP_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +TCP_CE_EDC_HI_REG__ERR_INFO_MASK = 0x007FFFF8 # macro +TCP_CE_EDC_HI_REG__CE_CNT_MASK = 0x03800000 # macro +TCP_CE_EDC_HI_REG__POISON_MASK = 0x04000000 # macro +TCP_CE_EDC_HI_REG__RESERVED_MASK = 0xF8000000 # macro +TCP_CE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT = 0x0 # macro +TCP_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT = 0x1 # macro +TCP_CE_EDC_LO_REG__ADDRESS__SHIFT = 0x2 # macro +TCP_CE_EDC_LO_REG__MEM_ID__SHIFT = 0x18 # macro +TCP_CE_EDC_LO_REG__STATUS_VALID_FLAG_MASK = 0x00000001 # macro +TCP_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK = 0x00000002 # macro +TCP_CE_EDC_LO_REG__ADDRESS_MASK = 0x00FFFFFC # macro +TCP_CE_EDC_LO_REG__MEM_ID_MASK = 0xFF000000 # macro +TCI_UE_EDC_HI_REG__ECC__SHIFT = 0x0 # macro +TCI_UE_EDC_HI_REG__PARITY__SHIFT = 0x1 # macro +TCI_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +TCI_UE_EDC_HI_REG__ERR_INFO__SHIFT = 0x3 # macro +TCI_UE_EDC_HI_REG__UE_CNT__SHIFT = 0x17 # macro +TCI_UE_EDC_HI_REG__FED_CNT__SHIFT = 0x1a # macro +TCI_UE_EDC_HI_REG__RESERVED__SHIFT = 0x1d # macro +TCI_UE_EDC_HI_REG__ECC_MASK = 0x00000001 # macro +TCI_UE_EDC_HI_REG__PARITY_MASK = 0x00000002 # macro +TCI_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +TCI_UE_EDC_HI_REG__ERR_INFO_MASK = 0x007FFFF8 # macro +TCI_UE_EDC_HI_REG__UE_CNT_MASK = 0x03800000 # macro +TCI_UE_EDC_HI_REG__FED_CNT_MASK = 0x1C000000 # macro +TCI_UE_EDC_HI_REG__RESERVED_MASK = 0xE0000000 # macro +TCI_UE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT = 0x0 # macro +TCI_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT = 0x1 # macro +TCI_UE_EDC_LO_REG__ADDRESS__SHIFT = 0x2 # macro +TCI_UE_EDC_LO_REG__MEM_ID__SHIFT = 0x18 # macro +TCI_UE_EDC_LO_REG__STATUS_VALID_FLAG_MASK = 0x00000001 # macro +TCI_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK = 0x00000002 # macro +TCI_UE_EDC_LO_REG__ADDRESS_MASK = 0x00FFFFFC # macro +TCI_UE_EDC_LO_REG__MEM_ID_MASK = 0xFF000000 # macro +TCI_CE_EDC_HI_REG__ECC__SHIFT = 0x0 # macro +TCI_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +TCI_CE_EDC_HI_REG__ERR_INFO__SHIFT = 0x3 # macro +TCI_CE_EDC_HI_REG__CE_CNT__SHIFT = 0x17 # macro +TCI_CE_EDC_HI_REG__POISON__SHIFT = 0x1a # macro +TCI_CE_EDC_HI_REG__RESERVED__SHIFT = 0x1b # macro +TCI_CE_EDC_HI_REG__ECC_MASK = 0x00000001 # macro +TCI_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +TCI_CE_EDC_HI_REG__ERR_INFO_MASK = 0x007FFFF8 # macro +TCI_CE_EDC_HI_REG__CE_CNT_MASK = 0x03800000 # macro +TCI_CE_EDC_HI_REG__POISON_MASK = 0x04000000 # macro +TCI_CE_EDC_HI_REG__RESERVED_MASK = 0xF8000000 # macro +TCI_CE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT = 0x0 # macro +TCI_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT = 0x1 # macro +TCI_CE_EDC_LO_REG__ADDRESS__SHIFT = 0x2 # macro +TCI_CE_EDC_LO_REG__MEM_ID__SHIFT = 0x18 # macro +TCI_CE_EDC_LO_REG__STATUS_VALID_FLAG_MASK = 0x00000001 # macro +TCI_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK = 0x00000002 # macro +TCI_CE_EDC_LO_REG__ADDRESS_MASK = 0x00FFFFFC # macro +TCI_CE_EDC_LO_REG__MEM_ID_MASK = 0xFF000000 # macro +TCI_MISC__FGCG_REPEATER_DISABLE__SHIFT = 0x0 # macro +TCI_MISC__LEGACY_MGCG_DISABLE__SHIFT = 0x1 # macro +TCI_MISC__FGCG_REPEATER_DISABLE_MASK = 0x00000001 # macro +TCI_MISC__LEGACY_MGCG_DISABLE_MASK = 0x00000002 # macro +TCI_CNTL_3__DISABLE_DOUBLING_L2_BANDWIDTH__SHIFT = 0x0 # macro +TCI_CNTL_3__COMBINING_DELAY_WINDOW__SHIFT = 0x2 # macro +TCI_CNTL_3__CHICKEN_BIT_TCR_MGCG__SHIFT = 0x4 # macro +TCI_CNTL_3__TCR_FGCG_REPEATER_DISABLE__SHIFT = 0x7 # macro +TCI_CNTL_3__DISABLE_DOUBLING_L2_BANDWIDTH_MASK = 0x00000003 # macro +TCI_CNTL_3__COMBINING_DELAY_WINDOW_MASK = 0x0000000C # macro +TCI_CNTL_3__CHICKEN_BIT_TCR_MGCG_MASK = 0x00000070 # macro +TCI_CNTL_3__TCR_FGCG_REPEATER_DISABLE_MASK = 0x00000080 # macro +TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_DATA_SEL__SHIFT = 0x0 # macro +TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT = 0x2 # macro +TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_DATA_SEL_MASK = 0x00000003 # macro +TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_SINGLE_WRITE_MASK = 0x00000004 # macro +TCI_DSM_CNTL2__WRITE_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +TCI_DSM_CNTL2__WRITE_RAM_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +TCI_DSM_CNTL2__TCI_INJECT_DELAY__SHIFT = 0x1a # macro +TCI_DSM_CNTL2__WRITE_RAM_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +TCI_DSM_CNTL2__WRITE_RAM_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +TCI_DSM_CNTL2__TCI_INJECT_DELAY_MASK = 0xFC000000 # macro +TCI_STATUS__TCI_BUSY__SHIFT = 0x0 # macro +TCI_STATUS__TCI_BUSY_MASK = 0x00000001 # macro +TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT = 0x0 # macro +TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT = 0x10 # macro +TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT = 0x18 # macro +TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK = 0x0000FFFF # macro +TCI_CNTL_1__REQ_FIFO_DEPTH_MASK = 0x00FF0000 # macro +TCI_CNTL_1__WDATA_RAM_DEPTH_MASK = 0xFF000000 # macro +TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT = 0x0 # macro +TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT = 0x1 # macro +TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK = 0x00000001 # macro +TCI_CNTL_2__TCA_MAX_CREDIT_MASK = 0x000001FE # macro +TCC_CTRL__CACHE_SIZE__SHIFT = 0x0 # macro +TCC_CTRL__RATE__SHIFT = 0x2 # macro +TCC_CTRL__WRITEBACK_MARGIN__SHIFT = 0x4 # macro +TCC_CTRL__SRC_FIFO_SIZE__SHIFT = 0xc # macro +TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT = 0x10 # macro +TCC_CTRL__LINEAR_SET_HASH__SHIFT = 0x15 # macro +TCC_CTRL__OUTPUT_FIFO_CLK_MODE__SHIFT = 0x16 # macro +TCC_CTRL__EXECUTE_CLK_MODE__SHIFT = 0x17 # macro +TCC_CTRL__RETURN_BUFFER_CLK_MODE__SHIFT = 0x19 # macro +TCC_CTRL__SRC_FIFO_CLK_MODE__SHIFT = 0x1a # macro +TCC_CTRL__MC_WRITE_CLK_MODE__SHIFT = 0x1b # macro +TCC_CTRL__LATENCY_FIFO_CLK_MODE__SHIFT = 0x1c # macro +TCC_CTRL__DISABLE_SHARED_128B_READ_REQUEST__SHIFT = 0x1d # macro +TCC_CTRL__CACHE_SIZE_MASK = 0x00000003 # macro +TCC_CTRL__RATE_MASK = 0x0000000C # macro +TCC_CTRL__WRITEBACK_MARGIN_MASK = 0x000000F0 # macro +TCC_CTRL__SRC_FIFO_SIZE_MASK = 0x0000F000 # macro +TCC_CTRL__LATENCY_FIFO_SIZE_MASK = 0x000F0000 # macro +TCC_CTRL__LINEAR_SET_HASH_MASK = 0x00200000 # macro +TCC_CTRL__OUTPUT_FIFO_CLK_MODE_MASK = 0x00400000 # macro +TCC_CTRL__EXECUTE_CLK_MODE_MASK = 0x01800000 # macro +TCC_CTRL__RETURN_BUFFER_CLK_MODE_MASK = 0x02000000 # macro +TCC_CTRL__SRC_FIFO_CLK_MODE_MASK = 0x04000000 # macro +TCC_CTRL__MC_WRITE_CLK_MODE_MASK = 0x08000000 # macro +TCC_CTRL__LATENCY_FIFO_CLK_MODE_MASK = 0x10000000 # macro +TCC_CTRL__DISABLE_SHARED_128B_READ_REQUEST_MASK = 0x20000000 # macro +TCC_CTRL2__PROBE_FIFO_SIZE__SHIFT = 0x0 # macro +TCC_CTRL2__INF_NAN_CLAMP__SHIFT = 0x10 # macro +TCC_CTRL2__PROBE_FILTER_CTRL__SHIFT = 0x11 # macro +TCC_CTRL2__WAIT_CLK_STABLE_CNT__SHIFT = 0x12 # macro +TCC_CTRL2__TCC_TCX_REPEATER_FGCG_DISABLE__SHIFT = 0x17 # macro +TCC_CTRL2__TCC_EA0_RDREQ_FGCG_DISABLE__SHIFT = 0x18 # macro +TCC_CTRL2__TCC_EA0_WRREQ_FGCG_DISABLE__SHIFT = 0x19 # macro +TCC_CTRL2__TCC_TCX_ACK_REPEATER_FGCG_DISABLE__SHIFT = 0x1a # macro +TCC_CTRL2__TCC_TCA_HOLE_REPEATER_FGCG_DISABLE__SHIFT = 0x1b # macro +TCC_CTRL2__TCC_TCA_RTN_REPEATER_FGCG_DISABLE__SHIFT = 0x1c # macro +TCC_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK__SHIFT = 0x1d # macro +TCC_CTRL2__Enable_TCC_64K_2M_1G_1T_hash__SHIFT = 0x1e # macro +TCC_CTRL2__PROBE_FIFO_SIZE_MASK = 0x0000000F # macro +TCC_CTRL2__INF_NAN_CLAMP_MASK = 0x00010000 # macro +TCC_CTRL2__PROBE_FILTER_CTRL_MASK = 0x00020000 # macro +TCC_CTRL2__WAIT_CLK_STABLE_CNT_MASK = 0x007C0000 # macro +TCC_CTRL2__TCC_TCX_REPEATER_FGCG_DISABLE_MASK = 0x00800000 # macro +TCC_CTRL2__TCC_EA0_RDREQ_FGCG_DISABLE_MASK = 0x01000000 # macro +TCC_CTRL2__TCC_EA0_WRREQ_FGCG_DISABLE_MASK = 0x02000000 # macro +TCC_CTRL2__TCC_TCX_ACK_REPEATER_FGCG_DISABLE_MASK = 0x04000000 # macro +TCC_CTRL2__TCC_TCA_HOLE_REPEATER_FGCG_DISABLE_MASK = 0x08000000 # macro +TCC_CTRL2__TCC_TCA_RTN_REPEATER_FGCG_DISABLE_MASK = 0x10000000 # macro +TCC_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK_MASK = 0x20000000 # macro +TCC_CTRL2__Enable_TCC_64K_2M_1G_1T_hash_MASK = 0x40000000 # macro +TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL__SHIFT = 0x0 # macro +TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE__SHIFT = 0x2 # macro +TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL__SHIFT = 0x3 # macro +TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE__SHIFT = 0x5 # macro +TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL__SHIFT = 0x6 # macro +TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE__SHIFT = 0x8 # macro +TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL__SHIFT = 0x9 # macro +TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE__SHIFT = 0xb # macro +TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL__SHIFT = 0xc # macro +TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE__SHIFT = 0xe # macro +TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL__SHIFT = 0xf # macro +TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE__SHIFT = 0x11 # macro +TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT = 0x12 # macro +TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT = 0x14 # macro +TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT = 0x15 # macro +TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT = 0x17 # macro +TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL__SHIFT = 0x18 # macro +TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE__SHIFT = 0x1a # macro +TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL__SHIFT = 0x1b # macro +TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE__SHIFT = 0x1d # macro +TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL_MASK = 0x00000003 # macro +TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE_MASK = 0x00000004 # macro +TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL_MASK = 0x00000018 # macro +TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE_MASK = 0x00000020 # macro +TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL_MASK = 0x000000C0 # macro +TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE_MASK = 0x00000100 # macro +TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL_MASK = 0x00000600 # macro +TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE_MASK = 0x00000800 # macro +TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL_MASK = 0x00003000 # macro +TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE_MASK = 0x00004000 # macro +TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL_MASK = 0x00018000 # macro +TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE_MASK = 0x00020000 # macro +TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL_MASK = 0x000C0000 # macro +TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK = 0x00100000 # macro +TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL_MASK = 0x00600000 # macro +TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK = 0x00800000 # macro +TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL_MASK = 0x03000000 # macro +TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE_MASK = 0x04000000 # macro +TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL_MASK = 0x18000000 # macro +TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE_MASK = 0x20000000 # macro +TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL__SHIFT = 0x0 # macro +TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT = 0x2 # macro +TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL__SHIFT = 0x3 # macro +TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT = 0x5 # macro +TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL__SHIFT = 0x6 # macro +TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT = 0x8 # macro +TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL__SHIFT = 0x9 # macro +TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE__SHIFT = 0xb # macro +TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT = 0xc # macro +TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT = 0xe # macro +TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL__SHIFT = 0xf # macro +TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT = 0x11 # macro +TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL__SHIFT = 0x12 # macro +TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT = 0x14 # macro +TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL__SHIFT = 0x15 # macro +TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE__SHIFT = 0x17 # macro +TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL__SHIFT = 0x18 # macro +TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE__SHIFT = 0x1a # macro +TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_DATA_SEL__SHIFT = 0x1b # macro +TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_SINGLE_WRITE__SHIFT = 0x1d # macro +TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL_MASK = 0x00000003 # macro +TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE_MASK = 0x00000004 # macro +TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL_MASK = 0x00000018 # macro +TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE_MASK = 0x00000020 # macro +TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL_MASK = 0x000000C0 # macro +TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE_MASK = 0x00000100 # macro +TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL_MASK = 0x00000600 # macro +TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE_MASK = 0x00000800 # macro +TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK = 0x00003000 # macro +TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK = 0x00004000 # macro +TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL_MASK = 0x00018000 # macro +TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE_MASK = 0x00020000 # macro +TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL_MASK = 0x000C0000 # macro +TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE_MASK = 0x00100000 # macro +TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL_MASK = 0x00600000 # macro +TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE_MASK = 0x00800000 # macro +TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL_MASK = 0x03000000 # macro +TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE_MASK = 0x04000000 # macro +TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_DATA_SEL_MASK = 0x18000000 # macro +TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_SINGLE_WRITE_MASK = 0x20000000 # macro +TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT__SHIFT = 0x6 # macro +TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY__SHIFT = 0x8 # macro +TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY__SHIFT = 0xb # macro +TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT__SHIFT = 0xc # macro +TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY__SHIFT = 0xe # macro +TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT__SHIFT = 0xf # macro +TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY__SHIFT = 0x11 # macro +TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT = 0x12 # macro +TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY__SHIFT = 0x14 # macro +TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT = 0x15 # macro +TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY__SHIFT = 0x17 # macro +TCC_DSM_CNTL2__INJECT_DELAY__SHIFT = 0x1a # macro +TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT_MASK = 0x000000C0 # macro +TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY_MASK = 0x00000100 # macro +TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT_MASK = 0x00003000 # macro +TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY_MASK = 0x00004000 # macro +TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT_MASK = 0x00018000 # macro +TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY_MASK = 0x00020000 # macro +TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT_MASK = 0x000C0000 # macro +TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY_MASK = 0x00100000 # macro +TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT_MASK = 0x00600000 # macro +TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY_MASK = 0x00800000 # macro +TCC_DSM_CNTL2__INJECT_DELAY_MASK = 0xFC000000 # macro +TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT__SHIFT = 0x6 # macro +TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY__SHIFT = 0x8 # macro +TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY__SHIFT = 0xb # macro +TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT__SHIFT = 0xc # macro +TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY__SHIFT = 0xe # macro +TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT__SHIFT = 0xf # macro +TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY__SHIFT = 0x11 # macro +TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT__SHIFT = 0x12 # macro +TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY__SHIFT = 0x14 # macro +TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT__SHIFT = 0x15 # macro +TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY__SHIFT = 0x17 # macro +TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT__SHIFT = 0x18 # macro +TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY__SHIFT = 0x1a # macro +TCC_DSM_CNTL2A__OUTPUT_FIFOS_ENABLE_ERROR_INJECT__SHIFT = 0x1b # macro +TCC_DSM_CNTL2A__OUTPUT_FIFOS_SELECT_INJECT_DELAY__SHIFT = 0x1d # macro +TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT_MASK = 0x000000C0 # macro +TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY_MASK = 0x00000100 # macro +TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT_MASK = 0x00003000 # macro +TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY_MASK = 0x00004000 # macro +TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT_MASK = 0x00018000 # macro +TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY_MASK = 0x00020000 # macro +TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT_MASK = 0x000C0000 # macro +TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY_MASK = 0x00100000 # macro +TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT_MASK = 0x00600000 # macro +TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY_MASK = 0x00800000 # macro +TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT_MASK = 0x03000000 # macro +TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY_MASK = 0x04000000 # macro +TCC_DSM_CNTL2A__OUTPUT_FIFOS_ENABLE_ERROR_INJECT_MASK = 0x18000000 # macro +TCC_DSM_CNTL2A__OUTPUT_FIFOS_SELECT_INJECT_DELAY_MASK = 0x20000000 # macro +TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_ENABLE_ERROR_INJECT__SHIFT = 0xc # macro +TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_SELECT_INJECT_DELAY__SHIFT = 0xe # macro +TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_DATA_SEL__SHIFT = 0xf # macro +TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT = 0x11 # macro +TCC_DSM_CNTL2B__RETURN_BUFFER_LEVEL_BUBBLE_THRESHOLD__SHIFT = 0x12 # macro +TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_ENABLE_ERROR_INJECT_MASK = 0x00003000 # macro +TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_SELECT_INJECT_DELAY_MASK = 0x00004000 # macro +TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_DATA_SEL_MASK = 0x00018000 # macro +TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_SINGLE_WRITE_MASK = 0x00020000 # macro +TCC_DSM_CNTL2B__RETURN_BUFFER_LEVEL_BUBBLE_THRESHOLD_MASK = 0x00FC0000 # macro +TCC_WBINVL2__DONE__SHIFT = 0x4 # macro +TCC_WBINVL2__DONE_MASK = 0x00000010 # macro +TCC_SOFT_RESET__HALT_FOR_RESET__SHIFT = 0x0 # macro +TCC_SOFT_RESET__HALT_FOR_RESET_MASK = 0x00000001 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_DATA_SEL__SHIFT = 0x0 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_SINGLE_WRITE__SHIFT = 0x2 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_DATA_SEL__SHIFT = 0x3 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_SINGLE_WRITE__SHIFT = 0x5 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_DATA_SEL__SHIFT = 0x6 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_SINGLE_WRITE__SHIFT = 0x8 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_DATA_SEL__SHIFT = 0x9 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_SINGLE_WRITE__SHIFT = 0xb # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_ENABLE_ERROR_INJECT__SHIFT = 0xc # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_SELECT_INJECT_DELAY__SHIFT = 0xe # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_ENABLE_ERROR_INJECT__SHIFT = 0xf # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_SELECT_INJECT_DELAY__SHIFT = 0x11 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_ENABLE_ERROR_INJECT__SHIFT = 0x12 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_SELECT_INJECT_DELAY__SHIFT = 0x14 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_ENABLE_ERROR_INJECT__SHIFT = 0x15 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_SELECT_INJECT_DELAY__SHIFT = 0x17 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_DATA_SEL_MASK = 0x00000003 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_SINGLE_WRITE_MASK = 0x00000004 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_DATA_SEL_MASK = 0x00000018 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_SINGLE_WRITE_MASK = 0x00000020 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_DATA_SEL_MASK = 0x000000C0 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_SINGLE_WRITE_MASK = 0x00000100 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_DATA_SEL_MASK = 0x00000600 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_SINGLE_WRITE_MASK = 0x00000800 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_ENABLE_ERROR_INJECT_MASK = 0x00003000 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_SELECT_INJECT_DELAY_MASK = 0x00004000 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_ENABLE_ERROR_INJECT_MASK = 0x00018000 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_SELECT_INJECT_DELAY_MASK = 0x00020000 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_ENABLE_ERROR_INJECT_MASK = 0x000C0000 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_SELECT_INJECT_DELAY_MASK = 0x00100000 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_ENABLE_ERROR_INJECT_MASK = 0x00600000 # macro +TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_SELECT_INJECT_DELAY_MASK = 0x00800000 # macro +TCA_CTRL__HOLE_TIMEOUT__SHIFT = 0x0 # macro +TCA_CTRL__RB_STILL_4_PHASE__SHIFT = 0x4 # macro +TCA_CTRL__RB_AS_TCI__SHIFT = 0x5 # macro +TCA_CTRL__DISABLE_UTCL2_PRIORITY__SHIFT = 0x6 # macro +TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER__SHIFT = 0x7 # macro +TCA_CTRL__TCA_TCC_FGCG_DISABLE__SHIFT = 0x8 # macro +TCA_CTRL__TCA_TCA_FGCG_DISABLE__SHIFT = 0x9 # macro +TCA_CTRL__TCA_TCH_FGCG_DISABLE__SHIFT = 0xa # macro +TCA_CTRL__TCA_TCX_FGCG_DISABLE__SHIFT = 0xb # macro +TCA_CTRL__TCA_RANDOM_REVERSE_PRIORITY_ENABLE__SHIFT = 0xc # macro +TCA_CTRL__RTN_CREDIT_THRESHOLD__SHIFT = 0xd # macro +TCA_CTRL__ACK_CREDIT_THRESHOLD__SHIFT = 0x10 # macro +TCA_CTRL__RTN_ARB_MODE__SHIFT = 0x13 # macro +TCA_CTRL__HOLE_ARB_SHARE_THRESHOLD__SHIFT = 0x18 # macro +TCA_CTRL__HOLE_ARB_LANE_THRESHOLD__SHIFT = 0x1c # macro +TCA_CTRL__HOLE_TIMEOUT_MASK = 0x0000000F # macro +TCA_CTRL__RB_STILL_4_PHASE_MASK = 0x00000010 # macro +TCA_CTRL__RB_AS_TCI_MASK = 0x00000020 # macro +TCA_CTRL__DISABLE_UTCL2_PRIORITY_MASK = 0x00000040 # macro +TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER_MASK = 0x00000080 # macro +TCA_CTRL__TCA_TCC_FGCG_DISABLE_MASK = 0x00000100 # macro +TCA_CTRL__TCA_TCA_FGCG_DISABLE_MASK = 0x00000200 # macro +TCA_CTRL__TCA_TCH_FGCG_DISABLE_MASK = 0x00000400 # macro +TCA_CTRL__TCA_TCX_FGCG_DISABLE_MASK = 0x00000800 # macro +TCA_CTRL__TCA_RANDOM_REVERSE_PRIORITY_ENABLE_MASK = 0x00001000 # macro +TCA_CTRL__RTN_CREDIT_THRESHOLD_MASK = 0x0000E000 # macro +TCA_CTRL__ACK_CREDIT_THRESHOLD_MASK = 0x00070000 # macro +TCA_CTRL__RTN_ARB_MODE_MASK = 0x00080000 # macro +TCA_CTRL__HOLE_ARB_SHARE_THRESHOLD_MASK = 0x07000000 # macro +TCA_CTRL__HOLE_ARB_LANE_THRESHOLD_MASK = 0x70000000 # macro +TCA_BURST_MASK__ADDR_MASK__SHIFT = 0x0 # macro +TCA_BURST_MASK__ADDR_MASK_MASK = 0xFFFFFFFF # macro +TCA_BURST_CTRL__MAX_BURST__SHIFT = 0x0 # macro +TCA_BURST_CTRL__TCP_DISABLE__SHIFT = 0x4 # macro +TCA_BURST_CTRL__SQC_DISABLE__SHIFT = 0x5 # macro +TCA_BURST_CTRL__CPF_DISABLE__SHIFT = 0x6 # macro +TCA_BURST_CTRL__CPG_DISABLE__SHIFT = 0x7 # macro +TCA_BURST_CTRL__SQG_DISABLE__SHIFT = 0xa # macro +TCA_BURST_CTRL__UTCL2_DISABLE__SHIFT = 0xb # macro +TCA_BURST_CTRL__TPI_DISABLE__SHIFT = 0xc # macro +TCA_BURST_CTRL__RLC_DISABLE__SHIFT = 0xd # macro +TCA_BURST_CTRL__MAX_BURST_MASK = 0x00000007 # macro +TCA_BURST_CTRL__TCP_DISABLE_MASK = 0x00000010 # macro +TCA_BURST_CTRL__SQC_DISABLE_MASK = 0x00000020 # macro +TCA_BURST_CTRL__CPF_DISABLE_MASK = 0x00000040 # macro +TCA_BURST_CTRL__CPG_DISABLE_MASK = 0x00000080 # macro +TCA_BURST_CTRL__SQG_DISABLE_MASK = 0x00000400 # macro +TCA_BURST_CTRL__UTCL2_DISABLE_MASK = 0x00000800 # macro +TCA_BURST_CTRL__TPI_DISABLE_MASK = 0x00001000 # macro +TCA_BURST_CTRL__RLC_DISABLE_MASK = 0x00002000 # macro +TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT = 0x0 # macro +TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT = 0x2 # macro +TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT = 0x3 # macro +TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT = 0x5 # macro +TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL_MASK = 0x00000003 # macro +TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK = 0x00000004 # macro +TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL_MASK = 0x00000018 # macro +TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK = 0x00000020 # macro +TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +TCA_DSM_CNTL2__INJECT_DELAY__SHIFT = 0x1a # macro +TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +TCA_DSM_CNTL2__INJECT_DELAY_MASK = 0xFC000000 # macro +TCX_CTRL__TCX_TCX_FGCG_DISABLE__SHIFT = 0x0 # macro +TCX_CTRL__TCX_TCR_FGCG_DISABLE__SHIFT = 0x1 # macro +TCX_CTRL__TCX_TCC_FGCG_DISABLE__SHIFT = 0x2 # macro +TCX_CTRL__TCX_TCX_FGCG_DISABLE_MASK = 0x00000001 # macro +TCX_CTRL__TCX_TCR_FGCG_DISABLE_MASK = 0x00000002 # macro +TCX_CTRL__TCX_TCC_FGCG_DISABLE_MASK = 0x00000004 # macro +TCX_DSM_CNTL__GROUP0_SED_IRRITATOR_DATA_SEL__SHIFT = 0x0 # macro +TCX_DSM_CNTL__GROUP1_SED_IRRITATOR_DATA_SEL__SHIFT = 0x2 # macro +TCX_DSM_CNTL__GROUP2_SED_IRRITATOR_DATA_SEL__SHIFT = 0x4 # macro +TCX_DSM_CNTL__GROUP4_SED_IRRITATOR_DATA_SEL__SHIFT = 0x8 # macro +TCX_DSM_CNTL__GROUP5_SED_IRRITATOR_DATA_SEL__SHIFT = 0xa # macro +TCX_DSM_CNTL__GROUP6_SED_IRRITATOR_DATA_SEL__SHIFT = 0xc # macro +TCX_DSM_CNTL__GROUP8_SED_IRRITATOR_DATA_SEL__SHIFT = 0x10 # macro +TCX_DSM_CNTL__GROUP9_SED_IRRITATOR_DATA_SEL__SHIFT = 0x12 # macro +TCX_DSM_CNTL__GROUP10_SED_IRRITATOR_DATA_SEL__SHIFT = 0x14 # macro +TCX_DSM_CNTL__GROUP13_SED_IRRITATOR_DATA_SEL__SHIFT = 0x1a # macro +TCX_DSM_CNTL__GROUP14_SED_IRRITATOR_DATA_SEL__SHIFT = 0x1c # macro +TCX_DSM_CNTL__SED_IRRITATOR_SINGLE_WRITE__SHIFT = 0x1e # macro +TCX_DSM_CNTL__GROUP0_SED_IRRITATOR_DATA_SEL_MASK = 0x00000003 # macro +TCX_DSM_CNTL__GROUP1_SED_IRRITATOR_DATA_SEL_MASK = 0x0000000C # macro +TCX_DSM_CNTL__GROUP2_SED_IRRITATOR_DATA_SEL_MASK = 0x00000030 # macro +TCX_DSM_CNTL__GROUP4_SED_IRRITATOR_DATA_SEL_MASK = 0x00000300 # macro +TCX_DSM_CNTL__GROUP5_SED_IRRITATOR_DATA_SEL_MASK = 0x00000C00 # macro +TCX_DSM_CNTL__GROUP6_SED_IRRITATOR_DATA_SEL_MASK = 0x00003000 # macro +TCX_DSM_CNTL__GROUP8_SED_IRRITATOR_DATA_SEL_MASK = 0x00030000 # macro +TCX_DSM_CNTL__GROUP9_SED_IRRITATOR_DATA_SEL_MASK = 0x000C0000 # macro +TCX_DSM_CNTL__GROUP10_SED_IRRITATOR_DATA_SEL_MASK = 0x00300000 # macro +TCX_DSM_CNTL__GROUP13_SED_IRRITATOR_DATA_SEL_MASK = 0x0C000000 # macro +TCX_DSM_CNTL__GROUP14_SED_IRRITATOR_DATA_SEL_MASK = 0x30000000 # macro +TCX_DSM_CNTL__SED_IRRITATOR_SINGLE_WRITE_MASK = 0x40000000 # macro +TCX_DSM_CNTL2__SED_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +TCX_DSM_CNTL2__SED_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +TCX_DSM_CNTL2__INJECT_DELAY__SHIFT = 0x1a # macro +TCX_DSM_CNTL2__SED_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +TCX_DSM_CNTL2__SED_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +TCX_DSM_CNTL2__INJECT_DELAY_MASK = 0xFC000000 # macro +TCA_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +TCA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +TCA_UE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +TCA_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +TCA_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +TCA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +TCA_UE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +TCA_UE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +TCA_UE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +TCA_UE_ERR_STATUS_HI__PARITY__SHIFT = 0x1 # macro +TCA_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +TCA_UE_ERR_STATUS_HI__ERROR_INFO__SHIFT = 0x3 # macro +TCA_UE_ERR_STATUS_HI__UE_CNT__SHIFT = 0x17 # macro +TCA_UE_ERR_STATUS_HI__FED_CNT__SHIFT = 0x1a # macro +TCA_UE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +TCA_UE_ERR_STATUS_HI__PARITY_MASK = 0x00000002 # macro +TCA_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +TCA_UE_ERR_STATUS_HI__ERROR_INFO_MASK = 0x007FFFF8 # macro +TCA_UE_ERR_STATUS_HI__UE_CNT_MASK = 0x03800000 # macro +TCA_UE_ERR_STATUS_HI__FED_CNT_MASK = 0x1C000000 # macro +TCX_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +TCX_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +TCX_UE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +TCX_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +TCX_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +TCX_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +TCX_UE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +TCX_UE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +TCX_UE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +TCX_UE_ERR_STATUS_HI__PARITY__SHIFT = 0x1 # macro +TCX_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +TCX_UE_ERR_STATUS_HI__ERROR_INFO__SHIFT = 0x3 # macro +TCX_UE_ERR_STATUS_HI__UE_CNT__SHIFT = 0x17 # macro +TCX_UE_ERR_STATUS_HI__FED_CNT__SHIFT = 0x1a # macro +TCX_UE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +TCX_UE_ERR_STATUS_HI__PARITY_MASK = 0x00000002 # macro +TCX_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +TCX_UE_ERR_STATUS_HI__ERROR_INFO_MASK = 0x007FFFF8 # macro +TCX_UE_ERR_STATUS_HI__UE_CNT_MASK = 0x03800000 # macro +TCX_UE_ERR_STATUS_HI__FED_CNT_MASK = 0x1C000000 # macro +TCX_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +TCX_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +TCX_CE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +TCX_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +TCX_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +TCX_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +TCX_CE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +TCX_CE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +TCX_CE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +TCX_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +TCX_CE_ERR_STATUS_HI__ERROR_INFO__SHIFT = 0x3 # macro +TCX_CE_ERR_STATUS_HI__CE_CNT__SHIFT = 0x17 # macro +TCX_CE_ERR_STATUS_HI__POISON__SHIFT = 0x1a # macro +TCX_CE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +TCX_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +TCX_CE_ERR_STATUS_HI__ERROR_INFO_MASK = 0x007FFFF8 # macro +TCX_CE_ERR_STATUS_HI__CE_CNT_MASK = 0x03800000 # macro +TCX_CE_ERR_STATUS_HI__POISON_MASK = 0x04000000 # macro +TCC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +TCC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +TCC_UE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +TCC_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +TCC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +TCC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +TCC_UE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +TCC_UE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +TCC_UE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +TCC_UE_ERR_STATUS_HI__PARITY__SHIFT = 0x1 # macro +TCC_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +TCC_UE_ERR_STATUS_HI__ERROR_INFO__SHIFT = 0x3 # macro +TCC_UE_ERR_STATUS_HI__UE_CNT__SHIFT = 0x17 # macro +TCC_UE_ERR_STATUS_HI__FED_CNT__SHIFT = 0x1a # macro +TCC_UE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +TCC_UE_ERR_STATUS_HI__PARITY_MASK = 0x00000002 # macro +TCC_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +TCC_UE_ERR_STATUS_HI__ERROR_INFO_MASK = 0x007FFFF8 # macro +TCC_UE_ERR_STATUS_HI__UE_CNT_MASK = 0x03800000 # macro +TCC_UE_ERR_STATUS_HI__FED_CNT_MASK = 0x1C000000 # macro +TCC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +TCC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +TCC_CE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +TCC_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +TCC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +TCC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +TCC_CE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +TCC_CE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +TCC_CE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +TCC_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +TCC_CE_ERR_STATUS_HI__ERROR_INFO__SHIFT = 0x3 # macro +TCC_CE_ERR_STATUS_HI__CE_CNT__SHIFT = 0x17 # macro +TCC_CE_ERR_STATUS_HI__POISON__SHIFT = 0x1a # macro +TCC_CE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +TCC_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +TCC_CE_ERR_STATUS_HI__ERROR_INFO_MASK = 0x007FFFF8 # macro +TCC_CE_ERR_STATUS_HI__CE_CNT_MASK = 0x03800000 # macro +TCC_CE_ERR_STATUS_HI__POISON_MASK = 0x04000000 # macro +SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT = 0x10 # macro +SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT = 0x16 # macro +SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE__SHIFT = 0x1a # macro +SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK = 0x0000FFFF # macro +SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK = 0x003F0000 # macro +SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK = 0x03C00000 # macro +SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE_MASK = 0x3C000000 # macro +SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK = 0xFF # macro +SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT = 0x6 # macro +SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT = 0xa # macro +SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT = 0xc # macro +SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT = 0x14 # macro +SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT = 0x15 # macro +SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT = 0x16 # macro +SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT = 0x17 # macro +SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT = 0x18 # macro +SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT = 0x1c # macro +SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT = 0x1d # macro +SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK = 0x0000003F # macro +SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK = 0x000003C0 # macro +SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK = 0x00000C00 # macro +SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK = 0x000FF000 # macro +SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK = 0x00100000 # macro +SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK = 0x00200000 # macro +SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK = 0x00400000 # macro +SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK = 0x00800000 # macro +SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK = 0x01000000 # macro +SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK = 0x10000000 # macro +SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK = 0x20000000 # macro +SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT = 0x1 # macro +SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT = 0x6 # macro +SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT = 0x7 # macro +SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT = 0x8 # macro +SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT = 0x10 # macro +SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT = 0x19 # macro +SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT = 0x1a # macro +SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0__SHIFT = 0x1b # macro +SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT = 0x1c # macro +SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK = 0x00000001 # macro +SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK = 0x0000003E # macro +SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK = 0x00000040 # macro +SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK = 0x00000080 # macro +SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK = 0x0000FF00 # macro +SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK = 0x01FF0000 # macro +SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK = 0x02000000 # macro +SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK = 0x04000000 # macro +SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0_MASK = 0x08000000 # macro +SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK = 0x10000000 # macro +SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_0__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_1__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_2__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_3__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_4__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_5__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_6__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_7__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_8__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_9__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_10__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_11__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_12__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_13__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_14__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_15__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_16__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_17__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_18__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_19__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_20__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_21__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_22__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_23__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_24__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_25__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_26__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_27__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_28__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_29__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_30__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_PS_31__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT = 0x10 # macro +SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT = 0x16 # macro +SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE__SHIFT = 0x1a # macro +SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK = 0x0000FFFF # macro +SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK = 0x003F0000 # macro +SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK = 0x03C00000 # macro +SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE_MASK = 0x3C000000 # macro +SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT = 0x0 # macro +SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK = 0x0000003F # macro +SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK = 0xFF # macro +SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT = 0x6 # macro +SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT = 0xa # macro +SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT = 0xc # macro +SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT = 0x14 # macro +SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT = 0x15 # macro +SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT = 0x16 # macro +SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT = 0x17 # macro +SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT = 0x18 # macro +SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT = 0x1a # macro +SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT = 0x1e # macro +SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT = 0x1f # macro +SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK = 0x0000003F # macro +SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK = 0x000003C0 # macro +SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK = 0x00000C00 # macro +SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK = 0x000FF000 # macro +SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK = 0x00100000 # macro +SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK = 0x00200000 # macro +SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK = 0x00400000 # macro +SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK = 0x00800000 # macro +SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK = 0x03000000 # macro +SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK = 0x04000000 # macro +SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK = 0x40000000 # macro +SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK = 0x80000000 # macro +SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT = 0x1 # macro +SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT = 0x6 # macro +SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT = 0x7 # macro +SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT = 0x8 # macro +SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT = 0x9 # macro +SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT = 0xa # macro +SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT = 0xb # macro +SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT = 0xc # macro +SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT = 0xd # macro +SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT = 0x16 # macro +SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT = 0x18 # macro +SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0__SHIFT = 0x1b # macro +SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT = 0x1c # macro +SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK = 0x00000001 # macro +SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK = 0x0000003E # macro +SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK = 0x00000040 # macro +SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK = 0x00000080 # macro +SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK = 0x00000100 # macro +SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK = 0x00000200 # macro +SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK = 0x00000400 # macro +SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK = 0x00000800 # macro +SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK = 0x00001000 # macro +SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK = 0x003FE000 # macro +SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK = 0x00400000 # macro +SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK = 0x01000000 # macro +SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0_MASK = 0x08000000 # macro +SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK = 0x10000000 # macro +SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_0__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_1__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_2__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_3__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_4__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_5__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_6__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_7__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_8__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_9__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_10__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_11__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_12__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_13__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_14__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_15__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_16__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_17__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_18__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_19__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_20__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_21__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_22__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_23__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_24__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_25__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_26__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_27__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_28__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_29__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_30__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_VS_31__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT = 0x1 # macro +SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT = 0x6 # macro +SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT = 0x7 # macro +SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT = 0x10 # macro +SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT = 0x12 # macro +SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT = 0x13 # macro +SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT = 0x1b # macro +SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT = 0x1c # macro +SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK = 0x00000001 # macro +SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK = 0x0000003E # macro +SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK = 0x00000040 # macro +SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK = 0x0000FF80 # macro +SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK = 0x00030000 # macro +SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK = 0x00040000 # macro +SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK = 0x07F80000 # macro +SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK = 0x08000000 # macro +SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK = 0x10000000 # macro +SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT = 0x7 # macro +SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH_MASK = 0x0000007F # macro +SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK = 0x00003F80 # macro +SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK = 0xFF # macro +SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT = 0x10 # macro +SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT = 0x16 # macro +SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE__SHIFT = 0x1a # macro +SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK = 0x0000FFFF # macro +SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK = 0x003F0000 # macro +SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK = 0x03C00000 # macro +SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE_MASK = 0x3C000000 # macro +SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK = 0xFF # macro +SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT = 0x6 # macro +SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT = 0xa # macro +SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT = 0xc # macro +SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT = 0x14 # macro +SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT = 0x15 # macro +SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT = 0x16 # macro +SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT = 0x17 # macro +SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT = 0x18 # macro +SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT = 0x1c # macro +SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT = 0x1d # macro +SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT = 0x1f # macro +SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK = 0x0000003F # macro +SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK = 0x000003C0 # macro +SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK = 0x00000C00 # macro +SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK = 0x000FF000 # macro +SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK = 0x00100000 # macro +SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK = 0x00200000 # macro +SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK = 0x00400000 # macro +SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK = 0x00800000 # macro +SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK = 0x01000000 # macro +SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK = 0x10000000 # macro +SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK = 0x60000000 # macro +SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK = 0x80000000 # macro +SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT = 0x1 # macro +SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT = 0x6 # macro +SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT = 0x7 # macro +SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT = 0x10 # macro +SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT = 0x12 # macro +SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT = 0x13 # macro +SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0__SHIFT = 0x1b # macro +SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT = 0x1c # macro +SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK = 0x00000001 # macro +SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK = 0x0000003E # macro +SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK = 0x00000040 # macro +SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK = 0x0000FF80 # macro +SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK = 0x00030000 # macro +SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK = 0x00040000 # macro +SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK = 0x07F80000 # macro +SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0_MASK = 0x08000000 # macro +SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK = 0x10000000 # macro +SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_0__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_1__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_2__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_3__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_4__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_5__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_6__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_7__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_8__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_9__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_10__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_11__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_12__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_13__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_14__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_15__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_16__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_16__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_17__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_17__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_18__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_18__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_19__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_19__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_20__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_20__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_21__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_21__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_22__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_22__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_23__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_23__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_24__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_24__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_25__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_25__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_26__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_26__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_27__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_27__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_28__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_28__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_29__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_29__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_30__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_30__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ES_31__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ES_31__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH_MASK = 0x0000007F # macro +SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK = 0xFF # macro +SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT = 0x6 # macro +SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT = 0xa # macro +SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT = 0x10 # macro +SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK = 0x0000003F # macro +SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK = 0x000003C0 # macro +SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE_MASK = 0x00003C00 # macro +SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK = 0xFFFF0000 # macro +SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK = 0xFFFFFFFF # macro +SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT = 0x0 # macro +SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK = 0xFF # macro +SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT = 0x6 # macro +SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT = 0xa # macro +SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT = 0xc # macro +SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT = 0x14 # macro +SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT = 0x15 # macro +SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT = 0x16 # macro +SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT = 0x17 # macro +SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT = 0x1b # macro +SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT = 0x1c # macro +SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT = 0x1e # macro +SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK = 0x0000003F # macro +SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK = 0x000003C0 # macro +SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK = 0x00000C00 # macro +SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK = 0x000FF000 # macro +SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK = 0x00100000 # macro +SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK = 0x00200000 # macro +SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK = 0x00400000 # macro +SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK = 0x00800000 # macro +SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK = 0x08000000 # macro +SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK = 0x30000000 # macro +SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK = 0x40000000 # macro +SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT = 0x0 # macro +SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT = 0x1 # macro +SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT = 0x6 # macro +SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT = 0x7 # macro +SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT = 0x10 # macro +SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0__SHIFT = 0x1b # macro +SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT = 0x1c # macro +SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK = 0x00000001 # macro +SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK = 0x0000003E # macro +SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK = 0x00000040 # macro +SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK = 0x0000FF80 # macro +SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK = 0x01FF0000 # macro +SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0_MASK = 0x08000000 # macro +SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK = 0x10000000 # macro +SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_0__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_1__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_2__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_3__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_4__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_5__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_6__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_7__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_8__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_9__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_10__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_11__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_12__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_13__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_14__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_15__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_16__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_16__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_17__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_17__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_18__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_18__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_19__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_19__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_20__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_20__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_21__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_21__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_22__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_22__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_23__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_23__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_24__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_24__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_25__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_25__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_26__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_26__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_27__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_27__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_28__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_28__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_29__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_29__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_30__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_30__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_LS_31__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_LS_31__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_0__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_0__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_1__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_1__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_2__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_2__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_3__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_3__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_4__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_4__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_5__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_5__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_6__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_6__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_7__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_7__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_8__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_8__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_9__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_9__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_10__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_10__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_11__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_11__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_12__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_12__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_13__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_13__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_14__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_14__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_15__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_15__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_16__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_16__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_17__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_17__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_18__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_18__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_19__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_19__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_20__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_20__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_21__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_21__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_22__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_22__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_23__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_23__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_24__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_24__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_25__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_25__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_26__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_26__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_27__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_27__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_28__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_28__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_29__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_29__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_30__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_30__DATA_MASK = 0xFFFFFFFF # macro +SPI_SHADER_USER_DATA_COMMON_31__DATA__SHIFT = 0x0 # macro +SPI_SHADER_USER_DATA_COMMON_31__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT = 0x0 # macro +COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT = 0x1 # macro +COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT = 0x2 # macro +COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT = 0x3 # macro +COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT = 0x4 # macro +COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT = 0x5 # macro +COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT = 0x6 # macro +COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT = 0xa # macro +COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT = 0xb # macro +COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT = 0xc # macro +COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT = 0xe # macro +COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK = 0x00000001 # macro +COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK = 0x00000002 # macro +COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK = 0x00000004 # macro +COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK = 0x00000008 # macro +COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK = 0x00000010 # macro +COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK = 0x00000020 # macro +COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK = 0x00000040 # macro +COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK = 0x00000400 # macro +COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK = 0x00000800 # macro +COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK = 0x00001000 # macro +COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK = 0x00004000 # macro +COMPUTE_DIM_X__SIZE__SHIFT = 0x0 # macro +COMPUTE_DIM_X__SIZE_MASK = 0xFFFFFFFF # macro +COMPUTE_DIM_Y__SIZE__SHIFT = 0x0 # macro +COMPUTE_DIM_Y__SIZE_MASK = 0xFFFFFFFF # macro +COMPUTE_DIM_Z__SIZE__SHIFT = 0x0 # macro +COMPUTE_DIM_Z__SIZE_MASK = 0xFFFFFFFF # macro +COMPUTE_START_X__START__SHIFT = 0x0 # macro +COMPUTE_START_X__START_MASK = 0xFFFFFFFF # macro +COMPUTE_START_Y__START__SHIFT = 0x0 # macro +COMPUTE_START_Y__START_MASK = 0xFFFFFFFF # macro +COMPUTE_START_Z__START__SHIFT = 0x0 # macro +COMPUTE_START_Z__START_MASK = 0xFFFFFFFF # macro +COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT = 0x0 # macro +COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT = 0x10 # macro +COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK = 0x0000FFFF # macro +COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK = 0xFFFF0000 # macro +COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT = 0x0 # macro +COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT = 0x10 # macro +COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK = 0x0000FFFF # macro +COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK = 0xFFFF0000 # macro +COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT = 0x0 # macro +COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT = 0x10 # macro +COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK = 0x0000FFFF # macro +COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK = 0xFFFF0000 # macro +COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT = 0x0 # macro +COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK = 0x00000001 # macro +COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT = 0x0 # macro +COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK = 0x00000001 # macro +COMPUTE_PGM_LO__DATA__SHIFT = 0x0 # macro +COMPUTE_PGM_LO__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_PGM_HI__DATA__SHIFT = 0x0 # macro +COMPUTE_PGM_HI__DATA_MASK = 0x000000FF # macro +COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT = 0x0 # macro +COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT = 0x0 # macro +COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK = 0x000000FF # macro +COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT = 0x0 # macro +COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT = 0x0 # macro +COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK = 0x000000FF # macro +COMPUTE_PGM_RSRC1__VGPRS__SHIFT = 0x0 # macro +COMPUTE_PGM_RSRC1__SGPRS__SHIFT = 0x6 # macro +COMPUTE_PGM_RSRC1__PRIORITY__SHIFT = 0xa # macro +COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT = 0xc # macro +COMPUTE_PGM_RSRC1__PRIV__SHIFT = 0x14 # macro +COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT = 0x15 # macro +COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT = 0x16 # macro +COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT = 0x17 # macro +COMPUTE_PGM_RSRC1__BULKY__SHIFT = 0x18 # macro +COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT = 0x19 # macro +COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT = 0x1a # macro +COMPUTE_PGM_RSRC1__VGPRS_MASK = 0x0000003F # macro +COMPUTE_PGM_RSRC1__SGPRS_MASK = 0x000003C0 # macro +COMPUTE_PGM_RSRC1__PRIORITY_MASK = 0x00000C00 # macro +COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK = 0x000FF000 # macro +COMPUTE_PGM_RSRC1__PRIV_MASK = 0x00100000 # macro +COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK = 0x00200000 # macro +COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK = 0x00400000 # macro +COMPUTE_PGM_RSRC1__IEEE_MODE_MASK = 0x00800000 # macro +COMPUTE_PGM_RSRC1__BULKY_MASK = 0x01000000 # macro +COMPUTE_PGM_RSRC1__CDBG_USER_MASK = 0x02000000 # macro +COMPUTE_PGM_RSRC1__FP16_OVFL_MASK = 0x04000000 # macro +COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT = 0x0 # macro +COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT = 0x1 # macro +COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT = 0x6 # macro +COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT = 0x7 # macro +COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT = 0x8 # macro +COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT = 0x9 # macro +COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT = 0xa # macro +COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT = 0xb # macro +COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT = 0xd # macro +COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT = 0xf # macro +COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT = 0x18 # macro +COMPUTE_PGM_RSRC2__SKIP_USGPR0__SHIFT = 0x1f # macro +COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK = 0x00000001 # macro +COMPUTE_PGM_RSRC2__USER_SGPR_MASK = 0x0000003E # macro +COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK = 0x00000040 # macro +COMPUTE_PGM_RSRC2__TGID_X_EN_MASK = 0x00000080 # macro +COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK = 0x00000100 # macro +COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK = 0x00000200 # macro +COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK = 0x00000400 # macro +COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK = 0x00001800 # macro +COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK = 0x00006000 # macro +COMPUTE_PGM_RSRC2__LDS_SIZE_MASK = 0x00FF8000 # macro +COMPUTE_PGM_RSRC2__EXCP_EN_MASK = 0x7F000000 # macro +COMPUTE_PGM_RSRC2__SKIP_USGPR0_MASK = 0x80000000 # macro +COMPUTE_VMID__DATA__SHIFT = 0x0 # macro +COMPUTE_VMID__DATA_MASK = 0x0000000F # macro +COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT = 0x0 # macro +COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT = 0xc # macro +COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT = 0x10 # macro +COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT = 0x16 # macro +COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT = 0x17 # macro +COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT = 0x18 # macro +COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE__SHIFT = 0x1b # macro +COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK = 0x000003FF # macro +COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK = 0x0000F000 # macro +COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK = 0x003F0000 # macro +COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK = 0x00400000 # macro +COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK = 0x00800000 # macro +COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK = 0x07000000 # macro +COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE_MASK = 0x78000000 # macro +COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT = 0x0 # macro +COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT = 0x10 # macro +COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK = 0x0000FFFF # macro +COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK = 0xFFFF0000 # macro +COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT = 0x0 # macro +COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT = 0x10 # macro +COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK = 0x0000FFFF # macro +COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK = 0xFFFF0000 # macro +COMPUTE_TMPRING_SIZE__WAVES__SHIFT = 0x0 # macro +COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT = 0xc # macro +COMPUTE_TMPRING_SIZE__WAVES_MASK = 0x00000FFF # macro +COMPUTE_TMPRING_SIZE__WAVESIZE_MASK = 0x01FFF000 # macro +COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT = 0x0 # macro +COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT = 0x10 # macro +COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK = 0x0000FFFF # macro +COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK = 0xFFFF0000 # macro +COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT = 0x0 # macro +COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT = 0x10 # macro +COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK = 0x0000FFFF # macro +COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK = 0xFFFF0000 # macro +COMPUTE_RESTART_X__RESTART__SHIFT = 0x0 # macro +COMPUTE_RESTART_X__RESTART_MASK = 0xFFFFFFFF # macro +COMPUTE_RESTART_Y__RESTART__SHIFT = 0x0 # macro +COMPUTE_RESTART_Y__RESTART_MASK = 0xFFFFFFFF # macro +COMPUTE_RESTART_Z__RESTART__SHIFT = 0x0 # macro +COMPUTE_RESTART_Z__RESTART_MASK = 0xFFFFFFFF # macro +COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT = 0x0 # macro +COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK = 0x00000001 # macro +COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT = 0x0 # macro +COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT = 0x5 # macro +COMPUTE_MISC_RESERVED__SEND_SEID_MASK = 0x00000003 # macro +COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK = 0x0001FFE0 # macro +COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT = 0x0 # macro +COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK = 0xFFFFFFFF # macro +COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT = 0x0 # macro +COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK = 0xFFFFFFFF # macro +COMPUTE_RELAUNCH__PAYLOAD__SHIFT = 0x0 # macro +COMPUTE_RELAUNCH__IS_EVENT__SHIFT = 0x1e # macro +COMPUTE_RELAUNCH__IS_STATE__SHIFT = 0x1f # macro +COMPUTE_RELAUNCH__PAYLOAD_MASK = 0x3FFFFFFF # macro +COMPUTE_RELAUNCH__IS_EVENT_MASK = 0x40000000 # macro +COMPUTE_RELAUNCH__IS_STATE_MASK = 0x80000000 # macro +COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT = 0x0 # macro +COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK = 0xFFFFFFFF # macro +COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT = 0x0 # macro +COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK = 0xFFFF # macro +COMPUTE_TG_CHUNK_SIZE__TG_CHUNK_SIZE__SHIFT = 0x0 # macro +COMPUTE_TG_CHUNK_SIZE__TG_CHUNK_SIZE_MASK = 0x0000FFFF # macro +COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT = 0x0 # macro +COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK = 0xFFFFFFFF # macro +COMPUTE_PGM_RSRC3__ACCUM_OFFSET__SHIFT = 0x0 # macro +COMPUTE_PGM_RSRC3__TRAP_ON_START__SHIFT = 0xa # macro +COMPUTE_PGM_RSRC3__TRAP_ON_END__SHIFT = 0xb # macro +COMPUTE_PGM_RSRC3__TG_SPLIT__SHIFT = 0x10 # macro +COMPUTE_PGM_RSRC3__ACCUM_OFFSET_MASK = 0x0000003F # macro +COMPUTE_PGM_RSRC3__TRAP_ON_START_MASK = 0x00000400 # macro +COMPUTE_PGM_RSRC3__TRAP_ON_END_MASK = 0x00000800 # macro +COMPUTE_PGM_RSRC3__TG_SPLIT_MASK = 0x00010000 # macro +COMPUTE_USER_DATA_0__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_0__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_1__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_1__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_2__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_2__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_3__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_3__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_4__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_4__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_5__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_5__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_6__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_6__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_7__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_7__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_8__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_8__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_9__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_9__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_10__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_10__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_11__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_11__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_12__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_12__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_13__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_13__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_14__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_14__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_USER_DATA_15__DATA__SHIFT = 0x0 # macro +COMPUTE_USER_DATA_15__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_DISPATCH_END__DATA__SHIFT = 0x0 # macro +COMPUTE_DISPATCH_END__DATA_MASK = 0xFFFFFFFF # macro +COMPUTE_NOWHERE__DATA__SHIFT = 0x0 # macro +COMPUTE_NOWHERE__DATA_MASK = 0xFFFFFFFF # macro +CP_DFY_CNTL__POLICY__SHIFT = 0x0 # macro +CP_DFY_CNTL__MTYPE__SHIFT = 0x2 # macro +CP_DFY_CNTL__WRITE_DIS__SHIFT = 0x1b # macro +CP_DFY_CNTL__LFSR_RESET__SHIFT = 0x1c # macro +CP_DFY_CNTL__MODE__SHIFT = 0x1d # macro +CP_DFY_CNTL__ENABLE__SHIFT = 0x1f # macro +CP_DFY_CNTL__POLICY_MASK = 0x00000001 # macro +CP_DFY_CNTL__MTYPE_MASK = 0x0000000C # macro +CP_DFY_CNTL__WRITE_DIS_MASK = 0x08000000 # macro +CP_DFY_CNTL__LFSR_RESET_MASK = 0x10000000 # macro +CP_DFY_CNTL__MODE_MASK = 0x60000000 # macro +CP_DFY_CNTL__ENABLE_MASK = 0x80000000 # macro +CP_DFY_STAT__BURST_COUNT__SHIFT = 0x0 # macro +CP_DFY_STAT__TAGS_PENDING__SHIFT = 0x10 # macro +CP_DFY_STAT__BUSY__SHIFT = 0x1f # macro +CP_DFY_STAT__BURST_COUNT_MASK = 0x0000FFFF # macro +CP_DFY_STAT__TAGS_PENDING_MASK = 0x07FF0000 # macro +CP_DFY_STAT__BUSY_MASK = 0x80000000 # macro +CP_DFY_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_DFY_ADDR_HI__ADDR_HI_MASK = 0xFFFFFFFF # macro +CP_DFY_ADDR_LO__ADDR_LO__SHIFT = 0x5 # macro +CP_DFY_ADDR_LO__ADDR_LO_MASK = 0xFFFFFFE0 # macro +CP_DFY_DATA_0__DATA__SHIFT = 0x0 # macro +CP_DFY_DATA_0__DATA_MASK = 0xFFFFFFFF # macro +CP_DFY_DATA_1__DATA__SHIFT = 0x0 # macro +CP_DFY_DATA_1__DATA_MASK = 0xFFFFFFFF # macro +CP_DFY_DATA_2__DATA__SHIFT = 0x0 # macro +CP_DFY_DATA_2__DATA_MASK = 0xFFFFFFFF # macro +CP_DFY_DATA_3__DATA__SHIFT = 0x0 # macro +CP_DFY_DATA_3__DATA_MASK = 0xFFFFFFFF # macro +CP_DFY_DATA_4__DATA__SHIFT = 0x0 # macro +CP_DFY_DATA_4__DATA_MASK = 0xFFFFFFFF # macro +CP_DFY_DATA_5__DATA__SHIFT = 0x0 # macro +CP_DFY_DATA_5__DATA_MASK = 0xFFFFFFFF # macro +CP_DFY_DATA_6__DATA__SHIFT = 0x0 # macro +CP_DFY_DATA_6__DATA_MASK = 0xFFFFFFFF # macro +CP_DFY_DATA_7__DATA__SHIFT = 0x0 # macro +CP_DFY_DATA_7__DATA_MASK = 0xFFFFFFFF # macro +CP_DFY_DATA_8__DATA__SHIFT = 0x0 # macro +CP_DFY_DATA_8__DATA_MASK = 0xFFFFFFFF # macro +CP_DFY_DATA_9__DATA__SHIFT = 0x0 # macro +CP_DFY_DATA_9__DATA_MASK = 0xFFFFFFFF # macro +CP_DFY_DATA_10__DATA__SHIFT = 0x0 # macro +CP_DFY_DATA_10__DATA_MASK = 0xFFFFFFFF # macro +CP_DFY_DATA_11__DATA__SHIFT = 0x0 # macro +CP_DFY_DATA_11__DATA_MASK = 0xFFFFFFFF # macro +CP_DFY_DATA_12__DATA__SHIFT = 0x0 # macro +CP_DFY_DATA_12__DATA_MASK = 0xFFFFFFFF # macro +CP_DFY_DATA_13__DATA__SHIFT = 0x0 # macro +CP_DFY_DATA_13__DATA_MASK = 0xFFFFFFFF # macro +CP_DFY_DATA_14__DATA__SHIFT = 0x0 # macro +CP_DFY_DATA_14__DATA_MASK = 0xFFFFFFFF # macro +CP_DFY_DATA_15__DATA__SHIFT = 0x0 # macro +CP_DFY_DATA_15__DATA_MASK = 0xFFFFFFFF # macro +CP_DFY_CMD__OFFSET__SHIFT = 0x0 # macro +CP_DFY_CMD__SIZE__SHIFT = 0x10 # macro +CP_DFY_CMD__OFFSET_MASK = 0x000001FF # macro +CP_DFY_CMD__SIZE_MASK = 0xFFFF0000 # macro +CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT = 0x0 # macro +CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT = 0xa # macro +CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK = 0x000003FF # macro +CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK = 0x0003FC00 # macro +CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT = 0x0 # macro +CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT = 0x8 # macro +CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK = 0x000000FF # macro +CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK = 0x0000FF00 # macro +CPC_INT_INFO__ADDR_HI__SHIFT = 0x0 # macro +CPC_INT_INFO__TYPE__SHIFT = 0x10 # macro +CPC_INT_INFO__VMID__SHIFT = 0x14 # macro +CPC_INT_INFO__QUEUE_ID__SHIFT = 0x1c # macro +CPC_INT_INFO__ADDR_HI_MASK = 0x0000FFFF # macro +CPC_INT_INFO__TYPE_MASK = 0x00010000 # macro +CPC_INT_INFO__VMID_MASK = 0x00F00000 # macro +CPC_INT_INFO__QUEUE_ID_MASK = 0x70000000 # macro +CP_VIRT_STATUS__VIRT_STATUS__SHIFT = 0x0 # macro +CP_VIRT_STATUS__VIRT_STATUS_MASK = 0xFFFFFFFF # macro +CPC_INT_ADDR__ADDR__SHIFT = 0x0 # macro +CPC_INT_ADDR__ADDR_MASK = 0xFFFFFFFF # macro +CPC_INT_PASID__PASID__SHIFT = 0x0 # macro +CPC_INT_PASID__PASID_MASK = 0x0000FFFF # macro +CP_GFX_ERROR__EDC_ERROR_ID__SHIFT = 0x0 # macro +CP_GFX_ERROR__SUA_ERROR__SHIFT = 0x4 # macro +CP_GFX_ERROR__RSVD1_ERROR__SHIFT = 0x5 # macro +CP_GFX_ERROR__RSVD2_ERROR__SHIFT = 0x6 # macro +CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT = 0x7 # macro +CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT = 0x8 # macro +CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT = 0x9 # macro +CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT = 0xa # macro +CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT = 0xb # macro +CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT = 0xc # macro +CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT = 0xd # macro +CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT = 0xe # macro +CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT = 0xf # macro +CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT = 0x10 # macro +CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT = 0x11 # macro +CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT = 0x12 # macro +CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT = 0x13 # macro +CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT = 0x14 # macro +CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT = 0x15 # macro +CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT = 0x16 # macro +CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT = 0x17 # macro +CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT = 0x18 # macro +CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT = 0x19 # macro +CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT = 0x1a # macro +CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT = 0x1b # macro +CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT = 0x1c # macro +CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT = 0x1d # macro +CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT = 0x1e # macro +CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT = 0x1f # macro +CP_GFX_ERROR__EDC_ERROR_ID_MASK = 0x0000000F # macro +CP_GFX_ERROR__SUA_ERROR_MASK = 0x00000010 # macro +CP_GFX_ERROR__RSVD1_ERROR_MASK = 0x00000020 # macro +CP_GFX_ERROR__RSVD2_ERROR_MASK = 0x00000040 # macro +CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK = 0x00000080 # macro +CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK = 0x00000100 # macro +CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK = 0x00000200 # macro +CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK = 0x00000400 # macro +CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK = 0x00000800 # macro +CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK = 0x00001000 # macro +CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK = 0x00002000 # macro +CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK = 0x00004000 # macro +CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK = 0x00008000 # macro +CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK = 0x00010000 # macro +CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK = 0x00020000 # macro +CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK = 0x00040000 # macro +CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK = 0x00080000 # macro +CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK = 0x00100000 # macro +CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK = 0x00200000 # macro +CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK = 0x00400000 # macro +CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK = 0x00800000 # macro +CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK = 0x01000000 # macro +CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK = 0x02000000 # macro +CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK = 0x04000000 # macro +CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK = 0x08000000 # macro +CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK = 0x10000000 # macro +CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK = 0x20000000 # macro +CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK = 0x40000000 # macro +CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK = 0x80000000 # macro +CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT = 0x0 # macro +CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT = 0x17 # macro +CPG_UTCL1_CNTL__DROP_MODE__SHIFT = 0x18 # macro +CPG_UTCL1_CNTL__INVALIDATE__SHIFT = 0x1a # macro +CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT = 0x1b # macro +CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT = 0x1c # macro +CPG_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT = 0x1d # macro +CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT = 0x1e # macro +CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK = 0x000FFFFF # macro +CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK = 0x00800000 # macro +CPG_UTCL1_CNTL__DROP_MODE_MASK = 0x01000000 # macro +CPG_UTCL1_CNTL__INVALIDATE_MASK = 0x04000000 # macro +CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK = 0x08000000 # macro +CPG_UTCL1_CNTL__FORCE_SNOOP_MASK = 0x10000000 # macro +CPG_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK = 0x20000000 # macro +CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK = 0x40000000 # macro +CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT = 0x0 # macro +CPC_UTCL1_CNTL__DROP_MODE__SHIFT = 0x18 # macro +CPC_UTCL1_CNTL__INVALIDATE__SHIFT = 0x1a # macro +CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT = 0x1b # macro +CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT = 0x1c # macro +CPC_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT = 0x1d # macro +CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT = 0x1e # macro +CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK = 0x000FFFFF # macro +CPC_UTCL1_CNTL__DROP_MODE_MASK = 0x01000000 # macro +CPC_UTCL1_CNTL__INVALIDATE_MASK = 0x04000000 # macro +CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK = 0x08000000 # macro +CPC_UTCL1_CNTL__FORCE_SNOOP_MASK = 0x10000000 # macro +CPC_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK = 0x20000000 # macro +CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK = 0x40000000 # macro +CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT = 0x0 # macro +CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT = 0x17 # macro +CPF_UTCL1_CNTL__DROP_MODE__SHIFT = 0x18 # macro +CPF_UTCL1_CNTL__INVALIDATE__SHIFT = 0x1a # macro +CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT = 0x1b # macro +CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT = 0x1c # macro +CPF_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT = 0x1d # macro +CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT = 0x1e # macro +CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT = 0x1f # macro +CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK = 0x000FFFFF # macro +CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK = 0x00800000 # macro +CPF_UTCL1_CNTL__DROP_MODE_MASK = 0x01000000 # macro +CPF_UTCL1_CNTL__INVALIDATE_MASK = 0x04000000 # macro +CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK = 0x08000000 # macro +CPF_UTCL1_CNTL__FORCE_SNOOP_MASK = 0x10000000 # macro +CPF_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK = 0x20000000 # macro +CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK = 0x40000000 # macro +CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK = 0x80000000 # macro +CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT = 0x0 # macro +CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK = 0xFFFFFFFF # macro +CP_RB0_BASE__RB_BASE__SHIFT = 0x0 # macro +CP_RB0_BASE__RB_BASE_MASK = 0xFFFFFFFF # macro +CP_RB_BASE__RB_BASE__SHIFT = 0x0 # macro +CP_RB_BASE__RB_BASE_MASK = 0xFFFFFFFF # macro +CP_RB0_CNTL__RB_BUFSZ__SHIFT = 0x0 # macro +CP_RB0_CNTL__RB_BLKSZ__SHIFT = 0x8 # macro +CP_RB0_CNTL__BUF_SWAP__SHIFT = 0x11 # macro +CP_RB0_CNTL__MIN_AVAILSZ__SHIFT = 0x14 # macro +CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT = 0x16 # macro +CP_RB0_CNTL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_RB0_CNTL__RB_NO_UPDATE__SHIFT = 0x1b # macro +CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT = 0x1f # macro +CP_RB0_CNTL__RB_BUFSZ_MASK = 0x0000003F # macro +CP_RB0_CNTL__RB_BLKSZ_MASK = 0x00003F00 # macro +CP_RB0_CNTL__BUF_SWAP_MASK = 0x00060000 # macro +CP_RB0_CNTL__MIN_AVAILSZ_MASK = 0x00300000 # macro +CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK = 0x00C00000 # macro +CP_RB0_CNTL__CACHE_POLICY_MASK = 0x01000000 # macro +CP_RB0_CNTL__RB_NO_UPDATE_MASK = 0x08000000 # macro +CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK = 0x80000000 # macro +CP_RB_CNTL__RB_BUFSZ__SHIFT = 0x0 # macro +CP_RB_CNTL__RB_BLKSZ__SHIFT = 0x8 # macro +CP_RB_CNTL__MIN_AVAILSZ__SHIFT = 0x14 # macro +CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT = 0x16 # macro +CP_RB_CNTL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_RB_CNTL__RB_NO_UPDATE__SHIFT = 0x1b # macro +CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT = 0x1f # macro +CP_RB_CNTL__RB_BUFSZ_MASK = 0x0000003F # macro +CP_RB_CNTL__RB_BLKSZ_MASK = 0x00003F00 # macro +CP_RB_CNTL__MIN_AVAILSZ_MASK = 0x00300000 # macro +CP_RB_CNTL__MIN_IB_AVAILSZ_MASK = 0x00C00000 # macro +CP_RB_CNTL__CACHE_POLICY_MASK = 0x01000000 # macro +CP_RB_CNTL__RB_NO_UPDATE_MASK = 0x08000000 # macro +CP_RB_CNTL__RB_RPTR_WR_ENA_MASK = 0x80000000 # macro +CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT = 0x0 # macro +CP_RB_RPTR_WR__RB_RPTR_WR_MASK = 0x000FFFFF # macro +CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT = 0x2 # macro +CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK = 0xFFFFFFFC # macro +CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT = 0x2 # macro +CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK = 0xFFFFFFFC # macro +CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT = 0x0 # macro +CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK = 0x0000FFFF # macro +CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT = 0x0 # macro +CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK = 0x0000FFFF # macro +CP_RB0_BUFSZ_MASK__DATA__SHIFT = 0x0 # macro +CP_RB0_BUFSZ_MASK__DATA_MASK = 0x000FFFFF # macro +CP_RB_BUFSZ_MASK__DATA__SHIFT = 0x0 # macro +CP_RB_BUFSZ_MASK__DATA_MASK = 0x000FFFFF # macro +CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT = 0x2 # macro +CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK = 0xFFFFFFFC # macro +CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT = 0x0 # macro +CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK = 0x0000FFFF # macro +GC_PRIV_MODE__MC_PRIV_MODE__SHIFT = 0x0 # macro +GC_PRIV_MODE__MC_PRIV_MODE_MASK = 0x00000001 # macro +CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT = 0xb # macro +CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_INT_CNTL__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT = 0x12 # macro +CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT = 0x13 # macro +CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT = 0x14 # macro +CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT = 0x15 # macro +CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT = 0x16 # macro +CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK = 0x00000800 # macro +CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_INT_CNTL__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK = 0x00040000 # macro +CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK = 0x00080000 # macro +CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK = 0x00100000 # macro +CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK = 0x00200000 # macro +CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK = 0x00400000 # macro +CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT = 0xb # macro +CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT = 0xe # macro +CP_INT_STATUS__GPF_INT_STAT__SHIFT = 0x10 # macro +CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT = 0x11 # macro +CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT = 0x12 # macro +CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT = 0x13 # macro +CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT = 0x14 # macro +CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT = 0x15 # macro +CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT = 0x16 # macro +CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT = 0x17 # macro +CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT = 0x18 # macro +CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT = 0x1a # macro +CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT = 0x1b # macro +CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT = 0x1d # macro +CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT = 0x1e # macro +CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT = 0x1f # macro +CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK = 0x00000800 # macro +CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK = 0x00004000 # macro +CP_INT_STATUS__GPF_INT_STAT_MASK = 0x00010000 # macro +CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK = 0x00020000 # macro +CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK = 0x00040000 # macro +CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK = 0x00080000 # macro +CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK = 0x00100000 # macro +CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK = 0x00200000 # macro +CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK = 0x00400000 # macro +CP_INT_STATUS__PRIV_REG_INT_STAT_MASK = 0x00800000 # macro +CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK = 0x01000000 # macro +CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK = 0x04000000 # macro +CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK = 0x08000000 # macro +CP_INT_STATUS__GENERIC2_INT_STAT_MASK = 0x20000000 # macro +CP_INT_STATUS__GENERIC1_INT_STAT_MASK = 0x40000000 # macro +CP_INT_STATUS__GENERIC0_INT_STAT_MASK = 0x80000000 # macro +CP_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +CP_DEVICE_ID__DEVICE_ID_MASK = 0x000000FF # macro +CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT = 0x0 # macro +CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT = 0x8 # macro +CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT = 0x10 # macro +CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT = 0x18 # macro +CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK = 0x000000FF # macro +CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK = 0x0000FF00 # macro +CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK = 0x00FF0000 # macro +CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK = 0xFF000000 # macro +CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT = 0x0 # macro +CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT = 0x8 # macro +CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT = 0x10 # macro +CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT = 0x18 # macro +CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK = 0x000000FF # macro +CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK = 0x0000FF00 # macro +CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK = 0x00FF0000 # macro +CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK = 0xFF000000 # macro +CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_RING0_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_RING0_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_RING1_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_RING1_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_RING2_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_RING2_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT = 0x0 # macro +CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT = 0x1 # macro +CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT = 0x2 # macro +CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT = 0x3 # macro +CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT = 0x4 # macro +CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK = 0x00000001 # macro +CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK = 0x00000002 # macro +CP_FATAL_ERROR__GFX_HALT_PROC_MASK = 0x00000004 # macro +CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK = 0x00000008 # macro +CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK = 0x00000010 # macro +CP_RB_VMID__RB0_VMID__SHIFT = 0x0 # macro +CP_RB_VMID__RB1_VMID__SHIFT = 0x8 # macro +CP_RB_VMID__RB2_VMID__SHIFT = 0x10 # macro +CP_RB_VMID__RB0_VMID_MASK = 0x0000000F # macro +CP_RB_VMID__RB1_VMID_MASK = 0x00000F00 # macro +CP_RB_VMID__RB2_VMID_MASK = 0x000F0000 # macro +CP_ME0_PIPE0_VMID__VMID__SHIFT = 0x0 # macro +CP_ME0_PIPE0_VMID__VMID_MASK = 0x0000000F # macro +CP_ME0_PIPE1_VMID__VMID__SHIFT = 0x0 # macro +CP_ME0_PIPE1_VMID__VMID_MASK = 0x0000000F # macro +CP_RB0_WPTR__RB_WPTR__SHIFT = 0x0 # macro +CP_RB0_WPTR__RB_WPTR_MASK = 0xFFFFFFFF # macro +CP_RB_WPTR__RB_WPTR__SHIFT = 0x0 # macro +CP_RB_WPTR__RB_WPTR_MASK = 0xFFFFFFFF # macro +CP_RB0_WPTR_HI__RB_WPTR__SHIFT = 0x0 # macro +CP_RB0_WPTR_HI__RB_WPTR_MASK = 0xFFFFFFFF # macro +CP_RB_WPTR_HI__RB_WPTR__SHIFT = 0x0 # macro +CP_RB_WPTR_HI__RB_WPTR_MASK = 0xFFFFFFFF # macro +CP_RB1_WPTR__RB_WPTR__SHIFT = 0x0 # macro +CP_RB1_WPTR__RB_WPTR_MASK = 0xFFFFFFFF # macro +CP_RB1_WPTR_HI__RB_WPTR__SHIFT = 0x0 # macro +CP_RB1_WPTR_HI__RB_WPTR_MASK = 0xFFFFFFFF # macro +CP_RB2_WPTR__RB_WPTR__SHIFT = 0x0 # macro +CP_RB2_WPTR__RB_WPTR_MASK = 0x000FFFFF # macro +CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT = 0x1 # macro +CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT = 0x2 # macro +CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT = 0x1e # macro +CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT = 0x1f # macro +CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK = 0x00000002 # macro +CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK = 0x0FFFFFFC # macro +CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK = 0x40000000 # macro +CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK = 0x80000000 # macro +CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT = 0x2 # macro +CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK = 0x0FFFFFFC # macro +CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT = 0x2 # macro +CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK = 0x0FFFFFFC # macro +CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT = 0x2 # macro +CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK = 0x0FFFFFFC # macro +CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT = 0x2 # macro +CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK = 0x0FFFFFFC # macro +CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT = 0x0 # macro +CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK = 0x00000001 # macro +CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT = 0x0 # macro +CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK = 0x00000001 # macro +CP_RB1_BASE__RB_BASE__SHIFT = 0x0 # macro +CP_RB1_BASE__RB_BASE_MASK = 0xFFFFFFFF # macro +CP_RB1_CNTL__RB_BUFSZ__SHIFT = 0x0 # macro +CP_RB1_CNTL__RB_BLKSZ__SHIFT = 0x8 # macro +CP_RB1_CNTL__MIN_AVAILSZ__SHIFT = 0x14 # macro +CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT = 0x16 # macro +CP_RB1_CNTL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_RB1_CNTL__RB_NO_UPDATE__SHIFT = 0x1b # macro +CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT = 0x1f # macro +CP_RB1_CNTL__RB_BUFSZ_MASK = 0x0000003F # macro +CP_RB1_CNTL__RB_BLKSZ_MASK = 0x00003F00 # macro +CP_RB1_CNTL__MIN_AVAILSZ_MASK = 0x00300000 # macro +CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK = 0x00C00000 # macro +CP_RB1_CNTL__CACHE_POLICY_MASK = 0x01000000 # macro +CP_RB1_CNTL__RB_NO_UPDATE_MASK = 0x08000000 # macro +CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK = 0x80000000 # macro +CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT = 0x2 # macro +CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK = 0xFFFFFFFC # macro +CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT = 0x0 # macro +CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK = 0x0000FFFF # macro +CP_RB2_BASE__RB_BASE__SHIFT = 0x0 # macro +CP_RB2_BASE__RB_BASE_MASK = 0xFFFFFFFF # macro +CP_RB2_CNTL__RB_BUFSZ__SHIFT = 0x0 # macro +CP_RB2_CNTL__RB_BLKSZ__SHIFT = 0x8 # macro +CP_RB2_CNTL__MIN_AVAILSZ__SHIFT = 0x14 # macro +CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT = 0x16 # macro +CP_RB2_CNTL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_RB2_CNTL__RB_NO_UPDATE__SHIFT = 0x1b # macro +CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT = 0x1f # macro +CP_RB2_CNTL__RB_BUFSZ_MASK = 0x0000003F # macro +CP_RB2_CNTL__RB_BLKSZ_MASK = 0x00003F00 # macro +CP_RB2_CNTL__MIN_AVAILSZ_MASK = 0x00300000 # macro +CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK = 0x00C00000 # macro +CP_RB2_CNTL__CACHE_POLICY_MASK = 0x01000000 # macro +CP_RB2_CNTL__RB_NO_UPDATE_MASK = 0x08000000 # macro +CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK = 0x80000000 # macro +CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT = 0x2 # macro +CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK = 0xFFFFFFFC # macro +CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT = 0x0 # macro +CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK = 0x0000FFFF # macro +CP_RB0_ACTIVE__ACTIVE__SHIFT = 0x0 # macro +CP_RB0_ACTIVE__ACTIVE_MASK = 0x00000001 # macro +CP_RB_ACTIVE__ACTIVE__SHIFT = 0x0 # macro +CP_RB_ACTIVE__ACTIVE_MASK = 0x00000001 # macro +CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT = 0xb # macro +CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT = 0x12 # macro +CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT = 0x13 # macro +CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT = 0x14 # macro +CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT = 0x15 # macro +CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT = 0x16 # macro +CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK = 0x00000800 # macro +CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK = 0x00040000 # macro +CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK = 0x00080000 # macro +CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK = 0x00100000 # macro +CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK = 0x00200000 # macro +CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK = 0x00400000 # macro +CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT = 0xb # macro +CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT = 0x12 # macro +CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT = 0x13 # macro +CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT = 0x14 # macro +CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT = 0x15 # macro +CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT = 0x16 # macro +CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK = 0x00000800 # macro +CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK = 0x00040000 # macro +CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK = 0x00080000 # macro +CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK = 0x00100000 # macro +CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK = 0x00200000 # macro +CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK = 0x00400000 # macro +CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT = 0xb # macro +CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT = 0x12 # macro +CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT = 0x13 # macro +CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT = 0x14 # macro +CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT = 0x15 # macro +CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT = 0x16 # macro +CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK = 0x00000800 # macro +CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK = 0x00040000 # macro +CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK = 0x00080000 # macro +CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK = 0x00100000 # macro +CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK = 0x00200000 # macro +CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK = 0x00400000 # macro +CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT = 0xb # macro +CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT = 0xe # macro +CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT = 0x10 # macro +CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT = 0x11 # macro +CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT = 0x12 # macro +CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT = 0x13 # macro +CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT = 0x14 # macro +CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT = 0x15 # macro +CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT = 0x16 # macro +CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT = 0x17 # macro +CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT = 0x18 # macro +CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT = 0x1a # macro +CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT = 0x1b # macro +CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT = 0x1d # macro +CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT = 0x1e # macro +CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT = 0x1f # macro +CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK = 0x00000800 # macro +CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK = 0x00004000 # macro +CP_INT_STATUS_RING0__GPF_INT_STAT_MASK = 0x00010000 # macro +CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK = 0x00020000 # macro +CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK = 0x00040000 # macro +CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK = 0x00080000 # macro +CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK = 0x00100000 # macro +CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK = 0x00200000 # macro +CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK = 0x00400000 # macro +CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK = 0x00800000 # macro +CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK = 0x01000000 # macro +CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK = 0x04000000 # macro +CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK = 0x08000000 # macro +CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK = 0x20000000 # macro +CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK = 0x40000000 # macro +CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK = 0x80000000 # macro +CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT = 0xb # macro +CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT = 0xe # macro +CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT = 0x10 # macro +CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT = 0x11 # macro +CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT = 0x12 # macro +CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT = 0x13 # macro +CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT = 0x14 # macro +CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT = 0x15 # macro +CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT = 0x16 # macro +CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT = 0x17 # macro +CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT = 0x18 # macro +CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT = 0x1a # macro +CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT = 0x1b # macro +CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT = 0x1d # macro +CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT = 0x1e # macro +CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT = 0x1f # macro +CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK = 0x00000800 # macro +CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK = 0x00004000 # macro +CP_INT_STATUS_RING1__GPF_INT_STAT_MASK = 0x00010000 # macro +CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK = 0x00020000 # macro +CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK = 0x00040000 # macro +CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK = 0x00080000 # macro +CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK = 0x00100000 # macro +CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK = 0x00200000 # macro +CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK = 0x00400000 # macro +CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK = 0x00800000 # macro +CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK = 0x01000000 # macro +CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK = 0x04000000 # macro +CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK = 0x08000000 # macro +CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK = 0x20000000 # macro +CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK = 0x40000000 # macro +CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK = 0x80000000 # macro +CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT = 0xb # macro +CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT = 0xe # macro +CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT = 0x10 # macro +CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT = 0x11 # macro +CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT = 0x12 # macro +CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT = 0x13 # macro +CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT = 0x14 # macro +CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT = 0x15 # macro +CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT = 0x16 # macro +CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT = 0x17 # macro +CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT = 0x18 # macro +CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT = 0x1a # macro +CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT = 0x1b # macro +CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT = 0x1d # macro +CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT = 0x1e # macro +CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT = 0x1f # macro +CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK = 0x00000800 # macro +CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK = 0x00004000 # macro +CP_INT_STATUS_RING2__GPF_INT_STAT_MASK = 0x00010000 # macro +CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK = 0x00020000 # macro +CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK = 0x00040000 # macro +CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK = 0x00080000 # macro +CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK = 0x00100000 # macro +CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK = 0x00200000 # macro +CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK = 0x00400000 # macro +CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK = 0x00800000 # macro +CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK = 0x01000000 # macro +CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK = 0x04000000 # macro +CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK = 0x08000000 # macro +CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK = 0x20000000 # macro +CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK = 0x40000000 # macro +CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK = 0x80000000 # macro +CP_ME_F32_INTERRUPT__ECC_ERROR_INT__SHIFT = 0x0 # macro +CP_ME_F32_INTERRUPT__TIME_STAMP_INT__SHIFT = 0x1 # macro +CP_ME_F32_INTERRUPT__ME_F32_INT_2__SHIFT = 0x2 # macro +CP_ME_F32_INTERRUPT__ME_F32_INT_3__SHIFT = 0x3 # macro +CP_ME_F32_INTERRUPT__ECC_ERROR_INT_MASK = 0x00000001 # macro +CP_ME_F32_INTERRUPT__TIME_STAMP_INT_MASK = 0x00000002 # macro +CP_ME_F32_INTERRUPT__ME_F32_INT_2_MASK = 0x00000004 # macro +CP_ME_F32_INTERRUPT__ME_F32_INT_3_MASK = 0x00000008 # macro +CP_PFP_F32_INTERRUPT__ECC_ERROR_INT__SHIFT = 0x0 # macro +CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT = 0x1 # macro +CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT = 0x2 # macro +CP_PFP_F32_INTERRUPT__PFP_F32_INT_3__SHIFT = 0x3 # macro +CP_PFP_F32_INTERRUPT__ECC_ERROR_INT_MASK = 0x00000001 # macro +CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK = 0x00000002 # macro +CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK = 0x00000004 # macro +CP_PFP_F32_INTERRUPT__PFP_F32_INT_3_MASK = 0x00000008 # macro +CP_CE_F32_INTERRUPT__ECC_ERROR_INT__SHIFT = 0x0 # macro +CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT = 0x1 # macro +CP_CE_F32_INTERRUPT__CE_F32_INT_2__SHIFT = 0x2 # macro +CP_CE_F32_INTERRUPT__CE_F32_INT_3__SHIFT = 0x3 # macro +CP_CE_F32_INTERRUPT__ECC_ERROR_INT_MASK = 0x00000001 # macro +CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK = 0x00000002 # macro +CP_CE_F32_INTERRUPT__CE_F32_INT_2_MASK = 0x00000004 # macro +CP_CE_F32_INTERRUPT__CE_F32_INT_3_MASK = 0x00000008 # macro +CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT = 0x0 # macro +CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT = 0x1 # macro +CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT = 0x2 # macro +CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT = 0x3 # macro +CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT = 0x4 # macro +CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT = 0x5 # macro +CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT = 0x6 # macro +CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT = 0x7 # macro +CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT = 0x8 # macro +CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT__SHIFT = 0x9 # macro +CP_MEC1_F32_INTERRUPT__GPF_INT_CPF__SHIFT = 0xa # macro +CP_MEC1_F32_INTERRUPT__GPF_INT_DMA__SHIFT = 0xb # macro +CP_MEC1_F32_INTERRUPT__GPF_INT_CPC__SHIFT = 0xc # macro +CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT = 0xd # macro +CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT = 0xe # macro +CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT = 0xf # macro +CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK = 0x00000001 # macro +CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK = 0x00000002 # macro +CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK = 0x00000004 # macro +CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT_MASK = 0x00000008 # macro +CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT_MASK = 0x00000010 # macro +CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK = 0x00000020 # macro +CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT_MASK = 0x00000040 # macro +CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT_MASK = 0x00000080 # macro +CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT_MASK = 0x00000100 # macro +CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT_MASK = 0x00000200 # macro +CP_MEC1_F32_INTERRUPT__GPF_INT_CPF_MASK = 0x00000400 # macro +CP_MEC1_F32_INTERRUPT__GPF_INT_DMA_MASK = 0x00000800 # macro +CP_MEC1_F32_INTERRUPT__GPF_INT_CPC_MASK = 0x00001000 # macro +CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK = 0x00002000 # macro +CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK = 0x00004000 # macro +CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK = 0x00008000 # macro +CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT = 0x0 # macro +CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT = 0x1 # macro +CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT = 0x2 # macro +CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT = 0x3 # macro +CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT = 0x4 # macro +CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT = 0x5 # macro +CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT = 0x6 # macro +CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT = 0x7 # macro +CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT = 0x8 # macro +CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT__SHIFT = 0x9 # macro +CP_MEC2_F32_INTERRUPT__GPF_INT_CPF__SHIFT = 0xa # macro +CP_MEC2_F32_INTERRUPT__GPF_INT_DMA__SHIFT = 0xb # macro +CP_MEC2_F32_INTERRUPT__GPF_INT_CPC__SHIFT = 0xc # macro +CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT = 0xd # macro +CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT = 0xe # macro +CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT = 0xf # macro +CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK = 0x00000001 # macro +CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK = 0x00000002 # macro +CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK = 0x00000004 # macro +CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT_MASK = 0x00000008 # macro +CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT_MASK = 0x00000010 # macro +CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK = 0x00000020 # macro +CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT_MASK = 0x00000040 # macro +CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT_MASK = 0x00000080 # macro +CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT_MASK = 0x00000100 # macro +CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT_MASK = 0x00000200 # macro +CP_MEC2_F32_INTERRUPT__GPF_INT_CPF_MASK = 0x00000400 # macro +CP_MEC2_F32_INTERRUPT__GPF_INT_DMA_MASK = 0x00000800 # macro +CP_MEC2_F32_INTERRUPT__GPF_INT_CPC_MASK = 0x00001000 # macro +CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK = 0x00002000 # macro +CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK = 0x00004000 # macro +CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK = 0x00008000 # macro +CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT = 0x0 # macro +CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT = 0x1 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT = 0x8 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT = 0x9 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT = 0xa # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT = 0xb # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT = 0x10 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT = 0x11 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT = 0x12 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT = 0x13 # macro +CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK = 0x00000001 # macro +CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK = 0x00000002 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK = 0x00000100 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK = 0x00000200 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK = 0x00000400 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK = 0x00000800 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK = 0x00010000 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK = 0x00020000 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK = 0x00040000 # macro +CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK = 0x00080000 # macro +CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT = 0x0 # macro +CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT = 0x1 # macro +CP_MEM_SLP_CNTL__RESERVED__SHIFT = 0x2 # macro +CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT = 0x7 # macro +CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT = 0x8 # macro +CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT = 0x10 # macro +CP_MEM_SLP_CNTL__RESERVED1__SHIFT = 0x18 # macro +CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK = 0x00000001 # macro +CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK = 0x00000002 # macro +CP_MEM_SLP_CNTL__RESERVED_MASK = 0x0000007C # macro +CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK = 0x00000080 # macro +CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK = 0x0000FF00 # macro +CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK = 0x00FF0000 # macro +CP_MEM_SLP_CNTL__RESERVED1_MASK = 0xFF000000 # macro +CP_ECC_DMA_FIRST_OCCURRENCE__INTERFACE__SHIFT = 0x0 # macro +CP_ECC_DMA_FIRST_OCCURRENCE__CLIENT__SHIFT = 0x4 # macro +CP_ECC_DMA_FIRST_OCCURRENCE__ME__SHIFT = 0x8 # macro +CP_ECC_DMA_FIRST_OCCURRENCE__PIPE__SHIFT = 0xa # macro +CP_ECC_DMA_FIRST_OCCURRENCE__VMID__SHIFT = 0x10 # macro +CP_ECC_DMA_FIRST_OCCURRENCE__INTERFACE_MASK = 0x00000003 # macro +CP_ECC_DMA_FIRST_OCCURRENCE__CLIENT_MASK = 0x000000F0 # macro +CP_ECC_DMA_FIRST_OCCURRENCE__ME_MASK = 0x00000300 # macro +CP_ECC_DMA_FIRST_OCCURRENCE__PIPE_MASK = 0x00000C00 # macro +CP_ECC_DMA_FIRST_OCCURRENCE__VMID_MASK = 0x000F0000 # macro +CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT = 0x0 # macro +CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT = 0x4 # macro +CP_ECC_FIRSTOCCURRENCE__ME__SHIFT = 0x8 # macro +CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT = 0xa # macro +CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT = 0xc # macro +CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT = 0x10 # macro +CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK = 0x00000003 # macro +CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK = 0x000000F0 # macro +CP_ECC_FIRSTOCCURRENCE__ME_MASK = 0x00000300 # macro +CP_ECC_FIRSTOCCURRENCE__PIPE_MASK = 0x00000C00 # macro +CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK = 0x00007000 # macro +CP_ECC_FIRSTOCCURRENCE__VMID_MASK = 0x000F0000 # macro +CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT = 0x0 # macro +CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK = 0xFFFFFFFF # macro +CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT = 0x0 # macro +CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK = 0xFFFFFFFF # macro +CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT = 0x0 # macro +CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK = 0xFFFFFFFF # macro +GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT = 0xf # macro +GB_EDC_MODE__COUNT_FED_OUT__SHIFT = 0x10 # macro +GB_EDC_MODE__GATE_FUE__SHIFT = 0x11 # macro +GB_EDC_MODE__DED_MODE__SHIFT = 0x14 # macro +GB_EDC_MODE__PROP_FED__SHIFT = 0x1d # macro +GB_EDC_MODE__BYPASS__SHIFT = 0x1f # macro +GB_EDC_MODE__FORCE_SEC_ON_DED_MASK = 0x00008000 # macro +GB_EDC_MODE__COUNT_FED_OUT_MASK = 0x00010000 # macro +GB_EDC_MODE__GATE_FUE_MASK = 0x00020000 # macro +GB_EDC_MODE__DED_MODE_MASK = 0x00300000 # macro +GB_EDC_MODE__PROP_FED_MASK = 0x20000000 # macro +GB_EDC_MODE__BYPASS_MASK = 0x80000000 # macro +CP_DEBUG__CPG_REPEATER_FGCG_OVERRIDE__SHIFT = 0x9 # macro +CP_DEBUG__CPG_RAM_CLK_GATING_DISABLE__SHIFT = 0xe # macro +CP_DEBUG__DISABLE_GFX_HALT_ON_UTCL1_ERROR__SHIFT = 0xf # macro +CP_DEBUG__SURFSYNC_CNTX_RDADDR__SHIFT = 0x10 # macro +CP_DEBUG__BUSY_EXTENDER__SHIFT = 0x13 # macro +CP_DEBUG__PRIV_REG_INTERRUPT_ENABLE__SHIFT = 0x15 # macro +CP_DEBUG__INTERRUPT_ENABLE__SHIFT = 0x16 # macro +CP_DEBUG__PREDICATE_DISABLE__SHIFT = 0x17 # macro +CP_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT = 0x18 # macro +CP_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT = 0x19 # macro +CP_DEBUG__EVENT_FILT_DISABLE__SHIFT = 0x1a # macro +CP_DEBUG__CPG_TC_MTYPE_OVERRIDE__SHIFT = 0x1b # macro +CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT = 0x1c # macro +CP_DEBUG__CS_STATE_FILT_DISABLE__SHIFT = 0x1d # macro +CP_DEBUG__CS_PIPELINE_RESET_DISABLE__SHIFT = 0x1e # macro +CP_DEBUG__IB_PACKET_INJECTOR_DISABLE__SHIFT = 0x1f # macro +CP_DEBUG__CPG_REPEATER_FGCG_OVERRIDE_MASK = 0x00000200 # macro +CP_DEBUG__CPG_RAM_CLK_GATING_DISABLE_MASK = 0x00004000 # macro +CP_DEBUG__DISABLE_GFX_HALT_ON_UTCL1_ERROR_MASK = 0x00008000 # macro +CP_DEBUG__SURFSYNC_CNTX_RDADDR_MASK = 0x00070000 # macro +CP_DEBUG__BUSY_EXTENDER_MASK = 0x00180000 # macro +CP_DEBUG__PRIV_REG_INTERRUPT_ENABLE_MASK = 0x00200000 # macro +CP_DEBUG__INTERRUPT_ENABLE_MASK = 0x00400000 # macro +CP_DEBUG__PREDICATE_DISABLE_MASK = 0x00800000 # macro +CP_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK = 0x01000000 # macro +CP_DEBUG__OVERFLOW_BUSY_DISABLE_MASK = 0x02000000 # macro +CP_DEBUG__EVENT_FILT_DISABLE_MASK = 0x04000000 # macro +CP_DEBUG__CPG_TC_MTYPE_OVERRIDE_MASK = 0x08000000 # macro +CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE_MASK = 0x10000000 # macro +CP_DEBUG__CS_STATE_FILT_DISABLE_MASK = 0x20000000 # macro +CP_DEBUG__CS_PIPELINE_RESET_DISABLE_MASK = 0x40000000 # macro +CP_DEBUG__IB_PACKET_INJECTOR_DISABLE_MASK = 0x80000000 # macro +CP_CPF_DEBUG__QUE_MANAGER_CLR_DBELLUPD_DIS__SHIFT = 0x6 # macro +CP_CPF_DEBUG__CPF_REPEATER_FGCG_OVERRIDE__SHIFT = 0x10 # macro +CP_CPF_DEBUG__CPF_RAM_CLK_GATING_DISABLE__SHIFT = 0x12 # macro +CP_CPF_DEBUG__BUSY_EXTENDER__SHIFT = 0x13 # macro +CP_CPF_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT = 0x18 # macro +CP_CPF_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT = 0x19 # macro +CP_CPF_DEBUG__CPF_PRIORITY_YIELD_ACTIVE_DIS__SHIFT = 0x1d # macro +CP_CPF_DEBUG__CPF_TC_MTYPE_OVERRIDE__SHIFT = 0x1e # macro +CP_CPF_DEBUG__DBGU_TRIGGER__SHIFT = 0x1f # macro +CP_CPF_DEBUG__QUE_MANAGER_CLR_DBELLUPD_DIS_MASK = 0x00000040 # macro +CP_CPF_DEBUG__CPF_REPEATER_FGCG_OVERRIDE_MASK = 0x00010000 # macro +CP_CPF_DEBUG__CPF_RAM_CLK_GATING_DISABLE_MASK = 0x00040000 # macro +CP_CPF_DEBUG__BUSY_EXTENDER_MASK = 0x00180000 # macro +CP_CPF_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK = 0x01000000 # macro +CP_CPF_DEBUG__OVERFLOW_BUSY_DISABLE_MASK = 0x02000000 # macro +CP_CPF_DEBUG__CPF_PRIORITY_YIELD_ACTIVE_DIS_MASK = 0x20000000 # macro +CP_CPF_DEBUG__CPF_TC_MTYPE_OVERRIDE_MASK = 0x40000000 # macro +CP_CPF_DEBUG__DBGU_TRIGGER_MASK = 0x80000000 # macro +CP_CPC_DEBUG__CPC_PIPE_SEL__SHIFT = 0x0 # macro +CP_CPC_DEBUG__CPC_ROLLOVER_EVENT_DEBUG_EN__SHIFT = 0x3 # macro +CP_CPC_DEBUG__CPC_HARVESTING_CONTINUE_DISABLE__SHIFT = 0xb # macro +CP_CPC_DEBUG__CPC_HARVESTING_RELAUNCH_DISABLE__SHIFT = 0xc # macro +CP_CPC_DEBUG__CPC_HARVEST_AUTO_DISABLE__SHIFT = 0xd # macro +CP_CPC_DEBUG__CPC_HARVESTING_DISPATCH_DISABLE__SHIFT = 0xe # macro +CP_CPC_DEBUG__CPC_REPEATER_FGCG_OVERRIDE__SHIFT = 0xf # macro +CP_CPC_DEBUG__CPC_RAM_CLK_GATING_DISABLE__SHIFT = 0x12 # macro +CP_CPC_DEBUG__BUSY_EXTENDER__SHIFT = 0x13 # macro +CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE__SHIFT = 0x15 # macro +CP_CPC_DEBUG__RESERVED_INTERRUPT_ENABLE__SHIFT = 0x16 # macro +CP_CPC_DEBUG__RESTORE_FIFO_EMPTY_SEL__SHIFT = 0x17 # macro +CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT = 0x18 # macro +CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT = 0x19 # macro +CP_CPC_DEBUG__EVENT_FILT_DISABLE__SHIFT = 0x1a # macro +CP_CPC_DEBUG__PRIV_REG_INTERRUPT_ENABLE__SHIFT = 0x1b # macro +CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT = 0x1c # macro +CP_CPC_DEBUG__CS_STATE_FILT_DISABLE__SHIFT = 0x1d # macro +CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE__SHIFT = 0x1f # macro +CP_CPC_DEBUG__CPC_PIPE_SEL_MASK = 0x00000003 # macro +CP_CPC_DEBUG__CPC_ROLLOVER_EVENT_DEBUG_EN_MASK = 0x00000008 # macro +CP_CPC_DEBUG__CPC_HARVESTING_CONTINUE_DISABLE_MASK = 0x00000800 # macro +CP_CPC_DEBUG__CPC_HARVESTING_RELAUNCH_DISABLE_MASK = 0x00001000 # macro +CP_CPC_DEBUG__CPC_HARVEST_AUTO_DISABLE_MASK = 0x00002000 # macro +CP_CPC_DEBUG__CPC_HARVESTING_DISPATCH_DISABLE_MASK = 0x00004000 # macro +CP_CPC_DEBUG__CPC_REPEATER_FGCG_OVERRIDE_MASK = 0x00008000 # macro +CP_CPC_DEBUG__CPC_RAM_CLK_GATING_DISABLE_MASK = 0x00040000 # macro +CP_CPC_DEBUG__BUSY_EXTENDER_MASK = 0x00180000 # macro +CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE_MASK = 0x00200000 # macro +CP_CPC_DEBUG__RESERVED_INTERRUPT_ENABLE_MASK = 0x00400000 # macro +CP_CPC_DEBUG__RESTORE_FIFO_EMPTY_SEL_MASK = 0x00800000 # macro +CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK = 0x01000000 # macro +CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE_MASK = 0x02000000 # macro +CP_CPC_DEBUG__EVENT_FILT_DISABLE_MASK = 0x04000000 # macro +CP_CPC_DEBUG__PRIV_REG_INTERRUPT_ENABLE_MASK = 0x08000000 # macro +CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE_MASK = 0x10000000 # macro +CP_CPC_DEBUG__CS_STATE_FILT_DISABLE_MASK = 0x20000000 # macro +CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE_MASK = 0x80000000 # macro +CP_CPC_DEBUG_2__DC_GD_PIPE3_QSWITCH_CNT__SHIFT = 0x0 # macro +CP_CPC_DEBUG_2__DC_GD_PIPE2_QSWITCH_CNT__SHIFT = 0x8 # macro +CP_CPC_DEBUG_2__DC_GD_PIPE1_QSWITCH_CNT__SHIFT = 0x10 # macro +CP_CPC_DEBUG_2__DC_GD_PIPE0_QSWITCH_CNT__SHIFT = 0x18 # macro +CP_CPC_DEBUG_2__DC_GD_PIPE3_QSWITCH_CNT_MASK = 0x000000FF # macro +CP_CPC_DEBUG_2__DC_GD_PIPE2_QSWITCH_CNT_MASK = 0x0000FF00 # macro +CP_CPC_DEBUG_2__DC_GD_PIPE1_QSWITCH_CNT_MASK = 0x00FF0000 # macro +CP_CPC_DEBUG_2__DC_GD_PIPE0_QSWITCH_CNT_MASK = 0xFF000000 # macro +CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT = 0x0 # macro +CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT = 0x1d # macro +CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT = 0x1e # macro +CP_PQ_WPTR_POLL_CNTL__EN__SHIFT = 0x1f # macro +CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK = 0x000000FF # macro +CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK = 0x20000000 # macro +CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK = 0x40000000 # macro +CP_PQ_WPTR_POLL_CNTL__EN_MASK = 0x80000000 # macro +CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT = 0x0 # macro +CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK = 0xFFFFFFFF # macro +CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT = 0xc # macro +CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT = 0xd # macro +CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT = 0xf # macro +CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK = 0x00001000 # macro +CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK = 0x00002000 # macro +CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK = 0x00008000 # macro +CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT = 0xc # macro +CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT = 0xd # macro +CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT = 0xf # macro +CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK = 0x00001000 # macro +CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK = 0x00002000 # macro +CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK = 0x00008000 # macro +CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT = 0xc # macro +CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT = 0xd # macro +CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT = 0xf # macro +CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK = 0x00001000 # macro +CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK = 0x00002000 # macro +CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK = 0x00008000 # macro +CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT = 0xc # macro +CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT = 0xd # macro +CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT = 0xf # macro +CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK = 0x00001000 # macro +CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK = 0x00002000 # macro +CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK = 0x00008000 # macro +CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT = 0xc # macro +CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT = 0xd # macro +CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT = 0xf # macro +CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK = 0x00001000 # macro +CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK = 0x00002000 # macro +CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK = 0x00008000 # macro +CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT = 0xc # macro +CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT = 0xd # macro +CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT = 0xf # macro +CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK = 0x00001000 # macro +CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK = 0x00002000 # macro +CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK = 0x00008000 # macro +CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT = 0xc # macro +CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT = 0xd # macro +CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT = 0xf # macro +CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK = 0x00001000 # macro +CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK = 0x00002000 # macro +CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK = 0x00008000 # macro +CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT = 0xc # macro +CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT = 0xd # macro +CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT = 0xf # macro +CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK = 0x00001000 # macro +CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK = 0x00002000 # macro +CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK = 0x00008000 # macro +CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT = 0xc # macro +CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT = 0xd # macro +CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT = 0xe # macro +CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT = 0xf # macro +CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT = 0x10 # macro +CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT = 0x11 # macro +CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT = 0x17 # macro +CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT = 0x18 # macro +CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT = 0x1a # macro +CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT = 0x1b # macro +CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT = 0x1d # macro +CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT = 0x1e # macro +CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT = 0x1f # macro +CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK = 0x00001000 # macro +CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK = 0x00002000 # macro +CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK = 0x00004000 # macro +CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK = 0x00008000 # macro +CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK = 0x00010000 # macro +CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK = 0x00020000 # macro +CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK = 0x00800000 # macro +CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK = 0x01000000 # macro +CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK = 0x04000000 # macro +CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK = 0x08000000 # macro +CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK = 0x20000000 # macro +CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK = 0x40000000 # macro +CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK = 0x80000000 # macro +CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT = 0xc # macro +CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT = 0xd # macro +CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT = 0xe # macro +CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT = 0xf # macro +CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT = 0x10 # macro +CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT = 0x11 # macro +CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT = 0x17 # macro +CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT = 0x18 # macro +CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT = 0x1a # macro +CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT = 0x1b # macro +CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT = 0x1d # macro +CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT = 0x1e # macro +CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT = 0x1f # macro +CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK = 0x00001000 # macro +CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK = 0x00002000 # macro +CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK = 0x00004000 # macro +CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK = 0x00008000 # macro +CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK = 0x00010000 # macro +CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK = 0x00020000 # macro +CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK = 0x00800000 # macro +CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK = 0x01000000 # macro +CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK = 0x04000000 # macro +CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK = 0x08000000 # macro +CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK = 0x20000000 # macro +CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK = 0x40000000 # macro +CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK = 0x80000000 # macro +CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT = 0xc # macro +CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT = 0xd # macro +CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT = 0xe # macro +CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT = 0xf # macro +CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT = 0x10 # macro +CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT = 0x11 # macro +CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT = 0x17 # macro +CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT = 0x18 # macro +CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT = 0x1a # macro +CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT = 0x1b # macro +CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT = 0x1d # macro +CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT = 0x1e # macro +CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT = 0x1f # macro +CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK = 0x00001000 # macro +CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK = 0x00002000 # macro +CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK = 0x00004000 # macro +CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK = 0x00008000 # macro +CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK = 0x00010000 # macro +CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK = 0x00020000 # macro +CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK = 0x00800000 # macro +CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK = 0x01000000 # macro +CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK = 0x04000000 # macro +CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK = 0x08000000 # macro +CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK = 0x20000000 # macro +CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK = 0x40000000 # macro +CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK = 0x80000000 # macro +CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT = 0xc # macro +CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT = 0xd # macro +CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT = 0xe # macro +CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT = 0xf # macro +CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT = 0x10 # macro +CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT = 0x11 # macro +CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT = 0x17 # macro +CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT = 0x18 # macro +CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT = 0x1a # macro +CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT = 0x1b # macro +CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT = 0x1d # macro +CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT = 0x1e # macro +CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT = 0x1f # macro +CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK = 0x00001000 # macro +CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK = 0x00002000 # macro +CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK = 0x00004000 # macro +CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK = 0x00008000 # macro +CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK = 0x00010000 # macro +CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK = 0x00020000 # macro +CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK = 0x00800000 # macro +CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK = 0x01000000 # macro +CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK = 0x04000000 # macro +CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK = 0x08000000 # macro +CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK = 0x20000000 # macro +CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK = 0x40000000 # macro +CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK = 0x80000000 # macro +CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT = 0xc # macro +CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT = 0xd # macro +CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT = 0xe # macro +CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT = 0xf # macro +CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT = 0x10 # macro +CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT = 0x11 # macro +CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT = 0x17 # macro +CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT = 0x18 # macro +CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT = 0x1a # macro +CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT = 0x1b # macro +CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT = 0x1d # macro +CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT = 0x1e # macro +CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT = 0x1f # macro +CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK = 0x00001000 # macro +CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK = 0x00002000 # macro +CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK = 0x00004000 # macro +CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK = 0x00008000 # macro +CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK = 0x00010000 # macro +CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK = 0x00020000 # macro +CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK = 0x00800000 # macro +CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK = 0x01000000 # macro +CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK = 0x04000000 # macro +CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK = 0x08000000 # macro +CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK = 0x20000000 # macro +CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK = 0x40000000 # macro +CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK = 0x80000000 # macro +CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT = 0xc # macro +CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT = 0xd # macro +CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT = 0xe # macro +CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT = 0xf # macro +CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT = 0x10 # macro +CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT = 0x11 # macro +CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT = 0x17 # macro +CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT = 0x18 # macro +CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT = 0x1a # macro +CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT = 0x1b # macro +CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT = 0x1d # macro +CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT = 0x1e # macro +CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT = 0x1f # macro +CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK = 0x00001000 # macro +CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK = 0x00002000 # macro +CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK = 0x00004000 # macro +CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK = 0x00008000 # macro +CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK = 0x00010000 # macro +CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK = 0x00020000 # macro +CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK = 0x00800000 # macro +CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK = 0x01000000 # macro +CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK = 0x04000000 # macro +CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK = 0x08000000 # macro +CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK = 0x20000000 # macro +CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK = 0x40000000 # macro +CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK = 0x80000000 # macro +CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT = 0xc # macro +CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT = 0xd # macro +CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT = 0xe # macro +CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT = 0xf # macro +CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT = 0x10 # macro +CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT = 0x11 # macro +CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT = 0x17 # macro +CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT = 0x18 # macro +CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT = 0x1a # macro +CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT = 0x1b # macro +CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT = 0x1d # macro +CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT = 0x1e # macro +CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT = 0x1f # macro +CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK = 0x00001000 # macro +CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK = 0x00002000 # macro +CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK = 0x00004000 # macro +CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK = 0x00008000 # macro +CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK = 0x00010000 # macro +CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK = 0x00020000 # macro +CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK = 0x00800000 # macro +CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK = 0x01000000 # macro +CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK = 0x04000000 # macro +CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK = 0x08000000 # macro +CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK = 0x20000000 # macro +CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK = 0x40000000 # macro +CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK = 0x80000000 # macro +CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT = 0xc # macro +CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT = 0xd # macro +CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT = 0xe # macro +CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT = 0xf # macro +CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT = 0x10 # macro +CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT = 0x11 # macro +CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT = 0x17 # macro +CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT = 0x18 # macro +CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT = 0x1a # macro +CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT = 0x1b # macro +CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT = 0x1d # macro +CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT = 0x1e # macro +CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT = 0x1f # macro +CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK = 0x00001000 # macro +CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK = 0x00002000 # macro +CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK = 0x00004000 # macro +CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK = 0x00008000 # macro +CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK = 0x00010000 # macro +CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK = 0x00020000 # macro +CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK = 0x00800000 # macro +CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK = 0x01000000 # macro +CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK = 0x04000000 # macro +CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK = 0x08000000 # macro +CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK = 0x20000000 # macro +CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK = 0x40000000 # macro +CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK = 0x80000000 # macro +CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT = 0xc # macro +CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT = 0xd # macro +CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT = 0xe # macro +CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT = 0xf # macro +CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT = 0x10 # macro +CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT = 0x11 # macro +CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT = 0x17 # macro +CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT = 0x18 # macro +CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT = 0x1a # macro +CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT = 0x1b # macro +CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT = 0x1d # macro +CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT = 0x1e # macro +CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT = 0x1f # macro +CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK = 0x00001000 # macro +CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK = 0x00002000 # macro +CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK = 0x00004000 # macro +CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK = 0x00008000 # macro +CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK = 0x00010000 # macro +CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK = 0x00020000 # macro +CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK = 0x00800000 # macro +CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK = 0x01000000 # macro +CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK = 0x04000000 # macro +CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK = 0x08000000 # macro +CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK = 0x20000000 # macro +CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK = 0x40000000 # macro +CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK = 0x80000000 # macro +CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT = 0xc # macro +CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT = 0xd # macro +CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT = 0xe # macro +CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT = 0xf # macro +CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT = 0x10 # macro +CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT = 0x11 # macro +CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT = 0x17 # macro +CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT = 0x18 # macro +CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT = 0x1a # macro +CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT = 0x1b # macro +CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT = 0x1d # macro +CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT = 0x1e # macro +CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT = 0x1f # macro +CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK = 0x00001000 # macro +CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK = 0x00002000 # macro +CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK = 0x00004000 # macro +CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK = 0x00008000 # macro +CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK = 0x00010000 # macro +CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK = 0x00020000 # macro +CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK = 0x00800000 # macro +CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK = 0x01000000 # macro +CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK = 0x04000000 # macro +CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK = 0x08000000 # macro +CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK = 0x20000000 # macro +CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK = 0x40000000 # macro +CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK = 0x80000000 # macro +CC_GC_EDC_CONFIG__WRITE_DIS__SHIFT = 0x0 # macro +CC_GC_EDC_CONFIG__DIS_EDC__SHIFT = 0x1 # macro +CC_GC_EDC_CONFIG__ENABLE_IRRITATOR_CLK__SHIFT = 0x2 # macro +CC_GC_EDC_CONFIG__WRITE_DIS_MASK = 0x00000001 # macro +CC_GC_EDC_CONFIG__DIS_EDC_MASK = 0x00000002 # macro +CC_GC_EDC_CONFIG__ENABLE_IRRITATOR_CLK_MASK = 0x00000004 # macro +CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT = 0x0 # macro +CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT = 0x8 # macro +CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT = 0x10 # macro +CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT = 0x18 # macro +CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK = 0x000000FF # macro +CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK = 0x0000FF00 # macro +CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK = 0x00FF0000 # macro +CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK = 0xFF000000 # macro +CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT = 0x0 # macro +CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT = 0x8 # macro +CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT = 0x10 # macro +CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT = 0x18 # macro +CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK = 0x000000FF # macro +CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK = 0x0000FF00 # macro +CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK = 0x00FF0000 # macro +CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK = 0xFF000000 # macro +CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT = 0x0 # macro +CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK = 0x00000003 # macro +CP_CE_PRGRM_CNTR_START__IP_START__SHIFT = 0x0 # macro +CP_CE_PRGRM_CNTR_START__IP_START_MASK = 0x000007FF # macro +CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT = 0x0 # macro +CP_PFP_PRGRM_CNTR_START__IP_START_MASK = 0x00001FFF # macro +CP_ME_PRGRM_CNTR_START__IP_START__SHIFT = 0x0 # macro +CP_ME_PRGRM_CNTR_START__IP_START_MASK = 0x00000FFF # macro +CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT = 0x0 # macro +CP_MEC1_PRGRM_CNTR_START__IP_START_MASK = 0x0000FFFF # macro +CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT = 0x0 # macro +CP_MEC2_PRGRM_CNTR_START__IP_START_MASK = 0x0000FFFF # macro +CP_CE_INTR_ROUTINE_START__IR_START__SHIFT = 0x0 # macro +CP_CE_INTR_ROUTINE_START__IR_START_MASK = 0x000007FF # macro +CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT = 0x0 # macro +CP_PFP_INTR_ROUTINE_START__IR_START_MASK = 0x00001FFF # macro +CP_ME_INTR_ROUTINE_START__IR_START__SHIFT = 0x0 # macro +CP_ME_INTR_ROUTINE_START__IR_START_MASK = 0x00000FFF # macro +CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT = 0x0 # macro +CP_MEC1_INTR_ROUTINE_START__IR_START_MASK = 0x0000FFFF # macro +CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT = 0x0 # macro +CP_MEC2_INTR_ROUTINE_START__IR_START_MASK = 0x0000FFFF # macro +CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT = 0x0 # macro +CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT = 0x4 # macro +CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT = 0x10 # macro +CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT = 0x14 # macro +CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK = 0x00000007 # macro +CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK = 0x00000070 # macro +CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK = 0x00070000 # macro +CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK = 0x00700000 # macro +CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT = 0x0 # macro +CP_MAX_CONTEXT__MAX_CONTEXT_MASK = 0x00000007 # macro +CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT = 0x0 # macro +CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT = 0x8 # macro +CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT = 0x10 # macro +CP_IQ_WAIT_TIME1__GWS__SHIFT = 0x18 # macro +CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK = 0x000000FF # macro +CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK = 0x0000FF00 # macro +CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK = 0x00FF0000 # macro +CP_IQ_WAIT_TIME1__GWS_MASK = 0xFF000000 # macro +CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT = 0x0 # macro +CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT = 0x8 # macro +CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT = 0x10 # macro +CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT = 0x18 # macro +CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK = 0x000000FF # macro +CP_IQ_WAIT_TIME2__SCH_WAVE_MASK = 0x0000FF00 # macro +CP_IQ_WAIT_TIME2__SEM_REARM_MASK = 0x00FF0000 # macro +CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK = 0xFF000000 # macro +CP_RB0_BASE_HI__RB_BASE_HI__SHIFT = 0x0 # macro +CP_RB0_BASE_HI__RB_BASE_HI_MASK = 0x000000FF # macro +CP_RB1_BASE_HI__RB_BASE_HI__SHIFT = 0x0 # macro +CP_RB1_BASE_HI__RB_BASE_HI_MASK = 0x000000FF # macro +CP_VMID_RESET__RESET_REQUEST__SHIFT = 0x0 # macro +CP_VMID_RESET__RESET_REQUEST_MASK = 0x0000FFFF # macro +CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT = 0xc # macro +CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT = 0xd # macro +CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT = 0xe # macro +CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT = 0xf # macro +CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT = 0x10 # macro +CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT = 0x11 # macro +CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT = 0x17 # macro +CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT = 0x18 # macro +CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT = 0x1a # macro +CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT = 0x1b # macro +CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT = 0x1d # macro +CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT = 0x1e # macro +CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT = 0x1f # macro +CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK = 0x00001000 # macro +CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK = 0x00002000 # macro +CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK = 0x00004000 # macro +CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK = 0x00008000 # macro +CPC_INT_CNTL__GPF_INT_ENABLE_MASK = 0x00010000 # macro +CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK = 0x00020000 # macro +CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK = 0x00800000 # macro +CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK = 0x01000000 # macro +CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK = 0x04000000 # macro +CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK = 0x08000000 # macro +CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK = 0x20000000 # macro +CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK = 0x40000000 # macro +CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK = 0x80000000 # macro +CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT = 0xc # macro +CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT = 0xd # macro +CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT = 0xe # macro +CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT = 0xf # macro +CPC_INT_STATUS__GPF_INT_STATUS__SHIFT = 0x10 # macro +CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT = 0x11 # macro +CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT = 0x17 # macro +CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT = 0x18 # macro +CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT = 0x1a # macro +CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT = 0x1b # macro +CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT = 0x1d # macro +CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT = 0x1e # macro +CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT = 0x1f # macro +CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK = 0x00001000 # macro +CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK = 0x00002000 # macro +CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK = 0x00004000 # macro +CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK = 0x00008000 # macro +CPC_INT_STATUS__GPF_INT_STATUS_MASK = 0x00010000 # macro +CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK = 0x00020000 # macro +CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK = 0x00800000 # macro +CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK = 0x01000000 # macro +CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK = 0x04000000 # macro +CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK = 0x08000000 # macro +CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK = 0x20000000 # macro +CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK = 0x40000000 # macro +CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK = 0x80000000 # macro +CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT = 0x0 # macro +CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT = 0x10 # macro +CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK = 0x0000FFFF # macro +CP_VMID_PREEMPT__VIRT_COMMAND_MASK = 0x000F0000 # macro +CPC_INT_CNTX_ID__CNTX_ID__SHIFT = 0x0 # macro +CPC_INT_CNTX_ID__CNTX_ID_MASK = 0xFFFFFFFF # macro +CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT = 0x0 # macro +CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT = 0x1 # macro +CP_PQ_STATUS__DOORBELL_UPDATED_EN__SHIFT = 0x2 # macro +CP_PQ_STATUS__DOORBELL_UPDATED_MASK = 0x00000001 # macro +CP_PQ_STATUS__DOORBELL_ENABLE_MASK = 0x00000002 # macro +CP_PQ_STATUS__DOORBELL_UPDATED_EN_MASK = 0x00000004 # macro +CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT = 0xc # macro +CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK = 0xFFFFF000 # macro +CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT = 0x0 # macro +CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK = 0x0000FFFF # macro +CP_CPC_IC_BASE_CNTL__VMID__SHIFT = 0x0 # macro +CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_CPC_IC_BASE_CNTL__VMID_MASK = 0x0000000F # macro +CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK = 0x01000000 # macro +CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT = 0x0 # macro +CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT = 0x4 # macro +CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT = 0x5 # macro +CP_CPC_IC_OP_CNTL__ICACHE_INVALIDATED__SHIFT = 0x6 # macro +CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK = 0x00000001 # macro +CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK = 0x00000010 # macro +CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK = 0x00000020 # macro +CP_CPC_IC_OP_CNTL__ICACHE_INVALIDATED_MASK = 0x00000040 # macro +CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT = 0x0 # macro +CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT = 0x1 # macro +CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT = 0x2 # macro +CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT = 0x3 # macro +CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT = 0x4 # macro +CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT = 0x5 # macro +CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT = 0x6 # macro +CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT = 0x7 # macro +CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT = 0x8 # macro +CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT = 0x9 # macro +CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT = 0xa # macro +CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT = 0xb # macro +CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT = 0xc # macro +CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT = 0xd # macro +CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT = 0xe # macro +CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT = 0xf # macro +CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK = 0x00000001 # macro +CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK = 0x00000002 # macro +CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK = 0x00000004 # macro +CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK = 0x00000008 # macro +CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK = 0x00000010 # macro +CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK = 0x00000020 # macro +CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK = 0x00000040 # macro +CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK = 0x00000080 # macro +CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK = 0x00000100 # macro +CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK = 0x00000200 # macro +CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK = 0x00000400 # macro +CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK = 0x00000800 # macro +CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK = 0x00001000 # macro +CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK = 0x00002000 # macro +CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK = 0x00004000 # macro +CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK = 0x00008000 # macro +CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT = 0x0 # macro +CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT = 0x1 # macro +CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT = 0x2 # macro +CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT = 0x3 # macro +CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT = 0x4 # macro +CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT = 0x5 # macro +CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT = 0x6 # macro +CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT = 0x7 # macro +CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT = 0x8 # macro +CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT = 0x9 # macro +CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT = 0xa # macro +CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT = 0xb # macro +CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT = 0xc # macro +CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT = 0xd # macro +CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT = 0xe # macro +CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT = 0xf # macro +CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK = 0x00000001 # macro +CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK = 0x00000002 # macro +CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK = 0x00000004 # macro +CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK = 0x00000008 # macro +CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK = 0x00000010 # macro +CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK = 0x00000020 # macro +CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK = 0x00000040 # macro +CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK = 0x00000080 # macro +CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK = 0x00000100 # macro +CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK = 0x00000200 # macro +CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK = 0x00000400 # macro +CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK = 0x00000800 # macro +CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK = 0x00001000 # macro +CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK = 0x00002000 # macro +CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK = 0x00004000 # macro +CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK = 0x00008000 # macro +CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT = 0x0 # macro +CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT = 0x10 # macro +CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK = 0x0000FFFF # macro +CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK = 0xFFFF0000 # macro +CPC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +CPC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +CPC_UE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +CPC_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +CPC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +CPC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +CPC_UE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +CPC_UE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +CPC_UE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +CPC_UE_ERR_STATUS_HI__PARITY__SHIFT = 0x1 # macro +CPC_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +CPC_UE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +CPC_UE_ERR_STATUS_HI__UE_CNT__SHIFT = 0x17 # macro +CPC_UE_ERR_STATUS_HI__FED_CNT__SHIFT = 0x1a # macro +CPC_UE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1d # macro +CPC_UE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +CPC_UE_ERR_STATUS_HI__PARITY_MASK = 0x00000002 # macro +CPC_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +CPC_UE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +CPC_UE_ERR_STATUS_HI__UE_CNT_MASK = 0x03800000 # macro +CPC_UE_ERR_STATUS_HI__FED_CNT_MASK = 0x1C000000 # macro +CPC_UE_ERR_STATUS_HI__RESERVED_MASK = 0xE0000000 # macro +CPC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +CPC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +CPC_CE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +CPC_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +CPC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +CPC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +CPC_CE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +CPC_CE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +CPC_CE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +CPC_CE_ERR_STATUS_HI__OTHER__SHIFT = 0x1 # macro +CPC_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +CPC_CE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +CPC_CE_ERR_STATUS_HI__CE_CNT__SHIFT = 0x17 # macro +CPC_CE_ERR_STATUS_HI__POISON__SHIFT = 0x1a # macro +CPC_CE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1b # macro +CPC_CE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +CPC_CE_ERR_STATUS_HI__OTHER_MASK = 0x00000002 # macro +CPC_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +CPC_CE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +CPC_CE_ERR_STATUS_HI__CE_CNT_MASK = 0x03800000 # macro +CPC_CE_ERR_STATUS_HI__POISON_MASK = 0x04000000 # macro +CPC_CE_ERR_STATUS_HI__RESERVED_MASK = 0xF8000000 # macro +CPF_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +CPF_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +CPF_UE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +CPF_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +CPF_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +CPF_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +CPF_UE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +CPF_UE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +CPF_UE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +CPF_UE_ERR_STATUS_HI__PARITY__SHIFT = 0x1 # macro +CPF_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +CPF_UE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +CPF_UE_ERR_STATUS_HI__UE_CNT__SHIFT = 0x17 # macro +CPF_UE_ERR_STATUS_HI__FED_CNT__SHIFT = 0x1a # macro +CPF_UE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1d # macro +CPF_UE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +CPF_UE_ERR_STATUS_HI__PARITY_MASK = 0x00000002 # macro +CPF_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +CPF_UE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +CPF_UE_ERR_STATUS_HI__UE_CNT_MASK = 0x03800000 # macro +CPF_UE_ERR_STATUS_HI__FED_CNT_MASK = 0x1C000000 # macro +CPF_UE_ERR_STATUS_HI__RESERVED_MASK = 0xE0000000 # macro +CPF_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +CPF_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +CPF_CE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +CPF_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +CPF_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +CPF_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +CPF_CE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +CPF_CE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +CPF_CE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +CPF_CE_ERR_STATUS_HI__OTHER__SHIFT = 0x1 # macro +CPF_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +CPF_CE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +CPF_CE_ERR_STATUS_HI__CE_CNT__SHIFT = 0x17 # macro +CPF_CE_ERR_STATUS_HI__POISON__SHIFT = 0x1a # macro +CPF_CE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1b # macro +CPF_CE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +CPF_CE_ERR_STATUS_HI__OTHER_MASK = 0x00000002 # macro +CPF_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +CPF_CE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +CPF_CE_ERR_STATUS_HI__CE_CNT_MASK = 0x03800000 # macro +CPF_CE_ERR_STATUS_HI__POISON_MASK = 0x04000000 # macro +CPF_CE_ERR_STATUS_HI__RESERVED_MASK = 0xF8000000 # macro +CPG_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +CPG_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +CPG_UE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +CPG_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +CPG_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +CPG_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +CPG_UE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +CPG_UE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +CPG_UE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +CPG_UE_ERR_STATUS_HI__PARITY__SHIFT = 0x1 # macro +CPG_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +CPG_UE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +CPG_UE_ERR_STATUS_HI__UE_CNT__SHIFT = 0x17 # macro +CPG_UE_ERR_STATUS_HI__FED_CNT__SHIFT = 0x1a # macro +CPG_UE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1d # macro +CPG_UE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +CPG_UE_ERR_STATUS_HI__PARITY_MASK = 0x00000002 # macro +CPG_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +CPG_UE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +CPG_UE_ERR_STATUS_HI__UE_CNT_MASK = 0x03800000 # macro +CPG_UE_ERR_STATUS_HI__FED_CNT_MASK = 0x1C000000 # macro +CPG_UE_ERR_STATUS_HI__RESERVED_MASK = 0xE0000000 # macro +CPG_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +CPG_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +CPG_CE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +CPG_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +CPG_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +CPG_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +CPG_CE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +CPG_CE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +CPG_CE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +CPG_CE_ERR_STATUS_HI__OTHER__SHIFT = 0x1 # macro +CPG_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +CPG_CE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +CPG_CE_ERR_STATUS_HI__CE_CNT__SHIFT = 0x17 # macro +CPG_CE_ERR_STATUS_HI__POISON__SHIFT = 0x1a # macro +CPG_CE_ERR_STATUS_HI__RESERVED__SHIFT = 0x1b # macro +CPG_CE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +CPG_CE_ERR_STATUS_HI__OTHER_MASK = 0x00000002 # macro +CPG_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +CPG_CE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +CPG_CE_ERR_STATUS_HI__CE_CNT_MASK = 0x03800000 # macro +CPG_CE_ERR_STATUS_HI__POISON_MASK = 0x04000000 # macro +CPG_CE_ERR_STATUS_HI__RESERVED_MASK = 0xF8000000 # macro +CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET__SHIFT = 0x2 # macro +CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN__SHIFT = 0x1e # macro +CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT__SHIFT = 0x1f # macro +CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET_MASK = 0x0FFFFFFC # macro +CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN_MASK = 0x40000000 # macro +CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT_MASK = 0x80000000 # macro +CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET__SHIFT = 0x2 # macro +CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN__SHIFT = 0x1e # macro +CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT__SHIFT = 0x1f # macro +CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET_MASK = 0x0FFFFFFC # macro +CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN_MASK = 0x40000000 # macro +CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT_MASK = 0x80000000 # macro +CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET__SHIFT = 0x2 # macro +CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN__SHIFT = 0x1e # macro +CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT__SHIFT = 0x1f # macro +CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET_MASK = 0x0FFFFFFC # macro +CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN_MASK = 0x40000000 # macro +CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT_MASK = 0x80000000 # macro +CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET__SHIFT = 0x2 # macro +CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN__SHIFT = 0x1e # macro +CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT__SHIFT = 0x1f # macro +CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET_MASK = 0x0FFFFFFC # macro +CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN_MASK = 0x40000000 # macro +CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT_MASK = 0x80000000 # macro +CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET__SHIFT = 0x2 # macro +CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN__SHIFT = 0x1e # macro +CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT__SHIFT = 0x1f # macro +CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET_MASK = 0x0FFFFFFC # macro +CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN_MASK = 0x40000000 # macro +CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT_MASK = 0x80000000 # macro +CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET__SHIFT = 0x2 # macro +CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN__SHIFT = 0x1e # macro +CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT__SHIFT = 0x1f # macro +CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET_MASK = 0x0FFFFFFC # macro +CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN_MASK = 0x40000000 # macro +CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT_MASK = 0x80000000 # macro +CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET__SHIFT = 0x2 # macro +CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN__SHIFT = 0x1e # macro +CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT__SHIFT = 0x1f # macro +CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET_MASK = 0x0FFFFFFC # macro +CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN_MASK = 0x40000000 # macro +CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT_MASK = 0x80000000 # macro +CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET__SHIFT = 0x2 # macro +CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN__SHIFT = 0x1e # macro +CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT__SHIFT = 0x1f # macro +CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET_MASK = 0x0FFFFFFC # macro +CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN_MASK = 0x40000000 # macro +CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT_MASK = 0x80000000 # macro +CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT = 0x0 # macro +CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT = 0x8 # macro +CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT = 0x9 # macro +CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT = 0xa # macro +CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT = 0xb # macro +CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT = 0xc # macro +CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT = 0xd # macro +CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK = 0x00000007 # macro +CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK = 0x00000100 # macro +CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK = 0x00000200 # macro +CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK = 0x00000400 # macro +CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK = 0x00000800 # macro +CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK = 0x00001000 # macro +CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK = 0x00002000 # macro +CP_CPF_DSM_CNTL__CPF0_DSM_IRRITATOR_DATA__SHIFT = 0x0 # macro +CP_CPF_DSM_CNTL__CPF0_ENABLE_SINGLE_WRITE__SHIFT = 0x2 # macro +CP_CPF_DSM_CNTL__CPF1_DSM_IRRITATOR_DATA__SHIFT = 0x3 # macro +CP_CPF_DSM_CNTL__CPF1_ENABLE_SINGLE_WRITE__SHIFT = 0x5 # macro +CP_CPF_DSM_CNTL__CPF2_DSM_IRRITATOR_DATA__SHIFT = 0x6 # macro +CP_CPF_DSM_CNTL__CPF2_ENABLE_SINGLE_WRITE__SHIFT = 0x8 # macro +CP_CPF_DSM_CNTL__CPF0_DSM_IRRITATOR_DATA_MASK = 0x00000003 # macro +CP_CPF_DSM_CNTL__CPF0_ENABLE_SINGLE_WRITE_MASK = 0x00000004 # macro +CP_CPF_DSM_CNTL__CPF1_DSM_IRRITATOR_DATA_MASK = 0x00000018 # macro +CP_CPF_DSM_CNTL__CPF1_ENABLE_SINGLE_WRITE_MASK = 0x00000020 # macro +CP_CPF_DSM_CNTL__CPF2_DSM_IRRITATOR_DATA_MASK = 0x000000C0 # macro +CP_CPF_DSM_CNTL__CPF2_ENABLE_SINGLE_WRITE_MASK = 0x00000100 # macro +CP_CPG_DSM_CNTL__CPG0_DSM_IRRITATOR_DATA__SHIFT = 0x0 # macro +CP_CPG_DSM_CNTL__CPG0_ENABLE_SINGLE_WRITE__SHIFT = 0x2 # macro +CP_CPG_DSM_CNTL__CPG1_DSM_IRRITATOR_DATA__SHIFT = 0x3 # macro +CP_CPG_DSM_CNTL__CPG1_ENABLE_SINGLE_WRITE__SHIFT = 0x5 # macro +CP_CPG_DSM_CNTL__CPG2_DSM_IRRITATOR_DATA__SHIFT = 0x6 # macro +CP_CPG_DSM_CNTL__CPG2_ENABLE_SINGLE_WRITE__SHIFT = 0x8 # macro +CP_CPG_DSM_CNTL__CPG0_DSM_IRRITATOR_DATA_MASK = 0x00000003 # macro +CP_CPG_DSM_CNTL__CPG0_ENABLE_SINGLE_WRITE_MASK = 0x00000004 # macro +CP_CPG_DSM_CNTL__CPG1_DSM_IRRITATOR_DATA_MASK = 0x00000018 # macro +CP_CPG_DSM_CNTL__CPG1_ENABLE_SINGLE_WRITE_MASK = 0x00000020 # macro +CP_CPG_DSM_CNTL__CPG2_DSM_IRRITATOR_DATA_MASK = 0x000000C0 # macro +CP_CPG_DSM_CNTL__CPG2_ENABLE_SINGLE_WRITE_MASK = 0x00000100 # macro +CP_CPC_DSM_CNTL__CPC0_DSM_IRRITATOR_DATA__SHIFT = 0x0 # macro +CP_CPC_DSM_CNTL__CPC0_ENABLE_SINGLE_WRITE__SHIFT = 0x2 # macro +CP_CPC_DSM_CNTL__CPC1_DSM_IRRITATOR_DATA__SHIFT = 0x3 # macro +CP_CPC_DSM_CNTL__CPC1_ENABLE_SINGLE_WRITE__SHIFT = 0x5 # macro +CP_CPC_DSM_CNTL__CPC2_DSM_IRRITATOR_DATA__SHIFT = 0x6 # macro +CP_CPC_DSM_CNTL__CPC2_ENABLE_SINGLE_WRITE__SHIFT = 0x8 # macro +CP_CPC_DSM_CNTL__CPC3_DSM_IRRITATOR_DATA__SHIFT = 0x9 # macro +CP_CPC_DSM_CNTL__CPC3_ENABLE_SINGLE_WRITE__SHIFT = 0xb # macro +CP_CPC_DSM_CNTL__CPC4_DSM_IRRITATOR_DATA__SHIFT = 0xc # macro +CP_CPC_DSM_CNTL__CPC4_ENABLE_SINGLE_WRITE__SHIFT = 0xe # macro +CP_CPC_DSM_CNTL__CPC5_DSM_IRRITATOR_DATA__SHIFT = 0xf # macro +CP_CPC_DSM_CNTL__CPC5_ENABLE_SINGLE_WRITE__SHIFT = 0x11 # macro +CP_CPC_DSM_CNTL__CPC6_DSM_IRRITATOR_DATA__SHIFT = 0x12 # macro +CP_CPC_DSM_CNTL__CPC6_ENABLE_SINGLE_WRITE__SHIFT = 0x14 # macro +CP_CPC_DSM_CNTL__CPC7_DSM_IRRITATOR_DATA__SHIFT = 0x15 # macro +CP_CPC_DSM_CNTL__CPC7_ENABLE_SINGLE_WRITE__SHIFT = 0x17 # macro +CP_CPC_DSM_CNTL__CPC8_DSM_IRRITATOR_DATA__SHIFT = 0x18 # macro +CP_CPC_DSM_CNTL__CPC8_ENABLE_SINGLE_WRITE__SHIFT = 0x1a # macro +CP_CPC_DSM_CNTL__CPC0_DSM_IRRITATOR_DATA_MASK = 0x00000003 # macro +CP_CPC_DSM_CNTL__CPC0_ENABLE_SINGLE_WRITE_MASK = 0x00000004 # macro +CP_CPC_DSM_CNTL__CPC1_DSM_IRRITATOR_DATA_MASK = 0x00000018 # macro +CP_CPC_DSM_CNTL__CPC1_ENABLE_SINGLE_WRITE_MASK = 0x00000020 # macro +CP_CPC_DSM_CNTL__CPC2_DSM_IRRITATOR_DATA_MASK = 0x000000C0 # macro +CP_CPC_DSM_CNTL__CPC2_ENABLE_SINGLE_WRITE_MASK = 0x00000100 # macro +CP_CPC_DSM_CNTL__CPC3_DSM_IRRITATOR_DATA_MASK = 0x00000600 # macro +CP_CPC_DSM_CNTL__CPC3_ENABLE_SINGLE_WRITE_MASK = 0x00000800 # macro +CP_CPC_DSM_CNTL__CPC4_DSM_IRRITATOR_DATA_MASK = 0x00003000 # macro +CP_CPC_DSM_CNTL__CPC4_ENABLE_SINGLE_WRITE_MASK = 0x00004000 # macro +CP_CPC_DSM_CNTL__CPC5_DSM_IRRITATOR_DATA_MASK = 0x00018000 # macro +CP_CPC_DSM_CNTL__CPC5_ENABLE_SINGLE_WRITE_MASK = 0x00020000 # macro +CP_CPC_DSM_CNTL__CPC6_DSM_IRRITATOR_DATA_MASK = 0x000C0000 # macro +CP_CPC_DSM_CNTL__CPC6_ENABLE_SINGLE_WRITE_MASK = 0x00100000 # macro +CP_CPC_DSM_CNTL__CPC7_DSM_IRRITATOR_DATA_MASK = 0x00600000 # macro +CP_CPC_DSM_CNTL__CPC7_ENABLE_SINGLE_WRITE_MASK = 0x00800000 # macro +CP_CPC_DSM_CNTL__CPC8_DSM_IRRITATOR_DATA_MASK = 0x03000000 # macro +CP_CPC_DSM_CNTL__CPC8_ENABLE_SINGLE_WRITE_MASK = 0x04000000 # macro +CP_CPF_DSM_CNTL2__CPF0_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +CP_CPF_DSM_CNTL2__CPF0_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +CP_CPF_DSM_CNTL2__CPF1_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +CP_CPF_DSM_CNTL2__CPF1_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +CP_CPF_DSM_CNTL2__CPF2_ENABLE_ERROR_INJECT__SHIFT = 0x6 # macro +CP_CPF_DSM_CNTL2__CPF2_SELECT_INJECT_DELAY__SHIFT = 0x8 # macro +CP_CPF_DSM_CNTL2__CPF0_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +CP_CPF_DSM_CNTL2__CPF0_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +CP_CPF_DSM_CNTL2__CPF1_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +CP_CPF_DSM_CNTL2__CPF1_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +CP_CPF_DSM_CNTL2__CPF2_ENABLE_ERROR_INJECT_MASK = 0x000000C0 # macro +CP_CPF_DSM_CNTL2__CPF2_SELECT_INJECT_DELAY_MASK = 0x00000100 # macro +CP_CPG_DSM_CNTL2__CPG0_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +CP_CPG_DSM_CNTL2__CPG0_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +CP_CPG_DSM_CNTL2__CPG1_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +CP_CPG_DSM_CNTL2__CPG1_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +CP_CPG_DSM_CNTL2__CPG2_ENABLE_ERROR_INJECT__SHIFT = 0x6 # macro +CP_CPG_DSM_CNTL2__CPG2_SELECT_INJECT_DELAY__SHIFT = 0x8 # macro +CP_CPG_DSM_CNTL2__CPG0_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +CP_CPG_DSM_CNTL2__CPG0_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +CP_CPG_DSM_CNTL2__CPG1_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +CP_CPG_DSM_CNTL2__CPG1_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +CP_CPG_DSM_CNTL2__CPG2_ENABLE_ERROR_INJECT_MASK = 0x000000C0 # macro +CP_CPG_DSM_CNTL2__CPG2_SELECT_INJECT_DELAY_MASK = 0x00000100 # macro +CP_CPC_DSM_CNTL2__CPC0_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +CP_CPC_DSM_CNTL2__CPC0_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +CP_CPC_DSM_CNTL2__CPC1_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +CP_CPC_DSM_CNTL2__CPC1_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +CP_CPC_DSM_CNTL2__CPC2_ENABLE_ERROR_INJECT__SHIFT = 0x6 # macro +CP_CPC_DSM_CNTL2__CPC2_SELECT_INJECT_DELAY__SHIFT = 0x8 # macro +CP_CPC_DSM_CNTL2__CPC3_ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +CP_CPC_DSM_CNTL2__CPC3_SELECT_INJECT_DELAY__SHIFT = 0xb # macro +CP_CPC_DSM_CNTL2__CPC4_ENABLE_ERROR_INJECT__SHIFT = 0xc # macro +CP_CPC_DSM_CNTL2__CPC4_SELECT_INJECT_DELAY__SHIFT = 0xe # macro +CP_CPC_DSM_CNTL2__CPC5_ENABLE_ERROR_INJECT__SHIFT = 0xf # macro +CP_CPC_DSM_CNTL2__CPC5_SELECT_INJECT_DELAY__SHIFT = 0x11 # macro +CP_CPC_DSM_CNTL2__CPC6_ENABLE_ERROR_INJECT__SHIFT = 0x12 # macro +CP_CPC_DSM_CNTL2__CPC6_SELECT_INJECT_DELAY__SHIFT = 0x14 # macro +CP_CPC_DSM_CNTL2__CPC7_ENABLE_ERROR_INJECT__SHIFT = 0x15 # macro +CP_CPC_DSM_CNTL2__CPC7_SELECT_INJECT_DELAY__SHIFT = 0x17 # macro +CP_CPC_DSM_CNTL2__CPC8_ENABLE_ERROR_INJECT__SHIFT = 0x18 # macro +CP_CPC_DSM_CNTL2__CPC8_SELECT_INJECT_DELAY__SHIFT = 0x1a # macro +CP_CPC_DSM_CNTL2__CPC0_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +CP_CPC_DSM_CNTL2__CPC0_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +CP_CPC_DSM_CNTL2__CPC1_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +CP_CPC_DSM_CNTL2__CPC1_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +CP_CPC_DSM_CNTL2__CPC2_ENABLE_ERROR_INJECT_MASK = 0x000000C0 # macro +CP_CPC_DSM_CNTL2__CPC2_SELECT_INJECT_DELAY_MASK = 0x00000100 # macro +CP_CPC_DSM_CNTL2__CPC3_ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +CP_CPC_DSM_CNTL2__CPC3_SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +CP_CPC_DSM_CNTL2__CPC4_ENABLE_ERROR_INJECT_MASK = 0x00003000 # macro +CP_CPC_DSM_CNTL2__CPC4_SELECT_INJECT_DELAY_MASK = 0x00004000 # macro +CP_CPC_DSM_CNTL2__CPC5_ENABLE_ERROR_INJECT_MASK = 0x00018000 # macro +CP_CPC_DSM_CNTL2__CPC5_SELECT_INJECT_DELAY_MASK = 0x00020000 # macro +CP_CPC_DSM_CNTL2__CPC6_ENABLE_ERROR_INJECT_MASK = 0x000C0000 # macro +CP_CPC_DSM_CNTL2__CPC6_SELECT_INJECT_DELAY_MASK = 0x00100000 # macro +CP_CPC_DSM_CNTL2__CPC7_ENABLE_ERROR_INJECT_MASK = 0x00600000 # macro +CP_CPC_DSM_CNTL2__CPC7_SELECT_INJECT_DELAY_MASK = 0x00800000 # macro +CP_CPC_DSM_CNTL2__CPC8_ENABLE_ERROR_INJECT_MASK = 0x03000000 # macro +CP_CPC_DSM_CNTL2__CPC8_SELECT_INJECT_DELAY_MASK = 0x04000000 # macro +CP_CPF_DSM_CNTL2A__CPF_INJECT_DELAY__SHIFT = 0x0 # macro +CP_CPF_DSM_CNTL2A__CPF_INJECT_DELAY_MASK = 0x0000003F # macro +CP_CPG_DSM_CNTL2A__CPG_INJECT_DELAY__SHIFT = 0x0 # macro +CP_CPG_DSM_CNTL2A__CPG_INJECT_DELAY_MASK = 0x0000003F # macro +CP_CPC_DSM_CNTL2A__CPC_INJECT_DELAY__SHIFT = 0x0 # macro +CP_CPC_DSM_CNTL2A__CPC_INJECT_DELAY_MASK = 0x0000003F # macro +CP_EDC_FUE_CNTL__CP_FUE_MASK__SHIFT = 0x0 # macro +CP_EDC_FUE_CNTL__SPI_FUE_MASK__SHIFT = 0x1 # macro +CP_EDC_FUE_CNTL__GDS_FUE_MASK__SHIFT = 0x2 # macro +CP_EDC_FUE_CNTL__TC_RLC_FUE_MASK__SHIFT = 0x3 # macro +CP_EDC_FUE_CNTL__TC_CPG_FUE_MASK__SHIFT = 0x4 # macro +CP_EDC_FUE_CNTL__TCA_FUE_MASK__SHIFT = 0x5 # macro +CP_EDC_FUE_CNTL__TCC_FUE_MASK__SHIFT = 0x6 # macro +CP_EDC_FUE_CNTL__UTCL2_FUE_MASK__SHIFT = 0x7 # macro +CP_EDC_FUE_CNTL__CP_FUE_FLAG__SHIFT = 0x10 # macro +CP_EDC_FUE_CNTL__SPI_FUE_FLAG__SHIFT = 0x11 # macro +CP_EDC_FUE_CNTL__GDS_FUE_FLAG__SHIFT = 0x12 # macro +CP_EDC_FUE_CNTL__TC_RLC_FUE_FLAG__SHIFT = 0x13 # macro +CP_EDC_FUE_CNTL__TC_CPG_FUE_FLAG__SHIFT = 0x14 # macro +CP_EDC_FUE_CNTL__TCA_FUE_FLAG__SHIFT = 0x15 # macro +CP_EDC_FUE_CNTL__TCC_FUE_FLAG__SHIFT = 0x16 # macro +CP_EDC_FUE_CNTL__UTCL2_FUE_FLAG__SHIFT = 0x17 # macro +CP_EDC_FUE_CNTL__CP_FUE_MASK_MASK = 0x00000001 # macro +CP_EDC_FUE_CNTL__SPI_FUE_MASK_MASK = 0x00000002 # macro +CP_EDC_FUE_CNTL__GDS_FUE_MASK_MASK = 0x00000004 # macro +CP_EDC_FUE_CNTL__TC_RLC_FUE_MASK_MASK = 0x00000008 # macro +CP_EDC_FUE_CNTL__TC_CPG_FUE_MASK_MASK = 0x00000010 # macro +CP_EDC_FUE_CNTL__TCA_FUE_MASK_MASK = 0x00000020 # macro +CP_EDC_FUE_CNTL__TCC_FUE_MASK_MASK = 0x00000040 # macro +CP_EDC_FUE_CNTL__UTCL2_FUE_MASK_MASK = 0x00000080 # macro +CP_EDC_FUE_CNTL__CP_FUE_FLAG_MASK = 0x00010000 # macro +CP_EDC_FUE_CNTL__SPI_FUE_FLAG_MASK = 0x00020000 # macro +CP_EDC_FUE_CNTL__GDS_FUE_FLAG_MASK = 0x00040000 # macro +CP_EDC_FUE_CNTL__TC_RLC_FUE_FLAG_MASK = 0x00080000 # macro +CP_EDC_FUE_CNTL__TC_CPG_FUE_FLAG_MASK = 0x00100000 # macro +CP_EDC_FUE_CNTL__TCA_FUE_FLAG_MASK = 0x00200000 # macro +CP_EDC_FUE_CNTL__TCC_FUE_FLAG_MASK = 0x00400000 # macro +CP_EDC_FUE_CNTL__UTCL2_FUE_FLAG_MASK = 0x00800000 # macro +CP_GFX_MQD_CONTROL__VMID__SHIFT = 0x0 # macro +CP_GFX_MQD_CONTROL__PRIV_STATE__SHIFT = 0x8 # macro +CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT = 0x17 # macro +CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_GFX_MQD_CONTROL__VMID_MASK = 0x0000000F # macro +CP_GFX_MQD_CONTROL__PRIV_STATE_MASK = 0x00000100 # macro +CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK = 0x00800000 # macro +CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK = 0x01000000 # macro +CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT = 0x2 # macro +CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFFFFC # macro +CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT = 0x0 # macro +CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK = 0x0000FFFF # macro +CP_RB_STATUS__DOORBELL_UPDATED__SHIFT = 0x0 # macro +CP_RB_STATUS__DOORBELL_ENABLE__SHIFT = 0x1 # macro +CP_RB_STATUS__DOORBELL_UPDATED_MASK = 0x00000001 # macro +CP_RB_STATUS__DOORBELL_ENABLE_MASK = 0x00000002 # macro +CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT = 0x0 # macro +CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT = 0x1 # macro +CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT = 0x2 # macro +CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT = 0x8 # macro +CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT = 0x10 # macro +CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT = 0x18 # macro +CPG_UTCL1_STATUS__FAULT_DETECTED_MASK = 0x00000001 # macro +CPG_UTCL1_STATUS__RETRY_DETECTED_MASK = 0x00000002 # macro +CPG_UTCL1_STATUS__PRT_DETECTED_MASK = 0x00000004 # macro +CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK = 0x00003F00 # macro +CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK = 0x003F0000 # macro +CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK = 0x3F000000 # macro +CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT = 0x0 # macro +CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT = 0x1 # macro +CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT = 0x2 # macro +CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT = 0x8 # macro +CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT = 0x10 # macro +CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT = 0x18 # macro +CPC_UTCL1_STATUS__FAULT_DETECTED_MASK = 0x00000001 # macro +CPC_UTCL1_STATUS__RETRY_DETECTED_MASK = 0x00000002 # macro +CPC_UTCL1_STATUS__PRT_DETECTED_MASK = 0x00000004 # macro +CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK = 0x00003F00 # macro +CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK = 0x003F0000 # macro +CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK = 0x3F000000 # macro +CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT = 0x0 # macro +CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT = 0x1 # macro +CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT = 0x2 # macro +CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT = 0x8 # macro +CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT = 0x10 # macro +CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT = 0x18 # macro +CPF_UTCL1_STATUS__FAULT_DETECTED_MASK = 0x00000001 # macro +CPF_UTCL1_STATUS__RETRY_DETECTED_MASK = 0x00000002 # macro +CPF_UTCL1_STATUS__PRT_DETECTED_MASK = 0x00000004 # macro +CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK = 0x00003F00 # macro +CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK = 0x003F0000 # macro +CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK = 0x3F000000 # macro +CP_SD_CNTL__CPF_EN__SHIFT = 0x0 # macro +CP_SD_CNTL__CPG_EN__SHIFT = 0x1 # macro +CP_SD_CNTL__CPC_EN__SHIFT = 0x2 # macro +CP_SD_CNTL__RLC_EN__SHIFT = 0x3 # macro +CP_SD_CNTL__SPI_EN__SHIFT = 0x4 # macro +CP_SD_CNTL__WD_EN__SHIFT = 0x5 # macro +CP_SD_CNTL__IA_EN__SHIFT = 0x6 # macro +CP_SD_CNTL__PA_EN__SHIFT = 0x7 # macro +CP_SD_CNTL__RMI_EN__SHIFT = 0x8 # macro +CP_SD_CNTL__EA_EN__SHIFT = 0x9 # macro +CP_SD_CNTL__CPF_EN_MASK = 0x00000001 # macro +CP_SD_CNTL__CPG_EN_MASK = 0x00000002 # macro +CP_SD_CNTL__CPC_EN_MASK = 0x00000004 # macro +CP_SD_CNTL__RLC_EN_MASK = 0x00000008 # macro +CP_SD_CNTL__SPI_EN_MASK = 0x00000010 # macro +CP_SD_CNTL__WD_EN_MASK = 0x00000020 # macro +CP_SD_CNTL__IA_EN_MASK = 0x00000040 # macro +CP_SD_CNTL__PA_EN_MASK = 0x00000080 # macro +CP_SD_CNTL__RMI_EN_MASK = 0x00000100 # macro +CP_SD_CNTL__EA_EN_MASK = 0x00000200 # macro +CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT = 0x0 # macro +CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT = 0x1 # macro +CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT = 0x2 # macro +CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT = 0x3 # macro +CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT = 0x4 # macro +CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT = 0x5 # macro +CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT = 0x6 # macro +CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK = 0x00000001 # macro +CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK = 0x00000002 # macro +CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK = 0x00000004 # macro +CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK = 0x00000008 # macro +CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK = 0x00000010 # macro +CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK = 0x00000020 # macro +CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK = 0x00000040 # macro +CP_CPC_GFX_CNTL__QUEUEID__SHIFT = 0x0 # macro +CP_CPC_GFX_CNTL__PIPEID__SHIFT = 0x3 # macro +CP_CPC_GFX_CNTL__MEID__SHIFT = 0x5 # macro +CP_CPC_GFX_CNTL__VALID__SHIFT = 0x7 # macro +CP_CPC_GFX_CNTL__QUEUEID_MASK = 0x00000007 # macro +CP_CPC_GFX_CNTL__PIPEID_MASK = 0x00000018 # macro +CP_CPC_GFX_CNTL__MEID_MASK = 0x00000060 # macro +CP_CPC_GFX_CNTL__VALID_MASK = 0x00000080 # macro +SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT = 0x0 # macro +SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT = 0x3 # macro +SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT = 0x6 # macro +SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT = 0x9 # macro +SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT = 0xc # macro +SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT = 0xe # macro +SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT = 0x10 # macro +SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT = 0x12 # macro +SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK = 0x00000007 # macro +SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK = 0x00000038 # macro +SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK = 0x000001C0 # macro +SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK = 0x00000E00 # macro +SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK = 0x00003000 # macro +SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK = 0x0000C000 # macro +SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK = 0x00030000 # macro +SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK = 0x000C0000 # macro +SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT = 0x0 # macro +SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT = 0x10 # macro +SPI_ARB_CYCLES_0__TS0_DURATION_MASK = 0x0000FFFF # macro +SPI_ARB_CYCLES_0__TS1_DURATION_MASK = 0xFFFF0000 # macro +SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT = 0x0 # macro +SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT = 0x10 # macro +SPI_ARB_CYCLES_1__TS2_DURATION_MASK = 0x0000FFFF # macro +SPI_ARB_CYCLES_1__TS3_DURATION_MASK = 0xFFFF0000 # macro +SPI_CDBG_SYS_GFX__PS_EN__SHIFT = 0x0 # macro +SPI_CDBG_SYS_GFX__VS_EN__SHIFT = 0x1 # macro +SPI_CDBG_SYS_GFX__GS_EN__SHIFT = 0x2 # macro +SPI_CDBG_SYS_GFX__ES_EN__SHIFT = 0x3 # macro +SPI_CDBG_SYS_GFX__HS_EN__SHIFT = 0x4 # macro +SPI_CDBG_SYS_GFX__LS_EN__SHIFT = 0x5 # macro +SPI_CDBG_SYS_GFX__CS_EN__SHIFT = 0x6 # macro +SPI_CDBG_SYS_GFX__PS_EN_MASK = 0x0001 # macro +SPI_CDBG_SYS_GFX__VS_EN_MASK = 0x0002 # macro +SPI_CDBG_SYS_GFX__GS_EN_MASK = 0x0004 # macro +SPI_CDBG_SYS_GFX__ES_EN_MASK = 0x0008 # macro +SPI_CDBG_SYS_GFX__HS_EN_MASK = 0x0010 # macro +SPI_CDBG_SYS_GFX__LS_EN_MASK = 0x0020 # macro +SPI_CDBG_SYS_GFX__CS_EN_MASK = 0x0040 # macro +SPI_CDBG_SYS_HP3D__PS_EN__SHIFT = 0x0 # macro +SPI_CDBG_SYS_HP3D__VS_EN__SHIFT = 0x1 # macro +SPI_CDBG_SYS_HP3D__GS_EN__SHIFT = 0x2 # macro +SPI_CDBG_SYS_HP3D__ES_EN__SHIFT = 0x3 # macro +SPI_CDBG_SYS_HP3D__HS_EN__SHIFT = 0x4 # macro +SPI_CDBG_SYS_HP3D__LS_EN__SHIFT = 0x5 # macro +SPI_CDBG_SYS_HP3D__PS_EN_MASK = 0x0001 # macro +SPI_CDBG_SYS_HP3D__VS_EN_MASK = 0x0002 # macro +SPI_CDBG_SYS_HP3D__GS_EN_MASK = 0x0004 # macro +SPI_CDBG_SYS_HP3D__ES_EN_MASK = 0x0008 # macro +SPI_CDBG_SYS_HP3D__HS_EN_MASK = 0x0010 # macro +SPI_CDBG_SYS_HP3D__LS_EN_MASK = 0x0020 # macro +SPI_CDBG_SYS_CS0__PIPE0__SHIFT = 0x0 # macro +SPI_CDBG_SYS_CS0__PIPE1__SHIFT = 0x8 # macro +SPI_CDBG_SYS_CS0__PIPE2__SHIFT = 0x10 # macro +SPI_CDBG_SYS_CS0__PIPE3__SHIFT = 0x18 # macro +SPI_CDBG_SYS_CS0__PIPE0_MASK = 0x000000FF # macro +SPI_CDBG_SYS_CS0__PIPE1_MASK = 0x0000FF00 # macro +SPI_CDBG_SYS_CS0__PIPE2_MASK = 0x00FF0000 # macro +SPI_CDBG_SYS_CS0__PIPE3_MASK = 0xFF000000 # macro +SPI_CDBG_SYS_CS1__PIPE0__SHIFT = 0x0 # macro +SPI_CDBG_SYS_CS1__PIPE1__SHIFT = 0x8 # macro +SPI_CDBG_SYS_CS1__PIPE2__SHIFT = 0x10 # macro +SPI_CDBG_SYS_CS1__PIPE3__SHIFT = 0x18 # macro +SPI_CDBG_SYS_CS1__PIPE0_MASK = 0x000000FF # macro +SPI_CDBG_SYS_CS1__PIPE1_MASK = 0x0000FF00 # macro +SPI_CDBG_SYS_CS1__PIPE2_MASK = 0x00FF0000 # macro +SPI_CDBG_SYS_CS1__PIPE3_MASK = 0xFF000000 # macro +SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT = 0x0 # macro +SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT = 0x7 # macro +SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT = 0xc # macro +SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT = 0x11 # macro +SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT = 0x16 # macro +SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK = 0x0000007F # macro +SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK = 0x00000F80 # macro +SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK = 0x0001F000 # macro +SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK = 0x003E0000 # macro +SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK = 0x07C00000 # macro +SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT = 0x0 # macro +SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT = 0xc # macro +SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT = 0x16 # macro +SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK = 0x0000007F # macro +SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK = 0x0001F000 # macro +SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK = 0x07C00000 # macro +SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT = 0x0 # macro +SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK = 0x7F # macro +SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT = 0x0 # macro +SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK = 0x7F # macro +SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT = 0x0 # macro +SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK = 0x7F # macro +SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT = 0x0 # macro +SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK = 0x7F # macro +SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT = 0x0 # macro +SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK = 0x7F # macro +SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT = 0x0 # macro +SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK = 0x7F # macro +SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT = 0x0 # macro +SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK = 0x7F # macro +SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT = 0x0 # macro +SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK = 0x7F # macro +SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT = 0x0 # macro +SPI_GDBG_WAVE_CNTL__STALL_RA_MASK = 0x01 # macro +SPI_GDBG_TRAP_CONFIG__PIPE0_EN__SHIFT = 0x0 # macro +SPI_GDBG_TRAP_CONFIG__PIPE1_EN__SHIFT = 0x8 # macro +SPI_GDBG_TRAP_CONFIG__PIPE2_EN__SHIFT = 0x10 # macro +SPI_GDBG_TRAP_CONFIG__PIPE3_EN__SHIFT = 0x18 # macro +SPI_GDBG_TRAP_CONFIG__PIPE0_EN_MASK = 0x000000FF # macro +SPI_GDBG_TRAP_CONFIG__PIPE1_EN_MASK = 0x0000FF00 # macro +SPI_GDBG_TRAP_CONFIG__PIPE2_EN_MASK = 0x00FF0000 # macro +SPI_GDBG_TRAP_CONFIG__PIPE3_EN_MASK = 0xFF000000 # macro +SPI_GDBG_PER_VMID_CNTL__STALL_VMID__SHIFT = 0x0 # macro +SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE__SHIFT = 0x1 # macro +SPI_GDBG_PER_VMID_CNTL__TRAP_EN__SHIFT = 0x3 # macro +SPI_GDBG_PER_VMID_CNTL__EXCP_EN__SHIFT = 0x4 # macro +SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE__SHIFT = 0xd # macro +SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START__SHIFT = 0xe # macro +SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END__SHIFT = 0xf # macro +SPI_GDBG_PER_VMID_CNTL__STALL_VMID_MASK = 0x0001 # macro +SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE_MASK = 0x0006 # macro +SPI_GDBG_PER_VMID_CNTL__TRAP_EN_MASK = 0x0008 # macro +SPI_GDBG_PER_VMID_CNTL__EXCP_EN_MASK = 0x1FF0 # macro +SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE_MASK = 0x2000 # macro +SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START_MASK = 0x4000 # macro +SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END_MASK = 0x8000 # macro +SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT = 0x0 # macro +SPI_GDBG_WAVE_CNTL3__STALL_VS__SHIFT = 0x1 # macro +SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT = 0x2 # macro +SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT = 0x3 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT = 0x4 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT = 0x5 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT = 0x6 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT = 0x7 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT = 0x8 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT = 0x9 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT = 0xa # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT = 0xb # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT = 0xc # macro +SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT = 0xd # macro +SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT = 0x1c # macro +SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK = 0x00000001 # macro +SPI_GDBG_WAVE_CNTL3__STALL_VS_MASK = 0x00000002 # macro +SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK = 0x00000004 # macro +SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK = 0x00000008 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK = 0x00000010 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK = 0x00000020 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK = 0x00000040 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK = 0x00000080 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK = 0x00000100 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK = 0x00000200 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK = 0x00000400 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK = 0x00000800 # macro +SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK = 0x00001000 # macro +SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK = 0x0FFFE000 # macro +SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK = 0x10000000 # macro +SPI_SCRATCH_ADDR_CHECK__RESERVED__SHIFT = 0x0 # macro +SPI_SCRATCH_ADDR_CHECK__RESERVED_MASK = 0x0F # macro +SPI_SCRATCH_ADDR_STATUS__WRITE_DIS__SHIFT = 0x0 # macro +SPI_SCRATCH_ADDR_STATUS__OVERFLOW_DETECTED__SHIFT = 0x1 # macro +SPI_SCRATCH_ADDR_STATUS__ME_ID__SHIFT = 0x2 # macro +SPI_SCRATCH_ADDR_STATUS__PIPE_ID__SHIFT = 0x4 # macro +SPI_SCRATCH_ADDR_STATUS__WRITE_DIS_MASK = 0x01 # macro +SPI_SCRATCH_ADDR_STATUS__OVERFLOW_DETECTED_MASK = 0x02 # macro +SPI_SCRATCH_ADDR_STATUS__ME_ID_MASK = 0x0C # macro +SPI_SCRATCH_ADDR_STATUS__PIPE_ID_MASK = 0x30 # macro +SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT = 0x0 # macro +SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT = 0x1 # macro +SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT = 0x2 # macro +SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT = 0x3 # macro +SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT = 0x4 # macro +SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK = 0x01 # macro +SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK = 0x02 # macro +SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK = 0x04 # macro +SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK = 0x08 # macro +SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK = 0x10 # macro +SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT = 0x0 # macro +SPI_COMPUTE_QUEUE_RESET__RESET_MASK = 0x01 # macro +SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_0__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_1__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_2__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_3__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_4__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_5__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_6__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_7__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_8__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_9__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT = 0x18 # macro +SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK = 0x01000000 # macro +SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT = 0x18 # macro +SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK = 0x01000000 # macro +SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT = 0x18 # macro +SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK = 0x01000000 # macro +SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT = 0x18 # macro +SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK = 0x01000000 # macro +SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT = 0x18 # macro +SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK = 0x01000000 # macro +SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT = 0x18 # macro +SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK = 0x01000000 # macro +SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT = 0x18 # macro +SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK = 0x01000000 # macro +SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT = 0x18 # macro +SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK = 0x01000000 # macro +SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT = 0x18 # macro +SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK = 0x01000000 # macro +SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT = 0x18 # macro +SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK = 0x01000000 # macro +SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_10__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_11__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT = 0x18 # macro +SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK = 0x01000000 # macro +SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT = 0x18 # macro +SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK = 0x01000000 # macro +SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_12__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_13__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_14__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT = 0x4 # macro +SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT = 0x8 # macro +SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT = 0xc # macro +SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT = 0xf # macro +SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK = 0x0000000F # macro +SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK = 0x000000F0 # macro +SPI_RESOURCE_RESERVE_CU_15__LDS_MASK = 0x00000F00 # macro +SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK = 0x00007000 # macro +SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK = 0x00078000 # macro +SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT = 0x18 # macro +SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK = 0x01000000 # macro +SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT = 0x18 # macro +SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK = 0x01000000 # macro +SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT = 0x18 # macro +SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK = 0x01000000 # macro +SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT = 0x0 # macro +SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT = 0x1 # macro +SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT = 0x10 # macro +SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT = 0x18 # macro +SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK = 0x00000001 # macro +SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK = 0x0000FFFE # macro +SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK = 0x00FF0000 # macro +SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK = 0x01000000 # macro +SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT = 0x0 # macro +SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT = 0x1 # macro +SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT = 0x2 # macro +SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT = 0x1e # macro +SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT = 0x1f # macro +SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK = 0x00000001 # macro +SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK = 0x00000002 # macro +SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK = 0x00000004 # macro +SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK = 0x40000000 # macro +SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK = 0x80000000 # macro +SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT = 0x0 # macro +SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT = 0x4 # macro +SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT = 0x8 # macro +SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK = 0x0000000F # macro +SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK = 0x000000F0 # macro +SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK = 0x00000F00 # macro +CP_HQD_GFX_CONTROL__MESSAGE__SHIFT = 0x0 # macro +CP_HQD_GFX_CONTROL__MISC__SHIFT = 0x4 # macro +CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT = 0xf # macro +CP_HQD_GFX_CONTROL__MESSAGE_MASK = 0x0000000F # macro +CP_HQD_GFX_CONTROL__MISC_MASK = 0x00007FF0 # macro +CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK = 0x00008000 # macro +CP_HQD_GFX_STATUS__STATUS__SHIFT = 0x0 # macro +CP_HQD_GFX_STATUS__STATUS_MASK = 0x0000FFFF # macro +CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT = 0x0 # macro +CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT = 0x8 # macro +CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT = 0x10 # macro +CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK = 0x00000007 # macro +CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK = 0x00003F00 # macro +CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK = 0x003F0000 # macro +CP_HPD_STATUS0__QUEUE_STATE__SHIFT = 0x0 # macro +CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT = 0x5 # macro +CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT = 0x8 # macro +CP_HPD_STATUS0__FETCHING_MQD__SHIFT = 0x10 # macro +CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT = 0x11 # macro +CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT = 0x12 # macro +CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT = 0x14 # macro +CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK__SHIFT = 0x1d # macro +CP_HPD_STATUS0__FORCE_QUEUE__SHIFT = 0x1f # macro +CP_HPD_STATUS0__QUEUE_STATE_MASK = 0x0000001F # macro +CP_HPD_STATUS0__MAPPED_QUEUE_MASK = 0x000000E0 # macro +CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK = 0x0000FF00 # macro +CP_HPD_STATUS0__FETCHING_MQD_MASK = 0x00010000 # macro +CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK = 0x00020000 # macro +CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK = 0x00040000 # macro +CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK = 0x01F00000 # macro +CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK_MASK = 0x20000000 # macro +CP_HPD_STATUS0__FORCE_QUEUE_MASK = 0x80000000 # macro +CP_HPD_UTCL1_CNTL__SELECT__SHIFT = 0x0 # macro +CP_HPD_UTCL1_CNTL__SELECT_MASK = 0x0000000F # macro +CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT = 0x0 # macro +CP_HPD_UTCL1_ERROR__TYPE__SHIFT = 0x10 # macro +CP_HPD_UTCL1_ERROR__VMID__SHIFT = 0x14 # macro +CP_HPD_UTCL1_ERROR__ADDR_HI_MASK = 0x0000FFFF # macro +CP_HPD_UTCL1_ERROR__TYPE_MASK = 0x00010000 # macro +CP_HPD_UTCL1_ERROR__VMID_MASK = 0x00F00000 # macro +CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT = 0xc # macro +CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK = 0xFFFFF000 # macro +CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT = 0x2 # macro +CP_MQD_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFFFFC # macro +CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT = 0x0 # macro +CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK = 0x0000FFFF # macro +CP_HQD_ACTIVE__ACTIVE__SHIFT = 0x0 # macro +CP_HQD_ACTIVE__BUSY_GATE__SHIFT = 0x1 # macro +CP_HQD_ACTIVE__ACTIVE_MASK = 0x00000001 # macro +CP_HQD_ACTIVE__BUSY_GATE_MASK = 0x00000002 # macro +CP_HQD_VMID__VMID__SHIFT = 0x0 # macro +CP_HQD_VMID__IB_VMID__SHIFT = 0x8 # macro +CP_HQD_VMID__VQID__SHIFT = 0x10 # macro +CP_HQD_VMID__VMID_MASK = 0x0000000F # macro +CP_HQD_VMID__IB_VMID_MASK = 0x00000F00 # macro +CP_HQD_VMID__VQID_MASK = 0x03FF0000 # macro +CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT = 0x0 # macro +CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT = 0x8 # macro +CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT = 0x15 # macro +CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT = 0x16 # macro +CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT = 0x17 # macro +CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT = 0x18 # macro +CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT = 0x19 # macro +CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT = 0x1a # macro +CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT = 0x1b # macro +CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT = 0x1c # macro +CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT = 0x1d # macro +CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT = 0x1e # macro +CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT = 0x1f # macro +CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK = 0x00000001 # macro +CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK = 0x0003FF00 # macro +CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK = 0x00200000 # macro +CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK = 0x00400000 # macro +CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK = 0x00800000 # macro +CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK = 0x01000000 # macro +CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK = 0x02000000 # macro +CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK = 0x04000000 # macro +CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK = 0x08000000 # macro +CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK = 0x10000000 # macro +CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK = 0x20000000 # macro +CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK = 0x40000000 # macro +CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK = 0x80000000 # macro +CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT = 0x0 # macro +CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK = 0x00000003 # macro +CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT = 0x0 # macro +CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK = 0x0000000F # macro +CP_HQD_QUANTUM__QUANTUM_EN__SHIFT = 0x0 # macro +CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT = 0x4 # macro +CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT = 0x8 # macro +CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT = 0x1f # macro +CP_HQD_QUANTUM__QUANTUM_EN_MASK = 0x00000001 # macro +CP_HQD_QUANTUM__QUANTUM_SCALE_MASK = 0x00000010 # macro +CP_HQD_QUANTUM__QUANTUM_DURATION_MASK = 0x00003F00 # macro +CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK = 0x80000000 # macro +CP_HQD_PQ_BASE__ADDR__SHIFT = 0x0 # macro +CP_HQD_PQ_BASE__ADDR_MASK = 0xFFFFFFFF # macro +CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_HQD_PQ_BASE_HI__ADDR_HI_MASK = 0x000000FF # macro +CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT = 0x0 # macro +CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK = 0xFFFFFFFF # macro +CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT = 0x2 # macro +CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK = 0xFFFFFFFC # macro +CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT = 0x0 # macro +CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK = 0x0000FFFF # macro +CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT = 0x3 # macro +CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK = 0xFFFFFFF8 # macro +CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT = 0x0 # macro +CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK = 0x0000FFFF # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT = 0x0 # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT = 0x1 # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT = 0x2 # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT = 0x1c # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT = 0x1d # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT = 0x1e # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT = 0x1f # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK = 0x00000001 # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK = 0x00000002 # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK = 0x0FFFFFFC # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK = 0x10000000 # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK = 0x20000000 # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK = 0x40000000 # macro +CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK = 0x80000000 # macro +CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT = 0x0 # macro +CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT = 0x6 # macro +CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT = 0x7 # macro +CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT = 0x8 # macro +CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT = 0xe # macro +CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT = 0xf # macro +CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT = 0x10 # macro +CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT = 0x11 # macro +CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT = 0x14 # macro +CP_HQD_PQ_CONTROL__TMZ__SHIFT = 0x16 # macro +CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT = 0x17 # macro +CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT = 0x19 # macro +CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT = 0x1b # macro +CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT = 0x1c # macro +CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT = 0x1d # macro +CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT = 0x1e # macro +CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT = 0x1f # macro +CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK = 0x0000003F # macro +CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK = 0x00000040 # macro +CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK = 0x00000080 # macro +CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK = 0x00003F00 # macro +CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK = 0x00004000 # macro +CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK = 0x00008000 # macro +CP_HQD_PQ_CONTROL__WPP_CLAMP_EN_MASK = 0x00010000 # macro +CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK = 0x00060000 # macro +CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK = 0x00300000 # macro +CP_HQD_PQ_CONTROL__TMZ_MASK = 0x00400000 # macro +CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK = 0x00800000 # macro +CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK = 0x01000000 # macro +CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK = 0x06000000 # macro +CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK = 0x08000000 # macro +CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK = 0x10000000 # macro +CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK = 0x20000000 # macro +CP_HQD_PQ_CONTROL__PRIV_STATE_MASK = 0x40000000 # macro +CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK = 0x80000000 # macro +CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT = 0x2 # macro +CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK = 0xFFFFFFFC # macro +CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT = 0x0 # macro +CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK = 0x0000FFFF # macro +CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT = 0x0 # macro +CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK = 0x000FFFFF # macro +CP_HQD_IB_CONTROL__IB_SIZE__SHIFT = 0x0 # macro +CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT = 0x14 # macro +CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT = 0x17 # macro +CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT = 0x18 # macro +CP_HQD_IB_CONTROL__IB_PRIV_STATE__SHIFT = 0x1e # macro +CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT = 0x1f # macro +CP_HQD_IB_CONTROL__IB_SIZE_MASK = 0x000FFFFF # macro +CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK = 0x00300000 # macro +CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK = 0x00800000 # macro +CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK = 0x01000000 # macro +CP_HQD_IB_CONTROL__IB_PRIV_STATE_MASK = 0x40000000 # macro +CP_HQD_IB_CONTROL__PROCESSING_IB_MASK = 0x80000000 # macro +CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT = 0x0 # macro +CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT = 0x8 # macro +CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT = 0xb # macro +CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT = 0xc # macro +CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT = 0xe # macro +CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT = 0x10 # macro +CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT = 0x16 # macro +CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT = 0x17 # macro +CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT = 0x18 # macro +CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT = 0x19 # macro +CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT = 0x1c # macro +CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT = 0x1d # macro +CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT = 0x1e # macro +CP_HQD_IQ_TIMER__ACTIVE__SHIFT = 0x1f # macro +CP_HQD_IQ_TIMER__WAIT_TIME_MASK = 0x000000FF # macro +CP_HQD_IQ_TIMER__RETRY_TYPE_MASK = 0x00000700 # macro +CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK = 0x00000800 # macro +CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK = 0x00003000 # macro +CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK = 0x0000C000 # macro +CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK = 0x003F0000 # macro +CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK = 0x00400000 # macro +CP_HQD_IQ_TIMER__EXE_DISABLE_MASK = 0x00800000 # macro +CP_HQD_IQ_TIMER__CACHE_POLICY_MASK = 0x01000000 # macro +CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK = 0x02000000 # macro +CP_HQD_IQ_TIMER__REARM_TIMER_MASK = 0x10000000 # macro +CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK = 0x20000000 # macro +CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK = 0x40000000 # macro +CP_HQD_IQ_TIMER__ACTIVE_MASK = 0x80000000 # macro +CP_HQD_IQ_RPTR__OFFSET__SHIFT = 0x0 # macro +CP_HQD_IQ_RPTR__OFFSET_MASK = 0x0000003F # macro +CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT = 0x0 # macro +CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT = 0x4 # macro +CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT = 0x8 # macro +CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT = 0x9 # macro +CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT = 0xa # macro +CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK = 0x00000007 # macro +CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK = 0x00000010 # macro +CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK = 0x00000100 # macro +CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK = 0x00000200 # macro +CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK = 0x00000400 # macro +CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT = 0x0 # macro +CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK = 0x00000001 # macro +CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT = 0x0 # macro +CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT = 0x1 # macro +CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT = 0x2 # macro +CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT = 0x3 # macro +CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT = 0x4 # macro +CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT = 0x5 # macro +CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK = 0x00000001 # macro +CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK = 0x00000002 # macro +CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK = 0x00000004 # macro +CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK = 0x00000008 # macro +CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK = 0x00000010 # macro +CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK = 0x00000020 # macro +CP_HQD_SEMA_CMD__RETRY__SHIFT = 0x0 # macro +CP_HQD_SEMA_CMD__RESULT__SHIFT = 0x1 # macro +CP_HQD_SEMA_CMD__RETRY_MASK = 0x00000001 # macro +CP_HQD_SEMA_CMD__RESULT_MASK = 0x00000006 # macro +CP_HQD_MSG_TYPE__ACTION__SHIFT = 0x0 # macro +CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT = 0x4 # macro +CP_HQD_MSG_TYPE__ACTION_MASK = 0x00000007 # macro +CP_HQD_MSG_TYPE__SAVE_STATE_MASK = 0x00000070 # macro +CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT = 0x0 # macro +CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT = 0x0 # macro +CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT = 0x0 # macro +CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT = 0x0 # macro +CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT = 0x0 # macro +CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK = 0xFFFFFFFF # macro +CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT = 0x0 # macro +CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT = 0x2 # macro +CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT = 0x4 # macro +CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT = 0x7 # macro +CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT = 0x8 # macro +CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT = 0x9 # macro +CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT = 0xa # macro +CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT = 0x1e # macro +CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT = 0x1f # macro +CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK = 0x00000003 # macro +CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK = 0x0000000C # macro +CP_HQD_HQ_STATUS0__RSV_6_4_MASK = 0x00000070 # macro +CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK = 0x00000080 # macro +CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK = 0x00000100 # macro +CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK = 0x00000200 # macro +CP_HQD_HQ_STATUS0__RSVR_29_10_MASK = 0x3FFFFC00 # macro +CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK = 0x40000000 # macro +CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK = 0x80000000 # macro +CP_HQD_HQ_CONTROL0__CONTROL__SHIFT = 0x0 # macro +CP_HQD_HQ_CONTROL0__CONTROL_MASK = 0xFFFFFFFF # macro +CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT = 0x0 # macro +CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK = 0xFFFFFFFF # macro +CP_MQD_CONTROL__VMID__SHIFT = 0x0 # macro +CP_MQD_CONTROL__PRIV_STATE__SHIFT = 0x8 # macro +CP_MQD_CONTROL__PROCESSING_MQD__SHIFT = 0xc # macro +CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT = 0xd # macro +CP_MQD_CONTROL__EXE_DISABLE__SHIFT = 0x17 # macro +CP_MQD_CONTROL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_MQD_CONTROL__VMID_MASK = 0x0000000F # macro +CP_MQD_CONTROL__PRIV_STATE_MASK = 0x00000100 # macro +CP_MQD_CONTROL__PROCESSING_MQD_MASK = 0x00001000 # macro +CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK = 0x00002000 # macro +CP_MQD_CONTROL__EXE_DISABLE_MASK = 0x00800000 # macro +CP_MQD_CONTROL__CACHE_POLICY_MASK = 0x01000000 # macro +CP_HQD_HQ_STATUS1__STATUS__SHIFT = 0x0 # macro +CP_HQD_HQ_STATUS1__STATUS_MASK = 0xFFFFFFFF # macro +CP_HQD_HQ_CONTROL1__CONTROL__SHIFT = 0x0 # macro +CP_HQD_HQ_CONTROL1__CONTROL_MASK = 0xFFFFFFFF # macro +CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT = 0x0 # macro +CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFFFFF # macro +CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT = 0x0 # macro +CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK = 0x000000FF # macro +CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT = 0x0 # macro +CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT = 0x8 # macro +CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT = 0xc # macro +CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT = 0xd # macro +CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT = 0xe # macro +CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT = 0x15 # macro +CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT = 0x16 # macro +CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT = 0x17 # macro +CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT = 0x18 # macro +CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT = 0x1d # macro +CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT = 0x1f # macro +CP_HQD_EOP_CONTROL__EOP_SIZE_MASK = 0x0000003F # macro +CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK = 0x00000100 # macro +CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK = 0x00001000 # macro +CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK = 0x00002000 # macro +CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK = 0x00004000 # macro +CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK = 0x00200000 # macro +CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK = 0x00400000 # macro +CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK = 0x00800000 # macro +CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK = 0x01000000 # macro +CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK = 0x60000000 # macro +CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK = 0x80000000 # macro +CP_HQD_EOP_RPTR__RPTR__SHIFT = 0x0 # macro +CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT = 0x1c # macro +CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT = 0x1d # macro +CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT = 0x1e # macro +CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT = 0x1f # macro +CP_HQD_EOP_RPTR__RPTR_MASK = 0x00001FFF # macro +CP_HQD_EOP_RPTR__RESET_FETCHER_MASK = 0x10000000 # macro +CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK = 0x20000000 # macro +CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK = 0x40000000 # macro +CP_HQD_EOP_RPTR__INIT_FETCHER_MASK = 0x80000000 # macro +CP_HQD_EOP_WPTR__WPTR__SHIFT = 0x0 # macro +CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT = 0xf # macro +CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT = 0x10 # macro +CP_HQD_EOP_WPTR__WPTR_MASK = 0x00001FFF # macro +CP_HQD_EOP_WPTR__EOP_EMPTY_MASK = 0x00008000 # macro +CP_HQD_EOP_WPTR__EOP_AVAIL_MASK = 0x1FFF0000 # macro +CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT = 0x0 # macro +CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT = 0x10 # macro +CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK = 0x00000FFF # macro +CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK = 0x00010000 # macro +CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT = 0xc # macro +CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK = 0xFFFFF000 # macro +CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT = 0x3 # macro +CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT = 0x17 # macro +CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK = 0x00000008 # macro +CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK = 0x00800000 # macro +CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT = 0x2 # macro +CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK = 0x0000FFFC # macro +CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT = 0xc # macro +CP_HQD_CNTL_STACK_SIZE__SIZE_MASK = 0x0000F000 # macro +CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT = 0x2 # macro +CP_HQD_WG_STATE_OFFSET__OFFSET_MASK = 0x07FFFFFC # macro +CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT = 0xc # macro +CP_HQD_CTX_SAVE_SIZE__SIZE_MASK = 0x07FFF000 # macro +CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT = 0x0 # macro +CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT = 0x1 # macro +CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT = 0x4 # macro +CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT = 0xc # macro +CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK = 0x00000001 # macro +CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK = 0x00000002 # macro +CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK = 0x000003F0 # macro +CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK = 0x0003F000 # macro +CP_HQD_ERROR__EDC_ERROR_ID__SHIFT = 0x0 # macro +CP_HQD_ERROR__SUA_ERROR__SHIFT = 0x4 # macro +CP_HQD_ERROR__AQL_ERROR__SHIFT = 0x5 # macro +CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT = 0x8 # macro +CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT = 0x9 # macro +CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT = 0xa # macro +CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT = 0xb # macro +CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT = 0xc # macro +CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT = 0xd # macro +CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT = 0xe # macro +CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT = 0xf # macro +CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT = 0x10 # macro +CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT = 0x11 # macro +CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT = 0x12 # macro +CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT = 0x13 # macro +CP_HQD_ERROR__EDC_ERROR_ID_MASK = 0x0000000F # macro +CP_HQD_ERROR__SUA_ERROR_MASK = 0x00000010 # macro +CP_HQD_ERROR__AQL_ERROR_MASK = 0x00000020 # macro +CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK = 0x00000100 # macro +CP_HQD_ERROR__IB_UTCL1_ERROR_MASK = 0x00000200 # macro +CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK = 0x00000400 # macro +CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK = 0x00000800 # macro +CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK = 0x00001000 # macro +CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK = 0x00002000 # macro +CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK = 0x00004000 # macro +CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK = 0x00008000 # macro +CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK = 0x00010000 # macro +CP_HQD_ERROR__SR_UTCL1_ERROR_MASK = 0x00020000 # macro +CP_HQD_ERROR__QU_UTCL1_ERROR_MASK = 0x00040000 # macro +CP_HQD_ERROR__TC_UTCL1_ERROR_MASK = 0x00080000 # macro +CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT = 0x0 # macro +CP_HQD_EOP_WPTR_MEM__WPTR_MASK = 0x00001FFF # macro +CP_HQD_AQL_CONTROL__CONTROL0__SHIFT = 0x0 # macro +CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT = 0xf # macro +CP_HQD_AQL_CONTROL__CONTROL1__SHIFT = 0x10 # macro +CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT = 0x1f # macro +CP_HQD_AQL_CONTROL__CONTROL0_MASK = 0x00007FFF # macro +CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK = 0x00008000 # macro +CP_HQD_AQL_CONTROL__CONTROL1_MASK = 0x7FFF0000 # macro +CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK = 0x80000000 # macro +CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT = 0x0 # macro +CP_HQD_PQ_WPTR_LO__OFFSET_MASK = 0xFFFFFFFF # macro +CP_HQD_PQ_WPTR_HI__DATA__SHIFT = 0x0 # macro +CP_HQD_PQ_WPTR_HI__DATA_MASK = 0xFFFFFFFF # macro +CP_HQD_AQL_CONTROL_1__RESERVED__SHIFT = 0x0 # macro +CP_HQD_AQL_CONTROL_1__RESERVED_MASK = 0xFFFFFFFF # macro +CP_HQD_AQL_DISPATCH_ID__CONSUMED_OFFSET__SHIFT = 0x0 # macro +CP_HQD_AQL_DISPATCH_ID__CONSUMED_OFFSET_MASK = 0xFFFFFFFF # macro +CP_HQD_AQL_DISPATCH_ID_HI__CONSUMED_OFFSET__SHIFT = 0x0 # macro +CP_HQD_AQL_DISPATCH_ID_HI__CONSUMED_OFFSET_MASK = 0xFFFFFFFF # macro +TCP_WATCH0_ADDR_H__ADDR__SHIFT = 0x0 # macro +TCP_WATCH0_ADDR_H__ADDR_MASK = 0x0000FFFF # macro +TCP_WATCH0_ADDR_L__ADDR__SHIFT = 0x7 # macro +TCP_WATCH0_ADDR_L__ADDR_MASK = 0xFFFFFF80 # macro +TCP_WATCH0_CNTL__MASK__SHIFT = 0x0 # macro +TCP_WATCH0_CNTL__VMID__SHIFT = 0x18 # macro +TCP_WATCH0_CNTL__ATC__SHIFT = 0x1c # macro +TCP_WATCH0_CNTL__MODE__SHIFT = 0x1d # macro +TCP_WATCH0_CNTL__VALID__SHIFT = 0x1f # macro +TCP_WATCH0_CNTL__MASK_MASK = 0x00FFFFFF # macro +TCP_WATCH0_CNTL__VMID_MASK = 0x0F000000 # macro +TCP_WATCH0_CNTL__ATC_MASK = 0x10000000 # macro +TCP_WATCH0_CNTL__MODE_MASK = 0x60000000 # macro +TCP_WATCH0_CNTL__VALID_MASK = 0x80000000 # macro +TCP_WATCH1_ADDR_H__ADDR__SHIFT = 0x0 # macro +TCP_WATCH1_ADDR_H__ADDR_MASK = 0x0000FFFF # macro +TCP_WATCH1_ADDR_L__ADDR__SHIFT = 0x7 # macro +TCP_WATCH1_ADDR_L__ADDR_MASK = 0xFFFFFF80 # macro +TCP_WATCH1_CNTL__MASK__SHIFT = 0x0 # macro +TCP_WATCH1_CNTL__VMID__SHIFT = 0x18 # macro +TCP_WATCH1_CNTL__ATC__SHIFT = 0x1c # macro +TCP_WATCH1_CNTL__MODE__SHIFT = 0x1d # macro +TCP_WATCH1_CNTL__VALID__SHIFT = 0x1f # macro +TCP_WATCH1_CNTL__MASK_MASK = 0x00FFFFFF # macro +TCP_WATCH1_CNTL__VMID_MASK = 0x0F000000 # macro +TCP_WATCH1_CNTL__ATC_MASK = 0x10000000 # macro +TCP_WATCH1_CNTL__MODE_MASK = 0x60000000 # macro +TCP_WATCH1_CNTL__VALID_MASK = 0x80000000 # macro +TCP_WATCH2_ADDR_H__ADDR__SHIFT = 0x0 # macro +TCP_WATCH2_ADDR_H__ADDR_MASK = 0x0000FFFF # macro +TCP_WATCH2_ADDR_L__ADDR__SHIFT = 0x7 # macro +TCP_WATCH2_ADDR_L__ADDR_MASK = 0xFFFFFF80 # macro +TCP_WATCH2_CNTL__MASK__SHIFT = 0x0 # macro +TCP_WATCH2_CNTL__VMID__SHIFT = 0x18 # macro +TCP_WATCH2_CNTL__ATC__SHIFT = 0x1c # macro +TCP_WATCH2_CNTL__MODE__SHIFT = 0x1d # macro +TCP_WATCH2_CNTL__VALID__SHIFT = 0x1f # macro +TCP_WATCH2_CNTL__MASK_MASK = 0x00FFFFFF # macro +TCP_WATCH2_CNTL__VMID_MASK = 0x0F000000 # macro +TCP_WATCH2_CNTL__ATC_MASK = 0x10000000 # macro +TCP_WATCH2_CNTL__MODE_MASK = 0x60000000 # macro +TCP_WATCH2_CNTL__VALID_MASK = 0x80000000 # macro +TCP_WATCH3_ADDR_H__ADDR__SHIFT = 0x0 # macro +TCP_WATCH3_ADDR_H__ADDR_MASK = 0x0000FFFF # macro +TCP_WATCH3_ADDR_L__ADDR__SHIFT = 0x7 # macro +TCP_WATCH3_ADDR_L__ADDR_MASK = 0xFFFFFF80 # macro +TCP_WATCH3_CNTL__MASK__SHIFT = 0x0 # macro +TCP_WATCH3_CNTL__VMID__SHIFT = 0x18 # macro +TCP_WATCH3_CNTL__ATC__SHIFT = 0x1c # macro +TCP_WATCH3_CNTL__MODE__SHIFT = 0x1d # macro +TCP_WATCH3_CNTL__VALID__SHIFT = 0x1f # macro +TCP_WATCH3_CNTL__MASK_MASK = 0x00FFFFFF # macro +TCP_WATCH3_CNTL__VMID_MASK = 0x0F000000 # macro +TCP_WATCH3_CNTL__ATC_MASK = 0x10000000 # macro +TCP_WATCH3_CNTL__MODE_MASK = 0x60000000 # macro +TCP_WATCH3_CNTL__VALID_MASK = 0x80000000 # macro +TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT = 0x19 # macro +TCP_GATCL1_CNTL__FORCE_MISS__SHIFT = 0x1a # macro +TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT = 0x1b # macro +TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT = 0x1c # macro +TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT = 0x1e # macro +TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK = 0x02000000 # macro +TCP_GATCL1_CNTL__FORCE_MISS_MASK = 0x04000000 # macro +TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK = 0x08000000 # macro +TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK = 0x30000000 # macro +TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK = 0xC0000000 # macro +TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT = 0x0 # macro +TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK = 0x000000FF # macro +TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT = 0x0 # macro +TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT = 0x1 # macro +TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT = 0x2 # macro +TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK = 0x00000001 # macro +TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK = 0x00000002 # macro +TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK = 0x00000004 # macro +TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT = 0x0 # macro +TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT = 0x2 # macro +TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL__SHIFT = 0x3 # macro +TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE__SHIFT = 0x5 # macro +TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_DATA_SEL__SHIFT = 0x6 # macro +TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT = 0x8 # macro +TCP_DSM_CNTL__VM_FIFO_IRRITATOR_DATA_SEL__SHIFT = 0x9 # macro +TCP_DSM_CNTL__VM_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT = 0xb # macro +TCP_DSM_CNTL__DB_RAM_IRRITATOR_DATA_SEL__SHIFT = 0xc # macro +TCP_DSM_CNTL__DB_RAM_IRRITATOR_SINGLE_WRITE__SHIFT = 0xe # macro +TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_DATA_SEL__SHIFT = 0xf # macro +TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_SINGLE_WRITE__SHIFT = 0x11 # macro +TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_DATA_SEL__SHIFT = 0x12 # macro +TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_SINGLE_WRITE__SHIFT = 0x14 # macro +TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK = 0x00000003 # macro +TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK = 0x00000004 # macro +TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL_MASK = 0x00000018 # macro +TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE_MASK = 0x00000020 # macro +TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_DATA_SEL_MASK = 0x000000C0 # macro +TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_SINGLE_WRITE_MASK = 0x00000100 # macro +TCP_DSM_CNTL__VM_FIFO_IRRITATOR_DATA_SEL_MASK = 0x00000600 # macro +TCP_DSM_CNTL__VM_FIFO_IRRITATOR_SINGLE_WRITE_MASK = 0x00000800 # macro +TCP_DSM_CNTL__DB_RAM_IRRITATOR_DATA_SEL_MASK = 0x00003000 # macro +TCP_DSM_CNTL__DB_RAM_IRRITATOR_SINGLE_WRITE_MASK = 0x00004000 # macro +TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_DATA_SEL_MASK = 0x00018000 # macro +TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_SINGLE_WRITE_MASK = 0x00020000 # macro +TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_DATA_SEL_MASK = 0x000C0000 # macro +TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_SINGLE_WRITE_MASK = 0x00100000 # macro +TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT = 0x0 # macro +TCP_CNTL2__TCPF_FMT_MGCG_DISABLE__SHIFT = 0x8 # macro +TCP_CNTL2__TCPI_NEW_MGCG_CTRL_BIT__SHIFT = 0xa # macro +TCP_CNTL2__MISS_CLK_DISABLE__SHIFT = 0xb # macro +TCP_CNTL2__ADRS_CLK_DISABLE__SHIFT = 0xc # macro +TCP_CNTL2__VM_CLK_DISABLE__SHIFT = 0xd # macro +TCP_CNTL2__TAGRAM_CLK_DISABLE__SHIFT = 0xe # macro +TCP_CNTL2__LEGACY_MGCG_DISABLE__SHIFT = 0xf # macro +TCP_CNTL2__MEM_MID_GATE_MGCG_DISABLE__SHIFT = 0x13 # macro +TCP_CNTL2__UTCL1_MID_GATE_MGCG_DISABLE__SHIFT = 0x14 # macro +TCP_CNTL2__LS_DISABLE_CLOCKS_MASK = 0x000000FF # macro +TCP_CNTL2__TCPF_FMT_MGCG_DISABLE_MASK = 0x00000100 # macro +TCP_CNTL2__TCPI_NEW_MGCG_CTRL_BIT_MASK = 0x00000400 # macro +TCP_CNTL2__MISS_CLK_DISABLE_MASK = 0x00000800 # macro +TCP_CNTL2__ADRS_CLK_DISABLE_MASK = 0x00001000 # macro +TCP_CNTL2__VM_CLK_DISABLE_MASK = 0x00002000 # macro +TCP_CNTL2__TAGRAM_CLK_DISABLE_MASK = 0x00004000 # macro +TCP_CNTL2__LEGACY_MGCG_DISABLE_MASK = 0x00008000 # macro +TCP_CNTL2__MEM_MID_GATE_MGCG_DISABLE_MASK = 0x00080000 # macro +TCP_CNTL2__UTCL1_MID_GATE_MGCG_DISABLE_MASK = 0x00100000 # macro +TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT = 0x0 # macro +TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT = 0x1 # macro +TCP_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT = 0x2 # macro +TCP_UTCL1_CNTL1__RESP_MODE__SHIFT = 0x3 # macro +TCP_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT = 0x5 # macro +TCP_UTCL1_CNTL1__CLIENTID__SHIFT = 0x7 # macro +TCP_UTCL1_CNTL1__UTCL1_FGCG_REPEATER_DISABLE__SHIFT = 0x10 # macro +TCP_UTCL1_CNTL1__REG_INV_VMID__SHIFT = 0x13 # macro +TCP_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT = 0x17 # macro +TCP_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT = 0x18 # macro +TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT = 0x19 # macro +TCP_UTCL1_CNTL1__FORCE_MISS__SHIFT = 0x1a # macro +TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT = 0x1c # macro +TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT = 0x1e # macro +TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK = 0x00000001 # macro +TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK = 0x00000002 # macro +TCP_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK = 0x00000004 # macro +TCP_UTCL1_CNTL1__RESP_MODE_MASK = 0x00000018 # macro +TCP_UTCL1_CNTL1__RESP_FAULT_MODE_MASK = 0x00000060 # macro +TCP_UTCL1_CNTL1__CLIENTID_MASK = 0x0000FF80 # macro +TCP_UTCL1_CNTL1__UTCL1_FGCG_REPEATER_DISABLE_MASK = 0x00010000 # macro +TCP_UTCL1_CNTL1__REG_INV_VMID_MASK = 0x00780000 # macro +TCP_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK = 0x00800000 # macro +TCP_UTCL1_CNTL1__REG_INV_TOGGLE_MASK = 0x01000000 # macro +TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK = 0x02000000 # macro +TCP_UTCL1_CNTL1__FORCE_MISS_MASK = 0x04000000 # macro +TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK = 0x30000000 # macro +TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK = 0xC0000000 # macro +TCP_UTCL1_CNTL2__SPARE__SHIFT = 0x0 # macro +TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT = 0x9 # macro +TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT = 0xa # macro +TCP_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT = 0xc # macro +TCP_UTCL1_CNTL2__FORCE_SNOOP__SHIFT = 0xe # macro +TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT = 0xf # macro +TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT = 0x1a # macro +TCP_UTCL1_CNTL2__THRASHING_TIMEOUT_PROTECT_ENABLE__SHIFT = 0x1b # macro +TCP_UTCL1_CNTL2__THRASHING_ENABLE__SHIFT = 0x1c # macro +TCP_UTCL1_CNTL2__SPARE_MASK = 0x000000FF # macro +TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK = 0x00000200 # macro +TCP_UTCL1_CNTL2__ANY_LINE_VALID_MASK = 0x00000400 # macro +TCP_UTCL1_CNTL2__GPUVM_INV_MODE_MASK = 0x00001000 # macro +TCP_UTCL1_CNTL2__FORCE_SNOOP_MASK = 0x00004000 # macro +TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK = 0x00008000 # macro +TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK = 0x04000000 # macro +TCP_UTCL1_CNTL2__THRASHING_TIMEOUT_PROTECT_ENABLE_MASK = 0x08000000 # macro +TCP_UTCL1_CNTL2__THRASHING_ENABLE_MASK = 0x10000000 # macro +TCP_UTCL1_STATUS__FAULT_DETECTED__SHIFT = 0x0 # macro +TCP_UTCL1_STATUS__RETRY_DETECTED__SHIFT = 0x1 # macro +TCP_UTCL1_STATUS__PRT_DETECTED__SHIFT = 0x2 # macro +TCP_UTCL1_STATUS__TIMEOUT_DETECTED__SHIFT = 0x3 # macro +TCP_UTCL1_STATUS__FAULT_DETECTED_MASK = 0x00000001 # macro +TCP_UTCL1_STATUS__RETRY_DETECTED_MASK = 0x00000002 # macro +TCP_UTCL1_STATUS__PRT_DETECTED_MASK = 0x00000004 # macro +TCP_UTCL1_STATUS__TIMEOUT_DETECTED_MASK = 0x00000008 # macro +TCP_DSM_CNTL2__CACHE_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +TCP_DSM_CNTL2__CACHE_RAM_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +TCP_DSM_CNTL2__LFIFO_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +TCP_DSM_CNTL2__LFIFO_RAM_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +TCP_DSM_CNTL2__CMD_FIFO_ENABLE_ERROR_INJECT__SHIFT = 0x6 # macro +TCP_DSM_CNTL2__CMD_FIFO_SELECT_INJECT_DELAY__SHIFT = 0x8 # macro +TCP_DSM_CNTL2__VM_FIFO_ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +TCP_DSM_CNTL2__VM_FIFO_SELECT_INJECT_DELAY__SHIFT = 0xb # macro +TCP_DSM_CNTL2__DB_RAM_ENABLE_ERROR_INJECT__SHIFT = 0xc # macro +TCP_DSM_CNTL2__DB_RAM_SELECT_INJECT_DELAY__SHIFT = 0xe # macro +TCP_DSM_CNTL2__UTCL1_LFIFO0_ENABLE_ERROR_INJECT__SHIFT = 0xf # macro +TCP_DSM_CNTL2__UTCL1_LFIFO0_SELECT_INJECT_DELAY__SHIFT = 0x11 # macro +TCP_DSM_CNTL2__UTCL1_LFIFO1_ENABLE_ERROR_INJECT__SHIFT = 0x12 # macro +TCP_DSM_CNTL2__UTCL1_LFIFO1_SELECT_INJECT_DELAY__SHIFT = 0x14 # macro +TCP_DSM_CNTL2__TCP_INJECT_DELAY__SHIFT = 0x1a # macro +TCP_DSM_CNTL2__CACHE_RAM_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +TCP_DSM_CNTL2__CACHE_RAM_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +TCP_DSM_CNTL2__LFIFO_RAM_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +TCP_DSM_CNTL2__LFIFO_RAM_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +TCP_DSM_CNTL2__CMD_FIFO_ENABLE_ERROR_INJECT_MASK = 0x000000C0 # macro +TCP_DSM_CNTL2__CMD_FIFO_SELECT_INJECT_DELAY_MASK = 0x00000100 # macro +TCP_DSM_CNTL2__VM_FIFO_ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +TCP_DSM_CNTL2__VM_FIFO_SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +TCP_DSM_CNTL2__DB_RAM_ENABLE_ERROR_INJECT_MASK = 0x00003000 # macro +TCP_DSM_CNTL2__DB_RAM_SELECT_INJECT_DELAY_MASK = 0x00004000 # macro +TCP_DSM_CNTL2__UTCL1_LFIFO0_ENABLE_ERROR_INJECT_MASK = 0x00018000 # macro +TCP_DSM_CNTL2__UTCL1_LFIFO0_SELECT_INJECT_DELAY_MASK = 0x00020000 # macro +TCP_DSM_CNTL2__UTCL1_LFIFO1_ENABLE_ERROR_INJECT_MASK = 0x000C0000 # macro +TCP_DSM_CNTL2__UTCL1_LFIFO1_SELECT_INJECT_DELAY_MASK = 0x00100000 # macro +TCP_DSM_CNTL2__TCP_INJECT_DELAY_MASK = 0xFC000000 # macro +TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT = 0x0 # macro +TCP_PERFCOUNTER_FILTER__FLAT__SHIFT = 0x1 # macro +TCP_PERFCOUNTER_FILTER__DIM__SHIFT = 0x2 # macro +TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT = 0x5 # macro +TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT = 0xb # macro +TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT = 0xf # macro +TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT = 0x14 # macro +TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT = 0x16 # macro +TCP_PERFCOUNTER_FILTER__GLC__SHIFT = 0x19 # macro +TCP_PERFCOUNTER_FILTER__SLC__SHIFT = 0x1a # macro +TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT = 0x1b # macro +TCP_PERFCOUNTER_FILTER__ADDR_MODE__SHIFT = 0x1c # macro +TCP_PERFCOUNTER_FILTER__BUFFER_MASK = 0x00000001 # macro +TCP_PERFCOUNTER_FILTER__FLAT_MASK = 0x00000002 # macro +TCP_PERFCOUNTER_FILTER__DIM_MASK = 0x0000001C # macro +TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK = 0x000007E0 # macro +TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK = 0x00007800 # macro +TCP_PERFCOUNTER_FILTER__SW_MODE_MASK = 0x000F8000 # macro +TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK = 0x00300000 # macro +TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK = 0x01C00000 # macro +TCP_PERFCOUNTER_FILTER__GLC_MASK = 0x02000000 # macro +TCP_PERFCOUNTER_FILTER__SLC_MASK = 0x04000000 # macro +TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK = 0x08000000 # macro +TCP_PERFCOUNTER_FILTER__ADDR_MODE_MASK = 0x70000000 # macro +TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT = 0x0 # macro +TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT = 0x1 # macro +TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT = 0x2 # macro +TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT = 0x3 # macro +TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT = 0x4 # macro +TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT = 0x5 # macro +TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT = 0x6 # macro +TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT = 0x7 # macro +TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT = 0x8 # macro +TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT = 0x9 # macro +TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT = 0xa # macro +TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE__SHIFT = 0xb # macro +TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK = 0x00000001 # macro +TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK = 0x00000002 # macro +TCP_PERFCOUNTER_FILTER_EN__DIM_MASK = 0x00000004 # macro +TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK = 0x00000008 # macro +TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK = 0x00000010 # macro +TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK = 0x00000020 # macro +TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK = 0x00000040 # macro +TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK = 0x00000080 # macro +TCP_PERFCOUNTER_FILTER_EN__GLC_MASK = 0x00000100 # macro +TCP_PERFCOUNTER_FILTER_EN__SLC_MASK = 0x00000200 # macro +TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK = 0x00000400 # macro +TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE_MASK = 0x00000800 # macro +GDS_VMID0_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID0_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID0_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID0_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID1_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID1_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID1_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID1_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID2_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID2_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID2_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID2_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID3_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID3_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID3_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID3_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID4_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID4_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID4_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID4_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID5_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID5_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID5_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID5_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID6_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID6_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID6_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID6_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID7_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID7_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID7_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID7_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID8_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID8_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID8_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID8_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID9_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID9_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID9_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID9_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID10_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID10_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID10_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID10_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID11_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID11_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID11_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID11_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID12_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID12_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID12_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID12_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID13_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID13_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID13_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID13_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID14_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID14_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID14_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID14_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_VMID15_BASE__BASE__SHIFT = 0x0 # macro +GDS_VMID15_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_VMID15_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_VMID15_SIZE__SIZE_MASK = 0x0001FFFF # macro +GDS_GWS_VMID0__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID0__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID0__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID0__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID1__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID1__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID1__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID1__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID2__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID2__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID2__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID2__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID3__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID3__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID3__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID3__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID4__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID4__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID4__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID4__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID5__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID5__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID5__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID5__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID6__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID6__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID6__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID6__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID7__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID7__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID7__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID7__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID8__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID8__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID8__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID8__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID9__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID9__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID9__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID9__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID10__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID10__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID10__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID10__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID11__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID11__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID11__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID11__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID12__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID12__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID12__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID12__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID13__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID13__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID13__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID13__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID14__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID14__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID14__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID14__SIZE_MASK = 0x007F0000 # macro +GDS_GWS_VMID15__BASE__SHIFT = 0x0 # macro +GDS_GWS_VMID15__SIZE__SHIFT = 0x10 # macro +GDS_GWS_VMID15__BASE_MASK = 0x0000003F # macro +GDS_GWS_VMID15__SIZE_MASK = 0x007F0000 # macro +GDS_OA_VMID0__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID0__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID0__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID0__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID1__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID1__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID1__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID1__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID2__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID2__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID2__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID2__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID3__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID3__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID3__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID3__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID4__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID4__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID4__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID4__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID5__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID5__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID5__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID5__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID6__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID6__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID6__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID6__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID7__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID7__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID7__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID7__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID8__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID8__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID8__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID8__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID9__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID9__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID9__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID9__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID10__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID10__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID10__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID10__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID11__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID11__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID11__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID11__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID12__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID12__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID12__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID12__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID13__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID13__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID13__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID13__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID14__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID14__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID14__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID14__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_VMID15__MASK__SHIFT = 0x0 # macro +GDS_OA_VMID15__UNUSED__SHIFT = 0x10 # macro +GDS_OA_VMID15__MASK_MASK = 0x0000FFFF # macro +GDS_OA_VMID15__UNUSED_MASK = 0xFFFF0000 # macro +GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT = 0x0 # macro +GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT = 0x1 # macro +GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT = 0x2 # macro +GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT = 0x3 # macro +GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT = 0x4 # macro +GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT = 0x5 # macro +GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT = 0x6 # macro +GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT = 0x7 # macro +GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT = 0x8 # macro +GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT = 0x9 # macro +GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT = 0xa # macro +GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT = 0xb # macro +GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT = 0xc # macro +GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT = 0xd # macro +GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT = 0xe # macro +GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT = 0xf # macro +GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT = 0x10 # macro +GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT = 0x11 # macro +GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT = 0x12 # macro +GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT = 0x13 # macro +GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT = 0x14 # macro +GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT = 0x15 # macro +GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT = 0x16 # macro +GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT = 0x17 # macro +GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT = 0x18 # macro +GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT = 0x19 # macro +GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT = 0x1a # macro +GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT = 0x1b # macro +GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT = 0x1c # macro +GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT = 0x1d # macro +GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT = 0x1e # macro +GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT = 0x1f # macro +GDS_GWS_RESET0__RESOURCE0_RESET_MASK = 0x00000001 # macro +GDS_GWS_RESET0__RESOURCE1_RESET_MASK = 0x00000002 # macro +GDS_GWS_RESET0__RESOURCE2_RESET_MASK = 0x00000004 # macro +GDS_GWS_RESET0__RESOURCE3_RESET_MASK = 0x00000008 # macro +GDS_GWS_RESET0__RESOURCE4_RESET_MASK = 0x00000010 # macro +GDS_GWS_RESET0__RESOURCE5_RESET_MASK = 0x00000020 # macro +GDS_GWS_RESET0__RESOURCE6_RESET_MASK = 0x00000040 # macro +GDS_GWS_RESET0__RESOURCE7_RESET_MASK = 0x00000080 # macro +GDS_GWS_RESET0__RESOURCE8_RESET_MASK = 0x00000100 # macro +GDS_GWS_RESET0__RESOURCE9_RESET_MASK = 0x00000200 # macro +GDS_GWS_RESET0__RESOURCE10_RESET_MASK = 0x00000400 # macro +GDS_GWS_RESET0__RESOURCE11_RESET_MASK = 0x00000800 # macro +GDS_GWS_RESET0__RESOURCE12_RESET_MASK = 0x00001000 # macro +GDS_GWS_RESET0__RESOURCE13_RESET_MASK = 0x00002000 # macro +GDS_GWS_RESET0__RESOURCE14_RESET_MASK = 0x00004000 # macro +GDS_GWS_RESET0__RESOURCE15_RESET_MASK = 0x00008000 # macro +GDS_GWS_RESET0__RESOURCE16_RESET_MASK = 0x00010000 # macro +GDS_GWS_RESET0__RESOURCE17_RESET_MASK = 0x00020000 # macro +GDS_GWS_RESET0__RESOURCE18_RESET_MASK = 0x00040000 # macro +GDS_GWS_RESET0__RESOURCE19_RESET_MASK = 0x00080000 # macro +GDS_GWS_RESET0__RESOURCE20_RESET_MASK = 0x00100000 # macro +GDS_GWS_RESET0__RESOURCE21_RESET_MASK = 0x00200000 # macro +GDS_GWS_RESET0__RESOURCE22_RESET_MASK = 0x00400000 # macro +GDS_GWS_RESET0__RESOURCE23_RESET_MASK = 0x00800000 # macro +GDS_GWS_RESET0__RESOURCE24_RESET_MASK = 0x01000000 # macro +GDS_GWS_RESET0__RESOURCE25_RESET_MASK = 0x02000000 # macro +GDS_GWS_RESET0__RESOURCE26_RESET_MASK = 0x04000000 # macro +GDS_GWS_RESET0__RESOURCE27_RESET_MASK = 0x08000000 # macro +GDS_GWS_RESET0__RESOURCE28_RESET_MASK = 0x10000000 # macro +GDS_GWS_RESET0__RESOURCE29_RESET_MASK = 0x20000000 # macro +GDS_GWS_RESET0__RESOURCE30_RESET_MASK = 0x40000000 # macro +GDS_GWS_RESET0__RESOURCE31_RESET_MASK = 0x80000000 # macro +GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT = 0x0 # macro +GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT = 0x1 # macro +GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT = 0x2 # macro +GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT = 0x3 # macro +GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT = 0x4 # macro +GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT = 0x5 # macro +GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT = 0x6 # macro +GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT = 0x7 # macro +GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT = 0x8 # macro +GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT = 0x9 # macro +GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT = 0xa # macro +GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT = 0xb # macro +GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT = 0xc # macro +GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT = 0xd # macro +GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT = 0xe # macro +GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT = 0xf # macro +GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT = 0x10 # macro +GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT = 0x11 # macro +GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT = 0x12 # macro +GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT = 0x13 # macro +GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT = 0x14 # macro +GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT = 0x15 # macro +GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT = 0x16 # macro +GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT = 0x17 # macro +GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT = 0x18 # macro +GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT = 0x19 # macro +GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT = 0x1a # macro +GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT = 0x1b # macro +GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT = 0x1c # macro +GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT = 0x1d # macro +GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT = 0x1e # macro +GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT = 0x1f # macro +GDS_GWS_RESET1__RESOURCE32_RESET_MASK = 0x00000001 # macro +GDS_GWS_RESET1__RESOURCE33_RESET_MASK = 0x00000002 # macro +GDS_GWS_RESET1__RESOURCE34_RESET_MASK = 0x00000004 # macro +GDS_GWS_RESET1__RESOURCE35_RESET_MASK = 0x00000008 # macro +GDS_GWS_RESET1__RESOURCE36_RESET_MASK = 0x00000010 # macro +GDS_GWS_RESET1__RESOURCE37_RESET_MASK = 0x00000020 # macro +GDS_GWS_RESET1__RESOURCE38_RESET_MASK = 0x00000040 # macro +GDS_GWS_RESET1__RESOURCE39_RESET_MASK = 0x00000080 # macro +GDS_GWS_RESET1__RESOURCE40_RESET_MASK = 0x00000100 # macro +GDS_GWS_RESET1__RESOURCE41_RESET_MASK = 0x00000200 # macro +GDS_GWS_RESET1__RESOURCE42_RESET_MASK = 0x00000400 # macro +GDS_GWS_RESET1__RESOURCE43_RESET_MASK = 0x00000800 # macro +GDS_GWS_RESET1__RESOURCE44_RESET_MASK = 0x00001000 # macro +GDS_GWS_RESET1__RESOURCE45_RESET_MASK = 0x00002000 # macro +GDS_GWS_RESET1__RESOURCE46_RESET_MASK = 0x00004000 # macro +GDS_GWS_RESET1__RESOURCE47_RESET_MASK = 0x00008000 # macro +GDS_GWS_RESET1__RESOURCE48_RESET_MASK = 0x00010000 # macro +GDS_GWS_RESET1__RESOURCE49_RESET_MASK = 0x00020000 # macro +GDS_GWS_RESET1__RESOURCE50_RESET_MASK = 0x00040000 # macro +GDS_GWS_RESET1__RESOURCE51_RESET_MASK = 0x00080000 # macro +GDS_GWS_RESET1__RESOURCE52_RESET_MASK = 0x00100000 # macro +GDS_GWS_RESET1__RESOURCE53_RESET_MASK = 0x00200000 # macro +GDS_GWS_RESET1__RESOURCE54_RESET_MASK = 0x00400000 # macro +GDS_GWS_RESET1__RESOURCE55_RESET_MASK = 0x00800000 # macro +GDS_GWS_RESET1__RESOURCE56_RESET_MASK = 0x01000000 # macro +GDS_GWS_RESET1__RESOURCE57_RESET_MASK = 0x02000000 # macro +GDS_GWS_RESET1__RESOURCE58_RESET_MASK = 0x04000000 # macro +GDS_GWS_RESET1__RESOURCE59_RESET_MASK = 0x08000000 # macro +GDS_GWS_RESET1__RESOURCE60_RESET_MASK = 0x10000000 # macro +GDS_GWS_RESET1__RESOURCE61_RESET_MASK = 0x20000000 # macro +GDS_GWS_RESET1__RESOURCE62_RESET_MASK = 0x40000000 # macro +GDS_GWS_RESET1__RESOURCE63_RESET_MASK = 0x80000000 # macro +GDS_GWS_RESOURCE_RESET__RESET__SHIFT = 0x0 # macro +GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT = 0x8 # macro +GDS_GWS_RESOURCE_RESET__RESET_MASK = 0x00000001 # macro +GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK = 0x0000FF00 # macro +GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT = 0x0 # macro +GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK = 0x00000FFF # macro +GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT = 0x0 # macro +GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT = 0x1 # macro +GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT = 0x2 # macro +GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT = 0x3 # macro +GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT = 0x4 # macro +GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT = 0x5 # macro +GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT = 0x6 # macro +GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT = 0x7 # macro +GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT = 0x8 # macro +GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT = 0x9 # macro +GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT = 0xa # macro +GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT = 0xb # macro +GDS_OA_RESET_MASK__UNUSED1__SHIFT = 0xc # macro +GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK = 0x00000001 # macro +GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK = 0x00000002 # macro +GDS_OA_RESET_MASK__ME0_CS_RESET_MASK = 0x00000004 # macro +GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK = 0x00000008 # macro +GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK = 0x00000010 # macro +GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK = 0x00000020 # macro +GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK = 0x00000040 # macro +GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK = 0x00000080 # macro +GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK = 0x00000100 # macro +GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK = 0x00000200 # macro +GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK = 0x00000400 # macro +GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK = 0x00000800 # macro +GDS_OA_RESET_MASK__UNUSED1_MASK = 0xFFFFF000 # macro +GDS_OA_RESET__RESET__SHIFT = 0x0 # macro +GDS_OA_RESET__PIPE_ID__SHIFT = 0x8 # macro +GDS_OA_RESET__RESET_MASK = 0x00000001 # macro +GDS_OA_RESET__PIPE_ID_MASK = 0x0000FF00 # macro +GDS_ENHANCE__MISC__SHIFT = 0x0 # macro +GDS_ENHANCE__AUTO_INC_INDEX__SHIFT = 0x10 # macro +GDS_ENHANCE__CGPG_RESTORE__SHIFT = 0x11 # macro +GDS_ENHANCE__RD_BUF_TAG_MISS__SHIFT = 0x12 # macro +GDS_ENHANCE__GDSA_PC_CGTS_DIS__SHIFT = 0x13 # macro +GDS_ENHANCE__GDSO_PC_CGTS_DIS__SHIFT = 0x14 # macro +GDS_ENHANCE__WD_GDS_CSB_OVERRIDE__SHIFT = 0x15 # macro +GDS_ENHANCE__GDS_CLK_ENHANCE_DIS__SHIFT = 0x16 # macro +GDS_ENHANCE__DS_MEM_CLK_GATE_DIS__SHIFT = 0x17 # macro +GDS_ENHANCE__UNUSED__SHIFT = 0x18 # macro +GDS_ENHANCE__MISC_MASK = 0x0000FFFF # macro +GDS_ENHANCE__AUTO_INC_INDEX_MASK = 0x00010000 # macro +GDS_ENHANCE__CGPG_RESTORE_MASK = 0x00020000 # macro +GDS_ENHANCE__RD_BUF_TAG_MISS_MASK = 0x00040000 # macro +GDS_ENHANCE__GDSA_PC_CGTS_DIS_MASK = 0x00080000 # macro +GDS_ENHANCE__GDSO_PC_CGTS_DIS_MASK = 0x00100000 # macro +GDS_ENHANCE__WD_GDS_CSB_OVERRIDE_MASK = 0x00200000 # macro +GDS_ENHANCE__GDS_CLK_ENHANCE_DIS_MASK = 0x00400000 # macro +GDS_ENHANCE__DS_MEM_CLK_GATE_DIS_MASK = 0x00800000 # macro +GDS_ENHANCE__UNUSED_MASK = 0xFF000000 # macro +GDS_OA_CGPG_RESTORE__VMID__SHIFT = 0x0 # macro +GDS_OA_CGPG_RESTORE__MEID__SHIFT = 0x8 # macro +GDS_OA_CGPG_RESTORE__PIPEID__SHIFT = 0xc # macro +GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT = 0x10 # macro +GDS_OA_CGPG_RESTORE__UNUSED__SHIFT = 0x14 # macro +GDS_OA_CGPG_RESTORE__VMID_MASK = 0x000000FF # macro +GDS_OA_CGPG_RESTORE__MEID_MASK = 0x00000F00 # macro +GDS_OA_CGPG_RESTORE__PIPEID_MASK = 0x0000F000 # macro +GDS_OA_CGPG_RESTORE__QUEUEID_MASK = 0x000F0000 # macro +GDS_OA_CGPG_RESTORE__UNUSED_MASK = 0xFFF00000 # macro +GDS_CS_CTXSW_STATUS__R__SHIFT = 0x0 # macro +GDS_CS_CTXSW_STATUS__W__SHIFT = 0x1 # macro +GDS_CS_CTXSW_STATUS__UNUSED__SHIFT = 0x2 # macro +GDS_CS_CTXSW_STATUS__R_MASK = 0x00000001 # macro +GDS_CS_CTXSW_STATUS__W_MASK = 0x00000002 # macro +GDS_CS_CTXSW_STATUS__UNUSED_MASK = 0xFFFFFFFC # macro +GDS_CS_CTXSW_CNT0__UPDN__SHIFT = 0x0 # macro +GDS_CS_CTXSW_CNT0__PTR__SHIFT = 0x10 # macro +GDS_CS_CTXSW_CNT0__UPDN_MASK = 0x0000FFFF # macro +GDS_CS_CTXSW_CNT0__PTR_MASK = 0xFFFF0000 # macro +GDS_CS_CTXSW_CNT1__UPDN__SHIFT = 0x0 # macro +GDS_CS_CTXSW_CNT1__PTR__SHIFT = 0x10 # macro +GDS_CS_CTXSW_CNT1__UPDN_MASK = 0x0000FFFF # macro +GDS_CS_CTXSW_CNT1__PTR_MASK = 0xFFFF0000 # macro +GDS_CS_CTXSW_CNT2__UPDN__SHIFT = 0x0 # macro +GDS_CS_CTXSW_CNT2__PTR__SHIFT = 0x10 # macro +GDS_CS_CTXSW_CNT2__UPDN_MASK = 0x0000FFFF # macro +GDS_CS_CTXSW_CNT2__PTR_MASK = 0xFFFF0000 # macro +GDS_CS_CTXSW_CNT3__UPDN__SHIFT = 0x0 # macro +GDS_CS_CTXSW_CNT3__PTR__SHIFT = 0x10 # macro +GDS_CS_CTXSW_CNT3__UPDN_MASK = 0x0000FFFF # macro +GDS_CS_CTXSW_CNT3__PTR_MASK = 0xFFFF0000 # macro +GDS_GFX_CTXSW_STATUS__R__SHIFT = 0x0 # macro +GDS_GFX_CTXSW_STATUS__W__SHIFT = 0x1 # macro +GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT = 0x2 # macro +GDS_GFX_CTXSW_STATUS__R_MASK = 0x00000001 # macro +GDS_GFX_CTXSW_STATUS__W_MASK = 0x00000002 # macro +GDS_GFX_CTXSW_STATUS__UNUSED_MASK = 0xFFFFFFFC # macro +GDS_VS_CTXSW_CNT0__UPDN__SHIFT = 0x0 # macro +GDS_VS_CTXSW_CNT0__PTR__SHIFT = 0x10 # macro +GDS_VS_CTXSW_CNT0__UPDN_MASK = 0x0000FFFF # macro +GDS_VS_CTXSW_CNT0__PTR_MASK = 0xFFFF0000 # macro +GDS_VS_CTXSW_CNT1__UPDN__SHIFT = 0x0 # macro +GDS_VS_CTXSW_CNT1__PTR__SHIFT = 0x10 # macro +GDS_VS_CTXSW_CNT1__UPDN_MASK = 0x0000FFFF # macro +GDS_VS_CTXSW_CNT1__PTR_MASK = 0xFFFF0000 # macro +GDS_VS_CTXSW_CNT2__UPDN__SHIFT = 0x0 # macro +GDS_VS_CTXSW_CNT2__PTR__SHIFT = 0x10 # macro +GDS_VS_CTXSW_CNT2__UPDN_MASK = 0x0000FFFF # macro +GDS_VS_CTXSW_CNT2__PTR_MASK = 0xFFFF0000 # macro +GDS_VS_CTXSW_CNT3__UPDN__SHIFT = 0x0 # macro +GDS_VS_CTXSW_CNT3__PTR__SHIFT = 0x10 # macro +GDS_VS_CTXSW_CNT3__UPDN_MASK = 0x0000FFFF # macro +GDS_VS_CTXSW_CNT3__PTR_MASK = 0xFFFF0000 # macro +GDS_PS0_CTXSW_CNT0__UPDN__SHIFT = 0x0 # macro +GDS_PS0_CTXSW_CNT0__PTR__SHIFT = 0x10 # macro +GDS_PS0_CTXSW_CNT0__UPDN_MASK = 0x0000FFFF # macro +GDS_PS0_CTXSW_CNT0__PTR_MASK = 0xFFFF0000 # macro +GDS_PS0_CTXSW_CNT1__UPDN__SHIFT = 0x0 # macro +GDS_PS0_CTXSW_CNT1__PTR__SHIFT = 0x10 # macro +GDS_PS0_CTXSW_CNT1__UPDN_MASK = 0x0000FFFF # macro +GDS_PS0_CTXSW_CNT1__PTR_MASK = 0xFFFF0000 # macro +GDS_PS0_CTXSW_CNT2__UPDN__SHIFT = 0x0 # macro +GDS_PS0_CTXSW_CNT2__PTR__SHIFT = 0x10 # macro +GDS_PS0_CTXSW_CNT2__UPDN_MASK = 0x0000FFFF # macro +GDS_PS0_CTXSW_CNT2__PTR_MASK = 0xFFFF0000 # macro +GDS_PS0_CTXSW_CNT3__UPDN__SHIFT = 0x0 # macro +GDS_PS0_CTXSW_CNT3__PTR__SHIFT = 0x10 # macro +GDS_PS0_CTXSW_CNT3__UPDN_MASK = 0x0000FFFF # macro +GDS_PS0_CTXSW_CNT3__PTR_MASK = 0xFFFF0000 # macro +GDS_PS1_CTXSW_CNT0__UPDN__SHIFT = 0x0 # macro +GDS_PS1_CTXSW_CNT0__PTR__SHIFT = 0x10 # macro +GDS_PS1_CTXSW_CNT0__UPDN_MASK = 0x0000FFFF # macro +GDS_PS1_CTXSW_CNT0__PTR_MASK = 0xFFFF0000 # macro +GDS_PS1_CTXSW_CNT1__UPDN__SHIFT = 0x0 # macro +GDS_PS1_CTXSW_CNT1__PTR__SHIFT = 0x10 # macro +GDS_PS1_CTXSW_CNT1__UPDN_MASK = 0x0000FFFF # macro +GDS_PS1_CTXSW_CNT1__PTR_MASK = 0xFFFF0000 # macro +GDS_PS1_CTXSW_CNT2__UPDN__SHIFT = 0x0 # macro +GDS_PS1_CTXSW_CNT2__PTR__SHIFT = 0x10 # macro +GDS_PS1_CTXSW_CNT2__UPDN_MASK = 0x0000FFFF # macro +GDS_PS1_CTXSW_CNT2__PTR_MASK = 0xFFFF0000 # macro +GDS_PS1_CTXSW_CNT3__UPDN__SHIFT = 0x0 # macro +GDS_PS1_CTXSW_CNT3__PTR__SHIFT = 0x10 # macro +GDS_PS1_CTXSW_CNT3__UPDN_MASK = 0x0000FFFF # macro +GDS_PS1_CTXSW_CNT3__PTR_MASK = 0xFFFF0000 # macro +GDS_PS2_CTXSW_CNT0__UPDN__SHIFT = 0x0 # macro +GDS_PS2_CTXSW_CNT0__PTR__SHIFT = 0x10 # macro +GDS_PS2_CTXSW_CNT0__UPDN_MASK = 0x0000FFFF # macro +GDS_PS2_CTXSW_CNT0__PTR_MASK = 0xFFFF0000 # macro +GDS_PS2_CTXSW_CNT1__UPDN__SHIFT = 0x0 # macro +GDS_PS2_CTXSW_CNT1__PTR__SHIFT = 0x10 # macro +GDS_PS2_CTXSW_CNT1__UPDN_MASK = 0x0000FFFF # macro +GDS_PS2_CTXSW_CNT1__PTR_MASK = 0xFFFF0000 # macro +GDS_PS2_CTXSW_CNT2__UPDN__SHIFT = 0x0 # macro +GDS_PS2_CTXSW_CNT2__PTR__SHIFT = 0x10 # macro +GDS_PS2_CTXSW_CNT2__UPDN_MASK = 0x0000FFFF # macro +GDS_PS2_CTXSW_CNT2__PTR_MASK = 0xFFFF0000 # macro +GDS_PS2_CTXSW_CNT3__UPDN__SHIFT = 0x0 # macro +GDS_PS2_CTXSW_CNT3__PTR__SHIFT = 0x10 # macro +GDS_PS2_CTXSW_CNT3__UPDN_MASK = 0x0000FFFF # macro +GDS_PS2_CTXSW_CNT3__PTR_MASK = 0xFFFF0000 # macro +GDS_PS3_CTXSW_CNT0__UPDN__SHIFT = 0x0 # macro +GDS_PS3_CTXSW_CNT0__PTR__SHIFT = 0x10 # macro +GDS_PS3_CTXSW_CNT0__UPDN_MASK = 0x0000FFFF # macro +GDS_PS3_CTXSW_CNT0__PTR_MASK = 0xFFFF0000 # macro +GDS_PS3_CTXSW_CNT1__UPDN__SHIFT = 0x0 # macro +GDS_PS3_CTXSW_CNT1__PTR__SHIFT = 0x10 # macro +GDS_PS3_CTXSW_CNT1__UPDN_MASK = 0x0000FFFF # macro +GDS_PS3_CTXSW_CNT1__PTR_MASK = 0xFFFF0000 # macro +GDS_PS3_CTXSW_CNT2__UPDN__SHIFT = 0x0 # macro +GDS_PS3_CTXSW_CNT2__PTR__SHIFT = 0x10 # macro +GDS_PS3_CTXSW_CNT2__UPDN_MASK = 0x0000FFFF # macro +GDS_PS3_CTXSW_CNT2__PTR_MASK = 0xFFFF0000 # macro +GDS_PS3_CTXSW_CNT3__UPDN__SHIFT = 0x0 # macro +GDS_PS3_CTXSW_CNT3__PTR__SHIFT = 0x10 # macro +GDS_PS3_CTXSW_CNT3__UPDN_MASK = 0x0000FFFF # macro +GDS_PS3_CTXSW_CNT3__PTR_MASK = 0xFFFF0000 # macro +GDS_PS4_CTXSW_CNT0__UPDN__SHIFT = 0x0 # macro +GDS_PS4_CTXSW_CNT0__PTR__SHIFT = 0x10 # macro +GDS_PS4_CTXSW_CNT0__UPDN_MASK = 0x0000FFFF # macro +GDS_PS4_CTXSW_CNT0__PTR_MASK = 0xFFFF0000 # macro +GDS_PS4_CTXSW_CNT1__UPDN__SHIFT = 0x0 # macro +GDS_PS4_CTXSW_CNT1__PTR__SHIFT = 0x10 # macro +GDS_PS4_CTXSW_CNT1__UPDN_MASK = 0x0000FFFF # macro +GDS_PS4_CTXSW_CNT1__PTR_MASK = 0xFFFF0000 # macro +GDS_PS4_CTXSW_CNT2__UPDN__SHIFT = 0x0 # macro +GDS_PS4_CTXSW_CNT2__PTR__SHIFT = 0x10 # macro +GDS_PS4_CTXSW_CNT2__UPDN_MASK = 0x0000FFFF # macro +GDS_PS4_CTXSW_CNT2__PTR_MASK = 0xFFFF0000 # macro +GDS_PS4_CTXSW_CNT3__UPDN__SHIFT = 0x0 # macro +GDS_PS4_CTXSW_CNT3__PTR__SHIFT = 0x10 # macro +GDS_PS4_CTXSW_CNT3__UPDN_MASK = 0x0000FFFF # macro +GDS_PS4_CTXSW_CNT3__PTR_MASK = 0xFFFF0000 # macro +GDS_PS5_CTXSW_CNT0__UPDN__SHIFT = 0x0 # macro +GDS_PS5_CTXSW_CNT0__PTR__SHIFT = 0x10 # macro +GDS_PS5_CTXSW_CNT0__UPDN_MASK = 0x0000FFFF # macro +GDS_PS5_CTXSW_CNT0__PTR_MASK = 0xFFFF0000 # macro +GDS_PS5_CTXSW_CNT1__UPDN__SHIFT = 0x0 # macro +GDS_PS5_CTXSW_CNT1__PTR__SHIFT = 0x10 # macro +GDS_PS5_CTXSW_CNT1__UPDN_MASK = 0x0000FFFF # macro +GDS_PS5_CTXSW_CNT1__PTR_MASK = 0xFFFF0000 # macro +GDS_PS5_CTXSW_CNT2__UPDN__SHIFT = 0x0 # macro +GDS_PS5_CTXSW_CNT2__PTR__SHIFT = 0x10 # macro +GDS_PS5_CTXSW_CNT2__UPDN_MASK = 0x0000FFFF # macro +GDS_PS5_CTXSW_CNT2__PTR_MASK = 0xFFFF0000 # macro +GDS_PS5_CTXSW_CNT3__UPDN__SHIFT = 0x0 # macro +GDS_PS5_CTXSW_CNT3__PTR__SHIFT = 0x10 # macro +GDS_PS5_CTXSW_CNT3__UPDN_MASK = 0x0000FFFF # macro +GDS_PS5_CTXSW_CNT3__PTR_MASK = 0xFFFF0000 # macro +GDS_PS6_CTXSW_CNT0__UPDN__SHIFT = 0x0 # macro +GDS_PS6_CTXSW_CNT0__PTR__SHIFT = 0x10 # macro +GDS_PS6_CTXSW_CNT0__UPDN_MASK = 0x0000FFFF # macro +GDS_PS6_CTXSW_CNT0__PTR_MASK = 0xFFFF0000 # macro +GDS_PS6_CTXSW_CNT1__UPDN__SHIFT = 0x0 # macro +GDS_PS6_CTXSW_CNT1__PTR__SHIFT = 0x10 # macro +GDS_PS6_CTXSW_CNT1__UPDN_MASK = 0x0000FFFF # macro +GDS_PS6_CTXSW_CNT1__PTR_MASK = 0xFFFF0000 # macro +GDS_PS6_CTXSW_CNT2__UPDN__SHIFT = 0x0 # macro +GDS_PS6_CTXSW_CNT2__PTR__SHIFT = 0x10 # macro +GDS_PS6_CTXSW_CNT2__UPDN_MASK = 0x0000FFFF # macro +GDS_PS6_CTXSW_CNT2__PTR_MASK = 0xFFFF0000 # macro +GDS_PS6_CTXSW_CNT3__UPDN__SHIFT = 0x0 # macro +GDS_PS6_CTXSW_CNT3__PTR__SHIFT = 0x10 # macro +GDS_PS6_CTXSW_CNT3__UPDN_MASK = 0x0000FFFF # macro +GDS_PS6_CTXSW_CNT3__PTR_MASK = 0xFFFF0000 # macro +GDS_PS7_CTXSW_CNT0__UPDN__SHIFT = 0x0 # macro +GDS_PS7_CTXSW_CNT0__PTR__SHIFT = 0x10 # macro +GDS_PS7_CTXSW_CNT0__UPDN_MASK = 0x0000FFFF # macro +GDS_PS7_CTXSW_CNT0__PTR_MASK = 0xFFFF0000 # macro +GDS_PS7_CTXSW_CNT1__UPDN__SHIFT = 0x0 # macro +GDS_PS7_CTXSW_CNT1__PTR__SHIFT = 0x10 # macro +GDS_PS7_CTXSW_CNT1__UPDN_MASK = 0x0000FFFF # macro +GDS_PS7_CTXSW_CNT1__PTR_MASK = 0xFFFF0000 # macro +GDS_PS7_CTXSW_CNT2__UPDN__SHIFT = 0x0 # macro +GDS_PS7_CTXSW_CNT2__PTR__SHIFT = 0x10 # macro +GDS_PS7_CTXSW_CNT2__UPDN_MASK = 0x0000FFFF # macro +GDS_PS7_CTXSW_CNT2__PTR_MASK = 0xFFFF0000 # macro +GDS_PS7_CTXSW_CNT3__UPDN__SHIFT = 0x0 # macro +GDS_PS7_CTXSW_CNT3__PTR__SHIFT = 0x10 # macro +GDS_PS7_CTXSW_CNT3__UPDN_MASK = 0x0000FFFF # macro +GDS_PS7_CTXSW_CNT3__PTR_MASK = 0xFFFF0000 # macro +GDS_GS_CTXSW_CNT0__UPDN__SHIFT = 0x0 # macro +GDS_GS_CTXSW_CNT0__PTR__SHIFT = 0x10 # macro +GDS_GS_CTXSW_CNT0__UPDN_MASK = 0x0000FFFF # macro +GDS_GS_CTXSW_CNT0__PTR_MASK = 0xFFFF0000 # macro +GDS_GS_CTXSW_CNT1__UPDN__SHIFT = 0x0 # macro +GDS_GS_CTXSW_CNT1__PTR__SHIFT = 0x10 # macro +GDS_GS_CTXSW_CNT1__UPDN_MASK = 0x0000FFFF # macro +GDS_GS_CTXSW_CNT1__PTR_MASK = 0xFFFF0000 # macro +GDS_GS_CTXSW_CNT2__UPDN__SHIFT = 0x0 # macro +GDS_GS_CTXSW_CNT2__PTR__SHIFT = 0x10 # macro +GDS_GS_CTXSW_CNT2__UPDN_MASK = 0x0000FFFF # macro +GDS_GS_CTXSW_CNT2__PTR_MASK = 0xFFFF0000 # macro +GDS_GS_CTXSW_CNT3__UPDN__SHIFT = 0x0 # macro +GDS_GS_CTXSW_CNT3__PTR__SHIFT = 0x10 # macro +GDS_GS_CTXSW_CNT3__UPDN_MASK = 0x0000FFFF # macro +GDS_GS_CTXSW_CNT3__PTR_MASK = 0xFFFF0000 # macro +RAS_SIGNATURE_CONTROL__ENABLE__SHIFT = 0x0 # macro +RAS_SIGNATURE_CONTROL__ENABLE_MASK = 0x00000001 # macro +RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT = 0x0 # macro +RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK = 0xFFFFFFFF # macro +RAS_SX_SIGNATURE0__SIGNATURE__SHIFT = 0x0 # macro +RAS_SX_SIGNATURE0__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_SX_SIGNATURE1__SIGNATURE__SHIFT = 0x0 # macro +RAS_SX_SIGNATURE1__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_SX_SIGNATURE2__SIGNATURE__SHIFT = 0x0 # macro +RAS_SX_SIGNATURE2__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_SX_SIGNATURE3__SIGNATURE__SHIFT = 0x0 # macro +RAS_SX_SIGNATURE3__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_DB_SIGNATURE0__SIGNATURE__SHIFT = 0x0 # macro +RAS_DB_SIGNATURE0__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_PA_SIGNATURE0__SIGNATURE__SHIFT = 0x0 # macro +RAS_PA_SIGNATURE0__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT = 0x0 # macro +RAS_VGT_SIGNATURE0__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT = 0x0 # macro +RAS_SQ_SIGNATURE0__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_SC_SIGNATURE0__SIGNATURE__SHIFT = 0x0 # macro +RAS_SC_SIGNATURE0__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_SC_SIGNATURE1__SIGNATURE__SHIFT = 0x0 # macro +RAS_SC_SIGNATURE1__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_SC_SIGNATURE2__SIGNATURE__SHIFT = 0x0 # macro +RAS_SC_SIGNATURE2__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_SC_SIGNATURE3__SIGNATURE__SHIFT = 0x0 # macro +RAS_SC_SIGNATURE3__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_SC_SIGNATURE4__SIGNATURE__SHIFT = 0x0 # macro +RAS_SC_SIGNATURE4__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_SC_SIGNATURE5__SIGNATURE__SHIFT = 0x0 # macro +RAS_SC_SIGNATURE5__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_SC_SIGNATURE6__SIGNATURE__SHIFT = 0x0 # macro +RAS_SC_SIGNATURE6__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_SC_SIGNATURE7__SIGNATURE__SHIFT = 0x0 # macro +RAS_SC_SIGNATURE7__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_IA_SIGNATURE0__SIGNATURE__SHIFT = 0x0 # macro +RAS_IA_SIGNATURE0__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_IA_SIGNATURE1__SIGNATURE__SHIFT = 0x0 # macro +RAS_IA_SIGNATURE1__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT = 0x0 # macro +RAS_SPI_SIGNATURE0__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT = 0x0 # macro +RAS_SPI_SIGNATURE1__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_TA_SIGNATURE0__SIGNATURE__SHIFT = 0x0 # macro +RAS_TA_SIGNATURE0__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_TD_SIGNATURE0__SIGNATURE__SHIFT = 0x0 # macro +RAS_TD_SIGNATURE0__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_CB_SIGNATURE0__SIGNATURE__SHIFT = 0x0 # macro +RAS_CB_SIGNATURE0__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT = 0x0 # macro +RAS_BCI_SIGNATURE0__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT = 0x0 # macro +RAS_BCI_SIGNATURE1__SIGNATURE_MASK = 0xFFFFFFFF # macro +RAS_TA_SIGNATURE1__SIGNATURE__SHIFT = 0x0 # macro +RAS_TA_SIGNATURE1__SIGNATURE_MASK = 0xFFFFFFFF # macro +DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT = 0x0 # macro +DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT = 0x1 # macro +DB_RENDER_CONTROL__DEPTH_COPY__SHIFT = 0x2 # macro +DB_RENDER_CONTROL__STENCIL_COPY__SHIFT = 0x3 # macro +DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT = 0x4 # macro +DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT = 0x5 # macro +DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT = 0x6 # macro +DB_RENDER_CONTROL__COPY_CENTROID__SHIFT = 0x7 # macro +DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT = 0x8 # macro +DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT = 0xc # macro +DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK = 0x00000001 # macro +DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK = 0x00000002 # macro +DB_RENDER_CONTROL__DEPTH_COPY_MASK = 0x00000004 # macro +DB_RENDER_CONTROL__STENCIL_COPY_MASK = 0x00000008 # macro +DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK = 0x00000010 # macro +DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK = 0x00000020 # macro +DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK = 0x00000040 # macro +DB_RENDER_CONTROL__COPY_CENTROID_MASK = 0x00000080 # macro +DB_RENDER_CONTROL__COPY_SAMPLE_MASK = 0x00000F00 # macro +DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK = 0x00001000 # macro +DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT = 0x0 # macro +DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT = 0x1 # macro +DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT = 0x4 # macro +DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT = 0x8 # macro +DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT = 0xc # macro +DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT = 0x10 # macro +DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT = 0x14 # macro +DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT = 0x18 # macro +DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT = 0x1c # macro +DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK = 0x00000001 # macro +DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK = 0x00000002 # macro +DB_COUNT_CONTROL__SAMPLE_RATE_MASK = 0x00000070 # macro +DB_COUNT_CONTROL__ZPASS_ENABLE_MASK = 0x00000F00 # macro +DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK = 0x0000F000 # macro +DB_COUNT_CONTROL__SFAIL_ENABLE_MASK = 0x000F0000 # macro +DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK = 0x00F00000 # macro +DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK = 0x0F000000 # macro +DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK = 0xF0000000 # macro +DB_DEPTH_VIEW__SLICE_START__SHIFT = 0x0 # macro +DB_DEPTH_VIEW__SLICE_MAX__SHIFT = 0xd # macro +DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT = 0x18 # macro +DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT = 0x19 # macro +DB_DEPTH_VIEW__MIPID__SHIFT = 0x1a # macro +DB_DEPTH_VIEW__SLICE_START_MASK = 0x000007FF # macro +DB_DEPTH_VIEW__SLICE_MAX_MASK = 0x00FFE000 # macro +DB_DEPTH_VIEW__Z_READ_ONLY_MASK = 0x01000000 # macro +DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK = 0x02000000 # macro +DB_DEPTH_VIEW__MIPID_MASK = 0x3C000000 # macro +DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT = 0x0 # macro +DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT = 0x2 # macro +DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT = 0x4 # macro +DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT = 0x6 # macro +DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT = 0x7 # macro +DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT = 0x8 # macro +DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT = 0x9 # macro +DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT = 0xa # macro +DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT = 0xb # macro +DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT = 0xc # macro +DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT = 0xd # macro +DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT = 0xf # macro +DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT = 0x10 # macro +DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT = 0x11 # macro +DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT = 0x12 # macro +DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT = 0x13 # macro +DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT = 0x15 # macro +DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT = 0x1a # macro +DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT = 0x1b # macro +DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT = 0x1c # macro +DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT = 0x1d # macro +DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT = 0x1e # macro +DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT = 0x1f # macro +DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK = 0x00000003 # macro +DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK = 0x0000000C # macro +DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK = 0x00000030 # macro +DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK = 0x00000040 # macro +DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK = 0x00000080 # macro +DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK = 0x00000100 # macro +DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK = 0x00000200 # macro +DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK = 0x00000400 # macro +DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK = 0x00000800 # macro +DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK = 0x00001000 # macro +DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK = 0x00006000 # macro +DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK = 0x00008000 # macro +DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK = 0x00010000 # macro +DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK = 0x00020000 # macro +DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK = 0x00040000 # macro +DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK = 0x00180000 # macro +DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK = 0x03E00000 # macro +DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK = 0x04000000 # macro +DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK = 0x08000000 # macro +DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK = 0x10000000 # macro +DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK = 0x20000000 # macro +DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK = 0x40000000 # macro +DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK = 0x80000000 # macro +DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT = 0x0 # macro +DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT = 0x2 # macro +DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT = 0x5 # macro +DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT = 0x6 # macro +DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT = 0x7 # macro +DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT = 0x8 # macro +DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT = 0x9 # macro +DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT = 0xa # macro +DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT = 0xb # macro +DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT = 0xc # macro +DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT = 0xf # macro +DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT = 0x12 # macro +DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT = 0x15 # macro +DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT = 0x16 # macro +DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT = 0x17 # macro +DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT = 0x19 # macro +DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK = 0x00000003 # macro +DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK = 0x0000001C # macro +DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK = 0x00000020 # macro +DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK = 0x00000040 # macro +DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK = 0x00000080 # macro +DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK = 0x00000100 # macro +DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK = 0x00000200 # macro +DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK = 0x00000400 # macro +DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK = 0x00000800 # macro +DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK = 0x00007000 # macro +DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK = 0x00038000 # macro +DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK = 0x001C0000 # macro +DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK = 0x00200000 # macro +DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK = 0x00400000 # macro +DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK = 0x00800000 # macro +DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK = 0x02000000 # macro +DB_HTILE_DATA_BASE__BASE_256B__SHIFT = 0x0 # macro +DB_HTILE_DATA_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT = 0x0 # macro +DB_HTILE_DATA_BASE_HI__BASE_HI_MASK = 0x000000FF # macro +DB_DEPTH_SIZE__X_MAX__SHIFT = 0x0 # macro +DB_DEPTH_SIZE__Y_MAX__SHIFT = 0x10 # macro +DB_DEPTH_SIZE__X_MAX_MASK = 0x00003FFF # macro +DB_DEPTH_SIZE__Y_MAX_MASK = 0x3FFF0000 # macro +DB_DEPTH_BOUNDS_MIN__MIN__SHIFT = 0x0 # macro +DB_DEPTH_BOUNDS_MIN__MIN_MASK = 0xFFFFFFFF # macro +DB_DEPTH_BOUNDS_MAX__MAX__SHIFT = 0x0 # macro +DB_DEPTH_BOUNDS_MAX__MAX_MASK = 0xFFFFFFFF # macro +DB_STENCIL_CLEAR__CLEAR__SHIFT = 0x0 # macro +DB_STENCIL_CLEAR__CLEAR_MASK = 0x000000FF # macro +DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT = 0x0 # macro +DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK = 0xFFFFFFFF # macro +PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK = 0x0000FFFF # macro +PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK = 0xFFFF0000 # macro +PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK = 0x0000FFFF # macro +PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK = 0xFFFF0000 # macro +DB_Z_INFO__FORMAT__SHIFT = 0x0 # macro +DB_Z_INFO__NUM_SAMPLES__SHIFT = 0x2 # macro +DB_Z_INFO__SW_MODE__SHIFT = 0x4 # macro +DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT = 0xc # macro +DB_Z_INFO__FAULT_BEHAVIOR__SHIFT = 0xd # macro +DB_Z_INFO__ITERATE_FLUSH__SHIFT = 0xf # macro +DB_Z_INFO__MAXMIP__SHIFT = 0x10 # macro +DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT = 0x17 # macro +DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT = 0x1b # macro +DB_Z_INFO__READ_SIZE__SHIFT = 0x1c # macro +DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT = 0x1d # macro +DB_Z_INFO__CLEAR_DISALLOWED__SHIFT = 0x1e # macro +DB_Z_INFO__ZRANGE_PRECISION__SHIFT = 0x1f # macro +DB_Z_INFO__FORMAT_MASK = 0x00000003 # macro +DB_Z_INFO__NUM_SAMPLES_MASK = 0x0000000C # macro +DB_Z_INFO__SW_MODE_MASK = 0x000001F0 # macro +DB_Z_INFO__PARTIALLY_RESIDENT_MASK = 0x00001000 # macro +DB_Z_INFO__FAULT_BEHAVIOR_MASK = 0x00006000 # macro +DB_Z_INFO__ITERATE_FLUSH_MASK = 0x00008000 # macro +DB_Z_INFO__MAXMIP_MASK = 0x000F0000 # macro +DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK = 0x07800000 # macro +DB_Z_INFO__ALLOW_EXPCLEAR_MASK = 0x08000000 # macro +DB_Z_INFO__READ_SIZE_MASK = 0x10000000 # macro +DB_Z_INFO__TILE_SURFACE_ENABLE_MASK = 0x20000000 # macro +DB_Z_INFO__CLEAR_DISALLOWED_MASK = 0x40000000 # macro +DB_Z_INFO__ZRANGE_PRECISION_MASK = 0x80000000 # macro +DB_STENCIL_INFO__FORMAT__SHIFT = 0x0 # macro +DB_STENCIL_INFO__SW_MODE__SHIFT = 0x4 # macro +DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT = 0xc # macro +DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT = 0xd # macro +DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT = 0xf # macro +DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT = 0x1b # macro +DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT = 0x1d # macro +DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT = 0x1e # macro +DB_STENCIL_INFO__FORMAT_MASK = 0x00000001 # macro +DB_STENCIL_INFO__SW_MODE_MASK = 0x000001F0 # macro +DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK = 0x00001000 # macro +DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK = 0x00006000 # macro +DB_STENCIL_INFO__ITERATE_FLUSH_MASK = 0x00008000 # macro +DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK = 0x08000000 # macro +DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK = 0x20000000 # macro +DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK = 0x40000000 # macro +DB_Z_READ_BASE__BASE_256B__SHIFT = 0x0 # macro +DB_Z_READ_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +DB_Z_READ_BASE_HI__BASE_HI__SHIFT = 0x0 # macro +DB_Z_READ_BASE_HI__BASE_HI_MASK = 0x000000FF # macro +DB_STENCIL_READ_BASE__BASE_256B__SHIFT = 0x0 # macro +DB_STENCIL_READ_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT = 0x0 # macro +DB_STENCIL_READ_BASE_HI__BASE_HI_MASK = 0x000000FF # macro +DB_Z_WRITE_BASE__BASE_256B__SHIFT = 0x0 # macro +DB_Z_WRITE_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT = 0x0 # macro +DB_Z_WRITE_BASE_HI__BASE_HI_MASK = 0x000000FF # macro +DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT = 0x0 # macro +DB_STENCIL_WRITE_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT = 0x0 # macro +DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK = 0x000000FF # macro +DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT = 0x0 # macro +DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT = 0x2 # macro +DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT = 0x3 # macro +DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK = 0x00000003 # macro +DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK = 0x00000004 # macro +DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK = 0x00000008 # macro +DB_Z_INFO2__EPITCH__SHIFT = 0x0 # macro +DB_Z_INFO2__EPITCH_MASK = 0x0000FFFF # macro +DB_STENCIL_INFO2__EPITCH__SHIFT = 0x0 # macro +DB_STENCIL_INFO2__EPITCH_MASK = 0x0000FFFF # macro +COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT = 0x0 # macro +COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK = 0x000000FF # macro +COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT = 0x0 # macro +COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK = 0x000000FF # macro +COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT = 0x0 # macro +COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK = 0x000000FF # macro +COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT = 0x0 # macro +COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK = 0x000000FF # macro +COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT = 0x0 # macro +COHER_DEST_BASE_2__DEST_BASE_256B_MASK = 0xFFFFFFFF # macro +COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT = 0x0 # macro +COHER_DEST_BASE_3__DEST_BASE_256B_MASK = 0xFFFFFFFF # macro +PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT = 0x0 # macro +PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT = 0x10 # macro +PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK = 0x0000FFFF # macro +PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK = 0xFFFF0000 # macro +PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT = 0x0 # macro +PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK = 0x0000FFFF # macro +PA_SC_CLIPRECT_0_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_CLIPRECT_0_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_CLIPRECT_0_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_CLIPRECT_0_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_CLIPRECT_0_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_CLIPRECT_0_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_CLIPRECT_1_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_CLIPRECT_1_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_CLIPRECT_1_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_CLIPRECT_1_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_CLIPRECT_1_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_CLIPRECT_1_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_CLIPRECT_2_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_CLIPRECT_2_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_CLIPRECT_2_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_CLIPRECT_2_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_CLIPRECT_2_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_CLIPRECT_2_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_CLIPRECT_3_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_CLIPRECT_3_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_CLIPRECT_3_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_CLIPRECT_3_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_CLIPRECT_3_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_CLIPRECT_3_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_EDGERULE__ER_TRI__SHIFT = 0x0 # macro +PA_SC_EDGERULE__ER_POINT__SHIFT = 0x4 # macro +PA_SC_EDGERULE__ER_RECT__SHIFT = 0x8 # macro +PA_SC_EDGERULE__ER_LINE_LR__SHIFT = 0xc # macro +PA_SC_EDGERULE__ER_LINE_RL__SHIFT = 0x12 # macro +PA_SC_EDGERULE__ER_LINE_TB__SHIFT = 0x18 # macro +PA_SC_EDGERULE__ER_LINE_BT__SHIFT = 0x1c # macro +PA_SC_EDGERULE__ER_TRI_MASK = 0x0000000F # macro +PA_SC_EDGERULE__ER_POINT_MASK = 0x000000F0 # macro +PA_SC_EDGERULE__ER_RECT_MASK = 0x00000F00 # macro +PA_SC_EDGERULE__ER_LINE_LR_MASK = 0x0003F000 # macro +PA_SC_EDGERULE__ER_LINE_RL_MASK = 0x00FC0000 # macro +PA_SC_EDGERULE__ER_LINE_TB_MASK = 0x0F000000 # macro +PA_SC_EDGERULE__ER_LINE_BT_MASK = 0xF0000000 # macro +PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT = 0x0 # macro +PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT = 0x10 # macro +PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK = 0x000001FF # macro +PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK = 0x01FF0000 # macro +CB_TARGET_MASK__TARGET0_ENABLE__SHIFT = 0x0 # macro +CB_TARGET_MASK__TARGET1_ENABLE__SHIFT = 0x4 # macro +CB_TARGET_MASK__TARGET2_ENABLE__SHIFT = 0x8 # macro +CB_TARGET_MASK__TARGET3_ENABLE__SHIFT = 0xc # macro +CB_TARGET_MASK__TARGET4_ENABLE__SHIFT = 0x10 # macro +CB_TARGET_MASK__TARGET5_ENABLE__SHIFT = 0x14 # macro +CB_TARGET_MASK__TARGET6_ENABLE__SHIFT = 0x18 # macro +CB_TARGET_MASK__TARGET7_ENABLE__SHIFT = 0x1c # macro +CB_TARGET_MASK__TARGET0_ENABLE_MASK = 0x0000000F # macro +CB_TARGET_MASK__TARGET1_ENABLE_MASK = 0x000000F0 # macro +CB_TARGET_MASK__TARGET2_ENABLE_MASK = 0x00000F00 # macro +CB_TARGET_MASK__TARGET3_ENABLE_MASK = 0x0000F000 # macro +CB_TARGET_MASK__TARGET4_ENABLE_MASK = 0x000F0000 # macro +CB_TARGET_MASK__TARGET5_ENABLE_MASK = 0x00F00000 # macro +CB_TARGET_MASK__TARGET6_ENABLE_MASK = 0x0F000000 # macro +CB_TARGET_MASK__TARGET7_ENABLE_MASK = 0xF0000000 # macro +CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT = 0x0 # macro +CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT = 0x4 # macro +CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT = 0x8 # macro +CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT = 0xc # macro +CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT = 0x10 # macro +CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT = 0x14 # macro +CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT = 0x18 # macro +CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT = 0x1c # macro +CB_SHADER_MASK__OUTPUT0_ENABLE_MASK = 0x0000000F # macro +CB_SHADER_MASK__OUTPUT1_ENABLE_MASK = 0x000000F0 # macro +CB_SHADER_MASK__OUTPUT2_ENABLE_MASK = 0x00000F00 # macro +CB_SHADER_MASK__OUTPUT3_ENABLE_MASK = 0x0000F000 # macro +CB_SHADER_MASK__OUTPUT4_ENABLE_MASK = 0x000F0000 # macro +CB_SHADER_MASK__OUTPUT5_ENABLE_MASK = 0x00F00000 # macro +CB_SHADER_MASK__OUTPUT6_ENABLE_MASK = 0x0F000000 # macro +CB_SHADER_MASK__OUTPUT7_ENABLE_MASK = 0xF0000000 # macro +PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK = 0x7FFF0000 # macro +COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT = 0x0 # macro +COHER_DEST_BASE_0__DEST_BASE_256B_MASK = 0xFFFFFFFF # macro +COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT = 0x0 # macro +COHER_DEST_BASE_1__DEST_BASE_256B_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT = 0x1f # macro +PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK = 0x80000000 # macro +PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT = 0x0 # macro +PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT = 0x10 # macro +PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK = 0x00007FFF # macro +PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK = 0x7FFF0000 # macro +PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK = 0xFFFFFFFF # macro +PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT = 0x0 # macro +PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK = 0xFFFFFFFF # macro +PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT = 0x0 # macro +PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT = 0x2 # macro +PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT = 0x4 # macro +PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT = 0x6 # macro +PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT = 0x7 # macro +PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT = 0x8 # macro +PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT = 0xa # macro +PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT = 0xc # macro +PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT = 0xe # macro +PA_SC_RASTER_CONFIG__SC_MAP__SHIFT = 0x10 # macro +PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT = 0x12 # macro +PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT = 0x14 # macro +PA_SC_RASTER_CONFIG__SE_MAP__SHIFT = 0x18 # macro +PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT = 0x1a # macro +PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT = 0x1d # macro +PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK = 0x00000003 # macro +PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK = 0x0000000C # macro +PA_SC_RASTER_CONFIG__RB_XSEL2_MASK = 0x00000030 # macro +PA_SC_RASTER_CONFIG__RB_XSEL_MASK = 0x00000040 # macro +PA_SC_RASTER_CONFIG__RB_YSEL_MASK = 0x00000080 # macro +PA_SC_RASTER_CONFIG__PKR_MAP_MASK = 0x00000300 # macro +PA_SC_RASTER_CONFIG__PKR_XSEL_MASK = 0x00000C00 # macro +PA_SC_RASTER_CONFIG__PKR_YSEL_MASK = 0x00003000 # macro +PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK = 0x0000C000 # macro +PA_SC_RASTER_CONFIG__SC_MAP_MASK = 0x00030000 # macro +PA_SC_RASTER_CONFIG__SC_XSEL_MASK = 0x000C0000 # macro +PA_SC_RASTER_CONFIG__SC_YSEL_MASK = 0x00300000 # macro +PA_SC_RASTER_CONFIG__SE_MAP_MASK = 0x03000000 # macro +PA_SC_RASTER_CONFIG__SE_XSEL_MASK = 0x1C000000 # macro +PA_SC_RASTER_CONFIG__SE_YSEL_MASK = 0xE0000000 # macro +PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT = 0x0 # macro +PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT = 0x2 # macro +PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT = 0x5 # macro +PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK = 0x00000003 # macro +PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK = 0x0000001C # macro +PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK = 0x000000E0 # macro +PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT = 0x0 # macro +PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT = 0x2 # macro +PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK = 0x00000003 # macro +PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK = 0x0000000C # macro +PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT = 0x0 # macro +PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT = 0x1 # macro +PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT = 0x5 # macro +PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT = 0x8 # macro +PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK = 0x00000001 # macro +PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK = 0x00000006 # macro +PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK = 0x00000060 # macro +PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK = 0x00000100 # macro +CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT = 0x1f # macro +CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK = 0x80000000 # macro +CP_PIPEID__PIPE_ID__SHIFT = 0x0 # macro +CP_PIPEID__PIPE_ID_MASK = 0x00000003 # macro +CP_RINGID__RINGID__SHIFT = 0x0 # macro +CP_RINGID__RINGID_MASK = 0x00000003 # macro +CP_VMID__VMID__SHIFT = 0x0 # macro +CP_VMID__VMID_MASK = 0x0000000F # macro +PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT = 0x0 # macro +PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT = 0x8 # macro +PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT = 0x10 # macro +PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT = 0x18 # macro +PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK = 0x000000FF # macro +PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK = 0x0000FF00 # macro +PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK = 0x00FF0000 # macro +PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK = 0xFF000000 # macro +PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT = 0x0 # macro +PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT = 0x8 # macro +PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT = 0x10 # macro +PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT = 0x18 # macro +PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK = 0x000000FF # macro +PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK = 0x0000FF00 # macro +PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK = 0x00FF0000 # macro +PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK = 0xFF000000 # macro +PA_SC_HORIZ_GRID__TOP_QTR__SHIFT = 0x0 # macro +PA_SC_HORIZ_GRID__TOP_HALF__SHIFT = 0x8 # macro +PA_SC_HORIZ_GRID__BOT_HALF__SHIFT = 0x10 # macro +PA_SC_HORIZ_GRID__BOT_QTR__SHIFT = 0x18 # macro +PA_SC_HORIZ_GRID__TOP_QTR_MASK = 0x000000FF # macro +PA_SC_HORIZ_GRID__TOP_HALF_MASK = 0x0000FF00 # macro +PA_SC_HORIZ_GRID__BOT_HALF_MASK = 0x00FF0000 # macro +PA_SC_HORIZ_GRID__BOT_QTR_MASK = 0xFF000000 # macro +VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT = 0x0 # macro +VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK = 0xFFFFFFFF # macro +CB_BLEND_RED__BLEND_RED__SHIFT = 0x0 # macro +CB_BLEND_RED__BLEND_RED_MASK = 0xFFFFFFFF # macro +CB_BLEND_GREEN__BLEND_GREEN__SHIFT = 0x0 # macro +CB_BLEND_GREEN__BLEND_GREEN_MASK = 0xFFFFFFFF # macro +CB_BLEND_BLUE__BLEND_BLUE__SHIFT = 0x0 # macro +CB_BLEND_BLUE__BLEND_BLUE_MASK = 0xFFFFFFFF # macro +CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT = 0x0 # macro +CB_BLEND_ALPHA__BLEND_ALPHA_MASK = 0xFFFFFFFF # macro +CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT = 0x0 # macro +CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT = 0x1 # macro +CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT = 0x2 # macro +CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01__SHIFT = 0x8 # macro +CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE__SHIFT = 0x9 # macro +CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT = 0xa # macro +CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01__SHIFT = 0xc # macro +CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE__SHIFT = 0xd # macro +CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG__SHIFT = 0xe # macro +CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK = 0x00000001 # macro +CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK = 0x00000002 # macro +CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK = 0x0000007C # macro +CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01_MASK = 0x00000100 # macro +CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE_MASK = 0x00000200 # macro +CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK = 0x00000400 # macro +CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01_MASK = 0x00001000 # macro +CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE_MASK = 0x00002000 # macro +CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG_MASK = 0x00004000 # macro +DB_STENCIL_CONTROL__STENCILFAIL__SHIFT = 0x0 # macro +DB_STENCIL_CONTROL__STENCILZPASS__SHIFT = 0x4 # macro +DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT = 0x8 # macro +DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT = 0xc # macro +DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT = 0x10 # macro +DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT = 0x14 # macro +DB_STENCIL_CONTROL__STENCILFAIL_MASK = 0x0000000F # macro +DB_STENCIL_CONTROL__STENCILZPASS_MASK = 0x000000F0 # macro +DB_STENCIL_CONTROL__STENCILZFAIL_MASK = 0x00000F00 # macro +DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK = 0x0000F000 # macro +DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK = 0x000F0000 # macro +DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK = 0x00F00000 # macro +DB_STENCILREFMASK__STENCILTESTVAL__SHIFT = 0x0 # macro +DB_STENCILREFMASK__STENCILMASK__SHIFT = 0x8 # macro +DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT = 0x10 # macro +DB_STENCILREFMASK__STENCILOPVAL__SHIFT = 0x18 # macro +DB_STENCILREFMASK__STENCILTESTVAL_MASK = 0x000000FF # macro +DB_STENCILREFMASK__STENCILMASK_MASK = 0x0000FF00 # macro +DB_STENCILREFMASK__STENCILWRITEMASK_MASK = 0x00FF0000 # macro +DB_STENCILREFMASK__STENCILOPVAL_MASK = 0xFF000000 # macro +DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT = 0x0 # macro +DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT = 0x8 # macro +DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT = 0x10 # macro +DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT = 0x18 # macro +DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK = 0x000000FF # macro +DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK = 0x0000FF00 # macro +DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK = 0x00FF0000 # macro +DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK = 0xFF000000 # macro +PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT = 0x0 # macro +PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK = 0xFFFFFFFF # macro +PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT = 0x0 # macro +PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_0_X__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_0_X__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_0_Y__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_0_Z__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_0_W__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_0_W__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_1_X__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_1_X__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_1_Y__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_1_Z__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_1_W__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_1_W__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_2_X__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_2_X__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_2_Y__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_2_Z__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_2_W__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_2_W__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_3_X__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_3_X__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_3_Y__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_3_Z__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_3_W__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_3_W__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_4_X__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_4_X__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_4_Y__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_4_Z__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_4_W__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_4_W__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_5_X__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_5_X__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_5_Y__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_5_Z__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_UCP_5_W__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_UCP_5_W__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT = 0xd # macro +SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_0__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_0__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK = 0x0001E000 # macro +SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_0__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT = 0xd # macro +SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_1__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_1__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK = 0x0001E000 # macro +SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_1__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT = 0xd # macro +SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_2__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_2__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK = 0x0001E000 # macro +SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_2__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT = 0xd # macro +SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_3__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_3__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK = 0x0001E000 # macro +SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_3__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT = 0xd # macro +SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_4__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_4__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK = 0x0001E000 # macro +SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_4__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT = 0xd # macro +SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_5__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_5__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK = 0x0001E000 # macro +SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_5__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT = 0xd # macro +SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_6__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_6__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK = 0x0001E000 # macro +SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_6__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT = 0xd # macro +SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_7__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_7__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK = 0x0001E000 # macro +SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_7__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT = 0xd # macro +SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_8__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_8__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK = 0x0001E000 # macro +SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_8__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT = 0xd # macro +SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_9__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_9__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK = 0x0001E000 # macro +SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_9__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT = 0xd # macro +SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_10__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_10__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK = 0x0001E000 # macro +SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_10__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT = 0xd # macro +SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_11__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_11__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK = 0x0001E000 # macro +SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_11__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT = 0xd # macro +SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_12__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_12__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK = 0x0001E000 # macro +SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_12__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT = 0xd # macro +SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_13__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_13__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK = 0x0001E000 # macro +SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_13__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT = 0xd # macro +SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_14__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_14__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK = 0x0001E000 # macro +SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_14__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT = 0xd # macro +SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_15__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_15__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK = 0x0001E000 # macro +SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_15__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT = 0xd # macro +SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_16__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_16__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK = 0x0001E000 # macro +SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_16__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT = 0xd # macro +SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_17__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_17__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK = 0x0001E000 # macro +SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_17__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT = 0xd # macro +SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_18__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_18__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK = 0x0001E000 # macro +SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_18__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT = 0xd # macro +SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT = 0x11 # macro +SPI_PS_INPUT_CNTL_19__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT = 0x17 # macro +SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_19__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK = 0x0001E000 # macro +SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK = 0x00020000 # macro +SPI_PS_INPUT_CNTL_19__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK = 0x00800000 # macro +SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_20__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_20__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_20__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_21__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_21__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_21__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_22__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_22__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_22__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_23__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_23__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_23__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_24__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_24__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_24__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_25__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_25__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_25__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_26__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_26__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_26__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_27__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_27__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_27__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_28__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_28__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_28__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_29__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_29__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_29__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_30__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_30__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_30__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT = 0x0 # macro +SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT = 0x8 # macro +SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT = 0xa # macro +SPI_PS_INPUT_CNTL_31__DUP__SHIFT = 0x12 # macro +SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT = 0x13 # macro +SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT = 0x14 # macro +SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT = 0x15 # macro +SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT = 0x18 # macro +SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT = 0x19 # macro +SPI_PS_INPUT_CNTL_31__OFFSET_MASK = 0x0000003F # macro +SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK = 0x00000300 # macro +SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK = 0x00000400 # macro +SPI_PS_INPUT_CNTL_31__DUP_MASK = 0x00040000 # macro +SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK = 0x00080000 # macro +SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK = 0x00100000 # macro +SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK = 0x00600000 # macro +SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK = 0x01000000 # macro +SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK = 0x02000000 # macro +SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT = 0x1 # macro +SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT = 0x6 # macro +SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK = 0x0000003E # macro +SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK = 0x00000040 # macro +SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT = 0x0 # macro +SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT = 0x1 # macro +SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT = 0x2 # macro +SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT = 0x3 # macro +SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT = 0x4 # macro +SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT = 0x5 # macro +SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT = 0x6 # macro +SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT = 0x7 # macro +SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT = 0x8 # macro +SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT = 0x9 # macro +SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT = 0xa # macro +SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT = 0xb # macro +SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT = 0xc # macro +SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT = 0xd # macro +SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT = 0xe # macro +SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT = 0xf # macro +SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK = 0x00000001 # macro +SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK = 0x00000002 # macro +SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK = 0x00000004 # macro +SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK = 0x00000008 # macro +SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK = 0x00000010 # macro +SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK = 0x00000020 # macro +SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK = 0x00000040 # macro +SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK = 0x00000080 # macro +SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK = 0x00000100 # macro +SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK = 0x00000200 # macro +SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK = 0x00000400 # macro +SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK = 0x00000800 # macro +SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK = 0x00001000 # macro +SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK = 0x00002000 # macro +SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK = 0x00004000 # macro +SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK = 0x00008000 # macro +SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT = 0x0 # macro +SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT = 0x1 # macro +SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT = 0x2 # macro +SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT = 0x3 # macro +SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT = 0x4 # macro +SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT = 0x5 # macro +SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT = 0x6 # macro +SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT = 0x7 # macro +SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT = 0x8 # macro +SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT = 0x9 # macro +SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT = 0xa # macro +SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT = 0xb # macro +SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT = 0xc # macro +SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT = 0xd # macro +SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT = 0xe # macro +SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT = 0xf # macro +SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK = 0x00000001 # macro +SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK = 0x00000002 # macro +SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK = 0x00000004 # macro +SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK = 0x00000008 # macro +SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK = 0x00000010 # macro +SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK = 0x00000020 # macro +SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK = 0x00000040 # macro +SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK = 0x00000080 # macro +SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK = 0x00000100 # macro +SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK = 0x00000200 # macro +SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK = 0x00000400 # macro +SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK = 0x00000800 # macro +SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK = 0x00001000 # macro +SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK = 0x00002000 # macro +SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK = 0x00004000 # macro +SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK = 0x00008000 # macro +SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT = 0x0 # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT = 0x1 # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT = 0x2 # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT = 0x5 # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT = 0x8 # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT = 0xb # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT = 0xe # macro +SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK = 0x00000001 # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK = 0x00000002 # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK = 0x0000001C # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK = 0x000000E0 # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK = 0x00000700 # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK = 0x00003800 # macro +SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK = 0x00004000 # macro +SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT = 0x0 # macro +SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT = 0x6 # macro +SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT = 0x7 # macro +SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT = 0x8 # macro +SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT = 0xe # macro +SPI_PS_IN_CONTROL__NUM_INTERP_MASK = 0x0000003F # macro +SPI_PS_IN_CONTROL__PARAM_GEN_MASK = 0x00000040 # macro +SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK = 0x00000080 # macro +SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK = 0x00000100 # macro +SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK = 0x00004000 # macro +SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT = 0x0 # macro +SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT = 0x4 # macro +SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT = 0x8 # macro +SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT = 0xc # macro +SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT = 0x10 # macro +SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT = 0x14 # macro +SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT = 0x18 # macro +SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK = 0x00000001 # macro +SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK = 0x00000010 # macro +SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK = 0x00000100 # macro +SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK = 0x00001000 # macro +SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK = 0x00030000 # macro +SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK = 0x00100000 # macro +SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK = 0x01000000 # macro +SPI_TMPRING_SIZE__WAVES__SHIFT = 0x0 # macro +SPI_TMPRING_SIZE__WAVESIZE__SHIFT = 0xc # macro +SPI_TMPRING_SIZE__WAVES_MASK = 0x00000FFF # macro +SPI_TMPRING_SIZE__WAVESIZE_MASK = 0x01FFF000 # macro +SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT = 0x0 # macro +SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT = 0x4 # macro +SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT = 0x8 # macro +SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT = 0xc # macro +SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK = 0x0000000F # macro +SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK = 0x000000F0 # macro +SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK = 0x00000F00 # macro +SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK = 0x0000F000 # macro +SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT = 0x0 # macro +SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK = 0x0000000F # macro +SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT = 0x0 # macro +SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT = 0x4 # macro +SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT = 0x8 # macro +SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT = 0xc # macro +SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT = 0x10 # macro +SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT = 0x14 # macro +SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT = 0x18 # macro +SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT = 0x1c # macro +SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK = 0x0000000F # macro +SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK = 0x000000F0 # macro +SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK = 0x00000F00 # macro +SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK = 0x0000F000 # macro +SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK = 0x000F0000 # macro +SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK = 0x00F00000 # macro +SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK = 0x0F000000 # macro +SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK = 0xF0000000 # macro +CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT = 0x0 # macro +CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT = 0x5 # macro +CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT = 0x8 # macro +CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT = 0x10 # macro +CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT = 0x15 # macro +CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT = 0x18 # macro +CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT = 0x1d # macro +CB_BLEND0_CONTROL__ENABLE__SHIFT = 0x1e # macro +CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT = 0x1f # macro +CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK = 0x0000001F # macro +CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK = 0x000000E0 # macro +CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK = 0x00001F00 # macro +CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK = 0x001F0000 # macro +CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK = 0x00E00000 # macro +CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK = 0x1F000000 # macro +CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK = 0x20000000 # macro +CB_BLEND0_CONTROL__ENABLE_MASK = 0x40000000 # macro +CB_BLEND0_CONTROL__DISABLE_ROP3_MASK = 0x80000000 # macro +CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT = 0x0 # macro +CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT = 0x5 # macro +CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT = 0x8 # macro +CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT = 0x10 # macro +CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT = 0x15 # macro +CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT = 0x18 # macro +CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT = 0x1d # macro +CB_BLEND1_CONTROL__ENABLE__SHIFT = 0x1e # macro +CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT = 0x1f # macro +CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK = 0x0000001F # macro +CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK = 0x000000E0 # macro +CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK = 0x00001F00 # macro +CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK = 0x001F0000 # macro +CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK = 0x00E00000 # macro +CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK = 0x1F000000 # macro +CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK = 0x20000000 # macro +CB_BLEND1_CONTROL__ENABLE_MASK = 0x40000000 # macro +CB_BLEND1_CONTROL__DISABLE_ROP3_MASK = 0x80000000 # macro +CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT = 0x0 # macro +CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT = 0x5 # macro +CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT = 0x8 # macro +CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT = 0x10 # macro +CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT = 0x15 # macro +CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT = 0x18 # macro +CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT = 0x1d # macro +CB_BLEND2_CONTROL__ENABLE__SHIFT = 0x1e # macro +CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT = 0x1f # macro +CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK = 0x0000001F # macro +CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK = 0x000000E0 # macro +CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK = 0x00001F00 # macro +CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK = 0x001F0000 # macro +CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK = 0x00E00000 # macro +CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK = 0x1F000000 # macro +CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK = 0x20000000 # macro +CB_BLEND2_CONTROL__ENABLE_MASK = 0x40000000 # macro +CB_BLEND2_CONTROL__DISABLE_ROP3_MASK = 0x80000000 # macro +CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT = 0x0 # macro +CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT = 0x5 # macro +CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT = 0x8 # macro +CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT = 0x10 # macro +CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT = 0x15 # macro +CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT = 0x18 # macro +CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT = 0x1d # macro +CB_BLEND3_CONTROL__ENABLE__SHIFT = 0x1e # macro +CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT = 0x1f # macro +CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK = 0x0000001F # macro +CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK = 0x000000E0 # macro +CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK = 0x00001F00 # macro +CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK = 0x001F0000 # macro +CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK = 0x00E00000 # macro +CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK = 0x1F000000 # macro +CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK = 0x20000000 # macro +CB_BLEND3_CONTROL__ENABLE_MASK = 0x40000000 # macro +CB_BLEND3_CONTROL__DISABLE_ROP3_MASK = 0x80000000 # macro +CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT = 0x0 # macro +CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT = 0x5 # macro +CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT = 0x8 # macro +CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT = 0x10 # macro +CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT = 0x15 # macro +CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT = 0x18 # macro +CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT = 0x1d # macro +CB_BLEND4_CONTROL__ENABLE__SHIFT = 0x1e # macro +CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT = 0x1f # macro +CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK = 0x0000001F # macro +CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK = 0x000000E0 # macro +CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK = 0x00001F00 # macro +CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK = 0x001F0000 # macro +CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK = 0x00E00000 # macro +CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK = 0x1F000000 # macro +CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK = 0x20000000 # macro +CB_BLEND4_CONTROL__ENABLE_MASK = 0x40000000 # macro +CB_BLEND4_CONTROL__DISABLE_ROP3_MASK = 0x80000000 # macro +CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT = 0x0 # macro +CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT = 0x5 # macro +CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT = 0x8 # macro +CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT = 0x10 # macro +CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT = 0x15 # macro +CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT = 0x18 # macro +CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT = 0x1d # macro +CB_BLEND5_CONTROL__ENABLE__SHIFT = 0x1e # macro +CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT = 0x1f # macro +CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK = 0x0000001F # macro +CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK = 0x000000E0 # macro +CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK = 0x00001F00 # macro +CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK = 0x001F0000 # macro +CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK = 0x00E00000 # macro +CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK = 0x1F000000 # macro +CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK = 0x20000000 # macro +CB_BLEND5_CONTROL__ENABLE_MASK = 0x40000000 # macro +CB_BLEND5_CONTROL__DISABLE_ROP3_MASK = 0x80000000 # macro +CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT = 0x0 # macro +CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT = 0x5 # macro +CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT = 0x8 # macro +CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT = 0x10 # macro +CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT = 0x15 # macro +CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT = 0x18 # macro +CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT = 0x1d # macro +CB_BLEND6_CONTROL__ENABLE__SHIFT = 0x1e # macro +CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT = 0x1f # macro +CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK = 0x0000001F # macro +CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK = 0x000000E0 # macro +CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK = 0x00001F00 # macro +CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK = 0x001F0000 # macro +CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK = 0x00E00000 # macro +CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK = 0x1F000000 # macro +CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK = 0x20000000 # macro +CB_BLEND6_CONTROL__ENABLE_MASK = 0x40000000 # macro +CB_BLEND6_CONTROL__DISABLE_ROP3_MASK = 0x80000000 # macro +CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT = 0x0 # macro +CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT = 0x5 # macro +CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT = 0x8 # macro +CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT = 0x10 # macro +CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT = 0x15 # macro +CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT = 0x18 # macro +CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT = 0x1d # macro +CB_BLEND7_CONTROL__ENABLE__SHIFT = 0x1e # macro +CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT = 0x1f # macro +CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK = 0x0000001F # macro +CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK = 0x000000E0 # macro +CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK = 0x00001F00 # macro +CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK = 0x001F0000 # macro +CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK = 0x00E00000 # macro +CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK = 0x1F000000 # macro +CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK = 0x20000000 # macro +CB_BLEND7_CONTROL__ENABLE_MASK = 0x40000000 # macro +CB_BLEND7_CONTROL__DISABLE_ROP3_MASK = 0x80000000 # macro +CB_MRT0_EPITCH__EPITCH__SHIFT = 0x0 # macro +CB_MRT0_EPITCH__EPITCH_MASK = 0x0000FFFF # macro +CB_MRT1_EPITCH__EPITCH__SHIFT = 0x0 # macro +CB_MRT1_EPITCH__EPITCH_MASK = 0x0000FFFF # macro +CB_MRT2_EPITCH__EPITCH__SHIFT = 0x0 # macro +CB_MRT2_EPITCH__EPITCH_MASK = 0x0000FFFF # macro +CB_MRT3_EPITCH__EPITCH__SHIFT = 0x0 # macro +CB_MRT3_EPITCH__EPITCH_MASK = 0x0000FFFF # macro +CB_MRT4_EPITCH__EPITCH__SHIFT = 0x0 # macro +CB_MRT4_EPITCH__EPITCH_MASK = 0x0000FFFF # macro +CB_MRT5_EPITCH__EPITCH__SHIFT = 0x0 # macro +CB_MRT5_EPITCH__EPITCH_MASK = 0x0000FFFF # macro +CB_MRT6_EPITCH__EPITCH__SHIFT = 0x0 # macro +CB_MRT6_EPITCH__EPITCH_MASK = 0x0000FFFF # macro +CB_MRT7_EPITCH__EPITCH__SHIFT = 0x0 # macro +CB_MRT7_EPITCH__EPITCH_MASK = 0x0000FFFF # macro +CS_COPY_STATE__SRC_STATE_ID__SHIFT = 0x0 # macro +CS_COPY_STATE__SRC_STATE_ID_MASK = 0x00000007 # macro +GFX_COPY_STATE__SRC_STATE_ID__SHIFT = 0x0 # macro +GFX_COPY_STATE__SRC_STATE_ID_MASK = 0x00000007 # macro +PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_POINT_X_RAD__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_POINT_SIZE__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +VGT_DMA_BASE_HI__BASE_ADDR__SHIFT = 0x0 # macro +VGT_DMA_BASE_HI__BASE_ADDR_MASK = 0x0000FFFF # macro +VGT_DMA_BASE__BASE_ADDR__SHIFT = 0x0 # macro +VGT_DMA_BASE__BASE_ADDR_MASK = 0xFFFFFFFF # macro +VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT = 0x0 # macro +VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT = 0x2 # macro +VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT = 0x4 # macro +VGT_DRAW_INITIATOR__NOT_EOP__SHIFT = 0x5 # macro +VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT = 0x6 # macro +VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT = 0x7 # macro +VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT = 0x8 # macro +VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT = 0x1d # macro +VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK = 0x00000003 # macro +VGT_DRAW_INITIATOR__MAJOR_MODE_MASK = 0x0000000C # macro +VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK = 0x00000010 # macro +VGT_DRAW_INITIATOR__NOT_EOP_MASK = 0x00000020 # macro +VGT_DRAW_INITIATOR__USE_OPAQUE_MASK = 0x00000040 # macro +VGT_DRAW_INITIATOR__UNROLLED_INST_MASK = 0x00000080 # macro +VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK = 0x00000100 # macro +VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK = 0xE0000000 # macro +VGT_IMMED_DATA__DATA__SHIFT = 0x0 # macro +VGT_IMMED_DATA__DATA_MASK = 0xFFFFFFFF # macro +VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT = 0x0 # macro +VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK = 0x0FFFFFFF # macro +DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT = 0x0 # macro +DB_DEPTH_CONTROL__Z_ENABLE__SHIFT = 0x1 # macro +DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT = 0x2 # macro +DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT = 0x3 # macro +DB_DEPTH_CONTROL__ZFUNC__SHIFT = 0x4 # macro +DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT = 0x7 # macro +DB_DEPTH_CONTROL__STENCILFUNC__SHIFT = 0x8 # macro +DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT = 0x14 # macro +DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT = 0x1e # macro +DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT = 0x1f # macro +DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK = 0x00000001 # macro +DB_DEPTH_CONTROL__Z_ENABLE_MASK = 0x00000002 # macro +DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK = 0x00000004 # macro +DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK = 0x00000008 # macro +DB_DEPTH_CONTROL__ZFUNC_MASK = 0x00000070 # macro +DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK = 0x00000080 # macro +DB_DEPTH_CONTROL__STENCILFUNC_MASK = 0x00000700 # macro +DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK = 0x00700000 # macro +DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK = 0x40000000 # macro +DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK = 0x80000000 # macro +DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT = 0x0 # macro +DB_EQAA__PS_ITER_SAMPLES__SHIFT = 0x4 # macro +DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT = 0x8 # macro +DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT = 0xc # macro +DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT = 0x10 # macro +DB_EQAA__INCOHERENT_EQAA_READS__SHIFT = 0x11 # macro +DB_EQAA__INTERPOLATE_COMP_Z__SHIFT = 0x12 # macro +DB_EQAA__INTERPOLATE_SRC_Z__SHIFT = 0x13 # macro +DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT = 0x14 # macro +DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT = 0x15 # macro +DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT = 0x18 # macro +DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT = 0x1b # macro +DB_EQAA__MAX_ANCHOR_SAMPLES_MASK = 0x00000007 # macro +DB_EQAA__PS_ITER_SAMPLES_MASK = 0x00000070 # macro +DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK = 0x00000700 # macro +DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK = 0x00007000 # macro +DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK = 0x00010000 # macro +DB_EQAA__INCOHERENT_EQAA_READS_MASK = 0x00020000 # macro +DB_EQAA__INTERPOLATE_COMP_Z_MASK = 0x00040000 # macro +DB_EQAA__INTERPOLATE_SRC_Z_MASK = 0x00080000 # macro +DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK = 0x00100000 # macro +DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK = 0x00200000 # macro +DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK = 0x07000000 # macro +DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK = 0x08000000 # macro +CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT = 0x0 # macro +CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT = 0x3 # macro +CB_COLOR_CONTROL__MODE__SHIFT = 0x4 # macro +CB_COLOR_CONTROL__ROP3__SHIFT = 0x10 # macro +CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK = 0x00000001 # macro +CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK = 0x00000008 # macro +CB_COLOR_CONTROL__MODE_MASK = 0x00000070 # macro +CB_COLOR_CONTROL__ROP3_MASK = 0x00FF0000 # macro +DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT = 0x0 # macro +DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT = 0x1 # macro +DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT = 0x2 # macro +DB_SHADER_CONTROL__Z_ORDER__SHIFT = 0x4 # macro +DB_SHADER_CONTROL__KILL_ENABLE__SHIFT = 0x6 # macro +DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT = 0x7 # macro +DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT = 0x8 # macro +DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT = 0x9 # macro +DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT = 0xa # macro +DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT = 0xb # macro +DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT = 0xc # macro +DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT = 0xd # macro +DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT = 0xf # macro +DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT = 0x10 # macro +DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT = 0x11 # macro +DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT = 0x14 # macro +DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK = 0x00000001 # macro +DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK = 0x00000002 # macro +DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK = 0x00000004 # macro +DB_SHADER_CONTROL__Z_ORDER_MASK = 0x00000030 # macro +DB_SHADER_CONTROL__KILL_ENABLE_MASK = 0x00000040 # macro +DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK = 0x00000080 # macro +DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK = 0x00000100 # macro +DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK = 0x00000200 # macro +DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK = 0x00000400 # macro +DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK = 0x00000800 # macro +DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK = 0x00001000 # macro +DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK = 0x00006000 # macro +DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK = 0x00008000 # macro +DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK = 0x00010000 # macro +DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK = 0x00020000 # macro +DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK = 0x00700000 # macro +PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT = 0x0 # macro +PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT = 0x1 # macro +PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT = 0x2 # macro +PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT = 0x3 # macro +PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT = 0x4 # macro +PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT = 0x5 # macro +PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT = 0xd # macro +PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT = 0xe # macro +PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT = 0x10 # macro +PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT = 0x11 # macro +PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT = 0x12 # macro +PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT = 0x13 # macro +PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT = 0x14 # macro +PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT = 0x15 # macro +PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT = 0x16 # macro +PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT = 0x18 # macro +PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT = 0x19 # macro +PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT = 0x1a # macro +PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT = 0x1b # macro +PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA__SHIFT = 0x1c # macro +PA_CL_CLIP_CNTL__UCP_ENA_0_MASK = 0x00000001 # macro +PA_CL_CLIP_CNTL__UCP_ENA_1_MASK = 0x00000002 # macro +PA_CL_CLIP_CNTL__UCP_ENA_2_MASK = 0x00000004 # macro +PA_CL_CLIP_CNTL__UCP_ENA_3_MASK = 0x00000008 # macro +PA_CL_CLIP_CNTL__UCP_ENA_4_MASK = 0x00000010 # macro +PA_CL_CLIP_CNTL__UCP_ENA_5_MASK = 0x00000020 # macro +PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK = 0x00002000 # macro +PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK = 0x0000C000 # macro +PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK = 0x00010000 # macro +PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK = 0x00020000 # macro +PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK = 0x00040000 # macro +PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK = 0x00080000 # macro +PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK = 0x00100000 # macro +PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK = 0x00200000 # macro +PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK = 0x00400000 # macro +PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK = 0x01000000 # macro +PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK = 0x02000000 # macro +PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK = 0x04000000 # macro +PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK = 0x08000000 # macro +PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA_MASK = 0x10000000 # macro +PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT = 0x0 # macro +PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT = 0x1 # macro +PA_SU_SC_MODE_CNTL__FACE__SHIFT = 0x2 # macro +PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT = 0x3 # macro +PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT = 0x5 # macro +PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT = 0x8 # macro +PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT = 0xb # macro +PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT = 0xc # macro +PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT = 0xd # macro +PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT = 0x10 # macro +PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT = 0x13 # macro +PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT = 0x14 # macro +PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT = 0x15 # macro +PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT = 0x16 # macro +PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT = 0x17 # macro +PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK = 0x00000001 # macro +PA_SU_SC_MODE_CNTL__CULL_BACK_MASK = 0x00000002 # macro +PA_SU_SC_MODE_CNTL__FACE_MASK = 0x00000004 # macro +PA_SU_SC_MODE_CNTL__POLY_MODE_MASK = 0x00000018 # macro +PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK = 0x000000E0 # macro +PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK = 0x00000700 # macro +PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK = 0x00000800 # macro +PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK = 0x00001000 # macro +PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK = 0x00002000 # macro +PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK = 0x00010000 # macro +PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK = 0x00080000 # macro +PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK = 0x00100000 # macro +PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK = 0x00200000 # macro +PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK = 0x00400000 # macro +PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK = 0x00800000 # macro +PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT = 0x0 # macro +PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT = 0x1 # macro +PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT = 0x2 # macro +PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT = 0x3 # macro +PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT = 0x4 # macro +PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT = 0x5 # macro +PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT = 0x8 # macro +PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT = 0x9 # macro +PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT = 0xa # macro +PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT = 0xb # macro +PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK = 0x00000001 # macro +PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK = 0x00000002 # macro +PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK = 0x00000004 # macro +PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK = 0x00000008 # macro +PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK = 0x00000010 # macro +PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK = 0x00000020 # macro +PA_CL_VTE_CNTL__VTX_XY_FMT_MASK = 0x00000100 # macro +PA_CL_VTE_CNTL__VTX_Z_FMT_MASK = 0x00000200 # macro +PA_CL_VTE_CNTL__VTX_W0_FMT_MASK = 0x00000400 # macro +PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK = 0x00000800 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT = 0x0 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT = 0x1 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT = 0x2 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT = 0x3 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT = 0x4 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT = 0x5 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT = 0x6 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT = 0x7 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT = 0x8 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT = 0x9 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT = 0xa # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT = 0xb # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT = 0xc # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT = 0xd # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT = 0xe # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT = 0xf # macro +PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT = 0x10 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT = 0x11 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT = 0x12 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT = 0x13 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT = 0x14 # macro +PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT = 0x15 # macro +PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT = 0x16 # macro +PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT = 0x17 # macro +PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT = 0x18 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT = 0x19 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT = 0x1a # macro +PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT = 0x1b # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK = 0x00000001 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK = 0x00000002 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK = 0x00000004 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK = 0x00000008 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK = 0x00000010 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK = 0x00000020 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK = 0x00000040 # macro +PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK = 0x00000080 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK = 0x00000100 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK = 0x00000200 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK = 0x00000400 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK = 0x00000800 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK = 0x00001000 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK = 0x00002000 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK = 0x00004000 # macro +PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK = 0x00008000 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK = 0x00010000 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK = 0x00020000 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK = 0x00040000 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK = 0x00080000 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK = 0x00100000 # macro +PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK = 0x00200000 # macro +PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK = 0x00400000 # macro +PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK = 0x00800000 # macro +PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK = 0x01000000 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK = 0x02000000 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK = 0x04000000 # macro +PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK = 0x08000000 # macro +PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT = 0x0 # macro +PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT = 0x1 # macro +PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT = 0x2 # macro +PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT = 0x3 # macro +PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT = 0x4 # macro +PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT = 0x5 # macro +PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT = 0x6 # macro +PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT = 0x7 # macro +PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT = 0x8 # macro +PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT = 0x9 # macro +PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT = 0xa # macro +PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT = 0xb # macro +PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT = 0xc # macro +PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT = 0xd # macro +PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT = 0xe # macro +PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT = 0x14 # macro +PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK = 0x00000001 # macro +PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK = 0x00000002 # macro +PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK = 0x00000004 # macro +PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK = 0x00000008 # macro +PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK = 0x00000010 # macro +PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK = 0x00000020 # macro +PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK = 0x00000040 # macro +PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK = 0x00000080 # macro +PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK = 0x00000100 # macro +PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK = 0x00000200 # macro +PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK = 0x00000400 # macro +PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK = 0x00000800 # macro +PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK = 0x00001000 # macro +PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK = 0x00002000 # macro +PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK = 0x00004000 # macro +PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK = 0x00100000 # macro +PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT = 0x0 # macro +PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT = 0x2 # macro +PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT = 0x3 # macro +PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT = 0x4 # macro +PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK = 0x00000003 # macro +PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK = 0x00000004 # macro +PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK = 0x00000008 # macro +PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK = 0x00000010 # macro +PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT = 0x0 # macro +PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK = 0xFFFFFFFF # macro +PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT = 0x0 # macro +PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT = 0x1 # macro +PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT = 0x2 # macro +PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT = 0x3 # macro +PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT = 0x4 # macro +PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT = 0x5 # macro +PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT = 0x6 # macro +PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT = 0x7 # macro +PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT = 0x8 # macro +PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT = 0x1e # macro +PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT = 0x1f # macro +PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK = 0x00000001 # macro +PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK = 0x00000002 # macro +PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK = 0x00000004 # macro +PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK = 0x00000008 # macro +PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK = 0x00000010 # macro +PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK = 0x00000020 # macro +PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK = 0x00000040 # macro +PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK = 0x00000080 # macro +PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK = 0x0000FF00 # macro +PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK = 0x40000000 # macro +PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK = 0x80000000 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT = 0x0 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT = 0x1 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT = 0x2 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT = 0x3 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT = 0x4 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE__SHIFT = 0x5 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE__SHIFT = 0x6 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK = 0x00000001 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK = 0x00000002 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK = 0x00000004 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK = 0x00000008 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK = 0x00000010 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE_MASK = 0x00000020 # macro +PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE_MASK = 0x00000040 # macro +PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT = 0x0 # macro +PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT = 0x1 # macro +PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID__SHIFT = 0x2 # macro +PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK = 0x00000001 # macro +PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK = 0x00000002 # macro +PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID_MASK = 0x00000004 # macro +PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT = 0x0 # macro +PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT = 0x1 # macro +PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK = 0x00000001 # macro +PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK = 0x00000002 # macro +PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT = 0x0 # macro +PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT = 0x1 # macro +PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT = 0x2 # macro +PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT = 0x3 # macro +PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT = 0x4 # macro +PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK = 0x00000001 # macro +PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK = 0x00000002 # macro +PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK = 0x00000004 # macro +PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK = 0x00000008 # macro +PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK = 0x00000010 # macro +PA_STEREO_CNTL__EN_STEREO__SHIFT = 0x0 # macro +PA_STEREO_CNTL__STEREO_MODE__SHIFT = 0x1 # macro +PA_STEREO_CNTL__RT_SLICE_MODE__SHIFT = 0x5 # macro +PA_STEREO_CNTL__RT_SLICE_OFFSET__SHIFT = 0x8 # macro +PA_STEREO_CNTL__VP_ID_MODE__SHIFT = 0xa # macro +PA_STEREO_CNTL__VP_ID_OFFSET__SHIFT = 0xd # macro +PA_STEREO_CNTL__EN_STEREO_MASK = 0x00000001 # macro +PA_STEREO_CNTL__STEREO_MODE_MASK = 0x0000001E # macro +PA_STEREO_CNTL__RT_SLICE_MODE_MASK = 0x000000E0 # macro +PA_STEREO_CNTL__RT_SLICE_OFFSET_MASK = 0x00000300 # macro +PA_STEREO_CNTL__VP_ID_MODE_MASK = 0x00001C00 # macro +PA_STEREO_CNTL__VP_ID_OFFSET_MASK = 0x0001E000 # macro +PA_SU_POINT_SIZE__HEIGHT__SHIFT = 0x0 # macro +PA_SU_POINT_SIZE__WIDTH__SHIFT = 0x10 # macro +PA_SU_POINT_SIZE__HEIGHT_MASK = 0x0000FFFF # macro +PA_SU_POINT_SIZE__WIDTH_MASK = 0xFFFF0000 # macro +PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT = 0x0 # macro +PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT = 0x10 # macro +PA_SU_POINT_MINMAX__MIN_SIZE_MASK = 0x0000FFFF # macro +PA_SU_POINT_MINMAX__MAX_SIZE_MASK = 0xFFFF0000 # macro +PA_SU_LINE_CNTL__WIDTH__SHIFT = 0x0 # macro +PA_SU_LINE_CNTL__WIDTH_MASK = 0x0000FFFF # macro +PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT = 0x0 # macro +PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT = 0x10 # macro +PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT = 0x1c # macro +PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT = 0x1d # macro +PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK = 0x0000FFFF # macro +PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK = 0x00FF0000 # macro +PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK = 0x10000000 # macro +PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK = 0x60000000 # macro +VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT = 0x0 # macro +VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK = 0x00000007 # macro +VGT_HOS_CNTL__TESS_MODE__SHIFT = 0x0 # macro +VGT_HOS_CNTL__TESS_MODE_MASK = 0x00000003 # macro +VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT = 0x0 # macro +VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK = 0xFFFFFFFF # macro +VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT = 0x0 # macro +VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK = 0xFFFFFFFF # macro +VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT = 0x0 # macro +VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK = 0x000000FF # macro +VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT = 0x0 # macro +VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT = 0xe # macro +VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT = 0xf # macro +VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT = 0x10 # macro +VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK = 0x0000001F # macro +VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK = 0x00004000 # macro +VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK = 0x00008000 # macro +VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK = 0x00070000 # macro +VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT = 0x0 # macro +VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK = 0x0000000F # macro +VGT_GROUP_DECR__DECR__SHIFT = 0x0 # macro +VGT_GROUP_DECR__DECR_MASK = 0x0000000F # macro +VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT = 0x0 # macro +VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT = 0x1 # macro +VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT = 0x2 # macro +VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT = 0x3 # macro +VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT = 0x8 # macro +VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT = 0x10 # macro +VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK = 0x00000001 # macro +VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK = 0x00000002 # macro +VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK = 0x00000004 # macro +VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK = 0x00000008 # macro +VGT_GROUP_VECT_0_CNTL__STRIDE_MASK = 0x0000FF00 # macro +VGT_GROUP_VECT_0_CNTL__SHIFT_MASK = 0x00FF0000 # macro +VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT = 0x0 # macro +VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT = 0x1 # macro +VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT = 0x2 # macro +VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT = 0x3 # macro +VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT = 0x8 # macro +VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT = 0x10 # macro +VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK = 0x00000001 # macro +VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK = 0x00000002 # macro +VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK = 0x00000004 # macro +VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK = 0x00000008 # macro +VGT_GROUP_VECT_1_CNTL__STRIDE_MASK = 0x0000FF00 # macro +VGT_GROUP_VECT_1_CNTL__SHIFT_MASK = 0x00FF0000 # macro +VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT = 0x0 # macro +VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT = 0x4 # macro +VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT = 0x8 # macro +VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT = 0xc # macro +VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT = 0x10 # macro +VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT = 0x14 # macro +VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT = 0x18 # macro +VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT = 0x1c # macro +VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK = 0x0000000F # macro +VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK = 0x000000F0 # macro +VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK = 0x00000F00 # macro +VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK = 0x0000F000 # macro +VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK = 0x000F0000 # macro +VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK = 0x00F00000 # macro +VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK = 0x0F000000 # macro +VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK = 0xF0000000 # macro +VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT = 0x0 # macro +VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT = 0x4 # macro +VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT = 0x8 # macro +VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT = 0xc # macro +VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT = 0x10 # macro +VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT = 0x14 # macro +VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT = 0x18 # macro +VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT = 0x1c # macro +VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK = 0x0000000F # macro +VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK = 0x000000F0 # macro +VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK = 0x00000F00 # macro +VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK = 0x0000F000 # macro +VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK = 0x000F0000 # macro +VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK = 0x00F00000 # macro +VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK = 0x0F000000 # macro +VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK = 0xF0000000 # macro +VGT_GS_MODE__MODE__SHIFT = 0x0 # macro +VGT_GS_MODE__RESERVED_0__SHIFT = 0x3 # macro +VGT_GS_MODE__CUT_MODE__SHIFT = 0x4 # macro +VGT_GS_MODE__RESERVED_1__SHIFT = 0x6 # macro +VGT_GS_MODE__GS_C_PACK_EN__SHIFT = 0xb # macro +VGT_GS_MODE__RESERVED_2__SHIFT = 0xc # macro +VGT_GS_MODE__ES_PASSTHRU__SHIFT = 0xd # macro +VGT_GS_MODE__RESERVED_3__SHIFT = 0xe # macro +VGT_GS_MODE__RESERVED_4__SHIFT = 0xf # macro +VGT_GS_MODE__RESERVED_5__SHIFT = 0x10 # macro +VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT = 0x11 # macro +VGT_GS_MODE__SUPPRESS_CUTS__SHIFT = 0x12 # macro +VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT = 0x13 # macro +VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT = 0x14 # macro +VGT_GS_MODE__ONCHIP__SHIFT = 0x15 # macro +VGT_GS_MODE__MODE_MASK = 0x00000007 # macro +VGT_GS_MODE__RESERVED_0_MASK = 0x00000008 # macro +VGT_GS_MODE__CUT_MODE_MASK = 0x00000030 # macro +VGT_GS_MODE__RESERVED_1_MASK = 0x000007C0 # macro +VGT_GS_MODE__GS_C_PACK_EN_MASK = 0x00000800 # macro +VGT_GS_MODE__RESERVED_2_MASK = 0x00001000 # macro +VGT_GS_MODE__ES_PASSTHRU_MASK = 0x00002000 # macro +VGT_GS_MODE__RESERVED_3_MASK = 0x00004000 # macro +VGT_GS_MODE__RESERVED_4_MASK = 0x00008000 # macro +VGT_GS_MODE__RESERVED_5_MASK = 0x00010000 # macro +VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK = 0x00020000 # macro +VGT_GS_MODE__SUPPRESS_CUTS_MASK = 0x00040000 # macro +VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK = 0x00080000 # macro +VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK = 0x00100000 # macro +VGT_GS_MODE__ONCHIP_MASK = 0x00600000 # macro +VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT = 0x0 # macro +VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT = 0xb # macro +VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT = 0x16 # macro +VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK = 0x000007FF # macro +VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK = 0x003FF800 # macro +VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK = 0xFFC00000 # macro +PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT = 0x0 # macro +PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT = 0x1 # macro +PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT = 0x2 # macro +PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT = 0x3 # macro +PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT = 0x4 # macro +PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT = 0x5 # macro +PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT = 0x6 # macro +PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK = 0x00000001 # macro +PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK = 0x00000002 # macro +PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK = 0x00000004 # macro +PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK = 0x00000008 # macro +PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK = 0x00000010 # macro +PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK = 0x00000020 # macro +PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK = 0x00000040 # macro +PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT = 0x0 # macro +PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT = 0x1 # macro +PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT = 0x2 # macro +PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT = 0x3 # macro +PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT = 0x4 # macro +PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT = 0x7 # macro +PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT = 0x8 # macro +PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT = 0x9 # macro +PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT = 0xa # macro +PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT = 0xb # macro +PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT = 0xc # macro +PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT = 0xd # macro +PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT = 0xe # macro +PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT = 0xf # macro +PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT = 0x10 # macro +PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT = 0x11 # macro +PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT = 0x12 # macro +PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT = 0x13 # macro +PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT = 0x14 # macro +PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT = 0x18 # macro +PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT = 0x19 # macro +PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT = 0x1a # macro +PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT = 0x1b # macro +PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT = 0x1c # macro +PA_SC_MODE_CNTL_1__WALK_SIZE_MASK = 0x00000001 # macro +PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK = 0x00000002 # macro +PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK = 0x00000004 # macro +PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK = 0x00000008 # macro +PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK = 0x00000070 # macro +PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK = 0x00000080 # macro +PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK = 0x00000100 # macro +PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK = 0x00000200 # macro +PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK = 0x00000400 # macro +PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK = 0x00000800 # macro +PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK = 0x00001000 # macro +PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK = 0x00002000 # macro +PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK = 0x00004000 # macro +PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK = 0x00008000 # macro +PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK = 0x00010000 # macro +PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK = 0x00020000 # macro +PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK = 0x00040000 # macro +PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK = 0x00080000 # macro +PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK = 0x00F00000 # macro +PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK = 0x01000000 # macro +PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK = 0x02000000 # macro +PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK = 0x04000000 # macro +PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK = 0x08000000 # macro +PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK = 0x70000000 # macro +VGT_ENHANCE__MISC__SHIFT = 0x0 # macro +VGT_ENHANCE__MISC_MASK = 0xFFFFFFFF # macro +VGT_GS_PER_ES__GS_PER_ES__SHIFT = 0x0 # macro +VGT_GS_PER_ES__GS_PER_ES_MASK = 0x000007FF # macro +VGT_ES_PER_GS__ES_PER_GS__SHIFT = 0x0 # macro +VGT_ES_PER_GS__ES_PER_GS_MASK = 0x000007FF # macro +VGT_GS_PER_VS__GS_PER_VS__SHIFT = 0x0 # macro +VGT_GS_PER_VS__GS_PER_VS_MASK = 0x0000000F # macro +VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT = 0x0 # macro +VGT_GSVS_RING_OFFSET_1__OFFSET_MASK = 0x00007FFF # macro +VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT = 0x0 # macro +VGT_GSVS_RING_OFFSET_2__OFFSET_MASK = 0x00007FFF # macro +VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT = 0x0 # macro +VGT_GSVS_RING_OFFSET_3__OFFSET_MASK = 0x00007FFF # macro +VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT = 0x0 # macro +VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT = 0x8 # macro +VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT = 0x10 # macro +VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT = 0x16 # macro +VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT = 0x1f # macro +VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK = 0x0000003F # macro +VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK = 0x00003F00 # macro +VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK = 0x003F0000 # macro +VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK = 0x0FC00000 # macro +VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK = 0x80000000 # macro +IA_ENHANCE__MISC__SHIFT = 0x0 # macro +IA_ENHANCE__MISC_MASK = 0xFFFFFFFF # macro +VGT_DMA_SIZE__NUM_INDICES__SHIFT = 0x0 # macro +VGT_DMA_SIZE__NUM_INDICES_MASK = 0xFFFFFFFF # macro +VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT = 0x0 # macro +VGT_DMA_MAX_SIZE__MAX_SIZE_MASK = 0xFFFFFFFF # macro +VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT = 0x0 # macro +VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT = 0x2 # macro +VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT = 0x4 # macro +VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT = 0x6 # macro +VGT_DMA_INDEX_TYPE__PRIMGEN_EN__SHIFT = 0x8 # macro +VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT = 0x9 # macro +VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT = 0xa # macro +VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK = 0x00000003 # macro +VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK = 0x0000000C # macro +VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK = 0x00000030 # macro +VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK = 0x00000040 # macro +VGT_DMA_INDEX_TYPE__PRIMGEN_EN_MASK = 0x00000100 # macro +VGT_DMA_INDEX_TYPE__NOT_EOP_MASK = 0x00000200 # macro +VGT_DMA_INDEX_TYPE__REQ_PATH_MASK = 0x00000400 # macro +WD_ENHANCE__MISC__SHIFT = 0x0 # macro +WD_ENHANCE__MISC_MASK = 0xFFFFFFFF # macro +VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT = 0x0 # macro +VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT = 0x1 # macro +VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT = 0x2 # macro +VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK = 0x00000001 # macro +VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK = 0x00000002 # macro +VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK = 0x00000004 # macro +VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT = 0x0 # macro +VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK = 0xFFFFFFFF # macro +VGT_PRIMITIVEID_RESET__VALUE__SHIFT = 0x0 # macro +VGT_PRIMITIVEID_RESET__VALUE_MASK = 0xFFFFFFFF # macro +VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT = 0x0 # macro +VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT = 0xa # macro +VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT = 0x1b # macro +VGT_EVENT_INITIATOR__EVENT_TYPE_MASK = 0x0000003F # macro +VGT_EVENT_INITIATOR__ADDRESS_HI_MASK = 0x07FFFC00 # macro +VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK = 0x08000000 # macro +VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP__SHIFT = 0x0 # macro +VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP_MASK = 0x0000FFFF # macro +VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT = 0x0 # macro +VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT = 0x1 # macro +VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID__SHIFT = 0x2 # macro +VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT = 0x3 # macro +VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK = 0x00000001 # macro +VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK = 0x00000002 # macro +VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK = 0x00000004 # macro +VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK = 0x00000008 # macro +VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT = 0x0 # macro +VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK = 0xFFFFFFFF # macro +VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT = 0x0 # macro +VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK = 0xFFFFFFFF # macro +VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT = 0x0 # macro +VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK = 0x00007FFF # macro +VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT = 0x0 # macro +VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK = 0x00007FFF # macro +VGT_REUSE_OFF__REUSE_OFF__SHIFT = 0x0 # macro +VGT_REUSE_OFF__REUSE_OFF_MASK = 0x00000001 # macro +VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT = 0x0 # macro +VGT_VTX_CNT_EN__VTX_CNT_EN_MASK = 0x00000001 # macro +DB_HTILE_SURFACE__FULL_CACHE__SHIFT = 0x1 # macro +DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT = 0x2 # macro +DB_HTILE_SURFACE__PRELOAD__SHIFT = 0x3 # macro +DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT = 0x4 # macro +DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT = 0xa # macro +DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT = 0x10 # macro +DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT = 0x12 # macro +DB_HTILE_SURFACE__RB_ALIGNED__SHIFT = 0x13 # macro +DB_HTILE_SURFACE__FULL_CACHE_MASK = 0x00000002 # macro +DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK = 0x00000004 # macro +DB_HTILE_SURFACE__PRELOAD_MASK = 0x00000008 # macro +DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK = 0x000003F0 # macro +DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK = 0x0000FC00 # macro +DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK = 0x00010000 # macro +DB_HTILE_SURFACE__PIPE_ALIGNED_MASK = 0x00040000 # macro +DB_HTILE_SURFACE__RB_ALIGNED_MASK = 0x00080000 # macro +DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT = 0x0 # macro +DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT = 0x4 # macro +DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT = 0xc # macro +DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT = 0x18 # macro +DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK = 0x00000007 # macro +DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK = 0x00000FF0 # macro +DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK = 0x000FF000 # macro +DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK = 0x01000000 # macro +DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT = 0x0 # macro +DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT = 0x4 # macro +DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT = 0xc # macro +DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT = 0x18 # macro +DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK = 0x00000007 # macro +DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK = 0x00000FF0 # macro +DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK = 0x000FF000 # macro +DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK = 0x01000000 # macro +DB_PRELOAD_CONTROL__START_X__SHIFT = 0x0 # macro +DB_PRELOAD_CONTROL__START_Y__SHIFT = 0x8 # macro +DB_PRELOAD_CONTROL__MAX_X__SHIFT = 0x10 # macro +DB_PRELOAD_CONTROL__MAX_Y__SHIFT = 0x18 # macro +DB_PRELOAD_CONTROL__START_X_MASK = 0x000000FF # macro +DB_PRELOAD_CONTROL__START_Y_MASK = 0x0000FF00 # macro +DB_PRELOAD_CONTROL__MAX_X_MASK = 0x00FF0000 # macro +DB_PRELOAD_CONTROL__MAX_Y_MASK = 0xFF000000 # macro +VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT = 0x0 # macro +VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK = 0xFFFFFFFF # macro +VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT = 0x0 # macro +VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK = 0x000003FF # macro +VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT = 0x0 # macro +VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK = 0xFFFFFFFF # macro +VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT = 0x0 # macro +VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK = 0xFFFFFFFF # macro +VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT = 0x0 # macro +VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK = 0x000003FF # macro +VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT = 0x0 # macro +VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK = 0xFFFFFFFF # macro +VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT = 0x0 # macro +VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK = 0xFFFFFFFF # macro +VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT = 0x0 # macro +VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK = 0x000003FF # macro +VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT = 0x0 # macro +VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK = 0xFFFFFFFF # macro +VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT = 0x0 # macro +VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK = 0xFFFFFFFF # macro +VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT = 0x0 # macro +VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK = 0x000003FF # macro +VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT = 0x0 # macro +VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK = 0xFFFFFFFF # macro +VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT = 0x0 # macro +VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK = 0xFFFFFFFF # macro +VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT = 0x0 # macro +VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK = 0xFFFFFFFF # macro +VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT = 0x0 # macro +VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK = 0x000001FF # macro +VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT = 0x0 # macro +VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK = 0x000007FF # macro +VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT = 0x0 # macro +VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT = 0x8 # macro +VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT = 0x10 # macro +VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT = 0x18 # macro +VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT = 0x1d # macro +VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK = 0x000000FF # macro +VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK = 0x0000FF00 # macro +VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK = 0x00FF0000 # macro +VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK = 0x1F000000 # macro +VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK = 0xE0000000 # macro +VGT_SHADER_STAGES_EN__LS_EN__SHIFT = 0x0 # macro +VGT_SHADER_STAGES_EN__HS_EN__SHIFT = 0x2 # macro +VGT_SHADER_STAGES_EN__ES_EN__SHIFT = 0x3 # macro +VGT_SHADER_STAGES_EN__GS_EN__SHIFT = 0x5 # macro +VGT_SHADER_STAGES_EN__VS_EN__SHIFT = 0x6 # macro +VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT = 0x9 # macro +VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT = 0xa # macro +VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT = 0xb # macro +VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT = 0xc # macro +VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT = 0xd # macro +VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT = 0xe # macro +VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT = 0xf # macro +VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT = 0x13 # macro +VGT_SHADER_STAGES_EN__LS_EN_MASK = 0x00000003 # macro +VGT_SHADER_STAGES_EN__HS_EN_MASK = 0x00000004 # macro +VGT_SHADER_STAGES_EN__ES_EN_MASK = 0x00000018 # macro +VGT_SHADER_STAGES_EN__GS_EN_MASK = 0x00000020 # macro +VGT_SHADER_STAGES_EN__VS_EN_MASK = 0x000000C0 # macro +VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK = 0x00000200 # macro +VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK = 0x00000400 # macro +VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK = 0x00000800 # macro +VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK = 0x00001000 # macro +VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK = 0x00002000 # macro +VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK = 0x00004000 # macro +VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK = 0x00078000 # macro +VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK = 0x00180000 # macro +VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT = 0x0 # macro +VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT = 0x8 # macro +VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT = 0xe # macro +VGT_LS_HS_CONFIG__NUM_PATCHES_MASK = 0x000000FF # macro +VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK = 0x00003F00 # macro +VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK = 0x000FC000 # macro +VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT = 0x0 # macro +VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK = 0x00007FFF # macro +VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT = 0x0 # macro +VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK = 0x00007FFF # macro +VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT = 0x0 # macro +VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK = 0x00007FFF # macro +VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT = 0x0 # macro +VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK = 0x00007FFF # macro +VGT_TF_PARAM__TYPE__SHIFT = 0x0 # macro +VGT_TF_PARAM__PARTITIONING__SHIFT = 0x2 # macro +VGT_TF_PARAM__TOPOLOGY__SHIFT = 0x5 # macro +VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT = 0x8 # macro +VGT_TF_PARAM__DEPRECATED__SHIFT = 0x9 # macro +VGT_TF_PARAM__DISABLE_DONUTS__SHIFT = 0xe # macro +VGT_TF_PARAM__RDREQ_POLICY__SHIFT = 0xf # macro +VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT = 0x11 # macro +VGT_TF_PARAM__TYPE_MASK = 0x00000003 # macro +VGT_TF_PARAM__PARTITIONING_MASK = 0x0000001C # macro +VGT_TF_PARAM__TOPOLOGY_MASK = 0x000000E0 # macro +VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK = 0x00000100 # macro +VGT_TF_PARAM__DEPRECATED_MASK = 0x00000200 # macro +VGT_TF_PARAM__DISABLE_DONUTS_MASK = 0x00004000 # macro +VGT_TF_PARAM__RDREQ_POLICY_MASK = 0x00008000 # macro +VGT_TF_PARAM__DISTRIBUTION_MODE_MASK = 0x00060000 # macro +DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT = 0x0 # macro +DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT = 0x8 # macro +DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT = 0xa # macro +DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT = 0xc # macro +DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT = 0xe # macro +DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT = 0x10 # macro +DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK = 0x00000001 # macro +DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK = 0x00000300 # macro +DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK = 0x00000C00 # macro +DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK = 0x00003000 # macro +DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK = 0x0000C000 # macro +DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK = 0x00010000 # macro +VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT = 0x0 # macro +VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK = 0xFFFFFFFF # macro +PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT = 0x0 # macro +PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT = 0x8 # macro +PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK = 0x000000FF # macro +PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK = 0x00000100 # macro +PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT = 0x0 # macro +PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK = 0xFFFFFFFF # macro +PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT = 0x0 # macro +PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK = 0xFFFFFFFF # macro +PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT = 0x0 # macro +PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK = 0xFFFFFFFF # macro +PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT = 0x0 # macro +PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK = 0xFFFFFFFF # macro +PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT = 0x0 # macro +PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK = 0xFFFFFFFF # macro +VGT_GS_INSTANCE_CNT__ENABLE__SHIFT = 0x0 # macro +VGT_GS_INSTANCE_CNT__CNT__SHIFT = 0x2 # macro +VGT_GS_INSTANCE_CNT__ENABLE_MASK = 0x00000001 # macro +VGT_GS_INSTANCE_CNT__CNT_MASK = 0x000001FC # macro +VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT = 0x0 # macro +VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT = 0x1 # macro +VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT = 0x2 # macro +VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT = 0x3 # macro +VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT = 0x4 # macro +VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT = 0x7 # macro +VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT = 0x8 # macro +VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT = 0x1f # macro +VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK = 0x00000001 # macro +VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK = 0x00000002 # macro +VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK = 0x00000004 # macro +VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK = 0x00000008 # macro +VGT_STRMOUT_CONFIG__RAST_STREAM_MASK = 0x00000070 # macro +VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK = 0x00000080 # macro +VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK = 0x00000F00 # macro +VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK = 0x80000000 # macro +VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT = 0x0 # macro +VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT = 0x4 # macro +VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT = 0x8 # macro +VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT = 0xc # macro +VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK = 0x0000000F # macro +VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK = 0x000000F0 # macro +VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK = 0x00000F00 # macro +VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK = 0x0000F000 # macro +VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT = 0x0 # macro +VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT = 0xa # macro +VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT = 0x1b # macro +VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK = 0x0000003F # macro +VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK = 0x07FFFC00 # macro +VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK = 0x08000000 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT = 0x0 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT = 0x4 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT = 0x8 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT = 0xc # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT = 0x10 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT = 0x14 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT = 0x18 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT = 0x1c # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK = 0x0000000F # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK = 0x000000F0 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK = 0x00000F00 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK = 0x0000F000 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK = 0x000F0000 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK = 0x00F00000 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK = 0x0F000000 # macro +PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK = 0xF0000000 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT = 0x0 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT = 0x4 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT = 0x8 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT = 0xc # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT = 0x10 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT = 0x14 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT = 0x18 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT = 0x1c # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK = 0x0000000F # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK = 0x000000F0 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK = 0x00000F00 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK = 0x0000F000 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK = 0x000F0000 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK = 0x00F00000 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK = 0x0F000000 # macro +PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK = 0xF0000000 # macro +PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT = 0x9 # macro +PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT = 0xa # macro +PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT = 0xb # macro +PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT = 0xc # macro +PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION__SHIFT = 0xd # macro +PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK = 0x00000200 # macro +PA_SC_LINE_CNTL__LAST_PIXEL_MASK = 0x00000400 # macro +PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK = 0x00000800 # macro +PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK = 0x00001000 # macro +PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION_MASK = 0x00002000 # macro +PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT = 0x0 # macro +PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT = 0x4 # macro +PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT = 0xd # macro +PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT = 0x14 # macro +PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT = 0x18 # macro +PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT = 0x1a # macro +PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK = 0x00000007 # macro +PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK = 0x00000010 # macro +PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK = 0x0001E000 # macro +PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK = 0x00700000 # macro +PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK = 0x03000000 # macro +PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK = 0x0C000000 # macro +PA_SU_VTX_CNTL__PIX_CENTER__SHIFT = 0x0 # macro +PA_SU_VTX_CNTL__ROUND_MODE__SHIFT = 0x1 # macro +PA_SU_VTX_CNTL__QUANT_MODE__SHIFT = 0x3 # macro +PA_SU_VTX_CNTL__PIX_CENTER_MASK = 0x00000001 # macro +PA_SU_VTX_CNTL__ROUND_MODE_MASK = 0x00000006 # macro +PA_SU_VTX_CNTL__QUANT_MODE_MASK = 0x00000038 # macro +PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT = 0x0 # macro +PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK = 0xFFFFFFFF # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK = 0xF0000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT = 0x0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT = 0x4 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT = 0x8 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT = 0xc # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT = 0x10 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT = 0x14 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT = 0x18 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT = 0x1c # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK = 0x0000000F # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK = 0x000000F0 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK = 0x00000F00 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK = 0x0000F000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK = 0x000F0000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK = 0x00F00000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK = 0x0F000000 # macro +PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK = 0xF0000000 # macro +PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT = 0x0 # macro +PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT = 0x10 # macro +PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK = 0x0000FFFF # macro +PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK = 0xFFFF0000 # macro +PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT = 0x0 # macro +PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT = 0x10 # macro +PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK = 0x0000FFFF # macro +PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK = 0xFFFF0000 # macro +PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT = 0x0 # macro +PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT = 0x2 # macro +PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT = 0x3 # macro +PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK = 0x00000003 # macro +PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK = 0x00000004 # macro +PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK = 0x00000008 # macro +PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT = 0x0 # macro +PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT = 0x2 # macro +PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT = 0x3 # macro +PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT = 0x4 # macro +PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT = 0x7 # macro +PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT = 0xa # macro +PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT = 0xd # macro +PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT = 0x12 # macro +PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT = 0x13 # macro +PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT = 0x1b # macro +PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION__SHIFT = 0x1c # macro +PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK = 0x00000003 # macro +PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK = 0x00000004 # macro +PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK = 0x00000008 # macro +PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK = 0x00000070 # macro +PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK = 0x00000380 # macro +PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK = 0x00001C00 # macro +PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK = 0x0003E000 # macro +PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK = 0x00040000 # macro +PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK = 0x07F80000 # macro +PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK = 0x08000000 # macro +PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION_MASK = 0x10000000 # macro +PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT = 0x0 # macro +PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT = 0x10 # macro +PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK = 0x0000FFFF # macro +PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK = 0xFFFF0000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT = 0x0 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT = 0x1 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT = 0x5 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT = 0x6 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT = 0xa # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT = 0xb # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT = 0xc # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT = 0xd # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT = 0xe # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT = 0xf # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT = 0x10 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT = 0x12 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT = 0x13 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT = 0x14 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT = 0x15 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT = 0x16 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT = 0x17 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT = 0x18 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK = 0x00000001 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK = 0x0000001E # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK = 0x00000020 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK = 0x000003C0 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK = 0x00000400 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK = 0x00000800 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK = 0x00001000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK = 0x00002000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK = 0x00004000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK = 0x00008000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK = 0x00030000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK = 0x00040000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK = 0x00080000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK = 0x00100000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK = 0x00200000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK = 0x00400000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK = 0x00800000 # macro +PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK = 0x01000000 # macro +PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT = 0x0 # macro +PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK = 0x000007FF # macro +VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT = 0x0 # macro +VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK = 0x000000FF # macro +VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT = 0x0 # macro +VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK = 0x0000007F # macro +CB_COLOR0_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR0_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR0_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR0_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT = 0x0 # macro +CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT = 0xe # macro +CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT = 0x1c # macro +CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK = 0x00003FFF # macro +CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK = 0x0FFFC000 # macro +CB_COLOR0_ATTRIB2__MAX_MIP_MASK = 0xF0000000 # macro +CB_COLOR0_VIEW__SLICE_START__SHIFT = 0x0 # macro +CB_COLOR0_VIEW__SLICE_MAX__SHIFT = 0xd # macro +CB_COLOR0_VIEW__MIP_LEVEL__SHIFT = 0x18 # macro +CB_COLOR0_VIEW__SLICE_START_MASK = 0x000007FF # macro +CB_COLOR0_VIEW__SLICE_MAX_MASK = 0x00FFE000 # macro +CB_COLOR0_VIEW__MIP_LEVEL_MASK = 0x0F000000 # macro +CB_COLOR0_INFO__ENDIAN__SHIFT = 0x0 # macro +CB_COLOR0_INFO__FORMAT__SHIFT = 0x2 # macro +CB_COLOR0_INFO__NUMBER_TYPE__SHIFT = 0x8 # macro +CB_COLOR0_INFO__COMP_SWAP__SHIFT = 0xb # macro +CB_COLOR0_INFO__FAST_CLEAR__SHIFT = 0xd # macro +CB_COLOR0_INFO__COMPRESSION__SHIFT = 0xe # macro +CB_COLOR0_INFO__BLEND_CLAMP__SHIFT = 0xf # macro +CB_COLOR0_INFO__BLEND_BYPASS__SHIFT = 0x10 # macro +CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT = 0x11 # macro +CB_COLOR0_INFO__ROUND_MODE__SHIFT = 0x12 # macro +CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT = 0x14 # macro +CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT = 0x17 # macro +CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT = 0x1a # macro +CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT = 0x1b # macro +CB_COLOR0_INFO__DCC_ENABLE__SHIFT = 0x1c # macro +CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT = 0x1d # macro +CB_COLOR0_INFO__ENDIAN_MASK = 0x00000003 # macro +CB_COLOR0_INFO__FORMAT_MASK = 0x0000007C # macro +CB_COLOR0_INFO__NUMBER_TYPE_MASK = 0x00000700 # macro +CB_COLOR0_INFO__COMP_SWAP_MASK = 0x00001800 # macro +CB_COLOR0_INFO__FAST_CLEAR_MASK = 0x00002000 # macro +CB_COLOR0_INFO__COMPRESSION_MASK = 0x00004000 # macro +CB_COLOR0_INFO__BLEND_CLAMP_MASK = 0x00008000 # macro +CB_COLOR0_INFO__BLEND_BYPASS_MASK = 0x00010000 # macro +CB_COLOR0_INFO__SIMPLE_FLOAT_MASK = 0x00020000 # macro +CB_COLOR0_INFO__ROUND_MODE_MASK = 0x00040000 # macro +CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK = 0x00700000 # macro +CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK = 0x03800000 # macro +CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK = 0x04000000 # macro +CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK = 0x08000000 # macro +CB_COLOR0_INFO__DCC_ENABLE_MASK = 0x10000000 # macro +CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK = 0x60000000 # macro +CB_COLOR0_ATTRIB__MIP0_DEPTH__SHIFT = 0x0 # macro +CB_COLOR0_ATTRIB__META_LINEAR__SHIFT = 0xb # macro +CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT = 0xc # macro +CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT = 0xf # macro +CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT = 0x11 # macro +CB_COLOR0_ATTRIB__COLOR_SW_MODE__SHIFT = 0x12 # macro +CB_COLOR0_ATTRIB__FMASK_SW_MODE__SHIFT = 0x17 # macro +CB_COLOR0_ATTRIB__RESOURCE_TYPE__SHIFT = 0x1c # macro +CB_COLOR0_ATTRIB__RB_ALIGNED__SHIFT = 0x1e # macro +CB_COLOR0_ATTRIB__PIPE_ALIGNED__SHIFT = 0x1f # macro +CB_COLOR0_ATTRIB__MIP0_DEPTH_MASK = 0x000007FF # macro +CB_COLOR0_ATTRIB__META_LINEAR_MASK = 0x00000800 # macro +CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK = 0x00007000 # macro +CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK = 0x00018000 # macro +CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK = 0x00020000 # macro +CB_COLOR0_ATTRIB__COLOR_SW_MODE_MASK = 0x007C0000 # macro +CB_COLOR0_ATTRIB__FMASK_SW_MODE_MASK = 0x0F800000 # macro +CB_COLOR0_ATTRIB__RESOURCE_TYPE_MASK = 0x30000000 # macro +CB_COLOR0_ATTRIB__RB_ALIGNED_MASK = 0x40000000 # macro +CB_COLOR0_ATTRIB__PIPE_ALIGNED_MASK = 0x80000000 # macro +CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT = 0x0 # macro +CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT = 0x1 # macro +CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT = 0x2 # macro +CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT = 0x4 # macro +CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT = 0x5 # macro +CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT = 0x7 # macro +CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT = 0x9 # macro +CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT = 0xa # macro +CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT = 0xe # macro +CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT = 0x12 # macro +CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT = 0x13 # macro +CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK = 0x00000001 # macro +CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK = 0x00000002 # macro +CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK = 0x0000000C # macro +CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK = 0x00000010 # macro +CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK = 0x00000060 # macro +CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK = 0x00000180 # macro +CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK = 0x00000200 # macro +CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK = 0x00003C00 # macro +CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK = 0x0003C000 # macro +CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK = 0x00040000 # macro +CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK = 0x00080000 # macro +CB_COLOR0_CMASK__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR0_CMASK__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR0_FMASK__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR0_FMASK__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT = 0x0 # macro +CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK = 0xFFFFFFFF # macro +CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT = 0x0 # macro +CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK = 0xFFFFFFFF # macro +CB_COLOR0_DCC_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR0_DCC_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR1_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR1_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR1_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR1_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT = 0x0 # macro +CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT = 0xe # macro +CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT = 0x1c # macro +CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK = 0x00003FFF # macro +CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK = 0x0FFFC000 # macro +CB_COLOR1_ATTRIB2__MAX_MIP_MASK = 0xF0000000 # macro +CB_COLOR1_VIEW__SLICE_START__SHIFT = 0x0 # macro +CB_COLOR1_VIEW__SLICE_MAX__SHIFT = 0xd # macro +CB_COLOR1_VIEW__MIP_LEVEL__SHIFT = 0x18 # macro +CB_COLOR1_VIEW__SLICE_START_MASK = 0x000007FF # macro +CB_COLOR1_VIEW__SLICE_MAX_MASK = 0x00FFE000 # macro +CB_COLOR1_VIEW__MIP_LEVEL_MASK = 0x0F000000 # macro +CB_COLOR1_INFO__ENDIAN__SHIFT = 0x0 # macro +CB_COLOR1_INFO__FORMAT__SHIFT = 0x2 # macro +CB_COLOR1_INFO__NUMBER_TYPE__SHIFT = 0x8 # macro +CB_COLOR1_INFO__COMP_SWAP__SHIFT = 0xb # macro +CB_COLOR1_INFO__FAST_CLEAR__SHIFT = 0xd # macro +CB_COLOR1_INFO__COMPRESSION__SHIFT = 0xe # macro +CB_COLOR1_INFO__BLEND_CLAMP__SHIFT = 0xf # macro +CB_COLOR1_INFO__BLEND_BYPASS__SHIFT = 0x10 # macro +CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT = 0x11 # macro +CB_COLOR1_INFO__ROUND_MODE__SHIFT = 0x12 # macro +CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT = 0x14 # macro +CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT = 0x17 # macro +CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT = 0x1a # macro +CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT = 0x1b # macro +CB_COLOR1_INFO__DCC_ENABLE__SHIFT = 0x1c # macro +CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT = 0x1d # macro +CB_COLOR1_INFO__ENDIAN_MASK = 0x00000003 # macro +CB_COLOR1_INFO__FORMAT_MASK = 0x0000007C # macro +CB_COLOR1_INFO__NUMBER_TYPE_MASK = 0x00000700 # macro +CB_COLOR1_INFO__COMP_SWAP_MASK = 0x00001800 # macro +CB_COLOR1_INFO__FAST_CLEAR_MASK = 0x00002000 # macro +CB_COLOR1_INFO__COMPRESSION_MASK = 0x00004000 # macro +CB_COLOR1_INFO__BLEND_CLAMP_MASK = 0x00008000 # macro +CB_COLOR1_INFO__BLEND_BYPASS_MASK = 0x00010000 # macro +CB_COLOR1_INFO__SIMPLE_FLOAT_MASK = 0x00020000 # macro +CB_COLOR1_INFO__ROUND_MODE_MASK = 0x00040000 # macro +CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK = 0x00700000 # macro +CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK = 0x03800000 # macro +CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK = 0x04000000 # macro +CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK = 0x08000000 # macro +CB_COLOR1_INFO__DCC_ENABLE_MASK = 0x10000000 # macro +CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK = 0x60000000 # macro +CB_COLOR1_ATTRIB__MIP0_DEPTH__SHIFT = 0x0 # macro +CB_COLOR1_ATTRIB__META_LINEAR__SHIFT = 0xb # macro +CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT = 0xc # macro +CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT = 0xf # macro +CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT = 0x11 # macro +CB_COLOR1_ATTRIB__COLOR_SW_MODE__SHIFT = 0x12 # macro +CB_COLOR1_ATTRIB__FMASK_SW_MODE__SHIFT = 0x17 # macro +CB_COLOR1_ATTRIB__RESOURCE_TYPE__SHIFT = 0x1c # macro +CB_COLOR1_ATTRIB__RB_ALIGNED__SHIFT = 0x1e # macro +CB_COLOR1_ATTRIB__PIPE_ALIGNED__SHIFT = 0x1f # macro +CB_COLOR1_ATTRIB__MIP0_DEPTH_MASK = 0x000007FF # macro +CB_COLOR1_ATTRIB__META_LINEAR_MASK = 0x00000800 # macro +CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK = 0x00007000 # macro +CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK = 0x00018000 # macro +CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK = 0x00020000 # macro +CB_COLOR1_ATTRIB__COLOR_SW_MODE_MASK = 0x007C0000 # macro +CB_COLOR1_ATTRIB__FMASK_SW_MODE_MASK = 0x0F800000 # macro +CB_COLOR1_ATTRIB__RESOURCE_TYPE_MASK = 0x30000000 # macro +CB_COLOR1_ATTRIB__RB_ALIGNED_MASK = 0x40000000 # macro +CB_COLOR1_ATTRIB__PIPE_ALIGNED_MASK = 0x80000000 # macro +CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT = 0x0 # macro +CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT = 0x1 # macro +CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT = 0x2 # macro +CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT = 0x4 # macro +CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT = 0x5 # macro +CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT = 0x7 # macro +CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT = 0x9 # macro +CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT = 0xa # macro +CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT = 0xe # macro +CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT = 0x12 # macro +CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT = 0x13 # macro +CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK = 0x00000001 # macro +CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK = 0x00000002 # macro +CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK = 0x0000000C # macro +CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK = 0x00000010 # macro +CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK = 0x00000060 # macro +CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK = 0x00000180 # macro +CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK = 0x00000200 # macro +CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK = 0x00003C00 # macro +CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK = 0x0003C000 # macro +CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK = 0x00040000 # macro +CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK = 0x00080000 # macro +CB_COLOR1_CMASK__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR1_CMASK__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR1_FMASK__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR1_FMASK__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT = 0x0 # macro +CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK = 0xFFFFFFFF # macro +CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT = 0x0 # macro +CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK = 0xFFFFFFFF # macro +CB_COLOR1_DCC_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR1_DCC_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR2_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR2_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR2_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR2_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT = 0x0 # macro +CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT = 0xe # macro +CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT = 0x1c # macro +CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK = 0x00003FFF # macro +CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK = 0x0FFFC000 # macro +CB_COLOR2_ATTRIB2__MAX_MIP_MASK = 0xF0000000 # macro +CB_COLOR2_VIEW__SLICE_START__SHIFT = 0x0 # macro +CB_COLOR2_VIEW__SLICE_MAX__SHIFT = 0xd # macro +CB_COLOR2_VIEW__MIP_LEVEL__SHIFT = 0x18 # macro +CB_COLOR2_VIEW__SLICE_START_MASK = 0x000007FF # macro +CB_COLOR2_VIEW__SLICE_MAX_MASK = 0x00FFE000 # macro +CB_COLOR2_VIEW__MIP_LEVEL_MASK = 0x0F000000 # macro +CB_COLOR2_INFO__ENDIAN__SHIFT = 0x0 # macro +CB_COLOR2_INFO__FORMAT__SHIFT = 0x2 # macro +CB_COLOR2_INFO__NUMBER_TYPE__SHIFT = 0x8 # macro +CB_COLOR2_INFO__COMP_SWAP__SHIFT = 0xb # macro +CB_COLOR2_INFO__FAST_CLEAR__SHIFT = 0xd # macro +CB_COLOR2_INFO__COMPRESSION__SHIFT = 0xe # macro +CB_COLOR2_INFO__BLEND_CLAMP__SHIFT = 0xf # macro +CB_COLOR2_INFO__BLEND_BYPASS__SHIFT = 0x10 # macro +CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT = 0x11 # macro +CB_COLOR2_INFO__ROUND_MODE__SHIFT = 0x12 # macro +CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT = 0x14 # macro +CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT = 0x17 # macro +CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT = 0x1a # macro +CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT = 0x1b # macro +CB_COLOR2_INFO__DCC_ENABLE__SHIFT = 0x1c # macro +CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT = 0x1d # macro +CB_COLOR2_INFO__ENDIAN_MASK = 0x00000003 # macro +CB_COLOR2_INFO__FORMAT_MASK = 0x0000007C # macro +CB_COLOR2_INFO__NUMBER_TYPE_MASK = 0x00000700 # macro +CB_COLOR2_INFO__COMP_SWAP_MASK = 0x00001800 # macro +CB_COLOR2_INFO__FAST_CLEAR_MASK = 0x00002000 # macro +CB_COLOR2_INFO__COMPRESSION_MASK = 0x00004000 # macro +CB_COLOR2_INFO__BLEND_CLAMP_MASK = 0x00008000 # macro +CB_COLOR2_INFO__BLEND_BYPASS_MASK = 0x00010000 # macro +CB_COLOR2_INFO__SIMPLE_FLOAT_MASK = 0x00020000 # macro +CB_COLOR2_INFO__ROUND_MODE_MASK = 0x00040000 # macro +CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK = 0x00700000 # macro +CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK = 0x03800000 # macro +CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK = 0x04000000 # macro +CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK = 0x08000000 # macro +CB_COLOR2_INFO__DCC_ENABLE_MASK = 0x10000000 # macro +CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK = 0x60000000 # macro +CB_COLOR2_ATTRIB__MIP0_DEPTH__SHIFT = 0x0 # macro +CB_COLOR2_ATTRIB__META_LINEAR__SHIFT = 0xb # macro +CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT = 0xc # macro +CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT = 0xf # macro +CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT = 0x11 # macro +CB_COLOR2_ATTRIB__COLOR_SW_MODE__SHIFT = 0x12 # macro +CB_COLOR2_ATTRIB__FMASK_SW_MODE__SHIFT = 0x17 # macro +CB_COLOR2_ATTRIB__RESOURCE_TYPE__SHIFT = 0x1c # macro +CB_COLOR2_ATTRIB__RB_ALIGNED__SHIFT = 0x1e # macro +CB_COLOR2_ATTRIB__PIPE_ALIGNED__SHIFT = 0x1f # macro +CB_COLOR2_ATTRIB__MIP0_DEPTH_MASK = 0x000007FF # macro +CB_COLOR2_ATTRIB__META_LINEAR_MASK = 0x00000800 # macro +CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK = 0x00007000 # macro +CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK = 0x00018000 # macro +CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK = 0x00020000 # macro +CB_COLOR2_ATTRIB__COLOR_SW_MODE_MASK = 0x007C0000 # macro +CB_COLOR2_ATTRIB__FMASK_SW_MODE_MASK = 0x0F800000 # macro +CB_COLOR2_ATTRIB__RESOURCE_TYPE_MASK = 0x30000000 # macro +CB_COLOR2_ATTRIB__RB_ALIGNED_MASK = 0x40000000 # macro +CB_COLOR2_ATTRIB__PIPE_ALIGNED_MASK = 0x80000000 # macro +CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT = 0x0 # macro +CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT = 0x1 # macro +CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT = 0x2 # macro +CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT = 0x4 # macro +CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT = 0x5 # macro +CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT = 0x7 # macro +CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT = 0x9 # macro +CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT = 0xa # macro +CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT = 0xe # macro +CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT = 0x12 # macro +CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT = 0x13 # macro +CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK = 0x00000001 # macro +CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK = 0x00000002 # macro +CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK = 0x0000000C # macro +CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK = 0x00000010 # macro +CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK = 0x00000060 # macro +CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK = 0x00000180 # macro +CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK = 0x00000200 # macro +CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK = 0x00003C00 # macro +CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK = 0x0003C000 # macro +CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK = 0x00040000 # macro +CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK = 0x00080000 # macro +CB_COLOR2_CMASK__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR2_CMASK__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR2_FMASK__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR2_FMASK__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT = 0x0 # macro +CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK = 0xFFFFFFFF # macro +CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT = 0x0 # macro +CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK = 0xFFFFFFFF # macro +CB_COLOR2_DCC_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR2_DCC_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR3_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR3_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR3_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR3_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT = 0x0 # macro +CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT = 0xe # macro +CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT = 0x1c # macro +CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK = 0x00003FFF # macro +CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK = 0x0FFFC000 # macro +CB_COLOR3_ATTRIB2__MAX_MIP_MASK = 0xF0000000 # macro +CB_COLOR3_VIEW__SLICE_START__SHIFT = 0x0 # macro +CB_COLOR3_VIEW__SLICE_MAX__SHIFT = 0xd # macro +CB_COLOR3_VIEW__MIP_LEVEL__SHIFT = 0x18 # macro +CB_COLOR3_VIEW__SLICE_START_MASK = 0x000007FF # macro +CB_COLOR3_VIEW__SLICE_MAX_MASK = 0x00FFE000 # macro +CB_COLOR3_VIEW__MIP_LEVEL_MASK = 0x0F000000 # macro +CB_COLOR3_INFO__ENDIAN__SHIFT = 0x0 # macro +CB_COLOR3_INFO__FORMAT__SHIFT = 0x2 # macro +CB_COLOR3_INFO__NUMBER_TYPE__SHIFT = 0x8 # macro +CB_COLOR3_INFO__COMP_SWAP__SHIFT = 0xb # macro +CB_COLOR3_INFO__FAST_CLEAR__SHIFT = 0xd # macro +CB_COLOR3_INFO__COMPRESSION__SHIFT = 0xe # macro +CB_COLOR3_INFO__BLEND_CLAMP__SHIFT = 0xf # macro +CB_COLOR3_INFO__BLEND_BYPASS__SHIFT = 0x10 # macro +CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT = 0x11 # macro +CB_COLOR3_INFO__ROUND_MODE__SHIFT = 0x12 # macro +CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT = 0x14 # macro +CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT = 0x17 # macro +CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT = 0x1a # macro +CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT = 0x1b # macro +CB_COLOR3_INFO__DCC_ENABLE__SHIFT = 0x1c # macro +CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT = 0x1d # macro +CB_COLOR3_INFO__ENDIAN_MASK = 0x00000003 # macro +CB_COLOR3_INFO__FORMAT_MASK = 0x0000007C # macro +CB_COLOR3_INFO__NUMBER_TYPE_MASK = 0x00000700 # macro +CB_COLOR3_INFO__COMP_SWAP_MASK = 0x00001800 # macro +CB_COLOR3_INFO__FAST_CLEAR_MASK = 0x00002000 # macro +CB_COLOR3_INFO__COMPRESSION_MASK = 0x00004000 # macro +CB_COLOR3_INFO__BLEND_CLAMP_MASK = 0x00008000 # macro +CB_COLOR3_INFO__BLEND_BYPASS_MASK = 0x00010000 # macro +CB_COLOR3_INFO__SIMPLE_FLOAT_MASK = 0x00020000 # macro +CB_COLOR3_INFO__ROUND_MODE_MASK = 0x00040000 # macro +CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK = 0x00700000 # macro +CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK = 0x03800000 # macro +CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK = 0x04000000 # macro +CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK = 0x08000000 # macro +CB_COLOR3_INFO__DCC_ENABLE_MASK = 0x10000000 # macro +CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK = 0x60000000 # macro +CB_COLOR3_ATTRIB__MIP0_DEPTH__SHIFT = 0x0 # macro +CB_COLOR3_ATTRIB__META_LINEAR__SHIFT = 0xb # macro +CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT = 0xc # macro +CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT = 0xf # macro +CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT = 0x11 # macro +CB_COLOR3_ATTRIB__COLOR_SW_MODE__SHIFT = 0x12 # macro +CB_COLOR3_ATTRIB__FMASK_SW_MODE__SHIFT = 0x17 # macro +CB_COLOR3_ATTRIB__RESOURCE_TYPE__SHIFT = 0x1c # macro +CB_COLOR3_ATTRIB__RB_ALIGNED__SHIFT = 0x1e # macro +CB_COLOR3_ATTRIB__PIPE_ALIGNED__SHIFT = 0x1f # macro +CB_COLOR3_ATTRIB__MIP0_DEPTH_MASK = 0x000007FF # macro +CB_COLOR3_ATTRIB__META_LINEAR_MASK = 0x00000800 # macro +CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK = 0x00007000 # macro +CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK = 0x00018000 # macro +CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK = 0x00020000 # macro +CB_COLOR3_ATTRIB__COLOR_SW_MODE_MASK = 0x007C0000 # macro +CB_COLOR3_ATTRIB__FMASK_SW_MODE_MASK = 0x0F800000 # macro +CB_COLOR3_ATTRIB__RESOURCE_TYPE_MASK = 0x30000000 # macro +CB_COLOR3_ATTRIB__RB_ALIGNED_MASK = 0x40000000 # macro +CB_COLOR3_ATTRIB__PIPE_ALIGNED_MASK = 0x80000000 # macro +CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT = 0x0 # macro +CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT = 0x1 # macro +CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT = 0x2 # macro +CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT = 0x4 # macro +CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT = 0x5 # macro +CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT = 0x7 # macro +CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT = 0x9 # macro +CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT = 0xa # macro +CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT = 0xe # macro +CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT = 0x12 # macro +CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT = 0x13 # macro +CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK = 0x00000001 # macro +CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK = 0x00000002 # macro +CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK = 0x0000000C # macro +CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK = 0x00000010 # macro +CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK = 0x00000060 # macro +CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK = 0x00000180 # macro +CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK = 0x00000200 # macro +CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK = 0x00003C00 # macro +CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK = 0x0003C000 # macro +CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK = 0x00040000 # macro +CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK = 0x00080000 # macro +CB_COLOR3_CMASK__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR3_CMASK__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR3_FMASK__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR3_FMASK__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT = 0x0 # macro +CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK = 0xFFFFFFFF # macro +CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT = 0x0 # macro +CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK = 0xFFFFFFFF # macro +CB_COLOR3_DCC_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR3_DCC_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR4_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR4_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR4_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR4_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT = 0x0 # macro +CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT = 0xe # macro +CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT = 0x1c # macro +CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK = 0x00003FFF # macro +CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK = 0x0FFFC000 # macro +CB_COLOR4_ATTRIB2__MAX_MIP_MASK = 0xF0000000 # macro +CB_COLOR4_VIEW__SLICE_START__SHIFT = 0x0 # macro +CB_COLOR4_VIEW__SLICE_MAX__SHIFT = 0xd # macro +CB_COLOR4_VIEW__MIP_LEVEL__SHIFT = 0x18 # macro +CB_COLOR4_VIEW__SLICE_START_MASK = 0x000007FF # macro +CB_COLOR4_VIEW__SLICE_MAX_MASK = 0x00FFE000 # macro +CB_COLOR4_VIEW__MIP_LEVEL_MASK = 0x0F000000 # macro +CB_COLOR4_INFO__ENDIAN__SHIFT = 0x0 # macro +CB_COLOR4_INFO__FORMAT__SHIFT = 0x2 # macro +CB_COLOR4_INFO__NUMBER_TYPE__SHIFT = 0x8 # macro +CB_COLOR4_INFO__COMP_SWAP__SHIFT = 0xb # macro +CB_COLOR4_INFO__FAST_CLEAR__SHIFT = 0xd # macro +CB_COLOR4_INFO__COMPRESSION__SHIFT = 0xe # macro +CB_COLOR4_INFO__BLEND_CLAMP__SHIFT = 0xf # macro +CB_COLOR4_INFO__BLEND_BYPASS__SHIFT = 0x10 # macro +CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT = 0x11 # macro +CB_COLOR4_INFO__ROUND_MODE__SHIFT = 0x12 # macro +CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT = 0x14 # macro +CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT = 0x17 # macro +CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT = 0x1a # macro +CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT = 0x1b # macro +CB_COLOR4_INFO__DCC_ENABLE__SHIFT = 0x1c # macro +CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT = 0x1d # macro +CB_COLOR4_INFO__ENDIAN_MASK = 0x00000003 # macro +CB_COLOR4_INFO__FORMAT_MASK = 0x0000007C # macro +CB_COLOR4_INFO__NUMBER_TYPE_MASK = 0x00000700 # macro +CB_COLOR4_INFO__COMP_SWAP_MASK = 0x00001800 # macro +CB_COLOR4_INFO__FAST_CLEAR_MASK = 0x00002000 # macro +CB_COLOR4_INFO__COMPRESSION_MASK = 0x00004000 # macro +CB_COLOR4_INFO__BLEND_CLAMP_MASK = 0x00008000 # macro +CB_COLOR4_INFO__BLEND_BYPASS_MASK = 0x00010000 # macro +CB_COLOR4_INFO__SIMPLE_FLOAT_MASK = 0x00020000 # macro +CB_COLOR4_INFO__ROUND_MODE_MASK = 0x00040000 # macro +CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK = 0x00700000 # macro +CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK = 0x03800000 # macro +CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK = 0x04000000 # macro +CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK = 0x08000000 # macro +CB_COLOR4_INFO__DCC_ENABLE_MASK = 0x10000000 # macro +CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK = 0x60000000 # macro +CB_COLOR4_ATTRIB__MIP0_DEPTH__SHIFT = 0x0 # macro +CB_COLOR4_ATTRIB__META_LINEAR__SHIFT = 0xb # macro +CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT = 0xc # macro +CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT = 0xf # macro +CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT = 0x11 # macro +CB_COLOR4_ATTRIB__COLOR_SW_MODE__SHIFT = 0x12 # macro +CB_COLOR4_ATTRIB__FMASK_SW_MODE__SHIFT = 0x17 # macro +CB_COLOR4_ATTRIB__RESOURCE_TYPE__SHIFT = 0x1c # macro +CB_COLOR4_ATTRIB__RB_ALIGNED__SHIFT = 0x1e # macro +CB_COLOR4_ATTRIB__PIPE_ALIGNED__SHIFT = 0x1f # macro +CB_COLOR4_ATTRIB__MIP0_DEPTH_MASK = 0x000007FF # macro +CB_COLOR4_ATTRIB__META_LINEAR_MASK = 0x00000800 # macro +CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK = 0x00007000 # macro +CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK = 0x00018000 # macro +CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK = 0x00020000 # macro +CB_COLOR4_ATTRIB__COLOR_SW_MODE_MASK = 0x007C0000 # macro +CB_COLOR4_ATTRIB__FMASK_SW_MODE_MASK = 0x0F800000 # macro +CB_COLOR4_ATTRIB__RESOURCE_TYPE_MASK = 0x30000000 # macro +CB_COLOR4_ATTRIB__RB_ALIGNED_MASK = 0x40000000 # macro +CB_COLOR4_ATTRIB__PIPE_ALIGNED_MASK = 0x80000000 # macro +CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT = 0x0 # macro +CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT = 0x1 # macro +CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT = 0x2 # macro +CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT = 0x4 # macro +CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT = 0x5 # macro +CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT = 0x7 # macro +CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT = 0x9 # macro +CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT = 0xa # macro +CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT = 0xe # macro +CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT = 0x12 # macro +CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT = 0x13 # macro +CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK = 0x00000001 # macro +CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK = 0x00000002 # macro +CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK = 0x0000000C # macro +CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK = 0x00000010 # macro +CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK = 0x00000060 # macro +CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK = 0x00000180 # macro +CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK = 0x00000200 # macro +CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK = 0x00003C00 # macro +CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK = 0x0003C000 # macro +CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK = 0x00040000 # macro +CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK = 0x00080000 # macro +CB_COLOR4_CMASK__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR4_CMASK__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR4_FMASK__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR4_FMASK__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT = 0x0 # macro +CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK = 0xFFFFFFFF # macro +CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT = 0x0 # macro +CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK = 0xFFFFFFFF # macro +CB_COLOR4_DCC_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR4_DCC_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR5_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR5_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR5_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR5_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT = 0x0 # macro +CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT = 0xe # macro +CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT = 0x1c # macro +CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK = 0x00003FFF # macro +CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK = 0x0FFFC000 # macro +CB_COLOR5_ATTRIB2__MAX_MIP_MASK = 0xF0000000 # macro +CB_COLOR5_VIEW__SLICE_START__SHIFT = 0x0 # macro +CB_COLOR5_VIEW__SLICE_MAX__SHIFT = 0xd # macro +CB_COLOR5_VIEW__MIP_LEVEL__SHIFT = 0x18 # macro +CB_COLOR5_VIEW__SLICE_START_MASK = 0x000007FF # macro +CB_COLOR5_VIEW__SLICE_MAX_MASK = 0x00FFE000 # macro +CB_COLOR5_VIEW__MIP_LEVEL_MASK = 0x0F000000 # macro +CB_COLOR5_INFO__ENDIAN__SHIFT = 0x0 # macro +CB_COLOR5_INFO__FORMAT__SHIFT = 0x2 # macro +CB_COLOR5_INFO__NUMBER_TYPE__SHIFT = 0x8 # macro +CB_COLOR5_INFO__COMP_SWAP__SHIFT = 0xb # macro +CB_COLOR5_INFO__FAST_CLEAR__SHIFT = 0xd # macro +CB_COLOR5_INFO__COMPRESSION__SHIFT = 0xe # macro +CB_COLOR5_INFO__BLEND_CLAMP__SHIFT = 0xf # macro +CB_COLOR5_INFO__BLEND_BYPASS__SHIFT = 0x10 # macro +CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT = 0x11 # macro +CB_COLOR5_INFO__ROUND_MODE__SHIFT = 0x12 # macro +CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT = 0x14 # macro +CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT = 0x17 # macro +CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT = 0x1a # macro +CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT = 0x1b # macro +CB_COLOR5_INFO__DCC_ENABLE__SHIFT = 0x1c # macro +CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT = 0x1d # macro +CB_COLOR5_INFO__ENDIAN_MASK = 0x00000003 # macro +CB_COLOR5_INFO__FORMAT_MASK = 0x0000007C # macro +CB_COLOR5_INFO__NUMBER_TYPE_MASK = 0x00000700 # macro +CB_COLOR5_INFO__COMP_SWAP_MASK = 0x00001800 # macro +CB_COLOR5_INFO__FAST_CLEAR_MASK = 0x00002000 # macro +CB_COLOR5_INFO__COMPRESSION_MASK = 0x00004000 # macro +CB_COLOR5_INFO__BLEND_CLAMP_MASK = 0x00008000 # macro +CB_COLOR5_INFO__BLEND_BYPASS_MASK = 0x00010000 # macro +CB_COLOR5_INFO__SIMPLE_FLOAT_MASK = 0x00020000 # macro +CB_COLOR5_INFO__ROUND_MODE_MASK = 0x00040000 # macro +CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK = 0x00700000 # macro +CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK = 0x03800000 # macro +CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK = 0x04000000 # macro +CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK = 0x08000000 # macro +CB_COLOR5_INFO__DCC_ENABLE_MASK = 0x10000000 # macro +CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK = 0x60000000 # macro +CB_COLOR5_ATTRIB__MIP0_DEPTH__SHIFT = 0x0 # macro +CB_COLOR5_ATTRIB__META_LINEAR__SHIFT = 0xb # macro +CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT = 0xc # macro +CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT = 0xf # macro +CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT = 0x11 # macro +CB_COLOR5_ATTRIB__COLOR_SW_MODE__SHIFT = 0x12 # macro +CB_COLOR5_ATTRIB__FMASK_SW_MODE__SHIFT = 0x17 # macro +CB_COLOR5_ATTRIB__RESOURCE_TYPE__SHIFT = 0x1c # macro +CB_COLOR5_ATTRIB__RB_ALIGNED__SHIFT = 0x1e # macro +CB_COLOR5_ATTRIB__PIPE_ALIGNED__SHIFT = 0x1f # macro +CB_COLOR5_ATTRIB__MIP0_DEPTH_MASK = 0x000007FF # macro +CB_COLOR5_ATTRIB__META_LINEAR_MASK = 0x00000800 # macro +CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK = 0x00007000 # macro +CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK = 0x00018000 # macro +CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK = 0x00020000 # macro +CB_COLOR5_ATTRIB__COLOR_SW_MODE_MASK = 0x007C0000 # macro +CB_COLOR5_ATTRIB__FMASK_SW_MODE_MASK = 0x0F800000 # macro +CB_COLOR5_ATTRIB__RESOURCE_TYPE_MASK = 0x30000000 # macro +CB_COLOR5_ATTRIB__RB_ALIGNED_MASK = 0x40000000 # macro +CB_COLOR5_ATTRIB__PIPE_ALIGNED_MASK = 0x80000000 # macro +CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT = 0x0 # macro +CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT = 0x1 # macro +CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT = 0x2 # macro +CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT = 0x4 # macro +CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT = 0x5 # macro +CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT = 0x7 # macro +CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT = 0x9 # macro +CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT = 0xa # macro +CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT = 0xe # macro +CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT = 0x12 # macro +CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT = 0x13 # macro +CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK = 0x00000001 # macro +CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK = 0x00000002 # macro +CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK = 0x0000000C # macro +CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK = 0x00000010 # macro +CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK = 0x00000060 # macro +CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK = 0x00000180 # macro +CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK = 0x00000200 # macro +CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK = 0x00003C00 # macro +CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK = 0x0003C000 # macro +CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK = 0x00040000 # macro +CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK = 0x00080000 # macro +CB_COLOR5_CMASK__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR5_CMASK__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR5_FMASK__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR5_FMASK__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT = 0x0 # macro +CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK = 0xFFFFFFFF # macro +CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT = 0x0 # macro +CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK = 0xFFFFFFFF # macro +CB_COLOR5_DCC_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR5_DCC_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR6_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR6_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR6_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR6_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT = 0x0 # macro +CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT = 0xe # macro +CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT = 0x1c # macro +CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK = 0x00003FFF # macro +CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK = 0x0FFFC000 # macro +CB_COLOR6_ATTRIB2__MAX_MIP_MASK = 0xF0000000 # macro +CB_COLOR6_VIEW__SLICE_START__SHIFT = 0x0 # macro +CB_COLOR6_VIEW__SLICE_MAX__SHIFT = 0xd # macro +CB_COLOR6_VIEW__MIP_LEVEL__SHIFT = 0x18 # macro +CB_COLOR6_VIEW__SLICE_START_MASK = 0x000007FF # macro +CB_COLOR6_VIEW__SLICE_MAX_MASK = 0x00FFE000 # macro +CB_COLOR6_VIEW__MIP_LEVEL_MASK = 0x0F000000 # macro +CB_COLOR6_INFO__ENDIAN__SHIFT = 0x0 # macro +CB_COLOR6_INFO__FORMAT__SHIFT = 0x2 # macro +CB_COLOR6_INFO__NUMBER_TYPE__SHIFT = 0x8 # macro +CB_COLOR6_INFO__COMP_SWAP__SHIFT = 0xb # macro +CB_COLOR6_INFO__FAST_CLEAR__SHIFT = 0xd # macro +CB_COLOR6_INFO__COMPRESSION__SHIFT = 0xe # macro +CB_COLOR6_INFO__BLEND_CLAMP__SHIFT = 0xf # macro +CB_COLOR6_INFO__BLEND_BYPASS__SHIFT = 0x10 # macro +CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT = 0x11 # macro +CB_COLOR6_INFO__ROUND_MODE__SHIFT = 0x12 # macro +CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT = 0x14 # macro +CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT = 0x17 # macro +CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT = 0x1a # macro +CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT = 0x1b # macro +CB_COLOR6_INFO__DCC_ENABLE__SHIFT = 0x1c # macro +CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT = 0x1d # macro +CB_COLOR6_INFO__ENDIAN_MASK = 0x00000003 # macro +CB_COLOR6_INFO__FORMAT_MASK = 0x0000007C # macro +CB_COLOR6_INFO__NUMBER_TYPE_MASK = 0x00000700 # macro +CB_COLOR6_INFO__COMP_SWAP_MASK = 0x00001800 # macro +CB_COLOR6_INFO__FAST_CLEAR_MASK = 0x00002000 # macro +CB_COLOR6_INFO__COMPRESSION_MASK = 0x00004000 # macro +CB_COLOR6_INFO__BLEND_CLAMP_MASK = 0x00008000 # macro +CB_COLOR6_INFO__BLEND_BYPASS_MASK = 0x00010000 # macro +CB_COLOR6_INFO__SIMPLE_FLOAT_MASK = 0x00020000 # macro +CB_COLOR6_INFO__ROUND_MODE_MASK = 0x00040000 # macro +CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK = 0x00700000 # macro +CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK = 0x03800000 # macro +CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK = 0x04000000 # macro +CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK = 0x08000000 # macro +CB_COLOR6_INFO__DCC_ENABLE_MASK = 0x10000000 # macro +CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK = 0x60000000 # macro +CB_COLOR6_ATTRIB__MIP0_DEPTH__SHIFT = 0x0 # macro +CB_COLOR6_ATTRIB__META_LINEAR__SHIFT = 0xb # macro +CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT = 0xc # macro +CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT = 0xf # macro +CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT = 0x11 # macro +CB_COLOR6_ATTRIB__COLOR_SW_MODE__SHIFT = 0x12 # macro +CB_COLOR6_ATTRIB__FMASK_SW_MODE__SHIFT = 0x17 # macro +CB_COLOR6_ATTRIB__RESOURCE_TYPE__SHIFT = 0x1c # macro +CB_COLOR6_ATTRIB__RB_ALIGNED__SHIFT = 0x1e # macro +CB_COLOR6_ATTRIB__PIPE_ALIGNED__SHIFT = 0x1f # macro +CB_COLOR6_ATTRIB__MIP0_DEPTH_MASK = 0x000007FF # macro +CB_COLOR6_ATTRIB__META_LINEAR_MASK = 0x00000800 # macro +CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK = 0x00007000 # macro +CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK = 0x00018000 # macro +CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK = 0x00020000 # macro +CB_COLOR6_ATTRIB__COLOR_SW_MODE_MASK = 0x007C0000 # macro +CB_COLOR6_ATTRIB__FMASK_SW_MODE_MASK = 0x0F800000 # macro +CB_COLOR6_ATTRIB__RESOURCE_TYPE_MASK = 0x30000000 # macro +CB_COLOR6_ATTRIB__RB_ALIGNED_MASK = 0x40000000 # macro +CB_COLOR6_ATTRIB__PIPE_ALIGNED_MASK = 0x80000000 # macro +CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT = 0x0 # macro +CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT = 0x1 # macro +CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT = 0x2 # macro +CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT = 0x4 # macro +CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT = 0x5 # macro +CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT = 0x7 # macro +CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT = 0x9 # macro +CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT = 0xa # macro +CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT = 0xe # macro +CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT = 0x12 # macro +CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT = 0x13 # macro +CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK = 0x00000001 # macro +CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK = 0x00000002 # macro +CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK = 0x0000000C # macro +CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK = 0x00000010 # macro +CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK = 0x00000060 # macro +CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK = 0x00000180 # macro +CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK = 0x00000200 # macro +CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK = 0x00003C00 # macro +CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK = 0x0003C000 # macro +CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK = 0x00040000 # macro +CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK = 0x00080000 # macro +CB_COLOR6_CMASK__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR6_CMASK__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR6_FMASK__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR6_FMASK__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT = 0x0 # macro +CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK = 0xFFFFFFFF # macro +CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT = 0x0 # macro +CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK = 0xFFFFFFFF # macro +CB_COLOR6_DCC_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR6_DCC_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR7_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR7_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR7_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR7_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT = 0x0 # macro +CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT = 0xe # macro +CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT = 0x1c # macro +CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK = 0x00003FFF # macro +CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK = 0x0FFFC000 # macro +CB_COLOR7_ATTRIB2__MAX_MIP_MASK = 0xF0000000 # macro +CB_COLOR7_VIEW__SLICE_START__SHIFT = 0x0 # macro +CB_COLOR7_VIEW__SLICE_MAX__SHIFT = 0xd # macro +CB_COLOR7_VIEW__MIP_LEVEL__SHIFT = 0x18 # macro +CB_COLOR7_VIEW__SLICE_START_MASK = 0x000007FF # macro +CB_COLOR7_VIEW__SLICE_MAX_MASK = 0x00FFE000 # macro +CB_COLOR7_VIEW__MIP_LEVEL_MASK = 0x0F000000 # macro +CB_COLOR7_INFO__ENDIAN__SHIFT = 0x0 # macro +CB_COLOR7_INFO__FORMAT__SHIFT = 0x2 # macro +CB_COLOR7_INFO__NUMBER_TYPE__SHIFT = 0x8 # macro +CB_COLOR7_INFO__COMP_SWAP__SHIFT = 0xb # macro +CB_COLOR7_INFO__FAST_CLEAR__SHIFT = 0xd # macro +CB_COLOR7_INFO__COMPRESSION__SHIFT = 0xe # macro +CB_COLOR7_INFO__BLEND_CLAMP__SHIFT = 0xf # macro +CB_COLOR7_INFO__BLEND_BYPASS__SHIFT = 0x10 # macro +CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT = 0x11 # macro +CB_COLOR7_INFO__ROUND_MODE__SHIFT = 0x12 # macro +CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT = 0x14 # macro +CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT = 0x17 # macro +CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT = 0x1a # macro +CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT = 0x1b # macro +CB_COLOR7_INFO__DCC_ENABLE__SHIFT = 0x1c # macro +CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT = 0x1d # macro +CB_COLOR7_INFO__ENDIAN_MASK = 0x00000003 # macro +CB_COLOR7_INFO__FORMAT_MASK = 0x0000007C # macro +CB_COLOR7_INFO__NUMBER_TYPE_MASK = 0x00000700 # macro +CB_COLOR7_INFO__COMP_SWAP_MASK = 0x00001800 # macro +CB_COLOR7_INFO__FAST_CLEAR_MASK = 0x00002000 # macro +CB_COLOR7_INFO__COMPRESSION_MASK = 0x00004000 # macro +CB_COLOR7_INFO__BLEND_CLAMP_MASK = 0x00008000 # macro +CB_COLOR7_INFO__BLEND_BYPASS_MASK = 0x00010000 # macro +CB_COLOR7_INFO__SIMPLE_FLOAT_MASK = 0x00020000 # macro +CB_COLOR7_INFO__ROUND_MODE_MASK = 0x00040000 # macro +CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK = 0x00700000 # macro +CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK = 0x03800000 # macro +CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK = 0x04000000 # macro +CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK = 0x08000000 # macro +CB_COLOR7_INFO__DCC_ENABLE_MASK = 0x10000000 # macro +CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK = 0x60000000 # macro +CB_COLOR7_ATTRIB__MIP0_DEPTH__SHIFT = 0x0 # macro +CB_COLOR7_ATTRIB__META_LINEAR__SHIFT = 0xb # macro +CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT = 0xc # macro +CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT = 0xf # macro +CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT = 0x11 # macro +CB_COLOR7_ATTRIB__COLOR_SW_MODE__SHIFT = 0x12 # macro +CB_COLOR7_ATTRIB__FMASK_SW_MODE__SHIFT = 0x17 # macro +CB_COLOR7_ATTRIB__RESOURCE_TYPE__SHIFT = 0x1c # macro +CB_COLOR7_ATTRIB__RB_ALIGNED__SHIFT = 0x1e # macro +CB_COLOR7_ATTRIB__PIPE_ALIGNED__SHIFT = 0x1f # macro +CB_COLOR7_ATTRIB__MIP0_DEPTH_MASK = 0x000007FF # macro +CB_COLOR7_ATTRIB__META_LINEAR_MASK = 0x00000800 # macro +CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK = 0x00007000 # macro +CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK = 0x00018000 # macro +CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK = 0x00020000 # macro +CB_COLOR7_ATTRIB__COLOR_SW_MODE_MASK = 0x007C0000 # macro +CB_COLOR7_ATTRIB__FMASK_SW_MODE_MASK = 0x0F800000 # macro +CB_COLOR7_ATTRIB__RESOURCE_TYPE_MASK = 0x30000000 # macro +CB_COLOR7_ATTRIB__RB_ALIGNED_MASK = 0x40000000 # macro +CB_COLOR7_ATTRIB__PIPE_ALIGNED_MASK = 0x80000000 # macro +CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT = 0x0 # macro +CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT = 0x1 # macro +CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT = 0x2 # macro +CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT = 0x4 # macro +CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT = 0x5 # macro +CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT = 0x7 # macro +CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT = 0x9 # macro +CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT = 0xa # macro +CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT = 0xe # macro +CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT = 0x12 # macro +CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT = 0x13 # macro +CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK = 0x00000001 # macro +CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK = 0x00000002 # macro +CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK = 0x0000000C # macro +CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK = 0x00000010 # macro +CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK = 0x00000060 # macro +CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK = 0x00000180 # macro +CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK = 0x00000200 # macro +CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK = 0x00003C00 # macro +CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK = 0x0003C000 # macro +CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK = 0x00040000 # macro +CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK = 0x00080000 # macro +CB_COLOR7_CMASK__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR7_CMASK__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR7_FMASK__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR7_FMASK__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT = 0x0 # macro +CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK = 0xFFFFFFFF # macro +CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT = 0x0 # macro +CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK = 0xFFFFFFFF # macro +CB_COLOR7_DCC_BASE__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR7_DCC_BASE__BASE_256B_MASK = 0xFFFFFFFF # macro +CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT = 0x0 # macro +CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK = 0x000000FF # macro +CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT = 0x2 # macro +CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK = 0xFFFFFFFC # macro +CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT = 0x0 # macro +CP_EOP_DONE_DATA_LO__DATA_LO_MASK = 0xFFFFFFFF # macro +CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT = 0x0 # macro +CP_EOP_DONE_DATA_HI__DATA_HI_MASK = 0xFFFFFFFF # macro +CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT = 0x0 # macro +CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK = 0xFFFFFFFF # macro +CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT = 0x0 # macro +CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK = 0xFFFFFFFF # macro +CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT = 0x2 # macro +CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK = 0xFFFFFFFC # macro +CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT = 0x0 # macro +CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK = 0x0000FFFF # macro +CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT = 0x0 # macro +CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK = 0xFFFFFFFF # macro +CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT = 0x0 # macro +CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK = 0xFFFFFFFF # macro +CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT = 0x0 # macro +CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK = 0xFFFFFFFF # macro +CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT = 0x0 # macro +CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK = 0xFFFFFFFF # macro +CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT = 0x0 # macro +CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK = 0xFFFFFFFF # macro +CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT = 0x0 # macro +CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK = 0xFFFFFFFF # macro +CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT = 0x0 # macro +CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK = 0xFFFFFFFF # macro +CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT = 0x0 # macro +CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK = 0xFFFFFFFF # macro +CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT = 0x0 # macro +CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK = 0xFFFFFFFF # macro +CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT = 0x0 # macro +CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK = 0xFFFFFFFF # macro +CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT = 0x0 # macro +CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK = 0xFFFFFFFF # macro +CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT = 0x0 # macro +CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK = 0xFFFFFFFF # macro +CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT = 0x0 # macro +CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK = 0xFFFFFFFF # macro +CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT = 0x0 # macro +CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK = 0xFFFFFFFF # macro +CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT = 0x0 # macro +CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK = 0xFFFFFFFF # macro +CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT = 0x0 # macro +CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK = 0xFFFFFFFF # macro +CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT = 0x2 # macro +CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK = 0xFFFFFFFC # macro +CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT = 0x0 # macro +CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK = 0x0000FFFF # macro +CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT = 0x0 # macro +CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT = 0x0 # macro +CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT = 0x0 # macro +CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT = 0x0 # macro +CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT = 0x0 # macro +CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT = 0x0 # macro +CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT = 0x0 # macro +CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT = 0x0 # macro +CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT = 0x0 # macro +CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT = 0x0 # macro +CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT = 0x0 # macro +CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT = 0x0 # macro +CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT = 0x0 # macro +CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT = 0x0 # macro +CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT = 0x0 # macro +CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT = 0x0 # macro +CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT = 0x0 # macro +CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT = 0x0 # macro +CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT = 0x0 # macro +CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK = 0xFFFFFFFF # macro +CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT = 0x0 # macro +CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK = 0xFFFFFFFF # macro +CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT = 0x0 # macro +CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK = 0xFFFFFFFF # macro +CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT = 0x0 # macro +CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK = 0xFFFFFFFF # macro +CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT = 0x0 # macro +CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK = 0xFFFFFFFF # macro +CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT = 0x0 # macro +CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK = 0xFFFFFFFF # macro +CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT = 0x19 # macro +CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK = 0x02000000 # macro +CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT = 0x19 # macro +CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK = 0x02000000 # macro +CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT = 0x0 # macro +CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK = 0x00000001 # macro +SCRATCH_REG0__SCRATCH_REG0__SHIFT = 0x0 # macro +SCRATCH_REG0__SCRATCH_REG0_MASK = 0xFFFFFFFF # macro +SCRATCH_REG1__SCRATCH_REG1__SHIFT = 0x0 # macro +SCRATCH_REG1__SCRATCH_REG1_MASK = 0xFFFFFFFF # macro +SCRATCH_REG2__SCRATCH_REG2__SHIFT = 0x0 # macro +SCRATCH_REG2__SCRATCH_REG2_MASK = 0xFFFFFFFF # macro +SCRATCH_REG3__SCRATCH_REG3__SHIFT = 0x0 # macro +SCRATCH_REG3__SCRATCH_REG3_MASK = 0xFFFFFFFF # macro +SCRATCH_REG4__SCRATCH_REG4__SHIFT = 0x0 # macro +SCRATCH_REG4__SCRATCH_REG4_MASK = 0xFFFFFFFF # macro +SCRATCH_REG5__SCRATCH_REG5__SHIFT = 0x0 # macro +SCRATCH_REG5__SCRATCH_REG5_MASK = 0xFFFFFFFF # macro +SCRATCH_REG6__SCRATCH_REG6__SHIFT = 0x0 # macro +SCRATCH_REG6__SCRATCH_REG6_MASK = 0xFFFFFFFF # macro +SCRATCH_REG7__SCRATCH_REG7__SHIFT = 0x0 # macro +SCRATCH_REG7__SCRATCH_REG7_MASK = 0xFFFFFFFF # macro +CP_APPEND_DATA_HI__DATA__SHIFT = 0x0 # macro +CP_APPEND_DATA_HI__DATA_MASK = 0xFFFFFFFF # macro +CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT = 0x0 # macro +CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK = 0xFFFFFFFF # macro +CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT = 0x0 # macro +CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK = 0xFFFFFFFF # macro +SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT = 0x0 # macro +SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT = 0x10 # macro +SCRATCH_UMSK__OBSOLETE_UMSK_MASK = 0x000000FF # macro +SCRATCH_UMSK__OBSOLETE_SWAP_MASK = 0x00030000 # macro +SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT = 0x0 # macro +SCRATCH_ADDR__OBSOLETE_ADDR_MASK = 0xFFFFFFFF # macro +CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT = 0x0 # macro +CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT = 0x0 # macro +CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT = 0x0 # macro +CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT = 0x0 # macro +CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT = 0x0 # macro +CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT = 0x0 # macro +CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT = 0x2 # macro +CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK = 0xFFFFFFFC # macro +CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT = 0x0 # macro +CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT = 0x10 # macro +CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT = 0x19 # macro +CP_APPEND_ADDR_HI__COMMAND__SHIFT = 0x1d # macro +CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK = 0x0000FFFF # macro +CP_APPEND_ADDR_HI__CS_PS_SEL_MASK = 0x00010000 # macro +CP_APPEND_ADDR_HI__CACHE_POLICY_MASK = 0x02000000 # macro +CP_APPEND_ADDR_HI__COMMAND_MASK = 0xE0000000 # macro +CP_APPEND_DATA_LO__DATA__SHIFT = 0x0 # macro +CP_APPEND_DATA_LO__DATA_MASK = 0xFFFFFFFF # macro +CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT = 0x0 # macro +CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK = 0xFFFFFFFF # macro +CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT = 0x0 # macro +CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK = 0xFFFFFFFF # macro +CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT = 0x0 # macro +CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT = 0x0 # macro +CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT = 0x0 # macro +CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT = 0x0 # macro +CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT = 0x0 # macro +CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT = 0x0 # macro +CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT = 0x0 # macro +CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT = 0x0 # macro +CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT = 0x0 # macro +CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT = 0x0 # macro +CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK = 0xFFFFFFFF # macro +CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT = 0x0 # macro +CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT = 0x0 # macro +CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK = 0xFFFFFFFF # macro +CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT = 0x2 # macro +CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK = 0xFFFFFFFC # macro +CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT = 0x0 # macro +CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT = 0x16 # macro +CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK = 0x0000FFFF # macro +CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK = 0x00400000 # macro +CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT = 0x0 # macro +CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK = 0xFFFFFFFF # macro +CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT = 0x0 # macro +CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK = 0xFFFFFFFF # macro +CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT = 0x2 # macro +CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK = 0xFFFFFFFC # macro +CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT = 0x0 # macro +CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT = 0x16 # macro +CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK = 0x0000FFFF # macro +CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK = 0x00400000 # macro +CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT = 0x0 # macro +CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK = 0xFFFFFFFF # macro +CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT = 0x0 # macro +CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT = 0x3 # macro +CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK = 0x00000003 # macro +CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK = 0xFFFFFFF8 # macro +CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT = 0x0 # macro +CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT = 0x10 # macro +CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT = 0x14 # macro +CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT = 0x18 # macro +CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT = 0x1d # macro +CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK = 0x0000FFFF # macro +CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK = 0x00010000 # macro +CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK = 0x00100000 # macro +CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK = 0x03000000 # macro +CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK = 0xE0000000 # macro +CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT = 0x0 # macro +CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK = 0xFFFFFFFF # macro +CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT = 0x0 # macro +CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT = 0x3 # macro +CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK = 0x00000003 # macro +CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK = 0xFFFFFFF8 # macro +CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT = 0x0 # macro +CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT = 0x10 # macro +CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT = 0x14 # macro +CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT = 0x18 # macro +CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT = 0x1d # macro +CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK = 0x0000FFFF # macro +CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK = 0x00010000 # macro +CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK = 0x00100000 # macro +CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK = 0x03000000 # macro +CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK = 0xE0000000 # macro +CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT = 0xa # macro +CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT = 0xd # macro +CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT = 0x14 # macro +CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT = 0x19 # macro +CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT = 0x1d # macro +CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK = 0x00000400 # macro +CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK = 0x00002000 # macro +CP_DMA_PFP_CONTROL__DST_SELECT_MASK = 0x00300000 # macro +CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK = 0x02000000 # macro +CP_DMA_PFP_CONTROL__SRC_SELECT_MASK = 0x60000000 # macro +CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT = 0xa # macro +CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT = 0xd # macro +CP_DMA_ME_CONTROL__DST_SELECT__SHIFT = 0x14 # macro +CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT = 0x19 # macro +CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT = 0x1d # macro +CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK = 0x00000400 # macro +CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK = 0x00002000 # macro +CP_DMA_ME_CONTROL__DST_SELECT_MASK = 0x00300000 # macro +CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK = 0x02000000 # macro +CP_DMA_ME_CONTROL__SRC_SELECT_MASK = 0x60000000 # macro +CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT = 0x0 # macro +CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK = 0x000000FF # macro +CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT = 0x0 # macro +CP_COHER_START_DELAY__START_DELAY_COUNT_MASK = 0x0000003F # macro +CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT = 0x3 # macro +CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT = 0x4 # macro +CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT = 0x5 # macro +CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT = 0xf # macro +CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT = 0x12 # macro +CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT = 0x16 # macro +CP_COHER_CNTL__TC_ACTION_ENA__SHIFT = 0x17 # macro +CP_COHER_CNTL__CB_ACTION_ENA__SHIFT = 0x19 # macro +CP_COHER_CNTL__DB_ACTION_ENA__SHIFT = 0x1a # macro +CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT = 0x1b # macro +CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT = 0x1c # macro +CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT = 0x1d # macro +CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT = 0x1e # macro +CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK = 0x00000008 # macro +CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK = 0x00000010 # macro +CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK = 0x00000020 # macro +CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK = 0x00008000 # macro +CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK = 0x00040000 # macro +CP_COHER_CNTL__TCL1_ACTION_ENA_MASK = 0x00400000 # macro +CP_COHER_CNTL__TC_ACTION_ENA_MASK = 0x00800000 # macro +CP_COHER_CNTL__CB_ACTION_ENA_MASK = 0x02000000 # macro +CP_COHER_CNTL__DB_ACTION_ENA_MASK = 0x04000000 # macro +CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK = 0x08000000 # macro +CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK = 0x10000000 # macro +CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK = 0x20000000 # macro +CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK = 0x40000000 # macro +CP_COHER_SIZE__COHER_SIZE_256B__SHIFT = 0x0 # macro +CP_COHER_SIZE__COHER_SIZE_256B_MASK = 0xFFFFFFFF # macro +CP_COHER_BASE__COHER_BASE_256B__SHIFT = 0x0 # macro +CP_COHER_BASE__COHER_BASE_256B_MASK = 0xFFFFFFFF # macro +CP_COHER_STATUS__MEID__SHIFT = 0x18 # macro +CP_COHER_STATUS__STATUS__SHIFT = 0x1f # macro +CP_COHER_STATUS__MEID_MASK = 0x03000000 # macro +CP_COHER_STATUS__STATUS_MASK = 0x80000000 # macro +CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT = 0x0 # macro +CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK = 0xFFFFFFFF # macro +CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT = 0x0 # macro +CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK = 0x0000FFFF # macro +CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT = 0x0 # macro +CP_DMA_ME_DST_ADDR__DST_ADDR_MASK = 0xFFFFFFFF # macro +CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT = 0x0 # macro +CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK = 0x0000FFFF # macro +CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT = 0x0 # macro +CP_DMA_ME_COMMAND__SAS__SHIFT = 0x1a # macro +CP_DMA_ME_COMMAND__DAS__SHIFT = 0x1b # macro +CP_DMA_ME_COMMAND__SAIC__SHIFT = 0x1c # macro +CP_DMA_ME_COMMAND__DAIC__SHIFT = 0x1d # macro +CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT = 0x1e # macro +CP_DMA_ME_COMMAND__DIS_WC__SHIFT = 0x1f # macro +CP_DMA_ME_COMMAND__BYTE_COUNT_MASK = 0x03FFFFFF # macro +CP_DMA_ME_COMMAND__SAS_MASK = 0x04000000 # macro +CP_DMA_ME_COMMAND__DAS_MASK = 0x08000000 # macro +CP_DMA_ME_COMMAND__SAIC_MASK = 0x10000000 # macro +CP_DMA_ME_COMMAND__DAIC_MASK = 0x20000000 # macro +CP_DMA_ME_COMMAND__RAW_WAIT_MASK = 0x40000000 # macro +CP_DMA_ME_COMMAND__DIS_WC_MASK = 0x80000000 # macro +CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT = 0x0 # macro +CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK = 0xFFFFFFFF # macro +CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT = 0x0 # macro +CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK = 0x0000FFFF # macro +CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT = 0x0 # macro +CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK = 0xFFFFFFFF # macro +CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT = 0x0 # macro +CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK = 0x0000FFFF # macro +CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT = 0x0 # macro +CP_DMA_PFP_COMMAND__SAS__SHIFT = 0x1a # macro +CP_DMA_PFP_COMMAND__DAS__SHIFT = 0x1b # macro +CP_DMA_PFP_COMMAND__SAIC__SHIFT = 0x1c # macro +CP_DMA_PFP_COMMAND__DAIC__SHIFT = 0x1d # macro +CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT = 0x1e # macro +CP_DMA_PFP_COMMAND__DIS_WC__SHIFT = 0x1f # macro +CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK = 0x03FFFFFF # macro +CP_DMA_PFP_COMMAND__SAS_MASK = 0x04000000 # macro +CP_DMA_PFP_COMMAND__DAS_MASK = 0x08000000 # macro +CP_DMA_PFP_COMMAND__SAIC_MASK = 0x10000000 # macro +CP_DMA_PFP_COMMAND__DAIC_MASK = 0x20000000 # macro +CP_DMA_PFP_COMMAND__RAW_WAIT_MASK = 0x40000000 # macro +CP_DMA_PFP_COMMAND__DIS_WC_MASK = 0x80000000 # macro +CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT = 0x0 # macro +CP_DMA_CNTL__MIN_AVAILSZ__SHIFT = 0x4 # macro +CP_DMA_CNTL__BUFFER_DEPTH__SHIFT = 0x10 # macro +CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT = 0x1c # macro +CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT = 0x1d # macro +CP_DMA_CNTL__PIO_COUNT__SHIFT = 0x1e # macro +CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK = 0x00000001 # macro +CP_DMA_CNTL__MIN_AVAILSZ_MASK = 0x00000030 # macro +CP_DMA_CNTL__BUFFER_DEPTH_MASK = 0x000F0000 # macro +CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK = 0x10000000 # macro +CP_DMA_CNTL__PIO_FIFO_FULL_MASK = 0x20000000 # macro +CP_DMA_CNTL__PIO_COUNT_MASK = 0xC0000000 # macro +CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT = 0x0 # macro +CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT = 0x1c # macro +CP_DMA_READ_TAGS__DMA_READ_TAG_MASK = 0x03FFFFFF # macro +CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK = 0x10000000 # macro +CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT = 0x0 # macro +CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK = 0x000000FF # macro +CP_PFP_IB_CONTROL__IB_EN__SHIFT = 0x0 # macro +CP_PFP_IB_CONTROL__IB_EN_MASK = 0x000000FF # macro +CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT = 0x0 # macro +CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT = 0x1 # macro +CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT = 0x10 # macro +CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT = 0x18 # macro +CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK = 0x00000001 # macro +CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK = 0x00000002 # macro +CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK = 0x00010000 # macro +CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK = 0x01000000 # macro +CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT = 0x0 # macro +CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK = 0x000000FF # macro +CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT = 0x0 # macro +CP_SCRATCH_DATA__SCRATCH_DATA_MASK = 0xFFFFFFFF # macro +CP_RB_OFFSET__RB_OFFSET__SHIFT = 0x0 # macro +CP_RB_OFFSET__RB_OFFSET_MASK = 0x000FFFFF # macro +CP_IB1_OFFSET__IB1_OFFSET__SHIFT = 0x0 # macro +CP_IB1_OFFSET__IB1_OFFSET_MASK = 0x000FFFFF # macro +CP_IB2_OFFSET__IB2_OFFSET__SHIFT = 0x0 # macro +CP_IB2_OFFSET__IB2_OFFSET_MASK = 0x000FFFFF # macro +CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT = 0x0 # macro +CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK = 0x000FFFFF # macro +CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT = 0x0 # macro +CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK = 0x000FFFFF # macro +CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT = 0x0 # macro +CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK = 0x000FFFFF # macro +CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT = 0x0 # macro +CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK = 0x000FFFFF # macro +CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT = 0x0 # macro +CP_CE_IB1_OFFSET__IB1_OFFSET_MASK = 0x000FFFFF # macro +CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT = 0x0 # macro +CP_CE_IB2_OFFSET__IB2_OFFSET_MASK = 0x000FFFFF # macro +CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT = 0x0 # macro +CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK = 0xFFFFFFFF # macro +CP_CE_RB_OFFSET__RB_OFFSET__SHIFT = 0x0 # macro +CP_CE_RB_OFFSET__RB_OFFSET_MASK = 0x000FFFFF # macro +CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT = 0x0 # macro +CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK = 0x00000FFF # macro +CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT = 0x0 # macro +CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK = 0x000FFFFF # macro +CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT = 0x0 # macro +CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK = 0x000FFFFF # macro +CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT = 0x0 # macro +CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK = 0x000FFFFF # macro +CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT = 0x0 # macro +CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK = 0x000FFFFF # macro +CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT = 0x0 # macro +CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK = 0x000FFFFF # macro +CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT = 0x5 # macro +CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK = 0xFFFFFFE0 # macro +CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT = 0x0 # macro +CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK = 0x0000FFFF # macro +CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT = 0x0 # macro +CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK = 0x00000FFF # macro +CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT = 0x2 # macro +CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK = 0xFFFFFFFC # macro +CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT = 0x0 # macro +CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK = 0x0000FFFF # macro +CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT = 0x0 # macro +CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK = 0x000FFFFF # macro +CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT = 0x2 # macro +CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK = 0xFFFFFFFC # macro +CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT = 0x0 # macro +CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK = 0x0000FFFF # macro +CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT = 0x0 # macro +CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK = 0x000FFFFF # macro +CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT = 0x2 # macro +CP_IB1_BASE_LO__IB1_BASE_LO_MASK = 0xFFFFFFFC # macro +CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT = 0x0 # macro +CP_IB1_BASE_HI__IB1_BASE_HI_MASK = 0x0000FFFF # macro +CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT = 0x0 # macro +CP_IB1_BUFSZ__IB1_BUFSZ_MASK = 0x000FFFFF # macro +CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT = 0x2 # macro +CP_IB2_BASE_LO__IB2_BASE_LO_MASK = 0xFFFFFFFC # macro +CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT = 0x0 # macro +CP_IB2_BASE_HI__IB2_BASE_HI_MASK = 0x0000FFFF # macro +CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT = 0x0 # macro +CP_IB2_BUFSZ__IB2_BUFSZ_MASK = 0x000FFFFF # macro +CP_ST_BASE_LO__ST_BASE_LO__SHIFT = 0x2 # macro +CP_ST_BASE_LO__ST_BASE_LO_MASK = 0xFFFFFFFC # macro +CP_ST_BASE_HI__ST_BASE_HI__SHIFT = 0x0 # macro +CP_ST_BASE_HI__ST_BASE_HI_MASK = 0x0000FFFF # macro +CP_ST_BUFSZ__ST_BUFSZ__SHIFT = 0x0 # macro +CP_ST_BUFSZ__ST_BUFSZ_MASK = 0x000FFFFF # macro +CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT = 0x0 # macro +CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT = 0xc # macro +CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT = 0x19 # macro +CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT = 0x1c # macro +CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK = 0x0000007F # macro +CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK = 0x0003F000 # macro +CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK = 0x02000000 # macro +CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK = 0x10000000 # macro +CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT = 0x10 # macro +CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT = 0x18 # macro +CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT = 0x1d # macro +CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK = 0x00030000 # macro +CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK = 0x07000000 # macro +CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK = 0xE0000000 # macro +CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT = 0x0 # macro +CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK = 0xFFFFFFFF # macro +CP_PFP_COMPLETION_STATUS__STATUS__SHIFT = 0x0 # macro +CP_PFP_COMPLETION_STATUS__STATUS_MASK = 0x00000003 # macro +CP_CE_COMPLETION_STATUS__STATUS__SHIFT = 0x0 # macro +CP_CE_COMPLETION_STATUS__STATUS_MASK = 0x00000003 # macro +CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT = 0x0 # macro +CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK = 0x00000001 # macro +CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT = 0x0 # macro +CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK = 0xFFFFFFFF # macro +CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT = 0x0 # macro +CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK = 0xFFFFFFFF # macro +CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT = 0x0 # macro +CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK = 0xFFFFFFFF # macro +CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT = 0x0 # macro +CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK = 0xFFFFFFFF # macro +CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT = 0x0 # macro +CP_INDEX_BASE_ADDR__ADDR_LO_MASK = 0xFFFFFFFF # macro +CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_INDEX_TYPE__INDEX_TYPE__SHIFT = 0x0 # macro +CP_INDEX_TYPE__INDEX_TYPE_MASK = 0x00000003 # macro +CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT = 0x0 # macro +CP_GDS_BKUP_ADDR__ADDR_LO_MASK = 0xFFFFFFFF # macro +CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT = 0x0 # macro +CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK = 0x0000FFFF # macro +CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT = 0x0 # macro +CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT = 0x1 # macro +CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT = 0x2 # macro +CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT = 0x3 # macro +CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT = 0x4 # macro +CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT = 0x5 # macro +CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT = 0x6 # macro +CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT = 0x7 # macro +CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK = 0x00000001 # macro +CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK = 0x00000002 # macro +CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK = 0x00000004 # macro +CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK = 0x00000008 # macro +CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK = 0x00000010 # macro +CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK = 0x00000020 # macro +CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK = 0x00000040 # macro +CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK = 0x00000080 # macro +CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT = 0x0 # macro +CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT = 0x1 # macro +CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT = 0x6 # macro +CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT = 0x7 # macro +CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT = 0x8 # macro +CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT = 0x9 # macro +CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT = 0xa # macro +CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT = 0xb # macro +CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT = 0xc # macro +CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT = 0xd # macro +CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT = 0xe # macro +CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT = 0x13 # macro +CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT = 0x15 # macro +CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK = 0x00000001 # macro +CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK = 0x00000002 # macro +CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK = 0x00000040 # macro +CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK = 0x00000080 # macro +CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK = 0x00000100 # macro +CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK = 0x00000200 # macro +CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK = 0x00000400 # macro +CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK = 0x00000800 # macro +CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK = 0x00001000 # macro +CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK = 0x00002000 # macro +CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK = 0x00004000 # macro +CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK = 0x00080000 # macro +CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK = 0x00200000 # macro +CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT = 0x0 # macro +CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK = 0xFFFFFFFF # macro +CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT = 0x0 # macro +CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK = 0x000000FF # macro +CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT = 0x0 # macro +CP_ME_COHER_BASE__COHER_BASE_256B_MASK = 0xFFFFFFFF # macro +CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT = 0x0 # macro +CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK = 0x000000FF # macro +CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT = 0x0 # macro +CP_ME_COHER_STATUS__STATUS__SHIFT = 0x1f # macro +CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK = 0x000000FF # macro +CP_ME_COHER_STATUS__STATUS_MASK = 0x80000000 # macro +RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT = 0x0 # macro +RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT = 0x4 # macro +RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT = 0x8 # macro +RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT = 0xc # macro +RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT = 0x10 # macro +RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT = 0x12 # macro +RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT = 0x14 # macro +RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT = 0x15 # macro +RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK = 0x0000000F # macro +RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK = 0x000000F0 # macro +RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK = 0x00000F00 # macro +RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK = 0x0000F000 # macro +RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK = 0x00030000 # macro +RLC_GPM_PERF_COUNT_0__UNUSED_MASK = 0x000C0000 # macro +RLC_GPM_PERF_COUNT_0__ENABLE_MASK = 0x00100000 # macro +RLC_GPM_PERF_COUNT_0__RESERVED_MASK = 0xFFE00000 # macro +RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT = 0x0 # macro +RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT = 0x4 # macro +RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT = 0x8 # macro +RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT = 0xc # macro +RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT = 0x10 # macro +RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT = 0x12 # macro +RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT = 0x14 # macro +RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT = 0x15 # macro +RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK = 0x0000000F # macro +RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK = 0x000000F0 # macro +RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK = 0x00000F00 # macro +RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK = 0x0000F000 # macro +RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK = 0x00030000 # macro +RLC_GPM_PERF_COUNT_1__UNUSED_MASK = 0x000C0000 # macro +RLC_GPM_PERF_COUNT_1__ENABLE_MASK = 0x00100000 # macro +RLC_GPM_PERF_COUNT_1__RESERVED_MASK = 0xFFE00000 # macro +GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT = 0x0 # macro +GRBM_GFX_INDEX__SH_INDEX__SHIFT = 0x8 # macro +GRBM_GFX_INDEX__SE_INDEX__SHIFT = 0x10 # macro +GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT = 0x1d # macro +GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT = 0x1e # macro +GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT = 0x1f # macro +GRBM_GFX_INDEX__INSTANCE_INDEX_MASK = 0x000000FF # macro +GRBM_GFX_INDEX__SH_INDEX_MASK = 0x0000FF00 # macro +GRBM_GFX_INDEX__SE_INDEX_MASK = 0x00FF0000 # macro +GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK = 0x20000000 # macro +GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK = 0x40000000 # macro +GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK = 0x80000000 # macro +VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT = 0x0 # macro +VGT_GSVS_RING_SIZE__MEM_SIZE_MASK = 0xFFFFFFFF # macro +VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT = 0x0 # macro +VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK = 0x0000003F # macro +VGT_INDEX_TYPE__INDEX_TYPE__SHIFT = 0x0 # macro +VGT_INDEX_TYPE__PRIMGEN_EN__SHIFT = 0x8 # macro +VGT_INDEX_TYPE__INDEX_TYPE_MASK = 0x00000003 # macro +VGT_INDEX_TYPE__PRIMGEN_EN_MASK = 0x00000100 # macro +VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT = 0x0 # macro +VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK = 0xFFFFFFFF # macro +VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT = 0x0 # macro +VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK = 0xFFFFFFFF # macro +VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT = 0x0 # macro +VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK = 0xFFFFFFFF # macro +VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT = 0x0 # macro +VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK = 0xFFFFFFFF # macro +VGT_MAX_VTX_INDX__MAX_INDX__SHIFT = 0x0 # macro +VGT_MAX_VTX_INDX__MAX_INDX_MASK = 0xFFFFFFFF # macro +VGT_MIN_VTX_INDX__MIN_INDX__SHIFT = 0x0 # macro +VGT_MIN_VTX_INDX__MIN_INDX_MASK = 0xFFFFFFFF # macro +VGT_INDX_OFFSET__INDX_OFFSET__SHIFT = 0x0 # macro +VGT_INDX_OFFSET__INDX_OFFSET_MASK = 0xFFFFFFFF # macro +VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT = 0x0 # macro +VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT = 0x1 # macro +VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK = 0x00000001 # macro +VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK = 0x00000002 # macro +VGT_NUM_INDICES__NUM_INDICES__SHIFT = 0x0 # macro +VGT_NUM_INDICES__NUM_INDICES_MASK = 0xFFFFFFFF # macro +VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT = 0x0 # macro +VGT_NUM_INSTANCES__NUM_INSTANCES_MASK = 0xFFFFFFFF # macro +VGT_TF_RING_SIZE__SIZE__SHIFT = 0x0 # macro +VGT_TF_RING_SIZE__SIZE_MASK = 0x0000FFFF # macro +VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT = 0x0 # macro +VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT = 0x9 # macro +VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK = 0x000001FF # macro +VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK = 0x00000600 # macro +VGT_TF_MEMORY_BASE__BASE__SHIFT = 0x0 # macro +VGT_TF_MEMORY_BASE__BASE_MASK = 0xFFFFFFFF # macro +VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT = 0x0 # macro +VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK = 0x000000FF # macro +WD_POS_BUF_BASE__BASE__SHIFT = 0x0 # macro +WD_POS_BUF_BASE__BASE_MASK = 0xFFFFFFFF # macro +WD_POS_BUF_BASE_HI__BASE_HI__SHIFT = 0x0 # macro +WD_POS_BUF_BASE_HI__BASE_HI_MASK = 0x000000FF # macro +WD_CNTL_SB_BUF_BASE__BASE__SHIFT = 0x0 # macro +WD_CNTL_SB_BUF_BASE__BASE_MASK = 0xFFFFFFFF # macro +WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT = 0x0 # macro +WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK = 0x000000FF # macro +WD_INDEX_BUF_BASE__BASE__SHIFT = 0x0 # macro +WD_INDEX_BUF_BASE__BASE_MASK = 0xFFFFFFFF # macro +WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT = 0x0 # macro +WD_INDEX_BUF_BASE_HI__BASE_HI_MASK = 0x000000FF # macro +IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT = 0x0 # macro +IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT = 0x10 # macro +IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT = 0x11 # macro +IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT = 0x12 # macro +IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT = 0x13 # macro +IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT = 0x14 # macro +IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC__SHIFT = 0x15 # macro +IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV__SHIFT = 0x16 # macro +IA_MULTI_VGT_PARAM__HW_USE_ONLY__SHIFT = 0x17 # macro +IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK = 0x0000FFFF # macro +IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK = 0x00010000 # macro +IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK = 0x00020000 # macro +IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK = 0x00040000 # macro +IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK = 0x00080000 # macro +IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK = 0x00100000 # macro +IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK = 0x00200000 # macro +IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK = 0x00400000 # macro +IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK = 0x00800000 # macro +VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT = 0x0 # macro +VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK = 0xFFFFFFFF # macro +PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT = 0x0 # macro +PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK = 0x00FFFFFF # macro +PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT = 0x0 # macro +PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT = 0x8 # macro +PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK = 0x0000000F # macro +PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK = 0x0000FF00 # macro +PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT = 0x0 # macro +PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT = 0x10 # macro +PA_SC_SCREEN_EXTENT_MIN_0__X_MASK = 0x0000FFFF # macro +PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK = 0xFFFF0000 # macro +PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT = 0x0 # macro +PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT = 0x10 # macro +PA_SC_SCREEN_EXTENT_MAX_0__X_MASK = 0x0000FFFF # macro +PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK = 0xFFFF0000 # macro +PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT = 0x0 # macro +PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT = 0x10 # macro +PA_SC_SCREEN_EXTENT_MIN_1__X_MASK = 0x0000FFFF # macro +PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK = 0xFFFF0000 # macro +PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT = 0x0 # macro +PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT = 0x10 # macro +PA_SC_SCREEN_EXTENT_MAX_1__X_MASK = 0x0000FFFF # macro +PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK = 0xFFFF0000 # macro +PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT = 0x0 # macro +PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT = 0x1 # macro +PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK = 0x00000001 # macro +PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK = 0x00000002 # macro +PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT = 0x0 # macro +PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK = 0x00003FFF # macro +PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT = 0x0 # macro +PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK = 0x00003FFF # macro +PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT = 0x0 # macro +PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK = 0x0000FFFF # macro +PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT = 0x0 # macro +PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK = 0x0000FFFF # macro +PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT = 0x0 # macro +PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT = 0x1 # macro +PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK = 0x00000001 # macro +PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK = 0x00000002 # macro +PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT = 0x0 # macro +PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK = 0x00003FFF # macro +PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT = 0x0 # macro +PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK = 0x00003FFF # macro +PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT = 0x0 # macro +PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK = 0x0000FFFF # macro +PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT = 0x0 # macro +PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK = 0x0000FFFF # macro +PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT = 0x0 # macro +PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT = 0x1 # macro +PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK = 0x00000001 # macro +PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK = 0x00000002 # macro +PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT = 0x0 # macro +PA_SC_TRAP_SCREEN_H__X_COORD_MASK = 0x00003FFF # macro +PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT = 0x0 # macro +PA_SC_TRAP_SCREEN_V__Y_COORD_MASK = 0x00003FFF # macro +PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT = 0x0 # macro +PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK = 0x0000FFFF # macro +PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT = 0x0 # macro +PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK = 0x0000FFFF # macro +PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT = 0x0 # macro +PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK = 0xFFFFFFFF # macro +SQ_THREAD_TRACE_BASE__ADDR__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_BASE__ADDR_MASK = 0xFFFFFFFF # macro +SQ_THREAD_TRACE_SIZE__SIZE__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_SIZE__SIZE_MASK = 0x003FFFFF # macro +SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT = 0x5 # macro +SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT = 0x7 # macro +SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT = 0x8 # macro +SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT = 0xc # macro +SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT = 0xe # macro +SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT = 0xf # macro +SQ_THREAD_TRACE_MASK__CU_SEL_MASK = 0x0000001F # macro +SQ_THREAD_TRACE_MASK__SH_SEL_MASK = 0x00000020 # macro +SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK = 0x00000080 # macro +SQ_THREAD_TRACE_MASK__SIMD_EN_MASK = 0x00000F00 # macro +SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK = 0x00003000 # macro +SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK = 0x00004000 # macro +SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK = 0x00008000 # macro +SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT = 0x10 # macro +SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT = 0x18 # macro +SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK = 0x0000FFFF # macro +SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK = 0x00FF0000 # macro +SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK = 0x01000000 # macro +SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT = 0x10 # macro +SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK = 0x0000FFFF # macro +SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK = 0xFFFF0000 # macro +SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT = 0x1f # macro +SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK = 0x80000000 # macro +SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT = 0x3 # macro +SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT = 0x6 # macro +SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT = 0x9 # macro +SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT = 0xc # macro +SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT = 0xf # macro +SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT = 0x12 # macro +SQ_THREAD_TRACE_MODE__MODE__SHIFT = 0x15 # macro +SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT = 0x17 # macro +SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT = 0x19 # macro +SQ_THREAD_TRACE_MODE__TC_PERF_EN__SHIFT = 0x1a # macro +SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT = 0x1b # macro +SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT = 0x1d # macro +SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT = 0x1e # macro +SQ_THREAD_TRACE_MODE__WRAP__SHIFT = 0x1f # macro +SQ_THREAD_TRACE_MODE__MASK_PS_MASK = 0x00000007 # macro +SQ_THREAD_TRACE_MODE__MASK_VS_MASK = 0x00000038 # macro +SQ_THREAD_TRACE_MODE__MASK_GS_MASK = 0x000001C0 # macro +SQ_THREAD_TRACE_MODE__MASK_ES_MASK = 0x00000E00 # macro +SQ_THREAD_TRACE_MODE__MASK_HS_MASK = 0x00007000 # macro +SQ_THREAD_TRACE_MODE__MASK_LS_MASK = 0x00038000 # macro +SQ_THREAD_TRACE_MODE__MASK_CS_MASK = 0x001C0000 # macro +SQ_THREAD_TRACE_MODE__MODE_MASK = 0x00600000 # macro +SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK = 0x01800000 # macro +SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK = 0x02000000 # macro +SQ_THREAD_TRACE_MODE__TC_PERF_EN_MASK = 0x04000000 # macro +SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK = 0x18000000 # macro +SQ_THREAD_TRACE_MODE__TEST_MODE_MASK = 0x20000000 # macro +SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK = 0x40000000 # macro +SQ_THREAD_TRACE_MODE__WRAP_MASK = 0x80000000 # macro +SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK = 0x0000000F # macro +SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK = 0xFFFFFFFF # macro +SQ_THREAD_TRACE_WPTR__WPTR__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT = 0x1e # macro +SQ_THREAD_TRACE_WPTR__WPTR_MASK = 0x3FFFFFFF # macro +SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK = 0xC0000000 # macro +SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT = 0x10 # macro +SQ_THREAD_TRACE_STATUS__UTC_ERROR__SHIFT = 0x1c # macro +SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT = 0x1d # macro +SQ_THREAD_TRACE_STATUS__BUSY__SHIFT = 0x1e # macro +SQ_THREAD_TRACE_STATUS__FULL__SHIFT = 0x1f # macro +SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK = 0x000003FF # macro +SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK = 0x03FF0000 # macro +SQ_THREAD_TRACE_STATUS__UTC_ERROR_MASK = 0x10000000 # macro +SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK = 0x20000000 # macro +SQ_THREAD_TRACE_STATUS__BUSY_MASK = 0x40000000 # macro +SQ_THREAD_TRACE_STATUS__FULL_MASK = 0x80000000 # macro +SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_HIWATER__HIWATER_MASK = 0x00000007 # macro +SQ_THREAD_TRACE_CNTR__CNTR__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_CNTR__CNTR_MASK = 0xFFFFFFFF # macro +SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_USERDATA_0__DATA_MASK = 0xFFFFFFFF # macro +SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_USERDATA_1__DATA_MASK = 0xFFFFFFFF # macro +SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_USERDATA_2__DATA_MASK = 0xFFFFFFFF # macro +SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT = 0x0 # macro +SQ_THREAD_TRACE_USERDATA_3__DATA_MASK = 0xFFFFFFFF # macro +SQC_CACHES__TARGET_INST__SHIFT = 0x0 # macro +SQC_CACHES__TARGET_DATA__SHIFT = 0x1 # macro +SQC_CACHES__INVALIDATE__SHIFT = 0x2 # macro +SQC_CACHES__WRITEBACK__SHIFT = 0x3 # macro +SQC_CACHES__VOL__SHIFT = 0x4 # macro +SQC_CACHES__COMPLETE__SHIFT = 0x10 # macro +SQC_CACHES__TARGET_INST_MASK = 0x00000001 # macro +SQC_CACHES__TARGET_DATA_MASK = 0x00000002 # macro +SQC_CACHES__INVALIDATE_MASK = 0x00000004 # macro +SQC_CACHES__WRITEBACK_MASK = 0x00000008 # macro +SQC_CACHES__VOL_MASK = 0x00000010 # macro +SQC_CACHES__COMPLETE_MASK = 0x00010000 # macro +SQC_WRITEBACK__DWB__SHIFT = 0x0 # macro +SQC_WRITEBACK__DIRTY__SHIFT = 0x1 # macro +SQC_WRITEBACK__DWB_MASK = 0x00000001 # macro +SQC_WRITEBACK__DIRTY_MASK = 0x00000002 # macro +DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT = 0x0 # macro +DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK = 0xFFFFFFFF # macro +DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT = 0x0 # macro +DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK = 0x7FFFFFFF # macro +DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT = 0x0 # macro +DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK = 0xFFFFFFFF # macro +DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT = 0x0 # macro +DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK = 0x7FFFFFFF # macro +DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT = 0x0 # macro +DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK = 0xFFFFFFFF # macro +DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT = 0x0 # macro +DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK = 0x7FFFFFFF # macro +DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT = 0x0 # macro +DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK = 0xFFFFFFFF # macro +DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT = 0x0 # macro +DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK = 0x7FFFFFFF # macro +DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT = 0x0 # macro +DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK = 0xFFFFFFFF # macro +DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT = 0x0 # macro +DB_ZPASS_COUNT_HI__COUNT_HI_MASK = 0x7FFFFFFF # macro +GDS_RD_ADDR__READ_ADDR__SHIFT = 0x0 # macro +GDS_RD_ADDR__READ_ADDR_MASK = 0xFFFFFFFF # macro +GDS_RD_DATA__READ_DATA__SHIFT = 0x0 # macro +GDS_RD_DATA__READ_DATA_MASK = 0xFFFFFFFF # macro +GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT = 0x0 # macro +GDS_RD_BURST_ADDR__BURST_ADDR_MASK = 0xFFFFFFFF # macro +GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT = 0x0 # macro +GDS_RD_BURST_COUNT__BURST_COUNT_MASK = 0xFFFFFFFF # macro +GDS_RD_BURST_DATA__BURST_DATA__SHIFT = 0x0 # macro +GDS_RD_BURST_DATA__BURST_DATA_MASK = 0xFFFFFFFF # macro +GDS_WR_ADDR__WRITE_ADDR__SHIFT = 0x0 # macro +GDS_WR_ADDR__WRITE_ADDR_MASK = 0xFFFFFFFF # macro +GDS_WR_DATA__WRITE_DATA__SHIFT = 0x0 # macro +GDS_WR_DATA__WRITE_DATA_MASK = 0xFFFFFFFF # macro +GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT = 0x0 # macro +GDS_WR_BURST_ADDR__WRITE_ADDR_MASK = 0xFFFFFFFF # macro +GDS_WR_BURST_DATA__WRITE_DATA__SHIFT = 0x0 # macro +GDS_WR_BURST_DATA__WRITE_DATA_MASK = 0xFFFFFFFF # macro +GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT = 0x0 # macro +GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK = 0xFFFFFFFF # macro +GDS_ATOM_CNTL__AINC__SHIFT = 0x0 # macro +GDS_ATOM_CNTL__UNUSED1__SHIFT = 0x6 # macro +GDS_ATOM_CNTL__DMODE__SHIFT = 0x8 # macro +GDS_ATOM_CNTL__UNUSED2__SHIFT = 0xa # macro +GDS_ATOM_CNTL__AINC_MASK = 0x0000003F # macro +GDS_ATOM_CNTL__UNUSED1_MASK = 0x000000C0 # macro +GDS_ATOM_CNTL__DMODE_MASK = 0x00000300 # macro +GDS_ATOM_CNTL__UNUSED2_MASK = 0xFFFFFC00 # macro +GDS_ATOM_COMPLETE__COMPLETE__SHIFT = 0x0 # macro +GDS_ATOM_COMPLETE__UNUSED__SHIFT = 0x1 # macro +GDS_ATOM_COMPLETE__COMPLETE_MASK = 0x00000001 # macro +GDS_ATOM_COMPLETE__UNUSED_MASK = 0xFFFFFFFE # macro +GDS_ATOM_BASE__BASE__SHIFT = 0x0 # macro +GDS_ATOM_BASE__UNUSED__SHIFT = 0x10 # macro +GDS_ATOM_BASE__BASE_MASK = 0x0000FFFF # macro +GDS_ATOM_BASE__UNUSED_MASK = 0xFFFF0000 # macro +GDS_ATOM_SIZE__SIZE__SHIFT = 0x0 # macro +GDS_ATOM_SIZE__UNUSED__SHIFT = 0x10 # macro +GDS_ATOM_SIZE__SIZE_MASK = 0x0000FFFF # macro +GDS_ATOM_SIZE__UNUSED_MASK = 0xFFFF0000 # macro +GDS_ATOM_OFFSET0__OFFSET0__SHIFT = 0x0 # macro +GDS_ATOM_OFFSET0__UNUSED__SHIFT = 0x8 # macro +GDS_ATOM_OFFSET0__OFFSET0_MASK = 0x000000FF # macro +GDS_ATOM_OFFSET0__UNUSED_MASK = 0xFFFFFF00 # macro +GDS_ATOM_OFFSET1__OFFSET1__SHIFT = 0x0 # macro +GDS_ATOM_OFFSET1__UNUSED__SHIFT = 0x8 # macro +GDS_ATOM_OFFSET1__OFFSET1_MASK = 0x000000FF # macro +GDS_ATOM_OFFSET1__UNUSED_MASK = 0xFFFFFF00 # macro +GDS_ATOM_DST__DST__SHIFT = 0x0 # macro +GDS_ATOM_DST__DST_MASK = 0xFFFFFFFF # macro +GDS_ATOM_OP__OP__SHIFT = 0x0 # macro +GDS_ATOM_OP__UNUSED__SHIFT = 0x8 # macro +GDS_ATOM_OP__OP_MASK = 0x000000FF # macro +GDS_ATOM_OP__UNUSED_MASK = 0xFFFFFF00 # macro +GDS_ATOM_SRC0__DATA__SHIFT = 0x0 # macro +GDS_ATOM_SRC0__DATA_MASK = 0xFFFFFFFF # macro +GDS_ATOM_SRC0_U__DATA__SHIFT = 0x0 # macro +GDS_ATOM_SRC0_U__DATA_MASK = 0xFFFFFFFF # macro +GDS_ATOM_SRC1__DATA__SHIFT = 0x0 # macro +GDS_ATOM_SRC1__DATA_MASK = 0xFFFFFFFF # macro +GDS_ATOM_SRC1_U__DATA__SHIFT = 0x0 # macro +GDS_ATOM_SRC1_U__DATA_MASK = 0xFFFFFFFF # macro +GDS_ATOM_READ0__DATA__SHIFT = 0x0 # macro +GDS_ATOM_READ0__DATA_MASK = 0xFFFFFFFF # macro +GDS_ATOM_READ0_U__DATA__SHIFT = 0x0 # macro +GDS_ATOM_READ0_U__DATA_MASK = 0xFFFFFFFF # macro +GDS_ATOM_READ1__DATA__SHIFT = 0x0 # macro +GDS_ATOM_READ1__DATA_MASK = 0xFFFFFFFF # macro +GDS_ATOM_READ1_U__DATA__SHIFT = 0x0 # macro +GDS_ATOM_READ1_U__DATA_MASK = 0xFFFFFFFF # macro +GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT = 0x0 # macro +GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT = 0x6 # macro +GDS_GWS_RESOURCE_CNTL__INDEX_MASK = 0x0000003F # macro +GDS_GWS_RESOURCE_CNTL__UNUSED_MASK = 0xFFFFFFC0 # macro +GDS_GWS_RESOURCE__FLAG__SHIFT = 0x0 # macro +GDS_GWS_RESOURCE__COUNTER__SHIFT = 0x1 # macro +GDS_GWS_RESOURCE__TYPE__SHIFT = 0xe # macro +GDS_GWS_RESOURCE__DED__SHIFT = 0xf # macro +GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT = 0x10 # macro +GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT = 0x11 # macro +GDS_GWS_RESOURCE__HEAD_VALID__SHIFT = 0x1d # macro +GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT = 0x1e # macro +GDS_GWS_RESOURCE__HALTED__SHIFT = 0x1f # macro +GDS_GWS_RESOURCE__FLAG_MASK = 0x00000001 # macro +GDS_GWS_RESOURCE__COUNTER_MASK = 0x00003FFE # macro +GDS_GWS_RESOURCE__TYPE_MASK = 0x00004000 # macro +GDS_GWS_RESOURCE__DED_MASK = 0x00008000 # macro +GDS_GWS_RESOURCE__RELEASE_ALL_MASK = 0x00010000 # macro +GDS_GWS_RESOURCE__HEAD_QUEUE_MASK = 0x1FFE0000 # macro +GDS_GWS_RESOURCE__HEAD_VALID_MASK = 0x20000000 # macro +GDS_GWS_RESOURCE__HEAD_FLAG_MASK = 0x40000000 # macro +GDS_GWS_RESOURCE__HALTED_MASK = 0x80000000 # macro +GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT = 0x0 # macro +GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT = 0x10 # macro +GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK = 0x0000FFFF # macro +GDS_GWS_RESOURCE_CNT__UNUSED_MASK = 0xFFFF0000 # macro +GDS_OA_CNTL__INDEX__SHIFT = 0x0 # macro +GDS_OA_CNTL__UNUSED__SHIFT = 0x4 # macro +GDS_OA_CNTL__INDEX_MASK = 0x0000000F # macro +GDS_OA_CNTL__UNUSED_MASK = 0xFFFFFFF0 # macro +GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT = 0x0 # macro +GDS_OA_COUNTER__SPACE_AVAILABLE_MASK = 0xFFFFFFFF # macro +GDS_OA_ADDRESS__DS_ADDRESS__SHIFT = 0x0 # macro +GDS_OA_ADDRESS__CRAWLER__SHIFT = 0x10 # macro +GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT = 0x14 # macro +GDS_OA_ADDRESS__UNUSED__SHIFT = 0x16 # macro +GDS_OA_ADDRESS__NO_ALLOC__SHIFT = 0x1e # macro +GDS_OA_ADDRESS__ENABLE__SHIFT = 0x1f # macro +GDS_OA_ADDRESS__DS_ADDRESS_MASK = 0x0000FFFF # macro +GDS_OA_ADDRESS__CRAWLER_MASK = 0x000F0000 # macro +GDS_OA_ADDRESS__CRAWLER_TYPE_MASK = 0x00300000 # macro +GDS_OA_ADDRESS__UNUSED_MASK = 0x3FC00000 # macro +GDS_OA_ADDRESS__NO_ALLOC_MASK = 0x40000000 # macro +GDS_OA_ADDRESS__ENABLE_MASK = 0x80000000 # macro +GDS_OA_INCDEC__VALUE__SHIFT = 0x0 # macro +GDS_OA_INCDEC__INCDEC__SHIFT = 0x1f # macro +GDS_OA_INCDEC__VALUE_MASK = 0x7FFFFFFF # macro +GDS_OA_INCDEC__INCDEC_MASK = 0x80000000 # macro +GDS_OA_RING_SIZE__RING_SIZE__SHIFT = 0x0 # macro +GDS_OA_RING_SIZE__RING_SIZE_MASK = 0xFFFFFFFF # macro +SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT = 0x0 # macro +SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT = 0x15 # macro +SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT = 0x18 # macro +SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT = 0x19 # macro +SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT = 0x1a # macro +SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT = 0x1b # macro +SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT = 0x1c # macro +SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT = 0x1d # macro +SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT = 0x1e # macro +SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK = 0x001FFFFF # macro +SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK = 0x00E00000 # macro +SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK = 0x01000000 # macro +SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK = 0x02000000 # macro +SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK = 0x04000000 # macro +SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK = 0x08000000 # macro +SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK = 0x10000000 # macro +SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK = 0x20000000 # macro +SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK = 0xC0000000 # macro +SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT = 0x0 # macro +SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT = 0x4 # macro +SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE__SHIFT = 0x5 # macro +SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT = 0x6 # macro +SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT = 0x7 # macro +SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT = 0x8 # macro +SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT = 0x9 # macro +SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT = 0xa # macro +SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT = 0xe # macro +SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT = 0xf # macro +SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT = 0x10 # macro +SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK = 0x0000000F # macro +SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK = 0x00000010 # macro +SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE_MASK = 0x00000020 # macro +SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK = 0x00000040 # macro +SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK = 0x00000080 # macro +SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK = 0x00000100 # macro +SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK = 0x00000200 # macro +SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK = 0x00003C00 # macro +SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK = 0x00004000 # macro +SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK = 0x00008000 # macro +SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK = 0xFFFF0000 # macro +SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT = 0x0 # macro +SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT = 0x4 # macro +SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK = 0x0000000F # macro +SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK = 0x000000F0 # macro +SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN__SHIFT = 0x0 # macro +SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN__SHIFT = 0x2 # macro +SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN__SHIFT = 0x4 # macro +SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN__SHIFT = 0x6 # macro +SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN_MASK = 0x00000003 # macro +SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN_MASK = 0x0000000C # macro +SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN_MASK = 0x00000030 # macro +SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN_MASK = 0x000000C0 # macro +GC_CANE_ERR_STATUS__SDPM_RDRSP_STATUS__SHIFT = 0x0 # macro +GC_CANE_ERR_STATUS__SDPM_WRRSP_STATUS__SHIFT = 0x4 # macro +GC_CANE_ERR_STATUS__SDPM_RDRSP_DATASTATUS__SHIFT = 0x8 # macro +GC_CANE_ERR_STATUS__SDPM_RDRSP_DATAPARITY_ERROR__SHIFT = 0xa # macro +GC_CANE_ERR_STATUS__SDPS_DAT_ERROR__SHIFT = 0xb # macro +GC_CANE_ERR_STATUS__SDPS_DAT_PARITY_ERROR__SHIFT = 0xc # macro +GC_CANE_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT = 0xd # macro +GC_CANE_ERR_STATUS__BUSY_ON_ERROR__SHIFT = 0xe # macro +GC_CANE_ERR_STATUS__BUSY_ON_UER_ERROR__SHIFT = 0xf # macro +GC_CANE_ERR_STATUS__FUE_FLAG__SHIFT = 0x10 # macro +GC_CANE_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT = 0x11 # macro +GC_CANE_ERR_STATUS__LEVEL_INTERRUPT__SHIFT = 0x12 # macro +GC_CANE_ERR_STATUS__SDPM_RDRSP_STATUS_MASK = 0x0000000F # macro +GC_CANE_ERR_STATUS__SDPM_WRRSP_STATUS_MASK = 0x000000F0 # macro +GC_CANE_ERR_STATUS__SDPM_RDRSP_DATASTATUS_MASK = 0x00000300 # macro +GC_CANE_ERR_STATUS__SDPM_RDRSP_DATAPARITY_ERROR_MASK = 0x00000400 # macro +GC_CANE_ERR_STATUS__SDPS_DAT_ERROR_MASK = 0x00000800 # macro +GC_CANE_ERR_STATUS__SDPS_DAT_PARITY_ERROR_MASK = 0x00001000 # macro +GC_CANE_ERR_STATUS__CLEAR_ERROR_STATUS_MASK = 0x00002000 # macro +GC_CANE_ERR_STATUS__BUSY_ON_ERROR_MASK = 0x00004000 # macro +GC_CANE_ERR_STATUS__BUSY_ON_UER_ERROR_MASK = 0x00008000 # macro +GC_CANE_ERR_STATUS__FUE_FLAG_MASK = 0x00010000 # macro +GC_CANE_ERR_STATUS__INTERRUPT_ON_FATAL_MASK = 0x00020000 # macro +GC_CANE_ERR_STATUS__LEVEL_INTERRUPT_MASK = 0x00040000 # macro +GC_CANE_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +GC_CANE_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +GC_CANE_UE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +GC_CANE_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +GC_CANE_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +GC_CANE_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +GC_CANE_UE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +GC_CANE_UE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +GC_CANE_UE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +GC_CANE_UE_ERR_STATUS_HI__PARITY__SHIFT = 0x1 # macro +GC_CANE_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +GC_CANE_UE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +GC_CANE_UE_ERR_STATUS_HI__UE_CNT__SHIFT = 0x17 # macro +GC_CANE_UE_ERR_STATUS_HI__FED_CNT__SHIFT = 0x1a # macro +GC_CANE_UE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +GC_CANE_UE_ERR_STATUS_HI__PARITY_MASK = 0x00000002 # macro +GC_CANE_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +GC_CANE_UE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +GC_CANE_UE_ERR_STATUS_HI__UE_CNT_MASK = 0x03800000 # macro +GC_CANE_UE_ERR_STATUS_HI__FED_CNT_MASK = 0x1C000000 # macro +GC_CANE_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +GC_CANE_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +GC_CANE_CE_ERR_STATUS_LO__ADDRESS__SHIFT = 0x2 # macro +GC_CANE_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT = 0x18 # macro +GC_CANE_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +GC_CANE_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +GC_CANE_CE_ERR_STATUS_LO__ADDRESS_MASK = 0x00FFFFFC # macro +GC_CANE_CE_ERR_STATUS_LO__MEMORY_ID_MASK = 0xFF000000 # macro +GC_CANE_CE_ERR_STATUS_HI__ECC__SHIFT = 0x0 # macro +GC_CANE_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +GC_CANE_CE_ERR_STATUS_HI__ERR_INFO__SHIFT = 0x3 # macro +GC_CANE_CE_ERR_STATUS_HI__CE_CNT__SHIFT = 0x17 # macro +GC_CANE_CE_ERR_STATUS_HI__POISON__SHIFT = 0x1a # macro +GC_CANE_CE_ERR_STATUS_HI__ECC_MASK = 0x00000001 # macro +GC_CANE_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +GC_CANE_CE_ERR_STATUS_HI__ERR_INFO_MASK = 0x007FFFF8 # macro +GC_CANE_CE_ERR_STATUS_HI__CE_CNT_MASK = 0x03800000 # macro +GC_CANE_CE_ERR_STATUS_HI__POISON_MASK = 0x04000000 # macro +CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CPF_LATENCY_STATS_DATA__DATA__SHIFT = 0x0 # macro +CPF_LATENCY_STATS_DATA__DATA_MASK = 0xFFFFFFFF # macro +CPG_LATENCY_STATS_DATA__DATA__SHIFT = 0x0 # macro +CPG_LATENCY_STATS_DATA__DATA_MASK = 0xFFFFFFFF # macro +CPC_LATENCY_STATS_DATA__DATA__SHIFT = 0x0 # macro +CPC_LATENCY_STATS_DATA__DATA_MASK = 0xFFFFFFFF # macro +GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0x0000FFFF # macro +PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0x0000FFFF # macro +PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0x0000FFFF # macro +PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0x0000FFFF # macro +PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT = 0x0 # macro +RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK = 0xFFFFFFFF # macro +RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT = 0x0 # macro +RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK = 0xFFFFFFFF # macro +ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +L2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +L2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +L2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +L2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +L2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +L2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +CPG_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT = 0x0 # macro +CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT = 0xa # macro +CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT = 0x14 # macro +CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT = 0x18 # macro +CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT = 0x1c # macro +CPG_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK = 0x000003FF # macro +CPG_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK = 0x000FFC00 # macro +CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK = 0x0F000000 # macro +CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK = 0xF0000000 # macro +CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT = 0x0 # macro +CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT = 0xa # macro +CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT = 0x18 # macro +CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT = 0x1c # macro +CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK = 0x000003FF # macro +CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK = 0x000FFC00 # macro +CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK = 0x0F000000 # macro +CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK = 0xF0000000 # macro +CPG_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT = 0x0 # macro +CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT = 0xa # macro +CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT = 0x14 # macro +CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT = 0x18 # macro +CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT = 0x1c # macro +CPG_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK = 0x000003FF # macro +CPG_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK = 0x000FFC00 # macro +CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK = 0x0F000000 # macro +CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK = 0xF0000000 # macro +CPC_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT = 0x0 # macro +CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT = 0x14 # macro +CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT = 0x1c # macro +CPC_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK = 0x000003FF # macro +CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK = 0xF0000000 # macro +CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT = 0x0 # macro +CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT = 0xa # macro +CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT = 0x18 # macro +CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT = 0x1c # macro +CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK = 0x000003FF # macro +CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK = 0x000FFC00 # macro +CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK = 0x0F000000 # macro +CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK = 0xF0000000 # macro +CPF_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT = 0x0 # macro +CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT = 0xa # macro +CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT = 0x14 # macro +CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT = 0x18 # macro +CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT = 0x1c # macro +CPF_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK = 0x000003FF # macro +CPF_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK = 0x000FFC00 # macro +CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK = 0x0F000000 # macro +CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK = 0xF0000000 # macro +CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT = 0x0 # macro +CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT = 0xa # macro +CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT = 0x18 # macro +CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT = 0x1c # macro +CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK = 0x000003FF # macro +CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK = 0x000FFC00 # macro +CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK = 0x0F000000 # macro +CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK = 0xF0000000 # macro +CPF_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT = 0x0 # macro +CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT = 0xa # macro +CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT = 0x14 # macro +CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT = 0x18 # macro +CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT = 0x1c # macro +CPF_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK = 0x000003FF # macro +CPF_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK = 0x000FFC00 # macro +CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK = 0x0F000000 # macro +CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK = 0xF0000000 # macro +CP_PERFMON_CNTL__PERFMON_STATE__SHIFT = 0x0 # macro +CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT = 0x4 # macro +CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT = 0x8 # macro +CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT = 0xa # macro +CP_PERFMON_CNTL__PERFMON_STATE_MASK = 0x0000000F # macro +CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK = 0x000000F0 # macro +CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK = 0x00000300 # macro +CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK = 0x00000400 # macro +CPC_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT = 0x0 # macro +CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT = 0xa # macro +CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT = 0x14 # macro +CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT = 0x18 # macro +CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT = 0x1c # macro +CPC_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK = 0x000003FF # macro +CPC_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK = 0x000FFC00 # macro +CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK = 0x0F000000 # macro +CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK = 0xF0000000 # macro +CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT = 0x0 # macro +CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT = 0x1e # macro +CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT = 0x1f # macro +CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK = 0x00000007 # macro +CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK = 0x40000000 # macro +CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK = 0x80000000 # macro +CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT = 0x0 # macro +CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT = 0x1e # macro +CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT = 0x1f # macro +CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK = 0x0000001F # macro +CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK = 0x40000000 # macro +CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK = 0x80000000 # macro +CPF_LATENCY_STATS_SELECT__INDEX__SHIFT = 0x0 # macro +CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT = 0x1e # macro +CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT = 0x1f # macro +CPF_LATENCY_STATS_SELECT__INDEX_MASK = 0x0000000F # macro +CPF_LATENCY_STATS_SELECT__CLEAR_MASK = 0x40000000 # macro +CPF_LATENCY_STATS_SELECT__ENABLE_MASK = 0x80000000 # macro +CPG_LATENCY_STATS_SELECT__INDEX__SHIFT = 0x0 # macro +CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT = 0x1e # macro +CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT = 0x1f # macro +CPG_LATENCY_STATS_SELECT__INDEX_MASK = 0x0000001F # macro +CPG_LATENCY_STATS_SELECT__CLEAR_MASK = 0x40000000 # macro +CPG_LATENCY_STATS_SELECT__ENABLE_MASK = 0x80000000 # macro +CPC_LATENCY_STATS_SELECT__INDEX__SHIFT = 0x0 # macro +CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT = 0x1e # macro +CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT = 0x1f # macro +CPC_LATENCY_STATS_SELECT__INDEX_MASK = 0x00000007 # macro +CPC_LATENCY_STATS_SELECT__CLEAR_MASK = 0x40000000 # macro +CPC_LATENCY_STATS_SELECT__ENABLE_MASK = 0x80000000 # macro +CP_DRAW_OBJECT__OBJECT__SHIFT = 0x0 # macro +CP_DRAW_OBJECT__OBJECT_MASK = 0xFFFFFFFF # macro +CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT = 0x0 # macro +CP_DRAW_OBJECT_COUNTER__COUNT_MASK = 0x0000FFFF # macro +CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT = 0x0 # macro +CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK = 0xFFFFFFFF # macro +CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT = 0x0 # macro +CP_DRAW_WINDOW_HI__WINDOW_HI_MASK = 0xFFFFFFFF # macro +CP_DRAW_WINDOW_LO__MIN__SHIFT = 0x0 # macro +CP_DRAW_WINDOW_LO__MAX__SHIFT = 0x10 # macro +CP_DRAW_WINDOW_LO__MIN_MASK = 0x0000FFFF # macro +CP_DRAW_WINDOW_LO__MAX_MASK = 0xFFFF0000 # macro +CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT = 0x0 # macro +CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT = 0x1 # macro +CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT = 0x2 # macro +CP_DRAW_WINDOW_CNTL__MODE__SHIFT = 0x8 # macro +CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK = 0x00000001 # macro +CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK = 0x00000002 # macro +CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK = 0x00000004 # macro +CP_DRAW_WINDOW_CNTL__MODE_MASK = 0x00000100 # macro +GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xa # macro +GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xb # macro +GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT = 0xc # macro +GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT = 0xd # macro +GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT = 0xe # macro +GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT = 0x10 # macro +GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT = 0x11 # macro +GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT = 0x12 # macro +GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT = 0x13 # macro +GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT = 0x14 # macro +GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT = 0x15 # macro +GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT = 0x16 # macro +GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT = 0x17 # macro +GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT = 0x18 # macro +GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT = 0x19 # macro +GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT = 0x1a # macro +GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT = 0x1b # macro +GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT = 0x1c # macro +GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT = 0x1d # macro +GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT = 0x1e # macro +GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT = 0x1f # macro +GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x0000003F # macro +GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000400 # macro +GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000800 # macro +GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK = 0x00001000 # macro +GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK = 0x00002000 # macro +GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK = 0x00004000 # macro +GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK = 0x00010000 # macro +GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK = 0x00020000 # macro +GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK = 0x00040000 # macro +GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK = 0x00080000 # macro +GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK = 0x00100000 # macro +GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK = 0x00200000 # macro +GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK = 0x00400000 # macro +GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK = 0x00800000 # macro +GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK = 0x01000000 # macro +GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK = 0x02000000 # macro +GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK = 0x04000000 # macro +GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK = 0x08000000 # macro +GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK = 0x10000000 # macro +GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK = 0x20000000 # macro +GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK = 0x40000000 # macro +GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK = 0x80000000 # macro +GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xa # macro +GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xb # macro +GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT = 0xc # macro +GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT = 0xd # macro +GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT = 0xe # macro +GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT = 0x10 # macro +GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT = 0x11 # macro +GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT = 0x12 # macro +GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT = 0x13 # macro +GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT = 0x14 # macro +GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT = 0x15 # macro +GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT = 0x16 # macro +GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT = 0x17 # macro +GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT = 0x18 # macro +GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT = 0x19 # macro +GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT = 0x1a # macro +GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT = 0x1b # macro +GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT = 0x1c # macro +GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT = 0x1d # macro +GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT = 0x1e # macro +GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT = 0x1f # macro +GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x0000003F # macro +GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000400 # macro +GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000800 # macro +GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK = 0x00001000 # macro +GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK = 0x00002000 # macro +GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK = 0x00004000 # macro +GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK = 0x00010000 # macro +GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK = 0x00020000 # macro +GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK = 0x00040000 # macro +GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK = 0x00080000 # macro +GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK = 0x00100000 # macro +GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK = 0x00200000 # macro +GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK = 0x00400000 # macro +GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK = 0x00800000 # macro +GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK = 0x01000000 # macro +GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK = 0x02000000 # macro +GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK = 0x04000000 # macro +GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK = 0x08000000 # macro +GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK = 0x10000000 # macro +GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK = 0x20000000 # macro +GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK = 0x40000000 # macro +GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK = 0x80000000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xa # macro +GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xb # macro +GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT = 0xc # macro +GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT = 0xd # macro +GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT = 0xf # macro +GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT = 0x10 # macro +GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT = 0x11 # macro +GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT = 0x12 # macro +GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT = 0x13 # macro +GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT = 0x14 # macro +GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT = 0x15 # macro +GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT = 0x16 # macro +GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK = 0x0000003F # macro +GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000400 # macro +GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000800 # macro +GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK = 0x00001000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK = 0x00002000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK = 0x00008000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK = 0x00010000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK = 0x00020000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK = 0x00040000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK = 0x00080000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK = 0x00100000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK = 0x00200000 # macro +GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK = 0x00400000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xa # macro +GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xb # macro +GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT = 0xc # macro +GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT = 0xd # macro +GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT = 0xf # macro +GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT = 0x10 # macro +GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT = 0x11 # macro +GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT = 0x12 # macro +GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT = 0x13 # macro +GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT = 0x14 # macro +GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT = 0x15 # macro +GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT = 0x16 # macro +GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK = 0x0000003F # macro +GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000400 # macro +GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000800 # macro +GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK = 0x00001000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK = 0x00002000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK = 0x00008000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK = 0x00010000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK = 0x00020000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK = 0x00040000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK = 0x00080000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK = 0x00100000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK = 0x00200000 # macro +GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK = 0x00400000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xa # macro +GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xb # macro +GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT = 0xc # macro +GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT = 0xd # macro +GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT = 0xf # macro +GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT = 0x10 # macro +GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT = 0x11 # macro +GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT = 0x12 # macro +GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT = 0x13 # macro +GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT = 0x14 # macro +GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT = 0x15 # macro +GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT = 0x16 # macro +GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK = 0x0000003F # macro +GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000400 # macro +GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000800 # macro +GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK = 0x00001000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK = 0x00002000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK = 0x00008000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK = 0x00010000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK = 0x00020000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK = 0x00040000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK = 0x00080000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK = 0x00100000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK = 0x00200000 # macro +GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK = 0x00400000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xa # macro +GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT = 0xb # macro +GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT = 0xc # macro +GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT = 0xd # macro +GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT = 0xf # macro +GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT = 0x10 # macro +GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT = 0x11 # macro +GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT = 0x12 # macro +GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT = 0x13 # macro +GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT = 0x14 # macro +GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT = 0x15 # macro +GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT = 0x16 # macro +GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK = 0x0000003F # macro +GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000400 # macro +GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK = 0x00000800 # macro +GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK = 0x00001000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK = 0x00002000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK = 0x00008000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK = 0x00010000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK = 0x00020000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK = 0x00040000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK = 0x00080000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK = 0x00100000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK = 0x00200000 # macro +GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK = 0x00400000 # macro +WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000000FF # macro +WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000000FF # macro +WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000000FF # macro +WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000000FF # macro +WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000000FF # macro +IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000000FF # macro +IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000000FF # macro +IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000000FF # macro +VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000000FF # macro +VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT = 0x0 # macro +VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK = 0x000000FF # macro +PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +PA_SU_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +PA_SU_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +PA_SU_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +PA_SU_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +PA_SU_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +PA_SU_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +PA_SU_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +PA_SU_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +PA_SC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +PA_SC_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK = 0x000003FF # macro +PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT = 0x0 # macro +PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT = 0xa # macro +SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT = 0xa # macro +SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK = 0x000000FF # macro +SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK = 0x000000FF # macro +SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT = 0x0 # macro +SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT = 0x4 # macro +SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT = 0x8 # macro +SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT = 0xc # macro +SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT = 0x10 # macro +SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT = 0x14 # macro +SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT = 0x18 # macro +SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT = 0x1c # macro +SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK = 0x0000000F # macro +SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK = 0x000000F0 # macro +SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK = 0x00000F00 # macro +SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK = 0x0000F000 # macro +SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK = 0x000F0000 # macro +SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK = 0x00F00000 # macro +SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK = 0x0F000000 # macro +SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT = 0xc # macro +SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT = 0x10 # macro +SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT = 0x18 # macro +SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK = 0x0000F000 # macro +SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK = 0x000F0000 # macro +SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK = 0x0F000000 # macro +SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT = 0xc # macro +SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT = 0x10 # macro +SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT = 0x18 # macro +SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK = 0x0000F000 # macro +SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK = 0x000F0000 # macro +SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK = 0x0F000000 # macro +SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT = 0xc # macro +SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT = 0x10 # macro +SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT = 0x18 # macro +SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK = 0x0000F000 # macro +SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK = 0x000F0000 # macro +SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK = 0x0F000000 # macro +SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT = 0xc # macro +SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT = 0x10 # macro +SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT = 0x18 # macro +SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK = 0x0000F000 # macro +SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK = 0x000F0000 # macro +SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK = 0x0F000000 # macro +SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT = 0xc # macro +SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT = 0x10 # macro +SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT = 0x18 # macro +SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK = 0x0000F000 # macro +SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK = 0x000F0000 # macro +SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK = 0x0F000000 # macro +SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT = 0xc # macro +SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT = 0x10 # macro +SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT = 0x18 # macro +SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK = 0x0000F000 # macro +SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK = 0x000F0000 # macro +SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK = 0x0F000000 # macro +SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT = 0xc # macro +SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT = 0x10 # macro +SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT = 0x18 # macro +SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK = 0x0000F000 # macro +SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK = 0x000F0000 # macro +SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK = 0x0F000000 # macro +SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT = 0xc # macro +SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT = 0x10 # macro +SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT = 0x18 # macro +SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK = 0x0000F000 # macro +SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK = 0x000F0000 # macro +SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK = 0x0F000000 # macro +SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT = 0xc # macro +SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT = 0x10 # macro +SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT = 0x18 # macro +SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK = 0x0000F000 # macro +SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK = 0x000F0000 # macro +SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK = 0x0F000000 # macro +SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT = 0xc # macro +SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT = 0x10 # macro +SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT = 0x18 # macro +SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK = 0x0000F000 # macro +SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK = 0x000F0000 # macro +SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK = 0x0F000000 # macro +SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT = 0xc # macro +SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT = 0x10 # macro +SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT = 0x18 # macro +SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK = 0x0000F000 # macro +SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK = 0x000F0000 # macro +SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK = 0x0F000000 # macro +SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT = 0xc # macro +SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT = 0x10 # macro +SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT = 0x18 # macro +SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK = 0x0000F000 # macro +SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK = 0x000F0000 # macro +SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK = 0x0F000000 # macro +SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT = 0xc # macro +SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT = 0x10 # macro +SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT = 0x18 # macro +SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK = 0x0000F000 # macro +SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK = 0x000F0000 # macro +SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK = 0x0F000000 # macro +SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT = 0xc # macro +SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT = 0x10 # macro +SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT = 0x18 # macro +SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK = 0x0000F000 # macro +SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK = 0x000F0000 # macro +SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK = 0x0F000000 # macro +SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT = 0xc # macro +SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT = 0x10 # macro +SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT = 0x18 # macro +SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK = 0x0000F000 # macro +SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK = 0x000F0000 # macro +SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK = 0x0F000000 # macro +SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT = 0xc # macro +SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT = 0x10 # macro +SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT = 0x14 # macro +SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT = 0x18 # macro +SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK = 0x000001FF # macro +SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK = 0x0000F000 # macro +SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK = 0x000F0000 # macro +SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK = 0x00F00000 # macro +SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK = 0x0F000000 # macro +SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT = 0x0 # macro +SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT = 0x1 # macro +SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT = 0x2 # macro +SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT = 0x3 # macro +SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT = 0x4 # macro +SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT = 0x5 # macro +SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT = 0x6 # macro +SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT = 0x8 # macro +SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT = 0xd # macro +SQ_PERFCOUNTER_CTRL__VMID_MASK__SHIFT = 0x10 # macro +SQ_PERFCOUNTER_CTRL__PS_EN_MASK = 0x00000001 # macro +SQ_PERFCOUNTER_CTRL__VS_EN_MASK = 0x00000002 # macro +SQ_PERFCOUNTER_CTRL__GS_EN_MASK = 0x00000004 # macro +SQ_PERFCOUNTER_CTRL__ES_EN_MASK = 0x00000008 # macro +SQ_PERFCOUNTER_CTRL__HS_EN_MASK = 0x00000010 # macro +SQ_PERFCOUNTER_CTRL__LS_EN_MASK = 0x00000020 # macro +SQ_PERFCOUNTER_CTRL__CS_EN_MASK = 0x00000040 # macro +SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK = 0x00001F00 # macro +SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK = 0x00002000 # macro +SQ_PERFCOUNTER_CTRL__VMID_MASK_MASK = 0xFFFF0000 # macro +SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT = 0x0 # macro +SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT = 0x10 # macro +SQ_PERFCOUNTER_MASK__SH0_MASK_MASK = 0x0000FFFF # macro +SQ_PERFCOUNTER_MASK__SH1_MASK_MASK = 0xFFFF0000 # macro +SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT = 0x0 # macro +SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK = 0x00000001 # macro +SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SX_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +SX_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +SX_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SX_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +SX_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +SX_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SX_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SX_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +SX_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +SX_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SX_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SX_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +SX_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +SX_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SX_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +SX_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SX_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +SX_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SX_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +SX_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +SX_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +SX_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +SX_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +SX_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +SX_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +SX_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +SX_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +SX_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +SX_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +SX_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +SX_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +SX_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +SX_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +SX_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +SX_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +SX_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +SX_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +SX_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +GDS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GDS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +GDS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GDS_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GDS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GDS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +GDS_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GDS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GDS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GDS_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GDS_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GDS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GDS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GDS_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GDS_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GDS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +GDS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +GDS_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +GDS_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +GDS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +GDS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +GDS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +GDS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +GDS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +GDS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +GDS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x0000007F # macro +TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x0001FC00 # macro +TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x0000007F # macro +TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x0001FC00 # macro +TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x0000007F # macro +TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x0000003F # macro +TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x0000FC00 # macro +TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x0000003F # macro +TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x0000FC00 # macro +TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x0000003F # macro +TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x0000007F # macro +TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x0001FC00 # macro +TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x0000007F # macro +TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x0001FC00 # macro +TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x0000007F # macro +TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x0001FC00 # macro +TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x0000007F # macro +TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x0001FC00 # macro +TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x0000007F # macro +TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x0000007F # macro +TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x18 # macro +TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x1c # macro +TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0x0F000000 # macro +TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0xF0000000 # macro +TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x18 # macro +TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x1c # macro +TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0x0F000000 # macro +TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0xF0000000 # macro +TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x18 # macro +TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x1c # macro +TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0x0F000000 # macro +TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0xF0000000 # macro +TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x18 # macro +TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x1c # macro +TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0x0F000000 # macro +TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0xF0000000 # macro +TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT = 0x0 # macro +CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT = 0x1 # macro +CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT = 0x4 # macro +CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT = 0x5 # macro +CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT = 0xa # macro +CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT = 0xb # macro +CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT = 0xc # macro +CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT = 0xd # macro +CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT = 0x11 # macro +CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT = 0x12 # macro +CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT = 0x15 # macro +CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT = 0x16 # macro +CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK = 0x00000001 # macro +CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK = 0x0000000E # macro +CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK = 0x00000010 # macro +CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK = 0x000003E0 # macro +CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK = 0x00000400 # macro +CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK = 0x00000800 # macro +CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK = 0x00001000 # macro +CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK = 0x0000E000 # macro +CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK = 0x00020000 # macro +CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK = 0x001C0000 # macro +CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK = 0x00200000 # macro +CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK = 0x00C00000 # macro +CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000001FF # macro +CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x0007FC00 # macro +CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000001FF # macro +CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x0007FC00 # macro +CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000001FF # macro +CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000001FF # macro +CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000001FF # macro +CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000003FF # macro +DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT = 0xa # macro +DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000003FF # macro +DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK = 0x000003FF # macro +DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK = 0x000FFC00 # macro +DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT = 0xa # macro +DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000003FF # macro +DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT = 0xa # macro +DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000003FF # macro +DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK = 0x000FFC00 # macro +DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT = 0x0 # macro +RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT = 0xc # macro +RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT = 0xe # macro +RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT = 0x10 # macro +RLC_SPM_PERFMON_CNTL__RESERVED1_MASK = 0x00000FFF # macro +RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK = 0x00003000 # macro +RLC_SPM_PERFMON_CNTL__RESERVED_MASK = 0x0000C000 # macro +RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK = 0xFFFF0000 # macro +RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT = 0x0 # macro +RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK = 0xFFFFFFFF # macro +RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT = 0x0 # macro +RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT = 0x10 # macro +RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK = 0x0000FFFF # macro +RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK = 0xFFFF0000 # macro +RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT = 0x0 # macro +RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK = 0xFFFFFFFF # macro +RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT = 0x0 # macro +RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT = 0x8 # macro +RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT = 0xb # macro +RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT = 0x10 # macro +RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT = 0x15 # macro +RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT = 0x1a # macro +RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT = 0x1f # macro +RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK = 0x000000FF # macro +RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK = 0x00000700 # macro +RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK = 0x0000F800 # macro +RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK = 0x001F0000 # macro +RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK = 0x03E00000 # macro +RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK = 0x7C000000 # macro +RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK = 0x80000000 # macro +RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT = 0x0 # macro +RLC_SPM_SE_MUXSEL_ADDR__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK = 0x000000FF # macro +RLC_SPM_SE_MUXSEL_ADDR__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT = 0x0 # macro +RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK = 0xFFFFFFFF # macro +RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT = 0x0 # macro +RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK = 0x000000FF # macro +RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT = 0x0 # macro +RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK = 0x000000FF # macro +RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT = 0x0 # macro +RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK = 0x000000FF # macro +RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT = 0x0 # macro +RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK = 0x000000FF # macro +RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT = 0x0 # macro +RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK = 0x000000FF # macro +RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT = 0x0 # macro +RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK = 0x000000FF # macro +RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT = 0x0 # macro +RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK = 0x000000FF # macro +RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT = 0x0 # macro +RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK = 0x000000FF # macro +RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT = 0x0 # macro +RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK = 0x000000FF # macro +RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT = 0x0 # macro +RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK = 0x000000FF # macro +RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT = 0x0 # macro +RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK = 0x000000FF # macro +RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT = 0x0 # macro +RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK = 0x000000FF # macro +RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT = 0x0 # macro +RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK = 0x000000FF # macro +RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT = 0x0 # macro +RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK = 0x000000FF # macro +RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT = 0x0 # macro +RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK = 0x000000FF # macro +RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT = 0x0 # macro +RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK = 0x000000FF # macro +RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT = 0x0 # macro +RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK = 0x000000FF # macro +RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT = 0x0 # macro +RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK = 0x000000FF # macro +RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT = 0x0 # macro +RLC_SPM_GLOBAL_MUXSEL_ADDR__RESERVED__SHIFT = 0x7 # macro +RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK = 0x0000007F # macro +RLC_SPM_GLOBAL_MUXSEL_ADDR__RESERVED_MASK = 0xFFFFFF80 # macro +RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT = 0x0 # macro +RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK = 0xFFFFFFFF # macro +RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT = 0x0 # macro +RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK = 0xFFFFFFFF # macro +RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT = 0x0 # macro +RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK = 0xFFFFFFFF # macro +RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT = 0x0 # macro +RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK = 0x000000FF # macro +RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__PERFMON_MAX_SAMPLE_DELAY__SHIFT = 0x0 # macro +RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__RESERVED__SHIFT = 0x8 # macro +RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__PERFMON_MAX_SAMPLE_DELAY_MASK = 0x000000FF # macro +RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT = 0x0 # macro +RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT = 0xa # macro +RLC_PERFMON_CNTL__PERFMON_STATE_MASK = 0x00000007 # macro +RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK = 0x00000400 # macro +RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT = 0x0 # macro +RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK = 0x00FF # macro +RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT = 0x0 # macro +RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK = 0x00FF # macro +RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT = 0x0 # macro +RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT = 0x1 # macro +RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT = 0x2 # macro +RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT = 0x3 # macro +RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK = 0x00000001 # macro +RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK = 0x00000002 # macro +RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK = 0x00000004 # macro +RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK = 0xFFFFFFF8 # macro +RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT = 0x0 # macro +RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT = 0x4 # macro +RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT = 0x6 # macro +RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK = 0x0000000F # macro +RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK = 0x00000030 # macro +RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK = 0xFFFFFFC0 # macro +RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT = 0x0 # macro +RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK = 0x0000000F # macro +RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT = 0x0 # macro +RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT = 0x4 # macro +RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT = 0x6 # macro +RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK = 0x0000000F # macro +RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK = 0x00000030 # macro +RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK = 0xFFFFFFC0 # macro +RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT = 0x0 # macro +RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK = 0x0000000F # macro +RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT = 0x0 # macro +RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT = 0xa # macro +RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT = 0x1c # macro +RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK = 0x000001FF # macro +RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK = 0x0007FC00 # macro +RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK = 0x000001FF # macro +RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK = 0x0007FC00 # macro +RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT = 0x0 # macro +RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT = 0x1c # macro +RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK = 0x000001FF # macro +RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT = 0x0 # macro +RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT = 0xa # macro +RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT = 0x14 # macro +RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT = 0x18 # macro +RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT = 0x1c # macro +RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK = 0x000001FF # macro +RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK = 0x0007FC00 # macro +RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK = 0x00F00000 # macro +RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK = 0x0F000000 # macro +RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT = 0x0 # macro +RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT = 0xa # macro +RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT = 0x18 # macro +RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT = 0x1c # macro +RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK = 0x000001FF # macro +RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK = 0x0007FC00 # macro +RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK = 0x0F000000 # macro +RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK = 0xF0000000 # macro +RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT = 0x0 # macro +RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT = 0x1c # macro +RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK = 0x000001FF # macro +RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK = 0xF0000000 # macro +RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT = 0x0 # macro +RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT = 0x2 # macro +RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT = 0x4 # macro +RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT = 0x6 # macro +RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT = 0x8 # macro +RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT = 0xa # macro +RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT = 0xe # macro +RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT = 0x13 # macro +RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT = 0x19 # macro +RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT = 0x1a # macro +RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK = 0x00000003 # macro +RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK = 0x0000000C # macro +RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK = 0x00000030 # macro +RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK = 0x000000C0 # macro +RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK = 0x00000300 # macro +RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK = 0x00003C00 # macro +RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK = 0x0007C000 # macro +RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK = 0x01F80000 # macro +RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK = 0x02000000 # macro +RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK = 0x04000000 # macro +ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x0000000F # macro +ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT = 0x0 # macro +MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT = 0x18 # macro +MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT = 0x1c # macro +MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT = 0x1d # macro +MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK = 0x000000FF # macro +MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK = 0x10000000 # macro +MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK = 0x20000000 # macro +MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT = 0x0 # macro +MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT = 0x18 # macro +MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT = 0x1c # macro +MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT = 0x1d # macro +MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK = 0x000000FF # macro +MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK = 0x10000000 # macro +MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK = 0x20000000 # macro +MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT = 0x0 # macro +MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT = 0x18 # macro +MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT = 0x1c # macro +MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT = 0x1d # macro +MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK = 0x000000FF # macro +MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK = 0x10000000 # macro +MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK = 0x20000000 # macro +MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT = 0x0 # macro +MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT = 0x18 # macro +MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT = 0x1c # macro +MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT = 0x1d # macro +MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK = 0x000000FF # macro +MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK = 0x10000000 # macro +MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK = 0x20000000 # macro +MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT = 0x0 # macro +MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT = 0x18 # macro +MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT = 0x1c # macro +MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT = 0x1d # macro +MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK = 0x000000FF # macro +MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK = 0x10000000 # macro +MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK = 0x20000000 # macro +MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT = 0x0 # macro +MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT = 0x18 # macro +MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT = 0x1c # macro +MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT = 0x1d # macro +MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK = 0x000000FF # macro +MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK = 0x10000000 # macro +MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK = 0x20000000 # macro +MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x0000000F # macro +MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +L2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +L2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +L2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +L2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +L2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +L2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +L2TLB_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +L2TLB_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +L2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +L2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +L2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +L2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +L2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +L2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +L2TLB_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +L2TLB_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +L2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT = 0x0 # macro +L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +L2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT = 0x18 # macro +L2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT = 0x1c # macro +L2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT = 0x1d # macro +L2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK = 0x000000FF # macro +L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +L2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK = 0x0F000000 # macro +L2TLB_PERFCOUNTER2_CFG__ENABLE_MASK = 0x10000000 # macro +L2TLB_PERFCOUNTER2_CFG__CLEAR_MASK = 0x20000000 # macro +L2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT = 0x0 # macro +L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +L2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT = 0x18 # macro +L2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT = 0x1c # macro +L2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT = 0x1d # macro +L2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK = 0x000000FF # macro +L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +L2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK = 0x0F000000 # macro +L2TLB_PERFCOUNTER3_CFG__ENABLE_MASK = 0x10000000 # macro +L2TLB_PERFCOUNTER3_CFG__CLEAR_MASK = 0x20000000 # macro +L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x0000000F # macro +L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +GDFLL_EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS__SHIFT = 0x0 # macro +GDFLL_EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS_MASK = 0x000000FF # macro +GDFLL_EDC_HYSTERESIS_STAT__HYSTERESIS_CNT__SHIFT = 0x0 # macro +GDFLL_EDC_HYSTERESIS_STAT__EDC__SHIFT = 0x8 # macro +GDFLL_EDC_HYSTERESIS_STAT__HYSTERESIS_CNT_MASK = 0x000000FF # macro +GDFLL_EDC_HYSTERESIS_STAT__EDC_MASK = 0x00000100 # macro +RLC_CNTL__RLC_ENABLE_F32__SHIFT = 0x0 # macro +RLC_CNTL__FORCE_RETRY__SHIFT = 0x1 # macro +RLC_CNTL__READ_CACHE_DISABLE__SHIFT = 0x2 # macro +RLC_CNTL__RLC_STEP_F32__SHIFT = 0x3 # macro +RLC_CNTL__RESERVED__SHIFT = 0x4 # macro +RLC_CNTL__RLC_ENABLE_F32_MASK = 0x00000001 # macro +RLC_CNTL__FORCE_RETRY_MASK = 0x00000002 # macro +RLC_CNTL__READ_CACHE_DISABLE_MASK = 0x00000004 # macro +RLC_CNTL__RLC_STEP_F32_MASK = 0x00000008 # macro +RLC_CNTL__RESERVED_MASK = 0xFFFFFFF0 # macro +RLC_CGCG_CGLS_CTRL_2__CANE_STAT_BUSY_MASK__SHIFT = 0x0 # macro +RLC_CGCG_CGLS_CTRL_2__RESERVED__SHIFT = 0x1 # macro +RLC_CGCG_CGLS_CTRL_2__CANE_STAT_BUSY_MASK_MASK = 0x00000001 # macro +RLC_CGCG_CGLS_CTRL_2__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_STAT__RLC_BUSY__SHIFT = 0x0 # macro +RLC_STAT__RLC_SRM_BUSY__SHIFT = 0x1 # macro +RLC_STAT__RLC_GPM_BUSY__SHIFT = 0x2 # macro +RLC_STAT__RLC_SPM_BUSY__SHIFT = 0x3 # macro +RLC_STAT__MC_BUSY__SHIFT = 0x4 # macro +RLC_STAT__RLC_THREAD_0_BUSY__SHIFT = 0x5 # macro +RLC_STAT__RLC_THREAD_1_BUSY__SHIFT = 0x6 # macro +RLC_STAT__RLC_THREAD_2_BUSY__SHIFT = 0x7 # macro +RLC_STAT__RESERVED__SHIFT = 0x8 # macro +RLC_STAT__RLC_BUSY_MASK = 0x00000001 # macro +RLC_STAT__RLC_SRM_BUSY_MASK = 0x00000002 # macro +RLC_STAT__RLC_GPM_BUSY_MASK = 0x00000004 # macro +RLC_STAT__RLC_SPM_BUSY_MASK = 0x00000008 # macro +RLC_STAT__MC_BUSY_MASK = 0x00000010 # macro +RLC_STAT__RLC_THREAD_0_BUSY_MASK = 0x00000020 # macro +RLC_STAT__RLC_THREAD_1_BUSY_MASK = 0x00000040 # macro +RLC_STAT__RLC_THREAD_2_BUSY_MASK = 0x00000080 # macro +RLC_STAT__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_SAFE_MODE__CMD__SHIFT = 0x0 # macro +RLC_SAFE_MODE__MESSAGE__SHIFT = 0x1 # macro +RLC_SAFE_MODE__RESERVED1__SHIFT = 0x5 # macro +RLC_SAFE_MODE__RESPONSE__SHIFT = 0x8 # macro +RLC_SAFE_MODE__RESERVED__SHIFT = 0xc # macro +RLC_SAFE_MODE__CMD_MASK = 0x00000001 # macro +RLC_SAFE_MODE__MESSAGE_MASK = 0x0000001E # macro +RLC_SAFE_MODE__RESERVED1_MASK = 0x000000E0 # macro +RLC_SAFE_MODE__RESPONSE_MASK = 0x00000F00 # macro +RLC_SAFE_MODE__RESERVED_MASK = 0xFFFFF000 # macro +RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT = 0x0 # macro +RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT = 0x1 # macro +RLC_MEM_SLP_CNTL__RESERVED__SHIFT = 0x2 # macro +RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT = 0x7 # macro +RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT = 0x8 # macro +RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT = 0x10 # macro +RLC_MEM_SLP_CNTL__RESERVED1__SHIFT = 0x18 # macro +RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK = 0x00000001 # macro +RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK = 0x00000002 # macro +RLC_MEM_SLP_CNTL__RESERVED_MASK = 0x0000007C # macro +RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK = 0x00000080 # macro +RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK = 0x0000FF00 # macro +RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK = 0x00FF0000 # macro +RLC_MEM_SLP_CNTL__RESERVED1_MASK = 0xFF000000 # macro +SMU_RLC_RESPONSE__RESP__SHIFT = 0x0 # macro +SMU_RLC_RESPONSE__RESP_MASK = 0xFFFFFFFF # macro +RLC_RLCV_SAFE_MODE__CMD__SHIFT = 0x0 # macro +RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT = 0x1 # macro +RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT = 0x5 # macro +RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT = 0x8 # macro +RLC_RLCV_SAFE_MODE__RESERVED__SHIFT = 0xc # macro +RLC_RLCV_SAFE_MODE__CMD_MASK = 0x00000001 # macro +RLC_RLCV_SAFE_MODE__MESSAGE_MASK = 0x0000001E # macro +RLC_RLCV_SAFE_MODE__RESERVED1_MASK = 0x000000E0 # macro +RLC_RLCV_SAFE_MODE__RESPONSE_MASK = 0x00000F00 # macro +RLC_RLCV_SAFE_MODE__RESERVED_MASK = 0xFFFFF000 # macro +RLC_SMU_SAFE_MODE__CMD__SHIFT = 0x0 # macro +RLC_SMU_SAFE_MODE__MESSAGE__SHIFT = 0x1 # macro +RLC_SMU_SAFE_MODE__RESERVED1__SHIFT = 0x5 # macro +RLC_SMU_SAFE_MODE__RESPONSE__SHIFT = 0x8 # macro +RLC_SMU_SAFE_MODE__RESERVED__SHIFT = 0xc # macro +RLC_SMU_SAFE_MODE__CMD_MASK = 0x00000001 # macro +RLC_SMU_SAFE_MODE__MESSAGE_MASK = 0x0000001E # macro +RLC_SMU_SAFE_MODE__RESERVED1_MASK = 0x000000E0 # macro +RLC_SMU_SAFE_MODE__RESPONSE_MASK = 0x00000F00 # macro +RLC_SMU_SAFE_MODE__RESERVED_MASK = 0xFFFFF000 # macro +RLC_RLCV_COMMAND__CMD__SHIFT = 0x0 # macro +RLC_RLCV_COMMAND__RESERVED__SHIFT = 0x4 # macro +RLC_RLCV_COMMAND__CMD_MASK = 0x0000000F # macro +RLC_RLCV_COMMAND__RESERVED_MASK = 0xFFFFFFF0 # macro +RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT = 0x0 # macro +RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK = 0xFFFFFFFF # macro +RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT = 0x0 # macro +RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK = 0xFFFFFFFF # macro +RLC_GPM_TIMER_INT_0__TIMER__SHIFT = 0x0 # macro +RLC_GPM_TIMER_INT_0__TIMER_MASK = 0xFFFFFFFF # macro +RLC_GPM_TIMER_INT_1__TIMER__SHIFT = 0x0 # macro +RLC_GPM_TIMER_INT_1__TIMER_MASK = 0xFFFFFFFF # macro +RLC_GPM_TIMER_INT_2__TIMER__SHIFT = 0x0 # macro +RLC_GPM_TIMER_INT_2__TIMER_MASK = 0xFFFFFFFF # macro +RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT = 0x0 # macro +RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT = 0x1 # macro +RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT = 0x2 # macro +RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT = 0x3 # macro +RLC_GPM_TIMER_CTRL__RESERVED__SHIFT = 0x4 # macro +RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK = 0x00000001 # macro +RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK = 0x00000002 # macro +RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK = 0x00000004 # macro +RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK = 0x00000008 # macro +RLC_GPM_TIMER_CTRL__RESERVED_MASK = 0xFFFFFFF0 # macro +RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT = 0x0 # macro +RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK = 0xFFFFFFFF # macro +RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT = 0x0 # macro +RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT = 0x1 # macro +RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT = 0x2 # macro +RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT = 0x3 # macro +RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT = 0x8 # macro +RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT = 0x9 # macro +RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT = 0xa # macro +RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC__SHIFT = 0xb # macro +RLC_GPM_TIMER_STAT__RESERVED__SHIFT = 0xc # macro +RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK = 0x00000001 # macro +RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK = 0x00000002 # macro +RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK = 0x00000004 # macro +RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK = 0x00000008 # macro +RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK = 0x00000100 # macro +RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK = 0x00000200 # macro +RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC_MASK = 0x00000400 # macro +RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC_MASK = 0x00000800 # macro +RLC_GPM_TIMER_STAT__RESERVED_MASK = 0xFFFFF000 # macro +RLC_GPM_TIMER_INT_3__TIMER__SHIFT = 0x0 # macro +RLC_GPM_TIMER_INT_3__TIMER_MASK = 0xFFFFFFFF # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1__SHIFT = 0x0 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1__SHIFT = 0x10 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1__SHIFT = 0x11 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK__SHIFT = 0x12 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1__SHIFT = 0x13 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK__SHIFT = 0x14 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK__SHIFT = 0x15 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK__SHIFT = 0x16 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK__SHIFT = 0x17 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK__SHIFT = 0x18 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED__SHIFT = 0x19 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1_MASK = 0x0000FFFF # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1_MASK = 0x00010000 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1_MASK = 0x00020000 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK_MASK = 0x00040000 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1_MASK = 0x00080000 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK_MASK = 0x00100000 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK_MASK = 0x00200000 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK_MASK = 0x00400000 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK_MASK = 0x00800000 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK_MASK = 0x01000000 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_MASK = 0xFE000000 # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1__SHIFT = 0x0 # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1__SHIFT = 0x10 # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1__SHIFT = 0x11 # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1__SHIFT = 0x12 # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1__SHIFT = 0x13 # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY__SHIFT = 0x14 # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY__SHIFT = 0x15 # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY__SHIFT = 0x16 # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY__SHIFT = 0x17 # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY__SHIFT = 0x18 # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED__SHIFT = 0x19 # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1_MASK = 0x0000FFFF # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1_MASK = 0x00010000 # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1_MASK = 0x00020000 # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1_MASK = 0x00040000 # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1_MASK = 0x00080000 # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY_MASK = 0x00100000 # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY_MASK = 0x00200000 # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY_MASK = 0x00400000 # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY_MASK = 0x00800000 # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY_MASK = 0x01000000 # macro +RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_MASK = 0xFE000000 # macro +RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT = 0x0 # macro +RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT = 0x8 # macro +RLC_INT_STAT__RESERVED__SHIFT = 0x9 # macro +RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK = 0x000000FF # macro +RLC_INT_STAT__CP_RLC_INT_PENDING_MASK = 0x00000100 # macro +RLC_INT_STAT__RESERVED_MASK = 0xFFFFFE00 # macro +RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT = 0x0 # macro +RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT = 0x1 # macro +RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT = 0x2 # macro +RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT = 0x3 # macro +RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT = 0x4 # macro +RLC_LB_CNTL__RESERVED__SHIFT = 0xc # macro +RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK = 0x00000001 # macro +RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK = 0x00000002 # macro +RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK = 0x00000004 # macro +RLC_LB_CNTL__LB_CNT_REG_INC_MASK = 0x00000008 # macro +RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK = 0x00000FF0 # macro +RLC_LB_CNTL__RESERVED_MASK = 0xFFFFF000 # macro +RLC_MGCG_CTRL__MGCG_EN__SHIFT = 0x0 # macro +RLC_MGCG_CTRL__SILICON_EN__SHIFT = 0x1 # macro +RLC_MGCG_CTRL__SIMULATION_EN__SHIFT = 0x2 # macro +RLC_MGCG_CTRL__ON_DELAY__SHIFT = 0x3 # macro +RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT = 0x7 # macro +RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT = 0xf # macro +RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT = 0x10 # macro +RLC_MGCG_CTRL__SPARE__SHIFT = 0x11 # macro +RLC_MGCG_CTRL__MGCG_EN_MASK = 0x00000001 # macro +RLC_MGCG_CTRL__SILICON_EN_MASK = 0x00000002 # macro +RLC_MGCG_CTRL__SIMULATION_EN_MASK = 0x00000004 # macro +RLC_MGCG_CTRL__ON_DELAY_MASK = 0x00000078 # macro +RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK = 0x00007F80 # macro +RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK = 0x00008000 # macro +RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK = 0x00010000 # macro +RLC_MGCG_CTRL__SPARE_MASK = 0xFFFE0000 # macro +RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT = 0x0 # macro +RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK = 0xFFFFFFFF # macro +RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT = 0x0 # macro +RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK = 0xFFFFFFFF # macro +RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT = 0x0 # macro +RLC_JUMP_TABLE_RESTORE__ADDR_MASK = 0xFFFFFFFF # macro +RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT = 0x0 # macro +RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT = 0x8 # macro +RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT = 0x10 # macro +RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK = 0x000000FF # macro +RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK = 0x0000FF00 # macro +RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK = 0xFFFF0000 # macro +RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT = 0x0 # macro +RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK = 0xFFFFFFFF # macro +RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT = 0x0 # macro +RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK = 0xFFFFFFFF # macro +RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT = 0x0 # macro +RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT = 0x1 # macro +RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK = 0x00000001 # macro +RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT = 0x0 # macro +RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK = 0xFFFFFFFF # macro +RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT = 0x0 # macro +RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT = 0x1 # macro +RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT = 0x2 # macro +RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT = 0x3 # macro +RLC_GPM_THREAD_RESET__RESERVED__SHIFT = 0x4 # macro +RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK = 0x00000001 # macro +RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK = 0x00000002 # macro +RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK = 0x00000004 # macro +RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK = 0x00000008 # macro +RLC_GPM_THREAD_RESET__RESERVED_MASK = 0xFFFFFFF0 # macro +RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT = 0x0 # macro +RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT = 0x1 # macro +RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK = 0x00000001 # macro +RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT = 0x0 # macro +RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT = 0x1 # macro +RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK = 0x00000001 # macro +RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_FIREWALL_VIOLATION__ADDR__SHIFT = 0x0 # macro +RLC_FIREWALL_VIOLATION__ADDR_MASK = 0xFFFFFFFF # macro +RLC_CLK_COUNT_GFXCLK_LSB__COUNTER__SHIFT = 0x0 # macro +RLC_CLK_COUNT_GFXCLK_LSB__COUNTER_MASK = 0xFFFFFFFF # macro +RLC_CLK_COUNT_GFXCLK_MSB__COUNTER__SHIFT = 0x0 # macro +RLC_CLK_COUNT_GFXCLK_MSB__COUNTER_MASK = 0xFFFFFFFF # macro +RLC_CLK_COUNT_REFCLK_LSB__COUNTER__SHIFT = 0x0 # macro +RLC_CLK_COUNT_REFCLK_LSB__COUNTER_MASK = 0xFFFFFFFF # macro +RLC_CLK_COUNT_REFCLK_MSB__COUNTER__SHIFT = 0x0 # macro +RLC_CLK_COUNT_REFCLK_MSB__COUNTER_MASK = 0xFFFFFFFF # macro +RLC_CLK_COUNT_CTRL__GFXCLK_RUN__SHIFT = 0x0 # macro +RLC_CLK_COUNT_CTRL__GFXCLK_RESET__SHIFT = 0x1 # macro +RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE__SHIFT = 0x2 # macro +RLC_CLK_COUNT_CTRL__REFCLK_RUN__SHIFT = 0x3 # macro +RLC_CLK_COUNT_CTRL__REFCLK_RESET__SHIFT = 0x4 # macro +RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE__SHIFT = 0x5 # macro +RLC_CLK_COUNT_CTRL__GFXCLK_RUN_MASK = 0x00000001 # macro +RLC_CLK_COUNT_CTRL__GFXCLK_RESET_MASK = 0x00000002 # macro +RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE_MASK = 0x00000004 # macro +RLC_CLK_COUNT_CTRL__REFCLK_RUN_MASK = 0x00000008 # macro +RLC_CLK_COUNT_CTRL__REFCLK_RESET_MASK = 0x00000010 # macro +RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE_MASK = 0x00000020 # macro +RLC_CLK_COUNT_STAT__GFXCLK_VALID__SHIFT = 0x0 # macro +RLC_CLK_COUNT_STAT__REFCLK_VALID__SHIFT = 0x1 # macro +RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC__SHIFT = 0x2 # macro +RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC__SHIFT = 0x3 # macro +RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC__SHIFT = 0x4 # macro +RLC_CLK_COUNT_STAT__RESERVED__SHIFT = 0x5 # macro +RLC_CLK_COUNT_STAT__GFXCLK_VALID_MASK = 0x00000001 # macro +RLC_CLK_COUNT_STAT__REFCLK_VALID_MASK = 0x00000002 # macro +RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC_MASK = 0x00000004 # macro +RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC_MASK = 0x00000008 # macro +RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC_MASK = 0x00000010 # macro +RLC_CLK_COUNT_STAT__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_GPM_STAT__RLC_BUSY__SHIFT = 0x0 # macro +RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT = 0x1 # macro +RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT = 0x2 # macro +RLC_GPM_STAT__GFX_LS_STATUS__SHIFT = 0x3 # macro +RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT = 0x4 # macro +RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT = 0x5 # macro +RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT = 0x6 # macro +RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT = 0x7 # macro +RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT = 0x8 # macro +RLC_GPM_STAT__SAVING_REGISTERS__SHIFT = 0x9 # macro +RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT = 0xa # macro +RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT = 0xb # macro +RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT = 0xc # macro +RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT = 0xd # macro +RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT = 0xe # macro +RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT = 0xf # macro +RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT = 0x10 # macro +RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT = 0x11 # macro +RLC_GPM_STAT__CMP_power_status__SHIFT = 0x12 # macro +RLC_GPM_STAT__RESERVED_1__SHIFT = 0x13 # macro +RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT = 0x15 # macro +RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT = 0x16 # macro +RLC_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT = 0x17 # macro +RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT = 0x18 # macro +RLC_GPM_STAT__RLC_BUSY_MASK = 0x00000001 # macro +RLC_GPM_STAT__GFX_POWER_STATUS_MASK = 0x00000002 # macro +RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK = 0x00000004 # macro +RLC_GPM_STAT__GFX_LS_STATUS_MASK = 0x00000008 # macro +RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK = 0x00000010 # macro +RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK = 0x00000020 # macro +RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK = 0x00000040 # macro +RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK = 0x00000080 # macro +RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK = 0x00000100 # macro +RLC_GPM_STAT__SAVING_REGISTERS_MASK = 0x00000200 # macro +RLC_GPM_STAT__RESTORING_REGISTERS_MASK = 0x00000400 # macro +RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK = 0x00000800 # macro +RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK = 0x00001000 # macro +RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK = 0x00002000 # macro +RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK = 0x00004000 # macro +RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK = 0x00008000 # macro +RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK = 0x00010000 # macro +RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK = 0x00020000 # macro +RLC_GPM_STAT__CMP_power_status_MASK = 0x00040000 # macro +RLC_GPM_STAT__RESERVED_1_MASK = 0x00180000 # macro +RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK = 0x00200000 # macro +RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK = 0x00400000 # macro +RLC_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK = 0x00800000 # macro +RLC_GPM_STAT__PG_ERROR_STATUS_MASK = 0xFF000000 # macro +RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT = 0x0 # macro +RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT = 0x6 # macro +RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK = 0x0000003F # macro +RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK = 0xFFFFFFC0 # macro +RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT = 0x0 # macro +RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK = 0xFFFFFFFF # macro +RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT = 0x0 # macro +RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT = 0x1 # macro +RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT = 0x2 # macro +RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT = 0x3 # macro +RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT = 0x4 # macro +RLC_PG_CNTL__RESERVED__SHIFT = 0x5 # macro +RLC_PG_CNTL__PG_OVERRIDE__SHIFT = 0xe # macro +RLC_PG_CNTL__CP_PG_DISABLE__SHIFT = 0xf # macro +RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT = 0x10 # macro +RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT = 0x11 # macro +RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT = 0x12 # macro +RLC_PG_CNTL__RESERVED1__SHIFT = 0x13 # macro +RLC_PG_CNTL__Ultra_Low_Voltage_Enable__SHIFT = 0x15 # macro +RLC_PG_CNTL__RESERVED2__SHIFT = 0x16 # macro +RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE__SHIFT = 0x17 # macro +RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK = 0x00000001 # macro +RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK = 0x00000002 # macro +RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK = 0x00000004 # macro +RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK = 0x00000008 # macro +RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK = 0x00000010 # macro +RLC_PG_CNTL__RESERVED_MASK = 0x00003FE0 # macro +RLC_PG_CNTL__PG_OVERRIDE_MASK = 0x00004000 # macro +RLC_PG_CNTL__CP_PG_DISABLE_MASK = 0x00008000 # macro +RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK = 0x00010000 # macro +RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK = 0x00020000 # macro +RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK = 0x00040000 # macro +RLC_PG_CNTL__RESERVED1_MASK = 0x00180000 # macro +RLC_PG_CNTL__Ultra_Low_Voltage_Enable_MASK = 0x00200000 # macro +RLC_PG_CNTL__RESERVED2_MASK = 0x00400000 # macro +RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK = 0x00800000 # macro +RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT = 0x0 # macro +RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT = 0x8 # macro +RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT = 0x10 # macro +RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT = 0x18 # macro +RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK = 0x000000FF # macro +RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK = 0x0000FF00 # macro +RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK = 0x00FF0000 # macro +RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK = 0xFF000000 # macro +RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT = 0x0 # macro +RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT = 0x1 # macro +RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT = 0x2 # macro +RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT = 0x3 # macro +RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT = 0x4 # macro +RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK = 0x00000001 # macro +RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK = 0x00000002 # macro +RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK = 0x00000004 # macro +RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK = 0x00000008 # macro +RLC_GPM_THREAD_ENABLE__RESERVED_MASK = 0xFFFFFFF0 # macro +RLC_CGTT_MGCG_OVERRIDE__RESERVED_0__SHIFT = 0x0 # macro +RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT = 0x1 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT = 0x2 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT = 0x3 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT = 0x4 # macro +RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT = 0x5 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT = 0x6 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT = 0x7 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE__SHIFT = 0x8 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE__SHIFT = 0x9 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_PERF_CLK_EN__SHIFT = 0xa # macro +RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_11__SHIFT = 0xb # macro +RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY__SHIFT = 0x10 # macro +RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17__SHIFT = 0x11 # macro +RLC_CGTT_MGCG_OVERRIDE__RESERVED_0_MASK = 0x00000001 # macro +RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK = 0x00000002 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK = 0x00000004 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK = 0x00000008 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK = 0x00000010 # macro +RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK = 0x00000020 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK = 0x00000040 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK = 0x00000080 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK = 0x00000100 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK = 0x00000200 # macro +RLC_CGTT_MGCG_OVERRIDE__GFXIP_PERF_CLK_EN_MASK = 0x00000400 # macro +RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_11_MASK = 0x0000F800 # macro +RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK = 0x00010000 # macro +RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17_MASK = 0xFFFE0000 # macro +RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT = 0x0 # macro +RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT = 0x1 # macro +RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT = 0x2 # macro +RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT = 0x8 # macro +RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT = 0x1b # macro +RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT = 0x1c # macro +RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT = 0x1d # macro +RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT = 0x1f # macro +RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK = 0x00000001 # macro +RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK = 0x00000002 # macro +RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK = 0x000000FC # macro +RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK = 0x07FFFF00 # macro +RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK = 0x08000000 # macro +RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK = 0x10000000 # macro +RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK = 0x60000000 # macro +RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK = 0x80000000 # macro +RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT = 0x0 # macro +RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT = 0x4 # macro +RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT = 0x8 # macro +RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT = 0xc # macro +RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT = 0x10 # macro +RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT = 0x1c # macro +RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK = 0x0000000F # macro +RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK = 0x000000F0 # macro +RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK = 0x00000F00 # macro +RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK = 0x0000F000 # macro +RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK = 0x0FFF0000 # macro +RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK = 0xF0000000 # macro +RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT = 0x0 # macro +RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK = 0xFFFFFFFF # macro +RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT = 0x0 # macro +RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK = 0xFFFFFFFF # macro +RLC_PG_DELAY__POWER_UP_DELAY__SHIFT = 0x0 # macro +RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT = 0x8 # macro +RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT = 0x10 # macro +RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT = 0x18 # macro +RLC_PG_DELAY__POWER_UP_DELAY_MASK = 0x000000FF # macro +RLC_PG_DELAY__POWER_DOWN_DELAY_MASK = 0x0000FF00 # macro +RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK = 0x00FF0000 # macro +RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK = 0xFF000000 # macro +RLC_CU_STATUS__WORK_PENDING__SHIFT = 0x0 # macro +RLC_CU_STATUS__WORK_PENDING_MASK = 0xFFFFFFFF # macro +RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT = 0x0 # macro +RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK = 0xFFFFFFFF # macro +RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT = 0x0 # macro +RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK = 0xFFFFFFFF # macro +RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT = 0x0 # macro +RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT = 0x1 # macro +RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT = 0x8 # macro +RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT = 0x10 # macro +RLC_LB_PARAMS__SKIP_L2_CHECK_MASK = 0x00000001 # macro +RLC_LB_PARAMS__FIFO_SAMPLES_MASK = 0x000000FE # macro +RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK = 0x0000FF00 # macro +RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK = 0xFFFF0000 # macro +RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT = 0x0 # macro +RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT = 0x8 # macro +RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT = 0x10 # macro +RLC_THREAD1_DELAY__SPARE__SHIFT = 0x18 # macro +RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK = 0x000000FF # macro +RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK = 0x0000FF00 # macro +RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK = 0x00FF0000 # macro +RLC_THREAD1_DELAY__SPARE_MASK = 0xFF000000 # macro +RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT = 0x0 # macro +RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK = 0xFFFFFFFF # macro +RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT = 0x0 # macro +RLC_MAX_PG_CU__SPARE__SHIFT = 0x8 # macro +RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK = 0x000000FF # macro +RLC_MAX_PG_CU__SPARE_MASK = 0xFFFFFF00 # macro +RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT = 0x0 # macro +RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT = 0x1 # macro +RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT = 0x2 # macro +RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT = 0x3 # macro +RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT = 0x13 # macro +RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK = 0x00000001 # macro +RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK = 0x00000002 # macro +RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK = 0x00000004 # macro +RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK = 0x0007FFF8 # macro +RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK = 0xFFF80000 # macro +RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT = 0x0 # macro +RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT = 0x1 # macro +RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK = 0x00000001 # macro +RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK = 0xFFFFFFFE # macro +RLC_SERDES_RD_PENDING__RD_PENDING__SHIFT = 0x0 # macro +RLC_SERDES_RD_PENDING__RD_PENDING_MASK = 0x00000001 # macro +RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT = 0x0 # macro +RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT = 0x4 # macro +RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT = 0x6 # macro +RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT = 0x9 # macro +RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT = 0xc # macro +RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT = 0xd # macro +RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT = 0x11 # macro +RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT = 0x13 # macro +RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK = 0x0000000F # macro +RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK = 0x00000030 # macro +RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK = 0x000001C0 # macro +RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK = 0x00000E00 # macro +RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK = 0x00001000 # macro +RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK = 0x0001E000 # macro +RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK = 0x00060000 # macro +RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK = 0xFFF80000 # macro +RLC_SERDES_RD_DATA_0__DATA__SHIFT = 0x0 # macro +RLC_SERDES_RD_DATA_0__DATA_MASK = 0xFFFFFFFF # macro +RLC_SERDES_RD_DATA_1__DATA__SHIFT = 0x0 # macro +RLC_SERDES_RD_DATA_1__DATA_MASK = 0xFFFFFFFF # macro +RLC_SERDES_RD_DATA_2__DATA__SHIFT = 0x0 # macro +RLC_SERDES_RD_DATA_2__DATA_MASK = 0xFFFFFFFF # macro +RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT = 0x0 # macro +RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK = 0xFFFFFFFF # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT = 0x0 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT = 0x10 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT = 0x11 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT = 0x12 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT = 0x13 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT = 0x14 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT = 0x15 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT = 0x16 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT = 0x17 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK__SHIFT = 0x18 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK__SHIFT = 0x19 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT = 0x1a # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK = 0x0000FFFF # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK = 0x00010000 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK = 0x00020000 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK = 0x00040000 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK = 0x00080000 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK = 0x00100000 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK = 0x00200000 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK = 0x00400000 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK = 0x00800000 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK_MASK = 0x01000000 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK_MASK = 0x02000000 # macro +RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK = 0xFC000000 # macro +RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT = 0x0 # macro +RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT = 0x8 # macro +RLC_SERDES_WR_CTRL__POWER_UP__SHIFT = 0x9 # macro +RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT = 0xa # macro +RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT = 0xb # macro +RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT = 0xc # macro +RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT = 0xd # macro +RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT = 0xe # macro +RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT = 0xf # macro +RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT = 0x10 # macro +RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT = 0x1a # macro +RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT = 0x1b # macro +RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT = 0x1c # macro +RLC_SERDES_WR_CTRL__BPM_ADDR_MASK = 0x000000FF # macro +RLC_SERDES_WR_CTRL__POWER_DOWN_MASK = 0x00000100 # macro +RLC_SERDES_WR_CTRL__POWER_UP_MASK = 0x00000200 # macro +RLC_SERDES_WR_CTRL__P1_SELECT_MASK = 0x00000400 # macro +RLC_SERDES_WR_CTRL__P2_SELECT_MASK = 0x00000800 # macro +RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK = 0x00001000 # macro +RLC_SERDES_WR_CTRL__READ_COMMAND_MASK = 0x00002000 # macro +RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK = 0x00004000 # macro +RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK = 0x00008000 # macro +RLC_SERDES_WR_CTRL__BPM_DATA_MASK = 0x03FF0000 # macro +RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK = 0x04000000 # macro +RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK = 0x08000000 # macro +RLC_SERDES_WR_CTRL__REG_ADDR_MASK = 0xF0000000 # macro +RLC_SERDES_WR_DATA__DATA__SHIFT = 0x0 # macro +RLC_SERDES_WR_DATA__DATA_MASK = 0xFFFFFFFF # macro +RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT = 0x0 # macro +RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK = 0xFFFFFFFF # macro +RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT = 0x0 # macro +RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT = 0x10 # macro +RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT = 0x11 # macro +RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT = 0x12 # macro +RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT = 0x13 # macro +RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT = 0x14 # macro +RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT = 0x15 # macro +RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT = 0x16 # macro +RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT = 0x17 # macro +RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY__SHIFT = 0x18 # macro +RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY__SHIFT = 0x19 # macro +RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT = 0x1a # macro +RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK = 0x0000FFFF # macro +RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK = 0x00010000 # macro +RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK = 0x00020000 # macro +RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK = 0x00040000 # macro +RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK = 0x00080000 # macro +RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK = 0x00100000 # macro +RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK = 0x00200000 # macro +RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK = 0x00400000 # macro +RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK = 0x00800000 # macro +RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY_MASK = 0x01000000 # macro +RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY_MASK = 0x02000000 # macro +RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK = 0xFC000000 # macro +RLC_GPM_GENERAL_0__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_0__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_1__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_1__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_2__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_2__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_3__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_3__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_4__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_4__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_5__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_5__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_6__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_6__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_7__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_7__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT = 0x0 # macro +RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT = 0x9 # macro +RLC_GPM_SCRATCH_ADDR__ADDR_MASK = 0x000001FF # macro +RLC_GPM_SCRATCH_ADDR__RESERVED_MASK = 0xFFFFFE00 # macro +RLC_GPM_SCRATCH_DATA__DATA__SHIFT = 0x0 # macro +RLC_GPM_SCRATCH_DATA__DATA_MASK = 0xFFFFFFFF # macro +RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT = 0x0 # macro +RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK = 0xFFFFFFFF # macro +RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT = 0x0 # macro +RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT = 0x4 # macro +RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT = 0x5 # macro +RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT = 0x6 # macro +RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT = 0x7 # macro +RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT = 0x8 # macro +RLC_SPM_MC_CNTL__RESERVED__SHIFT = 0xa # macro +RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK = 0x0000000F # macro +RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK = 0x00000010 # macro +RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK = 0x00000020 # macro +RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK = 0x00000040 # macro +RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK = 0x00000080 # macro +RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK = 0x00000300 # macro +RLC_SPM_MC_CNTL__RESERVED_MASK = 0xFFFFFC00 # macro +RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT = 0x0 # macro +RLC_SPM_INT_CNTL__RESERVED__SHIFT = 0x1 # macro +RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK = 0x00000001 # macro +RLC_SPM_INT_CNTL__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT = 0x0 # macro +RLC_SPM_INT_STATUS__RESERVED__SHIFT = 0x1 # macro +RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK = 0x00000001 # macro +RLC_SPM_INT_STATUS__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_SMU_MESSAGE__CMD__SHIFT = 0x0 # macro +RLC_SMU_MESSAGE__CMD_MASK = 0xFFFFFFFF # macro +RLC_GPM_LOG_SIZE__SIZE__SHIFT = 0x0 # macro +RLC_GPM_LOG_SIZE__SIZE_MASK = 0xFFFFFFFF # macro +RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT = 0x0 # macro +RLC_PG_DELAY_3__RESERVED__SHIFT = 0x8 # macro +RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK = 0x000000FF # macro +RLC_PG_DELAY_3__RESERVED_MASK = 0xFFFFFF00 # macro +RLC_GPR_REG1__DATA__SHIFT = 0x0 # macro +RLC_GPR_REG1__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPR_REG2__DATA__SHIFT = 0x0 # macro +RLC_GPR_REG2__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_LOG_CONT__CONT__SHIFT = 0x0 # macro +RLC_GPM_LOG_CONT__CONT_MASK = 0xFFFFFFFF # macro +RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT = 0x0 # macro +RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK = 0xFFFFFFFF # macro +RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT = 0x0 # macro +RLC_GPM_INT_FORCE_TH0__FORCE_MASK = 0xFFFFFFFF # macro +RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT = 0x0 # macro +RLC_GPM_INT_FORCE_TH1__FORCE_MASK = 0xFFFFFFFF # macro +RLC_SRM_CNTL__SRM_ENABLE__SHIFT = 0x0 # macro +RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT = 0x1 # macro +RLC_SRM_CNTL__RESERVED__SHIFT = 0x2 # macro +RLC_SRM_CNTL__SRM_ENABLE_MASK = 0x00000001 # macro +RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK = 0x00000002 # macro +RLC_SRM_CNTL__RESERVED_MASK = 0xFFFFFFFC # macro +RLC_SRM_ARAM_ADDR__ADDR__SHIFT = 0x0 # macro +RLC_SRM_ARAM_ADDR__RESERVED__SHIFT = 0xb # macro +RLC_SRM_ARAM_ADDR__ADDR_MASK = 0x000007FF # macro +RLC_SRM_ARAM_ADDR__RESERVED_MASK = 0xFFFFF800 # macro +RLC_SRM_ARAM_DATA__DATA__SHIFT = 0x0 # macro +RLC_SRM_ARAM_DATA__DATA_MASK = 0xFFFFFFFF # macro +RLC_SRM_DRAM_ADDR__ADDR__SHIFT = 0x0 # macro +RLC_SRM_DRAM_ADDR__RESERVED__SHIFT = 0xb # macro +RLC_SRM_DRAM_ADDR__ADDR_MASK = 0x000007FF # macro +RLC_SRM_DRAM_ADDR__RESERVED_MASK = 0xFFFFF800 # macro +RLC_SRM_DRAM_DATA__DATA__SHIFT = 0x0 # macro +RLC_SRM_DRAM_DATA__DATA_MASK = 0xFFFFFFFF # macro +RLC_SRM_GPM_COMMAND__OP__SHIFT = 0x0 # macro +RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT = 0x1 # macro +RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT = 0x2 # macro +RLC_SRM_GPM_COMMAND__SIZE__SHIFT = 0x5 # macro +RLC_SRM_GPM_COMMAND__RESERVED_16__SHIFT = 0x10 # macro +RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT = 0x11 # macro +RLC_SRM_GPM_COMMAND__RESERVED_30_29__SHIFT = 0x1d # macro +RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT = 0x1f # macro +RLC_SRM_GPM_COMMAND__OP_MASK = 0x00000001 # macro +RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK = 0x00000002 # macro +RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK = 0x0000001C # macro +RLC_SRM_GPM_COMMAND__SIZE_MASK = 0x0000FFE0 # macro +RLC_SRM_GPM_COMMAND__RESERVED_16_MASK = 0x00010000 # macro +RLC_SRM_GPM_COMMAND__START_OFFSET_MASK = 0x0FFE0000 # macro +RLC_SRM_GPM_COMMAND__RESERVED_30_29_MASK = 0x60000000 # macro +RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK = 0x80000000 # macro +RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT = 0x0 # macro +RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT = 0x1 # macro +RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT = 0x2 # macro +RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK = 0x00000001 # macro +RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK = 0x00000002 # macro +RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK = 0xFFFFFFFC # macro +RLC_SRM_RLCV_COMMAND__OP__SHIFT = 0x0 # macro +RLC_SRM_RLCV_COMMAND__INDEX_CNTL__SHIFT = 0x1 # macro +RLC_SRM_RLCV_COMMAND__INDEX_CNTL_NUM__SHIFT = 0x2 # macro +RLC_SRM_RLCV_COMMAND__SIZE__SHIFT = 0x5 # macro +RLC_SRM_RLCV_COMMAND__RESERVED_16__SHIFT = 0x10 # macro +RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT = 0x11 # macro +RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT = 0x1c # macro +RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT = 0x1f # macro +RLC_SRM_RLCV_COMMAND__OP_MASK = 0x00000001 # macro +RLC_SRM_RLCV_COMMAND__INDEX_CNTL_MASK = 0x00000002 # macro +RLC_SRM_RLCV_COMMAND__INDEX_CNTL_NUM_MASK = 0x0000001C # macro +RLC_SRM_RLCV_COMMAND__SIZE_MASK = 0x0000FFE0 # macro +RLC_SRM_RLCV_COMMAND__RESERVED_16_MASK = 0x00010000 # macro +RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK = 0x0FFE0000 # macro +RLC_SRM_RLCV_COMMAND__RESERVED1_MASK = 0x70000000 # macro +RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK = 0x80000000 # macro +RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT = 0x0 # macro +RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT = 0x1 # macro +RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT = 0x2 # macro +RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK = 0x00000001 # macro +RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK = 0x00000002 # macro +RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK = 0xFFFFFFFC # macro +RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT = 0x10 # macro +RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK = 0x0000FFFF # macro +RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK = 0xFFFF0000 # macro +RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT = 0x10 # macro +RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK = 0x0000FFFF # macro +RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK = 0xFFFF0000 # macro +RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT = 0x10 # macro +RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK = 0x0000FFFF # macro +RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK = 0xFFFF0000 # macro +RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT = 0x10 # macro +RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK = 0x0000FFFF # macro +RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK = 0xFFFF0000 # macro +RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT = 0x10 # macro +RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK = 0x0000FFFF # macro +RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK = 0xFFFF0000 # macro +RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT = 0x10 # macro +RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK = 0x0000FFFF # macro +RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK = 0xFFFF0000 # macro +RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT = 0x10 # macro +RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK = 0x0000FFFF # macro +RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK = 0xFFFF0000 # macro +RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT = 0x10 # macro +RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK = 0x0000FFFF # macro +RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK = 0xFFFF0000 # macro +RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK = 0xFFFFFFFF # macro +RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK = 0xFFFFFFFF # macro +RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK = 0xFFFFFFFF # macro +RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK = 0xFFFFFFFF # macro +RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK = 0xFFFFFFFF # macro +RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK = 0xFFFFFFFF # macro +RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK = 0xFFFFFFFF # macro +RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT = 0x0 # macro +RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK = 0xFFFFFFFF # macro +RLC_SRM_STAT__SRM_BUSY__SHIFT = 0x0 # macro +RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT = 0x1 # macro +RLC_SRM_STAT__RESERVED__SHIFT = 0x2 # macro +RLC_SRM_STAT__SRM_BUSY_MASK = 0x00000001 # macro +RLC_SRM_STAT__SRM_BUSY_DELAY_MASK = 0x00000002 # macro +RLC_SRM_STAT__RESERVED_MASK = 0xFFFFFFFC # macro +RLC_SRM_GPM_ABORT__ABORT__SHIFT = 0x0 # macro +RLC_SRM_GPM_ABORT__RESERVED__SHIFT = 0x1 # macro +RLC_SRM_GPM_ABORT__ABORT_MASK = 0x00000001 # macro +RLC_SRM_GPM_ABORT__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_CSIB_ADDR_LO__ADDRESS__SHIFT = 0x0 # macro +RLC_CSIB_ADDR_LO__ADDRESS_MASK = 0xFFFFFFFF # macro +RLC_CSIB_ADDR_HI__ADDRESS__SHIFT = 0x0 # macro +RLC_CSIB_ADDR_HI__ADDRESS_MASK = 0x0000FFFF # macro +RLC_CSIB_LENGTH__LENGTH__SHIFT = 0x0 # macro +RLC_CSIB_LENGTH__LENGTH_MASK = 0xFFFFFFFF # macro +RLC_SMU_COMMAND__CMD__SHIFT = 0x0 # macro +RLC_SMU_COMMAND__CMD_MASK = 0xFFFFFFFF # macro +RLC_CP_SCHEDULERS__scheduler0__SHIFT = 0x0 # macro +RLC_CP_SCHEDULERS__scheduler1__SHIFT = 0x8 # macro +RLC_CP_SCHEDULERS__scheduler2__SHIFT = 0x10 # macro +RLC_CP_SCHEDULERS__scheduler3__SHIFT = 0x18 # macro +RLC_CP_SCHEDULERS__scheduler0_MASK = 0x000000FF # macro +RLC_CP_SCHEDULERS__scheduler1_MASK = 0x0000FF00 # macro +RLC_CP_SCHEDULERS__scheduler2_MASK = 0x00FF0000 # macro +RLC_CP_SCHEDULERS__scheduler3_MASK = 0xFF000000 # macro +RLC_SMU_ARGUMENT_1__ARG__SHIFT = 0x0 # macro +RLC_SMU_ARGUMENT_1__ARG_MASK = 0xFFFFFFFF # macro +RLC_SMU_ARGUMENT_2__ARG__SHIFT = 0x0 # macro +RLC_SMU_ARGUMENT_2__ARG_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_8__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_8__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_9__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_9__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_10__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_10__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_11__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_11__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_12__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_12__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT = 0x0 # macro +RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT = 0x18 # macro +RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT = 0x19 # macro +RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT = 0x1a # macro +RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT = 0x1b # macro +RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT = 0x1c # macro +RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK = 0x000FFFFF # macro +RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK = 0x01000000 # macro +RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK = 0x02000000 # macro +RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK = 0x04000000 # macro +RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK = 0x08000000 # macro +RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK = 0x10000000 # macro +RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT = 0x0 # macro +RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT = 0x18 # macro +RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT = 0x19 # macro +RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT = 0x1a # macro +RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT = 0x1b # macro +RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT = 0x1c # macro +RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK = 0x000FFFFF # macro +RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK = 0x01000000 # macro +RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK = 0x02000000 # macro +RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK = 0x04000000 # macro +RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK = 0x08000000 # macro +RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK = 0x10000000 # macro +RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT = 0x0 # macro +RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT = 0x18 # macro +RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT = 0x19 # macro +RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT = 0x1a # macro +RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT = 0x1b # macro +RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT = 0x1c # macro +RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK = 0x000FFFFF # macro +RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK = 0x01000000 # macro +RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK = 0x02000000 # macro +RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK = 0x04000000 # macro +RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK = 0x08000000 # macro +RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK = 0x10000000 # macro +RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT = 0x0 # macro +RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT = 0x18 # macro +RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT = 0x19 # macro +RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT = 0x1a # macro +RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT = 0x1b # macro +RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT = 0x1c # macro +RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK = 0x000FFFFF # macro +RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK = 0x01000000 # macro +RLC_SPM_UTCL1_CNTL__RESERVED_MASK = 0x02000000 # macro +RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK = 0x04000000 # macro +RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK = 0x08000000 # macro +RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK = 0x10000000 # macro +RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT = 0x0 # macro +RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT = 0x1 # macro +RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT = 0x2 # macro +RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT = 0x3 # macro +RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT = 0x4 # macro +RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT = 0x5 # macro +RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT = 0x6 # macro +RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT = 0x7 # macro +RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT = 0x8 # macro +RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT = 0x9 # macro +RLC_UTCL1_STATUS_2__RESERVED__SHIFT = 0xa # macro +RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK = 0x00000001 # macro +RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK = 0x00000002 # macro +RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK = 0x00000004 # macro +RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK = 0x00000008 # macro +RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK = 0x00000010 # macro +RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK = 0x00000020 # macro +RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK = 0x00000040 # macro +RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK = 0x00000080 # macro +RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK = 0x00000100 # macro +RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK = 0x00000200 # macro +RLC_UTCL1_STATUS_2__RESERVED_MASK = 0xFFFFFC00 # macro +RLC_LB_THR_CONFIG_2__DATA__SHIFT = 0x0 # macro +RLC_LB_THR_CONFIG_2__DATA_MASK = 0xFFFFFFFF # macro +RLC_LB_THR_CONFIG_3__DATA__SHIFT = 0x0 # macro +RLC_LB_THR_CONFIG_3__DATA_MASK = 0xFFFFFFFF # macro +RLC_LB_THR_CONFIG_4__DATA__SHIFT = 0x0 # macro +RLC_LB_THR_CONFIG_4__DATA_MASK = 0xFFFFFFFF # macro +RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT = 0x0 # macro +RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT = 0x2 # macro +RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT = 0x6 # macro +RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK = 0x00000003 # macro +RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK = 0x0000003C # macro +RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK = 0x000003C0 # macro +RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT = 0x0 # macro +RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK = 0xFFFFFFFF # macro +RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT = 0x0 # macro +RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT = 0x2 # macro +RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT = 0x6 # macro +RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK = 0x00000003 # macro +RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK = 0x0000003C # macro +RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK = 0x000003C0 # macro +RLC_LB_THR_CONFIG_1__DATA__SHIFT = 0x0 # macro +RLC_LB_THR_CONFIG_1__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT = 0x0 # macro +RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK = 0xFFFFFFFF # macro +RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT = 0x0 # macro +RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT = 0x2 # macro +RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT = 0x6 # macro +RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK = 0x00000003 # macro +RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK = 0x0000003C # macro +RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK = 0x000003C0 # macro +RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT = 0x0 # macro +RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK = 0xFFFFFFFF # macro +RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT = 0x0 # macro +RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT = 0x2 # macro +RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT = 0x6 # macro +RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK = 0x00000003 # macro +RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK = 0x0000003C # macro +RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK = 0x000003C0 # macro +RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT = 0x0 # macro +RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK = 0xFFFFFFFF # macro +RLC_SEMAPHORE_0__CLIENT_ID__SHIFT = 0x0 # macro +RLC_SEMAPHORE_0__RESERVED__SHIFT = 0x5 # macro +RLC_SEMAPHORE_0__CLIENT_ID_MASK = 0x0000001F # macro +RLC_SEMAPHORE_0__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_SEMAPHORE_1__CLIENT_ID__SHIFT = 0x0 # macro +RLC_SEMAPHORE_1__RESERVED__SHIFT = 0x5 # macro +RLC_SEMAPHORE_1__CLIENT_ID_MASK = 0x0000001F # macro +RLC_SEMAPHORE_1__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_CP_EOF_INT__INTERRUPT__SHIFT = 0x0 # macro +RLC_CP_EOF_INT__RESERVED__SHIFT = 0x1 # macro +RLC_CP_EOF_INT__INTERRUPT_MASK = 0x00000001 # macro +RLC_CP_EOF_INT__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_CP_EOF_INT_CNT__CNT__SHIFT = 0x0 # macro +RLC_CP_EOF_INT_CNT__CNT_MASK = 0xFFFFFFFF # macro +RLC_SPARE_INT__INTERRUPT__SHIFT = 0x0 # macro +RLC_SPARE_INT__RESERVED__SHIFT = 0x1 # macro +RLC_SPARE_INT__INTERRUPT_MASK = 0x00000001 # macro +RLC_SPARE_INT__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT = 0x0 # macro +RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT = 0x18 # macro +RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT = 0x19 # macro +RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT = 0x1a # macro +RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT = 0x1b # macro +RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT = 0x1c # macro +RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK = 0x000FFFFF # macro +RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK = 0x01000000 # macro +RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK = 0x02000000 # macro +RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK = 0x04000000 # macro +RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK = 0x08000000 # macro +RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK = 0x10000000 # macro +RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT = 0x0 # macro +RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT = 0x1 # macro +RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT = 0x5 # macro +RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT = 0x6 # macro +RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT = 0x7 # macro +RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT = 0x8 # macro +RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT = 0x9 # macro +RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT = 0x1f # macro +RLC_PREWALKER_UTCL1_TRIG__VALID_MASK = 0x00000001 # macro +RLC_PREWALKER_UTCL1_TRIG__VMID_MASK = 0x0000001E # macro +RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK = 0x00000020 # macro +RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK = 0x00000040 # macro +RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK = 0x00000080 # macro +RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK = 0x00000100 # macro +RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK = 0x7FFFFE00 # macro +RLC_PREWALKER_UTCL1_TRIG__READY_MASK = 0x80000000 # macro +RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT = 0x0 # macro +RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK = 0xFFFFFFFF # macro +RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT = 0x0 # macro +RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK = 0x0000FFFF # macro +RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT = 0x0 # macro +RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK = 0xFFFFFFFF # macro +RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT = 0x0 # macro +RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK = 0x00000003 # macro +RLC_DSM_TRIG__START__SHIFT = 0x0 # macro +RLC_DSM_TRIG__START_MASK = 0x00000001 # macro +RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT = 0x0 # macro +RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT = 0x1 # macro +RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT = 0x2 # macro +RLC_UTCL1_STATUS__RESERVED__SHIFT = 0x3 # macro +RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT = 0x8 # macro +RLC_UTCL1_STATUS__RESERVED_1__SHIFT = 0xe # macro +RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT = 0x10 # macro +RLC_UTCL1_STATUS__RESERVED_2__SHIFT = 0x16 # macro +RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT = 0x18 # macro +RLC_UTCL1_STATUS__RESERVED_3__SHIFT = 0x1e # macro +RLC_UTCL1_STATUS__FAULT_DETECTED_MASK = 0x00000001 # macro +RLC_UTCL1_STATUS__RETRY_DETECTED_MASK = 0x00000002 # macro +RLC_UTCL1_STATUS__PRT_DETECTED_MASK = 0x00000004 # macro +RLC_UTCL1_STATUS__RESERVED_MASK = 0x000000F8 # macro +RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK = 0x00003F00 # macro +RLC_UTCL1_STATUS__RESERVED_1_MASK = 0x0000C000 # macro +RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK = 0x003F0000 # macro +RLC_UTCL1_STATUS__RESERVED_2_MASK = 0x00C00000 # macro +RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK = 0x3F000000 # macro +RLC_UTCL1_STATUS__RESERVED_3_MASK = 0xC0000000 # macro +RLC_R2I_CNTL_0__Data__SHIFT = 0x0 # macro +RLC_R2I_CNTL_0__Data_MASK = 0xFFFFFFFF # macro +RLC_R2I_CNTL_1__Data__SHIFT = 0x0 # macro +RLC_R2I_CNTL_1__Data_MASK = 0xFFFFFFFF # macro +RLC_R2I_CNTL_2__Data__SHIFT = 0x0 # macro +RLC_R2I_CNTL_2__Data_MASK = 0xFFFFFFFF # macro +RLC_R2I_CNTL_3__Data__SHIFT = 0x0 # macro +RLC_R2I_CNTL_3__Data_MASK = 0xFFFFFFFF # macro +RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT = 0x0 # macro +RLC_UTCL2_CNTL__IGNORE_PTE_PERMISSION__SHIFT = 0x1 # macro +RLC_UTCL2_CNTL__RESERVED__SHIFT = 0x2 # macro +RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK = 0x00000001 # macro +RLC_UTCL2_CNTL__IGNORE_PTE_PERMISSION_MASK = 0x00000002 # macro +RLC_UTCL2_CNTL__RESERVED_MASK = 0xFFFFFFFC # macro +RLC_LBPW_CU_STAT__MAX_CU__SHIFT = 0x0 # macro +RLC_LBPW_CU_STAT__ON_CU__SHIFT = 0x10 # macro +RLC_LBPW_CU_STAT__MAX_CU_MASK = 0x0000FFFF # macro +RLC_LBPW_CU_STAT__ON_CU_MASK = 0xFFFF0000 # macro +RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT = 0x0 # macro +RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT = 0x1 # macro +RLC_DS_CNTL__GFX_CLK_TCC_RLC_GRBM_CC_RESIDENT_MASK__SHIFT = 0x2 # macro +RLC_DS_CNTL__GFX_CLK_EA_RLC_GRBM_STAT_BUSY_MASK__SHIFT = 0x3 # macro +RLC_DS_CNTL__RESRVED__SHIFT = 0x4 # macro +RLC_DS_CNTL__SOC_CLK_TCC_RLC_GRBM_CC_RESIDENT_MASK__SHIFT = 0xe # macro +RLC_DS_CNTL__SOC_CLK_EA_RLC_GRBM_STAT_BUSY_MASK__SHIFT = 0xf # macro +RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT = 0x10 # macro +RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT = 0x11 # macro +RLC_DS_CNTL__RESRVED_1__SHIFT = 0x12 # macro +RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK = 0x00000001 # macro +RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK = 0x00000002 # macro +RLC_DS_CNTL__GFX_CLK_TCC_RLC_GRBM_CC_RESIDENT_MASK_MASK = 0x00000004 # macro +RLC_DS_CNTL__GFX_CLK_EA_RLC_GRBM_STAT_BUSY_MASK_MASK = 0x00000008 # macro +RLC_DS_CNTL__RESRVED_MASK = 0x00003FF0 # macro +RLC_DS_CNTL__SOC_CLK_TCC_RLC_GRBM_CC_RESIDENT_MASK_MASK = 0x00004000 # macro +RLC_DS_CNTL__SOC_CLK_EA_RLC_GRBM_STAT_BUSY_MASK_MASK = 0x00008000 # macro +RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK = 0x00010000 # macro +RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK = 0x00020000 # macro +RLC_DS_CNTL__RESRVED_1_MASK = 0xFFFC0000 # macro +RLC_GPM_INT_STAT_TH0__STATUS__SHIFT = 0x0 # macro +RLC_GPM_INT_STAT_TH0__STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_13__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_13__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_14__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_14__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPM_GENERAL_15__DATA__SHIFT = 0x0 # macro +RLC_GPM_GENERAL_15__DATA_MASK = 0xFFFFFFFF # macro +RLC_SPARE_INT_1__INTERRUPT__SHIFT = 0x0 # macro +RLC_SPARE_INT_1__RESERVED__SHIFT = 0x1 # macro +RLC_SPARE_INT_1__INTERRUPT_MASK = 0x00000001 # macro +RLC_SPARE_INT_1__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_RLCV_SPARE_INT_1__INTERRUPT__SHIFT = 0x0 # macro +RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT = 0x1 # macro +RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK = 0x00000001 # macro +RLC_RLCV_SPARE_INT_1__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_SEMAPHORE_2__CLIENT_ID__SHIFT = 0x0 # macro +RLC_SEMAPHORE_2__RESERVED__SHIFT = 0x5 # macro +RLC_SEMAPHORE_2__CLIENT_ID_MASK = 0x0000001F # macro +RLC_SEMAPHORE_2__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_SEMAPHORE_3__CLIENT_ID__SHIFT = 0x0 # macro +RLC_SEMAPHORE_3__RESERVED__SHIFT = 0x5 # macro +RLC_SEMAPHORE_3__CLIENT_ID_MASK = 0x0000001F # macro +RLC_SEMAPHORE_3__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_SMU_ARGUMENT_3__ARG__SHIFT = 0x0 # macro +RLC_SMU_ARGUMENT_3__ARG_MASK = 0xFFFFFFFF # macro +RLC_SMU_ARGUMENT_4__ARG__SHIFT = 0x0 # macro +RLC_SMU_ARGUMENT_4__ARG_MASK = 0xFFFFFFFF # macro +RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB__SHIFT = 0x0 # macro +RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB_MASK = 0xFFFFFFFF # macro +RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB__SHIFT = 0x0 # macro +RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB_MASK = 0xFFFFFFFF # macro +RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE__SHIFT = 0x0 # macro +RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED__SHIFT = 0x1 # macro +RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE_MASK = 0x00000001 # macro +RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB__SHIFT = 0x0 # macro +RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB_MASK = 0xFFFFFFFF # macro +RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB__SHIFT = 0x0 # macro +RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB_MASK = 0xFFFFFFFF # macro +RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE__SHIFT = 0x0 # macro +RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED__SHIFT = 0x1 # macro +RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE_MASK = 0x00000001 # macro +RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_CPG_STAT_INVAL__CPG_stat_inval__SHIFT = 0x0 # macro +RLC_CPG_STAT_INVAL__CPG_stat_inval_MASK = 0x00000001 # macro +RLC_UE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +RLC_UE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +RLC_UE_ERR_STATUS_LOW__ADDRESS__SHIFT = 0x2 # macro +RLC_UE_ERR_STATUS_LOW__MEMORY_ID__SHIFT = 0x18 # macro +RLC_UE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +RLC_UE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +RLC_UE_ERR_STATUS_LOW__ADDRESS_MASK = 0x00FFFFFC # macro +RLC_UE_ERR_STATUS_LOW__MEMORY_ID_MASK = 0xFF000000 # macro +RLC_UE_ERR_STATUS_HIGH__ECC__SHIFT = 0x0 # macro +RLC_UE_ERR_STATUS_HIGH__PARITY__SHIFT = 0x1 # macro +RLC_UE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +RLC_UE_ERR_STATUS_HIGH__ERR_INFO__SHIFT = 0x3 # macro +RLC_UE_ERR_STATUS_HIGH__UE_CNT__SHIFT = 0x17 # macro +RLC_UE_ERR_STATUS_HIGH__FED_CNT__SHIFT = 0x1a # macro +RLC_UE_ERR_STATUS_HIGH__RESERVED__SHIFT = 0x1d # macro +RLC_UE_ERR_STATUS_HIGH__ECC_MASK = 0x00000001 # macro +RLC_UE_ERR_STATUS_HIGH__PARITY_MASK = 0x00000002 # macro +RLC_UE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +RLC_UE_ERR_STATUS_HIGH__ERR_INFO_MASK = 0x007FFFF8 # macro +RLC_UE_ERR_STATUS_HIGH__UE_CNT_MASK = 0x03800000 # macro +RLC_UE_ERR_STATUS_HIGH__FED_CNT_MASK = 0x1C000000 # macro +RLC_UE_ERR_STATUS_HIGH__RESERVED_MASK = 0xE0000000 # macro +RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_DATA_SEL__SHIFT = 0x0 # macro +RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT = 0x2 # macro +RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT = 0x3 # macro +RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT = 0x5 # macro +RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_DATA_SEL__SHIFT = 0x6 # macro +RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT = 0x8 # macro +RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT = 0x9 # macro +RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT = 0xb # macro +RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_DATA_SEL__SHIFT = 0xc # macro +RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_SINGLE_WRITE__SHIFT = 0xe # macro +RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT = 0xf # macro +RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT = 0x11 # macro +RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_DATA_SEL__SHIFT = 0x12 # macro +RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_SINGLE_WRITE__SHIFT = 0x14 # macro +RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_DATA_SEL__SHIFT = 0x15 # macro +RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT = 0x17 # macro +RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_DATA_SEL_MASK = 0x00000003 # macro +RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_SINGLE_WRITE_MASK = 0x00000004 # macro +RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK = 0x00000018 # macro +RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK = 0x00000020 # macro +RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_DATA_SEL_MASK = 0x000000C0 # macro +RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_SINGLE_WRITE_MASK = 0x00000100 # macro +RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK = 0x00000600 # macro +RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK = 0x00000800 # macro +RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_DATA_SEL_MASK = 0x00003000 # macro +RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_SINGLE_WRITE_MASK = 0x00004000 # macro +RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK = 0x00018000 # macro +RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK = 0x00020000 # macro +RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_DATA_SEL_MASK = 0x000C0000 # macro +RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_SINGLE_WRITE_MASK = 0x00100000 # macro +RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_DATA_SEL_MASK = 0x00600000 # macro +RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_SINGLE_WRITE_MASK = 0x00800000 # macro +RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT = 0x0 # macro +RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT = 0x2 # macro +RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT = 0x3 # macro +RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT = 0x5 # macro +RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT = 0x6 # macro +RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT = 0x8 # macro +RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT = 0x9 # macro +RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT = 0xb # macro +RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK = 0x00000003 # macro +RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK = 0x00000004 # macro +RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK = 0x00000018 # macro +RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK = 0x00000020 # macro +RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK = 0x000000C0 # macro +RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK = 0x00000100 # macro +RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK = 0x00000600 # macro +RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK = 0x00000800 # macro +RLC_DSM_CNTL2__RLCG_INSTR_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +RLC_DSM_CNTL2__RLCG_INSTR_RAM_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +RLC_DSM_CNTL2__RLCV_INSTR_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x6 # macro +RLC_DSM_CNTL2__RLCV_INSTR_RAM_SELECT_INJECT_DELAY__SHIFT = 0x8 # macro +RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT = 0xb # macro +RLC_DSM_CNTL2__RLC_TCTAG_RAM_ENABLE_ERROR_INJECT__SHIFT = 0xc # macro +RLC_DSM_CNTL2__RLC_TCTAG_RAM_SELECT_INJECT_DELAY__SHIFT = 0xe # macro +RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT = 0xf # macro +RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT = 0x11 # macro +RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x12 # macro +RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_SELECT_INJECT_DELAY__SHIFT = 0x14 # macro +RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x15 # macro +RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_SELECT_INJECT_DELAY__SHIFT = 0x17 # macro +RLC_DSM_CNTL2__INJECT_DELAY__SHIFT = 0x1a # macro +RLC_DSM_CNTL2__RLCG_INSTR_RAM_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +RLC_DSM_CNTL2__RLCG_INSTR_RAM_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +RLC_DSM_CNTL2__RLCV_INSTR_RAM_ENABLE_ERROR_INJECT_MASK = 0x000000C0 # macro +RLC_DSM_CNTL2__RLCV_INSTR_RAM_SELECT_INJECT_DELAY_MASK = 0x00000100 # macro +RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +RLC_DSM_CNTL2__RLC_TCTAG_RAM_ENABLE_ERROR_INJECT_MASK = 0x00003000 # macro +RLC_DSM_CNTL2__RLC_TCTAG_RAM_SELECT_INJECT_DELAY_MASK = 0x00004000 # macro +RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK = 0x00018000 # macro +RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK = 0x00020000 # macro +RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_ENABLE_ERROR_INJECT_MASK = 0x000C0000 # macro +RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_SELECT_INJECT_DELAY_MASK = 0x00100000 # macro +RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_ENABLE_ERROR_INJECT_MASK = 0x00600000 # macro +RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_SELECT_INJECT_DELAY_MASK = 0x00800000 # macro +RLC_DSM_CNTL2__INJECT_DELAY_MASK = 0xFC000000 # macro +RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x0 # macro +RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT = 0x2 # macro +RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x3 # macro +RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT = 0x5 # macro +RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x6 # macro +RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT = 0x8 # macro +RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT = 0x9 # macro +RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT = 0xb # macro +RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK = 0x00000003 # macro +RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK = 0x00000004 # macro +RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK = 0x00000018 # macro +RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK = 0x00000020 # macro +RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK = 0x000000C0 # macro +RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK = 0x00000100 # macro +RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK = 0x00000600 # macro +RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK = 0x00000800 # macro +RLC_CE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG__SHIFT = 0x0 # macro +RLC_CE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG__SHIFT = 0x1 # macro +RLC_CE_ERR_STATUS_LOW__ADDRESS__SHIFT = 0x2 # macro +RLC_CE_ERR_STATUS_LOW__MEMORY_ID__SHIFT = 0x18 # macro +RLC_CE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG_MASK = 0x00000001 # macro +RLC_CE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG_MASK = 0x00000002 # macro +RLC_CE_ERR_STATUS_LOW__ADDRESS_MASK = 0x00FFFFFC # macro +RLC_CE_ERR_STATUS_LOW__MEMORY_ID_MASK = 0xFF000000 # macro +RLC_CE_ERR_STATUS_HIGH__ECC__SHIFT = 0x0 # macro +RLC_CE_ERR_STATUS_HIGH__OTHER__SHIFT = 0x1 # macro +RLC_CE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG__SHIFT = 0x2 # macro +RLC_CE_ERR_STATUS_HIGH__ERR_INFO__SHIFT = 0x3 # macro +RLC_CE_ERR_STATUS_HIGH__CE_CNT__SHIFT = 0x17 # macro +RLC_CE_ERR_STATUS_HIGH__POISON__SHIFT = 0x1a # macro +RLC_CE_ERR_STATUS_HIGH__RESERVED__SHIFT = 0x1b # macro +RLC_CE_ERR_STATUS_HIGH__ECC_MASK = 0x00000001 # macro +RLC_CE_ERR_STATUS_HIGH__OTHER_MASK = 0x00000002 # macro +RLC_CE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG_MASK = 0x00000004 # macro +RLC_CE_ERR_STATUS_HIGH__ERR_INFO_MASK = 0x007FFFF8 # macro +RLC_CE_ERR_STATUS_HIGH__CE_CNT_MASK = 0x03800000 # macro +RLC_CE_ERR_STATUS_HIGH__POISON_MASK = 0x04000000 # macro +RLC_CE_ERR_STATUS_HIGH__RESERVED_MASK = 0xF8000000 # macro +RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT = 0x0 # macro +RLC_RLCV_SPARE_INT__RESERVED__SHIFT = 0x1 # macro +RLC_RLCV_SPARE_INT__INTERRUPT_MASK = 0x00000001 # macro +RLC_RLCV_SPARE_INT__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_SMU_CLK_REQ__VALID__SHIFT = 0x0 # macro +RLC_SMU_CLK_REQ__VALID_MASK = 0x00000001 # macro +CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT = 0x0 # macro +CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT = 0x4 # macro +CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT = 0xc # macro +CGTS_SM_CTRL_REG__BASE_MODE__SHIFT = 0x10 # macro +CGTS_SM_CTRL_REG__SM_MODE__SHIFT = 0x11 # macro +CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT = 0x14 # macro +CGTS_SM_CTRL_REG__OVERRIDE__SHIFT = 0x15 # macro +CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT = 0x16 # macro +CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT = 0x17 # macro +CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT = 0x18 # macro +CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK = 0x0000000F # macro +CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK = 0x00000FF0 # macro +CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK = 0x00001000 # macro +CGTS_SM_CTRL_REG__BASE_MODE_MASK = 0x00010000 # macro +CGTS_SM_CTRL_REG__SM_MODE_MASK = 0x000E0000 # macro +CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK = 0x00100000 # macro +CGTS_SM_CTRL_REG__OVERRIDE_MASK = 0x00200000 # macro +CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK = 0x00400000 # macro +CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK = 0x00800000 # macro +CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK = 0xFF000000 # macro +CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT = 0x0 # macro +CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT = 0x8 # macro +CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK = 0x0000001F # macro +CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK = 0x00001F00 # macro +CGTS_RD_REG__READ_DATA__SHIFT = 0x0 # macro +CGTS_RD_REG__READ_DATA_MASK = 0x00003FFF # macro +CGTS_TCC_DISABLE__WRITE_DIS__SHIFT = 0x0 # macro +CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT = 0x10 # macro +CGTS_TCC_DISABLE__WRITE_DIS_MASK = 0x00000001 # macro +CGTS_TCC_DISABLE__TCC_DISABLE_MASK = 0xFFFF0000 # macro +CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT = 0x10 # macro +CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK = 0xFFFF0000 # macro +CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT = 0x0 # macro +CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT = 0x10 # macro +CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU0_SP0_CTRL_REG__SP00_MASK = 0x0000007F # macro +CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU0_SP0_CTRL_REG__SP01_MASK = 0x007F0000 # macro +CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT = 0x0 # macro +CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT = 0x10 # macro +CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK = 0x0000007F # macro +CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK = 0x007F0000 # macro +CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT = 0x0 # macro +CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT = 0x10 # macro +CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK = 0x0000007F # macro +CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK = 0x007F0000 # macro +CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT = 0x0 # macro +CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT = 0x10 # macro +CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU0_SP1_CTRL_REG__SP10_MASK = 0x0000007F # macro +CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU0_SP1_CTRL_REG__SP11_MASK = 0x007F0000 # macro +CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT = 0x0 # macro +CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU0_TD_TCP_CTRL_REG__TCPF__SHIFT = 0x10 # macro +CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK = 0x0000007F # macro +CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU0_TD_TCP_CTRL_REG__TCPF_MASK = 0x007F0000 # macro +CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT = 0x0 # macro +CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT = 0x10 # macro +CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU1_SP0_CTRL_REG__SP00_MASK = 0x0000007F # macro +CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU1_SP0_CTRL_REG__SP01_MASK = 0x007F0000 # macro +CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT = 0x0 # macro +CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT = 0x10 # macro +CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK = 0x0000007F # macro +CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK = 0x007F0000 # macro +CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU1_TA_SQC_CTRL_REG__TA__SHIFT = 0x0 # macro +CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU1_TA_SQC_CTRL_REG__TA_MASK = 0x0000007F # macro +CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT = 0x0 # macro +CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT = 0x10 # macro +CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU1_SP1_CTRL_REG__SP10_MASK = 0x0000007F # macro +CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU1_SP1_CTRL_REG__SP11_MASK = 0x007F0000 # macro +CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT = 0x0 # macro +CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU1_TD_TCP_CTRL_REG__TCPF__SHIFT = 0x10 # macro +CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK = 0x0000007F # macro +CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU1_TD_TCP_CTRL_REG__TCPF_MASK = 0x007F0000 # macro +CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT = 0x0 # macro +CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT = 0x10 # macro +CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU2_SP0_CTRL_REG__SP00_MASK = 0x0000007F # macro +CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU2_SP0_CTRL_REG__SP01_MASK = 0x007F0000 # macro +CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT = 0x0 # macro +CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT = 0x10 # macro +CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK = 0x0000007F # macro +CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK = 0x007F0000 # macro +CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU2_TA_SQC_CTRL_REG__TA__SHIFT = 0x0 # macro +CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU2_TA_SQC_CTRL_REG__SQC__SHIFT = 0x10 # macro +CGTS_CU2_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU2_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU2_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU2_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU2_TA_SQC_CTRL_REG__TA_MASK = 0x0000007F # macro +CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU2_TA_SQC_CTRL_REG__SQC_MASK = 0x007F0000 # macro +CGTS_CU2_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU2_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU2_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU2_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT = 0x0 # macro +CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT = 0x10 # macro +CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU2_SP1_CTRL_REG__SP10_MASK = 0x0000007F # macro +CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU2_SP1_CTRL_REG__SP11_MASK = 0x007F0000 # macro +CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT = 0x0 # macro +CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU2_TD_TCP_CTRL_REG__TCPF__SHIFT = 0x10 # macro +CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK = 0x0000007F # macro +CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU2_TD_TCP_CTRL_REG__TCPF_MASK = 0x007F0000 # macro +CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT = 0x0 # macro +CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT = 0x10 # macro +CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU3_SP0_CTRL_REG__SP00_MASK = 0x0000007F # macro +CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU3_SP0_CTRL_REG__SP01_MASK = 0x007F0000 # macro +CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT = 0x0 # macro +CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT = 0x10 # macro +CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK = 0x0000007F # macro +CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK = 0x007F0000 # macro +CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU3_TA_SQC_CTRL_REG__TA__SHIFT = 0x0 # macro +CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU3_TA_SQC_CTRL_REG__TA_MASK = 0x0000007F # macro +CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT = 0x0 # macro +CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT = 0x10 # macro +CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU3_SP1_CTRL_REG__SP10_MASK = 0x0000007F # macro +CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU3_SP1_CTRL_REG__SP11_MASK = 0x007F0000 # macro +CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT = 0x0 # macro +CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU3_TD_TCP_CTRL_REG__TCPF__SHIFT = 0x10 # macro +CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK = 0x0000007F # macro +CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU3_TD_TCP_CTRL_REG__TCPF_MASK = 0x007F0000 # macro +CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT = 0x0 # macro +CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT = 0x10 # macro +CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU4_SP0_CTRL_REG__SP00_MASK = 0x0000007F # macro +CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU4_SP0_CTRL_REG__SP01_MASK = 0x007F0000 # macro +CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT = 0x0 # macro +CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT = 0x10 # macro +CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK = 0x0000007F # macro +CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK = 0x007F0000 # macro +CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT = 0x0 # macro +CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT = 0x10 # macro +CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK = 0x0000007F # macro +CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK = 0x007F0000 # macro +CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT = 0x0 # macro +CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT = 0x10 # macro +CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU4_SP1_CTRL_REG__SP10_MASK = 0x0000007F # macro +CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU4_SP1_CTRL_REG__SP11_MASK = 0x007F0000 # macro +CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT = 0x0 # macro +CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU4_TD_TCP_CTRL_REG__TCPF__SHIFT = 0x10 # macro +CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK = 0x0000007F # macro +CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU4_TD_TCP_CTRL_REG__TCPF_MASK = 0x007F0000 # macro +CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT = 0x0 # macro +CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT = 0x10 # macro +CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU5_SP0_CTRL_REG__SP00_MASK = 0x0000007F # macro +CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU5_SP0_CTRL_REG__SP01_MASK = 0x007F0000 # macro +CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT = 0x0 # macro +CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT = 0x10 # macro +CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK = 0x0000007F # macro +CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK = 0x007F0000 # macro +CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU5_TA_SQC_CTRL_REG__TA__SHIFT = 0x0 # macro +CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU5_TA_SQC_CTRL_REG__TA_MASK = 0x0000007F # macro +CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT = 0x0 # macro +CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT = 0x10 # macro +CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU5_SP1_CTRL_REG__SP10_MASK = 0x0000007F # macro +CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU5_SP1_CTRL_REG__SP11_MASK = 0x007F0000 # macro +CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT = 0x0 # macro +CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU5_TD_TCP_CTRL_REG__TCPF__SHIFT = 0x10 # macro +CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK = 0x0000007F # macro +CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU5_TD_TCP_CTRL_REG__TCPF_MASK = 0x007F0000 # macro +CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT = 0x0 # macro +CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT = 0x10 # macro +CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU6_SP0_CTRL_REG__SP00_MASK = 0x0000007F # macro +CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU6_SP0_CTRL_REG__SP01_MASK = 0x007F0000 # macro +CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT = 0x0 # macro +CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT = 0x10 # macro +CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK = 0x0000007F # macro +CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK = 0x007F0000 # macro +CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU6_TA_SQC_CTRL_REG__TA__SHIFT = 0x0 # macro +CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU6_TA_SQC_CTRL_REG__SQC__SHIFT = 0x10 # macro +CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU6_TA_SQC_CTRL_REG__TA_MASK = 0x0000007F # macro +CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU6_TA_SQC_CTRL_REG__SQC_MASK = 0x007F0000 # macro +CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT = 0x0 # macro +CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT = 0x10 # macro +CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU6_SP1_CTRL_REG__SP10_MASK = 0x0000007F # macro +CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU6_SP1_CTRL_REG__SP11_MASK = 0x007F0000 # macro +CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT = 0x0 # macro +CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU6_TD_TCP_CTRL_REG__TCPF__SHIFT = 0x10 # macro +CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK = 0x0000007F # macro +CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU6_TD_TCP_CTRL_REG__TCPF_MASK = 0x007F0000 # macro +CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT = 0x0 # macro +CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT = 0x10 # macro +CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU7_SP0_CTRL_REG__SP00_MASK = 0x0000007F # macro +CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU7_SP0_CTRL_REG__SP01_MASK = 0x007F0000 # macro +CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT = 0x0 # macro +CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT = 0x10 # macro +CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK = 0x0000007F # macro +CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK = 0x007F0000 # macro +CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU7_TA_SQC_CTRL_REG__TA__SHIFT = 0x0 # macro +CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU7_TA_SQC_CTRL_REG__TA_MASK = 0x0000007F # macro +CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT = 0x0 # macro +CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT = 0x10 # macro +CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU7_SP1_CTRL_REG__SP10_MASK = 0x0000007F # macro +CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU7_SP1_CTRL_REG__SP11_MASK = 0x007F0000 # macro +CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT = 0x0 # macro +CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU7_TD_TCP_CTRL_REG__TCPF__SHIFT = 0x10 # macro +CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK = 0x0000007F # macro +CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU7_TD_TCP_CTRL_REG__TCPF_MASK = 0x007F0000 # macro +CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT = 0x0 # macro +CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT = 0x10 # macro +CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU8_SP0_CTRL_REG__SP00_MASK = 0x0000007F # macro +CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU8_SP0_CTRL_REG__SP01_MASK = 0x007F0000 # macro +CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT = 0x0 # macro +CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT = 0x10 # macro +CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK = 0x0000007F # macro +CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK = 0x007F0000 # macro +CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT = 0x0 # macro +CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT = 0x10 # macro +CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK = 0x0000007F # macro +CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK = 0x007F0000 # macro +CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT = 0x0 # macro +CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT = 0x10 # macro +CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU8_SP1_CTRL_REG__SP10_MASK = 0x0000007F # macro +CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU8_SP1_CTRL_REG__SP11_MASK = 0x007F0000 # macro +CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT = 0x0 # macro +CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU8_TD_TCP_CTRL_REG__TCPF__SHIFT = 0x10 # macro +CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK = 0x0000007F # macro +CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU8_TD_TCP_CTRL_REG__TCPF_MASK = 0x007F0000 # macro +CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT = 0x0 # macro +CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT = 0x10 # macro +CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU9_SP0_CTRL_REG__SP00_MASK = 0x0000007F # macro +CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU9_SP0_CTRL_REG__SP01_MASK = 0x007F0000 # macro +CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT = 0x0 # macro +CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT = 0x10 # macro +CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK = 0x0000007F # macro +CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK = 0x007F0000 # macro +CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU9_TA_SQC_CTRL_REG__TA__SHIFT = 0x0 # macro +CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU9_TA_SQC_CTRL_REG__TA_MASK = 0x0000007F # macro +CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT = 0x0 # macro +CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT = 0x10 # macro +CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU9_SP1_CTRL_REG__SP10_MASK = 0x0000007F # macro +CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU9_SP1_CTRL_REG__SP11_MASK = 0x007F0000 # macro +CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT = 0x0 # macro +CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU9_TD_TCP_CTRL_REG__TCPF__SHIFT = 0x10 # macro +CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK = 0x0000007F # macro +CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU9_TD_TCP_CTRL_REG__TCPF_MASK = 0x007F0000 # macro +CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT = 0x0 # macro +CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT = 0x10 # macro +CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU10_SP0_CTRL_REG__SP00_MASK = 0x0000007F # macro +CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU10_SP0_CTRL_REG__SP01_MASK = 0x007F0000 # macro +CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT = 0x0 # macro +CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT = 0x10 # macro +CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK = 0x0000007F # macro +CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK = 0x007F0000 # macro +CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU10_TA_SQC_CTRL_REG__TA__SHIFT = 0x0 # macro +CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU10_TA_SQC_CTRL_REG__SQC__SHIFT = 0x10 # macro +CGTS_CU10_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU10_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU10_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU10_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU10_TA_SQC_CTRL_REG__TA_MASK = 0x0000007F # macro +CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU10_TA_SQC_CTRL_REG__SQC_MASK = 0x007F0000 # macro +CGTS_CU10_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU10_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU10_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU10_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT = 0x0 # macro +CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT = 0x10 # macro +CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU10_SP1_CTRL_REG__SP10_MASK = 0x0000007F # macro +CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU10_SP1_CTRL_REG__SP11_MASK = 0x007F0000 # macro +CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT = 0x0 # macro +CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU10_TD_TCP_CTRL_REG__TCPF__SHIFT = 0x10 # macro +CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK = 0x0000007F # macro +CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU10_TD_TCP_CTRL_REG__TCPF_MASK = 0x007F0000 # macro +CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT = 0x0 # macro +CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT = 0x10 # macro +CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU11_SP0_CTRL_REG__SP00_MASK = 0x0000007F # macro +CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU11_SP0_CTRL_REG__SP01_MASK = 0x007F0000 # macro +CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT = 0x0 # macro +CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT = 0x10 # macro +CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK = 0x0000007F # macro +CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK = 0x007F0000 # macro +CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU11_TA_SQC_CTRL_REG__TA__SHIFT = 0x0 # macro +CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU11_TA_SQC_CTRL_REG__TA_MASK = 0x0000007F # macro +CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT = 0x0 # macro +CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT = 0x10 # macro +CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU11_SP1_CTRL_REG__SP10_MASK = 0x0000007F # macro +CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU11_SP1_CTRL_REG__SP11_MASK = 0x007F0000 # macro +CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT = 0x0 # macro +CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU11_TD_TCP_CTRL_REG__TCPF__SHIFT = 0x10 # macro +CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK = 0x0000007F # macro +CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU11_TD_TCP_CTRL_REG__TCPF_MASK = 0x007F0000 # macro +CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT = 0x0 # macro +CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT = 0x10 # macro +CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU12_SP0_CTRL_REG__SP00_MASK = 0x0000007F # macro +CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU12_SP0_CTRL_REG__SP01_MASK = 0x007F0000 # macro +CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT = 0x0 # macro +CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT = 0x10 # macro +CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK = 0x0000007F # macro +CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK = 0x007F0000 # macro +CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT = 0x0 # macro +CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT = 0x10 # macro +CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK = 0x0000007F # macro +CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK = 0x007F0000 # macro +CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT = 0x0 # macro +CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT = 0x10 # macro +CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU12_SP1_CTRL_REG__SP10_MASK = 0x0000007F # macro +CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU12_SP1_CTRL_REG__SP11_MASK = 0x007F0000 # macro +CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT = 0x0 # macro +CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU12_TD_TCP_CTRL_REG__TCPF__SHIFT = 0x10 # macro +CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK = 0x0000007F # macro +CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU12_TD_TCP_CTRL_REG__TCPF_MASK = 0x007F0000 # macro +CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT = 0x0 # macro +CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT = 0x10 # macro +CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU13_SP0_CTRL_REG__SP00_MASK = 0x0000007F # macro +CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU13_SP0_CTRL_REG__SP01_MASK = 0x007F0000 # macro +CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT = 0x0 # macro +CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT = 0x10 # macro +CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK = 0x0000007F # macro +CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK = 0x007F0000 # macro +CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU13_TA_SQC_CTRL_REG__TA__SHIFT = 0x0 # macro +CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU13_TA_SQC_CTRL_REG__TA_MASK = 0x0000007F # macro +CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT = 0x0 # macro +CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT = 0x10 # macro +CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU13_SP1_CTRL_REG__SP10_MASK = 0x0000007F # macro +CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU13_SP1_CTRL_REG__SP11_MASK = 0x007F0000 # macro +CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT = 0x0 # macro +CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU13_TD_TCP_CTRL_REG__TCPF__SHIFT = 0x10 # macro +CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK = 0x0000007F # macro +CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU13_TD_TCP_CTRL_REG__TCPF_MASK = 0x007F0000 # macro +CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT = 0x0 # macro +CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT = 0x10 # macro +CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU14_SP0_CTRL_REG__SP00_MASK = 0x0000007F # macro +CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU14_SP0_CTRL_REG__SP01_MASK = 0x007F0000 # macro +CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT = 0x0 # macro +CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT = 0x10 # macro +CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK = 0x0000007F # macro +CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK = 0x007F0000 # macro +CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU14_TA_SQC_CTRL_REG__TA__SHIFT = 0x0 # macro +CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU14_TA_SQC_CTRL_REG__SQC__SHIFT = 0x10 # macro +CGTS_CU14_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU14_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU14_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU14_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU14_TA_SQC_CTRL_REG__TA_MASK = 0x0000007F # macro +CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU14_TA_SQC_CTRL_REG__SQC_MASK = 0x007F0000 # macro +CGTS_CU14_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU14_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU14_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU14_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT = 0x0 # macro +CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT = 0x10 # macro +CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU14_SP1_CTRL_REG__SP10_MASK = 0x0000007F # macro +CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU14_SP1_CTRL_REG__SP11_MASK = 0x007F0000 # macro +CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT = 0x0 # macro +CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU14_TD_TCP_CTRL_REG__TCPF__SHIFT = 0x10 # macro +CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK = 0x0000007F # macro +CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU14_TD_TCP_CTRL_REG__TCPF_MASK = 0x007F0000 # macro +CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT = 0x0 # macro +CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT = 0x10 # macro +CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU15_SP0_CTRL_REG__SP00_MASK = 0x0000007F # macro +CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU15_SP0_CTRL_REG__SP01_MASK = 0x007F0000 # macro +CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT = 0x0 # macro +CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT = 0x10 # macro +CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK = 0x0000007F # macro +CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK = 0x007F0000 # macro +CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU15_TA_SQC_CTRL_REG__TA__SHIFT = 0x0 # macro +CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU15_TA_SQC_CTRL_REG__TA_MASK = 0x0000007F # macro +CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT = 0x0 # macro +CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT = 0x10 # macro +CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU15_SP1_CTRL_REG__SP10_MASK = 0x0000007F # macro +CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU15_SP1_CTRL_REG__SP11_MASK = 0x007F0000 # macro +CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT = 0x0 # macro +CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU15_TD_TCP_CTRL_REG__TCPF__SHIFT = 0x10 # macro +CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT = 0x17 # macro +CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT = 0x18 # macro +CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT = 0x1a # macro +CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT = 0x1b # macro +CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK = 0x0000007F # macro +CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU15_TD_TCP_CTRL_REG__TCPF_MASK = 0x007F0000 # macro +CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK = 0x00800000 # macro +CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK = 0x03000000 # macro +CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK = 0x04000000 # macro +CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK = 0x08000000 # macro +CGTS_CU0_TCPI_CTRL_REG__TCPI__SHIFT = 0x0 # macro +CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU0_TCPI_CTRL_REG__RESERVED__SHIFT = 0xc # macro +CGTS_CU0_TCPI_CTRL_REG__TCPI_MASK = 0x0000007F # macro +CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU0_TCPI_CTRL_REG__RESERVED_MASK = 0xFFFFF000 # macro +CGTS_CU1_TCPI_CTRL_REG__TCPI__SHIFT = 0x0 # macro +CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU1_TCPI_CTRL_REG__RESERVED__SHIFT = 0xc # macro +CGTS_CU1_TCPI_CTRL_REG__TCPI_MASK = 0x0000007F # macro +CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU1_TCPI_CTRL_REG__RESERVED_MASK = 0xFFFFF000 # macro +CGTS_CU2_TCPI_CTRL_REG__TCPI__SHIFT = 0x0 # macro +CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU2_TCPI_CTRL_REG__RESERVED__SHIFT = 0xc # macro +CGTS_CU2_TCPI_CTRL_REG__TCPI_MASK = 0x0000007F # macro +CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU2_TCPI_CTRL_REG__RESERVED_MASK = 0xFFFFF000 # macro +CGTS_CU3_TCPI_CTRL_REG__TCPI__SHIFT = 0x0 # macro +CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU3_TCPI_CTRL_REG__RESERVED__SHIFT = 0xc # macro +CGTS_CU3_TCPI_CTRL_REG__TCPI_MASK = 0x0000007F # macro +CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU3_TCPI_CTRL_REG__RESERVED_MASK = 0xFFFFF000 # macro +CGTS_CU4_TCPI_CTRL_REG__TCPI__SHIFT = 0x0 # macro +CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU4_TCPI_CTRL_REG__RESERVED__SHIFT = 0xc # macro +CGTS_CU4_TCPI_CTRL_REG__TCPI_MASK = 0x0000007F # macro +CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU4_TCPI_CTRL_REG__RESERVED_MASK = 0xFFFFF000 # macro +CGTS_CU5_TCPI_CTRL_REG__TCPI__SHIFT = 0x0 # macro +CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU5_TCPI_CTRL_REG__RESERVED__SHIFT = 0xc # macro +CGTS_CU5_TCPI_CTRL_REG__TCPI_MASK = 0x0000007F # macro +CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU5_TCPI_CTRL_REG__RESERVED_MASK = 0xFFFFF000 # macro +CGTS_CU6_TCPI_CTRL_REG__TCPI__SHIFT = 0x0 # macro +CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU6_TCPI_CTRL_REG__RESERVED__SHIFT = 0xc # macro +CGTS_CU6_TCPI_CTRL_REG__TCPI_MASK = 0x0000007F # macro +CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU6_TCPI_CTRL_REG__RESERVED_MASK = 0xFFFFF000 # macro +CGTS_CU7_TCPI_CTRL_REG__TCPI__SHIFT = 0x0 # macro +CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU7_TCPI_CTRL_REG__RESERVED__SHIFT = 0xc # macro +CGTS_CU7_TCPI_CTRL_REG__TCPI_MASK = 0x0000007F # macro +CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU7_TCPI_CTRL_REG__RESERVED_MASK = 0xFFFFF000 # macro +CGTS_CU8_TCPI_CTRL_REG__TCPI__SHIFT = 0x0 # macro +CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU8_TCPI_CTRL_REG__RESERVED__SHIFT = 0xc # macro +CGTS_CU8_TCPI_CTRL_REG__TCPI_MASK = 0x0000007F # macro +CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU8_TCPI_CTRL_REG__RESERVED_MASK = 0xFFFFF000 # macro +CGTS_CU9_TCPI_CTRL_REG__TCPI__SHIFT = 0x0 # macro +CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU9_TCPI_CTRL_REG__RESERVED__SHIFT = 0xc # macro +CGTS_CU9_TCPI_CTRL_REG__TCPI_MASK = 0x0000007F # macro +CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU9_TCPI_CTRL_REG__RESERVED_MASK = 0xFFFFF000 # macro +CGTS_CU10_TCPI_CTRL_REG__TCPI__SHIFT = 0x0 # macro +CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU10_TCPI_CTRL_REG__RESERVED__SHIFT = 0xc # macro +CGTS_CU10_TCPI_CTRL_REG__TCPI_MASK = 0x0000007F # macro +CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU10_TCPI_CTRL_REG__RESERVED_MASK = 0xFFFFF000 # macro +CGTS_CU11_TCPI_CTRL_REG__TCPI__SHIFT = 0x0 # macro +CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU11_TCPI_CTRL_REG__RESERVED__SHIFT = 0xc # macro +CGTS_CU11_TCPI_CTRL_REG__TCPI_MASK = 0x0000007F # macro +CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU11_TCPI_CTRL_REG__RESERVED_MASK = 0xFFFFF000 # macro +CGTS_CU12_TCPI_CTRL_REG__TCPI__SHIFT = 0x0 # macro +CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU12_TCPI_CTRL_REG__RESERVED__SHIFT = 0xc # macro +CGTS_CU12_TCPI_CTRL_REG__TCPI_MASK = 0x0000007F # macro +CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU12_TCPI_CTRL_REG__RESERVED_MASK = 0xFFFFF000 # macro +CGTS_CU13_TCPI_CTRL_REG__TCPI__SHIFT = 0x0 # macro +CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU13_TCPI_CTRL_REG__RESERVED__SHIFT = 0xc # macro +CGTS_CU13_TCPI_CTRL_REG__TCPI_MASK = 0x0000007F # macro +CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU13_TCPI_CTRL_REG__RESERVED_MASK = 0xFFFFF000 # macro +CGTS_CU14_TCPI_CTRL_REG__TCPI__SHIFT = 0x0 # macro +CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU14_TCPI_CTRL_REG__RESERVED__SHIFT = 0xc # macro +CGTS_CU14_TCPI_CTRL_REG__TCPI_MASK = 0x0000007F # macro +CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU14_TCPI_CTRL_REG__RESERVED_MASK = 0xFFFFF000 # macro +CGTS_CU15_TCPI_CTRL_REG__TCPI__SHIFT = 0x0 # macro +CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT = 0x7 # macro +CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT = 0x8 # macro +CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT = 0xa # macro +CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT = 0xb # macro +CGTS_CU15_TCPI_CTRL_REG__RESERVED__SHIFT = 0xc # macro +CGTS_CU15_TCPI_CTRL_REG__TCPI_MASK = 0x0000007F # macro +CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK = 0x00000080 # macro +CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK = 0x00000300 # macro +CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK = 0x00000400 # macro +CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK = 0x00000800 # macro +CGTS_CU15_TCPI_CTRL_REG__RESERVED_MASK = 0xFFFFF000 # macro +CGTT_SPI_PS_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x10 # macro +CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x11 # macro +CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x12 # macro +CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x13 # macro +CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x14 # macro +CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x15 # macro +CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x16 # macro +CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE__SHIFT = 0x18 # macro +CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE__SHIFT = 0x19 # macro +CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE__SHIFT = 0x1a # macro +CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE__SHIFT = 0x1b # macro +CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE__SHIFT = 0x1c # macro +CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE__SHIFT = 0x1d # macro +CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE__SHIFT = 0x1e # macro +CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE__SHIFT = 0x1f # macro +CGTT_SPI_PS_CLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00010000 # macro +CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00020000 # macro +CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00040000 # macro +CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00080000 # macro +CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00100000 # macro +CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00200000 # macro +CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00400000 # macro +CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE_MASK = 0x01000000 # macro +CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE_MASK = 0x02000000 # macro +CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE_MASK = 0x04000000 # macro +CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE_MASK = 0x08000000 # macro +CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE_MASK = 0x10000000 # macro +CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE_MASK = 0x20000000 # macro +CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE_MASK = 0x40000000 # macro +CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE_MASK = 0x80000000 # macro +CGTT_SPIS_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x10 # macro +CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x11 # macro +CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x12 # macro +CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x13 # macro +CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x14 # macro +CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x15 # macro +CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x16 # macro +CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE__SHIFT = 0x18 # macro +CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE__SHIFT = 0x19 # macro +CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE__SHIFT = 0x1a # macro +CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE__SHIFT = 0x1b # macro +CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE__SHIFT = 0x1c # macro +CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE__SHIFT = 0x1d # macro +CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE__SHIFT = 0x1e # macro +CGTT_SPIS_CLK_CTRL__REG_OVERRIDE__SHIFT = 0x1f # macro +CGTT_SPIS_CLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00010000 # macro +CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00020000 # macro +CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00040000 # macro +CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00080000 # macro +CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00100000 # macro +CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00200000 # macro +CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00400000 # macro +CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE_MASK = 0x01000000 # macro +CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE_MASK = 0x02000000 # macro +CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE_MASK = 0x04000000 # macro +CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE_MASK = 0x08000000 # macro +CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE_MASK = 0x10000000 # macro +CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE_MASK = 0x20000000 # macro +CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE_MASK = 0x40000000 # macro +CGTT_SPIS_CLK_CTRL__REG_OVERRIDE_MASK = 0x80000000 # macro +CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT = 0x0 # macro +CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT = 0x6 # macro +CGTX_SPI_DEBUG_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT = 0x7 # macro +CGTX_SPI_DEBUG_CLK_CTRL__SPI_SH_CLK_CONTROL__SHIFT = 0x8 # macro +CGTX_SPI_DEBUG_CLK_CTRL__SPI_REPEATER_FGCG_OVERRIDE__SHIFT = 0x9 # macro +CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OFF_HYST_MASK = 0x0000003F # macro +CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OVERRIDE_MASK = 0x00000040 # macro +CGTX_SPI_DEBUG_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK = 0x00000080 # macro +CGTX_SPI_DEBUG_CLK_CTRL__SPI_SH_CLK_CONTROL_MASK = 0x00000100 # macro +CGTX_SPI_DEBUG_CLK_CTRL__SPI_REPEATER_FGCG_OVERRIDE_MASK = 0x00000200 # macro +CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x14 # macro +CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x15 # macro +CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x16 # macro +CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT = 0x1c # macro +CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT = 0x1d # macro +CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT = 0x1e # macro +CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT = 0x1f # macro +CGTT_SPI_CLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00100000 # macro +CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00200000 # macro +CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00400000 # macro +CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK = 0x10000000 # macro +CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK = 0x20000000 # macro +CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK = 0x40000000 # macro +CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK = 0x80000000 # macro +CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE__SHIFT = 0x11 # macro +CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT = 0x12 # macro +CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT = 0x18 # macro +CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT = 0x19 # macro +CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT = 0x1a # macro +CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT = 0x1b # macro +CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT = 0x1c # macro +CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT = 0x1d # macro +CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT = 0x1e # macro +CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT = 0x1f # macro +CGTT_PC_CLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE_MASK = 0x00020000 # macro +CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK = 0x00FC0000 # macro +CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK = 0x01000000 # macro +CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK = 0x02000000 # macro +CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK = 0x04000000 # macro +CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK = 0x08000000 # macro +CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK = 0x10000000 # macro +CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK = 0x20000000 # macro +CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK = 0x40000000 # macro +CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK = 0x80000000 # macro +CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_BCI_CLK_CTRL__RESERVED__SHIFT = 0xc # macro +CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT = 0x10 # macro +CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x17 # macro +CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT = 0x18 # macro +CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT = 0x19 # macro +CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT = 0x1a # macro +CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT = 0x1b # macro +CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT = 0x1c # macro +CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT = 0x1d # macro +CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT = 0x1e # macro +CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT = 0x1f # macro +CGTT_BCI_CLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_BCI_CLK_CTRL__RESERVED_MASK = 0x0000F000 # macro +CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK = 0x00010000 # macro +CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00800000 # macro +CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK = 0x01000000 # macro +CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK = 0x02000000 # macro +CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK = 0x04000000 # macro +CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK = 0x08000000 # macro +CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK = 0x10000000 # macro +CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK = 0x20000000 # macro +CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK = 0x40000000 # macro +CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK = 0x80000000 # macro +CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT = 0xf # macro +CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT = 0x10 # macro +CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x17 # macro +CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9__SHIFT = 0x18 # macro +CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8__SHIFT = 0x19 # macro +CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT = 0x1a # macro +CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT = 0x1b # macro +CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT = 0x1c # macro +CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT = 0x1d # macro +CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT = 0x1e # macro +CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT = 0x1f # macro +CGTT_VGT_CLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK = 0x00008000 # macro +CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK = 0x00010000 # macro +CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00800000 # macro +CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9_MASK = 0x01000000 # macro +CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8_MASK = 0x02000000 # macro +CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK = 0x04000000 # macro +CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE_MASK = 0x08000000 # macro +CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK = 0x10000000 # macro +CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK = 0x20000000 # macro +CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK = 0x40000000 # macro +CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK = 0x80000000 # macro +CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT = 0x10 # macro +CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x17 # macro +CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT = 0x18 # macro +CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT = 0x19 # macro +CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT = 0x1a # macro +CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT = 0x1b # macro +CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT = 0x1c # macro +CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT = 0x1d # macro +CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT = 0x1e # macro +CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT = 0x1f # macro +CGTT_IA_CLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK = 0x00010000 # macro +CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00800000 # macro +CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK = 0x01000000 # macro +CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK = 0x02000000 # macro +CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK = 0x04000000 # macro +CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK = 0x08000000 # macro +CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK = 0x10000000 # macro +CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK = 0x20000000 # macro +CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK = 0x40000000 # macro +CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK = 0x80000000 # macro +CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT = 0xf # macro +CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT = 0x10 # macro +CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x17 # macro +CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8__SHIFT = 0x19 # macro +CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT = 0x1a # macro +CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT = 0x1b # macro +CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT = 0x1c # macro +CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT = 0x1d # macro +CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT = 0x1e # macro +CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT = 0x1f # macro +CGTT_WD_CLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK = 0x00008000 # macro +CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK = 0x00010000 # macro +CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00800000 # macro +CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8_MASK = 0x02000000 # macro +CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK = 0x04000000 # macro +CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE_MASK = 0x08000000 # macro +CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK = 0x10000000 # macro +CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK = 0x20000000 # macro +CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK = 0x40000000 # macro +CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK = 0x80000000 # macro +CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT = 0x10 # macro +CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +CGTT_PA_CLK_CTRL__DEBUG_BUS_EN__SHIFT = 0x17 # macro +CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT = 0x18 # macro +CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT = 0x19 # macro +CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT = 0x1a # macro +CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT = 0x1b # macro +CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT = 0x1c # macro +CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT = 0x1d # macro +CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT = 0x1e # macro +CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT = 0x1f # macro +CGTT_PA_CLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK = 0x00010000 # macro +CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +CGTT_PA_CLK_CTRL__DEBUG_BUS_EN_MASK = 0x00800000 # macro +CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK = 0x01000000 # macro +CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK = 0x02000000 # macro +CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK = 0x04000000 # macro +CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK = 0x08000000 # macro +CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK = 0x10000000 # macro +CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK = 0x20000000 # macro +CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK = 0x40000000 # macro +CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK = 0x80000000 # macro +CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT = 0x0 # macro +CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT = 0x10 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT = 0x11 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT = 0x12 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT = 0x13 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT = 0x14 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT = 0x15 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT = 0x16 # macro +CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT = 0x17 # macro +CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT = 0x18 # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT = 0x19 # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT = 0x1a # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT = 0x1b # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT = 0x1c # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT = 0x1d # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT = 0x1e # macro +CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT = 0x1f # macro +CGTT_SC_CLK_CTRL0__ON_DELAY_MASK = 0x0000000F # macro +CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK = 0x00010000 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK = 0x00020000 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK = 0x00040000 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK = 0x00080000 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK = 0x00100000 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK = 0x00200000 # macro +CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK = 0x00400000 # macro +CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK = 0x00800000 # macro +CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK = 0x01000000 # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK = 0x02000000 # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK = 0x04000000 # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK = 0x08000000 # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK = 0x10000000 # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK = 0x20000000 # macro +CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK = 0x40000000 # macro +CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK = 0x80000000 # macro +CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT = 0x0 # macro +CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT = 0x11 # macro +CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT = 0x12 # macro +CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT = 0x13 # macro +CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT = 0x14 # macro +CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT = 0x15 # macro +CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT = 0x16 # macro +CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT = 0x19 # macro +CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT = 0x1a # macro +CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT = 0x1b # macro +CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT = 0x1c # macro +CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT = 0x1d # macro +CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT = 0x1e # macro +CGTT_SC_CLK_CTRL1__ON_DELAY_MASK = 0x0000000F # macro +CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK = 0x00020000 # macro +CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK = 0x00040000 # macro +CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK = 0x00080000 # macro +CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK = 0x00100000 # macro +CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK = 0x00200000 # macro +CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK = 0x00400000 # macro +CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK = 0x02000000 # macro +CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK = 0x04000000 # macro +CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK = 0x08000000 # macro +CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK = 0x10000000 # macro +CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK = 0x20000000 # macro +CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK = 0x40000000 # macro +CGTT_SC_CLK_CTRL2__ON_DELAY__SHIFT = 0x0 # macro +CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE__SHIFT = 0x1b # macro +CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE__SHIFT = 0x1c # macro +CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE__SHIFT = 0x1d # macro +CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE__SHIFT = 0x1e # macro +CGTT_SC_CLK_CTRL2__ON_DELAY_MASK = 0x0000000F # macro +CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE_MASK = 0x08000000 # macro +CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE_MASK = 0x10000000 # macro +CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE_MASK = 0x20000000 # macro +CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE_MASK = 0x40000000 # macro +CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT = 0x10 # macro +CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x17 # macro +CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT = 0x1d # macro +CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT = 0x1e # macro +CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT = 0x1f # macro +CGTT_SQ_CLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK = 0x00010000 # macro +CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00800000 # macro +CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK = 0x20000000 # macro +CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK = 0x40000000 # macro +CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK = 0x80000000 # macro +CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT = 0x10 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x17 # macro +CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT = 0x1c # macro +CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT = 0x1d # macro +CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT = 0x1e # macro +CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT = 0x1f # macro +CGTT_SQG_CLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK = 0x00010000 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00800000 # macro +CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK = 0x10000000 # macro +CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK = 0x20000000 # macro +CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK = 0x40000000 # macro +CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK = 0x80000000 # macro +SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT = 0x0 # macro +SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT = 0x10 # macro +SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK = 0x0000FFFF # macro +SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK = 0xFFFF0000 # macro +SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT = 0x0 # macro +SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT = 0x10 # macro +SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK = 0x0000FFFF # macro +SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK = 0xFFFF0000 # macro +SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT = 0x0 # macro +SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT = 0x10 # macro +SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK = 0x0000FFFF # macro +SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK = 0xFFFF0000 # macro +SQ_POWER_THROTTLE__MIN_POWER__SHIFT = 0x0 # macro +SQ_POWER_THROTTLE__MAX_POWER__SHIFT = 0x10 # macro +SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT = 0x1e # macro +SQ_POWER_THROTTLE__MIN_POWER_MASK = 0x00003FFF # macro +SQ_POWER_THROTTLE__MAX_POWER_MASK = 0x3FFF0000 # macro +SQ_POWER_THROTTLE__PHASE_OFFSET_MASK = 0xC0000000 # macro +SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT = 0x0 # macro +SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT = 0x10 # macro +SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT = 0x1b # macro +SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT = 0x1f # macro +SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK = 0x00003FFF # macro +SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK = 0x03FF0000 # macro +SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK = 0x78000000 # macro +SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK = 0x80000000 # macro +TD_CGTT_CTRL__ON_DELAY__SHIFT = 0x0 # macro +TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT = 0x18 # macro +TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT = 0x19 # macro +TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT = 0x1a # macro +TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT = 0x1b # macro +TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT = 0x1c # macro +TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT = 0x1d # macro +TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT = 0x1e # macro +TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT = 0x1f # macro +TD_CGTT_CTRL__ON_DELAY_MASK = 0x0000000F # macro +TD_CGTT_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK = 0x01000000 # macro +TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK = 0x02000000 # macro +TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK = 0x04000000 # macro +TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK = 0x08000000 # macro +TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK = 0x10000000 # macro +TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK = 0x20000000 # macro +TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK = 0x40000000 # macro +TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK = 0x80000000 # macro +TA_CGTT_CTRL__ON_DELAY__SHIFT = 0x0 # macro +TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT = 0x18 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT = 0x19 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT = 0x1a # macro +TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT = 0x1b # macro +TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT = 0x1c # macro +TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT = 0x1d # macro +TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT = 0x1e # macro +TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT = 0x1f # macro +TA_CGTT_CTRL__ON_DELAY_MASK = 0x0000000F # macro +TA_CGTT_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK = 0x01000000 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK = 0x02000000 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK = 0x04000000 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK = 0x08000000 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK = 0x10000000 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK = 0x20000000 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK = 0x40000000 # macro +TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK = 0x80000000 # macro +CGTT_TCPI_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_TCPI_CLK_CTRL__SPARE__SHIFT = 0xc # macro +CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT = 0x10 # macro +CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x17 # macro +CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT = 0x18 # macro +CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT = 0x19 # macro +CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT = 0x1a # macro +CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT = 0x1b # macro +CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT = 0x1c # macro +CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT = 0x1d # macro +CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT = 0x1e # macro +CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT = 0x1f # macro +CGTT_TCPI_CLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_TCPI_CLK_CTRL__SPARE_MASK = 0x0000F000 # macro +CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK = 0x00010000 # macro +CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00800000 # macro +CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7_MASK = 0x01000000 # macro +CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6_MASK = 0x02000000 # macro +CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5_MASK = 0x04000000 # macro +CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4_MASK = 0x08000000 # macro +CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3_MASK = 0x10000000 # macro +CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2_MASK = 0x20000000 # macro +CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1_MASK = 0x40000000 # macro +CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0_MASK = 0x80000000 # macro +TCX_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT = 0x1a # macro +TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT = 0x1b # macro +TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT = 0x1c # macro +TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT = 0x1d # macro +TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT = 0x1e # macro +TCX_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK = 0x04000000 # macro +TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK = 0x08000000 # macro +TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK = 0x10000000 # macro +TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK = 0x20000000 # macro +TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK = 0x40000000 # macro +DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT = 0x0 # macro +DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT = 0x4 # macro +DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT = 0xc # macro +DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT = 0x10 # macro +DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT = 0x17 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT = 0x18 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT = 0x19 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT = 0x1a # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT = 0x1b # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT = 0x1c # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT = 0x1d # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT = 0x1e # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT = 0x1f # macro +DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK = 0x0000000F # macro +DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +DB_CGTT_CLK_CTRL_0__RESERVED_MASK = 0x0000F000 # macro +DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK = 0x00010000 # macro +DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK = 0x00800000 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK = 0x01000000 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK = 0x02000000 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK = 0x04000000 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK = 0x08000000 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK = 0x10000000 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK = 0x20000000 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK = 0x40000000 # macro +DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK = 0x80000000 # macro +CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT = 0x10 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x17 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT = 0x18 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT = 0x19 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT = 0x1a # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT = 0x1b # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT = 0x1c # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT = 0x1d # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT = 0x1e # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT = 0x1f # macro +CB_CGTT_SCLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK = 0x00010000 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00800000 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK = 0x01000000 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK = 0x02000000 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK = 0x04000000 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK = 0x08000000 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK = 0x10000000 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK = 0x20000000 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK = 0x40000000 # macro +CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK = 0x80000000 # macro +TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT = 0x19 # macro +TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT = 0x1a # macro +TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT = 0x1b # macro +TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT = 0x1c # macro +TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT = 0x1d # macro +TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT = 0x1e # macro +TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT = 0x1f # macro +TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK = 0x02000000 # macro +TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK = 0x04000000 # macro +TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK = 0x08000000 # macro +TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK = 0x10000000 # macro +TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK = 0x20000000 # macro +TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK = 0x40000000 # macro +TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK = 0x80000000 # macro +TCC_CGTT_SCLK_CTRL2__OFF_HYSTERESIS__SHIFT = 0x4 # macro +TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE4__SHIFT = 0x1b # macro +TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE3__SHIFT = 0x1c # macro +TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE2__SHIFT = 0x1d # macro +TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE1__SHIFT = 0x1e # macro +TCC_CGTT_SCLK_CTRL2__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE4_MASK = 0x08000000 # macro +TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE3_MASK = 0x10000000 # macro +TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE2_MASK = 0x20000000 # macro +TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE1_MASK = 0x40000000 # macro +TCC_CGTT_SCLK_CTRL3__OFF_HYSTERESIS__SHIFT = 0x4 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE18__SHIFT = 0xc # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE17__SHIFT = 0xd # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE16__SHIFT = 0xe # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE15__SHIFT = 0xf # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE14__SHIFT = 0x10 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE13__SHIFT = 0x11 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE12__SHIFT = 0x12 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE11__SHIFT = 0x13 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE10__SHIFT = 0x14 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE9__SHIFT = 0x15 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE8__SHIFT = 0x17 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE7__SHIFT = 0x18 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE6__SHIFT = 0x19 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE5__SHIFT = 0x1a # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE4__SHIFT = 0x1b # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE3__SHIFT = 0x1c # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE2__SHIFT = 0x1d # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE1__SHIFT = 0x1e # macro +TCC_CGTT_SCLK_CTRL3__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE18_MASK = 0x00001000 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE17_MASK = 0x00002000 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE16_MASK = 0x00004000 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE15_MASK = 0x00008000 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE14_MASK = 0x00010000 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE13_MASK = 0x00020000 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE12_MASK = 0x00040000 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE11_MASK = 0x00080000 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE10_MASK = 0x00100000 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE9_MASK = 0x00200000 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE8_MASK = 0x00800000 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE7_MASK = 0x01000000 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE6_MASK = 0x02000000 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE5_MASK = 0x04000000 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE4_MASK = 0x08000000 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE3_MASK = 0x10000000 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE2_MASK = 0x20000000 # macro +TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE1_MASK = 0x40000000 # macro +TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT = 0x1a # macro +TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT = 0x1b # macro +TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT = 0x1c # macro +TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT = 0x1d # macro +TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT = 0x1e # macro +TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT = 0x1f # macro +TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK = 0x04000000 # macro +TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK = 0x08000000 # macro +TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK = 0x10000000 # macro +TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK = 0x20000000 # macro +TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK = 0x40000000 # macro +TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK = 0x80000000 # macro +CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT = 0xf # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT = 0x10 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x17 # macro +CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT = 0x1d # macro +CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT = 0x1e # macro +CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT = 0x1f # macro +CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK = 0x00008000 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK = 0x00010000 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00800000 # macro +CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK = 0x20000000 # macro +CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK = 0x40000000 # macro +CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK = 0x80000000 # macro +CGTT_CPC_CLK_CTRL__REG_CLK_OFF_HYSTERESIS__SHIFT = 0x0 # macro +CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT = 0xf # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT = 0x10 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x17 # macro +CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT = 0x1d # macro +CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT = 0x1e # macro +CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT = 0x1f # macro +CGTT_CPC_CLK_CTRL__REG_CLK_OFF_HYSTERESIS_MASK = 0x0000000F # macro +CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK = 0x00008000 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK = 0x00010000 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00800000 # macro +CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK = 0x20000000 # macro +CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK = 0x40000000 # macro +CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK = 0x80000000 # macro +CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT = 0x10 # macro +CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x17 # macro +CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT = 0x1e # macro +CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT = 0x1f # macro +CGTT_RLC_CLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK = 0x00010000 # macro +CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00800000 # macro +CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK = 0x40000000 # macro +CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK = 0x80000000 # macro +RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT = 0x0 # macro +RLC_GFX_RM_CNTL__RESERVED__SHIFT = 0x1 # macro +RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK = 0x00000001 # macro +RLC_GFX_RM_CNTL__RESERVED_MASK = 0xFFFFFFFE # macro +RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT = 0x10 # macro +RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x17 # macro +RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT = 0x19 # macro +RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT = 0x1a # macro +RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT = 0x1b # macro +RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT = 0x1c # macro +RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT = 0x1d # macro +RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT = 0x1e # macro +RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT = 0x1f # macro +RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK = 0x00010000 # macro +RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00800000 # macro +RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK = 0x02000000 # macro +RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK = 0x04000000 # macro +RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK = 0x08000000 # macro +RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK = 0x10000000 # macro +RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK = 0x20000000 # macro +RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK = 0x40000000 # macro +RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK = 0x80000000 # macro +CGTT_TCPF_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x4 # macro +CGTT_TCPF_CLK_CTRL__SPARE__SHIFT = 0xc # macro +CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT = 0x10 # macro +CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT = 0x11 # macro +CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT = 0x12 # macro +CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT = 0x13 # macro +CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT = 0x14 # macro +CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT = 0x15 # macro +CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT = 0x16 # macro +CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT = 0x17 # macro +CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7__SHIFT = 0x18 # macro +CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6__SHIFT = 0x19 # macro +CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5__SHIFT = 0x1a # macro +CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4__SHIFT = 0x1b # macro +CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3__SHIFT = 0x1c # macro +CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2__SHIFT = 0x1d # macro +CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1__SHIFT = 0x1e # macro +CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0__SHIFT = 0x1f # macro +CGTT_TCPF_CLK_CTRL__ON_DELAY_MASK = 0x0000000F # macro +CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00000FF0 # macro +CGTT_TCPF_CLK_CTRL__SPARE_MASK = 0x0000F000 # macro +CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK = 0x00010000 # macro +CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK = 0x00020000 # macro +CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK = 0x00040000 # macro +CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK = 0x00080000 # macro +CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK = 0x00100000 # macro +CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK = 0x00200000 # macro +CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK = 0x00400000 # macro +CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK = 0x00800000 # macro +CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7_MASK = 0x01000000 # macro +CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6_MASK = 0x02000000 # macro +CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5_MASK = 0x04000000 # macro +CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4_MASK = 0x08000000 # macro +CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3_MASK = 0x10000000 # macro +CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2_MASK = 0x20000000 # macro +CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1_MASK = 0x40000000 # macro +CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0_MASK = 0x80000000 # macro +CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT = 0x0 # macro +CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK = 0x00003FFF # macro +CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT = 0x0 # macro +CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK = 0x00003FFF # macro +CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT = 0x0 # macro +CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK = 0xFFFFFFFF # macro +CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT = 0x0 # macro +CP_PFP_UCODE_DATA__UCODE_DATA_MASK = 0xFFFFFFFF # macro +CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT = 0x0 # macro +CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK = 0x00001FFF # macro +CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT = 0x0 # macro +CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK = 0x00001FFF # macro +CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT = 0x0 # macro +CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK = 0x00001FFF # macro +CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT = 0x0 # macro +CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK = 0xFFFFFFFF # macro +CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT = 0x0 # macro +CP_ME_RAM_DATA__ME_RAM_DATA_MASK = 0xFFFFFFFF # macro +CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT = 0x0 # macro +CP_CE_UCODE_ADDR__UCODE_ADDR_MASK = 0x00000FFF # macro +CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT = 0x0 # macro +CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK = 0x00000FFF # macro +CP_CE_UCODE_DATA__UCODE_DATA__SHIFT = 0x0 # macro +CP_CE_UCODE_DATA__UCODE_DATA_MASK = 0xFFFFFFFF # macro +CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT = 0x0 # macro +CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK = 0xFFFFFFFF # macro +CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT = 0x0 # macro +CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK = 0x0001FFFF # macro +CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT = 0x0 # macro +CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK = 0x0001FFFF # macro +CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT = 0x0 # macro +CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT = 0x0 # macro +CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK = 0xFFFFFFFF # macro +CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT = 0x0 # macro +CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK = 0x0001FFFF # macro +CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT = 0x0 # macro +CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK = 0x0001FFFF # macro +CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT = 0x0 # macro +CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK = 0xFFFFFFFF # macro +CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT = 0x0 # macro +CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK = 0xFFFFFFFF # macro +CP_HYP_PFP_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT = 0x0 # macro +CP_HYP_PFP_UCODE_CHKSUM__UCODE_CHKSUM_MASK = 0xFFFFFFFF # macro +CP_HYP_CE_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT = 0x0 # macro +CP_HYP_CE_UCODE_CHKSUM__UCODE_CHKSUM_MASK = 0xFFFFFFFF # macro +CP_HYP_ME_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT = 0x0 # macro +CP_HYP_ME_UCODE_CHKSUM__UCODE_CHKSUM_MASK = 0xFFFFFFFF # macro +CP_HYP_MEC_ME1_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT = 0x0 # macro +CP_HYP_MEC_ME1_UCODE_CHKSUM__UCODE_CHKSUM_MASK = 0xFFFFFFFF # macro +CP_HYP_MEC_ME2_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT = 0x0 # macro +CP_HYP_MEC_ME2_UCODE_CHKSUM__UCODE_CHKSUM_MASK = 0xFFFFFFFF # macro +CP_HYP_XCP_CTL__VIRTUAL_XCC_ID__SHIFT = 0x0 # macro +CP_HYP_XCP_CTL__NUM_XCC_IN_XCP__SHIFT = 0x3 # macro +CP_HYP_XCP_CTL__VIRTUAL_XCC_ID_MASK = 0x00000007 # macro +CP_HYP_XCP_CTL__NUM_XCC_IN_XCP_MASK = 0x00000078 # macro +RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT = 0x0 # macro +RLC_GPM_UCODE_ADDR__RESERVED__SHIFT = 0xe # macro +RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK = 0x00003FFF # macro +RLC_GPM_UCODE_ADDR__RESERVED_MASK = 0xFFFFC000 # macro +RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT = 0x0 # macro +RLC_GPM_UCODE_DATA__UCODE_DATA_MASK = 0xFFFFFFFF # macro +GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT = 0x0 # macro +GRBM_GFX_INDEX_SR_SELECT__VF_PF__SHIFT = 0x1f # macro +GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK = 0x00000007 # macro +GRBM_GFX_INDEX_SR_SELECT__VF_PF_MASK = 0x80000000 # macro +GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT = 0x0 # macro +GRBM_GFX_INDEX_SR_DATA__SH_INDEX__SHIFT = 0x8 # macro +GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT = 0x10 # macro +GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES__SHIFT = 0x1d # macro +GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT = 0x1e # macro +GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT = 0x1f # macro +GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK = 0x000000FF # macro +GRBM_GFX_INDEX_SR_DATA__SH_INDEX_MASK = 0x0000FF00 # macro +GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK = 0x00FF0000 # macro +GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES_MASK = 0x20000000 # macro +GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK = 0x40000000 # macro +GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK = 0x80000000 # macro +GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT = 0x0 # macro +GRBM_GFX_CNTL_SR_SELECT__VF_PF__SHIFT = 0x1f # macro +GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK = 0x00000007 # macro +GRBM_GFX_CNTL_SR_SELECT__VF_PF_MASK = 0x80000000 # macro +GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT = 0x0 # macro +GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT = 0x2 # macro +GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT = 0x4 # macro +GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT = 0x8 # macro +GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK = 0x00000003 # macro +GRBM_GFX_CNTL_SR_DATA__MEID_MASK = 0x0000000C # macro +GRBM_GFX_CNTL_SR_DATA__VMID_MASK = 0x000000F0 # macro +GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK = 0x00000700 # macro +GRBM_MCM_ADDR__MCM_ADDR_IH__SHIFT = 0x0 # macro +GRBM_MCM_ADDR__MCM_ADDR_IH_MASK = 0x000000FF # macro +RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT = 0x0 # macro +RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT = 0x1 # macro +RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT = 0x10 # macro +RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK = 0x00000001 # macro +RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK = 0x0000FFFE # macro +RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK = 0xFFFF0000 # macro +RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT = 0x0 # macro +RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT = 0x7 # macro +RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT = 0x8 # macro +RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT = 0xa # macro +RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK = 0x0000007F # macro +RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK = 0x00000080 # macro +RLC_GPU_IOV_CFG_REG6__RESERVED_MASK = 0x00000300 # macro +RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK = 0xFFFFFC00 # macro +RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_RLCV_TIMER_INT_0__TIMER__SHIFT = 0x0 # macro +RLC_RLCV_TIMER_INT_0__TIMER_MASK = 0xFFFFFFFF # macro +RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT = 0x0 # macro +RLC_RLCV_TIMER_CTRL__TIMER_1_EN__SHIFT = 0x1 # macro +RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT = 0x2 # macro +RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK = 0x00000001 # macro +RLC_RLCV_TIMER_CTRL__TIMER_1_EN_MASK = 0x00000002 # macro +RLC_RLCV_TIMER_CTRL__RESERVED_MASK = 0xFFFFFFFC # macro +RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT = 0x0 # macro +RLC_RLCV_TIMER_STAT__TIMER_1_STAT__SHIFT = 0x1 # macro +RLC_RLCV_TIMER_STAT__RESERVED__SHIFT = 0x2 # macro +RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT = 0x8 # macro +RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT = 0x9 # macro +RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK = 0x00000001 # macro +RLC_RLCV_TIMER_STAT__TIMER_1_STAT_MASK = 0x00000002 # macro +RLC_RLCV_TIMER_STAT__RESERVED_MASK = 0x000000FC # macro +RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK = 0x00000100 # macro +RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK = 0x00000200 # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED__SHIFT = 0x10 # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT = 0x1f # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK = 0x0000FFFF # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED_MASK = 0x7FFF0000 # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK = 0x80000000 # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT = 0x0 # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED__SHIFT = 0x10 # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT = 0x1f # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK = 0x0000FFFF # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED_MASK = 0x7FFF0000 # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK = 0x80000000 # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT = 0x0 # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED__SHIFT = 0x10 # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT = 0x1f # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK = 0x0000FFFF # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED_MASK = 0x7FFF0000 # macro +RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK = 0x80000000 # macro +RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT = 0x0 # macro +RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT = 0x10 # macro +RLC_GPU_IOV_VF_MASK__VF_MASK_MASK = 0x0000FFFF # macro +RLC_GPU_IOV_VF_MASK__RESERVED_MASK = 0xFFFF0000 # macro +RLC_HYP_SEMAPHORE_0__CLIENT_ID__SHIFT = 0x0 # macro +RLC_HYP_SEMAPHORE_0__RESERVED__SHIFT = 0x5 # macro +RLC_HYP_SEMAPHORE_0__CLIENT_ID_MASK = 0x0000001F # macro +RLC_HYP_SEMAPHORE_0__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_HYP_SEMAPHORE_1__CLIENT_ID__SHIFT = 0x0 # macro +RLC_HYP_SEMAPHORE_1__RESERVED__SHIFT = 0x5 # macro +RLC_HYP_SEMAPHORE_1__CLIENT_ID_MASK = 0x0000001F # macro +RLC_HYP_SEMAPHORE_1__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT = 0x0 # macro +RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT = 0x2 # macro +RLC_CLK_CNTL__RLC_GPM_CLK_CNTL__SHIFT = 0x4 # macro +RLC_CLK_CNTL__RLC_CMN_CLK_CNTL__SHIFT = 0x5 # macro +RLC_CLK_CNTL__RLC_TC_CLK_CNTL__SHIFT = 0x6 # macro +RLC_CLK_CNTL__RLC_SPP_CLK_CNTL__SHIFT = 0x7 # macro +RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE__SHIFT = 0x8 # macro +RLC_CLK_CNTL__RLC_EDC_OVERRIDE__SHIFT = 0x9 # macro +RLC_CLK_CNTL__RESERVED_11_10__SHIFT = 0xa # macro +RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE__SHIFT = 0xc # macro +RLC_CLK_CNTL__RLC_DFLL_CLK_CNTL__SHIFT = 0xd # macro +RLC_CLK_CNTL__DBGBUS_CLK_ACTIVE_OVERRIDE__SHIFT = 0xe # macro +RLC_CLK_CNTL__RLC_CAC2_CLK_CNTL__SHIFT = 0xf # macro +RLC_CLK_CNTL__RESERVED_1__SHIFT = 0x11 # macro +RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE__SHIFT = 0x12 # macro +RLC_CLK_CNTL__RESERVED__SHIFT = 0x13 # macro +RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK = 0x00000003 # macro +RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK = 0x0000000C # macro +RLC_CLK_CNTL__RLC_GPM_CLK_CNTL_MASK = 0x00000010 # macro +RLC_CLK_CNTL__RLC_CMN_CLK_CNTL_MASK = 0x00000020 # macro +RLC_CLK_CNTL__RLC_TC_CLK_CNTL_MASK = 0x00000040 # macro +RLC_CLK_CNTL__RLC_SPP_CLK_CNTL_MASK = 0x00000080 # macro +RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK = 0x00000100 # macro +RLC_CLK_CNTL__RLC_EDC_OVERRIDE_MASK = 0x00000200 # macro +RLC_CLK_CNTL__RESERVED_11_10_MASK = 0x00000C00 # macro +RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE_MASK = 0x00001000 # macro +RLC_CLK_CNTL__RLC_DFLL_CLK_CNTL_MASK = 0x00002000 # macro +RLC_CLK_CNTL__DBGBUS_CLK_ACTIVE_OVERRIDE_MASK = 0x00004000 # macro +RLC_CLK_CNTL__RLC_CAC2_CLK_CNTL_MASK = 0x00018000 # macro +RLC_CLK_CNTL__RESERVED_1_MASK = 0x00020000 # macro +RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE_MASK = 0x00040000 # macro +RLC_CLK_CNTL__RESERVED_MASK = 0xFFF80000 # macro +RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT = 0x0 # macro +RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT = 0x4 # macro +RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT = 0x8 # macro +RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT = 0x10 # macro +RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK = 0x0000000F # macro +RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK = 0x000000F0 # macro +RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK = 0x00007F00 # macro +RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK = 0x7FFF0000 # macro +RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT = 0x0 # macro +RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT = 0x4 # macro +RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT = 0x5 # macro +RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT = 0x6 # macro +RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT = 0x8 # macro +RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT = 0x10 # macro +RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT = 0x18 # macro +RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK = 0x0000000F # macro +RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK = 0x00000010 # macro +RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK = 0x00000020 # macro +RLC_GPU_IOV_CFG_REG1__RESERVED_MASK = 0x000000C0 # macro +RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK = 0x0000FF00 # macro +RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK = 0x00FF0000 # macro +RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK = 0xFF000000 # macro +RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT = 0x4 # macro +RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK = 0x0000000F # macro +RLC_GPU_IOV_CFG_REG2__RESERVED_MASK = 0xFFFFFFF0 # macro +RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT = 0x0 # macro +RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT = 0x4 # macro +RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT = 0x1f # macro +RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK = 0x0000000F # macro +RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK = 0x7FFFFFF0 # macro +RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK = 0x80000000 # macro +RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT = 0x0 # macro +RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SCH_1__DATA__SHIFT = 0x0 # macro +RLC_GPU_IOV_SCH_1__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SCH_2__DATA__SHIFT = 0x0 # macro +RLC_GPU_IOV_SCH_2__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_INT_STAT__STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_INT_STAT__STATUS_MASK = 0xFFFFFFFF # macro +RLC_RLCV_TIMER_INT_1__TIMER__SHIFT = 0x0 # macro +RLC_RLCV_TIMER_INT_1__TIMER_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT = 0x0 # macro +RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT = 0xc # macro +RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK = 0x00000FFF # macro +RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK = 0xFFFFF000 # macro +RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT = 0x0 # macro +RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT = 0x0 # macro +RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT = 0x9 # macro +RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK = 0x000001FF # macro +RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK = 0xFFFFFE00 # macro +RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT = 0x0 # macro +RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT = 0x0 # macro +RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT = 0x1 # macro +RLC_GPU_IOV_F32_CNTL__ENABLE_MASK = 0x00000001 # macro +RLC_GPU_IOV_F32_CNTL__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_GPU_IOV_F32_RESET__RESET__SHIFT = 0x0 # macro +RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT = 0x1 # macro +RLC_GPU_IOV_F32_RESET__RESET_MASK = 0x00000001 # macro +RLC_GPU_IOV_F32_RESET__RESERVED_MASK = 0xFFFFFFFE # macro +RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT = 0x1 # macro +RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT = 0x8 # macro +RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT = 0x9 # macro +RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT = 0xc # macro +RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT = 0xd # macro +RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK = 0x00000001 # macro +RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK = 0x000000FE # macro +RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK = 0x00000100 # macro +RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK = 0x00000E00 # macro +RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK = 0x00001000 # macro +RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK = 0xFFFFE000 # macro +RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT = 0x1 # macro +RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT = 0x8 # macro +RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT = 0x9 # macro +RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT = 0xc # macro +RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT = 0xd # macro +RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK = 0x00000001 # macro +RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK = 0x000000FE # macro +RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK = 0x00000100 # macro +RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK = 0x00000E00 # macro +RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK = 0x00001000 # macro +RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK = 0xFFFFE000 # macro +RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT = 0x0 # macro +RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT = 0x0 # macro +RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT = 0x10 # macro +RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT = 0x1f # macro +RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK = 0x0000FFFF # macro +RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK = 0x7FFF0000 # macro +RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK = 0x80000000 # macro +RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT = 0x0 # macro +RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT = 0x0 # macro +RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT = 0x0 # macro +RLC_GPU_IOV_INT_FORCE__FORCE_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT = 0x0 # macro +RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT = 0x5 # macro +RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK = 0x0000001F # macro +RLC_HYP_SEMAPHORE_2__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT = 0x0 # macro +RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT = 0x5 # macro +RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK = 0x0000001F # macro +RLC_HYP_SEMAPHORE_3__RESERVED_MASK = 0xFFFFFFE0 # macro +RLC_GPU_IOV_SDMA2_STATUS__PREEMPTED__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA2_STATUS__RESERVED__SHIFT = 0x1 # macro +RLC_GPU_IOV_SDMA2_STATUS__SAVED__SHIFT = 0x8 # macro +RLC_GPU_IOV_SDMA2_STATUS__RESERVED1__SHIFT = 0x9 # macro +RLC_GPU_IOV_SDMA2_STATUS__RESTORED__SHIFT = 0xc # macro +RLC_GPU_IOV_SDMA2_STATUS__RESERVED2__SHIFT = 0xd # macro +RLC_GPU_IOV_SDMA2_STATUS__PREEMPTED_MASK = 0x00000001 # macro +RLC_GPU_IOV_SDMA2_STATUS__RESERVED_MASK = 0x000000FE # macro +RLC_GPU_IOV_SDMA2_STATUS__SAVED_MASK = 0x00000100 # macro +RLC_GPU_IOV_SDMA2_STATUS__RESERVED1_MASK = 0x00000E00 # macro +RLC_GPU_IOV_SDMA2_STATUS__RESTORED_MASK = 0x00001000 # macro +RLC_GPU_IOV_SDMA2_STATUS__RESERVED2_MASK = 0xFFFFE000 # macro +RLC_GPU_IOV_SDMA3_STATUS__PREEMPTED__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA3_STATUS__RESERVED__SHIFT = 0x1 # macro +RLC_GPU_IOV_SDMA3_STATUS__SAVED__SHIFT = 0x8 # macro +RLC_GPU_IOV_SDMA3_STATUS__RESERVED1__SHIFT = 0x9 # macro +RLC_GPU_IOV_SDMA3_STATUS__RESTORED__SHIFT = 0xc # macro +RLC_GPU_IOV_SDMA3_STATUS__RESERVED2__SHIFT = 0xd # macro +RLC_GPU_IOV_SDMA3_STATUS__PREEMPTED_MASK = 0x00000001 # macro +RLC_GPU_IOV_SDMA3_STATUS__RESERVED_MASK = 0x000000FE # macro +RLC_GPU_IOV_SDMA3_STATUS__SAVED_MASK = 0x00000100 # macro +RLC_GPU_IOV_SDMA3_STATUS__RESERVED1_MASK = 0x00000E00 # macro +RLC_GPU_IOV_SDMA3_STATUS__RESTORED_MASK = 0x00001000 # macro +RLC_GPU_IOV_SDMA3_STATUS__RESERVED2_MASK = 0xFFFFE000 # macro +RLC_GPU_IOV_SDMA4_STATUS__PREEMPTED__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA4_STATUS__RESERVED__SHIFT = 0x1 # macro +RLC_GPU_IOV_SDMA4_STATUS__SAVED__SHIFT = 0x8 # macro +RLC_GPU_IOV_SDMA4_STATUS__RESERVED1__SHIFT = 0x9 # macro +RLC_GPU_IOV_SDMA4_STATUS__RESTORED__SHIFT = 0xc # macro +RLC_GPU_IOV_SDMA4_STATUS__RESERVED2__SHIFT = 0xd # macro +RLC_GPU_IOV_SDMA4_STATUS__PREEMPTED_MASK = 0x00000001 # macro +RLC_GPU_IOV_SDMA4_STATUS__RESERVED_MASK = 0x000000FE # macro +RLC_GPU_IOV_SDMA4_STATUS__SAVED_MASK = 0x00000100 # macro +RLC_GPU_IOV_SDMA4_STATUS__RESERVED1_MASK = 0x00000E00 # macro +RLC_GPU_IOV_SDMA4_STATUS__RESTORED_MASK = 0x00001000 # macro +RLC_GPU_IOV_SDMA4_STATUS__RESERVED2_MASK = 0xFFFFE000 # macro +RLC_GPU_IOV_SDMA5_STATUS__PREEMPTED__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA5_STATUS__RESERVED__SHIFT = 0x1 # macro +RLC_GPU_IOV_SDMA5_STATUS__SAVED__SHIFT = 0x8 # macro +RLC_GPU_IOV_SDMA5_STATUS__RESERVED1__SHIFT = 0x9 # macro +RLC_GPU_IOV_SDMA5_STATUS__RESTORED__SHIFT = 0xc # macro +RLC_GPU_IOV_SDMA5_STATUS__RESERVED2__SHIFT = 0xd # macro +RLC_GPU_IOV_SDMA5_STATUS__PREEMPTED_MASK = 0x00000001 # macro +RLC_GPU_IOV_SDMA5_STATUS__RESERVED_MASK = 0x000000FE # macro +RLC_GPU_IOV_SDMA5_STATUS__SAVED_MASK = 0x00000100 # macro +RLC_GPU_IOV_SDMA5_STATUS__RESERVED1_MASK = 0x00000E00 # macro +RLC_GPU_IOV_SDMA5_STATUS__RESTORED_MASK = 0x00001000 # macro +RLC_GPU_IOV_SDMA5_STATUS__RESERVED2_MASK = 0xFFFFE000 # macro +RLC_GPU_IOV_SDMA6_STATUS__PREEMPTED__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA6_STATUS__RESERVED__SHIFT = 0x1 # macro +RLC_GPU_IOV_SDMA6_STATUS__SAVED__SHIFT = 0x8 # macro +RLC_GPU_IOV_SDMA6_STATUS__RESERVED1__SHIFT = 0x9 # macro +RLC_GPU_IOV_SDMA6_STATUS__RESTORED__SHIFT = 0xc # macro +RLC_GPU_IOV_SDMA6_STATUS__RESERVED2__SHIFT = 0xd # macro +RLC_GPU_IOV_SDMA6_STATUS__PREEMPTED_MASK = 0x00000001 # macro +RLC_GPU_IOV_SDMA6_STATUS__RESERVED_MASK = 0x000000FE # macro +RLC_GPU_IOV_SDMA6_STATUS__SAVED_MASK = 0x00000100 # macro +RLC_GPU_IOV_SDMA6_STATUS__RESERVED1_MASK = 0x00000E00 # macro +RLC_GPU_IOV_SDMA6_STATUS__RESTORED_MASK = 0x00001000 # macro +RLC_GPU_IOV_SDMA6_STATUS__RESERVED2_MASK = 0xFFFFE000 # macro +RLC_GPU_IOV_SDMA7_STATUS__PREEMPTED__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA7_STATUS__RESERVED__SHIFT = 0x1 # macro +RLC_GPU_IOV_SDMA7_STATUS__SAVED__SHIFT = 0x8 # macro +RLC_GPU_IOV_SDMA7_STATUS__RESERVED1__SHIFT = 0x9 # macro +RLC_GPU_IOV_SDMA7_STATUS__RESTORED__SHIFT = 0xc # macro +RLC_GPU_IOV_SDMA7_STATUS__RESERVED2__SHIFT = 0xd # macro +RLC_GPU_IOV_SDMA7_STATUS__PREEMPTED_MASK = 0x00000001 # macro +RLC_GPU_IOV_SDMA7_STATUS__RESERVED_MASK = 0x000000FE # macro +RLC_GPU_IOV_SDMA7_STATUS__SAVED_MASK = 0x00000100 # macro +RLC_GPU_IOV_SDMA7_STATUS__RESERVED1_MASK = 0x00000E00 # macro +RLC_GPU_IOV_SDMA7_STATUS__RESTORED_MASK = 0x00001000 # macro +RLC_GPU_IOV_SDMA7_STATUS__RESERVED2_MASK = 0xFFFFE000 # macro +RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS_MASK = 0xFFFFFFFF # macro +RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS__SHIFT = 0x0 # macro +RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS_MASK = 0xFFFFFFFF # macro +MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT = 0x0 # macro +MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT = 0x10 # macro +MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT = 0x0 # macro +MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT = 0x10 # macro +MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT = 0x0 # macro +MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT = 0x10 # macro +MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT = 0x0 # macro +MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT = 0x10 # macro +MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT = 0x0 # macro +MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT = 0x10 # macro +MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT = 0x0 # macro +MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT = 0x10 # macro +MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT = 0x0 # macro +MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT = 0x10 # macro +MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT = 0x0 # macro +MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT = 0x10 # macro +MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT = 0x0 # macro +MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT = 0x10 # macro +MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT = 0x0 # macro +MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT = 0x10 # macro +MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT = 0x0 # macro +MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT = 0x10 # macro +MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT = 0x0 # macro +MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT = 0x10 # macro +MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT = 0x0 # macro +MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT = 0x10 # macro +MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT = 0x0 # macro +MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT = 0x10 # macro +MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT = 0x0 # macro +MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT = 0x10 # macro +MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT = 0x0 # macro +MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT = 0x10 # macro +MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT = 0x8 # macro +VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK = 0x00000100 # macro +MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT = 0xc # macro +MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK = 0xFFFFF000 # macro +MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT = 0xc # macro +MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK = 0xFFFFF000 # macro +MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT = 0xc # macro +MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK = 0xFFFFF000 # macro +MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT = 0xc # macro +MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK = 0xFFFFF000 # macro +MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT = 0x0 # macro +MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK = 0x000FFFFF # macro +MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT = 0x0 # macro +MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK = 0x000FFFFF # macro +MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT = 0x0 # macro +MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK = 0x000FFFFF # macro +MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT = 0x0 # macro +MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK = 0x000FFFFF # macro +MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT = 0x0 # macro +MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT = 0x1 # macro +MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT = 0xc # macro +MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK = 0x00000001 # macro +MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK = 0x00000002 # macro +MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK = 0xFFFFF000 # macro +MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT = 0x0 # macro +MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT = 0x1 # macro +MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT = 0xc # macro +MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK = 0x00000001 # macro +MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK = 0x00000002 # macro +MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK = 0xFFFFF000 # macro +MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT = 0x0 # macro +MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT = 0x1 # macro +MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT = 0xc # macro +MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK = 0x00000001 # macro +MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK = 0x00000002 # macro +MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK = 0xFFFFF000 # macro +MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT = 0x0 # macro +MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT = 0x1 # macro +MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT = 0xc # macro +MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK = 0x00000001 # macro +MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK = 0x00000002 # macro +MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK = 0xFFFFF000 # macro +MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT = 0x0 # macro +MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK = 0x000FFFFF # macro +MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT = 0x0 # macro +MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK = 0x000FFFFF # macro +MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT = 0x0 # macro +MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK = 0x000FFFFF # macro +MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT = 0x0 # macro +MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK = 0x000FFFFF # macro +MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT = 0xc # macro +MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK = 0xFFFFF000 # macro +MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT = 0xc # macro +MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK = 0xFFFFF000 # macro +MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT = 0xc # macro +MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK = 0xFFFFF000 # macro +MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT = 0xc # macro +MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK = 0xFFFFF000 # macro +MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT = 0x0 # macro +MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK = 0x000FFFFF # macro +MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT = 0x0 # macro +MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK = 0x000FFFFF # macro +MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT = 0x0 # macro +MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK = 0x000FFFFF # macro +MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT = 0x0 # macro +MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK = 0x000FFFFF # macro +VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT = 0x0 # macro +VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK = 0x00000001 # macro +VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT = 0xd # macro +VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK = 0x00002000 # macro +VM_PCIE_ATS_CNTL__STU__SHIFT = 0x10 # macro +VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT = 0x1f # macro +VM_PCIE_ATS_CNTL__STU_MASK = 0x001F0000 # macro +VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK = 0x80000000 # macro +VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT = 0x1f # macro +VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK = 0x80000000 # macro +VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT = 0x1f # macro +VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK = 0x80000000 # macro +VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT = 0x1f # macro +VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK = 0x80000000 # macro +VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT = 0x1f # macro +VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK = 0x80000000 # macro +VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT = 0x1f # macro +VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK = 0x80000000 # macro +VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT = 0x1f # macro +VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK = 0x80000000 # macro +VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT = 0x1f # macro +VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK = 0x80000000 # macro +VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT = 0x1f # macro +VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK = 0x80000000 # macro +VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT = 0x1f # macro +VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK = 0x80000000 # macro +VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT = 0x1f # macro +VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK = 0x80000000 # macro +VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT = 0x1f # macro +VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK = 0x80000000 # macro +VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT = 0x1f # macro +VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK = 0x80000000 # macro +VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT = 0x1f # macro +VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK = 0x80000000 # macro +VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT = 0x1f # macro +VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK = 0x80000000 # macro +VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT = 0x1f # macro +VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK = 0x80000000 # macro +VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT = 0x1f # macro +VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK = 0x80000000 # macro +MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT = 0x0 # macro +MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT = 0x1f # macro +MC_SHARED_ACTIVE_FCN_ID__VFID_MASK = 0x0000000F # macro +MC_SHARED_ACTIVE_FCN_ID__VF_MASK = 0x80000000 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT = 0x0 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT = 0x1 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT = 0x2 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT = 0x3 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT = 0x4 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT = 0x5 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT = 0x6 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT = 0x7 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT = 0x8 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT = 0x9 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT = 0xa # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT = 0xb # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT = 0xc # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT = 0xd # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT = 0xe # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT = 0xf # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT = 0x1f # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK = 0x00000001 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK = 0x00000002 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK = 0x00000004 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK = 0x00000008 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK = 0x00000010 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK = 0x00000020 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK = 0x00000040 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK = 0x00000080 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK = 0x00000100 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK = 0x00000200 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK = 0x00000400 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK = 0x00000800 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK = 0x00001000 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK = 0x00002000 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK = 0x00004000 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK = 0x00008000 # macro +MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK = 0x80000000 # macro +CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT = 0x0 # macro +CPG_PSP_DEBUG__VMID_VIOLATION_CNTL__SHIFT = 0x2 # macro +CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK = 0x00000003 # macro +CPG_PSP_DEBUG__VMID_VIOLATION_CNTL_MASK = 0x00000004 # macro +CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT = 0x0 # macro +CPC_PSP_DEBUG__VMID_VIOLATION_CNTL__SHIFT = 0x2 # macro +CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE__SHIFT = 0x3 # macro +CPC_PSP_DEBUG__CPC_DC_FIX_DISABLE__SHIFT = 0x4 # macro +CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK = 0x00000003 # macro +CPC_PSP_DEBUG__VMID_VIOLATION_CNTL_MASK = 0x00000004 # macro +CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK = 0x00000008 # macro +CPC_PSP_DEBUG__CPC_DC_FIX_DISABLE_MASK = 0x00000010 # macro +CP_PSP_XCP_CTL__PHYSICAL_XCC_ID__SHIFT = 0x0 # macro +CP_PSP_XCP_CTL__XCC_DIE_ID__SHIFT = 0x3 # macro +CP_PSP_XCP_CTL__PHYSICAL_XCC_ID_MASK = 0x00000007 # macro +CP_PSP_XCP_CTL__XCC_DIE_ID_MASK = 0x00000038 # macro +GRBM_SEC_CNTL__DEBUG_ENABLE__SHIFT = 0x0 # macro +GRBM_SEC_CNTL__DEBUG_ENABLE_MASK = 0x00000001 # macro +GRBM_IOV_ERROR_FIFO_DATA__IOV_ADDR__SHIFT = 0x0 # macro +GRBM_IOV_ERROR_FIFO_DATA__IOV_VFID__SHIFT = 0x12 # macro +GRBM_IOV_ERROR_FIFO_DATA__IOV_SSRCID__SHIFT = 0x18 # macro +GRBM_IOV_ERROR_FIFO_DATA__IOV_OP__SHIFT = 0x1c # macro +GRBM_IOV_ERROR_FIFO_DATA__IOV_VF__SHIFT = 0x1d # macro +GRBM_IOV_ERROR_FIFO_DATA__IOV_OVERFLOW__SHIFT = 0x1e # macro +GRBM_IOV_ERROR_FIFO_DATA__IOV_READ_VALID__SHIFT = 0x1f # macro +GRBM_IOV_ERROR_FIFO_DATA__IOV_ADDR_MASK = 0x0003FFFF # macro +GRBM_IOV_ERROR_FIFO_DATA__IOV_VFID_MASK = 0x00FC0000 # macro +GRBM_IOV_ERROR_FIFO_DATA__IOV_SSRCID_MASK = 0x0F000000 # macro +GRBM_IOV_ERROR_FIFO_DATA__IOV_OP_MASK = 0x10000000 # macro +GRBM_IOV_ERROR_FIFO_DATA__IOV_VF_MASK = 0x20000000 # macro +GRBM_IOV_ERROR_FIFO_DATA__IOV_OVERFLOW_MASK = 0x40000000 # macro +GRBM_IOV_ERROR_FIFO_DATA__IOV_READ_VALID_MASK = 0x80000000 # macro +GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT = 0x0 # macro +GRBM_DSM_BYPASS__BYPASS_EN__SHIFT = 0x2 # macro +GRBM_DSM_BYPASS__BYPASS_BITS_MASK = 0x00000003 # macro +GRBM_DSM_BYPASS__BYPASS_EN_MASK = 0x00000004 # macro +GRBM_CAM_INDEX__CAM_INDEX__SHIFT = 0x0 # macro +GRBM_CAM_INDEX__CAM_INDEX_MASK = 0x00000007 # macro +GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT = 0x0 # macro +GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK = 0x00000007 # macro +GRBM_CAM_DATA__CAM_ADDR__SHIFT = 0x0 # macro +GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT = 0x10 # macro +GRBM_CAM_DATA__CAM_ADDR_MASK = 0x0000FFFF # macro +GRBM_CAM_DATA__CAM_REMAPADDR_MASK = 0xFFFF0000 # macro +GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT = 0x0 # macro +GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT = 0x10 # macro +GRBM_HYP_CAM_DATA__CAM_ADDR_MASK = 0x0000FFFF # macro +GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK = 0xFFFF0000 # macro +RLC_FWL_FIRST_VIOL_ADDR__VIOL_STATUS__SHIFT = 0x0 # macro +RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP__SHIFT = 0x1 # macro +RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR__SHIFT = 0x2 # macro +RLC_FWL_FIRST_VIOL_ADDR__VIOL_APERTURE_ID__SHIFT = 0x14 # macro +RLC_FWL_FIRST_VIOL_ADDR__VIOL_STATUS_MASK = 0x00000001 # macro +RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP_MASK = 0x00000002 # macro +RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR_MASK = 0x000FFFFC # macro +RLC_FWL_FIRST_VIOL_ADDR__VIOL_APERTURE_ID_MASK = 0xFFF00000 # macro +SQ_DEBUG_STS_LOCAL__BUSY__SHIFT = 0x0 # macro +SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT = 0x4 # macro +SQ_DEBUG_STS_LOCAL__BUSY_MASK = 0x00000001 # macro +SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK = 0x000003F0 # macro +SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT = 0x0 # macro +SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_NON_WAVE__SHIFT = 0x8 # macro +SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_MOPS_NON_WAVE__SHIFT = 0x9 # macro +SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK = 0x000000FF # macro +SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_NON_WAVE_MASK = 0x00000100 # macro +SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_MOPS_NON_WAVE_MASK = 0x00000200 # macro +SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT__SHIFT = 0x0 # macro +SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT_MASK = 0xFFFFFFFF # macro +SQ_WAVE_MODE__FP_ROUND__SHIFT = 0x0 # macro +SQ_WAVE_MODE__FP_DENORM__SHIFT = 0x4 # macro +SQ_WAVE_MODE__DX10_CLAMP__SHIFT = 0x8 # macro +SQ_WAVE_MODE__IEEE__SHIFT = 0x9 # macro +SQ_WAVE_MODE__LOD_CLAMPED__SHIFT = 0xa # macro +SQ_WAVE_MODE__DEBUG_EN__SHIFT = 0xb # macro +SQ_WAVE_MODE__EXCP_EN__SHIFT = 0xc # macro +SQ_WAVE_MODE__FP16_OVFL__SHIFT = 0x17 # macro +SQ_WAVE_MODE__POPS_PACKER0__SHIFT = 0x18 # macro +SQ_WAVE_MODE__POPS_PACKER1__SHIFT = 0x19 # macro +SQ_WAVE_MODE__DISABLE_PERF__SHIFT = 0x1a # macro +SQ_WAVE_MODE__GPR_IDX_EN__SHIFT = 0x1b # macro +SQ_WAVE_MODE__VSKIP__SHIFT = 0x1c # macro +SQ_WAVE_MODE__CSP__SHIFT = 0x1d # macro +SQ_WAVE_MODE__FP_ROUND_MASK = 0x0000000F # macro +SQ_WAVE_MODE__FP_DENORM_MASK = 0x000000F0 # macro +SQ_WAVE_MODE__DX10_CLAMP_MASK = 0x00000100 # macro +SQ_WAVE_MODE__IEEE_MASK = 0x00000200 # macro +SQ_WAVE_MODE__LOD_CLAMPED_MASK = 0x00000400 # macro +SQ_WAVE_MODE__DEBUG_EN_MASK = 0x00000800 # macro +SQ_WAVE_MODE__EXCP_EN_MASK = 0x001FF000 # macro +SQ_WAVE_MODE__FP16_OVFL_MASK = 0x00800000 # macro +SQ_WAVE_MODE__POPS_PACKER0_MASK = 0x01000000 # macro +SQ_WAVE_MODE__POPS_PACKER1_MASK = 0x02000000 # macro +SQ_WAVE_MODE__DISABLE_PERF_MASK = 0x04000000 # macro +SQ_WAVE_MODE__GPR_IDX_EN_MASK = 0x08000000 # macro +SQ_WAVE_MODE__VSKIP_MASK = 0x10000000 # macro +SQ_WAVE_MODE__CSP_MASK = 0xE0000000 # macro +SQ_WAVE_STATUS__SCC__SHIFT = 0x0 # macro +SQ_WAVE_STATUS__SPI_PRIO__SHIFT = 0x1 # macro +SQ_WAVE_STATUS__USER_PRIO__SHIFT = 0x3 # macro +SQ_WAVE_STATUS__PRIV__SHIFT = 0x5 # macro +SQ_WAVE_STATUS__TRAP_EN__SHIFT = 0x6 # macro +SQ_WAVE_STATUS__TTRACE_EN__SHIFT = 0x7 # macro +SQ_WAVE_STATUS__EXPORT_RDY__SHIFT = 0x8 # macro +SQ_WAVE_STATUS__EXECZ__SHIFT = 0x9 # macro +SQ_WAVE_STATUS__VCCZ__SHIFT = 0xa # macro +SQ_WAVE_STATUS__IN_TG__SHIFT = 0xb # macro +SQ_WAVE_STATUS__IN_BARRIER__SHIFT = 0xc # macro +SQ_WAVE_STATUS__HALT__SHIFT = 0xd # macro +SQ_WAVE_STATUS__TRAP__SHIFT = 0xe # macro +SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT = 0xf # macro +SQ_WAVE_STATUS__VALID__SHIFT = 0x10 # macro +SQ_WAVE_STATUS__ECC_ERR__SHIFT = 0x11 # macro +SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT = 0x12 # macro +SQ_WAVE_STATUS__PERF_EN__SHIFT = 0x13 # macro +SQ_WAVE_STATUS__COND_DBG_USER__SHIFT = 0x14 # macro +SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT = 0x15 # macro +SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT = 0x16 # macro +SQ_WAVE_STATUS__FATAL_HALT__SHIFT = 0x17 # macro +SQ_WAVE_STATUS__MUST_EXPORT__SHIFT = 0x1b # macro +SQ_WAVE_STATUS__SCRATCH_EN__SHIFT = 0x1c # macro +SQ_WAVE_STATUS__IDLE__SHIFT = 0x1f # macro +SQ_WAVE_STATUS__SCC_MASK = 0x00000001 # macro +SQ_WAVE_STATUS__SPI_PRIO_MASK = 0x00000006 # macro +SQ_WAVE_STATUS__USER_PRIO_MASK = 0x00000018 # macro +SQ_WAVE_STATUS__PRIV_MASK = 0x00000020 # macro +SQ_WAVE_STATUS__TRAP_EN_MASK = 0x00000040 # macro +SQ_WAVE_STATUS__TTRACE_EN_MASK = 0x00000080 # macro +SQ_WAVE_STATUS__EXPORT_RDY_MASK = 0x00000100 # macro +SQ_WAVE_STATUS__EXECZ_MASK = 0x00000200 # macro +SQ_WAVE_STATUS__VCCZ_MASK = 0x00000400 # macro +SQ_WAVE_STATUS__IN_TG_MASK = 0x00000800 # macro +SQ_WAVE_STATUS__IN_BARRIER_MASK = 0x00001000 # macro +SQ_WAVE_STATUS__HALT_MASK = 0x00002000 # macro +SQ_WAVE_STATUS__TRAP_MASK = 0x00004000 # macro +SQ_WAVE_STATUS__TTRACE_CU_EN_MASK = 0x00008000 # macro +SQ_WAVE_STATUS__VALID_MASK = 0x00010000 # macro +SQ_WAVE_STATUS__ECC_ERR_MASK = 0x00020000 # macro +SQ_WAVE_STATUS__SKIP_EXPORT_MASK = 0x00040000 # macro +SQ_WAVE_STATUS__PERF_EN_MASK = 0x00080000 # macro +SQ_WAVE_STATUS__COND_DBG_USER_MASK = 0x00100000 # macro +SQ_WAVE_STATUS__COND_DBG_SYS_MASK = 0x00200000 # macro +SQ_WAVE_STATUS__ALLOW_REPLAY_MASK = 0x00400000 # macro +SQ_WAVE_STATUS__FATAL_HALT_MASK = 0x00800000 # macro +SQ_WAVE_STATUS__MUST_EXPORT_MASK = 0x08000000 # macro +SQ_WAVE_STATUS__SCRATCH_EN_MASK = 0x10000000 # macro +SQ_WAVE_STATUS__IDLE_MASK = 0x80000000 # macro +SQ_WAVE_TRAPSTS__EXCP__SHIFT = 0x0 # macro +SQ_WAVE_TRAPSTS__SAVECTX__SHIFT = 0xa # macro +SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT = 0xb # macro +SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT = 0xc # macro +SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT = 0x10 # macro +SQ_WAVE_TRAPSTS__HOST_TRAP__SHIFT = 0x16 # macro +SQ_WAVE_TRAPSTS__WAVE_END__SHIFT = 0x18 # macro +SQ_WAVE_TRAPSTS__TRAP_AFTER_INST__SHIFT = 0x19 # macro +SQ_WAVE_TRAPSTS__PERF_SNAPSHOT__SHIFT = 0x1a # macro +SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT = 0x1c # macro +SQ_WAVE_TRAPSTS__DP_RATE__SHIFT = 0x1d # macro +SQ_WAVE_TRAPSTS__EXCP_MASK = 0x000001FF # macro +SQ_WAVE_TRAPSTS__SAVECTX_MASK = 0x00000400 # macro +SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK = 0x00000800 # macro +SQ_WAVE_TRAPSTS__EXCP_HI_MASK = 0x00007000 # macro +SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK = 0x003F0000 # macro +SQ_WAVE_TRAPSTS__HOST_TRAP_MASK = 0x00400000 # macro +SQ_WAVE_TRAPSTS__WAVE_END_MASK = 0x01000000 # macro +SQ_WAVE_TRAPSTS__TRAP_AFTER_INST_MASK = 0x02000000 # macro +SQ_WAVE_TRAPSTS__PERF_SNAPSHOT_MASK = 0x04000000 # macro +SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK = 0x10000000 # macro +SQ_WAVE_TRAPSTS__DP_RATE_MASK = 0xE0000000 # macro +SQ_WAVE_HW_ID__WAVE_ID__SHIFT = 0x0 # macro +SQ_WAVE_HW_ID__SIMD_ID__SHIFT = 0x4 # macro +SQ_WAVE_HW_ID__PIPE_ID__SHIFT = 0x6 # macro +SQ_WAVE_HW_ID__CU_ID__SHIFT = 0x8 # macro +SQ_WAVE_HW_ID__SH_ID__SHIFT = 0xc # macro +SQ_WAVE_HW_ID__SE_ID__SHIFT = 0xd # macro +SQ_WAVE_HW_ID__TG_ID__SHIFT = 0x10 # macro +SQ_WAVE_HW_ID__VM_ID__SHIFT = 0x14 # macro +SQ_WAVE_HW_ID__QUEUE_ID__SHIFT = 0x18 # macro +SQ_WAVE_HW_ID__STATE_ID__SHIFT = 0x1b # macro +SQ_WAVE_HW_ID__ME_ID__SHIFT = 0x1e # macro +SQ_WAVE_HW_ID__WAVE_ID_MASK = 0x0000000F # macro +SQ_WAVE_HW_ID__SIMD_ID_MASK = 0x00000030 # macro +SQ_WAVE_HW_ID__PIPE_ID_MASK = 0x000000C0 # macro +SQ_WAVE_HW_ID__CU_ID_MASK = 0x00000F00 # macro +SQ_WAVE_HW_ID__SH_ID_MASK = 0x00001000 # macro +SQ_WAVE_HW_ID__SE_ID_MASK = 0x0000E000 # macro +SQ_WAVE_HW_ID__TG_ID_MASK = 0x000F0000 # macro +SQ_WAVE_HW_ID__VM_ID_MASK = 0x00F00000 # macro +SQ_WAVE_HW_ID__QUEUE_ID_MASK = 0x07000000 # macro +SQ_WAVE_HW_ID__STATE_ID_MASK = 0x38000000 # macro +SQ_WAVE_HW_ID__ME_ID_MASK = 0xC0000000 # macro +SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT = 0x0 # macro +SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT = 0x6 # macro +SQ_WAVE_GPR_ALLOC__ACCV_OFFSET__SHIFT = 0xc # macro +SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT = 0x12 # macro +SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT = 0x18 # macro +SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK = 0x0000003F # macro +SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK = 0x00000FC0 # macro +SQ_WAVE_GPR_ALLOC__ACCV_OFFSET_MASK = 0x0003F000 # macro +SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK = 0x00FC0000 # macro +SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK = 0x0F000000 # macro +SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT = 0x0 # macro +SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT = 0xc # macro +SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK = 0x000000FF # macro +SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK = 0x001FF000 # macro +SQ_WAVE_IB_STS__VM_CNT__SHIFT = 0x0 # macro +SQ_WAVE_IB_STS__EXP_CNT__SHIFT = 0x4 # macro +SQ_WAVE_IB_STS__LGKM_CNT__SHIFT = 0x8 # macro +SQ_WAVE_IB_STS__VALU_CNT__SHIFT = 0xc # macro +SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT = 0xf # macro +SQ_WAVE_IB_STS__RCNT__SHIFT = 0x10 # macro +SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT = 0x16 # macro +SQ_WAVE_IB_STS__VM_CNT_MASK = 0x0000000F # macro +SQ_WAVE_IB_STS__EXP_CNT_MASK = 0x00000070 # macro +SQ_WAVE_IB_STS__LGKM_CNT_MASK = 0x00000F00 # macro +SQ_WAVE_IB_STS__VALU_CNT_MASK = 0x00007000 # macro +SQ_WAVE_IB_STS__FIRST_REPLAY_MASK = 0x00008000 # macro +SQ_WAVE_IB_STS__RCNT_MASK = 0x001F0000 # macro +SQ_WAVE_IB_STS__VM_CNT_HI_MASK = 0x00C00000 # macro +SQ_WAVE_PC_LO__PC_LO__SHIFT = 0x0 # macro +SQ_WAVE_PC_LO__PC_LO_MASK = 0xFFFFFFFF # macro +SQ_WAVE_PC_HI__PC_HI__SHIFT = 0x0 # macro +SQ_WAVE_PC_HI__PC_HI_MASK = 0x0000FFFF # macro +SQ_WAVE_INST_DW0__INST_DW0__SHIFT = 0x0 # macro +SQ_WAVE_INST_DW0__INST_DW0_MASK = 0xFFFFFFFF # macro +SQ_WAVE_INST_DW1__INST_DW1__SHIFT = 0x0 # macro +SQ_WAVE_INST_DW1__INST_DW1_MASK = 0xFFFFFFFF # macro +SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT = 0x0 # macro +SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT = 0x3 # macro +SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT = 0x4 # macro +SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT = 0x5 # macro +SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT = 0x8 # macro +SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT = 0xa # macro +SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT = 0x10 # macro +SQ_WAVE_IB_DBG0__ECC_ST__SHIFT = 0x18 # macro +SQ_WAVE_IB_DBG0__IS_HYB__SHIFT = 0x1a # macro +SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT = 0x1b # macro +SQ_WAVE_IB_DBG0__KILL__SHIFT = 0x1d # macro +SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT = 0x1e # macro +SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI__SHIFT = 0x1f # macro +SQ_WAVE_IB_DBG0__IBUF_ST_MASK = 0x00000007 # macro +SQ_WAVE_IB_DBG0__PC_INVALID_MASK = 0x00000008 # macro +SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK = 0x00000010 # macro +SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK = 0x000000E0 # macro +SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK = 0x00000300 # macro +SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK = 0x00000C00 # macro +SQ_WAVE_IB_DBG0__INST_STR_ST_MASK = 0x000F0000 # macro +SQ_WAVE_IB_DBG0__ECC_ST_MASK = 0x03000000 # macro +SQ_WAVE_IB_DBG0__IS_HYB_MASK = 0x04000000 # macro +SQ_WAVE_IB_DBG0__HYB_CNT_MASK = 0x18000000 # macro +SQ_WAVE_IB_DBG0__KILL_MASK = 0x20000000 # macro +SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK = 0x40000000 # macro +SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI_MASK = 0x80000000 # macro +SQ_WAVE_IB_DBG1__IXNACK__SHIFT = 0x0 # macro +SQ_WAVE_IB_DBG1__XNACK__SHIFT = 0x1 # macro +SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT = 0x2 # macro +SQ_WAVE_IB_DBG1__XCNT__SHIFT = 0x4 # macro +SQ_WAVE_IB_DBG1__QCNT__SHIFT = 0xb # macro +SQ_WAVE_IB_DBG1__RCNT__SHIFT = 0x12 # macro +SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT = 0x19 # macro +SQ_WAVE_IB_DBG1__IXNACK_MASK = 0x00000001 # macro +SQ_WAVE_IB_DBG1__XNACK_MASK = 0x00000002 # macro +SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK = 0x00000004 # macro +SQ_WAVE_IB_DBG1__XCNT_MASK = 0x000001F0 # macro +SQ_WAVE_IB_DBG1__QCNT_MASK = 0x0000F800 # macro +SQ_WAVE_IB_DBG1__RCNT_MASK = 0x007C0000 # macro +SQ_WAVE_IB_DBG1__MISC_CNT_MASK = 0xFE000000 # macro +SQ_WAVE_FLUSH_IB__UNUSED__SHIFT = 0x0 # macro +SQ_WAVE_FLUSH_IB__UNUSED_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP0__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP0__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP1__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP1__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP2__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP2__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP3__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP3__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP4__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP4__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP5__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP5__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP6__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP6__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP7__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP7__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP8__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP8__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP9__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP9__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP10__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP10__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP11__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP11__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP12__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP12__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP13__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP13__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP14__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP14__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_TTMP15__DATA__SHIFT = 0x0 # macro +SQ_WAVE_TTMP15__DATA_MASK = 0xFFFFFFFF # macro +SQ_WAVE_M0__M0__SHIFT = 0x0 # macro +SQ_WAVE_M0__M0_MASK = 0xFFFFFFFF # macro +SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT = 0x0 # macro +SQ_WAVE_EXEC_LO__EXEC_LO_MASK = 0xFFFFFFFF # macro +SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT = 0x0 # macro +SQ_WAVE_EXEC_HI__EXEC_HI_MASK = 0xFFFFFFFF # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT = 0x0 # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT = 0x1 # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT = 0x2 # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT = 0x3 # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT = 0x4 # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT = 0x5 # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT = 0x6 # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT = 0x7 # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT = 0x8 # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT = 0x18 # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT = 0x1a # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK = 0x0000001 # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK = 0x0000002 # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK = 0x0000004 # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK = 0x0000008 # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK = 0x0000010 # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK = 0x0000020 # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK = 0x0000040 # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK = 0x0000080 # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK = 0x0000100 # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK = 0x3000000 # macro +SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK = 0xC000000 # macro +SQ_INTERRUPT_WORD_AUTO_HI__SE_ID__SHIFT = 0x8 # macro +SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT = 0xa # macro +SQ_INTERRUPT_WORD_AUTO_HI__SE_ID_MASK = 0x300 # macro +SQ_INTERRUPT_WORD_AUTO_HI__ENCODING_MASK = 0xC00 # macro +SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE__SHIFT = 0x0 # macro +SQ_INTERRUPT_WORD_AUTO_LO__WLT__SHIFT = 0x1 # macro +SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL__SHIFT = 0x2 # macro +SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP__SHIFT = 0x3 # macro +SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP__SHIFT = 0x4 # macro +SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW__SHIFT = 0x5 # macro +SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW__SHIFT = 0x6 # macro +SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW__SHIFT = 0x7 # macro +SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR__SHIFT = 0x8 # macro +SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_MASK = 0x001 # macro +SQ_INTERRUPT_WORD_AUTO_LO__WLT_MASK = 0x002 # macro +SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL_MASK = 0x004 # macro +SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP_MASK = 0x008 # macro +SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP_MASK = 0x010 # macro +SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW_MASK = 0x020 # macro +SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW_MASK = 0x040 # macro +SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW_MASK = 0x080 # macro +SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR_MASK = 0x100 # macro +SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID__SHIFT = 0x18 # macro +SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING__SHIFT = 0x1a # macro +SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID_MASK = 0x3000000 # macro +SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING_MASK = 0xC000000 # macro +SQ_INTERRUPT_WORD_CMN_HI__SE_ID__SHIFT = 0x8 # macro +SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT = 0xa # macro +SQ_INTERRUPT_WORD_CMN_HI__SE_ID_MASK = 0x300 # macro +SQ_INTERRUPT_WORD_CMN_HI__ENCODING_MASK = 0xC00 # macro +SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT = 0x0 # macro +SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT = 0xc # macro +SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT = 0xd # macro +SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT = 0xe # macro +SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT = 0x12 # macro +SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT = 0x14 # macro +SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT = 0x18 # macro +SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT = 0x1a # macro +SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK = 0x0000FFF # macro +SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK = 0x0001000 # macro +SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK = 0x0002000 # macro +SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK = 0x003C000 # macro +SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK = 0x00C0000 # macro +SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK = 0x0F00000 # macro +SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK = 0x3000000 # macro +SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK = 0xC000000 # macro +SQ_INTERRUPT_WORD_WAVE_HI__CU_ID__SHIFT = 0x0 # macro +SQ_INTERRUPT_WORD_WAVE_HI__VM_ID__SHIFT = 0x4 # macro +SQ_INTERRUPT_WORD_WAVE_HI__SE_ID__SHIFT = 0x8 # macro +SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT = 0xa # macro +SQ_INTERRUPT_WORD_WAVE_HI__CU_ID_MASK = 0x00F # macro +SQ_INTERRUPT_WORD_WAVE_HI__VM_ID_MASK = 0x0F0 # macro +SQ_INTERRUPT_WORD_WAVE_HI__SE_ID_MASK = 0x300 # macro +SQ_INTERRUPT_WORD_WAVE_HI__ENCODING_MASK = 0xC00 # macro +SQ_INTERRUPT_WORD_WAVE_LO__DATA__SHIFT = 0x0 # macro +SQ_INTERRUPT_WORD_WAVE_LO__SH_ID__SHIFT = 0x18 # macro +SQ_INTERRUPT_WORD_WAVE_LO__PRIV__SHIFT = 0x19 # macro +SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID__SHIFT = 0x1a # macro +SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID__SHIFT = 0x1e # macro +SQ_INTERRUPT_WORD_WAVE_LO__DATA_MASK = 0x00FFFFFF # macro +SQ_INTERRUPT_WORD_WAVE_LO__SH_ID_MASK = 0x01000000 # macro +SQ_INTERRUPT_WORD_WAVE_LO__PRIV_MASK = 0x02000000 # macro +SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID_MASK = 0x3C000000 # macro +SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID_MASK = 0xC0000000 # macro +regCOMPUTE_CURRENT_LOGIC_XCC_ID = 0x0e25 # macro +regCOMPUTE_CURRENT_LOGIC_XCC_ID_BASE_IDX = 0 # macro +COMPUTE_CURRENT_LOGIC_XCC_ID__CURRENT_LOGIC_XCC_ID__SHIFT = 0x0 # macro +COMPUTE_CURRENT_LOGIC_XCC_ID__CURRENT_LOGIC_XCC_ID_MASK = 0xFFFFFFFF # macro +__all__ = \ + ['ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK', + 'ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT', + 'ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK', + 'ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT', + 'ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK', + 'ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT', + 'ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK', + 'ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT', + 'ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK', + 'ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT', + 'ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK', + 'ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT', + 'ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK', + 'ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT', + 'ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK', + 'ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT', + 'ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK', + 'ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT', + 'ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK', + 'ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT', + 'ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT_MASK', + 'ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT__SHIFT', + 'ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK', + 'ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT', + 'ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK', + 'ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT', + 'ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK', + 'ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT', + 'ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY_MASK', + 'ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY__SHIFT', + 'ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT_MASK', + 'ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT__SHIFT', + 'ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY_MASK', + 'ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT', + 'ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE_MASK', + 'ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE__SHIFT', + 'ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS_MASK', + 'ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS__SHIFT', + 'ATC_L2_CACHE_32K_DSM_INDEX__INDEX_MASK', + 'ATC_L2_CACHE_32K_DSM_INDEX__INDEX__SHIFT', + 'ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK', + 'ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT', + 'ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK', + 'ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT', + 'ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK', + 'ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT', + 'ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK', + 'ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT', + 'ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK', + 'ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT', + 'ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK', + 'ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT', + 'ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK', + 'ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT', + 'ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK', + 'ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT', + 'ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK', + 'ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT', + 'ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK', + 'ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT', + 'ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK', + 'ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT', + 'ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK', + 'ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT', + 'ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK', + 'ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT', + 'ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK', + 'ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT', + 'ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK', + 'ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT', + 'ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK', + 'ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT', + 'ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS_MASK', + 'ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS__SHIFT', + 'ATC_L2_CE_ERR_STATUS_HI__CE_CNT_MASK', + 'ATC_L2_CE_ERR_STATUS_HI__CE_CNT__SHIFT', + 'ATC_L2_CE_ERR_STATUS_HI__ECC_MASK', + 'ATC_L2_CE_ERR_STATUS_HI__ECC__SHIFT', + 'ATC_L2_CE_ERR_STATUS_HI__ERR_INFO_MASK', + 'ATC_L2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'ATC_L2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'ATC_L2_CE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'ATC_L2_CE_ERR_STATUS_HI__OTHER_MASK', + 'ATC_L2_CE_ERR_STATUS_HI__OTHER__SHIFT', + 'ATC_L2_CE_ERR_STATUS_HI__POISON_MASK', + 'ATC_L2_CE_ERR_STATUS_HI__POISON__SHIFT', + 'ATC_L2_CE_ERR_STATUS_HI__RESERVED_MASK', + 'ATC_L2_CE_ERR_STATUS_HI__RESERVED__SHIFT', + 'ATC_L2_CE_ERR_STATUS_LO__ADDRESS_MASK', + 'ATC_L2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'ATC_L2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'ATC_L2_CE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'ATC_L2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'ATC_L2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'ATC_L2_CE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'ATC_L2_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK', + 'ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT', + 'ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK', + 'ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT', + 'ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK', + 'ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT', + 'ATC_L2_CNTL2__BANK_SELECT_MASK', + 'ATC_L2_CNTL2__BANK_SELECT__SHIFT', + 'ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK', + 'ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT', + 'ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK', + 'ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT', + 'ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK', + 'ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT', + 'ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK', + 'ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT', + 'ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK', + 'ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT', + 'ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK', + 'ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT', + 'ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK', + 'ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT', + 'ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK', + 'ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT', + 'ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK', + 'ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT', + 'ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE_MASK', + 'ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE__SHIFT', + 'ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE_MASK', + 'ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE__SHIFT', + 'ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE_MASK', + 'ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE__SHIFT', + 'ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK', + 'ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT', + 'ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK', + 'ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT', + 'ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK', + 'ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT', + 'ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK', + 'ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT', + 'ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK', + 'ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT', + 'ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK', + 'ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT', + 'ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK', + 'ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT', + 'ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK', + 'ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT', + 'ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK', + 'ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT', + 'ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK', + 'ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT', + 'ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK', + 'ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT', + 'ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK', + 'ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT', + 'ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK', + 'ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT', + 'ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK', + 'ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT', + 'ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK', + 'ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT', + 'ATC_L2_MEM_POWER_LS__LS_HOLD_MASK', + 'ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT', + 'ATC_L2_MEM_POWER_LS__LS_SETUP_MASK', + 'ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT', + 'ATC_L2_MISC_CG__ENABLE_MASK', 'ATC_L2_MISC_CG__ENABLE__SHIFT', + 'ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK', + 'ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT', + 'ATC_L2_MISC_CG__OFFDLY_MASK', 'ATC_L2_MISC_CG__OFFDLY__SHIFT', + 'ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK', + 'ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT', + 'ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK', + 'ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK', + 'ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK', + 'ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK', + 'ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'ATC_L2_STATUS2__UCE_MASK', 'ATC_L2_STATUS2__UCE_MEM_ADDR_MASK', + 'ATC_L2_STATUS2__UCE_MEM_ADDR__SHIFT', + 'ATC_L2_STATUS2__UCE_MEM_INST_MASK', + 'ATC_L2_STATUS2__UCE_MEM_INST__SHIFT', + 'ATC_L2_STATUS2__UCE_SRT_CACHE_MASK', + 'ATC_L2_STATUS2__UCE_SRT_CACHE__SHIFT', + 'ATC_L2_STATUS2__UCE__SHIFT', 'ATC_L2_STATUS__BUSY_MASK', + 'ATC_L2_STATUS__BUSY__SHIFT', + 'ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS_MASK', + 'ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS__SHIFT', + 'ATC_L2_UE_ERR_STATUS_HI__ECC_MASK', + 'ATC_L2_UE_ERR_STATUS_HI__ECC__SHIFT', + 'ATC_L2_UE_ERR_STATUS_HI__ERR_INFO_MASK', + 'ATC_L2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'ATC_L2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'ATC_L2_UE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'ATC_L2_UE_ERR_STATUS_HI__FED_CNT_MASK', + 'ATC_L2_UE_ERR_STATUS_HI__FED_CNT__SHIFT', + 'ATC_L2_UE_ERR_STATUS_HI__PARITY_MASK', + 'ATC_L2_UE_ERR_STATUS_HI__PARITY__SHIFT', + 'ATC_L2_UE_ERR_STATUS_HI__RESERVED_MASK', + 'ATC_L2_UE_ERR_STATUS_HI__RESERVED__SHIFT', + 'ATC_L2_UE_ERR_STATUS_HI__UE_CNT_MASK', + 'ATC_L2_UE_ERR_STATUS_HI__UE_CNT__SHIFT', + 'ATC_L2_UE_ERR_STATUS_LO__ADDRESS_MASK', + 'ATC_L2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'ATC_L2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'ATC_L2_UE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'ATC_L2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'ATC_L2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'ATC_L2_UE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'ATC_L2_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'BCI_DEBUG_READ__DATA_MASK', 'BCI_DEBUG_READ__DATA__SHIFT', + 'CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK', + 'CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT', + 'CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK', + 'CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT', + 'CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK', + 'CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT', + 'CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK', + 'CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT', + 'CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK', + 'CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT', + 'CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK', + 'CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT', + 'CB_BLEND0_CONTROL__DISABLE_ROP3_MASK', + 'CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT', + 'CB_BLEND0_CONTROL__ENABLE_MASK', + 'CB_BLEND0_CONTROL__ENABLE__SHIFT', + 'CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK', + 'CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT', + 'CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK', + 'CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT', + 'CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK', + 'CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT', + 'CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK', + 'CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT', + 'CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK', + 'CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT', + 'CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK', + 'CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT', + 'CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK', + 'CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT', + 'CB_BLEND1_CONTROL__DISABLE_ROP3_MASK', + 'CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT', + 'CB_BLEND1_CONTROL__ENABLE_MASK', + 'CB_BLEND1_CONTROL__ENABLE__SHIFT', + 'CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK', + 'CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT', + 'CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK', + 'CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT', + 'CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK', + 'CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT', + 'CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK', + 'CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT', + 'CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK', + 'CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT', + 'CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK', + 'CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT', + 'CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK', + 'CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT', + 'CB_BLEND2_CONTROL__DISABLE_ROP3_MASK', + 'CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT', + 'CB_BLEND2_CONTROL__ENABLE_MASK', + 'CB_BLEND2_CONTROL__ENABLE__SHIFT', + 'CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK', + 'CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT', + 'CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK', + 'CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT', + 'CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK', + 'CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT', + 'CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK', + 'CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT', + 'CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK', + 'CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT', + 'CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK', + 'CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT', + 'CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK', + 'CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT', + 'CB_BLEND3_CONTROL__DISABLE_ROP3_MASK', + 'CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT', + 'CB_BLEND3_CONTROL__ENABLE_MASK', + 'CB_BLEND3_CONTROL__ENABLE__SHIFT', + 'CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK', + 'CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT', + 'CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK', + 'CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT', + 'CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK', + 'CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT', + 'CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK', + 'CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT', + 'CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK', + 'CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT', + 'CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK', + 'CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT', + 'CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK', + 'CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT', + 'CB_BLEND4_CONTROL__DISABLE_ROP3_MASK', + 'CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT', + 'CB_BLEND4_CONTROL__ENABLE_MASK', + 'CB_BLEND4_CONTROL__ENABLE__SHIFT', + 'CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK', + 'CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT', + 'CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK', + 'CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT', + 'CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK', + 'CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT', + 'CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK', + 'CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT', + 'CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK', + 'CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT', + 'CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK', + 'CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT', + 'CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK', + 'CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT', + 'CB_BLEND5_CONTROL__DISABLE_ROP3_MASK', + 'CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT', + 'CB_BLEND5_CONTROL__ENABLE_MASK', + 'CB_BLEND5_CONTROL__ENABLE__SHIFT', + 'CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK', + 'CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT', + 'CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK', + 'CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT', + 'CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK', + 'CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT', + 'CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK', + 'CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT', + 'CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK', + 'CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT', + 'CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK', + 'CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT', + 'CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK', + 'CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT', + 'CB_BLEND6_CONTROL__DISABLE_ROP3_MASK', + 'CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT', + 'CB_BLEND6_CONTROL__ENABLE_MASK', + 'CB_BLEND6_CONTROL__ENABLE__SHIFT', + 'CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK', + 'CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT', + 'CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK', + 'CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT', + 'CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK', + 'CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT', + 'CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK', + 'CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT', + 'CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK', + 'CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT', + 'CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK', + 'CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT', + 'CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK', + 'CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT', + 'CB_BLEND7_CONTROL__DISABLE_ROP3_MASK', + 'CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT', + 'CB_BLEND7_CONTROL__ENABLE_MASK', + 'CB_BLEND7_CONTROL__ENABLE__SHIFT', + 'CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK', + 'CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT', + 'CB_BLEND_ALPHA__BLEND_ALPHA_MASK', + 'CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT', + 'CB_BLEND_BLUE__BLEND_BLUE_MASK', + 'CB_BLEND_BLUE__BLEND_BLUE__SHIFT', + 'CB_BLEND_GREEN__BLEND_GREEN_MASK', + 'CB_BLEND_GREEN__BLEND_GREEN__SHIFT', + 'CB_BLEND_RED__BLEND_RED_MASK', 'CB_BLEND_RED__BLEND_RED__SHIFT', + 'CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK', + 'CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CB_CGTT_SCLK_CTRL__ON_DELAY_MASK', + 'CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK', + 'CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT', + 'CB_COLOR0_ATTRIB2__MAX_MIP_MASK', + 'CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT', + 'CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK', + 'CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT', + 'CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK', + 'CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT', + 'CB_COLOR0_ATTRIB__COLOR_SW_MODE_MASK', + 'CB_COLOR0_ATTRIB__COLOR_SW_MODE__SHIFT', + 'CB_COLOR0_ATTRIB__FMASK_SW_MODE_MASK', + 'CB_COLOR0_ATTRIB__FMASK_SW_MODE__SHIFT', + 'CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK', + 'CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT', + 'CB_COLOR0_ATTRIB__META_LINEAR_MASK', + 'CB_COLOR0_ATTRIB__META_LINEAR__SHIFT', + 'CB_COLOR0_ATTRIB__MIP0_DEPTH_MASK', + 'CB_COLOR0_ATTRIB__MIP0_DEPTH__SHIFT', + 'CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK', + 'CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT', + 'CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK', + 'CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT', + 'CB_COLOR0_ATTRIB__PIPE_ALIGNED_MASK', + 'CB_COLOR0_ATTRIB__PIPE_ALIGNED__SHIFT', + 'CB_COLOR0_ATTRIB__RB_ALIGNED_MASK', + 'CB_COLOR0_ATTRIB__RB_ALIGNED__SHIFT', + 'CB_COLOR0_ATTRIB__RESOURCE_TYPE_MASK', + 'CB_COLOR0_ATTRIB__RESOURCE_TYPE__SHIFT', + 'CB_COLOR0_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR0_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR0_BASE__BASE_256B_MASK', + 'CB_COLOR0_BASE__BASE_256B__SHIFT', + 'CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK', + 'CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT', + 'CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK', + 'CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT', + 'CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR0_CMASK__BASE_256B_MASK', + 'CB_COLOR0_CMASK__BASE_256B__SHIFT', + 'CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR0_DCC_BASE__BASE_256B_MASK', + 'CB_COLOR0_DCC_BASE__BASE_256B__SHIFT', + 'CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK', + 'CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT', + 'CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK', + 'CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT', + 'CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK', + 'CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT', + 'CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK', + 'CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT', + 'CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK', + 'CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT', + 'CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK', + 'CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT', + 'CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK', + 'CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT', + 'CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK', + 'CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT', + 'CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR0_FMASK__BASE_256B_MASK', + 'CB_COLOR0_FMASK__BASE_256B__SHIFT', + 'CB_COLOR0_INFO__BLEND_BYPASS_MASK', + 'CB_COLOR0_INFO__BLEND_BYPASS__SHIFT', + 'CB_COLOR0_INFO__BLEND_CLAMP_MASK', + 'CB_COLOR0_INFO__BLEND_CLAMP__SHIFT', + 'CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK', + 'CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT', + 'CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK', + 'CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT', + 'CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK', + 'CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT', + 'CB_COLOR0_INFO__COMPRESSION_MASK', + 'CB_COLOR0_INFO__COMPRESSION__SHIFT', + 'CB_COLOR0_INFO__COMP_SWAP_MASK', + 'CB_COLOR0_INFO__COMP_SWAP__SHIFT', + 'CB_COLOR0_INFO__DCC_ENABLE_MASK', + 'CB_COLOR0_INFO__DCC_ENABLE__SHIFT', + 'CB_COLOR0_INFO__ENDIAN_MASK', 'CB_COLOR0_INFO__ENDIAN__SHIFT', + 'CB_COLOR0_INFO__FAST_CLEAR_MASK', + 'CB_COLOR0_INFO__FAST_CLEAR__SHIFT', + 'CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK', + 'CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT', + 'CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK', + 'CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT', + 'CB_COLOR0_INFO__FORMAT_MASK', 'CB_COLOR0_INFO__FORMAT__SHIFT', + 'CB_COLOR0_INFO__NUMBER_TYPE_MASK', + 'CB_COLOR0_INFO__NUMBER_TYPE__SHIFT', + 'CB_COLOR0_INFO__ROUND_MODE_MASK', + 'CB_COLOR0_INFO__ROUND_MODE__SHIFT', + 'CB_COLOR0_INFO__SIMPLE_FLOAT_MASK', + 'CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT', + 'CB_COLOR0_VIEW__MIP_LEVEL_MASK', + 'CB_COLOR0_VIEW__MIP_LEVEL__SHIFT', + 'CB_COLOR0_VIEW__SLICE_MAX_MASK', + 'CB_COLOR0_VIEW__SLICE_MAX__SHIFT', + 'CB_COLOR0_VIEW__SLICE_START_MASK', + 'CB_COLOR0_VIEW__SLICE_START__SHIFT', + 'CB_COLOR1_ATTRIB2__MAX_MIP_MASK', + 'CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT', + 'CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK', + 'CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT', + 'CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK', + 'CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT', + 'CB_COLOR1_ATTRIB__COLOR_SW_MODE_MASK', + 'CB_COLOR1_ATTRIB__COLOR_SW_MODE__SHIFT', + 'CB_COLOR1_ATTRIB__FMASK_SW_MODE_MASK', + 'CB_COLOR1_ATTRIB__FMASK_SW_MODE__SHIFT', + 'CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK', + 'CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT', + 'CB_COLOR1_ATTRIB__META_LINEAR_MASK', + 'CB_COLOR1_ATTRIB__META_LINEAR__SHIFT', + 'CB_COLOR1_ATTRIB__MIP0_DEPTH_MASK', + 'CB_COLOR1_ATTRIB__MIP0_DEPTH__SHIFT', + 'CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK', + 'CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT', + 'CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK', + 'CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT', + 'CB_COLOR1_ATTRIB__PIPE_ALIGNED_MASK', + 'CB_COLOR1_ATTRIB__PIPE_ALIGNED__SHIFT', + 'CB_COLOR1_ATTRIB__RB_ALIGNED_MASK', + 'CB_COLOR1_ATTRIB__RB_ALIGNED__SHIFT', + 'CB_COLOR1_ATTRIB__RESOURCE_TYPE_MASK', + 'CB_COLOR1_ATTRIB__RESOURCE_TYPE__SHIFT', + 'CB_COLOR1_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR1_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR1_BASE__BASE_256B_MASK', + 'CB_COLOR1_BASE__BASE_256B__SHIFT', + 'CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK', + 'CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT', + 'CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK', + 'CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT', + 'CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR1_CMASK__BASE_256B_MASK', + 'CB_COLOR1_CMASK__BASE_256B__SHIFT', + 'CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR1_DCC_BASE__BASE_256B_MASK', + 'CB_COLOR1_DCC_BASE__BASE_256B__SHIFT', + 'CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK', + 'CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT', + 'CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK', + 'CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT', + 'CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK', + 'CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT', + 'CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK', + 'CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT', + 'CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK', + 'CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT', + 'CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK', + 'CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT', + 'CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK', + 'CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT', + 'CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK', + 'CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT', + 'CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR1_FMASK__BASE_256B_MASK', + 'CB_COLOR1_FMASK__BASE_256B__SHIFT', + 'CB_COLOR1_INFO__BLEND_BYPASS_MASK', + 'CB_COLOR1_INFO__BLEND_BYPASS__SHIFT', + 'CB_COLOR1_INFO__BLEND_CLAMP_MASK', + 'CB_COLOR1_INFO__BLEND_CLAMP__SHIFT', + 'CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK', + 'CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT', + 'CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK', + 'CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT', + 'CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK', + 'CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT', + 'CB_COLOR1_INFO__COMPRESSION_MASK', + 'CB_COLOR1_INFO__COMPRESSION__SHIFT', + 'CB_COLOR1_INFO__COMP_SWAP_MASK', + 'CB_COLOR1_INFO__COMP_SWAP__SHIFT', + 'CB_COLOR1_INFO__DCC_ENABLE_MASK', + 'CB_COLOR1_INFO__DCC_ENABLE__SHIFT', + 'CB_COLOR1_INFO__ENDIAN_MASK', 'CB_COLOR1_INFO__ENDIAN__SHIFT', + 'CB_COLOR1_INFO__FAST_CLEAR_MASK', + 'CB_COLOR1_INFO__FAST_CLEAR__SHIFT', + 'CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK', + 'CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT', + 'CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK', + 'CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT', + 'CB_COLOR1_INFO__FORMAT_MASK', 'CB_COLOR1_INFO__FORMAT__SHIFT', + 'CB_COLOR1_INFO__NUMBER_TYPE_MASK', + 'CB_COLOR1_INFO__NUMBER_TYPE__SHIFT', + 'CB_COLOR1_INFO__ROUND_MODE_MASK', + 'CB_COLOR1_INFO__ROUND_MODE__SHIFT', + 'CB_COLOR1_INFO__SIMPLE_FLOAT_MASK', + 'CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT', + 'CB_COLOR1_VIEW__MIP_LEVEL_MASK', + 'CB_COLOR1_VIEW__MIP_LEVEL__SHIFT', + 'CB_COLOR1_VIEW__SLICE_MAX_MASK', + 'CB_COLOR1_VIEW__SLICE_MAX__SHIFT', + 'CB_COLOR1_VIEW__SLICE_START_MASK', + 'CB_COLOR1_VIEW__SLICE_START__SHIFT', + 'CB_COLOR2_ATTRIB2__MAX_MIP_MASK', + 'CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT', + 'CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK', + 'CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT', + 'CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK', + 'CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT', + 'CB_COLOR2_ATTRIB__COLOR_SW_MODE_MASK', + 'CB_COLOR2_ATTRIB__COLOR_SW_MODE__SHIFT', + 'CB_COLOR2_ATTRIB__FMASK_SW_MODE_MASK', + 'CB_COLOR2_ATTRIB__FMASK_SW_MODE__SHIFT', + 'CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK', + 'CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT', + 'CB_COLOR2_ATTRIB__META_LINEAR_MASK', + 'CB_COLOR2_ATTRIB__META_LINEAR__SHIFT', + 'CB_COLOR2_ATTRIB__MIP0_DEPTH_MASK', + 'CB_COLOR2_ATTRIB__MIP0_DEPTH__SHIFT', + 'CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK', + 'CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT', + 'CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK', + 'CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT', + 'CB_COLOR2_ATTRIB__PIPE_ALIGNED_MASK', + 'CB_COLOR2_ATTRIB__PIPE_ALIGNED__SHIFT', + 'CB_COLOR2_ATTRIB__RB_ALIGNED_MASK', + 'CB_COLOR2_ATTRIB__RB_ALIGNED__SHIFT', + 'CB_COLOR2_ATTRIB__RESOURCE_TYPE_MASK', + 'CB_COLOR2_ATTRIB__RESOURCE_TYPE__SHIFT', + 'CB_COLOR2_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR2_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR2_BASE__BASE_256B_MASK', + 'CB_COLOR2_BASE__BASE_256B__SHIFT', + 'CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK', + 'CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT', + 'CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK', + 'CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT', + 'CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR2_CMASK__BASE_256B_MASK', + 'CB_COLOR2_CMASK__BASE_256B__SHIFT', + 'CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR2_DCC_BASE__BASE_256B_MASK', + 'CB_COLOR2_DCC_BASE__BASE_256B__SHIFT', + 'CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK', + 'CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT', + 'CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK', + 'CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT', + 'CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK', + 'CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT', + 'CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK', + 'CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT', + 'CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK', + 'CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT', + 'CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK', + 'CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT', + 'CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK', + 'CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT', + 'CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK', + 'CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT', + 'CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR2_FMASK__BASE_256B_MASK', + 'CB_COLOR2_FMASK__BASE_256B__SHIFT', + 'CB_COLOR2_INFO__BLEND_BYPASS_MASK', + 'CB_COLOR2_INFO__BLEND_BYPASS__SHIFT', + 'CB_COLOR2_INFO__BLEND_CLAMP_MASK', + 'CB_COLOR2_INFO__BLEND_CLAMP__SHIFT', + 'CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK', + 'CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT', + 'CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK', + 'CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT', + 'CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK', + 'CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT', + 'CB_COLOR2_INFO__COMPRESSION_MASK', + 'CB_COLOR2_INFO__COMPRESSION__SHIFT', + 'CB_COLOR2_INFO__COMP_SWAP_MASK', + 'CB_COLOR2_INFO__COMP_SWAP__SHIFT', + 'CB_COLOR2_INFO__DCC_ENABLE_MASK', + 'CB_COLOR2_INFO__DCC_ENABLE__SHIFT', + 'CB_COLOR2_INFO__ENDIAN_MASK', 'CB_COLOR2_INFO__ENDIAN__SHIFT', + 'CB_COLOR2_INFO__FAST_CLEAR_MASK', + 'CB_COLOR2_INFO__FAST_CLEAR__SHIFT', + 'CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK', + 'CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT', + 'CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK', + 'CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT', + 'CB_COLOR2_INFO__FORMAT_MASK', 'CB_COLOR2_INFO__FORMAT__SHIFT', + 'CB_COLOR2_INFO__NUMBER_TYPE_MASK', + 'CB_COLOR2_INFO__NUMBER_TYPE__SHIFT', + 'CB_COLOR2_INFO__ROUND_MODE_MASK', + 'CB_COLOR2_INFO__ROUND_MODE__SHIFT', + 'CB_COLOR2_INFO__SIMPLE_FLOAT_MASK', + 'CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT', + 'CB_COLOR2_VIEW__MIP_LEVEL_MASK', + 'CB_COLOR2_VIEW__MIP_LEVEL__SHIFT', + 'CB_COLOR2_VIEW__SLICE_MAX_MASK', + 'CB_COLOR2_VIEW__SLICE_MAX__SHIFT', + 'CB_COLOR2_VIEW__SLICE_START_MASK', + 'CB_COLOR2_VIEW__SLICE_START__SHIFT', + 'CB_COLOR3_ATTRIB2__MAX_MIP_MASK', + 'CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT', + 'CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK', + 'CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT', + 'CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK', + 'CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT', + 'CB_COLOR3_ATTRIB__COLOR_SW_MODE_MASK', + 'CB_COLOR3_ATTRIB__COLOR_SW_MODE__SHIFT', + 'CB_COLOR3_ATTRIB__FMASK_SW_MODE_MASK', + 'CB_COLOR3_ATTRIB__FMASK_SW_MODE__SHIFT', + 'CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK', + 'CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT', + 'CB_COLOR3_ATTRIB__META_LINEAR_MASK', + 'CB_COLOR3_ATTRIB__META_LINEAR__SHIFT', + 'CB_COLOR3_ATTRIB__MIP0_DEPTH_MASK', + 'CB_COLOR3_ATTRIB__MIP0_DEPTH__SHIFT', + 'CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK', + 'CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT', + 'CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK', + 'CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT', + 'CB_COLOR3_ATTRIB__PIPE_ALIGNED_MASK', + 'CB_COLOR3_ATTRIB__PIPE_ALIGNED__SHIFT', + 'CB_COLOR3_ATTRIB__RB_ALIGNED_MASK', + 'CB_COLOR3_ATTRIB__RB_ALIGNED__SHIFT', + 'CB_COLOR3_ATTRIB__RESOURCE_TYPE_MASK', + 'CB_COLOR3_ATTRIB__RESOURCE_TYPE__SHIFT', + 'CB_COLOR3_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR3_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR3_BASE__BASE_256B_MASK', + 'CB_COLOR3_BASE__BASE_256B__SHIFT', + 'CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK', + 'CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT', + 'CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK', + 'CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT', + 'CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR3_CMASK__BASE_256B_MASK', + 'CB_COLOR3_CMASK__BASE_256B__SHIFT', + 'CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR3_DCC_BASE__BASE_256B_MASK', + 'CB_COLOR3_DCC_BASE__BASE_256B__SHIFT', + 'CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK', + 'CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT', + 'CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK', + 'CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT', + 'CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK', + 'CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT', + 'CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK', + 'CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT', + 'CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK', + 'CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT', + 'CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK', + 'CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT', + 'CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK', + 'CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT', + 'CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK', + 'CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT', + 'CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR3_FMASK__BASE_256B_MASK', + 'CB_COLOR3_FMASK__BASE_256B__SHIFT', + 'CB_COLOR3_INFO__BLEND_BYPASS_MASK', + 'CB_COLOR3_INFO__BLEND_BYPASS__SHIFT', + 'CB_COLOR3_INFO__BLEND_CLAMP_MASK', + 'CB_COLOR3_INFO__BLEND_CLAMP__SHIFT', + 'CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK', + 'CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT', + 'CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK', + 'CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT', + 'CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK', + 'CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT', + 'CB_COLOR3_INFO__COMPRESSION_MASK', + 'CB_COLOR3_INFO__COMPRESSION__SHIFT', + 'CB_COLOR3_INFO__COMP_SWAP_MASK', + 'CB_COLOR3_INFO__COMP_SWAP__SHIFT', + 'CB_COLOR3_INFO__DCC_ENABLE_MASK', + 'CB_COLOR3_INFO__DCC_ENABLE__SHIFT', + 'CB_COLOR3_INFO__ENDIAN_MASK', 'CB_COLOR3_INFO__ENDIAN__SHIFT', + 'CB_COLOR3_INFO__FAST_CLEAR_MASK', + 'CB_COLOR3_INFO__FAST_CLEAR__SHIFT', + 'CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK', + 'CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT', + 'CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK', + 'CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT', + 'CB_COLOR3_INFO__FORMAT_MASK', 'CB_COLOR3_INFO__FORMAT__SHIFT', + 'CB_COLOR3_INFO__NUMBER_TYPE_MASK', + 'CB_COLOR3_INFO__NUMBER_TYPE__SHIFT', + 'CB_COLOR3_INFO__ROUND_MODE_MASK', + 'CB_COLOR3_INFO__ROUND_MODE__SHIFT', + 'CB_COLOR3_INFO__SIMPLE_FLOAT_MASK', + 'CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT', + 'CB_COLOR3_VIEW__MIP_LEVEL_MASK', + 'CB_COLOR3_VIEW__MIP_LEVEL__SHIFT', + 'CB_COLOR3_VIEW__SLICE_MAX_MASK', + 'CB_COLOR3_VIEW__SLICE_MAX__SHIFT', + 'CB_COLOR3_VIEW__SLICE_START_MASK', + 'CB_COLOR3_VIEW__SLICE_START__SHIFT', + 'CB_COLOR4_ATTRIB2__MAX_MIP_MASK', + 'CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT', + 'CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK', + 'CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT', + 'CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK', + 'CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT', + 'CB_COLOR4_ATTRIB__COLOR_SW_MODE_MASK', + 'CB_COLOR4_ATTRIB__COLOR_SW_MODE__SHIFT', + 'CB_COLOR4_ATTRIB__FMASK_SW_MODE_MASK', + 'CB_COLOR4_ATTRIB__FMASK_SW_MODE__SHIFT', + 'CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK', + 'CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT', + 'CB_COLOR4_ATTRIB__META_LINEAR_MASK', + 'CB_COLOR4_ATTRIB__META_LINEAR__SHIFT', + 'CB_COLOR4_ATTRIB__MIP0_DEPTH_MASK', + 'CB_COLOR4_ATTRIB__MIP0_DEPTH__SHIFT', + 'CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK', + 'CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT', + 'CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK', + 'CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT', + 'CB_COLOR4_ATTRIB__PIPE_ALIGNED_MASK', + 'CB_COLOR4_ATTRIB__PIPE_ALIGNED__SHIFT', + 'CB_COLOR4_ATTRIB__RB_ALIGNED_MASK', + 'CB_COLOR4_ATTRIB__RB_ALIGNED__SHIFT', + 'CB_COLOR4_ATTRIB__RESOURCE_TYPE_MASK', + 'CB_COLOR4_ATTRIB__RESOURCE_TYPE__SHIFT', + 'CB_COLOR4_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR4_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR4_BASE__BASE_256B_MASK', + 'CB_COLOR4_BASE__BASE_256B__SHIFT', + 'CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK', + 'CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT', + 'CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK', + 'CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT', + 'CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR4_CMASK__BASE_256B_MASK', + 'CB_COLOR4_CMASK__BASE_256B__SHIFT', + 'CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR4_DCC_BASE__BASE_256B_MASK', + 'CB_COLOR4_DCC_BASE__BASE_256B__SHIFT', + 'CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK', + 'CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT', + 'CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK', + 'CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT', + 'CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK', + 'CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT', + 'CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK', + 'CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT', + 'CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK', + 'CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT', + 'CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK', + 'CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT', + 'CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK', + 'CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT', + 'CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK', + 'CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT', + 'CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR4_FMASK__BASE_256B_MASK', + 'CB_COLOR4_FMASK__BASE_256B__SHIFT', + 'CB_COLOR4_INFO__BLEND_BYPASS_MASK', + 'CB_COLOR4_INFO__BLEND_BYPASS__SHIFT', + 'CB_COLOR4_INFO__BLEND_CLAMP_MASK', + 'CB_COLOR4_INFO__BLEND_CLAMP__SHIFT', + 'CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK', + 'CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT', + 'CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK', + 'CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT', + 'CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK', + 'CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT', + 'CB_COLOR4_INFO__COMPRESSION_MASK', + 'CB_COLOR4_INFO__COMPRESSION__SHIFT', + 'CB_COLOR4_INFO__COMP_SWAP_MASK', + 'CB_COLOR4_INFO__COMP_SWAP__SHIFT', + 'CB_COLOR4_INFO__DCC_ENABLE_MASK', + 'CB_COLOR4_INFO__DCC_ENABLE__SHIFT', + 'CB_COLOR4_INFO__ENDIAN_MASK', 'CB_COLOR4_INFO__ENDIAN__SHIFT', + 'CB_COLOR4_INFO__FAST_CLEAR_MASK', + 'CB_COLOR4_INFO__FAST_CLEAR__SHIFT', + 'CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK', + 'CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT', + 'CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK', + 'CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT', + 'CB_COLOR4_INFO__FORMAT_MASK', 'CB_COLOR4_INFO__FORMAT__SHIFT', + 'CB_COLOR4_INFO__NUMBER_TYPE_MASK', + 'CB_COLOR4_INFO__NUMBER_TYPE__SHIFT', + 'CB_COLOR4_INFO__ROUND_MODE_MASK', + 'CB_COLOR4_INFO__ROUND_MODE__SHIFT', + 'CB_COLOR4_INFO__SIMPLE_FLOAT_MASK', + 'CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT', + 'CB_COLOR4_VIEW__MIP_LEVEL_MASK', + 'CB_COLOR4_VIEW__MIP_LEVEL__SHIFT', + 'CB_COLOR4_VIEW__SLICE_MAX_MASK', + 'CB_COLOR4_VIEW__SLICE_MAX__SHIFT', + 'CB_COLOR4_VIEW__SLICE_START_MASK', + 'CB_COLOR4_VIEW__SLICE_START__SHIFT', + 'CB_COLOR5_ATTRIB2__MAX_MIP_MASK', + 'CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT', + 'CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK', + 'CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT', + 'CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK', + 'CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT', + 'CB_COLOR5_ATTRIB__COLOR_SW_MODE_MASK', + 'CB_COLOR5_ATTRIB__COLOR_SW_MODE__SHIFT', + 'CB_COLOR5_ATTRIB__FMASK_SW_MODE_MASK', + 'CB_COLOR5_ATTRIB__FMASK_SW_MODE__SHIFT', + 'CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK', + 'CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT', + 'CB_COLOR5_ATTRIB__META_LINEAR_MASK', + 'CB_COLOR5_ATTRIB__META_LINEAR__SHIFT', + 'CB_COLOR5_ATTRIB__MIP0_DEPTH_MASK', + 'CB_COLOR5_ATTRIB__MIP0_DEPTH__SHIFT', + 'CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK', + 'CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT', + 'CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK', + 'CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT', + 'CB_COLOR5_ATTRIB__PIPE_ALIGNED_MASK', + 'CB_COLOR5_ATTRIB__PIPE_ALIGNED__SHIFT', + 'CB_COLOR5_ATTRIB__RB_ALIGNED_MASK', + 'CB_COLOR5_ATTRIB__RB_ALIGNED__SHIFT', + 'CB_COLOR5_ATTRIB__RESOURCE_TYPE_MASK', + 'CB_COLOR5_ATTRIB__RESOURCE_TYPE__SHIFT', + 'CB_COLOR5_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR5_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR5_BASE__BASE_256B_MASK', + 'CB_COLOR5_BASE__BASE_256B__SHIFT', + 'CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK', + 'CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT', + 'CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK', + 'CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT', + 'CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR5_CMASK__BASE_256B_MASK', + 'CB_COLOR5_CMASK__BASE_256B__SHIFT', + 'CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR5_DCC_BASE__BASE_256B_MASK', + 'CB_COLOR5_DCC_BASE__BASE_256B__SHIFT', + 'CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK', + 'CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT', + 'CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK', + 'CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT', + 'CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK', + 'CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT', + 'CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK', + 'CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT', + 'CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK', + 'CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT', + 'CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK', + 'CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT', + 'CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK', + 'CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT', + 'CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK', + 'CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT', + 'CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR5_FMASK__BASE_256B_MASK', + 'CB_COLOR5_FMASK__BASE_256B__SHIFT', + 'CB_COLOR5_INFO__BLEND_BYPASS_MASK', + 'CB_COLOR5_INFO__BLEND_BYPASS__SHIFT', + 'CB_COLOR5_INFO__BLEND_CLAMP_MASK', + 'CB_COLOR5_INFO__BLEND_CLAMP__SHIFT', + 'CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK', + 'CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT', + 'CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK', + 'CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT', + 'CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK', + 'CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT', + 'CB_COLOR5_INFO__COMPRESSION_MASK', + 'CB_COLOR5_INFO__COMPRESSION__SHIFT', + 'CB_COLOR5_INFO__COMP_SWAP_MASK', + 'CB_COLOR5_INFO__COMP_SWAP__SHIFT', + 'CB_COLOR5_INFO__DCC_ENABLE_MASK', + 'CB_COLOR5_INFO__DCC_ENABLE__SHIFT', + 'CB_COLOR5_INFO__ENDIAN_MASK', 'CB_COLOR5_INFO__ENDIAN__SHIFT', + 'CB_COLOR5_INFO__FAST_CLEAR_MASK', + 'CB_COLOR5_INFO__FAST_CLEAR__SHIFT', + 'CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK', + 'CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT', + 'CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK', + 'CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT', + 'CB_COLOR5_INFO__FORMAT_MASK', 'CB_COLOR5_INFO__FORMAT__SHIFT', + 'CB_COLOR5_INFO__NUMBER_TYPE_MASK', + 'CB_COLOR5_INFO__NUMBER_TYPE__SHIFT', + 'CB_COLOR5_INFO__ROUND_MODE_MASK', + 'CB_COLOR5_INFO__ROUND_MODE__SHIFT', + 'CB_COLOR5_INFO__SIMPLE_FLOAT_MASK', + 'CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT', + 'CB_COLOR5_VIEW__MIP_LEVEL_MASK', + 'CB_COLOR5_VIEW__MIP_LEVEL__SHIFT', + 'CB_COLOR5_VIEW__SLICE_MAX_MASK', + 'CB_COLOR5_VIEW__SLICE_MAX__SHIFT', + 'CB_COLOR5_VIEW__SLICE_START_MASK', + 'CB_COLOR5_VIEW__SLICE_START__SHIFT', + 'CB_COLOR6_ATTRIB2__MAX_MIP_MASK', + 'CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT', + 'CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK', + 'CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT', + 'CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK', + 'CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT', + 'CB_COLOR6_ATTRIB__COLOR_SW_MODE_MASK', + 'CB_COLOR6_ATTRIB__COLOR_SW_MODE__SHIFT', + 'CB_COLOR6_ATTRIB__FMASK_SW_MODE_MASK', + 'CB_COLOR6_ATTRIB__FMASK_SW_MODE__SHIFT', + 'CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK', + 'CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT', + 'CB_COLOR6_ATTRIB__META_LINEAR_MASK', + 'CB_COLOR6_ATTRIB__META_LINEAR__SHIFT', + 'CB_COLOR6_ATTRIB__MIP0_DEPTH_MASK', + 'CB_COLOR6_ATTRIB__MIP0_DEPTH__SHIFT', + 'CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK', + 'CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT', + 'CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK', + 'CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT', + 'CB_COLOR6_ATTRIB__PIPE_ALIGNED_MASK', + 'CB_COLOR6_ATTRIB__PIPE_ALIGNED__SHIFT', + 'CB_COLOR6_ATTRIB__RB_ALIGNED_MASK', + 'CB_COLOR6_ATTRIB__RB_ALIGNED__SHIFT', + 'CB_COLOR6_ATTRIB__RESOURCE_TYPE_MASK', + 'CB_COLOR6_ATTRIB__RESOURCE_TYPE__SHIFT', + 'CB_COLOR6_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR6_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR6_BASE__BASE_256B_MASK', + 'CB_COLOR6_BASE__BASE_256B__SHIFT', + 'CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK', + 'CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT', + 'CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK', + 'CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT', + 'CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR6_CMASK__BASE_256B_MASK', + 'CB_COLOR6_CMASK__BASE_256B__SHIFT', + 'CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR6_DCC_BASE__BASE_256B_MASK', + 'CB_COLOR6_DCC_BASE__BASE_256B__SHIFT', + 'CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK', + 'CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT', + 'CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK', + 'CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT', + 'CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK', + 'CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT', + 'CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK', + 'CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT', + 'CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK', + 'CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT', + 'CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK', + 'CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT', + 'CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK', + 'CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT', + 'CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK', + 'CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT', + 'CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR6_FMASK__BASE_256B_MASK', + 'CB_COLOR6_FMASK__BASE_256B__SHIFT', + 'CB_COLOR6_INFO__BLEND_BYPASS_MASK', + 'CB_COLOR6_INFO__BLEND_BYPASS__SHIFT', + 'CB_COLOR6_INFO__BLEND_CLAMP_MASK', + 'CB_COLOR6_INFO__BLEND_CLAMP__SHIFT', + 'CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK', + 'CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT', + 'CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK', + 'CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT', + 'CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK', + 'CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT', + 'CB_COLOR6_INFO__COMPRESSION_MASK', + 'CB_COLOR6_INFO__COMPRESSION__SHIFT', + 'CB_COLOR6_INFO__COMP_SWAP_MASK', + 'CB_COLOR6_INFO__COMP_SWAP__SHIFT', + 'CB_COLOR6_INFO__DCC_ENABLE_MASK', + 'CB_COLOR6_INFO__DCC_ENABLE__SHIFT', + 'CB_COLOR6_INFO__ENDIAN_MASK', 'CB_COLOR6_INFO__ENDIAN__SHIFT', + 'CB_COLOR6_INFO__FAST_CLEAR_MASK', + 'CB_COLOR6_INFO__FAST_CLEAR__SHIFT', + 'CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK', + 'CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT', + 'CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK', + 'CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT', + 'CB_COLOR6_INFO__FORMAT_MASK', 'CB_COLOR6_INFO__FORMAT__SHIFT', + 'CB_COLOR6_INFO__NUMBER_TYPE_MASK', + 'CB_COLOR6_INFO__NUMBER_TYPE__SHIFT', + 'CB_COLOR6_INFO__ROUND_MODE_MASK', + 'CB_COLOR6_INFO__ROUND_MODE__SHIFT', + 'CB_COLOR6_INFO__SIMPLE_FLOAT_MASK', + 'CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT', + 'CB_COLOR6_VIEW__MIP_LEVEL_MASK', + 'CB_COLOR6_VIEW__MIP_LEVEL__SHIFT', + 'CB_COLOR6_VIEW__SLICE_MAX_MASK', + 'CB_COLOR6_VIEW__SLICE_MAX__SHIFT', + 'CB_COLOR6_VIEW__SLICE_START_MASK', + 'CB_COLOR6_VIEW__SLICE_START__SHIFT', + 'CB_COLOR7_ATTRIB2__MAX_MIP_MASK', + 'CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT', + 'CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK', + 'CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT', + 'CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK', + 'CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT', + 'CB_COLOR7_ATTRIB__COLOR_SW_MODE_MASK', + 'CB_COLOR7_ATTRIB__COLOR_SW_MODE__SHIFT', + 'CB_COLOR7_ATTRIB__FMASK_SW_MODE_MASK', + 'CB_COLOR7_ATTRIB__FMASK_SW_MODE__SHIFT', + 'CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK', + 'CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT', + 'CB_COLOR7_ATTRIB__META_LINEAR_MASK', + 'CB_COLOR7_ATTRIB__META_LINEAR__SHIFT', + 'CB_COLOR7_ATTRIB__MIP0_DEPTH_MASK', + 'CB_COLOR7_ATTRIB__MIP0_DEPTH__SHIFT', + 'CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK', + 'CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT', + 'CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK', + 'CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT', + 'CB_COLOR7_ATTRIB__PIPE_ALIGNED_MASK', + 'CB_COLOR7_ATTRIB__PIPE_ALIGNED__SHIFT', + 'CB_COLOR7_ATTRIB__RB_ALIGNED_MASK', + 'CB_COLOR7_ATTRIB__RB_ALIGNED__SHIFT', + 'CB_COLOR7_ATTRIB__RESOURCE_TYPE_MASK', + 'CB_COLOR7_ATTRIB__RESOURCE_TYPE__SHIFT', + 'CB_COLOR7_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR7_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR7_BASE__BASE_256B_MASK', + 'CB_COLOR7_BASE__BASE_256B__SHIFT', + 'CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK', + 'CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT', + 'CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK', + 'CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT', + 'CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR7_CMASK__BASE_256B_MASK', + 'CB_COLOR7_CMASK__BASE_256B__SHIFT', + 'CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR7_DCC_BASE__BASE_256B_MASK', + 'CB_COLOR7_DCC_BASE__BASE_256B__SHIFT', + 'CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK', + 'CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT', + 'CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK', + 'CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT', + 'CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK', + 'CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT', + 'CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK', + 'CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT', + 'CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK', + 'CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT', + 'CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK', + 'CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT', + 'CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK', + 'CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT', + 'CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK', + 'CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT', + 'CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK', + 'CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT', + 'CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK', + 'CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT', + 'CB_COLOR7_FMASK__BASE_256B_MASK', + 'CB_COLOR7_FMASK__BASE_256B__SHIFT', + 'CB_COLOR7_INFO__BLEND_BYPASS_MASK', + 'CB_COLOR7_INFO__BLEND_BYPASS__SHIFT', + 'CB_COLOR7_INFO__BLEND_CLAMP_MASK', + 'CB_COLOR7_INFO__BLEND_CLAMP__SHIFT', + 'CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK', + 'CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT', + 'CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK', + 'CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT', + 'CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK', + 'CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT', + 'CB_COLOR7_INFO__COMPRESSION_MASK', + 'CB_COLOR7_INFO__COMPRESSION__SHIFT', + 'CB_COLOR7_INFO__COMP_SWAP_MASK', + 'CB_COLOR7_INFO__COMP_SWAP__SHIFT', + 'CB_COLOR7_INFO__DCC_ENABLE_MASK', + 'CB_COLOR7_INFO__DCC_ENABLE__SHIFT', + 'CB_COLOR7_INFO__ENDIAN_MASK', 'CB_COLOR7_INFO__ENDIAN__SHIFT', + 'CB_COLOR7_INFO__FAST_CLEAR_MASK', + 'CB_COLOR7_INFO__FAST_CLEAR__SHIFT', + 'CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK', + 'CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT', + 'CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK', + 'CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT', + 'CB_COLOR7_INFO__FORMAT_MASK', 'CB_COLOR7_INFO__FORMAT__SHIFT', + 'CB_COLOR7_INFO__NUMBER_TYPE_MASK', + 'CB_COLOR7_INFO__NUMBER_TYPE__SHIFT', + 'CB_COLOR7_INFO__ROUND_MODE_MASK', + 'CB_COLOR7_INFO__ROUND_MODE__SHIFT', + 'CB_COLOR7_INFO__SIMPLE_FLOAT_MASK', + 'CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT', + 'CB_COLOR7_VIEW__MIP_LEVEL_MASK', + 'CB_COLOR7_VIEW__MIP_LEVEL__SHIFT', + 'CB_COLOR7_VIEW__SLICE_MAX_MASK', + 'CB_COLOR7_VIEW__SLICE_MAX__SHIFT', + 'CB_COLOR7_VIEW__SLICE_START_MASK', + 'CB_COLOR7_VIEW__SLICE_START__SHIFT', + 'CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK', + 'CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT', + 'CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK', + 'CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT', + 'CB_COLOR_CONTROL__MODE_MASK', 'CB_COLOR_CONTROL__MODE__SHIFT', + 'CB_COLOR_CONTROL__ROP3_MASK', 'CB_COLOR_CONTROL__ROP3__SHIFT', + 'CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK', + 'CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT', + 'CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK', + 'CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT', + 'CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE_MASK', + 'CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE__SHIFT', + 'CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK', + 'CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT', + 'CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK', + 'CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT', + 'CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK', + 'CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT', + 'CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK', + 'CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT', + 'CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK', + 'CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT', + 'CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01_MASK', + 'CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01__SHIFT', + 'CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK', + 'CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT', + 'CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE_MASK', + 'CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE__SHIFT', + 'CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01_MASK', + 'CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01__SHIFT', + 'CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE_MASK', + 'CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE__SHIFT', + 'CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG_MASK', + 'CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG__SHIFT', + 'CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK', + 'CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT', + 'CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK', + 'CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT', + 'CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK', + 'CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT', + 'CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK', + 'CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT', + 'CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK', + 'CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT', + 'CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK', + 'CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT', + 'CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK', + 'CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT', + 'CB_HW_CONTROL_1__RMI_CREDITS_MASK', + 'CB_HW_CONTROL_1__RMI_CREDITS__SHIFT', + 'CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK', + 'CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT', + 'CB_HW_CONTROL_2__CHICKEN_BITS_MASK', + 'CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT', + 'CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK', + 'CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT', + 'CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK', + 'CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT', + 'CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK', + 'CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT', + 'CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS_MASK', + 'CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK', + 'CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK', + 'CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK', + 'CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK', + 'CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK', + 'CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK', + 'CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK', + 'CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK', + 'CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK', + 'CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK', + 'CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK', + 'CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK', + 'CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK', + 'CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK', + 'CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK', + 'CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK', + 'CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK', + 'CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK', + 'CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK', + 'CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK', + 'CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK', + 'CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK', + 'CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK', + 'CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT', + 'CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK', + 'CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT', + 'CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK', + 'CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT', + 'CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK', + 'CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT', + 'CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK', + 'CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT', + 'CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK', + 'CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT', + 'CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK', + 'CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT', + 'CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK', + 'CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT', + 'CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK', + 'CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT', + 'CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK', + 'CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT', + 'CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK', + 'CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT', + 'CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK', + 'CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT', + 'CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK', + 'CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT', + 'CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK', + 'CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT', + 'CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK', + 'CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT', + 'CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK', + 'CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT', + 'CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK', + 'CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT', + 'CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK', + 'CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT', + 'CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK', + 'CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT', + 'CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK', + 'CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT', + 'CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK', + 'CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT', + 'CB_HW_CONTROL__FORCE_NEEDS_DST_MASK', + 'CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT', + 'CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK', + 'CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT', + 'CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK', + 'CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT', + 'CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK', + 'CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT', + 'CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK', + 'CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT', + 'CB_HW_MEM_ARBITER_RD__MODE_MASK', + 'CB_HW_MEM_ARBITER_RD__MODE__SHIFT', + 'CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK', + 'CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT', + 'CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK', + 'CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT', + 'CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK', + 'CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK', + 'CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT', + 'CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK', + 'CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT', + 'CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK', + 'CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT', + 'CB_HW_MEM_ARBITER_WR__MODE_MASK', + 'CB_HW_MEM_ARBITER_WR__MODE__SHIFT', + 'CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK', + 'CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT', + 'CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK', + 'CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT', + 'CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK', + 'CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK', + 'CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT', + 'CB_MRT0_EPITCH__EPITCH_MASK', 'CB_MRT0_EPITCH__EPITCH__SHIFT', + 'CB_MRT1_EPITCH__EPITCH_MASK', 'CB_MRT1_EPITCH__EPITCH__SHIFT', + 'CB_MRT2_EPITCH__EPITCH_MASK', 'CB_MRT2_EPITCH__EPITCH__SHIFT', + 'CB_MRT3_EPITCH__EPITCH_MASK', 'CB_MRT3_EPITCH__EPITCH__SHIFT', + 'CB_MRT4_EPITCH__EPITCH_MASK', 'CB_MRT4_EPITCH__EPITCH__SHIFT', + 'CB_MRT5_EPITCH__EPITCH_MASK', 'CB_MRT5_EPITCH__EPITCH__SHIFT', + 'CB_MRT6_EPITCH__EPITCH_MASK', 'CB_MRT6_EPITCH__EPITCH__SHIFT', + 'CB_MRT7_EPITCH__EPITCH_MASK', 'CB_MRT7_EPITCH__EPITCH__SHIFT', + 'CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK', + 'CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT', + 'CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK', + 'CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT', + 'CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK', + 'CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT', + 'CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK', + 'CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT', + 'CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK', + 'CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT', + 'CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK', + 'CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT', + 'CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK', + 'CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT', + 'CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK', + 'CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT', + 'CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK', + 'CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT', + 'CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK', + 'CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT', + 'CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK', + 'CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT', + 'CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK', + 'CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT', + 'CB_SHADER_MASK__OUTPUT0_ENABLE_MASK', + 'CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT', + 'CB_SHADER_MASK__OUTPUT1_ENABLE_MASK', + 'CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT', + 'CB_SHADER_MASK__OUTPUT2_ENABLE_MASK', + 'CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT', + 'CB_SHADER_MASK__OUTPUT3_ENABLE_MASK', + 'CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT', + 'CB_SHADER_MASK__OUTPUT4_ENABLE_MASK', + 'CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT', + 'CB_SHADER_MASK__OUTPUT5_ENABLE_MASK', + 'CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT', + 'CB_SHADER_MASK__OUTPUT6_ENABLE_MASK', + 'CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT', + 'CB_SHADER_MASK__OUTPUT7_ENABLE_MASK', + 'CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT', + 'CB_TARGET_MASK__TARGET0_ENABLE_MASK', + 'CB_TARGET_MASK__TARGET0_ENABLE__SHIFT', + 'CB_TARGET_MASK__TARGET1_ENABLE_MASK', + 'CB_TARGET_MASK__TARGET1_ENABLE__SHIFT', + 'CB_TARGET_MASK__TARGET2_ENABLE_MASK', + 'CB_TARGET_MASK__TARGET2_ENABLE__SHIFT', + 'CB_TARGET_MASK__TARGET3_ENABLE_MASK', + 'CB_TARGET_MASK__TARGET3_ENABLE__SHIFT', + 'CB_TARGET_MASK__TARGET4_ENABLE_MASK', + 'CB_TARGET_MASK__TARGET4_ENABLE__SHIFT', + 'CB_TARGET_MASK__TARGET5_ENABLE_MASK', + 'CB_TARGET_MASK__TARGET5_ENABLE__SHIFT', + 'CB_TARGET_MASK__TARGET6_ENABLE_MASK', + 'CB_TARGET_MASK__TARGET6_ENABLE__SHIFT', + 'CB_TARGET_MASK__TARGET7_ENABLE_MASK', + 'CB_TARGET_MASK__TARGET7_ENABLE__SHIFT', + 'CC_GC_EDC_CONFIG__DIS_EDC_MASK', + 'CC_GC_EDC_CONFIG__DIS_EDC__SHIFT', + 'CC_GC_EDC_CONFIG__ENABLE_IRRITATOR_CLK_MASK', + 'CC_GC_EDC_CONFIG__ENABLE_IRRITATOR_CLK__SHIFT', + 'CC_GC_EDC_CONFIG__WRITE_DIS_MASK', + 'CC_GC_EDC_CONFIG__WRITE_DIS__SHIFT', + 'CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK', + 'CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT', + 'CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK', + 'CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT', + 'CC_GC_PRIM_CONFIG__WRITE_DIS_MASK', + 'CC_GC_PRIM_CONFIG__WRITE_DIS__SHIFT', + 'CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK', + 'CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT', + 'CC_GC_SHADER_ARRAY_CONFIG__WRITE_DIS_MASK', + 'CC_GC_SHADER_ARRAY_CONFIG__WRITE_DIS__SHIFT', + 'CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK', + 'CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT', + 'CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK', + 'CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT', + 'CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK', + 'CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT', + 'CC_GC_SHADER_RATE_CONFIG__WRITE_DIS_MASK', + 'CC_GC_SHADER_RATE_CONFIG__WRITE_DIS__SHIFT', + 'CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK', + 'CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT', + 'CC_RB_BACKEND_DISABLE__WRITE_DIS_MASK', + 'CC_RB_BACKEND_DISABLE__WRITE_DIS__SHIFT', + 'CC_RB_DAISY_CHAIN__RB_0_MASK', 'CC_RB_DAISY_CHAIN__RB_0__SHIFT', + 'CC_RB_DAISY_CHAIN__RB_1_MASK', 'CC_RB_DAISY_CHAIN__RB_1__SHIFT', + 'CC_RB_DAISY_CHAIN__RB_2_MASK', 'CC_RB_DAISY_CHAIN__RB_2__SHIFT', + 'CC_RB_DAISY_CHAIN__RB_3_MASK', 'CC_RB_DAISY_CHAIN__RB_3__SHIFT', + 'CC_RB_DAISY_CHAIN__RB_4_MASK', 'CC_RB_DAISY_CHAIN__RB_4__SHIFT', + 'CC_RB_DAISY_CHAIN__RB_5_MASK', 'CC_RB_DAISY_CHAIN__RB_5__SHIFT', + 'CC_RB_DAISY_CHAIN__RB_6_MASK', 'CC_RB_DAISY_CHAIN__RB_6__SHIFT', + 'CC_RB_DAISY_CHAIN__RB_7_MASK', 'CC_RB_DAISY_CHAIN__RB_7__SHIFT', + 'CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK', + 'CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT', + 'CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK', + 'CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT', + 'CC_RB_REDUNDANCY__FAILED_RB0_MASK', + 'CC_RB_REDUNDANCY__FAILED_RB0__SHIFT', + 'CC_RB_REDUNDANCY__FAILED_RB1_MASK', + 'CC_RB_REDUNDANCY__FAILED_RB1__SHIFT', + 'CC_RB_REDUNDANCY__WRITE_DIS_MASK', + 'CC_RB_REDUNDANCY__WRITE_DIS__SHIFT', + 'CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK', + 'CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK', + 'CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT', + 'CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK', + 'CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK', + 'CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT', + 'CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT', + 'CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK', + 'CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK', + 'CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT', + 'CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK', + 'CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK', + 'CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT', + 'CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT', + 'CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK', + 'CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK', + 'CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT', + 'CGTS_CU0_SP0_CTRL_REG__SP00_MASK', + 'CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK', + 'CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT', + 'CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT', + 'CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK', + 'CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK', + 'CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT', + 'CGTS_CU0_SP0_CTRL_REG__SP01_MASK', + 'CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK', + 'CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT', + 'CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT', + 'CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK', + 'CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK', + 'CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT', + 'CGTS_CU0_SP1_CTRL_REG__SP10_MASK', + 'CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK', + 'CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT', + 'CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT', + 'CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK', + 'CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK', + 'CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT', + 'CGTS_CU0_SP1_CTRL_REG__SP11_MASK', + 'CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK', + 'CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT', + 'CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT', + 'CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK', + 'CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK', + 'CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT', + 'CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK', + 'CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK', + 'CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT', + 'CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT', + 'CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK', + 'CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK', + 'CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT', + 'CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK', + 'CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK', + 'CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT', + 'CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT', + 'CGTS_CU0_TCPI_CTRL_REG__RESERVED_MASK', + 'CGTS_CU0_TCPI_CTRL_REG__RESERVED__SHIFT', + 'CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK', + 'CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK', + 'CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT', + 'CGTS_CU0_TCPI_CTRL_REG__TCPI_MASK', + 'CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK', + 'CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT', + 'CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_TCPI_CTRL_REG__TCPI__SHIFT', + 'CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK', + 'CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK', + 'CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT', + 'CGTS_CU0_TD_TCP_CTRL_REG__TCPF_MASK', + 'CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK', + 'CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT', + 'CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_TD_TCP_CTRL_REG__TCPF__SHIFT', + 'CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK', + 'CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK', + 'CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT', + 'CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK', + 'CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK', + 'CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT', + 'CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT', + 'CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK', + 'CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK', + 'CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT', + 'CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK', + 'CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK', + 'CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT', + 'CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT', + 'CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK', + 'CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK', + 'CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT', + 'CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK', + 'CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK', + 'CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT', + 'CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT', + 'CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK', + 'CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK', + 'CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT', + 'CGTS_CU10_SP0_CTRL_REG__SP00_MASK', + 'CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK', + 'CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT', + 'CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT', + 'CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK', + 'CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK', + 'CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT', + 'CGTS_CU10_SP0_CTRL_REG__SP01_MASK', + 'CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK', + 'CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT', + 'CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT', + 'CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK', + 'CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK', + 'CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT', + 'CGTS_CU10_SP1_CTRL_REG__SP10_MASK', + 'CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK', + 'CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT', + 'CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT', + 'CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK', + 'CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK', + 'CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT', + 'CGTS_CU10_SP1_CTRL_REG__SP11_MASK', + 'CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK', + 'CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT', + 'CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT', + 'CGTS_CU10_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK', + 'CGTS_CU10_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK', + 'CGTS_CU10_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT', + 'CGTS_CU10_TA_SQC_CTRL_REG__SQC_MASK', + 'CGTS_CU10_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK', + 'CGTS_CU10_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT', + 'CGTS_CU10_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU10_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_TA_SQC_CTRL_REG__SQC__SHIFT', + 'CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK', + 'CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK', + 'CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT', + 'CGTS_CU10_TA_SQC_CTRL_REG__TA_MASK', + 'CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK', + 'CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT', + 'CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_TA_SQC_CTRL_REG__TA__SHIFT', + 'CGTS_CU10_TCPI_CTRL_REG__RESERVED_MASK', + 'CGTS_CU10_TCPI_CTRL_REG__RESERVED__SHIFT', + 'CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK', + 'CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK', + 'CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT', + 'CGTS_CU10_TCPI_CTRL_REG__TCPI_MASK', + 'CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK', + 'CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT', + 'CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_TCPI_CTRL_REG__TCPI__SHIFT', + 'CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK', + 'CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK', + 'CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT', + 'CGTS_CU10_TD_TCP_CTRL_REG__TCPF_MASK', + 'CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK', + 'CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT', + 'CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_TD_TCP_CTRL_REG__TCPF__SHIFT', + 'CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK', + 'CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK', + 'CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT', + 'CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK', + 'CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK', + 'CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT', + 'CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT', + 'CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK', + 'CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK', + 'CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT', + 'CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK', + 'CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK', + 'CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT', + 'CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT', + 'CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK', + 'CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK', + 'CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT', + 'CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK', + 'CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK', + 'CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT', + 'CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT', + 'CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK', + 'CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK', + 'CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT', + 'CGTS_CU11_SP0_CTRL_REG__SP00_MASK', + 'CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK', + 'CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT', + 'CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT', + 'CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK', + 'CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK', + 'CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT', + 'CGTS_CU11_SP0_CTRL_REG__SP01_MASK', + 'CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK', + 'CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT', + 'CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT', + 'CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK', + 'CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK', + 'CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT', + 'CGTS_CU11_SP1_CTRL_REG__SP10_MASK', + 'CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK', + 'CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT', + 'CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT', + 'CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK', + 'CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK', + 'CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT', + 'CGTS_CU11_SP1_CTRL_REG__SP11_MASK', + 'CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK', + 'CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT', + 'CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT', + 'CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK', + 'CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK', + 'CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT', + 'CGTS_CU11_TA_SQC_CTRL_REG__TA_MASK', + 'CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK', + 'CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT', + 'CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU11_TA_SQC_CTRL_REG__TA__SHIFT', + 'CGTS_CU11_TCPI_CTRL_REG__RESERVED_MASK', + 'CGTS_CU11_TCPI_CTRL_REG__RESERVED__SHIFT', + 'CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK', + 'CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK', + 'CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT', + 'CGTS_CU11_TCPI_CTRL_REG__TCPI_MASK', + 'CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK', + 'CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT', + 'CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU11_TCPI_CTRL_REG__TCPI__SHIFT', + 'CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK', + 'CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK', + 'CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT', + 'CGTS_CU11_TD_TCP_CTRL_REG__TCPF_MASK', + 'CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK', + 'CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT', + 'CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU11_TD_TCP_CTRL_REG__TCPF__SHIFT', + 'CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK', + 'CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK', + 'CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT', + 'CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK', + 'CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK', + 'CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT', + 'CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT', + 'CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK', + 'CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK', + 'CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT', + 'CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK', + 'CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK', + 'CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT', + 'CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT', + 'CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK', + 'CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK', + 'CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT', + 'CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK', + 'CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK', + 'CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT', + 'CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT', + 'CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK', + 'CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK', + 'CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT', + 'CGTS_CU12_SP0_CTRL_REG__SP00_MASK', + 'CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK', + 'CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT', + 'CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT', + 'CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK', + 'CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK', + 'CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT', + 'CGTS_CU12_SP0_CTRL_REG__SP01_MASK', + 'CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK', + 'CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT', + 'CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT', + 'CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK', + 'CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK', + 'CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT', + 'CGTS_CU12_SP1_CTRL_REG__SP10_MASK', + 'CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK', + 'CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT', + 'CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT', + 'CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK', + 'CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK', + 'CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT', + 'CGTS_CU12_SP1_CTRL_REG__SP11_MASK', + 'CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK', + 'CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT', + 'CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT', + 'CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK', + 'CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK', + 'CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT', + 'CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK', + 'CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK', + 'CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT', + 'CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT', + 'CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK', + 'CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK', + 'CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT', + 'CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK', + 'CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK', + 'CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT', + 'CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT', + 'CGTS_CU12_TCPI_CTRL_REG__RESERVED_MASK', + 'CGTS_CU12_TCPI_CTRL_REG__RESERVED__SHIFT', + 'CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK', + 'CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK', + 'CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT', + 'CGTS_CU12_TCPI_CTRL_REG__TCPI_MASK', + 'CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK', + 'CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT', + 'CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_TCPI_CTRL_REG__TCPI__SHIFT', + 'CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK', + 'CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK', + 'CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT', + 'CGTS_CU12_TD_TCP_CTRL_REG__TCPF_MASK', + 'CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK', + 'CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT', + 'CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_TD_TCP_CTRL_REG__TCPF__SHIFT', + 'CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK', + 'CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK', + 'CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT', + 'CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK', + 'CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK', + 'CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT', + 'CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT', + 'CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK', + 'CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK', + 'CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT', + 'CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK', + 'CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK', + 'CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT', + 'CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT', + 'CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK', + 'CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK', + 'CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT', + 'CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK', + 'CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK', + 'CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT', + 'CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT', + 'CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK', + 'CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK', + 'CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT', + 'CGTS_CU13_SP0_CTRL_REG__SP00_MASK', + 'CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK', + 'CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT', + 'CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT', + 'CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK', + 'CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK', + 'CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT', + 'CGTS_CU13_SP0_CTRL_REG__SP01_MASK', + 'CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK', + 'CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT', + 'CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT', + 'CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK', + 'CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK', + 'CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT', + 'CGTS_CU13_SP1_CTRL_REG__SP10_MASK', + 'CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK', + 'CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT', + 'CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT', + 'CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK', + 'CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK', + 'CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT', + 'CGTS_CU13_SP1_CTRL_REG__SP11_MASK', + 'CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK', + 'CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT', + 'CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT', + 'CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK', + 'CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK', + 'CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT', + 'CGTS_CU13_TA_SQC_CTRL_REG__TA_MASK', + 'CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK', + 'CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT', + 'CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU13_TA_SQC_CTRL_REG__TA__SHIFT', + 'CGTS_CU13_TCPI_CTRL_REG__RESERVED_MASK', + 'CGTS_CU13_TCPI_CTRL_REG__RESERVED__SHIFT', + 'CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK', + 'CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK', + 'CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT', + 'CGTS_CU13_TCPI_CTRL_REG__TCPI_MASK', + 'CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK', + 'CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT', + 'CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU13_TCPI_CTRL_REG__TCPI__SHIFT', + 'CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK', + 'CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK', + 'CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT', + 'CGTS_CU13_TD_TCP_CTRL_REG__TCPF_MASK', + 'CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK', + 'CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT', + 'CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU13_TD_TCP_CTRL_REG__TCPF__SHIFT', + 'CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK', + 'CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK', + 'CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT', + 'CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK', + 'CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK', + 'CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT', + 'CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT', + 'CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK', + 'CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK', + 'CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT', + 'CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK', + 'CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK', + 'CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT', + 'CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT', + 'CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK', + 'CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK', + 'CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT', + 'CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK', + 'CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK', + 'CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT', + 'CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT', + 'CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK', + 'CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK', + 'CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT', + 'CGTS_CU14_SP0_CTRL_REG__SP00_MASK', + 'CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK', + 'CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT', + 'CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT', + 'CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK', + 'CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK', + 'CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT', + 'CGTS_CU14_SP0_CTRL_REG__SP01_MASK', + 'CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK', + 'CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT', + 'CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT', + 'CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK', + 'CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK', + 'CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT', + 'CGTS_CU14_SP1_CTRL_REG__SP10_MASK', + 'CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK', + 'CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT', + 'CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT', + 'CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK', + 'CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK', + 'CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT', + 'CGTS_CU14_SP1_CTRL_REG__SP11_MASK', + 'CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK', + 'CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT', + 'CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT', + 'CGTS_CU14_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK', + 'CGTS_CU14_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK', + 'CGTS_CU14_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT', + 'CGTS_CU14_TA_SQC_CTRL_REG__SQC_MASK', + 'CGTS_CU14_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK', + 'CGTS_CU14_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT', + 'CGTS_CU14_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU14_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_TA_SQC_CTRL_REG__SQC__SHIFT', + 'CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK', + 'CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK', + 'CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT', + 'CGTS_CU14_TA_SQC_CTRL_REG__TA_MASK', + 'CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK', + 'CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT', + 'CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_TA_SQC_CTRL_REG__TA__SHIFT', + 'CGTS_CU14_TCPI_CTRL_REG__RESERVED_MASK', + 'CGTS_CU14_TCPI_CTRL_REG__RESERVED__SHIFT', + 'CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK', + 'CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK', + 'CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT', + 'CGTS_CU14_TCPI_CTRL_REG__TCPI_MASK', + 'CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK', + 'CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT', + 'CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_TCPI_CTRL_REG__TCPI__SHIFT', + 'CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK', + 'CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK', + 'CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT', + 'CGTS_CU14_TD_TCP_CTRL_REG__TCPF_MASK', + 'CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK', + 'CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT', + 'CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_TD_TCP_CTRL_REG__TCPF__SHIFT', + 'CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK', + 'CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK', + 'CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT', + 'CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK', + 'CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK', + 'CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT', + 'CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT', + 'CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK', + 'CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK', + 'CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT', + 'CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK', + 'CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK', + 'CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT', + 'CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT', + 'CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK', + 'CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK', + 'CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT', + 'CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK', + 'CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK', + 'CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT', + 'CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT', + 'CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK', + 'CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK', + 'CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT', + 'CGTS_CU15_SP0_CTRL_REG__SP00_MASK', + 'CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK', + 'CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT', + 'CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT', + 'CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK', + 'CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK', + 'CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT', + 'CGTS_CU15_SP0_CTRL_REG__SP01_MASK', + 'CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK', + 'CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT', + 'CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT', + 'CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK', + 'CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK', + 'CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT', + 'CGTS_CU15_SP1_CTRL_REG__SP10_MASK', + 'CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK', + 'CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT', + 'CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT', + 'CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK', + 'CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK', + 'CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT', + 'CGTS_CU15_SP1_CTRL_REG__SP11_MASK', + 'CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK', + 'CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT', + 'CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT', + 'CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK', + 'CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK', + 'CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT', + 'CGTS_CU15_TA_SQC_CTRL_REG__TA_MASK', + 'CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK', + 'CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT', + 'CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU15_TA_SQC_CTRL_REG__TA__SHIFT', + 'CGTS_CU15_TCPI_CTRL_REG__RESERVED_MASK', + 'CGTS_CU15_TCPI_CTRL_REG__RESERVED__SHIFT', + 'CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK', + 'CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK', + 'CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT', + 'CGTS_CU15_TCPI_CTRL_REG__TCPI_MASK', + 'CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK', + 'CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT', + 'CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU15_TCPI_CTRL_REG__TCPI__SHIFT', + 'CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK', + 'CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK', + 'CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT', + 'CGTS_CU15_TD_TCP_CTRL_REG__TCPF_MASK', + 'CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK', + 'CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT', + 'CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU15_TD_TCP_CTRL_REG__TCPF__SHIFT', + 'CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK', + 'CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK', + 'CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT', + 'CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK', + 'CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK', + 'CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT', + 'CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT', + 'CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK', + 'CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK', + 'CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT', + 'CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK', + 'CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK', + 'CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT', + 'CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT', + 'CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK', + 'CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK', + 'CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT', + 'CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK', + 'CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK', + 'CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT', + 'CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT', + 'CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK', + 'CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK', + 'CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT', + 'CGTS_CU1_SP0_CTRL_REG__SP00_MASK', + 'CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK', + 'CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT', + 'CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT', + 'CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK', + 'CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK', + 'CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT', + 'CGTS_CU1_SP0_CTRL_REG__SP01_MASK', + 'CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK', + 'CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT', + 'CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT', + 'CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK', + 'CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK', + 'CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT', + 'CGTS_CU1_SP1_CTRL_REG__SP10_MASK', + 'CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK', + 'CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT', + 'CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT', + 'CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK', + 'CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK', + 'CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT', + 'CGTS_CU1_SP1_CTRL_REG__SP11_MASK', + 'CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK', + 'CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT', + 'CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT', + 'CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK', + 'CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK', + 'CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT', + 'CGTS_CU1_TA_SQC_CTRL_REG__TA_MASK', + 'CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK', + 'CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT', + 'CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU1_TA_SQC_CTRL_REG__TA__SHIFT', + 'CGTS_CU1_TCPI_CTRL_REG__RESERVED_MASK', + 'CGTS_CU1_TCPI_CTRL_REG__RESERVED__SHIFT', + 'CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK', + 'CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK', + 'CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT', + 'CGTS_CU1_TCPI_CTRL_REG__TCPI_MASK', + 'CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK', + 'CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT', + 'CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU1_TCPI_CTRL_REG__TCPI__SHIFT', + 'CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK', + 'CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK', + 'CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT', + 'CGTS_CU1_TD_TCP_CTRL_REG__TCPF_MASK', + 'CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK', + 'CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT', + 'CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU1_TD_TCP_CTRL_REG__TCPF__SHIFT', + 'CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK', + 'CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK', + 'CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT', + 'CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK', + 'CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK', + 'CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT', + 'CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT', + 'CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK', + 'CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK', + 'CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT', + 'CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK', + 'CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK', + 'CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT', + 'CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT', + 'CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK', + 'CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK', + 'CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT', + 'CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK', + 'CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK', + 'CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT', + 'CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT', + 'CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK', + 'CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK', + 'CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT', + 'CGTS_CU2_SP0_CTRL_REG__SP00_MASK', + 'CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK', + 'CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT', + 'CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT', + 'CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK', + 'CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK', + 'CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT', + 'CGTS_CU2_SP0_CTRL_REG__SP01_MASK', + 'CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK', + 'CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT', + 'CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT', + 'CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK', + 'CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK', + 'CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT', + 'CGTS_CU2_SP1_CTRL_REG__SP10_MASK', + 'CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK', + 'CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT', + 'CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT', + 'CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK', + 'CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK', + 'CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT', + 'CGTS_CU2_SP1_CTRL_REG__SP11_MASK', + 'CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK', + 'CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT', + 'CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT', + 'CGTS_CU2_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK', + 'CGTS_CU2_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK', + 'CGTS_CU2_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT', + 'CGTS_CU2_TA_SQC_CTRL_REG__SQC_MASK', + 'CGTS_CU2_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK', + 'CGTS_CU2_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT', + 'CGTS_CU2_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU2_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_TA_SQC_CTRL_REG__SQC__SHIFT', + 'CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK', + 'CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK', + 'CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT', + 'CGTS_CU2_TA_SQC_CTRL_REG__TA_MASK', + 'CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK', + 'CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT', + 'CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_TA_SQC_CTRL_REG__TA__SHIFT', + 'CGTS_CU2_TCPI_CTRL_REG__RESERVED_MASK', + 'CGTS_CU2_TCPI_CTRL_REG__RESERVED__SHIFT', + 'CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK', + 'CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK', + 'CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT', + 'CGTS_CU2_TCPI_CTRL_REG__TCPI_MASK', + 'CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK', + 'CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT', + 'CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_TCPI_CTRL_REG__TCPI__SHIFT', + 'CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK', + 'CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK', + 'CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT', + 'CGTS_CU2_TD_TCP_CTRL_REG__TCPF_MASK', + 'CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK', + 'CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT', + 'CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_TD_TCP_CTRL_REG__TCPF__SHIFT', + 'CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK', + 'CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK', + 'CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT', + 'CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK', + 'CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK', + 'CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT', + 'CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT', + 'CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK', + 'CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK', + 'CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT', + 'CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK', + 'CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK', + 'CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT', + 'CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT', + 'CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK', + 'CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK', + 'CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT', + 'CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK', + 'CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK', + 'CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT', + 'CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT', + 'CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK', + 'CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK', + 'CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT', + 'CGTS_CU3_SP0_CTRL_REG__SP00_MASK', + 'CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK', + 'CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT', + 'CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT', + 'CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK', + 'CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK', + 'CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT', + 'CGTS_CU3_SP0_CTRL_REG__SP01_MASK', + 'CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK', + 'CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT', + 'CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT', + 'CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK', + 'CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK', + 'CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT', + 'CGTS_CU3_SP1_CTRL_REG__SP10_MASK', + 'CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK', + 'CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT', + 'CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT', + 'CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK', + 'CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK', + 'CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT', + 'CGTS_CU3_SP1_CTRL_REG__SP11_MASK', + 'CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK', + 'CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT', + 'CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT', + 'CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK', + 'CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK', + 'CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT', + 'CGTS_CU3_TA_SQC_CTRL_REG__TA_MASK', + 'CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK', + 'CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT', + 'CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU3_TA_SQC_CTRL_REG__TA__SHIFT', + 'CGTS_CU3_TCPI_CTRL_REG__RESERVED_MASK', + 'CGTS_CU3_TCPI_CTRL_REG__RESERVED__SHIFT', + 'CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK', + 'CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK', + 'CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT', + 'CGTS_CU3_TCPI_CTRL_REG__TCPI_MASK', + 'CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK', + 'CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT', + 'CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU3_TCPI_CTRL_REG__TCPI__SHIFT', + 'CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK', + 'CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK', + 'CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT', + 'CGTS_CU3_TD_TCP_CTRL_REG__TCPF_MASK', + 'CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK', + 'CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT', + 'CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU3_TD_TCP_CTRL_REG__TCPF__SHIFT', + 'CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK', + 'CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK', + 'CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT', + 'CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK', + 'CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK', + 'CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT', + 'CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT', + 'CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK', + 'CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK', + 'CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT', + 'CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK', + 'CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK', + 'CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT', + 'CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT', + 'CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK', + 'CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK', + 'CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT', + 'CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK', + 'CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK', + 'CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT', + 'CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT', + 'CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK', + 'CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK', + 'CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT', + 'CGTS_CU4_SP0_CTRL_REG__SP00_MASK', + 'CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK', + 'CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT', + 'CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT', + 'CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK', + 'CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK', + 'CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT', + 'CGTS_CU4_SP0_CTRL_REG__SP01_MASK', + 'CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK', + 'CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT', + 'CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT', + 'CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK', + 'CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK', + 'CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT', + 'CGTS_CU4_SP1_CTRL_REG__SP10_MASK', + 'CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK', + 'CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT', + 'CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT', + 'CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK', + 'CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK', + 'CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT', + 'CGTS_CU4_SP1_CTRL_REG__SP11_MASK', + 'CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK', + 'CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT', + 'CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT', + 'CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK', + 'CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK', + 'CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT', + 'CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK', + 'CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK', + 'CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT', + 'CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT', + 'CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK', + 'CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK', + 'CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT', + 'CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK', + 'CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK', + 'CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT', + 'CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT', + 'CGTS_CU4_TCPI_CTRL_REG__RESERVED_MASK', + 'CGTS_CU4_TCPI_CTRL_REG__RESERVED__SHIFT', + 'CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK', + 'CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK', + 'CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT', + 'CGTS_CU4_TCPI_CTRL_REG__TCPI_MASK', + 'CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK', + 'CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT', + 'CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_TCPI_CTRL_REG__TCPI__SHIFT', + 'CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK', + 'CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK', + 'CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT', + 'CGTS_CU4_TD_TCP_CTRL_REG__TCPF_MASK', + 'CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK', + 'CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT', + 'CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_TD_TCP_CTRL_REG__TCPF__SHIFT', + 'CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK', + 'CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK', + 'CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT', + 'CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK', + 'CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK', + 'CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT', + 'CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT', + 'CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK', + 'CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK', + 'CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT', + 'CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK', + 'CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK', + 'CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT', + 'CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT', + 'CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK', + 'CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK', + 'CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT', + 'CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK', + 'CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK', + 'CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT', + 'CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT', + 'CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK', + 'CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK', + 'CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT', + 'CGTS_CU5_SP0_CTRL_REG__SP00_MASK', + 'CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK', + 'CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT', + 'CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT', + 'CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK', + 'CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK', + 'CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT', + 'CGTS_CU5_SP0_CTRL_REG__SP01_MASK', + 'CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK', + 'CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT', + 'CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT', + 'CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK', + 'CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK', + 'CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT', + 'CGTS_CU5_SP1_CTRL_REG__SP10_MASK', + 'CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK', + 'CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT', + 'CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT', + 'CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK', + 'CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK', + 'CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT', + 'CGTS_CU5_SP1_CTRL_REG__SP11_MASK', + 'CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK', + 'CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT', + 'CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT', + 'CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK', + 'CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK', + 'CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT', + 'CGTS_CU5_TA_SQC_CTRL_REG__TA_MASK', + 'CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK', + 'CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT', + 'CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU5_TA_SQC_CTRL_REG__TA__SHIFT', + 'CGTS_CU5_TCPI_CTRL_REG__RESERVED_MASK', + 'CGTS_CU5_TCPI_CTRL_REG__RESERVED__SHIFT', + 'CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK', + 'CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK', + 'CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT', + 'CGTS_CU5_TCPI_CTRL_REG__TCPI_MASK', + 'CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK', + 'CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT', + 'CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU5_TCPI_CTRL_REG__TCPI__SHIFT', + 'CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK', + 'CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK', + 'CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT', + 'CGTS_CU5_TD_TCP_CTRL_REG__TCPF_MASK', + 'CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK', + 'CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT', + 'CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU5_TD_TCP_CTRL_REG__TCPF__SHIFT', + 'CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK', + 'CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK', + 'CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT', + 'CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK', + 'CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK', + 'CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT', + 'CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT', + 'CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK', + 'CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK', + 'CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT', + 'CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK', + 'CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK', + 'CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT', + 'CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT', + 'CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK', + 'CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK', + 'CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT', + 'CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK', + 'CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK', + 'CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT', + 'CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT', + 'CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK', + 'CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK', + 'CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT', + 'CGTS_CU6_SP0_CTRL_REG__SP00_MASK', + 'CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK', + 'CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT', + 'CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT', + 'CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK', + 'CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK', + 'CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT', + 'CGTS_CU6_SP0_CTRL_REG__SP01_MASK', + 'CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK', + 'CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT', + 'CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT', + 'CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK', + 'CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK', + 'CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT', + 'CGTS_CU6_SP1_CTRL_REG__SP10_MASK', + 'CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK', + 'CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT', + 'CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT', + 'CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK', + 'CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK', + 'CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT', + 'CGTS_CU6_SP1_CTRL_REG__SP11_MASK', + 'CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK', + 'CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT', + 'CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT', + 'CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK', + 'CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK', + 'CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT', + 'CGTS_CU6_TA_SQC_CTRL_REG__SQC_MASK', + 'CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK', + 'CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT', + 'CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_TA_SQC_CTRL_REG__SQC__SHIFT', + 'CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK', + 'CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK', + 'CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT', + 'CGTS_CU6_TA_SQC_CTRL_REG__TA_MASK', + 'CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK', + 'CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT', + 'CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_TA_SQC_CTRL_REG__TA__SHIFT', + 'CGTS_CU6_TCPI_CTRL_REG__RESERVED_MASK', + 'CGTS_CU6_TCPI_CTRL_REG__RESERVED__SHIFT', + 'CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK', + 'CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK', + 'CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT', + 'CGTS_CU6_TCPI_CTRL_REG__TCPI_MASK', + 'CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK', + 'CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT', + 'CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_TCPI_CTRL_REG__TCPI__SHIFT', + 'CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK', + 'CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK', + 'CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT', + 'CGTS_CU6_TD_TCP_CTRL_REG__TCPF_MASK', + 'CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK', + 'CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT', + 'CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_TD_TCP_CTRL_REG__TCPF__SHIFT', + 'CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK', + 'CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK', + 'CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT', + 'CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK', + 'CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK', + 'CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT', + 'CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT', + 'CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK', + 'CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK', + 'CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT', + 'CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK', + 'CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK', + 'CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT', + 'CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT', + 'CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK', + 'CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK', + 'CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT', + 'CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK', + 'CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK', + 'CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT', + 'CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT', + 'CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK', + 'CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK', + 'CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT', + 'CGTS_CU7_SP0_CTRL_REG__SP00_MASK', + 'CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK', + 'CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT', + 'CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT', + 'CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK', + 'CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK', + 'CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT', + 'CGTS_CU7_SP0_CTRL_REG__SP01_MASK', + 'CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK', + 'CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT', + 'CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT', + 'CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK', + 'CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK', + 'CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT', + 'CGTS_CU7_SP1_CTRL_REG__SP10_MASK', + 'CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK', + 'CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT', + 'CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT', + 'CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK', + 'CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK', + 'CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT', + 'CGTS_CU7_SP1_CTRL_REG__SP11_MASK', + 'CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK', + 'CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT', + 'CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT', + 'CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK', + 'CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK', + 'CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT', + 'CGTS_CU7_TA_SQC_CTRL_REG__TA_MASK', + 'CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK', + 'CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT', + 'CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU7_TA_SQC_CTRL_REG__TA__SHIFT', + 'CGTS_CU7_TCPI_CTRL_REG__RESERVED_MASK', + 'CGTS_CU7_TCPI_CTRL_REG__RESERVED__SHIFT', + 'CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK', + 'CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK', + 'CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT', + 'CGTS_CU7_TCPI_CTRL_REG__TCPI_MASK', + 'CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK', + 'CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT', + 'CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU7_TCPI_CTRL_REG__TCPI__SHIFT', + 'CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK', + 'CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK', + 'CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT', + 'CGTS_CU7_TD_TCP_CTRL_REG__TCPF_MASK', + 'CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK', + 'CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT', + 'CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU7_TD_TCP_CTRL_REG__TCPF__SHIFT', + 'CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK', + 'CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK', + 'CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT', + 'CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK', + 'CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK', + 'CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT', + 'CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT', + 'CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK', + 'CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK', + 'CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT', + 'CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK', + 'CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK', + 'CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT', + 'CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT', + 'CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK', + 'CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK', + 'CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT', + 'CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK', + 'CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK', + 'CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT', + 'CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT', + 'CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK', + 'CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK', + 'CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT', + 'CGTS_CU8_SP0_CTRL_REG__SP00_MASK', + 'CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK', + 'CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT', + 'CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT', + 'CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK', + 'CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK', + 'CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT', + 'CGTS_CU8_SP0_CTRL_REG__SP01_MASK', + 'CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK', + 'CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT', + 'CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT', + 'CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK', + 'CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK', + 'CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT', + 'CGTS_CU8_SP1_CTRL_REG__SP10_MASK', + 'CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK', + 'CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT', + 'CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT', + 'CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK', + 'CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK', + 'CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT', + 'CGTS_CU8_SP1_CTRL_REG__SP11_MASK', + 'CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK', + 'CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT', + 'CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT', + 'CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK', + 'CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK', + 'CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT', + 'CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK', + 'CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK', + 'CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT', + 'CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT', + 'CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK', + 'CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK', + 'CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT', + 'CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK', + 'CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK', + 'CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT', + 'CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT', + 'CGTS_CU8_TCPI_CTRL_REG__RESERVED_MASK', + 'CGTS_CU8_TCPI_CTRL_REG__RESERVED__SHIFT', + 'CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK', + 'CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK', + 'CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT', + 'CGTS_CU8_TCPI_CTRL_REG__TCPI_MASK', + 'CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK', + 'CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT', + 'CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_TCPI_CTRL_REG__TCPI__SHIFT', + 'CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK', + 'CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK', + 'CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT', + 'CGTS_CU8_TD_TCP_CTRL_REG__TCPF_MASK', + 'CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK', + 'CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT', + 'CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_TD_TCP_CTRL_REG__TCPF__SHIFT', + 'CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK', + 'CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK', + 'CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT', + 'CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK', + 'CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK', + 'CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT', + 'CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT', + 'CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK', + 'CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK', + 'CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT', + 'CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK', + 'CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK', + 'CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT', + 'CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT', + 'CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK', + 'CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK', + 'CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT', + 'CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK', + 'CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK', + 'CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT', + 'CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT', + 'CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK', + 'CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK', + 'CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT', + 'CGTS_CU9_SP0_CTRL_REG__SP00_MASK', + 'CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK', + 'CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT', + 'CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT', + 'CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK', + 'CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK', + 'CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT', + 'CGTS_CU9_SP0_CTRL_REG__SP01_MASK', + 'CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK', + 'CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT', + 'CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT', + 'CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK', + 'CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK', + 'CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT', + 'CGTS_CU9_SP1_CTRL_REG__SP10_MASK', + 'CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK', + 'CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT', + 'CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT', + 'CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK', + 'CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK', + 'CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT', + 'CGTS_CU9_SP1_CTRL_REG__SP11_MASK', + 'CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK', + 'CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT', + 'CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT', + 'CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK', + 'CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK', + 'CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT', + 'CGTS_CU9_TA_SQC_CTRL_REG__TA_MASK', + 'CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK', + 'CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT', + 'CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU9_TA_SQC_CTRL_REG__TA__SHIFT', + 'CGTS_CU9_TCPI_CTRL_REG__RESERVED_MASK', + 'CGTS_CU9_TCPI_CTRL_REG__RESERVED__SHIFT', + 'CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK', + 'CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK', + 'CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT', + 'CGTS_CU9_TCPI_CTRL_REG__TCPI_MASK', + 'CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK', + 'CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT', + 'CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU9_TCPI_CTRL_REG__TCPI__SHIFT', + 'CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK', + 'CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK', + 'CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT', + 'CGTS_CU9_TD_TCP_CTRL_REG__TCPF_MASK', + 'CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK', + 'CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT', + 'CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU9_TD_TCP_CTRL_REG__TCPF__SHIFT', + 'CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK', + 'CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT', + 'CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK', + 'CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT', + 'CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK', + 'CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK', + 'CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT', + 'CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK', + 'CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT', + 'CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT', + 'CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK', + 'CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT', + 'CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK', + 'CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT', + 'CGTS_RD_REG__READ_DATA_MASK', 'CGTS_RD_REG__READ_DATA__SHIFT', + 'CGTS_SM_CTRL_REG__BASE_MODE_MASK', + 'CGTS_SM_CTRL_REG__BASE_MODE__SHIFT', + 'CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK', + 'CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT', + 'CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK', + 'CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT', + 'CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK', + 'CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT', + 'CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK', + 'CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT', + 'CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK', + 'CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT', + 'CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK', + 'CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT', + 'CGTS_SM_CTRL_REG__OVERRIDE_MASK', + 'CGTS_SM_CTRL_REG__OVERRIDE__SHIFT', + 'CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK', + 'CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT', + 'CGTS_SM_CTRL_REG__SM_MODE_MASK', + 'CGTS_SM_CTRL_REG__SM_MODE__SHIFT', + 'CGTS_TCC_DISABLE__TCC_DISABLE_MASK', + 'CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT', + 'CGTS_TCC_DISABLE__WRITE_DIS_MASK', + 'CGTS_TCC_DISABLE__WRITE_DIS__SHIFT', + 'CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK', + 'CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT', + 'CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK', + 'CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT', + 'CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK', + 'CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT', + 'CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK', + 'CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT', + 'CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK', + 'CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT', + 'CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK', + 'CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT', + 'CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK', + 'CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT', + 'CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK', + 'CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT', + 'CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CGTT_BCI_CLK_CTRL__ON_DELAY_MASK', + 'CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT', + 'CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK', + 'CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT', + 'CGTT_BCI_CLK_CTRL__RESERVED_MASK', + 'CGTT_BCI_CLK_CTRL__RESERVED__SHIFT', + 'CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK', + 'CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT', + 'CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK', + 'CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT', + 'CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CGTT_CPC_CLK_CTRL__REG_CLK_OFF_HYSTERESIS_MASK', + 'CGTT_CPC_CLK_CTRL__REG_CLK_OFF_HYSTERESIS__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK', + 'CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT', + 'CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK', + 'CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT', + 'CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK', + 'CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT', + 'CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK', + 'CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT', + 'CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK', + 'CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT', + 'CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CGTT_IA_CLK_CTRL__ON_DELAY_MASK', + 'CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT', + 'CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK', + 'CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT', + 'CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK', + 'CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT', + 'CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK', + 'CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT', + 'CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK', + 'CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT', + 'CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK', + 'CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT', + 'CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK', + 'CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT', + 'CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK', + 'CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT', + 'CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK', + 'CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT', + 'CGTT_PA_CLK_CTRL__DEBUG_BUS_EN_MASK', + 'CGTT_PA_CLK_CTRL__DEBUG_BUS_EN__SHIFT', + 'CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CGTT_PA_CLK_CTRL__ON_DELAY_MASK', + 'CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT', + 'CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK', + 'CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT', + 'CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK', + 'CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT', + 'CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK', + 'CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT', + 'CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK', + 'CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT', + 'CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK', + 'CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT', + 'CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK', + 'CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT', + 'CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK', + 'CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT', + 'CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK', + 'CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT', + 'CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK', + 'CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT', + 'CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK', + 'CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT', + 'CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK', + 'CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT', + 'CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK', + 'CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT', + 'CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK', + 'CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT', + 'CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK', + 'CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT', + 'CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CGTT_PC_CLK_CTRL__ON_DELAY_MASK', + 'CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT', + 'CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE_MASK', + 'CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE__SHIFT', + 'CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK', + 'CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT', + 'CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK', + 'CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT', + 'CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK', + 'CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT', + 'CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CGTT_RLC_CLK_CTRL__ON_DELAY_MASK', + 'CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT', + 'CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK', + 'CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT', + 'CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK', + 'CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT', + 'CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK', + 'CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT', + 'CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK', + 'CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT', + 'CGTT_SC_CLK_CTRL0__ON_DELAY_MASK', + 'CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT', + 'CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK', + 'CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT', + 'CGTT_SC_CLK_CTRL1__ON_DELAY_MASK', + 'CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT', + 'CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS_MASK', + 'CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS__SHIFT', + 'CGTT_SC_CLK_CTRL2__ON_DELAY_MASK', + 'CGTT_SC_CLK_CTRL2__ON_DELAY__SHIFT', + 'CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE__SHIFT', + 'CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE_MASK', + 'CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE__SHIFT', + 'CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE_MASK', + 'CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE__SHIFT', + 'CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE_MASK', + 'CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE__SHIFT', + 'CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE_MASK', + 'CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE__SHIFT', + 'CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE_MASK', + 'CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE__SHIFT', + 'CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE_MASK', + 'CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE__SHIFT', + 'CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE_MASK', + 'CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE__SHIFT', + 'CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE_MASK', + 'CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE__SHIFT', + 'CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CGTT_SPIS_CLK_CTRL__ON_DELAY_MASK', + 'CGTT_SPIS_CLK_CTRL__ON_DELAY__SHIFT', + 'CGTT_SPIS_CLK_CTRL__REG_OVERRIDE_MASK', + 'CGTT_SPIS_CLK_CTRL__REG_OVERRIDE__SHIFT', + 'CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK', + 'CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT', + 'CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK', + 'CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT', + 'CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK', + 'CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT', + 'CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CGTT_SPI_CLK_CTRL__ON_DELAY_MASK', + 'CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT', + 'CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK', + 'CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT', + 'CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE_MASK', + 'CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE__SHIFT', + 'CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE_MASK', + 'CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE__SHIFT', + 'CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE_MASK', + 'CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE__SHIFT', + 'CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE_MASK', + 'CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE__SHIFT', + 'CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE_MASK', + 'CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE__SHIFT', + 'CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE_MASK', + 'CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE__SHIFT', + 'CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE_MASK', + 'CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE__SHIFT', + 'CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CGTT_SPI_PS_CLK_CTRL__ON_DELAY_MASK', + 'CGTT_SPI_PS_CLK_CTRL__ON_DELAY__SHIFT', + 'CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE_MASK', + 'CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE__SHIFT', + 'CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK', + 'CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT', + 'CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CGTT_SQG_CLK_CTRL__ON_DELAY_MASK', + 'CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT', + 'CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK', + 'CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT', + 'CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK', + 'CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK', + 'CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT', + 'CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK', + 'CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT', + 'CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK', + 'CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT', + 'CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CGTT_SQ_CLK_CTRL__ON_DELAY_MASK', + 'CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT', + 'CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK', + 'CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT', + 'CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK', + 'CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT', + 'CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK', + 'CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT', + 'CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CGTT_TCPF_CLK_CTRL__ON_DELAY_MASK', + 'CGTT_TCPF_CLK_CTRL__ON_DELAY__SHIFT', + 'CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0_MASK', + 'CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0__SHIFT', + 'CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1_MASK', + 'CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1__SHIFT', + 'CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2_MASK', + 'CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2__SHIFT', + 'CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3_MASK', + 'CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3__SHIFT', + 'CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4_MASK', + 'CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4__SHIFT', + 'CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5_MASK', + 'CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5__SHIFT', + 'CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6_MASK', + 'CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6__SHIFT', + 'CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7_MASK', + 'CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7__SHIFT', + 'CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK', + 'CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT', + 'CGTT_TCPF_CLK_CTRL__SPARE_MASK', + 'CGTT_TCPF_CLK_CTRL__SPARE__SHIFT', + 'CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CGTT_TCPI_CLK_CTRL__ON_DELAY_MASK', + 'CGTT_TCPI_CLK_CTRL__ON_DELAY__SHIFT', + 'CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0_MASK', + 'CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT', + 'CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1_MASK', + 'CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT', + 'CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2_MASK', + 'CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT', + 'CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3_MASK', + 'CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT', + 'CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4_MASK', + 'CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT', + 'CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5_MASK', + 'CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT', + 'CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6_MASK', + 'CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT', + 'CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7_MASK', + 'CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT', + 'CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK', + 'CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT', + 'CGTT_TCPI_CLK_CTRL__SPARE_MASK', + 'CGTT_TCPI_CLK_CTRL__SPARE__SHIFT', + 'CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK', + 'CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT', + 'CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK', + 'CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT', + 'CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK', + 'CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT', + 'CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CGTT_VGT_CLK_CTRL__ON_DELAY_MASK', + 'CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT', + 'CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK', + 'CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT', + 'CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE_MASK', + 'CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT', + 'CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK', + 'CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT', + 'CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK', + 'CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT', + 'CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8_MASK', + 'CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8__SHIFT', + 'CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9_MASK', + 'CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9__SHIFT', + 'CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK', + 'CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT', + 'CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK', + 'CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT', + 'CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK', + 'CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT', + 'CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'CGTT_WD_CLK_CTRL__ON_DELAY_MASK', + 'CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT', + 'CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK', + 'CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT', + 'CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE_MASK', + 'CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT', + 'CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK', + 'CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT', + 'CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK', + 'CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT', + 'CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK', + 'CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT', + 'CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8_MASK', + 'CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8__SHIFT', + 'CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK', + 'CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT', + 'CGTX_SPI_DEBUG_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK', + 'CGTX_SPI_DEBUG_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT', + 'CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OFF_HYST_MASK', + 'CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT', + 'CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OVERRIDE_MASK', + 'CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT', + 'CGTX_SPI_DEBUG_CLK_CTRL__SPI_REPEATER_FGCG_OVERRIDE_MASK', + 'CGTX_SPI_DEBUG_CLK_CTRL__SPI_REPEATER_FGCG_OVERRIDE__SHIFT', + 'CGTX_SPI_DEBUG_CLK_CTRL__SPI_SH_CLK_CONTROL_MASK', + 'CGTX_SPI_DEBUG_CLK_CTRL__SPI_SH_CLK_CONTROL__SHIFT', + 'COHER_DEST_BASE_0__DEST_BASE_256B_MASK', + 'COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT', + 'COHER_DEST_BASE_1__DEST_BASE_256B_MASK', + 'COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT', + 'COHER_DEST_BASE_2__DEST_BASE_256B_MASK', + 'COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT', + 'COHER_DEST_BASE_3__DEST_BASE_256B_MASK', + 'COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT', + 'COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK', + 'COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT', + 'COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK', + 'COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT', + 'COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK', + 'COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT', + 'COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK', + 'COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT', + 'COMPUTE_CURRENT_LOGIC_XCC_ID__CURRENT_LOGIC_XCC_ID_MASK', + 'COMPUTE_CURRENT_LOGIC_XCC_ID__CURRENT_LOGIC_XCC_ID__SHIFT', + 'COMPUTE_DIM_X__SIZE_MASK', 'COMPUTE_DIM_X__SIZE__SHIFT', + 'COMPUTE_DIM_Y__SIZE_MASK', 'COMPUTE_DIM_Y__SIZE__SHIFT', + 'COMPUTE_DIM_Z__SIZE_MASK', 'COMPUTE_DIM_Z__SIZE__SHIFT', + 'COMPUTE_DISPATCH_END__DATA_MASK', + 'COMPUTE_DISPATCH_END__DATA__SHIFT', + 'COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK', + 'COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK', + 'COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK', + 'COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK', + 'COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK', + 'COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK', + 'COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK', + 'COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK', + 'COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK', + 'COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK', + 'COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK', + 'COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT', + 'COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK', + 'COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT', + 'COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK', + 'COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT', + 'COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK', + 'COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT', + 'COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK', + 'COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT', + 'COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK', + 'COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT', + 'COMPUTE_MISC_RESERVED__SEND_SEID_MASK', + 'COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT', + 'COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK', + 'COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT', + 'COMPUTE_NOWHERE__DATA_MASK', 'COMPUTE_NOWHERE__DATA__SHIFT', + 'COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK', + 'COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT', + 'COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK', + 'COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT', + 'COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK', + 'COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT', + 'COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK', + 'COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT', + 'COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK', + 'COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT', + 'COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK', + 'COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT', + 'COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK', + 'COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT', + 'COMPUTE_PGM_HI__DATA_MASK', 'COMPUTE_PGM_HI__DATA__SHIFT', + 'COMPUTE_PGM_LO__DATA_MASK', 'COMPUTE_PGM_LO__DATA__SHIFT', + 'COMPUTE_PGM_RSRC1__BULKY_MASK', + 'COMPUTE_PGM_RSRC1__BULKY__SHIFT', + 'COMPUTE_PGM_RSRC1__CDBG_USER_MASK', + 'COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT', + 'COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK', + 'COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT', + 'COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK', + 'COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT', + 'COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK', + 'COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT', + 'COMPUTE_PGM_RSRC1__FP16_OVFL_MASK', + 'COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT', + 'COMPUTE_PGM_RSRC1__IEEE_MODE_MASK', + 'COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT', + 'COMPUTE_PGM_RSRC1__PRIORITY_MASK', + 'COMPUTE_PGM_RSRC1__PRIORITY__SHIFT', + 'COMPUTE_PGM_RSRC1__PRIV_MASK', 'COMPUTE_PGM_RSRC1__PRIV__SHIFT', + 'COMPUTE_PGM_RSRC1__SGPRS_MASK', + 'COMPUTE_PGM_RSRC1__SGPRS__SHIFT', + 'COMPUTE_PGM_RSRC1__VGPRS_MASK', + 'COMPUTE_PGM_RSRC1__VGPRS__SHIFT', + 'COMPUTE_PGM_RSRC2__EXCP_EN_MASK', + 'COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK', + 'COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT', + 'COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT', + 'COMPUTE_PGM_RSRC2__LDS_SIZE_MASK', + 'COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT', + 'COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK', + 'COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT', + 'COMPUTE_PGM_RSRC2__SKIP_USGPR0_MASK', + 'COMPUTE_PGM_RSRC2__SKIP_USGPR0__SHIFT', + 'COMPUTE_PGM_RSRC2__TGID_X_EN_MASK', + 'COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT', + 'COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK', + 'COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT', + 'COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK', + 'COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT', + 'COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK', + 'COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT', + 'COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK', + 'COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT', + 'COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK', + 'COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT', + 'COMPUTE_PGM_RSRC2__USER_SGPR_MASK', + 'COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT', + 'COMPUTE_PGM_RSRC3__ACCUM_OFFSET_MASK', + 'COMPUTE_PGM_RSRC3__ACCUM_OFFSET__SHIFT', + 'COMPUTE_PGM_RSRC3__TG_SPLIT_MASK', + 'COMPUTE_PGM_RSRC3__TG_SPLIT__SHIFT', + 'COMPUTE_PGM_RSRC3__TRAP_ON_END_MASK', + 'COMPUTE_PGM_RSRC3__TRAP_ON_END__SHIFT', + 'COMPUTE_PGM_RSRC3__TRAP_ON_START_MASK', + 'COMPUTE_PGM_RSRC3__TRAP_ON_START__SHIFT', + 'COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK', + 'COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT', + 'COMPUTE_RELAUNCH__IS_EVENT_MASK', + 'COMPUTE_RELAUNCH__IS_EVENT__SHIFT', + 'COMPUTE_RELAUNCH__IS_STATE_MASK', + 'COMPUTE_RELAUNCH__IS_STATE__SHIFT', + 'COMPUTE_RELAUNCH__PAYLOAD_MASK', + 'COMPUTE_RELAUNCH__PAYLOAD__SHIFT', + 'COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK', + 'COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT', + 'COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK', + 'COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT', + 'COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK', + 'COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT', + 'COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK', + 'COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT', + 'COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE_MASK', + 'COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE__SHIFT', + 'COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK', + 'COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT', + 'COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK', + 'COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT', + 'COMPUTE_RESTART_X__RESTART_MASK', + 'COMPUTE_RESTART_X__RESTART__SHIFT', + 'COMPUTE_RESTART_Y__RESTART_MASK', + 'COMPUTE_RESTART_Y__RESTART__SHIFT', + 'COMPUTE_RESTART_Z__RESTART_MASK', + 'COMPUTE_RESTART_Z__RESTART__SHIFT', + 'COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK', + 'COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT', + 'COMPUTE_START_X__START_MASK', 'COMPUTE_START_X__START__SHIFT', + 'COMPUTE_START_Y__START_MASK', 'COMPUTE_START_Y__START__SHIFT', + 'COMPUTE_START_Z__START_MASK', 'COMPUTE_START_Z__START__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT', + 'COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK', + 'COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT', + 'COMPUTE_TG_CHUNK_SIZE__TG_CHUNK_SIZE_MASK', + 'COMPUTE_TG_CHUNK_SIZE__TG_CHUNK_SIZE__SHIFT', + 'COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK', + 'COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT', + 'COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK', + 'COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT', + 'COMPUTE_TMPRING_SIZE__WAVESIZE_MASK', + 'COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT', + 'COMPUTE_TMPRING_SIZE__WAVES_MASK', + 'COMPUTE_TMPRING_SIZE__WAVES__SHIFT', + 'COMPUTE_USER_DATA_0__DATA_MASK', + 'COMPUTE_USER_DATA_0__DATA__SHIFT', + 'COMPUTE_USER_DATA_10__DATA_MASK', + 'COMPUTE_USER_DATA_10__DATA__SHIFT', + 'COMPUTE_USER_DATA_11__DATA_MASK', + 'COMPUTE_USER_DATA_11__DATA__SHIFT', + 'COMPUTE_USER_DATA_12__DATA_MASK', + 'COMPUTE_USER_DATA_12__DATA__SHIFT', + 'COMPUTE_USER_DATA_13__DATA_MASK', + 'COMPUTE_USER_DATA_13__DATA__SHIFT', + 'COMPUTE_USER_DATA_14__DATA_MASK', + 'COMPUTE_USER_DATA_14__DATA__SHIFT', + 'COMPUTE_USER_DATA_15__DATA_MASK', + 'COMPUTE_USER_DATA_15__DATA__SHIFT', + 'COMPUTE_USER_DATA_1__DATA_MASK', + 'COMPUTE_USER_DATA_1__DATA__SHIFT', + 'COMPUTE_USER_DATA_2__DATA_MASK', + 'COMPUTE_USER_DATA_2__DATA__SHIFT', + 'COMPUTE_USER_DATA_3__DATA_MASK', + 'COMPUTE_USER_DATA_3__DATA__SHIFT', + 'COMPUTE_USER_DATA_4__DATA_MASK', + 'COMPUTE_USER_DATA_4__DATA__SHIFT', + 'COMPUTE_USER_DATA_5__DATA_MASK', + 'COMPUTE_USER_DATA_5__DATA__SHIFT', + 'COMPUTE_USER_DATA_6__DATA_MASK', + 'COMPUTE_USER_DATA_6__DATA__SHIFT', + 'COMPUTE_USER_DATA_7__DATA_MASK', + 'COMPUTE_USER_DATA_7__DATA__SHIFT', + 'COMPUTE_USER_DATA_8__DATA_MASK', + 'COMPUTE_USER_DATA_8__DATA__SHIFT', + 'COMPUTE_USER_DATA_9__DATA_MASK', + 'COMPUTE_USER_DATA_9__DATA__SHIFT', 'COMPUTE_VMID__DATA_MASK', + 'COMPUTE_VMID__DATA__SHIFT', + 'COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK', + 'COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT', + 'COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK', + 'COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT', + 'CPC_CE_ERR_STATUS_HI__CE_CNT_MASK', + 'CPC_CE_ERR_STATUS_HI__CE_CNT__SHIFT', + 'CPC_CE_ERR_STATUS_HI__ECC_MASK', + 'CPC_CE_ERR_STATUS_HI__ECC__SHIFT', + 'CPC_CE_ERR_STATUS_HI__ERR_INFO_MASK', + 'CPC_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'CPC_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'CPC_CE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'CPC_CE_ERR_STATUS_HI__OTHER_MASK', + 'CPC_CE_ERR_STATUS_HI__OTHER__SHIFT', + 'CPC_CE_ERR_STATUS_HI__POISON_MASK', + 'CPC_CE_ERR_STATUS_HI__POISON__SHIFT', + 'CPC_CE_ERR_STATUS_HI__RESERVED_MASK', + 'CPC_CE_ERR_STATUS_HI__RESERVED__SHIFT', + 'CPC_CE_ERR_STATUS_LO__ADDRESS_MASK', + 'CPC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'CPC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'CPC_CE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'CPC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'CPC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'CPC_CE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'CPC_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'CPC_INT_ADDR__ADDR_MASK', 'CPC_INT_ADDR__ADDR__SHIFT', + 'CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK', + 'CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK', + 'CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK', + 'CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK', + 'CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK', + 'CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__GPF_INT_ENABLE_MASK', + 'CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK', + 'CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK', + 'CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK', + 'CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK', + 'CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT', + 'CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CPC_INT_CNTX_ID__CNTX_ID_MASK', + 'CPC_INT_CNTX_ID__CNTX_ID__SHIFT', 'CPC_INT_INFO__ADDR_HI_MASK', + 'CPC_INT_INFO__ADDR_HI__SHIFT', 'CPC_INT_INFO__QUEUE_ID_MASK', + 'CPC_INT_INFO__QUEUE_ID__SHIFT', 'CPC_INT_INFO__TYPE_MASK', + 'CPC_INT_INFO__TYPE__SHIFT', 'CPC_INT_INFO__VMID_MASK', + 'CPC_INT_INFO__VMID__SHIFT', 'CPC_INT_PASID__PASID_MASK', + 'CPC_INT_PASID__PASID__SHIFT', + 'CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK', + 'CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK', + 'CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK', + 'CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK', + 'CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK', + 'CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK', + 'CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__GPF_INT_STATUS_MASK', + 'CPC_INT_STATUS__GPF_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK', + 'CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK', + 'CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK', + 'CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK', + 'CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK', + 'CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT', + 'CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK', + 'CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT', + 'CPC_LATENCY_STATS_DATA__DATA_MASK', + 'CPC_LATENCY_STATS_DATA__DATA__SHIFT', + 'CPC_LATENCY_STATS_SELECT__CLEAR_MASK', + 'CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT', + 'CPC_LATENCY_STATS_SELECT__ENABLE_MASK', + 'CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT', + 'CPC_LATENCY_STATS_SELECT__INDEX_MASK', + 'CPC_LATENCY_STATS_SELECT__INDEX__SHIFT', + 'CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK', + 'CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT', + 'CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK', + 'CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT', + 'CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK', + 'CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT', + 'CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK', + 'CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT', + 'CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK', + 'CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT', + 'CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK', + 'CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT', + 'CPC_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK', + 'CPC_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT', + 'CPC_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK', + 'CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT', + 'CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK', + 'CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT', + 'CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK', + 'CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT', + 'CPC_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK', + 'CPC_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT', + 'CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK', + 'CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT', + 'CPC_PSP_DEBUG__CPC_DC_FIX_DISABLE_MASK', + 'CPC_PSP_DEBUG__CPC_DC_FIX_DISABLE__SHIFT', + 'CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK', + 'CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT', + 'CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK', + 'CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE__SHIFT', + 'CPC_PSP_DEBUG__VMID_VIOLATION_CNTL_MASK', + 'CPC_PSP_DEBUG__VMID_VIOLATION_CNTL__SHIFT', + 'CPC_UE_ERR_STATUS_HI__ECC_MASK', + 'CPC_UE_ERR_STATUS_HI__ECC__SHIFT', + 'CPC_UE_ERR_STATUS_HI__ERR_INFO_MASK', + 'CPC_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'CPC_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'CPC_UE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'CPC_UE_ERR_STATUS_HI__FED_CNT_MASK', + 'CPC_UE_ERR_STATUS_HI__FED_CNT__SHIFT', + 'CPC_UE_ERR_STATUS_HI__PARITY_MASK', + 'CPC_UE_ERR_STATUS_HI__PARITY__SHIFT', + 'CPC_UE_ERR_STATUS_HI__RESERVED_MASK', + 'CPC_UE_ERR_STATUS_HI__RESERVED__SHIFT', + 'CPC_UE_ERR_STATUS_HI__UE_CNT_MASK', + 'CPC_UE_ERR_STATUS_HI__UE_CNT__SHIFT', + 'CPC_UE_ERR_STATUS_LO__ADDRESS_MASK', + 'CPC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'CPC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'CPC_UE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'CPC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'CPC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'CPC_UE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'CPC_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'CPC_UTCL1_CNTL__DROP_MODE_MASK', + 'CPC_UTCL1_CNTL__DROP_MODE__SHIFT', + 'CPC_UTCL1_CNTL__FORCE_SNOOP_MASK', + 'CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT', + 'CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK', + 'CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT', + 'CPC_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK', + 'CPC_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT', + 'CPC_UTCL1_CNTL__INVALIDATE_MASK', + 'CPC_UTCL1_CNTL__INVALIDATE__SHIFT', + 'CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK', + 'CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT', + 'CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK', + 'CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT', + 'CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK', + 'CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT', + 'CPC_UTCL1_STATUS__FAULT_DETECTED_MASK', + 'CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT', + 'CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK', + 'CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT', + 'CPC_UTCL1_STATUS__PRT_DETECTED_MASK', + 'CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT', + 'CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK', + 'CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT', + 'CPC_UTCL1_STATUS__RETRY_DETECTED_MASK', + 'CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT', + 'CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK', + 'CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT', + 'CPF_CE_ERR_STATUS_HI__CE_CNT_MASK', + 'CPF_CE_ERR_STATUS_HI__CE_CNT__SHIFT', + 'CPF_CE_ERR_STATUS_HI__ECC_MASK', + 'CPF_CE_ERR_STATUS_HI__ECC__SHIFT', + 'CPF_CE_ERR_STATUS_HI__ERR_INFO_MASK', + 'CPF_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'CPF_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'CPF_CE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'CPF_CE_ERR_STATUS_HI__OTHER_MASK', + 'CPF_CE_ERR_STATUS_HI__OTHER__SHIFT', + 'CPF_CE_ERR_STATUS_HI__POISON_MASK', + 'CPF_CE_ERR_STATUS_HI__POISON__SHIFT', + 'CPF_CE_ERR_STATUS_HI__RESERVED_MASK', + 'CPF_CE_ERR_STATUS_HI__RESERVED__SHIFT', + 'CPF_CE_ERR_STATUS_LO__ADDRESS_MASK', + 'CPF_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'CPF_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'CPF_CE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'CPF_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'CPF_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'CPF_CE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'CPF_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'CPF_LATENCY_STATS_DATA__DATA_MASK', + 'CPF_LATENCY_STATS_DATA__DATA__SHIFT', + 'CPF_LATENCY_STATS_SELECT__CLEAR_MASK', + 'CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT', + 'CPF_LATENCY_STATS_SELECT__ENABLE_MASK', + 'CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT', + 'CPF_LATENCY_STATS_SELECT__INDEX_MASK', + 'CPF_LATENCY_STATS_SELECT__INDEX__SHIFT', + 'CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK', + 'CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT', + 'CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK', + 'CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT', + 'CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK', + 'CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT', + 'CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK', + 'CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT', + 'CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK', + 'CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT', + 'CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK', + 'CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT', + 'CPF_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK', + 'CPF_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT', + 'CPF_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK', + 'CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT', + 'CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK', + 'CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT', + 'CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK', + 'CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT', + 'CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK', + 'CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT', + 'CPF_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK', + 'CPF_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT', + 'CPF_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK', + 'CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT', + 'CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK', + 'CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT', + 'CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK', + 'CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT', + 'CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK', + 'CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT', + 'CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK', + 'CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT', + 'CPF_UE_ERR_STATUS_HI__ECC_MASK', + 'CPF_UE_ERR_STATUS_HI__ECC__SHIFT', + 'CPF_UE_ERR_STATUS_HI__ERR_INFO_MASK', + 'CPF_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'CPF_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'CPF_UE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'CPF_UE_ERR_STATUS_HI__FED_CNT_MASK', + 'CPF_UE_ERR_STATUS_HI__FED_CNT__SHIFT', + 'CPF_UE_ERR_STATUS_HI__PARITY_MASK', + 'CPF_UE_ERR_STATUS_HI__PARITY__SHIFT', + 'CPF_UE_ERR_STATUS_HI__RESERVED_MASK', + 'CPF_UE_ERR_STATUS_HI__RESERVED__SHIFT', + 'CPF_UE_ERR_STATUS_HI__UE_CNT_MASK', + 'CPF_UE_ERR_STATUS_HI__UE_CNT__SHIFT', + 'CPF_UE_ERR_STATUS_LO__ADDRESS_MASK', + 'CPF_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'CPF_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'CPF_UE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'CPF_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'CPF_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'CPF_UE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'CPF_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'CPF_UTCL1_CNTL__DROP_MODE_MASK', + 'CPF_UTCL1_CNTL__DROP_MODE__SHIFT', + 'CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK', + 'CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT', + 'CPF_UTCL1_CNTL__FORCE_SNOOP_MASK', + 'CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT', + 'CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK', + 'CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT', + 'CPF_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK', + 'CPF_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT', + 'CPF_UTCL1_CNTL__INVALIDATE_MASK', + 'CPF_UTCL1_CNTL__INVALIDATE__SHIFT', + 'CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK', + 'CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT', + 'CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK', + 'CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT', + 'CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK', + 'CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT', + 'CPF_UTCL1_STATUS__FAULT_DETECTED_MASK', + 'CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT', + 'CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK', + 'CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT', + 'CPF_UTCL1_STATUS__PRT_DETECTED_MASK', + 'CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT', + 'CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK', + 'CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT', + 'CPF_UTCL1_STATUS__RETRY_DETECTED_MASK', + 'CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT', + 'CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK', + 'CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT', + 'CPG_CE_ERR_STATUS_HI__CE_CNT_MASK', + 'CPG_CE_ERR_STATUS_HI__CE_CNT__SHIFT', + 'CPG_CE_ERR_STATUS_HI__ECC_MASK', + 'CPG_CE_ERR_STATUS_HI__ECC__SHIFT', + 'CPG_CE_ERR_STATUS_HI__ERR_INFO_MASK', + 'CPG_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'CPG_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'CPG_CE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'CPG_CE_ERR_STATUS_HI__OTHER_MASK', + 'CPG_CE_ERR_STATUS_HI__OTHER__SHIFT', + 'CPG_CE_ERR_STATUS_HI__POISON_MASK', + 'CPG_CE_ERR_STATUS_HI__POISON__SHIFT', + 'CPG_CE_ERR_STATUS_HI__RESERVED_MASK', + 'CPG_CE_ERR_STATUS_HI__RESERVED__SHIFT', + 'CPG_CE_ERR_STATUS_LO__ADDRESS_MASK', + 'CPG_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'CPG_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'CPG_CE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'CPG_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'CPG_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'CPG_CE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'CPG_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'CPG_LATENCY_STATS_DATA__DATA_MASK', + 'CPG_LATENCY_STATS_DATA__DATA__SHIFT', + 'CPG_LATENCY_STATS_SELECT__CLEAR_MASK', + 'CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT', + 'CPG_LATENCY_STATS_SELECT__ENABLE_MASK', + 'CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT', + 'CPG_LATENCY_STATS_SELECT__INDEX_MASK', + 'CPG_LATENCY_STATS_SELECT__INDEX__SHIFT', + 'CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK', + 'CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT', + 'CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK', + 'CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT', + 'CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK', + 'CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT', + 'CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK', + 'CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT', + 'CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK', + 'CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT', + 'CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK', + 'CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT', + 'CPG_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK', + 'CPG_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT', + 'CPG_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK', + 'CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT', + 'CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK', + 'CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT', + 'CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK', + 'CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT', + 'CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK', + 'CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT', + 'CPG_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK', + 'CPG_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT', + 'CPG_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK', + 'CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT', + 'CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK', + 'CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT', + 'CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK', + 'CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT', + 'CPG_PSP_DEBUG__VMID_VIOLATION_CNTL_MASK', + 'CPG_PSP_DEBUG__VMID_VIOLATION_CNTL__SHIFT', + 'CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK', + 'CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT', + 'CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK', + 'CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT', + 'CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK', + 'CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT', + 'CPG_UE_ERR_STATUS_HI__ECC_MASK', + 'CPG_UE_ERR_STATUS_HI__ECC__SHIFT', + 'CPG_UE_ERR_STATUS_HI__ERR_INFO_MASK', + 'CPG_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'CPG_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'CPG_UE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'CPG_UE_ERR_STATUS_HI__FED_CNT_MASK', + 'CPG_UE_ERR_STATUS_HI__FED_CNT__SHIFT', + 'CPG_UE_ERR_STATUS_HI__PARITY_MASK', + 'CPG_UE_ERR_STATUS_HI__PARITY__SHIFT', + 'CPG_UE_ERR_STATUS_HI__RESERVED_MASK', + 'CPG_UE_ERR_STATUS_HI__RESERVED__SHIFT', + 'CPG_UE_ERR_STATUS_HI__UE_CNT_MASK', + 'CPG_UE_ERR_STATUS_HI__UE_CNT__SHIFT', + 'CPG_UE_ERR_STATUS_LO__ADDRESS_MASK', + 'CPG_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'CPG_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'CPG_UE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'CPG_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'CPG_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'CPG_UE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'CPG_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'CPG_UTCL1_CNTL__DROP_MODE_MASK', + 'CPG_UTCL1_CNTL__DROP_MODE__SHIFT', + 'CPG_UTCL1_CNTL__FORCE_SNOOP_MASK', + 'CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT', + 'CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK', + 'CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT', + 'CPG_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK', + 'CPG_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT', + 'CPG_UTCL1_CNTL__INVALIDATE_MASK', + 'CPG_UTCL1_CNTL__INVALIDATE__SHIFT', + 'CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK', + 'CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT', + 'CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK', + 'CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT', + 'CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK', + 'CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT', + 'CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK', + 'CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT', + 'CPG_UTCL1_STATUS__FAULT_DETECTED_MASK', + 'CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT', + 'CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK', + 'CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT', + 'CPG_UTCL1_STATUS__PRT_DETECTED_MASK', + 'CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT', + 'CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK', + 'CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT', + 'CPG_UTCL1_STATUS__RETRY_DETECTED_MASK', + 'CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT', + 'CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK', + 'CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT', + 'CP_APPEND_ADDR_HI__CACHE_POLICY_MASK', + 'CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT', + 'CP_APPEND_ADDR_HI__COMMAND_MASK', + 'CP_APPEND_ADDR_HI__COMMAND__SHIFT', + 'CP_APPEND_ADDR_HI__CS_PS_SEL_MASK', + 'CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT', + 'CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK', + 'CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT', + 'CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK', + 'CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT', + 'CP_APPEND_DATA_HI__DATA_MASK', 'CP_APPEND_DATA_HI__DATA__SHIFT', + 'CP_APPEND_DATA_LO__DATA_MASK', 'CP_APPEND_DATA_LO__DATA__SHIFT', + 'CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK', + 'CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT', + 'CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK', + 'CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT', + 'CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK', + 'CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT', + 'CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK', + 'CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT', + 'CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK', + 'CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT', + 'CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK', + 'CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT', + 'CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK', + 'CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT', + 'CP_BUSY_STAT__CE_PARSING_PACKETS_MASK', + 'CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT', + 'CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK', + 'CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT', + 'CP_BUSY_STAT__EOP_DONE_BUSY_MASK', + 'CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT', + 'CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK', + 'CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT', + 'CP_BUSY_STAT__ME_PARSER_BUSY_MASK', + 'CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT', + 'CP_BUSY_STAT__ME_PARSING_PACKETS_MASK', + 'CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT', + 'CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK', + 'CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT', + 'CP_BUSY_STAT__PIPE_STATS_BUSY_MASK', + 'CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT', + 'CP_BUSY_STAT__RCIU_CE_BUSY_MASK', + 'CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT', + 'CP_BUSY_STAT__RCIU_ME_BUSY_MASK', + 'CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT', + 'CP_BUSY_STAT__RCIU_PFP_BUSY_MASK', + 'CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT', + 'CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK', + 'CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT', + 'CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK', + 'CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT', + 'CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK', + 'CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT', + 'CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK', + 'CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT', + 'CP_BUSY_STAT__STRM_OUT_BUSY_MASK', + 'CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT', + 'CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK', + 'CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT', + 'CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK', + 'CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT', + 'CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK', + 'CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT', + 'CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK', + 'CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT', + 'CP_CE_COMPLETION_STATUS__STATUS_MASK', + 'CP_CE_COMPLETION_STATUS__STATUS__SHIFT', + 'CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK', + 'CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT', + 'CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK', + 'CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT', + 'CP_CE_F32_INTERRUPT__CE_F32_INT_2_MASK', + 'CP_CE_F32_INTERRUPT__CE_F32_INT_2__SHIFT', + 'CP_CE_F32_INTERRUPT__CE_F32_INT_3_MASK', + 'CP_CE_F32_INTERRUPT__CE_F32_INT_3__SHIFT', + 'CP_CE_F32_INTERRUPT__ECC_ERROR_INT_MASK', + 'CP_CE_F32_INTERRUPT__ECC_ERROR_INT__SHIFT', + 'CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK', + 'CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT', + 'CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK', + 'CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT', + 'CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK', + 'CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT', + 'CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK', + 'CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT', + 'CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK', + 'CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT', + 'CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK', + 'CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT', + 'CP_CE_IB1_OFFSET__IB1_OFFSET_MASK', + 'CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT', + 'CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK', + 'CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT', + 'CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK', + 'CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT', + 'CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK', + 'CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT', + 'CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK', + 'CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT', + 'CP_CE_IB2_OFFSET__IB2_OFFSET_MASK', + 'CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT', + 'CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK', + 'CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT', + 'CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK', + 'CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT', + 'CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK', + 'CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT', + 'CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK', + 'CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT', + 'CP_CE_INSTR_PNTR__INSTR_PNTR_MASK', + 'CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT', + 'CP_CE_INTR_ROUTINE_START__IR_START_MASK', + 'CP_CE_INTR_ROUTINE_START__IR_START__SHIFT', + 'CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK', + 'CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT', + 'CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK', + 'CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT', + 'CP_CE_PRGRM_CNTR_START__IP_START_MASK', + 'CP_CE_PRGRM_CNTR_START__IP_START__SHIFT', + 'CP_CE_RB_OFFSET__RB_OFFSET_MASK', + 'CP_CE_RB_OFFSET__RB_OFFSET__SHIFT', + 'CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK', + 'CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT', + 'CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK', + 'CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT', + 'CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK', + 'CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT', + 'CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK', + 'CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT', + 'CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK', + 'CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT', + 'CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK', + 'CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT', + 'CP_CE_UCODE_ADDR__UCODE_ADDR_MASK', + 'CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT', + 'CP_CE_UCODE_DATA__UCODE_DATA_MASK', + 'CP_CE_UCODE_DATA__UCODE_DATA__SHIFT', + 'CP_CMD_DATA__CMD_DATA_MASK', 'CP_CMD_DATA__CMD_DATA__SHIFT', + 'CP_CMD_INDEX__CMD_INDEX_MASK', 'CP_CMD_INDEX__CMD_INDEX__SHIFT', + 'CP_CMD_INDEX__CMD_ME_SEL_MASK', + 'CP_CMD_INDEX__CMD_ME_SEL__SHIFT', + 'CP_CMD_INDEX__CMD_QUEUE_SEL_MASK', + 'CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT', + 'CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK', + 'CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT', + 'CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK', + 'CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT', + 'CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK', + 'CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT', + 'CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK', + 'CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT', + 'CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK', + 'CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT', + 'CP_COHER_BASE__COHER_BASE_256B_MASK', + 'CP_COHER_BASE__COHER_BASE_256B__SHIFT', + 'CP_COHER_CNTL__CB_ACTION_ENA_MASK', + 'CP_COHER_CNTL__CB_ACTION_ENA__SHIFT', + 'CP_COHER_CNTL__DB_ACTION_ENA_MASK', + 'CP_COHER_CNTL__DB_ACTION_ENA__SHIFT', + 'CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK', + 'CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT', + 'CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK', + 'CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT', + 'CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK', + 'CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT', + 'CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK', + 'CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT', + 'CP_COHER_CNTL__TCL1_ACTION_ENA_MASK', + 'CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT', + 'CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK', + 'CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT', + 'CP_COHER_CNTL__TC_ACTION_ENA_MASK', + 'CP_COHER_CNTL__TC_ACTION_ENA__SHIFT', + 'CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK', + 'CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT', + 'CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK', + 'CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT', + 'CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK', + 'CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT', + 'CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK', + 'CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT', + 'CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK', + 'CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT', + 'CP_COHER_SIZE__COHER_SIZE_256B_MASK', + 'CP_COHER_SIZE__COHER_SIZE_256B__SHIFT', + 'CP_COHER_START_DELAY__START_DELAY_COUNT_MASK', + 'CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT', + 'CP_COHER_STATUS__MEID_MASK', 'CP_COHER_STATUS__MEID__SHIFT', + 'CP_COHER_STATUS__STATUS_MASK', 'CP_COHER_STATUS__STATUS__SHIFT', + 'CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK', + 'CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT', + 'CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK', + 'CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT', + 'CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK', + 'CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT', + 'CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK', + 'CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT', + 'CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK', + 'CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT', + 'CP_CPC_DEBUG_2__DC_GD_PIPE0_QSWITCH_CNT_MASK', + 'CP_CPC_DEBUG_2__DC_GD_PIPE0_QSWITCH_CNT__SHIFT', + 'CP_CPC_DEBUG_2__DC_GD_PIPE1_QSWITCH_CNT_MASK', + 'CP_CPC_DEBUG_2__DC_GD_PIPE1_QSWITCH_CNT__SHIFT', + 'CP_CPC_DEBUG_2__DC_GD_PIPE2_QSWITCH_CNT_MASK', + 'CP_CPC_DEBUG_2__DC_GD_PIPE2_QSWITCH_CNT__SHIFT', + 'CP_CPC_DEBUG_2__DC_GD_PIPE3_QSWITCH_CNT_MASK', + 'CP_CPC_DEBUG_2__DC_GD_PIPE3_QSWITCH_CNT__SHIFT', + 'CP_CPC_DEBUG_CNTL__DEBUG_BUS_DC_GD_SEL_MASK', + 'CP_CPC_DEBUG_CNTL__DEBUG_BUS_DC_GD_SEL__SHIFT', + 'CP_CPC_DEBUG_CNTL__DEBUG_BUS_FLOP_EN_MASK', + 'CP_CPC_DEBUG_CNTL__DEBUG_BUS_FLOP_EN__SHIFT', + 'CP_CPC_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS_MASK', + 'CP_CPC_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS__SHIFT', + 'CP_CPC_DEBUG_CNTL__DEBUG_INDX_MASK', + 'CP_CPC_DEBUG_CNTL__DEBUG_INDX__SHIFT', + 'CP_CPC_DEBUG__BUSY_EXTENDER_MASK', + 'CP_CPC_DEBUG__BUSY_EXTENDER__SHIFT', + 'CP_CPC_DEBUG__CPC_HARVESTING_CONTINUE_DISABLE_MASK', + 'CP_CPC_DEBUG__CPC_HARVESTING_CONTINUE_DISABLE__SHIFT', + 'CP_CPC_DEBUG__CPC_HARVESTING_DISPATCH_DISABLE_MASK', + 'CP_CPC_DEBUG__CPC_HARVESTING_DISPATCH_DISABLE__SHIFT', + 'CP_CPC_DEBUG__CPC_HARVESTING_RELAUNCH_DISABLE_MASK', + 'CP_CPC_DEBUG__CPC_HARVESTING_RELAUNCH_DISABLE__SHIFT', + 'CP_CPC_DEBUG__CPC_HARVEST_AUTO_DISABLE_MASK', + 'CP_CPC_DEBUG__CPC_HARVEST_AUTO_DISABLE__SHIFT', + 'CP_CPC_DEBUG__CPC_PIPE_SEL_MASK', + 'CP_CPC_DEBUG__CPC_PIPE_SEL__SHIFT', + 'CP_CPC_DEBUG__CPC_RAM_CLK_GATING_DISABLE_MASK', + 'CP_CPC_DEBUG__CPC_RAM_CLK_GATING_DISABLE__SHIFT', + 'CP_CPC_DEBUG__CPC_REPEATER_FGCG_OVERRIDE_MASK', + 'CP_CPC_DEBUG__CPC_REPEATER_FGCG_OVERRIDE__SHIFT', + 'CP_CPC_DEBUG__CPC_ROLLOVER_EVENT_DEBUG_EN_MASK', + 'CP_CPC_DEBUG__CPC_ROLLOVER_EVENT_DEBUG_EN__SHIFT', + 'CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE_MASK', + 'CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT', + 'CP_CPC_DEBUG__CS_STATE_FILT_DISABLE_MASK', + 'CP_CPC_DEBUG__CS_STATE_FILT_DISABLE__SHIFT', + 'CP_CPC_DEBUG__EVENT_FILT_DISABLE_MASK', + 'CP_CPC_DEBUG__EVENT_FILT_DISABLE__SHIFT', + 'CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE_MASK', + 'CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE__SHIFT', + 'CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE_MASK', + 'CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT', + 'CP_CPC_DEBUG__PRIV_REG_INTERRUPT_ENABLE_MASK', + 'CP_CPC_DEBUG__PRIV_REG_INTERRUPT_ENABLE__SHIFT', + 'CP_CPC_DEBUG__RESERVED_INTERRUPT_ENABLE_MASK', + 'CP_CPC_DEBUG__RESERVED_INTERRUPT_ENABLE__SHIFT', + 'CP_CPC_DEBUG__RESTORE_FIFO_EMPTY_SEL_MASK', + 'CP_CPC_DEBUG__RESTORE_FIFO_EMPTY_SEL__SHIFT', + 'CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE_MASK', + 'CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE__SHIFT', + 'CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK', + 'CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT', + 'CP_CPC_DSM_CNTL2A__CPC_INJECT_DELAY_MASK', + 'CP_CPC_DSM_CNTL2A__CPC_INJECT_DELAY__SHIFT', + 'CP_CPC_DSM_CNTL2__CPC0_ENABLE_ERROR_INJECT_MASK', + 'CP_CPC_DSM_CNTL2__CPC0_ENABLE_ERROR_INJECT__SHIFT', + 'CP_CPC_DSM_CNTL2__CPC0_SELECT_INJECT_DELAY_MASK', + 'CP_CPC_DSM_CNTL2__CPC0_SELECT_INJECT_DELAY__SHIFT', + 'CP_CPC_DSM_CNTL2__CPC1_ENABLE_ERROR_INJECT_MASK', + 'CP_CPC_DSM_CNTL2__CPC1_ENABLE_ERROR_INJECT__SHIFT', + 'CP_CPC_DSM_CNTL2__CPC1_SELECT_INJECT_DELAY_MASK', + 'CP_CPC_DSM_CNTL2__CPC1_SELECT_INJECT_DELAY__SHIFT', + 'CP_CPC_DSM_CNTL2__CPC2_ENABLE_ERROR_INJECT_MASK', + 'CP_CPC_DSM_CNTL2__CPC2_ENABLE_ERROR_INJECT__SHIFT', + 'CP_CPC_DSM_CNTL2__CPC2_SELECT_INJECT_DELAY_MASK', + 'CP_CPC_DSM_CNTL2__CPC2_SELECT_INJECT_DELAY__SHIFT', + 'CP_CPC_DSM_CNTL2__CPC3_ENABLE_ERROR_INJECT_MASK', + 'CP_CPC_DSM_CNTL2__CPC3_ENABLE_ERROR_INJECT__SHIFT', + 'CP_CPC_DSM_CNTL2__CPC3_SELECT_INJECT_DELAY_MASK', + 'CP_CPC_DSM_CNTL2__CPC3_SELECT_INJECT_DELAY__SHIFT', + 'CP_CPC_DSM_CNTL2__CPC4_ENABLE_ERROR_INJECT_MASK', + 'CP_CPC_DSM_CNTL2__CPC4_ENABLE_ERROR_INJECT__SHIFT', + 'CP_CPC_DSM_CNTL2__CPC4_SELECT_INJECT_DELAY_MASK', + 'CP_CPC_DSM_CNTL2__CPC4_SELECT_INJECT_DELAY__SHIFT', + 'CP_CPC_DSM_CNTL2__CPC5_ENABLE_ERROR_INJECT_MASK', + 'CP_CPC_DSM_CNTL2__CPC5_ENABLE_ERROR_INJECT__SHIFT', + 'CP_CPC_DSM_CNTL2__CPC5_SELECT_INJECT_DELAY_MASK', + 'CP_CPC_DSM_CNTL2__CPC5_SELECT_INJECT_DELAY__SHIFT', + 'CP_CPC_DSM_CNTL2__CPC6_ENABLE_ERROR_INJECT_MASK', + 'CP_CPC_DSM_CNTL2__CPC6_ENABLE_ERROR_INJECT__SHIFT', + 'CP_CPC_DSM_CNTL2__CPC6_SELECT_INJECT_DELAY_MASK', + 'CP_CPC_DSM_CNTL2__CPC6_SELECT_INJECT_DELAY__SHIFT', + 'CP_CPC_DSM_CNTL2__CPC7_ENABLE_ERROR_INJECT_MASK', + 'CP_CPC_DSM_CNTL2__CPC7_ENABLE_ERROR_INJECT__SHIFT', + 'CP_CPC_DSM_CNTL2__CPC7_SELECT_INJECT_DELAY_MASK', + 'CP_CPC_DSM_CNTL2__CPC7_SELECT_INJECT_DELAY__SHIFT', + 'CP_CPC_DSM_CNTL2__CPC8_ENABLE_ERROR_INJECT_MASK', + 'CP_CPC_DSM_CNTL2__CPC8_ENABLE_ERROR_INJECT__SHIFT', + 'CP_CPC_DSM_CNTL2__CPC8_SELECT_INJECT_DELAY_MASK', + 'CP_CPC_DSM_CNTL2__CPC8_SELECT_INJECT_DELAY__SHIFT', + 'CP_CPC_DSM_CNTL__CPC0_DSM_IRRITATOR_DATA_MASK', + 'CP_CPC_DSM_CNTL__CPC0_DSM_IRRITATOR_DATA__SHIFT', + 'CP_CPC_DSM_CNTL__CPC0_ENABLE_SINGLE_WRITE_MASK', + 'CP_CPC_DSM_CNTL__CPC0_ENABLE_SINGLE_WRITE__SHIFT', + 'CP_CPC_DSM_CNTL__CPC1_DSM_IRRITATOR_DATA_MASK', + 'CP_CPC_DSM_CNTL__CPC1_DSM_IRRITATOR_DATA__SHIFT', + 'CP_CPC_DSM_CNTL__CPC1_ENABLE_SINGLE_WRITE_MASK', + 'CP_CPC_DSM_CNTL__CPC1_ENABLE_SINGLE_WRITE__SHIFT', + 'CP_CPC_DSM_CNTL__CPC2_DSM_IRRITATOR_DATA_MASK', + 'CP_CPC_DSM_CNTL__CPC2_DSM_IRRITATOR_DATA__SHIFT', + 'CP_CPC_DSM_CNTL__CPC2_ENABLE_SINGLE_WRITE_MASK', + 'CP_CPC_DSM_CNTL__CPC2_ENABLE_SINGLE_WRITE__SHIFT', + 'CP_CPC_DSM_CNTL__CPC3_DSM_IRRITATOR_DATA_MASK', + 'CP_CPC_DSM_CNTL__CPC3_DSM_IRRITATOR_DATA__SHIFT', + 'CP_CPC_DSM_CNTL__CPC3_ENABLE_SINGLE_WRITE_MASK', + 'CP_CPC_DSM_CNTL__CPC3_ENABLE_SINGLE_WRITE__SHIFT', + 'CP_CPC_DSM_CNTL__CPC4_DSM_IRRITATOR_DATA_MASK', + 'CP_CPC_DSM_CNTL__CPC4_DSM_IRRITATOR_DATA__SHIFT', + 'CP_CPC_DSM_CNTL__CPC4_ENABLE_SINGLE_WRITE_MASK', + 'CP_CPC_DSM_CNTL__CPC4_ENABLE_SINGLE_WRITE__SHIFT', + 'CP_CPC_DSM_CNTL__CPC5_DSM_IRRITATOR_DATA_MASK', + 'CP_CPC_DSM_CNTL__CPC5_DSM_IRRITATOR_DATA__SHIFT', + 'CP_CPC_DSM_CNTL__CPC5_ENABLE_SINGLE_WRITE_MASK', + 'CP_CPC_DSM_CNTL__CPC5_ENABLE_SINGLE_WRITE__SHIFT', + 'CP_CPC_DSM_CNTL__CPC6_DSM_IRRITATOR_DATA_MASK', + 'CP_CPC_DSM_CNTL__CPC6_DSM_IRRITATOR_DATA__SHIFT', + 'CP_CPC_DSM_CNTL__CPC6_ENABLE_SINGLE_WRITE_MASK', + 'CP_CPC_DSM_CNTL__CPC6_ENABLE_SINGLE_WRITE__SHIFT', + 'CP_CPC_DSM_CNTL__CPC7_DSM_IRRITATOR_DATA_MASK', + 'CP_CPC_DSM_CNTL__CPC7_DSM_IRRITATOR_DATA__SHIFT', + 'CP_CPC_DSM_CNTL__CPC7_ENABLE_SINGLE_WRITE_MASK', + 'CP_CPC_DSM_CNTL__CPC7_ENABLE_SINGLE_WRITE__SHIFT', + 'CP_CPC_DSM_CNTL__CPC8_DSM_IRRITATOR_DATA_MASK', + 'CP_CPC_DSM_CNTL__CPC8_DSM_IRRITATOR_DATA__SHIFT', + 'CP_CPC_DSM_CNTL__CPC8_ENABLE_SINGLE_WRITE_MASK', + 'CP_CPC_DSM_CNTL__CPC8_ENABLE_SINGLE_WRITE__SHIFT', + 'CP_CPC_GFX_CNTL__MEID_MASK', 'CP_CPC_GFX_CNTL__MEID__SHIFT', + 'CP_CPC_GFX_CNTL__PIPEID_MASK', 'CP_CPC_GFX_CNTL__PIPEID__SHIFT', + 'CP_CPC_GFX_CNTL__QUEUEID_MASK', + 'CP_CPC_GFX_CNTL__QUEUEID__SHIFT', 'CP_CPC_GFX_CNTL__VALID_MASK', + 'CP_CPC_GFX_CNTL__VALID__SHIFT', + 'CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK', + 'CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT', + 'CP_CPC_HALT_HYST_COUNT__COUNT_MASK', + 'CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT', + 'CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK', + 'CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT', + 'CP_CPC_IC_BASE_CNTL__VMID_MASK', + 'CP_CPC_IC_BASE_CNTL__VMID__SHIFT', + 'CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK', + 'CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT', + 'CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK', + 'CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT', + 'CP_CPC_IC_OP_CNTL__ICACHE_INVALIDATED_MASK', + 'CP_CPC_IC_OP_CNTL__ICACHE_INVALIDATED__SHIFT', + 'CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK', + 'CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT', + 'CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK', + 'CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT', + 'CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK', + 'CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT', + 'CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK', + 'CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT', + 'CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK', + 'CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT', + 'CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK', + 'CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT', + 'CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_APERTURE_ID_MASK', + 'CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_APERTURE_ID__SHIFT', + 'CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_OP_MASK', + 'CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_OP__SHIFT', + 'CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_STATUS_MASK', + 'CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_STATUS__SHIFT', + 'CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK', + 'CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT', + 'CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK', + 'CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT', + 'CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK', + 'CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT', + 'CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK', + 'CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK', + 'CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT', + 'CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT', + 'CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK', + 'CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT', + 'CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK', + 'CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT', + 'CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK', + 'CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK', + 'CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT', + 'CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT', + 'CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK', + 'CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT', + 'CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK', + 'CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT', + 'CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK', + 'CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT', + 'CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK', + 'CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT', + 'CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK', + 'CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT', + 'CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK', + 'CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT', + 'CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK', + 'CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT', + 'CP_CPC_STATUS__CPC_BUSY_MASK', 'CP_CPC_STATUS__CPC_BUSY__SHIFT', + 'CP_CPC_STATUS__CPF_CPC_BUSY_MASK', + 'CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT', + 'CP_CPC_STATUS__CPG_CPC_BUSY_MASK', + 'CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT', + 'CP_CPC_STATUS__DC0_BUSY_MASK', 'CP_CPC_STATUS__DC0_BUSY__SHIFT', + 'CP_CPC_STATUS__DC1_BUSY_MASK', 'CP_CPC_STATUS__DC1_BUSY__SHIFT', + 'CP_CPC_STATUS__MEC1_BUSY_MASK', + 'CP_CPC_STATUS__MEC1_BUSY__SHIFT', + 'CP_CPC_STATUS__MEC2_BUSY_MASK', + 'CP_CPC_STATUS__MEC2_BUSY__SHIFT', 'CP_CPC_STATUS__QU_BUSY_MASK', + 'CP_CPC_STATUS__QU_BUSY__SHIFT', 'CP_CPC_STATUS__RCIU1_BUSY_MASK', + 'CP_CPC_STATUS__RCIU1_BUSY__SHIFT', + 'CP_CPC_STATUS__RCIU2_BUSY_MASK', + 'CP_CPC_STATUS__RCIU2_BUSY__SHIFT', + 'CP_CPC_STATUS__ROQ1_BUSY_MASK', + 'CP_CPC_STATUS__ROQ1_BUSY__SHIFT', + 'CP_CPC_STATUS__ROQ2_BUSY_MASK', + 'CP_CPC_STATUS__ROQ2_BUSY__SHIFT', + 'CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK', + 'CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT', + 'CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK', + 'CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT', + 'CP_CPC_STATUS__TCIU_BUSY_MASK', + 'CP_CPC_STATUS__TCIU_BUSY__SHIFT', + 'CP_CPC_STATUS__UTCL2IU_BUSY_MASK', + 'CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK', + 'CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK', + 'CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK', + 'CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK', + 'CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK', + 'CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK', + 'CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK', + 'CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK', + 'CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK', + 'CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT', + 'CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK', + 'CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT', + 'CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK', + 'CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT', + 'CP_CPF_DEBUG_CNTL__DEBUG_BUS_FLOP_EN_MASK', + 'CP_CPF_DEBUG_CNTL__DEBUG_BUS_FLOP_EN__SHIFT', + 'CP_CPF_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS_MASK', + 'CP_CPF_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS__SHIFT', + 'CP_CPF_DEBUG_CNTL__DEBUG_INDX_MASK', + 'CP_CPF_DEBUG_CNTL__DEBUG_INDX__SHIFT', + 'CP_CPF_DEBUG__BUSY_EXTENDER_MASK', + 'CP_CPF_DEBUG__BUSY_EXTENDER__SHIFT', + 'CP_CPF_DEBUG__CPF_PRIORITY_YIELD_ACTIVE_DIS_MASK', + 'CP_CPF_DEBUG__CPF_PRIORITY_YIELD_ACTIVE_DIS__SHIFT', + 'CP_CPF_DEBUG__CPF_RAM_CLK_GATING_DISABLE_MASK', + 'CP_CPF_DEBUG__CPF_RAM_CLK_GATING_DISABLE__SHIFT', + 'CP_CPF_DEBUG__CPF_REPEATER_FGCG_OVERRIDE_MASK', + 'CP_CPF_DEBUG__CPF_REPEATER_FGCG_OVERRIDE__SHIFT', + 'CP_CPF_DEBUG__CPF_TC_MTYPE_OVERRIDE_MASK', + 'CP_CPF_DEBUG__CPF_TC_MTYPE_OVERRIDE__SHIFT', + 'CP_CPF_DEBUG__DBGU_TRIGGER_MASK', + 'CP_CPF_DEBUG__DBGU_TRIGGER__SHIFT', + 'CP_CPF_DEBUG__OVERFLOW_BUSY_DISABLE_MASK', + 'CP_CPF_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT', + 'CP_CPF_DEBUG__QUE_MANAGER_CLR_DBELLUPD_DIS_MASK', + 'CP_CPF_DEBUG__QUE_MANAGER_CLR_DBELLUPD_DIS__SHIFT', + 'CP_CPF_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK', + 'CP_CPF_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT', + 'CP_CPF_DSM_CNTL2A__CPF_INJECT_DELAY_MASK', + 'CP_CPF_DSM_CNTL2A__CPF_INJECT_DELAY__SHIFT', + 'CP_CPF_DSM_CNTL2__CPF0_ENABLE_ERROR_INJECT_MASK', + 'CP_CPF_DSM_CNTL2__CPF0_ENABLE_ERROR_INJECT__SHIFT', + 'CP_CPF_DSM_CNTL2__CPF0_SELECT_INJECT_DELAY_MASK', + 'CP_CPF_DSM_CNTL2__CPF0_SELECT_INJECT_DELAY__SHIFT', + 'CP_CPF_DSM_CNTL2__CPF1_ENABLE_ERROR_INJECT_MASK', + 'CP_CPF_DSM_CNTL2__CPF1_ENABLE_ERROR_INJECT__SHIFT', + 'CP_CPF_DSM_CNTL2__CPF1_SELECT_INJECT_DELAY_MASK', + 'CP_CPF_DSM_CNTL2__CPF1_SELECT_INJECT_DELAY__SHIFT', + 'CP_CPF_DSM_CNTL2__CPF2_ENABLE_ERROR_INJECT_MASK', + 'CP_CPF_DSM_CNTL2__CPF2_ENABLE_ERROR_INJECT__SHIFT', + 'CP_CPF_DSM_CNTL2__CPF2_SELECT_INJECT_DELAY_MASK', + 'CP_CPF_DSM_CNTL2__CPF2_SELECT_INJECT_DELAY__SHIFT', + 'CP_CPF_DSM_CNTL__CPF0_DSM_IRRITATOR_DATA_MASK', + 'CP_CPF_DSM_CNTL__CPF0_DSM_IRRITATOR_DATA__SHIFT', + 'CP_CPF_DSM_CNTL__CPF0_ENABLE_SINGLE_WRITE_MASK', + 'CP_CPF_DSM_CNTL__CPF0_ENABLE_SINGLE_WRITE__SHIFT', + 'CP_CPF_DSM_CNTL__CPF1_DSM_IRRITATOR_DATA_MASK', + 'CP_CPF_DSM_CNTL__CPF1_DSM_IRRITATOR_DATA__SHIFT', + 'CP_CPF_DSM_CNTL__CPF1_ENABLE_SINGLE_WRITE_MASK', + 'CP_CPF_DSM_CNTL__CPF1_ENABLE_SINGLE_WRITE__SHIFT', + 'CP_CPF_DSM_CNTL__CPF2_DSM_IRRITATOR_DATA_MASK', + 'CP_CPF_DSM_CNTL__CPF2_DSM_IRRITATOR_DATA__SHIFT', + 'CP_CPF_DSM_CNTL__CPF2_ENABLE_SINGLE_WRITE_MASK', + 'CP_CPF_DSM_CNTL__CPF2_ENABLE_SINGLE_WRITE__SHIFT', + 'CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK', + 'CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT', + 'CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK', + 'CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT', + 'CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK', + 'CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT', + 'CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK', + 'CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT', + 'CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK', + 'CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT', + 'CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK', + 'CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT', + 'CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK', + 'CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT', + 'CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK', + 'CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT', + 'CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK', + 'CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT', + 'CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK', + 'CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT', + 'CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK', + 'CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT', + 'CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK', + 'CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT', + 'CP_CPF_STATUS__CPC_CPF_BUSY_MASK', + 'CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT', + 'CP_CPF_STATUS__CPF_BUSY_MASK', 'CP_CPF_STATUS__CPF_BUSY__SHIFT', + 'CP_CPF_STATUS__CPF_CMP_BUSY_MASK', + 'CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT', + 'CP_CPF_STATUS__CPF_GFX_BUSY_MASK', + 'CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT', + 'CP_CPF_STATUS__CSF_BUSY_MASK', 'CP_CPF_STATUS__CSF_BUSY__SHIFT', + 'CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK', + 'CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT', + 'CP_CPF_STATUS__HQD_BUSY_MASK', 'CP_CPF_STATUS__HQD_BUSY__SHIFT', + 'CP_CPF_STATUS__INTERRUPT_BUSY_MASK', + 'CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT', + 'CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK', + 'CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT', + 'CP_CPF_STATUS__PRT_BUSY_MASK', 'CP_CPF_STATUS__PRT_BUSY__SHIFT', + 'CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK', + 'CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT', + 'CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK', + 'CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT', + 'CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK', + 'CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT', + 'CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK', + 'CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT', + 'CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK', + 'CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT', + 'CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK', + 'CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT', + 'CP_CPF_STATUS__ROQ_RING_BUSY_MASK', + 'CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT', + 'CP_CPF_STATUS__ROQ_STATE_BUSY_MASK', + 'CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT', + 'CP_CPF_STATUS__SEMAPHORE_BUSY_MASK', + 'CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT', + 'CP_CPF_STATUS__TCIU_BUSY_MASK', + 'CP_CPF_STATUS__TCIU_BUSY__SHIFT', + 'CP_CPF_STATUS__UTCL2IU_BUSY_MASK', + 'CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT', + 'CP_CPG_DSM_CNTL2A__CPG_INJECT_DELAY_MASK', + 'CP_CPG_DSM_CNTL2A__CPG_INJECT_DELAY__SHIFT', + 'CP_CPG_DSM_CNTL2__CPG0_ENABLE_ERROR_INJECT_MASK', + 'CP_CPG_DSM_CNTL2__CPG0_ENABLE_ERROR_INJECT__SHIFT', + 'CP_CPG_DSM_CNTL2__CPG0_SELECT_INJECT_DELAY_MASK', + 'CP_CPG_DSM_CNTL2__CPG0_SELECT_INJECT_DELAY__SHIFT', + 'CP_CPG_DSM_CNTL2__CPG1_ENABLE_ERROR_INJECT_MASK', + 'CP_CPG_DSM_CNTL2__CPG1_ENABLE_ERROR_INJECT__SHIFT', + 'CP_CPG_DSM_CNTL2__CPG1_SELECT_INJECT_DELAY_MASK', + 'CP_CPG_DSM_CNTL2__CPG1_SELECT_INJECT_DELAY__SHIFT', + 'CP_CPG_DSM_CNTL2__CPG2_ENABLE_ERROR_INJECT_MASK', + 'CP_CPG_DSM_CNTL2__CPG2_ENABLE_ERROR_INJECT__SHIFT', + 'CP_CPG_DSM_CNTL2__CPG2_SELECT_INJECT_DELAY_MASK', + 'CP_CPG_DSM_CNTL2__CPG2_SELECT_INJECT_DELAY__SHIFT', + 'CP_CPG_DSM_CNTL__CPG0_DSM_IRRITATOR_DATA_MASK', + 'CP_CPG_DSM_CNTL__CPG0_DSM_IRRITATOR_DATA__SHIFT', + 'CP_CPG_DSM_CNTL__CPG0_ENABLE_SINGLE_WRITE_MASK', + 'CP_CPG_DSM_CNTL__CPG0_ENABLE_SINGLE_WRITE__SHIFT', + 'CP_CPG_DSM_CNTL__CPG1_DSM_IRRITATOR_DATA_MASK', + 'CP_CPG_DSM_CNTL__CPG1_DSM_IRRITATOR_DATA__SHIFT', + 'CP_CPG_DSM_CNTL__CPG1_ENABLE_SINGLE_WRITE_MASK', + 'CP_CPG_DSM_CNTL__CPG1_ENABLE_SINGLE_WRITE__SHIFT', + 'CP_CPG_DSM_CNTL__CPG2_DSM_IRRITATOR_DATA_MASK', + 'CP_CPG_DSM_CNTL__CPG2_DSM_IRRITATOR_DATA__SHIFT', + 'CP_CPG_DSM_CNTL__CPG2_ENABLE_SINGLE_WRITE_MASK', + 'CP_CPG_DSM_CNTL__CPG2_ENABLE_SINGLE_WRITE__SHIFT', + 'CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK', + 'CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT', + 'CP_DEBUG_CNTL__DEBUG_BUS_FLOP_EN_MASK', + 'CP_DEBUG_CNTL__DEBUG_BUS_FLOP_EN__SHIFT', + 'CP_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS_MASK', + 'CP_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS__SHIFT', + 'CP_DEBUG_CNTL__DEBUG_INDX_MASK', + 'CP_DEBUG_CNTL__DEBUG_INDX__SHIFT', + 'CP_DEBUG__BUSY_EXTENDER_MASK', 'CP_DEBUG__BUSY_EXTENDER__SHIFT', + 'CP_DEBUG__CPG_RAM_CLK_GATING_DISABLE_MASK', + 'CP_DEBUG__CPG_RAM_CLK_GATING_DISABLE__SHIFT', + 'CP_DEBUG__CPG_REPEATER_FGCG_OVERRIDE_MASK', + 'CP_DEBUG__CPG_REPEATER_FGCG_OVERRIDE__SHIFT', + 'CP_DEBUG__CPG_TC_MTYPE_OVERRIDE_MASK', + 'CP_DEBUG__CPG_TC_MTYPE_OVERRIDE__SHIFT', + 'CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE_MASK', + 'CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT', + 'CP_DEBUG__CS_PIPELINE_RESET_DISABLE_MASK', + 'CP_DEBUG__CS_PIPELINE_RESET_DISABLE__SHIFT', + 'CP_DEBUG__CS_STATE_FILT_DISABLE_MASK', + 'CP_DEBUG__CS_STATE_FILT_DISABLE__SHIFT', + 'CP_DEBUG__DISABLE_GFX_HALT_ON_UTCL1_ERROR_MASK', + 'CP_DEBUG__DISABLE_GFX_HALT_ON_UTCL1_ERROR__SHIFT', + 'CP_DEBUG__EVENT_FILT_DISABLE_MASK', + 'CP_DEBUG__EVENT_FILT_DISABLE__SHIFT', + 'CP_DEBUG__IB_PACKET_INJECTOR_DISABLE_MASK', + 'CP_DEBUG__IB_PACKET_INJECTOR_DISABLE__SHIFT', + 'CP_DEBUG__INTERRUPT_ENABLE_MASK', + 'CP_DEBUG__INTERRUPT_ENABLE__SHIFT', + 'CP_DEBUG__OVERFLOW_BUSY_DISABLE_MASK', + 'CP_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT', + 'CP_DEBUG__PREDICATE_DISABLE_MASK', + 'CP_DEBUG__PREDICATE_DISABLE__SHIFT', + 'CP_DEBUG__PRIV_REG_INTERRUPT_ENABLE_MASK', + 'CP_DEBUG__PRIV_REG_INTERRUPT_ENABLE__SHIFT', + 'CP_DEBUG__SURFSYNC_CNTX_RDADDR_MASK', + 'CP_DEBUG__SURFSYNC_CNTX_RDADDR__SHIFT', + 'CP_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK', + 'CP_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT', + 'CP_DEVICE_ID__DEVICE_ID_MASK', 'CP_DEVICE_ID__DEVICE_ID__SHIFT', + 'CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK', + 'CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT', + 'CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK', + 'CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT', + 'CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK', + 'CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT', + 'CP_DFY_ADDR_HI__ADDR_HI_MASK', 'CP_DFY_ADDR_HI__ADDR_HI__SHIFT', + 'CP_DFY_ADDR_LO__ADDR_LO_MASK', 'CP_DFY_ADDR_LO__ADDR_LO__SHIFT', + 'CP_DFY_CMD__OFFSET_MASK', 'CP_DFY_CMD__OFFSET__SHIFT', + 'CP_DFY_CMD__SIZE_MASK', 'CP_DFY_CMD__SIZE__SHIFT', + 'CP_DFY_CNTL__ENABLE_MASK', 'CP_DFY_CNTL__ENABLE__SHIFT', + 'CP_DFY_CNTL__LFSR_RESET_MASK', 'CP_DFY_CNTL__LFSR_RESET__SHIFT', + 'CP_DFY_CNTL__MODE_MASK', 'CP_DFY_CNTL__MODE__SHIFT', + 'CP_DFY_CNTL__MTYPE_MASK', 'CP_DFY_CNTL__MTYPE__SHIFT', + 'CP_DFY_CNTL__POLICY_MASK', 'CP_DFY_CNTL__POLICY__SHIFT', + 'CP_DFY_CNTL__WRITE_DIS_MASK', 'CP_DFY_CNTL__WRITE_DIS__SHIFT', + 'CP_DFY_DATA_0__DATA_MASK', 'CP_DFY_DATA_0__DATA__SHIFT', + 'CP_DFY_DATA_10__DATA_MASK', 'CP_DFY_DATA_10__DATA__SHIFT', + 'CP_DFY_DATA_11__DATA_MASK', 'CP_DFY_DATA_11__DATA__SHIFT', + 'CP_DFY_DATA_12__DATA_MASK', 'CP_DFY_DATA_12__DATA__SHIFT', + 'CP_DFY_DATA_13__DATA_MASK', 'CP_DFY_DATA_13__DATA__SHIFT', + 'CP_DFY_DATA_14__DATA_MASK', 'CP_DFY_DATA_14__DATA__SHIFT', + 'CP_DFY_DATA_15__DATA_MASK', 'CP_DFY_DATA_15__DATA__SHIFT', + 'CP_DFY_DATA_1__DATA_MASK', 'CP_DFY_DATA_1__DATA__SHIFT', + 'CP_DFY_DATA_2__DATA_MASK', 'CP_DFY_DATA_2__DATA__SHIFT', + 'CP_DFY_DATA_3__DATA_MASK', 'CP_DFY_DATA_3__DATA__SHIFT', + 'CP_DFY_DATA_4__DATA_MASK', 'CP_DFY_DATA_4__DATA__SHIFT', + 'CP_DFY_DATA_5__DATA_MASK', 'CP_DFY_DATA_5__DATA__SHIFT', + 'CP_DFY_DATA_6__DATA_MASK', 'CP_DFY_DATA_6__DATA__SHIFT', + 'CP_DFY_DATA_7__DATA_MASK', 'CP_DFY_DATA_7__DATA__SHIFT', + 'CP_DFY_DATA_8__DATA_MASK', 'CP_DFY_DATA_8__DATA__SHIFT', + 'CP_DFY_DATA_9__DATA_MASK', 'CP_DFY_DATA_9__DATA__SHIFT', + 'CP_DFY_STAT__BURST_COUNT_MASK', + 'CP_DFY_STAT__BURST_COUNT__SHIFT', 'CP_DFY_STAT__BUSY_MASK', + 'CP_DFY_STAT__BUSY__SHIFT', 'CP_DFY_STAT__TAGS_PENDING_MASK', + 'CP_DFY_STAT__TAGS_PENDING__SHIFT', + 'CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK', + 'CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT', + 'CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK', + 'CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT', + 'CP_DMA_CNTL__BUFFER_DEPTH_MASK', + 'CP_DMA_CNTL__BUFFER_DEPTH__SHIFT', + 'CP_DMA_CNTL__MIN_AVAILSZ_MASK', + 'CP_DMA_CNTL__MIN_AVAILSZ__SHIFT', 'CP_DMA_CNTL__PIO_COUNT_MASK', + 'CP_DMA_CNTL__PIO_COUNT__SHIFT', + 'CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK', + 'CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT', + 'CP_DMA_CNTL__PIO_FIFO_FULL_MASK', + 'CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT', + 'CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK', + 'CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT', + 'CP_DMA_ME_COMMAND__BYTE_COUNT_MASK', + 'CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT', + 'CP_DMA_ME_COMMAND__DAIC_MASK', 'CP_DMA_ME_COMMAND__DAIC__SHIFT', + 'CP_DMA_ME_COMMAND__DAS_MASK', 'CP_DMA_ME_COMMAND__DAS__SHIFT', + 'CP_DMA_ME_COMMAND__DIS_WC_MASK', + 'CP_DMA_ME_COMMAND__DIS_WC__SHIFT', + 'CP_DMA_ME_COMMAND__RAW_WAIT_MASK', + 'CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT', + 'CP_DMA_ME_COMMAND__SAIC_MASK', 'CP_DMA_ME_COMMAND__SAIC__SHIFT', + 'CP_DMA_ME_COMMAND__SAS_MASK', 'CP_DMA_ME_COMMAND__SAS__SHIFT', + 'CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK', + 'CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT', + 'CP_DMA_ME_CONTROL__DST_SELECT_MASK', + 'CP_DMA_ME_CONTROL__DST_SELECT__SHIFT', + 'CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK', + 'CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT', + 'CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK', + 'CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT', + 'CP_DMA_ME_CONTROL__SRC_SELECT_MASK', + 'CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT', + 'CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK', + 'CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT', + 'CP_DMA_ME_DST_ADDR__DST_ADDR_MASK', + 'CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT', + 'CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK', + 'CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT', + 'CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK', + 'CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT', + 'CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK', + 'CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT', + 'CP_DMA_PFP_COMMAND__DAIC_MASK', + 'CP_DMA_PFP_COMMAND__DAIC__SHIFT', 'CP_DMA_PFP_COMMAND__DAS_MASK', + 'CP_DMA_PFP_COMMAND__DAS__SHIFT', + 'CP_DMA_PFP_COMMAND__DIS_WC_MASK', + 'CP_DMA_PFP_COMMAND__DIS_WC__SHIFT', + 'CP_DMA_PFP_COMMAND__RAW_WAIT_MASK', + 'CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT', + 'CP_DMA_PFP_COMMAND__SAIC_MASK', + 'CP_DMA_PFP_COMMAND__SAIC__SHIFT', 'CP_DMA_PFP_COMMAND__SAS_MASK', + 'CP_DMA_PFP_COMMAND__SAS__SHIFT', + 'CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK', + 'CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT', + 'CP_DMA_PFP_CONTROL__DST_SELECT_MASK', + 'CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT', + 'CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK', + 'CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT', + 'CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK', + 'CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT', + 'CP_DMA_PFP_CONTROL__SRC_SELECT_MASK', + 'CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT', + 'CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK', + 'CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT', + 'CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK', + 'CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT', + 'CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK', + 'CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT', + 'CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK', + 'CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT', + 'CP_DMA_READ_TAGS__DMA_READ_TAG_MASK', + 'CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK', + 'CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT', + 'CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT', + 'CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK', + 'CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT', + 'CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK', + 'CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT', + 'CP_DRAW_OBJECT_COUNTER__COUNT_MASK', + 'CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT', + 'CP_DRAW_OBJECT__OBJECT_MASK', 'CP_DRAW_OBJECT__OBJECT__SHIFT', + 'CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK', + 'CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT', + 'CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK', + 'CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT', + 'CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK', + 'CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT', + 'CP_DRAW_WINDOW_CNTL__MODE_MASK', + 'CP_DRAW_WINDOW_CNTL__MODE__SHIFT', + 'CP_DRAW_WINDOW_HI__WINDOW_HI_MASK', + 'CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT', + 'CP_DRAW_WINDOW_LO__MAX_MASK', 'CP_DRAW_WINDOW_LO__MAX__SHIFT', + 'CP_DRAW_WINDOW_LO__MIN_MASK', 'CP_DRAW_WINDOW_LO__MIN__SHIFT', + 'CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK', + 'CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT', + 'CP_ECC_DMA_FIRST_OCCURRENCE__CLIENT_MASK', + 'CP_ECC_DMA_FIRST_OCCURRENCE__CLIENT__SHIFT', + 'CP_ECC_DMA_FIRST_OCCURRENCE__INTERFACE_MASK', + 'CP_ECC_DMA_FIRST_OCCURRENCE__INTERFACE__SHIFT', + 'CP_ECC_DMA_FIRST_OCCURRENCE__ME_MASK', + 'CP_ECC_DMA_FIRST_OCCURRENCE__ME__SHIFT', + 'CP_ECC_DMA_FIRST_OCCURRENCE__PIPE_MASK', + 'CP_ECC_DMA_FIRST_OCCURRENCE__PIPE__SHIFT', + 'CP_ECC_DMA_FIRST_OCCURRENCE__VMID_MASK', + 'CP_ECC_DMA_FIRST_OCCURRENCE__VMID__SHIFT', + 'CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK', + 'CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT', + 'CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK', + 'CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT', + 'CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK', + 'CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT', + 'CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK', + 'CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT', + 'CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK', + 'CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT', + 'CP_ECC_FIRSTOCCURRENCE__ME_MASK', + 'CP_ECC_FIRSTOCCURRENCE__ME__SHIFT', + 'CP_ECC_FIRSTOCCURRENCE__PIPE_MASK', + 'CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT', + 'CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK', + 'CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT', + 'CP_ECC_FIRSTOCCURRENCE__VMID_MASK', + 'CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT', + 'CP_EDC_FUE_CNTL__CP_FUE_FLAG_MASK', + 'CP_EDC_FUE_CNTL__CP_FUE_FLAG__SHIFT', + 'CP_EDC_FUE_CNTL__CP_FUE_MASK_MASK', + 'CP_EDC_FUE_CNTL__CP_FUE_MASK__SHIFT', + 'CP_EDC_FUE_CNTL__GDS_FUE_FLAG_MASK', + 'CP_EDC_FUE_CNTL__GDS_FUE_FLAG__SHIFT', + 'CP_EDC_FUE_CNTL__GDS_FUE_MASK_MASK', + 'CP_EDC_FUE_CNTL__GDS_FUE_MASK__SHIFT', + 'CP_EDC_FUE_CNTL__SPI_FUE_FLAG_MASK', + 'CP_EDC_FUE_CNTL__SPI_FUE_FLAG__SHIFT', + 'CP_EDC_FUE_CNTL__SPI_FUE_MASK_MASK', + 'CP_EDC_FUE_CNTL__SPI_FUE_MASK__SHIFT', + 'CP_EDC_FUE_CNTL__TCA_FUE_FLAG_MASK', + 'CP_EDC_FUE_CNTL__TCA_FUE_FLAG__SHIFT', + 'CP_EDC_FUE_CNTL__TCA_FUE_MASK_MASK', + 'CP_EDC_FUE_CNTL__TCA_FUE_MASK__SHIFT', + 'CP_EDC_FUE_CNTL__TCC_FUE_FLAG_MASK', + 'CP_EDC_FUE_CNTL__TCC_FUE_FLAG__SHIFT', + 'CP_EDC_FUE_CNTL__TCC_FUE_MASK_MASK', + 'CP_EDC_FUE_CNTL__TCC_FUE_MASK__SHIFT', + 'CP_EDC_FUE_CNTL__TC_CPG_FUE_FLAG_MASK', + 'CP_EDC_FUE_CNTL__TC_CPG_FUE_FLAG__SHIFT', + 'CP_EDC_FUE_CNTL__TC_CPG_FUE_MASK_MASK', + 'CP_EDC_FUE_CNTL__TC_CPG_FUE_MASK__SHIFT', + 'CP_EDC_FUE_CNTL__TC_RLC_FUE_FLAG_MASK', + 'CP_EDC_FUE_CNTL__TC_RLC_FUE_FLAG__SHIFT', + 'CP_EDC_FUE_CNTL__TC_RLC_FUE_MASK_MASK', + 'CP_EDC_FUE_CNTL__TC_RLC_FUE_MASK__SHIFT', + 'CP_EDC_FUE_CNTL__UTCL2_FUE_FLAG_MASK', + 'CP_EDC_FUE_CNTL__UTCL2_FUE_FLAG__SHIFT', + 'CP_EDC_FUE_CNTL__UTCL2_FUE_MASK_MASK', + 'CP_EDC_FUE_CNTL__UTCL2_FUE_MASK__SHIFT', + 'CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK', + 'CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT', + 'CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK', + 'CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT', + 'CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK', + 'CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT', + 'CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK', + 'CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT', + 'CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK', + 'CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT', + 'CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK', + 'CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT', + 'CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK', + 'CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT', + 'CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK', + 'CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT', + 'CP_EOP_DONE_DATA_HI__DATA_HI_MASK', + 'CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT', + 'CP_EOP_DONE_DATA_LO__DATA_LO_MASK', + 'CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT', + 'CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK', + 'CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT', + 'CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK', + 'CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT', + 'CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK', + 'CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT', + 'CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK', + 'CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT', + 'CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK', + 'CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT', + 'CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK', + 'CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT', + 'CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK', + 'CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT', + 'CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK', + 'CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT', + 'CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK', + 'CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT', + 'CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK', + 'CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT', + 'CP_FATAL_ERROR__GFX_HALT_PROC_MASK', + 'CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT', + 'CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK', + 'CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT', + 'CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK', + 'CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT', + 'CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK', + 'CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT', + 'CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK', + 'CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT', + 'CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK', + 'CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT', + 'CP_GDS_BKUP_ADDR__ADDR_LO_MASK', + 'CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT', + 'CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__EDC_ERROR_ID_MASK', + 'CP_GFX_ERROR__EDC_ERROR_ID__SHIFT', + 'CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__RSVD1_ERROR_MASK', + 'CP_GFX_ERROR__RSVD1_ERROR__SHIFT', + 'CP_GFX_ERROR__RSVD2_ERROR_MASK', + 'CP_GFX_ERROR__RSVD2_ERROR__SHIFT', + 'CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__SUA_ERROR_MASK', 'CP_GFX_ERROR__SUA_ERROR__SHIFT', + 'CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT', + 'CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK', + 'CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT', + 'CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK', + 'CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT', + 'CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK', + 'CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT', + 'CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK', + 'CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT', + 'CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK', + 'CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT', + 'CP_GFX_MQD_CONTROL__PRIV_STATE_MASK', + 'CP_GFX_MQD_CONTROL__PRIV_STATE__SHIFT', + 'CP_GFX_MQD_CONTROL__VMID_MASK', + 'CP_GFX_MQD_CONTROL__VMID__SHIFT', + 'CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK', + 'CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT', + 'CP_GRBM_FREE_COUNT__FREE_COUNT_MASK', + 'CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK', + 'CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT', + 'CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT', + 'CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK', + 'CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT', + 'CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK', + 'CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT', + 'CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK', + 'CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT', + 'CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK_MASK', + 'CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK__SHIFT', + 'CP_HPD_STATUS0__FETCHING_MQD_MASK', + 'CP_HPD_STATUS0__FETCHING_MQD__SHIFT', + 'CP_HPD_STATUS0__FORCE_QUEUE_MASK', + 'CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK', + 'CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT', + 'CP_HPD_STATUS0__FORCE_QUEUE__SHIFT', + 'CP_HPD_STATUS0__MAPPED_QUEUE_MASK', + 'CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT', + 'CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK', + 'CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT', + 'CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK', + 'CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT', + 'CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK', + 'CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT', + 'CP_HPD_STATUS0__QUEUE_STATE_MASK', + 'CP_HPD_STATUS0__QUEUE_STATE__SHIFT', + 'CP_HPD_UTCL1_CNTL__SELECT_MASK', + 'CP_HPD_UTCL1_CNTL__SELECT__SHIFT', + 'CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK', + 'CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT', + 'CP_HPD_UTCL1_ERROR__ADDR_HI_MASK', + 'CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT', + 'CP_HPD_UTCL1_ERROR__TYPE_MASK', + 'CP_HPD_UTCL1_ERROR__TYPE__SHIFT', + 'CP_HPD_UTCL1_ERROR__VMID_MASK', + 'CP_HPD_UTCL1_ERROR__VMID__SHIFT', 'CP_HQD_ACTIVE__ACTIVE_MASK', + 'CP_HQD_ACTIVE__ACTIVE__SHIFT', 'CP_HQD_ACTIVE__BUSY_GATE_MASK', + 'CP_HQD_ACTIVE__BUSY_GATE__SHIFT', + 'CP_HQD_AQL_CONTROL_1__RESERVED_MASK', + 'CP_HQD_AQL_CONTROL_1__RESERVED__SHIFT', + 'CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK', + 'CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT', + 'CP_HQD_AQL_CONTROL__CONTROL0_MASK', + 'CP_HQD_AQL_CONTROL__CONTROL0__SHIFT', + 'CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK', + 'CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT', + 'CP_HQD_AQL_CONTROL__CONTROL1_MASK', + 'CP_HQD_AQL_CONTROL__CONTROL1__SHIFT', + 'CP_HQD_AQL_DISPATCH_ID_HI__CONSUMED_OFFSET_MASK', + 'CP_HQD_AQL_DISPATCH_ID_HI__CONSUMED_OFFSET__SHIFT', + 'CP_HQD_AQL_DISPATCH_ID__CONSUMED_OFFSET_MASK', + 'CP_HQD_AQL_DISPATCH_ID__CONSUMED_OFFSET__SHIFT', + 'CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK', + 'CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT', + 'CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK', + 'CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT', + 'CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK', + 'CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT', + 'CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK', + 'CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT', + 'CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK', + 'CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT', + 'CP_HQD_CNTL_STACK_SIZE__SIZE_MASK', + 'CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT', + 'CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK', + 'CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT', + 'CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK', + 'CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT', + 'CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK', + 'CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT', + 'CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK', + 'CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT', + 'CP_HQD_CTX_SAVE_SIZE__SIZE_MASK', + 'CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT', + 'CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK', + 'CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT', + 'CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK', + 'CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT', + 'CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK', + 'CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT', + 'CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK', + 'CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT', + 'CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK', + 'CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT', + 'CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK', + 'CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT', + 'CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK', + 'CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT', + 'CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK', + 'CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT', + 'CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK', + 'CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT', + 'CP_HQD_EOP_CONTROL__EOP_SIZE_MASK', + 'CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT', + 'CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK', + 'CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT', + 'CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK', + 'CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT', + 'CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK', + 'CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT', + 'CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK', + 'CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT', + 'CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK', + 'CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT', + 'CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK', + 'CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT', + 'CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK', + 'CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT', + 'CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK', + 'CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT', + 'CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK', + 'CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT', + 'CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK', + 'CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT', + 'CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK', + 'CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT', + 'CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK', + 'CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT', + 'CP_HQD_EOP_RPTR__INIT_FETCHER_MASK', + 'CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT', + 'CP_HQD_EOP_RPTR__RESET_FETCHER_MASK', + 'CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT', + 'CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK', + 'CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT', + 'CP_HQD_EOP_RPTR__RPTR_MASK', 'CP_HQD_EOP_RPTR__RPTR__SHIFT', + 'CP_HQD_EOP_WPTR_MEM__WPTR_MASK', + 'CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT', + 'CP_HQD_EOP_WPTR__EOP_AVAIL_MASK', + 'CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT', + 'CP_HQD_EOP_WPTR__EOP_EMPTY_MASK', + 'CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT', 'CP_HQD_EOP_WPTR__WPTR_MASK', + 'CP_HQD_EOP_WPTR__WPTR__SHIFT', 'CP_HQD_ERROR__AQL_ERROR_MASK', + 'CP_HQD_ERROR__AQL_ERROR__SHIFT', + 'CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__EDC_ERROR_ID_MASK', + 'CP_HQD_ERROR__EDC_ERROR_ID__SHIFT', + 'CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__IB_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__QU_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__SR_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__SUA_ERROR_MASK', 'CP_HQD_ERROR__SUA_ERROR__SHIFT', + 'CP_HQD_ERROR__TC_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT', + 'CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK', + 'CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT', + 'CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK', + 'CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT', + 'CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK', + 'CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT', + 'CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK', + 'CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT', + 'CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK', + 'CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT', + 'CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK', + 'CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT', + 'CP_HQD_GFX_CONTROL__MESSAGE_MASK', + 'CP_HQD_GFX_CONTROL__MESSAGE__SHIFT', + 'CP_HQD_GFX_CONTROL__MISC_MASK', + 'CP_HQD_GFX_CONTROL__MISC__SHIFT', + 'CP_HQD_GFX_STATUS__STATUS_MASK', + 'CP_HQD_GFX_STATUS__STATUS__SHIFT', + 'CP_HQD_HQ_CONTROL0__CONTROL_MASK', + 'CP_HQD_HQ_CONTROL0__CONTROL__SHIFT', + 'CP_HQD_HQ_CONTROL1__CONTROL_MASK', + 'CP_HQD_HQ_CONTROL1__CONTROL__SHIFT', + 'CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK', + 'CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT', + 'CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK', + 'CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT', + 'CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK', + 'CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT', + 'CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK', + 'CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT', + 'CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK', + 'CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT', + 'CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK', + 'CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT', + 'CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK', + 'CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT', + 'CP_HQD_HQ_STATUS0__RSVR_29_10_MASK', + 'CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT', + 'CP_HQD_HQ_STATUS0__RSV_6_4_MASK', + 'CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT', + 'CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK', + 'CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT', + 'CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK', + 'CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT', + 'CP_HQD_HQ_STATUS1__STATUS_MASK', + 'CP_HQD_HQ_STATUS1__STATUS__SHIFT', + 'CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK', + 'CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT', + 'CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK', + 'CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT', + 'CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK', + 'CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT', + 'CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK', + 'CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT', + 'CP_HQD_IB_CONTROL__IB_PRIV_STATE_MASK', + 'CP_HQD_IB_CONTROL__IB_PRIV_STATE__SHIFT', + 'CP_HQD_IB_CONTROL__IB_SIZE_MASK', + 'CP_HQD_IB_CONTROL__IB_SIZE__SHIFT', + 'CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK', + 'CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT', + 'CP_HQD_IB_CONTROL__PROCESSING_IB_MASK', + 'CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT', + 'CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK', + 'CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT', + 'CP_HQD_IQ_RPTR__OFFSET_MASK', 'CP_HQD_IQ_RPTR__OFFSET__SHIFT', + 'CP_HQD_IQ_TIMER__ACTIVE_MASK', 'CP_HQD_IQ_TIMER__ACTIVE__SHIFT', + 'CP_HQD_IQ_TIMER__CACHE_POLICY_MASK', + 'CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT', + 'CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK', + 'CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT', + 'CP_HQD_IQ_TIMER__EXE_DISABLE_MASK', + 'CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT', + 'CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK', + 'CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT', + 'CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK', + 'CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT', + 'CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK', + 'CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT', + 'CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK', + 'CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT', + 'CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK', + 'CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT', + 'CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK', + 'CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT', + 'CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK', + 'CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT', + 'CP_HQD_IQ_TIMER__REARM_TIMER_MASK', + 'CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT', + 'CP_HQD_IQ_TIMER__RETRY_TYPE_MASK', + 'CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT', + 'CP_HQD_IQ_TIMER__WAIT_TIME_MASK', + 'CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT', + 'CP_HQD_MSG_TYPE__ACTION_MASK', 'CP_HQD_MSG_TYPE__ACTION__SHIFT', + 'CP_HQD_MSG_TYPE__SAVE_STATE_MASK', + 'CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT', + 'CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK', + 'CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT', + 'CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK', + 'CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT', + 'CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK', + 'CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT', + 'CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK', + 'CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT', + 'CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK', + 'CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT', + 'CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK', + 'CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT', + 'CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK', + 'CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT', + 'CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK', + 'CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT', + 'CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK', + 'CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT', + 'CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK', + 'CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT', + 'CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK', + 'CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT', + 'CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK', + 'CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT', + 'CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK', + 'CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT', + 'CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK', + 'CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT', + 'CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK', + 'CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT', + 'CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK', + 'CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT', + 'CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK', + 'CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT', + 'CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK', + 'CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT', + 'CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK', + 'CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT', + 'CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK', + 'CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT', + 'CP_HQD_PQ_BASE_HI__ADDR_HI_MASK', + 'CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT', 'CP_HQD_PQ_BASE__ADDR_MASK', + 'CP_HQD_PQ_BASE__ADDR__SHIFT', + 'CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK', + 'CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT', + 'CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK', + 'CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT', + 'CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK', + 'CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT', + 'CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK', + 'CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT', + 'CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK', + 'CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT', + 'CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK', + 'CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT', + 'CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK', + 'CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT', + 'CP_HQD_PQ_CONTROL__PRIV_STATE_MASK', + 'CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT', + 'CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK', + 'CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT', + 'CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK', + 'CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT', + 'CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK', + 'CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT', + 'CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK', + 'CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT', + 'CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK', + 'CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT', + 'CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK', + 'CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT', + 'CP_HQD_PQ_CONTROL__TMZ_MASK', 'CP_HQD_PQ_CONTROL__TMZ__SHIFT', + 'CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK', + 'CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT', + 'CP_HQD_PQ_CONTROL__WPP_CLAMP_EN_MASK', + 'CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT', + 'CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK', + 'CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK', + 'CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT', + 'CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK', + 'CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT', + 'CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK', + 'CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT', + 'CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK', + 'CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT', + 'CP_HQD_PQ_WPTR_HI__DATA_MASK', 'CP_HQD_PQ_WPTR_HI__DATA__SHIFT', + 'CP_HQD_PQ_WPTR_LO__OFFSET_MASK', + 'CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT', + 'CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK', + 'CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT', + 'CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK', + 'CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT', + 'CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK', + 'CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT', + 'CP_HQD_QUANTUM__QUANTUM_DURATION_MASK', + 'CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT', + 'CP_HQD_QUANTUM__QUANTUM_EN_MASK', + 'CP_HQD_QUANTUM__QUANTUM_EN__SHIFT', + 'CP_HQD_QUANTUM__QUANTUM_SCALE_MASK', + 'CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT', + 'CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK', + 'CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT', + 'CP_HQD_SEMA_CMD__RESULT_MASK', 'CP_HQD_SEMA_CMD__RESULT__SHIFT', + 'CP_HQD_SEMA_CMD__RETRY_MASK', 'CP_HQD_SEMA_CMD__RETRY__SHIFT', + 'CP_HQD_VMID__IB_VMID_MASK', 'CP_HQD_VMID__IB_VMID__SHIFT', + 'CP_HQD_VMID__VMID_MASK', 'CP_HQD_VMID__VMID__SHIFT', + 'CP_HQD_VMID__VQID_MASK', 'CP_HQD_VMID__VQID__SHIFT', + 'CP_HQD_WG_STATE_OFFSET__OFFSET_MASK', + 'CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT', + 'CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK', + 'CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT', + 'CP_HYP_CE_UCODE_CHKSUM__UCODE_CHKSUM_MASK', + 'CP_HYP_CE_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT', + 'CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK', + 'CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT', + 'CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK', + 'CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT', + 'CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK', + 'CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT', + 'CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK', + 'CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT', + 'CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK', + 'CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT', + 'CP_HYP_MEC_ME1_UCODE_CHKSUM__UCODE_CHKSUM_MASK', + 'CP_HYP_MEC_ME1_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT', + 'CP_HYP_MEC_ME2_UCODE_CHKSUM__UCODE_CHKSUM_MASK', + 'CP_HYP_MEC_ME2_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT', + 'CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK', + 'CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT', + 'CP_HYP_ME_UCODE_CHKSUM__UCODE_CHKSUM_MASK', + 'CP_HYP_ME_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT', + 'CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK', + 'CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT', + 'CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK', + 'CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT', + 'CP_HYP_PFP_UCODE_CHKSUM__UCODE_CHKSUM_MASK', + 'CP_HYP_PFP_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT', + 'CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK', + 'CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT', + 'CP_HYP_XCP_CTL__NUM_XCC_IN_XCP_MASK', + 'CP_HYP_XCP_CTL__NUM_XCC_IN_XCP__SHIFT', + 'CP_HYP_XCP_CTL__VIRTUAL_XCC_ID_MASK', + 'CP_HYP_XCP_CTL__VIRTUAL_XCC_ID__SHIFT', + 'CP_IB1_BASE_HI__IB1_BASE_HI_MASK', + 'CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT', + 'CP_IB1_BASE_LO__IB1_BASE_LO_MASK', + 'CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT', + 'CP_IB1_BUFSZ__IB1_BUFSZ_MASK', 'CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT', + 'CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK', + 'CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT', + 'CP_IB1_OFFSET__IB1_OFFSET_MASK', + 'CP_IB1_OFFSET__IB1_OFFSET__SHIFT', + 'CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK', + 'CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT', + 'CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK', + 'CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT', + 'CP_IB2_BASE_HI__IB2_BASE_HI_MASK', + 'CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT', + 'CP_IB2_BASE_LO__IB2_BASE_LO_MASK', + 'CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT', + 'CP_IB2_BUFSZ__IB2_BUFSZ_MASK', 'CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT', + 'CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK', + 'CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT', + 'CP_IB2_OFFSET__IB2_OFFSET_MASK', + 'CP_IB2_OFFSET__IB2_OFFSET__SHIFT', + 'CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK', + 'CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT', + 'CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK', + 'CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT', + 'CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK', + 'CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT', + 'CP_INDEX_BASE_ADDR__ADDR_LO_MASK', + 'CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT', + 'CP_INDEX_TYPE__INDEX_TYPE_MASK', + 'CP_INDEX_TYPE__INDEX_TYPE__SHIFT', + 'CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK', + 'CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK', + 'CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK', + 'CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK', + 'CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK', + 'CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK', + 'CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK', + 'CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK', + 'CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__GPF_INT_ENABLE_MASK', + 'CP_INT_CNTL__GPF_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK', + 'CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK', + 'CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK', + 'CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__GPF_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK', + 'CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__GPF_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK', + 'CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK', + 'CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK', + 'CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK', + 'CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK', + 'CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK', + 'CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK', + 'CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK', + 'CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK', + 'CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK', + 'CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING2__GPF_INT_STAT_MASK', + 'CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK', + 'CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK', + 'CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK', + 'CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK', + 'CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK', + 'CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT', + 'CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK', + 'CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT', + 'CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK', + 'CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT', + 'CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK', + 'CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT', + 'CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK', + 'CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT', + 'CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK', + 'CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT', + 'CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK', + 'CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT', + 'CP_INT_STATUS__GENERIC0_INT_STAT_MASK', + 'CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT', + 'CP_INT_STATUS__GENERIC1_INT_STAT_MASK', + 'CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT', + 'CP_INT_STATUS__GENERIC2_INT_STAT_MASK', + 'CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT', + 'CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK', + 'CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT', + 'CP_INT_STATUS__GPF_INT_STAT_MASK', + 'CP_INT_STATUS__GPF_INT_STAT__SHIFT', + 'CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK', + 'CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT', + 'CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK', + 'CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT', + 'CP_INT_STATUS__PRIV_REG_INT_STAT_MASK', + 'CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT', + 'CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK', + 'CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT', + 'CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK', + 'CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT', + 'CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK', + 'CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT', + 'CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK', + 'CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT', + 'CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK', + 'CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT', + 'CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK', + 'CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT', + 'CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK', + 'CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT', + 'CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK', + 'CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT', + 'CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK', + 'CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT', + 'CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK', + 'CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT', + 'CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK', + 'CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT', + 'CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK', + 'CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT', + 'CP_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK', + 'CP_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT', + 'CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK', + 'CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT', + 'CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK', + 'CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT', + 'CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK', + 'CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT', + 'CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK', + 'CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT', + 'CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK', + 'CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT', + 'CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK', + 'CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT', + 'CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK', + 'CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT', + 'CP_IQ_WAIT_TIME1__GWS_MASK', 'CP_IQ_WAIT_TIME1__GWS__SHIFT', + 'CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK', + 'CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT', + 'CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK', + 'CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT', + 'CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK', + 'CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT', + 'CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK', + 'CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT', + 'CP_IQ_WAIT_TIME2__SCH_WAVE_MASK', + 'CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT', + 'CP_IQ_WAIT_TIME2__SEM_REARM_MASK', + 'CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT', + 'CP_MAX_CONTEXT__MAX_CONTEXT_MASK', + 'CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT', + 'CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK', + 'CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT', + 'CP_ME0_PIPE0_VMID__VMID_MASK', 'CP_ME0_PIPE0_VMID__VMID__SHIFT', + 'CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK', + 'CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT', + 'CP_ME0_PIPE1_VMID__VMID_MASK', 'CP_ME0_PIPE1_VMID__VMID__SHIFT', + 'CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK', + 'CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT', + 'CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK', + 'CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT', + 'CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK', + 'CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT', + 'CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK', + 'CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT', + 'CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK', + 'CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT', + 'CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK', + 'CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT', + 'CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK', + 'CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT', + 'CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK', + 'CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT', + 'CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK', + 'CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT', + 'CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK', + 'CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT', + 'CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK', + 'CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT', + 'CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK', + 'CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT', + 'CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK', + 'CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT', + 'CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK', + 'CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT', + 'CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK', + 'CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT', + 'CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK', + 'CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT', + 'CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK', + 'CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT', + 'CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK', + 'CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK', + 'CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT', + 'CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK', + 'CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK', + 'CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT', + 'CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK', + 'CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK', + 'CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT', + 'CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK', + 'CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK', + 'CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT', + 'CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK', + 'CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT', + 'CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK', + 'CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT', + 'CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK', + 'CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT', + 'CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK', + 'CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT', + 'CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK', + 'CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT', + 'CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK', + 'CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT', + 'CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK', + 'CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT', + 'CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK', + 'CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT', + 'CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK', + 'CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT', + 'CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK', + 'CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT', + 'CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK', + 'CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT', + 'CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK', + 'CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT', + 'CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK', + 'CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT', + 'CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK', + 'CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT', + 'CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK', + 'CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT', + 'CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK', + 'CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT', + 'CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK', + 'CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT', + 'CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK', + 'CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK', + 'CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT', + 'CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK', + 'CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK', + 'CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT', + 'CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK', + 'CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK', + 'CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT', + 'CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK', + 'CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK', + 'CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK', + 'CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT', + 'CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK', + 'CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT', + 'CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK', + 'CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT', + 'CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK', + 'CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT', + 'CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK', + 'CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT', + 'CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK', + 'CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__GPF_INT_CPC_MASK', + 'CP_MEC1_F32_INTERRUPT__GPF_INT_CPC__SHIFT', + 'CP_MEC1_F32_INTERRUPT__GPF_INT_CPF_MASK', + 'CP_MEC1_F32_INTERRUPT__GPF_INT_CPF__SHIFT', + 'CP_MEC1_F32_INTERRUPT__GPF_INT_DMA_MASK', + 'CP_MEC1_F32_INTERRUPT__GPF_INT_DMA__SHIFT', + 'CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT', + 'CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT_MASK', + 'CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK', + 'CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK', + 'CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK', + 'CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK', + 'CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK', + 'CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK', + 'CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK', + 'CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK', + 'CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT', + 'CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK', + 'CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT', + 'CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK', + 'CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT', + 'CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK', + 'CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK', + 'CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK', + 'CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK', + 'CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK', + 'CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT', + 'CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK', + 'CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT', + 'CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK', + 'CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT', + 'CP_MEC1_INTR_ROUTINE_START__IR_START_MASK', + 'CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT', + 'CP_MEC1_PRGRM_CNTR_START__IP_START_MASK', + 'CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT', + 'CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__GPF_INT_CPC_MASK', + 'CP_MEC2_F32_INTERRUPT__GPF_INT_CPC__SHIFT', + 'CP_MEC2_F32_INTERRUPT__GPF_INT_CPF_MASK', + 'CP_MEC2_F32_INTERRUPT__GPF_INT_CPF__SHIFT', + 'CP_MEC2_F32_INTERRUPT__GPF_INT_DMA_MASK', + 'CP_MEC2_F32_INTERRUPT__GPF_INT_DMA__SHIFT', + 'CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT', + 'CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT_MASK', + 'CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK', + 'CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK', + 'CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK', + 'CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK', + 'CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK', + 'CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK', + 'CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK', + 'CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK', + 'CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT', + 'CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK', + 'CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT', + 'CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK', + 'CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT', + 'CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK', + 'CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK', + 'CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK', + 'CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK', + 'CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK', + 'CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT', + 'CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK', + 'CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT', + 'CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK', + 'CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT', + 'CP_MEC2_INTR_ROUTINE_START__IR_START_MASK', + 'CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT', + 'CP_MEC2_PRGRM_CNTR_START__IP_START_MASK', + 'CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT', + 'CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK', + 'CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT', + 'CP_MEC_CNTL__MEC_ME1_HALT_MASK', + 'CP_MEC_CNTL__MEC_ME1_HALT__SHIFT', + 'CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK', + 'CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT', + 'CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK', + 'CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT', + 'CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK', + 'CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT', + 'CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK', + 'CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT', + 'CP_MEC_CNTL__MEC_ME1_STEP_MASK', + 'CP_MEC_CNTL__MEC_ME1_STEP__SHIFT', + 'CP_MEC_CNTL__MEC_ME2_HALT_MASK', + 'CP_MEC_CNTL__MEC_ME2_HALT__SHIFT', + 'CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK', + 'CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT', + 'CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK', + 'CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT', + 'CP_MEC_CNTL__MEC_ME2_STEP_MASK', + 'CP_MEC_CNTL__MEC_ME2_STEP__SHIFT', + 'CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK', + 'CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT', + 'CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK', + 'CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT', + 'CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK', + 'CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT', + 'CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK', + 'CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT', + 'CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK', + 'CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT', + 'CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK', + 'CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT', + 'CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK', + 'CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT', + 'CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK', + 'CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT', + 'CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK', + 'CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT', + 'CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK', + 'CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT', + 'CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK', + 'CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT', + 'CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK', + 'CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT', + 'CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK', + 'CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT', + 'CP_MEM_SLP_CNTL__RESERVED1_MASK', + 'CP_MEM_SLP_CNTL__RESERVED1__SHIFT', + 'CP_MEM_SLP_CNTL__RESERVED_MASK', + 'CP_MEM_SLP_CNTL__RESERVED__SHIFT', 'CP_MEQ_AVAIL__MEQ_CNT_MASK', + 'CP_MEQ_AVAIL__MEQ_CNT__SHIFT', 'CP_MEQ_STAT__MEQ_RPTR_MASK', + 'CP_MEQ_STAT__MEQ_RPTR__SHIFT', 'CP_MEQ_STAT__MEQ_WPTR_MASK', + 'CP_MEQ_STAT__MEQ_WPTR__SHIFT', + 'CP_MEQ_STQ_THRESHOLD__STQ_START_MASK', + 'CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT', + 'CP_MEQ_THRESHOLDS__MEQ1_START_MASK', + 'CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT', + 'CP_MEQ_THRESHOLDS__MEQ2_START_MASK', + 'CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT', + 'CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK', + 'CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT', + 'CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK', + 'CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT', + 'CP_ME_CNTL__CE_HALT_MASK', 'CP_ME_CNTL__CE_HALT__SHIFT', + 'CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK', + 'CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT', + 'CP_ME_CNTL__CE_PIPE0_RESET_MASK', + 'CP_ME_CNTL__CE_PIPE0_RESET__SHIFT', + 'CP_ME_CNTL__CE_PIPE1_RESET_MASK', + 'CP_ME_CNTL__CE_PIPE1_RESET__SHIFT', 'CP_ME_CNTL__CE_STEP_MASK', + 'CP_ME_CNTL__CE_STEP__SHIFT', 'CP_ME_CNTL__ME_HALT_MASK', + 'CP_ME_CNTL__ME_HALT__SHIFT', + 'CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK', + 'CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT', + 'CP_ME_CNTL__ME_PIPE0_RESET_MASK', + 'CP_ME_CNTL__ME_PIPE0_RESET__SHIFT', + 'CP_ME_CNTL__ME_PIPE1_RESET_MASK', + 'CP_ME_CNTL__ME_PIPE1_RESET__SHIFT', 'CP_ME_CNTL__ME_STEP_MASK', + 'CP_ME_CNTL__ME_STEP__SHIFT', 'CP_ME_CNTL__PFP_HALT_MASK', + 'CP_ME_CNTL__PFP_HALT__SHIFT', + 'CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK', + 'CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT', + 'CP_ME_CNTL__PFP_PIPE0_RESET_MASK', + 'CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT', + 'CP_ME_CNTL__PFP_PIPE1_RESET_MASK', + 'CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT', 'CP_ME_CNTL__PFP_STEP_MASK', + 'CP_ME_CNTL__PFP_STEP__SHIFT', + 'CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK', + 'CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT', + 'CP_ME_COHER_BASE__COHER_BASE_256B_MASK', + 'CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT', + 'CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK', + 'CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT', + 'CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK', + 'CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT', + 'CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK', + 'CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT', + 'CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK', + 'CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT', + 'CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK', + 'CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT', + 'CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK', + 'CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT', + 'CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK', + 'CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT', + 'CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK', + 'CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT', + 'CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK', + 'CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT', + 'CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK', + 'CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT', + 'CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK', + 'CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT', + 'CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK', + 'CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT', + 'CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK', + 'CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT', + 'CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK', + 'CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT', + 'CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK', + 'CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT', + 'CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK', + 'CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT', + 'CP_ME_COHER_STATUS__STATUS_MASK', + 'CP_ME_COHER_STATUS__STATUS__SHIFT', + 'CP_ME_F32_INTERRUPT__ECC_ERROR_INT_MASK', + 'CP_ME_F32_INTERRUPT__ECC_ERROR_INT__SHIFT', + 'CP_ME_F32_INTERRUPT__ME_F32_INT_2_MASK', + 'CP_ME_F32_INTERRUPT__ME_F32_INT_2__SHIFT', + 'CP_ME_F32_INTERRUPT__ME_F32_INT_3_MASK', + 'CP_ME_F32_INTERRUPT__ME_F32_INT_3__SHIFT', + 'CP_ME_F32_INTERRUPT__TIME_STAMP_INT_MASK', + 'CP_ME_F32_INTERRUPT__TIME_STAMP_INT__SHIFT', + 'CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK', + 'CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT', + 'CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK', + 'CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT', + 'CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK', + 'CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT', + 'CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK', + 'CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT', + 'CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK', + 'CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT', + 'CP_ME_INSTR_PNTR__INSTR_PNTR_MASK', + 'CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT', + 'CP_ME_INTR_ROUTINE_START__IR_START_MASK', + 'CP_ME_INTR_ROUTINE_START__IR_START__SHIFT', + 'CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK', + 'CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT', + 'CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK', + 'CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT', + 'CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK', + 'CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT', + 'CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK', + 'CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT', + 'CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK', + 'CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT', + 'CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK', + 'CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT', + 'CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK', + 'CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT', + 'CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK', + 'CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT', + 'CP_ME_PREEMPTION__OBSOLETE_MASK', + 'CP_ME_PREEMPTION__OBSOLETE__SHIFT', + 'CP_ME_PRGRM_CNTR_START__IP_START_MASK', + 'CP_ME_PRGRM_CNTR_START__IP_START__SHIFT', + 'CP_ME_RAM_DATA__ME_RAM_DATA_MASK', + 'CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT', + 'CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK', + 'CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT', + 'CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK', + 'CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT', + 'CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK', + 'CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT', + 'CP_MQD_BASE_ADDR__BASE_ADDR_MASK', + 'CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT', + 'CP_MQD_CONTROL__CACHE_POLICY_MASK', + 'CP_MQD_CONTROL__CACHE_POLICY__SHIFT', + 'CP_MQD_CONTROL__EXE_DISABLE_MASK', + 'CP_MQD_CONTROL__EXE_DISABLE__SHIFT', + 'CP_MQD_CONTROL__PRIV_STATE_MASK', + 'CP_MQD_CONTROL__PRIV_STATE__SHIFT', + 'CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK', + 'CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT', + 'CP_MQD_CONTROL__PROCESSING_MQD_MASK', + 'CP_MQD_CONTROL__PROCESSING_MQD__SHIFT', + 'CP_MQD_CONTROL__VMID_MASK', 'CP_MQD_CONTROL__VMID__SHIFT', + 'CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK', + 'CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT', + 'CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK', + 'CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT', + 'CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK', + 'CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT', + 'CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK', + 'CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT', + 'CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK', + 'CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT', + 'CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK', + 'CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT', + 'CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK', + 'CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT', + 'CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK', + 'CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT', + 'CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK', + 'CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT', + 'CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK', + 'CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT', + 'CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK', + 'CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT', + 'CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK', + 'CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT', + 'CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK', + 'CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT', + 'CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK', + 'CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT', + 'CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK', + 'CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT', + 'CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK', + 'CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT', + 'CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK', + 'CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT', + 'CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK', + 'CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT', + 'CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK', + 'CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT', + 'CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK', + 'CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT', + 'CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK', + 'CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT', + 'CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK', + 'CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT', + 'CP_PERFMON_CNTL__PERFMON_STATE_MASK', + 'CP_PERFMON_CNTL__PERFMON_STATE__SHIFT', + 'CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK', + 'CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT', + 'CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK', + 'CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT', + 'CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK', + 'CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT', + 'CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK', + 'CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT', + 'CP_PFP_COMPLETION_STATUS__STATUS_MASK', + 'CP_PFP_COMPLETION_STATUS__STATUS__SHIFT', + 'CP_PFP_F32_INTERRUPT__ECC_ERROR_INT_MASK', + 'CP_PFP_F32_INTERRUPT__ECC_ERROR_INT__SHIFT', + 'CP_PFP_F32_INTERRUPT__PFP_F32_INT_3_MASK', + 'CP_PFP_F32_INTERRUPT__PFP_F32_INT_3__SHIFT', + 'CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK', + 'CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT', + 'CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK', + 'CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT', + 'CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK', + 'CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT', + 'CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK', + 'CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT', + 'CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK', + 'CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT', + 'CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK', + 'CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT', + 'CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK', + 'CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT', + 'CP_PFP_IB_CONTROL__IB_EN_MASK', + 'CP_PFP_IB_CONTROL__IB_EN__SHIFT', + 'CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK', + 'CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT', + 'CP_PFP_INTR_ROUTINE_START__IR_START_MASK', + 'CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT', + 'CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK', + 'CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT', + 'CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK', + 'CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT', + 'CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK', + 'CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT', + 'CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK', + 'CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT', + 'CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK', + 'CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT', + 'CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK', + 'CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT', + 'CP_PFP_PRGRM_CNTR_START__IP_START_MASK', + 'CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT', + 'CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK', + 'CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT', + 'CP_PFP_UCODE_DATA__UCODE_DATA_MASK', + 'CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT', 'CP_PIPEID__PIPE_ID_MASK', + 'CP_PIPEID__PIPE_ID__SHIFT', + 'CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK', + 'CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT', + 'CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK', + 'CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT', + 'CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK', + 'CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT', + 'CP_PQ_STATUS__DOORBELL_ENABLE_MASK', + 'CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT', + 'CP_PQ_STATUS__DOORBELL_UPDATED_EN_MASK', + 'CP_PQ_STATUS__DOORBELL_UPDATED_EN__SHIFT', + 'CP_PQ_STATUS__DOORBELL_UPDATED_MASK', + 'CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT', + 'CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK', + 'CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT', + 'CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK', + 'CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT', + 'CP_PQ_WPTR_POLL_CNTL__EN_MASK', + 'CP_PQ_WPTR_POLL_CNTL__EN__SHIFT', + 'CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK', + 'CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT', + 'CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK', + 'CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT', + 'CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK', + 'CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT', + 'CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK', + 'CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT', + 'CP_PSP_XCP_CTL__PHYSICAL_XCC_ID_MASK', + 'CP_PSP_XCP_CTL__PHYSICAL_XCC_ID__SHIFT', + 'CP_PSP_XCP_CTL__XCC_DIE_ID_MASK', + 'CP_PSP_XCP_CTL__XCC_DIE_ID__SHIFT', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK', + 'CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT', + 'CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK', + 'CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT', + 'CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK', + 'CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT', + 'CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK', + 'CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT', + 'CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK', + 'CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT', + 'CP_RB0_ACTIVE__ACTIVE_MASK', 'CP_RB0_ACTIVE__ACTIVE__SHIFT', + 'CP_RB0_BASE_HI__RB_BASE_HI_MASK', + 'CP_RB0_BASE_HI__RB_BASE_HI__SHIFT', 'CP_RB0_BASE__RB_BASE_MASK', + 'CP_RB0_BASE__RB_BASE__SHIFT', 'CP_RB0_BUFSZ_MASK__DATA_MASK', + 'CP_RB0_BUFSZ_MASK__DATA__SHIFT', 'CP_RB0_CNTL__BUF_SWAP_MASK', + 'CP_RB0_CNTL__BUF_SWAP__SHIFT', 'CP_RB0_CNTL__CACHE_POLICY_MASK', + 'CP_RB0_CNTL__CACHE_POLICY__SHIFT', + 'CP_RB0_CNTL__MIN_AVAILSZ_MASK', + 'CP_RB0_CNTL__MIN_AVAILSZ__SHIFT', + 'CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK', + 'CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT', + 'CP_RB0_CNTL__RB_BLKSZ_MASK', 'CP_RB0_CNTL__RB_BLKSZ__SHIFT', + 'CP_RB0_CNTL__RB_BUFSZ_MASK', 'CP_RB0_CNTL__RB_BUFSZ__SHIFT', + 'CP_RB0_CNTL__RB_NO_UPDATE_MASK', + 'CP_RB0_CNTL__RB_NO_UPDATE__SHIFT', + 'CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK', + 'CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT', + 'CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK', + 'CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT', + 'CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK', + 'CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT', + 'CP_RB0_RPTR__RB_RPTR_MASK', 'CP_RB0_RPTR__RB_RPTR__SHIFT', + 'CP_RB0_WPTR_HI__RB_WPTR_MASK', 'CP_RB0_WPTR_HI__RB_WPTR__SHIFT', + 'CP_RB0_WPTR__RB_WPTR_MASK', 'CP_RB0_WPTR__RB_WPTR__SHIFT', + 'CP_RB1_BASE_HI__RB_BASE_HI_MASK', + 'CP_RB1_BASE_HI__RB_BASE_HI__SHIFT', 'CP_RB1_BASE__RB_BASE_MASK', + 'CP_RB1_BASE__RB_BASE__SHIFT', 'CP_RB1_CNTL__CACHE_POLICY_MASK', + 'CP_RB1_CNTL__CACHE_POLICY__SHIFT', + 'CP_RB1_CNTL__MIN_AVAILSZ_MASK', + 'CP_RB1_CNTL__MIN_AVAILSZ__SHIFT', + 'CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK', + 'CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT', + 'CP_RB1_CNTL__RB_BLKSZ_MASK', 'CP_RB1_CNTL__RB_BLKSZ__SHIFT', + 'CP_RB1_CNTL__RB_BUFSZ_MASK', 'CP_RB1_CNTL__RB_BUFSZ__SHIFT', + 'CP_RB1_CNTL__RB_NO_UPDATE_MASK', + 'CP_RB1_CNTL__RB_NO_UPDATE__SHIFT', + 'CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK', + 'CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT', + 'CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK', + 'CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT', + 'CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK', + 'CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT', + 'CP_RB1_RPTR__RB_RPTR_MASK', 'CP_RB1_RPTR__RB_RPTR__SHIFT', + 'CP_RB1_WPTR_HI__RB_WPTR_MASK', 'CP_RB1_WPTR_HI__RB_WPTR__SHIFT', + 'CP_RB1_WPTR__RB_WPTR_MASK', 'CP_RB1_WPTR__RB_WPTR__SHIFT', + 'CP_RB2_BASE__RB_BASE_MASK', 'CP_RB2_BASE__RB_BASE__SHIFT', + 'CP_RB2_CNTL__CACHE_POLICY_MASK', + 'CP_RB2_CNTL__CACHE_POLICY__SHIFT', + 'CP_RB2_CNTL__MIN_AVAILSZ_MASK', + 'CP_RB2_CNTL__MIN_AVAILSZ__SHIFT', + 'CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK', + 'CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT', + 'CP_RB2_CNTL__RB_BLKSZ_MASK', 'CP_RB2_CNTL__RB_BLKSZ__SHIFT', + 'CP_RB2_CNTL__RB_BUFSZ_MASK', 'CP_RB2_CNTL__RB_BUFSZ__SHIFT', + 'CP_RB2_CNTL__RB_NO_UPDATE_MASK', + 'CP_RB2_CNTL__RB_NO_UPDATE__SHIFT', + 'CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK', + 'CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT', + 'CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK', + 'CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT', + 'CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK', + 'CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT', + 'CP_RB2_RPTR__RB_RPTR_MASK', 'CP_RB2_RPTR__RB_RPTR__SHIFT', + 'CP_RB2_WPTR__RB_WPTR_MASK', 'CP_RB2_WPTR__RB_WPTR__SHIFT', + 'CP_RB_ACTIVE__ACTIVE_MASK', 'CP_RB_ACTIVE__ACTIVE__SHIFT', + 'CP_RB_BASE__RB_BASE_MASK', 'CP_RB_BASE__RB_BASE__SHIFT', + 'CP_RB_BUFSZ_MASK__DATA_MASK', 'CP_RB_BUFSZ_MASK__DATA__SHIFT', + 'CP_RB_CNTL__CACHE_POLICY_MASK', + 'CP_RB_CNTL__CACHE_POLICY__SHIFT', 'CP_RB_CNTL__MIN_AVAILSZ_MASK', + 'CP_RB_CNTL__MIN_AVAILSZ__SHIFT', + 'CP_RB_CNTL__MIN_IB_AVAILSZ_MASK', + 'CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT', 'CP_RB_CNTL__RB_BLKSZ_MASK', + 'CP_RB_CNTL__RB_BLKSZ__SHIFT', 'CP_RB_CNTL__RB_BUFSZ_MASK', + 'CP_RB_CNTL__RB_BUFSZ__SHIFT', 'CP_RB_CNTL__RB_NO_UPDATE_MASK', + 'CP_RB_CNTL__RB_NO_UPDATE__SHIFT', + 'CP_RB_CNTL__RB_RPTR_WR_ENA_MASK', + 'CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT', + 'CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK', + 'CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT', + 'CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK', + 'CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT', + 'CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK', + 'CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT', + 'CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK', + 'CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT', + 'CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK', + 'CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT', + 'CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK', + 'CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT', + 'CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK', + 'CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT__SHIFT', + 'CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET_MASK', + 'CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET__SHIFT', + 'CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK', + 'CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT', + 'CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK', + 'CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT', + 'CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK', + 'CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT', + 'CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK', + 'CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT', + 'CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK', + 'CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT', + 'CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK', + 'CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT', + 'CP_RB_OFFSET__RB_OFFSET_MASK', 'CP_RB_OFFSET__RB_OFFSET__SHIFT', + 'CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK', + 'CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT', + 'CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK', + 'CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT', + 'CP_RB_RPTR_WR__RB_RPTR_WR_MASK', + 'CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT', 'CP_RB_RPTR__RB_RPTR_MASK', + 'CP_RB_RPTR__RB_RPTR__SHIFT', + 'CP_RB_STATUS__DOORBELL_ENABLE_MASK', + 'CP_RB_STATUS__DOORBELL_ENABLE__SHIFT', + 'CP_RB_STATUS__DOORBELL_UPDATED_MASK', + 'CP_RB_STATUS__DOORBELL_UPDATED__SHIFT', + 'CP_RB_VMID__RB0_VMID_MASK', 'CP_RB_VMID__RB0_VMID__SHIFT', + 'CP_RB_VMID__RB1_VMID_MASK', 'CP_RB_VMID__RB1_VMID__SHIFT', + 'CP_RB_VMID__RB2_VMID_MASK', 'CP_RB_VMID__RB2_VMID__SHIFT', + 'CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK', + 'CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT', + 'CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK', + 'CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT', + 'CP_RB_WPTR_HI__RB_WPTR_MASK', 'CP_RB_WPTR_HI__RB_WPTR__SHIFT', + 'CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK', + 'CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT', + 'CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK', + 'CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT', + 'CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK', + 'CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT', + 'CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK', + 'CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT', + 'CP_RB_WPTR__RB_WPTR_MASK', 'CP_RB_WPTR__RB_WPTR__SHIFT', + 'CP_RING0_PRIORITY__PRIORITY_MASK', + 'CP_RING0_PRIORITY__PRIORITY__SHIFT', + 'CP_RING1_PRIORITY__PRIORITY_MASK', + 'CP_RING1_PRIORITY__PRIORITY__SHIFT', + 'CP_RING2_PRIORITY__PRIORITY_MASK', + 'CP_RING2_PRIORITY__PRIORITY__SHIFT', 'CP_RINGID__RINGID_MASK', + 'CP_RINGID__RINGID__SHIFT', + 'CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK', + 'CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT', + 'CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK', + 'CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT', + 'CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK', + 'CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT', + 'CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK', + 'CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT', + 'CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK', + 'CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT', + 'CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK', + 'CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT', + 'CP_ROQ1_THRESHOLDS__RB1_START_MASK', + 'CP_ROQ1_THRESHOLDS__RB1_START__SHIFT', + 'CP_ROQ1_THRESHOLDS__RB2_START_MASK', + 'CP_ROQ1_THRESHOLDS__RB2_START__SHIFT', + 'CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK', + 'CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT', + 'CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK', + 'CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT', + 'CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK', + 'CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT', + 'CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK', + 'CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT', + 'CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK', + 'CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT', + 'CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK', + 'CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT', + 'CP_ROQ_AVAIL__ROQ_CNT_RING_MASK', + 'CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT', + 'CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK', + 'CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT', + 'CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK', + 'CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT', + 'CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK', + 'CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT', + 'CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK', + 'CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT', + 'CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK', + 'CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT', + 'CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK', + 'CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT', + 'CP_ROQ_THRESHOLDS__IB1_START_MASK', + 'CP_ROQ_THRESHOLDS__IB1_START__SHIFT', + 'CP_ROQ_THRESHOLDS__IB2_START_MASK', + 'CP_ROQ_THRESHOLDS__IB2_START__SHIFT', + 'CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK', + 'CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT', + 'CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK', + 'CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT', + 'CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK', + 'CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT', + 'CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK', + 'CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT', + 'CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK', + 'CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT', + 'CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK', + 'CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT', + 'CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK', + 'CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT', + 'CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK', + 'CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT', + 'CP_SCRATCH_DATA__SCRATCH_DATA_MASK', + 'CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT', + 'CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK', + 'CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT', + 'CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK', + 'CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT', + 'CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK', + 'CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT', + 'CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK', + 'CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT', + 'CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK', + 'CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT', + 'CP_SD_CNTL__CPC_EN_MASK', 'CP_SD_CNTL__CPC_EN__SHIFT', + 'CP_SD_CNTL__CPF_EN_MASK', 'CP_SD_CNTL__CPF_EN__SHIFT', + 'CP_SD_CNTL__CPG_EN_MASK', 'CP_SD_CNTL__CPG_EN__SHIFT', + 'CP_SD_CNTL__EA_EN_MASK', 'CP_SD_CNTL__EA_EN__SHIFT', + 'CP_SD_CNTL__IA_EN_MASK', 'CP_SD_CNTL__IA_EN__SHIFT', + 'CP_SD_CNTL__PA_EN_MASK', 'CP_SD_CNTL__PA_EN__SHIFT', + 'CP_SD_CNTL__RLC_EN_MASK', 'CP_SD_CNTL__RLC_EN__SHIFT', + 'CP_SD_CNTL__RMI_EN_MASK', 'CP_SD_CNTL__RMI_EN__SHIFT', + 'CP_SD_CNTL__SPI_EN_MASK', 'CP_SD_CNTL__SPI_EN__SHIFT', + 'CP_SD_CNTL__WD_EN_MASK', 'CP_SD_CNTL__WD_EN__SHIFT', + 'CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK', + 'CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT', + 'CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK', + 'CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT', + 'CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK', + 'CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT', + 'CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK', + 'CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT', + 'CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK', + 'CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT', + 'CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK', + 'CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT', + 'CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK', + 'CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT', + 'CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK', + 'CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT', + 'CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK', + 'CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT', + 'CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK', + 'CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT', + 'CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK', + 'CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT', + 'CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK', + 'CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT', + 'CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK', + 'CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT', + 'CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK', + 'CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT', + 'CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK', + 'CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT', + 'CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK', + 'CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT', + 'CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK', + 'CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT', + 'CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK', + 'CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT', + 'CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK', + 'CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT', + 'CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK', + 'CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT', + 'CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK', + 'CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT', + 'CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK', + 'CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT', + 'CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK', + 'CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT', + 'CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK', + 'CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT', + 'CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK', + 'CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT', + 'CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK', + 'CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT', + 'CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK', + 'CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT', + 'CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK', + 'CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT', + 'CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK', + 'CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT', + 'CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK', + 'CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT', + 'CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK', + 'CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT', + 'CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK', + 'CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT', + 'CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK', + 'CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT', + 'CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK', + 'CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT', + 'CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK', + 'CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT', + 'CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK', + 'CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT', + 'CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK', + 'CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT', + 'CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK', + 'CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT', + 'CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK', + 'CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT', + 'CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK', + 'CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT', + 'CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK', + 'CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT', + 'CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK', + 'CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT', + 'CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK', + 'CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT', + 'CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK', + 'CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT', + 'CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK', + 'CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT', + 'CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK', + 'CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT', + 'CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK', + 'CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT', + 'CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK', + 'CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT', + 'CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK', + 'CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT', + 'CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK', + 'CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT', + 'CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK', + 'CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT', + 'CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK', + 'CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT', + 'CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK', + 'CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT', + 'CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK', + 'CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT', + 'CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK', + 'CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT', + 'CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK', + 'CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT', + 'CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK', + 'CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT', + 'CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK', + 'CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT', + 'CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK', + 'CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT', + 'CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK', + 'CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK', + 'CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT', + 'CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT', + 'CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK', + 'CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT', + 'CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK', + 'CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT', + 'CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK', + 'CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT', + 'CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK', + 'CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT', + 'CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK', + 'CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT', + 'CP_STAT__CE_BUSY_MASK', 'CP_STAT__CE_BUSY__SHIFT', + 'CP_STAT__CP_BUSY_MASK', 'CP_STAT__CP_BUSY__SHIFT', + 'CP_STAT__DC_BUSY_MASK', 'CP_STAT__DC_BUSY__SHIFT', + 'CP_STAT__DMA_BUSY_MASK', 'CP_STAT__DMA_BUSY__SHIFT', + 'CP_STAT__INTERRUPT_BUSY_MASK', 'CP_STAT__INTERRUPT_BUSY__SHIFT', + 'CP_STAT__MEQ_BUSY_MASK', 'CP_STAT__MEQ_BUSY__SHIFT', + 'CP_STAT__ME_BUSY_MASK', 'CP_STAT__ME_BUSY__SHIFT', + 'CP_STAT__PFP_BUSY_MASK', 'CP_STAT__PFP_BUSY__SHIFT', + 'CP_STAT__QUERY_BUSY_MASK', 'CP_STAT__QUERY_BUSY__SHIFT', + 'CP_STAT__RCIU_BUSY_MASK', 'CP_STAT__RCIU_BUSY__SHIFT', + 'CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK', + 'CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT', + 'CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK', + 'CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT', + 'CP_STAT__ROQ_CE_RING_BUSY_MASK', + 'CP_STAT__ROQ_CE_RING_BUSY__SHIFT', + 'CP_STAT__ROQ_INDIRECT1_BUSY_MASK', + 'CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT', + 'CP_STAT__ROQ_INDIRECT2_BUSY_MASK', + 'CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT', + 'CP_STAT__ROQ_RING_BUSY_MASK', 'CP_STAT__ROQ_RING_BUSY__SHIFT', + 'CP_STAT__ROQ_STATE_BUSY_MASK', 'CP_STAT__ROQ_STATE_BUSY__SHIFT', + 'CP_STAT__SCRATCH_RAM_BUSY_MASK', + 'CP_STAT__SCRATCH_RAM_BUSY__SHIFT', + 'CP_STAT__SEMAPHORE_BUSY_MASK', 'CP_STAT__SEMAPHORE_BUSY__SHIFT', + 'CP_STAT__SURFACE_SYNC_BUSY_MASK', + 'CP_STAT__SURFACE_SYNC_BUSY__SHIFT', 'CP_STAT__TCIU_BUSY_MASK', + 'CP_STAT__TCIU_BUSY__SHIFT', 'CP_STAT__UTCL2IU_BUSY_MASK', + 'CP_STAT__UTCL2IU_BUSY__SHIFT', 'CP_STQ_AVAIL__STQ_CNT_MASK', + 'CP_STQ_AVAIL__STQ_CNT__SHIFT', 'CP_STQ_STAT__STQ_RPTR_MASK', + 'CP_STQ_STAT__STQ_RPTR__SHIFT', + 'CP_STQ_THRESHOLDS__STQ0_START_MASK', + 'CP_STQ_THRESHOLDS__STQ0_START__SHIFT', + 'CP_STQ_THRESHOLDS__STQ1_START_MASK', + 'CP_STQ_THRESHOLDS__STQ1_START__SHIFT', + 'CP_STQ_THRESHOLDS__STQ2_START_MASK', + 'CP_STQ_THRESHOLDS__STQ2_START__SHIFT', + 'CP_STQ_WR_STAT__STQ_WPTR_MASK', + 'CP_STQ_WR_STAT__STQ_WPTR__SHIFT', + 'CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK', + 'CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT', + 'CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK', + 'CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT', + 'CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK', + 'CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT', + 'CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK', + 'CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT', + 'CP_ST_BASE_HI__ST_BASE_HI_MASK', + 'CP_ST_BASE_HI__ST_BASE_HI__SHIFT', + 'CP_ST_BASE_LO__ST_BASE_LO_MASK', + 'CP_ST_BASE_LO__ST_BASE_LO__SHIFT', 'CP_ST_BUFSZ__ST_BUFSZ_MASK', + 'CP_ST_BUFSZ__ST_BUFSZ__SHIFT', + 'CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK', + 'CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT', + 'CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK', + 'CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT', + 'CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK', + 'CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT', + 'CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK', + 'CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT', + 'CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK', + 'CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT', + 'CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK', + 'CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT', + 'CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK', + 'CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT', + 'CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK', + 'CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT', + 'CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK', + 'CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT', + 'CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK', + 'CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT', + 'CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK', + 'CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT', + 'CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK', + 'CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT', + 'CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK', + 'CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT', + 'CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK', + 'CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT', + 'CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK', + 'CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT', + 'CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK', + 'CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT', + 'CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK', + 'CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT', + 'CP_VIRT_STATUS__VIRT_STATUS_MASK', + 'CP_VIRT_STATUS__VIRT_STATUS__SHIFT', + 'CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK', + 'CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT', + 'CP_VMID_PREEMPT__VIRT_COMMAND_MASK', + 'CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT', + 'CP_VMID_RESET__RESET_REQUEST_MASK', + 'CP_VMID_RESET__RESET_REQUEST__SHIFT', + 'CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK', + 'CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT', + 'CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK', + 'CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT', 'CP_VMID__VMID_MASK', + 'CP_VMID__VMID__SHIFT', + 'CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK', + 'CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT', + 'CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK', + 'CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT', + 'CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK', + 'CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT', + 'CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK', + 'CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT', + 'CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK', + 'CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT', + 'CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK', + 'CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT', + 'CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK', + 'CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT', + 'CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK', + 'CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT', + 'CS_COPY_STATE__SRC_STATE_ID_MASK', + 'CS_COPY_STATE__SRC_STATE_ID__SHIFT', + 'DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK', + 'DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT', + 'DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK', + 'DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT', + 'DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK', + 'DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT', + 'DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK', + 'DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT', + 'DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK', + 'DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT', + 'DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK', + 'DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT', + 'DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK', + 'DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT', + 'DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK', + 'DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT', + 'DB_CGTT_CLK_CTRL_0__RESERVED_MASK', + 'DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT', + 'DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK', + 'DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT', + 'DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK', + 'DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT', + 'DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK', + 'DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT', + 'DB_COUNT_CONTROL__SAMPLE_RATE_MASK', + 'DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT', + 'DB_COUNT_CONTROL__SFAIL_ENABLE_MASK', + 'DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT', + 'DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK', + 'DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT', + 'DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK', + 'DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT', + 'DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK', + 'DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT', + 'DB_COUNT_CONTROL__ZPASS_ENABLE_MASK', + 'DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT', + 'DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK', + 'DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT', + 'DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK', + 'DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT', + 'DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK', + 'DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT', + 'DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK', + 'DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT', + 'DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK', + 'DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT', + 'DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK', + 'DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT', + 'DB_DEBUG2__CLK_OFF_DELAY_MASK', + 'DB_DEBUG2__CLK_OFF_DELAY__SHIFT', + 'DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK', + 'DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT', + 'DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK', + 'DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT', + 'DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK', + 'DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK', + 'DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT', + 'DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT', + 'DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK', + 'DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT', + 'DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK', + 'DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT', + 'DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK', + 'DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT', + 'DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK', + 'DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT', + 'DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK', + 'DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT', + 'DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK', + 'DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT', + 'DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID_MASK', + 'DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID__SHIFT', + 'DB_DEBUG2__DISABLE_VR_PS_INVOKE_MASK', + 'DB_DEBUG2__DISABLE_VR_PS_INVOKE__SHIFT', + 'DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK', + 'DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT', + 'DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK', + 'DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT', + 'DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK', + 'DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT', + 'DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK', + 'DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT', + 'DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK', + 'DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT', + 'DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK', + 'DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT', + 'DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK', + 'DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT', + 'DB_DEBUG2__RESERVED_MASK', 'DB_DEBUG2__RESERVED__SHIFT', + 'DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK', + 'DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT', + 'DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK', + 'DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT', + 'DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK', + 'DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT', + 'DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK', + 'DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT', + 'DB_DEBUG3__DISABLE_DI_DT_STALL_MASK', + 'DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT', + 'DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK', + 'DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT', + 'DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK', + 'DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT', + 'DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK', + 'DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT', + 'DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK', + 'DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT', + 'DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK', + 'DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT', + 'DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK', + 'DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT', + 'DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK', + 'DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT', + 'DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK', + 'DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT', + 'DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK', + 'DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT', + 'DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK', + 'DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT', + 'DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK', + 'DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT', + 'DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK', + 'DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT', + 'DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK', + 'DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT', + 'DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK', + 'DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT', + 'DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK', + 'DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT', + 'DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK', + 'DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT', + 'DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK', + 'DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT', + 'DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK', + 'DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT', + 'DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK', + 'DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT', + 'DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK', + 'DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT', + 'DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK', + 'DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT', + 'DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK', + 'DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT', + 'DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK', + 'DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT', + 'DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK', + 'DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT', + 'DB_DEBUG3__FORCE_DB_IS_GOOD_MASK', + 'DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT', + 'DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK', + 'DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT', + 'DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK', + 'DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT', + 'DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK', + 'DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT', + 'DB_DEBUG4__DB_EXTRA_DEBUG4_MASK', + 'DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT', + 'DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK', + 'DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT', + 'DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK', + 'DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT', + 'DB_DEBUG4__DISABLE_8PPC_OBJPRIMID_WHEN_NO_SHADER_EXPORTS_MASK', + 'DB_DEBUG4__DISABLE_8PPC_OBJPRIMID_WHEN_NO_SHADER_EXPORTS__SHIFT', + 'DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK', + 'DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT', + 'DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK', + 'DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT', + 'DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK', + 'DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT', + 'DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK', + 'DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT', + 'DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK', + 'DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT', + 'DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK', + 'DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT', + 'DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK', + 'DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT', + 'DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK', + 'DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT', + 'DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK', + 'DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT', + 'DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK', + 'DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT', + 'DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK', + 'DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT', + 'DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK', + 'DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT', + 'DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK', + 'DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT', + 'DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK', + 'DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT', + 'DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK', + 'DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT', + 'DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK', + 'DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT', + 'DB_DEBUG4__FULL_TILE_CACHE_EVICT_ON_HALF_FULL_MASK', + 'DB_DEBUG4__FULL_TILE_CACHE_EVICT_ON_HALF_FULL__SHIFT', + 'DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK', + 'DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT', + 'DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK', + 'DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT', + 'DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK', + 'DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT', + 'DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK', + 'DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT', + 'DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK', + 'DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT', + 'DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK', + 'DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT', + 'DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK', + 'DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT', + 'DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK', + 'DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT', + 'DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK', + 'DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT', + 'DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK', + 'DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT', + 'DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK', + 'DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT', + 'DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK', + 'DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT', + 'DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK', + 'DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT', + 'DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK', + 'DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT', + 'DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK', + 'DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT', + 'DB_DEBUG__DISABLE_SUMM_SQUADS_MASK', + 'DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT', + 'DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK', + 'DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT', + 'DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK', + 'DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT', + 'DB_DEBUG__FETCH_FULL_Z_TILE_MASK', + 'DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT', + 'DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK', + 'DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT', + 'DB_DEBUG__FORCE_Z_MODE_MASK', 'DB_DEBUG__FORCE_Z_MODE__SHIFT', + 'DB_DEBUG__NEVER_FREE_Z_ONLY_MASK', + 'DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT', + 'DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK', + 'DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT', + 'DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK', + 'DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT', + 'DB_DEPTH_BOUNDS_MAX__MAX_MASK', + 'DB_DEPTH_BOUNDS_MAX__MAX__SHIFT', + 'DB_DEPTH_BOUNDS_MIN__MIN_MASK', + 'DB_DEPTH_BOUNDS_MIN__MIN__SHIFT', + 'DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK', + 'DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT', + 'DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK', + 'DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT', + 'DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK', + 'DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT', + 'DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK', + 'DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT', + 'DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK', + 'DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT', + 'DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK', + 'DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT', + 'DB_DEPTH_CONTROL__STENCILFUNC_MASK', + 'DB_DEPTH_CONTROL__STENCILFUNC__SHIFT', + 'DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK', + 'DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT', + 'DB_DEPTH_CONTROL__ZFUNC_MASK', 'DB_DEPTH_CONTROL__ZFUNC__SHIFT', + 'DB_DEPTH_CONTROL__Z_ENABLE_MASK', + 'DB_DEPTH_CONTROL__Z_ENABLE__SHIFT', + 'DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK', + 'DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT', + 'DB_DEPTH_SIZE__X_MAX_MASK', 'DB_DEPTH_SIZE__X_MAX__SHIFT', + 'DB_DEPTH_SIZE__Y_MAX_MASK', 'DB_DEPTH_SIZE__Y_MAX__SHIFT', + 'DB_DEPTH_VIEW__MIPID_MASK', 'DB_DEPTH_VIEW__MIPID__SHIFT', + 'DB_DEPTH_VIEW__SLICE_MAX_MASK', + 'DB_DEPTH_VIEW__SLICE_MAX__SHIFT', + 'DB_DEPTH_VIEW__SLICE_START_MASK', + 'DB_DEPTH_VIEW__SLICE_START__SHIFT', + 'DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK', + 'DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT', + 'DB_DEPTH_VIEW__Z_READ_ONLY_MASK', + 'DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT', + 'DB_DFSM_CONFIG__BYPASS_DFSM_MASK', + 'DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT', + 'DB_DFSM_CONFIG__DISABLE_POPS_MASK', + 'DB_DFSM_CONFIG__DISABLE_POPS__SHIFT', + 'DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK', + 'DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT', + 'DB_DFSM_CONFIG__FORCE_FLUSH_MASK', + 'DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT', + 'DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK', + 'DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT', + 'DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK', + 'DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT', + 'DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK', + 'DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT', + 'DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK', + 'DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT', + 'DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK', + 'DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT', + 'DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK', + 'DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT', + 'DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK', + 'DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT', + 'DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK', + 'DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT', + 'DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK', + 'DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT', + 'DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK', + 'DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT', + 'DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK', + 'DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT', + 'DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK', + 'DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT', + 'DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK', + 'DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT', + 'DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK', + 'DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT', + 'DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK', + 'DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT', + 'DB_DFSM_WATCHDOG__TIMER_TARGET_MASK', + 'DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT', + 'DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK', + 'DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT', + 'DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK', + 'DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT', + 'DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK', + 'DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT', + 'DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK', + 'DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT', + 'DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK', + 'DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT', + 'DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK', + 'DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT', + 'DB_EQAA__INCOHERENT_EQAA_READS_MASK', + 'DB_EQAA__INCOHERENT_EQAA_READS__SHIFT', + 'DB_EQAA__INTERPOLATE_COMP_Z_MASK', + 'DB_EQAA__INTERPOLATE_COMP_Z__SHIFT', + 'DB_EQAA__INTERPOLATE_SRC_Z_MASK', + 'DB_EQAA__INTERPOLATE_SRC_Z__SHIFT', + 'DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK', + 'DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT', + 'DB_EQAA__MAX_ANCHOR_SAMPLES_MASK', + 'DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT', + 'DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK', + 'DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT', + 'DB_EQAA__PS_ITER_SAMPLES_MASK', + 'DB_EQAA__PS_ITER_SAMPLES__SHIFT', + 'DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK', + 'DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT', + 'DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK', + 'DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT', + 'DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK', + 'DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT', + 'DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK', + 'DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT', + 'DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK', + 'DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT', + 'DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK', + 'DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT', + 'DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK', + 'DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT', + 'DB_FIFO_DEPTH1__MCC_DEPTH_MASK', + 'DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT', + 'DB_FIFO_DEPTH1__QC_DEPTH_MASK', + 'DB_FIFO_DEPTH1__QC_DEPTH__SHIFT', + 'DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK', + 'DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT', + 'DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK', + 'DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT', + 'DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK', + 'DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT', + 'DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK', + 'DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT', + 'DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK', + 'DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT', + 'DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK', + 'DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT', + 'DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK', + 'DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT', + 'DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK', + 'DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT', + 'DB_FREE_CACHELINES__QUAD_READ_REQS_MASK', + 'DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT', + 'DB_HTILE_DATA_BASE_HI__BASE_HI_MASK', + 'DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT', + 'DB_HTILE_DATA_BASE__BASE_256B_MASK', + 'DB_HTILE_DATA_BASE__BASE_256B__SHIFT', + 'DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK', + 'DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT', + 'DB_HTILE_SURFACE__FULL_CACHE_MASK', + 'DB_HTILE_SURFACE__FULL_CACHE__SHIFT', + 'DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK', + 'DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT', + 'DB_HTILE_SURFACE__PIPE_ALIGNED_MASK', + 'DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT', + 'DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK', + 'DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT', + 'DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK', + 'DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT', + 'DB_HTILE_SURFACE__PRELOAD_MASK', + 'DB_HTILE_SURFACE__PRELOAD__SHIFT', + 'DB_HTILE_SURFACE__RB_ALIGNED_MASK', + 'DB_HTILE_SURFACE__RB_ALIGNED__SHIFT', + 'DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK', + 'DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT', + 'DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK', + 'DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT', + 'DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK', + 'DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT', + 'DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK', + 'DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT', + 'DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK', + 'DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT', + 'DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK', + 'DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT', + 'DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK', + 'DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT', + 'DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK', + 'DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT', + 'DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK', + 'DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT', + 'DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK', + 'DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT', + 'DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK', + 'DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT', + 'DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK', + 'DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT', + 'DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK', + 'DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT', + 'DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK', + 'DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT', + 'DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK', + 'DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT', + 'DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK', + 'DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT', + 'DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'DB_PRELOAD_CONTROL__MAX_X_MASK', + 'DB_PRELOAD_CONTROL__MAX_X__SHIFT', + 'DB_PRELOAD_CONTROL__MAX_Y_MASK', + 'DB_PRELOAD_CONTROL__MAX_Y__SHIFT', + 'DB_PRELOAD_CONTROL__START_X_MASK', + 'DB_PRELOAD_CONTROL__START_X__SHIFT', + 'DB_PRELOAD_CONTROL__START_Y_MASK', + 'DB_PRELOAD_CONTROL__START_Y__SHIFT', + 'DB_RENDER_CONTROL__COPY_CENTROID_MASK', + 'DB_RENDER_CONTROL__COPY_CENTROID__SHIFT', + 'DB_RENDER_CONTROL__COPY_SAMPLE_MASK', + 'DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT', + 'DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK', + 'DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT', + 'DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK', + 'DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT', + 'DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK', + 'DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT', + 'DB_RENDER_CONTROL__DEPTH_COPY_MASK', + 'DB_RENDER_CONTROL__DEPTH_COPY__SHIFT', + 'DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK', + 'DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT', + 'DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK', + 'DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT', + 'DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK', + 'DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT', + 'DB_RENDER_CONTROL__STENCIL_COPY_MASK', + 'DB_RENDER_CONTROL__STENCIL_COPY__SHIFT', + 'DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK', + 'DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT', + 'DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK', + 'DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT', + 'DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK', + 'DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT', + 'DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK', + 'DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT', + 'DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK', + 'DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT', + 'DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK', + 'DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT', + 'DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK', + 'DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT', + 'DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK', + 'DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT', + 'DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK', + 'DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT', + 'DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK', + 'DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT', + 'DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK', + 'DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT', + 'DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK', + 'DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT', + 'DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK', + 'DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT', + 'DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK', + 'DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT', + 'DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK', + 'DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT', + 'DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK', + 'DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT', + 'DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK', + 'DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT', + 'DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK', + 'DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT', + 'DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK', + 'DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT', + 'DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK', + 'DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT', + 'DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK', + 'DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK', + 'DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK', + 'DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK', + 'DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK', + 'DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK', + 'DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK', + 'DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK', + 'DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK', + 'DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK', + 'DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK', + 'DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK', + 'DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK', + 'DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK', + 'DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT', + 'DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK', + 'DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT', + 'DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK', + 'DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT', + 'DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK', + 'DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT', + 'DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK', + 'DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT', + 'DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK', + 'DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT', + 'DB_RING_CONTROL__COUNTER_CONTROL_MASK', + 'DB_RING_CONTROL__COUNTER_CONTROL__SHIFT', + 'DB_RMI_CACHE_POLICY__CC_RD_MASK', + 'DB_RMI_CACHE_POLICY__CC_RD__SHIFT', + 'DB_RMI_CACHE_POLICY__CC_WR_MASK', + 'DB_RMI_CACHE_POLICY__CC_WR__SHIFT', + 'DB_RMI_CACHE_POLICY__CMASK_RD_MASK', + 'DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT', + 'DB_RMI_CACHE_POLICY__CMASK_WR_MASK', + 'DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT', + 'DB_RMI_CACHE_POLICY__DCC_RD_MASK', + 'DB_RMI_CACHE_POLICY__DCC_RD__SHIFT', + 'DB_RMI_CACHE_POLICY__DCC_WR_MASK', + 'DB_RMI_CACHE_POLICY__DCC_WR__SHIFT', + 'DB_RMI_CACHE_POLICY__FMASK_RD_MASK', + 'DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT', + 'DB_RMI_CACHE_POLICY__FMASK_WR_MASK', + 'DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT', + 'DB_RMI_CACHE_POLICY__HTILE_RD_MASK', + 'DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT', + 'DB_RMI_CACHE_POLICY__HTILE_WR_MASK', + 'DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT', + 'DB_RMI_CACHE_POLICY__S_RD_MASK', + 'DB_RMI_CACHE_POLICY__S_RD__SHIFT', + 'DB_RMI_CACHE_POLICY__S_WR_MASK', + 'DB_RMI_CACHE_POLICY__S_WR__SHIFT', + 'DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK', + 'DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT', + 'DB_RMI_CACHE_POLICY__Z_RD_MASK', + 'DB_RMI_CACHE_POLICY__Z_RD__SHIFT', + 'DB_RMI_CACHE_POLICY__Z_WR_MASK', + 'DB_RMI_CACHE_POLICY__Z_WR__SHIFT', + 'DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK', + 'DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT', + 'DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK', + 'DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT', + 'DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK', + 'DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT', + 'DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK', + 'DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT', + 'DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK', + 'DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT', + 'DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK', + 'DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT', + 'DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK', + 'DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT', + 'DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK', + 'DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT', + 'DB_SHADER_CONTROL__KILL_ENABLE_MASK', + 'DB_SHADER_CONTROL__KILL_ENABLE__SHIFT', + 'DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK', + 'DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT', + 'DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK', + 'DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT', + 'DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK', + 'DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT', + 'DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK', + 'DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT', + 'DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK', + 'DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT', + 'DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK', + 'DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT', + 'DB_SHADER_CONTROL__Z_ORDER_MASK', + 'DB_SHADER_CONTROL__Z_ORDER__SHIFT', + 'DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK', + 'DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT', + 'DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK', + 'DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT', + 'DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK', + 'DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT', + 'DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK', + 'DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT', + 'DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK', + 'DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT', + 'DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK', + 'DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT', + 'DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK', + 'DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT', + 'DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK', + 'DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT', + 'DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK', + 'DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT', + 'DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK', + 'DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT', + 'DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK', + 'DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT', + 'DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK', + 'DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT', + 'DB_STENCILREFMASK__STENCILMASK_MASK', + 'DB_STENCILREFMASK__STENCILMASK__SHIFT', + 'DB_STENCILREFMASK__STENCILOPVAL_MASK', + 'DB_STENCILREFMASK__STENCILOPVAL__SHIFT', + 'DB_STENCILREFMASK__STENCILTESTVAL_MASK', + 'DB_STENCILREFMASK__STENCILTESTVAL__SHIFT', + 'DB_STENCILREFMASK__STENCILWRITEMASK_MASK', + 'DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT', + 'DB_STENCIL_CLEAR__CLEAR_MASK', 'DB_STENCIL_CLEAR__CLEAR__SHIFT', + 'DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK', + 'DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT', + 'DB_STENCIL_CONTROL__STENCILFAIL_MASK', + 'DB_STENCIL_CONTROL__STENCILFAIL__SHIFT', + 'DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK', + 'DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT', + 'DB_STENCIL_CONTROL__STENCILZFAIL_MASK', + 'DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT', + 'DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK', + 'DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT', + 'DB_STENCIL_CONTROL__STENCILZPASS_MASK', + 'DB_STENCIL_CONTROL__STENCILZPASS__SHIFT', + 'DB_STENCIL_INFO2__EPITCH_MASK', + 'DB_STENCIL_INFO2__EPITCH__SHIFT', + 'DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK', + 'DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT', + 'DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK', + 'DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT', + 'DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK', + 'DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT', + 'DB_STENCIL_INFO__FORMAT_MASK', 'DB_STENCIL_INFO__FORMAT__SHIFT', + 'DB_STENCIL_INFO__ITERATE_FLUSH_MASK', + 'DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT', + 'DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK', + 'DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT', + 'DB_STENCIL_INFO__SW_MODE_MASK', + 'DB_STENCIL_INFO__SW_MODE__SHIFT', + 'DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK', + 'DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT', + 'DB_STENCIL_READ_BASE_HI__BASE_HI_MASK', + 'DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT', + 'DB_STENCIL_READ_BASE__BASE_256B_MASK', + 'DB_STENCIL_READ_BASE__BASE_256B__SHIFT', + 'DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK', + 'DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT', + 'DB_STENCIL_WRITE_BASE__BASE_256B_MASK', + 'DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT', + 'DB_SUBTILE_CONTROL__MSAA16_X_MASK', + 'DB_SUBTILE_CONTROL__MSAA16_X__SHIFT', + 'DB_SUBTILE_CONTROL__MSAA16_Y_MASK', + 'DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT', + 'DB_SUBTILE_CONTROL__MSAA1_X_MASK', + 'DB_SUBTILE_CONTROL__MSAA1_X__SHIFT', + 'DB_SUBTILE_CONTROL__MSAA1_Y_MASK', + 'DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT', + 'DB_SUBTILE_CONTROL__MSAA2_X_MASK', + 'DB_SUBTILE_CONTROL__MSAA2_X__SHIFT', + 'DB_SUBTILE_CONTROL__MSAA2_Y_MASK', + 'DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT', + 'DB_SUBTILE_CONTROL__MSAA4_X_MASK', + 'DB_SUBTILE_CONTROL__MSAA4_X__SHIFT', + 'DB_SUBTILE_CONTROL__MSAA4_Y_MASK', + 'DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT', + 'DB_SUBTILE_CONTROL__MSAA8_X_MASK', + 'DB_SUBTILE_CONTROL__MSAA8_X__SHIFT', + 'DB_SUBTILE_CONTROL__MSAA8_Y_MASK', + 'DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT', + 'DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK', + 'DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT', + 'DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK', + 'DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT', + 'DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK', + 'DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT', + 'DB_WATERMARKS__DEPTH_FLUSH_MASK', + 'DB_WATERMARKS__DEPTH_FLUSH__SHIFT', + 'DB_WATERMARKS__DEPTH_FREE_MASK', + 'DB_WATERMARKS__DEPTH_FREE__SHIFT', + 'DB_WATERMARKS__DEPTH_PENDING_FREE_MASK', + 'DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT', + 'DB_WATERMARKS__FORCE_SUMMARIZE_MASK', + 'DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT', + 'DB_ZPASS_COUNT_HI__COUNT_HI_MASK', + 'DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT', + 'DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK', + 'DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT', 'DB_Z_INFO2__EPITCH_MASK', + 'DB_Z_INFO2__EPITCH__SHIFT', 'DB_Z_INFO__ALLOW_EXPCLEAR_MASK', + 'DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT', + 'DB_Z_INFO__CLEAR_DISALLOWED_MASK', + 'DB_Z_INFO__CLEAR_DISALLOWED__SHIFT', + 'DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK', + 'DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT', + 'DB_Z_INFO__FAULT_BEHAVIOR_MASK', + 'DB_Z_INFO__FAULT_BEHAVIOR__SHIFT', 'DB_Z_INFO__FORMAT_MASK', + 'DB_Z_INFO__FORMAT__SHIFT', 'DB_Z_INFO__ITERATE_FLUSH_MASK', + 'DB_Z_INFO__ITERATE_FLUSH__SHIFT', 'DB_Z_INFO__MAXMIP_MASK', + 'DB_Z_INFO__MAXMIP__SHIFT', 'DB_Z_INFO__NUM_SAMPLES_MASK', + 'DB_Z_INFO__NUM_SAMPLES__SHIFT', + 'DB_Z_INFO__PARTIALLY_RESIDENT_MASK', + 'DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT', + 'DB_Z_INFO__READ_SIZE_MASK', 'DB_Z_INFO__READ_SIZE__SHIFT', + 'DB_Z_INFO__SW_MODE_MASK', 'DB_Z_INFO__SW_MODE__SHIFT', + 'DB_Z_INFO__TILE_SURFACE_ENABLE_MASK', + 'DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT', + 'DB_Z_INFO__ZRANGE_PRECISION_MASK', + 'DB_Z_INFO__ZRANGE_PRECISION__SHIFT', + 'DB_Z_READ_BASE_HI__BASE_HI_MASK', + 'DB_Z_READ_BASE_HI__BASE_HI__SHIFT', + 'DB_Z_READ_BASE__BASE_256B_MASK', + 'DB_Z_READ_BASE__BASE_256B__SHIFT', + 'DB_Z_WRITE_BASE_HI__BASE_HI_MASK', + 'DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT', + 'DB_Z_WRITE_BASE__BASE_256B_MASK', + 'DB_Z_WRITE_BASE__BASE_256B__SHIFT', + 'GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK', + 'GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT', + 'GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK', + 'GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT', + 'GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK', + 'GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT', + 'GB_ADDR_CONFIG_READ__NUM_BANKS_MASK', + 'GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT', + 'GB_ADDR_CONFIG_READ__NUM_GPUS_MASK', + 'GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT', + 'GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK', + 'GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT', + 'GB_ADDR_CONFIG_READ__NUM_PIPES_MASK', + 'GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT', + 'GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK', + 'GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT', + 'GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK', + 'GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT', + 'GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK', + 'GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT', + 'GB_ADDR_CONFIG_READ__ROW_SIZE_MASK', + 'GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT', + 'GB_ADDR_CONFIG_READ__SE_ENABLE_MASK', + 'GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT', + 'GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK', + 'GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT', + 'GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK', + 'GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT', + 'GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK', + 'GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT', + 'GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK', + 'GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT', + 'GB_ADDR_CONFIG__NUM_BANKS_MASK', + 'GB_ADDR_CONFIG__NUM_BANKS__SHIFT', + 'GB_ADDR_CONFIG__NUM_GPUS_MASK', + 'GB_ADDR_CONFIG__NUM_GPUS__SHIFT', + 'GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK', + 'GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT', + 'GB_ADDR_CONFIG__NUM_PIPES_MASK', + 'GB_ADDR_CONFIG__NUM_PIPES__SHIFT', + 'GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK', + 'GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT', + 'GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK', + 'GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT', + 'GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK', + 'GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT', + 'GB_ADDR_CONFIG__ROW_SIZE_MASK', + 'GB_ADDR_CONFIG__ROW_SIZE__SHIFT', + 'GB_ADDR_CONFIG__SE_ENABLE_MASK', + 'GB_ADDR_CONFIG__SE_ENABLE__SHIFT', + 'GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK', + 'GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT', + 'GB_BACKEND_MAP__BACKEND_MAP_MASK', + 'GB_BACKEND_MAP__BACKEND_MAP__SHIFT', 'GB_EDC_MODE__BYPASS_MASK', + 'GB_EDC_MODE__BYPASS__SHIFT', 'GB_EDC_MODE__COUNT_FED_OUT_MASK', + 'GB_EDC_MODE__COUNT_FED_OUT__SHIFT', 'GB_EDC_MODE__DED_MODE_MASK', + 'GB_EDC_MODE__DED_MODE__SHIFT', + 'GB_EDC_MODE__FORCE_SEC_ON_DED_MASK', + 'GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT', + 'GB_EDC_MODE__GATE_FUE_MASK', 'GB_EDC_MODE__GATE_FUE__SHIFT', + 'GB_EDC_MODE__PROP_FED_MASK', 'GB_EDC_MODE__PROP_FED__SHIFT', + 'GB_GPU_ID__GPU_ID_MASK', 'GB_GPU_ID__GPU_ID__SHIFT', + 'GB_MACROTILE_MODE0__BANK_HEIGHT_MASK', + 'GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT', + 'GB_MACROTILE_MODE0__BANK_WIDTH_MASK', + 'GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT', + 'GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK', + 'GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT', + 'GB_MACROTILE_MODE0__NUM_BANKS_MASK', + 'GB_MACROTILE_MODE0__NUM_BANKS__SHIFT', + 'GB_MACROTILE_MODE10__BANK_HEIGHT_MASK', + 'GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT', + 'GB_MACROTILE_MODE10__BANK_WIDTH_MASK', + 'GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT', + 'GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK', + 'GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT', + 'GB_MACROTILE_MODE10__NUM_BANKS_MASK', + 'GB_MACROTILE_MODE10__NUM_BANKS__SHIFT', + 'GB_MACROTILE_MODE11__BANK_HEIGHT_MASK', + 'GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT', + 'GB_MACROTILE_MODE11__BANK_WIDTH_MASK', + 'GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT', + 'GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK', + 'GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT', + 'GB_MACROTILE_MODE11__NUM_BANKS_MASK', + 'GB_MACROTILE_MODE11__NUM_BANKS__SHIFT', + 'GB_MACROTILE_MODE12__BANK_HEIGHT_MASK', + 'GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT', + 'GB_MACROTILE_MODE12__BANK_WIDTH_MASK', + 'GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT', + 'GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK', + 'GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT', + 'GB_MACROTILE_MODE12__NUM_BANKS_MASK', + 'GB_MACROTILE_MODE12__NUM_BANKS__SHIFT', + 'GB_MACROTILE_MODE13__BANK_HEIGHT_MASK', + 'GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT', + 'GB_MACROTILE_MODE13__BANK_WIDTH_MASK', + 'GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT', + 'GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK', + 'GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT', + 'GB_MACROTILE_MODE13__NUM_BANKS_MASK', + 'GB_MACROTILE_MODE13__NUM_BANKS__SHIFT', + 'GB_MACROTILE_MODE14__BANK_HEIGHT_MASK', + 'GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT', + 'GB_MACROTILE_MODE14__BANK_WIDTH_MASK', + 'GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT', + 'GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK', + 'GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT', + 'GB_MACROTILE_MODE14__NUM_BANKS_MASK', + 'GB_MACROTILE_MODE14__NUM_BANKS__SHIFT', + 'GB_MACROTILE_MODE15__BANK_HEIGHT_MASK', + 'GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT', + 'GB_MACROTILE_MODE15__BANK_WIDTH_MASK', + 'GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT', + 'GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK', + 'GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT', + 'GB_MACROTILE_MODE15__NUM_BANKS_MASK', + 'GB_MACROTILE_MODE15__NUM_BANKS__SHIFT', + 'GB_MACROTILE_MODE1__BANK_HEIGHT_MASK', + 'GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT', + 'GB_MACROTILE_MODE1__BANK_WIDTH_MASK', + 'GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT', + 'GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK', + 'GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT', + 'GB_MACROTILE_MODE1__NUM_BANKS_MASK', + 'GB_MACROTILE_MODE1__NUM_BANKS__SHIFT', + 'GB_MACROTILE_MODE2__BANK_HEIGHT_MASK', + 'GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT', + 'GB_MACROTILE_MODE2__BANK_WIDTH_MASK', + 'GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT', + 'GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK', + 'GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT', + 'GB_MACROTILE_MODE2__NUM_BANKS_MASK', + 'GB_MACROTILE_MODE2__NUM_BANKS__SHIFT', + 'GB_MACROTILE_MODE3__BANK_HEIGHT_MASK', + 'GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT', + 'GB_MACROTILE_MODE3__BANK_WIDTH_MASK', + 'GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT', + 'GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK', + 'GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT', + 'GB_MACROTILE_MODE3__NUM_BANKS_MASK', + 'GB_MACROTILE_MODE3__NUM_BANKS__SHIFT', + 'GB_MACROTILE_MODE4__BANK_HEIGHT_MASK', + 'GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT', + 'GB_MACROTILE_MODE4__BANK_WIDTH_MASK', + 'GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT', + 'GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK', + 'GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT', + 'GB_MACROTILE_MODE4__NUM_BANKS_MASK', + 'GB_MACROTILE_MODE4__NUM_BANKS__SHIFT', + 'GB_MACROTILE_MODE5__BANK_HEIGHT_MASK', + 'GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT', + 'GB_MACROTILE_MODE5__BANK_WIDTH_MASK', + 'GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT', + 'GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK', + 'GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT', + 'GB_MACROTILE_MODE5__NUM_BANKS_MASK', + 'GB_MACROTILE_MODE5__NUM_BANKS__SHIFT', + 'GB_MACROTILE_MODE6__BANK_HEIGHT_MASK', + 'GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT', + 'GB_MACROTILE_MODE6__BANK_WIDTH_MASK', + 'GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT', + 'GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK', + 'GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT', + 'GB_MACROTILE_MODE6__NUM_BANKS_MASK', + 'GB_MACROTILE_MODE6__NUM_BANKS__SHIFT', + 'GB_MACROTILE_MODE7__BANK_HEIGHT_MASK', + 'GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT', + 'GB_MACROTILE_MODE7__BANK_WIDTH_MASK', + 'GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT', + 'GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK', + 'GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT', + 'GB_MACROTILE_MODE7__NUM_BANKS_MASK', + 'GB_MACROTILE_MODE7__NUM_BANKS__SHIFT', + 'GB_MACROTILE_MODE8__BANK_HEIGHT_MASK', + 'GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT', + 'GB_MACROTILE_MODE8__BANK_WIDTH_MASK', + 'GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT', + 'GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK', + 'GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT', + 'GB_MACROTILE_MODE8__NUM_BANKS_MASK', + 'GB_MACROTILE_MODE8__NUM_BANKS__SHIFT', + 'GB_MACROTILE_MODE9__BANK_HEIGHT_MASK', + 'GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT', + 'GB_MACROTILE_MODE9__BANK_WIDTH_MASK', + 'GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT', + 'GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK', + 'GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT', + 'GB_MACROTILE_MODE9__NUM_BANKS_MASK', + 'GB_MACROTILE_MODE9__NUM_BANKS__SHIFT', + 'GB_TILE_MODE0__ARRAY_MODE_MASK', + 'GB_TILE_MODE0__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE0__PIPE_CONFIG_MASK', + 'GB_TILE_MODE0__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE0__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE0__TILE_SPLIT_MASK', + 'GB_TILE_MODE0__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE10__ARRAY_MODE_MASK', + 'GB_TILE_MODE10__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE10__PIPE_CONFIG_MASK', + 'GB_TILE_MODE10__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE10__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE10__TILE_SPLIT_MASK', + 'GB_TILE_MODE10__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE11__ARRAY_MODE_MASK', + 'GB_TILE_MODE11__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE11__PIPE_CONFIG_MASK', + 'GB_TILE_MODE11__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE11__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE11__TILE_SPLIT_MASK', + 'GB_TILE_MODE11__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE12__ARRAY_MODE_MASK', + 'GB_TILE_MODE12__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE12__PIPE_CONFIG_MASK', + 'GB_TILE_MODE12__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE12__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE12__TILE_SPLIT_MASK', + 'GB_TILE_MODE12__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE13__ARRAY_MODE_MASK', + 'GB_TILE_MODE13__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE13__PIPE_CONFIG_MASK', + 'GB_TILE_MODE13__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE13__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE13__TILE_SPLIT_MASK', + 'GB_TILE_MODE13__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE14__ARRAY_MODE_MASK', + 'GB_TILE_MODE14__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE14__PIPE_CONFIG_MASK', + 'GB_TILE_MODE14__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE14__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE14__TILE_SPLIT_MASK', + 'GB_TILE_MODE14__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE15__ARRAY_MODE_MASK', + 'GB_TILE_MODE15__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE15__PIPE_CONFIG_MASK', + 'GB_TILE_MODE15__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE15__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE15__TILE_SPLIT_MASK', + 'GB_TILE_MODE15__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE16__ARRAY_MODE_MASK', + 'GB_TILE_MODE16__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE16__PIPE_CONFIG_MASK', + 'GB_TILE_MODE16__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE16__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE16__TILE_SPLIT_MASK', + 'GB_TILE_MODE16__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE17__ARRAY_MODE_MASK', + 'GB_TILE_MODE17__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE17__PIPE_CONFIG_MASK', + 'GB_TILE_MODE17__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE17__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE17__TILE_SPLIT_MASK', + 'GB_TILE_MODE17__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE18__ARRAY_MODE_MASK', + 'GB_TILE_MODE18__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE18__PIPE_CONFIG_MASK', + 'GB_TILE_MODE18__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE18__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE18__TILE_SPLIT_MASK', + 'GB_TILE_MODE18__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE19__ARRAY_MODE_MASK', + 'GB_TILE_MODE19__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE19__PIPE_CONFIG_MASK', + 'GB_TILE_MODE19__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE19__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE19__TILE_SPLIT_MASK', + 'GB_TILE_MODE19__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE1__ARRAY_MODE_MASK', + 'GB_TILE_MODE1__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE1__PIPE_CONFIG_MASK', + 'GB_TILE_MODE1__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE1__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE1__TILE_SPLIT_MASK', + 'GB_TILE_MODE1__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE20__ARRAY_MODE_MASK', + 'GB_TILE_MODE20__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE20__PIPE_CONFIG_MASK', + 'GB_TILE_MODE20__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE20__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE20__TILE_SPLIT_MASK', + 'GB_TILE_MODE20__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE21__ARRAY_MODE_MASK', + 'GB_TILE_MODE21__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE21__PIPE_CONFIG_MASK', + 'GB_TILE_MODE21__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE21__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE21__TILE_SPLIT_MASK', + 'GB_TILE_MODE21__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE22__ARRAY_MODE_MASK', + 'GB_TILE_MODE22__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE22__PIPE_CONFIG_MASK', + 'GB_TILE_MODE22__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE22__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE22__TILE_SPLIT_MASK', + 'GB_TILE_MODE22__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE23__ARRAY_MODE_MASK', + 'GB_TILE_MODE23__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE23__PIPE_CONFIG_MASK', + 'GB_TILE_MODE23__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE23__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE23__TILE_SPLIT_MASK', + 'GB_TILE_MODE23__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE24__ARRAY_MODE_MASK', + 'GB_TILE_MODE24__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE24__PIPE_CONFIG_MASK', + 'GB_TILE_MODE24__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE24__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE24__TILE_SPLIT_MASK', + 'GB_TILE_MODE24__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE25__ARRAY_MODE_MASK', + 'GB_TILE_MODE25__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE25__PIPE_CONFIG_MASK', + 'GB_TILE_MODE25__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE25__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE25__TILE_SPLIT_MASK', + 'GB_TILE_MODE25__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE26__ARRAY_MODE_MASK', + 'GB_TILE_MODE26__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE26__PIPE_CONFIG_MASK', + 'GB_TILE_MODE26__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE26__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE26__TILE_SPLIT_MASK', + 'GB_TILE_MODE26__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE27__ARRAY_MODE_MASK', + 'GB_TILE_MODE27__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE27__PIPE_CONFIG_MASK', + 'GB_TILE_MODE27__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE27__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE27__TILE_SPLIT_MASK', + 'GB_TILE_MODE27__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE28__ARRAY_MODE_MASK', + 'GB_TILE_MODE28__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE28__PIPE_CONFIG_MASK', + 'GB_TILE_MODE28__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE28__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE28__TILE_SPLIT_MASK', + 'GB_TILE_MODE28__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE29__ARRAY_MODE_MASK', + 'GB_TILE_MODE29__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE29__PIPE_CONFIG_MASK', + 'GB_TILE_MODE29__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE29__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE29__TILE_SPLIT_MASK', + 'GB_TILE_MODE29__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE2__ARRAY_MODE_MASK', + 'GB_TILE_MODE2__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE2__PIPE_CONFIG_MASK', + 'GB_TILE_MODE2__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE2__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE2__TILE_SPLIT_MASK', + 'GB_TILE_MODE2__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE30__ARRAY_MODE_MASK', + 'GB_TILE_MODE30__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE30__PIPE_CONFIG_MASK', + 'GB_TILE_MODE30__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE30__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE30__TILE_SPLIT_MASK', + 'GB_TILE_MODE30__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE31__ARRAY_MODE_MASK', + 'GB_TILE_MODE31__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE31__PIPE_CONFIG_MASK', + 'GB_TILE_MODE31__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE31__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE31__TILE_SPLIT_MASK', + 'GB_TILE_MODE31__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE3__ARRAY_MODE_MASK', + 'GB_TILE_MODE3__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE3__PIPE_CONFIG_MASK', + 'GB_TILE_MODE3__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE3__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE3__TILE_SPLIT_MASK', + 'GB_TILE_MODE3__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE4__ARRAY_MODE_MASK', + 'GB_TILE_MODE4__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE4__PIPE_CONFIG_MASK', + 'GB_TILE_MODE4__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE4__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE4__TILE_SPLIT_MASK', + 'GB_TILE_MODE4__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE5__ARRAY_MODE_MASK', + 'GB_TILE_MODE5__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE5__PIPE_CONFIG_MASK', + 'GB_TILE_MODE5__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE5__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE5__TILE_SPLIT_MASK', + 'GB_TILE_MODE5__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE6__ARRAY_MODE_MASK', + 'GB_TILE_MODE6__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE6__PIPE_CONFIG_MASK', + 'GB_TILE_MODE6__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE6__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE6__TILE_SPLIT_MASK', + 'GB_TILE_MODE6__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE7__ARRAY_MODE_MASK', + 'GB_TILE_MODE7__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE7__PIPE_CONFIG_MASK', + 'GB_TILE_MODE7__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE7__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE7__TILE_SPLIT_MASK', + 'GB_TILE_MODE7__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE8__ARRAY_MODE_MASK', + 'GB_TILE_MODE8__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE8__PIPE_CONFIG_MASK', + 'GB_TILE_MODE8__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE8__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE8__TILE_SPLIT_MASK', + 'GB_TILE_MODE8__TILE_SPLIT__SHIFT', + 'GB_TILE_MODE9__ARRAY_MODE_MASK', + 'GB_TILE_MODE9__ARRAY_MODE__SHIFT', + 'GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK', + 'GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT', + 'GB_TILE_MODE9__PIPE_CONFIG_MASK', + 'GB_TILE_MODE9__PIPE_CONFIG__SHIFT', + 'GB_TILE_MODE9__SAMPLE_SPLIT_MASK', + 'GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT', + 'GB_TILE_MODE9__TILE_SPLIT_MASK', + 'GB_TILE_MODE9__TILE_SPLIT__SHIFT', + 'GCEA_CE_ERR_STATUS_HI__CE_CNT_MASK', + 'GCEA_CE_ERR_STATUS_HI__CE_CNT__SHIFT', + 'GCEA_CE_ERR_STATUS_HI__ECC_MASK', + 'GCEA_CE_ERR_STATUS_HI__ECC__SHIFT', + 'GCEA_CE_ERR_STATUS_HI__ERR_INFO_MASK', + 'GCEA_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'GCEA_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'GCEA_CE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'GCEA_CE_ERR_STATUS_HI__POISON_MASK', + 'GCEA_CE_ERR_STATUS_HI__POISON__SHIFT', + 'GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD0_MASK', + 'GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD0__SHIFT', + 'GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD1_MASK', + 'GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD1__SHIFT', + 'GCEA_CE_ERR_STATUS_LO__ADDRESS_MASK', + 'GCEA_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'GCEA_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'GCEA_CE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'GCEA_CE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'GCEA_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'GCEA_CE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK', + 'GCEA_CE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT', + 'GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK', + 'GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT', + 'GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK', + 'GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT', + 'GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK', + 'GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT', + 'GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK', + 'GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT', + 'GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK', + 'GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT', + 'GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK', + 'GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT', + 'GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK', + 'GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT', + 'GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK', + 'GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT', + 'GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK', + 'GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT', + 'GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK', + 'GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT', + 'GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK', + 'GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT', + 'GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK', + 'GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT', + 'GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK', + 'GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK', + 'GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT', + 'GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK', + 'GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT', + 'GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK', + 'GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT', + 'GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK', + 'GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT', + 'GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK', + 'GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT', + 'GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK', + 'GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT', + 'GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK', + 'GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT', + 'GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK', + 'GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT', + 'GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK', + 'GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT', + 'GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK', + 'GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT', + 'GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK', + 'GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT', + 'GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK', + 'GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT', + 'GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK', + 'GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT', + 'GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK', + 'GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT', + 'GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK', + 'GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT', + 'GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK', + 'GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT', + 'GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK', + 'GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT', + 'GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK', + 'GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT', + 'GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK', + 'GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT', + 'GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK', + 'GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT', + 'GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK', + 'GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT', + 'GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK', + 'GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT', + 'GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK', + 'GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT', + 'GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK', + 'GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT', + 'GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK', + 'GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT', + 'GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK', + 'GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT', + 'GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK', + 'GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK', + 'GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT', + 'GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK', + 'GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT', + 'GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK', + 'GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT', + 'GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK', + 'GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT', + 'GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK', + 'GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT', + 'GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK', + 'GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT', + 'GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK', + 'GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT', + 'GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK', + 'GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT', + 'GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK', + 'GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT', + 'GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK', + 'GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT', + 'GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK', + 'GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT', + 'GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK', + 'GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT', + 'GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK', + 'GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT', + 'GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK', + 'GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT', + 'GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK', + 'GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT', + 'GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK', + 'GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT', + 'GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK', + 'GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT', + 'GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK', + 'GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT', + 'GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2B__MAM_A0MEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2B__MAM_A0MEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2B__MAM_A0MEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2B__MAM_A0MEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2B__MAM_A1MEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2B__MAM_A1MEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2B__MAM_A1MEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2B__MAM_A1MEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2B__MAM_A2MEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2B__MAM_A2MEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2B__MAM_A2MEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2B__MAM_A2MEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2B__MAM_A3MEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2B__MAM_A3MEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2B__MAM_A3MEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2B__MAM_A3MEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2B__MAM_AFMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2B__MAM_AFMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2B__MAM_AFMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2B__MAM_AFMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2__INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK', + 'GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT', + 'GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK', + 'GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT', + 'GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTLB__MAM_A0MEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLB__MAM_A0MEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLB__MAM_A0MEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLB__MAM_A0MEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTLB__MAM_A1MEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLB__MAM_A1MEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLB__MAM_A1MEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLB__MAM_A1MEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTLB__MAM_A2MEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLB__MAM_A2MEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLB__MAM_A2MEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLB__MAM_A2MEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTLB__MAM_A3MEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLB__MAM_A3MEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLB__MAM_A3MEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLB__MAM_A3MEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTLB__MAM_AFMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLB__MAM_AFMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLB__MAM_AFMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLB__MAM_AFMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK', + 'GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT', + 'GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK', + 'GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GCEA_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK', + 'GCEA_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT', + 'GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK', + 'GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT', + 'GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK', + 'GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT', + 'GCEA_ERR_STATUS__FUE_FLAG_CLIENT_MASK', + 'GCEA_ERR_STATUS__FUE_FLAG_CLIENT__SHIFT', + 'GCEA_ERR_STATUS__FUE_FLAG_MASK', + 'GCEA_ERR_STATUS__FUE_FLAG__SHIFT', + 'GCEA_ERR_STATUS__IGNORE_RDRSP_FED_MASK', + 'GCEA_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT', + 'GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK', + 'GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT', + 'GCEA_ERR_STATUS__INTERRUPT_ON_FATAL_MASK', + 'GCEA_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT', + 'GCEA_ERR_STATUS__LEVEL_INTERRUPT_MASK', + 'GCEA_ERR_STATUS__LEVEL_INTERRUPT__SHIFT', + 'GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK', + 'GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT', + 'GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK', + 'GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT', + 'GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK', + 'GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT', + 'GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK', + 'GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT', + 'GCEA_ICG_CTRL__SOFT_OVERRIDE_READ_MASK', + 'GCEA_ICG_CTRL__SOFT_OVERRIDE_READ__SHIFT', + 'GCEA_ICG_CTRL__SOFT_OVERRIDE_REGISTER_MASK', + 'GCEA_ICG_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT', + 'GCEA_ICG_CTRL__SOFT_OVERRIDE_RETURN_MASK', + 'GCEA_ICG_CTRL__SOFT_OVERRIDE_RETURN__SHIFT', + 'GCEA_ICG_CTRL__SOFT_OVERRIDE_WRITE_MASK', + 'GCEA_ICG_CTRL__SOFT_OVERRIDE_WRITE__SHIFT', + 'GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK', + 'GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT', + 'GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK', + 'GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT', + 'GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK', + 'GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT', + 'GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK', + 'GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK', + 'GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT', + 'GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK', + 'GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT', + 'GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK', + 'GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT', + 'GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK', + 'GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT', + 'GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK', + 'GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT', + 'GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK', + 'GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT', + 'GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK', + 'GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT', + 'GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK', + 'GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT', + 'GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK', + 'GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT', + 'GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK', + 'GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT', + 'GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK', + 'GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT', + 'GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK', + 'GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK', + 'GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK', + 'GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK', + 'GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK', + 'GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK', + 'GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK', + 'GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT', + 'GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK', + 'GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT', + 'GCEA_IO_WR_COMBINE_FLUSH__DISABLE_MAM_CHAINING_MASK', + 'GCEA_IO_WR_COMBINE_FLUSH__DISABLE_MAM_CHAINING__SHIFT', + 'GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK', + 'GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT', + 'GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK', + 'GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT', + 'GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK', + 'GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT', + 'GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK', + 'GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT', + 'GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK', + 'GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT', + 'GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK', + 'GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT', + 'GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK', + 'GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT', + 'GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK', + 'GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT', + 'GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK', + 'GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT', + 'GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK', + 'GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK', + 'GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK', + 'GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK', + 'GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK', + 'GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT', + 'GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK', + 'GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK', + 'GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT', + 'GCEA_MAM_CTRL2__ADDR_HI_MASK', 'GCEA_MAM_CTRL2__ADDR_HI__SHIFT', + 'GCEA_MAM_CTRL2__ALOG_MODE2_INTR_THRESHOLD_MASK', + 'GCEA_MAM_CTRL2__ALOG_MODE2_INTR_THRESHOLD__SHIFT', + 'GCEA_MAM_CTRL2__ALOG_SPACE_EN_MASK', + 'GCEA_MAM_CTRL2__ALOG_SPACE_EN__SHIFT', + 'GCEA_MAM_CTRL2__ARAM_FLUSH_NOALLOC_MASK', + 'GCEA_MAM_CTRL2__ARAM_FLUSH_NOALLOC__SHIFT', + 'GCEA_MAM_CTRL2__ARAM_FLUSH_SNOOP_EN_MASK', + 'GCEA_MAM_CTRL2__ARAM_FLUSH_SNOOP_EN__SHIFT', + 'GCEA_MAM_CTRL2__RESERVED_FIELD_MASK', + 'GCEA_MAM_CTRL2__RESERVED_FIELD__SHIFT', + 'GCEA_MAM_CTRL__ADRAM_COALESCE_DISABLE_MASK', + 'GCEA_MAM_CTRL__ADRAM_COALESCE_DISABLE__SHIFT', + 'GCEA_MAM_CTRL__ADRAM_MODE_MASK', + 'GCEA_MAM_CTRL__ADRAM_MODE__SHIFT', + 'GCEA_MAM_CTRL__ALOG_ACTIVE_MASK', + 'GCEA_MAM_CTRL__ALOG_ACTIVE__SHIFT', + 'GCEA_MAM_CTRL__ALOG_MODE1_FILTER1_THRESHOLD_MASK', + 'GCEA_MAM_CTRL__ALOG_MODE1_FILTER1_THRESHOLD__SHIFT', + 'GCEA_MAM_CTRL__ALOG_MODE1_FILTER2_BYPASS_MASK', + 'GCEA_MAM_CTRL__ALOG_MODE1_FILTER2_BYPASS__SHIFT', + 'GCEA_MAM_CTRL__ALOG_MODE2_LOCK_WINDOW_MASK', + 'GCEA_MAM_CTRL__ALOG_MODE2_LOCK_WINDOW__SHIFT', + 'GCEA_MAM_CTRL__ALOG_MODE_MASK', + 'GCEA_MAM_CTRL__ALOG_MODE__SHIFT', + 'GCEA_MAM_CTRL__ALOG_TRACK_2M_SEGMENT_MASK', + 'GCEA_MAM_CTRL__ALOG_TRACK_2M_SEGMENT__SHIFT', + 'GCEA_MAM_CTRL__ARAM_FLUSH_CNTR_DISABLE_MASK', + 'GCEA_MAM_CTRL__ARAM_FLUSH_CNTR_DISABLE__SHIFT', + 'GCEA_MAM_CTRL__ARAM_FLUSH_CNTR_THRESHOLD_MASK', + 'GCEA_MAM_CTRL__ARAM_FLUSH_CNTR_THRESHOLD__SHIFT', + 'GCEA_MAM_CTRL__ARAM_FLUSH_RB_SIZE_MASK', + 'GCEA_MAM_CTRL__ARAM_FLUSH_RB_SIZE__SHIFT', + 'GCEA_MAM_CTRL__ARAM_FORCE_FLUSH_MASK', + 'GCEA_MAM_CTRL__ARAM_FORCE_FLUSH__SHIFT', + 'GCEA_MAM_CTRL__CLIENT_ID_MASK', + 'GCEA_MAM_CTRL__CLIENT_ID__SHIFT', + 'GCEA_MAM_CTRL__MAM_DISABLE_MASK', + 'GCEA_MAM_CTRL__MAM_DISABLE__SHIFT', + 'GCEA_MAM_CTRL__SDP_PRIORITY_MASK', + 'GCEA_MAM_CTRL__SDP_PRIORITY__SHIFT', + 'GCEA_MISC2__BLOCK_REQUESTS_MASK', + 'GCEA_MISC2__BLOCK_REQUESTS__SHIFT', + 'GCEA_MISC2__CONTAIN_ILLEGAL_OP_MASK', + 'GCEA_MISC2__CONTAIN_ILLEGAL_OP__SHIFT', + 'GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK', + 'GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT', + 'GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK', + 'GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT', + 'GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK', + 'GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT', + 'GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK', + 'GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT', + 'GCEA_MISC2__DRAM_RD_THROTTLE_MASK', + 'GCEA_MISC2__DRAM_RD_THROTTLE__SHIFT', + 'GCEA_MISC2__DRAM_WR_THROTTLE_MASK', + 'GCEA_MISC2__DRAM_WR_THROTTLE__SHIFT', + 'GCEA_MISC2__FGCLKEN_OVERRIDE_MASK', + 'GCEA_MISC2__FGCLKEN_OVERRIDE__SHIFT', + 'GCEA_MISC2__GMI_RD_THROTTLE_MASK', + 'GCEA_MISC2__GMI_RD_THROTTLE__SHIFT', + 'GCEA_MISC2__GMI_WR_THROTTLE_MASK', + 'GCEA_MISC2__GMI_WR_THROTTLE__SHIFT', + 'GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK', + 'GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT', + 'GCEA_MISC2__REPORT_ILLEGAL_OP_MASK', + 'GCEA_MISC2__REPORT_ILLEGAL_OP__SHIFT', + 'GCEA_MISC2__REQUESTS_BLOCKED_MASK', + 'GCEA_MISC2__REQUESTS_BLOCKED__SHIFT', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK', + 'GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT', + 'GCEA_MISC__EARLY_SDP_ORIGDATA_MASK', + 'GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT', + 'GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK', + 'GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT', + 'GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK', + 'GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT', + 'GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK', + 'GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT', + 'GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK', + 'GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT', + 'GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK', + 'GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT', + 'GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK', + 'GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT', + 'GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK', + 'GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT', + 'GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK', + 'GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT', + 'GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK', + 'GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT', + 'GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK', + 'GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT', + 'GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK', + 'GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT', + 'GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK', + 'GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT', + 'GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK', + 'GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT', + 'GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK', + 'GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT', + 'GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK', + 'GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT', + 'GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK', + 'GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT', + 'GCEA_PERFCOUNTER0_CFG__CLEAR_MASK', + 'GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'GCEA_PERFCOUNTER0_CFG__ENABLE_MASK', + 'GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'GCEA_PERFCOUNTER1_CFG__CLEAR_MASK', + 'GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'GCEA_PERFCOUNTER1_CFG__ENABLE_MASK', + 'GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK', + 'GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT', + 'GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK', + 'GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT', + 'GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC_MASK', + 'GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC__SHIFT', + 'GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC_MASK', + 'GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC__SHIFT', + 'GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC_MASK', + 'GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC__SHIFT', + 'GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC_MASK', + 'GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC__SHIFT', + 'GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC_MASK', + 'GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC__SHIFT', + 'GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC_MASK', + 'GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC__SHIFT', + 'GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC_MASK', + 'GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC__SHIFT', + 'GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC_MASK', + 'GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC__SHIFT', + 'GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC_MASK', + 'GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC__SHIFT', + 'GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC_MASK', + 'GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC__SHIFT', + 'GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC_MASK', + 'GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC__SHIFT', + 'GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC_MASK', + 'GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC__SHIFT', + 'GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC_MASK', + 'GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC__SHIFT', + 'GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC_MASK', + 'GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC__SHIFT', + 'GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC_MASK', + 'GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC__SHIFT', + 'GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC_MASK', + 'GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC__SHIFT', + 'GCEA_PROBE_MAP__INTLV_SIZE_MASK', + 'GCEA_PROBE_MAP__INTLV_SIZE__SHIFT', + 'GCEA_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING_MASK', + 'GCEA_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING__SHIFT', + 'GCEA_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK', + 'GCEA_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT', + 'GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK', + 'GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT', + 'GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK', + 'GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT', + 'GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK', + 'GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT', + 'GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK', + 'GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT', + 'GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK', + 'GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT', + 'GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK', + 'GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT', + 'GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK', + 'GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT', + 'GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK', + 'GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT', + 'GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK', + 'GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT', + 'GCEA_SDP_ARB_FINAL__DRAM_BURST_STRETCH_MASK', + 'GCEA_SDP_ARB_FINAL__DRAM_BURST_STRETCH__SHIFT', + 'GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK', + 'GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT', + 'GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK', + 'GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT', + 'GCEA_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK', + 'GCEA_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT', + 'GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK', + 'GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT', + 'GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK', + 'GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC0_MASK', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC0__SHIFT', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC1_MASK', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC1__SHIFT', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC2_MASK', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC2__SHIFT', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC3_MASK', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC3__SHIFT', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC4_MASK', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC4__SHIFT', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC5_MASK', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC5__SHIFT', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC6_MASK', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC6__SHIFT', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC7_MASK', + 'GCEA_SDP_ARB_FINAL__RDONLY_VC7__SHIFT', + 'GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED_MASK', + 'GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED__SHIFT', + 'GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED_MASK', + 'GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED__SHIFT', + 'GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED_MASK', + 'GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED__SHIFT', + 'GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED_MASK', + 'GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED__SHIFT', + 'GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED_MASK', + 'GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED__SHIFT', + 'GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED_MASK', + 'GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED__SHIFT', + 'GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED_MASK', + 'GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED__SHIFT', + 'GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED_MASK', + 'GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED__SHIFT', + 'GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED_MASK', + 'GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED__SHIFT', + 'GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED_MASK', + 'GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED__SHIFT', + 'GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED_MASK', + 'GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED__SHIFT', + 'GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED_MASK', + 'GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED__SHIFT', + 'GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED_MASK', + 'GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED__SHIFT', + 'GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED_MASK', + 'GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED__SHIFT', + 'GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED_MASK', + 'GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED__SHIFT', + 'GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED_MASK', + 'GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED__SHIFT', + 'GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED_MASK', + 'GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED__SHIFT', + 'GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED_MASK', + 'GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED__SHIFT', + 'GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED_MASK', + 'GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED__SHIFT', + 'GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED_MASK', + 'GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED__SHIFT', + 'GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED_MASK', + 'GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED__SHIFT', + 'GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED_MASK', + 'GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED__SHIFT', + 'GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK', + 'GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT', + 'GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK', + 'GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT', + 'GCEA_SDP_CREDITS__PRB_REQ_CREDITS_MASK', + 'GCEA_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT', + 'GCEA_SDP_CREDITS__RD_RESP_CREDITS_MASK', + 'GCEA_SDP_CREDITS__RD_RESP_CREDITS__SHIFT', + 'GCEA_SDP_CREDITS__TAG_LIMIT_MASK', + 'GCEA_SDP_CREDITS__TAG_LIMIT__SHIFT', + 'GCEA_SDP_CREDITS__WR_RESP_CREDITS_MASK', + 'GCEA_SDP_CREDITS__WR_RESP_CREDITS__SHIFT', + 'GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK', + 'GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT', + 'GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK', + 'GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT', + 'GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK', + 'GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT', + 'GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK', + 'GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT', + 'GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK', + 'GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT', + 'GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK', + 'GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT', + 'GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK', + 'GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT', + 'GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK', + 'GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT', + 'GCEA_SDP_ENABLE__ENABLE_MASK', 'GCEA_SDP_ENABLE__ENABLE__SHIFT', + 'GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK', + 'GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT', + 'GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK', + 'GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT', + 'GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK', + 'GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT', + 'GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK', + 'GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT', + 'GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK', + 'GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT', + 'GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK', + 'GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT', + 'GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK', + 'GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT', + 'GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK', + 'GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT', + 'GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK', + 'GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT', + 'GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK', + 'GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT', + 'GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK', + 'GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT', + 'GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK', + 'GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT', + 'GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK', + 'GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT', + 'GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK', + 'GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT', + 'GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK', + 'GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT', + 'GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK', + 'GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT', + 'GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK', + 'GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT', + 'GCEA_SDP_TAG_RESERVE0__VC0_MASK', + 'GCEA_SDP_TAG_RESERVE0__VC0__SHIFT', + 'GCEA_SDP_TAG_RESERVE0__VC1_MASK', + 'GCEA_SDP_TAG_RESERVE0__VC1__SHIFT', + 'GCEA_SDP_TAG_RESERVE0__VC2_MASK', + 'GCEA_SDP_TAG_RESERVE0__VC2__SHIFT', + 'GCEA_SDP_TAG_RESERVE0__VC3_MASK', + 'GCEA_SDP_TAG_RESERVE0__VC3__SHIFT', + 'GCEA_SDP_TAG_RESERVE1__VC4_MASK', + 'GCEA_SDP_TAG_RESERVE1__VC4__SHIFT', + 'GCEA_SDP_TAG_RESERVE1__VC5_MASK', + 'GCEA_SDP_TAG_RESERVE1__VC5__SHIFT', + 'GCEA_SDP_TAG_RESERVE1__VC6_MASK', + 'GCEA_SDP_TAG_RESERVE1__VC6__SHIFT', + 'GCEA_SDP_TAG_RESERVE1__VC7_MASK', + 'GCEA_SDP_TAG_RESERVE1__VC7__SHIFT', + 'GCEA_SDP_VCC_RESERVE0__VC0_CREDITS_MASK', + 'GCEA_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT', + 'GCEA_SDP_VCC_RESERVE0__VC1_CREDITS_MASK', + 'GCEA_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT', + 'GCEA_SDP_VCC_RESERVE0__VC2_CREDITS_MASK', + 'GCEA_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT', + 'GCEA_SDP_VCC_RESERVE0__VC3_CREDITS_MASK', + 'GCEA_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT', + 'GCEA_SDP_VCC_RESERVE0__VC4_CREDITS_MASK', + 'GCEA_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT', + 'GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK', + 'GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT', + 'GCEA_SDP_VCC_RESERVE1__VC5_CREDITS_MASK', + 'GCEA_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT', + 'GCEA_SDP_VCC_RESERVE1__VC6_CREDITS_MASK', + 'GCEA_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT', + 'GCEA_SDP_VCC_RESERVE1__VC7_CREDITS_MASK', + 'GCEA_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT', + 'GCEA_SDP_VCD_RESERVE0__VC0_CREDITS_MASK', + 'GCEA_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT', + 'GCEA_SDP_VCD_RESERVE0__VC1_CREDITS_MASK', + 'GCEA_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT', + 'GCEA_SDP_VCD_RESERVE0__VC2_CREDITS_MASK', + 'GCEA_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT', + 'GCEA_SDP_VCD_RESERVE0__VC3_CREDITS_MASK', + 'GCEA_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT', + 'GCEA_SDP_VCD_RESERVE0__VC4_CREDITS_MASK', + 'GCEA_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT', + 'GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK', + 'GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT', + 'GCEA_SDP_VCD_RESERVE1__VC5_CREDITS_MASK', + 'GCEA_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT', + 'GCEA_SDP_VCD_RESERVE1__VC6_CREDITS_MASK', + 'GCEA_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT', + 'GCEA_SDP_VCD_RESERVE1__VC7_CREDITS_MASK', + 'GCEA_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT', + 'GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT_MASK', + 'GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT', + 'GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE_MASK', + 'GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT', + 'GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT_MASK', + 'GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT', + 'GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE_MASK', + 'GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT', + 'GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT_MASK', + 'GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT__SHIFT', + 'GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE_MASK', + 'GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE__SHIFT', + 'GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT_MASK', + 'GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT__SHIFT', + 'GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE_MASK', + 'GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE__SHIFT', + 'GCEA_TCC_XBR_MAXBURST__DRAM_RD_MASK', + 'GCEA_TCC_XBR_MAXBURST__DRAM_RD__SHIFT', + 'GCEA_TCC_XBR_MAXBURST__DRAM_WR_MASK', + 'GCEA_TCC_XBR_MAXBURST__DRAM_WR__SHIFT', + 'GCEA_TCC_XBR_MAXBURST__IO_RD_MASK', + 'GCEA_TCC_XBR_MAXBURST__IO_RD__SHIFT', + 'GCEA_TCC_XBR_MAXBURST__IO_WR_MASK', + 'GCEA_TCC_XBR_MAXBURST__IO_WR__SHIFT', + 'GCEA_UE_ERR_STATUS_HI__ECC_MASK', + 'GCEA_UE_ERR_STATUS_HI__ECC__SHIFT', + 'GCEA_UE_ERR_STATUS_HI__ERR_INFO_MASK', + 'GCEA_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'GCEA_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'GCEA_UE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'GCEA_UE_ERR_STATUS_HI__FED_CNT_MASK', + 'GCEA_UE_ERR_STATUS_HI__FED_CNT__SHIFT', + 'GCEA_UE_ERR_STATUS_HI__PARITY_MASK', + 'GCEA_UE_ERR_STATUS_HI__PARITY__SHIFT', + 'GCEA_UE_ERR_STATUS_HI__RESERVED_FIELD_MASK', + 'GCEA_UE_ERR_STATUS_HI__RESERVED_FIELD__SHIFT', + 'GCEA_UE_ERR_STATUS_HI__UE_CNT_MASK', + 'GCEA_UE_ERR_STATUS_HI__UE_CNT__SHIFT', + 'GCEA_UE_ERR_STATUS_LO__ADDRESS_MASK', + 'GCEA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'GCEA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'GCEA_UE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'GCEA_UE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'GCEA_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'GCEA_UE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK', + 'GCEA_UE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT', + 'GC_CANE_CE_ERR_STATUS_HI__CE_CNT_MASK', + 'GC_CANE_CE_ERR_STATUS_HI__CE_CNT__SHIFT', + 'GC_CANE_CE_ERR_STATUS_HI__ECC_MASK', + 'GC_CANE_CE_ERR_STATUS_HI__ECC__SHIFT', + 'GC_CANE_CE_ERR_STATUS_HI__ERR_INFO_MASK', + 'GC_CANE_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'GC_CANE_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'GC_CANE_CE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'GC_CANE_CE_ERR_STATUS_HI__POISON_MASK', + 'GC_CANE_CE_ERR_STATUS_HI__POISON__SHIFT', + 'GC_CANE_CE_ERR_STATUS_LO__ADDRESS_MASK', + 'GC_CANE_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'GC_CANE_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'GC_CANE_CE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'GC_CANE_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'GC_CANE_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'GC_CANE_CE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'GC_CANE_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'GC_CANE_ERR_STATUS__BUSY_ON_ERROR_MASK', + 'GC_CANE_ERR_STATUS__BUSY_ON_ERROR__SHIFT', + 'GC_CANE_ERR_STATUS__BUSY_ON_UER_ERROR_MASK', + 'GC_CANE_ERR_STATUS__BUSY_ON_UER_ERROR__SHIFT', + 'GC_CANE_ERR_STATUS__CLEAR_ERROR_STATUS_MASK', + 'GC_CANE_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT', + 'GC_CANE_ERR_STATUS__FUE_FLAG_MASK', + 'GC_CANE_ERR_STATUS__FUE_FLAG__SHIFT', + 'GC_CANE_ERR_STATUS__INTERRUPT_ON_FATAL_MASK', + 'GC_CANE_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT', + 'GC_CANE_ERR_STATUS__LEVEL_INTERRUPT_MASK', + 'GC_CANE_ERR_STATUS__LEVEL_INTERRUPT__SHIFT', + 'GC_CANE_ERR_STATUS__SDPM_RDRSP_DATAPARITY_ERROR_MASK', + 'GC_CANE_ERR_STATUS__SDPM_RDRSP_DATAPARITY_ERROR__SHIFT', + 'GC_CANE_ERR_STATUS__SDPM_RDRSP_DATASTATUS_MASK', + 'GC_CANE_ERR_STATUS__SDPM_RDRSP_DATASTATUS__SHIFT', + 'GC_CANE_ERR_STATUS__SDPM_RDRSP_STATUS_MASK', + 'GC_CANE_ERR_STATUS__SDPM_RDRSP_STATUS__SHIFT', + 'GC_CANE_ERR_STATUS__SDPM_WRRSP_STATUS_MASK', + 'GC_CANE_ERR_STATUS__SDPM_WRRSP_STATUS__SHIFT', + 'GC_CANE_ERR_STATUS__SDPS_DAT_ERROR_MASK', + 'GC_CANE_ERR_STATUS__SDPS_DAT_ERROR__SHIFT', + 'GC_CANE_ERR_STATUS__SDPS_DAT_PARITY_ERROR_MASK', + 'GC_CANE_ERR_STATUS__SDPS_DAT_PARITY_ERROR__SHIFT', + 'GC_CANE_UE_ERR_STATUS_HI__ECC_MASK', + 'GC_CANE_UE_ERR_STATUS_HI__ECC__SHIFT', + 'GC_CANE_UE_ERR_STATUS_HI__ERR_INFO_MASK', + 'GC_CANE_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'GC_CANE_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'GC_CANE_UE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'GC_CANE_UE_ERR_STATUS_HI__FED_CNT_MASK', + 'GC_CANE_UE_ERR_STATUS_HI__FED_CNT__SHIFT', + 'GC_CANE_UE_ERR_STATUS_HI__PARITY_MASK', + 'GC_CANE_UE_ERR_STATUS_HI__PARITY__SHIFT', + 'GC_CANE_UE_ERR_STATUS_HI__UE_CNT_MASK', + 'GC_CANE_UE_ERR_STATUS_HI__UE_CNT__SHIFT', + 'GC_CANE_UE_ERR_STATUS_LO__ADDRESS_MASK', + 'GC_CANE_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'GC_CANE_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'GC_CANE_UE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'GC_CANE_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'GC_CANE_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'GC_CANE_UE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'GC_CANE_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'GC_PRIV_MODE__MC_PRIV_MODE_MASK', + 'GC_PRIV_MODE__MC_PRIV_MODE__SHIFT', + 'GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK', + 'GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT', + 'GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK', + 'GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT', + 'GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK', + 'GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT', + 'GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK', + 'GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT', + 'GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK', + 'GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT', + 'GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK', + 'GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT', + 'GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK', + 'GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT', + 'GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK', + 'GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT', + 'GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK', + 'GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT', + 'GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK', + 'GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT', + 'GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK', + 'GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT', + 'GDFLL_EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS_MASK', + 'GDFLL_EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS__SHIFT', + 'GDFLL_EDC_HYSTERESIS_STAT__EDC_MASK', + 'GDFLL_EDC_HYSTERESIS_STAT__EDC__SHIFT', + 'GDFLL_EDC_HYSTERESIS_STAT__HYSTERESIS_CNT_MASK', + 'GDFLL_EDC_HYSTERESIS_STAT__HYSTERESIS_CNT__SHIFT', + 'GDS_ATOM_BASE__BASE_MASK', 'GDS_ATOM_BASE__BASE__SHIFT', + 'GDS_ATOM_BASE__UNUSED_MASK', 'GDS_ATOM_BASE__UNUSED__SHIFT', + 'GDS_ATOM_CNTL__AINC_MASK', 'GDS_ATOM_CNTL__AINC__SHIFT', + 'GDS_ATOM_CNTL__DMODE_MASK', 'GDS_ATOM_CNTL__DMODE__SHIFT', + 'GDS_ATOM_CNTL__UNUSED1_MASK', 'GDS_ATOM_CNTL__UNUSED1__SHIFT', + 'GDS_ATOM_CNTL__UNUSED2_MASK', 'GDS_ATOM_CNTL__UNUSED2__SHIFT', + 'GDS_ATOM_COMPLETE__COMPLETE_MASK', + 'GDS_ATOM_COMPLETE__COMPLETE__SHIFT', + 'GDS_ATOM_COMPLETE__UNUSED_MASK', + 'GDS_ATOM_COMPLETE__UNUSED__SHIFT', 'GDS_ATOM_DST__DST_MASK', + 'GDS_ATOM_DST__DST__SHIFT', 'GDS_ATOM_OFFSET0__OFFSET0_MASK', + 'GDS_ATOM_OFFSET0__OFFSET0__SHIFT', + 'GDS_ATOM_OFFSET0__UNUSED_MASK', + 'GDS_ATOM_OFFSET0__UNUSED__SHIFT', + 'GDS_ATOM_OFFSET1__OFFSET1_MASK', + 'GDS_ATOM_OFFSET1__OFFSET1__SHIFT', + 'GDS_ATOM_OFFSET1__UNUSED_MASK', + 'GDS_ATOM_OFFSET1__UNUSED__SHIFT', 'GDS_ATOM_OP__OP_MASK', + 'GDS_ATOM_OP__OP__SHIFT', 'GDS_ATOM_OP__UNUSED_MASK', + 'GDS_ATOM_OP__UNUSED__SHIFT', 'GDS_ATOM_READ0_U__DATA_MASK', + 'GDS_ATOM_READ0_U__DATA__SHIFT', 'GDS_ATOM_READ0__DATA_MASK', + 'GDS_ATOM_READ0__DATA__SHIFT', 'GDS_ATOM_READ1_U__DATA_MASK', + 'GDS_ATOM_READ1_U__DATA__SHIFT', 'GDS_ATOM_READ1__DATA_MASK', + 'GDS_ATOM_READ1__DATA__SHIFT', 'GDS_ATOM_SIZE__SIZE_MASK', + 'GDS_ATOM_SIZE__SIZE__SHIFT', 'GDS_ATOM_SIZE__UNUSED_MASK', + 'GDS_ATOM_SIZE__UNUSED__SHIFT', 'GDS_ATOM_SRC0_U__DATA_MASK', + 'GDS_ATOM_SRC0_U__DATA__SHIFT', 'GDS_ATOM_SRC0__DATA_MASK', + 'GDS_ATOM_SRC0__DATA__SHIFT', 'GDS_ATOM_SRC1_U__DATA_MASK', + 'GDS_ATOM_SRC1_U__DATA__SHIFT', 'GDS_ATOM_SRC1__DATA_MASK', + 'GDS_ATOM_SRC1__DATA__SHIFT', 'GDS_CE_ERR_STATUS_HI__CE_CNT_MASK', + 'GDS_CE_ERR_STATUS_HI__CE_CNT__SHIFT', + 'GDS_CE_ERR_STATUS_HI__ECC_MASK', + 'GDS_CE_ERR_STATUS_HI__ECC__SHIFT', + 'GDS_CE_ERR_STATUS_HI__ERR_INFO_MASK', + 'GDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'GDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'GDS_CE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'GDS_CE_ERR_STATUS_HI__OTHER_MASK', + 'GDS_CE_ERR_STATUS_HI__OTHER__SHIFT', + 'GDS_CE_ERR_STATUS_HI__POISON_MASK', + 'GDS_CE_ERR_STATUS_HI__POISON__SHIFT', + 'GDS_CE_ERR_STATUS_HI__RESERVED_MASK', + 'GDS_CE_ERR_STATUS_HI__RESERVED__SHIFT', + 'GDS_CE_ERR_STATUS_LO__ADDRESS_MASK', + 'GDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'GDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'GDS_CE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'GDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'GDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'GDS_CE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'GDS_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'GDS_CNTL_STATUS__CREDIT_BUSY0_MASK', + 'GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT', + 'GDS_CNTL_STATUS__CREDIT_BUSY1_MASK', + 'GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT', + 'GDS_CNTL_STATUS__CREDIT_BUSY2_MASK', + 'GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT', + 'GDS_CNTL_STATUS__CREDIT_BUSY3_MASK', + 'GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT', + 'GDS_CNTL_STATUS__CREDIT_BUSY4_MASK', + 'GDS_CNTL_STATUS__CREDIT_BUSY4__SHIFT', + 'GDS_CNTL_STATUS__CREDIT_BUSY5_MASK', + 'GDS_CNTL_STATUS__CREDIT_BUSY5__SHIFT', + 'GDS_CNTL_STATUS__CREDIT_BUSY6_MASK', + 'GDS_CNTL_STATUS__CREDIT_BUSY6__SHIFT', + 'GDS_CNTL_STATUS__CREDIT_BUSY7_MASK', + 'GDS_CNTL_STATUS__CREDIT_BUSY7__SHIFT', + 'GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK', + 'GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT', + 'GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK', + 'GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT', + 'GDS_CNTL_STATUS__DS_BUSY_MASK', + 'GDS_CNTL_STATUS__DS_BUSY__SHIFT', + 'GDS_CNTL_STATUS__DS_RD_CLAMP_MASK', + 'GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT', + 'GDS_CNTL_STATUS__DS_WR_CLAMP_MASK', + 'GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT', + 'GDS_CNTL_STATUS__GDS_BUSY_MASK', + 'GDS_CNTL_STATUS__GDS_BUSY__SHIFT', + 'GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK', + 'GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT', + 'GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK', + 'GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT', + 'GDS_CNTL_STATUS__GWS_BUSY_MASK', + 'GDS_CNTL_STATUS__GWS_BUSY__SHIFT', + 'GDS_CNTL_STATUS__ORD_APP_BUSY_MASK', + 'GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT', + 'GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK', + 'GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT', + 'GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK', + 'GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT', + 'GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK', + 'GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT', + 'GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK', + 'GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT', + 'GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK', + 'GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT', + 'GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK', + 'GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT', + 'GDS_CONFIG__SH4_GPR_PHASE_SEL_MASK', + 'GDS_CONFIG__SH4_GPR_PHASE_SEL__SHIFT', + 'GDS_CONFIG__SH5_GPR_PHASE_SEL_MASK', + 'GDS_CONFIG__SH5_GPR_PHASE_SEL__SHIFT', + 'GDS_CONFIG__SH6_GPR_PHASE_SEL_MASK', + 'GDS_CONFIG__SH6_GPR_PHASE_SEL__SHIFT', + 'GDS_CONFIG__SH7_GPR_PHASE_SEL_MASK', + 'GDS_CONFIG__SH7_GPR_PHASE_SEL__SHIFT', + 'GDS_CONFIG__WRITE_DIS_MASK', 'GDS_CONFIG__WRITE_DIS__SHIFT', + 'GDS_CS_CTXSW_CNT0__PTR_MASK', 'GDS_CS_CTXSW_CNT0__PTR__SHIFT', + 'GDS_CS_CTXSW_CNT0__UPDN_MASK', 'GDS_CS_CTXSW_CNT0__UPDN__SHIFT', + 'GDS_CS_CTXSW_CNT1__PTR_MASK', 'GDS_CS_CTXSW_CNT1__PTR__SHIFT', + 'GDS_CS_CTXSW_CNT1__UPDN_MASK', 'GDS_CS_CTXSW_CNT1__UPDN__SHIFT', + 'GDS_CS_CTXSW_CNT2__PTR_MASK', 'GDS_CS_CTXSW_CNT2__PTR__SHIFT', + 'GDS_CS_CTXSW_CNT2__UPDN_MASK', 'GDS_CS_CTXSW_CNT2__UPDN__SHIFT', + 'GDS_CS_CTXSW_CNT3__PTR_MASK', 'GDS_CS_CTXSW_CNT3__PTR__SHIFT', + 'GDS_CS_CTXSW_CNT3__UPDN_MASK', 'GDS_CS_CTXSW_CNT3__UPDN__SHIFT', + 'GDS_CS_CTXSW_STATUS__R_MASK', 'GDS_CS_CTXSW_STATUS__R__SHIFT', + 'GDS_CS_CTXSW_STATUS__UNUSED_MASK', + 'GDS_CS_CTXSW_STATUS__UNUSED__SHIFT', + 'GDS_CS_CTXSW_STATUS__W_MASK', 'GDS_CS_CTXSW_STATUS__W__SHIFT', + 'GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK', + 'GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT', + 'GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK', + 'GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT', + 'GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK', + 'GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT', + 'GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK', + 'GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT', + 'GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK', + 'GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT', + 'GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK', + 'GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK', + 'GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT', + 'GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK', + 'GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK', + 'GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT', + 'GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK', + 'GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT', + 'GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK', + 'GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT', + 'GDS_DSM_CNTL2__UNUSED_MASK', 'GDS_DSM_CNTL2__UNUSED__SHIFT', + 'GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK', + 'GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT', + 'GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK', + 'GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK', + 'GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT', + 'GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK', + 'GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT', + 'GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK', + 'GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT', + 'GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK', + 'GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT', + 'GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK', + 'GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT', + 'GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK', + 'GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT', + 'GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK', + 'GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK', + 'GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT', + 'GDS_DSM_CNTL__UNUSED_MASK', 'GDS_DSM_CNTL__UNUSED__SHIFT', + 'GDS_EDC_CNT__GDS_MEM_DED_MASK', + 'GDS_EDC_CNT__GDS_MEM_DED__SHIFT', + 'GDS_EDC_CNT__GDS_MEM_SEC_MASK', + 'GDS_EDC_CNT__GDS_MEM_SEC__SHIFT', 'GDS_EDC_CNT__UNUSED_MASK', + 'GDS_EDC_CNT__UNUSED__SHIFT', 'GDS_EDC_GRBM_CNT__DED_MASK', + 'GDS_EDC_GRBM_CNT__DED__SHIFT', 'GDS_EDC_GRBM_CNT__SEC_MASK', + 'GDS_EDC_GRBM_CNT__SEC__SHIFT', 'GDS_EDC_GRBM_CNT__UNUSED_MASK', + 'GDS_EDC_GRBM_CNT__UNUSED__SHIFT', + 'GDS_EDC_OA_DED__ME0_CS_DED_MASK', + 'GDS_EDC_OA_DED__ME0_CS_DED__SHIFT', + 'GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK', + 'GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT', + 'GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK', + 'GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT', + 'GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK', + 'GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT', + 'GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK', + 'GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT', + 'GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK', + 'GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT', + 'GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK', + 'GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT', + 'GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK', + 'GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT', + 'GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK', + 'GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT', + 'GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK', + 'GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT', + 'GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK', + 'GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT', + 'GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK', + 'GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT', + 'GDS_EDC_OA_DED__UNUSED1_MASK', 'GDS_EDC_OA_DED__UNUSED1__SHIFT', + 'GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK', + 'GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT', + 'GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK', + 'GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT', + 'GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK', + 'GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT', + 'GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK', + 'GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT', + 'GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_DED_MASK', + 'GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_DED__SHIFT', + 'GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SEC_MASK', + 'GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SEC__SHIFT', + 'GDS_EDC_OA_PHY_CNT__UNUSED1_MASK', + 'GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK', + 'GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT', + 'GDS_EDC_OA_PIPE_CNT__UNUSED_MASK', + 'GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT', + 'GDS_ENHANCE2__GDS_FED_IN_PROPAGATE_MASK', + 'GDS_ENHANCE2__GDS_FED_IN_PROPAGATE__SHIFT', + 'GDS_ENHANCE2__GDS_PHY_CMD_RAM_FGCG_OVERRIDE_MASK', + 'GDS_ENHANCE2__GDS_PHY_CMD_RAM_FGCG_OVERRIDE__SHIFT', + 'GDS_ENHANCE2__GDS_TD_INTERFACES_FGCG_OVERRIDE_MASK', + 'GDS_ENHANCE2__GDS_TD_INTERFACES_FGCG_OVERRIDE__SHIFT', + 'GDS_ENHANCE2__MISC_MASK', 'GDS_ENHANCE2__MISC__SHIFT', + 'GDS_ENHANCE2__UNUSED_MASK', 'GDS_ENHANCE2__UNUSED__SHIFT', + 'GDS_ENHANCE__AUTO_INC_INDEX_MASK', + 'GDS_ENHANCE__AUTO_INC_INDEX__SHIFT', + 'GDS_ENHANCE__CGPG_RESTORE_MASK', + 'GDS_ENHANCE__CGPG_RESTORE__SHIFT', + 'GDS_ENHANCE__DS_MEM_CLK_GATE_DIS_MASK', + 'GDS_ENHANCE__DS_MEM_CLK_GATE_DIS__SHIFT', + 'GDS_ENHANCE__GDSA_PC_CGTS_DIS_MASK', + 'GDS_ENHANCE__GDSA_PC_CGTS_DIS__SHIFT', + 'GDS_ENHANCE__GDSO_PC_CGTS_DIS_MASK', + 'GDS_ENHANCE__GDSO_PC_CGTS_DIS__SHIFT', + 'GDS_ENHANCE__GDS_CLK_ENHANCE_DIS_MASK', + 'GDS_ENHANCE__GDS_CLK_ENHANCE_DIS__SHIFT', + 'GDS_ENHANCE__MISC_MASK', 'GDS_ENHANCE__MISC__SHIFT', + 'GDS_ENHANCE__RD_BUF_TAG_MISS_MASK', + 'GDS_ENHANCE__RD_BUF_TAG_MISS__SHIFT', 'GDS_ENHANCE__UNUSED_MASK', + 'GDS_ENHANCE__UNUSED__SHIFT', + 'GDS_ENHANCE__WD_GDS_CSB_OVERRIDE_MASK', + 'GDS_ENHANCE__WD_GDS_CSB_OVERRIDE__SHIFT', + 'GDS_GFX_CTXSW_STATUS__R_MASK', 'GDS_GFX_CTXSW_STATUS__R__SHIFT', + 'GDS_GFX_CTXSW_STATUS__UNUSED_MASK', + 'GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT', + 'GDS_GFX_CTXSW_STATUS__W_MASK', 'GDS_GFX_CTXSW_STATUS__W__SHIFT', + 'GDS_GS_CTXSW_CNT0__PTR_MASK', 'GDS_GS_CTXSW_CNT0__PTR__SHIFT', + 'GDS_GS_CTXSW_CNT0__UPDN_MASK', 'GDS_GS_CTXSW_CNT0__UPDN__SHIFT', + 'GDS_GS_CTXSW_CNT1__PTR_MASK', 'GDS_GS_CTXSW_CNT1__PTR__SHIFT', + 'GDS_GS_CTXSW_CNT1__UPDN_MASK', 'GDS_GS_CTXSW_CNT1__UPDN__SHIFT', + 'GDS_GS_CTXSW_CNT2__PTR_MASK', 'GDS_GS_CTXSW_CNT2__PTR__SHIFT', + 'GDS_GS_CTXSW_CNT2__UPDN_MASK', 'GDS_GS_CTXSW_CNT2__UPDN__SHIFT', + 'GDS_GS_CTXSW_CNT3__PTR_MASK', 'GDS_GS_CTXSW_CNT3__PTR__SHIFT', + 'GDS_GS_CTXSW_CNT3__UPDN_MASK', 'GDS_GS_CTXSW_CNT3__UPDN__SHIFT', + 'GDS_GWS_RESET0__RESOURCE0_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE10_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE11_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE12_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE13_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE14_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE15_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE16_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE17_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE18_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE19_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE1_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE20_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE21_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE22_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE23_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE24_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE25_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE26_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE27_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE28_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE29_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE2_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE30_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE31_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE3_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE4_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE5_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE6_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE7_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE8_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT', + 'GDS_GWS_RESET0__RESOURCE9_RESET_MASK', + 'GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE32_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE33_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE34_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE35_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE36_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE37_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE38_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE39_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE40_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE41_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE42_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE43_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE44_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE45_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE46_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE47_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE48_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE49_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE50_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE51_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE52_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE53_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE54_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE55_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE56_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE57_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE58_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE59_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE60_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE61_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE62_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT', + 'GDS_GWS_RESET1__RESOURCE63_RESET_MASK', + 'GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT', + 'GDS_GWS_RESOURCE_CNTL__INDEX_MASK', + 'GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT', + 'GDS_GWS_RESOURCE_CNTL__UNUSED_MASK', + 'GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT', + 'GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK', + 'GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT', + 'GDS_GWS_RESOURCE_CNT__UNUSED_MASK', + 'GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT', + 'GDS_GWS_RESOURCE_RESET__RESET_MASK', + 'GDS_GWS_RESOURCE_RESET__RESET__SHIFT', + 'GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK', + 'GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT', + 'GDS_GWS_RESOURCE__COUNTER_MASK', + 'GDS_GWS_RESOURCE__COUNTER__SHIFT', 'GDS_GWS_RESOURCE__DED_MASK', + 'GDS_GWS_RESOURCE__DED__SHIFT', 'GDS_GWS_RESOURCE__FLAG_MASK', + 'GDS_GWS_RESOURCE__FLAG__SHIFT', 'GDS_GWS_RESOURCE__HALTED_MASK', + 'GDS_GWS_RESOURCE__HALTED__SHIFT', + 'GDS_GWS_RESOURCE__HEAD_FLAG_MASK', + 'GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT', + 'GDS_GWS_RESOURCE__HEAD_QUEUE_MASK', + 'GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT', + 'GDS_GWS_RESOURCE__HEAD_VALID_MASK', + 'GDS_GWS_RESOURCE__HEAD_VALID__SHIFT', + 'GDS_GWS_RESOURCE__RELEASE_ALL_MASK', + 'GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT', + 'GDS_GWS_RESOURCE__TYPE_MASK', 'GDS_GWS_RESOURCE__TYPE__SHIFT', + 'GDS_GWS_VMID0__BASE_MASK', 'GDS_GWS_VMID0__BASE__SHIFT', + 'GDS_GWS_VMID0__SIZE_MASK', 'GDS_GWS_VMID0__SIZE__SHIFT', + 'GDS_GWS_VMID10__BASE_MASK', 'GDS_GWS_VMID10__BASE__SHIFT', + 'GDS_GWS_VMID10__SIZE_MASK', 'GDS_GWS_VMID10__SIZE__SHIFT', + 'GDS_GWS_VMID11__BASE_MASK', 'GDS_GWS_VMID11__BASE__SHIFT', + 'GDS_GWS_VMID11__SIZE_MASK', 'GDS_GWS_VMID11__SIZE__SHIFT', + 'GDS_GWS_VMID12__BASE_MASK', 'GDS_GWS_VMID12__BASE__SHIFT', + 'GDS_GWS_VMID12__SIZE_MASK', 'GDS_GWS_VMID12__SIZE__SHIFT', + 'GDS_GWS_VMID13__BASE_MASK', 'GDS_GWS_VMID13__BASE__SHIFT', + 'GDS_GWS_VMID13__SIZE_MASK', 'GDS_GWS_VMID13__SIZE__SHIFT', + 'GDS_GWS_VMID14__BASE_MASK', 'GDS_GWS_VMID14__BASE__SHIFT', + 'GDS_GWS_VMID14__SIZE_MASK', 'GDS_GWS_VMID14__SIZE__SHIFT', + 'GDS_GWS_VMID15__BASE_MASK', 'GDS_GWS_VMID15__BASE__SHIFT', + 'GDS_GWS_VMID15__SIZE_MASK', 'GDS_GWS_VMID15__SIZE__SHIFT', + 'GDS_GWS_VMID1__BASE_MASK', 'GDS_GWS_VMID1__BASE__SHIFT', + 'GDS_GWS_VMID1__SIZE_MASK', 'GDS_GWS_VMID1__SIZE__SHIFT', + 'GDS_GWS_VMID2__BASE_MASK', 'GDS_GWS_VMID2__BASE__SHIFT', + 'GDS_GWS_VMID2__SIZE_MASK', 'GDS_GWS_VMID2__SIZE__SHIFT', + 'GDS_GWS_VMID3__BASE_MASK', 'GDS_GWS_VMID3__BASE__SHIFT', + 'GDS_GWS_VMID3__SIZE_MASK', 'GDS_GWS_VMID3__SIZE__SHIFT', + 'GDS_GWS_VMID4__BASE_MASK', 'GDS_GWS_VMID4__BASE__SHIFT', + 'GDS_GWS_VMID4__SIZE_MASK', 'GDS_GWS_VMID4__SIZE__SHIFT', + 'GDS_GWS_VMID5__BASE_MASK', 'GDS_GWS_VMID5__BASE__SHIFT', + 'GDS_GWS_VMID5__SIZE_MASK', 'GDS_GWS_VMID5__SIZE__SHIFT', + 'GDS_GWS_VMID6__BASE_MASK', 'GDS_GWS_VMID6__BASE__SHIFT', + 'GDS_GWS_VMID6__SIZE_MASK', 'GDS_GWS_VMID6__SIZE__SHIFT', + 'GDS_GWS_VMID7__BASE_MASK', 'GDS_GWS_VMID7__BASE__SHIFT', + 'GDS_GWS_VMID7__SIZE_MASK', 'GDS_GWS_VMID7__SIZE__SHIFT', + 'GDS_GWS_VMID8__BASE_MASK', 'GDS_GWS_VMID8__BASE__SHIFT', + 'GDS_GWS_VMID8__SIZE_MASK', 'GDS_GWS_VMID8__SIZE__SHIFT', + 'GDS_GWS_VMID9__BASE_MASK', 'GDS_GWS_VMID9__BASE__SHIFT', + 'GDS_GWS_VMID9__SIZE_MASK', 'GDS_GWS_VMID9__SIZE__SHIFT', + 'GDS_OA_ADDRESS__CRAWLER_MASK', + 'GDS_OA_ADDRESS__CRAWLER_TYPE_MASK', + 'GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT', + 'GDS_OA_ADDRESS__CRAWLER__SHIFT', + 'GDS_OA_ADDRESS__DS_ADDRESS_MASK', + 'GDS_OA_ADDRESS__DS_ADDRESS__SHIFT', + 'GDS_OA_ADDRESS__ENABLE_MASK', 'GDS_OA_ADDRESS__ENABLE__SHIFT', + 'GDS_OA_ADDRESS__NO_ALLOC_MASK', + 'GDS_OA_ADDRESS__NO_ALLOC__SHIFT', 'GDS_OA_ADDRESS__UNUSED_MASK', + 'GDS_OA_ADDRESS__UNUSED__SHIFT', 'GDS_OA_CGPG_RESTORE__MEID_MASK', + 'GDS_OA_CGPG_RESTORE__MEID__SHIFT', + 'GDS_OA_CGPG_RESTORE__PIPEID_MASK', + 'GDS_OA_CGPG_RESTORE__PIPEID__SHIFT', + 'GDS_OA_CGPG_RESTORE__QUEUEID_MASK', + 'GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT', + 'GDS_OA_CGPG_RESTORE__UNUSED_MASK', + 'GDS_OA_CGPG_RESTORE__UNUSED__SHIFT', + 'GDS_OA_CGPG_RESTORE__VMID_MASK', + 'GDS_OA_CGPG_RESTORE__VMID__SHIFT', 'GDS_OA_CNTL__INDEX_MASK', + 'GDS_OA_CNTL__INDEX__SHIFT', 'GDS_OA_CNTL__UNUSED_MASK', + 'GDS_OA_CNTL__UNUSED__SHIFT', + 'GDS_OA_COUNTER__SPACE_AVAILABLE_MASK', + 'GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT', + 'GDS_OA_INCDEC__INCDEC_MASK', 'GDS_OA_INCDEC__INCDEC__SHIFT', + 'GDS_OA_INCDEC__VALUE_MASK', 'GDS_OA_INCDEC__VALUE__SHIFT', + 'GDS_OA_RESET_MASK__ME0_CS_RESET_MASK', + 'GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK', + 'GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK', + 'GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK', + 'GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK', + 'GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK', + 'GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK', + 'GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK', + 'GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK', + 'GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK', + 'GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK', + 'GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT', + 'GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK', + 'GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT', + 'GDS_OA_RESET_MASK__UNUSED1_MASK', + 'GDS_OA_RESET_MASK__UNUSED1__SHIFT', 'GDS_OA_RESET__PIPE_ID_MASK', + 'GDS_OA_RESET__PIPE_ID__SHIFT', 'GDS_OA_RESET__RESET_MASK', + 'GDS_OA_RESET__RESET__SHIFT', 'GDS_OA_RING_SIZE__RING_SIZE_MASK', + 'GDS_OA_RING_SIZE__RING_SIZE__SHIFT', 'GDS_OA_VMID0__MASK_MASK', + 'GDS_OA_VMID0__MASK__SHIFT', 'GDS_OA_VMID0__UNUSED_MASK', + 'GDS_OA_VMID0__UNUSED__SHIFT', 'GDS_OA_VMID10__MASK_MASK', + 'GDS_OA_VMID10__MASK__SHIFT', 'GDS_OA_VMID10__UNUSED_MASK', + 'GDS_OA_VMID10__UNUSED__SHIFT', 'GDS_OA_VMID11__MASK_MASK', + 'GDS_OA_VMID11__MASK__SHIFT', 'GDS_OA_VMID11__UNUSED_MASK', + 'GDS_OA_VMID11__UNUSED__SHIFT', 'GDS_OA_VMID12__MASK_MASK', + 'GDS_OA_VMID12__MASK__SHIFT', 'GDS_OA_VMID12__UNUSED_MASK', + 'GDS_OA_VMID12__UNUSED__SHIFT', 'GDS_OA_VMID13__MASK_MASK', + 'GDS_OA_VMID13__MASK__SHIFT', 'GDS_OA_VMID13__UNUSED_MASK', + 'GDS_OA_VMID13__UNUSED__SHIFT', 'GDS_OA_VMID14__MASK_MASK', + 'GDS_OA_VMID14__MASK__SHIFT', 'GDS_OA_VMID14__UNUSED_MASK', + 'GDS_OA_VMID14__UNUSED__SHIFT', 'GDS_OA_VMID15__MASK_MASK', + 'GDS_OA_VMID15__MASK__SHIFT', 'GDS_OA_VMID15__UNUSED_MASK', + 'GDS_OA_VMID15__UNUSED__SHIFT', 'GDS_OA_VMID1__MASK_MASK', + 'GDS_OA_VMID1__MASK__SHIFT', 'GDS_OA_VMID1__UNUSED_MASK', + 'GDS_OA_VMID1__UNUSED__SHIFT', 'GDS_OA_VMID2__MASK_MASK', + 'GDS_OA_VMID2__MASK__SHIFT', 'GDS_OA_VMID2__UNUSED_MASK', + 'GDS_OA_VMID2__UNUSED__SHIFT', 'GDS_OA_VMID3__MASK_MASK', + 'GDS_OA_VMID3__MASK__SHIFT', 'GDS_OA_VMID3__UNUSED_MASK', + 'GDS_OA_VMID3__UNUSED__SHIFT', 'GDS_OA_VMID4__MASK_MASK', + 'GDS_OA_VMID4__MASK__SHIFT', 'GDS_OA_VMID4__UNUSED_MASK', + 'GDS_OA_VMID4__UNUSED__SHIFT', 'GDS_OA_VMID5__MASK_MASK', + 'GDS_OA_VMID5__MASK__SHIFT', 'GDS_OA_VMID5__UNUSED_MASK', + 'GDS_OA_VMID5__UNUSED__SHIFT', 'GDS_OA_VMID6__MASK_MASK', + 'GDS_OA_VMID6__MASK__SHIFT', 'GDS_OA_VMID6__UNUSED_MASK', + 'GDS_OA_VMID6__UNUSED__SHIFT', 'GDS_OA_VMID7__MASK_MASK', + 'GDS_OA_VMID7__MASK__SHIFT', 'GDS_OA_VMID7__UNUSED_MASK', + 'GDS_OA_VMID7__UNUSED__SHIFT', 'GDS_OA_VMID8__MASK_MASK', + 'GDS_OA_VMID8__MASK__SHIFT', 'GDS_OA_VMID8__UNUSED_MASK', + 'GDS_OA_VMID8__UNUSED__SHIFT', 'GDS_OA_VMID9__MASK_MASK', + 'GDS_OA_VMID9__MASK__SHIFT', 'GDS_OA_VMID9__UNUSED_MASK', + 'GDS_OA_VMID9__UNUSED__SHIFT', + 'GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'GDS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'GDS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'GDS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'GDS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'GDS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'GDS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'GDS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'GDS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'GDS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'GDS_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'GDS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'GDS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'GDS_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'GDS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'GDS_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'GDS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'GDS_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'GDS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'GDS_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'GDS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'GDS_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'GDS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'GDS_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'GDS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'GDS_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'GDS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'GDS_PROTECTION_FAULT__ADDRESS_MASK', + 'GDS_PROTECTION_FAULT__ADDRESS__SHIFT', + 'GDS_PROTECTION_FAULT__CU_ID_MASK', + 'GDS_PROTECTION_FAULT__CU_ID__SHIFT', + 'GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK', + 'GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT', + 'GDS_PROTECTION_FAULT__GRBM_MASK', + 'GDS_PROTECTION_FAULT__GRBM__SHIFT', + 'GDS_PROTECTION_FAULT__SH_ID_MASK', + 'GDS_PROTECTION_FAULT__SH_ID__SHIFT', + 'GDS_PROTECTION_FAULT__SIMD_ID_MASK', + 'GDS_PROTECTION_FAULT__SIMD_ID__SHIFT', + 'GDS_PROTECTION_FAULT__WAVE_ID_MASK', + 'GDS_PROTECTION_FAULT__WAVE_ID__SHIFT', + 'GDS_PROTECTION_FAULT__WRITE_DIS_MASK', + 'GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT', + 'GDS_PS0_CTXSW_CNT0__PTR_MASK', 'GDS_PS0_CTXSW_CNT0__PTR__SHIFT', + 'GDS_PS0_CTXSW_CNT0__UPDN_MASK', + 'GDS_PS0_CTXSW_CNT0__UPDN__SHIFT', 'GDS_PS0_CTXSW_CNT1__PTR_MASK', + 'GDS_PS0_CTXSW_CNT1__PTR__SHIFT', 'GDS_PS0_CTXSW_CNT1__UPDN_MASK', + 'GDS_PS0_CTXSW_CNT1__UPDN__SHIFT', 'GDS_PS0_CTXSW_CNT2__PTR_MASK', + 'GDS_PS0_CTXSW_CNT2__PTR__SHIFT', 'GDS_PS0_CTXSW_CNT2__UPDN_MASK', + 'GDS_PS0_CTXSW_CNT2__UPDN__SHIFT', 'GDS_PS0_CTXSW_CNT3__PTR_MASK', + 'GDS_PS0_CTXSW_CNT3__PTR__SHIFT', 'GDS_PS0_CTXSW_CNT3__UPDN_MASK', + 'GDS_PS0_CTXSW_CNT3__UPDN__SHIFT', 'GDS_PS1_CTXSW_CNT0__PTR_MASK', + 'GDS_PS1_CTXSW_CNT0__PTR__SHIFT', 'GDS_PS1_CTXSW_CNT0__UPDN_MASK', + 'GDS_PS1_CTXSW_CNT0__UPDN__SHIFT', 'GDS_PS1_CTXSW_CNT1__PTR_MASK', + 'GDS_PS1_CTXSW_CNT1__PTR__SHIFT', 'GDS_PS1_CTXSW_CNT1__UPDN_MASK', + 'GDS_PS1_CTXSW_CNT1__UPDN__SHIFT', 'GDS_PS1_CTXSW_CNT2__PTR_MASK', + 'GDS_PS1_CTXSW_CNT2__PTR__SHIFT', 'GDS_PS1_CTXSW_CNT2__UPDN_MASK', + 'GDS_PS1_CTXSW_CNT2__UPDN__SHIFT', 'GDS_PS1_CTXSW_CNT3__PTR_MASK', + 'GDS_PS1_CTXSW_CNT3__PTR__SHIFT', 'GDS_PS1_CTXSW_CNT3__UPDN_MASK', + 'GDS_PS1_CTXSW_CNT3__UPDN__SHIFT', 'GDS_PS2_CTXSW_CNT0__PTR_MASK', + 'GDS_PS2_CTXSW_CNT0__PTR__SHIFT', 'GDS_PS2_CTXSW_CNT0__UPDN_MASK', + 'GDS_PS2_CTXSW_CNT0__UPDN__SHIFT', 'GDS_PS2_CTXSW_CNT1__PTR_MASK', + 'GDS_PS2_CTXSW_CNT1__PTR__SHIFT', 'GDS_PS2_CTXSW_CNT1__UPDN_MASK', + 'GDS_PS2_CTXSW_CNT1__UPDN__SHIFT', 'GDS_PS2_CTXSW_CNT2__PTR_MASK', + 'GDS_PS2_CTXSW_CNT2__PTR__SHIFT', 'GDS_PS2_CTXSW_CNT2__UPDN_MASK', + 'GDS_PS2_CTXSW_CNT2__UPDN__SHIFT', 'GDS_PS2_CTXSW_CNT3__PTR_MASK', + 'GDS_PS2_CTXSW_CNT3__PTR__SHIFT', 'GDS_PS2_CTXSW_CNT3__UPDN_MASK', + 'GDS_PS2_CTXSW_CNT3__UPDN__SHIFT', 'GDS_PS3_CTXSW_CNT0__PTR_MASK', + 'GDS_PS3_CTXSW_CNT0__PTR__SHIFT', 'GDS_PS3_CTXSW_CNT0__UPDN_MASK', + 'GDS_PS3_CTXSW_CNT0__UPDN__SHIFT', 'GDS_PS3_CTXSW_CNT1__PTR_MASK', + 'GDS_PS3_CTXSW_CNT1__PTR__SHIFT', 'GDS_PS3_CTXSW_CNT1__UPDN_MASK', + 'GDS_PS3_CTXSW_CNT1__UPDN__SHIFT', 'GDS_PS3_CTXSW_CNT2__PTR_MASK', + 'GDS_PS3_CTXSW_CNT2__PTR__SHIFT', 'GDS_PS3_CTXSW_CNT2__UPDN_MASK', + 'GDS_PS3_CTXSW_CNT2__UPDN__SHIFT', 'GDS_PS3_CTXSW_CNT3__PTR_MASK', + 'GDS_PS3_CTXSW_CNT3__PTR__SHIFT', 'GDS_PS3_CTXSW_CNT3__UPDN_MASK', + 'GDS_PS3_CTXSW_CNT3__UPDN__SHIFT', 'GDS_PS4_CTXSW_CNT0__PTR_MASK', + 'GDS_PS4_CTXSW_CNT0__PTR__SHIFT', 'GDS_PS4_CTXSW_CNT0__UPDN_MASK', + 'GDS_PS4_CTXSW_CNT0__UPDN__SHIFT', 'GDS_PS4_CTXSW_CNT1__PTR_MASK', + 'GDS_PS4_CTXSW_CNT1__PTR__SHIFT', 'GDS_PS4_CTXSW_CNT1__UPDN_MASK', + 'GDS_PS4_CTXSW_CNT1__UPDN__SHIFT', 'GDS_PS4_CTXSW_CNT2__PTR_MASK', + 'GDS_PS4_CTXSW_CNT2__PTR__SHIFT', 'GDS_PS4_CTXSW_CNT2__UPDN_MASK', + 'GDS_PS4_CTXSW_CNT2__UPDN__SHIFT', 'GDS_PS4_CTXSW_CNT3__PTR_MASK', + 'GDS_PS4_CTXSW_CNT3__PTR__SHIFT', 'GDS_PS4_CTXSW_CNT3__UPDN_MASK', + 'GDS_PS4_CTXSW_CNT3__UPDN__SHIFT', 'GDS_PS5_CTXSW_CNT0__PTR_MASK', + 'GDS_PS5_CTXSW_CNT0__PTR__SHIFT', 'GDS_PS5_CTXSW_CNT0__UPDN_MASK', + 'GDS_PS5_CTXSW_CNT0__UPDN__SHIFT', 'GDS_PS5_CTXSW_CNT1__PTR_MASK', + 'GDS_PS5_CTXSW_CNT1__PTR__SHIFT', 'GDS_PS5_CTXSW_CNT1__UPDN_MASK', + 'GDS_PS5_CTXSW_CNT1__UPDN__SHIFT', 'GDS_PS5_CTXSW_CNT2__PTR_MASK', + 'GDS_PS5_CTXSW_CNT2__PTR__SHIFT', 'GDS_PS5_CTXSW_CNT2__UPDN_MASK', + 'GDS_PS5_CTXSW_CNT2__UPDN__SHIFT', 'GDS_PS5_CTXSW_CNT3__PTR_MASK', + 'GDS_PS5_CTXSW_CNT3__PTR__SHIFT', 'GDS_PS5_CTXSW_CNT3__UPDN_MASK', + 'GDS_PS5_CTXSW_CNT3__UPDN__SHIFT', 'GDS_PS6_CTXSW_CNT0__PTR_MASK', + 'GDS_PS6_CTXSW_CNT0__PTR__SHIFT', 'GDS_PS6_CTXSW_CNT0__UPDN_MASK', + 'GDS_PS6_CTXSW_CNT0__UPDN__SHIFT', 'GDS_PS6_CTXSW_CNT1__PTR_MASK', + 'GDS_PS6_CTXSW_CNT1__PTR__SHIFT', 'GDS_PS6_CTXSW_CNT1__UPDN_MASK', + 'GDS_PS6_CTXSW_CNT1__UPDN__SHIFT', 'GDS_PS6_CTXSW_CNT2__PTR_MASK', + 'GDS_PS6_CTXSW_CNT2__PTR__SHIFT', 'GDS_PS6_CTXSW_CNT2__UPDN_MASK', + 'GDS_PS6_CTXSW_CNT2__UPDN__SHIFT', 'GDS_PS6_CTXSW_CNT3__PTR_MASK', + 'GDS_PS6_CTXSW_CNT3__PTR__SHIFT', 'GDS_PS6_CTXSW_CNT3__UPDN_MASK', + 'GDS_PS6_CTXSW_CNT3__UPDN__SHIFT', 'GDS_PS7_CTXSW_CNT0__PTR_MASK', + 'GDS_PS7_CTXSW_CNT0__PTR__SHIFT', 'GDS_PS7_CTXSW_CNT0__UPDN_MASK', + 'GDS_PS7_CTXSW_CNT0__UPDN__SHIFT', 'GDS_PS7_CTXSW_CNT1__PTR_MASK', + 'GDS_PS7_CTXSW_CNT1__PTR__SHIFT', 'GDS_PS7_CTXSW_CNT1__UPDN_MASK', + 'GDS_PS7_CTXSW_CNT1__UPDN__SHIFT', 'GDS_PS7_CTXSW_CNT2__PTR_MASK', + 'GDS_PS7_CTXSW_CNT2__PTR__SHIFT', 'GDS_PS7_CTXSW_CNT2__UPDN_MASK', + 'GDS_PS7_CTXSW_CNT2__UPDN__SHIFT', 'GDS_PS7_CTXSW_CNT3__PTR_MASK', + 'GDS_PS7_CTXSW_CNT3__PTR__SHIFT', 'GDS_PS7_CTXSW_CNT3__UPDN_MASK', + 'GDS_PS7_CTXSW_CNT3__UPDN__SHIFT', 'GDS_RD_ADDR__READ_ADDR_MASK', + 'GDS_RD_ADDR__READ_ADDR__SHIFT', + 'GDS_RD_BURST_ADDR__BURST_ADDR_MASK', + 'GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT', + 'GDS_RD_BURST_COUNT__BURST_COUNT_MASK', + 'GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT', + 'GDS_RD_BURST_DATA__BURST_DATA_MASK', + 'GDS_RD_BURST_DATA__BURST_DATA__SHIFT', + 'GDS_RD_DATA__READ_DATA_MASK', 'GDS_RD_DATA__READ_DATA__SHIFT', + 'GDS_UE_ERR_STATUS_HI__ECC_MASK', + 'GDS_UE_ERR_STATUS_HI__ECC__SHIFT', + 'GDS_UE_ERR_STATUS_HI__ERR_INFO_MASK', + 'GDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'GDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'GDS_UE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'GDS_UE_ERR_STATUS_HI__FED_CNT_MASK', + 'GDS_UE_ERR_STATUS_HI__FED_CNT__SHIFT', + 'GDS_UE_ERR_STATUS_HI__PARITY_MASK', + 'GDS_UE_ERR_STATUS_HI__PARITY__SHIFT', + 'GDS_UE_ERR_STATUS_HI__RESERVED_MASK', + 'GDS_UE_ERR_STATUS_HI__RESERVED__SHIFT', + 'GDS_UE_ERR_STATUS_HI__UE_CNT_MASK', + 'GDS_UE_ERR_STATUS_HI__UE_CNT__SHIFT', + 'GDS_UE_ERR_STATUS_LO__ADDRESS_MASK', + 'GDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'GDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'GDS_UE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'GDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'GDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'GDS_UE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'GDS_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'GDS_VMID0_BASE__BASE_MASK', 'GDS_VMID0_BASE__BASE__SHIFT', + 'GDS_VMID0_SIZE__SIZE_MASK', 'GDS_VMID0_SIZE__SIZE__SHIFT', + 'GDS_VMID10_BASE__BASE_MASK', 'GDS_VMID10_BASE__BASE__SHIFT', + 'GDS_VMID10_SIZE__SIZE_MASK', 'GDS_VMID10_SIZE__SIZE__SHIFT', + 'GDS_VMID11_BASE__BASE_MASK', 'GDS_VMID11_BASE__BASE__SHIFT', + 'GDS_VMID11_SIZE__SIZE_MASK', 'GDS_VMID11_SIZE__SIZE__SHIFT', + 'GDS_VMID12_BASE__BASE_MASK', 'GDS_VMID12_BASE__BASE__SHIFT', + 'GDS_VMID12_SIZE__SIZE_MASK', 'GDS_VMID12_SIZE__SIZE__SHIFT', + 'GDS_VMID13_BASE__BASE_MASK', 'GDS_VMID13_BASE__BASE__SHIFT', + 'GDS_VMID13_SIZE__SIZE_MASK', 'GDS_VMID13_SIZE__SIZE__SHIFT', + 'GDS_VMID14_BASE__BASE_MASK', 'GDS_VMID14_BASE__BASE__SHIFT', + 'GDS_VMID14_SIZE__SIZE_MASK', 'GDS_VMID14_SIZE__SIZE__SHIFT', + 'GDS_VMID15_BASE__BASE_MASK', 'GDS_VMID15_BASE__BASE__SHIFT', + 'GDS_VMID15_SIZE__SIZE_MASK', 'GDS_VMID15_SIZE__SIZE__SHIFT', + 'GDS_VMID1_BASE__BASE_MASK', 'GDS_VMID1_BASE__BASE__SHIFT', + 'GDS_VMID1_SIZE__SIZE_MASK', 'GDS_VMID1_SIZE__SIZE__SHIFT', + 'GDS_VMID2_BASE__BASE_MASK', 'GDS_VMID2_BASE__BASE__SHIFT', + 'GDS_VMID2_SIZE__SIZE_MASK', 'GDS_VMID2_SIZE__SIZE__SHIFT', + 'GDS_VMID3_BASE__BASE_MASK', 'GDS_VMID3_BASE__BASE__SHIFT', + 'GDS_VMID3_SIZE__SIZE_MASK', 'GDS_VMID3_SIZE__SIZE__SHIFT', + 'GDS_VMID4_BASE__BASE_MASK', 'GDS_VMID4_BASE__BASE__SHIFT', + 'GDS_VMID4_SIZE__SIZE_MASK', 'GDS_VMID4_SIZE__SIZE__SHIFT', + 'GDS_VMID5_BASE__BASE_MASK', 'GDS_VMID5_BASE__BASE__SHIFT', + 'GDS_VMID5_SIZE__SIZE_MASK', 'GDS_VMID5_SIZE__SIZE__SHIFT', + 'GDS_VMID6_BASE__BASE_MASK', 'GDS_VMID6_BASE__BASE__SHIFT', + 'GDS_VMID6_SIZE__SIZE_MASK', 'GDS_VMID6_SIZE__SIZE__SHIFT', + 'GDS_VMID7_BASE__BASE_MASK', 'GDS_VMID7_BASE__BASE__SHIFT', + 'GDS_VMID7_SIZE__SIZE_MASK', 'GDS_VMID7_SIZE__SIZE__SHIFT', + 'GDS_VMID8_BASE__BASE_MASK', 'GDS_VMID8_BASE__BASE__SHIFT', + 'GDS_VMID8_SIZE__SIZE_MASK', 'GDS_VMID8_SIZE__SIZE__SHIFT', + 'GDS_VMID9_BASE__BASE_MASK', 'GDS_VMID9_BASE__BASE__SHIFT', + 'GDS_VMID9_SIZE__SIZE_MASK', 'GDS_VMID9_SIZE__SIZE__SHIFT', + 'GDS_VM_PROTECTION_FAULT__ADDRESS_MASK', + 'GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT', + 'GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK', + 'GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT', + 'GDS_VM_PROTECTION_FAULT__GRBM_MASK', + 'GDS_VM_PROTECTION_FAULT__GRBM__SHIFT', + 'GDS_VM_PROTECTION_FAULT__GWS_MASK', + 'GDS_VM_PROTECTION_FAULT__GWS__SHIFT', + 'GDS_VM_PROTECTION_FAULT__OA_MASK', + 'GDS_VM_PROTECTION_FAULT__OA__SHIFT', + 'GDS_VM_PROTECTION_FAULT__TMZ_MASK', + 'GDS_VM_PROTECTION_FAULT__TMZ__SHIFT', + 'GDS_VM_PROTECTION_FAULT__VMID_MASK', + 'GDS_VM_PROTECTION_FAULT__VMID__SHIFT', + 'GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK', + 'GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT', + 'GDS_VS_CTXSW_CNT0__PTR_MASK', 'GDS_VS_CTXSW_CNT0__PTR__SHIFT', + 'GDS_VS_CTXSW_CNT0__UPDN_MASK', 'GDS_VS_CTXSW_CNT0__UPDN__SHIFT', + 'GDS_VS_CTXSW_CNT1__PTR_MASK', 'GDS_VS_CTXSW_CNT1__PTR__SHIFT', + 'GDS_VS_CTXSW_CNT1__UPDN_MASK', 'GDS_VS_CTXSW_CNT1__UPDN__SHIFT', + 'GDS_VS_CTXSW_CNT2__PTR_MASK', 'GDS_VS_CTXSW_CNT2__PTR__SHIFT', + 'GDS_VS_CTXSW_CNT2__UPDN_MASK', 'GDS_VS_CTXSW_CNT2__UPDN__SHIFT', + 'GDS_VS_CTXSW_CNT3__PTR_MASK', 'GDS_VS_CTXSW_CNT3__PTR__SHIFT', + 'GDS_VS_CTXSW_CNT3__UPDN_MASK', 'GDS_VS_CTXSW_CNT3__UPDN__SHIFT', + 'GDS_WD_GDS_CSB__COUNTER_MASK', 'GDS_WD_GDS_CSB__COUNTER__SHIFT', + 'GDS_WD_GDS_CSB__UNUSED_MASK', 'GDS_WD_GDS_CSB__UNUSED__SHIFT', + 'GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK', + 'GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT', + 'GDS_WR_ADDR__WRITE_ADDR_MASK', 'GDS_WR_ADDR__WRITE_ADDR__SHIFT', + 'GDS_WR_BURST_ADDR__WRITE_ADDR_MASK', + 'GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT', + 'GDS_WR_BURST_DATA__WRITE_DATA_MASK', + 'GDS_WR_BURST_DATA__WRITE_DATA__SHIFT', + 'GDS_WR_DATA__WRITE_DATA_MASK', 'GDS_WR_DATA__WRITE_DATA__SHIFT', + 'GFX_COPY_STATE__SRC_STATE_ID_MASK', + 'GFX_COPY_STATE__SRC_STATE_ID__SHIFT', + 'GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK', + 'GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT', + 'GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK', + 'GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT', + 'GFX_PIPE_CONTROL__RESERVED_MASK', + 'GFX_PIPE_CONTROL__RESERVED__SHIFT', + 'GRBM_CAM_DATA__CAM_ADDR_MASK', 'GRBM_CAM_DATA__CAM_ADDR__SHIFT', + 'GRBM_CAM_DATA__CAM_REMAPADDR_MASK', + 'GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT', + 'GRBM_CAM_INDEX__CAM_INDEX_MASK', + 'GRBM_CAM_INDEX__CAM_INDEX__SHIFT', + 'GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK', + 'GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT', + 'GRBM_CHIP_REVISION__CHIP_REVISION_MASK', + 'GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT', + 'GRBM_CNTL__READ_TIMEOUT_MASK', 'GRBM_CNTL__READ_TIMEOUT__SHIFT', + 'GRBM_CNTL__REPORT_LAST_RDERR_MASK', + 'GRBM_CNTL__REPORT_LAST_RDERR__SHIFT', + 'GRBM_DSM_BYPASS__BYPASS_BITS_MASK', + 'GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT', + 'GRBM_DSM_BYPASS__BYPASS_EN_MASK', + 'GRBM_DSM_BYPASS__BYPASS_EN__SHIFT', + 'GRBM_FENCE_RANGE0__END_MASK', 'GRBM_FENCE_RANGE0__END__SHIFT', + 'GRBM_FENCE_RANGE0__START_MASK', + 'GRBM_FENCE_RANGE0__START__SHIFT', 'GRBM_FENCE_RANGE1__END_MASK', + 'GRBM_FENCE_RANGE1__END__SHIFT', 'GRBM_FENCE_RANGE1__START_MASK', + 'GRBM_FENCE_RANGE1__START__SHIFT', + 'GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK', + 'GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT', + 'GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK', + 'GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT', + 'GRBM_GFX_CNTL_SR_DATA__MEID_MASK', + 'GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT', + 'GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK', + 'GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT', + 'GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK', + 'GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT', + 'GRBM_GFX_CNTL_SR_DATA__VMID_MASK', + 'GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT', + 'GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK', + 'GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT', + 'GRBM_GFX_CNTL_SR_SELECT__VF_PF_MASK', + 'GRBM_GFX_CNTL_SR_SELECT__VF_PF__SHIFT', + 'GRBM_GFX_CNTL__MEID_MASK', 'GRBM_GFX_CNTL__MEID__SHIFT', + 'GRBM_GFX_CNTL__PIPEID_MASK', 'GRBM_GFX_CNTL__PIPEID__SHIFT', + 'GRBM_GFX_CNTL__QUEUEID_MASK', 'GRBM_GFX_CNTL__QUEUEID__SHIFT', + 'GRBM_GFX_CNTL__VMID_MASK', 'GRBM_GFX_CNTL__VMID__SHIFT', + 'GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK', + 'GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT', + 'GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK', + 'GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT', + 'GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK', + 'GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT', + 'GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK', + 'GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT', + 'GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES_MASK', + 'GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES__SHIFT', + 'GRBM_GFX_INDEX_SR_DATA__SH_INDEX_MASK', + 'GRBM_GFX_INDEX_SR_DATA__SH_INDEX__SHIFT', + 'GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK', + 'GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT', + 'GRBM_GFX_INDEX_SR_SELECT__VF_PF_MASK', + 'GRBM_GFX_INDEX_SR_SELECT__VF_PF__SHIFT', + 'GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK', + 'GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT', + 'GRBM_GFX_INDEX__INSTANCE_INDEX_MASK', + 'GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT', + 'GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK', + 'GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT', + 'GRBM_GFX_INDEX__SE_INDEX_MASK', + 'GRBM_GFX_INDEX__SE_INDEX__SHIFT', + 'GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK', + 'GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT', + 'GRBM_GFX_INDEX__SH_INDEX_MASK', + 'GRBM_GFX_INDEX__SH_INDEX__SHIFT', + 'GRBM_HYP_CAM_DATA__CAM_ADDR_MASK', + 'GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT', + 'GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK', + 'GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT', + 'GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK', + 'GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT', + 'GRBM_IH_CREDIT__CREDIT_VALUE_MASK', + 'GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT', + 'GRBM_IH_CREDIT__IH_CLIENT_ID_MASK', + 'GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT', + 'GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK', + 'GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT', + 'GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK', + 'GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT', + 'GRBM_IOV_ERROR_FIFO_DATA__IOV_ADDR_MASK', + 'GRBM_IOV_ERROR_FIFO_DATA__IOV_ADDR__SHIFT', + 'GRBM_IOV_ERROR_FIFO_DATA__IOV_OP_MASK', + 'GRBM_IOV_ERROR_FIFO_DATA__IOV_OP__SHIFT', + 'GRBM_IOV_ERROR_FIFO_DATA__IOV_OVERFLOW_MASK', + 'GRBM_IOV_ERROR_FIFO_DATA__IOV_OVERFLOW__SHIFT', + 'GRBM_IOV_ERROR_FIFO_DATA__IOV_READ_VALID_MASK', + 'GRBM_IOV_ERROR_FIFO_DATA__IOV_READ_VALID__SHIFT', + 'GRBM_IOV_ERROR_FIFO_DATA__IOV_SSRCID_MASK', + 'GRBM_IOV_ERROR_FIFO_DATA__IOV_SSRCID__SHIFT', + 'GRBM_IOV_ERROR_FIFO_DATA__IOV_VFID_MASK', + 'GRBM_IOV_ERROR_FIFO_DATA__IOV_VFID__SHIFT', + 'GRBM_IOV_ERROR_FIFO_DATA__IOV_VF_MASK', + 'GRBM_IOV_ERROR_FIFO_DATA__IOV_VF__SHIFT', + 'GRBM_IOV_ERROR__IOV_ADDR_MASK', + 'GRBM_IOV_ERROR__IOV_ADDR__SHIFT', + 'GRBM_IOV_ERROR__IOV_ERROR_MASK', + 'GRBM_IOV_ERROR__IOV_ERROR__SHIFT', 'GRBM_IOV_ERROR__IOV_OP_MASK', + 'GRBM_IOV_ERROR__IOV_OP__SHIFT', 'GRBM_IOV_ERROR__IOV_VFID_MASK', + 'GRBM_IOV_ERROR__IOV_VFID__SHIFT', 'GRBM_IOV_ERROR__IOV_VF_MASK', + 'GRBM_IOV_ERROR__IOV_VF__SHIFT', + 'GRBM_IOV_READ_ERROR__IOV_ADDR_MASK', + 'GRBM_IOV_READ_ERROR__IOV_ADDR__SHIFT', + 'GRBM_IOV_READ_ERROR__IOV_ERROR_MASK', + 'GRBM_IOV_READ_ERROR__IOV_ERROR__SHIFT', + 'GRBM_IOV_READ_ERROR__IOV_OP_MASK', + 'GRBM_IOV_READ_ERROR__IOV_OP__SHIFT', + 'GRBM_IOV_READ_ERROR__IOV_VFID_MASK', + 'GRBM_IOV_READ_ERROR__IOV_VFID__SHIFT', + 'GRBM_IOV_READ_ERROR__IOV_VF_MASK', + 'GRBM_IOV_READ_ERROR__IOV_VF__SHIFT', + 'GRBM_MCM_ADDR__MCM_ADDR_IH_MASK', + 'GRBM_MCM_ADDR__MCM_ADDR_IH__SHIFT', 'GRBM_NOWHERE__DATA_MASK', + 'GRBM_NOWHERE__DATA__SHIFT', + 'GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK', + 'GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT', + 'GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK', + 'GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT', + 'GRBM_PWR_CNTL__ALL_REQ_EN_MASK', + 'GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT', + 'GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK', + 'GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT', + 'GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK', + 'GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT', + 'GRBM_PWR_CNTL__GFX_REQ_EN_MASK', + 'GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT', + 'GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK', + 'GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT', + 'GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK', + 'GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT', + 'GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK', + 'GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT', + 'GRBM_READ_ERROR__READ_ADDRESS_MASK', + 'GRBM_READ_ERROR__READ_ADDRESS__SHIFT', + 'GRBM_READ_ERROR__READ_ERROR_MASK', + 'GRBM_READ_ERROR__READ_ERROR__SHIFT', + 'GRBM_READ_ERROR__READ_MEID_MASK', + 'GRBM_READ_ERROR__READ_MEID__SHIFT', + 'GRBM_READ_ERROR__READ_PIPEID_MASK', + 'GRBM_READ_ERROR__READ_PIPEID__SHIFT', + 'GRBM_RSMU_CFG__APERTURE_ID_MASK', + 'GRBM_RSMU_CFG__APERTURE_ID__SHIFT', + 'GRBM_RSMU_CFG__DEBUG_MASK_MASK', + 'GRBM_RSMU_CFG__DEBUG_MASK__SHIFT', + 'GRBM_RSMU_CFG__POSTED_WR_MASK', + 'GRBM_RSMU_CFG__POSTED_WR__SHIFT', 'GRBM_RSMU_CFG__QOS_MASK', + 'GRBM_RSMU_CFG__QOS__SHIFT', + 'GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK', + 'GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT', + 'GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK', + 'GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK', + 'GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT', + 'GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT', + 'GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK', + 'GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT', + 'GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK', + 'GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT', + 'GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK', + 'GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT', + 'GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK', + 'GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT', + 'GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK', + 'GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT', + 'GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK', + 'GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT', + 'GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK', + 'GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT', + 'GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK', + 'GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT', + 'GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK', + 'GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT', + 'GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK', + 'GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT', + 'GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK', + 'GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT', + 'GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK', + 'GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK', + 'GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT', + 'GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK', + 'GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK', + 'GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT', + 'GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK', + 'GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK', + 'GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT', + 'GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK', + 'GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK', + 'GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT', + 'GRBM_SEC_CNTL__DEBUG_ENABLE_MASK', + 'GRBM_SEC_CNTL__DEBUG_ENABLE__SHIFT', + 'GRBM_SKEW_CNTL__SKEW_COUNT_MASK', + 'GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT', + 'GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK', + 'GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT', + 'GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK', + 'GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT', + 'GRBM_SOFT_RESET__SOFT_RESET_CANE_MASK', + 'GRBM_SOFT_RESET__SOFT_RESET_CANE__SHIFT', + 'GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK', + 'GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT', + 'GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK', + 'GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT', + 'GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK', + 'GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT', + 'GRBM_SOFT_RESET__SOFT_RESET_CP_MASK', + 'GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT', + 'GRBM_SOFT_RESET__SOFT_RESET_EA_MASK', + 'GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT', + 'GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK', + 'GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT', + 'GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK', + 'GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT', + 'GRBM_SOFT_RESET__SOFT_RESET_UTCL2_MASK', + 'GRBM_SOFT_RESET__SOFT_RESET_UTCL2__SHIFT', + 'GRBM_STATUS2__CANE_BUSY_MASK', 'GRBM_STATUS2__CANE_BUSY__SHIFT', + 'GRBM_STATUS2__CANE_LINK_BUSY_MASK', + 'GRBM_STATUS2__CANE_LINK_BUSY__SHIFT', + 'GRBM_STATUS2__CPAXI_BUSY_MASK', + 'GRBM_STATUS2__CPAXI_BUSY__SHIFT', 'GRBM_STATUS2__CPC_BUSY_MASK', + 'GRBM_STATUS2__CPC_BUSY__SHIFT', 'GRBM_STATUS2__CPF_BUSY_MASK', + 'GRBM_STATUS2__CPF_BUSY__SHIFT', + 'GRBM_STATUS2__CPF_RQ_PENDING_MASK', + 'GRBM_STATUS2__CPF_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__CPG_BUSY_MASK', 'GRBM_STATUS2__CPG_BUSY__SHIFT', + 'GRBM_STATUS2__EA_BUSY_MASK', 'GRBM_STATUS2__EA_BUSY__SHIFT', + 'GRBM_STATUS2__EA_LINK_BUSY_MASK', + 'GRBM_STATUS2__EA_LINK_BUSY__SHIFT', + 'GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK', + 'GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK', + 'GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT', + 'GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK', + 'GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK', + 'GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK', + 'GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK', + 'GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK', + 'GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK', + 'GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK', + 'GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK', + 'GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK', + 'GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__RLC_BUSY_MASK', 'GRBM_STATUS2__RLC_BUSY__SHIFT', + 'GRBM_STATUS2__RLC_RQ_PENDING_MASK', + 'GRBM_STATUS2__RLC_RQ_PENDING__SHIFT', + 'GRBM_STATUS2__RMI_BUSY_MASK', 'GRBM_STATUS2__RMI_BUSY__SHIFT', + 'GRBM_STATUS2__TCC_CC_RESIDENT_MASK', + 'GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT', + 'GRBM_STATUS2__TC_BUSY_MASK', 'GRBM_STATUS2__TC_BUSY__SHIFT', + 'GRBM_STATUS2__UTCL2_BUSY_MASK', + 'GRBM_STATUS2__UTCL2_BUSY__SHIFT', + 'GRBM_STATUS2__UTCL2_RQ_PENDING_MASK', + 'GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT', + 'GRBM_STATUS_SE0__BCI_BUSY_MASK', + 'GRBM_STATUS_SE0__BCI_BUSY__SHIFT', + 'GRBM_STATUS_SE0__CB_BUSY_MASK', + 'GRBM_STATUS_SE0__CB_BUSY__SHIFT', + 'GRBM_STATUS_SE0__CB_CLEAN_MASK', + 'GRBM_STATUS_SE0__CB_CLEAN__SHIFT', + 'GRBM_STATUS_SE0__DB_BUSY_MASK', + 'GRBM_STATUS_SE0__DB_BUSY__SHIFT', + 'GRBM_STATUS_SE0__DB_CLEAN_MASK', + 'GRBM_STATUS_SE0__DB_CLEAN__SHIFT', + 'GRBM_STATUS_SE0__PA_BUSY_MASK', + 'GRBM_STATUS_SE0__PA_BUSY__SHIFT', + 'GRBM_STATUS_SE0__RMI_BUSY_MASK', + 'GRBM_STATUS_SE0__RMI_BUSY__SHIFT', + 'GRBM_STATUS_SE0__SC_BUSY_MASK', + 'GRBM_STATUS_SE0__SC_BUSY__SHIFT', + 'GRBM_STATUS_SE0__SPI_BUSY_MASK', + 'GRBM_STATUS_SE0__SPI_BUSY__SHIFT', + 'GRBM_STATUS_SE0__SX_BUSY_MASK', + 'GRBM_STATUS_SE0__SX_BUSY__SHIFT', + 'GRBM_STATUS_SE0__TA_BUSY_MASK', + 'GRBM_STATUS_SE0__TA_BUSY__SHIFT', + 'GRBM_STATUS_SE0__VGT_BUSY_MASK', + 'GRBM_STATUS_SE0__VGT_BUSY__SHIFT', + 'GRBM_STATUS_SE1__BCI_BUSY_MASK', + 'GRBM_STATUS_SE1__BCI_BUSY__SHIFT', + 'GRBM_STATUS_SE1__CB_BUSY_MASK', + 'GRBM_STATUS_SE1__CB_BUSY__SHIFT', + 'GRBM_STATUS_SE1__CB_CLEAN_MASK', + 'GRBM_STATUS_SE1__CB_CLEAN__SHIFT', + 'GRBM_STATUS_SE1__DB_BUSY_MASK', + 'GRBM_STATUS_SE1__DB_BUSY__SHIFT', + 'GRBM_STATUS_SE1__DB_CLEAN_MASK', + 'GRBM_STATUS_SE1__DB_CLEAN__SHIFT', + 'GRBM_STATUS_SE1__PA_BUSY_MASK', + 'GRBM_STATUS_SE1__PA_BUSY__SHIFT', + 'GRBM_STATUS_SE1__RMI_BUSY_MASK', + 'GRBM_STATUS_SE1__RMI_BUSY__SHIFT', + 'GRBM_STATUS_SE1__SC_BUSY_MASK', + 'GRBM_STATUS_SE1__SC_BUSY__SHIFT', + 'GRBM_STATUS_SE1__SPI_BUSY_MASK', + 'GRBM_STATUS_SE1__SPI_BUSY__SHIFT', + 'GRBM_STATUS_SE1__SX_BUSY_MASK', + 'GRBM_STATUS_SE1__SX_BUSY__SHIFT', + 'GRBM_STATUS_SE1__TA_BUSY_MASK', + 'GRBM_STATUS_SE1__TA_BUSY__SHIFT', + 'GRBM_STATUS_SE1__VGT_BUSY_MASK', + 'GRBM_STATUS_SE1__VGT_BUSY__SHIFT', + 'GRBM_STATUS_SE2__BCI_BUSY_MASK', + 'GRBM_STATUS_SE2__BCI_BUSY__SHIFT', + 'GRBM_STATUS_SE2__CB_BUSY_MASK', + 'GRBM_STATUS_SE2__CB_BUSY__SHIFT', + 'GRBM_STATUS_SE2__CB_CLEAN_MASK', + 'GRBM_STATUS_SE2__CB_CLEAN__SHIFT', + 'GRBM_STATUS_SE2__DB_BUSY_MASK', + 'GRBM_STATUS_SE2__DB_BUSY__SHIFT', + 'GRBM_STATUS_SE2__DB_CLEAN_MASK', + 'GRBM_STATUS_SE2__DB_CLEAN__SHIFT', + 'GRBM_STATUS_SE2__PA_BUSY_MASK', + 'GRBM_STATUS_SE2__PA_BUSY__SHIFT', + 'GRBM_STATUS_SE2__RMI_BUSY_MASK', + 'GRBM_STATUS_SE2__RMI_BUSY__SHIFT', + 'GRBM_STATUS_SE2__SC_BUSY_MASK', + 'GRBM_STATUS_SE2__SC_BUSY__SHIFT', + 'GRBM_STATUS_SE2__SPI_BUSY_MASK', + 'GRBM_STATUS_SE2__SPI_BUSY__SHIFT', + 'GRBM_STATUS_SE2__SX_BUSY_MASK', + 'GRBM_STATUS_SE2__SX_BUSY__SHIFT', + 'GRBM_STATUS_SE2__TA_BUSY_MASK', + 'GRBM_STATUS_SE2__TA_BUSY__SHIFT', + 'GRBM_STATUS_SE2__VGT_BUSY_MASK', + 'GRBM_STATUS_SE2__VGT_BUSY__SHIFT', + 'GRBM_STATUS_SE3__BCI_BUSY_MASK', + 'GRBM_STATUS_SE3__BCI_BUSY__SHIFT', + 'GRBM_STATUS_SE3__CB_BUSY_MASK', + 'GRBM_STATUS_SE3__CB_BUSY__SHIFT', + 'GRBM_STATUS_SE3__CB_CLEAN_MASK', + 'GRBM_STATUS_SE3__CB_CLEAN__SHIFT', + 'GRBM_STATUS_SE3__DB_BUSY_MASK', + 'GRBM_STATUS_SE3__DB_BUSY__SHIFT', + 'GRBM_STATUS_SE3__DB_CLEAN_MASK', + 'GRBM_STATUS_SE3__DB_CLEAN__SHIFT', + 'GRBM_STATUS_SE3__PA_BUSY_MASK', + 'GRBM_STATUS_SE3__PA_BUSY__SHIFT', + 'GRBM_STATUS_SE3__RMI_BUSY_MASK', + 'GRBM_STATUS_SE3__RMI_BUSY__SHIFT', + 'GRBM_STATUS_SE3__SC_BUSY_MASK', + 'GRBM_STATUS_SE3__SC_BUSY__SHIFT', + 'GRBM_STATUS_SE3__SPI_BUSY_MASK', + 'GRBM_STATUS_SE3__SPI_BUSY__SHIFT', + 'GRBM_STATUS_SE3__SX_BUSY_MASK', + 'GRBM_STATUS_SE3__SX_BUSY__SHIFT', + 'GRBM_STATUS_SE3__TA_BUSY_MASK', + 'GRBM_STATUS_SE3__TA_BUSY__SHIFT', + 'GRBM_STATUS_SE3__VGT_BUSY_MASK', + 'GRBM_STATUS_SE3__VGT_BUSY__SHIFT', 'GRBM_STATUS__BCI_BUSY_MASK', + 'GRBM_STATUS__BCI_BUSY__SHIFT', 'GRBM_STATUS__CB_BUSY_MASK', + 'GRBM_STATUS__CB_BUSY__SHIFT', 'GRBM_STATUS__CB_CLEAN_MASK', + 'GRBM_STATUS__CB_CLEAN__SHIFT', 'GRBM_STATUS__CP_BUSY_MASK', + 'GRBM_STATUS__CP_BUSY__SHIFT', + 'GRBM_STATUS__CP_COHERENCY_BUSY_MASK', + 'GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT', + 'GRBM_STATUS__DB_BUSY_MASK', 'GRBM_STATUS__DB_BUSY__SHIFT', + 'GRBM_STATUS__DB_CLEAN_MASK', 'GRBM_STATUS__DB_CLEAN__SHIFT', + 'GRBM_STATUS__GDS_BUSY_MASK', 'GRBM_STATUS__GDS_BUSY__SHIFT', + 'GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK', + 'GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT', + 'GRBM_STATUS__GUI_ACTIVE_MASK', 'GRBM_STATUS__GUI_ACTIVE__SHIFT', + 'GRBM_STATUS__IA_BUSY_MASK', 'GRBM_STATUS__IA_BUSY_NO_DMA_MASK', + 'GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT', + 'GRBM_STATUS__IA_BUSY__SHIFT', + 'GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK', + 'GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT', + 'GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK', + 'GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT', + 'GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK', + 'GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT', + 'GRBM_STATUS__PA_BUSY_MASK', 'GRBM_STATUS__PA_BUSY__SHIFT', + 'GRBM_STATUS__RSMU_RQ_PENDING_MASK', + 'GRBM_STATUS__RSMU_RQ_PENDING__SHIFT', + 'GRBM_STATUS__SC_BUSY_MASK', 'GRBM_STATUS__SC_BUSY__SHIFT', + 'GRBM_STATUS__SPI_BUSY_MASK', 'GRBM_STATUS__SPI_BUSY__SHIFT', + 'GRBM_STATUS__SX_BUSY_MASK', 'GRBM_STATUS__SX_BUSY__SHIFT', + 'GRBM_STATUS__TA_BUSY_MASK', 'GRBM_STATUS__TA_BUSY__SHIFT', + 'GRBM_STATUS__VGT_BUSY_MASK', 'GRBM_STATUS__VGT_BUSY__SHIFT', + 'GRBM_STATUS__WD_BUSY_MASK', 'GRBM_STATUS__WD_BUSY_NO_DMA_MASK', + 'GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT', + 'GRBM_STATUS__WD_BUSY__SHIFT', 'GRBM_TRAP_ADDR_MSK__DATA_MASK', + 'GRBM_TRAP_ADDR_MSK__DATA__SHIFT', 'GRBM_TRAP_ADDR__DATA_MASK', + 'GRBM_TRAP_ADDR__DATA__SHIFT', 'GRBM_TRAP_OP__RW_MASK', + 'GRBM_TRAP_OP__RW__SHIFT', 'GRBM_TRAP_WD_MSK__DATA_MASK', + 'GRBM_TRAP_WD_MSK__DATA__SHIFT', 'GRBM_TRAP_WD__DATA_MASK', + 'GRBM_TRAP_WD__DATA__SHIFT', + 'GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK', + 'GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT', + 'GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK', + 'GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT', + 'GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK', + 'GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT', + 'GRBM_WRITE_ERROR__CP_SECURE_WR_ILLEGAL_MASK', + 'GRBM_WRITE_ERROR__CP_SECURE_WR_ILLEGAL__SHIFT', + 'GRBM_WRITE_ERROR__TMZ_MASK', 'GRBM_WRITE_ERROR__TMZ__SHIFT', + 'GRBM_WRITE_ERROR__WRITE_ERROR_MASK', + 'GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT', + 'GRBM_WRITE_ERROR__WRITE_MEID_MASK', + 'GRBM_WRITE_ERROR__WRITE_MEID__SHIFT', + 'GRBM_WRITE_ERROR__WRITE_PIPEID_MASK', + 'GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT', + 'GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK', + 'GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT', + 'GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK', + 'GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT', + 'GRBM_WRITE_ERROR__WRITE_SSRCID_MASK', + 'GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT', + 'GRBM_WRITE_ERROR__WRITE_VFID_MASK', + 'GRBM_WRITE_ERROR__WRITE_VFID__SHIFT', + 'GRBM_WRITE_ERROR__WRITE_VF_MASK', + 'GRBM_WRITE_ERROR__WRITE_VF__SHIFT', + 'GRBM_WRITE_ERROR__WRITE_VMID_MASK', + 'GRBM_WRITE_ERROR__WRITE_VMID__SHIFT', + 'IA_CNTL_STATUS__IA_ADC_BUSY_MASK', + 'IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT', + 'IA_CNTL_STATUS__IA_BUSY_MASK', 'IA_CNTL_STATUS__IA_BUSY__SHIFT', + 'IA_CNTL_STATUS__IA_DMA_BUSY_MASK', + 'IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT', + 'IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK', + 'IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT', + 'IA_CNTL_STATUS__IA_GRP_BUSY_MASK', + 'IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT', 'IA_ENHANCE__MISC_MASK', + 'IA_ENHANCE__MISC__SHIFT', + 'IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK', + 'IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV__SHIFT', + 'IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK', + 'IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC__SHIFT', + 'IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK', + 'IA_MULTI_VGT_PARAM__HW_USE_ONLY__SHIFT', + 'IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK', + 'IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT', + 'IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK', + 'IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT', + 'IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK', + 'IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT', + 'IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK', + 'IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT', + 'IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK', + 'IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT', + 'IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK', + 'IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT', + 'IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'IA_UTCL1_CNTL__BYPASS_MASK', 'IA_UTCL1_CNTL__BYPASS__SHIFT', + 'IA_UTCL1_CNTL__DROP_MODE_MASK', + 'IA_UTCL1_CNTL__DROP_MODE__SHIFT', + 'IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK', + 'IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT', + 'IA_UTCL1_CNTL__FORCE_SNOOP_MASK', + 'IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT', + 'IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK', + 'IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT', + 'IA_UTCL1_CNTL__INVALIDATE_MASK', + 'IA_UTCL1_CNTL__INVALIDATE__SHIFT', + 'IA_UTCL1_CNTL__VMID_RESET_MODE_MASK', + 'IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT', + 'IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK', + 'IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT', + 'IA_UTCL1_STATUS__FAULT_DETECTED_MASK', + 'IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT', + 'IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK', + 'IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT', + 'IA_UTCL1_STATUS__PRT_DETECTED_MASK', + 'IA_UTCL1_STATUS__PRT_DETECTED__SHIFT', + 'IA_UTCL1_STATUS__PRT_UTCL1ID_MASK', + 'IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT', + 'IA_UTCL1_STATUS__RETRY_DETECTED_MASK', + 'IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT', + 'IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK', + 'IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT', + 'L2TLB_PERFCOUNTER0_CFG__CLEAR_MASK', + 'L2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'L2TLB_PERFCOUNTER0_CFG__ENABLE_MASK', + 'L2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'L2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'L2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'L2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'L2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'L2TLB_PERFCOUNTER1_CFG__CLEAR_MASK', + 'L2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'L2TLB_PERFCOUNTER1_CFG__ENABLE_MASK', + 'L2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'L2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'L2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'L2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'L2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'L2TLB_PERFCOUNTER2_CFG__CLEAR_MASK', + 'L2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT', + 'L2TLB_PERFCOUNTER2_CFG__ENABLE_MASK', + 'L2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT', + 'L2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK', + 'L2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT', + 'L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK', + 'L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT', + 'L2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK', + 'L2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT', + 'L2TLB_PERFCOUNTER3_CFG__CLEAR_MASK', + 'L2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT', + 'L2TLB_PERFCOUNTER3_CFG__ENABLE_MASK', + 'L2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT', + 'L2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK', + 'L2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT', + 'L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK', + 'L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT', + 'L2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK', + 'L2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT', + 'L2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'L2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'L2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'L2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'L2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'L2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'L2TLB_TLB0_STATUS__BUSY_MASK', 'L2TLB_TLB0_STATUS__BUSY__SHIFT', + 'L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK', + 'L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT', + 'LDS_CE_ERR_STATUS_HI__CE_CNT_MASK', + 'LDS_CE_ERR_STATUS_HI__CE_CNT__SHIFT', + 'LDS_CE_ERR_STATUS_HI__ECC_MASK', + 'LDS_CE_ERR_STATUS_HI__ECC__SHIFT', + 'LDS_CE_ERR_STATUS_HI__ERR_INFO_MASK', + 'LDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'LDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'LDS_CE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'LDS_CE_ERR_STATUS_HI__OTHER_MASK', + 'LDS_CE_ERR_STATUS_HI__OTHER__SHIFT', + 'LDS_CE_ERR_STATUS_HI__POISON_MASK', + 'LDS_CE_ERR_STATUS_HI__POISON__SHIFT', + 'LDS_CE_ERR_STATUS_HI__RESERVED_MASK', + 'LDS_CE_ERR_STATUS_HI__RESERVED__SHIFT', + 'LDS_CE_ERR_STATUS_LO__ADDRESS_MASK', + 'LDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'LDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'LDS_CE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'LDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'LDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'LDS_CE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'LDS_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK', + 'LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT', + 'LDS_CONFIG__DISABLE_ATODFPCLK_MGCG_MASK', + 'LDS_CONFIG__DISABLE_ATODFPCLK_MGCG__SHIFT', + 'LDS_CONFIG__DISABLE_ATTRCLK_MGCG_MASK', + 'LDS_CONFIG__DISABLE_ATTRCLK_MGCG__SHIFT', + 'LDS_CONFIG__DISABLE_IDXCLK_MGCG_MASK', + 'LDS_CONFIG__DISABLE_IDXCLK_MGCG__SHIFT', + 'LDS_CONFIG__DISABLE_LDS_SP_READ_FGCG_MASK', + 'LDS_CONFIG__DISABLE_LDS_SP_READ_FGCG__SHIFT', + 'LDS_CONFIG__DISABLE_MEMCLK_MGCG_MASK', + 'LDS_CONFIG__DISABLE_MEMCLK_MGCG__SHIFT', + 'LDS_CONFIG__DISABLE_PHASE_FGCG_MASK', + 'LDS_CONFIG__DISABLE_PHASE_FGCG__SHIFT', + 'LDS_CONFIG__DISABLE_RAM_CLOCK_GATING_MASK', + 'LDS_CONFIG__DISABLE_RAM_CLOCK_GATING__SHIFT', + 'LDS_CONFIG__DISABLE_SP_DATA_CLOCK_GATING_MASK', + 'LDS_CONFIG__DISABLE_SP_DATA_CLOCK_GATING__SHIFT', + 'LDS_CONFIG__DISABLE_TD_DATA_CLOCK_GATING_MASK', + 'LDS_CONFIG__DISABLE_TD_DATA_CLOCK_GATING__SHIFT', + 'LDS_CONFIG__TMZ_VIOLATION_REPORTING_MASK', + 'LDS_CONFIG__TMZ_VIOLATION_REPORTING__SHIFT', + 'LDS_UE_ERR_STATUS_HI__ECC_MASK', + 'LDS_UE_ERR_STATUS_HI__ECC__SHIFT', + 'LDS_UE_ERR_STATUS_HI__ERR_INFO_MASK', + 'LDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'LDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'LDS_UE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'LDS_UE_ERR_STATUS_HI__FED_CNT_MASK', + 'LDS_UE_ERR_STATUS_HI__FED_CNT__SHIFT', + 'LDS_UE_ERR_STATUS_HI__PARITY_MASK', + 'LDS_UE_ERR_STATUS_HI__PARITY__SHIFT', + 'LDS_UE_ERR_STATUS_HI__RESERVED_MASK', + 'LDS_UE_ERR_STATUS_HI__RESERVED__SHIFT', + 'LDS_UE_ERR_STATUS_HI__UE_CNT_MASK', + 'LDS_UE_ERR_STATUS_HI__UE_CNT__SHIFT', + 'LDS_UE_ERR_STATUS_LO__ADDRESS_MASK', + 'LDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'LDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'LDS_UE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'LDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'LDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'LDS_UE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'LDS_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'MC_MEM_POWER_LS__LS_HOLD_MASK', + 'MC_MEM_POWER_LS__LS_HOLD__SHIFT', + 'MC_MEM_POWER_LS__LS_SETUP_MASK', + 'MC_MEM_POWER_LS__LS_SETUP__SHIFT', + 'MC_SHARED_ACTIVE_FCN_ID__VFID_MASK', + 'MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT', + 'MC_SHARED_ACTIVE_FCN_ID__VF_MASK', + 'MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT', + 'MC_SHARED_VIRT_RESET_REQ__PF_MASK', + 'MC_SHARED_VIRT_RESET_REQ__PF__SHIFT', + 'MC_SHARED_VIRT_RESET_REQ__VF_MASK', + 'MC_SHARED_VIRT_RESET_REQ__VF__SHIFT', + 'MC_VM_AGP_BASE__AGP_BASE_MASK', + 'MC_VM_AGP_BASE__AGP_BASE__SHIFT', 'MC_VM_AGP_BOT__AGP_BOT_MASK', + 'MC_VM_AGP_BOT__AGP_BOT__SHIFT', 'MC_VM_AGP_TOP__AGP_TOP_MASK', + 'MC_VM_AGP_TOP__AGP_TOP__SHIFT', + 'MC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK', + 'MC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT', + 'MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK', + 'MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT', + 'MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK', + 'MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT', + 'MC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK', + 'MC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT', + 'MC_VM_APT_CNTL__PERMS_GRANTED_MASK', + 'MC_VM_APT_CNTL__PERMS_GRANTED__SHIFT', + 'MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK', + 'MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT', + 'MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK', + 'MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT', + 'MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK', + 'MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT', + 'MC_VM_FB_LOCATION_BASE__FB_BASE_MASK', + 'MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT', + 'MC_VM_FB_LOCATION_TOP__FB_TOP_MASK', + 'MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT', + 'MC_VM_FB_OFFSET__FB_OFFSET_MASK', + 'MC_VM_FB_OFFSET__FB_OFFSET__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT', + 'MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK', + 'MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT', + 'MC_VM_HOST_MAPPING__MODE_MASK', + 'MC_VM_HOST_MAPPING__MODE__SHIFT', + 'MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK', + 'MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK', + 'MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK', + 'MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK', + 'MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK', + 'MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT', + 'MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK', + 'MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT', + 'MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK', + 'MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT', + 'MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK', + 'MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT', + 'MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK', + 'MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT', + 'MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK', + 'MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT', + 'MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK', + 'MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT', + 'MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK', + 'MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT', + 'MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK', + 'MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT', + 'MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK', + 'MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT', + 'MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK', + 'MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT', + 'MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK', + 'MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT', + 'MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK', + 'MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT', + 'MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK', + 'MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT', + 'MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK', + 'MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT', + 'MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK', + 'MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT', + 'MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK', + 'MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT', + 'MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK', + 'MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT', + 'MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK', + 'MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT', + 'MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK', + 'MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT', + 'MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK', + 'MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT', + 'MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK', + 'MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT', + 'MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK', + 'MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT', + 'MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK', + 'MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT', + 'MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK', + 'MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT', + 'MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK', + 'MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT', + 'MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK', + 'MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT', + 'MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK', + 'MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT', + 'MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK', + 'MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT', + 'MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK', + 'MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT', + 'MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK', + 'MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT', + 'MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK', + 'MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT', + 'MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK', + 'MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT', + 'MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK', + 'MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT', + 'MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK', + 'MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT', + 'MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK', + 'MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT', + 'MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK', + 'MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT', + 'MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK', + 'MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT', + 'MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK', + 'MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT', + 'MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK', + 'MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT', + 'MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK', + 'MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT', + 'MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK', + 'MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT', + 'MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK', + 'MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT', + 'MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK', + 'MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT', + 'MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK', + 'MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT', + 'MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK', + 'MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT', + 'MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK', + 'MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT', + 'MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK', + 'MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT', + 'MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK', + 'MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT', + 'MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK', + 'MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT', + 'MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK', + 'MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT', + 'MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK', + 'MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT', + 'MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK', + 'MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT', + 'MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK', + 'MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT', + 'MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK', + 'MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT', + 'MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK', + 'MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT', + 'MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK', + 'MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT', + 'MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK', + 'MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT', + 'MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK', + 'MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT', + 'MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK', + 'MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT', + 'MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK', + 'MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT', + 'MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK', + 'MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT', + 'MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK', + 'MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT', + 'MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK', + 'MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT', + 'MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK', + 'MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT', + 'MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK', + 'MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT', + 'MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK', + 'MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT', + 'MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK', + 'MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT', + 'MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK', + 'MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT', + 'MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK', + 'MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT', + 'MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK', + 'MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT', + 'MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK', + 'MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT', + 'MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK', + 'MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT', + 'MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK', + 'MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT', + 'MC_VM_NB_MMIOBASE__MMIOBASE_MASK', + 'MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT', + 'MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK', + 'MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT', + 'MC_VM_NB_PCI_ARB__VGA_HOLE_MASK', + 'MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT', + 'MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK', + 'MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT', + 'MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK', + 'MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT', + 'MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK', + 'MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT', + 'MC_VM_STEERING__DEFAULT_STEERING_MASK', + 'MC_VM_STEERING__DEFAULT_STEERING__SHIFT', + 'MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK', + 'MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT', + 'MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK', + 'MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT', + 'MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK', + 'MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT', + 'MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK', + 'MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK', + 'MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT', + 'MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK', + 'MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT', + 'MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK', + 'MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT', + 'MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK', + 'MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT', + 'PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK', + 'PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT', + 'PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK', + 'PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT', + 'PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK', + 'PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT', + 'PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK', + 'PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT', + 'PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK', + 'PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT', + 'PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK', + 'PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT', + 'PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK', + 'PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT', + 'PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK', + 'PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT', + 'PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK', + 'PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT', + 'PA_CL_CLIP_CNTL__UCP_ENA_0_MASK', + 'PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT', + 'PA_CL_CLIP_CNTL__UCP_ENA_1_MASK', + 'PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT', + 'PA_CL_CLIP_CNTL__UCP_ENA_2_MASK', + 'PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT', + 'PA_CL_CLIP_CNTL__UCP_ENA_3_MASK', + 'PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT', + 'PA_CL_CLIP_CNTL__UCP_ENA_4_MASK', + 'PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT', + 'PA_CL_CLIP_CNTL__UCP_ENA_5_MASK', + 'PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT', + 'PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK', + 'PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT', + 'PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK', + 'PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT', + 'PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK', + 'PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT', + 'PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK', + 'PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT', + 'PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA_MASK', + 'PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA__SHIFT', + 'PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK', + 'PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT', + 'PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK', + 'PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT', + 'PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK', + 'PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT', + 'PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK', + 'PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT', + 'PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK', + 'PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT', + 'PA_CL_ENHANCE__ECO_SPARE0_MASK', + 'PA_CL_ENHANCE__ECO_SPARE0__SHIFT', + 'PA_CL_ENHANCE__ECO_SPARE1_MASK', + 'PA_CL_ENHANCE__ECO_SPARE1__SHIFT', + 'PA_CL_ENHANCE__ECO_SPARE2_MASK', + 'PA_CL_ENHANCE__ECO_SPARE2__SHIFT', + 'PA_CL_ENHANCE__ECO_SPARE3_MASK', + 'PA_CL_ENHANCE__ECO_SPARE3__SHIFT', + 'PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK', + 'PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT', + 'PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK', + 'PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT', + 'PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK', + 'PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT', + 'PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK', + 'PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT', + 'PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK', + 'PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT', + 'PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK', + 'PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT', + 'PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET_MASK', + 'PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET__SHIFT', + 'PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK', + 'PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT', + 'PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT_MASK', + 'PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT__SHIFT', + 'PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK', + 'PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT', + 'PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK', + 'PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT', + 'PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK', + 'PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT', + 'PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK', + 'PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT', + 'PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK', + 'PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT', + 'PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK', + 'PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT', + 'PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK', + 'PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT', + 'PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK', + 'PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT', + 'PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK', + 'PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT', + 'PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK', + 'PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT', + 'PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK', + 'PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT', + 'PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK', + 'PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT', + 'PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK', + 'PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT', + 'PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK', + 'PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT', + 'PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK', + 'PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT', + 'PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK', + 'PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT', + 'PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK', + 'PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT', + 'PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK', + 'PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT', + 'PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK', + 'PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT', + 'PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK', + 'PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT', + 'PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK', + 'PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT', + 'PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK', + 'PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT', + 'PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK', + 'PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT', + 'PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK', + 'PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT', + 'PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK', + 'PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT', + 'PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK', + 'PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT', + 'PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK', + 'PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT', + 'PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK', + 'PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT', + 'PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK', + 'PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT', + 'PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID_MASK', + 'PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID__SHIFT', + 'PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK', + 'PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT', + 'PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK', + 'PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT', + 'PA_CL_POINT_SIZE__DATA_REGISTER_MASK', + 'PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT', + 'PA_CL_POINT_X_RAD__DATA_REGISTER_MASK', + 'PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT', + 'PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK', + 'PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT', + 'PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER_MASK', + 'PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER__SHIFT', + 'PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK', + 'PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT', + 'PA_CL_UCP_0_W__DATA_REGISTER_MASK', + 'PA_CL_UCP_0_W__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_0_X__DATA_REGISTER_MASK', + 'PA_CL_UCP_0_X__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_0_Y__DATA_REGISTER_MASK', + 'PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_0_Z__DATA_REGISTER_MASK', + 'PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_1_W__DATA_REGISTER_MASK', + 'PA_CL_UCP_1_W__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_1_X__DATA_REGISTER_MASK', + 'PA_CL_UCP_1_X__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_1_Y__DATA_REGISTER_MASK', + 'PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_1_Z__DATA_REGISTER_MASK', + 'PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_2_W__DATA_REGISTER_MASK', + 'PA_CL_UCP_2_W__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_2_X__DATA_REGISTER_MASK', + 'PA_CL_UCP_2_X__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_2_Y__DATA_REGISTER_MASK', + 'PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_2_Z__DATA_REGISTER_MASK', + 'PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_3_W__DATA_REGISTER_MASK', + 'PA_CL_UCP_3_W__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_3_X__DATA_REGISTER_MASK', + 'PA_CL_UCP_3_X__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_3_Y__DATA_REGISTER_MASK', + 'PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_3_Z__DATA_REGISTER_MASK', + 'PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_4_W__DATA_REGISTER_MASK', + 'PA_CL_UCP_4_W__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_4_X__DATA_REGISTER_MASK', + 'PA_CL_UCP_4_X__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_4_Y__DATA_REGISTER_MASK', + 'PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_4_Z__DATA_REGISTER_MASK', + 'PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_5_W__DATA_REGISTER_MASK', + 'PA_CL_UCP_5_W__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_5_X__DATA_REGISTER_MASK', + 'PA_CL_UCP_5_X__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_5_Y__DATA_REGISTER_MASK', + 'PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT', + 'PA_CL_UCP_5_Z__DATA_REGISTER_MASK', + 'PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT', + 'PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK', + 'PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT', + 'PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK', + 'PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT', + 'PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK', + 'PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT', + 'PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK', + 'PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT', + 'PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK', + 'PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT', + 'PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT', + 'PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK', + 'PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK', + 'PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK', + 'PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT', + 'PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK', + 'PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT', + 'PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK', + 'PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT', + 'PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK', + 'PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT', + 'PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK', + 'PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT', + 'PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK', + 'PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT', + 'PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK', + 'PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT', + 'PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK', + 'PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT', + 'PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK', + 'PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT', + 'PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK', + 'PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT', + 'PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK', + 'PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT', + 'PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK', + 'PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT', + 'PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK', + 'PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT', + 'PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK', + 'PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT', + 'PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK', + 'PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT', + 'PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK', + 'PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT', + 'PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK', + 'PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT', + 'PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK', + 'PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT', + 'PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK', + 'PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT', + 'PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK', + 'PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT', + 'PA_CL_VTE_CNTL__VTX_W0_FMT_MASK', + 'PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT', + 'PA_CL_VTE_CNTL__VTX_XY_FMT_MASK', + 'PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT', + 'PA_CL_VTE_CNTL__VTX_Z_FMT_MASK', + 'PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT', + 'PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK', + 'PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT', + 'PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK', + 'PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT', + 'PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK', + 'PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT', + 'PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK', + 'PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT', + 'PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK', + 'PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT', + 'PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK', + 'PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT', + 'PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK', + 'PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT', + 'PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK', + 'PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT', + 'PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK', + 'PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT', + 'PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK', + 'PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK', + 'PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT', + 'PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK', + 'PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT', + 'PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK', + 'PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT', + 'PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK', + 'PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT', + 'PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK', + 'PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT', + 'PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK', + 'PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT', + 'PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK', + 'PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT', + 'PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK', + 'PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT', + 'PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION_MASK', + 'PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION__SHIFT', + 'PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK', + 'PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT', + 'PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK', + 'PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT', + 'PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK', + 'PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT', + 'PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK', + 'PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT', + 'PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK', + 'PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK', + 'PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK', + 'PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK', + 'PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT', + 'PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK', + 'PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT', + 'PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK', + 'PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT', + 'PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK', + 'PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT', + 'PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK', + 'PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT', + 'PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK', + 'PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT', + 'PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK', + 'PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT', + 'PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK', + 'PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT', + 'PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK', + 'PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT', + 'PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK', + 'PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT', + 'PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK', + 'PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT', + 'PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK', + 'PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT', + 'PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK', + 'PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK', + 'PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK', + 'PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT', + 'PA_SC_CLIPRECT_0_BR__BR_X_MASK', + 'PA_SC_CLIPRECT_0_BR__BR_X__SHIFT', + 'PA_SC_CLIPRECT_0_BR__BR_Y_MASK', + 'PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT', + 'PA_SC_CLIPRECT_0_TL__TL_X_MASK', + 'PA_SC_CLIPRECT_0_TL__TL_X__SHIFT', + 'PA_SC_CLIPRECT_0_TL__TL_Y_MASK', + 'PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT', + 'PA_SC_CLIPRECT_1_BR__BR_X_MASK', + 'PA_SC_CLIPRECT_1_BR__BR_X__SHIFT', + 'PA_SC_CLIPRECT_1_BR__BR_Y_MASK', + 'PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT', + 'PA_SC_CLIPRECT_1_TL__TL_X_MASK', + 'PA_SC_CLIPRECT_1_TL__TL_X__SHIFT', + 'PA_SC_CLIPRECT_1_TL__TL_Y_MASK', + 'PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT', + 'PA_SC_CLIPRECT_2_BR__BR_X_MASK', + 'PA_SC_CLIPRECT_2_BR__BR_X__SHIFT', + 'PA_SC_CLIPRECT_2_BR__BR_Y_MASK', + 'PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT', + 'PA_SC_CLIPRECT_2_TL__TL_X_MASK', + 'PA_SC_CLIPRECT_2_TL__TL_X__SHIFT', + 'PA_SC_CLIPRECT_2_TL__TL_Y_MASK', + 'PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT', + 'PA_SC_CLIPRECT_3_BR__BR_X_MASK', + 'PA_SC_CLIPRECT_3_BR__BR_X__SHIFT', + 'PA_SC_CLIPRECT_3_BR__BR_Y_MASK', + 'PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT', + 'PA_SC_CLIPRECT_3_TL__TL_X_MASK', + 'PA_SC_CLIPRECT_3_TL__TL_X__SHIFT', + 'PA_SC_CLIPRECT_3_TL__TL_Y_MASK', + 'PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT', + 'PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK', + 'PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK', + 'PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT', + 'PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK', + 'PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT', + 'PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK', + 'PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT', + 'PA_SC_EDGERULE__ER_LINE_BT_MASK', + 'PA_SC_EDGERULE__ER_LINE_BT__SHIFT', + 'PA_SC_EDGERULE__ER_LINE_LR_MASK', + 'PA_SC_EDGERULE__ER_LINE_LR__SHIFT', + 'PA_SC_EDGERULE__ER_LINE_RL_MASK', + 'PA_SC_EDGERULE__ER_LINE_RL__SHIFT', + 'PA_SC_EDGERULE__ER_LINE_TB_MASK', + 'PA_SC_EDGERULE__ER_LINE_TB__SHIFT', + 'PA_SC_EDGERULE__ER_POINT_MASK', + 'PA_SC_EDGERULE__ER_POINT__SHIFT', 'PA_SC_EDGERULE__ER_RECT_MASK', + 'PA_SC_EDGERULE__ER_RECT__SHIFT', 'PA_SC_EDGERULE__ER_TRI_MASK', + 'PA_SC_EDGERULE__ER_TRI__SHIFT', + 'PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK', + 'PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT', + 'PA_SC_ENHANCE_1__BYPASS_PBB_MASK', + 'PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT', + 'PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK_MASK', + 'PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK', + 'PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK', + 'PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK', + 'PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK', + 'PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK', + 'PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK', + 'PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK', + 'PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK', + 'PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK', + 'PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK', + 'PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK', + 'PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK', + 'PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK', + 'PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK', + 'PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK', + 'PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT', + 'PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK', + 'PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT', + 'PA_SC_ENHANCE_1__ECO_SPARE0_MASK', + 'PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT', + 'PA_SC_ENHANCE_1__ECO_SPARE1_MASK', + 'PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT', + 'PA_SC_ENHANCE_1__ECO_SPARE2_MASK', + 'PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT', + 'PA_SC_ENHANCE_1__ECO_SPARE3_MASK', + 'PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT', + 'PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK', + 'PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT', + 'PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK', + 'PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT', + 'PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK', + 'PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT', + 'PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK', + 'PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT', + 'PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK', + 'PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT', + 'PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK', + 'PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT', + 'PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK', + 'PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT', + 'PA_SC_ENHANCE_1__RSVD_MASK', 'PA_SC_ENHANCE_1__RSVD__SHIFT', + 'PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN_MASK', + 'PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN__SHIFT', + 'PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PIPELINE_PRIMID_MASK', + 'PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PIPELINE_PRIMID__SHIFT', + 'PA_SC_ENHANCE_2__RESERVED_0_MASK', + 'PA_SC_ENHANCE_2__RESERVED_0__SHIFT', + 'PA_SC_ENHANCE_2__RESERVED_1_MASK', + 'PA_SC_ENHANCE_2__RESERVED_1__SHIFT', + 'PA_SC_ENHANCE_2__RESERVED_2_MASK', + 'PA_SC_ENHANCE_2__RESERVED_2__SHIFT', + 'PA_SC_ENHANCE_2__RESERVED_3_MASK', + 'PA_SC_ENHANCE_2__RESERVED_3__SHIFT', + 'PA_SC_ENHANCE_2__RESERVED_4_MASK', + 'PA_SC_ENHANCE_2__RESERVED_4__SHIFT', + 'PA_SC_ENHANCE_2__RESERVED_5_MASK', + 'PA_SC_ENHANCE_2__RESERVED_5__SHIFT', + 'PA_SC_ENHANCE_2__RSVD_MASK', 'PA_SC_ENHANCE_2__RSVD__SHIFT', + 'PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK', + 'PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT', + 'PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK', + 'PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT', + 'PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK', + 'PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT', + 'PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK', + 'PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT', + 'PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK', + 'PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK', + 'PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT', + 'PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK', + 'PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT', + 'PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK', + 'PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT', + 'PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK', + 'PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT', + 'PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK', + 'PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT', + 'PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK', + 'PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT', + 'PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK', + 'PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT', + 'PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK', + 'PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT', + 'PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK', + 'PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT', + 'PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK', + 'PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT', + 'PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK', + 'PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT', + 'PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK', + 'PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT', + 'PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK', + 'PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT', + 'PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK', + 'PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT', + 'PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK', + 'PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT', + 'PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK', + 'PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT', + 'PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK', + 'PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT', + 'PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK', + 'PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT', + 'PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK', + 'PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT', + 'PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK', + 'PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT', + 'PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK', + 'PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT', + 'PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK', + 'PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT', + 'PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK', + 'PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT', + 'PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK', + 'PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT', + 'PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK', + 'PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT', + 'PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK', + 'PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT', + 'PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK', + 'PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT', + 'PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK', + 'PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT', + 'PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK', + 'PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT', + 'PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK', + 'PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT', + 'PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK', + 'PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT', + 'PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_HORIZ_GRID__BOT_HALF_MASK', + 'PA_SC_HORIZ_GRID__BOT_HALF__SHIFT', + 'PA_SC_HORIZ_GRID__BOT_QTR_MASK', + 'PA_SC_HORIZ_GRID__BOT_QTR__SHIFT', + 'PA_SC_HORIZ_GRID__TOP_HALF_MASK', + 'PA_SC_HORIZ_GRID__TOP_HALF__SHIFT', + 'PA_SC_HORIZ_GRID__TOP_QTR_MASK', + 'PA_SC_HORIZ_GRID__TOP_QTR__SHIFT', + 'PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK', + 'PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT', + 'PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK', + 'PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT', + 'PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK', + 'PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT', + 'PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK', + 'PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT', + 'PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK', + 'PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT', + 'PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK', + 'PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT', + 'PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK', + 'PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT', + 'PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK', + 'PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT', + 'PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK', + 'PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT', + 'PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK', + 'PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT', + 'PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK', + 'PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT', + 'PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK', + 'PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT', + 'PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK', + 'PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT', + 'PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK', + 'PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT', + 'PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK', + 'PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT', + 'PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK', + 'PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT', + 'PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK', + 'PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT', + 'PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION_MASK', + 'PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION__SHIFT', + 'PA_SC_LINE_CNTL__LAST_PIXEL_MASK', + 'PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT', + 'PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK', + 'PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT', + 'PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK', + 'PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT', + 'PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK', + 'PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT', + 'PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK', + 'PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT', + 'PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK', + 'PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT', + 'PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK', + 'PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT', + 'PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK', + 'PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT', + 'PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK', + 'PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT', + 'PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK', + 'PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT', + 'PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK', + 'PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK', + 'PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK', + 'PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT', + 'PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK', + 'PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT', + 'PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK', + 'PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK', + 'PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK', + 'PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK', + 'PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK', + 'PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT', + 'PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK', + 'PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT', + 'PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK', + 'PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT', + 'PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK', + 'PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK', + 'PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK', + 'PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK', + 'PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK', + 'PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT', + 'PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK', + 'PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT', + 'PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK', + 'PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK', + 'PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK', + 'PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT', + 'PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK', + 'PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK', + 'PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT', + 'PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK', + 'PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT', + 'PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK', + 'PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT', + 'PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK', + 'PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT', + 'PA_SC_MODE_CNTL_1__WALK_SIZE_MASK', + 'PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT', + 'PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK', + 'PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT', + 'PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK', + 'PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT', + 'PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK', + 'PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT', + 'PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK', + 'PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT', + 'PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK', + 'PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT', + 'PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK', + 'PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT', + 'PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK', + 'PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT', + 'PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK', + 'PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT', + 'PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK', + 'PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT', + 'PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK', + 'PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT', + 'PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK', + 'PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT', + 'PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'PA_SC_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'PA_SC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK', + 'PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK', + 'PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK', + 'PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT', + 'PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK', + 'PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK', + 'PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK', + 'PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT', + 'PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK', + 'PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK', + 'PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK', + 'PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT', + 'PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK', + 'PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK', + 'PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK', + 'PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT', + 'PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK', + 'PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT', + 'PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK', + 'PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT', + 'PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK', + 'PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT', + 'PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK', + 'PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT', + 'PA_SC_RASTER_CONFIG__PKR_MAP_MASK', + 'PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT', + 'PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK', + 'PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT', + 'PA_SC_RASTER_CONFIG__PKR_XSEL_MASK', + 'PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT', + 'PA_SC_RASTER_CONFIG__PKR_YSEL_MASK', + 'PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT', + 'PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK', + 'PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT', + 'PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK', + 'PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT', + 'PA_SC_RASTER_CONFIG__RB_XSEL2_MASK', + 'PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT', + 'PA_SC_RASTER_CONFIG__RB_XSEL_MASK', + 'PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT', + 'PA_SC_RASTER_CONFIG__RB_YSEL_MASK', + 'PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT', + 'PA_SC_RASTER_CONFIG__SC_MAP_MASK', + 'PA_SC_RASTER_CONFIG__SC_MAP__SHIFT', + 'PA_SC_RASTER_CONFIG__SC_XSEL_MASK', + 'PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT', + 'PA_SC_RASTER_CONFIG__SC_YSEL_MASK', + 'PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT', + 'PA_SC_RASTER_CONFIG__SE_MAP_MASK', + 'PA_SC_RASTER_CONFIG__SE_MAP__SHIFT', + 'PA_SC_RASTER_CONFIG__SE_XSEL_MASK', + 'PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT', + 'PA_SC_RASTER_CONFIG__SE_YSEL_MASK', + 'PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT', + 'PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK', + 'PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT', + 'PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK', + 'PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT', + 'PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK', + 'PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT', + 'PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK', + 'PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT', + 'PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK', + 'PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT', + 'PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK', + 'PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT', + 'PA_SC_SCREEN_EXTENT_MAX_0__X_MASK', + 'PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT', + 'PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK', + 'PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT', + 'PA_SC_SCREEN_EXTENT_MAX_1__X_MASK', + 'PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT', + 'PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK', + 'PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT', + 'PA_SC_SCREEN_EXTENT_MIN_0__X_MASK', + 'PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT', + 'PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK', + 'PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT', + 'PA_SC_SCREEN_EXTENT_MIN_1__X_MASK', + 'PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT', + 'PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK', + 'PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT', + 'PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK', + 'PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT', + 'PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK', + 'PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT', + 'PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK', + 'PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT', + 'PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK', + 'PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT', + 'PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK', + 'PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT', + 'PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK', + 'PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT', + 'PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK', + 'PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT', + 'PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK', + 'PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT', + 'PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK', + 'PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT', + 'PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK', + 'PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT', + 'PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK', + 'PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT', + 'PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK', + 'PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT', + 'PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK', + 'PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT', + 'PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK', + 'PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT', + 'PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK', + 'PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT', + 'PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK', + 'PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT', + 'PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK', + 'PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT', + 'PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK', + 'PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT', + 'PA_SC_TRAP_SCREEN_H__X_COORD_MASK', + 'PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT', + 'PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK', + 'PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT', + 'PA_SC_TRAP_SCREEN_V__Y_COORD_MASK', + 'PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT', + 'PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK', + 'PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK', + 'PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK', + 'PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT', + 'PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK', + 'PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT', + 'PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK', + 'PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT', + 'PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT', + 'PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK', + 'PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT', + 'PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK', + 'PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT', + 'PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK', + 'PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT', + 'PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK', + 'PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT', + 'PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK', + 'PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT', + 'PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK', + 'PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT', + 'PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK', + 'PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT', + 'PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK', + 'PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT', + 'PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK', + 'PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT', + 'PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK', + 'PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT', + 'PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK', + 'PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT', + 'PA_STEREO_CNTL__EN_STEREO_MASK', + 'PA_STEREO_CNTL__EN_STEREO__SHIFT', + 'PA_STEREO_CNTL__RT_SLICE_MODE_MASK', + 'PA_STEREO_CNTL__RT_SLICE_MODE__SHIFT', + 'PA_STEREO_CNTL__RT_SLICE_OFFSET_MASK', + 'PA_STEREO_CNTL__RT_SLICE_OFFSET__SHIFT', + 'PA_STEREO_CNTL__STEREO_MODE_MASK', + 'PA_STEREO_CNTL__STEREO_MODE__SHIFT', + 'PA_STEREO_CNTL__VP_ID_MODE_MASK', + 'PA_STEREO_CNTL__VP_ID_MODE__SHIFT', + 'PA_STEREO_CNTL__VP_ID_OFFSET_MASK', + 'PA_STEREO_CNTL__VP_ID_OFFSET__SHIFT', + 'PA_SU_CNTL_STATUS__SU_BUSY_MASK', + 'PA_SU_CNTL_STATUS__SU_BUSY__SHIFT', + 'PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK', + 'PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT', + 'PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK', + 'PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT', + 'PA_SU_LINE_CNTL__WIDTH_MASK', 'PA_SU_LINE_CNTL__WIDTH__SHIFT', + 'PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK', + 'PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT', + 'PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK', + 'PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT', + 'PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK', + 'PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT', + 'PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK', + 'PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT', + 'PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK', + 'PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT', + 'PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK', + 'PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT', + 'PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK', + 'PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT', + 'PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK', + 'PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT', + 'PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK', + 'PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT', + 'PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK', + 'PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT', + 'PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK', + 'PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT', + 'PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'PA_SU_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'PA_SU_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'PA_SU_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'PA_SU_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'PA_SU_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'PA_SU_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'PA_SU_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'PA_SU_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'PA_SU_POINT_MINMAX__MAX_SIZE_MASK', + 'PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT', + 'PA_SU_POINT_MINMAX__MIN_SIZE_MASK', + 'PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT', + 'PA_SU_POINT_SIZE__HEIGHT_MASK', + 'PA_SU_POINT_SIZE__HEIGHT__SHIFT', 'PA_SU_POINT_SIZE__WIDTH_MASK', + 'PA_SU_POINT_SIZE__WIDTH__SHIFT', + 'PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK', + 'PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT', + 'PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK', + 'PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT', + 'PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK', + 'PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT', + 'PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK', + 'PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT', + 'PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK', + 'PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT', + 'PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK', + 'PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT', + 'PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK', + 'PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK', + 'PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK', + 'PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK', + 'PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK', + 'PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK', + 'PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK', + 'PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK', + 'PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK', + 'PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK', + 'PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK', + 'PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT', + 'PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK', + 'PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT', + 'PA_SU_SC_MODE_CNTL__CULL_BACK_MASK', + 'PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT', + 'PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK', + 'PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT', + 'PA_SU_SC_MODE_CNTL__FACE_MASK', + 'PA_SU_SC_MODE_CNTL__FACE__SHIFT', + 'PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK', + 'PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT', + 'PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK', + 'PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT', + 'PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK', + 'PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT', + 'PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK', + 'PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT', + 'PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK', + 'PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT', + 'PA_SU_SC_MODE_CNTL__POLY_MODE_MASK', + 'PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT', + 'PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK', + 'PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT', + 'PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK', + 'PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT', + 'PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK', + 'PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT', + 'PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK', + 'PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT', + 'PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK', + 'PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT', + 'PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK', + 'PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE_MASK', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE__SHIFT', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE_MASK', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE__SHIFT', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK', + 'PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT', + 'PA_SU_VTX_CNTL__PIX_CENTER_MASK', + 'PA_SU_VTX_CNTL__PIX_CENTER__SHIFT', + 'PA_SU_VTX_CNTL__QUANT_MODE_MASK', + 'PA_SU_VTX_CNTL__QUANT_MODE__SHIFT', + 'PA_SU_VTX_CNTL__ROUND_MODE_MASK', + 'PA_SU_VTX_CNTL__ROUND_MODE__SHIFT', + 'PA_UTCL1_CNTL1__CLIENTID_MASK', + 'PA_UTCL1_CNTL1__CLIENTID__SHIFT', + 'PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK', + 'PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT', + 'PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK', + 'PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT', + 'PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK', + 'PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT', + 'PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK', + 'PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT', + 'PA_UTCL1_CNTL1__FORCE_MISS_MASK', + 'PA_UTCL1_CNTL1__FORCE_MISS__SHIFT', + 'PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK', + 'PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT', + 'PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK', + 'PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT', + 'PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK', + 'PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT', + 'PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK', + 'PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT', + 'PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK', + 'PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT', + 'PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK', + 'PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT', + 'PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK', + 'PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT', + 'PA_UTCL1_CNTL1__REG_INV_VMID_MASK', + 'PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT', + 'PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK', + 'PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT', + 'PA_UTCL1_CNTL1__RESP_MODE_MASK', + 'PA_UTCL1_CNTL1__RESP_MODE__SHIFT', 'PA_UTCL1_CNTL1__SPARE_MASK', + 'PA_UTCL1_CNTL1__SPARE__SHIFT', + 'PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK', + 'PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT', + 'PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK', + 'PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT', + 'PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK', + 'PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT', + 'PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK', + 'PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT', + 'PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK', + 'PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT', + 'PA_UTCL1_CNTL2__FORCE_SNOOP_MASK', + 'PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT', + 'PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK', + 'PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT', + 'PA_UTCL1_CNTL2__LINE_VALID_MASK', + 'PA_UTCL1_CNTL2__LINE_VALID__SHIFT', + 'PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK', + 'PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT', + 'PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK', + 'PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT', + 'PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK', + 'PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT', + 'PA_UTCL1_CNTL2__RESERVED_MASK', + 'PA_UTCL1_CNTL2__RESERVED__SHIFT', 'PA_UTCL1_CNTL2__SPARE1_MASK', + 'PA_UTCL1_CNTL2__SPARE1__SHIFT', 'PA_UTCL1_CNTL2__SPARE2_MASK', + 'PA_UTCL1_CNTL2__SPARE2__SHIFT', 'PA_UTCL1_CNTL2__SPARE3_MASK', + 'PA_UTCL1_CNTL2__SPARE3__SHIFT', 'PA_UTCL1_CNTL2__SPARE4_MASK', + 'PA_UTCL1_CNTL2__SPARE4__SHIFT', 'PA_UTCL1_CNTL2__SPARE5_MASK', + 'PA_UTCL1_CNTL2__SPARE5__SHIFT', + 'RAS_BCI_SIGNATURE0__SIGNATURE_MASK', + 'RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT', + 'RAS_BCI_SIGNATURE1__SIGNATURE_MASK', + 'RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT', + 'RAS_CB_SIGNATURE0__SIGNATURE_MASK', + 'RAS_CB_SIGNATURE0__SIGNATURE__SHIFT', + 'RAS_DB_SIGNATURE0__SIGNATURE_MASK', + 'RAS_DB_SIGNATURE0__SIGNATURE__SHIFT', + 'RAS_IA_SIGNATURE0__SIGNATURE_MASK', + 'RAS_IA_SIGNATURE0__SIGNATURE__SHIFT', + 'RAS_IA_SIGNATURE1__SIGNATURE_MASK', + 'RAS_IA_SIGNATURE1__SIGNATURE__SHIFT', + 'RAS_PA_SIGNATURE0__SIGNATURE_MASK', + 'RAS_PA_SIGNATURE0__SIGNATURE__SHIFT', + 'RAS_SC_SIGNATURE0__SIGNATURE_MASK', + 'RAS_SC_SIGNATURE0__SIGNATURE__SHIFT', + 'RAS_SC_SIGNATURE1__SIGNATURE_MASK', + 'RAS_SC_SIGNATURE1__SIGNATURE__SHIFT', + 'RAS_SC_SIGNATURE2__SIGNATURE_MASK', + 'RAS_SC_SIGNATURE2__SIGNATURE__SHIFT', + 'RAS_SC_SIGNATURE3__SIGNATURE_MASK', + 'RAS_SC_SIGNATURE3__SIGNATURE__SHIFT', + 'RAS_SC_SIGNATURE4__SIGNATURE_MASK', + 'RAS_SC_SIGNATURE4__SIGNATURE__SHIFT', + 'RAS_SC_SIGNATURE5__SIGNATURE_MASK', + 'RAS_SC_SIGNATURE5__SIGNATURE__SHIFT', + 'RAS_SC_SIGNATURE6__SIGNATURE_MASK', + 'RAS_SC_SIGNATURE6__SIGNATURE__SHIFT', + 'RAS_SC_SIGNATURE7__SIGNATURE_MASK', + 'RAS_SC_SIGNATURE7__SIGNATURE__SHIFT', + 'RAS_SIGNATURE_CONTROL__ENABLE_MASK', + 'RAS_SIGNATURE_CONTROL__ENABLE__SHIFT', + 'RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK', + 'RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT', + 'RAS_SPI_SIGNATURE0__SIGNATURE_MASK', + 'RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT', + 'RAS_SPI_SIGNATURE1__SIGNATURE_MASK', + 'RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT', + 'RAS_SQ_SIGNATURE0__SIGNATURE_MASK', + 'RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT', + 'RAS_SX_SIGNATURE0__SIGNATURE_MASK', + 'RAS_SX_SIGNATURE0__SIGNATURE__SHIFT', + 'RAS_SX_SIGNATURE1__SIGNATURE_MASK', + 'RAS_SX_SIGNATURE1__SIGNATURE__SHIFT', + 'RAS_SX_SIGNATURE2__SIGNATURE_MASK', + 'RAS_SX_SIGNATURE2__SIGNATURE__SHIFT', + 'RAS_SX_SIGNATURE3__SIGNATURE_MASK', + 'RAS_SX_SIGNATURE3__SIGNATURE__SHIFT', + 'RAS_TA_SIGNATURE0__SIGNATURE_MASK', + 'RAS_TA_SIGNATURE0__SIGNATURE__SHIFT', + 'RAS_TA_SIGNATURE1__SIGNATURE_MASK', + 'RAS_TA_SIGNATURE1__SIGNATURE__SHIFT', + 'RAS_TD_SIGNATURE0__SIGNATURE_MASK', + 'RAS_TD_SIGNATURE0__SIGNATURE__SHIFT', + 'RAS_VGT_SIGNATURE0__SIGNATURE_MASK', + 'RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT', + 'RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK', + 'RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT', + 'RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK', + 'RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT', + 'RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK', + 'RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT', + 'RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK', + 'RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT', + 'RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK', + 'RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT', + 'RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE_MASK', + 'RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE__SHIFT', + 'RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED_MASK', + 'RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED__SHIFT', + 'RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE_MASK', + 'RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE__SHIFT', + 'RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED_MASK', + 'RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED__SHIFT', + 'RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK', + 'RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT', + 'RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK', + 'RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT', + 'RLC_CE_ERR_STATUS_HIGH__CE_CNT_MASK', + 'RLC_CE_ERR_STATUS_HIGH__CE_CNT__SHIFT', + 'RLC_CE_ERR_STATUS_HIGH__ECC_MASK', + 'RLC_CE_ERR_STATUS_HIGH__ECC__SHIFT', + 'RLC_CE_ERR_STATUS_HIGH__ERR_INFO_MASK', + 'RLC_CE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG_MASK', + 'RLC_CE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG__SHIFT', + 'RLC_CE_ERR_STATUS_HIGH__ERR_INFO__SHIFT', + 'RLC_CE_ERR_STATUS_HIGH__OTHER_MASK', + 'RLC_CE_ERR_STATUS_HIGH__OTHER__SHIFT', + 'RLC_CE_ERR_STATUS_HIGH__POISON_MASK', + 'RLC_CE_ERR_STATUS_HIGH__POISON__SHIFT', + 'RLC_CE_ERR_STATUS_HIGH__RESERVED_MASK', + 'RLC_CE_ERR_STATUS_HIGH__RESERVED__SHIFT', + 'RLC_CE_ERR_STATUS_LOW__ADDRESS_MASK', + 'RLC_CE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG_MASK', + 'RLC_CE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG__SHIFT', + 'RLC_CE_ERR_STATUS_LOW__ADDRESS__SHIFT', + 'RLC_CE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG_MASK', + 'RLC_CE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG__SHIFT', + 'RLC_CE_ERR_STATUS_LOW__MEMORY_ID_MASK', + 'RLC_CE_ERR_STATUS_LOW__MEMORY_ID__SHIFT', + 'RLC_CGCG_CGLS_CTRL_2__CANE_STAT_BUSY_MASK_MASK', + 'RLC_CGCG_CGLS_CTRL_2__CANE_STAT_BUSY_MASK__SHIFT', + 'RLC_CGCG_CGLS_CTRL_2__RESERVED_MASK', + 'RLC_CGCG_CGLS_CTRL_2__RESERVED__SHIFT', + 'RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK', + 'RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT', + 'RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK', + 'RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT', + 'RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK', + 'RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT', + 'RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK', + 'RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT', + 'RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK', + 'RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT', + 'RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK', + 'RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT', + 'RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK', + 'RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT', + 'RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK', + 'RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT', + 'RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK', + 'RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT', + 'RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK', + 'RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT', + 'RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK', + 'RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT', + 'RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK', + 'RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT', + 'RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK', + 'RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT', + 'RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK', + 'RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_PERF_CLK_EN_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_PERF_CLK_EN__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__RESERVED_0_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__RESERVED_0__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_11_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_11__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17__SHIFT', + 'RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK', + 'RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT', + 'RLC_CLK_CNTL__DBGBUS_CLK_ACTIVE_OVERRIDE_MASK', + 'RLC_CLK_CNTL__DBGBUS_CLK_ACTIVE_OVERRIDE__SHIFT', + 'RLC_CLK_CNTL__RESERVED_11_10_MASK', + 'RLC_CLK_CNTL__RESERVED_11_10__SHIFT', + 'RLC_CLK_CNTL__RESERVED_1_MASK', + 'RLC_CLK_CNTL__RESERVED_1__SHIFT', 'RLC_CLK_CNTL__RESERVED_MASK', + 'RLC_CLK_CNTL__RESERVED__SHIFT', + 'RLC_CLK_CNTL__RLC_CAC2_CLK_CNTL_MASK', + 'RLC_CLK_CNTL__RLC_CAC2_CLK_CNTL__SHIFT', + 'RLC_CLK_CNTL__RLC_CMN_CLK_CNTL_MASK', + 'RLC_CLK_CNTL__RLC_CMN_CLK_CNTL__SHIFT', + 'RLC_CLK_CNTL__RLC_DFLL_CLK_CNTL_MASK', + 'RLC_CLK_CNTL__RLC_DFLL_CLK_CNTL__SHIFT', + 'RLC_CLK_CNTL__RLC_EDC_OVERRIDE_MASK', + 'RLC_CLK_CNTL__RLC_EDC_OVERRIDE__SHIFT', + 'RLC_CLK_CNTL__RLC_GPM_CLK_CNTL_MASK', + 'RLC_CLK_CNTL__RLC_GPM_CLK_CNTL__SHIFT', + 'RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK', + 'RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT', + 'RLC_CLK_CNTL__RLC_SPP_CLK_CNTL_MASK', + 'RLC_CLK_CNTL__RLC_SPP_CLK_CNTL__SHIFT', + 'RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK', + 'RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE__SHIFT', + 'RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK', + 'RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT', + 'RLC_CLK_CNTL__RLC_TC_CLK_CNTL_MASK', + 'RLC_CLK_CNTL__RLC_TC_CLK_CNTL__SHIFT', + 'RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE_MASK', + 'RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE__SHIFT', + 'RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE_MASK', + 'RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE__SHIFT', + 'RLC_CLK_COUNT_CTRL__GFXCLK_RESET_MASK', + 'RLC_CLK_COUNT_CTRL__GFXCLK_RESET__SHIFT', + 'RLC_CLK_COUNT_CTRL__GFXCLK_RUN_MASK', + 'RLC_CLK_COUNT_CTRL__GFXCLK_RUN__SHIFT', + 'RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE_MASK', + 'RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE__SHIFT', + 'RLC_CLK_COUNT_CTRL__REFCLK_RESET_MASK', + 'RLC_CLK_COUNT_CTRL__REFCLK_RESET__SHIFT', + 'RLC_CLK_COUNT_CTRL__REFCLK_RUN_MASK', + 'RLC_CLK_COUNT_CTRL__REFCLK_RUN__SHIFT', + 'RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE_MASK', + 'RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE__SHIFT', + 'RLC_CLK_COUNT_GFXCLK_LSB__COUNTER_MASK', + 'RLC_CLK_COUNT_GFXCLK_LSB__COUNTER__SHIFT', + 'RLC_CLK_COUNT_GFXCLK_MSB__COUNTER_MASK', + 'RLC_CLK_COUNT_GFXCLK_MSB__COUNTER__SHIFT', + 'RLC_CLK_COUNT_REFCLK_LSB__COUNTER_MASK', + 'RLC_CLK_COUNT_REFCLK_LSB__COUNTER__SHIFT', + 'RLC_CLK_COUNT_REFCLK_MSB__COUNTER_MASK', + 'RLC_CLK_COUNT_REFCLK_MSB__COUNTER__SHIFT', + 'RLC_CLK_COUNT_STAT__GFXCLK_VALID_MASK', + 'RLC_CLK_COUNT_STAT__GFXCLK_VALID__SHIFT', + 'RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC_MASK', + 'RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC__SHIFT', + 'RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC_MASK', + 'RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC__SHIFT', + 'RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC_MASK', + 'RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC__SHIFT', + 'RLC_CLK_COUNT_STAT__REFCLK_VALID_MASK', + 'RLC_CLK_COUNT_STAT__REFCLK_VALID__SHIFT', + 'RLC_CLK_COUNT_STAT__RESERVED_MASK', + 'RLC_CLK_COUNT_STAT__RESERVED__SHIFT', + 'RLC_CNTL__FORCE_RETRY_MASK', 'RLC_CNTL__FORCE_RETRY__SHIFT', + 'RLC_CNTL__READ_CACHE_DISABLE_MASK', + 'RLC_CNTL__READ_CACHE_DISABLE__SHIFT', 'RLC_CNTL__RESERVED_MASK', + 'RLC_CNTL__RESERVED__SHIFT', 'RLC_CNTL__RLC_ENABLE_F32_MASK', + 'RLC_CNTL__RLC_ENABLE_F32__SHIFT', 'RLC_CNTL__RLC_STEP_F32_MASK', + 'RLC_CNTL__RLC_STEP_F32__SHIFT', + 'RLC_CPG_STAT_INVAL__CPG_stat_inval_MASK', + 'RLC_CPG_STAT_INVAL__CPG_stat_inval__SHIFT', + 'RLC_CP_EOF_INT_CNT__CNT_MASK', 'RLC_CP_EOF_INT_CNT__CNT__SHIFT', + 'RLC_CP_EOF_INT__INTERRUPT_MASK', + 'RLC_CP_EOF_INT__INTERRUPT__SHIFT', + 'RLC_CP_EOF_INT__RESERVED_MASK', + 'RLC_CP_EOF_INT__RESERVED__SHIFT', + 'RLC_CP_SCHEDULERS__scheduler0_MASK', + 'RLC_CP_SCHEDULERS__scheduler0__SHIFT', + 'RLC_CP_SCHEDULERS__scheduler1_MASK', + 'RLC_CP_SCHEDULERS__scheduler1__SHIFT', + 'RLC_CP_SCHEDULERS__scheduler2_MASK', + 'RLC_CP_SCHEDULERS__scheduler2__SHIFT', + 'RLC_CP_SCHEDULERS__scheduler3_MASK', + 'RLC_CP_SCHEDULERS__scheduler3__SHIFT', + 'RLC_CSIB_ADDR_HI__ADDRESS_MASK', + 'RLC_CSIB_ADDR_HI__ADDRESS__SHIFT', + 'RLC_CSIB_ADDR_LO__ADDRESS_MASK', + 'RLC_CSIB_ADDR_LO__ADDRESS__SHIFT', + 'RLC_CSIB_LENGTH__LENGTH_MASK', 'RLC_CSIB_LENGTH__LENGTH__SHIFT', + 'RLC_CU_STATUS__WORK_PENDING_MASK', + 'RLC_CU_STATUS__WORK_PENDING__SHIFT', + 'RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK', + 'RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK', + 'RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT', + 'RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK', + 'RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK', + 'RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT', + 'RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK', + 'RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK', + 'RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT', + 'RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK', + 'RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK', + 'RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT', + 'RLC_DSM_CNTL2__INJECT_DELAY_MASK', + 'RLC_DSM_CNTL2__INJECT_DELAY__SHIFT', + 'RLC_DSM_CNTL2__RLCG_INSTR_RAM_ENABLE_ERROR_INJECT_MASK', + 'RLC_DSM_CNTL2__RLCG_INSTR_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'RLC_DSM_CNTL2__RLCG_INSTR_RAM_SELECT_INJECT_DELAY_MASK', + 'RLC_DSM_CNTL2__RLCG_INSTR_RAM_SELECT_INJECT_DELAY__SHIFT', + 'RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK', + 'RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK', + 'RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT', + 'RLC_DSM_CNTL2__RLCV_INSTR_RAM_ENABLE_ERROR_INJECT_MASK', + 'RLC_DSM_CNTL2__RLCV_INSTR_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'RLC_DSM_CNTL2__RLCV_INSTR_RAM_SELECT_INJECT_DELAY_MASK', + 'RLC_DSM_CNTL2__RLCV_INSTR_RAM_SELECT_INJECT_DELAY__SHIFT', + 'RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK', + 'RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK', + 'RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT', + 'RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK', + 'RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK', + 'RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT', + 'RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_ENABLE_ERROR_INJECT_MASK', + 'RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_SELECT_INJECT_DELAY_MASK', + 'RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_SELECT_INJECT_DELAY__SHIFT', + 'RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_ENABLE_ERROR_INJECT_MASK', + 'RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_SELECT_INJECT_DELAY_MASK', + 'RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_SELECT_INJECT_DELAY__SHIFT', + 'RLC_DSM_CNTL2__RLC_TCTAG_RAM_ENABLE_ERROR_INJECT_MASK', + 'RLC_DSM_CNTL2__RLC_TCTAG_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'RLC_DSM_CNTL2__RLC_TCTAG_RAM_SELECT_INJECT_DELAY_MASK', + 'RLC_DSM_CNTL2__RLC_TCTAG_RAM_SELECT_INJECT_DELAY__SHIFT', + 'RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK', + 'RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT', + 'RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK', + 'RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT', + 'RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK', + 'RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT', + 'RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK', + 'RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT', + 'RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK', + 'RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT', + 'RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK', + 'RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT', + 'RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK', + 'RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT', + 'RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK', + 'RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT', + 'RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_DATA_SEL_MASK', + 'RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_DATA_SEL__SHIFT', + 'RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_SINGLE_WRITE_MASK', + 'RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT', + 'RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK', + 'RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT', + 'RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK', + 'RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT', + 'RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_DATA_SEL_MASK', + 'RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_DATA_SEL__SHIFT', + 'RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_SINGLE_WRITE_MASK', + 'RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT', + 'RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK', + 'RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT', + 'RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK', + 'RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT', + 'RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK', + 'RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT', + 'RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK', + 'RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT', + 'RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_DATA_SEL_MASK', + 'RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_DATA_SEL__SHIFT', + 'RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_SINGLE_WRITE_MASK', + 'RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT', + 'RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_DATA_SEL_MASK', + 'RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_DATA_SEL__SHIFT', + 'RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_SINGLE_WRITE_MASK', + 'RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_SINGLE_WRITE__SHIFT', + 'RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_DATA_SEL_MASK', + 'RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_DATA_SEL__SHIFT', + 'RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_SINGLE_WRITE_MASK', + 'RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_SINGLE_WRITE__SHIFT', + 'RLC_DSM_TRIG__START_MASK', 'RLC_DSM_TRIG__START__SHIFT', + 'RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK', + 'RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT', + 'RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK', + 'RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT', + 'RLC_DS_CNTL__GFX_CLK_EA_RLC_GRBM_STAT_BUSY_MASK_MASK', + 'RLC_DS_CNTL__GFX_CLK_EA_RLC_GRBM_STAT_BUSY_MASK__SHIFT', + 'RLC_DS_CNTL__GFX_CLK_TCC_RLC_GRBM_CC_RESIDENT_MASK_MASK', + 'RLC_DS_CNTL__GFX_CLK_TCC_RLC_GRBM_CC_RESIDENT_MASK__SHIFT', + 'RLC_DS_CNTL__RESRVED_1_MASK', 'RLC_DS_CNTL__RESRVED_1__SHIFT', + 'RLC_DS_CNTL__RESRVED_MASK', 'RLC_DS_CNTL__RESRVED__SHIFT', + 'RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK', + 'RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT', + 'RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK', + 'RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT', + 'RLC_DS_CNTL__SOC_CLK_EA_RLC_GRBM_STAT_BUSY_MASK_MASK', + 'RLC_DS_CNTL__SOC_CLK_EA_RLC_GRBM_STAT_BUSY_MASK__SHIFT', + 'RLC_DS_CNTL__SOC_CLK_TCC_RLC_GRBM_CC_RESIDENT_MASK_MASK', + 'RLC_DS_CNTL__SOC_CLK_TCC_RLC_GRBM_CC_RESIDENT_MASK__SHIFT', + 'RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK', + 'RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT', + 'RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK', + 'RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT', + 'RLC_FIREWALL_VIOLATION__ADDR_MASK', + 'RLC_FIREWALL_VIOLATION__ADDR__SHIFT', + 'RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR_MASK', + 'RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR__SHIFT', + 'RLC_FWL_FIRST_VIOL_ADDR__VIOL_APERTURE_ID_MASK', + 'RLC_FWL_FIRST_VIOL_ADDR__VIOL_APERTURE_ID__SHIFT', + 'RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP_MASK', + 'RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP__SHIFT', + 'RLC_FWL_FIRST_VIOL_ADDR__VIOL_STATUS_MASK', + 'RLC_FWL_FIRST_VIOL_ADDR__VIOL_STATUS__SHIFT', + 'RLC_GFX_RM_CNTL__RESERVED_MASK', + 'RLC_GFX_RM_CNTL__RESERVED__SHIFT', + 'RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK', + 'RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT', + 'RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK', + 'RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT', + 'RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK', + 'RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT', + 'RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK', + 'RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT', + 'RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK', + 'RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT', + 'RLC_GPM_GENERAL_0__DATA_MASK', 'RLC_GPM_GENERAL_0__DATA__SHIFT', + 'RLC_GPM_GENERAL_10__DATA_MASK', + 'RLC_GPM_GENERAL_10__DATA__SHIFT', + 'RLC_GPM_GENERAL_11__DATA_MASK', + 'RLC_GPM_GENERAL_11__DATA__SHIFT', + 'RLC_GPM_GENERAL_12__DATA_MASK', + 'RLC_GPM_GENERAL_12__DATA__SHIFT', + 'RLC_GPM_GENERAL_13__DATA_MASK', + 'RLC_GPM_GENERAL_13__DATA__SHIFT', + 'RLC_GPM_GENERAL_14__DATA_MASK', + 'RLC_GPM_GENERAL_14__DATA__SHIFT', + 'RLC_GPM_GENERAL_15__DATA_MASK', + 'RLC_GPM_GENERAL_15__DATA__SHIFT', 'RLC_GPM_GENERAL_1__DATA_MASK', + 'RLC_GPM_GENERAL_1__DATA__SHIFT', 'RLC_GPM_GENERAL_2__DATA_MASK', + 'RLC_GPM_GENERAL_2__DATA__SHIFT', 'RLC_GPM_GENERAL_3__DATA_MASK', + 'RLC_GPM_GENERAL_3__DATA__SHIFT', 'RLC_GPM_GENERAL_4__DATA_MASK', + 'RLC_GPM_GENERAL_4__DATA__SHIFT', 'RLC_GPM_GENERAL_5__DATA_MASK', + 'RLC_GPM_GENERAL_5__DATA__SHIFT', 'RLC_GPM_GENERAL_6__DATA_MASK', + 'RLC_GPM_GENERAL_6__DATA__SHIFT', 'RLC_GPM_GENERAL_7__DATA_MASK', + 'RLC_GPM_GENERAL_7__DATA__SHIFT', 'RLC_GPM_GENERAL_8__DATA_MASK', + 'RLC_GPM_GENERAL_8__DATA__SHIFT', 'RLC_GPM_GENERAL_9__DATA_MASK', + 'RLC_GPM_GENERAL_9__DATA__SHIFT', + 'RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK', + 'RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT', + 'RLC_GPM_INT_FORCE_TH0__FORCE_MASK', + 'RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT', + 'RLC_GPM_INT_FORCE_TH1__FORCE_MASK', + 'RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT', + 'RLC_GPM_INT_STAT_TH0__STATUS_MASK', + 'RLC_GPM_INT_STAT_TH0__STATUS__SHIFT', + 'RLC_GPM_LOG_CONT__CONT_MASK', 'RLC_GPM_LOG_CONT__CONT__SHIFT', + 'RLC_GPM_LOG_SIZE__SIZE_MASK', 'RLC_GPM_LOG_SIZE__SIZE__SHIFT', + 'RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK', + 'RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT', + 'RLC_GPM_PERF_COUNT_0__ENABLE_MASK', + 'RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT', + 'RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK', + 'RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT', + 'RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK', + 'RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT', + 'RLC_GPM_PERF_COUNT_0__RESERVED_MASK', + 'RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT', + 'RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK', + 'RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT', + 'RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK', + 'RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT', + 'RLC_GPM_PERF_COUNT_0__UNUSED_MASK', + 'RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT', + 'RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK', + 'RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT', + 'RLC_GPM_PERF_COUNT_1__ENABLE_MASK', + 'RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT', + 'RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK', + 'RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT', + 'RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK', + 'RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT', + 'RLC_GPM_PERF_COUNT_1__RESERVED_MASK', + 'RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT', + 'RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK', + 'RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT', + 'RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK', + 'RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT', + 'RLC_GPM_PERF_COUNT_1__UNUSED_MASK', + 'RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT', + 'RLC_GPM_SCRATCH_ADDR__ADDR_MASK', + 'RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT', + 'RLC_GPM_SCRATCH_ADDR__RESERVED_MASK', + 'RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT', + 'RLC_GPM_SCRATCH_DATA__DATA_MASK', + 'RLC_GPM_SCRATCH_DATA__DATA__SHIFT', + 'RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK', + 'RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT', + 'RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK', + 'RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT', + 'RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK', + 'RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT', + 'RLC_GPM_STAT__CMP_power_status_MASK', + 'RLC_GPM_STAT__CMP_power_status__SHIFT', + 'RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK', + 'RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT', + 'RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK', + 'RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT', + 'RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK', + 'RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT', + 'RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK', + 'RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT', + 'RLC_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK', + 'RLC_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT', + 'RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK', + 'RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT', + 'RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK', + 'RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT', + 'RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK', + 'RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT', + 'RLC_GPM_STAT__GFX_LS_STATUS_MASK', + 'RLC_GPM_STAT__GFX_LS_STATUS__SHIFT', + 'RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK', + 'RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT', + 'RLC_GPM_STAT__GFX_POWER_STATUS_MASK', + 'RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT', + 'RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK', + 'RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT', + 'RLC_GPM_STAT__PG_ERROR_STATUS_MASK', + 'RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT', + 'RLC_GPM_STAT__RESERVED_1_MASK', + 'RLC_GPM_STAT__RESERVED_1__SHIFT', + 'RLC_GPM_STAT__RESTORING_REGISTERS_MASK', + 'RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT', + 'RLC_GPM_STAT__RLC_BUSY_MASK', 'RLC_GPM_STAT__RLC_BUSY__SHIFT', + 'RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK', + 'RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT', + 'RLC_GPM_STAT__SAVING_REGISTERS_MASK', + 'RLC_GPM_STAT__SAVING_REGISTERS__SHIFT', + 'RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK', + 'RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT', + 'RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK', + 'RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT', + 'RLC_GPM_THREAD_ENABLE__RESERVED_MASK', + 'RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT', + 'RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK', + 'RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT', + 'RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK', + 'RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT', + 'RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK', + 'RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT', + 'RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK', + 'RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT', + 'RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK', + 'RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT', + 'RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK', + 'RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT', + 'RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK', + 'RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT', + 'RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK', + 'RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT', + 'RLC_GPM_THREAD_RESET__RESERVED_MASK', + 'RLC_GPM_THREAD_RESET__RESERVED__SHIFT', + 'RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK', + 'RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT', + 'RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK', + 'RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT', + 'RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK', + 'RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT', + 'RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK', + 'RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT', + 'RLC_GPM_TIMER_CTRL__RESERVED_MASK', + 'RLC_GPM_TIMER_CTRL__RESERVED__SHIFT', + 'RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK', + 'RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT', + 'RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK', + 'RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT', + 'RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK', + 'RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT', + 'RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK', + 'RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT', + 'RLC_GPM_TIMER_INT_0__TIMER_MASK', + 'RLC_GPM_TIMER_INT_0__TIMER__SHIFT', + 'RLC_GPM_TIMER_INT_1__TIMER_MASK', + 'RLC_GPM_TIMER_INT_1__TIMER__SHIFT', + 'RLC_GPM_TIMER_INT_2__TIMER_MASK', + 'RLC_GPM_TIMER_INT_2__TIMER__SHIFT', + 'RLC_GPM_TIMER_INT_3__TIMER_MASK', + 'RLC_GPM_TIMER_INT_3__TIMER__SHIFT', + 'RLC_GPM_TIMER_STAT__RESERVED_MASK', + 'RLC_GPM_TIMER_STAT__RESERVED__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC__SHIFT', + 'RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK', + 'RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT', + 'RLC_GPM_UCODE_ADDR__RESERVED_MASK', + 'RLC_GPM_UCODE_ADDR__RESERVED__SHIFT', + 'RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK', + 'RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT', + 'RLC_GPM_UCODE_DATA__UCODE_DATA_MASK', + 'RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT', + 'RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK', + 'RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT', + 'RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK', + 'RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT', + 'RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK', + 'RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT', + 'RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK', + 'RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT', + 'RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK', + 'RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT', + 'RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK', + 'RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT', + 'RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK', + 'RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT', + 'RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK', + 'RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT', + 'RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK', + 'RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT', + 'RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK', + 'RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT', + 'RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK', + 'RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT', + 'RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK', + 'RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT', + 'RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK', + 'RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT', + 'RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK', + 'RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT', + 'RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK', + 'RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT', + 'RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK', + 'RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT', + 'RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK', + 'RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT', + 'RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK', + 'RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT', + 'RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK', + 'RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT', + 'RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK', + 'RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT', + 'RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK', + 'RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT', + 'RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK', + 'RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT', + 'RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK', + 'RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT', + 'RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK', + 'RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT', + 'RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK', + 'RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT', + 'RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK', + 'RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT', + 'RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK', + 'RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT', + 'RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK', + 'RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT', + 'RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK', + 'RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT', + 'RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK', + 'RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT', + 'RLC_GPR_REG1__DATA_MASK', 'RLC_GPR_REG1__DATA__SHIFT', + 'RLC_GPR_REG2__DATA_MASK', 'RLC_GPR_REG2__DATA__SHIFT', + 'RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK', + 'RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT', + 'RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK', + 'RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT', + 'RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK', + 'RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT', + 'RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB_MASK', + 'RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB__SHIFT', + 'RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB_MASK', + 'RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB__SHIFT', + 'RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK', + 'RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT', + 'RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB_MASK', + 'RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB__SHIFT', + 'RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB_MASK', + 'RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB__SHIFT', + 'RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK', + 'RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT', + 'RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK', + 'RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT', + 'RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK', + 'RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT', + 'RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK', + 'RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT', + 'RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK', + 'RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT', + 'RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK', + 'RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT', + 'RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK', + 'RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT', + 'RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK', + 'RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT', + 'RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK', + 'RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT', + 'RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK', + 'RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT', + 'RLC_GPU_IOV_CFG_REG1__RESERVED_MASK', + 'RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT', + 'RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK', + 'RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT', + 'RLC_GPU_IOV_CFG_REG2__RESERVED_MASK', + 'RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT', + 'RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK', + 'RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT', + 'RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK', + 'RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT', + 'RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK', + 'RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT', + 'RLC_GPU_IOV_CFG_REG6__RESERVED_MASK', + 'RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT', + 'RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK', + 'RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT', + 'RLC_GPU_IOV_F32_CNTL__ENABLE_MASK', + 'RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT', + 'RLC_GPU_IOV_F32_CNTL__RESERVED_MASK', + 'RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT', + 'RLC_GPU_IOV_F32_RESET__RESERVED_MASK', + 'RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT', + 'RLC_GPU_IOV_F32_RESET__RESET_MASK', + 'RLC_GPU_IOV_F32_RESET__RESET__SHIFT', + 'RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK', + 'RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT', + 'RLC_GPU_IOV_INT_FORCE__FORCE_MASK', + 'RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT', + 'RLC_GPU_IOV_INT_STAT__STATUS_MASK', + 'RLC_GPU_IOV_INT_STAT__STATUS__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK', + 'RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK', + 'RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK', + 'RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK', + 'RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK', + 'RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK', + 'RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK', + 'RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK', + 'RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK', + 'RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK', + 'RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK', + 'RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT', + 'RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK', + 'RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT', + 'RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK', + 'RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT', + 'RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK', + 'RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT', + 'RLC_GPU_IOV_SCH_1__DATA_MASK', 'RLC_GPU_IOV_SCH_1__DATA__SHIFT', + 'RLC_GPU_IOV_SCH_2__DATA_MASK', 'RLC_GPU_IOV_SCH_2__DATA__SHIFT', + 'RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK', + 'RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT', + 'RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK', + 'RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT', + 'RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK', + 'RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT', + 'RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK', + 'RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT', + 'RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK', + 'RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT', + 'RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK', + 'RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT', + 'RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK', + 'RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT', + 'RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK', + 'RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT', + 'RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK', + 'RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK', + 'RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT', + 'RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK', + 'RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT', + 'RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK', + 'RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT', + 'RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK', + 'RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT', + 'RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK', + 'RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT', + 'RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK', + 'RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT', + 'RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK', + 'RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK', + 'RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT', + 'RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK', + 'RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT', + 'RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK', + 'RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT', + 'RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK', + 'RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT', + 'RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK', + 'RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT', + 'RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK', + 'RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT', + 'RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS_MASK', + 'RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA2_STATUS__PREEMPTED_MASK', + 'RLC_GPU_IOV_SDMA2_STATUS__PREEMPTED__SHIFT', + 'RLC_GPU_IOV_SDMA2_STATUS__RESERVED1_MASK', + 'RLC_GPU_IOV_SDMA2_STATUS__RESERVED1__SHIFT', + 'RLC_GPU_IOV_SDMA2_STATUS__RESERVED2_MASK', + 'RLC_GPU_IOV_SDMA2_STATUS__RESERVED2__SHIFT', + 'RLC_GPU_IOV_SDMA2_STATUS__RESERVED_MASK', + 'RLC_GPU_IOV_SDMA2_STATUS__RESERVED__SHIFT', + 'RLC_GPU_IOV_SDMA2_STATUS__RESTORED_MASK', + 'RLC_GPU_IOV_SDMA2_STATUS__RESTORED__SHIFT', + 'RLC_GPU_IOV_SDMA2_STATUS__SAVED_MASK', + 'RLC_GPU_IOV_SDMA2_STATUS__SAVED__SHIFT', + 'RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS_MASK', + 'RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA3_STATUS__PREEMPTED_MASK', + 'RLC_GPU_IOV_SDMA3_STATUS__PREEMPTED__SHIFT', + 'RLC_GPU_IOV_SDMA3_STATUS__RESERVED1_MASK', + 'RLC_GPU_IOV_SDMA3_STATUS__RESERVED1__SHIFT', + 'RLC_GPU_IOV_SDMA3_STATUS__RESERVED2_MASK', + 'RLC_GPU_IOV_SDMA3_STATUS__RESERVED2__SHIFT', + 'RLC_GPU_IOV_SDMA3_STATUS__RESERVED_MASK', + 'RLC_GPU_IOV_SDMA3_STATUS__RESERVED__SHIFT', + 'RLC_GPU_IOV_SDMA3_STATUS__RESTORED_MASK', + 'RLC_GPU_IOV_SDMA3_STATUS__RESTORED__SHIFT', + 'RLC_GPU_IOV_SDMA3_STATUS__SAVED_MASK', + 'RLC_GPU_IOV_SDMA3_STATUS__SAVED__SHIFT', + 'RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS_MASK', + 'RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA4_STATUS__PREEMPTED_MASK', + 'RLC_GPU_IOV_SDMA4_STATUS__PREEMPTED__SHIFT', + 'RLC_GPU_IOV_SDMA4_STATUS__RESERVED1_MASK', + 'RLC_GPU_IOV_SDMA4_STATUS__RESERVED1__SHIFT', + 'RLC_GPU_IOV_SDMA4_STATUS__RESERVED2_MASK', + 'RLC_GPU_IOV_SDMA4_STATUS__RESERVED2__SHIFT', + 'RLC_GPU_IOV_SDMA4_STATUS__RESERVED_MASK', + 'RLC_GPU_IOV_SDMA4_STATUS__RESERVED__SHIFT', + 'RLC_GPU_IOV_SDMA4_STATUS__RESTORED_MASK', + 'RLC_GPU_IOV_SDMA4_STATUS__RESTORED__SHIFT', + 'RLC_GPU_IOV_SDMA4_STATUS__SAVED_MASK', + 'RLC_GPU_IOV_SDMA4_STATUS__SAVED__SHIFT', + 'RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS_MASK', + 'RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA5_STATUS__PREEMPTED_MASK', + 'RLC_GPU_IOV_SDMA5_STATUS__PREEMPTED__SHIFT', + 'RLC_GPU_IOV_SDMA5_STATUS__RESERVED1_MASK', + 'RLC_GPU_IOV_SDMA5_STATUS__RESERVED1__SHIFT', + 'RLC_GPU_IOV_SDMA5_STATUS__RESERVED2_MASK', + 'RLC_GPU_IOV_SDMA5_STATUS__RESERVED2__SHIFT', + 'RLC_GPU_IOV_SDMA5_STATUS__RESERVED_MASK', + 'RLC_GPU_IOV_SDMA5_STATUS__RESERVED__SHIFT', + 'RLC_GPU_IOV_SDMA5_STATUS__RESTORED_MASK', + 'RLC_GPU_IOV_SDMA5_STATUS__RESTORED__SHIFT', + 'RLC_GPU_IOV_SDMA5_STATUS__SAVED_MASK', + 'RLC_GPU_IOV_SDMA5_STATUS__SAVED__SHIFT', + 'RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS_MASK', + 'RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA6_STATUS__PREEMPTED_MASK', + 'RLC_GPU_IOV_SDMA6_STATUS__PREEMPTED__SHIFT', + 'RLC_GPU_IOV_SDMA6_STATUS__RESERVED1_MASK', + 'RLC_GPU_IOV_SDMA6_STATUS__RESERVED1__SHIFT', + 'RLC_GPU_IOV_SDMA6_STATUS__RESERVED2_MASK', + 'RLC_GPU_IOV_SDMA6_STATUS__RESERVED2__SHIFT', + 'RLC_GPU_IOV_SDMA6_STATUS__RESERVED_MASK', + 'RLC_GPU_IOV_SDMA6_STATUS__RESERVED__SHIFT', + 'RLC_GPU_IOV_SDMA6_STATUS__RESTORED_MASK', + 'RLC_GPU_IOV_SDMA6_STATUS__RESTORED__SHIFT', + 'RLC_GPU_IOV_SDMA6_STATUS__SAVED_MASK', + 'RLC_GPU_IOV_SDMA6_STATUS__SAVED__SHIFT', + 'RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS_MASK', + 'RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS__SHIFT', + 'RLC_GPU_IOV_SDMA7_STATUS__PREEMPTED_MASK', + 'RLC_GPU_IOV_SDMA7_STATUS__PREEMPTED__SHIFT', + 'RLC_GPU_IOV_SDMA7_STATUS__RESERVED1_MASK', + 'RLC_GPU_IOV_SDMA7_STATUS__RESERVED1__SHIFT', + 'RLC_GPU_IOV_SDMA7_STATUS__RESERVED2_MASK', + 'RLC_GPU_IOV_SDMA7_STATUS__RESERVED2__SHIFT', + 'RLC_GPU_IOV_SDMA7_STATUS__RESERVED_MASK', + 'RLC_GPU_IOV_SDMA7_STATUS__RESERVED__SHIFT', + 'RLC_GPU_IOV_SDMA7_STATUS__RESTORED_MASK', + 'RLC_GPU_IOV_SDMA7_STATUS__RESTORED__SHIFT', + 'RLC_GPU_IOV_SDMA7_STATUS__SAVED_MASK', + 'RLC_GPU_IOV_SDMA7_STATUS__SAVED__SHIFT', + 'RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK', + 'RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT', + 'RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK', + 'RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT', + 'RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK', + 'RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT', + 'RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK', + 'RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED_MASK', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED__SHIFT', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED_MASK', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED__SHIFT', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED_MASK', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED__SHIFT', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK', + 'RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT', + 'RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK', + 'RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT', + 'RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK', + 'RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT', + 'RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK', + 'RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT', + 'RLC_GPU_IOV_VF_MASK__RESERVED_MASK', + 'RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT', + 'RLC_GPU_IOV_VF_MASK__VF_MASK_MASK', + 'RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT', + 'RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK', + 'RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT', + 'RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK', + 'RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT', + 'RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK', + 'RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT', + 'RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK', + 'RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT', + 'RLC_HYP_SEMAPHORE_0__CLIENT_ID_MASK', + 'RLC_HYP_SEMAPHORE_0__CLIENT_ID__SHIFT', + 'RLC_HYP_SEMAPHORE_0__RESERVED_MASK', + 'RLC_HYP_SEMAPHORE_0__RESERVED__SHIFT', + 'RLC_HYP_SEMAPHORE_1__CLIENT_ID_MASK', + 'RLC_HYP_SEMAPHORE_1__CLIENT_ID__SHIFT', + 'RLC_HYP_SEMAPHORE_1__RESERVED_MASK', + 'RLC_HYP_SEMAPHORE_1__RESERVED__SHIFT', + 'RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK', + 'RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT', + 'RLC_HYP_SEMAPHORE_2__RESERVED_MASK', + 'RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT', + 'RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK', + 'RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT', + 'RLC_HYP_SEMAPHORE_3__RESERVED_MASK', + 'RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT', + 'RLC_INT_STAT__CP_RLC_INT_PENDING_MASK', + 'RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT', + 'RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK', + 'RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT', + 'RLC_INT_STAT__RESERVED_MASK', 'RLC_INT_STAT__RESERVED__SHIFT', + 'RLC_JUMP_TABLE_RESTORE__ADDR_MASK', + 'RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT', + 'RLC_LBPW_CU_STAT__MAX_CU_MASK', + 'RLC_LBPW_CU_STAT__MAX_CU__SHIFT', 'RLC_LBPW_CU_STAT__ON_CU_MASK', + 'RLC_LBPW_CU_STAT__ON_CU__SHIFT', + 'RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK', + 'RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT', + 'RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK', + 'RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT', + 'RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK', + 'RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT', + 'RLC_LB_CNTL__LB_CNT_REG_INC_MASK', + 'RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT', + 'RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK', + 'RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT', + 'RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK', + 'RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT', + 'RLC_LB_CNTL__RESERVED_MASK', 'RLC_LB_CNTL__RESERVED__SHIFT', + 'RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK', + 'RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT', + 'RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK', + 'RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT', + 'RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK', + 'RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT', + 'RLC_LB_PARAMS__FIFO_SAMPLES_MASK', + 'RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT', + 'RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK', + 'RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT', + 'RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK', + 'RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT', + 'RLC_LB_PARAMS__SKIP_L2_CHECK_MASK', + 'RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT', + 'RLC_LB_THR_CONFIG_1__DATA_MASK', + 'RLC_LB_THR_CONFIG_1__DATA__SHIFT', + 'RLC_LB_THR_CONFIG_2__DATA_MASK', + 'RLC_LB_THR_CONFIG_2__DATA__SHIFT', + 'RLC_LB_THR_CONFIG_3__DATA_MASK', + 'RLC_LB_THR_CONFIG_3__DATA__SHIFT', + 'RLC_LB_THR_CONFIG_4__DATA_MASK', + 'RLC_LB_THR_CONFIG_4__DATA__SHIFT', + 'RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK', + 'RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT', + 'RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK', + 'RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT', + 'RLC_MAX_PG_CU__SPARE_MASK', 'RLC_MAX_PG_CU__SPARE__SHIFT', + 'RLC_MEM_SLP_CNTL__RESERVED1_MASK', + 'RLC_MEM_SLP_CNTL__RESERVED1__SHIFT', + 'RLC_MEM_SLP_CNTL__RESERVED_MASK', + 'RLC_MEM_SLP_CNTL__RESERVED__SHIFT', + 'RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK', + 'RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT', + 'RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK', + 'RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT', + 'RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK', + 'RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT', + 'RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK', + 'RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT', + 'RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK', + 'RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT', + 'RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK', + 'RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT', + 'RLC_MGCG_CTRL__MGCG_EN_MASK', 'RLC_MGCG_CTRL__MGCG_EN__SHIFT', + 'RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK', + 'RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT', + 'RLC_MGCG_CTRL__ON_DELAY_MASK', 'RLC_MGCG_CTRL__ON_DELAY__SHIFT', + 'RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK', + 'RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT', + 'RLC_MGCG_CTRL__SILICON_EN_MASK', + 'RLC_MGCG_CTRL__SILICON_EN__SHIFT', + 'RLC_MGCG_CTRL__SIMULATION_EN_MASK', + 'RLC_MGCG_CTRL__SIMULATION_EN__SHIFT', + 'RLC_MGCG_CTRL__SPARE_MASK', 'RLC_MGCG_CTRL__SPARE__SHIFT', + 'RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK', + 'RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT', + 'RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK', + 'RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT', + 'RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK', + 'RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT', + 'RLC_PERFMON_CNTL__PERFMON_STATE_MASK', + 'RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT', + 'RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK', + 'RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT', + 'RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK', + 'RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT', + 'RLC_PG_CNTL__CP_PG_DISABLE_MASK', + 'RLC_PG_CNTL__CP_PG_DISABLE__SHIFT', + 'RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK', + 'RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT', + 'RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK', + 'RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT', + 'RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK', + 'RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT', + 'RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK', + 'RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT', + 'RLC_PG_CNTL__PG_OVERRIDE_MASK', + 'RLC_PG_CNTL__PG_OVERRIDE__SHIFT', 'RLC_PG_CNTL__RESERVED1_MASK', + 'RLC_PG_CNTL__RESERVED1__SHIFT', 'RLC_PG_CNTL__RESERVED2_MASK', + 'RLC_PG_CNTL__RESERVED2__SHIFT', 'RLC_PG_CNTL__RESERVED_MASK', + 'RLC_PG_CNTL__RESERVED__SHIFT', + 'RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK', + 'RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT', + 'RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK', + 'RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT', + 'RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK', + 'RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE__SHIFT', + 'RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK', + 'RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT', + 'RLC_PG_CNTL__Ultra_Low_Voltage_Enable_MASK', + 'RLC_PG_CNTL__Ultra_Low_Voltage_Enable__SHIFT', + 'RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK', + 'RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT', + 'RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK', + 'RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT', + 'RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK', + 'RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT', + 'RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK', + 'RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT', + 'RLC_PG_DELAY_3__RESERVED_MASK', + 'RLC_PG_DELAY_3__RESERVED__SHIFT', + 'RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK', + 'RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT', + 'RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK', + 'RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT', + 'RLC_PG_DELAY__POWER_DOWN_DELAY_MASK', + 'RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT', + 'RLC_PG_DELAY__POWER_UP_DELAY_MASK', + 'RLC_PG_DELAY__POWER_UP_DELAY__SHIFT', + 'RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK', + 'RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT', + 'RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK', + 'RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT', + 'RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK', + 'RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT', + 'RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK', + 'RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT', + 'RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK', + 'RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT', + 'RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK', + 'RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT', + 'RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK', + 'RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT', + 'RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK', + 'RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT', + 'RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK', + 'RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT', + 'RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK', + 'RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT', + 'RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK', + 'RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT', + 'RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK', + 'RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT', + 'RLC_PREWALKER_UTCL1_TRIG__READY_MASK', + 'RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT', + 'RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK', + 'RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT', + 'RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK', + 'RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT', + 'RLC_PREWALKER_UTCL1_TRIG__VALID_MASK', + 'RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT', + 'RLC_PREWALKER_UTCL1_TRIG__VMID_MASK', + 'RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT', + 'RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK', + 'RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT', + 'RLC_R2I_CNTL_0__Data_MASK', 'RLC_R2I_CNTL_0__Data__SHIFT', + 'RLC_R2I_CNTL_1__Data_MASK', 'RLC_R2I_CNTL_1__Data__SHIFT', + 'RLC_R2I_CNTL_2__Data_MASK', 'RLC_R2I_CNTL_2__Data__SHIFT', + 'RLC_R2I_CNTL_3__Data_MASK', 'RLC_R2I_CNTL_3__Data__SHIFT', + 'RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK', + 'RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT', + 'RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK', + 'RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT', + 'RLC_RLCV_COMMAND__CMD_MASK', 'RLC_RLCV_COMMAND__CMD__SHIFT', + 'RLC_RLCV_COMMAND__RESERVED_MASK', + 'RLC_RLCV_COMMAND__RESERVED__SHIFT', + 'RLC_RLCV_SAFE_MODE__CMD_MASK', 'RLC_RLCV_SAFE_MODE__CMD__SHIFT', + 'RLC_RLCV_SAFE_MODE__MESSAGE_MASK', + 'RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT', + 'RLC_RLCV_SAFE_MODE__RESERVED1_MASK', + 'RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT', + 'RLC_RLCV_SAFE_MODE__RESERVED_MASK', + 'RLC_RLCV_SAFE_MODE__RESERVED__SHIFT', + 'RLC_RLCV_SAFE_MODE__RESPONSE_MASK', + 'RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT', + 'RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK', + 'RLC_RLCV_SPARE_INT_1__INTERRUPT__SHIFT', + 'RLC_RLCV_SPARE_INT_1__RESERVED_MASK', + 'RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT', + 'RLC_RLCV_SPARE_INT__INTERRUPT_MASK', + 'RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT', + 'RLC_RLCV_SPARE_INT__RESERVED_MASK', + 'RLC_RLCV_SPARE_INT__RESERVED__SHIFT', + 'RLC_RLCV_TIMER_CTRL__RESERVED_MASK', + 'RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT', + 'RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK', + 'RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT', + 'RLC_RLCV_TIMER_CTRL__TIMER_1_EN_MASK', + 'RLC_RLCV_TIMER_CTRL__TIMER_1_EN__SHIFT', + 'RLC_RLCV_TIMER_INT_0__TIMER_MASK', + 'RLC_RLCV_TIMER_INT_0__TIMER__SHIFT', + 'RLC_RLCV_TIMER_INT_1__TIMER_MASK', + 'RLC_RLCV_TIMER_INT_1__TIMER__SHIFT', + 'RLC_RLCV_TIMER_STAT__RESERVED_MASK', + 'RLC_RLCV_TIMER_STAT__RESERVED__SHIFT', + 'RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK', + 'RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT', + 'RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK', + 'RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT', + 'RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK', + 'RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT', + 'RLC_RLCV_TIMER_STAT__TIMER_1_STAT_MASK', + 'RLC_RLCV_TIMER_STAT__TIMER_1_STAT__SHIFT', + 'RLC_SAFE_MODE__CMD_MASK', 'RLC_SAFE_MODE__CMD__SHIFT', + 'RLC_SAFE_MODE__MESSAGE_MASK', 'RLC_SAFE_MODE__MESSAGE__SHIFT', + 'RLC_SAFE_MODE__RESERVED1_MASK', + 'RLC_SAFE_MODE__RESERVED1__SHIFT', 'RLC_SAFE_MODE__RESERVED_MASK', + 'RLC_SAFE_MODE__RESERVED__SHIFT', 'RLC_SAFE_MODE__RESPONSE_MASK', + 'RLC_SAFE_MODE__RESPONSE__SHIFT', + 'RLC_SEMAPHORE_0__CLIENT_ID_MASK', + 'RLC_SEMAPHORE_0__CLIENT_ID__SHIFT', + 'RLC_SEMAPHORE_0__RESERVED_MASK', + 'RLC_SEMAPHORE_0__RESERVED__SHIFT', + 'RLC_SEMAPHORE_1__CLIENT_ID_MASK', + 'RLC_SEMAPHORE_1__CLIENT_ID__SHIFT', + 'RLC_SEMAPHORE_1__RESERVED_MASK', + 'RLC_SEMAPHORE_1__RESERVED__SHIFT', + 'RLC_SEMAPHORE_2__CLIENT_ID_MASK', + 'RLC_SEMAPHORE_2__CLIENT_ID__SHIFT', + 'RLC_SEMAPHORE_2__RESERVED_MASK', + 'RLC_SEMAPHORE_2__RESERVED__SHIFT', + 'RLC_SEMAPHORE_3__CLIENT_ID_MASK', + 'RLC_SEMAPHORE_3__CLIENT_ID__SHIFT', + 'RLC_SEMAPHORE_3__RESERVED_MASK', + 'RLC_SEMAPHORE_3__RESERVED__SHIFT', + 'RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK', + 'RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT', + 'RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY_MASK', + 'RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY__SHIFT', + 'RLC_SERDES_RD_DATA_0__DATA_MASK', + 'RLC_SERDES_RD_DATA_0__DATA__SHIFT', + 'RLC_SERDES_RD_DATA_1__DATA_MASK', + 'RLC_SERDES_RD_DATA_1__DATA__SHIFT', + 'RLC_SERDES_RD_DATA_2__DATA_MASK', + 'RLC_SERDES_RD_DATA_2__DATA__SHIFT', + 'RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK', + 'RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT', + 'RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK', + 'RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT', + 'RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK', + 'RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT', + 'RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK', + 'RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT', + 'RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK', + 'RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT', + 'RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK', + 'RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT', + 'RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK', + 'RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT', + 'RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK', + 'RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT', + 'RLC_SERDES_RD_PENDING__RD_PENDING_MASK', + 'RLC_SERDES_RD_PENDING__RD_PENDING__SHIFT', + 'RLC_SERDES_WR_CTRL__BPM_ADDR_MASK', + 'RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT', + 'RLC_SERDES_WR_CTRL__BPM_DATA_MASK', + 'RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT', + 'RLC_SERDES_WR_CTRL__P1_SELECT_MASK', + 'RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT', + 'RLC_SERDES_WR_CTRL__P2_SELECT_MASK', + 'RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT', + 'RLC_SERDES_WR_CTRL__POWER_DOWN_MASK', + 'RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT', + 'RLC_SERDES_WR_CTRL__POWER_UP_MASK', + 'RLC_SERDES_WR_CTRL__POWER_UP__SHIFT', + 'RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK', + 'RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT', + 'RLC_SERDES_WR_CTRL__READ_COMMAND_MASK', + 'RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT', + 'RLC_SERDES_WR_CTRL__REG_ADDR_MASK', + 'RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT', + 'RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK', + 'RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT', + 'RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK', + 'RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT', + 'RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK', + 'RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT', + 'RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK', + 'RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT', + 'RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK', + 'RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT', + 'RLC_SERDES_WR_DATA__DATA_MASK', + 'RLC_SERDES_WR_DATA__DATA__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK_MASK', + 'RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK__SHIFT', + 'RLC_SMU_ARGUMENT_1__ARG_MASK', 'RLC_SMU_ARGUMENT_1__ARG__SHIFT', + 'RLC_SMU_ARGUMENT_2__ARG_MASK', 'RLC_SMU_ARGUMENT_2__ARG__SHIFT', + 'RLC_SMU_ARGUMENT_3__ARG_MASK', 'RLC_SMU_ARGUMENT_3__ARG__SHIFT', + 'RLC_SMU_ARGUMENT_4__ARG_MASK', 'RLC_SMU_ARGUMENT_4__ARG__SHIFT', + 'RLC_SMU_CLK_REQ__VALID_MASK', 'RLC_SMU_CLK_REQ__VALID__SHIFT', + 'RLC_SMU_COMMAND__CMD_MASK', 'RLC_SMU_COMMAND__CMD__SHIFT', + 'RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK', + 'RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT', + 'RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK', + 'RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT', + 'RLC_SMU_MESSAGE__CMD_MASK', 'RLC_SMU_MESSAGE__CMD__SHIFT', + 'RLC_SMU_SAFE_MODE__CMD_MASK', 'RLC_SMU_SAFE_MODE__CMD__SHIFT', + 'RLC_SMU_SAFE_MODE__MESSAGE_MASK', + 'RLC_SMU_SAFE_MODE__MESSAGE__SHIFT', + 'RLC_SMU_SAFE_MODE__RESERVED1_MASK', + 'RLC_SMU_SAFE_MODE__RESERVED1__SHIFT', + 'RLC_SMU_SAFE_MODE__RESERVED_MASK', + 'RLC_SMU_SAFE_MODE__RESERVED__SHIFT', + 'RLC_SMU_SAFE_MODE__RESPONSE_MASK', + 'RLC_SMU_SAFE_MODE__RESPONSE__SHIFT', + 'RLC_SPARE_INT_1__INTERRUPT_MASK', + 'RLC_SPARE_INT_1__INTERRUPT__SHIFT', + 'RLC_SPARE_INT_1__RESERVED_MASK', + 'RLC_SPARE_INT_1__RESERVED__SHIFT', + 'RLC_SPARE_INT__INTERRUPT_MASK', + 'RLC_SPARE_INT__INTERRUPT__SHIFT', 'RLC_SPARE_INT__RESERVED_MASK', + 'RLC_SPARE_INT__RESERVED__SHIFT', + 'RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK', + 'RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT', + 'RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK', + 'RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT', + 'RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK', + 'RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT', + 'RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK', + 'RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT', + 'RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK', + 'RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT', + 'RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK', + 'RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT', + 'RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK', + 'RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT', + 'RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK', + 'RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT', + 'RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK', + 'RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT', + 'RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK', + 'RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT', + 'RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK', + 'RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT', + 'RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK', + 'RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT', + 'RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK', + 'RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT', + 'RLC_SPM_GLOBAL_MUXSEL_ADDR__RESERVED_MASK', + 'RLC_SPM_GLOBAL_MUXSEL_ADDR__RESERVED__SHIFT', + 'RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK', + 'RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT', + 'RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK', + 'RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT', + 'RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK', + 'RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT', + 'RLC_SPM_INT_CNTL__RESERVED_MASK', + 'RLC_SPM_INT_CNTL__RESERVED__SHIFT', + 'RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK', + 'RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT', + 'RLC_SPM_INT_STATUS__RESERVED_MASK', + 'RLC_SPM_INT_STATUS__RESERVED__SHIFT', + 'RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK', + 'RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT', + 'RLC_SPM_MC_CNTL__RESERVED_MASK', + 'RLC_SPM_MC_CNTL__RESERVED__SHIFT', + 'RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK', + 'RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT', + 'RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK', + 'RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK', + 'RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT', + 'RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT', + 'RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK', + 'RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT', + 'RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK', + 'RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT', + 'RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK', + 'RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT', + 'RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK', + 'RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT', + 'RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK', + 'RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT', + 'RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK', + 'RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT', + 'RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK', + 'RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT', + 'RLC_SPM_PERFMON_CNTL__RESERVED1_MASK', + 'RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT', + 'RLC_SPM_PERFMON_CNTL__RESERVED_MASK', + 'RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT', + 'RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK', + 'RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT', + 'RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK', + 'RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT', + 'RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK', + 'RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT', + 'RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK', + 'RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT', + 'RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__PERFMON_MAX_SAMPLE_DELAY_MASK', + 'RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__PERFMON_MAX_SAMPLE_DELAY__SHIFT', + 'RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__RESERVED_MASK', + 'RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__RESERVED__SHIFT', + 'RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK', + 'RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT', + 'RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK', + 'RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT', + 'RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK', + 'RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT', + 'RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK', + 'RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT', + 'RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK', + 'RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT', + 'RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK', + 'RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT', + 'RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK', + 'RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT', + 'RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK', + 'RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT', + 'RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK', + 'RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT', + 'RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED_MASK', + 'RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT', + 'RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK', + 'RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT', + 'RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK', + 'RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT', + 'RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK', + 'RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT', + 'RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK', + 'RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT', + 'RLC_SPM_SE_MUXSEL_ADDR__RESERVED_MASK', + 'RLC_SPM_SE_MUXSEL_ADDR__RESERVED__SHIFT', + 'RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK', + 'RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT', + 'RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK', + 'RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT', + 'RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK', + 'RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT', + 'RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK', + 'RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT', + 'RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK', + 'RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT', + 'RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK', + 'RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT', + 'RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK', + 'RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT', + 'RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK', + 'RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT', + 'RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK', + 'RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT', + 'RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK', + 'RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT', + 'RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK', + 'RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT', + 'RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK', + 'RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT', + 'RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK', + 'RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT', + 'RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK', + 'RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT', + 'RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK', + 'RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT', + 'RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK', + 'RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT', + 'RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK', + 'RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT', + 'RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK', + 'RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT', + 'RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK', + 'RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT', + 'RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK', + 'RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT', + 'RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK', + 'RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT', + 'RLC_SPM_UTCL1_CNTL__RESERVED_MASK', + 'RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT', + 'RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK', + 'RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT', + 'RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK', + 'RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT', + 'RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK', + 'RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT', + 'RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK', + 'RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT', + 'RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK', + 'RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT', + 'RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK', + 'RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT', + 'RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK', + 'RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT', + 'RLC_SRM_ARAM_ADDR__ADDR_MASK', 'RLC_SRM_ARAM_ADDR__ADDR__SHIFT', + 'RLC_SRM_ARAM_ADDR__RESERVED_MASK', + 'RLC_SRM_ARAM_ADDR__RESERVED__SHIFT', + 'RLC_SRM_ARAM_DATA__DATA_MASK', 'RLC_SRM_ARAM_DATA__DATA__SHIFT', + 'RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK', + 'RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT', + 'RLC_SRM_CNTL__RESERVED_MASK', 'RLC_SRM_CNTL__RESERVED__SHIFT', + 'RLC_SRM_CNTL__SRM_ENABLE_MASK', + 'RLC_SRM_CNTL__SRM_ENABLE__SHIFT', 'RLC_SRM_DRAM_ADDR__ADDR_MASK', + 'RLC_SRM_DRAM_ADDR__ADDR__SHIFT', + 'RLC_SRM_DRAM_ADDR__RESERVED_MASK', + 'RLC_SRM_DRAM_ADDR__RESERVED__SHIFT', + 'RLC_SRM_DRAM_DATA__DATA_MASK', 'RLC_SRM_DRAM_DATA__DATA__SHIFT', + 'RLC_SRM_GPM_ABORT__ABORT_MASK', + 'RLC_SRM_GPM_ABORT__ABORT__SHIFT', + 'RLC_SRM_GPM_ABORT__RESERVED_MASK', + 'RLC_SRM_GPM_ABORT__RESERVED__SHIFT', + 'RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK', + 'RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT', + 'RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK', + 'RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT', + 'RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK', + 'RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT', + 'RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK', + 'RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT', + 'RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK', + 'RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK', + 'RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT', + 'RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT', + 'RLC_SRM_GPM_COMMAND__OP_MASK', 'RLC_SRM_GPM_COMMAND__OP__SHIFT', + 'RLC_SRM_GPM_COMMAND__RESERVED_16_MASK', + 'RLC_SRM_GPM_COMMAND__RESERVED_16__SHIFT', + 'RLC_SRM_GPM_COMMAND__RESERVED_30_29_MASK', + 'RLC_SRM_GPM_COMMAND__RESERVED_30_29__SHIFT', + 'RLC_SRM_GPM_COMMAND__SIZE_MASK', + 'RLC_SRM_GPM_COMMAND__SIZE__SHIFT', + 'RLC_SRM_GPM_COMMAND__START_OFFSET_MASK', + 'RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT', + 'RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK', + 'RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT', + 'RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK', + 'RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT', + 'RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK', + 'RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT', + 'RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK', + 'RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT', + 'RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK', + 'RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT', + 'RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK', + 'RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT', + 'RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK', + 'RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT', + 'RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK', + 'RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT', + 'RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK', + 'RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT', + 'RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK', + 'RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT', + 'RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK', + 'RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT', + 'RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK', + 'RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT', + 'RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK', + 'RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT', + 'RLC_SRM_RLCV_COMMAND__INDEX_CNTL_MASK', + 'RLC_SRM_RLCV_COMMAND__INDEX_CNTL_NUM_MASK', + 'RLC_SRM_RLCV_COMMAND__INDEX_CNTL_NUM__SHIFT', + 'RLC_SRM_RLCV_COMMAND__INDEX_CNTL__SHIFT', + 'RLC_SRM_RLCV_COMMAND__OP_MASK', + 'RLC_SRM_RLCV_COMMAND__OP__SHIFT', + 'RLC_SRM_RLCV_COMMAND__RESERVED1_MASK', + 'RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT', + 'RLC_SRM_RLCV_COMMAND__RESERVED_16_MASK', + 'RLC_SRM_RLCV_COMMAND__RESERVED_16__SHIFT', + 'RLC_SRM_RLCV_COMMAND__SIZE_MASK', + 'RLC_SRM_RLCV_COMMAND__SIZE__SHIFT', + 'RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK', + 'RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT', + 'RLC_SRM_STAT__RESERVED_MASK', 'RLC_SRM_STAT__RESERVED__SHIFT', + 'RLC_SRM_STAT__SRM_BUSY_DELAY_MASK', + 'RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT', + 'RLC_SRM_STAT__SRM_BUSY_MASK', 'RLC_SRM_STAT__SRM_BUSY__SHIFT', + 'RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK', + 'RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT', + 'RLC_STAT__MC_BUSY_MASK', 'RLC_STAT__MC_BUSY__SHIFT', + 'RLC_STAT__RESERVED_MASK', 'RLC_STAT__RESERVED__SHIFT', + 'RLC_STAT__RLC_BUSY_MASK', 'RLC_STAT__RLC_BUSY__SHIFT', + 'RLC_STAT__RLC_GPM_BUSY_MASK', 'RLC_STAT__RLC_GPM_BUSY__SHIFT', + 'RLC_STAT__RLC_SPM_BUSY_MASK', 'RLC_STAT__RLC_SPM_BUSY__SHIFT', + 'RLC_STAT__RLC_SRM_BUSY_MASK', 'RLC_STAT__RLC_SRM_BUSY__SHIFT', + 'RLC_STAT__RLC_THREAD_0_BUSY_MASK', + 'RLC_STAT__RLC_THREAD_0_BUSY__SHIFT', + 'RLC_STAT__RLC_THREAD_1_BUSY_MASK', + 'RLC_STAT__RLC_THREAD_1_BUSY__SHIFT', + 'RLC_STAT__RLC_THREAD_2_BUSY_MASK', + 'RLC_STAT__RLC_THREAD_2_BUSY__SHIFT', + 'RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK', + 'RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT', + 'RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK', + 'RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT', + 'RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK', + 'RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT', + 'RLC_THREAD1_DELAY__SPARE_MASK', + 'RLC_THREAD1_DELAY__SPARE__SHIFT', + 'RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK', + 'RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT', + 'RLC_UE_ERR_STATUS_HIGH__ECC_MASK', + 'RLC_UE_ERR_STATUS_HIGH__ECC__SHIFT', + 'RLC_UE_ERR_STATUS_HIGH__ERR_INFO_MASK', + 'RLC_UE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG_MASK', + 'RLC_UE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG__SHIFT', + 'RLC_UE_ERR_STATUS_HIGH__ERR_INFO__SHIFT', + 'RLC_UE_ERR_STATUS_HIGH__FED_CNT_MASK', + 'RLC_UE_ERR_STATUS_HIGH__FED_CNT__SHIFT', + 'RLC_UE_ERR_STATUS_HIGH__PARITY_MASK', + 'RLC_UE_ERR_STATUS_HIGH__PARITY__SHIFT', + 'RLC_UE_ERR_STATUS_HIGH__RESERVED_MASK', + 'RLC_UE_ERR_STATUS_HIGH__RESERVED__SHIFT', + 'RLC_UE_ERR_STATUS_HIGH__UE_CNT_MASK', + 'RLC_UE_ERR_STATUS_HIGH__UE_CNT__SHIFT', + 'RLC_UE_ERR_STATUS_LOW__ADDRESS_MASK', + 'RLC_UE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG_MASK', + 'RLC_UE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG__SHIFT', + 'RLC_UE_ERR_STATUS_LOW__ADDRESS__SHIFT', + 'RLC_UE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG_MASK', + 'RLC_UE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG__SHIFT', + 'RLC_UE_ERR_STATUS_LOW__MEMORY_ID_MASK', + 'RLC_UE_ERR_STATUS_LOW__MEMORY_ID__SHIFT', + 'RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK', + 'RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT', + 'RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK', + 'RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT', + 'RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK', + 'RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT', + 'RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK', + 'RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT', + 'RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK', + 'RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT', + 'RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK', + 'RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT', + 'RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK', + 'RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT', + 'RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK', + 'RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT', + 'RLC_UTCL1_STATUS_2__RESERVED_MASK', + 'RLC_UTCL1_STATUS_2__RESERVED__SHIFT', + 'RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK', + 'RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT', + 'RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK', + 'RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT', + 'RLC_UTCL1_STATUS__FAULT_DETECTED_MASK', + 'RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT', + 'RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK', + 'RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT', + 'RLC_UTCL1_STATUS__PRT_DETECTED_MASK', + 'RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT', + 'RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK', + 'RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT', + 'RLC_UTCL1_STATUS__RESERVED_1_MASK', + 'RLC_UTCL1_STATUS__RESERVED_1__SHIFT', + 'RLC_UTCL1_STATUS__RESERVED_2_MASK', + 'RLC_UTCL1_STATUS__RESERVED_2__SHIFT', + 'RLC_UTCL1_STATUS__RESERVED_3_MASK', + 'RLC_UTCL1_STATUS__RESERVED_3__SHIFT', + 'RLC_UTCL1_STATUS__RESERVED_MASK', + 'RLC_UTCL1_STATUS__RESERVED__SHIFT', + 'RLC_UTCL1_STATUS__RETRY_DETECTED_MASK', + 'RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT', + 'RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK', + 'RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT', + 'RLC_UTCL2_CNTL__IGNORE_PTE_PERMISSION_MASK', + 'RLC_UTCL2_CNTL__IGNORE_PTE_PERMISSION__SHIFT', + 'RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK', + 'RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT', + 'RLC_UTCL2_CNTL__RESERVED_MASK', + 'RLC_UTCL2_CNTL__RESERVED__SHIFT', + 'RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK', + 'RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK', + 'RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT', + 'RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK', + 'RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT', + 'RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK', + 'RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT', + 'RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK', + 'RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT', + 'RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK', + 'RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT', + 'RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK', + 'RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT', + 'RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK', + 'RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT', + 'RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK', + 'RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT', + 'RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK', + 'RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT', + 'RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK', + 'RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT', + 'RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK', + 'RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT', + 'RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK', + 'RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT', + 'RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK', + 'RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT', + 'RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK', + 'RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT', + 'RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK', + 'RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT', + 'RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK', + 'RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT', + 'RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK', + 'RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT', + 'RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK', + 'RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT', + 'RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK', + 'RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT', + 'RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK', + 'RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT', + 'RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK', + 'RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT', + 'RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK', + 'RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT', + 'RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK', + 'RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT', + 'RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK', + 'RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT', + 'RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK', + 'RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK', + 'RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT', + 'RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK', + 'RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT', + 'RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT', + 'RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK', + 'RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT', + 'RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK', + 'RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT', + 'RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK', + 'RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK', + 'RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT', + 'RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK', + 'RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT', + 'RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT', + 'RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK', + 'RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT', + 'RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK', + 'RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT', + 'RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK', + 'RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK', + 'RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT', + 'RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT', + 'RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK', + 'RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT', + 'RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK', + 'RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT', + 'RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK', + 'RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT', + 'RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK', + 'RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT', + 'RMI_GENERAL_CNTL__BURST_DISABLE_MASK', + 'RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT', + 'RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK', + 'RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT', + 'RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK', + 'RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT', + 'RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK', + 'RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT', + 'RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK', + 'RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT', + 'RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK', + 'RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT', + 'RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK', + 'RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT', + 'RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK', + 'RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT', + 'RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK', + 'RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT', + 'RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK', + 'RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT', + 'RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK', + 'RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK', + 'RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT', + 'RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT', + 'RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK', + 'RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT', + 'RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK', + 'RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK', + 'RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK', + 'RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK', + 'RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK', + 'RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK', + 'RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK', + 'RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT', + 'RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK', + 'RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT', + 'RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK', + 'RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT', + 'RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK', + 'RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT', + 'RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK', + 'RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT', + 'RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK', + 'RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK', + 'RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK', + 'RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK', + 'RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK', + 'RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK', + 'RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK', + 'RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK', + 'RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK', + 'RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK', + 'RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT', + 'RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK', + 'RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT', + 'RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK', + 'RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT', + 'RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK', + 'RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT', + 'RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK', + 'RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT', + 'RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK', + 'RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT', + 'RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK', + 'RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT', + 'RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK', + 'RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT', + 'RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK', + 'RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT', + 'RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK', + 'RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT', + 'RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK', + 'RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT', + 'RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK', + 'RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT', + 'RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK', + 'RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT', + 'RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK', + 'RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT', + 'RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK', + 'RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT', + 'RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK', + 'RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT', + 'RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK', + 'RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT', + 'RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK', + 'RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT', + 'RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK', + 'RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT', + 'RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK', + 'RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT', + 'RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK', + 'RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT', + 'RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK', + 'RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT', + 'RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK', + 'RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT', + 'RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK', + 'RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT', + 'RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK', + 'RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT', + 'RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK', + 'RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT', + 'RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK', + 'RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT', + 'RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK', + 'RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT', + 'RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK', + 'RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT', + 'RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK', + 'RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT', + 'RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK', + 'RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT', + 'RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK', + 'RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT', + 'RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK', + 'RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT', + 'RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK', + 'RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT', + 'RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK', + 'RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT', + 'RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK', + 'RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT', + 'RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK', + 'RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT', + 'RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK', + 'RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT', + 'RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK', + 'RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT', + 'RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK', + 'RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT', + 'RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK', + 'RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT', + 'RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK', + 'RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT', + 'RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK', + 'RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT', + 'RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK', + 'RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT', + 'RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK', + 'RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK', + 'RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT', + 'RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK', + 'RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT', + 'RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK', + 'RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT', + 'RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK', + 'RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT', + 'RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK', + 'RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT', + 'RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK', + 'RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT', + 'RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK', + 'RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT', + 'RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK', + 'RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT', + 'RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK', + 'RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT', + 'RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK', + 'RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT', + 'RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK', + 'RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT', + 'RMI_SPARE_1__SPARE_BIT_10_MASK', + 'RMI_SPARE_1__SPARE_BIT_10__SHIFT', + 'RMI_SPARE_1__SPARE_BIT_11_MASK', + 'RMI_SPARE_1__SPARE_BIT_11__SHIFT', + 'RMI_SPARE_1__SPARE_BIT_12_MASK', + 'RMI_SPARE_1__SPARE_BIT_12__SHIFT', + 'RMI_SPARE_1__SPARE_BIT_13_MASK', + 'RMI_SPARE_1__SPARE_BIT_13__SHIFT', + 'RMI_SPARE_1__SPARE_BIT_14_MASK', + 'RMI_SPARE_1__SPARE_BIT_14__SHIFT', + 'RMI_SPARE_1__SPARE_BIT_15_MASK', + 'RMI_SPARE_1__SPARE_BIT_15__SHIFT', + 'RMI_SPARE_1__SPARE_BIT_16_1_MASK', + 'RMI_SPARE_1__SPARE_BIT_16_1__SHIFT', + 'RMI_SPARE_1__SPARE_BIT_8_1_MASK', + 'RMI_SPARE_1__SPARE_BIT_8_1__SHIFT', + 'RMI_SPARE_1__SPARE_BIT_8_MASK', + 'RMI_SPARE_1__SPARE_BIT_8__SHIFT', + 'RMI_SPARE_1__SPARE_BIT_9_MASK', + 'RMI_SPARE_1__SPARE_BIT_9__SHIFT', + 'RMI_SPARE_2__SPARE_BIT_16_MASK', + 'RMI_SPARE_2__SPARE_BIT_16__SHIFT', + 'RMI_SPARE_2__SPARE_BIT_17_MASK', + 'RMI_SPARE_2__SPARE_BIT_17__SHIFT', + 'RMI_SPARE_2__SPARE_BIT_18_MASK', + 'RMI_SPARE_2__SPARE_BIT_18__SHIFT', + 'RMI_SPARE_2__SPARE_BIT_19_MASK', + 'RMI_SPARE_2__SPARE_BIT_19__SHIFT', + 'RMI_SPARE_2__SPARE_BIT_20_MASK', + 'RMI_SPARE_2__SPARE_BIT_20__SHIFT', + 'RMI_SPARE_2__SPARE_BIT_21_MASK', + 'RMI_SPARE_2__SPARE_BIT_21__SHIFT', + 'RMI_SPARE_2__SPARE_BIT_22_MASK', + 'RMI_SPARE_2__SPARE_BIT_22__SHIFT', + 'RMI_SPARE_2__SPARE_BIT_23_MASK', + 'RMI_SPARE_2__SPARE_BIT_23__SHIFT', + 'RMI_SPARE_2__SPARE_BIT_4_0_MASK', + 'RMI_SPARE_2__SPARE_BIT_4_0__SHIFT', + 'RMI_SPARE_2__SPARE_BIT_4_1_MASK', + 'RMI_SPARE_2__SPARE_BIT_4_1__SHIFT', + 'RMI_SPARE_2__SPARE_BIT_8_2_MASK', + 'RMI_SPARE_2__SPARE_BIT_8_2__SHIFT', + 'RMI_SPARE_2__SPARE_BIT_8_3_MASK', + 'RMI_SPARE_2__SPARE_BIT_8_3__SHIFT', + 'RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK', + 'RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT', + 'RMI_SPARE__SPARE_BIT_16_0_MASK', + 'RMI_SPARE__SPARE_BIT_16_0__SHIFT', 'RMI_SPARE__SPARE_BIT_1_MASK', + 'RMI_SPARE__SPARE_BIT_1__SHIFT', 'RMI_SPARE__SPARE_BIT_2_MASK', + 'RMI_SPARE__SPARE_BIT_2__SHIFT', 'RMI_SPARE__SPARE_BIT_3_MASK', + 'RMI_SPARE__SPARE_BIT_3__SHIFT', 'RMI_SPARE__SPARE_BIT_4_MASK', + 'RMI_SPARE__SPARE_BIT_4__SHIFT', 'RMI_SPARE__SPARE_BIT_5_MASK', + 'RMI_SPARE__SPARE_BIT_5__SHIFT', 'RMI_SPARE__SPARE_BIT_6_MASK', + 'RMI_SPARE__SPARE_BIT_6__SHIFT', 'RMI_SPARE__SPARE_BIT_7_MASK', + 'RMI_SPARE__SPARE_BIT_7__SHIFT', 'RMI_SPARE__SPARE_BIT_8_0_MASK', + 'RMI_SPARE__SPARE_BIT_8_0__SHIFT', + 'RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK', + 'RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK', + 'RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT', + 'RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK', + 'RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT', + 'RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK', + 'RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT', + 'RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK', + 'RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT', + 'RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK', + 'RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT', + 'RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK', + 'RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT', + 'RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK', + 'RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT', + 'RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK', + 'RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT', + 'RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK', + 'RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT', + 'RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK', + 'RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT', + 'RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK', + 'RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK', + 'RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT', + 'RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT', + 'RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK', + 'RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT', + 'RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK', + 'RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT', + 'RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK', + 'RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT', + 'RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK', + 'RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT', + 'RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK', + 'RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT', + 'RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK', + 'RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT', + 'RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK', + 'RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT', + 'RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK', + 'RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK', + 'RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT', + 'RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT', + 'RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK', + 'RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT', + 'RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK', + 'RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT', + 'RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK', + 'RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT', + 'RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK', + 'RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT', + 'RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK', + 'RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT', + 'RMI_UTCL1_CNTL1__CLIENTID_MASK', + 'RMI_UTCL1_CNTL1__CLIENTID__SHIFT', + 'RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK', + 'RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT', + 'RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK', + 'RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT', + 'RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK', + 'RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT', + 'RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK', + 'RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT', + 'RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK', + 'RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT', + 'RMI_UTCL1_CNTL1__FORCE_MISS_MASK', + 'RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT', + 'RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK', + 'RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT', + 'RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK', + 'RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT', + 'RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK', + 'RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT', + 'RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK', + 'RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT', + 'RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK', + 'RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT', + 'RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK', + 'RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT', + 'RMI_UTCL1_CNTL1__REG_INV_VMID_MASK', + 'RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT', + 'RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK', + 'RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT', + 'RMI_UTCL1_CNTL1__RESP_MODE_MASK', + 'RMI_UTCL1_CNTL1__RESP_MODE__SHIFT', + 'RMI_UTCL1_CNTL1__USERVM_DIS_MASK', + 'RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT', + 'RMI_UTCL1_CNTL2__DIS_EDC_MASK', + 'RMI_UTCL1_CNTL2__DIS_EDC__SHIFT', + 'RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK', + 'RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT', + 'RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK', + 'RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT', + 'RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK', + 'RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT', + 'RMI_UTCL1_CNTL2__LINE_VALID_MASK', + 'RMI_UTCL1_CNTL2__LINE_VALID__SHIFT', + 'RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK', + 'RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT', + 'RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK', + 'RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT', + 'RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK', + 'RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT', + 'RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK', + 'RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT', + 'RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK', + 'RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT', + 'RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK', + 'RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT', + 'RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK', + 'RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT', + 'RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK', + 'RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT', + 'RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK', + 'RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT', + 'RMI_UTCL1_CNTL2__UTC_SPARE_MASK', + 'RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT', + 'RMI_UTCL1_STATUS__FAULT_DETECTED_MASK', + 'RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT', + 'RMI_UTCL1_STATUS__PRT_DETECTED_MASK', + 'RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT', + 'RMI_UTCL1_STATUS__RETRY_DETECTED_MASK', + 'RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT', + 'RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN_MASK', + 'RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN__SHIFT', + 'RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK', + 'RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT', + 'RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK', + 'RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT', + 'RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK', + 'RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT', + 'RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK', + 'RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK', + 'RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK', + 'RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK', + 'RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK', + 'RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT', + 'RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT', + 'RMI_XBAR_CONFIG__ARBITER_DIS_MASK', + 'RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT', + 'RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK', + 'RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT', + 'RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK', + 'RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT', + 'RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK', + 'RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK', + 'RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT', + 'RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT', + 'RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK', + 'RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT', + 'RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK', + 'RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT', + 'RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK', + 'RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT', + 'RMI_XNACK_DEBUG__XNACK_PER_VMID_MASK', + 'RMI_XNACK_DEBUG__XNACK_PER_VMID__SHIFT', + 'SCRATCH_ADDR__OBSOLETE_ADDR_MASK', + 'SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT', + 'SCRATCH_REG0__SCRATCH_REG0_MASK', + 'SCRATCH_REG0__SCRATCH_REG0__SHIFT', + 'SCRATCH_REG1__SCRATCH_REG1_MASK', + 'SCRATCH_REG1__SCRATCH_REG1__SHIFT', + 'SCRATCH_REG2__SCRATCH_REG2_MASK', + 'SCRATCH_REG2__SCRATCH_REG2__SHIFT', + 'SCRATCH_REG3__SCRATCH_REG3_MASK', + 'SCRATCH_REG3__SCRATCH_REG3__SHIFT', + 'SCRATCH_REG4__SCRATCH_REG4_MASK', + 'SCRATCH_REG4__SCRATCH_REG4__SHIFT', + 'SCRATCH_REG5__SCRATCH_REG5_MASK', + 'SCRATCH_REG5__SCRATCH_REG5__SHIFT', + 'SCRATCH_REG6__SCRATCH_REG6_MASK', + 'SCRATCH_REG6__SCRATCH_REG6__SHIFT', + 'SCRATCH_REG7__SCRATCH_REG7_MASK', + 'SCRATCH_REG7__SCRATCH_REG7__SHIFT', + 'SCRATCH_UMSK__OBSOLETE_SWAP_MASK', + 'SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT', + 'SCRATCH_UMSK__OBSOLETE_UMSK_MASK', + 'SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT', + 'SH_CAC_CONFIG__SPI_SQ_CMD_REPEATER_FGCG_DISABLE_MASK', + 'SH_CAC_CONFIG__SPI_SQ_CMD_REPEATER_FGCG_DISABLE__SHIFT', + 'SH_CAC_CONFIG__SQC_DCACHE_CTRL_MGCG_DISABLE_MASK', + 'SH_CAC_CONFIG__SQC_DCACHE_CTRL_MGCG_DISABLE__SHIFT', + 'SH_CAC_CONFIG__SQC_DISABLE_RAM_CLOCK_GATING_MASK', + 'SH_CAC_CONFIG__SQC_DISABLE_RAM_CLOCK_GATING__SHIFT', + 'SH_CAC_CONFIG__SQC_DISABLE_UTCL1_FGCG_PADDR_MASK', + 'SH_CAC_CONFIG__SQC_DISABLE_UTCL1_FGCG_PADDR__SHIFT', + 'SH_CAC_CONFIG__SQC_ICACHE_CTRL_MGCG_DISABLE_MASK', + 'SH_CAC_CONFIG__SQC_ICACHE_CTRL_MGCG_DISABLE__SHIFT', + 'SH_CAC_CONFIG__SQC_MGCG_CLOCK_OFF_DELAY_CNT_MASK', + 'SH_CAC_CONFIG__SQC_MGCG_CLOCK_OFF_DELAY_CNT__SHIFT', + 'SH_CAC_CONFIG__SQC_MGCG_DISABLE_MASK', + 'SH_CAC_CONFIG__SQC_MGCG_DISABLE__SHIFT', + 'SH_CAC_CONFIG__SQC_SQ_REPEATER_FGCG_DISABLE_MASK', + 'SH_CAC_CONFIG__SQC_SQ_REPEATER_FGCG_DISABLE__SHIFT', + 'SH_CAC_CONFIG__SQC_TC_REPEATER_FGCG_DISABLE_MASK', + 'SH_CAC_CONFIG__SQC_TC_REPEATER_FGCG_DISABLE__SHIFT', + 'SH_CAC_CONFIG__SQC_TC_REQ_CLKEN_CHICKENBIT_MASK', + 'SH_CAC_CONFIG__SQC_TC_REQ_CLKEN_CHICKENBIT__SHIFT', + 'SH_CAC_CONFIG__SQC_UTCL1_REPEATER_FGCG_DISABLE_MASK', + 'SH_CAC_CONFIG__SQC_UTCL1_REPEATER_FGCG_DISABLE__SHIFT', + 'SH_CAC_CONFIG__SQG_DISABLE_RAM_CLOCK_GATING_MASK', + 'SH_CAC_CONFIG__SQG_DISABLE_RAM_CLOCK_GATING__SHIFT', + 'SH_CAC_CONFIG__SQG_TC_REPEATER_FGCG_DISABLE_MASK', + 'SH_CAC_CONFIG__SQG_TC_REPEATER_FGCG_DISABLE__SHIFT', + 'SH_CAC_CONFIG__SQG_UTCL1_REPEATER_FGCG_DISABLE_MASK', + 'SH_CAC_CONFIG__SQG_UTCL1_REPEATER_FGCG_DISABLE__SHIFT', + 'SH_CAC_CONFIG__SQ_MSG_REPEATER_FGCG_DISABLE_MASK', + 'SH_CAC_CONFIG__SQ_MSG_REPEATER_FGCG_DISABLE__SHIFT', + 'SH_MEM_BASES__PRIVATE_BASE_MASK', + 'SH_MEM_BASES__PRIVATE_BASE__SHIFT', + 'SH_MEM_BASES__SHARED_BASE_MASK', + 'SH_MEM_BASES__SHARED_BASE__SHIFT', + 'SH_MEM_CONFIG__ADDRESS_MODE_MASK', + 'SH_MEM_CONFIG__ADDRESS_MODE__SHIFT', + 'SH_MEM_CONFIG__ALIGNMENT_MODE_MASK', + 'SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT', + 'SH_MEM_CONFIG__F8_MODE_MASK', 'SH_MEM_CONFIG__F8_MODE__SHIFT', + 'SH_MEM_CONFIG__PRIVATE_NV_MASK', + 'SH_MEM_CONFIG__PRIVATE_NV__SHIFT', + 'SH_MEM_CONFIG__RETRY_DISABLE_MASK', + 'SH_MEM_CONFIG__RETRY_DISABLE__SHIFT', + 'SMU_RLC_RESPONSE__RESP_MASK', 'SMU_RLC_RESPONSE__RESP__SHIFT', + 'SP0_CE_ERR_STATUS_HI__CE_CNT_MASK', + 'SP0_CE_ERR_STATUS_HI__CE_CNT__SHIFT', + 'SP0_CE_ERR_STATUS_HI__ECC_MASK', + 'SP0_CE_ERR_STATUS_HI__ECC__SHIFT', + 'SP0_CE_ERR_STATUS_HI__ERR_INFO_MASK', + 'SP0_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'SP0_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'SP0_CE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'SP0_CE_ERR_STATUS_HI__OTHER_MASK', + 'SP0_CE_ERR_STATUS_HI__OTHER__SHIFT', + 'SP0_CE_ERR_STATUS_HI__POISON_MASK', + 'SP0_CE_ERR_STATUS_HI__POISON__SHIFT', + 'SP0_CE_ERR_STATUS_HI__RESERVED_MASK', + 'SP0_CE_ERR_STATUS_HI__RESERVED__SHIFT', + 'SP0_CE_ERR_STATUS_LO__ADDRESS_MASK', + 'SP0_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'SP0_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'SP0_CE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'SP0_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'SP0_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'SP0_CE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'SP0_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'SP0_UE_ERR_STATUS_HI__ECC_MASK', + 'SP0_UE_ERR_STATUS_HI__ECC__SHIFT', + 'SP0_UE_ERR_STATUS_HI__ERR_INFO_MASK', + 'SP0_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'SP0_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'SP0_UE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'SP0_UE_ERR_STATUS_HI__FED_CNT_MASK', + 'SP0_UE_ERR_STATUS_HI__FED_CNT__SHIFT', + 'SP0_UE_ERR_STATUS_HI__PARITY_MASK', + 'SP0_UE_ERR_STATUS_HI__PARITY__SHIFT', + 'SP0_UE_ERR_STATUS_HI__RESERVED_MASK', + 'SP0_UE_ERR_STATUS_HI__RESERVED__SHIFT', + 'SP0_UE_ERR_STATUS_HI__UE_CNT_MASK', + 'SP0_UE_ERR_STATUS_HI__UE_CNT__SHIFT', + 'SP0_UE_ERR_STATUS_LO__ADDRESS_MASK', + 'SP0_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'SP0_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'SP0_UE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'SP0_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'SP0_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'SP0_UE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'SP0_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'SP1_CE_ERR_STATUS_HI__CE_CNT_MASK', + 'SP1_CE_ERR_STATUS_HI__CE_CNT__SHIFT', + 'SP1_CE_ERR_STATUS_HI__ECC_MASK', + 'SP1_CE_ERR_STATUS_HI__ECC__SHIFT', + 'SP1_CE_ERR_STATUS_HI__ERR_INFO_MASK', + 'SP1_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'SP1_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'SP1_CE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'SP1_CE_ERR_STATUS_HI__OTHER_MASK', + 'SP1_CE_ERR_STATUS_HI__OTHER__SHIFT', + 'SP1_CE_ERR_STATUS_HI__POISON_MASK', + 'SP1_CE_ERR_STATUS_HI__POISON__SHIFT', + 'SP1_CE_ERR_STATUS_HI__RESERVED_MASK', + 'SP1_CE_ERR_STATUS_HI__RESERVED__SHIFT', + 'SP1_CE_ERR_STATUS_LO__ADDRESS_MASK', + 'SP1_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'SP1_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'SP1_CE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'SP1_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'SP1_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'SP1_CE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'SP1_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'SP1_UE_ERR_STATUS_HI__ECC_MASK', + 'SP1_UE_ERR_STATUS_HI__ECC__SHIFT', + 'SP1_UE_ERR_STATUS_HI__ERR_INFO_MASK', + 'SP1_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'SP1_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'SP1_UE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'SP1_UE_ERR_STATUS_HI__FED_CNT_MASK', + 'SP1_UE_ERR_STATUS_HI__FED_CNT__SHIFT', + 'SP1_UE_ERR_STATUS_HI__PARITY_MASK', + 'SP1_UE_ERR_STATUS_HI__PARITY__SHIFT', + 'SP1_UE_ERR_STATUS_HI__RESERVED_MASK', + 'SP1_UE_ERR_STATUS_HI__RESERVED__SHIFT', + 'SP1_UE_ERR_STATUS_HI__UE_CNT_MASK', + 'SP1_UE_ERR_STATUS_HI__UE_CNT__SHIFT', + 'SP1_UE_ERR_STATUS_LO__ADDRESS_MASK', + 'SP1_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'SP1_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'SP1_UE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'SP1_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'SP1_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'SP1_UE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'SP1_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'SPIS_DEBUG_READ__DATA_MASK', 'SPIS_DEBUG_READ__DATA__SHIFT', + 'SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK', + 'SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT', + 'SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK', + 'SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT', + 'SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK', + 'SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT', + 'SPI_ARB_CYCLES_0__TS0_DURATION_MASK', + 'SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT', + 'SPI_ARB_CYCLES_0__TS1_DURATION_MASK', + 'SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT', + 'SPI_ARB_CYCLES_1__TS2_DURATION_MASK', + 'SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT', + 'SPI_ARB_CYCLES_1__TS3_DURATION_MASK', + 'SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT', + 'SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK', + 'SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT', + 'SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK', + 'SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT', + 'SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK', + 'SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT', + 'SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK', + 'SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT', + 'SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK', + 'SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT', + 'SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK', + 'SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT', + 'SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK', + 'SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT', + 'SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK', + 'SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT', + 'SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK', + 'SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT', + 'SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK', + 'SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT', + 'SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK', + 'SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT', + 'SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK', + 'SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT', + 'SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK', + 'SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT', + 'SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK', + 'SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT', + 'SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK', + 'SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT', + 'SPI_CDBG_SYS_CS0__PIPE0_MASK', 'SPI_CDBG_SYS_CS0__PIPE0__SHIFT', + 'SPI_CDBG_SYS_CS0__PIPE1_MASK', 'SPI_CDBG_SYS_CS0__PIPE1__SHIFT', + 'SPI_CDBG_SYS_CS0__PIPE2_MASK', 'SPI_CDBG_SYS_CS0__PIPE2__SHIFT', + 'SPI_CDBG_SYS_CS0__PIPE3_MASK', 'SPI_CDBG_SYS_CS0__PIPE3__SHIFT', + 'SPI_CDBG_SYS_CS1__PIPE0_MASK', 'SPI_CDBG_SYS_CS1__PIPE0__SHIFT', + 'SPI_CDBG_SYS_CS1__PIPE1_MASK', 'SPI_CDBG_SYS_CS1__PIPE1__SHIFT', + 'SPI_CDBG_SYS_CS1__PIPE2_MASK', 'SPI_CDBG_SYS_CS1__PIPE2__SHIFT', + 'SPI_CDBG_SYS_CS1__PIPE3_MASK', 'SPI_CDBG_SYS_CS1__PIPE3__SHIFT', + 'SPI_CDBG_SYS_GFX__CS_EN_MASK', 'SPI_CDBG_SYS_GFX__CS_EN__SHIFT', + 'SPI_CDBG_SYS_GFX__ES_EN_MASK', 'SPI_CDBG_SYS_GFX__ES_EN__SHIFT', + 'SPI_CDBG_SYS_GFX__GS_EN_MASK', 'SPI_CDBG_SYS_GFX__GS_EN__SHIFT', + 'SPI_CDBG_SYS_GFX__HS_EN_MASK', 'SPI_CDBG_SYS_GFX__HS_EN__SHIFT', + 'SPI_CDBG_SYS_GFX__LS_EN_MASK', 'SPI_CDBG_SYS_GFX__LS_EN__SHIFT', + 'SPI_CDBG_SYS_GFX__PS_EN_MASK', 'SPI_CDBG_SYS_GFX__PS_EN__SHIFT', + 'SPI_CDBG_SYS_GFX__VS_EN_MASK', 'SPI_CDBG_SYS_GFX__VS_EN__SHIFT', + 'SPI_CDBG_SYS_HP3D__ES_EN_MASK', + 'SPI_CDBG_SYS_HP3D__ES_EN__SHIFT', + 'SPI_CDBG_SYS_HP3D__GS_EN_MASK', + 'SPI_CDBG_SYS_HP3D__GS_EN__SHIFT', + 'SPI_CDBG_SYS_HP3D__HS_EN_MASK', + 'SPI_CDBG_SYS_HP3D__HS_EN__SHIFT', + 'SPI_CDBG_SYS_HP3D__LS_EN_MASK', + 'SPI_CDBG_SYS_HP3D__LS_EN__SHIFT', + 'SPI_CDBG_SYS_HP3D__PS_EN_MASK', + 'SPI_CDBG_SYS_HP3D__PS_EN__SHIFT', + 'SPI_CDBG_SYS_HP3D__VS_EN_MASK', + 'SPI_CDBG_SYS_HP3D__VS_EN__SHIFT', + 'SPI_CE_ERR_STATUS_HI__CE_CNT_MASK', + 'SPI_CE_ERR_STATUS_HI__CE_CNT__SHIFT', + 'SPI_CE_ERR_STATUS_HI__ECC_MASK', + 'SPI_CE_ERR_STATUS_HI__ECC__SHIFT', + 'SPI_CE_ERR_STATUS_HI__ERR_INFO_MASK', + 'SPI_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'SPI_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'SPI_CE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'SPI_CE_ERR_STATUS_HI__OTHER_MASK', + 'SPI_CE_ERR_STATUS_HI__OTHER__SHIFT', + 'SPI_CE_ERR_STATUS_HI__POISON_MASK', + 'SPI_CE_ERR_STATUS_HI__POISON__SHIFT', + 'SPI_CE_ERR_STATUS_HI__RESERVED_MASK', + 'SPI_CE_ERR_STATUS_HI__RESERVED__SHIFT', + 'SPI_CE_ERR_STATUS_LO__ADDRESS_MASK', + 'SPI_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'SPI_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'SPI_CE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'SPI_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'SPI_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'SPI_CE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'SPI_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'SPI_COMPUTE_QUEUE_RESET__RESET_MASK', + 'SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT', + 'SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK', + 'SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT', + 'SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE_MASK', + 'SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE__SHIFT', + 'SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK', + 'SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT', + 'SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK', + 'SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT', + 'SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK', + 'SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT', + 'SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK', + 'SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT', + 'SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK', + 'SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT', + 'SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK', + 'SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT', + 'SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK', + 'SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT', + 'SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK', + 'SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT', + 'SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK', + 'SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT', + 'SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK', + 'SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT', + 'SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK', + 'SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT', + 'SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK', + 'SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT', + 'SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK', + 'SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT', + 'SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK', + 'SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT', + 'SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK', + 'SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT', + 'SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK', + 'SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT', + 'SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK', + 'SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT', + 'SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK', + 'SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT', + 'SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK', + 'SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT', + 'SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK', + 'SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT', + 'SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK', + 'SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT', + 'SPI_CONFIG_PS_CU_EN__ENABLE_MASK', + 'SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT', + 'SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK', + 'SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT', + 'SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK', + 'SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT', + 'SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK', + 'SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT', + 'SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK', + 'SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT', + 'SPI_DEBUG_BUSY__CS0_BUSY_MASK', + 'SPI_DEBUG_BUSY__CS0_BUSY__SHIFT', + 'SPI_DEBUG_BUSY__CS1_BUSY_MASK', + 'SPI_DEBUG_BUSY__CS1_BUSY__SHIFT', + 'SPI_DEBUG_BUSY__CS2_BUSY_MASK', + 'SPI_DEBUG_BUSY__CS2_BUSY__SHIFT', + 'SPI_DEBUG_BUSY__CS3_BUSY_MASK', + 'SPI_DEBUG_BUSY__CS3_BUSY__SHIFT', + 'SPI_DEBUG_BUSY__CS4_BUSY_MASK', + 'SPI_DEBUG_BUSY__CS4_BUSY__SHIFT', + 'SPI_DEBUG_BUSY__CS5_BUSY_MASK', + 'SPI_DEBUG_BUSY__CS5_BUSY__SHIFT', + 'SPI_DEBUG_BUSY__CS6_BUSY_MASK', + 'SPI_DEBUG_BUSY__CS6_BUSY__SHIFT', + 'SPI_DEBUG_BUSY__CS7_BUSY_MASK', + 'SPI_DEBUG_BUSY__CS7_BUSY__SHIFT', + 'SPI_DEBUG_BUSY__CSG_BUSY_MASK', + 'SPI_DEBUG_BUSY__CSG_BUSY__SHIFT', + 'SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK', + 'SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT', + 'SPI_DEBUG_BUSY__GRBM_BUSY_MASK', + 'SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT', + 'SPI_DEBUG_BUSY__GS_BUSY_MASK', 'SPI_DEBUG_BUSY__GS_BUSY__SHIFT', + 'SPI_DEBUG_BUSY__HS_BUSY_MASK', 'SPI_DEBUG_BUSY__HS_BUSY__SHIFT', + 'SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK', + 'SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT', + 'SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK', + 'SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT', + 'SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK', + 'SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT', + 'SPI_DEBUG_BUSY__PS0_BUSY_MASK', + 'SPI_DEBUG_BUSY__PS0_BUSY__SHIFT', + 'SPI_DEBUG_BUSY__PS1_BUSY_MASK', + 'SPI_DEBUG_BUSY__PS1_BUSY__SHIFT', + 'SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK', + 'SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT', + 'SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK', + 'SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT', + 'SPI_DEBUG_BUSY__SPIS_BUSY_MASK', + 'SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT', + 'SPI_DEBUG_BUSY__VS_BUSY_MASK', 'SPI_DEBUG_BUSY__VS_BUSY__SHIFT', + 'SPI_DEBUG_READ__DATA_MASK', 'SPI_DEBUG_READ__DATA__SHIFT', + 'SPI_DSM_CNTL2__RESERVED_MASK', 'SPI_DSM_CNTL2__RESERVED__SHIFT', + 'SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_ENABLE_ERROR_INJECT_MASK', + 'SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_ENABLE_ERROR_INJECT__SHIFT', + 'SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_SELECT_INJECT_DELAY_MASK', + 'SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_SELECT_INJECT_DELAY__SHIFT', + 'SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_ENABLE_ERROR_INJECT_MASK', + 'SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_ENABLE_ERROR_INJECT__SHIFT', + 'SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_SELECT_INJECT_DELAY_MASK', + 'SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_SELECT_INJECT_DELAY__SHIFT', + 'SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK', + 'SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT', + 'SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK', + 'SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT', + 'SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK', + 'SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT', + 'SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_ENABLE_ERROR_INJECT_MASK', + 'SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_ENABLE_ERROR_INJECT__SHIFT', + 'SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_SELECT_INJECT_DELAY_MASK', + 'SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_SELECT_INJECT_DELAY__SHIFT', + 'SPI_DSM_CNTL2__UNUSED_MASK', 'SPI_DSM_CNTL2__UNUSED__SHIFT', + 'SPI_DSM_CNTL__RESERVED_MASK', 'SPI_DSM_CNTL__RESERVED__SHIFT', + 'SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_DSM_IRRITATOR_DATA_MASK', + 'SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_DSM_IRRITATOR_DATA__SHIFT', + 'SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_ENABLE_SINGLE_WRITE_MASK', + 'SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_ENABLE_SINGLE_WRITE__SHIFT', + 'SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_DSM_IRRITATOR_DATA_MASK', + 'SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_DSM_IRRITATOR_DATA__SHIFT', + 'SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_ENABLE_SINGLE_WRITE_MASK', + 'SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_ENABLE_SINGLE_WRITE__SHIFT', + 'SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK', + 'SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT', + 'SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK', + 'SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT', + 'SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_DSM_IRRITATOR_DATA_MASK', + 'SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_DSM_IRRITATOR_DATA__SHIFT', + 'SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_ENABLE_SINGLE_WRITE_MASK', + 'SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_ENABLE_SINGLE_WRITE__SHIFT', + 'SPI_DSM_CNTL__UNUSED_MASK', 'SPI_DSM_CNTL__UNUSED__SHIFT', + 'SPI_EDC_CNT__RESERVED_MASK', 'SPI_EDC_CNT__RESERVED__SHIFT', + 'SPI_EDC_CNT__SPI_GDS_EXPREQ_DED_COUNT_MASK', + 'SPI_EDC_CNT__SPI_GDS_EXPREQ_DED_COUNT__SHIFT', + 'SPI_EDC_CNT__SPI_GDS_EXPREQ_SEC_COUNT_MASK', + 'SPI_EDC_CNT__SPI_GDS_EXPREQ_SEC_COUNT__SHIFT', + 'SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT_MASK', + 'SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT__SHIFT', + 'SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT_MASK', + 'SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT__SHIFT', + 'SPI_EDC_CNT__SPI_SR_MEM_DED_COUNT_MASK', + 'SPI_EDC_CNT__SPI_SR_MEM_DED_COUNT__SHIFT', + 'SPI_EDC_CNT__SPI_SR_MEM_SEC_COUNT_MASK', + 'SPI_EDC_CNT__SPI_SR_MEM_SEC_COUNT__SHIFT', + 'SPI_EDC_CNT__SPI_WB_GRANT_30_DED_COUNT_MASK', + 'SPI_EDC_CNT__SPI_WB_GRANT_30_DED_COUNT__SHIFT', + 'SPI_EDC_CNT__SPI_WB_GRANT_30_SEC_COUNT_MASK', + 'SPI_EDC_CNT__SPI_WB_GRANT_30_SEC_COUNT__SHIFT', + 'SPI_EDC_CNT__UNUSED_MASK', 'SPI_EDC_CNT__UNUSED__SHIFT', + 'SPI_GDBG_PER_VMID_CNTL__EXCP_EN_MASK', + 'SPI_GDBG_PER_VMID_CNTL__EXCP_EN__SHIFT', + 'SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE_MASK', + 'SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE__SHIFT', + 'SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE_MASK', + 'SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE__SHIFT', + 'SPI_GDBG_PER_VMID_CNTL__STALL_VMID_MASK', + 'SPI_GDBG_PER_VMID_CNTL__STALL_VMID__SHIFT', + 'SPI_GDBG_PER_VMID_CNTL__TRAP_EN_MASK', + 'SPI_GDBG_PER_VMID_CNTL__TRAP_EN__SHIFT', + 'SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END_MASK', + 'SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END__SHIFT', + 'SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START_MASK', + 'SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START__SHIFT', + 'SPI_GDBG_TRAP_CONFIG__PIPE0_EN_MASK', + 'SPI_GDBG_TRAP_CONFIG__PIPE0_EN__SHIFT', + 'SPI_GDBG_TRAP_CONFIG__PIPE1_EN_MASK', + 'SPI_GDBG_TRAP_CONFIG__PIPE1_EN__SHIFT', + 'SPI_GDBG_TRAP_CONFIG__PIPE2_EN_MASK', + 'SPI_GDBG_TRAP_CONFIG__PIPE2_EN__SHIFT', + 'SPI_GDBG_TRAP_CONFIG__PIPE3_EN_MASK', + 'SPI_GDBG_TRAP_CONFIG__PIPE3_EN__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT', + 'SPI_GDBG_WAVE_CNTL3__STALL_VS_MASK', + 'SPI_GDBG_WAVE_CNTL3__STALL_VS__SHIFT', + 'SPI_GDBG_WAVE_CNTL__STALL_RA_MASK', + 'SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT', + 'SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK', + 'SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT', + 'SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK', + 'SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT', + 'SPI_GDS_CREDITS__UNUSED_MASK', 'SPI_GDS_CREDITS__UNUSED__SHIFT', + 'SPI_GFX_CNTL__RESET_COUNTS_MASK', + 'SPI_GFX_CNTL__RESET_COUNTS__SHIFT', + 'SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK', + 'SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK', + 'SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT', + 'SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK', + 'SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT', + 'SPI_LB_CTR_CTRL__LOAD_MASK', 'SPI_LB_CTR_CTRL__LOAD__SHIFT', + 'SPI_LB_CTR_CTRL__RESET_COUNTS_MASK', + 'SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT', + 'SPI_LB_CTR_CTRL__WAVES_SELECT_MASK', + 'SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT', + 'SPI_LB_CU_MASK__CU_MASK_MASK', 'SPI_LB_CU_MASK__CU_MASK__SHIFT', + 'SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK', + 'SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT', + 'SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK', + 'SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT', + 'SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK', + 'SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT', + 'SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK', + 'SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT', + 'SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK', + 'SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT', + 'SPI_LB_DATA_REG__CNT_DATA_MASK', + 'SPI_LB_DATA_REG__CNT_DATA__SHIFT', + 'SPI_LB_DATA_WAVES__COUNT0_MASK', + 'SPI_LB_DATA_WAVES__COUNT0__SHIFT', + 'SPI_LB_DATA_WAVES__COUNT1_MASK', + 'SPI_LB_DATA_WAVES__COUNT1__SHIFT', + 'SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK', + 'SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT', + 'SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK', + 'SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT', + 'SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK', + 'SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT', + 'SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK', + 'SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT', + 'SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK', + 'SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT', + 'SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK', + 'SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT', + 'SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK', + 'SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT', + 'SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK', + 'SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT', + 'SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK', + 'SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT', + 'SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK', + 'SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT', + 'SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK', + 'SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT', + 'SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK', + 'SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT', + 'SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK', + 'SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT', + 'SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK', + 'SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT', + 'SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK', + 'SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT', + 'SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK', + 'SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT', + 'SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK', + 'SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT', + 'SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK', + 'SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT', + 'SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK', + 'SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT', + 'SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK', + 'SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT', + 'SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK', + 'SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT', + 'SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK', + 'SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT', + 'SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK', + 'SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT', + 'SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK', + 'SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT', + 'SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK', + 'SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT', + 'SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK', + 'SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT', + 'SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK', + 'SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT', + 'SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK', + 'SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT', + 'SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK', + 'SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT', + 'SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK', + 'SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT', + 'SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK', + 'SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT', + 'SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK', + 'SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT', + 'SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK', + 'SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT', + 'SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK', + 'SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT', + 'SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK', + 'SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT', + 'SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK', + 'SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT', + 'SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK', + 'SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT', + 'SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK', + 'SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT', + 'SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK', + 'SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT', + 'SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK', + 'SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK', + 'SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK', + 'SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK', + 'SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK', + 'SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK', + 'SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK', + 'SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK', + 'SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK', + 'SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK', + 'SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK', + 'SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK', + 'SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK', + 'SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK', + 'SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK', + 'SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT', + 'SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK', + 'SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT', + 'SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK', + 'SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT', + 'SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_0__DUP_MASK', + 'SPI_PS_INPUT_CNTL_0__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_0__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK', + 'SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT', + 'SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_10__DUP_MASK', + 'SPI_PS_INPUT_CNTL_10__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_10__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK', + 'SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT', + 'SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_11__DUP_MASK', + 'SPI_PS_INPUT_CNTL_11__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_11__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK', + 'SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT', + 'SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_12__DUP_MASK', + 'SPI_PS_INPUT_CNTL_12__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_12__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK', + 'SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT', + 'SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_13__DUP_MASK', + 'SPI_PS_INPUT_CNTL_13__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_13__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK', + 'SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT', + 'SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_14__DUP_MASK', + 'SPI_PS_INPUT_CNTL_14__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_14__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK', + 'SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT', + 'SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_15__DUP_MASK', + 'SPI_PS_INPUT_CNTL_15__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_15__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK', + 'SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT', + 'SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_16__DUP_MASK', + 'SPI_PS_INPUT_CNTL_16__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_16__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK', + 'SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT', + 'SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_17__DUP_MASK', + 'SPI_PS_INPUT_CNTL_17__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_17__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK', + 'SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT', + 'SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_18__DUP_MASK', + 'SPI_PS_INPUT_CNTL_18__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_18__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK', + 'SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT', + 'SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_19__DUP_MASK', + 'SPI_PS_INPUT_CNTL_19__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_19__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK', + 'SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT', + 'SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_1__DUP_MASK', + 'SPI_PS_INPUT_CNTL_1__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_1__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_20__DUP_MASK', + 'SPI_PS_INPUT_CNTL_20__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_20__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_21__DUP_MASK', + 'SPI_PS_INPUT_CNTL_21__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_21__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_22__DUP_MASK', + 'SPI_PS_INPUT_CNTL_22__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_22__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_23__DUP_MASK', + 'SPI_PS_INPUT_CNTL_23__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_23__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_24__DUP_MASK', + 'SPI_PS_INPUT_CNTL_24__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_24__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_25__DUP_MASK', + 'SPI_PS_INPUT_CNTL_25__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_25__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_26__DUP_MASK', + 'SPI_PS_INPUT_CNTL_26__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_26__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_27__DUP_MASK', + 'SPI_PS_INPUT_CNTL_27__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_27__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_28__DUP_MASK', + 'SPI_PS_INPUT_CNTL_28__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_28__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_29__DUP_MASK', + 'SPI_PS_INPUT_CNTL_29__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_29__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK', + 'SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT', + 'SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_2__DUP_MASK', + 'SPI_PS_INPUT_CNTL_2__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_2__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_30__DUP_MASK', + 'SPI_PS_INPUT_CNTL_30__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_30__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_31__DUP_MASK', + 'SPI_PS_INPUT_CNTL_31__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_31__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK', + 'SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT', + 'SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_3__DUP_MASK', + 'SPI_PS_INPUT_CNTL_3__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_3__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK', + 'SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT', + 'SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_4__DUP_MASK', + 'SPI_PS_INPUT_CNTL_4__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_4__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK', + 'SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT', + 'SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_5__DUP_MASK', + 'SPI_PS_INPUT_CNTL_5__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_5__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK', + 'SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT', + 'SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_6__DUP_MASK', + 'SPI_PS_INPUT_CNTL_6__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_6__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK', + 'SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT', + 'SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_7__DUP_MASK', + 'SPI_PS_INPUT_CNTL_7__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_7__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK', + 'SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT', + 'SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_8__DUP_MASK', + 'SPI_PS_INPUT_CNTL_8__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_8__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK', + 'SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK', + 'SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT', + 'SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK', + 'SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT', + 'SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK', + 'SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT', + 'SPI_PS_INPUT_CNTL_9__DUP_MASK', + 'SPI_PS_INPUT_CNTL_9__DUP__SHIFT', + 'SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK', + 'SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT', + 'SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK', + 'SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT', + 'SPI_PS_INPUT_CNTL_9__OFFSET_MASK', + 'SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT', + 'SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT', + 'SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK', + 'SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT', + 'SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK', + 'SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT', + 'SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK', + 'SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK', + 'SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK', + 'SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK', + 'SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK', + 'SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK', + 'SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK', + 'SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK', + 'SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK', + 'SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK', + 'SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK', + 'SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK', + 'SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK', + 'SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK', + 'SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK', + 'SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT', + 'SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK', + 'SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT', + 'SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK', + 'SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT', + 'SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK', + 'SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT', + 'SPI_PS_IN_CONTROL__NUM_INTERP_MASK', + 'SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT', + 'SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK', + 'SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT', + 'SPI_PS_IN_CONTROL__PARAM_GEN_MASK', + 'SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT', + 'SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK', + 'SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT', + 'SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK', + 'SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT', + 'SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK', + 'SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT', + 'SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK', + 'SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK', + 'SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT', + 'SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK', + 'SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT', + 'SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK', + 'SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT', + 'SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_0__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_10__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_11__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_12__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_13__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_14__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_15__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_1__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_2__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_3__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_4__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_5__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_6__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_7__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_8__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK', + 'SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_9__LDS_MASK', + 'SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK', + 'SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT', + 'SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK', + 'SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT', + 'SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK', + 'SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT', + 'SPI_SCRATCH_ADDR_CHECK__RESERVED_MASK', + 'SPI_SCRATCH_ADDR_CHECK__RESERVED__SHIFT', + 'SPI_SCRATCH_ADDR_STATUS__ME_ID_MASK', + 'SPI_SCRATCH_ADDR_STATUS__ME_ID__SHIFT', + 'SPI_SCRATCH_ADDR_STATUS__OVERFLOW_DETECTED_MASK', + 'SPI_SCRATCH_ADDR_STATUS__OVERFLOW_DETECTED__SHIFT', + 'SPI_SCRATCH_ADDR_STATUS__PIPE_ID_MASK', + 'SPI_SCRATCH_ADDR_STATUS__PIPE_ID__SHIFT', + 'SPI_SCRATCH_ADDR_STATUS__WRITE_DIS_MASK', + 'SPI_SCRATCH_ADDR_STATUS__WRITE_DIS__SHIFT', + 'SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK', + 'SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK', + 'SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK', + 'SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK', + 'SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK', + 'SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK', + 'SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK', + 'SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK', + 'SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK', + 'SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT', + 'SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK', + 'SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK', + 'SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK', + 'SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT', + 'SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK', + 'SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT', + 'SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK', + 'SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT', + 'SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK', + 'SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT', + 'SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK', + 'SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT', + 'SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK', + 'SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK', + 'SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK', + 'SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT', + 'SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK', + 'SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK', + 'SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT', + 'SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK', + 'SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT', + 'SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK', + 'SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT', + 'SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK', + 'SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT', + 'SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK', + 'SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT', + 'SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK', + 'SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT', + 'SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK', + 'SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK', + 'SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK', + 'SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK', + 'SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK', + 'SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK', + 'SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK', + 'SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK', + 'SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK', + 'SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0_MASK', + 'SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK', + 'SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK', + 'SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK', + 'SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT', + 'SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT', + 'SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK', + 'SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT', + 'SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0_MASK', + 'SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0__SHIFT', + 'SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK', + 'SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT', + 'SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK', + 'SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK', + 'SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT', + 'SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT', + 'SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK', + 'SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT', + 'SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK', + 'SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT', + 'SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK', + 'SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT', + 'SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0_MASK', + 'SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0__SHIFT', + 'SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK', + 'SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT', + 'SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK', + 'SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK', + 'SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT', + 'SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT', + 'SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0_MASK', + 'SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0__SHIFT', + 'SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK', + 'SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK', + 'SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT', + 'SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK', + 'SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK', + 'SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT', + 'SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT', + 'SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK', + 'SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK', + 'SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT', + 'SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE_MASK', + 'SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE__SHIFT', + 'SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK', + 'SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT', + 'SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK', + 'SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK', + 'SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT', + 'SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE_MASK', + 'SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT', + 'SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK', + 'SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT', + 'SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK', + 'SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK', + 'SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT', + 'SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE_MASK', + 'SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE__SHIFT', + 'SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK', + 'SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT', + 'SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK', + 'SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT', + 'SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK', + 'SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT', + 'SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE_MASK', + 'SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE__SHIFT', + 'SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK', + 'SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT', + 'SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH_MASK', + 'SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH__SHIFT', + 'SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK', + 'SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT', + 'SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH_MASK', + 'SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH__SHIFT', + 'SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK', + 'SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK', + 'SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK', + 'SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK', + 'SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT', + 'SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK', + 'SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT', + 'SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK', + 'SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT', + 'SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK', + 'SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT', + 'SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK', + 'SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_0__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_0__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_10__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_10__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_11__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_11__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_12__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_12__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_13__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_13__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_14__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_14__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_15__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_15__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_16__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_16__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_17__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_17__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_18__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_18__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_19__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_19__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_1__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_1__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_20__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_20__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_21__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_21__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_22__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_22__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_23__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_23__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_24__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_24__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_25__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_25__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_26__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_26__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_27__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_27__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_28__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_28__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_29__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_29__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_2__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_2__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_30__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_30__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_31__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_31__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_3__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_3__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_4__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_4__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_5__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_5__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_6__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_6__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_7__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_7__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_8__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_8__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_COMMON_9__DATA_MASK', + 'SPI_SHADER_USER_DATA_COMMON_9__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_0__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_10__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_11__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_12__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_13__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_14__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_15__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_16__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_16__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_17__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_17__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_18__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_18__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_19__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_19__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_1__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_20__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_20__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_21__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_21__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_22__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_22__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_23__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_23__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_24__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_24__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_25__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_25__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_26__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_26__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_27__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_27__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_28__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_28__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_29__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_29__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_2__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_30__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_30__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_31__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_31__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_3__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_4__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_5__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_6__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_7__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_8__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_ES_9__DATA_MASK', + 'SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_0__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_10__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_11__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_12__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_13__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_14__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_15__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_16__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_16__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_17__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_17__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_18__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_18__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_19__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_19__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_1__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_20__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_20__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_21__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_21__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_22__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_22__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_23__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_23__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_24__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_24__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_25__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_25__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_26__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_26__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_27__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_27__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_28__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_28__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_29__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_29__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_2__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_30__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_30__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_31__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_31__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_3__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_4__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_5__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_6__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_7__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_8__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_LS_9__DATA_MASK', + 'SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_0__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_10__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_11__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_12__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_13__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_14__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_15__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_16__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_17__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_18__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_19__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_1__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_20__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_21__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_22__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_23__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_24__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_25__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_26__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_27__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_28__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_29__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_2__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_30__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_31__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_3__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_4__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_5__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_6__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_7__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_8__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_PS_9__DATA_MASK', + 'SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_0__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_10__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_11__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_12__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_13__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_14__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_15__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_16__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_17__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_18__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_19__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_1__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_20__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_21__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_22__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_23__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_24__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_25__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_26__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_27__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_28__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_29__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_2__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_30__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_31__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_3__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_4__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_5__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_6__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_7__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_8__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT', + 'SPI_SHADER_USER_DATA_VS_9__DATA_MASK', + 'SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT', + 'SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK', + 'SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT', + 'SPI_START_PHASE__SGPR_START_PHASE_MASK', + 'SPI_START_PHASE__SGPR_START_PHASE__SHIFT', + 'SPI_START_PHASE__SPI_TD_GAP_MASK', + 'SPI_START_PHASE__SPI_TD_GAP__SHIFT', + 'SPI_START_PHASE__VGPR_START_PHASE_MASK', + 'SPI_START_PHASE__VGPR_START_PHASE__SHIFT', + 'SPI_START_PHASE__WAVE_START_PHASE_MASK', + 'SPI_START_PHASE__WAVE_START_PHASE__SHIFT', + 'SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK', + 'SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT', + 'SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK', + 'SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT', + 'SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK', + 'SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT', + 'SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK', + 'SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT', + 'SPI_TMPRING_SIZE__WAVESIZE_MASK', + 'SPI_TMPRING_SIZE__WAVESIZE__SHIFT', + 'SPI_TMPRING_SIZE__WAVES_MASK', 'SPI_TMPRING_SIZE__WAVES__SHIFT', + 'SPI_UE_ERR_STATUS_HI__ECC_MASK', + 'SPI_UE_ERR_STATUS_HI__ECC__SHIFT', + 'SPI_UE_ERR_STATUS_HI__ERR_INFO_MASK', + 'SPI_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'SPI_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'SPI_UE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'SPI_UE_ERR_STATUS_HI__FED_CNT_MASK', + 'SPI_UE_ERR_STATUS_HI__FED_CNT__SHIFT', + 'SPI_UE_ERR_STATUS_HI__PARITY_MASK', + 'SPI_UE_ERR_STATUS_HI__PARITY__SHIFT', + 'SPI_UE_ERR_STATUS_HI__RESERVED_MASK', + 'SPI_UE_ERR_STATUS_HI__RESERVED__SHIFT', + 'SPI_UE_ERR_STATUS_HI__UE_CNT_MASK', + 'SPI_UE_ERR_STATUS_HI__UE_CNT__SHIFT', + 'SPI_UE_ERR_STATUS_LO__ADDRESS_MASK', + 'SPI_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'SPI_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'SPI_UE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'SPI_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'SPI_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'SPI_UE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'SPI_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK', + 'SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT', + 'SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK', + 'SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT', + 'SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN_MASK', + 'SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN__SHIFT', + 'SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN_MASK', + 'SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN__SHIFT', + 'SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN_MASK', + 'SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN__SHIFT', + 'SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN_MASK', + 'SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN__SHIFT', + 'SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT', + 'SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK', + 'SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT', + 'SPI_WF_LIFETIME_CNTL__EN_MASK', + 'SPI_WF_LIFETIME_CNTL__EN__SHIFT', + 'SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK', + 'SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT', + 'SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK', + 'SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT', + 'SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK', + 'SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK', + 'SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK', + 'SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK', + 'SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK', + 'SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK', + 'SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK', + 'SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK', + 'SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK', + 'SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK', + 'SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK', + 'SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT', + 'SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK', + 'SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT', + 'SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK', + 'SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT', + 'SP_MFMA_PORTD_RD_CONFIG__LAST_PASS_MASK', + 'SP_MFMA_PORTD_RD_CONFIG__LAST_PASS__SHIFT', + 'SP_MFMA_PORTD_RD_CONFIG__PORTD_PATTERN_MASK', + 'SP_MFMA_PORTD_RD_CONFIG__PORTD_PATTERN__SHIFT', + 'SP_MFMA_PORTD_RD_CONFIG__SET_MASK', + 'SP_MFMA_PORTD_RD_CONFIG__SET__SHIFT', + 'SP_MFMA_PORTD_RD_CONFIG__TYPE_MASK', + 'SP_MFMA_PORTD_RD_CONFIG__TYPE__SHIFT', + 'SQC_CACHES__COMPLETE_MASK', 'SQC_CACHES__COMPLETE__SHIFT', + 'SQC_CACHES__INVALIDATE_MASK', 'SQC_CACHES__INVALIDATE__SHIFT', + 'SQC_CACHES__TARGET_DATA_MASK', 'SQC_CACHES__TARGET_DATA__SHIFT', + 'SQC_CACHES__TARGET_INST_MASK', 'SQC_CACHES__TARGET_INST__SHIFT', + 'SQC_CACHES__VOL_MASK', 'SQC_CACHES__VOL__SHIFT', + 'SQC_CACHES__WRITEBACK_MASK', 'SQC_CACHES__WRITEBACK__SHIFT', + 'SQC_CE_EDC_HI__CE_CNT_MASK', 'SQC_CE_EDC_HI__CE_CNT__SHIFT', + 'SQC_CE_EDC_HI__ECC_MASK', 'SQC_CE_EDC_HI__ECC__SHIFT', + 'SQC_CE_EDC_HI__ERR_INFO_MASK', + 'SQC_CE_EDC_HI__ERR_INFO_VALID_FLAG_MASK', + 'SQC_CE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'SQC_CE_EDC_HI__ERR_INFO__SHIFT', 'SQC_CE_EDC_HI__POSION_MASK', + 'SQC_CE_EDC_HI__POSION__SHIFT', + 'SQC_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK', + 'SQC_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT', + 'SQC_CE_EDC_LO__ADDRESS_MASK', 'SQC_CE_EDC_LO__ADDRESS__SHIFT', + 'SQC_CE_EDC_LO__MEM_ID_MASK', 'SQC_CE_EDC_LO__MEM_ID__SHIFT', + 'SQC_CE_EDC_LO__STATUS_VALID_FLAG_MASK', + 'SQC_CE_EDC_LO__STATUS_VALID_FLAG__SHIFT', + 'SQC_CONFIG__DATA_CACHE_SIZE_MASK', + 'SQC_CONFIG__DATA_CACHE_SIZE__SHIFT', + 'SQC_CONFIG__DISABLE_PREFETCH_CROSS_4K_BOUNDARY_CHECK_MASK', + 'SQC_CONFIG__DISABLE_PREFETCH_CROSS_4K_BOUNDARY_CHECK__SHIFT', + 'SQC_CONFIG__EVICT_LRU_MASK', 'SQC_CONFIG__EVICT_LRU__SHIFT', + 'SQC_CONFIG__FORCE_1_BANK_MASK', + 'SQC_CONFIG__FORCE_1_BANK__SHIFT', + 'SQC_CONFIG__FORCE_2_BANK_MASK', + 'SQC_CONFIG__FORCE_2_BANK__SHIFT', + 'SQC_CONFIG__FORCE_ALWAYS_MISS_MASK', + 'SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT', + 'SQC_CONFIG__FORCE_IN_ORDER_MASK', + 'SQC_CONFIG__FORCE_IN_ORDER__SHIFT', + 'SQC_CONFIG__HIT_FIFO_DEPTH_MASK', + 'SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT', + 'SQC_CONFIG__IDENTITY_HASH_BANK_MASK', + 'SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT', + 'SQC_CONFIG__IDENTITY_HASH_SET_MASK', + 'SQC_CONFIG__IDENTITY_HASH_SET__SHIFT', + 'SQC_CONFIG__INST_CACHE_SIZE_MASK', + 'SQC_CONFIG__INST_CACHE_SIZE__SHIFT', + 'SQC_CONFIG__INST_PRF_COUNT_MASK', + 'SQC_CONFIG__INST_PRF_COUNT__SHIFT', + 'SQC_CONFIG__INST_PRF_FILTER_DIS_MASK', + 'SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT', + 'SQC_CONFIG__LS_DISABLE_CLOCKS_MASK', + 'SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT', + 'SQC_CONFIG__MEM_LS_DISABLE_MASK', + 'SQC_CONFIG__MEM_LS_DISABLE__SHIFT', + 'SQC_CONFIG__MISS_FIFO_DEPTH_MASK', + 'SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT', + 'SQC_CONFIG__PER_VMID_INV_DISABLE_MASK', + 'SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK', + 'SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK', + 'SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK', + 'SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK', + 'SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK', + 'SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK', + 'SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK', + 'SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK', + 'SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK', + 'SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK', + 'SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK', + 'SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK', + 'SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK', + 'SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK', + 'SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL1__RESERVED_MASK', + 'SQC_DCACHE_UTCL1_CNTL1__RESERVED__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK', + 'SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK', + 'SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK', + 'SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK', + 'SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK', + 'SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK', + 'SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK', + 'SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK', + 'SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK', + 'SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK', + 'SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK', + 'SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK', + 'SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK', + 'SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK', + 'SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK', + 'SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL2__RESERVED_MASK', + 'SQC_DCACHE_UTCL1_CNTL2__RESERVED__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK', + 'SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT', + 'SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK', + 'SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT', + 'SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK', + 'SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT', + 'SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK', + 'SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT', + 'SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK', + 'SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT', + 'SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2__INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2__INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK', + 'SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT', + 'SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK', + 'SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT', + 'SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK', + 'SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT', + 'SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK', + 'SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT', + 'SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK', + 'SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT', + 'SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK', + 'SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT', + 'SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_DED_COUNT_MASK', + 'SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_DED_COUNT__SHIFT', + 'SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SEC_COUNT_MASK', + 'SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SEC_COUNT__SHIFT', + 'SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK', + 'SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT', + 'SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK', + 'SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT', + 'SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK', + 'SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT', + 'SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK', + 'SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT', + 'SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK', + 'SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT', + 'SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK', + 'SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT', + 'SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK', + 'SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT', + 'SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK', + 'SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT', + 'SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK', + 'SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT', + 'SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK', + 'SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT', + 'SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_DED_COUNT_MASK', + 'SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_DED_COUNT__SHIFT', + 'SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SEC_COUNT_MASK', + 'SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SEC_COUNT__SHIFT', + 'SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK', + 'SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT', + 'SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK', + 'SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT', + 'SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK', + 'SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT', + 'SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK', + 'SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT', + 'SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK', + 'SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT', + 'SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK', + 'SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT', + 'SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK', + 'SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT', + 'SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK', + 'SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT', + 'SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK', + 'SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT', + 'SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK', + 'SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT', + 'SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK', + 'SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT', + 'SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK', + 'SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT', + 'SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK', + 'SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT', + 'SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK', + 'SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT', + 'SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK', + 'SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT', + 'SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK', + 'SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT', + 'SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK', + 'SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT', + 'SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK', + 'SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT', + 'SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK', + 'SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT', + 'SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK', + 'SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT', + 'SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK', + 'SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT', + 'SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK', + 'SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT', + 'SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK', + 'SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT', + 'SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK', + 'SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT', + 'SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_DED_COUNT_MASK', + 'SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_DED_COUNT__SHIFT', + 'SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_SEC_COUNT_MASK', + 'SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_SEC_COUNT__SHIFT', + 'SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_DED_COUNT_MASK', + 'SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_DED_COUNT__SHIFT', + 'SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_SEC_COUNT_MASK', + 'SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_SEC_COUNT__SHIFT', + 'SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_DED_COUNT_MASK', + 'SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_DED_COUNT__SHIFT', + 'SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_SEC_COUNT_MASK', + 'SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_SEC_COUNT__SHIFT', + 'SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_DED_COUNT_MASK', + 'SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_DED_COUNT__SHIFT', + 'SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_SEC_COUNT_MASK', + 'SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_SEC_COUNT__SHIFT', + 'SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_DED_COUNT_MASK', + 'SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_DED_COUNT__SHIFT', + 'SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_SEC_COUNT_MASK', + 'SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_SEC_COUNT__SHIFT', + 'SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT_MASK', + 'SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT__SHIFT', + 'SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT_MASK', + 'SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT__SHIFT', + 'SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_DED_COUNT_MASK', + 'SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_DED_COUNT__SHIFT', + 'SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT_MASK', + 'SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT__SHIFT', + 'SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT_MASK', + 'SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT__SHIFT', + 'SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT_MASK', + 'SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK', + 'SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK', + 'SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK', + 'SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK', + 'SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK', + 'SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK', + 'SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK', + 'SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK', + 'SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK', + 'SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK', + 'SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK', + 'SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK', + 'SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK', + 'SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK', + 'SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL1__RESERVED_MASK', + 'SQC_ICACHE_UTCL1_CNTL1__RESERVED__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK', + 'SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK', + 'SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK', + 'SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK', + 'SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK', + 'SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK', + 'SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK', + 'SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK', + 'SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK', + 'SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK', + 'SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK', + 'SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK', + 'SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK', + 'SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK', + 'SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK', + 'SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL2__RESERVED_MASK', + 'SQC_ICACHE_UTCL1_CNTL2__RESERVED__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK', + 'SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT', + 'SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK', + 'SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT', + 'SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK', + 'SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT', + 'SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK', + 'SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT', + 'SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK', + 'SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT', + 'SQC_UE_EDC_HI__ECC_MASK', 'SQC_UE_EDC_HI__ECC__SHIFT', + 'SQC_UE_EDC_HI__ERR_INFO_MASK', + 'SQC_UE_EDC_HI__ERR_INFO_VALID_FLAG_MASK', + 'SQC_UE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'SQC_UE_EDC_HI__ERR_INFO__SHIFT', 'SQC_UE_EDC_HI__FED_CNT_MASK', + 'SQC_UE_EDC_HI__FED_CNT__SHIFT', 'SQC_UE_EDC_HI__PARITY_MASK', + 'SQC_UE_EDC_HI__PARITY__SHIFT', 'SQC_UE_EDC_HI__UE_CNT_MASK', + 'SQC_UE_EDC_HI__UE_CNT__SHIFT', + 'SQC_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK', + 'SQC_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT', + 'SQC_UE_EDC_LO__ADDRESS_MASK', 'SQC_UE_EDC_LO__ADDRESS__SHIFT', + 'SQC_UE_EDC_LO__MEM_ID_MASK', 'SQC_UE_EDC_LO__MEM_ID__SHIFT', + 'SQC_UE_EDC_LO__STATUS_VALID_FLAG_MASK', + 'SQC_UE_EDC_LO__STATUS_VALID_FLAG__SHIFT', + 'SQC_WRITEBACK__DIRTY_MASK', 'SQC_WRITEBACK__DIRTY__SHIFT', + 'SQC_WRITEBACK__DWB_MASK', 'SQC_WRITEBACK__DWB__SHIFT', + 'SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK', + 'SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT', + 'SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK', + 'SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT', + 'SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK', + 'SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT', + 'SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK', + 'SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT', + 'SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK', + 'SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT', + 'SQ_BUF_RSRC_WORD1__STRIDE_MASK', + 'SQ_BUF_RSRC_WORD1__STRIDE__SHIFT', + 'SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK', + 'SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT', + 'SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK', + 'SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT', + 'SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK', + 'SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT', + 'SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK', + 'SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT', + 'SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK', + 'SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT', + 'SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK', + 'SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT', + 'SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK', + 'SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT', + 'SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK', + 'SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT', + 'SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK', + 'SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT', + 'SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK', + 'SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT', + 'SQ_BUF_RSRC_WORD3__NV_MASK', 'SQ_BUF_RSRC_WORD3__NV__SHIFT', + 'SQ_BUF_RSRC_WORD3__TYPE_MASK', 'SQ_BUF_RSRC_WORD3__TYPE__SHIFT', + 'SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK', + 'SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT', + 'SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK', + 'SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT', + 'SQ_CE_ERR_STATUS_HI__CE_CNT_MASK', + 'SQ_CE_ERR_STATUS_HI__CE_CNT__SHIFT', + 'SQ_CE_ERR_STATUS_HI__ECC_MASK', + 'SQ_CE_ERR_STATUS_HI__ECC__SHIFT', + 'SQ_CE_ERR_STATUS_HI__ERR_INFO_MASK', + 'SQ_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'SQ_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'SQ_CE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'SQ_CE_ERR_STATUS_HI__OTHER_MASK', + 'SQ_CE_ERR_STATUS_HI__OTHER__SHIFT', + 'SQ_CE_ERR_STATUS_HI__POISON_MASK', + 'SQ_CE_ERR_STATUS_HI__POISON__SHIFT', + 'SQ_CE_ERR_STATUS_HI__RESERVED_MASK', + 'SQ_CE_ERR_STATUS_HI__RESERVED__SHIFT', + 'SQ_CE_ERR_STATUS_LO__ADDRESS_MASK', + 'SQ_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'SQ_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'SQ_CE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'SQ_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'SQ_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'SQ_CE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'SQ_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'SQ_CGTS_CONFIG__DGEMM_EXTRA_BUSY_PASS_MASK', + 'SQ_CGTS_CONFIG__DGEMM_EXTRA_BUSY_PASS__SHIFT', + 'SQ_CGTS_CONFIG__DGEMM_EXTRA_GAP_PASS_MASK', + 'SQ_CGTS_CONFIG__DGEMM_EXTRA_GAP_PASS__SHIFT', + 'SQ_CGTS_CONFIG__DLOP_EXTRA_BUSY_PASS_MASK', + 'SQ_CGTS_CONFIG__DLOP_EXTRA_BUSY_PASS__SHIFT', + 'SQ_CGTS_CONFIG__DLOP_EXTRA_GAP_PASS_MASK', + 'SQ_CGTS_CONFIG__DLOP_EXTRA_GAP_PASS__SHIFT', + 'SQ_CGTS_CONFIG__VALU_EXTRA_BUSY_PASS_MASK', + 'SQ_CGTS_CONFIG__VALU_EXTRA_BUSY_PASS__SHIFT', + 'SQ_CGTS_CONFIG__XDL_EXTRA_BUSY_PASS_MASK', + 'SQ_CGTS_CONFIG__XDL_EXTRA_BUSY_PASS__SHIFT', + 'SQ_CGTS_CONFIG__XDL_EXTRA_GAP_PASS_MASK', + 'SQ_CGTS_CONFIG__XDL_EXTRA_GAP_PASS__SHIFT', + 'SQ_CMD_TIMESTAMP__TIMESTAMP_MASK', + 'SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT', 'SQ_CMD__CHECK_VMID_MASK', + 'SQ_CMD__CHECK_VMID__SHIFT', 'SQ_CMD__CMD_MASK', + 'SQ_CMD__CMD__SHIFT', 'SQ_CMD__DATA_MASK', 'SQ_CMD__DATA__SHIFT', + 'SQ_CMD__MODE_MASK', 'SQ_CMD__MODE__SHIFT', + 'SQ_CMD__QUEUE_ID_MASK', 'SQ_CMD__QUEUE_ID__SHIFT', + 'SQ_CMD__SIMD_ID_MASK', 'SQ_CMD__SIMD_ID__SHIFT', + 'SQ_CMD__VM_ID_MASK', 'SQ_CMD__VM_ID__SHIFT', + 'SQ_CMD__WAVE_ID_MASK', 'SQ_CMD__WAVE_ID__SHIFT', + 'SQ_CONFIG1__DISABLE_BARRIER_ADDR_WATCH_MASK', + 'SQ_CONFIG1__DISABLE_BARRIER_ADDR_WATCH__SHIFT', + 'SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_BACKOFF_MASK', + 'SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_BACKOFF__SHIFT', + 'SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_WAIT_MASK', + 'SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_WAIT__SHIFT', + 'SQ_CONFIG1__DISABLE_MGCG_ON_EXP_MASK', + 'SQ_CONFIG1__DISABLE_MGCG_ON_EXP__SHIFT', + 'SQ_CONFIG1__DISABLE_MGCG_ON_IBUF_MASK', + 'SQ_CONFIG1__DISABLE_MGCG_ON_IBUF__SHIFT', + 'SQ_CONFIG1__DISABLE_MGCG_ON_PERF_MASK', + 'SQ_CONFIG1__DISABLE_MGCG_ON_PERF_SNAP_MASK', + 'SQ_CONFIG1__DISABLE_MGCG_ON_PERF_SNAP__SHIFT', + 'SQ_CONFIG1__DISABLE_MGCG_ON_PERF__SHIFT', + 'SQ_CONFIG1__DISABLE_MGCG_ON_SCA_MASK', + 'SQ_CONFIG1__DISABLE_MGCG_ON_SCA__SHIFT', + 'SQ_CONFIG1__DISABLE_MGCG_ON_SREG_MASK', + 'SQ_CONFIG1__DISABLE_MGCG_ON_SREG__SHIFT', + 'SQ_CONFIG1__DISABLE_MGCG_ON_VDEC_MASK', + 'SQ_CONFIG1__DISABLE_MGCG_ON_VDEC__SHIFT', + 'SQ_CONFIG1__DISABLE_SP_VGPR_COLLAPSE_MASK', + 'SQ_CONFIG1__DISABLE_SP_VGPR_COLLAPSE__SHIFT', + 'SQ_CONFIG1__DISABLE_SP_VGPR_READ_SKIP_MASK', + 'SQ_CONFIG1__DISABLE_SP_VGPR_READ_SKIP__SHIFT', + 'SQ_CONFIG1__DISABLE_VALU_COEXEC_MASK', + 'SQ_CONFIG1__DISABLE_VALU_COEXEC_MODE_AUTO_CLEAN_MASK', + 'SQ_CONFIG1__DISABLE_VALU_COEXEC_MODE_AUTO_CLEAN__SHIFT', + 'SQ_CONFIG1__DISABLE_VALU_COEXEC__SHIFT', + 'SQ_CONFIG1__DISABLE_VGPR_COLLAPSE_MASK', + 'SQ_CONFIG1__DISABLE_VGPR_COLLAPSE__SHIFT', + 'SQ_CONFIG1__DISABLE_WAVE_VALU_COEXEC_MASK', + 'SQ_CONFIG1__DISABLE_WAVE_VALU_COEXEC__SHIFT', + 'SQ_CONFIG1__DISABLE_XDL_PORTD_CO_EXEC_MASK', + 'SQ_CONFIG1__DISABLE_XDL_PORTD_CO_EXEC__SHIFT', + 'SQ_CONFIG1__DISABLE_XNACK_CHECK_IN_RETRY_DISABLE_MASK', + 'SQ_CONFIG1__DISABLE_XNACK_CHECK_IN_RETRY_DISABLE__SHIFT', + 'SQ_CONFIG1__DPMACC_DGEMM2X_MGCG_OVERRIDE_MASK', + 'SQ_CONFIG1__DPMACC_DGEMM2X_MGCG_OVERRIDE__SHIFT', + 'SQ_CONFIG1__DPMACC_MGCG_OVERRIDE_MASK', + 'SQ_CONFIG1__DPMACC_MGCG_OVERRIDE__SHIFT', + 'SQ_CONFIG1__EXPAND_SP_CMD_FGCG_MASK', + 'SQ_CONFIG1__EXPAND_SP_CMD_FGCG__SHIFT', + 'SQ_CONFIG1__EXPAND_SP_EXPORT_FGCG_MASK', + 'SQ_CONFIG1__EXPAND_SP_EXPORT_FGCG__SHIFT', + 'SQ_CONFIG1__EXTRA_DGEMM_PROTECT_EN_MASK', + 'SQ_CONFIG1__EXTRA_DGEMM_PROTECT_EN__SHIFT', + 'SQ_CONFIG1__SPMACC_MGCG_OVERRIDE_MASK', + 'SQ_CONFIG1__SPMACC_MGCG_OVERRIDE__SHIFT', + 'SQ_CONFIG1__SP_CORE1_MGCG_OVERRIDE_MASK', + 'SQ_CONFIG1__SP_CORE1_MGCG_OVERRIDE__SHIFT', + 'SQ_CONFIG1__SP_CORE4_MGCG_OVERRIDE_MASK', + 'SQ_CONFIG1__SP_CORE4_MGCG_OVERRIDE__SHIFT', + 'SQ_CONFIG1__SP_CORE5_MGCG_OVERRIDE_MASK', + 'SQ_CONFIG1__SP_CORE5_MGCG_OVERRIDE__SHIFT', + 'SQ_CONFIG1__SP_FGCG_REP_OVERRIDE_MASK', + 'SQ_CONFIG1__SP_FGCG_REP_OVERRIDE__SHIFT', + 'SQ_CONFIG1__SP_SRC_1ST_BUFFER_MGCG_OVERRIDE_MASK', + 'SQ_CONFIG1__SP_SRC_1ST_BUFFER_MGCG_OVERRIDE__SHIFT', + 'SQ_CONFIG1__TRANSMACC_MGCG_OVERRIDE_MASK', + 'SQ_CONFIG1__TRANSMACC_MGCG_OVERRIDE__SHIFT', + 'SQ_CONFIG1__VGPR_ARB_PLUS1_MASK', + 'SQ_CONFIG1__VGPR_ARB_PLUS1__SHIFT', + 'SQ_CONFIG1__XDLMACC_MGCG_OVERRIDE_MASK', + 'SQ_CONFIG1__XDLMACC_MGCG_OVERRIDE__SHIFT', + 'SQ_CONFIG__DEBUG_EN_MASK', 'SQ_CONFIG__DEBUG_EN__SHIFT', + 'SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK', + 'SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT', + 'SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK', + 'SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT', + 'SQ_CONFIG__DISABLE_BARRIER_WAITCNT_MASK', + 'SQ_CONFIG__DISABLE_BARRIER_WAITCNT__SHIFT', + 'SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK', + 'SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT', + 'SQ_CONFIG__DISABLE_MAI_CO_EXEC_MASK', + 'SQ_CONFIG__DISABLE_MAI_CO_EXEC__SHIFT', + 'SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK', + 'SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT', + 'SQ_CONFIG__DISABLE_RAM_CLOCK_GATING_MASK', + 'SQ_CONFIG__DISABLE_RAM_CLOCK_GATING__SHIFT', + 'SQ_CONFIG__DISABLE_REPEATER_FGCG_CLOCK_GATING_MASK', + 'SQ_CONFIG__DISABLE_REPEATER_FGCG_CLOCK_GATING__SHIFT', + 'SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK', + 'SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT', + 'SQ_CONFIG__DISABLE_SPIPRIO_OVER_USERPRIO_MASK', + 'SQ_CONFIG__DISABLE_SPIPRIO_OVER_USERPRIO__SHIFT', + 'SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK', + 'SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT', + 'SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK', + 'SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT', + 'SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK', + 'SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT', + 'SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK', + 'SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT', + 'SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK', + 'SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT', + 'SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK', + 'SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT', + 'SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK', + 'SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT', + 'SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK', + 'SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT', + 'SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK', + 'SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT', + 'SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK', + 'SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT', + 'SQ_CONFIG__OVERRIDE_MAI_ALU_BUSY_MASK', + 'SQ_CONFIG__OVERRIDE_MAI_ALU_BUSY__SHIFT', + 'SQ_CONFIG__OVERRIDE_SP_MAI_ALU_BUSY_MASK', + 'SQ_CONFIG__OVERRIDE_SP_MAI_ALU_BUSY__SHIFT', + 'SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK', + 'SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT', + 'SQ_CONFIG__REPLAY_SLEEP_CNT_MASK', + 'SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT', + 'SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_MOPS_NON_WAVE_MASK', + 'SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_MOPS_NON_WAVE__SHIFT', + 'SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_NON_WAVE_MASK', + 'SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_NON_WAVE__SHIFT', + 'SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK', + 'SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT', + 'SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_FLAT_SCRATCH_READ_PROTECT_MASK', + 'SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_FLAT_SCRATCH_READ_PROTECT__SHIFT', + 'SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_FLAT_SCRATCH_WRITE_PROTECT_MASK', + 'SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_FLAT_SCRATCH_WRITE_PROTECT__SHIFT', + 'SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_SNAPSHOT_TRAP_ON_BARRIER_MASK', + 'SQ_DEBUG_FOR_INTERNAL_CTRL__DISABLE_SNAPSHOT_TRAP_ON_BARRIER__SHIFT', + 'SQ_DEBUG_FOR_INTERNAL_CTRL__ENABLE_DED_TRIGGER_HALT_MASK', + 'SQ_DEBUG_FOR_INTERNAL_CTRL__ENABLE_DED_TRIGGER_HALT__SHIFT', + 'SQ_DEBUG_FOR_INTERNAL_CTRL__FLAG_RD_FLAT_SCRATCH_RETURN_ZERO_MASK', + 'SQ_DEBUG_FOR_INTERNAL_CTRL__FLAG_RD_FLAT_SCRATCH_RETURN_ZERO__SHIFT', + 'SQ_DEBUG_FOR_INTERNAL_CTRL__FLAG_WR_ADDR_MATCH_FLAT_SCRATCH_MASK', + 'SQ_DEBUG_FOR_INTERNAL_CTRL__FLAG_WR_ADDR_MATCH_FLAT_SCRATCH__SHIFT', + 'SQ_DEBUG_PERFCOUNT_TRAP__COUNTER_MASK', + 'SQ_DEBUG_PERFCOUNT_TRAP__COUNTER__SHIFT', + 'SQ_DEBUG_PERFCOUNT_TRAP__ENABLE_MASK', + 'SQ_DEBUG_PERFCOUNT_TRAP__ENABLE__SHIFT', + 'SQ_DEBUG_PERFCOUNT_TRAP__LIMIT_MASK', + 'SQ_DEBUG_PERFCOUNT_TRAP__LIMIT__SHIFT', + 'SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK', + 'SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT', + 'SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK', + 'SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT', + 'SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK', + 'SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT', + 'SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK', + 'SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT', + 'SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK', + 'SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT', + 'SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK', + 'SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT', + 'SQ_DEBUG_STS_GLOBAL__BUSY_MASK', + 'SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT', + 'SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK', + 'SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT', + 'SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK', + 'SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT', + 'SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK', + 'SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT', + 'SQ_DEBUG_STS_LOCAL__BUSY_MASK', + 'SQ_DEBUG_STS_LOCAL__BUSY__SHIFT', + 'SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK', + 'SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT', + 'SQ_DEBUG__SINGLE_ALU_OP_MASK', 'SQ_DEBUG__SINGLE_ALU_OP__SHIFT', + 'SQ_DEBUG__SINGLE_MEMOP_MASK', 'SQ_DEBUG__SINGLE_MEMOP__SHIFT', + 'SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK', + 'SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT', + 'SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK', + 'SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT', + 'SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK', + 'SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT', + 'SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK', + 'SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT', + 'SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK', + 'SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT', + 'SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK', + 'SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT', + 'SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK', + 'SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT', + 'SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK', + 'SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT', + 'SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK', + 'SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT', + 'SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK', + 'SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT', + 'SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK', + 'SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT', + 'SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK', + 'SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT', + 'SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK', + 'SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT', + 'SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK', + 'SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT', + 'SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK', + 'SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT', + 'SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK', + 'SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT', + 'SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK', + 'SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT', + 'SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK', + 'SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT', + 'SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK', + 'SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT', + 'SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK', + 'SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT', + 'SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK', + 'SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT', + 'SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK', + 'SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT', + 'SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK', + 'SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT', + 'SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK', + 'SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT', + 'SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK', + 'SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT', + 'SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK', + 'SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT', + 'SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK', + 'SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT', 'SQ_DS_0__ACC_MASK', + 'SQ_DS_0__ACC__SHIFT', 'SQ_DS_0__ENCODING_MASK', + 'SQ_DS_0__ENCODING__SHIFT', 'SQ_DS_0__GDS_MASK', + 'SQ_DS_0__GDS__SHIFT', 'SQ_DS_0__OFFSET0_MASK', + 'SQ_DS_0__OFFSET0__SHIFT', 'SQ_DS_0__OFFSET1_MASK', + 'SQ_DS_0__OFFSET1__SHIFT', 'SQ_DS_0__OP_MASK', + 'SQ_DS_0__OP__SHIFT', 'SQ_DS_1__ADDR_MASK', + 'SQ_DS_1__ADDR__SHIFT', 'SQ_DS_1__DATA0_MASK', + 'SQ_DS_1__DATA0__SHIFT', 'SQ_DS_1__DATA1_MASK', + 'SQ_DS_1__DATA1__SHIFT', 'SQ_DS_1__VDST_MASK', + 'SQ_DS_1__VDST__SHIFT', 'SQ_EDC_CNT__LDS_D_DED_COUNT_MASK', + 'SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT', + 'SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK', + 'SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT', + 'SQ_EDC_CNT__LDS_I_DED_COUNT_MASK', + 'SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT', + 'SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK', + 'SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT', + 'SQ_EDC_CNT__SGPR_DED_COUNT_MASK', + 'SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT', + 'SQ_EDC_CNT__SGPR_SEC_COUNT_MASK', + 'SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT', + 'SQ_EDC_CNT__VGPR0_DED_COUNT_MASK', + 'SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT', + 'SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK', + 'SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT', + 'SQ_EDC_CNT__VGPR1_DED_COUNT_MASK', + 'SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT', + 'SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK', + 'SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT', + 'SQ_EDC_CNT__VGPR2_DED_COUNT_MASK', + 'SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT', + 'SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK', + 'SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT', + 'SQ_EDC_CNT__VGPR3_DED_COUNT_MASK', + 'SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT', + 'SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK', + 'SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT', + 'SQ_EDC_DED_CNT__LDS_DED_MASK', 'SQ_EDC_DED_CNT__LDS_DED__SHIFT', + 'SQ_EDC_DED_CNT__SGPR_DED_MASK', + 'SQ_EDC_DED_CNT__SGPR_DED__SHIFT', + 'SQ_EDC_DED_CNT__VGPR_DED_MASK', + 'SQ_EDC_DED_CNT__VGPR_DED__SHIFT', + 'SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK', + 'SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT', + 'SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK', + 'SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT', + 'SQ_EDC_INFO__SIMD_ID_MASK', 'SQ_EDC_INFO__SIMD_ID__SHIFT', + 'SQ_EDC_INFO__SOURCE_MASK', 'SQ_EDC_INFO__SOURCE__SHIFT', + 'SQ_EDC_INFO__VM_ID_MASK', 'SQ_EDC_INFO__VM_ID__SHIFT', + 'SQ_EDC_INFO__WAVE_ID_MASK', 'SQ_EDC_INFO__WAVE_ID__SHIFT', + 'SQ_EDC_SEC_CNT__LDS_SEC_MASK', 'SQ_EDC_SEC_CNT__LDS_SEC__SHIFT', + 'SQ_EDC_SEC_CNT__SGPR_SEC_MASK', + 'SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT', + 'SQ_EDC_SEC_CNT__VGPR_SEC_MASK', + 'SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT', 'SQ_EXP_0__COMPR_MASK', + 'SQ_EXP_0__COMPR__SHIFT', 'SQ_EXP_0__DONE_MASK', + 'SQ_EXP_0__DONE__SHIFT', 'SQ_EXP_0__ENCODING_MASK', + 'SQ_EXP_0__ENCODING__SHIFT', 'SQ_EXP_0__EN_MASK', + 'SQ_EXP_0__EN__SHIFT', 'SQ_EXP_0__TGT_MASK', + 'SQ_EXP_0__TGT__SHIFT', 'SQ_EXP_0__VM_MASK', + 'SQ_EXP_0__VM__SHIFT', 'SQ_EXP_1__VSRC0_MASK', + 'SQ_EXP_1__VSRC0__SHIFT', 'SQ_EXP_1__VSRC1_MASK', + 'SQ_EXP_1__VSRC1__SHIFT', 'SQ_EXP_1__VSRC2_MASK', + 'SQ_EXP_1__VSRC2__SHIFT', 'SQ_EXP_1__VSRC3_MASK', + 'SQ_EXP_1__VSRC3__SHIFT', + 'SQ_FED_INTERRUPT_STATUS__FED_HALT_DISABLE_MASK', + 'SQ_FED_INTERRUPT_STATUS__FED_HALT_DISABLE__SHIFT', + 'SQ_FED_INTERRUPT_STATUS__INTERRUPT_CU_ID_MASK', + 'SQ_FED_INTERRUPT_STATUS__INTERRUPT_CU_ID__SHIFT', + 'SQ_FED_INTERRUPT_STATUS__INTERRUPT_SIMD_ID_MASK', + 'SQ_FED_INTERRUPT_STATUS__INTERRUPT_SIMD_ID__SHIFT', + 'SQ_FED_INTERRUPT_STATUS__INTERRUPT_STATUS_MASK', + 'SQ_FED_INTERRUPT_STATUS__INTERRUPT_STATUS__SHIFT', + 'SQ_FED_INTERRUPT_STATUS__INTERRUPT_VM_ID_MASK', + 'SQ_FED_INTERRUPT_STATUS__INTERRUPT_VM_ID__SHIFT', + 'SQ_FED_INTERRUPT_STATUS__INTERRUPT_WAVE_ID_MASK', + 'SQ_FED_INTERRUPT_STATUS__INTERRUPT_WAVE_ID__SHIFT', + 'SQ_FED_INTERRUPT_STATUS__TO_IH_DISABLE_MASK', + 'SQ_FED_INTERRUPT_STATUS__TO_IH_DISABLE__SHIFT', + 'SQ_FED_INTERRUPT_STATUS__TO_RSMU_DISABLE_MASK', + 'SQ_FED_INTERRUPT_STATUS__TO_RSMU_DISABLE__SHIFT', + 'SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK', + 'SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT', + 'SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK', + 'SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT', + 'SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK', + 'SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT', + 'SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK', + 'SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT', + 'SQ_FLAT_0__ENCODING_MASK', 'SQ_FLAT_0__ENCODING__SHIFT', + 'SQ_FLAT_0__NT_MASK', 'SQ_FLAT_0__NT__SHIFT', + 'SQ_FLAT_0__OFFSET_MASK', 'SQ_FLAT_0__OFFSET__SHIFT', + 'SQ_FLAT_0__OP_MASK', 'SQ_FLAT_0__OP__SHIFT', + 'SQ_FLAT_0__SC0_MASK', 'SQ_FLAT_0__SC0__SHIFT', + 'SQ_FLAT_0__SC1_MASK', 'SQ_FLAT_0__SC1__SHIFT', + 'SQ_FLAT_0__SEG_MASK', 'SQ_FLAT_0__SEG__SHIFT', + 'SQ_FLAT_0__SVE_MASK', 'SQ_FLAT_0__SVE__SHIFT', + 'SQ_FLAT_1__ACC_MASK', 'SQ_FLAT_1__ACC__SHIFT', + 'SQ_FLAT_1__ADDR_MASK', 'SQ_FLAT_1__ADDR__SHIFT', + 'SQ_FLAT_1__DATA_MASK', 'SQ_FLAT_1__DATA__SHIFT', + 'SQ_FLAT_1__SADDR_MASK', 'SQ_FLAT_1__SADDR__SHIFT', + 'SQ_FLAT_1__VDST_MASK', 'SQ_FLAT_1__VDST__SHIFT', + 'SQ_FLAT_SCRATCH_WORD0__SIZE_MASK', + 'SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT', + 'SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK', + 'SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT', + 'SQ_GLBL_0__ENCODING_MASK', 'SQ_GLBL_0__ENCODING__SHIFT', + 'SQ_GLBL_0__NT_MASK', 'SQ_GLBL_0__NT__SHIFT', + 'SQ_GLBL_0__OFFSET_MASK', 'SQ_GLBL_0__OFFSET__SHIFT', + 'SQ_GLBL_0__OP_MASK', 'SQ_GLBL_0__OP__SHIFT', + 'SQ_GLBL_0__SC0_MASK', 'SQ_GLBL_0__SC0__SHIFT', + 'SQ_GLBL_0__SC1_MASK', 'SQ_GLBL_0__SC1__SHIFT', + 'SQ_GLBL_0__SEG_MASK', 'SQ_GLBL_0__SEG__SHIFT', + 'SQ_GLBL_0__SVE_MASK', 'SQ_GLBL_0__SVE__SHIFT', + 'SQ_GLBL_1__ACC_MASK', 'SQ_GLBL_1__ACC__SHIFT', + 'SQ_GLBL_1__ADDR_MASK', 'SQ_GLBL_1__ADDR__SHIFT', + 'SQ_GLBL_1__DATA_MASK', 'SQ_GLBL_1__DATA__SHIFT', + 'SQ_GLBL_1__SADDR_MASK', 'SQ_GLBL_1__SADDR__SHIFT', + 'SQ_GLBL_1__VDST_MASK', 'SQ_GLBL_1__VDST__SHIFT', + 'SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT_MASK', + 'SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT__SHIFT', + 'SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE_MASK', + 'SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE__SHIFT', + 'SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK', + 'SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT', + 'SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK', + 'SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT', + 'SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK', + 'SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT', + 'SQ_IMG_RSRC_WORD1__META_DIRECT_MASK', + 'SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT', + 'SQ_IMG_RSRC_WORD1__MIN_LOD_MASK', + 'SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT', + 'SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK', + 'SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT', + 'SQ_IMG_RSRC_WORD1__NV_MASK', 'SQ_IMG_RSRC_WORD1__NV__SHIFT', + 'SQ_IMG_RSRC_WORD2__HEIGHT_MASK', + 'SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT', + 'SQ_IMG_RSRC_WORD2__PERF_MOD_MASK', + 'SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT', + 'SQ_IMG_RSRC_WORD2__WIDTH_MASK', + 'SQ_IMG_RSRC_WORD2__WIDTH__SHIFT', + 'SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK', + 'SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT', + 'SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK', + 'SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT', + 'SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK', + 'SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT', + 'SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK', + 'SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT', + 'SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK', + 'SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT', + 'SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK', + 'SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT', + 'SQ_IMG_RSRC_WORD3__SW_MODE_MASK', + 'SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT', + 'SQ_IMG_RSRC_WORD3__TYPE_MASK', 'SQ_IMG_RSRC_WORD3__TYPE__SHIFT', + 'SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK', + 'SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT', + 'SQ_IMG_RSRC_WORD4__DEPTH_MASK', + 'SQ_IMG_RSRC_WORD4__DEPTH__SHIFT', + 'SQ_IMG_RSRC_WORD4__PITCH_MASK', + 'SQ_IMG_RSRC_WORD4__PITCH__SHIFT', + 'SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK', + 'SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT', + 'SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK', + 'SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT', + 'SQ_IMG_RSRC_WORD5__MAX_MIP_MASK', + 'SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT', + 'SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK', + 'SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT', + 'SQ_IMG_RSRC_WORD5__META_LINEAR_MASK', + 'SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT', + 'SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK', + 'SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT', + 'SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK', + 'SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT', + 'SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK', + 'SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT', + 'SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK', + 'SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT', + 'SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK', + 'SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT', + 'SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK', + 'SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT', + 'SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK', + 'SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT', + 'SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK', + 'SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT', + 'SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK', + 'SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT', + 'SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK', + 'SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT', + 'SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK', + 'SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT', + 'SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK', + 'SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT', + 'SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK', + 'SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT', + 'SQ_IMG_SAMP_WORD0__CLAMP_X_MASK', + 'SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT', + 'SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK', + 'SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT', + 'SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK', + 'SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT', + 'SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK', + 'SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT', + 'SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK', + 'SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT', + 'SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK', + 'SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT', + 'SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK', + 'SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT', + 'SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK', + 'SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT', + 'SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK', + 'SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT', + 'SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK', + 'SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT', + 'SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK', + 'SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT', + 'SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK', + 'SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT', + 'SQ_IMG_SAMP_WORD1__MAX_LOD_MASK', + 'SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT', + 'SQ_IMG_SAMP_WORD1__MIN_LOD_MASK', + 'SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT', + 'SQ_IMG_SAMP_WORD1__PERF_MIP_MASK', + 'SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT', + 'SQ_IMG_SAMP_WORD1__PERF_Z_MASK', + 'SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT', + 'SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK', + 'SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT', + 'SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK', + 'SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT', + 'SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK', + 'SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT', + 'SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK', + 'SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK', + 'SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT', + 'SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT', + 'SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK', + 'SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT', + 'SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK', + 'SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT', + 'SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK', + 'SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT', + 'SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK', + 'SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT', + 'SQ_IMG_SAMP_WORD2__Z_FILTER_MASK', + 'SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT', + 'SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK', + 'SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT', + 'SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK', + 'SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT', + 'SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK', + 'SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT', + 'SQ_IND_DATA__DATA_MASK', 'SQ_IND_DATA__DATA__SHIFT', + 'SQ_IND_INDEX__AUTO_INCR_MASK', 'SQ_IND_INDEX__AUTO_INCR__SHIFT', + 'SQ_IND_INDEX__FORCE_READ_MASK', + 'SQ_IND_INDEX__FORCE_READ__SHIFT', 'SQ_IND_INDEX__INDEX_MASK', + 'SQ_IND_INDEX__INDEX__SHIFT', 'SQ_IND_INDEX__READ_TIMEOUT_MASK', + 'SQ_IND_INDEX__READ_TIMEOUT__SHIFT', 'SQ_IND_INDEX__SIMD_ID_MASK', + 'SQ_IND_INDEX__SIMD_ID__SHIFT', 'SQ_IND_INDEX__THREAD_ID_MASK', + 'SQ_IND_INDEX__THREAD_ID__SHIFT', 'SQ_IND_INDEX__UNINDEXED_MASK', + 'SQ_IND_INDEX__UNINDEXED__SHIFT', 'SQ_IND_INDEX__WAVE_ID_MASK', + 'SQ_IND_INDEX__WAVE_ID__SHIFT', 'SQ_INST__ENCODING_MASK', + 'SQ_INST__ENCODING__SHIFT', 'SQ_INTERRUPT_AUTO_MASK__MASK_MASK', + 'SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT', + 'SQ_INTERRUPT_MSG_CTRL__STALL_MASK', + 'SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK', + 'SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_HI__ENCODING_MASK', + 'SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_HI__SE_ID_MASK', + 'SQ_INTERRUPT_WORD_AUTO_HI__SE_ID__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP_MASK', + 'SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW_MASK', + 'SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW_MASK', + 'SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW_MASK', + 'SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP_MASK', + 'SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL_MASK', + 'SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_MASK', + 'SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR_MASK', + 'SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE__SHIFT', + 'SQ_INTERRUPT_WORD_AUTO_LO__WLT_MASK', + 'SQ_INTERRUPT_WORD_AUTO_LO__WLT__SHIFT', + 'SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING_MASK', + 'SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING__SHIFT', + 'SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID_MASK', + 'SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID__SHIFT', + 'SQ_INTERRUPT_WORD_CMN_HI__ENCODING_MASK', + 'SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT', + 'SQ_INTERRUPT_WORD_CMN_HI__SE_ID_MASK', + 'SQ_INTERRUPT_WORD_CMN_HI__SE_ID__SHIFT', + 'SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK', + 'SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT', + 'SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK', + 'SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT', + 'SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK', + 'SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT', + 'SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK', + 'SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT', + 'SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK', + 'SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT', + 'SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK', + 'SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT', + 'SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK', + 'SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT', + 'SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK', + 'SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT', + 'SQ_INTERRUPT_WORD_WAVE_HI__CU_ID_MASK', + 'SQ_INTERRUPT_WORD_WAVE_HI__CU_ID__SHIFT', + 'SQ_INTERRUPT_WORD_WAVE_HI__ENCODING_MASK', + 'SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT', + 'SQ_INTERRUPT_WORD_WAVE_HI__SE_ID_MASK', + 'SQ_INTERRUPT_WORD_WAVE_HI__SE_ID__SHIFT', + 'SQ_INTERRUPT_WORD_WAVE_HI__VM_ID_MASK', + 'SQ_INTERRUPT_WORD_WAVE_HI__VM_ID__SHIFT', + 'SQ_INTERRUPT_WORD_WAVE_LO__DATA_MASK', + 'SQ_INTERRUPT_WORD_WAVE_LO__DATA__SHIFT', + 'SQ_INTERRUPT_WORD_WAVE_LO__PRIV_MASK', + 'SQ_INTERRUPT_WORD_WAVE_LO__PRIV__SHIFT', + 'SQ_INTERRUPT_WORD_WAVE_LO__SH_ID_MASK', + 'SQ_INTERRUPT_WORD_WAVE_LO__SH_ID__SHIFT', + 'SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID_MASK', + 'SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID__SHIFT', + 'SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID_MASK', + 'SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID__SHIFT', + 'SQ_LB_CTR0_CU__SH0_MASK_MASK', 'SQ_LB_CTR0_CU__SH0_MASK__SHIFT', + 'SQ_LB_CTR0_CU__SH1_MASK_MASK', 'SQ_LB_CTR0_CU__SH1_MASK__SHIFT', + 'SQ_LB_CTR1_CU__SH0_MASK_MASK', 'SQ_LB_CTR1_CU__SH0_MASK__SHIFT', + 'SQ_LB_CTR1_CU__SH1_MASK_MASK', 'SQ_LB_CTR1_CU__SH1_MASK__SHIFT', + 'SQ_LB_CTR2_CU__SH0_MASK_MASK', 'SQ_LB_CTR2_CU__SH0_MASK__SHIFT', + 'SQ_LB_CTR2_CU__SH1_MASK_MASK', 'SQ_LB_CTR2_CU__SH1_MASK__SHIFT', + 'SQ_LB_CTR3_CU__SH0_MASK_MASK', 'SQ_LB_CTR3_CU__SH0_MASK__SHIFT', + 'SQ_LB_CTR3_CU__SH1_MASK_MASK', 'SQ_LB_CTR3_CU__SH1_MASK__SHIFT', + 'SQ_LB_CTR_CTRL__CLEAR_MASK', 'SQ_LB_CTR_CTRL__CLEAR__SHIFT', + 'SQ_LB_CTR_CTRL__LOAD_MASK', 'SQ_LB_CTR_CTRL__LOAD__SHIFT', + 'SQ_LB_CTR_CTRL__START_MASK', 'SQ_LB_CTR_CTRL__START__SHIFT', + 'SQ_LB_CTR_SEL__SEL0_MASK', 'SQ_LB_CTR_SEL__SEL0__SHIFT', + 'SQ_LB_CTR_SEL__SEL1_MASK', 'SQ_LB_CTR_SEL__SEL1__SHIFT', + 'SQ_LB_CTR_SEL__SEL2_MASK', 'SQ_LB_CTR_SEL__SEL2__SHIFT', + 'SQ_LB_CTR_SEL__SEL3_MASK', 'SQ_LB_CTR_SEL__SEL3__SHIFT', + 'SQ_LB_DATA0__DATA_MASK', 'SQ_LB_DATA0__DATA__SHIFT', + 'SQ_LB_DATA1__DATA_MASK', 'SQ_LB_DATA1__DATA__SHIFT', + 'SQ_LB_DATA2__DATA_MASK', 'SQ_LB_DATA2__DATA__SHIFT', + 'SQ_LB_DATA3__DATA_MASK', 'SQ_LB_DATA3__DATA__SHIFT', + 'SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK', + 'SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT', + 'SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK', + 'SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT', + 'SQ_M0_GPR_IDX_WORD__INDEX_MASK', + 'SQ_M0_GPR_IDX_WORD__INDEX__SHIFT', + 'SQ_M0_GPR_IDX_WORD__VDST_REL_MASK', + 'SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT', + 'SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK', + 'SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT', + 'SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK', + 'SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT', + 'SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK', + 'SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT', 'SQ_MIMG_0__A16_MASK', + 'SQ_MIMG_0__A16__SHIFT', 'SQ_MIMG_0__ACC_MASK', + 'SQ_MIMG_0__ACC__SHIFT', 'SQ_MIMG_0__DA_MASK', + 'SQ_MIMG_0__DA__SHIFT', 'SQ_MIMG_0__DMASK_MASK', + 'SQ_MIMG_0__DMASK__SHIFT', 'SQ_MIMG_0__ENCODING_MASK', + 'SQ_MIMG_0__ENCODING__SHIFT', 'SQ_MIMG_0__LWE_MASK', + 'SQ_MIMG_0__LWE__SHIFT', 'SQ_MIMG_0__NT_MASK', + 'SQ_MIMG_0__NT__SHIFT', 'SQ_MIMG_0__OPM_MASK', + 'SQ_MIMG_0__OPM__SHIFT', 'SQ_MIMG_0__OP_MASK', + 'SQ_MIMG_0__OP__SHIFT', 'SQ_MIMG_0__SC0_MASK', + 'SQ_MIMG_0__SC0__SHIFT', 'SQ_MIMG_0__SC1_MASK', + 'SQ_MIMG_0__SC1__SHIFT', 'SQ_MIMG_0__UNORM_MASK', + 'SQ_MIMG_0__UNORM__SHIFT', 'SQ_MIMG_1__D16_MASK', + 'SQ_MIMG_1__D16__SHIFT', 'SQ_MIMG_1__SRSRC_MASK', + 'SQ_MIMG_1__SRSRC__SHIFT', 'SQ_MIMG_1__SSAMP_MASK', + 'SQ_MIMG_1__SSAMP__SHIFT', 'SQ_MIMG_1__VADDR_MASK', + 'SQ_MIMG_1__VADDR__SHIFT', 'SQ_MIMG_1__VDATA_MASK', + 'SQ_MIMG_1__VDATA__SHIFT', 'SQ_MTBUF_0__DFMT_MASK', + 'SQ_MTBUF_0__DFMT__SHIFT', 'SQ_MTBUF_0__ENCODING_MASK', + 'SQ_MTBUF_0__ENCODING__SHIFT', 'SQ_MTBUF_0__IDXEN_MASK', + 'SQ_MTBUF_0__IDXEN__SHIFT', 'SQ_MTBUF_0__NFMT_MASK', + 'SQ_MTBUF_0__NFMT__SHIFT', 'SQ_MTBUF_0__OFFEN_MASK', + 'SQ_MTBUF_0__OFFEN__SHIFT', 'SQ_MTBUF_0__OFFSET_MASK', + 'SQ_MTBUF_0__OFFSET__SHIFT', 'SQ_MTBUF_0__OP_MASK', + 'SQ_MTBUF_0__OP__SHIFT', 'SQ_MTBUF_0__SC0_MASK', + 'SQ_MTBUF_0__SC0__SHIFT', 'SQ_MTBUF_1__ACC_MASK', + 'SQ_MTBUF_1__ACC__SHIFT', 'SQ_MTBUF_1__NT_MASK', + 'SQ_MTBUF_1__NT__SHIFT', 'SQ_MTBUF_1__SC1_MASK', + 'SQ_MTBUF_1__SC1__SHIFT', 'SQ_MTBUF_1__SOFFSET_MASK', + 'SQ_MTBUF_1__SOFFSET__SHIFT', 'SQ_MTBUF_1__SRSRC_MASK', + 'SQ_MTBUF_1__SRSRC__SHIFT', 'SQ_MTBUF_1__VADDR_MASK', + 'SQ_MTBUF_1__VADDR__SHIFT', 'SQ_MTBUF_1__VDATA_MASK', + 'SQ_MTBUF_1__VDATA__SHIFT', 'SQ_MUBUF_0__ENCODING_MASK', + 'SQ_MUBUF_0__ENCODING__SHIFT', 'SQ_MUBUF_0__IDXEN_MASK', + 'SQ_MUBUF_0__IDXEN__SHIFT', 'SQ_MUBUF_0__LDS_MASK', + 'SQ_MUBUF_0__LDS__SHIFT', 'SQ_MUBUF_0__NT_MASK', + 'SQ_MUBUF_0__NT__SHIFT', 'SQ_MUBUF_0__OFFEN_MASK', + 'SQ_MUBUF_0__OFFEN__SHIFT', 'SQ_MUBUF_0__OFFSET_MASK', + 'SQ_MUBUF_0__OFFSET__SHIFT', 'SQ_MUBUF_0__OP_MASK', + 'SQ_MUBUF_0__OP__SHIFT', 'SQ_MUBUF_0__SC0_MASK', + 'SQ_MUBUF_0__SC0__SHIFT', 'SQ_MUBUF_0__SC1_MASK', + 'SQ_MUBUF_0__SC1__SHIFT', 'SQ_MUBUF_1__ACC_MASK', + 'SQ_MUBUF_1__ACC__SHIFT', 'SQ_MUBUF_1__SOFFSET_MASK', + 'SQ_MUBUF_1__SOFFSET__SHIFT', 'SQ_MUBUF_1__SRSRC_MASK', + 'SQ_MUBUF_1__SRSRC__SHIFT', 'SQ_MUBUF_1__VADDR_MASK', + 'SQ_MUBUF_1__VADDR__SHIFT', 'SQ_MUBUF_1__VDATA_MASK', + 'SQ_MUBUF_1__VDATA__SHIFT', + 'SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK', + 'SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT', + 'SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK', + 'SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT', + 'SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK', + 'SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT', + 'SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK', + 'SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT', + 'SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK', + 'SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT', + 'SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK', + 'SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT', + 'SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK', + 'SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT', + 'SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK', + 'SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT', + 'SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK', + 'SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT', + 'SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK', + 'SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT', + 'SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK', + 'SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT', + 'SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK', + 'SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT', + 'SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK', + 'SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT', + 'SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK', + 'SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT', + 'SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK', + 'SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT', + 'SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK', + 'SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT', + 'SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK', + 'SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT', + 'SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK', + 'SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT', + 'SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK', + 'SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT', + 'SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK', + 'SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT', + 'SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK', + 'SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT', + 'SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK', + 'SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT', + 'SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK', + 'SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT', + 'SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK', + 'SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT', + 'SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK', + 'SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT', + 'SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK', + 'SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT', + 'SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK', + 'SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT', + 'SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK', + 'SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT', + 'SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK', + 'SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT', + 'SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK', + 'SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT', + 'SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK', + 'SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT', + 'SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK', + 'SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT', + 'SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK', + 'SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT', + 'SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK', + 'SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT', + 'SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK', + 'SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT', + 'SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK', + 'SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT', + 'SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK', + 'SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT', + 'SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK', + 'SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT', + 'SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK', + 'SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT', + 'SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK', + 'SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT', + 'SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK', + 'SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT', + 'SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK', + 'SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT', + 'SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK', + 'SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT', + 'SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK', + 'SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT', + 'SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK', + 'SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT', + 'SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK', + 'SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT', + 'SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK', + 'SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT', + 'SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK', + 'SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT', + 'SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK', + 'SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT', + 'SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK', + 'SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT', + 'SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK', + 'SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT', + 'SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK', + 'SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT', + 'SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK', + 'SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT', + 'SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK', + 'SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT', + 'SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK', + 'SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT', + 'SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK', + 'SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT', + 'SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK', + 'SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT', + 'SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK', + 'SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT', + 'SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK', + 'SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT', + 'SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK', + 'SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT', + 'SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK', + 'SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT', + 'SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK', + 'SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT', + 'SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK', + 'SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT', + 'SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK', + 'SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT', + 'SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK', + 'SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT', + 'SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK', + 'SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT', + 'SQ_PERFCOUNTER_CTRL__CS_EN_MASK', + 'SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT', + 'SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK', + 'SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT', + 'SQ_PERFCOUNTER_CTRL__ES_EN_MASK', + 'SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT', + 'SQ_PERFCOUNTER_CTRL__GS_EN_MASK', + 'SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT', + 'SQ_PERFCOUNTER_CTRL__HS_EN_MASK', + 'SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT', + 'SQ_PERFCOUNTER_CTRL__LS_EN_MASK', + 'SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT', + 'SQ_PERFCOUNTER_CTRL__PS_EN_MASK', + 'SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT', + 'SQ_PERFCOUNTER_CTRL__VMID_MASK_MASK', + 'SQ_PERFCOUNTER_CTRL__VMID_MASK__SHIFT', + 'SQ_PERFCOUNTER_CTRL__VS_EN_MASK', + 'SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT', + 'SQ_PERFCOUNTER_MASK__SH0_MASK_MASK', + 'SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT', + 'SQ_PERFCOUNTER_MASK__SH1_MASK_MASK', + 'SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT', + 'SQ_PERF_SNAPSHOT_CTRL__COUNT_INTVAL_MASK', + 'SQ_PERF_SNAPSHOT_CTRL__COUNT_INTVAL__SHIFT', + 'SQ_PERF_SNAPSHOT_CTRL__COUNT_SEL_MASK', + 'SQ_PERF_SNAPSHOT_CTRL__COUNT_SEL__SHIFT', + 'SQ_PERF_SNAPSHOT_CTRL__ENABLE_MASK', + 'SQ_PERF_SNAPSHOT_CTRL__ENABLE__SHIFT', + 'SQ_PERF_SNAPSHOT_CTRL__TEST_MODE_MASK', + 'SQ_PERF_SNAPSHOT_CTRL__TEST_MODE__SHIFT', + 'SQ_PERF_SNAPSHOT_CTRL__VMID_MASK_MASK', + 'SQ_PERF_SNAPSHOT_CTRL__VMID_MASK__SHIFT', + 'SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK', + 'SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT', + 'SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK', + 'SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT', + 'SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK', + 'SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT', + 'SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK', + 'SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT', + 'SQ_POWER_THROTTLE__MAX_POWER_MASK', + 'SQ_POWER_THROTTLE__MAX_POWER__SHIFT', + 'SQ_POWER_THROTTLE__MIN_POWER_MASK', + 'SQ_POWER_THROTTLE__MIN_POWER__SHIFT', + 'SQ_POWER_THROTTLE__PHASE_OFFSET_MASK', + 'SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT', + 'SQ_RANDOM_WAVE_PRI__RET_MASK', 'SQ_RANDOM_WAVE_PRI__RET__SHIFT', + 'SQ_RANDOM_WAVE_PRI__RNG_MASK', 'SQ_RANDOM_WAVE_PRI__RNG__SHIFT', + 'SQ_RANDOM_WAVE_PRI__RUI_MASK', 'SQ_RANDOM_WAVE_PRI__RUI__SHIFT', + 'SQ_REG_CREDITS__CMD_CREDITS_MASK', + 'SQ_REG_CREDITS__CMD_CREDITS__SHIFT', + 'SQ_REG_CREDITS__CMD_OVERFLOW_MASK', + 'SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT', + 'SQ_REG_CREDITS__IMMED_OVERFLOW_MASK', + 'SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT', + 'SQ_REG_CREDITS__REG_BUSY_MASK', + 'SQ_REG_CREDITS__REG_BUSY__SHIFT', + 'SQ_REG_CREDITS__SRBM_CREDITS_MASK', + 'SQ_REG_CREDITS__SRBM_CREDITS__SHIFT', + 'SQ_REG_CREDITS__SRBM_OVERFLOW_MASK', + 'SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT', + 'SQ_REG_TIMESTAMP__TIMESTAMP_MASK', + 'SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT', + 'SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK', + 'SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT', + 'SQ_SCRATCH_0__ENCODING_MASK', 'SQ_SCRATCH_0__ENCODING__SHIFT', + 'SQ_SCRATCH_0__NT_MASK', 'SQ_SCRATCH_0__NT__SHIFT', + 'SQ_SCRATCH_0__OFFSET_MASK', 'SQ_SCRATCH_0__OFFSET__SHIFT', + 'SQ_SCRATCH_0__OP_MASK', 'SQ_SCRATCH_0__OP__SHIFT', + 'SQ_SCRATCH_0__SC0_MASK', 'SQ_SCRATCH_0__SC0__SHIFT', + 'SQ_SCRATCH_0__SC1_MASK', 'SQ_SCRATCH_0__SC1__SHIFT', + 'SQ_SCRATCH_0__SEG_MASK', 'SQ_SCRATCH_0__SEG__SHIFT', + 'SQ_SCRATCH_0__SVE_MASK', 'SQ_SCRATCH_0__SVE__SHIFT', + 'SQ_SCRATCH_1__ACC_MASK', 'SQ_SCRATCH_1__ACC__SHIFT', + 'SQ_SCRATCH_1__ADDR_MASK', 'SQ_SCRATCH_1__ADDR__SHIFT', + 'SQ_SCRATCH_1__DATA_MASK', 'SQ_SCRATCH_1__DATA__SHIFT', + 'SQ_SCRATCH_1__SADDR_MASK', 'SQ_SCRATCH_1__SADDR__SHIFT', + 'SQ_SCRATCH_1__VDST_MASK', 'SQ_SCRATCH_1__VDST__SHIFT', + 'SQ_SHADER_TBA_HI__ADDR_HI_MASK', + 'SQ_SHADER_TBA_HI__ADDR_HI__SHIFT', + 'SQ_SHADER_TBA_LO__ADDR_LO_MASK', + 'SQ_SHADER_TBA_LO__ADDR_LO__SHIFT', + 'SQ_SHADER_TMA_HI__ADDR_HI_MASK', + 'SQ_SHADER_TMA_HI__ADDR_HI__SHIFT', + 'SQ_SHADER_TMA_LO__ADDR_LO_MASK', + 'SQ_SHADER_TMA_LO__ADDR_LO__SHIFT', 'SQ_SMEM_0__ENCODING_MASK', + 'SQ_SMEM_0__ENCODING__SHIFT', 'SQ_SMEM_0__GLC_MASK', + 'SQ_SMEM_0__GLC__SHIFT', 'SQ_SMEM_0__IMM_MASK', + 'SQ_SMEM_0__IMM__SHIFT', 'SQ_SMEM_0__NV_MASK', + 'SQ_SMEM_0__NV__SHIFT', 'SQ_SMEM_0__OP_MASK', + 'SQ_SMEM_0__OP__SHIFT', 'SQ_SMEM_0__SBASE_MASK', + 'SQ_SMEM_0__SBASE__SHIFT', 'SQ_SMEM_0__SDATA_MASK', + 'SQ_SMEM_0__SDATA__SHIFT', 'SQ_SMEM_0__SOFFSET_EN_MASK', + 'SQ_SMEM_0__SOFFSET_EN__SHIFT', 'SQ_SMEM_1__OFFSET_MASK', + 'SQ_SMEM_1__OFFSET__SHIFT', 'SQ_SMEM_1__SOFFSET_MASK', + 'SQ_SMEM_1__SOFFSET__SHIFT', 'SQ_SOP1__ENCODING_MASK', + 'SQ_SOP1__ENCODING__SHIFT', 'SQ_SOP1__OP_MASK', + 'SQ_SOP1__OP__SHIFT', 'SQ_SOP1__SDST_MASK', + 'SQ_SOP1__SDST__SHIFT', 'SQ_SOP1__SSRC0_MASK', + 'SQ_SOP1__SSRC0__SHIFT', 'SQ_SOP2__ENCODING_MASK', + 'SQ_SOP2__ENCODING__SHIFT', 'SQ_SOP2__OP_MASK', + 'SQ_SOP2__OP__SHIFT', 'SQ_SOP2__SDST_MASK', + 'SQ_SOP2__SDST__SHIFT', 'SQ_SOP2__SSRC0_MASK', + 'SQ_SOP2__SSRC0__SHIFT', 'SQ_SOP2__SSRC1_MASK', + 'SQ_SOP2__SSRC1__SHIFT', 'SQ_SOPC__ENCODING_MASK', + 'SQ_SOPC__ENCODING__SHIFT', 'SQ_SOPC__OP_MASK', + 'SQ_SOPC__OP__SHIFT', 'SQ_SOPC__SSRC0_MASK', + 'SQ_SOPC__SSRC0__SHIFT', 'SQ_SOPC__SSRC1_MASK', + 'SQ_SOPC__SSRC1__SHIFT', 'SQ_SOPK__ENCODING_MASK', + 'SQ_SOPK__ENCODING__SHIFT', 'SQ_SOPK__OP_MASK', + 'SQ_SOPK__OP__SHIFT', 'SQ_SOPK__SDST_MASK', + 'SQ_SOPK__SDST__SHIFT', 'SQ_SOPK__SIMM16_MASK', + 'SQ_SOPK__SIMM16__SHIFT', 'SQ_SOPP__ENCODING_MASK', + 'SQ_SOPP__ENCODING__SHIFT', 'SQ_SOPP__OP_MASK', + 'SQ_SOPP__OP__SHIFT', 'SQ_SOPP__SIMM16_MASK', + 'SQ_SOPP__SIMM16__SHIFT', 'SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK', + 'SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT', + 'SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK', + 'SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT', + 'SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK', + 'SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT', + 'SQ_THREAD_TRACE_BASE__ADDR_MASK', + 'SQ_THREAD_TRACE_BASE__ADDR__SHIFT', + 'SQ_THREAD_TRACE_CNTR__CNTR_MASK', + 'SQ_THREAD_TRACE_CNTR__CNTR__SHIFT', + 'SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK', + 'SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT', + 'SQ_THREAD_TRACE_HIWATER__HIWATER_MASK', + 'SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT', + 'SQ_THREAD_TRACE_MASK__CU_SEL_MASK', + 'SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT', + 'SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK', + 'SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT', + 'SQ_THREAD_TRACE_MASK__SH_SEL_MASK', + 'SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT', + 'SQ_THREAD_TRACE_MASK__SIMD_EN_MASK', + 'SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT', + 'SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK', + 'SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT', + 'SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK', + 'SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT', + 'SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK', + 'SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT', + 'SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK', + 'SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT', + 'SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK', + 'SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT', + 'SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK', + 'SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT', + 'SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK', + 'SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT', + 'SQ_THREAD_TRACE_MODE__MASK_CS_MASK', + 'SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT', + 'SQ_THREAD_TRACE_MODE__MASK_ES_MASK', + 'SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT', + 'SQ_THREAD_TRACE_MODE__MASK_GS_MASK', + 'SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT', + 'SQ_THREAD_TRACE_MODE__MASK_HS_MASK', + 'SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT', + 'SQ_THREAD_TRACE_MODE__MASK_LS_MASK', + 'SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT', + 'SQ_THREAD_TRACE_MODE__MASK_PS_MASK', + 'SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT', + 'SQ_THREAD_TRACE_MODE__MASK_VS_MASK', + 'SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT', + 'SQ_THREAD_TRACE_MODE__MODE_MASK', + 'SQ_THREAD_TRACE_MODE__MODE__SHIFT', + 'SQ_THREAD_TRACE_MODE__TC_PERF_EN_MASK', + 'SQ_THREAD_TRACE_MODE__TC_PERF_EN__SHIFT', + 'SQ_THREAD_TRACE_MODE__TEST_MODE_MASK', + 'SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT', + 'SQ_THREAD_TRACE_MODE__WRAP_MASK', + 'SQ_THREAD_TRACE_MODE__WRAP__SHIFT', + 'SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK', + 'SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT', + 'SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK', + 'SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT', + 'SQ_THREAD_TRACE_SIZE__SIZE_MASK', + 'SQ_THREAD_TRACE_SIZE__SIZE__SHIFT', + 'SQ_THREAD_TRACE_STATUS__BUSY_MASK', + 'SQ_THREAD_TRACE_STATUS__BUSY__SHIFT', + 'SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK', + 'SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT', + 'SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK', + 'SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT', + 'SQ_THREAD_TRACE_STATUS__FULL_MASK', + 'SQ_THREAD_TRACE_STATUS__FULL__SHIFT', + 'SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK', + 'SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT', + 'SQ_THREAD_TRACE_STATUS__UTC_ERROR_MASK', + 'SQ_THREAD_TRACE_STATUS__UTC_ERROR__SHIFT', + 'SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK', + 'SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT', + 'SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK', + 'SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT', + 'SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK', + 'SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT', + 'SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK', + 'SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT', + 'SQ_THREAD_TRACE_USERDATA_0__DATA_MASK', + 'SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT', + 'SQ_THREAD_TRACE_USERDATA_1__DATA_MASK', + 'SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT', + 'SQ_THREAD_TRACE_USERDATA_2__DATA_MASK', + 'SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT', + 'SQ_THREAD_TRACE_USERDATA_3__DATA_MASK', + 'SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT', + 'SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK', + 'SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT', + 'SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK', + 'SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT', + 'SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK', + 'SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT', + 'SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK', + 'SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK', + 'SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT', + 'SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK', + 'SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT', + 'SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK', + 'SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT', + 'SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK', + 'SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT', + 'SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK', + 'SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK', + 'SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT', + 'SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK', + 'SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT', + 'SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK', + 'SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT', + 'SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK', + 'SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK', + 'SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT', + 'SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK', + 'SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK', + 'SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT', + 'SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__PRIV_MASK', + 'SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__PRIV__SHIFT', + 'SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK', + 'SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK', + 'SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT', + 'SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK', + 'SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT', + 'SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK', + 'SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK', + 'SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT', + 'SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK', + 'SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT', + 'SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK', + 'SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK', + 'SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT', + 'SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK', + 'SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT', + 'SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK', + 'SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK', + 'SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT', + 'SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK', + 'SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT', + 'SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK', + 'SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT', + 'SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK', + 'SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT', + 'SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK', + 'SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT', + 'SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK', + 'SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT', + 'SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK', + 'SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT', + 'SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK', + 'SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT', + 'SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK', + 'SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT', + 'SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK', + 'SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT', + 'SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK', + 'SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK', + 'SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT', + 'SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK', + 'SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT', + 'SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK', + 'SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT', + 'SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK', + 'SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK', + 'SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT', + 'SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK', + 'SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT', + 'SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK', + 'SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT', + 'SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK', + 'SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT', + 'SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK', + 'SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT', + 'SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK', + 'SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK', + 'SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK', + 'SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT', + 'SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK', + 'SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT', + 'SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK', + 'SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT', + 'SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK', + 'SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT', + 'SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK', + 'SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT', + 'SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK', + 'SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK', + 'SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK', + 'SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT', + 'SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK', + 'SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT', + 'SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK', + 'SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT', + 'SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK', + 'SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT', + 'SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK', + 'SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT', + 'SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK', + 'SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT', + 'SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK', + 'SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT', + 'SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK', + 'SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT', + 'SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK', + 'SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT', + 'SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK', + 'SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK', + 'SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK', + 'SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT', + 'SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK', + 'SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT', + 'SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK', + 'SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT', + 'SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK', + 'SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT', + 'SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK', + 'SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT', + 'SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK', + 'SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT', + 'SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK', + 'SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT', + 'SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK', + 'SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT', + 'SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK', + 'SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK', + 'SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT', + 'SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK', + 'SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK', + 'SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK', + 'SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK', + 'SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT', + 'SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK', + 'SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT', + 'SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK', + 'SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT', + 'SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK', + 'SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK', + 'SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK', + 'SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK', + 'SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT', + 'SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK', + 'SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT', + 'SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK', + 'SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT', + 'SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK', + 'SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT', + 'SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK', + 'SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT', + 'SQ_THREAD_TRACE_WPTR__WPTR_MASK', + 'SQ_THREAD_TRACE_WPTR__WPTR__SHIFT', + 'SQ_TIMEOUT_CONFIG__PERIOD_SEL_MASK', + 'SQ_TIMEOUT_CONFIG__PERIOD_SEL__SHIFT', + 'SQ_TIMEOUT_CONFIG__TIMEOUT_CONDITIONS_MASK_MASK', + 'SQ_TIMEOUT_CONFIG__TIMEOUT_CONDITIONS_MASK__SHIFT', + 'SQ_TIMEOUT_CONFIG__TIMEOUT_FATAL_DISABLE_MASK', + 'SQ_TIMEOUT_CONFIG__TIMEOUT_FATAL_DISABLE__SHIFT', + 'SQ_TIMEOUT_CONFIG__TIMER_LONGER_SEL_MASK', + 'SQ_TIMEOUT_CONFIG__TIMER_LONGER_SEL__SHIFT', + 'SQ_TIMEOUT_STATUS__WAVE_TIMEOUT_MASK', + 'SQ_TIMEOUT_STATUS__WAVE_TIMEOUT__SHIFT', 'SQ_TIME_HI__TIME_MASK', + 'SQ_TIME_HI__TIME__SHIFT', 'SQ_TIME_LO__TIME_MASK', + 'SQ_TIME_LO__TIME__SHIFT', 'SQ_UE_ERR_STATUS_HI__ECC_MASK', + 'SQ_UE_ERR_STATUS_HI__ECC__SHIFT', + 'SQ_UE_ERR_STATUS_HI__ERR_INFO_MASK', + 'SQ_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'SQ_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'SQ_UE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'SQ_UE_ERR_STATUS_HI__FED_CNT_MASK', + 'SQ_UE_ERR_STATUS_HI__FED_CNT__SHIFT', + 'SQ_UE_ERR_STATUS_HI__PARITY_MASK', + 'SQ_UE_ERR_STATUS_HI__PARITY__SHIFT', + 'SQ_UE_ERR_STATUS_HI__RESERVED_MASK', + 'SQ_UE_ERR_STATUS_HI__RESERVED__SHIFT', + 'SQ_UE_ERR_STATUS_HI__UE_CNT_MASK', + 'SQ_UE_ERR_STATUS_HI__UE_CNT__SHIFT', + 'SQ_UE_ERR_STATUS_LO__ADDRESS_MASK', + 'SQ_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'SQ_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'SQ_UE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'SQ_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'SQ_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'SQ_UE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'SQ_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'SQ_UTCL1_CNTL1__CLIENTID_MASK', + 'SQ_UTCL1_CNTL1__CLIENTID__SHIFT', + 'SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK', + 'SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT', + 'SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK', + 'SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT', + 'SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK', + 'SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT', + 'SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK', + 'SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT', + 'SQ_UTCL1_CNTL1__FORCE_MISS_MASK', + 'SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT', + 'SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK', + 'SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT', + 'SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK', + 'SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT', + 'SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK', + 'SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT', + 'SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK', + 'SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT', + 'SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK', + 'SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK', + 'SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT', + 'SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT', + 'SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK', + 'SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT', + 'SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK', + 'SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT', + 'SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK', + 'SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT', + 'SQ_UTCL1_CNTL1__RESP_MODE_MASK', + 'SQ_UTCL1_CNTL1__RESP_MODE__SHIFT', + 'SQ_UTCL1_CNTL1__USERVM_DIS_MASK', + 'SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT', + 'SQ_UTCL1_CNTL2__DIS_EDC_MASK', 'SQ_UTCL1_CNTL2__DIS_EDC__SHIFT', + 'SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK', + 'SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT', + 'SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK', + 'SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT', + 'SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK', + 'SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT', + 'SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK', + 'SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT', + 'SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK', + 'SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT', + 'SQ_UTCL1_CNTL2__LINE_VALID_MASK', + 'SQ_UTCL1_CNTL2__LINE_VALID__SHIFT', + 'SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK', + 'SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT', + 'SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK', + 'SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT', + 'SQ_UTCL1_CNTL2__RETRY_TIMER_MASK', + 'SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT', + 'SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK', + 'SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT', + 'SQ_UTCL1_CNTL2__SPARE_MASK', 'SQ_UTCL1_CNTL2__SPARE__SHIFT', + 'SQ_UTCL1_STATUS__FAULT_DETECTED_MASK', + 'SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT', + 'SQ_UTCL1_STATUS__PRT_DETECTED_MASK', + 'SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT', + 'SQ_UTCL1_STATUS__RESERVED_MASK', + 'SQ_UTCL1_STATUS__RESERVED__SHIFT', + 'SQ_UTCL1_STATUS__RETRY_DETECTED_MASK', + 'SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT', + 'SQ_UTCL1_STATUS__UNUSED_MASK', 'SQ_UTCL1_STATUS__UNUSED__SHIFT', + 'SQ_VINTRP__ATTRCHAN_MASK', 'SQ_VINTRP__ATTRCHAN__SHIFT', + 'SQ_VINTRP__ATTR_MASK', 'SQ_VINTRP__ATTR__SHIFT', + 'SQ_VINTRP__ENCODING_MASK', 'SQ_VINTRP__ENCODING__SHIFT', + 'SQ_VINTRP__OP_MASK', 'SQ_VINTRP__OP__SHIFT', + 'SQ_VINTRP__VDST_MASK', 'SQ_VINTRP__VDST__SHIFT', + 'SQ_VINTRP__VSRC_MASK', 'SQ_VINTRP__VSRC__SHIFT', + 'SQ_VOP1__ENCODING_MASK', 'SQ_VOP1__ENCODING__SHIFT', + 'SQ_VOP1__OP_MASK', 'SQ_VOP1__OP__SHIFT', 'SQ_VOP1__SRC0_MASK', + 'SQ_VOP1__SRC0__SHIFT', 'SQ_VOP1__VDST_MASK', + 'SQ_VOP1__VDST__SHIFT', 'SQ_VOP2__ENCODING_MASK', + 'SQ_VOP2__ENCODING__SHIFT', 'SQ_VOP2__OP_MASK', + 'SQ_VOP2__OP__SHIFT', 'SQ_VOP2__SRC0_MASK', + 'SQ_VOP2__SRC0__SHIFT', 'SQ_VOP2__VDST_MASK', + 'SQ_VOP2__VDST__SHIFT', 'SQ_VOP2__VSRC1_MASK', + 'SQ_VOP2__VSRC1__SHIFT', 'SQ_VOP3P_0__CLAMP_MASK', + 'SQ_VOP3P_0__CLAMP__SHIFT', 'SQ_VOP3P_0__ENCODING_MASK', + 'SQ_VOP3P_0__ENCODING__SHIFT', 'SQ_VOP3P_0__NEG_HI_MASK', + 'SQ_VOP3P_0__NEG_HI__SHIFT', 'SQ_VOP3P_0__OP_MASK', + 'SQ_VOP3P_0__OP_SEL_HI_2_MASK', 'SQ_VOP3P_0__OP_SEL_HI_2__SHIFT', + 'SQ_VOP3P_0__OP_SEL_MASK', 'SQ_VOP3P_0__OP_SEL__SHIFT', + 'SQ_VOP3P_0__OP__SHIFT', 'SQ_VOP3P_0__VDST_MASK', + 'SQ_VOP3P_0__VDST__SHIFT', 'SQ_VOP3P_1__NEG_MASK', + 'SQ_VOP3P_1__NEG__SHIFT', 'SQ_VOP3P_1__OP_SEL_HI_MASK', + 'SQ_VOP3P_1__OP_SEL_HI__SHIFT', 'SQ_VOP3P_1__SRC0_MASK', + 'SQ_VOP3P_1__SRC0__SHIFT', 'SQ_VOP3P_1__SRC1_MASK', + 'SQ_VOP3P_1__SRC1__SHIFT', 'SQ_VOP3P_1__SRC2_MASK', + 'SQ_VOP3P_1__SRC2__SHIFT', 'SQ_VOP3P_MFMA_0__ABID_MASK', + 'SQ_VOP3P_MFMA_0__ABID__SHIFT', 'SQ_VOP3P_MFMA_0__ACC_CD_MASK', + 'SQ_VOP3P_MFMA_0__ACC_CD__SHIFT', 'SQ_VOP3P_MFMA_0__CBSZ_MASK', + 'SQ_VOP3P_MFMA_0__CBSZ__SHIFT', 'SQ_VOP3P_MFMA_0__ENCODING_MASK', + 'SQ_VOP3P_MFMA_0__ENCODING__SHIFT', 'SQ_VOP3P_MFMA_0__OP_MASK', + 'SQ_VOP3P_MFMA_0__OP__SHIFT', 'SQ_VOP3P_MFMA_0__VDST_MASK', + 'SQ_VOP3P_MFMA_0__VDST__SHIFT', 'SQ_VOP3P_MFMA_1__ACC_MASK', + 'SQ_VOP3P_MFMA_1__ACC__SHIFT', 'SQ_VOP3P_MFMA_1__BLGP_MASK', + 'SQ_VOP3P_MFMA_1__BLGP__SHIFT', 'SQ_VOP3P_MFMA_1__SRC0_MASK', + 'SQ_VOP3P_MFMA_1__SRC0__SHIFT', 'SQ_VOP3P_MFMA_1__SRC1_MASK', + 'SQ_VOP3P_MFMA_1__SRC1__SHIFT', 'SQ_VOP3P_MFMA_1__SRC2_MASK', + 'SQ_VOP3P_MFMA_1__SRC2__SHIFT', 'SQ_VOP3_0_SDST_ENC__CLAMP_MASK', + 'SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT', + 'SQ_VOP3_0_SDST_ENC__ENCODING_MASK', + 'SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT', + 'SQ_VOP3_0_SDST_ENC__OP_MASK', 'SQ_VOP3_0_SDST_ENC__OP__SHIFT', + 'SQ_VOP3_0_SDST_ENC__SDST_MASK', + 'SQ_VOP3_0_SDST_ENC__SDST__SHIFT', + 'SQ_VOP3_0_SDST_ENC__VDST_MASK', + 'SQ_VOP3_0_SDST_ENC__VDST__SHIFT', 'SQ_VOP3_0__ABS_MASK', + 'SQ_VOP3_0__ABS__SHIFT', 'SQ_VOP3_0__CLAMP_MASK', + 'SQ_VOP3_0__CLAMP__SHIFT', 'SQ_VOP3_0__ENCODING_MASK', + 'SQ_VOP3_0__ENCODING__SHIFT', 'SQ_VOP3_0__OP_MASK', + 'SQ_VOP3_0__OP_SEL_MASK', 'SQ_VOP3_0__OP_SEL__SHIFT', + 'SQ_VOP3_0__OP__SHIFT', 'SQ_VOP3_0__VDST_MASK', + 'SQ_VOP3_0__VDST__SHIFT', 'SQ_VOP3_1__NEG_MASK', + 'SQ_VOP3_1__NEG__SHIFT', 'SQ_VOP3_1__OMOD_MASK', + 'SQ_VOP3_1__OMOD__SHIFT', 'SQ_VOP3_1__SRC0_MASK', + 'SQ_VOP3_1__SRC0__SHIFT', 'SQ_VOP3_1__SRC1_MASK', + 'SQ_VOP3_1__SRC1__SHIFT', 'SQ_VOP3_1__SRC2_MASK', + 'SQ_VOP3_1__SRC2__SHIFT', 'SQ_VOPC__ENCODING_MASK', + 'SQ_VOPC__ENCODING__SHIFT', 'SQ_VOPC__OP_MASK', + 'SQ_VOPC__OP__SHIFT', 'SQ_VOPC__SRC0_MASK', + 'SQ_VOPC__SRC0__SHIFT', 'SQ_VOPC__VSRC1_MASK', + 'SQ_VOPC__VSRC1__SHIFT', 'SQ_VOP_DPP__BANK_MASK_MASK', + 'SQ_VOP_DPP__BANK_MASK__SHIFT', 'SQ_VOP_DPP__BOUND_CTRL_MASK', + 'SQ_VOP_DPP__BOUND_CTRL__SHIFT', 'SQ_VOP_DPP__DPP_CTRL_MASK', + 'SQ_VOP_DPP__DPP_CTRL__SHIFT', 'SQ_VOP_DPP__ROW_MASK_MASK', + 'SQ_VOP_DPP__ROW_MASK__SHIFT', 'SQ_VOP_DPP__SRC0_ABS_MASK', + 'SQ_VOP_DPP__SRC0_ABS__SHIFT', 'SQ_VOP_DPP__SRC0_MASK', + 'SQ_VOP_DPP__SRC0_NEG_MASK', 'SQ_VOP_DPP__SRC0_NEG__SHIFT', + 'SQ_VOP_DPP__SRC0__SHIFT', 'SQ_VOP_DPP__SRC1_ABS_MASK', + 'SQ_VOP_DPP__SRC1_ABS__SHIFT', 'SQ_VOP_DPP__SRC1_NEG_MASK', + 'SQ_VOP_DPP__SRC1_NEG__SHIFT', 'SQ_VOP_SDWA_SDST_ENC__S0_MASK', + 'SQ_VOP_SDWA_SDST_ENC__S0__SHIFT', + 'SQ_VOP_SDWA_SDST_ENC__S1_MASK', + 'SQ_VOP_SDWA_SDST_ENC__S1__SHIFT', + 'SQ_VOP_SDWA_SDST_ENC__SDST_MASK', + 'SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT', + 'SQ_VOP_SDWA_SDST_ENC__SD_MASK', + 'SQ_VOP_SDWA_SDST_ENC__SD__SHIFT', + 'SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK', + 'SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT', + 'SQ_VOP_SDWA_SDST_ENC__SRC0_MASK', + 'SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK', + 'SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT', + 'SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK', + 'SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT', + 'SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK', + 'SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT', + 'SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT', + 'SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK', + 'SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT', + 'SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK', + 'SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT', + 'SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK', + 'SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT', + 'SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK', + 'SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT', + 'SQ_VOP_SDWA__CLAMP_MASK', 'SQ_VOP_SDWA__CLAMP__SHIFT', + 'SQ_VOP_SDWA__DST_SEL_MASK', 'SQ_VOP_SDWA__DST_SEL__SHIFT', + 'SQ_VOP_SDWA__DST_UNUSED_MASK', 'SQ_VOP_SDWA__DST_UNUSED__SHIFT', + 'SQ_VOP_SDWA__OMOD_MASK', 'SQ_VOP_SDWA__OMOD__SHIFT', + 'SQ_VOP_SDWA__S0_MASK', 'SQ_VOP_SDWA__S0__SHIFT', + 'SQ_VOP_SDWA__S1_MASK', 'SQ_VOP_SDWA__S1__SHIFT', + 'SQ_VOP_SDWA__SRC0_ABS_MASK', 'SQ_VOP_SDWA__SRC0_ABS__SHIFT', + 'SQ_VOP_SDWA__SRC0_MASK', 'SQ_VOP_SDWA__SRC0_NEG_MASK', + 'SQ_VOP_SDWA__SRC0_NEG__SHIFT', 'SQ_VOP_SDWA__SRC0_SEL_MASK', + 'SQ_VOP_SDWA__SRC0_SEL__SHIFT', 'SQ_VOP_SDWA__SRC0_SEXT_MASK', + 'SQ_VOP_SDWA__SRC0_SEXT__SHIFT', 'SQ_VOP_SDWA__SRC0__SHIFT', + 'SQ_VOP_SDWA__SRC1_ABS_MASK', 'SQ_VOP_SDWA__SRC1_ABS__SHIFT', + 'SQ_VOP_SDWA__SRC1_NEG_MASK', 'SQ_VOP_SDWA__SRC1_NEG__SHIFT', + 'SQ_VOP_SDWA__SRC1_SEL_MASK', 'SQ_VOP_SDWA__SRC1_SEL__SHIFT', + 'SQ_VOP_SDWA__SRC1_SEXT_MASK', 'SQ_VOP_SDWA__SRC1_SEXT__SHIFT', + 'SQ_WAVE_EXEC_HI__EXEC_HI_MASK', + 'SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT', + 'SQ_WAVE_EXEC_LO__EXEC_LO_MASK', + 'SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT', + 'SQ_WAVE_FLUSH_IB__UNUSED_MASK', + 'SQ_WAVE_FLUSH_IB__UNUSED__SHIFT', + 'SQ_WAVE_GPR_ALLOC__ACCV_OFFSET_MASK', + 'SQ_WAVE_GPR_ALLOC__ACCV_OFFSET__SHIFT', + 'SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK', + 'SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT', + 'SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK', + 'SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT', + 'SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK', + 'SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT', + 'SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK', + 'SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT', + 'SQ_WAVE_HW_ID__CU_ID_MASK', 'SQ_WAVE_HW_ID__CU_ID__SHIFT', + 'SQ_WAVE_HW_ID__ME_ID_MASK', 'SQ_WAVE_HW_ID__ME_ID__SHIFT', + 'SQ_WAVE_HW_ID__PIPE_ID_MASK', 'SQ_WAVE_HW_ID__PIPE_ID__SHIFT', + 'SQ_WAVE_HW_ID__QUEUE_ID_MASK', 'SQ_WAVE_HW_ID__QUEUE_ID__SHIFT', + 'SQ_WAVE_HW_ID__SE_ID_MASK', 'SQ_WAVE_HW_ID__SE_ID__SHIFT', + 'SQ_WAVE_HW_ID__SH_ID_MASK', 'SQ_WAVE_HW_ID__SH_ID__SHIFT', + 'SQ_WAVE_HW_ID__SIMD_ID_MASK', 'SQ_WAVE_HW_ID__SIMD_ID__SHIFT', + 'SQ_WAVE_HW_ID__STATE_ID_MASK', 'SQ_WAVE_HW_ID__STATE_ID__SHIFT', + 'SQ_WAVE_HW_ID__TG_ID_MASK', 'SQ_WAVE_HW_ID__TG_ID__SHIFT', + 'SQ_WAVE_HW_ID__VM_ID_MASK', 'SQ_WAVE_HW_ID__VM_ID__SHIFT', + 'SQ_WAVE_HW_ID__WAVE_ID_MASK', 'SQ_WAVE_HW_ID__WAVE_ID__SHIFT', + 'SQ_WAVE_IB_DBG0__ECC_ST_MASK', 'SQ_WAVE_IB_DBG0__ECC_ST__SHIFT', + 'SQ_WAVE_IB_DBG0__HYB_CNT_MASK', + 'SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT', + 'SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK', + 'SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT', + 'SQ_WAVE_IB_DBG0__IBUF_ST_MASK', + 'SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT', + 'SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK', + 'SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT', + 'SQ_WAVE_IB_DBG0__INST_STR_ST_MASK', + 'SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT', + 'SQ_WAVE_IB_DBG0__IS_HYB_MASK', 'SQ_WAVE_IB_DBG0__IS_HYB__SHIFT', + 'SQ_WAVE_IB_DBG0__KILL_MASK', 'SQ_WAVE_IB_DBG0__KILL__SHIFT', + 'SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK', + 'SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT', + 'SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK', + 'SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT', + 'SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI_MASK', + 'SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI__SHIFT', + 'SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK', + 'SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT', + 'SQ_WAVE_IB_DBG0__PC_INVALID_MASK', + 'SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT', + 'SQ_WAVE_IB_DBG1__IXNACK_MASK', 'SQ_WAVE_IB_DBG1__IXNACK__SHIFT', + 'SQ_WAVE_IB_DBG1__MISC_CNT_MASK', + 'SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT', 'SQ_WAVE_IB_DBG1__QCNT_MASK', + 'SQ_WAVE_IB_DBG1__QCNT__SHIFT', 'SQ_WAVE_IB_DBG1__RCNT_MASK', + 'SQ_WAVE_IB_DBG1__RCNT__SHIFT', + 'SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK', + 'SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT', + 'SQ_WAVE_IB_DBG1__XCNT_MASK', 'SQ_WAVE_IB_DBG1__XCNT__SHIFT', + 'SQ_WAVE_IB_DBG1__XNACK_MASK', 'SQ_WAVE_IB_DBG1__XNACK__SHIFT', + 'SQ_WAVE_IB_STS__EXP_CNT_MASK', 'SQ_WAVE_IB_STS__EXP_CNT__SHIFT', + 'SQ_WAVE_IB_STS__FIRST_REPLAY_MASK', + 'SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT', + 'SQ_WAVE_IB_STS__LGKM_CNT_MASK', + 'SQ_WAVE_IB_STS__LGKM_CNT__SHIFT', 'SQ_WAVE_IB_STS__RCNT_MASK', + 'SQ_WAVE_IB_STS__RCNT__SHIFT', 'SQ_WAVE_IB_STS__VALU_CNT_MASK', + 'SQ_WAVE_IB_STS__VALU_CNT__SHIFT', + 'SQ_WAVE_IB_STS__VM_CNT_HI_MASK', + 'SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT', 'SQ_WAVE_IB_STS__VM_CNT_MASK', + 'SQ_WAVE_IB_STS__VM_CNT__SHIFT', + 'SQ_WAVE_INST_DW0__INST_DW0_MASK', + 'SQ_WAVE_INST_DW0__INST_DW0__SHIFT', + 'SQ_WAVE_INST_DW1__INST_DW1_MASK', + 'SQ_WAVE_INST_DW1__INST_DW1__SHIFT', + 'SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK', + 'SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT', + 'SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK', + 'SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT', 'SQ_WAVE_M0__M0_MASK', + 'SQ_WAVE_M0__M0__SHIFT', 'SQ_WAVE_MODE__CSP_MASK', + 'SQ_WAVE_MODE__CSP__SHIFT', 'SQ_WAVE_MODE__DEBUG_EN_MASK', + 'SQ_WAVE_MODE__DEBUG_EN__SHIFT', + 'SQ_WAVE_MODE__DISABLE_PERF_MASK', + 'SQ_WAVE_MODE__DISABLE_PERF__SHIFT', + 'SQ_WAVE_MODE__DX10_CLAMP_MASK', + 'SQ_WAVE_MODE__DX10_CLAMP__SHIFT', 'SQ_WAVE_MODE__EXCP_EN_MASK', + 'SQ_WAVE_MODE__EXCP_EN__SHIFT', 'SQ_WAVE_MODE__FP16_OVFL_MASK', + 'SQ_WAVE_MODE__FP16_OVFL__SHIFT', 'SQ_WAVE_MODE__FP_DENORM_MASK', + 'SQ_WAVE_MODE__FP_DENORM__SHIFT', 'SQ_WAVE_MODE__FP_ROUND_MASK', + 'SQ_WAVE_MODE__FP_ROUND__SHIFT', 'SQ_WAVE_MODE__GPR_IDX_EN_MASK', + 'SQ_WAVE_MODE__GPR_IDX_EN__SHIFT', 'SQ_WAVE_MODE__IEEE_MASK', + 'SQ_WAVE_MODE__IEEE__SHIFT', 'SQ_WAVE_MODE__LOD_CLAMPED_MASK', + 'SQ_WAVE_MODE__LOD_CLAMPED__SHIFT', + 'SQ_WAVE_MODE__POPS_PACKER0_MASK', + 'SQ_WAVE_MODE__POPS_PACKER0__SHIFT', + 'SQ_WAVE_MODE__POPS_PACKER1_MASK', + 'SQ_WAVE_MODE__POPS_PACKER1__SHIFT', 'SQ_WAVE_MODE__VSKIP_MASK', + 'SQ_WAVE_MODE__VSKIP__SHIFT', 'SQ_WAVE_PC_HI__PC_HI_MASK', + 'SQ_WAVE_PC_HI__PC_HI__SHIFT', 'SQ_WAVE_PC_LO__PC_LO_MASK', + 'SQ_WAVE_PC_LO__PC_LO__SHIFT', + 'SQ_WAVE_STATUS__ALLOW_REPLAY_MASK', + 'SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT', + 'SQ_WAVE_STATUS__COND_DBG_SYS_MASK', + 'SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT', + 'SQ_WAVE_STATUS__COND_DBG_USER_MASK', + 'SQ_WAVE_STATUS__COND_DBG_USER__SHIFT', + 'SQ_WAVE_STATUS__ECC_ERR_MASK', 'SQ_WAVE_STATUS__ECC_ERR__SHIFT', + 'SQ_WAVE_STATUS__EXECZ_MASK', 'SQ_WAVE_STATUS__EXECZ__SHIFT', + 'SQ_WAVE_STATUS__EXPORT_RDY_MASK', + 'SQ_WAVE_STATUS__EXPORT_RDY__SHIFT', + 'SQ_WAVE_STATUS__FATAL_HALT_MASK', + 'SQ_WAVE_STATUS__FATAL_HALT__SHIFT', 'SQ_WAVE_STATUS__HALT_MASK', + 'SQ_WAVE_STATUS__HALT__SHIFT', 'SQ_WAVE_STATUS__IDLE_MASK', + 'SQ_WAVE_STATUS__IDLE__SHIFT', 'SQ_WAVE_STATUS__IN_BARRIER_MASK', + 'SQ_WAVE_STATUS__IN_BARRIER__SHIFT', 'SQ_WAVE_STATUS__IN_TG_MASK', + 'SQ_WAVE_STATUS__IN_TG__SHIFT', + 'SQ_WAVE_STATUS__MUST_EXPORT_MASK', + 'SQ_WAVE_STATUS__MUST_EXPORT__SHIFT', + 'SQ_WAVE_STATUS__PERF_EN_MASK', 'SQ_WAVE_STATUS__PERF_EN__SHIFT', + 'SQ_WAVE_STATUS__PRIV_MASK', 'SQ_WAVE_STATUS__PRIV__SHIFT', + 'SQ_WAVE_STATUS__SCC_MASK', 'SQ_WAVE_STATUS__SCC__SHIFT', + 'SQ_WAVE_STATUS__SCRATCH_EN_MASK', + 'SQ_WAVE_STATUS__SCRATCH_EN__SHIFT', + 'SQ_WAVE_STATUS__SKIP_EXPORT_MASK', + 'SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT', + 'SQ_WAVE_STATUS__SPI_PRIO_MASK', + 'SQ_WAVE_STATUS__SPI_PRIO__SHIFT', 'SQ_WAVE_STATUS__TRAP_EN_MASK', + 'SQ_WAVE_STATUS__TRAP_EN__SHIFT', 'SQ_WAVE_STATUS__TRAP_MASK', + 'SQ_WAVE_STATUS__TRAP__SHIFT', + 'SQ_WAVE_STATUS__TTRACE_CU_EN_MASK', + 'SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT', + 'SQ_WAVE_STATUS__TTRACE_EN_MASK', + 'SQ_WAVE_STATUS__TTRACE_EN__SHIFT', + 'SQ_WAVE_STATUS__USER_PRIO_MASK', + 'SQ_WAVE_STATUS__USER_PRIO__SHIFT', 'SQ_WAVE_STATUS__VALID_MASK', + 'SQ_WAVE_STATUS__VALID__SHIFT', 'SQ_WAVE_STATUS__VCCZ_MASK', + 'SQ_WAVE_STATUS__VCCZ__SHIFT', 'SQ_WAVE_TRAPSTS__DP_RATE_MASK', + 'SQ_WAVE_TRAPSTS__DP_RATE__SHIFT', + 'SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK', + 'SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT', + 'SQ_WAVE_TRAPSTS__EXCP_HI_MASK', + 'SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT', 'SQ_WAVE_TRAPSTS__EXCP_MASK', + 'SQ_WAVE_TRAPSTS__EXCP__SHIFT', 'SQ_WAVE_TRAPSTS__HOST_TRAP_MASK', + 'SQ_WAVE_TRAPSTS__HOST_TRAP__SHIFT', + 'SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK', + 'SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT', + 'SQ_WAVE_TRAPSTS__PERF_SNAPSHOT_MASK', + 'SQ_WAVE_TRAPSTS__PERF_SNAPSHOT__SHIFT', + 'SQ_WAVE_TRAPSTS__SAVECTX_MASK', + 'SQ_WAVE_TRAPSTS__SAVECTX__SHIFT', + 'SQ_WAVE_TRAPSTS__TRAP_AFTER_INST_MASK', + 'SQ_WAVE_TRAPSTS__TRAP_AFTER_INST__SHIFT', + 'SQ_WAVE_TRAPSTS__WAVE_END_MASK', + 'SQ_WAVE_TRAPSTS__WAVE_END__SHIFT', + 'SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK', + 'SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT', 'SQ_WAVE_TTMP0__DATA_MASK', + 'SQ_WAVE_TTMP0__DATA__SHIFT', 'SQ_WAVE_TTMP10__DATA_MASK', + 'SQ_WAVE_TTMP10__DATA__SHIFT', 'SQ_WAVE_TTMP11__DATA_MASK', + 'SQ_WAVE_TTMP11__DATA__SHIFT', 'SQ_WAVE_TTMP12__DATA_MASK', + 'SQ_WAVE_TTMP12__DATA__SHIFT', 'SQ_WAVE_TTMP13__DATA_MASK', + 'SQ_WAVE_TTMP13__DATA__SHIFT', 'SQ_WAVE_TTMP14__DATA_MASK', + 'SQ_WAVE_TTMP14__DATA__SHIFT', 'SQ_WAVE_TTMP15__DATA_MASK', + 'SQ_WAVE_TTMP15__DATA__SHIFT', 'SQ_WAVE_TTMP1__DATA_MASK', + 'SQ_WAVE_TTMP1__DATA__SHIFT', 'SQ_WAVE_TTMP2__DATA_MASK', + 'SQ_WAVE_TTMP2__DATA__SHIFT', 'SQ_WAVE_TTMP3__DATA_MASK', + 'SQ_WAVE_TTMP3__DATA__SHIFT', 'SQ_WAVE_TTMP4__DATA_MASK', + 'SQ_WAVE_TTMP4__DATA__SHIFT', 'SQ_WAVE_TTMP5__DATA_MASK', + 'SQ_WAVE_TTMP5__DATA__SHIFT', 'SQ_WAVE_TTMP6__DATA_MASK', + 'SQ_WAVE_TTMP6__DATA__SHIFT', 'SQ_WAVE_TTMP7__DATA_MASK', + 'SQ_WAVE_TTMP7__DATA__SHIFT', 'SQ_WAVE_TTMP8__DATA_MASK', + 'SQ_WAVE_TTMP8__DATA__SHIFT', 'SQ_WAVE_TTMP9__DATA_MASK', + 'SQ_WAVE_TTMP9__DATA__SHIFT', + 'SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT_MASK', + 'SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT__SHIFT', + 'SQ_WREXEC_EXEC_HI__ADDR_HI_MASK', + 'SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT', + 'SQ_WREXEC_EXEC_HI__ATC_MASK', 'SQ_WREXEC_EXEC_HI__ATC__SHIFT', + 'SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK', + 'SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT', + 'SQ_WREXEC_EXEC_HI__MSB_MASK', 'SQ_WREXEC_EXEC_HI__MSB__SHIFT', + 'SQ_WREXEC_EXEC_HI__MTYPE_MASK', + 'SQ_WREXEC_EXEC_HI__MTYPE__SHIFT', + 'SQ_WREXEC_EXEC_LO__ADDR_LO_MASK', + 'SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT', + 'SX_DEBUG_1__DISABLE_REP_FGCG_MASK', + 'SX_DEBUG_1__DISABLE_REP_FGCG__SHIFT', + 'SX_DEBUG_1__RESERVED_MASK', 'SX_DEBUG_1__RESERVED__SHIFT', + 'SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK', + 'SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT', + 'SX_DEBUG_BUSY__PCCMD_VALID_MASK', + 'SX_DEBUG_BUSY__PCCMD_VALID__SHIFT', + 'SX_DEBUG_BUSY__PCDATA_VALID_MASK', + 'SX_DEBUG_BUSY__PCDATA_VALID__SHIFT', + 'SX_DEBUG_BUSY__RESERVED_MASK', 'SX_DEBUG_BUSY__RESERVED__SHIFT', + 'SX_DEBUG_BUSY__VDATA0_VALID_MASK', + 'SX_DEBUG_BUSY__VDATA0_VALID__SHIFT', + 'SX_DEBUG_BUSY__VDATA1_VALID_MASK', + 'SX_DEBUG_BUSY__VDATA1_VALID__SHIFT', + 'SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'SX_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'SX_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'SX_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'SX_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'SX_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'SX_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'SX_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'SX_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'SX_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'SX_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'SX_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'SX_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'SX_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'SX_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'SX_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'SX_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'SX_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'SX_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'SX_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'SX_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'SX_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'SX_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'SX_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'SX_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'SX_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'SX_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'SX_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'SX_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'SX_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'SX_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'SX_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'SX_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'SX_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'SX_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'SX_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'SX_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'SX_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'SX_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'TA_CE_EDC_HI__CE_CNT_MASK', 'TA_CE_EDC_HI__CE_CNT__SHIFT', + 'TA_CE_EDC_HI__ECC_MASK', 'TA_CE_EDC_HI__ECC__SHIFT', + 'TA_CE_EDC_HI__ERR_INFO_MASK', + 'TA_CE_EDC_HI__ERR_INFO_VALID_FLAG_MASK', + 'TA_CE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'TA_CE_EDC_HI__ERR_INFO__SHIFT', 'TA_CE_EDC_HI__POISON_MASK', + 'TA_CE_EDC_HI__POISON__SHIFT', + 'TA_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK', + 'TA_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT', + 'TA_CE_EDC_LO__ADDRESS_MASK', 'TA_CE_EDC_LO__ADDRESS__SHIFT', + 'TA_CE_EDC_LO__MEM_ID_MASK', 'TA_CE_EDC_LO__MEM_ID__SHIFT', + 'TA_CE_EDC_LO__STATUS_VALID_FLAG_MASK', + 'TA_CE_EDC_LO__STATUS_VALID_FLAG__SHIFT', + 'TA_CGTT_CTRL__OFF_HYSTERESIS_MASK', + 'TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT', + 'TA_CGTT_CTRL__ON_DELAY_MASK', 'TA_CGTT_CTRL__ON_DELAY__SHIFT', + 'TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK', + 'TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT', + 'TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK', + 'TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT', + 'TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK', + 'TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT', + 'TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK', + 'TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT', + 'TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK', + 'TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT', + 'TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK', + 'TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT', + 'TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK', + 'TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT', + 'TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK', + 'TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT', + 'TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK', + 'TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT', + 'TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK', + 'TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT', + 'TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK', + 'TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT', + 'TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK', + 'TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT', + 'TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK', + 'TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT', + 'TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK', + 'TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT', + 'TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK', + 'TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT', + 'TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK', + 'TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT', + 'TA_CNTL_AUX__RESERVED_MASK', 'TA_CNTL_AUX__RESERVED__SHIFT', + 'TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK', + 'TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT', + 'TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK', + 'TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT', + 'TA_CNTL__ALIGNER_CREDIT_MASK', 'TA_CNTL__ALIGNER_CREDIT__SHIFT', + 'TA_CNTL__FX_XNACK_CREDIT_MASK', + 'TA_CNTL__FX_XNACK_CREDIT__SHIFT', + 'TA_CNTL__SQ_XNACK_CREDIT_MASK', + 'TA_CNTL__SQ_XNACK_CREDIT__SHIFT', 'TA_CNTL__TC_DATA_CREDIT_MASK', + 'TA_CNTL__TC_DATA_CREDIT__SHIFT', 'TA_CNTL__TD_FIFO_CREDIT_MASK', + 'TA_CNTL__TD_FIFO_CREDIT__SHIFT', + 'TA_DSM_CNTL2__TA_FS_AFIFO_HI_ENABLE_ERROR_INJECT_MASK', + 'TA_DSM_CNTL2__TA_FS_AFIFO_HI_ENABLE_ERROR_INJECT__SHIFT', + 'TA_DSM_CNTL2__TA_FS_AFIFO_HI_SELECT_INJECT_DELAY_MASK', + 'TA_DSM_CNTL2__TA_FS_AFIFO_HI_SELECT_INJECT_DELAY__SHIFT', + 'TA_DSM_CNTL2__TA_FS_AFIFO_LO_ENABLE_ERROR_INJECT_MASK', + 'TA_DSM_CNTL2__TA_FS_AFIFO_LO_ENABLE_ERROR_INJECT__SHIFT', + 'TA_DSM_CNTL2__TA_FS_AFIFO_LO_SELECT_INJECT_DELAY_MASK', + 'TA_DSM_CNTL2__TA_FS_AFIFO_LO_SELECT_INJECT_DELAY__SHIFT', + 'TA_DSM_CNTL2__TA_FS_CFIFO_ENABLE_ERROR_INJECT_MASK', + 'TA_DSM_CNTL2__TA_FS_CFIFO_ENABLE_ERROR_INJECT__SHIFT', + 'TA_DSM_CNTL2__TA_FS_CFIFO_SELECT_INJECT_DELAY_MASK', + 'TA_DSM_CNTL2__TA_FS_CFIFO_SELECT_INJECT_DELAY__SHIFT', + 'TA_DSM_CNTL2__TA_FS_DFIFO_ENABLE_ERROR_INJECT_MASK', + 'TA_DSM_CNTL2__TA_FS_DFIFO_ENABLE_ERROR_INJECT__SHIFT', + 'TA_DSM_CNTL2__TA_FS_DFIFO_SELECT_INJECT_DELAY_MASK', + 'TA_DSM_CNTL2__TA_FS_DFIFO_SELECT_INJECT_DELAY__SHIFT', + 'TA_DSM_CNTL2__TA_FX_LFIFO_ENABLE_ERROR_INJECT_MASK', + 'TA_DSM_CNTL2__TA_FX_LFIFO_ENABLE_ERROR_INJECT__SHIFT', + 'TA_DSM_CNTL2__TA_FX_LFIFO_SELECT_INJECT_DELAY_MASK', + 'TA_DSM_CNTL2__TA_FX_LFIFO_SELECT_INJECT_DELAY__SHIFT', + 'TA_DSM_CNTL2__TA_INJECT_DELAY_MASK', + 'TA_DSM_CNTL2__TA_INJECT_DELAY__SHIFT', + 'TA_DSM_CNTL__TA_FS_AFIFO_HI_DSM_IRRITATOR_DATA_MASK', + 'TA_DSM_CNTL__TA_FS_AFIFO_HI_DSM_IRRITATOR_DATA__SHIFT', + 'TA_DSM_CNTL__TA_FS_AFIFO_HI_ENABLE_SINGLE_WRITE_MASK', + 'TA_DSM_CNTL__TA_FS_AFIFO_HI_ENABLE_SINGLE_WRITE__SHIFT', + 'TA_DSM_CNTL__TA_FS_AFIFO_LO_DSM_IRRITATOR_DATA_MASK', + 'TA_DSM_CNTL__TA_FS_AFIFO_LO_DSM_IRRITATOR_DATA__SHIFT', + 'TA_DSM_CNTL__TA_FS_AFIFO_LO_ENABLE_SINGLE_WRITE_MASK', + 'TA_DSM_CNTL__TA_FS_AFIFO_LO_ENABLE_SINGLE_WRITE__SHIFT', + 'TA_DSM_CNTL__TA_FS_CFIFO_DSM_IRRITATOR_DATA_MASK', + 'TA_DSM_CNTL__TA_FS_CFIFO_DSM_IRRITATOR_DATA__SHIFT', + 'TA_DSM_CNTL__TA_FS_CFIFO_ENABLE_SINGLE_WRITE_MASK', + 'TA_DSM_CNTL__TA_FS_CFIFO_ENABLE_SINGLE_WRITE__SHIFT', + 'TA_DSM_CNTL__TA_FS_DFIFO_DSM_IRRITATOR_DATA_MASK', + 'TA_DSM_CNTL__TA_FS_DFIFO_DSM_IRRITATOR_DATA__SHIFT', + 'TA_DSM_CNTL__TA_FS_DFIFO_ENABLE_SINGLE_WRITE_MASK', + 'TA_DSM_CNTL__TA_FS_DFIFO_ENABLE_SINGLE_WRITE__SHIFT', + 'TA_DSM_CNTL__TA_FX_LFIFO_DSM_IRRITATOR_DATA_MASK', + 'TA_DSM_CNTL__TA_FX_LFIFO_DSM_IRRITATOR_DATA__SHIFT', + 'TA_DSM_CNTL__TA_FX_LFIFO_ENABLE_SINGLE_WRITE_MASK', + 'TA_DSM_CNTL__TA_FX_LFIFO_ENABLE_SINGLE_WRITE__SHIFT', + 'TA_FEATURE_CNTL__AFIFO_SPLIT_CHICKEN_MASK', + 'TA_FEATURE_CNTL__AFIFO_SPLIT_CHICKEN__SHIFT', + 'TA_FEATURE_CNTL__ATOMIC_COALESCING_EN_MASK', + 'TA_FEATURE_CNTL__ATOMIC_COALESCING_EN__SHIFT', + 'TA_FEATURE_CNTL__TA_ACFIFO_CHICKEN_MASK', + 'TA_FEATURE_CNTL__TA_ACFIFO_CHICKEN__SHIFT', + 'TA_FEATURE_CNTL__TA_CAC_CHICKEN_MASK', + 'TA_FEATURE_CNTL__TA_CAC_CHICKEN__SHIFT', + 'TA_FEATURE_CNTL__TA_DXFIFO_CHICKEN_MASK', + 'TA_FEATURE_CNTL__TA_DXFIFO_CHICKEN__SHIFT', + 'TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'TA_POWER_CNTL__INPUT_CLK_EN_MODE_MASK', + 'TA_POWER_CNTL__INPUT_CLK_EN_MODE__SHIFT', + 'TA_POWER_CNTL__LOD_CLK_EN_MODE_MASK', + 'TA_POWER_CNTL__LOD_CLK_EN_MODE__SHIFT', + 'TA_POWER_CNTL__WDP_CLK_EN_MODE_MASK', + 'TA_POWER_CNTL__WDP_CLK_EN_MODE__SHIFT', + 'TA_SCRATCH__SCRATCH_MASK', 'TA_SCRATCH__SCRATCH__SHIFT', + 'TA_STATUS__AL_BUSY_MASK', 'TA_STATUS__AL_BUSY__SHIFT', + 'TA_STATUS__BUSY_MASK', 'TA_STATUS__BUSY__SHIFT', + 'TA_STATUS__FA_BUSY_MASK', 'TA_STATUS__FA_BUSY__SHIFT', + 'TA_STATUS__FA_PFIFO_EMPTYB_MASK', + 'TA_STATUS__FA_PFIFO_EMPTYB__SHIFT', 'TA_STATUS__FG_BUSY_MASK', + 'TA_STATUS__FG_BUSY__SHIFT', 'TA_STATUS__FG_PFIFO_EMPTYB_MASK', + 'TA_STATUS__FG_PFIFO_EMPTYB__SHIFT', + 'TA_STATUS__FL_PFIFO_EMPTYB_MASK', + 'TA_STATUS__FL_PFIFO_EMPTYB__SHIFT', 'TA_STATUS__IN_BUSY_MASK', + 'TA_STATUS__IN_BUSY__SHIFT', 'TA_STATUS__TA_BUSY_MASK', + 'TA_STATUS__TA_BUSY__SHIFT', 'TA_UE_EDC_HI__ECC_MASK', + 'TA_UE_EDC_HI__ECC__SHIFT', 'TA_UE_EDC_HI__ERR_INFO_MASK', + 'TA_UE_EDC_HI__ERR_INFO_VALID_FLAG_MASK', + 'TA_UE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'TA_UE_EDC_HI__ERR_INFO__SHIFT', 'TA_UE_EDC_HI__FED_CNT_MASK', + 'TA_UE_EDC_HI__FED_CNT__SHIFT', 'TA_UE_EDC_HI__PARITY_MASK', + 'TA_UE_EDC_HI__PARITY__SHIFT', 'TA_UE_EDC_HI__UE_CNT_MASK', + 'TA_UE_EDC_HI__UE_CNT__SHIFT', + 'TA_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK', + 'TA_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT', + 'TA_UE_EDC_LO__ADDRESS_MASK', 'TA_UE_EDC_LO__ADDRESS__SHIFT', + 'TA_UE_EDC_LO__MEM_ID_MASK', 'TA_UE_EDC_LO__MEM_ID__SHIFT', + 'TA_UE_EDC_LO__STATUS_VALID_FLAG_MASK', + 'TA_UE_EDC_LO__STATUS_VALID_FLAG__SHIFT', + 'TCA_BURST_CTRL__CPF_DISABLE_MASK', + 'TCA_BURST_CTRL__CPF_DISABLE__SHIFT', + 'TCA_BURST_CTRL__CPG_DISABLE_MASK', + 'TCA_BURST_CTRL__CPG_DISABLE__SHIFT', + 'TCA_BURST_CTRL__MAX_BURST_MASK', + 'TCA_BURST_CTRL__MAX_BURST__SHIFT', + 'TCA_BURST_CTRL__RLC_DISABLE_MASK', + 'TCA_BURST_CTRL__RLC_DISABLE__SHIFT', + 'TCA_BURST_CTRL__SQC_DISABLE_MASK', + 'TCA_BURST_CTRL__SQC_DISABLE__SHIFT', + 'TCA_BURST_CTRL__SQG_DISABLE_MASK', + 'TCA_BURST_CTRL__SQG_DISABLE__SHIFT', + 'TCA_BURST_CTRL__TCP_DISABLE_MASK', + 'TCA_BURST_CTRL__TCP_DISABLE__SHIFT', + 'TCA_BURST_CTRL__TPI_DISABLE_MASK', + 'TCA_BURST_CTRL__TPI_DISABLE__SHIFT', + 'TCA_BURST_CTRL__UTCL2_DISABLE_MASK', + 'TCA_BURST_CTRL__UTCL2_DISABLE__SHIFT', + 'TCA_BURST_MASK__ADDR_MASK_MASK', + 'TCA_BURST_MASK__ADDR_MASK__SHIFT', + 'TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK', + 'TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK', + 'TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT', + 'TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK', + 'TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT', + 'TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK', + 'TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT', + 'TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK', + 'TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT', + 'TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK', + 'TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT', + 'TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK', + 'TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT', + 'TCA_CTRL__ACK_CREDIT_THRESHOLD_MASK', + 'TCA_CTRL__ACK_CREDIT_THRESHOLD__SHIFT', + 'TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER_MASK', + 'TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER__SHIFT', + 'TCA_CTRL__DISABLE_UTCL2_PRIORITY_MASK', + 'TCA_CTRL__DISABLE_UTCL2_PRIORITY__SHIFT', + 'TCA_CTRL__HOLE_ARB_LANE_THRESHOLD_MASK', + 'TCA_CTRL__HOLE_ARB_LANE_THRESHOLD__SHIFT', + 'TCA_CTRL__HOLE_ARB_SHARE_THRESHOLD_MASK', + 'TCA_CTRL__HOLE_ARB_SHARE_THRESHOLD__SHIFT', + 'TCA_CTRL__HOLE_TIMEOUT_MASK', 'TCA_CTRL__HOLE_TIMEOUT__SHIFT', + 'TCA_CTRL__RB_AS_TCI_MASK', 'TCA_CTRL__RB_AS_TCI__SHIFT', + 'TCA_CTRL__RB_STILL_4_PHASE_MASK', + 'TCA_CTRL__RB_STILL_4_PHASE__SHIFT', + 'TCA_CTRL__RTN_ARB_MODE_MASK', 'TCA_CTRL__RTN_ARB_MODE__SHIFT', + 'TCA_CTRL__RTN_CREDIT_THRESHOLD_MASK', + 'TCA_CTRL__RTN_CREDIT_THRESHOLD__SHIFT', + 'TCA_CTRL__TCA_RANDOM_REVERSE_PRIORITY_ENABLE_MASK', + 'TCA_CTRL__TCA_RANDOM_REVERSE_PRIORITY_ENABLE__SHIFT', + 'TCA_CTRL__TCA_TCA_FGCG_DISABLE_MASK', + 'TCA_CTRL__TCA_TCA_FGCG_DISABLE__SHIFT', + 'TCA_CTRL__TCA_TCC_FGCG_DISABLE_MASK', + 'TCA_CTRL__TCA_TCC_FGCG_DISABLE__SHIFT', + 'TCA_CTRL__TCA_TCH_FGCG_DISABLE_MASK', + 'TCA_CTRL__TCA_TCH_FGCG_DISABLE__SHIFT', + 'TCA_CTRL__TCA_TCX_FGCG_DISABLE_MASK', + 'TCA_CTRL__TCA_TCX_FGCG_DISABLE__SHIFT', + 'TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT_MASK', + 'TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT', + 'TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY_MASK', + 'TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY__SHIFT', + 'TCA_DSM_CNTL2__INJECT_DELAY_MASK', + 'TCA_DSM_CNTL2__INJECT_DELAY__SHIFT', + 'TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT_MASK', + 'TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT', + 'TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY_MASK', + 'TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY__SHIFT', + 'TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL_MASK', + 'TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT', + 'TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK', + 'TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL_MASK', + 'TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT', + 'TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK', + 'TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'TCA_UE_ERR_STATUS_HI__ECC_MASK', + 'TCA_UE_ERR_STATUS_HI__ECC__SHIFT', + 'TCA_UE_ERR_STATUS_HI__ERROR_INFO_MASK', + 'TCA_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK', + 'TCA_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT', + 'TCA_UE_ERR_STATUS_HI__ERROR_INFO__SHIFT', + 'TCA_UE_ERR_STATUS_HI__FED_CNT_MASK', + 'TCA_UE_ERR_STATUS_HI__FED_CNT__SHIFT', + 'TCA_UE_ERR_STATUS_HI__PARITY_MASK', + 'TCA_UE_ERR_STATUS_HI__PARITY__SHIFT', + 'TCA_UE_ERR_STATUS_HI__UE_CNT_MASK', + 'TCA_UE_ERR_STATUS_HI__UE_CNT__SHIFT', + 'TCA_UE_ERR_STATUS_LO__ADDRESS_MASK', + 'TCA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'TCA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'TCA_UE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'TCA_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'TCA_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'TCA_UE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'TCA_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'TCC_CE_ERR_STATUS_HI__CE_CNT_MASK', + 'TCC_CE_ERR_STATUS_HI__CE_CNT__SHIFT', + 'TCC_CE_ERR_STATUS_HI__ECC_MASK', + 'TCC_CE_ERR_STATUS_HI__ECC__SHIFT', + 'TCC_CE_ERR_STATUS_HI__ERROR_INFO_MASK', + 'TCC_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK', + 'TCC_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT', + 'TCC_CE_ERR_STATUS_HI__ERROR_INFO__SHIFT', + 'TCC_CE_ERR_STATUS_HI__POISON_MASK', + 'TCC_CE_ERR_STATUS_HI__POISON__SHIFT', + 'TCC_CE_ERR_STATUS_LO__ADDRESS_MASK', + 'TCC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'TCC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'TCC_CE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'TCC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'TCC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'TCC_CE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'TCC_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'TCC_CGTT_SCLK_CTRL2__OFF_HYSTERESIS_MASK', + 'TCC_CGTT_SCLK_CTRL2__OFF_HYSTERESIS__SHIFT', + 'TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE1_MASK', + 'TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE1__SHIFT', + 'TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE2_MASK', + 'TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE2__SHIFT', + 'TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE3_MASK', + 'TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE3__SHIFT', + 'TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE4_MASK', + 'TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE4__SHIFT', + 'TCC_CGTT_SCLK_CTRL3__OFF_HYSTERESIS_MASK', + 'TCC_CGTT_SCLK_CTRL3__OFF_HYSTERESIS__SHIFT', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE10_MASK', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE10__SHIFT', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE11_MASK', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE11__SHIFT', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE12_MASK', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE12__SHIFT', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE13_MASK', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE13__SHIFT', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE14_MASK', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE14__SHIFT', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE15_MASK', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE15__SHIFT', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE16_MASK', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE16__SHIFT', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE17_MASK', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE17__SHIFT', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE18_MASK', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE18__SHIFT', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE1_MASK', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE1__SHIFT', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE2_MASK', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE2__SHIFT', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE3_MASK', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE3__SHIFT', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE4_MASK', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE4__SHIFT', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE5_MASK', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE5__SHIFT', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE6_MASK', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE6__SHIFT', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE7_MASK', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE7__SHIFT', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE8_MASK', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE8__SHIFT', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE9_MASK', + 'TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE9__SHIFT', + 'TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK', + 'TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK', + 'TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT', + 'TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK', + 'TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT', + 'TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK', + 'TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT', + 'TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK', + 'TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT', + 'TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK', + 'TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT', + 'TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK', + 'TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT', + 'TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK', + 'TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT', + 'TCC_CTRL2__Enable_TCC_64K_2M_1G_1T_hash_MASK', + 'TCC_CTRL2__Enable_TCC_64K_2M_1G_1T_hash__SHIFT', + 'TCC_CTRL2__INF_NAN_CLAMP_MASK', + 'TCC_CTRL2__INF_NAN_CLAMP__SHIFT', + 'TCC_CTRL2__PROBE_FIFO_SIZE_MASK', + 'TCC_CTRL2__PROBE_FIFO_SIZE__SHIFT', + 'TCC_CTRL2__PROBE_FILTER_CTRL_MASK', + 'TCC_CTRL2__PROBE_FILTER_CTRL__SHIFT', + 'TCC_CTRL2__TCC_EA0_RDREQ_FGCG_DISABLE_MASK', + 'TCC_CTRL2__TCC_EA0_RDREQ_FGCG_DISABLE__SHIFT', + 'TCC_CTRL2__TCC_EA0_WRREQ_FGCG_DISABLE_MASK', + 'TCC_CTRL2__TCC_EA0_WRREQ_FGCG_DISABLE__SHIFT', + 'TCC_CTRL2__TCC_TCA_HOLE_REPEATER_FGCG_DISABLE_MASK', + 'TCC_CTRL2__TCC_TCA_HOLE_REPEATER_FGCG_DISABLE__SHIFT', + 'TCC_CTRL2__TCC_TCA_RTN_REPEATER_FGCG_DISABLE_MASK', + 'TCC_CTRL2__TCC_TCA_RTN_REPEATER_FGCG_DISABLE__SHIFT', + 'TCC_CTRL2__TCC_TCX_ACK_REPEATER_FGCG_DISABLE_MASK', + 'TCC_CTRL2__TCC_TCX_ACK_REPEATER_FGCG_DISABLE__SHIFT', + 'TCC_CTRL2__TCC_TCX_REPEATER_FGCG_DISABLE_MASK', + 'TCC_CTRL2__TCC_TCX_REPEATER_FGCG_DISABLE__SHIFT', + 'TCC_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK_MASK', + 'TCC_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK__SHIFT', + 'TCC_CTRL2__WAIT_CLK_STABLE_CNT_MASK', + 'TCC_CTRL2__WAIT_CLK_STABLE_CNT__SHIFT', + 'TCC_CTRL__CACHE_SIZE_MASK', 'TCC_CTRL__CACHE_SIZE__SHIFT', + 'TCC_CTRL__DISABLE_SHARED_128B_READ_REQUEST_MASK', + 'TCC_CTRL__DISABLE_SHARED_128B_READ_REQUEST__SHIFT', + 'TCC_CTRL__EXECUTE_CLK_MODE_MASK', + 'TCC_CTRL__EXECUTE_CLK_MODE__SHIFT', + 'TCC_CTRL__LATENCY_FIFO_CLK_MODE_MASK', + 'TCC_CTRL__LATENCY_FIFO_CLK_MODE__SHIFT', + 'TCC_CTRL__LATENCY_FIFO_SIZE_MASK', + 'TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT', + 'TCC_CTRL__LINEAR_SET_HASH_MASK', + 'TCC_CTRL__LINEAR_SET_HASH__SHIFT', + 'TCC_CTRL__MC_WRITE_CLK_MODE_MASK', + 'TCC_CTRL__MC_WRITE_CLK_MODE__SHIFT', + 'TCC_CTRL__OUTPUT_FIFO_CLK_MODE_MASK', + 'TCC_CTRL__OUTPUT_FIFO_CLK_MODE__SHIFT', 'TCC_CTRL__RATE_MASK', + 'TCC_CTRL__RATE__SHIFT', 'TCC_CTRL__RETURN_BUFFER_CLK_MODE_MASK', + 'TCC_CTRL__RETURN_BUFFER_CLK_MODE__SHIFT', + 'TCC_CTRL__SRC_FIFO_CLK_MODE_MASK', + 'TCC_CTRL__SRC_FIFO_CLK_MODE__SHIFT', + 'TCC_CTRL__SRC_FIFO_SIZE_MASK', 'TCC_CTRL__SRC_FIFO_SIZE__SHIFT', + 'TCC_CTRL__WRITEBACK_MARGIN_MASK', + 'TCC_CTRL__WRITEBACK_MARGIN__SHIFT', + 'TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL2A__OUTPUT_FIFOS_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL2A__OUTPUT_FIFOS_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL2A__OUTPUT_FIFOS_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2A__OUTPUT_FIFOS_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL2B__RETURN_BUFFER_LEVEL_BUBBLE_THRESHOLD_MASK', + 'TCC_DSM_CNTL2B__RETURN_BUFFER_LEVEL_BUBBLE_THRESHOLD__SHIFT', + 'TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL2__INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2__INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_ENABLE_ERROR_INJECT_MASK', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_ENABLE_ERROR_INJECT__SHIFT', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_SELECT_INJECT_DELAY_MASK', + 'TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_SELECT_INJECT_DELAY__SHIFT', + 'TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL_MASK', + 'TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT', + 'TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK', + 'TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'TCC_SOFT_RESET__HALT_FOR_RESET_MASK', + 'TCC_SOFT_RESET__HALT_FOR_RESET__SHIFT', + 'TCC_UE_ERR_STATUS_HI__ECC_MASK', + 'TCC_UE_ERR_STATUS_HI__ECC__SHIFT', + 'TCC_UE_ERR_STATUS_HI__ERROR_INFO_MASK', + 'TCC_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK', + 'TCC_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT', + 'TCC_UE_ERR_STATUS_HI__ERROR_INFO__SHIFT', + 'TCC_UE_ERR_STATUS_HI__FED_CNT_MASK', + 'TCC_UE_ERR_STATUS_HI__FED_CNT__SHIFT', + 'TCC_UE_ERR_STATUS_HI__PARITY_MASK', + 'TCC_UE_ERR_STATUS_HI__PARITY__SHIFT', + 'TCC_UE_ERR_STATUS_HI__UE_CNT_MASK', + 'TCC_UE_ERR_STATUS_HI__UE_CNT__SHIFT', + 'TCC_UE_ERR_STATUS_LO__ADDRESS_MASK', + 'TCC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'TCC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'TCC_UE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'TCC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'TCC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'TCC_UE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'TCC_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'TCC_WBINVL2__DONE_MASK', 'TCC_WBINVL2__DONE__SHIFT', + 'TCI_CE_EDC_HI_REG__CE_CNT_MASK', + 'TCI_CE_EDC_HI_REG__CE_CNT__SHIFT', 'TCI_CE_EDC_HI_REG__ECC_MASK', + 'TCI_CE_EDC_HI_REG__ECC__SHIFT', + 'TCI_CE_EDC_HI_REG__ERR_INFO_MASK', + 'TCI_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK', + 'TCI_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT', + 'TCI_CE_EDC_HI_REG__ERR_INFO__SHIFT', + 'TCI_CE_EDC_HI_REG__POISON_MASK', + 'TCI_CE_EDC_HI_REG__POISON__SHIFT', + 'TCI_CE_EDC_HI_REG__RESERVED_MASK', + 'TCI_CE_EDC_HI_REG__RESERVED__SHIFT', + 'TCI_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK', + 'TCI_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT', + 'TCI_CE_EDC_LO_REG__ADDRESS_MASK', + 'TCI_CE_EDC_LO_REG__ADDRESS__SHIFT', + 'TCI_CE_EDC_LO_REG__MEM_ID_MASK', + 'TCI_CE_EDC_LO_REG__MEM_ID__SHIFT', + 'TCI_CE_EDC_LO_REG__STATUS_VALID_FLAG_MASK', + 'TCI_CE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT', + 'TCI_CNTL_1__REQ_FIFO_DEPTH_MASK', + 'TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT', + 'TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK', + 'TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT', + 'TCI_CNTL_1__WDATA_RAM_DEPTH_MASK', + 'TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT', + 'TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK', + 'TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT', + 'TCI_CNTL_2__TCA_MAX_CREDIT_MASK', + 'TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT', + 'TCI_CNTL_3__CHICKEN_BIT_TCR_MGCG_MASK', + 'TCI_CNTL_3__CHICKEN_BIT_TCR_MGCG__SHIFT', + 'TCI_CNTL_3__COMBINING_DELAY_WINDOW_MASK', + 'TCI_CNTL_3__COMBINING_DELAY_WINDOW__SHIFT', + 'TCI_CNTL_3__DISABLE_DOUBLING_L2_BANDWIDTH_MASK', + 'TCI_CNTL_3__DISABLE_DOUBLING_L2_BANDWIDTH__SHIFT', + 'TCI_CNTL_3__TCR_FGCG_REPEATER_DISABLE_MASK', + 'TCI_CNTL_3__TCR_FGCG_REPEATER_DISABLE__SHIFT', + 'TCI_DSM_CNTL2__TCI_INJECT_DELAY_MASK', + 'TCI_DSM_CNTL2__TCI_INJECT_DELAY__SHIFT', + 'TCI_DSM_CNTL2__WRITE_RAM_ENABLE_ERROR_INJECT_MASK', + 'TCI_DSM_CNTL2__WRITE_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'TCI_DSM_CNTL2__WRITE_RAM_SELECT_INJECT_DELAY_MASK', + 'TCI_DSM_CNTL2__WRITE_RAM_SELECT_INJECT_DELAY__SHIFT', + 'TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_DATA_SEL_MASK', + 'TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_DATA_SEL__SHIFT', + 'TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_SINGLE_WRITE_MASK', + 'TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCI_MISC__FGCG_REPEATER_DISABLE_MASK', + 'TCI_MISC__FGCG_REPEATER_DISABLE__SHIFT', + 'TCI_MISC__LEGACY_MGCG_DISABLE_MASK', + 'TCI_MISC__LEGACY_MGCG_DISABLE__SHIFT', + 'TCI_STATUS__TCI_BUSY_MASK', 'TCI_STATUS__TCI_BUSY__SHIFT', + 'TCI_UE_EDC_HI_REG__ECC_MASK', 'TCI_UE_EDC_HI_REG__ECC__SHIFT', + 'TCI_UE_EDC_HI_REG__ERR_INFO_MASK', + 'TCI_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK', + 'TCI_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT', + 'TCI_UE_EDC_HI_REG__ERR_INFO__SHIFT', + 'TCI_UE_EDC_HI_REG__FED_CNT_MASK', + 'TCI_UE_EDC_HI_REG__FED_CNT__SHIFT', + 'TCI_UE_EDC_HI_REG__PARITY_MASK', + 'TCI_UE_EDC_HI_REG__PARITY__SHIFT', + 'TCI_UE_EDC_HI_REG__RESERVED_MASK', + 'TCI_UE_EDC_HI_REG__RESERVED__SHIFT', + 'TCI_UE_EDC_HI_REG__UE_CNT_MASK', + 'TCI_UE_EDC_HI_REG__UE_CNT__SHIFT', + 'TCI_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK', + 'TCI_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT', + 'TCI_UE_EDC_LO_REG__ADDRESS_MASK', + 'TCI_UE_EDC_LO_REG__ADDRESS__SHIFT', + 'TCI_UE_EDC_LO_REG__MEM_ID_MASK', + 'TCI_UE_EDC_LO_REG__MEM_ID__SHIFT', + 'TCI_UE_EDC_LO_REG__STATUS_VALID_FLAG_MASK', + 'TCI_UE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT', + 'TCP_ADDR_CONFIG__ENABLE1GHASH_MASK', + 'TCP_ADDR_CONFIG__ENABLE1GHASH__SHIFT', + 'TCP_ADDR_CONFIG__ENABLE1THASH_MASK', + 'TCP_ADDR_CONFIG__ENABLE1THASH__SHIFT', + 'TCP_ADDR_CONFIG__ENABLE2MHASH_MASK', + 'TCP_ADDR_CONFIG__ENABLE2MHASH__SHIFT', + 'TCP_ADDR_CONFIG__ENABLE4KHASH_MASK', + 'TCP_ADDR_CONFIG__ENABLE4KHASH__SHIFT', + 'TCP_ADDR_CONFIG__ENABLE64KHASH_MASK', + 'TCP_ADDR_CONFIG__ENABLE64KHASH__SHIFT', + 'TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK', + 'TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT', + 'TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK', + 'TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT', + 'TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK', + 'TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT', + 'TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK', + 'TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT', + 'TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK', + 'TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT', + 'TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK', + 'TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT', + 'TCP_CE_EDC_HI_REG__CE_CNT_MASK', + 'TCP_CE_EDC_HI_REG__CE_CNT__SHIFT', 'TCP_CE_EDC_HI_REG__ECC_MASK', + 'TCP_CE_EDC_HI_REG__ECC__SHIFT', + 'TCP_CE_EDC_HI_REG__ERR_INFO_MASK', + 'TCP_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK', + 'TCP_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT', + 'TCP_CE_EDC_HI_REG__ERR_INFO__SHIFT', + 'TCP_CE_EDC_HI_REG__POISON_MASK', + 'TCP_CE_EDC_HI_REG__POISON__SHIFT', + 'TCP_CE_EDC_HI_REG__RESERVED_MASK', + 'TCP_CE_EDC_HI_REG__RESERVED__SHIFT', + 'TCP_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK', + 'TCP_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT', + 'TCP_CE_EDC_LO_REG__ADDRESS_MASK', + 'TCP_CE_EDC_LO_REG__ADDRESS__SHIFT', + 'TCP_CE_EDC_LO_REG__MEM_ID_MASK', + 'TCP_CE_EDC_LO_REG__MEM_ID__SHIFT', + 'TCP_CE_EDC_LO_REG__STATUS_VALID_FLAG_MASK', + 'TCP_CE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT', + 'TCP_CHAN_STEER_0__CHAN0_MASK', 'TCP_CHAN_STEER_0__CHAN0__SHIFT', + 'TCP_CHAN_STEER_0__CHAN1_MASK', 'TCP_CHAN_STEER_0__CHAN1__SHIFT', + 'TCP_CHAN_STEER_0__CHAN2_MASK', 'TCP_CHAN_STEER_0__CHAN2__SHIFT', + 'TCP_CHAN_STEER_0__CHAN3_MASK', 'TCP_CHAN_STEER_0__CHAN3__SHIFT', + 'TCP_CHAN_STEER_0__CHAN4_MASK', 'TCP_CHAN_STEER_0__CHAN4__SHIFT', + 'TCP_CHAN_STEER_0__CHAN5_MASK', 'TCP_CHAN_STEER_0__CHAN5__SHIFT', + 'TCP_CHAN_STEER_0__CHAN6_MASK', 'TCP_CHAN_STEER_0__CHAN6__SHIFT', + 'TCP_CHAN_STEER_0__CHAN7_MASK', 'TCP_CHAN_STEER_0__CHAN7__SHIFT', + 'TCP_CHAN_STEER_1__CHAN8_MASK', 'TCP_CHAN_STEER_1__CHAN8__SHIFT', + 'TCP_CHAN_STEER_1__CHAN9_MASK', 'TCP_CHAN_STEER_1__CHAN9__SHIFT', + 'TCP_CHAN_STEER_1__CHANA_MASK', 'TCP_CHAN_STEER_1__CHANA__SHIFT', + 'TCP_CHAN_STEER_1__CHANB_MASK', 'TCP_CHAN_STEER_1__CHANB__SHIFT', + 'TCP_CHAN_STEER_1__CHANC_MASK', 'TCP_CHAN_STEER_1__CHANC__SHIFT', + 'TCP_CHAN_STEER_1__CHAND_MASK', 'TCP_CHAN_STEER_1__CHAND__SHIFT', + 'TCP_CHAN_STEER_1__CHANE_MASK', 'TCP_CHAN_STEER_1__CHANE__SHIFT', + 'TCP_CHAN_STEER_1__CHANF_MASK', 'TCP_CHAN_STEER_1__CHANF__SHIFT', + 'TCP_CNTL2__ADRS_CLK_DISABLE_MASK', + 'TCP_CNTL2__ADRS_CLK_DISABLE__SHIFT', + 'TCP_CNTL2__LEGACY_MGCG_DISABLE_MASK', + 'TCP_CNTL2__LEGACY_MGCG_DISABLE__SHIFT', + 'TCP_CNTL2__LS_DISABLE_CLOCKS_MASK', + 'TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT', + 'TCP_CNTL2__MEM_MID_GATE_MGCG_DISABLE_MASK', + 'TCP_CNTL2__MEM_MID_GATE_MGCG_DISABLE__SHIFT', + 'TCP_CNTL2__MISS_CLK_DISABLE_MASK', + 'TCP_CNTL2__MISS_CLK_DISABLE__SHIFT', + 'TCP_CNTL2__TAGRAM_CLK_DISABLE_MASK', + 'TCP_CNTL2__TAGRAM_CLK_DISABLE__SHIFT', + 'TCP_CNTL2__TCPF_FMT_MGCG_DISABLE_MASK', + 'TCP_CNTL2__TCPF_FMT_MGCG_DISABLE__SHIFT', + 'TCP_CNTL2__TCPI_NEW_MGCG_CTRL_BIT_MASK', + 'TCP_CNTL2__TCPI_NEW_MGCG_CTRL_BIT__SHIFT', + 'TCP_CNTL2__UTCL1_MID_GATE_MGCG_DISABLE_MASK', + 'TCP_CNTL2__UTCL1_MID_GATE_MGCG_DISABLE__SHIFT', + 'TCP_CNTL2__VM_CLK_DISABLE_MASK', + 'TCP_CNTL2__VM_CLK_DISABLE__SHIFT', + 'TCP_CNTL__DISABLE_Z_MAP_MASK', 'TCP_CNTL__DISABLE_Z_MAP__SHIFT', + 'TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK', + 'TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT', + 'TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK', + 'TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT', + 'TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK', + 'TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT', + 'TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK', + 'TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT', + 'TCP_CNTL__FORCE_HIT_MASK', 'TCP_CNTL__FORCE_HIT__SHIFT', + 'TCP_CNTL__FORCE_MISS_MASK', 'TCP_CNTL__FORCE_MISS__SHIFT', + 'TCP_CNTL__L1_SIZE_MASK', 'TCP_CNTL__L1_SIZE__SHIFT', + 'TCP_CREDIT__LFIFO_CREDIT_MASK', + 'TCP_CREDIT__LFIFO_CREDIT__SHIFT', + 'TCP_CREDIT__REQ_FIFO_CREDIT_MASK', + 'TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT', + 'TCP_CREDIT__TD_CREDIT_MASK', 'TCP_CREDIT__TD_CREDIT__SHIFT', + 'TCP_DSM_CNTL2__CACHE_RAM_ENABLE_ERROR_INJECT_MASK', + 'TCP_DSM_CNTL2__CACHE_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'TCP_DSM_CNTL2__CACHE_RAM_SELECT_INJECT_DELAY_MASK', + 'TCP_DSM_CNTL2__CACHE_RAM_SELECT_INJECT_DELAY__SHIFT', + 'TCP_DSM_CNTL2__CMD_FIFO_ENABLE_ERROR_INJECT_MASK', + 'TCP_DSM_CNTL2__CMD_FIFO_ENABLE_ERROR_INJECT__SHIFT', + 'TCP_DSM_CNTL2__CMD_FIFO_SELECT_INJECT_DELAY_MASK', + 'TCP_DSM_CNTL2__CMD_FIFO_SELECT_INJECT_DELAY__SHIFT', + 'TCP_DSM_CNTL2__DB_RAM_ENABLE_ERROR_INJECT_MASK', + 'TCP_DSM_CNTL2__DB_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'TCP_DSM_CNTL2__DB_RAM_SELECT_INJECT_DELAY_MASK', + 'TCP_DSM_CNTL2__DB_RAM_SELECT_INJECT_DELAY__SHIFT', + 'TCP_DSM_CNTL2__LFIFO_RAM_ENABLE_ERROR_INJECT_MASK', + 'TCP_DSM_CNTL2__LFIFO_RAM_ENABLE_ERROR_INJECT__SHIFT', + 'TCP_DSM_CNTL2__LFIFO_RAM_SELECT_INJECT_DELAY_MASK', + 'TCP_DSM_CNTL2__LFIFO_RAM_SELECT_INJECT_DELAY__SHIFT', + 'TCP_DSM_CNTL2__TCP_INJECT_DELAY_MASK', + 'TCP_DSM_CNTL2__TCP_INJECT_DELAY__SHIFT', + 'TCP_DSM_CNTL2__UTCL1_LFIFO0_ENABLE_ERROR_INJECT_MASK', + 'TCP_DSM_CNTL2__UTCL1_LFIFO0_ENABLE_ERROR_INJECT__SHIFT', + 'TCP_DSM_CNTL2__UTCL1_LFIFO0_SELECT_INJECT_DELAY_MASK', + 'TCP_DSM_CNTL2__UTCL1_LFIFO0_SELECT_INJECT_DELAY__SHIFT', + 'TCP_DSM_CNTL2__UTCL1_LFIFO1_ENABLE_ERROR_INJECT_MASK', + 'TCP_DSM_CNTL2__UTCL1_LFIFO1_ENABLE_ERROR_INJECT__SHIFT', + 'TCP_DSM_CNTL2__UTCL1_LFIFO1_SELECT_INJECT_DELAY_MASK', + 'TCP_DSM_CNTL2__UTCL1_LFIFO1_SELECT_INJECT_DELAY__SHIFT', + 'TCP_DSM_CNTL2__VM_FIFO_ENABLE_ERROR_INJECT_MASK', + 'TCP_DSM_CNTL2__VM_FIFO_ENABLE_ERROR_INJECT__SHIFT', + 'TCP_DSM_CNTL2__VM_FIFO_SELECT_INJECT_DELAY_MASK', + 'TCP_DSM_CNTL2__VM_FIFO_SELECT_INJECT_DELAY__SHIFT', + 'TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK', + 'TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT', + 'TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK', + 'TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_DATA_SEL_MASK', + 'TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_DATA_SEL__SHIFT', + 'TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_SINGLE_WRITE_MASK', + 'TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCP_DSM_CNTL__DB_RAM_IRRITATOR_DATA_SEL_MASK', + 'TCP_DSM_CNTL__DB_RAM_IRRITATOR_DATA_SEL__SHIFT', + 'TCP_DSM_CNTL__DB_RAM_IRRITATOR_SINGLE_WRITE_MASK', + 'TCP_DSM_CNTL__DB_RAM_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL_MASK', + 'TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL__SHIFT', + 'TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE_MASK', + 'TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_DATA_SEL_MASK', + 'TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_DATA_SEL__SHIFT', + 'TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_SINGLE_WRITE_MASK', + 'TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_DATA_SEL_MASK', + 'TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_DATA_SEL__SHIFT', + 'TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_SINGLE_WRITE_MASK', + 'TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCP_DSM_CNTL__VM_FIFO_IRRITATOR_DATA_SEL_MASK', + 'TCP_DSM_CNTL__VM_FIFO_IRRITATOR_DATA_SEL__SHIFT', + 'TCP_DSM_CNTL__VM_FIFO_IRRITATOR_SINGLE_WRITE_MASK', + 'TCP_DSM_CNTL__VM_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK', + 'TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT', + 'TCP_GATCL1_CNTL__FORCE_MISS_MASK', + 'TCP_GATCL1_CNTL__FORCE_MISS__SHIFT', + 'TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK', + 'TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT', + 'TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK', + 'TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT', + 'TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK', + 'TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT', + 'TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK', + 'TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT', + 'TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK', + 'TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT', + 'TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK', + 'TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT', + 'TCP_INVALIDATE__START_MASK', 'TCP_INVALIDATE__START__SHIFT', + 'TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK', + 'TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT', + 'TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK', + 'TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT', + 'TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__DIM_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__GLC_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__SLC_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT', + 'TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK', + 'TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT', + 'TCP_PERFCOUNTER_FILTER__ADDR_MODE_MASK', + 'TCP_PERFCOUNTER_FILTER__ADDR_MODE__SHIFT', + 'TCP_PERFCOUNTER_FILTER__BUFFER_MASK', + 'TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT', + 'TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK', + 'TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT', + 'TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK', + 'TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT', + 'TCP_PERFCOUNTER_FILTER__DIM_MASK', + 'TCP_PERFCOUNTER_FILTER__DIM__SHIFT', + 'TCP_PERFCOUNTER_FILTER__FLAT_MASK', + 'TCP_PERFCOUNTER_FILTER__FLAT__SHIFT', + 'TCP_PERFCOUNTER_FILTER__GLC_MASK', + 'TCP_PERFCOUNTER_FILTER__GLC__SHIFT', + 'TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK', + 'TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT', + 'TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK', + 'TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT', + 'TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK', + 'TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT', + 'TCP_PERFCOUNTER_FILTER__SLC_MASK', + 'TCP_PERFCOUNTER_FILTER__SLC__SHIFT', + 'TCP_PERFCOUNTER_FILTER__SW_MODE_MASK', + 'TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT', + 'TCP_STATUS__ADRS_BUSY_MASK', 'TCP_STATUS__ADRS_BUSY__SHIFT', + 'TCP_STATUS__CNTRL_BUSY_MASK', 'TCP_STATUS__CNTRL_BUSY__SHIFT', + 'TCP_STATUS__FORMAT_BUSY_MASK', 'TCP_STATUS__FORMAT_BUSY__SHIFT', + 'TCP_STATUS__INPUT_BUSY_MASK', 'TCP_STATUS__INPUT_BUSY__SHIFT', + 'TCP_STATUS__LFIFO_BUSY_MASK', 'TCP_STATUS__LFIFO_BUSY__SHIFT', + 'TCP_STATUS__READ_BUSY_MASK', 'TCP_STATUS__READ_BUSY__SHIFT', + 'TCP_STATUS__TAGRAMS_BUSY_MASK', + 'TCP_STATUS__TAGRAMS_BUSY__SHIFT', 'TCP_STATUS__TCP_BUSY_MASK', + 'TCP_STATUS__TCP_BUSY__SHIFT', 'TCP_STATUS__VM_BUSY_MASK', + 'TCP_STATUS__VM_BUSY__SHIFT', 'TCP_UE_EDC_HI_REG__ECC_MASK', + 'TCP_UE_EDC_HI_REG__ECC__SHIFT', + 'TCP_UE_EDC_HI_REG__ERR_INFO_MASK', + 'TCP_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK', + 'TCP_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT', + 'TCP_UE_EDC_HI_REG__ERR_INFO__SHIFT', + 'TCP_UE_EDC_HI_REG__FED_CNT_MASK', + 'TCP_UE_EDC_HI_REG__FED_CNT__SHIFT', + 'TCP_UE_EDC_HI_REG__PARITY_MASK', + 'TCP_UE_EDC_HI_REG__PARITY__SHIFT', + 'TCP_UE_EDC_HI_REG__RESERVED_MASK', + 'TCP_UE_EDC_HI_REG__RESERVED__SHIFT', + 'TCP_UE_EDC_HI_REG__UE_CNT_MASK', + 'TCP_UE_EDC_HI_REG__UE_CNT__SHIFT', + 'TCP_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK', + 'TCP_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT', + 'TCP_UE_EDC_LO_REG__ADDRESS_MASK', + 'TCP_UE_EDC_LO_REG__ADDRESS__SHIFT', + 'TCP_UE_EDC_LO_REG__MEM_ID_MASK', + 'TCP_UE_EDC_LO_REG__MEM_ID__SHIFT', + 'TCP_UE_EDC_LO_REG__STATUS_VALID_FLAG_MASK', + 'TCP_UE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT', + 'TCP_UTCL1_CNTL1__CLIENTID_MASK', + 'TCP_UTCL1_CNTL1__CLIENTID__SHIFT', + 'TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK', + 'TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT', + 'TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK', + 'TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT', + 'TCP_UTCL1_CNTL1__FORCE_MISS_MASK', + 'TCP_UTCL1_CNTL1__FORCE_MISS__SHIFT', + 'TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK', + 'TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT', + 'TCP_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK', + 'TCP_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT', + 'TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK', + 'TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT', + 'TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK', + 'TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT', + 'TCP_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK', + 'TCP_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT', + 'TCP_UTCL1_CNTL1__REG_INV_TOGGLE_MASK', + 'TCP_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT', + 'TCP_UTCL1_CNTL1__REG_INV_VMID_MASK', + 'TCP_UTCL1_CNTL1__REG_INV_VMID__SHIFT', + 'TCP_UTCL1_CNTL1__RESP_FAULT_MODE_MASK', + 'TCP_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT', + 'TCP_UTCL1_CNTL1__RESP_MODE_MASK', + 'TCP_UTCL1_CNTL1__RESP_MODE__SHIFT', + 'TCP_UTCL1_CNTL1__UTCL1_FGCG_REPEATER_DISABLE_MASK', + 'TCP_UTCL1_CNTL1__UTCL1_FGCG_REPEATER_DISABLE__SHIFT', + 'TCP_UTCL1_CNTL2__ANY_LINE_VALID_MASK', + 'TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT', + 'TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK', + 'TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT', + 'TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK', + 'TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT', + 'TCP_UTCL1_CNTL2__FORCE_SNOOP_MASK', + 'TCP_UTCL1_CNTL2__FORCE_SNOOP__SHIFT', + 'TCP_UTCL1_CNTL2__GPUVM_INV_MODE_MASK', + 'TCP_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT', + 'TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK', + 'TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT', + 'TCP_UTCL1_CNTL2__SPARE_MASK', 'TCP_UTCL1_CNTL2__SPARE__SHIFT', + 'TCP_UTCL1_CNTL2__THRASHING_ENABLE_MASK', + 'TCP_UTCL1_CNTL2__THRASHING_ENABLE__SHIFT', + 'TCP_UTCL1_CNTL2__THRASHING_TIMEOUT_PROTECT_ENABLE_MASK', + 'TCP_UTCL1_CNTL2__THRASHING_TIMEOUT_PROTECT_ENABLE__SHIFT', + 'TCP_UTCL1_STATUS__FAULT_DETECTED_MASK', + 'TCP_UTCL1_STATUS__FAULT_DETECTED__SHIFT', + 'TCP_UTCL1_STATUS__PRT_DETECTED_MASK', + 'TCP_UTCL1_STATUS__PRT_DETECTED__SHIFT', + 'TCP_UTCL1_STATUS__RETRY_DETECTED_MASK', + 'TCP_UTCL1_STATUS__RETRY_DETECTED__SHIFT', + 'TCP_UTCL1_STATUS__TIMEOUT_DETECTED_MASK', + 'TCP_UTCL1_STATUS__TIMEOUT_DETECTED__SHIFT', + 'TCP_WATCH0_ADDR_H__ADDR_MASK', 'TCP_WATCH0_ADDR_H__ADDR__SHIFT', + 'TCP_WATCH0_ADDR_L__ADDR_MASK', 'TCP_WATCH0_ADDR_L__ADDR__SHIFT', + 'TCP_WATCH0_CNTL__ATC_MASK', 'TCP_WATCH0_CNTL__ATC__SHIFT', + 'TCP_WATCH0_CNTL__MASK_MASK', 'TCP_WATCH0_CNTL__MASK__SHIFT', + 'TCP_WATCH0_CNTL__MODE_MASK', 'TCP_WATCH0_CNTL__MODE__SHIFT', + 'TCP_WATCH0_CNTL__VALID_MASK', 'TCP_WATCH0_CNTL__VALID__SHIFT', + 'TCP_WATCH0_CNTL__VMID_MASK', 'TCP_WATCH0_CNTL__VMID__SHIFT', + 'TCP_WATCH1_ADDR_H__ADDR_MASK', 'TCP_WATCH1_ADDR_H__ADDR__SHIFT', + 'TCP_WATCH1_ADDR_L__ADDR_MASK', 'TCP_WATCH1_ADDR_L__ADDR__SHIFT', + 'TCP_WATCH1_CNTL__ATC_MASK', 'TCP_WATCH1_CNTL__ATC__SHIFT', + 'TCP_WATCH1_CNTL__MASK_MASK', 'TCP_WATCH1_CNTL__MASK__SHIFT', + 'TCP_WATCH1_CNTL__MODE_MASK', 'TCP_WATCH1_CNTL__MODE__SHIFT', + 'TCP_WATCH1_CNTL__VALID_MASK', 'TCP_WATCH1_CNTL__VALID__SHIFT', + 'TCP_WATCH1_CNTL__VMID_MASK', 'TCP_WATCH1_CNTL__VMID__SHIFT', + 'TCP_WATCH2_ADDR_H__ADDR_MASK', 'TCP_WATCH2_ADDR_H__ADDR__SHIFT', + 'TCP_WATCH2_ADDR_L__ADDR_MASK', 'TCP_WATCH2_ADDR_L__ADDR__SHIFT', + 'TCP_WATCH2_CNTL__ATC_MASK', 'TCP_WATCH2_CNTL__ATC__SHIFT', + 'TCP_WATCH2_CNTL__MASK_MASK', 'TCP_WATCH2_CNTL__MASK__SHIFT', + 'TCP_WATCH2_CNTL__MODE_MASK', 'TCP_WATCH2_CNTL__MODE__SHIFT', + 'TCP_WATCH2_CNTL__VALID_MASK', 'TCP_WATCH2_CNTL__VALID__SHIFT', + 'TCP_WATCH2_CNTL__VMID_MASK', 'TCP_WATCH2_CNTL__VMID__SHIFT', + 'TCP_WATCH3_ADDR_H__ADDR_MASK', 'TCP_WATCH3_ADDR_H__ADDR__SHIFT', + 'TCP_WATCH3_ADDR_L__ADDR_MASK', 'TCP_WATCH3_ADDR_L__ADDR__SHIFT', + 'TCP_WATCH3_CNTL__ATC_MASK', 'TCP_WATCH3_CNTL__ATC__SHIFT', + 'TCP_WATCH3_CNTL__MASK_MASK', 'TCP_WATCH3_CNTL__MASK__SHIFT', + 'TCP_WATCH3_CNTL__MODE_MASK', 'TCP_WATCH3_CNTL__MODE__SHIFT', + 'TCP_WATCH3_CNTL__VALID_MASK', 'TCP_WATCH3_CNTL__VALID__SHIFT', + 'TCP_WATCH3_CNTL__VMID_MASK', 'TCP_WATCH3_CNTL__VMID__SHIFT', + 'TCX_CE_ERR_STATUS_HI__CE_CNT_MASK', + 'TCX_CE_ERR_STATUS_HI__CE_CNT__SHIFT', + 'TCX_CE_ERR_STATUS_HI__ECC_MASK', + 'TCX_CE_ERR_STATUS_HI__ECC__SHIFT', + 'TCX_CE_ERR_STATUS_HI__ERROR_INFO_MASK', + 'TCX_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK', + 'TCX_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT', + 'TCX_CE_ERR_STATUS_HI__ERROR_INFO__SHIFT', + 'TCX_CE_ERR_STATUS_HI__POISON_MASK', + 'TCX_CE_ERR_STATUS_HI__POISON__SHIFT', + 'TCX_CE_ERR_STATUS_LO__ADDRESS_MASK', + 'TCX_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'TCX_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'TCX_CE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'TCX_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'TCX_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'TCX_CE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'TCX_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'TCX_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK', + 'TCX_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK', + 'TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT', + 'TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK', + 'TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT', + 'TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK', + 'TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT', + 'TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK', + 'TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT', + 'TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK', + 'TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT', + 'TCX_CTRL__TCX_TCC_FGCG_DISABLE_MASK', + 'TCX_CTRL__TCX_TCC_FGCG_DISABLE__SHIFT', + 'TCX_CTRL__TCX_TCR_FGCG_DISABLE_MASK', + 'TCX_CTRL__TCX_TCR_FGCG_DISABLE__SHIFT', + 'TCX_CTRL__TCX_TCX_FGCG_DISABLE_MASK', + 'TCX_CTRL__TCX_TCX_FGCG_DISABLE__SHIFT', + 'TCX_DSM_CNTL2__INJECT_DELAY_MASK', + 'TCX_DSM_CNTL2__INJECT_DELAY__SHIFT', + 'TCX_DSM_CNTL2__SED_ENABLE_ERROR_INJECT_MASK', + 'TCX_DSM_CNTL2__SED_ENABLE_ERROR_INJECT__SHIFT', + 'TCX_DSM_CNTL2__SED_SELECT_INJECT_DELAY_MASK', + 'TCX_DSM_CNTL2__SED_SELECT_INJECT_DELAY__SHIFT', + 'TCX_DSM_CNTL__GROUP0_SED_IRRITATOR_DATA_SEL_MASK', + 'TCX_DSM_CNTL__GROUP0_SED_IRRITATOR_DATA_SEL__SHIFT', + 'TCX_DSM_CNTL__GROUP10_SED_IRRITATOR_DATA_SEL_MASK', + 'TCX_DSM_CNTL__GROUP10_SED_IRRITATOR_DATA_SEL__SHIFT', + 'TCX_DSM_CNTL__GROUP13_SED_IRRITATOR_DATA_SEL_MASK', + 'TCX_DSM_CNTL__GROUP13_SED_IRRITATOR_DATA_SEL__SHIFT', + 'TCX_DSM_CNTL__GROUP14_SED_IRRITATOR_DATA_SEL_MASK', + 'TCX_DSM_CNTL__GROUP14_SED_IRRITATOR_DATA_SEL__SHIFT', + 'TCX_DSM_CNTL__GROUP1_SED_IRRITATOR_DATA_SEL_MASK', + 'TCX_DSM_CNTL__GROUP1_SED_IRRITATOR_DATA_SEL__SHIFT', + 'TCX_DSM_CNTL__GROUP2_SED_IRRITATOR_DATA_SEL_MASK', + 'TCX_DSM_CNTL__GROUP2_SED_IRRITATOR_DATA_SEL__SHIFT', + 'TCX_DSM_CNTL__GROUP4_SED_IRRITATOR_DATA_SEL_MASK', + 'TCX_DSM_CNTL__GROUP4_SED_IRRITATOR_DATA_SEL__SHIFT', + 'TCX_DSM_CNTL__GROUP5_SED_IRRITATOR_DATA_SEL_MASK', + 'TCX_DSM_CNTL__GROUP5_SED_IRRITATOR_DATA_SEL__SHIFT', + 'TCX_DSM_CNTL__GROUP6_SED_IRRITATOR_DATA_SEL_MASK', + 'TCX_DSM_CNTL__GROUP6_SED_IRRITATOR_DATA_SEL__SHIFT', + 'TCX_DSM_CNTL__GROUP8_SED_IRRITATOR_DATA_SEL_MASK', + 'TCX_DSM_CNTL__GROUP8_SED_IRRITATOR_DATA_SEL__SHIFT', + 'TCX_DSM_CNTL__GROUP9_SED_IRRITATOR_DATA_SEL_MASK', + 'TCX_DSM_CNTL__GROUP9_SED_IRRITATOR_DATA_SEL__SHIFT', + 'TCX_DSM_CNTL__SED_IRRITATOR_SINGLE_WRITE_MASK', + 'TCX_DSM_CNTL__SED_IRRITATOR_SINGLE_WRITE__SHIFT', + 'TCX_UE_ERR_STATUS_HI__ECC_MASK', + 'TCX_UE_ERR_STATUS_HI__ECC__SHIFT', + 'TCX_UE_ERR_STATUS_HI__ERROR_INFO_MASK', + 'TCX_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK', + 'TCX_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT', + 'TCX_UE_ERR_STATUS_HI__ERROR_INFO__SHIFT', + 'TCX_UE_ERR_STATUS_HI__FED_CNT_MASK', + 'TCX_UE_ERR_STATUS_HI__FED_CNT__SHIFT', + 'TCX_UE_ERR_STATUS_HI__PARITY_MASK', + 'TCX_UE_ERR_STATUS_HI__PARITY__SHIFT', + 'TCX_UE_ERR_STATUS_HI__UE_CNT_MASK', + 'TCX_UE_ERR_STATUS_HI__UE_CNT__SHIFT', + 'TCX_UE_ERR_STATUS_LO__ADDRESS_MASK', + 'TCX_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'TCX_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'TCX_UE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'TCX_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'TCX_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'TCX_UE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'TCX_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK', + 'TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK', + 'TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_0_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_10_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_11_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_12_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_13_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_14_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_15_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_16_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_17_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_18_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_19_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_1_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_20_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_21_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_22_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_23_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_24_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_25_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_26_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_27_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_28_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_29_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_2_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_30_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_31_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_3_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_4_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_5_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_6_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_7_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_8_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT', + 'TC_CFG_L1_STORE_POLICY__POLICY_9_MASK', + 'TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT', + 'TC_CFG_L1_VOLATILE__VOL_MASK', 'TC_CFG_L1_VOLATILE__VOL__SHIFT', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK', + 'TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK', + 'TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK', + 'TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT', + 'TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK', + 'TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT', + 'TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK', + 'TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT', + 'TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK', + 'TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT', + 'TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK', + 'TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT', + 'TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK', + 'TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT', + 'TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK', + 'TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT', + 'TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK', + 'TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT', + 'TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK', + 'TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT', + 'TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK', + 'TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT', + 'TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK', + 'TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT', + 'TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK', + 'TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT', + 'TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK', + 'TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT', + 'TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK', + 'TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT', + 'TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK', + 'TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT', + 'TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK', + 'TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT', + 'TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK', + 'TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT', + 'TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK', + 'TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT', + 'TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK', + 'TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT', + 'TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK', + 'TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT', + 'TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK', + 'TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT', + 'TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK', + 'TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT', + 'TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK', + 'TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT', + 'TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK', + 'TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT', + 'TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK', + 'TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT', + 'TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK', + 'TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT', + 'TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK', + 'TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT', + 'TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK', + 'TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT', + 'TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK', + 'TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT', + 'TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK', + 'TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT', + 'TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK', + 'TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT', + 'TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK', + 'TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT', + 'TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK', + 'TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT', + 'TC_CFG_L2_VOLATILE__VOL_MASK', 'TC_CFG_L2_VOLATILE__VOL__SHIFT', + 'TD_CE_EDC_HI__CE_CNT_MASK', 'TD_CE_EDC_HI__CE_CNT__SHIFT', + 'TD_CE_EDC_HI__ECC_MASK', 'TD_CE_EDC_HI__ECC__SHIFT', + 'TD_CE_EDC_HI__ERR_INFO_MASK', + 'TD_CE_EDC_HI__ERR_INFO_VALID_FLAG_MASK', + 'TD_CE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'TD_CE_EDC_HI__ERR_INFO__SHIFT', 'TD_CE_EDC_HI__POISON_MASK', + 'TD_CE_EDC_HI__POISON__SHIFT', + 'TD_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK', + 'TD_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT', + 'TD_CE_EDC_LO__ADDRESS_MASK', 'TD_CE_EDC_LO__ADDRESS__SHIFT', + 'TD_CE_EDC_LO__MEM_ID_MASK', 'TD_CE_EDC_LO__MEM_ID__SHIFT', + 'TD_CE_EDC_LO__STATUS_VALID_FLAG_MASK', + 'TD_CE_EDC_LO__STATUS_VALID_FLAG__SHIFT', + 'TD_CGTT_CTRL__OFF_HYSTERESIS_MASK', + 'TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT', + 'TD_CGTT_CTRL__ON_DELAY_MASK', 'TD_CGTT_CTRL__ON_DELAY__SHIFT', + 'TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK', + 'TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT', + 'TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK', + 'TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT', + 'TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK', + 'TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT', + 'TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK', + 'TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT', + 'TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK', + 'TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT', + 'TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK', + 'TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT', + 'TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK', + 'TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT', + 'TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK', + 'TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT', + 'TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK', + 'TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT', + 'TD_CNTL__DISABLE_POWER_THROTTLE_MASK', + 'TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT', + 'TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK', + 'TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT', + 'TD_CNTL__EXTEND_LDS_STALL_MASK', + 'TD_CNTL__EXTEND_LDS_STALL__SHIFT', + 'TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK', + 'TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT', + 'TD_CNTL__RFGCG_CHICKEN_MASK', 'TD_CNTL__RFGCG_CHICKEN__SHIFT', + 'TD_CNTL__SRAM_FGCG_TD_KCLARR_LG_MASK', + 'TD_CNTL__SRAM_FGCG_TD_KCLARR_LG__SHIFT', + 'TD_CNTL__SYNC_PHASE_SH_MASK', 'TD_CNTL__SYNC_PHASE_SH__SHIFT', + 'TD_CNTL__TD_IN_CAC_CHICKENBITS_MASK', + 'TD_CNTL__TD_IN_CAC_CHICKENBITS__SHIFT', + 'TD_CNTL__TD_OUT_CAC_CHICKENBITS_MASK', + 'TD_CNTL__TD_OUT_CAC_CHICKENBITS__SHIFT', + 'TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK', + 'TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT', + 'TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK', + 'TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT', + 'TD_DSM_CNTL2__TD_INJECT_DELAY_MASK', + 'TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT', + 'TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK', + 'TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT', + 'TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK', + 'TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT', + 'TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK', + 'TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT', + 'TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK', + 'TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT', + 'TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK', + 'TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT', + 'TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK', + 'TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT', + 'TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK', + 'TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT', + 'TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK', + 'TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT', + 'TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK', + 'TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT', + 'TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK', + 'TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT', + 'TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'TD_POWER_CNTL__MGCG_OUTPUTSTAGE_MASK', + 'TD_POWER_CNTL__MGCG_OUTPUTSTAGE__SHIFT', + 'TD_POWER_CNTL__MID0_THREAD_DATA_MASK', + 'TD_POWER_CNTL__MID0_THREAD_DATA__SHIFT', + 'TD_POWER_CNTL__MID2_ACCUM_DATA_MASK', + 'TD_POWER_CNTL__MID2_ACCUM_DATA__SHIFT', + 'TD_SCRATCH__SCRATCH_MASK', 'TD_SCRATCH__SCRATCH__SHIFT', + 'TD_STATUS__BUSY_MASK', 'TD_STATUS__BUSY__SHIFT', + 'TD_UE_EDC_HI__ECC_MASK', 'TD_UE_EDC_HI__ECC__SHIFT', + 'TD_UE_EDC_HI__ERR_INFO_MASK', + 'TD_UE_EDC_HI__ERR_INFO_VALID_FLAG_MASK', + 'TD_UE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'TD_UE_EDC_HI__ERR_INFO__SHIFT', 'TD_UE_EDC_HI__FED_CNT_MASK', + 'TD_UE_EDC_HI__FED_CNT__SHIFT', 'TD_UE_EDC_HI__PARITY_MASK', + 'TD_UE_EDC_HI__PARITY__SHIFT', 'TD_UE_EDC_HI__UE_CNT_MASK', + 'TD_UE_EDC_HI__UE_CNT__SHIFT', + 'TD_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK', + 'TD_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT', + 'TD_UE_EDC_LO__ADDRESS_MASK', 'TD_UE_EDC_LO__ADDRESS__SHIFT', + 'TD_UE_EDC_LO__MEM_ID_MASK', 'TD_UE_EDC_LO__MEM_ID__SHIFT', + 'TD_UE_EDC_LO__STATUS_VALID_FLAG_MASK', + 'TD_UE_EDC_LO__STATUS_VALID_FLAG__SHIFT', + 'UTCL2_CE_ERR_STATUS_HI__CE_CNT_MASK', + 'UTCL2_CE_ERR_STATUS_HI__CE_CNT__SHIFT', + 'UTCL2_CE_ERR_STATUS_HI__ECC_MASK', + 'UTCL2_CE_ERR_STATUS_HI__ECC__SHIFT', + 'UTCL2_CE_ERR_STATUS_HI__ERR_INFO_MASK', + 'UTCL2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'UTCL2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'UTCL2_CE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'UTCL2_CE_ERR_STATUS_HI__OTHER_MASK', + 'UTCL2_CE_ERR_STATUS_HI__OTHER__SHIFT', + 'UTCL2_CE_ERR_STATUS_HI__POISON_MASK', + 'UTCL2_CE_ERR_STATUS_HI__POISON__SHIFT', + 'UTCL2_CE_ERR_STATUS_HI__RESERVED_MASK', + 'UTCL2_CE_ERR_STATUS_HI__RESERVED__SHIFT', + 'UTCL2_CE_ERR_STATUS_LO__ADDRESS_MASK', + 'UTCL2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'UTCL2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'UTCL2_CE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'UTCL2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'UTCL2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'UTCL2_CE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'UTCL2_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK', + 'UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT', + 'UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK', + 'UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT', + 'UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK', + 'UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT', + 'UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK', + 'UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT', + 'UTCL2_EDC_CONFIG__DIS_EDC_MASK', + 'UTCL2_EDC_CONFIG__DIS_EDC__SHIFT', + 'UTCL2_EDC_CONFIG__WRITE_DIS_MASK', + 'UTCL2_EDC_CONFIG__WRITE_DIS__SHIFT', + 'UTCL2_EDC_MODE__BYPASS_MASK', 'UTCL2_EDC_MODE__BYPASS__SHIFT', + 'UTCL2_EDC_MODE__COUNT_FED_OUT_MASK', + 'UTCL2_EDC_MODE__COUNT_FED_OUT__SHIFT', + 'UTCL2_EDC_MODE__DED_MODE_MASK', + 'UTCL2_EDC_MODE__DED_MODE__SHIFT', + 'UTCL2_EDC_MODE__FORCE_SEC_ON_DED_MASK', + 'UTCL2_EDC_MODE__FORCE_SEC_ON_DED__SHIFT', + 'UTCL2_EDC_MODE__GATE_FUE_MASK', + 'UTCL2_EDC_MODE__GATE_FUE__SHIFT', + 'UTCL2_EDC_MODE__PROP_FED_MASK', + 'UTCL2_EDC_MODE__PROP_FED__SHIFT', + 'UTCL2_MEM_ECC_CNTL__DED_COUNT_MASK', + 'UTCL2_MEM_ECC_CNTL__DED_COUNT__SHIFT', + 'UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK', + 'UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT', + 'UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK', + 'UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT', + 'UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK', + 'UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT', + 'UTCL2_MEM_ECC_CNTL__INJECT_DELAY_MASK', + 'UTCL2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT', + 'UTCL2_MEM_ECC_CNTL__SEC_COUNT_MASK', + 'UTCL2_MEM_ECC_CNTL__SEC_COUNT__SHIFT', + 'UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK', + 'UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT', + 'UTCL2_MEM_ECC_CNTL__TEST_FUE_MASK', + 'UTCL2_MEM_ECC_CNTL__TEST_FUE__SHIFT', + 'UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK', + 'UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT', + 'UTCL2_MEM_ECC_INDEX__INDEX_MASK', + 'UTCL2_MEM_ECC_INDEX__INDEX__SHIFT', + 'UTCL2_MEM_ECC_STATUS__FED_MASK', + 'UTCL2_MEM_ECC_STATUS__FED__SHIFT', + 'UTCL2_MEM_ECC_STATUS__UCE_MASK', + 'UTCL2_MEM_ECC_STATUS__UCE__SHIFT', + 'UTCL2_UE_ERR_STATUS_HI__ECC_MASK', + 'UTCL2_UE_ERR_STATUS_HI__ECC__SHIFT', + 'UTCL2_UE_ERR_STATUS_HI__ERR_INFO_MASK', + 'UTCL2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'UTCL2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'UTCL2_UE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'UTCL2_UE_ERR_STATUS_HI__FED_CNT_MASK', + 'UTCL2_UE_ERR_STATUS_HI__FED_CNT__SHIFT', + 'UTCL2_UE_ERR_STATUS_HI__PARITY_MASK', + 'UTCL2_UE_ERR_STATUS_HI__PARITY__SHIFT', + 'UTCL2_UE_ERR_STATUS_HI__RESERVED_MASK', + 'UTCL2_UE_ERR_STATUS_HI__RESERVED__SHIFT', + 'UTCL2_UE_ERR_STATUS_HI__UE_CNT_MASK', + 'UTCL2_UE_ERR_STATUS_HI__UE_CNT__SHIFT', + 'UTCL2_UE_ERR_STATUS_LO__ADDRESS_MASK', + 'UTCL2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'UTCL2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'UTCL2_UE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'UTCL2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'UTCL2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'UTCL2_UE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'UTCL2_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK', + 'UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT', + 'VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK', + 'VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT', + 'VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK', + 'VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT', + 'VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK', + 'VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT', + 'VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK', + 'VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT', + 'VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK', + 'VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT', + 'VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK', + 'VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT', + 'VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK', + 'VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT', + 'VGT_CACHE_INVALIDATION__ES_LIMIT_MASK', + 'VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT', + 'VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK', + 'VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT', + 'VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK', + 'VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT', + 'VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK', + 'VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT', + 'VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK', + 'VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT', + 'VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK', + 'VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT', + 'VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK', + 'VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT', + 'VGT_CNTL_STATUS__VGT_BUSY_MASK', + 'VGT_CNTL_STATUS__VGT_BUSY__SHIFT', + 'VGT_CNTL_STATUS__VGT_GS_BUSY_MASK', + 'VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT', + 'VGT_CNTL_STATUS__VGT_HS_BUSY_MASK', + 'VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT', + 'VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK', + 'VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT', + 'VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK', + 'VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT', + 'VGT_CNTL_STATUS__VGT_PI_BUSY_MASK', + 'VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT', + 'VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK', + 'VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT', + 'VGT_CNTL_STATUS__VGT_PT_BUSY_MASK', + 'VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT', + 'VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK', + 'VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT', + 'VGT_CNTL_STATUS__VGT_TE_BUSY_MASK', + 'VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT', + 'VGT_CNTL_STATUS__VGT_VR_BUSY_MASK', + 'VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT', + 'VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK', + 'VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT', + 'VGT_DMA_BASE_HI__BASE_ADDR_MASK', + 'VGT_DMA_BASE_HI__BASE_ADDR__SHIFT', + 'VGT_DMA_BASE__BASE_ADDR_MASK', 'VGT_DMA_BASE__BASE_ADDR__SHIFT', + 'VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK', + 'VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT', + 'VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK', + 'VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT', + 'VGT_DMA_CONTROL__HW_USE_ONLY_MASK', + 'VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT', + 'VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK', + 'VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT', + 'VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK', + 'VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT', + 'VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK', + 'VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT', + 'VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK', + 'VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT', + 'VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK', + 'VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT', + 'VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK', + 'VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT', + 'VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK', + 'VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT', + 'VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK', + 'VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT', + 'VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK', + 'VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT', + 'VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK', + 'VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT', + 'VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK', + 'VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT', + 'VGT_DMA_INDEX_TYPE__NOT_EOP_MASK', + 'VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT', + 'VGT_DMA_INDEX_TYPE__PRIMGEN_EN_MASK', + 'VGT_DMA_INDEX_TYPE__PRIMGEN_EN__SHIFT', + 'VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK', + 'VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT', + 'VGT_DMA_INDEX_TYPE__REQ_PATH_MASK', + 'VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT', + 'VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK', + 'VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT', + 'VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK', + 'VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT', + 'VGT_DMA_MAX_SIZE__MAX_SIZE_MASK', + 'VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT', + 'VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK', + 'VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT', + 'VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK', + 'VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT', + 'VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK', + 'VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT', + 'VGT_DMA_SIZE__NUM_INDICES_MASK', + 'VGT_DMA_SIZE__NUM_INDICES__SHIFT', + 'VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK', + 'VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT', + 'VGT_DRAW_INITIATOR__MAJOR_MODE_MASK', + 'VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT', + 'VGT_DRAW_INITIATOR__NOT_EOP_MASK', + 'VGT_DRAW_INITIATOR__NOT_EOP__SHIFT', + 'VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK', + 'VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT', + 'VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK', + 'VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT', + 'VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK', + 'VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT', + 'VGT_DRAW_INITIATOR__UNROLLED_INST_MASK', + 'VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT', + 'VGT_DRAW_INITIATOR__USE_OPAQUE_MASK', + 'VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT', + 'VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK', + 'VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT', + 'VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK', + 'VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID__SHIFT', + 'VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK', + 'VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT', + 'VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK', + 'VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT', + 'VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK', + 'VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT', + 'VGT_ENHANCE__MISC_MASK', 'VGT_ENHANCE__MISC__SHIFT', + 'VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK', + 'VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT', + 'VGT_ES_PER_GS__ES_PER_GS_MASK', + 'VGT_ES_PER_GS__ES_PER_GS__SHIFT', + 'VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK', + 'VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT', + 'VGT_EVENT_INITIATOR__ADDRESS_HI_MASK', + 'VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT', + 'VGT_EVENT_INITIATOR__EVENT_TYPE_MASK', + 'VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT', + 'VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK', + 'VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT', + 'VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK', + 'VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT', + 'VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK', + 'VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT', + 'VGT_FIFO_DEPTHS__RESERVED_0_MASK', + 'VGT_FIFO_DEPTHS__RESERVED_0__SHIFT', + 'VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK', + 'VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT', + 'VGT_GROUP_DECR__DECR_MASK', 'VGT_GROUP_DECR__DECR__SHIFT', + 'VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK', + 'VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT', + 'VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK', + 'VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT', + 'VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK', + 'VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT', + 'VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK', + 'VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT', + 'VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK', + 'VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT', + 'VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK', + 'VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT', + 'VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK', + 'VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT', + 'VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK', + 'VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT', + 'VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK', + 'VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT', + 'VGT_GROUP_VECT_0_CNTL__SHIFT_MASK', + 'VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT', + 'VGT_GROUP_VECT_0_CNTL__STRIDE_MASK', + 'VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT', + 'VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK', + 'VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT', + 'VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK', + 'VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT', + 'VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK', + 'VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT', + 'VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK', + 'VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT', + 'VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK', + 'VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT', + 'VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK', + 'VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT', + 'VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK', + 'VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT', + 'VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK', + 'VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT', + 'VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK', + 'VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT', + 'VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK', + 'VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT', + 'VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK', + 'VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT', + 'VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK', + 'VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT', + 'VGT_GROUP_VECT_1_CNTL__SHIFT_MASK', + 'VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT', + 'VGT_GROUP_VECT_1_CNTL__STRIDE_MASK', + 'VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT', + 'VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK', + 'VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT', + 'VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK', + 'VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT', + 'VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK', + 'VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT', + 'VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK', + 'VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT', + 'VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK', + 'VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT', + 'VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK', + 'VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT', + 'VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK', + 'VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT', + 'VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK', + 'VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT', + 'VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK', + 'VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT', + 'VGT_GSVS_RING_OFFSET_1__OFFSET_MASK', + 'VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT', + 'VGT_GSVS_RING_OFFSET_2__OFFSET_MASK', + 'VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT', + 'VGT_GSVS_RING_OFFSET_3__OFFSET_MASK', + 'VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT', + 'VGT_GSVS_RING_SIZE__MEM_SIZE_MASK', + 'VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT', + 'VGT_GS_INSTANCE_CNT__CNT_MASK', + 'VGT_GS_INSTANCE_CNT__CNT__SHIFT', + 'VGT_GS_INSTANCE_CNT__ENABLE_MASK', + 'VGT_GS_INSTANCE_CNT__ENABLE__SHIFT', + 'VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP_MASK', + 'VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP__SHIFT', + 'VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK', + 'VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT', + 'VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK', + 'VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT', + 'VGT_GS_MODE__CUT_MODE_MASK', 'VGT_GS_MODE__CUT_MODE__SHIFT', + 'VGT_GS_MODE__ES_PASSTHRU_MASK', + 'VGT_GS_MODE__ES_PASSTHRU__SHIFT', + 'VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK', + 'VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT', + 'VGT_GS_MODE__GS_C_PACK_EN_MASK', + 'VGT_GS_MODE__GS_C_PACK_EN__SHIFT', + 'VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK', + 'VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT', 'VGT_GS_MODE__MODE_MASK', + 'VGT_GS_MODE__MODE__SHIFT', 'VGT_GS_MODE__ONCHIP_MASK', + 'VGT_GS_MODE__ONCHIP__SHIFT', + 'VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK', + 'VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT', + 'VGT_GS_MODE__RESERVED_0_MASK', 'VGT_GS_MODE__RESERVED_0__SHIFT', + 'VGT_GS_MODE__RESERVED_1_MASK', 'VGT_GS_MODE__RESERVED_1__SHIFT', + 'VGT_GS_MODE__RESERVED_2_MASK', 'VGT_GS_MODE__RESERVED_2__SHIFT', + 'VGT_GS_MODE__RESERVED_3_MASK', 'VGT_GS_MODE__RESERVED_3__SHIFT', + 'VGT_GS_MODE__RESERVED_4_MASK', 'VGT_GS_MODE__RESERVED_4__SHIFT', + 'VGT_GS_MODE__RESERVED_5_MASK', 'VGT_GS_MODE__RESERVED_5__SHIFT', + 'VGT_GS_MODE__SUPPRESS_CUTS_MASK', + 'VGT_GS_MODE__SUPPRESS_CUTS__SHIFT', + 'VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK', + 'VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT', + 'VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK', + 'VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT', + 'VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK', + 'VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT', + 'VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK', + 'VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT', + 'VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK', + 'VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT', + 'VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK', + 'VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT', + 'VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK', + 'VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT', + 'VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK', + 'VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT', + 'VGT_GS_PER_ES__GS_PER_ES_MASK', + 'VGT_GS_PER_ES__GS_PER_ES__SHIFT', + 'VGT_GS_PER_VS__GS_PER_VS_MASK', + 'VGT_GS_PER_VS__GS_PER_VS__SHIFT', + 'VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK', + 'VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT', + 'VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK', + 'VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT', + 'VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK', + 'VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT', + 'VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK', + 'VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT', + 'VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK', + 'VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT', + 'VGT_HOS_CNTL__TESS_MODE_MASK', 'VGT_HOS_CNTL__TESS_MODE__SHIFT', + 'VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK', + 'VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT', + 'VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK', + 'VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT', + 'VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK', + 'VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT', + 'VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK', + 'VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT', + 'VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK', + 'VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT', + 'VGT_IMMED_DATA__DATA_MASK', 'VGT_IMMED_DATA__DATA__SHIFT', + 'VGT_INDEX_TYPE__INDEX_TYPE_MASK', + 'VGT_INDEX_TYPE__INDEX_TYPE__SHIFT', + 'VGT_INDEX_TYPE__PRIMGEN_EN_MASK', + 'VGT_INDEX_TYPE__PRIMGEN_EN__SHIFT', + 'VGT_INDX_OFFSET__INDX_OFFSET_MASK', + 'VGT_INDX_OFFSET__INDX_OFFSET__SHIFT', + 'VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK', + 'VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT', + 'VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK', + 'VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT', + 'VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK', + 'VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT', + 'VGT_LAST_COPY_STATE__DST_STATE_ID_MASK', + 'VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT', + 'VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK', + 'VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT', + 'VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK', + 'VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT', + 'VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK', + 'VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT', + 'VGT_LS_HS_CONFIG__NUM_PATCHES_MASK', + 'VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT', + 'VGT_MAX_VTX_INDX__MAX_INDX_MASK', + 'VGT_MAX_VTX_INDX__MAX_INDX__SHIFT', + 'VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK', + 'VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT', + 'VGT_MIN_VTX_INDX__MIN_INDX_MASK', + 'VGT_MIN_VTX_INDX__MIN_INDX__SHIFT', + 'VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK', + 'VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT', + 'VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK', + 'VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT', + 'VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK', + 'VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT', + 'VGT_NUM_INDICES__NUM_INDICES_MASK', + 'VGT_NUM_INDICES__NUM_INDICES__SHIFT', + 'VGT_NUM_INSTANCES__NUM_INSTANCES_MASK', + 'VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT', + 'VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK', + 'VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT', + 'VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK', + 'VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT', + 'VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK', + 'VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT', + 'VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK', + 'VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT', + 'VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK', + 'VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT', + 'VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK', + 'VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT', + 'VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK', + 'VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT', + 'VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK', + 'VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT', + 'VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK', + 'VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT', + 'VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK', + 'VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT', + 'VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK', + 'VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT', + 'VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK', + 'VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT', + 'VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK', + 'VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT', + 'VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK', + 'VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT', + 'VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK', + 'VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT', + 'VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK', + 'VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT', + 'VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK', + 'VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT', + 'VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK', + 'VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT', + 'VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK', + 'VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT', + 'VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK', + 'VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT', + 'VGT_PRIMITIVEID_RESET__VALUE_MASK', + 'VGT_PRIMITIVEID_RESET__VALUE__SHIFT', + 'VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK', + 'VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT', + 'VGT_RESET_DEBUG__GS_DISABLE_MASK', + 'VGT_RESET_DEBUG__GS_DISABLE__SHIFT', + 'VGT_RESET_DEBUG__TESS_DISABLE_MASK', + 'VGT_RESET_DEBUG__TESS_DISABLE__SHIFT', + 'VGT_RESET_DEBUG__WD_DISABLE_MASK', + 'VGT_RESET_DEBUG__WD_DISABLE__SHIFT', + 'VGT_REUSE_OFF__REUSE_OFF_MASK', + 'VGT_REUSE_OFF__REUSE_OFF__SHIFT', + 'VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK', + 'VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT', + 'VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK', + 'VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT', + 'VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK', + 'VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT', + 'VGT_SHADER_STAGES_EN__ES_EN_MASK', + 'VGT_SHADER_STAGES_EN__ES_EN__SHIFT', + 'VGT_SHADER_STAGES_EN__GS_EN_MASK', + 'VGT_SHADER_STAGES_EN__GS_EN__SHIFT', + 'VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK', + 'VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT', + 'VGT_SHADER_STAGES_EN__HS_EN_MASK', + 'VGT_SHADER_STAGES_EN__HS_EN__SHIFT', + 'VGT_SHADER_STAGES_EN__LS_EN_MASK', + 'VGT_SHADER_STAGES_EN__LS_EN__SHIFT', + 'VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK', + 'VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT', + 'VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK', + 'VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT', + 'VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK', + 'VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT', + 'VGT_SHADER_STAGES_EN__VS_EN_MASK', + 'VGT_SHADER_STAGES_EN__VS_EN__SHIFT', + 'VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK', + 'VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT', + 'VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK', + 'VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT', + 'VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK', + 'VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT', + 'VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK', + 'VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT', + 'VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK', + 'VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT', + 'VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK', + 'VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT', + 'VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK', + 'VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT', + 'VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK', + 'VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT', + 'VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK', + 'VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT', + 'VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK', + 'VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT', + 'VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK', + 'VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT', + 'VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK', + 'VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT', + 'VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK', + 'VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT', + 'VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK', + 'VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT', + 'VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK', + 'VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT', + 'VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK', + 'VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT', + 'VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK', + 'VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT', + 'VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK', + 'VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT', + 'VGT_STRMOUT_CONFIG__RAST_STREAM_MASK', + 'VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK', + 'VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT', + 'VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT', + 'VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK', + 'VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT', + 'VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK', + 'VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT', + 'VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK', + 'VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT', + 'VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK', + 'VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT', + 'VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK', + 'VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT', + 'VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK', + 'VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT', + 'VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK', + 'VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT', + 'VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK', + 'VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT', + 'VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK', + 'VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT', + 'VGT_STRMOUT_DELAY__SKIP_DELAY_MASK', + 'VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT', + 'VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK', + 'VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT', + 'VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK', + 'VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT', + 'VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK', + 'VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT', + 'VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK', + 'VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT', + 'VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK', + 'VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT', + 'VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK', + 'VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT', + 'VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK', + 'VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT', + 'VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK', + 'VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT', + 'VGT_SYS_CONFIG__DUAL_CORE_EN_MASK', + 'VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT', + 'VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK', + 'VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT', + 'VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK', + 'VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT', + 'VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK', + 'VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT', + 'VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK', + 'VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT', + 'VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK', + 'VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT', + 'VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK', + 'VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT', + 'VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK', + 'VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT', + 'VGT_TF_MEMORY_BASE__BASE_MASK', + 'VGT_TF_MEMORY_BASE__BASE__SHIFT', + 'VGT_TF_PARAM__DEPRECATED_MASK', + 'VGT_TF_PARAM__DEPRECATED__SHIFT', + 'VGT_TF_PARAM__DISABLE_DONUTS_MASK', + 'VGT_TF_PARAM__DISABLE_DONUTS__SHIFT', + 'VGT_TF_PARAM__DISTRIBUTION_MODE_MASK', + 'VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT', + 'VGT_TF_PARAM__PARTITIONING_MASK', + 'VGT_TF_PARAM__PARTITIONING__SHIFT', + 'VGT_TF_PARAM__RDREQ_POLICY_MASK', + 'VGT_TF_PARAM__RDREQ_POLICY__SHIFT', + 'VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK', + 'VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT', + 'VGT_TF_PARAM__TOPOLOGY_MASK', 'VGT_TF_PARAM__TOPOLOGY__SHIFT', + 'VGT_TF_PARAM__TYPE_MASK', 'VGT_TF_PARAM__TYPE__SHIFT', + 'VGT_TF_RING_SIZE__SIZE_MASK', 'VGT_TF_RING_SIZE__SIZE__SHIFT', + 'VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK', + 'VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT', + 'VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK', + 'VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT', + 'VGT_VTX_CNT_EN__VTX_CNT_EN_MASK', + 'VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT', + 'VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK', + 'VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT', + 'VIOLATION_DATA_ASYNC_VF_PROG__SSRCID_MASK', + 'VIOLATION_DATA_ASYNC_VF_PROG__SSRCID__SHIFT', + 'VIOLATION_DATA_ASYNC_VF_PROG__VFID_MASK', + 'VIOLATION_DATA_ASYNC_VF_PROG__VFID__SHIFT', + 'VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR_MASK', + 'VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR__SHIFT', + 'VML2_CE_ERR_STATUS_HI__CE_CNT_MASK', + 'VML2_CE_ERR_STATUS_HI__CE_CNT__SHIFT', + 'VML2_CE_ERR_STATUS_HI__ECC_MASK', + 'VML2_CE_ERR_STATUS_HI__ECC__SHIFT', + 'VML2_CE_ERR_STATUS_HI__ERR_INFO_MASK', + 'VML2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'VML2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'VML2_CE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'VML2_CE_ERR_STATUS_HI__OTHER_MASK', + 'VML2_CE_ERR_STATUS_HI__OTHER__SHIFT', + 'VML2_CE_ERR_STATUS_HI__POISON_MASK', + 'VML2_CE_ERR_STATUS_HI__POISON__SHIFT', + 'VML2_CE_ERR_STATUS_HI__RESERVED_MASK', + 'VML2_CE_ERR_STATUS_HI__RESERVED__SHIFT', + 'VML2_CE_ERR_STATUS_LO__ADDRESS_MASK', + 'VML2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'VML2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'VML2_CE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'VML2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'VML2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'VML2_CE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'VML2_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'VML2_MEM_ECC_CNTL__DED_COUNT_MASK', + 'VML2_MEM_ECC_CNTL__DED_COUNT__SHIFT', + 'VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK', + 'VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT', + 'VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK', + 'VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT', + 'VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK', + 'VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT', + 'VML2_MEM_ECC_CNTL__INJECT_DELAY_MASK', + 'VML2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT', + 'VML2_MEM_ECC_CNTL__SEC_COUNT_MASK', + 'VML2_MEM_ECC_CNTL__SEC_COUNT__SHIFT', + 'VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK', + 'VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT', + 'VML2_MEM_ECC_CNTL__TEST_FUE_MASK', + 'VML2_MEM_ECC_CNTL__TEST_FUE__SHIFT', + 'VML2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK', + 'VML2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT', + 'VML2_MEM_ECC_INDEX__INDEX_MASK', + 'VML2_MEM_ECC_INDEX__INDEX__SHIFT', + 'VML2_MEM_ECC_STATUS__FED_MASK', + 'VML2_MEM_ECC_STATUS__FED__SHIFT', + 'VML2_MEM_ECC_STATUS__UCE_MASK', + 'VML2_MEM_ECC_STATUS__UCE__SHIFT', + 'VML2_UE_ERR_STATUS_HI__ECC_MASK', + 'VML2_UE_ERR_STATUS_HI__ECC__SHIFT', + 'VML2_UE_ERR_STATUS_HI__ERR_INFO_MASK', + 'VML2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'VML2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'VML2_UE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'VML2_UE_ERR_STATUS_HI__FED_CNT_MASK', + 'VML2_UE_ERR_STATUS_HI__FED_CNT__SHIFT', + 'VML2_UE_ERR_STATUS_HI__PARITY_MASK', + 'VML2_UE_ERR_STATUS_HI__PARITY__SHIFT', + 'VML2_UE_ERR_STATUS_HI__RESERVED_MASK', + 'VML2_UE_ERR_STATUS_HI__RESERVED__SHIFT', + 'VML2_UE_ERR_STATUS_HI__UE_CNT_MASK', + 'VML2_UE_ERR_STATUS_HI__UE_CNT__SHIFT', + 'VML2_UE_ERR_STATUS_LO__ADDRESS_MASK', + 'VML2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'VML2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'VML2_UE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'VML2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'VML2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'VML2_UE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'VML2_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'VML2_WALKER_CE_ERR_STATUS_HI__CE_CNT_MASK', + 'VML2_WALKER_CE_ERR_STATUS_HI__CE_CNT__SHIFT', + 'VML2_WALKER_CE_ERR_STATUS_HI__ECC_MASK', + 'VML2_WALKER_CE_ERR_STATUS_HI__ECC__SHIFT', + 'VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO_MASK', + 'VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'VML2_WALKER_CE_ERR_STATUS_HI__OTHER_MASK', + 'VML2_WALKER_CE_ERR_STATUS_HI__OTHER__SHIFT', + 'VML2_WALKER_CE_ERR_STATUS_HI__POISON_MASK', + 'VML2_WALKER_CE_ERR_STATUS_HI__POISON__SHIFT', + 'VML2_WALKER_CE_ERR_STATUS_HI__RESERVED_MASK', + 'VML2_WALKER_CE_ERR_STATUS_HI__RESERVED__SHIFT', + 'VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS_MASK', + 'VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'VML2_WALKER_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'VML2_WALKER_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'VML2_WALKER_CE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'VML2_WALKER_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'VML2_WALKER_MEM_ECC_CNTL__DED_COUNT_MASK', + 'VML2_WALKER_MEM_ECC_CNTL__DED_COUNT__SHIFT', + 'VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK', + 'VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT', + 'VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK', + 'VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT', + 'VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK', + 'VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT', + 'VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY_MASK', + 'VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY__SHIFT', + 'VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT_MASK', + 'VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT__SHIFT', + 'VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK', + 'VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT', + 'VML2_WALKER_MEM_ECC_CNTL__TEST_FUE_MASK', + 'VML2_WALKER_MEM_ECC_CNTL__TEST_FUE__SHIFT', + 'VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS_MASK', + 'VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT', + 'VML2_WALKER_MEM_ECC_INDEX__INDEX_MASK', + 'VML2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT', + 'VML2_WALKER_MEM_ECC_STATUS__FED_MASK', + 'VML2_WALKER_MEM_ECC_STATUS__FED__SHIFT', + 'VML2_WALKER_MEM_ECC_STATUS__UCE_MASK', + 'VML2_WALKER_MEM_ECC_STATUS__UCE__SHIFT', + 'VML2_WALKER_UE_ERR_STATUS_HI__ECC_MASK', + 'VML2_WALKER_UE_ERR_STATUS_HI__ECC__SHIFT', + 'VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO_MASK', + 'VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK', + 'VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT', + 'VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO__SHIFT', + 'VML2_WALKER_UE_ERR_STATUS_HI__FED_CNT_MASK', + 'VML2_WALKER_UE_ERR_STATUS_HI__FED_CNT__SHIFT', + 'VML2_WALKER_UE_ERR_STATUS_HI__PARITY_MASK', + 'VML2_WALKER_UE_ERR_STATUS_HI__PARITY__SHIFT', + 'VML2_WALKER_UE_ERR_STATUS_HI__RESERVED_MASK', + 'VML2_WALKER_UE_ERR_STATUS_HI__RESERVED__SHIFT', + 'VML2_WALKER_UE_ERR_STATUS_HI__UE_CNT_MASK', + 'VML2_WALKER_UE_ERR_STATUS_HI__UE_CNT__SHIFT', + 'VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS_MASK', + 'VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK', + 'VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT', + 'VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS__SHIFT', + 'VML2_WALKER_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK', + 'VML2_WALKER_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT', + 'VML2_WALKER_UE_ERR_STATUS_LO__MEMORY_ID_MASK', + 'VML2_WALKER_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT', + 'VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK', + 'VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT', + 'VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK', + 'VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK', + 'VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK', + 'VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT', + 'VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK', + 'VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK', + 'VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK', + 'VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT', + 'VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK', + 'VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK', + 'VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK', + 'VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT', + 'VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK', + 'VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK', + 'VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK', + 'VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT', + 'VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK', + 'VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK', + 'VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK', + 'VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT', + 'VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK', + 'VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK', + 'VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK', + 'VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT', + 'VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK', + 'VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK', + 'VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK', + 'VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT', + 'VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK', + 'VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK', + 'VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK', + 'VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT', + 'VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK', + 'VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK', + 'VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK', + 'VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT', + 'VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK', + 'VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK', + 'VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK', + 'VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT', + 'VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK', + 'VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK', + 'VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK', + 'VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT', + 'VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK', + 'VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK', + 'VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK', + 'VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT', + 'VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK', + 'VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK', + 'VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK', + 'VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT', + 'VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK', + 'VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK', + 'VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK', + 'VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT', + 'VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK', + 'VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK', + 'VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK', + 'VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT', + 'VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK', + 'VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK', + 'VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK', + 'VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT', + 'VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK', + 'VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT', + 'VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK', + 'VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT', + 'VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK', + 'VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT', + 'VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK', + 'VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT', + 'VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK', + 'VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT', + 'VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK', + 'VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK', + 'VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT', + 'VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK', + 'VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT', + 'VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK', + 'VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK', + 'VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK', + 'VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK', + 'VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT', + 'VM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK', + 'VM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT', + 'VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK', + 'VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK', + 'VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT', + 'VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK', + 'VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT', + 'VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK', + 'VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK', + 'VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK', + 'VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK', + 'VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT', + 'VM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK', + 'VM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT', + 'VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK', + 'VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK', + 'VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT', + 'VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK', + 'VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT', + 'VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK', + 'VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK', + 'VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK', + 'VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK', + 'VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT', + 'VM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK', + 'VM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT', + 'VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK', + 'VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK', + 'VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT', + 'VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK', + 'VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT', + 'VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK', + 'VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK', + 'VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK', + 'VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK', + 'VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT', + 'VM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK', + 'VM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT', + 'VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK', + 'VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK', + 'VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT', + 'VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK', + 'VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT', + 'VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK', + 'VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK', + 'VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK', + 'VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK', + 'VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT', + 'VM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK', + 'VM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT', + 'VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK', + 'VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK', + 'VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT', + 'VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK', + 'VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT', + 'VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK', + 'VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK', + 'VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK', + 'VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK', + 'VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT', + 'VM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK', + 'VM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT', + 'VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK', + 'VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK', + 'VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT', + 'VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK', + 'VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT', + 'VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK', + 'VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK', + 'VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK', + 'VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK', + 'VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT', + 'VM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK', + 'VM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT', + 'VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK', + 'VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK', + 'VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT', + 'VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK', + 'VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT', + 'VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK', + 'VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK', + 'VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK', + 'VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK', + 'VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT', + 'VM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK', + 'VM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT', + 'VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK', + 'VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK', + 'VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT', + 'VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK', + 'VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT', + 'VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK', + 'VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK', + 'VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK', + 'VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK', + 'VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT', + 'VM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK', + 'VM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT', + 'VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK', + 'VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK', + 'VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT', + 'VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK', + 'VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT', + 'VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK', + 'VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK', + 'VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK', + 'VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK', + 'VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT', + 'VM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK', + 'VM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT', + 'VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK', + 'VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK', + 'VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT', + 'VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK', + 'VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT', + 'VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK', + 'VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK', + 'VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK', + 'VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK', + 'VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT', + 'VM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK', + 'VM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT', + 'VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK', + 'VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK', + 'VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT', + 'VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK', + 'VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT', + 'VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK', + 'VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK', + 'VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK', + 'VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK', + 'VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT', + 'VM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK', + 'VM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT', + 'VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK', + 'VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK', + 'VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT', + 'VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK', + 'VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT', + 'VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK', + 'VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK', + 'VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK', + 'VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK', + 'VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT', + 'VM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK', + 'VM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT', + 'VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK', + 'VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK', + 'VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT', + 'VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK', + 'VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT', + 'VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK', + 'VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK', + 'VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK', + 'VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK', + 'VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT', + 'VM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK', + 'VM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT', + 'VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK', + 'VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK', + 'VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT', + 'VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK', + 'VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT', + 'VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK', + 'VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK', + 'VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK', + 'VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK', + 'VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT', + 'VM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK', + 'VM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT', + 'VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK', + 'VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK', + 'VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT', + 'VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK', + 'VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT', + 'VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK', + 'VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK', + 'VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK', + 'VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK', + 'VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT', + 'VM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK', + 'VM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT', + 'VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK', + 'VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK', + 'VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT', + 'VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK', + 'VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT', + 'VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK', + 'VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK', + 'VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK', + 'VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK', + 'VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT', + 'VM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK', + 'VM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT', + 'VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT', + 'VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK', + 'VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK', + 'VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT', + 'VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK', + 'VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT', + 'VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK', + 'VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK', + 'VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK', + 'VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK', + 'VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT', + 'VM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK', + 'VM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT', + 'VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK', + 'VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT', + 'VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK', + 'VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT', + 'VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK', + 'VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT', + 'VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK', + 'VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT', + 'VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK', + 'VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT', + 'VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK', + 'VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT', + 'VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK', + 'VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT', + 'VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK', + 'VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT', + 'VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK', + 'VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT', + 'VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK', + 'VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT', + 'VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK', + 'VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT', + 'VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK', + 'VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT', + 'VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK', + 'VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT', + 'VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK', + 'VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT', + 'VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK', + 'VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT', + 'VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK', + 'VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT', + 'VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK', + 'VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT', + 'VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK', + 'VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT', + 'VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK', + 'VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT', + 'VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK', + 'VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT', + 'VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK', + 'VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT', + 'VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK', + 'VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT', + 'VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK', + 'VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT', + 'VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK', + 'VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT', + 'VM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK', + 'VM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT', + 'VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK', + 'VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT', + 'VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK', + 'VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT', + 'VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK', + 'VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT', + 'VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK', + 'VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT', + 'VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK', + 'VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT', + 'VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK', + 'VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT', + 'VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK', + 'VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT', + 'VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK', + 'VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT', + 'VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK', + 'VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT', + 'VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK', + 'VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT', + 'VM_L2_CNTL3__BANK_SELECT_MASK', + 'VM_L2_CNTL3__BANK_SELECT__SHIFT', + 'VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK', + 'VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT', + 'VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK', + 'VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT', + 'VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK', + 'VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT', + 'VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK', + 'VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT', + 'VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK', + 'VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT', + 'VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK', + 'VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT', + 'VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK', + 'VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT', + 'VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK', + 'VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT', + 'VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK', + 'VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT', + 'VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK', + 'VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT', + 'VM_L2_CNTL4__GC_CH_FGCG_OFF_MASK', + 'VM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT', + 'VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK', + 'VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT', + 'VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK', + 'VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT', + 'VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK', + 'VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT', + 'VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK', + 'VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT', + 'VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK', + 'VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT', + 'VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK', + 'VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT', + 'VM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK', + 'VM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT', + 'VM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK', + 'VM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT', + 'VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK', + 'VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT', + 'VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK', + 'VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT', + 'VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK', + 'VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT', + 'VM_L2_CNTL__ENABLE_L2_CACHE_MASK', + 'VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT', + 'VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK', + 'VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT', + 'VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK', + 'VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT', + 'VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK', + 'VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT', + 'VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK', + 'VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT', + 'VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK', + 'VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT', + 'VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK', + 'VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT', + 'VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK', + 'VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT', + 'VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK', + 'VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT', + 'VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK', + 'VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT', + 'VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK', + 'VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT', + 'VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK', + 'VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT', + 'VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK', + 'VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK', + 'VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT', + 'VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK', + 'VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT', + 'VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK', + 'VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK', + 'VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT', + 'VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK', + 'VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT', + 'VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK', + 'VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT', + 'VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK', + 'VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT', + 'VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK', + 'VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT', + 'VM_L2_PROTECTION_FAULT_STATUS__CID_MASK', + 'VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT', + 'VM_L2_PROTECTION_FAULT_STATUS__FED_MASK', + 'VM_L2_PROTECTION_FAULT_STATUS__FED__SHIFT', + 'VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK', + 'VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT', + 'VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK', + 'VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT', + 'VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK', + 'VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT', + 'VM_L2_PROTECTION_FAULT_STATUS__RW_MASK', + 'VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT', + 'VM_L2_PROTECTION_FAULT_STATUS__UCE_MASK', + 'VM_L2_PROTECTION_FAULT_STATUS__UCE__SHIFT', + 'VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK', + 'VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT', + 'VM_L2_PROTECTION_FAULT_STATUS__VF_MASK', + 'VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT', + 'VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK', + 'VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT', + 'VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK', + 'VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT', + 'VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK', + 'VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT', + 'VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK', + 'VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT', + 'VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK', + 'VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT', + 'VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK', + 'VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT', + 'VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK', + 'VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT', + 'VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK', + 'VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT', + 'VM_L2_STATUS__L2_BUSY_MASK', 'VM_L2_STATUS__L2_BUSY__SHIFT', + 'VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK', + 'VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT', + 'VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK', + 'VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT', + 'VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK', + 'VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT', + 'VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK', + 'VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT', + 'VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK', + 'VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT', + 'VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK', + 'VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT', + 'VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK', + 'VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT', + 'VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK', + 'VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT', + 'VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK', + 'VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT', + 'VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK', + 'VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT', + 'VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK', + 'VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT', + 'VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK', + 'VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT', + 'VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK', + 'VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT', + 'VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK', + 'VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT', + 'VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK', + 'VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT', + 'VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK', + 'VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT', + 'VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK', + 'VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT', + 'VM_PCIE_ATS_CNTL__STU_MASK', 'VM_PCIE_ATS_CNTL__STU__SHIFT', + 'WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK', + 'WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT', + 'WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK', + 'WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT', + 'WD_BUF_RESOURCE_2__ADDR_MODE_MASK', + 'WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT', + 'WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK', + 'WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT', + 'WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK', + 'WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT', + 'WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK', + 'WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT', + 'WD_CNTL_SB_BUF_BASE__BASE_MASK', + 'WD_CNTL_SB_BUF_BASE__BASE__SHIFT', + 'WD_CNTL_STATUS__WD_ADC_BUSY_MASK', + 'WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT', + 'WD_CNTL_STATUS__WD_BUSY_MASK', 'WD_CNTL_STATUS__WD_BUSY__SHIFT', + 'WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK', + 'WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT', + 'WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK', + 'WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT', 'WD_ENHANCE__MISC_MASK', + 'WD_ENHANCE__MISC__SHIFT', 'WD_INDEX_BUF_BASE_HI__BASE_HI_MASK', + 'WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT', + 'WD_INDEX_BUF_BASE__BASE_MASK', 'WD_INDEX_BUF_BASE__BASE__SHIFT', + 'WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK', + 'WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT', + 'WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK', + 'WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT', + 'WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK', + 'WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT', + 'WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK', + 'WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT', + 'WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK', + 'WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT', + 'WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK', + 'WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT', + 'WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK', + 'WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT', + 'WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK', + 'WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT', + 'WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK', + 'WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT', + 'WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK', + 'WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT', + 'WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK', + 'WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT', + 'WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK', + 'WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT', + 'WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK', + 'WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT', + 'WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK', + 'WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT', + 'WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK', + 'WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT', + 'WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK', + 'WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT', + 'WD_POS_BUF_BASE_HI__BASE_HI_MASK', + 'WD_POS_BUF_BASE_HI__BASE_HI__SHIFT', + 'WD_POS_BUF_BASE__BASE_MASK', 'WD_POS_BUF_BASE__BASE__SHIFT', + 'WD_QOS__DRAW_STALL_MASK', 'WD_QOS__DRAW_STALL__SHIFT', + 'WD_UTCL1_CNTL__BYPASS_MASK', 'WD_UTCL1_CNTL__BYPASS__SHIFT', + 'WD_UTCL1_CNTL__DROP_MODE_MASK', + 'WD_UTCL1_CNTL__DROP_MODE__SHIFT', + 'WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK', + 'WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT', + 'WD_UTCL1_CNTL__FORCE_SNOOP_MASK', + 'WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT', + 'WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK', + 'WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT', + 'WD_UTCL1_CNTL__INVALIDATE_MASK', + 'WD_UTCL1_CNTL__INVALIDATE__SHIFT', + 'WD_UTCL1_CNTL__VMID_RESET_MODE_MASK', + 'WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT', + 'WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK', + 'WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT', + 'WD_UTCL1_STATUS__FAULT_DETECTED_MASK', + 'WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT', + 'WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK', + 'WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT', + 'WD_UTCL1_STATUS__PRT_DETECTED_MASK', + 'WD_UTCL1_STATUS__PRT_DETECTED__SHIFT', + 'WD_UTCL1_STATUS__PRT_UTCL1ID_MASK', + 'WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT', + 'WD_UTCL1_STATUS__RETRY_DETECTED_MASK', + 'WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT', + 'WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK', + 'WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT', + '_gc_9_4_3_OFFSET_HEADER', '_gc_9_4_3_SH_MASK_HEADER', + 'ixSQ_DEBUG_CTRL_LOCAL', 'ixSQ_DEBUG_STS_LOCAL', + 'ixSQ_INTERRUPT_WORD_AUTO_CTXID', 'ixSQ_INTERRUPT_WORD_AUTO_HI', + 'ixSQ_INTERRUPT_WORD_AUTO_LO', 'ixSQ_INTERRUPT_WORD_CMN_CTXID', + 'ixSQ_INTERRUPT_WORD_CMN_HI', 'ixSQ_INTERRUPT_WORD_WAVE_CTXID', + 'ixSQ_INTERRUPT_WORD_WAVE_HI', 'ixSQ_INTERRUPT_WORD_WAVE_LO', + 'ixSQ_WAVE_EXEC_HI', 'ixSQ_WAVE_EXEC_LO', 'ixSQ_WAVE_FLUSH_IB', + 'ixSQ_WAVE_GPR_ALLOC', 'ixSQ_WAVE_HW_ID', 'ixSQ_WAVE_IB_DBG0', + 'ixSQ_WAVE_IB_DBG1', 'ixSQ_WAVE_IB_STS', 'ixSQ_WAVE_INST_DW0', + 'ixSQ_WAVE_INST_DW1', 'ixSQ_WAVE_LDS_ALLOC', 'ixSQ_WAVE_M0', + 'ixSQ_WAVE_MODE', 'ixSQ_WAVE_PC_HI', 'ixSQ_WAVE_PC_LO', + 'ixSQ_WAVE_STATUS', 'ixSQ_WAVE_TRAPSTS', 'ixSQ_WAVE_TTMP0', + 'ixSQ_WAVE_TTMP1', 'ixSQ_WAVE_TTMP10', 'ixSQ_WAVE_TTMP11', + 'ixSQ_WAVE_TTMP12', 'ixSQ_WAVE_TTMP13', 'ixSQ_WAVE_TTMP14', + 'ixSQ_WAVE_TTMP15', 'ixSQ_WAVE_TTMP2', 'ixSQ_WAVE_TTMP3', + 'ixSQ_WAVE_TTMP4', 'ixSQ_WAVE_TTMP5', 'ixSQ_WAVE_TTMP6', + 'ixSQ_WAVE_TTMP7', 'ixSQ_WAVE_TTMP8', 'ixSQ_WAVE_TTMP9', + 'ixSQ_WAVE_VALID_AND_IDLE', 'regATC_L2_CACHE_2M_DSM_CNTL', + 'regATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX', + 'regATC_L2_CACHE_2M_DSM_INDEX', + 'regATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX', + 'regATC_L2_CACHE_32K_DSM_CNTL', + 'regATC_L2_CACHE_32K_DSM_CNTL_BASE_IDX', + 'regATC_L2_CACHE_32K_DSM_INDEX', + 'regATC_L2_CACHE_32K_DSM_INDEX_BASE_IDX', + 'regATC_L2_CACHE_4K_DSM_CNTL', + 'regATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX', + 'regATC_L2_CACHE_4K_DSM_INDEX', + 'regATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX', 'regATC_L2_CACHE_DATA0', + 'regATC_L2_CACHE_DATA0_BASE_IDX', 'regATC_L2_CACHE_DATA1', + 'regATC_L2_CACHE_DATA1_BASE_IDX', 'regATC_L2_CACHE_DATA2', + 'regATC_L2_CACHE_DATA2_BASE_IDX', 'regATC_L2_CACHE_DATA3', + 'regATC_L2_CACHE_DATA3_BASE_IDX', 'regATC_L2_CE_ERR_STATUS_HI', + 'regATC_L2_CE_ERR_STATUS_HI_BASE_IDX', + 'regATC_L2_CE_ERR_STATUS_LO', + 'regATC_L2_CE_ERR_STATUS_LO_BASE_IDX', 'regATC_L2_CGTT_CLK_CTRL', + 'regATC_L2_CGTT_CLK_CTRL_BASE_IDX', 'regATC_L2_CNTL', + 'regATC_L2_CNTL2', 'regATC_L2_CNTL2_BASE_IDX', 'regATC_L2_CNTL3', + 'regATC_L2_CNTL3_BASE_IDX', 'regATC_L2_CNTL4', + 'regATC_L2_CNTL4_BASE_IDX', 'regATC_L2_CNTL_BASE_IDX', + 'regATC_L2_MEM_POWER_LS', 'regATC_L2_MEM_POWER_LS_BASE_IDX', + 'regATC_L2_MISC_CG', 'regATC_L2_MISC_CG_BASE_IDX', + 'regATC_L2_MM_GROUP_RT_CLASSES', + 'regATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX', + 'regATC_L2_PERFCOUNTER0_CFG', + 'regATC_L2_PERFCOUNTER0_CFG_BASE_IDX', + 'regATC_L2_PERFCOUNTER1_CFG', + 'regATC_L2_PERFCOUNTER1_CFG_BASE_IDX', 'regATC_L2_PERFCOUNTER_HI', + 'regATC_L2_PERFCOUNTER_HI_BASE_IDX', 'regATC_L2_PERFCOUNTER_LO', + 'regATC_L2_PERFCOUNTER_LO_BASE_IDX', + 'regATC_L2_PERFCOUNTER_RSLT_CNTL', + 'regATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'regATC_L2_STATUS', + 'regATC_L2_STATUS2', 'regATC_L2_STATUS2_BASE_IDX', + 'regATC_L2_STATUS_BASE_IDX', 'regATC_L2_UE_ERR_STATUS_HI', + 'regATC_L2_UE_ERR_STATUS_HI_BASE_IDX', + 'regATC_L2_UE_ERR_STATUS_LO', + 'regATC_L2_UE_ERR_STATUS_LO_BASE_IDX', 'regBCI_DEBUG_READ', + 'regBCI_DEBUG_READ_BASE_IDX', 'regCB_BLEND0_CONTROL', + 'regCB_BLEND0_CONTROL_BASE_IDX', 'regCB_BLEND1_CONTROL', + 'regCB_BLEND1_CONTROL_BASE_IDX', 'regCB_BLEND2_CONTROL', + 'regCB_BLEND2_CONTROL_BASE_IDX', 'regCB_BLEND3_CONTROL', + 'regCB_BLEND3_CONTROL_BASE_IDX', 'regCB_BLEND4_CONTROL', + 'regCB_BLEND4_CONTROL_BASE_IDX', 'regCB_BLEND5_CONTROL', + 'regCB_BLEND5_CONTROL_BASE_IDX', 'regCB_BLEND6_CONTROL', + 'regCB_BLEND6_CONTROL_BASE_IDX', 'regCB_BLEND7_CONTROL', + 'regCB_BLEND7_CONTROL_BASE_IDX', 'regCB_BLEND_ALPHA', + 'regCB_BLEND_ALPHA_BASE_IDX', 'regCB_BLEND_BLUE', + 'regCB_BLEND_BLUE_BASE_IDX', 'regCB_BLEND_GREEN', + 'regCB_BLEND_GREEN_BASE_IDX', 'regCB_BLEND_RED', + 'regCB_BLEND_RED_BASE_IDX', 'regCB_CGTT_SCLK_CTRL', + 'regCB_CGTT_SCLK_CTRL_BASE_IDX', 'regCB_COLOR0_ATTRIB', + 'regCB_COLOR0_ATTRIB2', 'regCB_COLOR0_ATTRIB2_BASE_IDX', + 'regCB_COLOR0_ATTRIB_BASE_IDX', 'regCB_COLOR0_BASE', + 'regCB_COLOR0_BASE_BASE_IDX', 'regCB_COLOR0_BASE_EXT', + 'regCB_COLOR0_BASE_EXT_BASE_IDX', 'regCB_COLOR0_CLEAR_WORD0', + 'regCB_COLOR0_CLEAR_WORD0_BASE_IDX', 'regCB_COLOR0_CLEAR_WORD1', + 'regCB_COLOR0_CLEAR_WORD1_BASE_IDX', 'regCB_COLOR0_CMASK', + 'regCB_COLOR0_CMASK_BASE_EXT', + 'regCB_COLOR0_CMASK_BASE_EXT_BASE_IDX', + 'regCB_COLOR0_CMASK_BASE_IDX', 'regCB_COLOR0_DCC_BASE', + 'regCB_COLOR0_DCC_BASE_BASE_IDX', 'regCB_COLOR0_DCC_BASE_EXT', + 'regCB_COLOR0_DCC_BASE_EXT_BASE_IDX', 'regCB_COLOR0_DCC_CONTROL', + 'regCB_COLOR0_DCC_CONTROL_BASE_IDX', 'regCB_COLOR0_FMASK', + 'regCB_COLOR0_FMASK_BASE_EXT', + 'regCB_COLOR0_FMASK_BASE_EXT_BASE_IDX', + 'regCB_COLOR0_FMASK_BASE_IDX', 'regCB_COLOR0_INFO', + 'regCB_COLOR0_INFO_BASE_IDX', 'regCB_COLOR0_VIEW', + 'regCB_COLOR0_VIEW_BASE_IDX', 'regCB_COLOR1_ATTRIB', + 'regCB_COLOR1_ATTRIB2', 'regCB_COLOR1_ATTRIB2_BASE_IDX', + 'regCB_COLOR1_ATTRIB_BASE_IDX', 'regCB_COLOR1_BASE', + 'regCB_COLOR1_BASE_BASE_IDX', 'regCB_COLOR1_BASE_EXT', + 'regCB_COLOR1_BASE_EXT_BASE_IDX', 'regCB_COLOR1_CLEAR_WORD0', + 'regCB_COLOR1_CLEAR_WORD0_BASE_IDX', 'regCB_COLOR1_CLEAR_WORD1', + 'regCB_COLOR1_CLEAR_WORD1_BASE_IDX', 'regCB_COLOR1_CMASK', + 'regCB_COLOR1_CMASK_BASE_EXT', + 'regCB_COLOR1_CMASK_BASE_EXT_BASE_IDX', + 'regCB_COLOR1_CMASK_BASE_IDX', 'regCB_COLOR1_DCC_BASE', + 'regCB_COLOR1_DCC_BASE_BASE_IDX', 'regCB_COLOR1_DCC_BASE_EXT', + 'regCB_COLOR1_DCC_BASE_EXT_BASE_IDX', 'regCB_COLOR1_DCC_CONTROL', + 'regCB_COLOR1_DCC_CONTROL_BASE_IDX', 'regCB_COLOR1_FMASK', + 'regCB_COLOR1_FMASK_BASE_EXT', + 'regCB_COLOR1_FMASK_BASE_EXT_BASE_IDX', + 'regCB_COLOR1_FMASK_BASE_IDX', 'regCB_COLOR1_INFO', + 'regCB_COLOR1_INFO_BASE_IDX', 'regCB_COLOR1_VIEW', + 'regCB_COLOR1_VIEW_BASE_IDX', 'regCB_COLOR2_ATTRIB', + 'regCB_COLOR2_ATTRIB2', 'regCB_COLOR2_ATTRIB2_BASE_IDX', + 'regCB_COLOR2_ATTRIB_BASE_IDX', 'regCB_COLOR2_BASE', + 'regCB_COLOR2_BASE_BASE_IDX', 'regCB_COLOR2_BASE_EXT', + 'regCB_COLOR2_BASE_EXT_BASE_IDX', 'regCB_COLOR2_CLEAR_WORD0', + 'regCB_COLOR2_CLEAR_WORD0_BASE_IDX', 'regCB_COLOR2_CLEAR_WORD1', + 'regCB_COLOR2_CLEAR_WORD1_BASE_IDX', 'regCB_COLOR2_CMASK', + 'regCB_COLOR2_CMASK_BASE_EXT', + 'regCB_COLOR2_CMASK_BASE_EXT_BASE_IDX', + 'regCB_COLOR2_CMASK_BASE_IDX', 'regCB_COLOR2_DCC_BASE', + 'regCB_COLOR2_DCC_BASE_BASE_IDX', 'regCB_COLOR2_DCC_BASE_EXT', + 'regCB_COLOR2_DCC_BASE_EXT_BASE_IDX', 'regCB_COLOR2_DCC_CONTROL', + 'regCB_COLOR2_DCC_CONTROL_BASE_IDX', 'regCB_COLOR2_FMASK', + 'regCB_COLOR2_FMASK_BASE_EXT', + 'regCB_COLOR2_FMASK_BASE_EXT_BASE_IDX', + 'regCB_COLOR2_FMASK_BASE_IDX', 'regCB_COLOR2_INFO', + 'regCB_COLOR2_INFO_BASE_IDX', 'regCB_COLOR2_VIEW', + 'regCB_COLOR2_VIEW_BASE_IDX', 'regCB_COLOR3_ATTRIB', + 'regCB_COLOR3_ATTRIB2', 'regCB_COLOR3_ATTRIB2_BASE_IDX', + 'regCB_COLOR3_ATTRIB_BASE_IDX', 'regCB_COLOR3_BASE', + 'regCB_COLOR3_BASE_BASE_IDX', 'regCB_COLOR3_BASE_EXT', + 'regCB_COLOR3_BASE_EXT_BASE_IDX', 'regCB_COLOR3_CLEAR_WORD0', + 'regCB_COLOR3_CLEAR_WORD0_BASE_IDX', 'regCB_COLOR3_CLEAR_WORD1', + 'regCB_COLOR3_CLEAR_WORD1_BASE_IDX', 'regCB_COLOR3_CMASK', + 'regCB_COLOR3_CMASK_BASE_EXT', + 'regCB_COLOR3_CMASK_BASE_EXT_BASE_IDX', + 'regCB_COLOR3_CMASK_BASE_IDX', 'regCB_COLOR3_DCC_BASE', + 'regCB_COLOR3_DCC_BASE_BASE_IDX', 'regCB_COLOR3_DCC_BASE_EXT', + 'regCB_COLOR3_DCC_BASE_EXT_BASE_IDX', 'regCB_COLOR3_DCC_CONTROL', + 'regCB_COLOR3_DCC_CONTROL_BASE_IDX', 'regCB_COLOR3_FMASK', + 'regCB_COLOR3_FMASK_BASE_EXT', + 'regCB_COLOR3_FMASK_BASE_EXT_BASE_IDX', + 'regCB_COLOR3_FMASK_BASE_IDX', 'regCB_COLOR3_INFO', + 'regCB_COLOR3_INFO_BASE_IDX', 'regCB_COLOR3_VIEW', + 'regCB_COLOR3_VIEW_BASE_IDX', 'regCB_COLOR4_ATTRIB', + 'regCB_COLOR4_ATTRIB2', 'regCB_COLOR4_ATTRIB2_BASE_IDX', + 'regCB_COLOR4_ATTRIB_BASE_IDX', 'regCB_COLOR4_BASE', + 'regCB_COLOR4_BASE_BASE_IDX', 'regCB_COLOR4_BASE_EXT', + 'regCB_COLOR4_BASE_EXT_BASE_IDX', 'regCB_COLOR4_CLEAR_WORD0', + 'regCB_COLOR4_CLEAR_WORD0_BASE_IDX', 'regCB_COLOR4_CLEAR_WORD1', + 'regCB_COLOR4_CLEAR_WORD1_BASE_IDX', 'regCB_COLOR4_CMASK', + 'regCB_COLOR4_CMASK_BASE_EXT', + 'regCB_COLOR4_CMASK_BASE_EXT_BASE_IDX', + 'regCB_COLOR4_CMASK_BASE_IDX', 'regCB_COLOR4_DCC_BASE', + 'regCB_COLOR4_DCC_BASE_BASE_IDX', 'regCB_COLOR4_DCC_BASE_EXT', + 'regCB_COLOR4_DCC_BASE_EXT_BASE_IDX', 'regCB_COLOR4_DCC_CONTROL', + 'regCB_COLOR4_DCC_CONTROL_BASE_IDX', 'regCB_COLOR4_FMASK', + 'regCB_COLOR4_FMASK_BASE_EXT', + 'regCB_COLOR4_FMASK_BASE_EXT_BASE_IDX', + 'regCB_COLOR4_FMASK_BASE_IDX', 'regCB_COLOR4_INFO', + 'regCB_COLOR4_INFO_BASE_IDX', 'regCB_COLOR4_VIEW', + 'regCB_COLOR4_VIEW_BASE_IDX', 'regCB_COLOR5_ATTRIB', + 'regCB_COLOR5_ATTRIB2', 'regCB_COLOR5_ATTRIB2_BASE_IDX', + 'regCB_COLOR5_ATTRIB_BASE_IDX', 'regCB_COLOR5_BASE', + 'regCB_COLOR5_BASE_BASE_IDX', 'regCB_COLOR5_BASE_EXT', + 'regCB_COLOR5_BASE_EXT_BASE_IDX', 'regCB_COLOR5_CLEAR_WORD0', + 'regCB_COLOR5_CLEAR_WORD0_BASE_IDX', 'regCB_COLOR5_CLEAR_WORD1', + 'regCB_COLOR5_CLEAR_WORD1_BASE_IDX', 'regCB_COLOR5_CMASK', + 'regCB_COLOR5_CMASK_BASE_EXT', + 'regCB_COLOR5_CMASK_BASE_EXT_BASE_IDX', + 'regCB_COLOR5_CMASK_BASE_IDX', 'regCB_COLOR5_DCC_BASE', + 'regCB_COLOR5_DCC_BASE_BASE_IDX', 'regCB_COLOR5_DCC_BASE_EXT', + 'regCB_COLOR5_DCC_BASE_EXT_BASE_IDX', 'regCB_COLOR5_DCC_CONTROL', + 'regCB_COLOR5_DCC_CONTROL_BASE_IDX', 'regCB_COLOR5_FMASK', + 'regCB_COLOR5_FMASK_BASE_EXT', + 'regCB_COLOR5_FMASK_BASE_EXT_BASE_IDX', + 'regCB_COLOR5_FMASK_BASE_IDX', 'regCB_COLOR5_INFO', + 'regCB_COLOR5_INFO_BASE_IDX', 'regCB_COLOR5_VIEW', + 'regCB_COLOR5_VIEW_BASE_IDX', 'regCB_COLOR6_ATTRIB', + 'regCB_COLOR6_ATTRIB2', 'regCB_COLOR6_ATTRIB2_BASE_IDX', + 'regCB_COLOR6_ATTRIB_BASE_IDX', 'regCB_COLOR6_BASE', + 'regCB_COLOR6_BASE_BASE_IDX', 'regCB_COLOR6_BASE_EXT', + 'regCB_COLOR6_BASE_EXT_BASE_IDX', 'regCB_COLOR6_CLEAR_WORD0', + 'regCB_COLOR6_CLEAR_WORD0_BASE_IDX', 'regCB_COLOR6_CLEAR_WORD1', + 'regCB_COLOR6_CLEAR_WORD1_BASE_IDX', 'regCB_COLOR6_CMASK', + 'regCB_COLOR6_CMASK_BASE_EXT', + 'regCB_COLOR6_CMASK_BASE_EXT_BASE_IDX', + 'regCB_COLOR6_CMASK_BASE_IDX', 'regCB_COLOR6_DCC_BASE', + 'regCB_COLOR6_DCC_BASE_BASE_IDX', 'regCB_COLOR6_DCC_BASE_EXT', + 'regCB_COLOR6_DCC_BASE_EXT_BASE_IDX', 'regCB_COLOR6_DCC_CONTROL', + 'regCB_COLOR6_DCC_CONTROL_BASE_IDX', 'regCB_COLOR6_FMASK', + 'regCB_COLOR6_FMASK_BASE_EXT', + 'regCB_COLOR6_FMASK_BASE_EXT_BASE_IDX', + 'regCB_COLOR6_FMASK_BASE_IDX', 'regCB_COLOR6_INFO', + 'regCB_COLOR6_INFO_BASE_IDX', 'regCB_COLOR6_VIEW', + 'regCB_COLOR6_VIEW_BASE_IDX', 'regCB_COLOR7_ATTRIB', + 'regCB_COLOR7_ATTRIB2', 'regCB_COLOR7_ATTRIB2_BASE_IDX', + 'regCB_COLOR7_ATTRIB_BASE_IDX', 'regCB_COLOR7_BASE', + 'regCB_COLOR7_BASE_BASE_IDX', 'regCB_COLOR7_BASE_EXT', + 'regCB_COLOR7_BASE_EXT_BASE_IDX', 'regCB_COLOR7_CLEAR_WORD0', + 'regCB_COLOR7_CLEAR_WORD0_BASE_IDX', 'regCB_COLOR7_CLEAR_WORD1', + 'regCB_COLOR7_CLEAR_WORD1_BASE_IDX', 'regCB_COLOR7_CMASK', + 'regCB_COLOR7_CMASK_BASE_EXT', + 'regCB_COLOR7_CMASK_BASE_EXT_BASE_IDX', + 'regCB_COLOR7_CMASK_BASE_IDX', 'regCB_COLOR7_DCC_BASE', + 'regCB_COLOR7_DCC_BASE_BASE_IDX', 'regCB_COLOR7_DCC_BASE_EXT', + 'regCB_COLOR7_DCC_BASE_EXT_BASE_IDX', 'regCB_COLOR7_DCC_CONTROL', + 'regCB_COLOR7_DCC_CONTROL_BASE_IDX', 'regCB_COLOR7_FMASK', + 'regCB_COLOR7_FMASK_BASE_EXT', + 'regCB_COLOR7_FMASK_BASE_EXT_BASE_IDX', + 'regCB_COLOR7_FMASK_BASE_IDX', 'regCB_COLOR7_INFO', + 'regCB_COLOR7_INFO_BASE_IDX', 'regCB_COLOR7_VIEW', + 'regCB_COLOR7_VIEW_BASE_IDX', 'regCB_COLOR_CONTROL', + 'regCB_COLOR_CONTROL_BASE_IDX', 'regCB_DCC_CONFIG', + 'regCB_DCC_CONFIG_BASE_IDX', 'regCB_DCC_CONTROL', + 'regCB_DCC_CONTROL_BASE_IDX', 'regCB_HW_CONTROL', + 'regCB_HW_CONTROL_1', 'regCB_HW_CONTROL_1_BASE_IDX', + 'regCB_HW_CONTROL_2', 'regCB_HW_CONTROL_2_BASE_IDX', + 'regCB_HW_CONTROL_3', 'regCB_HW_CONTROL_3_BASE_IDX', + 'regCB_HW_CONTROL_BASE_IDX', 'regCB_HW_MEM_ARBITER_RD', + 'regCB_HW_MEM_ARBITER_RD_BASE_IDX', 'regCB_HW_MEM_ARBITER_WR', + 'regCB_HW_MEM_ARBITER_WR_BASE_IDX', 'regCB_MRT0_EPITCH', + 'regCB_MRT0_EPITCH_BASE_IDX', 'regCB_MRT1_EPITCH', + 'regCB_MRT1_EPITCH_BASE_IDX', 'regCB_MRT2_EPITCH', + 'regCB_MRT2_EPITCH_BASE_IDX', 'regCB_MRT3_EPITCH', + 'regCB_MRT3_EPITCH_BASE_IDX', 'regCB_MRT4_EPITCH', + 'regCB_MRT4_EPITCH_BASE_IDX', 'regCB_MRT5_EPITCH', + 'regCB_MRT5_EPITCH_BASE_IDX', 'regCB_MRT6_EPITCH', + 'regCB_MRT6_EPITCH_BASE_IDX', 'regCB_MRT7_EPITCH', + 'regCB_MRT7_EPITCH_BASE_IDX', 'regCB_PERFCOUNTER0_HI', + 'regCB_PERFCOUNTER0_HI_BASE_IDX', 'regCB_PERFCOUNTER0_LO', + 'regCB_PERFCOUNTER0_LO_BASE_IDX', 'regCB_PERFCOUNTER0_SELECT', + 'regCB_PERFCOUNTER0_SELECT1', + 'regCB_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regCB_PERFCOUNTER0_SELECT_BASE_IDX', 'regCB_PERFCOUNTER1_HI', + 'regCB_PERFCOUNTER1_HI_BASE_IDX', 'regCB_PERFCOUNTER1_LO', + 'regCB_PERFCOUNTER1_LO_BASE_IDX', 'regCB_PERFCOUNTER1_SELECT', + 'regCB_PERFCOUNTER1_SELECT_BASE_IDX', 'regCB_PERFCOUNTER2_HI', + 'regCB_PERFCOUNTER2_HI_BASE_IDX', 'regCB_PERFCOUNTER2_LO', + 'regCB_PERFCOUNTER2_LO_BASE_IDX', 'regCB_PERFCOUNTER2_SELECT', + 'regCB_PERFCOUNTER2_SELECT_BASE_IDX', 'regCB_PERFCOUNTER3_HI', + 'regCB_PERFCOUNTER3_HI_BASE_IDX', 'regCB_PERFCOUNTER3_LO', + 'regCB_PERFCOUNTER3_LO_BASE_IDX', 'regCB_PERFCOUNTER3_SELECT', + 'regCB_PERFCOUNTER3_SELECT_BASE_IDX', 'regCB_PERFCOUNTER_FILTER', + 'regCB_PERFCOUNTER_FILTER_BASE_IDX', 'regCB_SHADER_MASK', + 'regCB_SHADER_MASK_BASE_IDX', 'regCB_TARGET_MASK', + 'regCB_TARGET_MASK_BASE_IDX', 'regCC_GC_EDC_CONFIG', + 'regCC_GC_EDC_CONFIG_BASE_IDX', 'regCC_GC_PRIM_CONFIG', + 'regCC_GC_PRIM_CONFIG_BASE_IDX', 'regCC_GC_SHADER_ARRAY_CONFIG', + 'regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX', + 'regCC_GC_SHADER_RATE_CONFIG', + 'regCC_GC_SHADER_RATE_CONFIG_BASE_IDX', + 'regCC_RB_BACKEND_DISABLE', 'regCC_RB_BACKEND_DISABLE_BASE_IDX', + 'regCC_RB_DAISY_CHAIN', 'regCC_RB_DAISY_CHAIN_BASE_IDX', + 'regCC_RB_REDUNDANCY', 'regCC_RB_REDUNDANCY_BASE_IDX', + 'regCGTS_CU0_LDS_SQ_CTRL_REG', + 'regCGTS_CU0_LDS_SQ_CTRL_REG_BASE_IDX', + 'regCGTS_CU0_SP0_CTRL_REG', 'regCGTS_CU0_SP0_CTRL_REG_BASE_IDX', + 'regCGTS_CU0_SP1_CTRL_REG', 'regCGTS_CU0_SP1_CTRL_REG_BASE_IDX', + 'regCGTS_CU0_TA_SQC_CTRL_REG', + 'regCGTS_CU0_TA_SQC_CTRL_REG_BASE_IDX', + 'regCGTS_CU0_TCPI_CTRL_REG', 'regCGTS_CU0_TCPI_CTRL_REG_BASE_IDX', + 'regCGTS_CU0_TD_TCP_CTRL_REG', + 'regCGTS_CU0_TD_TCP_CTRL_REG_BASE_IDX', + 'regCGTS_CU10_LDS_SQ_CTRL_REG', + 'regCGTS_CU10_LDS_SQ_CTRL_REG_BASE_IDX', + 'regCGTS_CU10_SP0_CTRL_REG', 'regCGTS_CU10_SP0_CTRL_REG_BASE_IDX', + 'regCGTS_CU10_SP1_CTRL_REG', 'regCGTS_CU10_SP1_CTRL_REG_BASE_IDX', + 'regCGTS_CU10_TA_SQC_CTRL_REG', + 'regCGTS_CU10_TA_SQC_CTRL_REG_BASE_IDX', + 'regCGTS_CU10_TCPI_CTRL_REG', + 'regCGTS_CU10_TCPI_CTRL_REG_BASE_IDX', + 'regCGTS_CU10_TD_TCP_CTRL_REG', + 'regCGTS_CU10_TD_TCP_CTRL_REG_BASE_IDX', + 'regCGTS_CU11_LDS_SQ_CTRL_REG', + 'regCGTS_CU11_LDS_SQ_CTRL_REG_BASE_IDX', + 'regCGTS_CU11_SP0_CTRL_REG', 'regCGTS_CU11_SP0_CTRL_REG_BASE_IDX', + 'regCGTS_CU11_SP1_CTRL_REG', 'regCGTS_CU11_SP1_CTRL_REG_BASE_IDX', + 'regCGTS_CU11_TA_SQC_CTRL_REG', + 'regCGTS_CU11_TA_SQC_CTRL_REG_BASE_IDX', + 'regCGTS_CU11_TCPI_CTRL_REG', + 'regCGTS_CU11_TCPI_CTRL_REG_BASE_IDX', + 'regCGTS_CU11_TD_TCP_CTRL_REG', + 'regCGTS_CU11_TD_TCP_CTRL_REG_BASE_IDX', + 'regCGTS_CU12_LDS_SQ_CTRL_REG', + 'regCGTS_CU12_LDS_SQ_CTRL_REG_BASE_IDX', + 'regCGTS_CU12_SP0_CTRL_REG', 'regCGTS_CU12_SP0_CTRL_REG_BASE_IDX', + 'regCGTS_CU12_SP1_CTRL_REG', 'regCGTS_CU12_SP1_CTRL_REG_BASE_IDX', + 'regCGTS_CU12_TA_SQC_CTRL_REG', + 'regCGTS_CU12_TA_SQC_CTRL_REG_BASE_IDX', + 'regCGTS_CU12_TCPI_CTRL_REG', + 'regCGTS_CU12_TCPI_CTRL_REG_BASE_IDX', + 'regCGTS_CU12_TD_TCP_CTRL_REG', + 'regCGTS_CU12_TD_TCP_CTRL_REG_BASE_IDX', + 'regCGTS_CU13_LDS_SQ_CTRL_REG', + 'regCGTS_CU13_LDS_SQ_CTRL_REG_BASE_IDX', + 'regCGTS_CU13_SP0_CTRL_REG', 'regCGTS_CU13_SP0_CTRL_REG_BASE_IDX', + 'regCGTS_CU13_SP1_CTRL_REG', 'regCGTS_CU13_SP1_CTRL_REG_BASE_IDX', + 'regCGTS_CU13_TA_SQC_CTRL_REG', + 'regCGTS_CU13_TA_SQC_CTRL_REG_BASE_IDX', + 'regCGTS_CU13_TCPI_CTRL_REG', + 'regCGTS_CU13_TCPI_CTRL_REG_BASE_IDX', + 'regCGTS_CU13_TD_TCP_CTRL_REG', + 'regCGTS_CU13_TD_TCP_CTRL_REG_BASE_IDX', + 'regCGTS_CU14_LDS_SQ_CTRL_REG', + 'regCGTS_CU14_LDS_SQ_CTRL_REG_BASE_IDX', + 'regCGTS_CU14_SP0_CTRL_REG', 'regCGTS_CU14_SP0_CTRL_REG_BASE_IDX', + 'regCGTS_CU14_SP1_CTRL_REG', 'regCGTS_CU14_SP1_CTRL_REG_BASE_IDX', + 'regCGTS_CU14_TA_SQC_CTRL_REG', + 'regCGTS_CU14_TA_SQC_CTRL_REG_BASE_IDX', + 'regCGTS_CU14_TCPI_CTRL_REG', + 'regCGTS_CU14_TCPI_CTRL_REG_BASE_IDX', + 'regCGTS_CU14_TD_TCP_CTRL_REG', + 'regCGTS_CU14_TD_TCP_CTRL_REG_BASE_IDX', + 'regCGTS_CU15_LDS_SQ_CTRL_REG', + 'regCGTS_CU15_LDS_SQ_CTRL_REG_BASE_IDX', + 'regCGTS_CU15_SP0_CTRL_REG', 'regCGTS_CU15_SP0_CTRL_REG_BASE_IDX', + 'regCGTS_CU15_SP1_CTRL_REG', 'regCGTS_CU15_SP1_CTRL_REG_BASE_IDX', + 'regCGTS_CU15_TA_SQC_CTRL_REG', + 'regCGTS_CU15_TA_SQC_CTRL_REG_BASE_IDX', + 'regCGTS_CU15_TCPI_CTRL_REG', + 'regCGTS_CU15_TCPI_CTRL_REG_BASE_IDX', + 'regCGTS_CU15_TD_TCP_CTRL_REG', + 'regCGTS_CU15_TD_TCP_CTRL_REG_BASE_IDX', + 'regCGTS_CU1_LDS_SQ_CTRL_REG', + 'regCGTS_CU1_LDS_SQ_CTRL_REG_BASE_IDX', + 'regCGTS_CU1_SP0_CTRL_REG', 'regCGTS_CU1_SP0_CTRL_REG_BASE_IDX', + 'regCGTS_CU1_SP1_CTRL_REG', 'regCGTS_CU1_SP1_CTRL_REG_BASE_IDX', + 'regCGTS_CU1_TA_SQC_CTRL_REG', + 'regCGTS_CU1_TA_SQC_CTRL_REG_BASE_IDX', + 'regCGTS_CU1_TCPI_CTRL_REG', 'regCGTS_CU1_TCPI_CTRL_REG_BASE_IDX', + 'regCGTS_CU1_TD_TCP_CTRL_REG', + 'regCGTS_CU1_TD_TCP_CTRL_REG_BASE_IDX', + 'regCGTS_CU2_LDS_SQ_CTRL_REG', + 'regCGTS_CU2_LDS_SQ_CTRL_REG_BASE_IDX', + 'regCGTS_CU2_SP0_CTRL_REG', 'regCGTS_CU2_SP0_CTRL_REG_BASE_IDX', + 'regCGTS_CU2_SP1_CTRL_REG', 'regCGTS_CU2_SP1_CTRL_REG_BASE_IDX', + 'regCGTS_CU2_TA_SQC_CTRL_REG', + 'regCGTS_CU2_TA_SQC_CTRL_REG_BASE_IDX', + 'regCGTS_CU2_TCPI_CTRL_REG', 'regCGTS_CU2_TCPI_CTRL_REG_BASE_IDX', + 'regCGTS_CU2_TD_TCP_CTRL_REG', + 'regCGTS_CU2_TD_TCP_CTRL_REG_BASE_IDX', + 'regCGTS_CU3_LDS_SQ_CTRL_REG', + 'regCGTS_CU3_LDS_SQ_CTRL_REG_BASE_IDX', + 'regCGTS_CU3_SP0_CTRL_REG', 'regCGTS_CU3_SP0_CTRL_REG_BASE_IDX', + 'regCGTS_CU3_SP1_CTRL_REG', 'regCGTS_CU3_SP1_CTRL_REG_BASE_IDX', + 'regCGTS_CU3_TA_SQC_CTRL_REG', + 'regCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX', + 'regCGTS_CU3_TCPI_CTRL_REG', 'regCGTS_CU3_TCPI_CTRL_REG_BASE_IDX', + 'regCGTS_CU3_TD_TCP_CTRL_REG', + 'regCGTS_CU3_TD_TCP_CTRL_REG_BASE_IDX', + 'regCGTS_CU4_LDS_SQ_CTRL_REG', + 'regCGTS_CU4_LDS_SQ_CTRL_REG_BASE_IDX', + 'regCGTS_CU4_SP0_CTRL_REG', 'regCGTS_CU4_SP0_CTRL_REG_BASE_IDX', + 'regCGTS_CU4_SP1_CTRL_REG', 'regCGTS_CU4_SP1_CTRL_REG_BASE_IDX', + 'regCGTS_CU4_TA_SQC_CTRL_REG', + 'regCGTS_CU4_TA_SQC_CTRL_REG_BASE_IDX', + 'regCGTS_CU4_TCPI_CTRL_REG', 'regCGTS_CU4_TCPI_CTRL_REG_BASE_IDX', + 'regCGTS_CU4_TD_TCP_CTRL_REG', + 'regCGTS_CU4_TD_TCP_CTRL_REG_BASE_IDX', + 'regCGTS_CU5_LDS_SQ_CTRL_REG', + 'regCGTS_CU5_LDS_SQ_CTRL_REG_BASE_IDX', + 'regCGTS_CU5_SP0_CTRL_REG', 'regCGTS_CU5_SP0_CTRL_REG_BASE_IDX', + 'regCGTS_CU5_SP1_CTRL_REG', 'regCGTS_CU5_SP1_CTRL_REG_BASE_IDX', + 'regCGTS_CU5_TA_SQC_CTRL_REG', + 'regCGTS_CU5_TA_SQC_CTRL_REG_BASE_IDX', + 'regCGTS_CU5_TCPI_CTRL_REG', 'regCGTS_CU5_TCPI_CTRL_REG_BASE_IDX', + 'regCGTS_CU5_TD_TCP_CTRL_REG', + 'regCGTS_CU5_TD_TCP_CTRL_REG_BASE_IDX', + 'regCGTS_CU6_LDS_SQ_CTRL_REG', + 'regCGTS_CU6_LDS_SQ_CTRL_REG_BASE_IDX', + 'regCGTS_CU6_SP0_CTRL_REG', 'regCGTS_CU6_SP0_CTRL_REG_BASE_IDX', + 'regCGTS_CU6_SP1_CTRL_REG', 'regCGTS_CU6_SP1_CTRL_REG_BASE_IDX', + 'regCGTS_CU6_TA_SQC_CTRL_REG', + 'regCGTS_CU6_TA_SQC_CTRL_REG_BASE_IDX', + 'regCGTS_CU6_TCPI_CTRL_REG', 'regCGTS_CU6_TCPI_CTRL_REG_BASE_IDX', + 'regCGTS_CU6_TD_TCP_CTRL_REG', + 'regCGTS_CU6_TD_TCP_CTRL_REG_BASE_IDX', + 'regCGTS_CU7_LDS_SQ_CTRL_REG', + 'regCGTS_CU7_LDS_SQ_CTRL_REG_BASE_IDX', + 'regCGTS_CU7_SP0_CTRL_REG', 'regCGTS_CU7_SP0_CTRL_REG_BASE_IDX', + 'regCGTS_CU7_SP1_CTRL_REG', 'regCGTS_CU7_SP1_CTRL_REG_BASE_IDX', + 'regCGTS_CU7_TA_SQC_CTRL_REG', + 'regCGTS_CU7_TA_SQC_CTRL_REG_BASE_IDX', + 'regCGTS_CU7_TCPI_CTRL_REG', 'regCGTS_CU7_TCPI_CTRL_REG_BASE_IDX', + 'regCGTS_CU7_TD_TCP_CTRL_REG', + 'regCGTS_CU7_TD_TCP_CTRL_REG_BASE_IDX', + 'regCGTS_CU8_LDS_SQ_CTRL_REG', + 'regCGTS_CU8_LDS_SQ_CTRL_REG_BASE_IDX', + 'regCGTS_CU8_SP0_CTRL_REG', 'regCGTS_CU8_SP0_CTRL_REG_BASE_IDX', + 'regCGTS_CU8_SP1_CTRL_REG', 'regCGTS_CU8_SP1_CTRL_REG_BASE_IDX', + 'regCGTS_CU8_TA_SQC_CTRL_REG', + 'regCGTS_CU8_TA_SQC_CTRL_REG_BASE_IDX', + 'regCGTS_CU8_TCPI_CTRL_REG', 'regCGTS_CU8_TCPI_CTRL_REG_BASE_IDX', + 'regCGTS_CU8_TD_TCP_CTRL_REG', + 'regCGTS_CU8_TD_TCP_CTRL_REG_BASE_IDX', + 'regCGTS_CU9_LDS_SQ_CTRL_REG', + 'regCGTS_CU9_LDS_SQ_CTRL_REG_BASE_IDX', + 'regCGTS_CU9_SP0_CTRL_REG', 'regCGTS_CU9_SP0_CTRL_REG_BASE_IDX', + 'regCGTS_CU9_SP1_CTRL_REG', 'regCGTS_CU9_SP1_CTRL_REG_BASE_IDX', + 'regCGTS_CU9_TA_SQC_CTRL_REG', + 'regCGTS_CU9_TA_SQC_CTRL_REG_BASE_IDX', + 'regCGTS_CU9_TCPI_CTRL_REG', 'regCGTS_CU9_TCPI_CTRL_REG_BASE_IDX', + 'regCGTS_CU9_TD_TCP_CTRL_REG', + 'regCGTS_CU9_TD_TCP_CTRL_REG_BASE_IDX', 'regCGTS_RD_CTRL_REG', + 'regCGTS_RD_CTRL_REG_BASE_IDX', 'regCGTS_RD_REG', + 'regCGTS_RD_REG_BASE_IDX', 'regCGTS_SM_CTRL_REG', + 'regCGTS_SM_CTRL_REG_BASE_IDX', 'regCGTS_TCC_DISABLE', + 'regCGTS_TCC_DISABLE_BASE_IDX', 'regCGTS_USER_TCC_DISABLE', + 'regCGTS_USER_TCC_DISABLE_BASE_IDX', 'regCGTT_BCI_CLK_CTRL', + 'regCGTT_BCI_CLK_CTRL_BASE_IDX', 'regCGTT_CPC_CLK_CTRL', + 'regCGTT_CPC_CLK_CTRL_BASE_IDX', 'regCGTT_CP_CLK_CTRL', + 'regCGTT_CP_CLK_CTRL_BASE_IDX', 'regCGTT_IA_CLK_CTRL', + 'regCGTT_IA_CLK_CTRL_BASE_IDX', 'regCGTT_PA_CLK_CTRL', + 'regCGTT_PA_CLK_CTRL_BASE_IDX', 'regCGTT_PC_CLK_CTRL', + 'regCGTT_PC_CLK_CTRL_BASE_IDX', 'regCGTT_RLC_CLK_CTRL', + 'regCGTT_RLC_CLK_CTRL_BASE_IDX', 'regCGTT_SC_CLK_CTRL0', + 'regCGTT_SC_CLK_CTRL0_BASE_IDX', 'regCGTT_SC_CLK_CTRL1', + 'regCGTT_SC_CLK_CTRL1_BASE_IDX', 'regCGTT_SC_CLK_CTRL2', + 'regCGTT_SC_CLK_CTRL2_BASE_IDX', 'regCGTT_SPIS_CLK_CTRL', + 'regCGTT_SPIS_CLK_CTRL_BASE_IDX', 'regCGTT_SPI_CLK_CTRL', + 'regCGTT_SPI_CLK_CTRL_BASE_IDX', 'regCGTT_SPI_PS_CLK_CTRL', + 'regCGTT_SPI_PS_CLK_CTRL_BASE_IDX', 'regCGTT_SQG_CLK_CTRL', + 'regCGTT_SQG_CLK_CTRL_BASE_IDX', 'regCGTT_SQ_CLK_CTRL', + 'regCGTT_SQ_CLK_CTRL_BASE_IDX', 'regCGTT_TCPF_CLK_CTRL', + 'regCGTT_TCPF_CLK_CTRL_BASE_IDX', 'regCGTT_TCPI_CLK_CTRL', + 'regCGTT_TCPI_CLK_CTRL_BASE_IDX', 'regCGTT_VGT_CLK_CTRL', + 'regCGTT_VGT_CLK_CTRL_BASE_IDX', 'regCGTT_WD_CLK_CTRL', + 'regCGTT_WD_CLK_CTRL_BASE_IDX', 'regCGTX_SPI_DEBUG_CLK_CTRL', + 'regCGTX_SPI_DEBUG_CLK_CTRL_BASE_IDX', 'regCOHER_DEST_BASE_0', + 'regCOHER_DEST_BASE_0_BASE_IDX', 'regCOHER_DEST_BASE_1', + 'regCOHER_DEST_BASE_1_BASE_IDX', 'regCOHER_DEST_BASE_2', + 'regCOHER_DEST_BASE_2_BASE_IDX', 'regCOHER_DEST_BASE_3', + 'regCOHER_DEST_BASE_3_BASE_IDX', 'regCOHER_DEST_BASE_HI_0', + 'regCOHER_DEST_BASE_HI_0_BASE_IDX', 'regCOHER_DEST_BASE_HI_1', + 'regCOHER_DEST_BASE_HI_1_BASE_IDX', 'regCOHER_DEST_BASE_HI_2', + 'regCOHER_DEST_BASE_HI_2_BASE_IDX', 'regCOHER_DEST_BASE_HI_3', + 'regCOHER_DEST_BASE_HI_3_BASE_IDX', + 'regCOMPUTE_CURRENT_LOGIC_XCC_ID', + 'regCOMPUTE_CURRENT_LOGIC_XCC_ID_BASE_IDX', 'regCOMPUTE_DIM_X', + 'regCOMPUTE_DIM_X_BASE_IDX', 'regCOMPUTE_DIM_Y', + 'regCOMPUTE_DIM_Y_BASE_IDX', 'regCOMPUTE_DIM_Z', + 'regCOMPUTE_DIM_Z_BASE_IDX', 'regCOMPUTE_DISPATCH_END', + 'regCOMPUTE_DISPATCH_END_BASE_IDX', 'regCOMPUTE_DISPATCH_ID', + 'regCOMPUTE_DISPATCH_ID_BASE_IDX', + 'regCOMPUTE_DISPATCH_INITIATOR', + 'regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX', + 'regCOMPUTE_DISPATCH_PKT_ADDR_HI', + 'regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX', + 'regCOMPUTE_DISPATCH_PKT_ADDR_LO', + 'regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX', + 'regCOMPUTE_DISPATCH_SCRATCH_BASE_HI', + 'regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX', + 'regCOMPUTE_DISPATCH_SCRATCH_BASE_LO', + 'regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX', + 'regCOMPUTE_MISC_RESERVED', 'regCOMPUTE_MISC_RESERVED_BASE_IDX', + 'regCOMPUTE_NOWHERE', 'regCOMPUTE_NOWHERE_BASE_IDX', + 'regCOMPUTE_NUM_THREAD_X', 'regCOMPUTE_NUM_THREAD_X_BASE_IDX', + 'regCOMPUTE_NUM_THREAD_Y', 'regCOMPUTE_NUM_THREAD_Y_BASE_IDX', + 'regCOMPUTE_NUM_THREAD_Z', 'regCOMPUTE_NUM_THREAD_Z_BASE_IDX', + 'regCOMPUTE_PERFCOUNT_ENABLE', + 'regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX', 'regCOMPUTE_PGM_HI', + 'regCOMPUTE_PGM_HI_BASE_IDX', 'regCOMPUTE_PGM_LO', + 'regCOMPUTE_PGM_LO_BASE_IDX', 'regCOMPUTE_PGM_RSRC1', + 'regCOMPUTE_PGM_RSRC1_BASE_IDX', 'regCOMPUTE_PGM_RSRC2', + 'regCOMPUTE_PGM_RSRC2_BASE_IDX', 'regCOMPUTE_PGM_RSRC3', + 'regCOMPUTE_PGM_RSRC3_BASE_IDX', 'regCOMPUTE_PIPELINESTAT_ENABLE', + 'regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX', 'regCOMPUTE_RELAUNCH', + 'regCOMPUTE_RELAUNCH_BASE_IDX', 'regCOMPUTE_RESOURCE_LIMITS', + 'regCOMPUTE_RESOURCE_LIMITS_BASE_IDX', 'regCOMPUTE_RESTART_X', + 'regCOMPUTE_RESTART_X_BASE_IDX', 'regCOMPUTE_RESTART_Y', + 'regCOMPUTE_RESTART_Y_BASE_IDX', 'regCOMPUTE_RESTART_Z', + 'regCOMPUTE_RESTART_Z_BASE_IDX', 'regCOMPUTE_SHADER_CHKSUM', + 'regCOMPUTE_SHADER_CHKSUM_BASE_IDX', 'regCOMPUTE_START_X', + 'regCOMPUTE_START_X_BASE_IDX', 'regCOMPUTE_START_Y', + 'regCOMPUTE_START_Y_BASE_IDX', 'regCOMPUTE_START_Z', + 'regCOMPUTE_START_Z_BASE_IDX', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE0', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE1', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE2', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE3', + 'regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX', + 'regCOMPUTE_TG_CHUNK_SIZE', 'regCOMPUTE_TG_CHUNK_SIZE_BASE_IDX', + 'regCOMPUTE_THREADGROUP_ID', 'regCOMPUTE_THREADGROUP_ID_BASE_IDX', + 'regCOMPUTE_THREAD_TRACE_ENABLE', + 'regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX', + 'regCOMPUTE_TMPRING_SIZE', 'regCOMPUTE_TMPRING_SIZE_BASE_IDX', + 'regCOMPUTE_USER_DATA_0', 'regCOMPUTE_USER_DATA_0_BASE_IDX', + 'regCOMPUTE_USER_DATA_1', 'regCOMPUTE_USER_DATA_10', + 'regCOMPUTE_USER_DATA_10_BASE_IDX', 'regCOMPUTE_USER_DATA_11', + 'regCOMPUTE_USER_DATA_11_BASE_IDX', 'regCOMPUTE_USER_DATA_12', + 'regCOMPUTE_USER_DATA_12_BASE_IDX', 'regCOMPUTE_USER_DATA_13', + 'regCOMPUTE_USER_DATA_13_BASE_IDX', 'regCOMPUTE_USER_DATA_14', + 'regCOMPUTE_USER_DATA_14_BASE_IDX', 'regCOMPUTE_USER_DATA_15', + 'regCOMPUTE_USER_DATA_15_BASE_IDX', + 'regCOMPUTE_USER_DATA_1_BASE_IDX', 'regCOMPUTE_USER_DATA_2', + 'regCOMPUTE_USER_DATA_2_BASE_IDX', 'regCOMPUTE_USER_DATA_3', + 'regCOMPUTE_USER_DATA_3_BASE_IDX', 'regCOMPUTE_USER_DATA_4', + 'regCOMPUTE_USER_DATA_4_BASE_IDX', 'regCOMPUTE_USER_DATA_5', + 'regCOMPUTE_USER_DATA_5_BASE_IDX', 'regCOMPUTE_USER_DATA_6', + 'regCOMPUTE_USER_DATA_6_BASE_IDX', 'regCOMPUTE_USER_DATA_7', + 'regCOMPUTE_USER_DATA_7_BASE_IDX', 'regCOMPUTE_USER_DATA_8', + 'regCOMPUTE_USER_DATA_8_BASE_IDX', 'regCOMPUTE_USER_DATA_9', + 'regCOMPUTE_USER_DATA_9_BASE_IDX', 'regCOMPUTE_VMID', + 'regCOMPUTE_VMID_BASE_IDX', 'regCOMPUTE_WAVE_RESTORE_ADDR_HI', + 'regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX', + 'regCOMPUTE_WAVE_RESTORE_ADDR_LO', + 'regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX', + 'regCPC_CE_ERR_STATUS_HI', 'regCPC_CE_ERR_STATUS_HI_BASE_IDX', + 'regCPC_CE_ERR_STATUS_LO', 'regCPC_CE_ERR_STATUS_LO_BASE_IDX', + 'regCPC_INT_ADDR', 'regCPC_INT_ADDR_BASE_IDX', 'regCPC_INT_CNTL', + 'regCPC_INT_CNTL_BASE_IDX', 'regCPC_INT_CNTX_ID', + 'regCPC_INT_CNTX_ID_BASE_IDX', 'regCPC_INT_INFO', + 'regCPC_INT_INFO_BASE_IDX', 'regCPC_INT_PASID', + 'regCPC_INT_PASID_BASE_IDX', 'regCPC_INT_STATUS', + 'regCPC_INT_STATUS_BASE_IDX', 'regCPC_LATENCY_STATS_DATA', + 'regCPC_LATENCY_STATS_DATA_BASE_IDX', + 'regCPC_LATENCY_STATS_SELECT', + 'regCPC_LATENCY_STATS_SELECT_BASE_IDX', 'regCPC_PERFCOUNTER0_HI', + 'regCPC_PERFCOUNTER0_HI_BASE_IDX', 'regCPC_PERFCOUNTER0_LO', + 'regCPC_PERFCOUNTER0_LO_BASE_IDX', 'regCPC_PERFCOUNTER0_SELECT', + 'regCPC_PERFCOUNTER0_SELECT1', + 'regCPC_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regCPC_PERFCOUNTER0_SELECT_BASE_IDX', 'regCPC_PERFCOUNTER1_HI', + 'regCPC_PERFCOUNTER1_HI_BASE_IDX', 'regCPC_PERFCOUNTER1_LO', + 'regCPC_PERFCOUNTER1_LO_BASE_IDX', 'regCPC_PERFCOUNTER1_SELECT', + 'regCPC_PERFCOUNTER1_SELECT_BASE_IDX', 'regCPC_PSP_DEBUG', + 'regCPC_PSP_DEBUG_BASE_IDX', 'regCPC_UE_ERR_STATUS_HI', + 'regCPC_UE_ERR_STATUS_HI_BASE_IDX', 'regCPC_UE_ERR_STATUS_LO', + 'regCPC_UE_ERR_STATUS_LO_BASE_IDX', 'regCPC_UTCL1_CNTL', + 'regCPC_UTCL1_CNTL_BASE_IDX', 'regCPC_UTCL1_ERROR', + 'regCPC_UTCL1_ERROR_BASE_IDX', 'regCPC_UTCL1_STATUS', + 'regCPC_UTCL1_STATUS_BASE_IDX', 'regCPF_CE_ERR_STATUS_HI', + 'regCPF_CE_ERR_STATUS_HI_BASE_IDX', 'regCPF_CE_ERR_STATUS_LO', + 'regCPF_CE_ERR_STATUS_LO_BASE_IDX', 'regCPF_LATENCY_STATS_DATA', + 'regCPF_LATENCY_STATS_DATA_BASE_IDX', + 'regCPF_LATENCY_STATS_SELECT', + 'regCPF_LATENCY_STATS_SELECT_BASE_IDX', 'regCPF_PERFCOUNTER0_HI', + 'regCPF_PERFCOUNTER0_HI_BASE_IDX', 'regCPF_PERFCOUNTER0_LO', + 'regCPF_PERFCOUNTER0_LO_BASE_IDX', 'regCPF_PERFCOUNTER0_SELECT', + 'regCPF_PERFCOUNTER0_SELECT1', + 'regCPF_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regCPF_PERFCOUNTER0_SELECT_BASE_IDX', 'regCPF_PERFCOUNTER1_HI', + 'regCPF_PERFCOUNTER1_HI_BASE_IDX', 'regCPF_PERFCOUNTER1_LO', + 'regCPF_PERFCOUNTER1_LO_BASE_IDX', 'regCPF_PERFCOUNTER1_SELECT', + 'regCPF_PERFCOUNTER1_SELECT_BASE_IDX', + 'regCPF_TC_PERF_COUNTER_WINDOW_SELECT', + 'regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX', + 'regCPF_UE_ERR_STATUS_HI', 'regCPF_UE_ERR_STATUS_HI_BASE_IDX', + 'regCPF_UE_ERR_STATUS_LO', 'regCPF_UE_ERR_STATUS_LO_BASE_IDX', + 'regCPF_UTCL1_CNTL', 'regCPF_UTCL1_CNTL_BASE_IDX', + 'regCPF_UTCL1_STATUS', 'regCPF_UTCL1_STATUS_BASE_IDX', + 'regCPG_CE_ERR_STATUS_HI', 'regCPG_CE_ERR_STATUS_HI_BASE_IDX', + 'regCPG_CE_ERR_STATUS_LO', 'regCPG_CE_ERR_STATUS_LO_BASE_IDX', + 'regCPG_LATENCY_STATS_DATA', 'regCPG_LATENCY_STATS_DATA_BASE_IDX', + 'regCPG_LATENCY_STATS_SELECT', + 'regCPG_LATENCY_STATS_SELECT_BASE_IDX', 'regCPG_PERFCOUNTER0_HI', + 'regCPG_PERFCOUNTER0_HI_BASE_IDX', 'regCPG_PERFCOUNTER0_LO', + 'regCPG_PERFCOUNTER0_LO_BASE_IDX', 'regCPG_PERFCOUNTER0_SELECT', + 'regCPG_PERFCOUNTER0_SELECT1', + 'regCPG_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regCPG_PERFCOUNTER0_SELECT_BASE_IDX', 'regCPG_PERFCOUNTER1_HI', + 'regCPG_PERFCOUNTER1_HI_BASE_IDX', 'regCPG_PERFCOUNTER1_LO', + 'regCPG_PERFCOUNTER1_LO_BASE_IDX', 'regCPG_PERFCOUNTER1_SELECT', + 'regCPG_PERFCOUNTER1_SELECT_BASE_IDX', 'regCPG_PSP_DEBUG', + 'regCPG_PSP_DEBUG_BASE_IDX', + 'regCPG_TC_PERF_COUNTER_WINDOW_SELECT', + 'regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX', + 'regCPG_UE_ERR_STATUS_HI', 'regCPG_UE_ERR_STATUS_HI_BASE_IDX', + 'regCPG_UE_ERR_STATUS_LO', 'regCPG_UE_ERR_STATUS_LO_BASE_IDX', + 'regCPG_UTCL1_CNTL', 'regCPG_UTCL1_CNTL_BASE_IDX', + 'regCPG_UTCL1_ERROR', 'regCPG_UTCL1_ERROR_BASE_IDX', + 'regCPG_UTCL1_STATUS', 'regCPG_UTCL1_STATUS_BASE_IDX', + 'regCP_APPEND_ADDR_HI', 'regCP_APPEND_ADDR_HI_BASE_IDX', + 'regCP_APPEND_ADDR_LO', 'regCP_APPEND_ADDR_LO_BASE_IDX', + 'regCP_APPEND_DATA_HI', 'regCP_APPEND_DATA_HI_BASE_IDX', + 'regCP_APPEND_DATA_LO', 'regCP_APPEND_DATA_LO_BASE_IDX', + 'regCP_APPEND_LAST_CS_FENCE_HI', + 'regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX', + 'regCP_APPEND_LAST_CS_FENCE_LO', + 'regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX', + 'regCP_APPEND_LAST_PS_FENCE_HI', + 'regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX', + 'regCP_APPEND_LAST_PS_FENCE_LO', + 'regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX', 'regCP_AQL_SMM_STATUS', + 'regCP_AQL_SMM_STATUS_BASE_IDX', 'regCP_ATOMIC_PREOP_HI', + 'regCP_ATOMIC_PREOP_HI_BASE_IDX', 'regCP_ATOMIC_PREOP_LO', + 'regCP_ATOMIC_PREOP_LO_BASE_IDX', 'regCP_BUSY_STAT', + 'regCP_BUSY_STAT_BASE_IDX', 'regCP_CEQ1_AVAIL', + 'regCP_CEQ1_AVAIL_BASE_IDX', 'regCP_CEQ2_AVAIL', + 'regCP_CEQ2_AVAIL_BASE_IDX', 'regCP_CE_COMPARE_COUNT', + 'regCP_CE_COMPARE_COUNT_BASE_IDX', 'regCP_CE_COMPLETION_STATUS', + 'regCP_CE_COMPLETION_STATUS_BASE_IDX', 'regCP_CE_COUNTER', + 'regCP_CE_COUNTER_BASE_IDX', 'regCP_CE_DE_COUNT', + 'regCP_CE_DE_COUNT_BASE_IDX', 'regCP_CE_F32_INTERRUPT', + 'regCP_CE_F32_INTERRUPT_BASE_IDX', 'regCP_CE_HEADER_DUMP', + 'regCP_CE_HEADER_DUMP_BASE_IDX', 'regCP_CE_IB1_BASE_HI', + 'regCP_CE_IB1_BASE_HI_BASE_IDX', 'regCP_CE_IB1_BASE_LO', + 'regCP_CE_IB1_BASE_LO_BASE_IDX', 'regCP_CE_IB1_BUFSZ', + 'regCP_CE_IB1_BUFSZ_BASE_IDX', 'regCP_CE_IB1_CMD_BUFSZ', + 'regCP_CE_IB1_CMD_BUFSZ_BASE_IDX', 'regCP_CE_IB1_OFFSET', + 'regCP_CE_IB1_OFFSET_BASE_IDX', 'regCP_CE_IB2_BASE_HI', + 'regCP_CE_IB2_BASE_HI_BASE_IDX', 'regCP_CE_IB2_BASE_LO', + 'regCP_CE_IB2_BASE_LO_BASE_IDX', 'regCP_CE_IB2_BUFSZ', + 'regCP_CE_IB2_BUFSZ_BASE_IDX', 'regCP_CE_IB2_CMD_BUFSZ', + 'regCP_CE_IB2_CMD_BUFSZ_BASE_IDX', 'regCP_CE_IB2_OFFSET', + 'regCP_CE_IB2_OFFSET_BASE_IDX', 'regCP_CE_INIT_BASE_HI', + 'regCP_CE_INIT_BASE_HI_BASE_IDX', 'regCP_CE_INIT_BASE_LO', + 'regCP_CE_INIT_BASE_LO_BASE_IDX', 'regCP_CE_INIT_BUFSZ', + 'regCP_CE_INIT_BUFSZ_BASE_IDX', 'regCP_CE_INIT_CMD_BUFSZ', + 'regCP_CE_INIT_CMD_BUFSZ_BASE_IDX', 'regCP_CE_INSTR_PNTR', + 'regCP_CE_INSTR_PNTR_BASE_IDX', 'regCP_CE_INTR_ROUTINE_START', + 'regCP_CE_INTR_ROUTINE_START_BASE_IDX', + 'regCP_CE_METADATA_BASE_ADDR', + 'regCP_CE_METADATA_BASE_ADDR_BASE_IDX', + 'regCP_CE_METADATA_BASE_ADDR_HI', + 'regCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX', + 'regCP_CE_PRGRM_CNTR_START', 'regCP_CE_PRGRM_CNTR_START_BASE_IDX', + 'regCP_CE_RB_OFFSET', 'regCP_CE_RB_OFFSET_BASE_IDX', + 'regCP_CE_ROQ_IB1_STAT', 'regCP_CE_ROQ_IB1_STAT_BASE_IDX', + 'regCP_CE_ROQ_IB2_STAT', 'regCP_CE_ROQ_IB2_STAT_BASE_IDX', + 'regCP_CE_ROQ_RB_STAT', 'regCP_CE_ROQ_RB_STAT_BASE_IDX', + 'regCP_CE_UCODE_ADDR', 'regCP_CE_UCODE_ADDR_BASE_IDX', + 'regCP_CE_UCODE_DATA', 'regCP_CE_UCODE_DATA_BASE_IDX', + 'regCP_CMD_DATA', 'regCP_CMD_DATA_BASE_IDX', 'regCP_CMD_INDEX', + 'regCP_CMD_INDEX_BASE_IDX', 'regCP_CNTX_STAT', + 'regCP_CNTX_STAT_BASE_IDX', 'regCP_COHER_BASE', + 'regCP_COHER_BASE_BASE_IDX', 'regCP_COHER_BASE_HI', + 'regCP_COHER_BASE_HI_BASE_IDX', 'regCP_COHER_CNTL', + 'regCP_COHER_CNTL_BASE_IDX', 'regCP_COHER_SIZE', + 'regCP_COHER_SIZE_BASE_IDX', 'regCP_COHER_SIZE_HI', + 'regCP_COHER_SIZE_HI_BASE_IDX', 'regCP_COHER_START_DELAY', + 'regCP_COHER_START_DELAY_BASE_IDX', 'regCP_COHER_STATUS', + 'regCP_COHER_STATUS_BASE_IDX', 'regCP_CONTEXT_CNTL', + 'regCP_CONTEXT_CNTL_BASE_IDX', 'regCP_CPC_BUSY_STAT', + 'regCP_CPC_BUSY_STAT_BASE_IDX', 'regCP_CPC_DEBUG', + 'regCP_CPC_DEBUG_2', 'regCP_CPC_DEBUG_2_BASE_IDX', + 'regCP_CPC_DEBUG_BASE_IDX', 'regCP_CPC_DEBUG_CNTL', + 'regCP_CPC_DEBUG_CNTL_BASE_IDX', 'regCP_CPC_DSM_CNTL', + 'regCP_CPC_DSM_CNTL2', 'regCP_CPC_DSM_CNTL2A', + 'regCP_CPC_DSM_CNTL2A_BASE_IDX', 'regCP_CPC_DSM_CNTL2_BASE_IDX', + 'regCP_CPC_DSM_CNTL_BASE_IDX', 'regCP_CPC_GFX_CNTL', + 'regCP_CPC_GFX_CNTL_BASE_IDX', 'regCP_CPC_GRBM_FREE_COUNT', + 'regCP_CPC_GRBM_FREE_COUNT_BASE_IDX', 'regCP_CPC_HALT_HYST_COUNT', + 'regCP_CPC_HALT_HYST_COUNT_BASE_IDX', 'regCP_CPC_IC_BASE_CNTL', + 'regCP_CPC_IC_BASE_CNTL_BASE_IDX', 'regCP_CPC_IC_BASE_HI', + 'regCP_CPC_IC_BASE_HI_BASE_IDX', 'regCP_CPC_IC_BASE_LO', + 'regCP_CPC_IC_BASE_LO_BASE_IDX', 'regCP_CPC_IC_OP_CNTL', + 'regCP_CPC_IC_OP_CNTL_BASE_IDX', 'regCP_CPC_MGCG_SYNC_CNTL', + 'regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX', + 'regCP_CPC_PRIV_VIOLATION_ADDR', + 'regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX', + 'regCP_CPC_SCRATCH_DATA', 'regCP_CPC_SCRATCH_DATA_BASE_IDX', + 'regCP_CPC_SCRATCH_INDEX', 'regCP_CPC_SCRATCH_INDEX_BASE_IDX', + 'regCP_CPC_STALLED_STAT1', 'regCP_CPC_STALLED_STAT1_BASE_IDX', + 'regCP_CPC_STATUS', 'regCP_CPC_STATUS_BASE_IDX', + 'regCP_CPF_BUSY_STAT', 'regCP_CPF_BUSY_STAT_BASE_IDX', + 'regCP_CPF_DEBUG', 'regCP_CPF_DEBUG_BASE_IDX', + 'regCP_CPF_DEBUG_CNTL', 'regCP_CPF_DEBUG_CNTL_BASE_IDX', + 'regCP_CPF_DSM_CNTL', 'regCP_CPF_DSM_CNTL2', + 'regCP_CPF_DSM_CNTL2A', 'regCP_CPF_DSM_CNTL2A_BASE_IDX', + 'regCP_CPF_DSM_CNTL2_BASE_IDX', 'regCP_CPF_DSM_CNTL_BASE_IDX', + 'regCP_CPF_GRBM_FREE_COUNT', 'regCP_CPF_GRBM_FREE_COUNT_BASE_IDX', + 'regCP_CPF_STALLED_STAT1', 'regCP_CPF_STALLED_STAT1_BASE_IDX', + 'regCP_CPF_STATUS', 'regCP_CPF_STATUS_BASE_IDX', + 'regCP_CPG_DSM_CNTL', 'regCP_CPG_DSM_CNTL2', + 'regCP_CPG_DSM_CNTL2A', 'regCP_CPG_DSM_CNTL2A_BASE_IDX', + 'regCP_CPG_DSM_CNTL2_BASE_IDX', 'regCP_CPG_DSM_CNTL_BASE_IDX', + 'regCP_CSF_STAT', 'regCP_CSF_STAT_BASE_IDX', 'regCP_DEBUG', + 'regCP_DEBUG_BASE_IDX', 'regCP_DEBUG_CNTL', + 'regCP_DEBUG_CNTL_BASE_IDX', 'regCP_DEVICE_ID', + 'regCP_DEVICE_ID_BASE_IDX', 'regCP_DE_CE_COUNT', + 'regCP_DE_CE_COUNT_BASE_IDX', 'regCP_DE_DE_COUNT', + 'regCP_DE_DE_COUNT_BASE_IDX', 'regCP_DE_LAST_INVAL_COUNT', + 'regCP_DE_LAST_INVAL_COUNT_BASE_IDX', 'regCP_DFY_ADDR_HI', + 'regCP_DFY_ADDR_HI_BASE_IDX', 'regCP_DFY_ADDR_LO', + 'regCP_DFY_ADDR_LO_BASE_IDX', 'regCP_DFY_CMD', + 'regCP_DFY_CMD_BASE_IDX', 'regCP_DFY_CNTL', + 'regCP_DFY_CNTL_BASE_IDX', 'regCP_DFY_DATA_0', + 'regCP_DFY_DATA_0_BASE_IDX', 'regCP_DFY_DATA_1', + 'regCP_DFY_DATA_10', 'regCP_DFY_DATA_10_BASE_IDX', + 'regCP_DFY_DATA_11', 'regCP_DFY_DATA_11_BASE_IDX', + 'regCP_DFY_DATA_12', 'regCP_DFY_DATA_12_BASE_IDX', + 'regCP_DFY_DATA_13', 'regCP_DFY_DATA_13_BASE_IDX', + 'regCP_DFY_DATA_14', 'regCP_DFY_DATA_14_BASE_IDX', + 'regCP_DFY_DATA_15', 'regCP_DFY_DATA_15_BASE_IDX', + 'regCP_DFY_DATA_1_BASE_IDX', 'regCP_DFY_DATA_2', + 'regCP_DFY_DATA_2_BASE_IDX', 'regCP_DFY_DATA_3', + 'regCP_DFY_DATA_3_BASE_IDX', 'regCP_DFY_DATA_4', + 'regCP_DFY_DATA_4_BASE_IDX', 'regCP_DFY_DATA_5', + 'regCP_DFY_DATA_5_BASE_IDX', 'regCP_DFY_DATA_6', + 'regCP_DFY_DATA_6_BASE_IDX', 'regCP_DFY_DATA_7', + 'regCP_DFY_DATA_7_BASE_IDX', 'regCP_DFY_DATA_8', + 'regCP_DFY_DATA_8_BASE_IDX', 'regCP_DFY_DATA_9', + 'regCP_DFY_DATA_9_BASE_IDX', 'regCP_DFY_STAT', + 'regCP_DFY_STAT_BASE_IDX', 'regCP_DISPATCH_INDR_ADDR', + 'regCP_DISPATCH_INDR_ADDR_BASE_IDX', + 'regCP_DISPATCH_INDR_ADDR_HI', + 'regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX', 'regCP_DMA_CNTL', + 'regCP_DMA_CNTL_BASE_IDX', 'regCP_DMA_ME_COMMAND', + 'regCP_DMA_ME_COMMAND_BASE_IDX', 'regCP_DMA_ME_CONTROL', + 'regCP_DMA_ME_CONTROL_BASE_IDX', 'regCP_DMA_ME_DST_ADDR', + 'regCP_DMA_ME_DST_ADDR_BASE_IDX', 'regCP_DMA_ME_DST_ADDR_HI', + 'regCP_DMA_ME_DST_ADDR_HI_BASE_IDX', 'regCP_DMA_ME_SRC_ADDR', + 'regCP_DMA_ME_SRC_ADDR_BASE_IDX', 'regCP_DMA_ME_SRC_ADDR_HI', + 'regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX', 'regCP_DMA_PFP_COMMAND', + 'regCP_DMA_PFP_COMMAND_BASE_IDX', 'regCP_DMA_PFP_CONTROL', + 'regCP_DMA_PFP_CONTROL_BASE_IDX', 'regCP_DMA_PFP_DST_ADDR', + 'regCP_DMA_PFP_DST_ADDR_BASE_IDX', 'regCP_DMA_PFP_DST_ADDR_HI', + 'regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX', 'regCP_DMA_PFP_SRC_ADDR', + 'regCP_DMA_PFP_SRC_ADDR_BASE_IDX', 'regCP_DMA_PFP_SRC_ADDR_HI', + 'regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX', 'regCP_DMA_READ_TAGS', + 'regCP_DMA_READ_TAGS_BASE_IDX', 'regCP_DRAW_INDX_INDR_ADDR', + 'regCP_DRAW_INDX_INDR_ADDR_BASE_IDX', + 'regCP_DRAW_INDX_INDR_ADDR_HI', + 'regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX', 'regCP_DRAW_OBJECT', + 'regCP_DRAW_OBJECT_BASE_IDX', 'regCP_DRAW_OBJECT_COUNTER', + 'regCP_DRAW_OBJECT_COUNTER_BASE_IDX', 'regCP_DRAW_WINDOW_CNTL', + 'regCP_DRAW_WINDOW_CNTL_BASE_IDX', 'regCP_DRAW_WINDOW_HI', + 'regCP_DRAW_WINDOW_HI_BASE_IDX', 'regCP_DRAW_WINDOW_LO', + 'regCP_DRAW_WINDOW_LO_BASE_IDX', 'regCP_DRAW_WINDOW_MASK_HI', + 'regCP_DRAW_WINDOW_MASK_HI_BASE_IDX', + 'regCP_ECC_DMA_FIRST_OCCURRENCE', + 'regCP_ECC_DMA_FIRST_OCCURRENCE_BASE_IDX', + 'regCP_ECC_FIRSTOCCURRENCE', 'regCP_ECC_FIRSTOCCURRENCE_BASE_IDX', + 'regCP_ECC_FIRSTOCCURRENCE_RING0', + 'regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX', + 'regCP_ECC_FIRSTOCCURRENCE_RING1', + 'regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX', + 'regCP_ECC_FIRSTOCCURRENCE_RING2', + 'regCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX', 'regCP_EDC_FUE_CNTL', + 'regCP_EDC_FUE_CNTL_BASE_IDX', 'regCP_EOPQ_WAIT_TIME', + 'regCP_EOPQ_WAIT_TIME_BASE_IDX', 'regCP_EOP_DONE_ADDR_HI', + 'regCP_EOP_DONE_ADDR_HI_BASE_IDX', 'regCP_EOP_DONE_ADDR_LO', + 'regCP_EOP_DONE_ADDR_LO_BASE_IDX', 'regCP_EOP_DONE_CNTX_ID', + 'regCP_EOP_DONE_CNTX_ID_BASE_IDX', 'regCP_EOP_DONE_DATA_CNTL', + 'regCP_EOP_DONE_DATA_CNTL_BASE_IDX', 'regCP_EOP_DONE_DATA_HI', + 'regCP_EOP_DONE_DATA_HI_BASE_IDX', 'regCP_EOP_DONE_DATA_LO', + 'regCP_EOP_DONE_DATA_LO_BASE_IDX', 'regCP_EOP_DONE_EVENT_CNTL', + 'regCP_EOP_DONE_EVENT_CNTL_BASE_IDX', 'regCP_EOP_LAST_FENCE_HI', + 'regCP_EOP_LAST_FENCE_HI_BASE_IDX', 'regCP_EOP_LAST_FENCE_LO', + 'regCP_EOP_LAST_FENCE_LO_BASE_IDX', 'regCP_FATAL_ERROR', + 'regCP_FATAL_ERROR_BASE_IDX', 'regCP_GDS_ATOMIC0_PREOP_HI', + 'regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX', + 'regCP_GDS_ATOMIC0_PREOP_LO', + 'regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX', + 'regCP_GDS_ATOMIC1_PREOP_HI', + 'regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX', + 'regCP_GDS_ATOMIC1_PREOP_LO', + 'regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'regCP_GDS_BKUP_ADDR', + 'regCP_GDS_BKUP_ADDR_BASE_IDX', 'regCP_GDS_BKUP_ADDR_HI', + 'regCP_GDS_BKUP_ADDR_HI_BASE_IDX', 'regCP_GFX_ERROR', + 'regCP_GFX_ERROR_BASE_IDX', 'regCP_GFX_MQD_BASE_ADDR', + 'regCP_GFX_MQD_BASE_ADDR_BASE_IDX', 'regCP_GFX_MQD_BASE_ADDR_HI', + 'regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX', 'regCP_GFX_MQD_CONTROL', + 'regCP_GFX_MQD_CONTROL_BASE_IDX', 'regCP_GRBM_FREE_COUNT', + 'regCP_GRBM_FREE_COUNT_BASE_IDX', 'regCP_HPD_ROQ_OFFSETS', + 'regCP_HPD_ROQ_OFFSETS_BASE_IDX', 'regCP_HPD_STATUS0', + 'regCP_HPD_STATUS0_BASE_IDX', 'regCP_HPD_UTCL1_CNTL', + 'regCP_HPD_UTCL1_CNTL_BASE_IDX', 'regCP_HPD_UTCL1_ERROR', + 'regCP_HPD_UTCL1_ERROR_ADDR', + 'regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX', + 'regCP_HPD_UTCL1_ERROR_BASE_IDX', 'regCP_HQD_ACTIVE', + 'regCP_HQD_ACTIVE_BASE_IDX', 'regCP_HQD_AQL_CONTROL', + 'regCP_HQD_AQL_CONTROL_1', 'regCP_HQD_AQL_CONTROL_1_BASE_IDX', + 'regCP_HQD_AQL_CONTROL_BASE_IDX', 'regCP_HQD_AQL_DISPATCH_ID', + 'regCP_HQD_AQL_DISPATCH_ID_BASE_IDX', + 'regCP_HQD_AQL_DISPATCH_ID_HI', + 'regCP_HQD_AQL_DISPATCH_ID_HI_BASE_IDX', + 'regCP_HQD_ATOMIC0_PREOP_HI', + 'regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX', + 'regCP_HQD_ATOMIC0_PREOP_LO', + 'regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX', + 'regCP_HQD_ATOMIC1_PREOP_HI', + 'regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX', + 'regCP_HQD_ATOMIC1_PREOP_LO', + 'regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX', + 'regCP_HQD_CNTL_STACK_OFFSET', + 'regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX', + 'regCP_HQD_CNTL_STACK_SIZE', 'regCP_HQD_CNTL_STACK_SIZE_BASE_IDX', + 'regCP_HQD_CTX_SAVE_BASE_ADDR_HI', + 'regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX', + 'regCP_HQD_CTX_SAVE_BASE_ADDR_LO', + 'regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX', + 'regCP_HQD_CTX_SAVE_CONTROL', + 'regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX', 'regCP_HQD_CTX_SAVE_SIZE', + 'regCP_HQD_CTX_SAVE_SIZE_BASE_IDX', 'regCP_HQD_DEQUEUE_REQUEST', + 'regCP_HQD_DEQUEUE_REQUEST_BASE_IDX', 'regCP_HQD_DMA_OFFLOAD', + 'regCP_HQD_DMA_OFFLOAD_BASE_IDX', 'regCP_HQD_EOP_BASE_ADDR', + 'regCP_HQD_EOP_BASE_ADDR_BASE_IDX', 'regCP_HQD_EOP_BASE_ADDR_HI', + 'regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX', 'regCP_HQD_EOP_CONTROL', + 'regCP_HQD_EOP_CONTROL_BASE_IDX', 'regCP_HQD_EOP_EVENTS', + 'regCP_HQD_EOP_EVENTS_BASE_IDX', 'regCP_HQD_EOP_RPTR', + 'regCP_HQD_EOP_RPTR_BASE_IDX', 'regCP_HQD_EOP_WPTR', + 'regCP_HQD_EOP_WPTR_BASE_IDX', 'regCP_HQD_EOP_WPTR_MEM', + 'regCP_HQD_EOP_WPTR_MEM_BASE_IDX', 'regCP_HQD_ERROR', + 'regCP_HQD_ERROR_BASE_IDX', 'regCP_HQD_GDS_RESOURCE_STATE', + 'regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX', 'regCP_HQD_GFX_CONTROL', + 'regCP_HQD_GFX_CONTROL_BASE_IDX', 'regCP_HQD_GFX_STATUS', + 'regCP_HQD_GFX_STATUS_BASE_IDX', 'regCP_HQD_HQ_CONTROL0', + 'regCP_HQD_HQ_CONTROL0_BASE_IDX', 'regCP_HQD_HQ_CONTROL1', + 'regCP_HQD_HQ_CONTROL1_BASE_IDX', 'regCP_HQD_HQ_SCHEDULER0', + 'regCP_HQD_HQ_SCHEDULER0_BASE_IDX', 'regCP_HQD_HQ_SCHEDULER1', + 'regCP_HQD_HQ_SCHEDULER1_BASE_IDX', 'regCP_HQD_HQ_STATUS0', + 'regCP_HQD_HQ_STATUS0_BASE_IDX', 'regCP_HQD_HQ_STATUS1', + 'regCP_HQD_HQ_STATUS1_BASE_IDX', 'regCP_HQD_IB_BASE_ADDR', + 'regCP_HQD_IB_BASE_ADDR_BASE_IDX', 'regCP_HQD_IB_BASE_ADDR_HI', + 'regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX', 'regCP_HQD_IB_CONTROL', + 'regCP_HQD_IB_CONTROL_BASE_IDX', 'regCP_HQD_IB_RPTR', + 'regCP_HQD_IB_RPTR_BASE_IDX', 'regCP_HQD_IQ_RPTR', + 'regCP_HQD_IQ_RPTR_BASE_IDX', 'regCP_HQD_IQ_TIMER', + 'regCP_HQD_IQ_TIMER_BASE_IDX', 'regCP_HQD_MSG_TYPE', + 'regCP_HQD_MSG_TYPE_BASE_IDX', 'regCP_HQD_OFFLOAD', + 'regCP_HQD_OFFLOAD_BASE_IDX', 'regCP_HQD_PERSISTENT_STATE', + 'regCP_HQD_PERSISTENT_STATE_BASE_IDX', 'regCP_HQD_PIPE_PRIORITY', + 'regCP_HQD_PIPE_PRIORITY_BASE_IDX', 'regCP_HQD_PQ_BASE', + 'regCP_HQD_PQ_BASE_BASE_IDX', 'regCP_HQD_PQ_BASE_HI', + 'regCP_HQD_PQ_BASE_HI_BASE_IDX', 'regCP_HQD_PQ_CONTROL', + 'regCP_HQD_PQ_CONTROL_BASE_IDX', 'regCP_HQD_PQ_DOORBELL_CONTROL', + 'regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX', 'regCP_HQD_PQ_RPTR', + 'regCP_HQD_PQ_RPTR_BASE_IDX', 'regCP_HQD_PQ_RPTR_REPORT_ADDR', + 'regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX', + 'regCP_HQD_PQ_RPTR_REPORT_ADDR_HI', + 'regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX', + 'regCP_HQD_PQ_WPTR_HI', 'regCP_HQD_PQ_WPTR_HI_BASE_IDX', + 'regCP_HQD_PQ_WPTR_LO', 'regCP_HQD_PQ_WPTR_LO_BASE_IDX', + 'regCP_HQD_PQ_WPTR_POLL_ADDR', + 'regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX', + 'regCP_HQD_PQ_WPTR_POLL_ADDR_HI', + 'regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX', 'regCP_HQD_QUANTUM', + 'regCP_HQD_QUANTUM_BASE_IDX', 'regCP_HQD_QUEUE_PRIORITY', + 'regCP_HQD_QUEUE_PRIORITY_BASE_IDX', 'regCP_HQD_SEMA_CMD', + 'regCP_HQD_SEMA_CMD_BASE_IDX', 'regCP_HQD_VMID', + 'regCP_HQD_VMID_BASE_IDX', 'regCP_HQD_WG_STATE_OFFSET', + 'regCP_HQD_WG_STATE_OFFSET_BASE_IDX', 'regCP_HYP_CE_UCODE_ADDR', + 'regCP_HYP_CE_UCODE_ADDR_BASE_IDX', 'regCP_HYP_CE_UCODE_CHKSUM', + 'regCP_HYP_CE_UCODE_CHKSUM_BASE_IDX', 'regCP_HYP_CE_UCODE_DATA', + 'regCP_HYP_CE_UCODE_DATA_BASE_IDX', 'regCP_HYP_MEC1_UCODE_ADDR', + 'regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX', 'regCP_HYP_MEC1_UCODE_DATA', + 'regCP_HYP_MEC1_UCODE_DATA_BASE_IDX', 'regCP_HYP_MEC2_UCODE_ADDR', + 'regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX', 'regCP_HYP_MEC2_UCODE_DATA', + 'regCP_HYP_MEC2_UCODE_DATA_BASE_IDX', + 'regCP_HYP_MEC_ME1_UCODE_CHKSUM', + 'regCP_HYP_MEC_ME1_UCODE_CHKSUM_BASE_IDX', + 'regCP_HYP_MEC_ME2_UCODE_CHKSUM', + 'regCP_HYP_MEC_ME2_UCODE_CHKSUM_BASE_IDX', + 'regCP_HYP_ME_UCODE_ADDR', 'regCP_HYP_ME_UCODE_ADDR_BASE_IDX', + 'regCP_HYP_ME_UCODE_CHKSUM', 'regCP_HYP_ME_UCODE_CHKSUM_BASE_IDX', + 'regCP_HYP_ME_UCODE_DATA', 'regCP_HYP_ME_UCODE_DATA_BASE_IDX', + 'regCP_HYP_PFP_UCODE_ADDR', 'regCP_HYP_PFP_UCODE_ADDR_BASE_IDX', + 'regCP_HYP_PFP_UCODE_CHKSUM', + 'regCP_HYP_PFP_UCODE_CHKSUM_BASE_IDX', 'regCP_HYP_PFP_UCODE_DATA', + 'regCP_HYP_PFP_UCODE_DATA_BASE_IDX', 'regCP_HYP_XCP_CTL', + 'regCP_HYP_XCP_CTL_BASE_IDX', 'regCP_IB1_BASE_HI', + 'regCP_IB1_BASE_HI_BASE_IDX', 'regCP_IB1_BASE_LO', + 'regCP_IB1_BASE_LO_BASE_IDX', 'regCP_IB1_BUFSZ', + 'regCP_IB1_BUFSZ_BASE_IDX', 'regCP_IB1_CMD_BUFSZ', + 'regCP_IB1_CMD_BUFSZ_BASE_IDX', 'regCP_IB1_OFFSET', + 'regCP_IB1_OFFSET_BASE_IDX', 'regCP_IB1_PREAMBLE_BEGIN', + 'regCP_IB1_PREAMBLE_BEGIN_BASE_IDX', 'regCP_IB1_PREAMBLE_END', + 'regCP_IB1_PREAMBLE_END_BASE_IDX', 'regCP_IB2_BASE_HI', + 'regCP_IB2_BASE_HI_BASE_IDX', 'regCP_IB2_BASE_LO', + 'regCP_IB2_BASE_LO_BASE_IDX', 'regCP_IB2_BUFSZ', + 'regCP_IB2_BUFSZ_BASE_IDX', 'regCP_IB2_CMD_BUFSZ', + 'regCP_IB2_CMD_BUFSZ_BASE_IDX', 'regCP_IB2_OFFSET', + 'regCP_IB2_OFFSET_BASE_IDX', 'regCP_IB2_PREAMBLE_BEGIN', + 'regCP_IB2_PREAMBLE_BEGIN_BASE_IDX', 'regCP_IB2_PREAMBLE_END', + 'regCP_IB2_PREAMBLE_END_BASE_IDX', 'regCP_INDEX_BASE_ADDR', + 'regCP_INDEX_BASE_ADDR_BASE_IDX', 'regCP_INDEX_BASE_ADDR_HI', + 'regCP_INDEX_BASE_ADDR_HI_BASE_IDX', 'regCP_INDEX_TYPE', + 'regCP_INDEX_TYPE_BASE_IDX', 'regCP_INT_CNTL', + 'regCP_INT_CNTL_BASE_IDX', 'regCP_INT_CNTL_RING0', + 'regCP_INT_CNTL_RING0_BASE_IDX', 'regCP_INT_CNTL_RING1', + 'regCP_INT_CNTL_RING1_BASE_IDX', 'regCP_INT_CNTL_RING2', + 'regCP_INT_CNTL_RING2_BASE_IDX', 'regCP_INT_STATUS', + 'regCP_INT_STATUS_BASE_IDX', 'regCP_INT_STATUS_RING0', + 'regCP_INT_STATUS_RING0_BASE_IDX', 'regCP_INT_STATUS_RING1', + 'regCP_INT_STATUS_RING1_BASE_IDX', 'regCP_INT_STATUS_RING2', + 'regCP_INT_STATUS_RING2_BASE_IDX', 'regCP_INT_STAT_DEBUG', + 'regCP_INT_STAT_DEBUG_BASE_IDX', 'regCP_IQ_WAIT_TIME1', + 'regCP_IQ_WAIT_TIME1_BASE_IDX', 'regCP_IQ_WAIT_TIME2', + 'regCP_IQ_WAIT_TIME2_BASE_IDX', 'regCP_MAX_CONTEXT', + 'regCP_MAX_CONTEXT_BASE_IDX', 'regCP_ME0_PIPE0_PRIORITY', + 'regCP_ME0_PIPE0_PRIORITY_BASE_IDX', 'regCP_ME0_PIPE0_VMID', + 'regCP_ME0_PIPE0_VMID_BASE_IDX', 'regCP_ME0_PIPE1_PRIORITY', + 'regCP_ME0_PIPE1_PRIORITY_BASE_IDX', 'regCP_ME0_PIPE1_VMID', + 'regCP_ME0_PIPE1_VMID_BASE_IDX', 'regCP_ME0_PIPE2_PRIORITY', + 'regCP_ME0_PIPE2_PRIORITY_BASE_IDX', + 'regCP_ME0_PIPE_PRIORITY_CNTS', + 'regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX', + 'regCP_ME1_INT_STAT_DEBUG', 'regCP_ME1_INT_STAT_DEBUG_BASE_IDX', + 'regCP_ME1_PIPE0_INT_CNTL', 'regCP_ME1_PIPE0_INT_CNTL_BASE_IDX', + 'regCP_ME1_PIPE0_INT_STATUS', + 'regCP_ME1_PIPE0_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE0_PRIORITY', + 'regCP_ME1_PIPE0_PRIORITY_BASE_IDX', 'regCP_ME1_PIPE1_INT_CNTL', + 'regCP_ME1_PIPE1_INT_CNTL_BASE_IDX', 'regCP_ME1_PIPE1_INT_STATUS', + 'regCP_ME1_PIPE1_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE1_PRIORITY', + 'regCP_ME1_PIPE1_PRIORITY_BASE_IDX', 'regCP_ME1_PIPE2_INT_CNTL', + 'regCP_ME1_PIPE2_INT_CNTL_BASE_IDX', 'regCP_ME1_PIPE2_INT_STATUS', + 'regCP_ME1_PIPE2_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE2_PRIORITY', + 'regCP_ME1_PIPE2_PRIORITY_BASE_IDX', 'regCP_ME1_PIPE3_INT_CNTL', + 'regCP_ME1_PIPE3_INT_CNTL_BASE_IDX', 'regCP_ME1_PIPE3_INT_STATUS', + 'regCP_ME1_PIPE3_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE3_PRIORITY', + 'regCP_ME1_PIPE3_PRIORITY_BASE_IDX', + 'regCP_ME1_PIPE_PRIORITY_CNTS', + 'regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX', + 'regCP_ME2_INT_STAT_DEBUG', 'regCP_ME2_INT_STAT_DEBUG_BASE_IDX', + 'regCP_ME2_PIPE0_INT_CNTL', 'regCP_ME2_PIPE0_INT_CNTL_BASE_IDX', + 'regCP_ME2_PIPE0_INT_STATUS', + 'regCP_ME2_PIPE0_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE0_PRIORITY', + 'regCP_ME2_PIPE0_PRIORITY_BASE_IDX', 'regCP_ME2_PIPE1_INT_CNTL', + 'regCP_ME2_PIPE1_INT_CNTL_BASE_IDX', 'regCP_ME2_PIPE1_INT_STATUS', + 'regCP_ME2_PIPE1_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE1_PRIORITY', + 'regCP_ME2_PIPE1_PRIORITY_BASE_IDX', 'regCP_ME2_PIPE2_INT_CNTL', + 'regCP_ME2_PIPE2_INT_CNTL_BASE_IDX', 'regCP_ME2_PIPE2_INT_STATUS', + 'regCP_ME2_PIPE2_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE2_PRIORITY', + 'regCP_ME2_PIPE2_PRIORITY_BASE_IDX', 'regCP_ME2_PIPE3_INT_CNTL', + 'regCP_ME2_PIPE3_INT_CNTL_BASE_IDX', 'regCP_ME2_PIPE3_INT_STATUS', + 'regCP_ME2_PIPE3_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE3_PRIORITY', + 'regCP_ME2_PIPE3_PRIORITY_BASE_IDX', + 'regCP_ME2_PIPE_PRIORITY_CNTS', + 'regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX', + 'regCP_MEC1_F32_INTERRUPT', 'regCP_MEC1_F32_INTERRUPT_BASE_IDX', + 'regCP_MEC1_F32_INT_DIS', 'regCP_MEC1_F32_INT_DIS_BASE_IDX', + 'regCP_MEC1_INSTR_PNTR', 'regCP_MEC1_INSTR_PNTR_BASE_IDX', + 'regCP_MEC1_INTR_ROUTINE_START', + 'regCP_MEC1_INTR_ROUTINE_START_BASE_IDX', + 'regCP_MEC1_PRGRM_CNTR_START', + 'regCP_MEC1_PRGRM_CNTR_START_BASE_IDX', + 'regCP_MEC2_F32_INTERRUPT', 'regCP_MEC2_F32_INTERRUPT_BASE_IDX', + 'regCP_MEC2_F32_INT_DIS', 'regCP_MEC2_F32_INT_DIS_BASE_IDX', + 'regCP_MEC2_INSTR_PNTR', 'regCP_MEC2_INSTR_PNTR_BASE_IDX', + 'regCP_MEC2_INTR_ROUTINE_START', + 'regCP_MEC2_INTR_ROUTINE_START_BASE_IDX', + 'regCP_MEC2_PRGRM_CNTR_START', + 'regCP_MEC2_PRGRM_CNTR_START_BASE_IDX', 'regCP_MEC_CNTL', + 'regCP_MEC_CNTL_BASE_IDX', 'regCP_MEC_DOORBELL_RANGE_LOWER', + 'regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX', + 'regCP_MEC_DOORBELL_RANGE_UPPER', + 'regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX', + 'regCP_MEC_ME1_HEADER_DUMP', 'regCP_MEC_ME1_HEADER_DUMP_BASE_IDX', + 'regCP_MEC_ME1_UCODE_ADDR', 'regCP_MEC_ME1_UCODE_ADDR_BASE_IDX', + 'regCP_MEC_ME1_UCODE_DATA', 'regCP_MEC_ME1_UCODE_DATA_BASE_IDX', + 'regCP_MEC_ME2_HEADER_DUMP', 'regCP_MEC_ME2_HEADER_DUMP_BASE_IDX', + 'regCP_MEC_ME2_UCODE_ADDR', 'regCP_MEC_ME2_UCODE_ADDR_BASE_IDX', + 'regCP_MEC_ME2_UCODE_DATA', 'regCP_MEC_ME2_UCODE_DATA_BASE_IDX', + 'regCP_MEM_SLP_CNTL', 'regCP_MEM_SLP_CNTL_BASE_IDX', + 'regCP_MEQ_AVAIL', 'regCP_MEQ_AVAIL_BASE_IDX', 'regCP_MEQ_STAT', + 'regCP_MEQ_STAT_BASE_IDX', 'regCP_MEQ_STQ_THRESHOLD', + 'regCP_MEQ_STQ_THRESHOLD_BASE_IDX', 'regCP_MEQ_THRESHOLDS', + 'regCP_MEQ_THRESHOLDS_BASE_IDX', 'regCP_ME_ATOMIC_PREOP_HI', + 'regCP_ME_ATOMIC_PREOP_HI_BASE_IDX', 'regCP_ME_ATOMIC_PREOP_LO', + 'regCP_ME_ATOMIC_PREOP_LO_BASE_IDX', 'regCP_ME_CNTL', + 'regCP_ME_CNTL_BASE_IDX', 'regCP_ME_COHER_BASE', + 'regCP_ME_COHER_BASE_BASE_IDX', 'regCP_ME_COHER_BASE_HI', + 'regCP_ME_COHER_BASE_HI_BASE_IDX', 'regCP_ME_COHER_CNTL', + 'regCP_ME_COHER_CNTL_BASE_IDX', 'regCP_ME_COHER_SIZE', + 'regCP_ME_COHER_SIZE_BASE_IDX', 'regCP_ME_COHER_SIZE_HI', + 'regCP_ME_COHER_SIZE_HI_BASE_IDX', 'regCP_ME_COHER_STATUS', + 'regCP_ME_COHER_STATUS_BASE_IDX', 'regCP_ME_F32_INTERRUPT', + 'regCP_ME_F32_INTERRUPT_BASE_IDX', + 'regCP_ME_GDS_ATOMIC0_PREOP_HI', + 'regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX', + 'regCP_ME_GDS_ATOMIC0_PREOP_LO', + 'regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX', + 'regCP_ME_GDS_ATOMIC1_PREOP_HI', + 'regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX', + 'regCP_ME_GDS_ATOMIC1_PREOP_LO', + 'regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'regCP_ME_HEADER_DUMP', + 'regCP_ME_HEADER_DUMP_BASE_IDX', 'regCP_ME_INSTR_PNTR', + 'regCP_ME_INSTR_PNTR_BASE_IDX', 'regCP_ME_INTR_ROUTINE_START', + 'regCP_ME_INTR_ROUTINE_START_BASE_IDX', 'regCP_ME_MC_RADDR_HI', + 'regCP_ME_MC_RADDR_HI_BASE_IDX', 'regCP_ME_MC_RADDR_LO', + 'regCP_ME_MC_RADDR_LO_BASE_IDX', 'regCP_ME_MC_WADDR_HI', + 'regCP_ME_MC_WADDR_HI_BASE_IDX', 'regCP_ME_MC_WADDR_LO', + 'regCP_ME_MC_WADDR_LO_BASE_IDX', 'regCP_ME_MC_WDATA_HI', + 'regCP_ME_MC_WDATA_HI_BASE_IDX', 'regCP_ME_MC_WDATA_LO', + 'regCP_ME_MC_WDATA_LO_BASE_IDX', 'regCP_ME_PREEMPTION', + 'regCP_ME_PREEMPTION_BASE_IDX', 'regCP_ME_PRGRM_CNTR_START', + 'regCP_ME_PRGRM_CNTR_START_BASE_IDX', 'regCP_ME_RAM_DATA', + 'regCP_ME_RAM_DATA_BASE_IDX', 'regCP_ME_RAM_RADDR', + 'regCP_ME_RAM_RADDR_BASE_IDX', 'regCP_ME_RAM_WADDR', + 'regCP_ME_RAM_WADDR_BASE_IDX', 'regCP_MQD_BASE_ADDR', + 'regCP_MQD_BASE_ADDR_BASE_IDX', 'regCP_MQD_BASE_ADDR_HI', + 'regCP_MQD_BASE_ADDR_HI_BASE_IDX', 'regCP_MQD_CONTROL', + 'regCP_MQD_CONTROL_BASE_IDX', 'regCP_NUM_PRIM_NEEDED_COUNT0_HI', + 'regCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX', + 'regCP_NUM_PRIM_NEEDED_COUNT0_LO', + 'regCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX', + 'regCP_NUM_PRIM_NEEDED_COUNT1_HI', + 'regCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX', + 'regCP_NUM_PRIM_NEEDED_COUNT1_LO', + 'regCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX', + 'regCP_NUM_PRIM_NEEDED_COUNT2_HI', + 'regCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX', + 'regCP_NUM_PRIM_NEEDED_COUNT2_LO', + 'regCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX', + 'regCP_NUM_PRIM_NEEDED_COUNT3_HI', + 'regCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX', + 'regCP_NUM_PRIM_NEEDED_COUNT3_LO', + 'regCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX', + 'regCP_NUM_PRIM_WRITTEN_COUNT0_HI', + 'regCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX', + 'regCP_NUM_PRIM_WRITTEN_COUNT0_LO', + 'regCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX', + 'regCP_NUM_PRIM_WRITTEN_COUNT1_HI', + 'regCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX', + 'regCP_NUM_PRIM_WRITTEN_COUNT1_LO', + 'regCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX', + 'regCP_NUM_PRIM_WRITTEN_COUNT2_HI', + 'regCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX', + 'regCP_NUM_PRIM_WRITTEN_COUNT2_LO', + 'regCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX', + 'regCP_NUM_PRIM_WRITTEN_COUNT3_HI', + 'regCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX', + 'regCP_NUM_PRIM_WRITTEN_COUNT3_LO', + 'regCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX', + 'regCP_PA_CINVOC_COUNT_HI', 'regCP_PA_CINVOC_COUNT_HI_BASE_IDX', + 'regCP_PA_CINVOC_COUNT_LO', 'regCP_PA_CINVOC_COUNT_LO_BASE_IDX', + 'regCP_PA_CPRIM_COUNT_HI', 'regCP_PA_CPRIM_COUNT_HI_BASE_IDX', + 'regCP_PA_CPRIM_COUNT_LO', 'regCP_PA_CPRIM_COUNT_LO_BASE_IDX', + 'regCP_PERFMON_CNTL', 'regCP_PERFMON_CNTL_BASE_IDX', + 'regCP_PERFMON_CNTX_CNTL', 'regCP_PERFMON_CNTX_CNTL_BASE_IDX', + 'regCP_PFP_ATOMIC_PREOP_HI', 'regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX', + 'regCP_PFP_ATOMIC_PREOP_LO', 'regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX', + 'regCP_PFP_COMPLETION_STATUS', + 'regCP_PFP_COMPLETION_STATUS_BASE_IDX', 'regCP_PFP_F32_INTERRUPT', + 'regCP_PFP_F32_INTERRUPT_BASE_IDX', + 'regCP_PFP_GDS_ATOMIC0_PREOP_HI', + 'regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX', + 'regCP_PFP_GDS_ATOMIC0_PREOP_LO', + 'regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX', + 'regCP_PFP_GDS_ATOMIC1_PREOP_HI', + 'regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX', + 'regCP_PFP_GDS_ATOMIC1_PREOP_LO', + 'regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX', + 'regCP_PFP_HEADER_DUMP', 'regCP_PFP_HEADER_DUMP_BASE_IDX', + 'regCP_PFP_IB_CONTROL', 'regCP_PFP_IB_CONTROL_BASE_IDX', + 'regCP_PFP_INSTR_PNTR', 'regCP_PFP_INSTR_PNTR_BASE_IDX', + 'regCP_PFP_INTR_ROUTINE_START', + 'regCP_PFP_INTR_ROUTINE_START_BASE_IDX', 'regCP_PFP_LOAD_CONTROL', + 'regCP_PFP_LOAD_CONTROL_BASE_IDX', 'regCP_PFP_METADATA_BASE_ADDR', + 'regCP_PFP_METADATA_BASE_ADDR_BASE_IDX', + 'regCP_PFP_METADATA_BASE_ADDR_HI', + 'regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX', + 'regCP_PFP_PRGRM_CNTR_START', + 'regCP_PFP_PRGRM_CNTR_START_BASE_IDX', 'regCP_PFP_UCODE_ADDR', + 'regCP_PFP_UCODE_ADDR_BASE_IDX', 'regCP_PFP_UCODE_DATA', + 'regCP_PFP_UCODE_DATA_BASE_IDX', 'regCP_PIPEID', + 'regCP_PIPEID_BASE_IDX', 'regCP_PIPE_STATS_ADDR_HI', + 'regCP_PIPE_STATS_ADDR_HI_BASE_IDX', 'regCP_PIPE_STATS_ADDR_LO', + 'regCP_PIPE_STATS_ADDR_LO_BASE_IDX', 'regCP_PIPE_STATS_CONTROL', + 'regCP_PIPE_STATS_CONTROL_BASE_IDX', 'regCP_PQ_STATUS', + 'regCP_PQ_STATUS_BASE_IDX', 'regCP_PQ_WPTR_POLL_CNTL', + 'regCP_PQ_WPTR_POLL_CNTL1', 'regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX', + 'regCP_PQ_WPTR_POLL_CNTL_BASE_IDX', 'regCP_PRED_NOT_VISIBLE', + 'regCP_PRED_NOT_VISIBLE_BASE_IDX', 'regCP_PRIV_VIOLATION_ADDR', + 'regCP_PRIV_VIOLATION_ADDR_BASE_IDX', 'regCP_PSP_XCP_CTL', + 'regCP_PSP_XCP_CTL_BASE_IDX', 'regCP_PWR_CNTL', + 'regCP_PWR_CNTL_BASE_IDX', 'regCP_QUEUE_THRESHOLDS', + 'regCP_QUEUE_THRESHOLDS_BASE_IDX', 'regCP_RB0_ACTIVE', + 'regCP_RB0_ACTIVE_BASE_IDX', 'regCP_RB0_BASE', + 'regCP_RB0_BASE_BASE_IDX', 'regCP_RB0_BASE_HI', + 'regCP_RB0_BASE_HI_BASE_IDX', 'regCP_RB0_BUFSZ_MASK', + 'regCP_RB0_BUFSZ_MASK_BASE_IDX', 'regCP_RB0_CNTL', + 'regCP_RB0_CNTL_BASE_IDX', 'regCP_RB0_RPTR', + 'regCP_RB0_RPTR_ADDR', 'regCP_RB0_RPTR_ADDR_BASE_IDX', + 'regCP_RB0_RPTR_ADDR_HI', 'regCP_RB0_RPTR_ADDR_HI_BASE_IDX', + 'regCP_RB0_RPTR_BASE_IDX', 'regCP_RB0_WPTR', + 'regCP_RB0_WPTR_BASE_IDX', 'regCP_RB0_WPTR_HI', + 'regCP_RB0_WPTR_HI_BASE_IDX', 'regCP_RB1_BASE', + 'regCP_RB1_BASE_BASE_IDX', 'regCP_RB1_BASE_HI', + 'regCP_RB1_BASE_HI_BASE_IDX', 'regCP_RB1_CNTL', + 'regCP_RB1_CNTL_BASE_IDX', 'regCP_RB1_RPTR', + 'regCP_RB1_RPTR_ADDR', 'regCP_RB1_RPTR_ADDR_BASE_IDX', + 'regCP_RB1_RPTR_ADDR_HI', 'regCP_RB1_RPTR_ADDR_HI_BASE_IDX', + 'regCP_RB1_RPTR_BASE_IDX', 'regCP_RB1_WPTR', + 'regCP_RB1_WPTR_BASE_IDX', 'regCP_RB1_WPTR_HI', + 'regCP_RB1_WPTR_HI_BASE_IDX', 'regCP_RB2_BASE', + 'regCP_RB2_BASE_BASE_IDX', 'regCP_RB2_CNTL', + 'regCP_RB2_CNTL_BASE_IDX', 'regCP_RB2_RPTR', + 'regCP_RB2_RPTR_ADDR', 'regCP_RB2_RPTR_ADDR_BASE_IDX', + 'regCP_RB2_RPTR_ADDR_HI', 'regCP_RB2_RPTR_ADDR_HI_BASE_IDX', + 'regCP_RB2_RPTR_BASE_IDX', 'regCP_RB2_WPTR', + 'regCP_RB2_WPTR_BASE_IDX', 'regCP_RB_ACTIVE', + 'regCP_RB_ACTIVE_BASE_IDX', 'regCP_RB_BASE', + 'regCP_RB_BASE_BASE_IDX', 'regCP_RB_BUFSZ_MASK', + 'regCP_RB_BUFSZ_MASK_BASE_IDX', 'regCP_RB_CNTL', + 'regCP_RB_CNTL_BASE_IDX', 'regCP_RB_DOORBELL_CLEAR', + 'regCP_RB_DOORBELL_CLEAR_BASE_IDX', 'regCP_RB_DOORBELL_CONTROL', + 'regCP_RB_DOORBELL_CONTROL_BASE_IDX', + 'regCP_RB_DOORBELL_CONTROL_SCH_0', + 'regCP_RB_DOORBELL_CONTROL_SCH_0_BASE_IDX', + 'regCP_RB_DOORBELL_CONTROL_SCH_1', + 'regCP_RB_DOORBELL_CONTROL_SCH_1_BASE_IDX', + 'regCP_RB_DOORBELL_CONTROL_SCH_2', + 'regCP_RB_DOORBELL_CONTROL_SCH_2_BASE_IDX', + 'regCP_RB_DOORBELL_CONTROL_SCH_3', + 'regCP_RB_DOORBELL_CONTROL_SCH_3_BASE_IDX', + 'regCP_RB_DOORBELL_CONTROL_SCH_4', + 'regCP_RB_DOORBELL_CONTROL_SCH_4_BASE_IDX', + 'regCP_RB_DOORBELL_CONTROL_SCH_5', + 'regCP_RB_DOORBELL_CONTROL_SCH_5_BASE_IDX', + 'regCP_RB_DOORBELL_CONTROL_SCH_6', + 'regCP_RB_DOORBELL_CONTROL_SCH_6_BASE_IDX', + 'regCP_RB_DOORBELL_CONTROL_SCH_7', + 'regCP_RB_DOORBELL_CONTROL_SCH_7_BASE_IDX', + 'regCP_RB_DOORBELL_RANGE_LOWER', + 'regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX', + 'regCP_RB_DOORBELL_RANGE_UPPER', + 'regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX', 'regCP_RB_OFFSET', + 'regCP_RB_OFFSET_BASE_IDX', 'regCP_RB_RPTR', 'regCP_RB_RPTR_ADDR', + 'regCP_RB_RPTR_ADDR_BASE_IDX', 'regCP_RB_RPTR_ADDR_HI', + 'regCP_RB_RPTR_ADDR_HI_BASE_IDX', 'regCP_RB_RPTR_BASE_IDX', + 'regCP_RB_RPTR_WR', 'regCP_RB_RPTR_WR_BASE_IDX', + 'regCP_RB_STATUS', 'regCP_RB_STATUS_BASE_IDX', 'regCP_RB_VMID', + 'regCP_RB_VMID_BASE_IDX', 'regCP_RB_WPTR', + 'regCP_RB_WPTR_BASE_IDX', 'regCP_RB_WPTR_DELAY', + 'regCP_RB_WPTR_DELAY_BASE_IDX', 'regCP_RB_WPTR_HI', + 'regCP_RB_WPTR_HI_BASE_IDX', 'regCP_RB_WPTR_POLL_ADDR_HI', + 'regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'regCP_RB_WPTR_POLL_ADDR_LO', + 'regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX', 'regCP_RB_WPTR_POLL_CNTL', + 'regCP_RB_WPTR_POLL_CNTL_BASE_IDX', 'regCP_RING0_PRIORITY', + 'regCP_RING0_PRIORITY_BASE_IDX', 'regCP_RING1_PRIORITY', + 'regCP_RING1_PRIORITY_BASE_IDX', 'regCP_RING2_PRIORITY', + 'regCP_RING2_PRIORITY_BASE_IDX', 'regCP_RINGID', + 'regCP_RINGID_BASE_IDX', 'regCP_RING_PRIORITY_CNTS', + 'regCP_RING_PRIORITY_CNTS_BASE_IDX', 'regCP_ROQ1_THRESHOLDS', + 'regCP_ROQ1_THRESHOLDS_BASE_IDX', 'regCP_ROQ2_AVAIL', + 'regCP_ROQ2_AVAIL_BASE_IDX', 'regCP_ROQ2_THRESHOLDS', + 'regCP_ROQ2_THRESHOLDS_BASE_IDX', 'regCP_ROQ_AVAIL', + 'regCP_ROQ_AVAIL_BASE_IDX', 'regCP_ROQ_IB1_STAT', + 'regCP_ROQ_IB1_STAT_BASE_IDX', 'regCP_ROQ_IB2_STAT', + 'regCP_ROQ_IB2_STAT_BASE_IDX', 'regCP_ROQ_RB_STAT', + 'regCP_ROQ_RB_STAT_BASE_IDX', 'regCP_ROQ_THRESHOLDS', + 'regCP_ROQ_THRESHOLDS_BASE_IDX', 'regCP_SAMPLE_STATUS', + 'regCP_SAMPLE_STATUS_BASE_IDX', 'regCP_SCRATCH_DATA', + 'regCP_SCRATCH_DATA_BASE_IDX', 'regCP_SCRATCH_INDEX', + 'regCP_SCRATCH_INDEX_BASE_IDX', 'regCP_SC_PSINVOC_COUNT0_HI', + 'regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX', + 'regCP_SC_PSINVOC_COUNT0_LO', + 'regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX', + 'regCP_SC_PSINVOC_COUNT1_HI', + 'regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX', + 'regCP_SC_PSINVOC_COUNT1_LO', + 'regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX', 'regCP_SD_CNTL', + 'regCP_SD_CNTL_BASE_IDX', 'regCP_SEM_WAIT_TIMER', + 'regCP_SEM_WAIT_TIMER_BASE_IDX', 'regCP_SIG_SEM_ADDR_HI', + 'regCP_SIG_SEM_ADDR_HI_BASE_IDX', 'regCP_SIG_SEM_ADDR_LO', + 'regCP_SIG_SEM_ADDR_LO_BASE_IDX', 'regCP_SOFT_RESET_CNTL', + 'regCP_SOFT_RESET_CNTL_BASE_IDX', 'regCP_STALLED_STAT1', + 'regCP_STALLED_STAT1_BASE_IDX', 'regCP_STALLED_STAT2', + 'regCP_STALLED_STAT2_BASE_IDX', 'regCP_STALLED_STAT3', + 'regCP_STALLED_STAT3_BASE_IDX', 'regCP_STAT', + 'regCP_STAT_BASE_IDX', 'regCP_STQ_AVAIL', + 'regCP_STQ_AVAIL_BASE_IDX', 'regCP_STQ_STAT', + 'regCP_STQ_STAT_BASE_IDX', 'regCP_STQ_THRESHOLDS', + 'regCP_STQ_THRESHOLDS_BASE_IDX', 'regCP_STQ_WR_STAT', + 'regCP_STQ_WR_STAT_BASE_IDX', 'regCP_STREAM_OUT_ADDR_HI', + 'regCP_STREAM_OUT_ADDR_HI_BASE_IDX', 'regCP_STREAM_OUT_ADDR_LO', + 'regCP_STREAM_OUT_ADDR_LO_BASE_IDX', 'regCP_STREAM_OUT_CONTROL', + 'regCP_STREAM_OUT_CONTROL_BASE_IDX', 'regCP_STRMOUT_CNTL', + 'regCP_STRMOUT_CNTL_BASE_IDX', 'regCP_ST_BASE_HI', + 'regCP_ST_BASE_HI_BASE_IDX', 'regCP_ST_BASE_LO', + 'regCP_ST_BASE_LO_BASE_IDX', 'regCP_ST_BUFSZ', + 'regCP_ST_BUFSZ_BASE_IDX', 'regCP_ST_CMD_BUFSZ', + 'regCP_ST_CMD_BUFSZ_BASE_IDX', 'regCP_VGT_CSINVOC_COUNT_HI', + 'regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX', + 'regCP_VGT_CSINVOC_COUNT_LO', + 'regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX', + 'regCP_VGT_DSINVOC_COUNT_HI', + 'regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX', + 'regCP_VGT_DSINVOC_COUNT_LO', + 'regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX', + 'regCP_VGT_GSINVOC_COUNT_HI', + 'regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX', + 'regCP_VGT_GSINVOC_COUNT_LO', + 'regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX', + 'regCP_VGT_GSPRIM_COUNT_HI', 'regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX', + 'regCP_VGT_GSPRIM_COUNT_LO', 'regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX', + 'regCP_VGT_HSINVOC_COUNT_HI', + 'regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX', + 'regCP_VGT_HSINVOC_COUNT_LO', + 'regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX', + 'regCP_VGT_IAPRIM_COUNT_HI', 'regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX', + 'regCP_VGT_IAPRIM_COUNT_LO', 'regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX', + 'regCP_VGT_IAVERT_COUNT_HI', 'regCP_VGT_IAVERT_COUNT_HI_BASE_IDX', + 'regCP_VGT_IAVERT_COUNT_LO', 'regCP_VGT_IAVERT_COUNT_LO_BASE_IDX', + 'regCP_VGT_VSINVOC_COUNT_HI', + 'regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX', + 'regCP_VGT_VSINVOC_COUNT_LO', + 'regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX', 'regCP_VIRT_STATUS', + 'regCP_VIRT_STATUS_BASE_IDX', 'regCP_VMID', 'regCP_VMID_BASE_IDX', + 'regCP_VMID_PREEMPT', 'regCP_VMID_PREEMPT_BASE_IDX', + 'regCP_VMID_RESET', 'regCP_VMID_RESET_BASE_IDX', + 'regCP_VMID_STATUS', 'regCP_VMID_STATUS_BASE_IDX', + 'regCP_WAIT_REG_MEM_TIMEOUT', + 'regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX', 'regCP_WAIT_SEM_ADDR_HI', + 'regCP_WAIT_SEM_ADDR_HI_BASE_IDX', 'regCP_WAIT_SEM_ADDR_LO', + 'regCP_WAIT_SEM_ADDR_LO_BASE_IDX', 'regCS_COPY_STATE', + 'regCS_COPY_STATE_BASE_IDX', 'regDB_ALPHA_TO_MASK', + 'regDB_ALPHA_TO_MASK_BASE_IDX', 'regDB_CGTT_CLK_CTRL_0', + 'regDB_CGTT_CLK_CTRL_0_BASE_IDX', 'regDB_COUNT_CONTROL', + 'regDB_COUNT_CONTROL_BASE_IDX', 'regDB_CREDIT_LIMIT', + 'regDB_CREDIT_LIMIT_BASE_IDX', 'regDB_DEBUG', 'regDB_DEBUG2', + 'regDB_DEBUG2_BASE_IDX', 'regDB_DEBUG3', 'regDB_DEBUG3_BASE_IDX', + 'regDB_DEBUG4', 'regDB_DEBUG4_BASE_IDX', 'regDB_DEBUG_BASE_IDX', + 'regDB_DEPTH_BOUNDS_MAX', 'regDB_DEPTH_BOUNDS_MAX_BASE_IDX', + 'regDB_DEPTH_BOUNDS_MIN', 'regDB_DEPTH_BOUNDS_MIN_BASE_IDX', + 'regDB_DEPTH_CLEAR', 'regDB_DEPTH_CLEAR_BASE_IDX', + 'regDB_DEPTH_CONTROL', 'regDB_DEPTH_CONTROL_BASE_IDX', + 'regDB_DEPTH_SIZE', 'regDB_DEPTH_SIZE_BASE_IDX', + 'regDB_DEPTH_VIEW', 'regDB_DEPTH_VIEW_BASE_IDX', + 'regDB_DFSM_CONFIG', 'regDB_DFSM_CONFIG_BASE_IDX', + 'regDB_DFSM_CONTROL', 'regDB_DFSM_CONTROL_BASE_IDX', + 'regDB_DFSM_FLUSH_AUX_EVENT', + 'regDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX', 'regDB_DFSM_FLUSH_ENABLE', + 'regDB_DFSM_FLUSH_ENABLE_BASE_IDX', 'regDB_DFSM_PRIMS_IN_FLIGHT', + 'regDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX', + 'regDB_DFSM_TILES_IN_FLIGHT', + 'regDB_DFSM_TILES_IN_FLIGHT_BASE_IDX', 'regDB_DFSM_WATCHDOG', + 'regDB_DFSM_WATCHDOG_BASE_IDX', 'regDB_DFSM_WATERMARK', + 'regDB_DFSM_WATERMARK_BASE_IDX', 'regDB_EQAA', + 'regDB_EQAA_BASE_IDX', 'regDB_EXCEPTION_CONTROL', + 'regDB_EXCEPTION_CONTROL_BASE_IDX', 'regDB_FIFO_DEPTH1', + 'regDB_FIFO_DEPTH1_BASE_IDX', 'regDB_FIFO_DEPTH2', + 'regDB_FIFO_DEPTH2_BASE_IDX', 'regDB_FREE_CACHELINES', + 'regDB_FREE_CACHELINES_BASE_IDX', 'regDB_HTILE_DATA_BASE', + 'regDB_HTILE_DATA_BASE_BASE_IDX', 'regDB_HTILE_DATA_BASE_HI', + 'regDB_HTILE_DATA_BASE_HI_BASE_IDX', 'regDB_HTILE_SURFACE', + 'regDB_HTILE_SURFACE_BASE_IDX', 'regDB_MEM_ARB_WATERMARKS', + 'regDB_MEM_ARB_WATERMARKS_BASE_IDX', 'regDB_OCCLUSION_COUNT0_HI', + 'regDB_OCCLUSION_COUNT0_HI_BASE_IDX', + 'regDB_OCCLUSION_COUNT0_LOW', + 'regDB_OCCLUSION_COUNT0_LOW_BASE_IDX', + 'regDB_OCCLUSION_COUNT1_HI', 'regDB_OCCLUSION_COUNT1_HI_BASE_IDX', + 'regDB_OCCLUSION_COUNT1_LOW', + 'regDB_OCCLUSION_COUNT1_LOW_BASE_IDX', + 'regDB_OCCLUSION_COUNT2_HI', 'regDB_OCCLUSION_COUNT2_HI_BASE_IDX', + 'regDB_OCCLUSION_COUNT2_LOW', + 'regDB_OCCLUSION_COUNT2_LOW_BASE_IDX', + 'regDB_OCCLUSION_COUNT3_HI', 'regDB_OCCLUSION_COUNT3_HI_BASE_IDX', + 'regDB_OCCLUSION_COUNT3_LOW', + 'regDB_OCCLUSION_COUNT3_LOW_BASE_IDX', 'regDB_PERFCOUNTER0_HI', + 'regDB_PERFCOUNTER0_HI_BASE_IDX', 'regDB_PERFCOUNTER0_LO', + 'regDB_PERFCOUNTER0_LO_BASE_IDX', 'regDB_PERFCOUNTER0_SELECT', + 'regDB_PERFCOUNTER0_SELECT1', + 'regDB_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regDB_PERFCOUNTER0_SELECT_BASE_IDX', 'regDB_PERFCOUNTER1_HI', + 'regDB_PERFCOUNTER1_HI_BASE_IDX', 'regDB_PERFCOUNTER1_LO', + 'regDB_PERFCOUNTER1_LO_BASE_IDX', 'regDB_PERFCOUNTER1_SELECT', + 'regDB_PERFCOUNTER1_SELECT1', + 'regDB_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regDB_PERFCOUNTER1_SELECT_BASE_IDX', 'regDB_PERFCOUNTER2_HI', + 'regDB_PERFCOUNTER2_HI_BASE_IDX', 'regDB_PERFCOUNTER2_LO', + 'regDB_PERFCOUNTER2_LO_BASE_IDX', 'regDB_PERFCOUNTER2_SELECT', + 'regDB_PERFCOUNTER2_SELECT_BASE_IDX', 'regDB_PERFCOUNTER3_HI', + 'regDB_PERFCOUNTER3_HI_BASE_IDX', 'regDB_PERFCOUNTER3_LO', + 'regDB_PERFCOUNTER3_LO_BASE_IDX', 'regDB_PERFCOUNTER3_SELECT', + 'regDB_PERFCOUNTER3_SELECT_BASE_IDX', 'regDB_PRELOAD_CONTROL', + 'regDB_PRELOAD_CONTROL_BASE_IDX', 'regDB_RENDER_CONTROL', + 'regDB_RENDER_CONTROL_BASE_IDX', 'regDB_RENDER_OVERRIDE', + 'regDB_RENDER_OVERRIDE2', 'regDB_RENDER_OVERRIDE2_BASE_IDX', + 'regDB_RENDER_OVERRIDE_BASE_IDX', 'regDB_RING_CONTROL', + 'regDB_RING_CONTROL_BASE_IDX', 'regDB_RMI_CACHE_POLICY', + 'regDB_RMI_CACHE_POLICY_BASE_IDX', 'regDB_SHADER_CONTROL', + 'regDB_SHADER_CONTROL_BASE_IDX', 'regDB_SRESULTS_COMPARE_STATE0', + 'regDB_SRESULTS_COMPARE_STATE0_BASE_IDX', + 'regDB_SRESULTS_COMPARE_STATE1', + 'regDB_SRESULTS_COMPARE_STATE1_BASE_IDX', 'regDB_STENCILREFMASK', + 'regDB_STENCILREFMASK_BASE_IDX', 'regDB_STENCILREFMASK_BF', + 'regDB_STENCILREFMASK_BF_BASE_IDX', 'regDB_STENCIL_CLEAR', + 'regDB_STENCIL_CLEAR_BASE_IDX', 'regDB_STENCIL_CONTROL', + 'regDB_STENCIL_CONTROL_BASE_IDX', 'regDB_STENCIL_INFO', + 'regDB_STENCIL_INFO2', 'regDB_STENCIL_INFO2_BASE_IDX', + 'regDB_STENCIL_INFO_BASE_IDX', 'regDB_STENCIL_READ_BASE', + 'regDB_STENCIL_READ_BASE_BASE_IDX', 'regDB_STENCIL_READ_BASE_HI', + 'regDB_STENCIL_READ_BASE_HI_BASE_IDX', 'regDB_STENCIL_WRITE_BASE', + 'regDB_STENCIL_WRITE_BASE_BASE_IDX', + 'regDB_STENCIL_WRITE_BASE_HI', + 'regDB_STENCIL_WRITE_BASE_HI_BASE_IDX', 'regDB_SUBTILE_CONTROL', + 'regDB_SUBTILE_CONTROL_BASE_IDX', 'regDB_WATERMARKS', + 'regDB_WATERMARKS_BASE_IDX', 'regDB_ZPASS_COUNT_HI', + 'regDB_ZPASS_COUNT_HI_BASE_IDX', 'regDB_ZPASS_COUNT_LOW', + 'regDB_ZPASS_COUNT_LOW_BASE_IDX', 'regDB_Z_INFO', 'regDB_Z_INFO2', + 'regDB_Z_INFO2_BASE_IDX', 'regDB_Z_INFO_BASE_IDX', + 'regDB_Z_READ_BASE', 'regDB_Z_READ_BASE_BASE_IDX', + 'regDB_Z_READ_BASE_HI', 'regDB_Z_READ_BASE_HI_BASE_IDX', + 'regDB_Z_WRITE_BASE', 'regDB_Z_WRITE_BASE_BASE_IDX', + 'regDB_Z_WRITE_BASE_HI', 'regDB_Z_WRITE_BASE_HI_BASE_IDX', + 'regGB_ADDR_CONFIG', 'regGB_ADDR_CONFIG_BASE_IDX', + 'regGB_ADDR_CONFIG_READ', 'regGB_ADDR_CONFIG_READ_BASE_IDX', + 'regGB_BACKEND_MAP', 'regGB_BACKEND_MAP_BASE_IDX', + 'regGB_EDC_MODE', 'regGB_EDC_MODE_BASE_IDX', 'regGB_GPU_ID', + 'regGB_GPU_ID_BASE_IDX', 'regGB_MACROTILE_MODE0', + 'regGB_MACROTILE_MODE0_BASE_IDX', 'regGB_MACROTILE_MODE1', + 'regGB_MACROTILE_MODE10', 'regGB_MACROTILE_MODE10_BASE_IDX', + 'regGB_MACROTILE_MODE11', 'regGB_MACROTILE_MODE11_BASE_IDX', + 'regGB_MACROTILE_MODE12', 'regGB_MACROTILE_MODE12_BASE_IDX', + 'regGB_MACROTILE_MODE13', 'regGB_MACROTILE_MODE13_BASE_IDX', + 'regGB_MACROTILE_MODE14', 'regGB_MACROTILE_MODE14_BASE_IDX', + 'regGB_MACROTILE_MODE15', 'regGB_MACROTILE_MODE15_BASE_IDX', + 'regGB_MACROTILE_MODE1_BASE_IDX', 'regGB_MACROTILE_MODE2', + 'regGB_MACROTILE_MODE2_BASE_IDX', 'regGB_MACROTILE_MODE3', + 'regGB_MACROTILE_MODE3_BASE_IDX', 'regGB_MACROTILE_MODE4', + 'regGB_MACROTILE_MODE4_BASE_IDX', 'regGB_MACROTILE_MODE5', + 'regGB_MACROTILE_MODE5_BASE_IDX', 'regGB_MACROTILE_MODE6', + 'regGB_MACROTILE_MODE6_BASE_IDX', 'regGB_MACROTILE_MODE7', + 'regGB_MACROTILE_MODE7_BASE_IDX', 'regGB_MACROTILE_MODE8', + 'regGB_MACROTILE_MODE8_BASE_IDX', 'regGB_MACROTILE_MODE9', + 'regGB_MACROTILE_MODE9_BASE_IDX', 'regGB_TILE_MODE0', + 'regGB_TILE_MODE0_BASE_IDX', 'regGB_TILE_MODE1', + 'regGB_TILE_MODE10', 'regGB_TILE_MODE10_BASE_IDX', + 'regGB_TILE_MODE11', 'regGB_TILE_MODE11_BASE_IDX', + 'regGB_TILE_MODE12', 'regGB_TILE_MODE12_BASE_IDX', + 'regGB_TILE_MODE13', 'regGB_TILE_MODE13_BASE_IDX', + 'regGB_TILE_MODE14', 'regGB_TILE_MODE14_BASE_IDX', + 'regGB_TILE_MODE15', 'regGB_TILE_MODE15_BASE_IDX', + 'regGB_TILE_MODE16', 'regGB_TILE_MODE16_BASE_IDX', + 'regGB_TILE_MODE17', 'regGB_TILE_MODE17_BASE_IDX', + 'regGB_TILE_MODE18', 'regGB_TILE_MODE18_BASE_IDX', + 'regGB_TILE_MODE19', 'regGB_TILE_MODE19_BASE_IDX', + 'regGB_TILE_MODE1_BASE_IDX', 'regGB_TILE_MODE2', + 'regGB_TILE_MODE20', 'regGB_TILE_MODE20_BASE_IDX', + 'regGB_TILE_MODE21', 'regGB_TILE_MODE21_BASE_IDX', + 'regGB_TILE_MODE22', 'regGB_TILE_MODE22_BASE_IDX', + 'regGB_TILE_MODE23', 'regGB_TILE_MODE23_BASE_IDX', + 'regGB_TILE_MODE24', 'regGB_TILE_MODE24_BASE_IDX', + 'regGB_TILE_MODE25', 'regGB_TILE_MODE25_BASE_IDX', + 'regGB_TILE_MODE26', 'regGB_TILE_MODE26_BASE_IDX', + 'regGB_TILE_MODE27', 'regGB_TILE_MODE27_BASE_IDX', + 'regGB_TILE_MODE28', 'regGB_TILE_MODE28_BASE_IDX', + 'regGB_TILE_MODE29', 'regGB_TILE_MODE29_BASE_IDX', + 'regGB_TILE_MODE2_BASE_IDX', 'regGB_TILE_MODE3', + 'regGB_TILE_MODE30', 'regGB_TILE_MODE30_BASE_IDX', + 'regGB_TILE_MODE31', 'regGB_TILE_MODE31_BASE_IDX', + 'regGB_TILE_MODE3_BASE_IDX', 'regGB_TILE_MODE4', + 'regGB_TILE_MODE4_BASE_IDX', 'regGB_TILE_MODE5', + 'regGB_TILE_MODE5_BASE_IDX', 'regGB_TILE_MODE6', + 'regGB_TILE_MODE6_BASE_IDX', 'regGB_TILE_MODE7', + 'regGB_TILE_MODE7_BASE_IDX', 'regGB_TILE_MODE8', + 'regGB_TILE_MODE8_BASE_IDX', 'regGB_TILE_MODE9', + 'regGB_TILE_MODE9_BASE_IDX', 'regGCEA_CE_ERR_STATUS_HI', + 'regGCEA_CE_ERR_STATUS_HI_BASE_IDX', 'regGCEA_CE_ERR_STATUS_LO', + 'regGCEA_CE_ERR_STATUS_LO_BASE_IDX', 'regGCEA_DRAM_PAGE_BURST', + 'regGCEA_DRAM_PAGE_BURST_BASE_IDX', 'regGCEA_DRAM_RD_CAM_CNTL', + 'regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX', + 'regGCEA_DRAM_RD_CLI2GRP_MAP0', + 'regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX', + 'regGCEA_DRAM_RD_CLI2GRP_MAP1', + 'regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX', + 'regGCEA_DRAM_RD_GRP2VC_MAP', + 'regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX', 'regGCEA_DRAM_RD_LAZY', + 'regGCEA_DRAM_RD_LAZY_BASE_IDX', 'regGCEA_DRAM_RD_PRI_AGE', + 'regGCEA_DRAM_RD_PRI_AGE_BASE_IDX', 'regGCEA_DRAM_RD_PRI_FIXED', + 'regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX', + 'regGCEA_DRAM_RD_PRI_QUANT_PRI1', + 'regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX', + 'regGCEA_DRAM_RD_PRI_QUANT_PRI2', + 'regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX', + 'regGCEA_DRAM_RD_PRI_QUANT_PRI3', + 'regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX', + 'regGCEA_DRAM_RD_PRI_QUEUING', + 'regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX', + 'regGCEA_DRAM_RD_PRI_URGENCY', + 'regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX', + 'regGCEA_DRAM_WR_CAM_CNTL', 'regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX', + 'regGCEA_DRAM_WR_CLI2GRP_MAP0', + 'regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX', + 'regGCEA_DRAM_WR_CLI2GRP_MAP1', + 'regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX', + 'regGCEA_DRAM_WR_GRP2VC_MAP', + 'regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX', 'regGCEA_DRAM_WR_LAZY', + 'regGCEA_DRAM_WR_LAZY_BASE_IDX', 'regGCEA_DRAM_WR_PRI_AGE', + 'regGCEA_DRAM_WR_PRI_AGE_BASE_IDX', 'regGCEA_DRAM_WR_PRI_FIXED', + 'regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX', + 'regGCEA_DRAM_WR_PRI_QUANT_PRI1', + 'regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX', + 'regGCEA_DRAM_WR_PRI_QUANT_PRI2', + 'regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX', + 'regGCEA_DRAM_WR_PRI_QUANT_PRI3', + 'regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX', + 'regGCEA_DRAM_WR_PRI_QUEUING', + 'regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX', + 'regGCEA_DRAM_WR_PRI_URGENCY', + 'regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX', 'regGCEA_DSM_CNTL', + 'regGCEA_DSM_CNTL2', 'regGCEA_DSM_CNTL2A', + 'regGCEA_DSM_CNTL2A_BASE_IDX', 'regGCEA_DSM_CNTL2B', + 'regGCEA_DSM_CNTL2B_BASE_IDX', 'regGCEA_DSM_CNTL2_BASE_IDX', + 'regGCEA_DSM_CNTLA', 'regGCEA_DSM_CNTLA_BASE_IDX', + 'regGCEA_DSM_CNTLB', 'regGCEA_DSM_CNTLB_BASE_IDX', + 'regGCEA_DSM_CNTL_BASE_IDX', 'regGCEA_ERR_STATUS', + 'regGCEA_ERR_STATUS_BASE_IDX', 'regGCEA_ICG_CTRL', + 'regGCEA_ICG_CTRL_BASE_IDX', 'regGCEA_IO_GROUP_BURST', + 'regGCEA_IO_GROUP_BURST_BASE_IDX', 'regGCEA_IO_RD_CLI2GRP_MAP0', + 'regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX', + 'regGCEA_IO_RD_CLI2GRP_MAP1', + 'regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX', + 'regGCEA_IO_RD_COMBINE_FLUSH', + 'regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX', 'regGCEA_IO_RD_PRI_AGE', + 'regGCEA_IO_RD_PRI_AGE_BASE_IDX', 'regGCEA_IO_RD_PRI_FIXED', + 'regGCEA_IO_RD_PRI_FIXED_BASE_IDX', + 'regGCEA_IO_RD_PRI_QUANT_PRI1', + 'regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX', + 'regGCEA_IO_RD_PRI_QUANT_PRI2', + 'regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX', + 'regGCEA_IO_RD_PRI_QUANT_PRI3', + 'regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX', + 'regGCEA_IO_RD_PRI_QUEUING', 'regGCEA_IO_RD_PRI_QUEUING_BASE_IDX', + 'regGCEA_IO_RD_PRI_URGENCY', 'regGCEA_IO_RD_PRI_URGENCY_BASE_IDX', + 'regGCEA_IO_RD_PRI_URGENCY_MASKING', + 'regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX', + 'regGCEA_IO_WR_CLI2GRP_MAP0', + 'regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX', + 'regGCEA_IO_WR_CLI2GRP_MAP1', + 'regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX', + 'regGCEA_IO_WR_COMBINE_FLUSH', + 'regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX', 'regGCEA_IO_WR_PRI_AGE', + 'regGCEA_IO_WR_PRI_AGE_BASE_IDX', 'regGCEA_IO_WR_PRI_FIXED', + 'regGCEA_IO_WR_PRI_FIXED_BASE_IDX', + 'regGCEA_IO_WR_PRI_QUANT_PRI1', + 'regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX', + 'regGCEA_IO_WR_PRI_QUANT_PRI2', + 'regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX', + 'regGCEA_IO_WR_PRI_QUANT_PRI3', + 'regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX', + 'regGCEA_IO_WR_PRI_QUEUING', 'regGCEA_IO_WR_PRI_QUEUING_BASE_IDX', + 'regGCEA_IO_WR_PRI_URGENCY', 'regGCEA_IO_WR_PRI_URGENCY_BASE_IDX', + 'regGCEA_IO_WR_PRI_URGENCY_MASKING', + 'regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX', + 'regGCEA_LATENCY_SAMPLING', 'regGCEA_LATENCY_SAMPLING_BASE_IDX', + 'regGCEA_MAM_CTRL', 'regGCEA_MAM_CTRL2', + 'regGCEA_MAM_CTRL2_BASE_IDX', 'regGCEA_MAM_CTRL_BASE_IDX', + 'regGCEA_MISC', 'regGCEA_MISC2', 'regGCEA_MISC2_BASE_IDX', + 'regGCEA_MISC_BASE_IDX', 'regGCEA_PERFCOUNTER0_CFG', + 'regGCEA_PERFCOUNTER0_CFG_BASE_IDX', 'regGCEA_PERFCOUNTER1_CFG', + 'regGCEA_PERFCOUNTER1_CFG_BASE_IDX', 'regGCEA_PERFCOUNTER_HI', + 'regGCEA_PERFCOUNTER_HI_BASE_IDX', 'regGCEA_PERFCOUNTER_LO', + 'regGCEA_PERFCOUNTER_LO_BASE_IDX', + 'regGCEA_PERFCOUNTER_RSLT_CNTL', + 'regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'regGCEA_PROBE_CNTL', + 'regGCEA_PROBE_CNTL_BASE_IDX', 'regGCEA_PROBE_MAP', + 'regGCEA_PROBE_MAP_BASE_IDX', 'regGCEA_SDP_ARB_DRAM', + 'regGCEA_SDP_ARB_DRAM_BASE_IDX', 'regGCEA_SDP_ARB_FINAL', + 'regGCEA_SDP_ARB_FINAL_BASE_IDX', + 'regGCEA_SDP_BACKDOOR_CMDCREDITS0', + 'regGCEA_SDP_BACKDOOR_CMDCREDITS0_BASE_IDX', + 'regGCEA_SDP_BACKDOOR_CMDCREDITS1', + 'regGCEA_SDP_BACKDOOR_CMDCREDITS1_BASE_IDX', + 'regGCEA_SDP_BACKDOOR_DATACREDITS0', + 'regGCEA_SDP_BACKDOOR_DATACREDITS0_BASE_IDX', + 'regGCEA_SDP_BACKDOOR_DATACREDITS1', + 'regGCEA_SDP_BACKDOOR_DATACREDITS1_BASE_IDX', + 'regGCEA_SDP_BACKDOOR_MISCCREDITS', + 'regGCEA_SDP_BACKDOOR_MISCCREDITS_BASE_IDX', + 'regGCEA_SDP_CREDITS', 'regGCEA_SDP_CREDITS_BASE_IDX', + 'regGCEA_SDP_DRAM_PRIORITY', 'regGCEA_SDP_DRAM_PRIORITY_BASE_IDX', + 'regGCEA_SDP_ENABLE', 'regGCEA_SDP_ENABLE_BASE_IDX', + 'regGCEA_SDP_IO_PRIORITY', 'regGCEA_SDP_IO_PRIORITY_BASE_IDX', + 'regGCEA_SDP_REQ_CNTL', 'regGCEA_SDP_REQ_CNTL_BASE_IDX', + 'regGCEA_SDP_TAG_RESERVE0', 'regGCEA_SDP_TAG_RESERVE0_BASE_IDX', + 'regGCEA_SDP_TAG_RESERVE1', 'regGCEA_SDP_TAG_RESERVE1_BASE_IDX', + 'regGCEA_SDP_VCC_RESERVE0', 'regGCEA_SDP_VCC_RESERVE0_BASE_IDX', + 'regGCEA_SDP_VCC_RESERVE1', 'regGCEA_SDP_VCC_RESERVE1_BASE_IDX', + 'regGCEA_SDP_VCD_RESERVE0', 'regGCEA_SDP_VCD_RESERVE0_BASE_IDX', + 'regGCEA_SDP_VCD_RESERVE1', 'regGCEA_SDP_VCD_RESERVE1_BASE_IDX', + 'regGCEA_TCC_XBR_CREDITS', 'regGCEA_TCC_XBR_CREDITS_BASE_IDX', + 'regGCEA_TCC_XBR_MAXBURST', 'regGCEA_TCC_XBR_MAXBURST_BASE_IDX', + 'regGCEA_UE_ERR_STATUS_HI', 'regGCEA_UE_ERR_STATUS_HI_BASE_IDX', + 'regGCEA_UE_ERR_STATUS_LO', 'regGCEA_UE_ERR_STATUS_LO_BASE_IDX', + 'regGC_CANE_CE_ERR_STATUS_HI', + 'regGC_CANE_CE_ERR_STATUS_HI_BASE_IDX', + 'regGC_CANE_CE_ERR_STATUS_LO', + 'regGC_CANE_CE_ERR_STATUS_LO_BASE_IDX', 'regGC_CANE_ERR_STATUS', + 'regGC_CANE_ERR_STATUS_BASE_IDX', 'regGC_CANE_UE_ERR_STATUS_HI', + 'regGC_CANE_UE_ERR_STATUS_HI_BASE_IDX', + 'regGC_CANE_UE_ERR_STATUS_LO', + 'regGC_CANE_UE_ERR_STATUS_LO_BASE_IDX', 'regGC_PRIV_MODE', + 'regGC_PRIV_MODE_BASE_IDX', 'regGC_USER_PRIM_CONFIG', + 'regGC_USER_PRIM_CONFIG_BASE_IDX', + 'regGC_USER_RB_BACKEND_DISABLE', + 'regGC_USER_RB_BACKEND_DISABLE_BASE_IDX', + 'regGC_USER_RB_REDUNDANCY', 'regGC_USER_RB_REDUNDANCY_BASE_IDX', + 'regGC_USER_SHADER_ARRAY_CONFIG', + 'regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX', + 'regGC_USER_SHADER_RATE_CONFIG', + 'regGC_USER_SHADER_RATE_CONFIG_BASE_IDX', + 'regGDFLL_EDC_HYSTERESIS_CNTL', + 'regGDFLL_EDC_HYSTERESIS_CNTL_BASE_IDX', + 'regGDFLL_EDC_HYSTERESIS_STAT', + 'regGDFLL_EDC_HYSTERESIS_STAT_BASE_IDX', 'regGDS_ATOM_BASE', + 'regGDS_ATOM_BASE_BASE_IDX', 'regGDS_ATOM_CNTL', + 'regGDS_ATOM_CNTL_BASE_IDX', 'regGDS_ATOM_COMPLETE', + 'regGDS_ATOM_COMPLETE_BASE_IDX', 'regGDS_ATOM_DST', + 'regGDS_ATOM_DST_BASE_IDX', 'regGDS_ATOM_OFFSET0', + 'regGDS_ATOM_OFFSET0_BASE_IDX', 'regGDS_ATOM_OFFSET1', + 'regGDS_ATOM_OFFSET1_BASE_IDX', 'regGDS_ATOM_OP', + 'regGDS_ATOM_OP_BASE_IDX', 'regGDS_ATOM_READ0', + 'regGDS_ATOM_READ0_BASE_IDX', 'regGDS_ATOM_READ0_U', + 'regGDS_ATOM_READ0_U_BASE_IDX', 'regGDS_ATOM_READ1', + 'regGDS_ATOM_READ1_BASE_IDX', 'regGDS_ATOM_READ1_U', + 'regGDS_ATOM_READ1_U_BASE_IDX', 'regGDS_ATOM_SIZE', + 'regGDS_ATOM_SIZE_BASE_IDX', 'regGDS_ATOM_SRC0', + 'regGDS_ATOM_SRC0_BASE_IDX', 'regGDS_ATOM_SRC0_U', + 'regGDS_ATOM_SRC0_U_BASE_IDX', 'regGDS_ATOM_SRC1', + 'regGDS_ATOM_SRC1_BASE_IDX', 'regGDS_ATOM_SRC1_U', + 'regGDS_ATOM_SRC1_U_BASE_IDX', 'regGDS_CE_ERR_STATUS_HI', + 'regGDS_CE_ERR_STATUS_HI_BASE_IDX', 'regGDS_CE_ERR_STATUS_LO', + 'regGDS_CE_ERR_STATUS_LO_BASE_IDX', 'regGDS_CNTL_STATUS', + 'regGDS_CNTL_STATUS_BASE_IDX', 'regGDS_COMPUTE_MAX_WAVE_ID', + 'regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX', 'regGDS_CONFIG', + 'regGDS_CONFIG_BASE_IDX', 'regGDS_CS_CTXSW_CNT0', + 'regGDS_CS_CTXSW_CNT0_BASE_IDX', 'regGDS_CS_CTXSW_CNT1', + 'regGDS_CS_CTXSW_CNT1_BASE_IDX', 'regGDS_CS_CTXSW_CNT2', + 'regGDS_CS_CTXSW_CNT2_BASE_IDX', 'regGDS_CS_CTXSW_CNT3', + 'regGDS_CS_CTXSW_CNT3_BASE_IDX', 'regGDS_CS_CTXSW_STATUS', + 'regGDS_CS_CTXSW_STATUS_BASE_IDX', 'regGDS_DSM_CNTL', + 'regGDS_DSM_CNTL2', 'regGDS_DSM_CNTL2_BASE_IDX', + 'regGDS_DSM_CNTL_BASE_IDX', 'regGDS_EDC_CNT', + 'regGDS_EDC_CNT_BASE_IDX', 'regGDS_EDC_GRBM_CNT', + 'regGDS_EDC_GRBM_CNT_BASE_IDX', 'regGDS_EDC_OA_DED', + 'regGDS_EDC_OA_DED_BASE_IDX', 'regGDS_EDC_OA_PHY_CNT', + 'regGDS_EDC_OA_PHY_CNT_BASE_IDX', 'regGDS_EDC_OA_PIPE_CNT', + 'regGDS_EDC_OA_PIPE_CNT_BASE_IDX', 'regGDS_ENHANCE', + 'regGDS_ENHANCE2', 'regGDS_ENHANCE2_BASE_IDX', + 'regGDS_ENHANCE_BASE_IDX', 'regGDS_GFX_CTXSW_STATUS', + 'regGDS_GFX_CTXSW_STATUS_BASE_IDX', 'regGDS_GS_CTXSW_CNT0', + 'regGDS_GS_CTXSW_CNT0_BASE_IDX', 'regGDS_GS_CTXSW_CNT1', + 'regGDS_GS_CTXSW_CNT1_BASE_IDX', 'regGDS_GS_CTXSW_CNT2', + 'regGDS_GS_CTXSW_CNT2_BASE_IDX', 'regGDS_GS_CTXSW_CNT3', + 'regGDS_GS_CTXSW_CNT3_BASE_IDX', 'regGDS_GWS_RESET0', + 'regGDS_GWS_RESET0_BASE_IDX', 'regGDS_GWS_RESET1', + 'regGDS_GWS_RESET1_BASE_IDX', 'regGDS_GWS_RESOURCE', + 'regGDS_GWS_RESOURCE_BASE_IDX', 'regGDS_GWS_RESOURCE_CNT', + 'regGDS_GWS_RESOURCE_CNTL', 'regGDS_GWS_RESOURCE_CNTL_BASE_IDX', + 'regGDS_GWS_RESOURCE_CNT_BASE_IDX', 'regGDS_GWS_RESOURCE_RESET', + 'regGDS_GWS_RESOURCE_RESET_BASE_IDX', 'regGDS_GWS_VMID0', + 'regGDS_GWS_VMID0_BASE_IDX', 'regGDS_GWS_VMID1', + 'regGDS_GWS_VMID10', 'regGDS_GWS_VMID10_BASE_IDX', + 'regGDS_GWS_VMID11', 'regGDS_GWS_VMID11_BASE_IDX', + 'regGDS_GWS_VMID12', 'regGDS_GWS_VMID12_BASE_IDX', + 'regGDS_GWS_VMID13', 'regGDS_GWS_VMID13_BASE_IDX', + 'regGDS_GWS_VMID14', 'regGDS_GWS_VMID14_BASE_IDX', + 'regGDS_GWS_VMID15', 'regGDS_GWS_VMID15_BASE_IDX', + 'regGDS_GWS_VMID1_BASE_IDX', 'regGDS_GWS_VMID2', + 'regGDS_GWS_VMID2_BASE_IDX', 'regGDS_GWS_VMID3', + 'regGDS_GWS_VMID3_BASE_IDX', 'regGDS_GWS_VMID4', + 'regGDS_GWS_VMID4_BASE_IDX', 'regGDS_GWS_VMID5', + 'regGDS_GWS_VMID5_BASE_IDX', 'regGDS_GWS_VMID6', + 'regGDS_GWS_VMID6_BASE_IDX', 'regGDS_GWS_VMID7', + 'regGDS_GWS_VMID7_BASE_IDX', 'regGDS_GWS_VMID8', + 'regGDS_GWS_VMID8_BASE_IDX', 'regGDS_GWS_VMID9', + 'regGDS_GWS_VMID9_BASE_IDX', 'regGDS_OA_ADDRESS', + 'regGDS_OA_ADDRESS_BASE_IDX', 'regGDS_OA_CGPG_RESTORE', + 'regGDS_OA_CGPG_RESTORE_BASE_IDX', 'regGDS_OA_CNTL', + 'regGDS_OA_CNTL_BASE_IDX', 'regGDS_OA_COUNTER', + 'regGDS_OA_COUNTER_BASE_IDX', 'regGDS_OA_INCDEC', + 'regGDS_OA_INCDEC_BASE_IDX', 'regGDS_OA_RESET', + 'regGDS_OA_RESET_BASE_IDX', 'regGDS_OA_RESET_MASK', + 'regGDS_OA_RESET_MASK_BASE_IDX', 'regGDS_OA_RING_SIZE', + 'regGDS_OA_RING_SIZE_BASE_IDX', 'regGDS_OA_VMID0', + 'regGDS_OA_VMID0_BASE_IDX', 'regGDS_OA_VMID1', 'regGDS_OA_VMID10', + 'regGDS_OA_VMID10_BASE_IDX', 'regGDS_OA_VMID11', + 'regGDS_OA_VMID11_BASE_IDX', 'regGDS_OA_VMID12', + 'regGDS_OA_VMID12_BASE_IDX', 'regGDS_OA_VMID13', + 'regGDS_OA_VMID13_BASE_IDX', 'regGDS_OA_VMID14', + 'regGDS_OA_VMID14_BASE_IDX', 'regGDS_OA_VMID15', + 'regGDS_OA_VMID15_BASE_IDX', 'regGDS_OA_VMID1_BASE_IDX', + 'regGDS_OA_VMID2', 'regGDS_OA_VMID2_BASE_IDX', 'regGDS_OA_VMID3', + 'regGDS_OA_VMID3_BASE_IDX', 'regGDS_OA_VMID4', + 'regGDS_OA_VMID4_BASE_IDX', 'regGDS_OA_VMID5', + 'regGDS_OA_VMID5_BASE_IDX', 'regGDS_OA_VMID6', + 'regGDS_OA_VMID6_BASE_IDX', 'regGDS_OA_VMID7', + 'regGDS_OA_VMID7_BASE_IDX', 'regGDS_OA_VMID8', + 'regGDS_OA_VMID8_BASE_IDX', 'regGDS_OA_VMID9', + 'regGDS_OA_VMID9_BASE_IDX', 'regGDS_PERFCOUNTER0_HI', + 'regGDS_PERFCOUNTER0_HI_BASE_IDX', 'regGDS_PERFCOUNTER0_LO', + 'regGDS_PERFCOUNTER0_LO_BASE_IDX', 'regGDS_PERFCOUNTER0_SELECT', + 'regGDS_PERFCOUNTER0_SELECT1', + 'regGDS_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regGDS_PERFCOUNTER0_SELECT_BASE_IDX', 'regGDS_PERFCOUNTER1_HI', + 'regGDS_PERFCOUNTER1_HI_BASE_IDX', 'regGDS_PERFCOUNTER1_LO', + 'regGDS_PERFCOUNTER1_LO_BASE_IDX', 'regGDS_PERFCOUNTER1_SELECT', + 'regGDS_PERFCOUNTER1_SELECT_BASE_IDX', 'regGDS_PERFCOUNTER2_HI', + 'regGDS_PERFCOUNTER2_HI_BASE_IDX', 'regGDS_PERFCOUNTER2_LO', + 'regGDS_PERFCOUNTER2_LO_BASE_IDX', 'regGDS_PERFCOUNTER2_SELECT', + 'regGDS_PERFCOUNTER2_SELECT_BASE_IDX', 'regGDS_PERFCOUNTER3_HI', + 'regGDS_PERFCOUNTER3_HI_BASE_IDX', 'regGDS_PERFCOUNTER3_LO', + 'regGDS_PERFCOUNTER3_LO_BASE_IDX', 'regGDS_PERFCOUNTER3_SELECT', + 'regGDS_PERFCOUNTER3_SELECT_BASE_IDX', 'regGDS_PROTECTION_FAULT', + 'regGDS_PROTECTION_FAULT_BASE_IDX', 'regGDS_PS0_CTXSW_CNT0', + 'regGDS_PS0_CTXSW_CNT0_BASE_IDX', 'regGDS_PS0_CTXSW_CNT1', + 'regGDS_PS0_CTXSW_CNT1_BASE_IDX', 'regGDS_PS0_CTXSW_CNT2', + 'regGDS_PS0_CTXSW_CNT2_BASE_IDX', 'regGDS_PS0_CTXSW_CNT3', + 'regGDS_PS0_CTXSW_CNT3_BASE_IDX', 'regGDS_PS1_CTXSW_CNT0', + 'regGDS_PS1_CTXSW_CNT0_BASE_IDX', 'regGDS_PS1_CTXSW_CNT1', + 'regGDS_PS1_CTXSW_CNT1_BASE_IDX', 'regGDS_PS1_CTXSW_CNT2', + 'regGDS_PS1_CTXSW_CNT2_BASE_IDX', 'regGDS_PS1_CTXSW_CNT3', + 'regGDS_PS1_CTXSW_CNT3_BASE_IDX', 'regGDS_PS2_CTXSW_CNT0', + 'regGDS_PS2_CTXSW_CNT0_BASE_IDX', 'regGDS_PS2_CTXSW_CNT1', + 'regGDS_PS2_CTXSW_CNT1_BASE_IDX', 'regGDS_PS2_CTXSW_CNT2', + 'regGDS_PS2_CTXSW_CNT2_BASE_IDX', 'regGDS_PS2_CTXSW_CNT3', + 'regGDS_PS2_CTXSW_CNT3_BASE_IDX', 'regGDS_PS3_CTXSW_CNT0', + 'regGDS_PS3_CTXSW_CNT0_BASE_IDX', 'regGDS_PS3_CTXSW_CNT1', + 'regGDS_PS3_CTXSW_CNT1_BASE_IDX', 'regGDS_PS3_CTXSW_CNT2', + 'regGDS_PS3_CTXSW_CNT2_BASE_IDX', 'regGDS_PS3_CTXSW_CNT3', + 'regGDS_PS3_CTXSW_CNT3_BASE_IDX', 'regGDS_PS4_CTXSW_CNT0', + 'regGDS_PS4_CTXSW_CNT0_BASE_IDX', 'regGDS_PS4_CTXSW_CNT1', + 'regGDS_PS4_CTXSW_CNT1_BASE_IDX', 'regGDS_PS4_CTXSW_CNT2', + 'regGDS_PS4_CTXSW_CNT2_BASE_IDX', 'regGDS_PS4_CTXSW_CNT3', + 'regGDS_PS4_CTXSW_CNT3_BASE_IDX', 'regGDS_PS5_CTXSW_CNT0', + 'regGDS_PS5_CTXSW_CNT0_BASE_IDX', 'regGDS_PS5_CTXSW_CNT1', + 'regGDS_PS5_CTXSW_CNT1_BASE_IDX', 'regGDS_PS5_CTXSW_CNT2', + 'regGDS_PS5_CTXSW_CNT2_BASE_IDX', 'regGDS_PS5_CTXSW_CNT3', + 'regGDS_PS5_CTXSW_CNT3_BASE_IDX', 'regGDS_PS6_CTXSW_CNT0', + 'regGDS_PS6_CTXSW_CNT0_BASE_IDX', 'regGDS_PS6_CTXSW_CNT1', + 'regGDS_PS6_CTXSW_CNT1_BASE_IDX', 'regGDS_PS6_CTXSW_CNT2', + 'regGDS_PS6_CTXSW_CNT2_BASE_IDX', 'regGDS_PS6_CTXSW_CNT3', + 'regGDS_PS6_CTXSW_CNT3_BASE_IDX', 'regGDS_PS7_CTXSW_CNT0', + 'regGDS_PS7_CTXSW_CNT0_BASE_IDX', 'regGDS_PS7_CTXSW_CNT1', + 'regGDS_PS7_CTXSW_CNT1_BASE_IDX', 'regGDS_PS7_CTXSW_CNT2', + 'regGDS_PS7_CTXSW_CNT2_BASE_IDX', 'regGDS_PS7_CTXSW_CNT3', + 'regGDS_PS7_CTXSW_CNT3_BASE_IDX', 'regGDS_RD_ADDR', + 'regGDS_RD_ADDR_BASE_IDX', 'regGDS_RD_BURST_ADDR', + 'regGDS_RD_BURST_ADDR_BASE_IDX', 'regGDS_RD_BURST_COUNT', + 'regGDS_RD_BURST_COUNT_BASE_IDX', 'regGDS_RD_BURST_DATA', + 'regGDS_RD_BURST_DATA_BASE_IDX', 'regGDS_RD_DATA', + 'regGDS_RD_DATA_BASE_IDX', 'regGDS_UE_ERR_STATUS_HI', + 'regGDS_UE_ERR_STATUS_HI_BASE_IDX', 'regGDS_UE_ERR_STATUS_LO', + 'regGDS_UE_ERR_STATUS_LO_BASE_IDX', 'regGDS_VMID0_BASE', + 'regGDS_VMID0_BASE_BASE_IDX', 'regGDS_VMID0_SIZE', + 'regGDS_VMID0_SIZE_BASE_IDX', 'regGDS_VMID10_BASE', + 'regGDS_VMID10_BASE_BASE_IDX', 'regGDS_VMID10_SIZE', + 'regGDS_VMID10_SIZE_BASE_IDX', 'regGDS_VMID11_BASE', + 'regGDS_VMID11_BASE_BASE_IDX', 'regGDS_VMID11_SIZE', + 'regGDS_VMID11_SIZE_BASE_IDX', 'regGDS_VMID12_BASE', + 'regGDS_VMID12_BASE_BASE_IDX', 'regGDS_VMID12_SIZE', + 'regGDS_VMID12_SIZE_BASE_IDX', 'regGDS_VMID13_BASE', + 'regGDS_VMID13_BASE_BASE_IDX', 'regGDS_VMID13_SIZE', + 'regGDS_VMID13_SIZE_BASE_IDX', 'regGDS_VMID14_BASE', + 'regGDS_VMID14_BASE_BASE_IDX', 'regGDS_VMID14_SIZE', + 'regGDS_VMID14_SIZE_BASE_IDX', 'regGDS_VMID15_BASE', + 'regGDS_VMID15_BASE_BASE_IDX', 'regGDS_VMID15_SIZE', + 'regGDS_VMID15_SIZE_BASE_IDX', 'regGDS_VMID1_BASE', + 'regGDS_VMID1_BASE_BASE_IDX', 'regGDS_VMID1_SIZE', + 'regGDS_VMID1_SIZE_BASE_IDX', 'regGDS_VMID2_BASE', + 'regGDS_VMID2_BASE_BASE_IDX', 'regGDS_VMID2_SIZE', + 'regGDS_VMID2_SIZE_BASE_IDX', 'regGDS_VMID3_BASE', + 'regGDS_VMID3_BASE_BASE_IDX', 'regGDS_VMID3_SIZE', + 'regGDS_VMID3_SIZE_BASE_IDX', 'regGDS_VMID4_BASE', + 'regGDS_VMID4_BASE_BASE_IDX', 'regGDS_VMID4_SIZE', + 'regGDS_VMID4_SIZE_BASE_IDX', 'regGDS_VMID5_BASE', + 'regGDS_VMID5_BASE_BASE_IDX', 'regGDS_VMID5_SIZE', + 'regGDS_VMID5_SIZE_BASE_IDX', 'regGDS_VMID6_BASE', + 'regGDS_VMID6_BASE_BASE_IDX', 'regGDS_VMID6_SIZE', + 'regGDS_VMID6_SIZE_BASE_IDX', 'regGDS_VMID7_BASE', + 'regGDS_VMID7_BASE_BASE_IDX', 'regGDS_VMID7_SIZE', + 'regGDS_VMID7_SIZE_BASE_IDX', 'regGDS_VMID8_BASE', + 'regGDS_VMID8_BASE_BASE_IDX', 'regGDS_VMID8_SIZE', + 'regGDS_VMID8_SIZE_BASE_IDX', 'regGDS_VMID9_BASE', + 'regGDS_VMID9_BASE_BASE_IDX', 'regGDS_VMID9_SIZE', + 'regGDS_VMID9_SIZE_BASE_IDX', 'regGDS_VM_PROTECTION_FAULT', + 'regGDS_VM_PROTECTION_FAULT_BASE_IDX', 'regGDS_VS_CTXSW_CNT0', + 'regGDS_VS_CTXSW_CNT0_BASE_IDX', 'regGDS_VS_CTXSW_CNT1', + 'regGDS_VS_CTXSW_CNT1_BASE_IDX', 'regGDS_VS_CTXSW_CNT2', + 'regGDS_VS_CTXSW_CNT2_BASE_IDX', 'regGDS_VS_CTXSW_CNT3', + 'regGDS_VS_CTXSW_CNT3_BASE_IDX', 'regGDS_WD_GDS_CSB', + 'regGDS_WD_GDS_CSB_BASE_IDX', 'regGDS_WRITE_COMPLETE', + 'regGDS_WRITE_COMPLETE_BASE_IDX', 'regGDS_WR_ADDR', + 'regGDS_WR_ADDR_BASE_IDX', 'regGDS_WR_BURST_ADDR', + 'regGDS_WR_BURST_ADDR_BASE_IDX', 'regGDS_WR_BURST_DATA', + 'regGDS_WR_BURST_DATA_BASE_IDX', 'regGDS_WR_DATA', + 'regGDS_WR_DATA_BASE_IDX', 'regGFX_COPY_STATE', + 'regGFX_COPY_STATE_BASE_IDX', 'regGFX_PIPE_CONTROL', + 'regGFX_PIPE_CONTROL_BASE_IDX', 'regGRBM_CAM_DATA', + 'regGRBM_CAM_DATA_BASE_IDX', 'regGRBM_CAM_INDEX', + 'regGRBM_CAM_INDEX_BASE_IDX', 'regGRBM_CHICKEN_BITS', + 'regGRBM_CHICKEN_BITS_BASE_IDX', 'regGRBM_CHIP_REVISION', + 'regGRBM_CHIP_REVISION_BASE_IDX', 'regGRBM_CNTL', + 'regGRBM_CNTL_BASE_IDX', 'regGRBM_DSM_BYPASS', + 'regGRBM_DSM_BYPASS_BASE_IDX', 'regGRBM_FENCE_RANGE0', + 'regGRBM_FENCE_RANGE0_BASE_IDX', 'regGRBM_FENCE_RANGE1', + 'regGRBM_FENCE_RANGE1_BASE_IDX', 'regGRBM_GFX_CLKEN_CNTL', + 'regGRBM_GFX_CLKEN_CNTL_BASE_IDX', 'regGRBM_GFX_CNTL', + 'regGRBM_GFX_CNTL_BASE_IDX', 'regGRBM_GFX_CNTL_SR_DATA', + 'regGRBM_GFX_CNTL_SR_DATA_BASE_IDX', 'regGRBM_GFX_CNTL_SR_SELECT', + 'regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX', 'regGRBM_GFX_INDEX', + 'regGRBM_GFX_INDEX_BASE_IDX', 'regGRBM_GFX_INDEX_SR_DATA', + 'regGRBM_GFX_INDEX_SR_DATA_BASE_IDX', + 'regGRBM_GFX_INDEX_SR_SELECT', + 'regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX', 'regGRBM_HYP_CAM_DATA', + 'regGRBM_HYP_CAM_DATA_BASE_IDX', 'regGRBM_HYP_CAM_INDEX', + 'regGRBM_HYP_CAM_INDEX_BASE_IDX', 'regGRBM_IH_CREDIT', + 'regGRBM_IH_CREDIT_BASE_IDX', 'regGRBM_INT_CNTL', + 'regGRBM_INT_CNTL_BASE_IDX', 'regGRBM_IOV_ERROR', + 'regGRBM_IOV_ERROR_BASE_IDX', 'regGRBM_IOV_ERROR_FIFO_DATA', + 'regGRBM_IOV_ERROR_FIFO_DATA_BASE_IDX', 'regGRBM_IOV_READ_ERROR', + 'regGRBM_IOV_READ_ERROR_BASE_IDX', 'regGRBM_MCM_ADDR', + 'regGRBM_MCM_ADDR_BASE_IDX', 'regGRBM_NOWHERE', + 'regGRBM_NOWHERE_BASE_IDX', 'regGRBM_PERFCOUNTER0_HI', + 'regGRBM_PERFCOUNTER0_HI_BASE_IDX', 'regGRBM_PERFCOUNTER0_LO', + 'regGRBM_PERFCOUNTER0_LO_BASE_IDX', 'regGRBM_PERFCOUNTER0_SELECT', + 'regGRBM_PERFCOUNTER0_SELECT_BASE_IDX', 'regGRBM_PERFCOUNTER1_HI', + 'regGRBM_PERFCOUNTER1_HI_BASE_IDX', 'regGRBM_PERFCOUNTER1_LO', + 'regGRBM_PERFCOUNTER1_LO_BASE_IDX', 'regGRBM_PERFCOUNTER1_SELECT', + 'regGRBM_PERFCOUNTER1_SELECT_BASE_IDX', 'regGRBM_PWR_CNTL', + 'regGRBM_PWR_CNTL2', 'regGRBM_PWR_CNTL2_BASE_IDX', + 'regGRBM_PWR_CNTL_BASE_IDX', 'regGRBM_READ_ERROR', + 'regGRBM_READ_ERROR2', 'regGRBM_READ_ERROR2_BASE_IDX', + 'regGRBM_READ_ERROR_BASE_IDX', 'regGRBM_RSMU_CFG', + 'regGRBM_RSMU_CFG_BASE_IDX', 'regGRBM_RSMU_READ_ERROR', + 'regGRBM_RSMU_READ_ERROR_BASE_IDX', 'regGRBM_SCRATCH_REG0', + 'regGRBM_SCRATCH_REG0_BASE_IDX', 'regGRBM_SCRATCH_REG1', + 'regGRBM_SCRATCH_REG1_BASE_IDX', 'regGRBM_SCRATCH_REG2', + 'regGRBM_SCRATCH_REG2_BASE_IDX', 'regGRBM_SCRATCH_REG3', + 'regGRBM_SCRATCH_REG3_BASE_IDX', 'regGRBM_SCRATCH_REG4', + 'regGRBM_SCRATCH_REG4_BASE_IDX', 'regGRBM_SCRATCH_REG5', + 'regGRBM_SCRATCH_REG5_BASE_IDX', 'regGRBM_SCRATCH_REG6', + 'regGRBM_SCRATCH_REG6_BASE_IDX', 'regGRBM_SCRATCH_REG7', + 'regGRBM_SCRATCH_REG7_BASE_IDX', 'regGRBM_SE0_PERFCOUNTER_HI', + 'regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX', + 'regGRBM_SE0_PERFCOUNTER_LO', + 'regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX', + 'regGRBM_SE0_PERFCOUNTER_SELECT', + 'regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX', + 'regGRBM_SE1_PERFCOUNTER_HI', + 'regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX', + 'regGRBM_SE1_PERFCOUNTER_LO', + 'regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX', + 'regGRBM_SE1_PERFCOUNTER_SELECT', + 'regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX', + 'regGRBM_SE2_PERFCOUNTER_HI', + 'regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX', + 'regGRBM_SE2_PERFCOUNTER_LO', + 'regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX', + 'regGRBM_SE2_PERFCOUNTER_SELECT', + 'regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX', + 'regGRBM_SE3_PERFCOUNTER_HI', + 'regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX', + 'regGRBM_SE3_PERFCOUNTER_LO', + 'regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX', + 'regGRBM_SE3_PERFCOUNTER_SELECT', + 'regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX', 'regGRBM_SEC_CNTL', + 'regGRBM_SEC_CNTL_BASE_IDX', 'regGRBM_SKEW_CNTL', + 'regGRBM_SKEW_CNTL_BASE_IDX', 'regGRBM_SOFT_RESET', + 'regGRBM_SOFT_RESET_BASE_IDX', 'regGRBM_STATUS', + 'regGRBM_STATUS2', 'regGRBM_STATUS2_BASE_IDX', + 'regGRBM_STATUS_BASE_IDX', 'regGRBM_STATUS_SE0', + 'regGRBM_STATUS_SE0_BASE_IDX', 'regGRBM_STATUS_SE1', + 'regGRBM_STATUS_SE1_BASE_IDX', 'regGRBM_STATUS_SE2', + 'regGRBM_STATUS_SE2_BASE_IDX', 'regGRBM_STATUS_SE3', + 'regGRBM_STATUS_SE3_BASE_IDX', 'regGRBM_TRAP_ADDR', + 'regGRBM_TRAP_ADDR_BASE_IDX', 'regGRBM_TRAP_ADDR_MSK', + 'regGRBM_TRAP_ADDR_MSK_BASE_IDX', 'regGRBM_TRAP_OP', + 'regGRBM_TRAP_OP_BASE_IDX', 'regGRBM_TRAP_WD', + 'regGRBM_TRAP_WD_BASE_IDX', 'regGRBM_TRAP_WD_MSK', + 'regGRBM_TRAP_WD_MSK_BASE_IDX', 'regGRBM_UTCL2_INVAL_RANGE_END', + 'regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX', + 'regGRBM_UTCL2_INVAL_RANGE_START', + 'regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX', + 'regGRBM_WAIT_IDLE_CLOCKS', 'regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX', + 'regGRBM_WRITE_ERROR', 'regGRBM_WRITE_ERROR_BASE_IDX', + 'regIA_CNTL_STATUS', 'regIA_CNTL_STATUS_BASE_IDX', + 'regIA_ENHANCE', 'regIA_ENHANCE_BASE_IDX', + 'regIA_MULTI_VGT_PARAM', 'regIA_MULTI_VGT_PARAM_BASE_IDX', + 'regIA_MULTI_VGT_PARAM_BC', 'regIA_MULTI_VGT_PARAM_BC_BASE_IDX', + 'regIA_PERFCOUNTER0_HI', 'regIA_PERFCOUNTER0_HI_BASE_IDX', + 'regIA_PERFCOUNTER0_LO', 'regIA_PERFCOUNTER0_LO_BASE_IDX', + 'regIA_PERFCOUNTER0_SELECT', 'regIA_PERFCOUNTER0_SELECT1', + 'regIA_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regIA_PERFCOUNTER0_SELECT_BASE_IDX', 'regIA_PERFCOUNTER1_HI', + 'regIA_PERFCOUNTER1_HI_BASE_IDX', 'regIA_PERFCOUNTER1_LO', + 'regIA_PERFCOUNTER1_LO_BASE_IDX', 'regIA_PERFCOUNTER1_SELECT', + 'regIA_PERFCOUNTER1_SELECT_BASE_IDX', 'regIA_PERFCOUNTER2_HI', + 'regIA_PERFCOUNTER2_HI_BASE_IDX', 'regIA_PERFCOUNTER2_LO', + 'regIA_PERFCOUNTER2_LO_BASE_IDX', 'regIA_PERFCOUNTER2_SELECT', + 'regIA_PERFCOUNTER2_SELECT_BASE_IDX', 'regIA_PERFCOUNTER3_HI', + 'regIA_PERFCOUNTER3_HI_BASE_IDX', 'regIA_PERFCOUNTER3_LO', + 'regIA_PERFCOUNTER3_LO_BASE_IDX', 'regIA_PERFCOUNTER3_SELECT', + 'regIA_PERFCOUNTER3_SELECT_BASE_IDX', 'regIA_UTCL1_CNTL', + 'regIA_UTCL1_CNTL_BASE_IDX', 'regIA_UTCL1_STATUS', + 'regIA_UTCL1_STATUS_BASE_IDX', 'regL2TLB_PERFCOUNTER0_CFG', + 'regL2TLB_PERFCOUNTER0_CFG_BASE_IDX', 'regL2TLB_PERFCOUNTER1_CFG', + 'regL2TLB_PERFCOUNTER1_CFG_BASE_IDX', 'regL2TLB_PERFCOUNTER2_CFG', + 'regL2TLB_PERFCOUNTER2_CFG_BASE_IDX', 'regL2TLB_PERFCOUNTER3_CFG', + 'regL2TLB_PERFCOUNTER3_CFG_BASE_IDX', 'regL2TLB_PERFCOUNTER_HI', + 'regL2TLB_PERFCOUNTER_HI_BASE_IDX', 'regL2TLB_PERFCOUNTER_LO', + 'regL2TLB_PERFCOUNTER_LO_BASE_IDX', + 'regL2TLB_PERFCOUNTER_RSLT_CNTL', + 'regL2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'regL2TLB_TLB0_STATUS', + 'regL2TLB_TLB0_STATUS_BASE_IDX', 'regLDS_CE_ERR_STATUS_HI', + 'regLDS_CE_ERR_STATUS_HI_BASE_IDX', 'regLDS_CE_ERR_STATUS_LO', + 'regLDS_CE_ERR_STATUS_LO_BASE_IDX', 'regLDS_CONFIG', + 'regLDS_CONFIG_BASE_IDX', 'regLDS_UE_ERR_STATUS_HI', + 'regLDS_UE_ERR_STATUS_HI_BASE_IDX', 'regLDS_UE_ERR_STATUS_LO', + 'regLDS_UE_ERR_STATUS_LO_BASE_IDX', 'regMC_MEM_POWER_LS', + 'regMC_MEM_POWER_LS_BASE_IDX', 'regMC_SHARED_ACTIVE_FCN_ID', + 'regMC_SHARED_ACTIVE_FCN_ID_BASE_IDX', + 'regMC_SHARED_VIRT_RESET_REQ', + 'regMC_SHARED_VIRT_RESET_REQ_BASE_IDX', 'regMC_VM_AGP_BASE', + 'regMC_VM_AGP_BASE_BASE_IDX', 'regMC_VM_AGP_BOT', + 'regMC_VM_AGP_BOT_BASE_IDX', 'regMC_VM_AGP_TOP', + 'regMC_VM_AGP_TOP_BASE_IDX', 'regMC_VM_APT_CNTL', + 'regMC_VM_APT_CNTL_BASE_IDX', + 'regMC_VM_CACHEABLE_DRAM_ADDRESS_END', + 'regMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX', + 'regMC_VM_CACHEABLE_DRAM_ADDRESS_START', + 'regMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX', + 'regMC_VM_CACHEABLE_DRAM_CNTL', + 'regMC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX', + 'regMC_VM_FB_LOCATION_BASE', 'regMC_VM_FB_LOCATION_BASE_BASE_IDX', + 'regMC_VM_FB_LOCATION_TOP', 'regMC_VM_FB_LOCATION_TOP_BASE_IDX', + 'regMC_VM_FB_OFFSET', 'regMC_VM_FB_OFFSET_BASE_IDX', + 'regMC_VM_FB_SIZE_OFFSET_VF0', + 'regMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX', + 'regMC_VM_FB_SIZE_OFFSET_VF1', 'regMC_VM_FB_SIZE_OFFSET_VF10', + 'regMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX', + 'regMC_VM_FB_SIZE_OFFSET_VF11', + 'regMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX', + 'regMC_VM_FB_SIZE_OFFSET_VF12', + 'regMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX', + 'regMC_VM_FB_SIZE_OFFSET_VF13', + 'regMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX', + 'regMC_VM_FB_SIZE_OFFSET_VF14', + 'regMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX', + 'regMC_VM_FB_SIZE_OFFSET_VF15', + 'regMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX', + 'regMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX', + 'regMC_VM_FB_SIZE_OFFSET_VF2', + 'regMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX', + 'regMC_VM_FB_SIZE_OFFSET_VF3', + 'regMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX', + 'regMC_VM_FB_SIZE_OFFSET_VF4', + 'regMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX', + 'regMC_VM_FB_SIZE_OFFSET_VF5', + 'regMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX', + 'regMC_VM_FB_SIZE_OFFSET_VF6', + 'regMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX', + 'regMC_VM_FB_SIZE_OFFSET_VF7', + 'regMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX', + 'regMC_VM_FB_SIZE_OFFSET_VF8', + 'regMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX', + 'regMC_VM_FB_SIZE_OFFSET_VF9', + 'regMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX', 'regMC_VM_HOST_MAPPING', + 'regMC_VM_HOST_MAPPING_BASE_IDX', 'regMC_VM_L2_PERFCOUNTER0_CFG', + 'regMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX', + 'regMC_VM_L2_PERFCOUNTER1_CFG', + 'regMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX', + 'regMC_VM_L2_PERFCOUNTER2_CFG', + 'regMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX', + 'regMC_VM_L2_PERFCOUNTER3_CFG', + 'regMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX', + 'regMC_VM_L2_PERFCOUNTER4_CFG', + 'regMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX', + 'regMC_VM_L2_PERFCOUNTER5_CFG', + 'regMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX', + 'regMC_VM_L2_PERFCOUNTER6_CFG', + 'regMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX', + 'regMC_VM_L2_PERFCOUNTER7_CFG', + 'regMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX', + 'regMC_VM_L2_PERFCOUNTER_HI', + 'regMC_VM_L2_PERFCOUNTER_HI_BASE_IDX', + 'regMC_VM_L2_PERFCOUNTER_LO', + 'regMC_VM_L2_PERFCOUNTER_LO_BASE_IDX', + 'regMC_VM_L2_PERFCOUNTER_RSLT_CNTL', + 'regMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX', + 'regMC_VM_LOCAL_HBM_ADDRESS_END', + 'regMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX', + 'regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL', + 'regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX', + 'regMC_VM_LOCAL_HBM_ADDRESS_START', + 'regMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX', + 'regMC_VM_MARC_BASE_HI_0', 'regMC_VM_MARC_BASE_HI_0_BASE_IDX', + 'regMC_VM_MARC_BASE_HI_1', 'regMC_VM_MARC_BASE_HI_1_BASE_IDX', + 'regMC_VM_MARC_BASE_HI_2', 'regMC_VM_MARC_BASE_HI_2_BASE_IDX', + 'regMC_VM_MARC_BASE_HI_3', 'regMC_VM_MARC_BASE_HI_3_BASE_IDX', + 'regMC_VM_MARC_BASE_LO_0', 'regMC_VM_MARC_BASE_LO_0_BASE_IDX', + 'regMC_VM_MARC_BASE_LO_1', 'regMC_VM_MARC_BASE_LO_1_BASE_IDX', + 'regMC_VM_MARC_BASE_LO_2', 'regMC_VM_MARC_BASE_LO_2_BASE_IDX', + 'regMC_VM_MARC_BASE_LO_3', 'regMC_VM_MARC_BASE_LO_3_BASE_IDX', + 'regMC_VM_MARC_LEN_HI_0', 'regMC_VM_MARC_LEN_HI_0_BASE_IDX', + 'regMC_VM_MARC_LEN_HI_1', 'regMC_VM_MARC_LEN_HI_1_BASE_IDX', + 'regMC_VM_MARC_LEN_HI_2', 'regMC_VM_MARC_LEN_HI_2_BASE_IDX', + 'regMC_VM_MARC_LEN_HI_3', 'regMC_VM_MARC_LEN_HI_3_BASE_IDX', + 'regMC_VM_MARC_LEN_LO_0', 'regMC_VM_MARC_LEN_LO_0_BASE_IDX', + 'regMC_VM_MARC_LEN_LO_1', 'regMC_VM_MARC_LEN_LO_1_BASE_IDX', + 'regMC_VM_MARC_LEN_LO_2', 'regMC_VM_MARC_LEN_LO_2_BASE_IDX', + 'regMC_VM_MARC_LEN_LO_3', 'regMC_VM_MARC_LEN_LO_3_BASE_IDX', + 'regMC_VM_MARC_RELOC_HI_0', 'regMC_VM_MARC_RELOC_HI_0_BASE_IDX', + 'regMC_VM_MARC_RELOC_HI_1', 'regMC_VM_MARC_RELOC_HI_1_BASE_IDX', + 'regMC_VM_MARC_RELOC_HI_2', 'regMC_VM_MARC_RELOC_HI_2_BASE_IDX', + 'regMC_VM_MARC_RELOC_HI_3', 'regMC_VM_MARC_RELOC_HI_3_BASE_IDX', + 'regMC_VM_MARC_RELOC_LO_0', 'regMC_VM_MARC_RELOC_LO_0_BASE_IDX', + 'regMC_VM_MARC_RELOC_LO_1', 'regMC_VM_MARC_RELOC_LO_1_BASE_IDX', + 'regMC_VM_MARC_RELOC_LO_2', 'regMC_VM_MARC_RELOC_LO_2_BASE_IDX', + 'regMC_VM_MARC_RELOC_LO_3', 'regMC_VM_MARC_RELOC_LO_3_BASE_IDX', + 'regMC_VM_MX_L1_TLB_CNTL', 'regMC_VM_MX_L1_TLB_CNTL_BASE_IDX', + 'regMC_VM_NB_LOWER_TOP_OF_DRAM2', + 'regMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX', 'regMC_VM_NB_MMIOBASE', + 'regMC_VM_NB_MMIOBASE_BASE_IDX', 'regMC_VM_NB_MMIOLIMIT', + 'regMC_VM_NB_MMIOLIMIT_BASE_IDX', 'regMC_VM_NB_PCI_ARB', + 'regMC_VM_NB_PCI_ARB_BASE_IDX', 'regMC_VM_NB_PCI_CTRL', + 'regMC_VM_NB_PCI_CTRL_BASE_IDX', 'regMC_VM_NB_TOP_OF_DRAM_SLOT1', + 'regMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX', + 'regMC_VM_NB_UPPER_TOP_OF_DRAM2', + 'regMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX', 'regMC_VM_STEERING', + 'regMC_VM_STEERING_BASE_IDX', + 'regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB', + 'regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX', + 'regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB', + 'regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX', + 'regMC_VM_SYSTEM_APERTURE_HIGH_ADDR', + 'regMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX', + 'regMC_VM_SYSTEM_APERTURE_LOW_ADDR', + 'regMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX', + 'regMC_VM_XGMI_GPUIOV_ENABLE', + 'regMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX', 'regMC_VM_XGMI_LFB_CNTL', + 'regMC_VM_XGMI_LFB_CNTL_BASE_IDX', 'regMC_VM_XGMI_LFB_SIZE', + 'regMC_VM_XGMI_LFB_SIZE_BASE_IDX', 'regPA_CL_CLIP_CNTL', + 'regPA_CL_CLIP_CNTL_BASE_IDX', 'regPA_CL_CNTL_STATUS', + 'regPA_CL_CNTL_STATUS_BASE_IDX', 'regPA_CL_ENHANCE', + 'regPA_CL_ENHANCE_BASE_IDX', 'regPA_CL_GB_HORZ_CLIP_ADJ', + 'regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX', 'regPA_CL_GB_HORZ_DISC_ADJ', + 'regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX', 'regPA_CL_GB_VERT_CLIP_ADJ', + 'regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX', 'regPA_CL_GB_VERT_DISC_ADJ', + 'regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX', 'regPA_CL_NANINF_CNTL', + 'regPA_CL_NANINF_CNTL_BASE_IDX', 'regPA_CL_NGG_CNTL', + 'regPA_CL_NGG_CNTL_BASE_IDX', 'regPA_CL_OBJPRIM_ID_CNTL', + 'regPA_CL_OBJPRIM_ID_CNTL_BASE_IDX', 'regPA_CL_POINT_CULL_RAD', + 'regPA_CL_POINT_CULL_RAD_BASE_IDX', 'regPA_CL_POINT_SIZE', + 'regPA_CL_POINT_SIZE_BASE_IDX', 'regPA_CL_POINT_X_RAD', + 'regPA_CL_POINT_X_RAD_BASE_IDX', 'regPA_CL_POINT_Y_RAD', + 'regPA_CL_POINT_Y_RAD_BASE_IDX', 'regPA_CL_PROG_NEAR_CLIP_Z', + 'regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX', 'regPA_CL_RESET_DEBUG', + 'regPA_CL_RESET_DEBUG_BASE_IDX', 'regPA_CL_UCP_0_W', + 'regPA_CL_UCP_0_W_BASE_IDX', 'regPA_CL_UCP_0_X', + 'regPA_CL_UCP_0_X_BASE_IDX', 'regPA_CL_UCP_0_Y', + 'regPA_CL_UCP_0_Y_BASE_IDX', 'regPA_CL_UCP_0_Z', + 'regPA_CL_UCP_0_Z_BASE_IDX', 'regPA_CL_UCP_1_W', + 'regPA_CL_UCP_1_W_BASE_IDX', 'regPA_CL_UCP_1_X', + 'regPA_CL_UCP_1_X_BASE_IDX', 'regPA_CL_UCP_1_Y', + 'regPA_CL_UCP_1_Y_BASE_IDX', 'regPA_CL_UCP_1_Z', + 'regPA_CL_UCP_1_Z_BASE_IDX', 'regPA_CL_UCP_2_W', + 'regPA_CL_UCP_2_W_BASE_IDX', 'regPA_CL_UCP_2_X', + 'regPA_CL_UCP_2_X_BASE_IDX', 'regPA_CL_UCP_2_Y', + 'regPA_CL_UCP_2_Y_BASE_IDX', 'regPA_CL_UCP_2_Z', + 'regPA_CL_UCP_2_Z_BASE_IDX', 'regPA_CL_UCP_3_W', + 'regPA_CL_UCP_3_W_BASE_IDX', 'regPA_CL_UCP_3_X', + 'regPA_CL_UCP_3_X_BASE_IDX', 'regPA_CL_UCP_3_Y', + 'regPA_CL_UCP_3_Y_BASE_IDX', 'regPA_CL_UCP_3_Z', + 'regPA_CL_UCP_3_Z_BASE_IDX', 'regPA_CL_UCP_4_W', + 'regPA_CL_UCP_4_W_BASE_IDX', 'regPA_CL_UCP_4_X', + 'regPA_CL_UCP_4_X_BASE_IDX', 'regPA_CL_UCP_4_Y', + 'regPA_CL_UCP_4_Y_BASE_IDX', 'regPA_CL_UCP_4_Z', + 'regPA_CL_UCP_4_Z_BASE_IDX', 'regPA_CL_UCP_5_W', + 'regPA_CL_UCP_5_W_BASE_IDX', 'regPA_CL_UCP_5_X', + 'regPA_CL_UCP_5_X_BASE_IDX', 'regPA_CL_UCP_5_Y', + 'regPA_CL_UCP_5_Y_BASE_IDX', 'regPA_CL_UCP_5_Z', + 'regPA_CL_UCP_5_Z_BASE_IDX', 'regPA_CL_VPORT_XOFFSET', + 'regPA_CL_VPORT_XOFFSET_1', 'regPA_CL_VPORT_XOFFSET_10', + 'regPA_CL_VPORT_XOFFSET_10_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_11', + 'regPA_CL_VPORT_XOFFSET_11_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_12', + 'regPA_CL_VPORT_XOFFSET_12_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_13', + 'regPA_CL_VPORT_XOFFSET_13_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_14', + 'regPA_CL_VPORT_XOFFSET_14_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_15', + 'regPA_CL_VPORT_XOFFSET_15_BASE_IDX', + 'regPA_CL_VPORT_XOFFSET_1_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_2', + 'regPA_CL_VPORT_XOFFSET_2_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_3', + 'regPA_CL_VPORT_XOFFSET_3_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_4', + 'regPA_CL_VPORT_XOFFSET_4_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_5', + 'regPA_CL_VPORT_XOFFSET_5_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_6', + 'regPA_CL_VPORT_XOFFSET_6_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_7', + 'regPA_CL_VPORT_XOFFSET_7_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_8', + 'regPA_CL_VPORT_XOFFSET_8_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_9', + 'regPA_CL_VPORT_XOFFSET_9_BASE_IDX', + 'regPA_CL_VPORT_XOFFSET_BASE_IDX', 'regPA_CL_VPORT_XSCALE', + 'regPA_CL_VPORT_XSCALE_1', 'regPA_CL_VPORT_XSCALE_10', + 'regPA_CL_VPORT_XSCALE_10_BASE_IDX', 'regPA_CL_VPORT_XSCALE_11', + 'regPA_CL_VPORT_XSCALE_11_BASE_IDX', 'regPA_CL_VPORT_XSCALE_12', + 'regPA_CL_VPORT_XSCALE_12_BASE_IDX', 'regPA_CL_VPORT_XSCALE_13', + 'regPA_CL_VPORT_XSCALE_13_BASE_IDX', 'regPA_CL_VPORT_XSCALE_14', + 'regPA_CL_VPORT_XSCALE_14_BASE_IDX', 'regPA_CL_VPORT_XSCALE_15', + 'regPA_CL_VPORT_XSCALE_15_BASE_IDX', + 'regPA_CL_VPORT_XSCALE_1_BASE_IDX', 'regPA_CL_VPORT_XSCALE_2', + 'regPA_CL_VPORT_XSCALE_2_BASE_IDX', 'regPA_CL_VPORT_XSCALE_3', + 'regPA_CL_VPORT_XSCALE_3_BASE_IDX', 'regPA_CL_VPORT_XSCALE_4', + 'regPA_CL_VPORT_XSCALE_4_BASE_IDX', 'regPA_CL_VPORT_XSCALE_5', + 'regPA_CL_VPORT_XSCALE_5_BASE_IDX', 'regPA_CL_VPORT_XSCALE_6', + 'regPA_CL_VPORT_XSCALE_6_BASE_IDX', 'regPA_CL_VPORT_XSCALE_7', + 'regPA_CL_VPORT_XSCALE_7_BASE_IDX', 'regPA_CL_VPORT_XSCALE_8', + 'regPA_CL_VPORT_XSCALE_8_BASE_IDX', 'regPA_CL_VPORT_XSCALE_9', + 'regPA_CL_VPORT_XSCALE_9_BASE_IDX', + 'regPA_CL_VPORT_XSCALE_BASE_IDX', 'regPA_CL_VPORT_YOFFSET', + 'regPA_CL_VPORT_YOFFSET_1', 'regPA_CL_VPORT_YOFFSET_10', + 'regPA_CL_VPORT_YOFFSET_10_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_11', + 'regPA_CL_VPORT_YOFFSET_11_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_12', + 'regPA_CL_VPORT_YOFFSET_12_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_13', + 'regPA_CL_VPORT_YOFFSET_13_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_14', + 'regPA_CL_VPORT_YOFFSET_14_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_15', + 'regPA_CL_VPORT_YOFFSET_15_BASE_IDX', + 'regPA_CL_VPORT_YOFFSET_1_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_2', + 'regPA_CL_VPORT_YOFFSET_2_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_3', + 'regPA_CL_VPORT_YOFFSET_3_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_4', + 'regPA_CL_VPORT_YOFFSET_4_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_5', + 'regPA_CL_VPORT_YOFFSET_5_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_6', + 'regPA_CL_VPORT_YOFFSET_6_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_7', + 'regPA_CL_VPORT_YOFFSET_7_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_8', + 'regPA_CL_VPORT_YOFFSET_8_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_9', + 'regPA_CL_VPORT_YOFFSET_9_BASE_IDX', + 'regPA_CL_VPORT_YOFFSET_BASE_IDX', 'regPA_CL_VPORT_YSCALE', + 'regPA_CL_VPORT_YSCALE_1', 'regPA_CL_VPORT_YSCALE_10', + 'regPA_CL_VPORT_YSCALE_10_BASE_IDX', 'regPA_CL_VPORT_YSCALE_11', + 'regPA_CL_VPORT_YSCALE_11_BASE_IDX', 'regPA_CL_VPORT_YSCALE_12', + 'regPA_CL_VPORT_YSCALE_12_BASE_IDX', 'regPA_CL_VPORT_YSCALE_13', + 'regPA_CL_VPORT_YSCALE_13_BASE_IDX', 'regPA_CL_VPORT_YSCALE_14', + 'regPA_CL_VPORT_YSCALE_14_BASE_IDX', 'regPA_CL_VPORT_YSCALE_15', + 'regPA_CL_VPORT_YSCALE_15_BASE_IDX', + 'regPA_CL_VPORT_YSCALE_1_BASE_IDX', 'regPA_CL_VPORT_YSCALE_2', + 'regPA_CL_VPORT_YSCALE_2_BASE_IDX', 'regPA_CL_VPORT_YSCALE_3', + 'regPA_CL_VPORT_YSCALE_3_BASE_IDX', 'regPA_CL_VPORT_YSCALE_4', + 'regPA_CL_VPORT_YSCALE_4_BASE_IDX', 'regPA_CL_VPORT_YSCALE_5', + 'regPA_CL_VPORT_YSCALE_5_BASE_IDX', 'regPA_CL_VPORT_YSCALE_6', + 'regPA_CL_VPORT_YSCALE_6_BASE_IDX', 'regPA_CL_VPORT_YSCALE_7', + 'regPA_CL_VPORT_YSCALE_7_BASE_IDX', 'regPA_CL_VPORT_YSCALE_8', + 'regPA_CL_VPORT_YSCALE_8_BASE_IDX', 'regPA_CL_VPORT_YSCALE_9', + 'regPA_CL_VPORT_YSCALE_9_BASE_IDX', + 'regPA_CL_VPORT_YSCALE_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET', + 'regPA_CL_VPORT_ZOFFSET_1', 'regPA_CL_VPORT_ZOFFSET_10', + 'regPA_CL_VPORT_ZOFFSET_10_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_11', + 'regPA_CL_VPORT_ZOFFSET_11_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_12', + 'regPA_CL_VPORT_ZOFFSET_12_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_13', + 'regPA_CL_VPORT_ZOFFSET_13_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_14', + 'regPA_CL_VPORT_ZOFFSET_14_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_15', + 'regPA_CL_VPORT_ZOFFSET_15_BASE_IDX', + 'regPA_CL_VPORT_ZOFFSET_1_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_2', + 'regPA_CL_VPORT_ZOFFSET_2_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_3', + 'regPA_CL_VPORT_ZOFFSET_3_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_4', + 'regPA_CL_VPORT_ZOFFSET_4_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_5', + 'regPA_CL_VPORT_ZOFFSET_5_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_6', + 'regPA_CL_VPORT_ZOFFSET_6_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_7', + 'regPA_CL_VPORT_ZOFFSET_7_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_8', + 'regPA_CL_VPORT_ZOFFSET_8_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_9', + 'regPA_CL_VPORT_ZOFFSET_9_BASE_IDX', + 'regPA_CL_VPORT_ZOFFSET_BASE_IDX', 'regPA_CL_VPORT_ZSCALE', + 'regPA_CL_VPORT_ZSCALE_1', 'regPA_CL_VPORT_ZSCALE_10', + 'regPA_CL_VPORT_ZSCALE_10_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_11', + 'regPA_CL_VPORT_ZSCALE_11_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_12', + 'regPA_CL_VPORT_ZSCALE_12_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_13', + 'regPA_CL_VPORT_ZSCALE_13_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_14', + 'regPA_CL_VPORT_ZSCALE_14_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_15', + 'regPA_CL_VPORT_ZSCALE_15_BASE_IDX', + 'regPA_CL_VPORT_ZSCALE_1_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_2', + 'regPA_CL_VPORT_ZSCALE_2_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_3', + 'regPA_CL_VPORT_ZSCALE_3_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_4', + 'regPA_CL_VPORT_ZSCALE_4_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_5', + 'regPA_CL_VPORT_ZSCALE_5_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_6', + 'regPA_CL_VPORT_ZSCALE_6_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_7', + 'regPA_CL_VPORT_ZSCALE_7_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_8', + 'regPA_CL_VPORT_ZSCALE_8_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_9', + 'regPA_CL_VPORT_ZSCALE_9_BASE_IDX', + 'regPA_CL_VPORT_ZSCALE_BASE_IDX', 'regPA_CL_VS_OUT_CNTL', + 'regPA_CL_VS_OUT_CNTL_BASE_IDX', 'regPA_CL_VTE_CNTL', + 'regPA_CL_VTE_CNTL_BASE_IDX', 'regPA_SC_AA_CONFIG', + 'regPA_SC_AA_CONFIG_BASE_IDX', 'regPA_SC_AA_MASK_X0Y0_X1Y0', + 'regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX', + 'regPA_SC_AA_MASK_X0Y1_X1Y1', + 'regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3', + 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX', + 'regPA_SC_BINNER_CNTL_0', 'regPA_SC_BINNER_CNTL_0_BASE_IDX', + 'regPA_SC_BINNER_CNTL_1', 'regPA_SC_BINNER_CNTL_1_BASE_IDX', + 'regPA_SC_BINNER_EVENT_CNTL_0', + 'regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX', + 'regPA_SC_BINNER_EVENT_CNTL_1', + 'regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX', + 'regPA_SC_BINNER_EVENT_CNTL_2', + 'regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX', + 'regPA_SC_BINNER_EVENT_CNTL_3', + 'regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX', + 'regPA_SC_BINNER_PERF_CNTL_0', + 'regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX', + 'regPA_SC_BINNER_PERF_CNTL_1', + 'regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX', + 'regPA_SC_BINNER_PERF_CNTL_2', + 'regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX', + 'regPA_SC_BINNER_PERF_CNTL_3', + 'regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX', + 'regPA_SC_BINNER_TIMEOUT_COUNTER', + 'regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX', + 'regPA_SC_CENTROID_PRIORITY_0', + 'regPA_SC_CENTROID_PRIORITY_0_BASE_IDX', + 'regPA_SC_CENTROID_PRIORITY_1', + 'regPA_SC_CENTROID_PRIORITY_1_BASE_IDX', 'regPA_SC_CLIPRECT_0_BR', + 'regPA_SC_CLIPRECT_0_BR_BASE_IDX', 'regPA_SC_CLIPRECT_0_TL', + 'regPA_SC_CLIPRECT_0_TL_BASE_IDX', 'regPA_SC_CLIPRECT_1_BR', + 'regPA_SC_CLIPRECT_1_BR_BASE_IDX', 'regPA_SC_CLIPRECT_1_TL', + 'regPA_SC_CLIPRECT_1_TL_BASE_IDX', 'regPA_SC_CLIPRECT_2_BR', + 'regPA_SC_CLIPRECT_2_BR_BASE_IDX', 'regPA_SC_CLIPRECT_2_TL', + 'regPA_SC_CLIPRECT_2_TL_BASE_IDX', 'regPA_SC_CLIPRECT_3_BR', + 'regPA_SC_CLIPRECT_3_BR_BASE_IDX', 'regPA_SC_CLIPRECT_3_TL', + 'regPA_SC_CLIPRECT_3_TL_BASE_IDX', 'regPA_SC_CLIPRECT_RULE', + 'regPA_SC_CLIPRECT_RULE_BASE_IDX', + 'regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL', + 'regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX', + 'regPA_SC_DSM_CNTL', 'regPA_SC_DSM_CNTL_BASE_IDX', + 'regPA_SC_EDGERULE', 'regPA_SC_EDGERULE_BASE_IDX', + 'regPA_SC_ENHANCE', 'regPA_SC_ENHANCE_1', + 'regPA_SC_ENHANCE_1_BASE_IDX', 'regPA_SC_ENHANCE_2', + 'regPA_SC_ENHANCE_2_BASE_IDX', 'regPA_SC_ENHANCE_BASE_IDX', + 'regPA_SC_FIFO_DEPTH_CNTL', 'regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX', + 'regPA_SC_FIFO_SIZE', 'regPA_SC_FIFO_SIZE_BASE_IDX', + 'regPA_SC_FORCE_EOV_MAX_CNTS', + 'regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX', + 'regPA_SC_GENERIC_SCISSOR_BR', + 'regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX', + 'regPA_SC_GENERIC_SCISSOR_TL', + 'regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX', 'regPA_SC_HORIZ_GRID', + 'regPA_SC_HORIZ_GRID_BASE_IDX', 'regPA_SC_HP3D_TRAP_SCREEN_COUNT', + 'regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX', + 'regPA_SC_HP3D_TRAP_SCREEN_H', 'regPA_SC_HP3D_TRAP_SCREEN_HV_EN', + 'regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX', + 'regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK', + 'regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX', + 'regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX', + 'regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE', + 'regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX', + 'regPA_SC_HP3D_TRAP_SCREEN_V', + 'regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX', 'regPA_SC_IF_FIFO_SIZE', + 'regPA_SC_IF_FIFO_SIZE_BASE_IDX', 'regPA_SC_LEFT_VERT_GRID', + 'regPA_SC_LEFT_VERT_GRID_BASE_IDX', 'regPA_SC_LINE_CNTL', + 'regPA_SC_LINE_CNTL_BASE_IDX', 'regPA_SC_LINE_STIPPLE', + 'regPA_SC_LINE_STIPPLE_BASE_IDX', 'regPA_SC_LINE_STIPPLE_STATE', + 'regPA_SC_LINE_STIPPLE_STATE_BASE_IDX', 'regPA_SC_MODE_CNTL_0', + 'regPA_SC_MODE_CNTL_0_BASE_IDX', 'regPA_SC_MODE_CNTL_1', + 'regPA_SC_MODE_CNTL_1_BASE_IDX', 'regPA_SC_NGG_MODE_CNTL', + 'regPA_SC_NGG_MODE_CNTL_BASE_IDX', + 'regPA_SC_P3D_TRAP_SCREEN_COUNT', + 'regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX', + 'regPA_SC_P3D_TRAP_SCREEN_H', 'regPA_SC_P3D_TRAP_SCREEN_HV_EN', + 'regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX', + 'regPA_SC_P3D_TRAP_SCREEN_HV_LOCK', + 'regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX', + 'regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX', + 'regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE', + 'regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX', + 'regPA_SC_P3D_TRAP_SCREEN_V', + 'regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX', 'regPA_SC_PERFCOUNTER0_HI', + 'regPA_SC_PERFCOUNTER0_HI_BASE_IDX', 'regPA_SC_PERFCOUNTER0_LO', + 'regPA_SC_PERFCOUNTER0_LO_BASE_IDX', + 'regPA_SC_PERFCOUNTER0_SELECT', 'regPA_SC_PERFCOUNTER0_SELECT1', + 'regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX', + 'regPA_SC_PERFCOUNTER1_HI', 'regPA_SC_PERFCOUNTER1_HI_BASE_IDX', + 'regPA_SC_PERFCOUNTER1_LO', 'regPA_SC_PERFCOUNTER1_LO_BASE_IDX', + 'regPA_SC_PERFCOUNTER1_SELECT', + 'regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX', + 'regPA_SC_PERFCOUNTER2_HI', 'regPA_SC_PERFCOUNTER2_HI_BASE_IDX', + 'regPA_SC_PERFCOUNTER2_LO', 'regPA_SC_PERFCOUNTER2_LO_BASE_IDX', + 'regPA_SC_PERFCOUNTER2_SELECT', + 'regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX', + 'regPA_SC_PERFCOUNTER3_HI', 'regPA_SC_PERFCOUNTER3_HI_BASE_IDX', + 'regPA_SC_PERFCOUNTER3_LO', 'regPA_SC_PERFCOUNTER3_LO_BASE_IDX', + 'regPA_SC_PERFCOUNTER3_SELECT', + 'regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX', + 'regPA_SC_PERFCOUNTER4_HI', 'regPA_SC_PERFCOUNTER4_HI_BASE_IDX', + 'regPA_SC_PERFCOUNTER4_LO', 'regPA_SC_PERFCOUNTER4_LO_BASE_IDX', + 'regPA_SC_PERFCOUNTER4_SELECT', + 'regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX', + 'regPA_SC_PERFCOUNTER5_HI', 'regPA_SC_PERFCOUNTER5_HI_BASE_IDX', + 'regPA_SC_PERFCOUNTER5_LO', 'regPA_SC_PERFCOUNTER5_LO_BASE_IDX', + 'regPA_SC_PERFCOUNTER5_SELECT', + 'regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX', + 'regPA_SC_PERFCOUNTER6_HI', 'regPA_SC_PERFCOUNTER6_HI_BASE_IDX', + 'regPA_SC_PERFCOUNTER6_LO', 'regPA_SC_PERFCOUNTER6_LO_BASE_IDX', + 'regPA_SC_PERFCOUNTER6_SELECT', + 'regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX', + 'regPA_SC_PERFCOUNTER7_HI', 'regPA_SC_PERFCOUNTER7_HI_BASE_IDX', + 'regPA_SC_PERFCOUNTER7_LO', 'regPA_SC_PERFCOUNTER7_LO_BASE_IDX', + 'regPA_SC_PERFCOUNTER7_SELECT', + 'regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX', + 'regPA_SC_PKR_WAVE_TABLE_CNTL', + 'regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX', 'regPA_SC_RASTER_CONFIG', + 'regPA_SC_RASTER_CONFIG_1', 'regPA_SC_RASTER_CONFIG_1_BASE_IDX', + 'regPA_SC_RASTER_CONFIG_BASE_IDX', 'regPA_SC_RIGHT_VERT_GRID', + 'regPA_SC_RIGHT_VERT_GRID_BASE_IDX', + 'regPA_SC_SCREEN_EXTENT_CONTROL', + 'regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX', + 'regPA_SC_SCREEN_EXTENT_MAX_0', + 'regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX', + 'regPA_SC_SCREEN_EXTENT_MAX_1', + 'regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX', + 'regPA_SC_SCREEN_EXTENT_MIN_0', + 'regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX', + 'regPA_SC_SCREEN_EXTENT_MIN_1', + 'regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX', + 'regPA_SC_SCREEN_SCISSOR_BR', + 'regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX', + 'regPA_SC_SCREEN_SCISSOR_TL', + 'regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX', 'regPA_SC_SHADER_CONTROL', + 'regPA_SC_SHADER_CONTROL_BASE_IDX', + 'regPA_SC_TILE_STEERING_CREST_OVERRIDE', + 'regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX', + 'regPA_SC_TILE_STEERING_OVERRIDE', + 'regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX', + 'regPA_SC_TRAP_SCREEN_COUNT', + 'regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX', 'regPA_SC_TRAP_SCREEN_H', + 'regPA_SC_TRAP_SCREEN_HV_EN', + 'regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX', + 'regPA_SC_TRAP_SCREEN_HV_LOCK', + 'regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX', + 'regPA_SC_TRAP_SCREEN_H_BASE_IDX', + 'regPA_SC_TRAP_SCREEN_OCCURRENCE', + 'regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX', + 'regPA_SC_TRAP_SCREEN_V', 'regPA_SC_TRAP_SCREEN_V_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_0_BR', + 'regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_0_TL', + 'regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_10_BR', + 'regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_10_TL', + 'regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_11_BR', + 'regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_11_TL', + 'regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_12_BR', + 'regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_12_TL', + 'regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_13_BR', + 'regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_13_TL', + 'regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_14_BR', + 'regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_14_TL', + 'regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_15_BR', + 'regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_15_TL', + 'regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_1_BR', + 'regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_1_TL', + 'regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_2_BR', + 'regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_2_TL', + 'regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_3_BR', + 'regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_3_TL', + 'regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_4_BR', + 'regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_4_TL', + 'regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_5_BR', + 'regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_5_TL', + 'regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_6_BR', + 'regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_6_TL', + 'regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_7_BR', + 'regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_7_TL', + 'regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_8_BR', + 'regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_8_TL', + 'regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_9_BR', + 'regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX', + 'regPA_SC_VPORT_SCISSOR_9_TL', + 'regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX', 'regPA_SC_VPORT_ZMAX_0', + 'regPA_SC_VPORT_ZMAX_0_BASE_IDX', 'regPA_SC_VPORT_ZMAX_1', + 'regPA_SC_VPORT_ZMAX_10', 'regPA_SC_VPORT_ZMAX_10_BASE_IDX', + 'regPA_SC_VPORT_ZMAX_11', 'regPA_SC_VPORT_ZMAX_11_BASE_IDX', + 'regPA_SC_VPORT_ZMAX_12', 'regPA_SC_VPORT_ZMAX_12_BASE_IDX', + 'regPA_SC_VPORT_ZMAX_13', 'regPA_SC_VPORT_ZMAX_13_BASE_IDX', + 'regPA_SC_VPORT_ZMAX_14', 'regPA_SC_VPORT_ZMAX_14_BASE_IDX', + 'regPA_SC_VPORT_ZMAX_15', 'regPA_SC_VPORT_ZMAX_15_BASE_IDX', + 'regPA_SC_VPORT_ZMAX_1_BASE_IDX', 'regPA_SC_VPORT_ZMAX_2', + 'regPA_SC_VPORT_ZMAX_2_BASE_IDX', 'regPA_SC_VPORT_ZMAX_3', + 'regPA_SC_VPORT_ZMAX_3_BASE_IDX', 'regPA_SC_VPORT_ZMAX_4', + 'regPA_SC_VPORT_ZMAX_4_BASE_IDX', 'regPA_SC_VPORT_ZMAX_5', + 'regPA_SC_VPORT_ZMAX_5_BASE_IDX', 'regPA_SC_VPORT_ZMAX_6', + 'regPA_SC_VPORT_ZMAX_6_BASE_IDX', 'regPA_SC_VPORT_ZMAX_7', + 'regPA_SC_VPORT_ZMAX_7_BASE_IDX', 'regPA_SC_VPORT_ZMAX_8', + 'regPA_SC_VPORT_ZMAX_8_BASE_IDX', 'regPA_SC_VPORT_ZMAX_9', + 'regPA_SC_VPORT_ZMAX_9_BASE_IDX', 'regPA_SC_VPORT_ZMIN_0', + 'regPA_SC_VPORT_ZMIN_0_BASE_IDX', 'regPA_SC_VPORT_ZMIN_1', + 'regPA_SC_VPORT_ZMIN_10', 'regPA_SC_VPORT_ZMIN_10_BASE_IDX', + 'regPA_SC_VPORT_ZMIN_11', 'regPA_SC_VPORT_ZMIN_11_BASE_IDX', + 'regPA_SC_VPORT_ZMIN_12', 'regPA_SC_VPORT_ZMIN_12_BASE_IDX', + 'regPA_SC_VPORT_ZMIN_13', 'regPA_SC_VPORT_ZMIN_13_BASE_IDX', + 'regPA_SC_VPORT_ZMIN_14', 'regPA_SC_VPORT_ZMIN_14_BASE_IDX', + 'regPA_SC_VPORT_ZMIN_15', 'regPA_SC_VPORT_ZMIN_15_BASE_IDX', + 'regPA_SC_VPORT_ZMIN_1_BASE_IDX', 'regPA_SC_VPORT_ZMIN_2', + 'regPA_SC_VPORT_ZMIN_2_BASE_IDX', 'regPA_SC_VPORT_ZMIN_3', + 'regPA_SC_VPORT_ZMIN_3_BASE_IDX', 'regPA_SC_VPORT_ZMIN_4', + 'regPA_SC_VPORT_ZMIN_4_BASE_IDX', 'regPA_SC_VPORT_ZMIN_5', + 'regPA_SC_VPORT_ZMIN_5_BASE_IDX', 'regPA_SC_VPORT_ZMIN_6', + 'regPA_SC_VPORT_ZMIN_6_BASE_IDX', 'regPA_SC_VPORT_ZMIN_7', + 'regPA_SC_VPORT_ZMIN_7_BASE_IDX', 'regPA_SC_VPORT_ZMIN_8', + 'regPA_SC_VPORT_ZMIN_8_BASE_IDX', 'regPA_SC_VPORT_ZMIN_9', + 'regPA_SC_VPORT_ZMIN_9_BASE_IDX', 'regPA_SC_WINDOW_OFFSET', + 'regPA_SC_WINDOW_OFFSET_BASE_IDX', 'regPA_SC_WINDOW_SCISSOR_BR', + 'regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX', + 'regPA_SC_WINDOW_SCISSOR_TL', + 'regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX', + 'regPA_SIDEBAND_REQUEST_DELAYS', + 'regPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX', 'regPA_STATE_STEREO_X', + 'regPA_STATE_STEREO_X_BASE_IDX', 'regPA_STEREO_CNTL', + 'regPA_STEREO_CNTL_BASE_IDX', 'regPA_SU_CNTL_STATUS', + 'regPA_SU_CNTL_STATUS_BASE_IDX', + 'regPA_SU_HARDWARE_SCREEN_OFFSET', + 'regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX', 'regPA_SU_LINE_CNTL', + 'regPA_SU_LINE_CNTL_BASE_IDX', 'regPA_SU_LINE_STIPPLE_CNTL', + 'regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX', + 'regPA_SU_LINE_STIPPLE_SCALE', + 'regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX', + 'regPA_SU_LINE_STIPPLE_VALUE', + 'regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX', + 'regPA_SU_OVER_RASTERIZATION_CNTL', + 'regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX', + 'regPA_SU_PERFCOUNTER0_HI', 'regPA_SU_PERFCOUNTER0_HI_BASE_IDX', + 'regPA_SU_PERFCOUNTER0_LO', 'regPA_SU_PERFCOUNTER0_LO_BASE_IDX', + 'regPA_SU_PERFCOUNTER0_SELECT', 'regPA_SU_PERFCOUNTER0_SELECT1', + 'regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX', + 'regPA_SU_PERFCOUNTER1_HI', 'regPA_SU_PERFCOUNTER1_HI_BASE_IDX', + 'regPA_SU_PERFCOUNTER1_LO', 'regPA_SU_PERFCOUNTER1_LO_BASE_IDX', + 'regPA_SU_PERFCOUNTER1_SELECT', 'regPA_SU_PERFCOUNTER1_SELECT1', + 'regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX', + 'regPA_SU_PERFCOUNTER2_HI', 'regPA_SU_PERFCOUNTER2_HI_BASE_IDX', + 'regPA_SU_PERFCOUNTER2_LO', 'regPA_SU_PERFCOUNTER2_LO_BASE_IDX', + 'regPA_SU_PERFCOUNTER2_SELECT', + 'regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX', + 'regPA_SU_PERFCOUNTER3_HI', 'regPA_SU_PERFCOUNTER3_HI_BASE_IDX', + 'regPA_SU_PERFCOUNTER3_LO', 'regPA_SU_PERFCOUNTER3_LO_BASE_IDX', + 'regPA_SU_PERFCOUNTER3_SELECT', + 'regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX', 'regPA_SU_POINT_MINMAX', + 'regPA_SU_POINT_MINMAX_BASE_IDX', 'regPA_SU_POINT_SIZE', + 'regPA_SU_POINT_SIZE_BASE_IDX', + 'regPA_SU_POLY_OFFSET_BACK_OFFSET', + 'regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX', + 'regPA_SU_POLY_OFFSET_BACK_SCALE', + 'regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX', + 'regPA_SU_POLY_OFFSET_CLAMP', + 'regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX', + 'regPA_SU_POLY_OFFSET_DB_FMT_CNTL', + 'regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX', + 'regPA_SU_POLY_OFFSET_FRONT_OFFSET', + 'regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX', + 'regPA_SU_POLY_OFFSET_FRONT_SCALE', + 'regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX', + 'regPA_SU_PRIM_FILTER_CNTL', 'regPA_SU_PRIM_FILTER_CNTL_BASE_IDX', + 'regPA_SU_SC_MODE_CNTL', 'regPA_SU_SC_MODE_CNTL_BASE_IDX', + 'regPA_SU_SMALL_PRIM_FILTER_CNTL', + 'regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX', 'regPA_SU_VTX_CNTL', + 'regPA_SU_VTX_CNTL_BASE_IDX', 'regPA_UTCL1_CNTL1', + 'regPA_UTCL1_CNTL1_BASE_IDX', 'regPA_UTCL1_CNTL2', + 'regPA_UTCL1_CNTL2_BASE_IDX', 'regRAS_BCI_SIGNATURE0', + 'regRAS_BCI_SIGNATURE0_BASE_IDX', 'regRAS_BCI_SIGNATURE1', + 'regRAS_BCI_SIGNATURE1_BASE_IDX', 'regRAS_CB_SIGNATURE0', + 'regRAS_CB_SIGNATURE0_BASE_IDX', 'regRAS_DB_SIGNATURE0', + 'regRAS_DB_SIGNATURE0_BASE_IDX', 'regRAS_IA_SIGNATURE0', + 'regRAS_IA_SIGNATURE0_BASE_IDX', 'regRAS_IA_SIGNATURE1', + 'regRAS_IA_SIGNATURE1_BASE_IDX', 'regRAS_PA_SIGNATURE0', + 'regRAS_PA_SIGNATURE0_BASE_IDX', 'regRAS_SC_SIGNATURE0', + 'regRAS_SC_SIGNATURE0_BASE_IDX', 'regRAS_SC_SIGNATURE1', + 'regRAS_SC_SIGNATURE1_BASE_IDX', 'regRAS_SC_SIGNATURE2', + 'regRAS_SC_SIGNATURE2_BASE_IDX', 'regRAS_SC_SIGNATURE3', + 'regRAS_SC_SIGNATURE3_BASE_IDX', 'regRAS_SC_SIGNATURE4', + 'regRAS_SC_SIGNATURE4_BASE_IDX', 'regRAS_SC_SIGNATURE5', + 'regRAS_SC_SIGNATURE5_BASE_IDX', 'regRAS_SC_SIGNATURE6', + 'regRAS_SC_SIGNATURE6_BASE_IDX', 'regRAS_SC_SIGNATURE7', + 'regRAS_SC_SIGNATURE7_BASE_IDX', 'regRAS_SIGNATURE_CONTROL', + 'regRAS_SIGNATURE_CONTROL_BASE_IDX', 'regRAS_SIGNATURE_MASK', + 'regRAS_SIGNATURE_MASK_BASE_IDX', 'regRAS_SPI_SIGNATURE0', + 'regRAS_SPI_SIGNATURE0_BASE_IDX', 'regRAS_SPI_SIGNATURE1', + 'regRAS_SPI_SIGNATURE1_BASE_IDX', 'regRAS_SQ_SIGNATURE0', + 'regRAS_SQ_SIGNATURE0_BASE_IDX', 'regRAS_SX_SIGNATURE0', + 'regRAS_SX_SIGNATURE0_BASE_IDX', 'regRAS_SX_SIGNATURE1', + 'regRAS_SX_SIGNATURE1_BASE_IDX', 'regRAS_SX_SIGNATURE2', + 'regRAS_SX_SIGNATURE2_BASE_IDX', 'regRAS_SX_SIGNATURE3', + 'regRAS_SX_SIGNATURE3_BASE_IDX', 'regRAS_TA_SIGNATURE0', + 'regRAS_TA_SIGNATURE0_BASE_IDX', 'regRAS_TA_SIGNATURE1', + 'regRAS_TA_SIGNATURE1_BASE_IDX', 'regRAS_TD_SIGNATURE0', + 'regRAS_TD_SIGNATURE0_BASE_IDX', 'regRAS_VGT_SIGNATURE0', + 'regRAS_VGT_SIGNATURE0_BASE_IDX', 'regRLC_AUTO_PG_CTRL', + 'regRLC_AUTO_PG_CTRL_BASE_IDX', 'regRLC_CAPTURE_GPU_CLOCK_COUNT', + 'regRLC_CAPTURE_GPU_CLOCK_COUNT_1', + 'regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX', + 'regRLC_CAPTURE_GPU_CLOCK_COUNT_2', + 'regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX', + 'regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX', + 'regRLC_CE_ERR_STATUS_HIGH', 'regRLC_CE_ERR_STATUS_HIGH_BASE_IDX', + 'regRLC_CE_ERR_STATUS_LOW', 'regRLC_CE_ERR_STATUS_LOW_BASE_IDX', + 'regRLC_CGCG_CGLS_CTRL', 'regRLC_CGCG_CGLS_CTRL_2', + 'regRLC_CGCG_CGLS_CTRL_2_BASE_IDX', + 'regRLC_CGCG_CGLS_CTRL_BASE_IDX', 'regRLC_CGCG_RAMP_CTRL', + 'regRLC_CGCG_RAMP_CTRL_BASE_IDX', 'regRLC_CGTT_MGCG_OVERRIDE', + 'regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX', 'regRLC_CLK_CNTL', + 'regRLC_CLK_CNTL_BASE_IDX', 'regRLC_CLK_COUNT_CTRL', + 'regRLC_CLK_COUNT_CTRL_BASE_IDX', 'regRLC_CLK_COUNT_GFXCLK_LSB', + 'regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX', + 'regRLC_CLK_COUNT_GFXCLK_MSB', + 'regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX', + 'regRLC_CLK_COUNT_REFCLK_LSB', + 'regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX', + 'regRLC_CLK_COUNT_REFCLK_MSB', + 'regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX', 'regRLC_CLK_COUNT_STAT', + 'regRLC_CLK_COUNT_STAT_BASE_IDX', 'regRLC_CNTL', + 'regRLC_CNTL_BASE_IDX', 'regRLC_CPG_STAT_INVAL', + 'regRLC_CPG_STAT_INVAL_BASE_IDX', 'regRLC_CP_EOF_INT', + 'regRLC_CP_EOF_INT_BASE_IDX', 'regRLC_CP_EOF_INT_CNT', + 'regRLC_CP_EOF_INT_CNT_BASE_IDX', 'regRLC_CP_SCHEDULERS', + 'regRLC_CP_SCHEDULERS_BASE_IDX', 'regRLC_CSIB_ADDR_HI', + 'regRLC_CSIB_ADDR_HI_BASE_IDX', 'regRLC_CSIB_ADDR_LO', + 'regRLC_CSIB_ADDR_LO_BASE_IDX', 'regRLC_CSIB_LENGTH', + 'regRLC_CSIB_LENGTH_BASE_IDX', 'regRLC_CU_STATUS', + 'regRLC_CU_STATUS_BASE_IDX', 'regRLC_DSM_CNTL', + 'regRLC_DSM_CNTL2', 'regRLC_DSM_CNTL2A', + 'regRLC_DSM_CNTL2A_BASE_IDX', 'regRLC_DSM_CNTL2_BASE_IDX', + 'regRLC_DSM_CNTLA', 'regRLC_DSM_CNTLA_BASE_IDX', + 'regRLC_DSM_CNTL_BASE_IDX', 'regRLC_DSM_TRIG', + 'regRLC_DSM_TRIG_BASE_IDX', 'regRLC_DS_CNTL', + 'regRLC_DS_CNTL_BASE_IDX', 'regRLC_DYN_PG_REQUEST', + 'regRLC_DYN_PG_REQUEST_BASE_IDX', 'regRLC_DYN_PG_STATUS', + 'regRLC_DYN_PG_STATUS_BASE_IDX', 'regRLC_FIREWALL_VIOLATION', + 'regRLC_FIREWALL_VIOLATION_BASE_IDX', + 'regRLC_FWL_FIRST_VIOL_ADDR', + 'regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX', 'regRLC_GFX_RM_CNTL', + 'regRLC_GFX_RM_CNTL_BASE_IDX', 'regRLC_GPM_CP_DMA_COMPLETE_T0', + 'regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX', + 'regRLC_GPM_CP_DMA_COMPLETE_T1', + 'regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX', 'regRLC_GPM_GENERAL_0', + 'regRLC_GPM_GENERAL_0_BASE_IDX', 'regRLC_GPM_GENERAL_1', + 'regRLC_GPM_GENERAL_10', 'regRLC_GPM_GENERAL_10_BASE_IDX', + 'regRLC_GPM_GENERAL_11', 'regRLC_GPM_GENERAL_11_BASE_IDX', + 'regRLC_GPM_GENERAL_12', 'regRLC_GPM_GENERAL_12_BASE_IDX', + 'regRLC_GPM_GENERAL_13', 'regRLC_GPM_GENERAL_13_BASE_IDX', + 'regRLC_GPM_GENERAL_14', 'regRLC_GPM_GENERAL_14_BASE_IDX', + 'regRLC_GPM_GENERAL_15', 'regRLC_GPM_GENERAL_15_BASE_IDX', + 'regRLC_GPM_GENERAL_1_BASE_IDX', 'regRLC_GPM_GENERAL_2', + 'regRLC_GPM_GENERAL_2_BASE_IDX', 'regRLC_GPM_GENERAL_3', + 'regRLC_GPM_GENERAL_3_BASE_IDX', 'regRLC_GPM_GENERAL_4', + 'regRLC_GPM_GENERAL_4_BASE_IDX', 'regRLC_GPM_GENERAL_5', + 'regRLC_GPM_GENERAL_5_BASE_IDX', 'regRLC_GPM_GENERAL_6', + 'regRLC_GPM_GENERAL_6_BASE_IDX', 'regRLC_GPM_GENERAL_7', + 'regRLC_GPM_GENERAL_7_BASE_IDX', 'regRLC_GPM_GENERAL_8', + 'regRLC_GPM_GENERAL_8_BASE_IDX', 'regRLC_GPM_GENERAL_9', + 'regRLC_GPM_GENERAL_9_BASE_IDX', 'regRLC_GPM_INT_DISABLE_TH0', + 'regRLC_GPM_INT_DISABLE_TH0_BASE_IDX', 'regRLC_GPM_INT_FORCE_TH0', + 'regRLC_GPM_INT_FORCE_TH0_BASE_IDX', 'regRLC_GPM_INT_FORCE_TH1', + 'regRLC_GPM_INT_FORCE_TH1_BASE_IDX', 'regRLC_GPM_INT_STAT_TH0', + 'regRLC_GPM_INT_STAT_TH0_BASE_IDX', 'regRLC_GPM_LOG_CONT', + 'regRLC_GPM_LOG_CONT_BASE_IDX', 'regRLC_GPM_LOG_SIZE', + 'regRLC_GPM_LOG_SIZE_BASE_IDX', 'regRLC_GPM_PERF_COUNT_0', + 'regRLC_GPM_PERF_COUNT_0_BASE_IDX', 'regRLC_GPM_PERF_COUNT_1', + 'regRLC_GPM_PERF_COUNT_1_BASE_IDX', 'regRLC_GPM_SCRATCH_ADDR', + 'regRLC_GPM_SCRATCH_ADDR_BASE_IDX', 'regRLC_GPM_SCRATCH_DATA', + 'regRLC_GPM_SCRATCH_DATA_BASE_IDX', 'regRLC_GPM_STAT', + 'regRLC_GPM_STAT_BASE_IDX', 'regRLC_GPM_THREAD_ENABLE', + 'regRLC_GPM_THREAD_ENABLE_BASE_IDX', 'regRLC_GPM_THREAD_PRIORITY', + 'regRLC_GPM_THREAD_PRIORITY_BASE_IDX', 'regRLC_GPM_THREAD_RESET', + 'regRLC_GPM_THREAD_RESET_BASE_IDX', 'regRLC_GPM_TIMER_CTRL', + 'regRLC_GPM_TIMER_CTRL_BASE_IDX', 'regRLC_GPM_TIMER_INT_0', + 'regRLC_GPM_TIMER_INT_0_BASE_IDX', 'regRLC_GPM_TIMER_INT_1', + 'regRLC_GPM_TIMER_INT_1_BASE_IDX', 'regRLC_GPM_TIMER_INT_2', + 'regRLC_GPM_TIMER_INT_2_BASE_IDX', 'regRLC_GPM_TIMER_INT_3', + 'regRLC_GPM_TIMER_INT_3_BASE_IDX', 'regRLC_GPM_TIMER_STAT', + 'regRLC_GPM_TIMER_STAT_BASE_IDX', 'regRLC_GPM_UCODE_ADDR', + 'regRLC_GPM_UCODE_ADDR_BASE_IDX', 'regRLC_GPM_UCODE_DATA', + 'regRLC_GPM_UCODE_DATA_BASE_IDX', 'regRLC_GPM_UTCL1_CNTL_0', + 'regRLC_GPM_UTCL1_CNTL_0_BASE_IDX', 'regRLC_GPM_UTCL1_CNTL_1', + 'regRLC_GPM_UTCL1_CNTL_1_BASE_IDX', 'regRLC_GPM_UTCL1_CNTL_2', + 'regRLC_GPM_UTCL1_CNTL_2_BASE_IDX', + 'regRLC_GPM_UTCL1_TH0_ERROR_1', + 'regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX', + 'regRLC_GPM_UTCL1_TH0_ERROR_2', + 'regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX', + 'regRLC_GPM_UTCL1_TH1_ERROR_1', + 'regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX', + 'regRLC_GPM_UTCL1_TH1_ERROR_2', + 'regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX', + 'regRLC_GPM_UTCL1_TH2_ERROR_1', + 'regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX', + 'regRLC_GPM_UTCL1_TH2_ERROR_2', + 'regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX', 'regRLC_GPR_REG1', + 'regRLC_GPR_REG1_BASE_IDX', 'regRLC_GPR_REG2', + 'regRLC_GPR_REG2_BASE_IDX', 'regRLC_GPU_CLOCK_32', + 'regRLC_GPU_CLOCK_32_BASE_IDX', 'regRLC_GPU_CLOCK_32_RES_SEL', + 'regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX', + 'regRLC_GPU_CLOCK_COUNT_LSB', 'regRLC_GPU_CLOCK_COUNT_LSB_1', + 'regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX', + 'regRLC_GPU_CLOCK_COUNT_LSB_2', + 'regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX', + 'regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX', + 'regRLC_GPU_CLOCK_COUNT_MSB', 'regRLC_GPU_CLOCK_COUNT_MSB_1', + 'regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX', + 'regRLC_GPU_CLOCK_COUNT_MSB_2', + 'regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX', + 'regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX', + 'regRLC_GPU_IOV_ACTIVE_FCN_ID', + 'regRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX', + 'regRLC_GPU_IOV_CFG_REG1', 'regRLC_GPU_IOV_CFG_REG1_BASE_IDX', + 'regRLC_GPU_IOV_CFG_REG2', 'regRLC_GPU_IOV_CFG_REG2_BASE_IDX', + 'regRLC_GPU_IOV_CFG_REG6', 'regRLC_GPU_IOV_CFG_REG6_BASE_IDX', + 'regRLC_GPU_IOV_CFG_REG8', 'regRLC_GPU_IOV_CFG_REG8_BASE_IDX', + 'regRLC_GPU_IOV_F32_CNTL', 'regRLC_GPU_IOV_F32_CNTL_BASE_IDX', + 'regRLC_GPU_IOV_F32_RESET', 'regRLC_GPU_IOV_F32_RESET_BASE_IDX', + 'regRLC_GPU_IOV_INT_DISABLE', + 'regRLC_GPU_IOV_INT_DISABLE_BASE_IDX', 'regRLC_GPU_IOV_INT_FORCE', + 'regRLC_GPU_IOV_INT_FORCE_BASE_IDX', 'regRLC_GPU_IOV_INT_STAT', + 'regRLC_GPU_IOV_INT_STAT_BASE_IDX', + 'regRLC_GPU_IOV_PERF_CNT_CNTL', + 'regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX', + 'regRLC_GPU_IOV_PERF_CNT_RD_ADDR', + 'regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX', + 'regRLC_GPU_IOV_PERF_CNT_RD_DATA', + 'regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX', + 'regRLC_GPU_IOV_PERF_CNT_WR_ADDR', + 'regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX', + 'regRLC_GPU_IOV_PERF_CNT_WR_DATA', + 'regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX', + 'regRLC_GPU_IOV_RLC_RESPONSE', + 'regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX', 'regRLC_GPU_IOV_SCH_0', + 'regRLC_GPU_IOV_SCH_0_BASE_IDX', 'regRLC_GPU_IOV_SCH_1', + 'regRLC_GPU_IOV_SCH_1_BASE_IDX', 'regRLC_GPU_IOV_SCH_2', + 'regRLC_GPU_IOV_SCH_2_BASE_IDX', 'regRLC_GPU_IOV_SCH_3', + 'regRLC_GPU_IOV_SCH_3_BASE_IDX', 'regRLC_GPU_IOV_SCH_BLOCK', + 'regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX', + 'regRLC_GPU_IOV_SCRATCH_ADDR', + 'regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX', + 'regRLC_GPU_IOV_SCRATCH_DATA', + 'regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX', + 'regRLC_GPU_IOV_SDMA0_BUSY_STATUS', + 'regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA0_STATUS', + 'regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA1_BUSY_STATUS', + 'regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA1_STATUS', + 'regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA2_BUSY_STATUS', + 'regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA2_STATUS', + 'regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA3_BUSY_STATUS', + 'regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA3_STATUS', + 'regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA4_BUSY_STATUS', + 'regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA4_STATUS', + 'regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA5_BUSY_STATUS', + 'regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA5_STATUS', + 'regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA6_BUSY_STATUS', + 'regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA6_STATUS', + 'regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA7_BUSY_STATUS', + 'regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SDMA7_STATUS', + 'regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_SMU_RESPONSE', + 'regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX', + 'regRLC_GPU_IOV_UCODE_ADDR', 'regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX', + 'regRLC_GPU_IOV_UCODE_DATA', 'regRLC_GPU_IOV_UCODE_DATA_BASE_IDX', + 'regRLC_GPU_IOV_VF_DOORBELL_STATUS', + 'regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX', + 'regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR', + 'regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX', + 'regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET', + 'regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX', + 'regRLC_GPU_IOV_VF_ENABLE', 'regRLC_GPU_IOV_VF_ENABLE_BASE_IDX', + 'regRLC_GPU_IOV_VF_MASK', 'regRLC_GPU_IOV_VF_MASK_BASE_IDX', + 'regRLC_GPU_IOV_VIRT_RESET_REQ', + 'regRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX', + 'regRLC_GPU_IOV_VM_BUSY_STATUS', + 'regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX', + 'regRLC_HYP_SEMAPHORE_0', 'regRLC_HYP_SEMAPHORE_0_BASE_IDX', + 'regRLC_HYP_SEMAPHORE_1', 'regRLC_HYP_SEMAPHORE_1_BASE_IDX', + 'regRLC_HYP_SEMAPHORE_2', 'regRLC_HYP_SEMAPHORE_2_BASE_IDX', + 'regRLC_HYP_SEMAPHORE_3', 'regRLC_HYP_SEMAPHORE_3_BASE_IDX', + 'regRLC_INT_STAT', 'regRLC_INT_STAT_BASE_IDX', + 'regRLC_JUMP_TABLE_RESTORE', 'regRLC_JUMP_TABLE_RESTORE_BASE_IDX', + 'regRLC_LBPW_CU_STAT', 'regRLC_LBPW_CU_STAT_BASE_IDX', + 'regRLC_LB_ALWAYS_ACTIVE_CU_MASK', + 'regRLC_LB_ALWAYS_ACTIVE_CU_MASK_BASE_IDX', 'regRLC_LB_CNTL', + 'regRLC_LB_CNTL_BASE_IDX', 'regRLC_LB_CNTR_INIT', + 'regRLC_LB_CNTR_INIT_BASE_IDX', 'regRLC_LB_CNTR_MAX', + 'regRLC_LB_CNTR_MAX_BASE_IDX', 'regRLC_LB_INIT_CU_MASK', + 'regRLC_LB_INIT_CU_MASK_BASE_IDX', 'regRLC_LB_PARAMS', + 'regRLC_LB_PARAMS_BASE_IDX', 'regRLC_LB_THR_CONFIG_1', + 'regRLC_LB_THR_CONFIG_1_BASE_IDX', 'regRLC_LB_THR_CONFIG_2', + 'regRLC_LB_THR_CONFIG_2_BASE_IDX', 'regRLC_LB_THR_CONFIG_3', + 'regRLC_LB_THR_CONFIG_3_BASE_IDX', 'regRLC_LB_THR_CONFIG_4', + 'regRLC_LB_THR_CONFIG_4_BASE_IDX', 'regRLC_LOAD_BALANCE_CNTR', + 'regRLC_LOAD_BALANCE_CNTR_BASE_IDX', 'regRLC_MAX_PG_CU', + 'regRLC_MAX_PG_CU_BASE_IDX', 'regRLC_MEM_SLP_CNTL', + 'regRLC_MEM_SLP_CNTL_BASE_IDX', 'regRLC_MGCG_CTRL', + 'regRLC_MGCG_CTRL_BASE_IDX', 'regRLC_PERFCOUNTER0_HI', + 'regRLC_PERFCOUNTER0_HI_BASE_IDX', 'regRLC_PERFCOUNTER0_LO', + 'regRLC_PERFCOUNTER0_LO_BASE_IDX', 'regRLC_PERFCOUNTER0_SELECT', + 'regRLC_PERFCOUNTER0_SELECT_BASE_IDX', 'regRLC_PERFCOUNTER1_HI', + 'regRLC_PERFCOUNTER1_HI_BASE_IDX', 'regRLC_PERFCOUNTER1_LO', + 'regRLC_PERFCOUNTER1_LO_BASE_IDX', 'regRLC_PERFCOUNTER1_SELECT', + 'regRLC_PERFCOUNTER1_SELECT_BASE_IDX', 'regRLC_PERFMON_CNTL', + 'regRLC_PERFMON_CNTL_BASE_IDX', 'regRLC_PG_ALWAYS_ON_CU_MASK', + 'regRLC_PG_ALWAYS_ON_CU_MASK_BASE_IDX', 'regRLC_PG_CNTL', + 'regRLC_PG_CNTL_BASE_IDX', 'regRLC_PG_DELAY', 'regRLC_PG_DELAY_2', + 'regRLC_PG_DELAY_2_BASE_IDX', 'regRLC_PG_DELAY_3', + 'regRLC_PG_DELAY_3_BASE_IDX', 'regRLC_PG_DELAY_BASE_IDX', + 'regRLC_PREWALKER_UTCL1_ADDR_LSB', + 'regRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX', + 'regRLC_PREWALKER_UTCL1_ADDR_MSB', + 'regRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX', + 'regRLC_PREWALKER_UTCL1_CNTL', + 'regRLC_PREWALKER_UTCL1_CNTL_BASE_IDX', + 'regRLC_PREWALKER_UTCL1_SIZE_LSB', + 'regRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX', + 'regRLC_PREWALKER_UTCL1_SIZE_MSB', + 'regRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX', + 'regRLC_PREWALKER_UTCL1_TRIG', + 'regRLC_PREWALKER_UTCL1_TRIG_BASE_IDX', 'regRLC_R2I_CNTL_0', + 'regRLC_R2I_CNTL_0_BASE_IDX', 'regRLC_R2I_CNTL_1', + 'regRLC_R2I_CNTL_1_BASE_IDX', 'regRLC_R2I_CNTL_2', + 'regRLC_R2I_CNTL_2_BASE_IDX', 'regRLC_R2I_CNTL_3', + 'regRLC_R2I_CNTL_3_BASE_IDX', 'regRLC_REFCLOCK_TIMESTAMP_LSB', + 'regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX', + 'regRLC_REFCLOCK_TIMESTAMP_MSB', + 'regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX', 'regRLC_RLCV_COMMAND', + 'regRLC_RLCV_COMMAND_BASE_IDX', 'regRLC_RLCV_SAFE_MODE', + 'regRLC_RLCV_SAFE_MODE_BASE_IDX', 'regRLC_RLCV_SPARE_INT', + 'regRLC_RLCV_SPARE_INT_1', 'regRLC_RLCV_SPARE_INT_1_BASE_IDX', + 'regRLC_RLCV_SPARE_INT_BASE_IDX', 'regRLC_RLCV_TIMER_CTRL', + 'regRLC_RLCV_TIMER_CTRL_BASE_IDX', 'regRLC_RLCV_TIMER_INT_0', + 'regRLC_RLCV_TIMER_INT_0_BASE_IDX', 'regRLC_RLCV_TIMER_INT_1', + 'regRLC_RLCV_TIMER_INT_1_BASE_IDX', 'regRLC_RLCV_TIMER_STAT', + 'regRLC_RLCV_TIMER_STAT_BASE_IDX', 'regRLC_SAFE_MODE', + 'regRLC_SAFE_MODE_BASE_IDX', 'regRLC_SEMAPHORE_0', + 'regRLC_SEMAPHORE_0_BASE_IDX', 'regRLC_SEMAPHORE_1', + 'regRLC_SEMAPHORE_1_BASE_IDX', 'regRLC_SEMAPHORE_2', + 'regRLC_SEMAPHORE_2_BASE_IDX', 'regRLC_SEMAPHORE_3', + 'regRLC_SEMAPHORE_3_BASE_IDX', 'regRLC_SERDES_CU_MASTER_BUSY', + 'regRLC_SERDES_CU_MASTER_BUSY_BASE_IDX', + 'regRLC_SERDES_NONCU_MASTER_BUSY', + 'regRLC_SERDES_NONCU_MASTER_BUSY_1', + 'regRLC_SERDES_NONCU_MASTER_BUSY_1_BASE_IDX', + 'regRLC_SERDES_NONCU_MASTER_BUSY_BASE_IDX', + 'regRLC_SERDES_RD_DATA_0', 'regRLC_SERDES_RD_DATA_0_BASE_IDX', + 'regRLC_SERDES_RD_DATA_1', 'regRLC_SERDES_RD_DATA_1_BASE_IDX', + 'regRLC_SERDES_RD_DATA_2', 'regRLC_SERDES_RD_DATA_2_BASE_IDX', + 'regRLC_SERDES_RD_MASTER_INDEX', + 'regRLC_SERDES_RD_MASTER_INDEX_BASE_IDX', + 'regRLC_SERDES_RD_PENDING', 'regRLC_SERDES_RD_PENDING_BASE_IDX', + 'regRLC_SERDES_WR_CTRL', 'regRLC_SERDES_WR_CTRL_BASE_IDX', + 'regRLC_SERDES_WR_CU_MASTER_MASK', + 'regRLC_SERDES_WR_CU_MASTER_MASK_BASE_IDX', + 'regRLC_SERDES_WR_DATA', 'regRLC_SERDES_WR_DATA_BASE_IDX', + 'regRLC_SERDES_WR_NONCU_MASTER_MASK', + 'regRLC_SERDES_WR_NONCU_MASTER_MASK_1', + 'regRLC_SERDES_WR_NONCU_MASTER_MASK_1_BASE_IDX', + 'regRLC_SERDES_WR_NONCU_MASTER_MASK_BASE_IDX', + 'regRLC_SMU_ARGUMENT_1', 'regRLC_SMU_ARGUMENT_1_BASE_IDX', + 'regRLC_SMU_ARGUMENT_2', 'regRLC_SMU_ARGUMENT_2_BASE_IDX', + 'regRLC_SMU_ARGUMENT_3', 'regRLC_SMU_ARGUMENT_3_BASE_IDX', + 'regRLC_SMU_ARGUMENT_4', 'regRLC_SMU_ARGUMENT_4_BASE_IDX', + 'regRLC_SMU_CLK_REQ', 'regRLC_SMU_CLK_REQ_BASE_IDX', + 'regRLC_SMU_COMMAND', 'regRLC_SMU_COMMAND_BASE_IDX', + 'regRLC_SMU_GRBM_REG_SAVE_CTRL', + 'regRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX', 'regRLC_SMU_MESSAGE', + 'regRLC_SMU_MESSAGE_BASE_IDX', 'regRLC_SMU_SAFE_MODE', + 'regRLC_SMU_SAFE_MODE_BASE_IDX', 'regRLC_SPARE_INT', + 'regRLC_SPARE_INT_1', 'regRLC_SPARE_INT_1_BASE_IDX', + 'regRLC_SPARE_INT_BASE_IDX', 'regRLC_SPM_CB_PERFMON_SAMPLE_DELAY', + 'regRLC_SPM_CB_PERFMON_SAMPLE_DELAY_BASE_IDX', + 'regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY', + 'regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_BASE_IDX', + 'regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY', + 'regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_BASE_IDX', + 'regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY', + 'regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_BASE_IDX', + 'regRLC_SPM_DB_PERFMON_SAMPLE_DELAY', + 'regRLC_SPM_DB_PERFMON_SAMPLE_DELAY_BASE_IDX', + 'regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY', + 'regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_BASE_IDX', + 'regRLC_SPM_GLOBAL_MUXSEL_ADDR', + 'regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX', + 'regRLC_SPM_GLOBAL_MUXSEL_DATA', + 'regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX', + 'regRLC_SPM_IA_PERFMON_SAMPLE_DELAY', + 'regRLC_SPM_IA_PERFMON_SAMPLE_DELAY_BASE_IDX', + 'regRLC_SPM_INT_CNTL', 'regRLC_SPM_INT_CNTL_BASE_IDX', + 'regRLC_SPM_INT_STATUS', 'regRLC_SPM_INT_STATUS_BASE_IDX', + 'regRLC_SPM_MC_CNTL', 'regRLC_SPM_MC_CNTL_BASE_IDX', + 'regRLC_SPM_PA_PERFMON_SAMPLE_DELAY', + 'regRLC_SPM_PA_PERFMON_SAMPLE_DELAY_BASE_IDX', + 'regRLC_SPM_PERFMON_CNTL', 'regRLC_SPM_PERFMON_CNTL_BASE_IDX', + 'regRLC_SPM_PERFMON_RING_BASE_HI', + 'regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX', + 'regRLC_SPM_PERFMON_RING_BASE_LO', + 'regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX', + 'regRLC_SPM_PERFMON_RING_SIZE', + 'regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX', + 'regRLC_SPM_PERFMON_SAMPLE_DELAY_MAX', + 'regRLC_SPM_PERFMON_SAMPLE_DELAY_MAX_BASE_IDX', + 'regRLC_SPM_PERFMON_SEGMENT_SIZE', + 'regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX', + 'regRLC_SPM_RING_RDPTR', 'regRLC_SPM_RING_RDPTR_BASE_IDX', + 'regRLC_SPM_RMI_PERFMON_SAMPLE_DELAY', + 'regRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_BASE_IDX', + 'regRLC_SPM_SC_PERFMON_SAMPLE_DELAY', + 'regRLC_SPM_SC_PERFMON_SAMPLE_DELAY_BASE_IDX', + 'regRLC_SPM_SEGMENT_THRESHOLD', + 'regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX', + 'regRLC_SPM_SE_MUXSEL_ADDR', 'regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX', + 'regRLC_SPM_SE_MUXSEL_DATA', 'regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX', + 'regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY', + 'regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_BASE_IDX', + 'regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY', + 'regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_BASE_IDX', + 'regRLC_SPM_SX_PERFMON_SAMPLE_DELAY', + 'regRLC_SPM_SX_PERFMON_SAMPLE_DELAY_BASE_IDX', + 'regRLC_SPM_TA_PERFMON_SAMPLE_DELAY', + 'regRLC_SPM_TA_PERFMON_SAMPLE_DELAY_BASE_IDX', + 'regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY', + 'regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_BASE_IDX', + 'regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY', + 'regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_BASE_IDX', + 'regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY', + 'regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_BASE_IDX', + 'regRLC_SPM_TD_PERFMON_SAMPLE_DELAY', + 'regRLC_SPM_TD_PERFMON_SAMPLE_DELAY_BASE_IDX', + 'regRLC_SPM_UTCL1_CNTL', 'regRLC_SPM_UTCL1_CNTL_BASE_IDX', + 'regRLC_SPM_UTCL1_ERROR_1', 'regRLC_SPM_UTCL1_ERROR_1_BASE_IDX', + 'regRLC_SPM_UTCL1_ERROR_2', 'regRLC_SPM_UTCL1_ERROR_2_BASE_IDX', + 'regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY', + 'regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_BASE_IDX', + 'regRLC_SRM_ARAM_ADDR', 'regRLC_SRM_ARAM_ADDR_BASE_IDX', + 'regRLC_SRM_ARAM_DATA', 'regRLC_SRM_ARAM_DATA_BASE_IDX', + 'regRLC_SRM_CNTL', 'regRLC_SRM_CNTL_BASE_IDX', + 'regRLC_SRM_DRAM_ADDR', 'regRLC_SRM_DRAM_ADDR_BASE_IDX', + 'regRLC_SRM_DRAM_DATA', 'regRLC_SRM_DRAM_DATA_BASE_IDX', + 'regRLC_SRM_GPM_ABORT', 'regRLC_SRM_GPM_ABORT_BASE_IDX', + 'regRLC_SRM_GPM_COMMAND', 'regRLC_SRM_GPM_COMMAND_BASE_IDX', + 'regRLC_SRM_GPM_COMMAND_STATUS', + 'regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_ADDR_0', + 'regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_ADDR_1', + 'regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_ADDR_2', + 'regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_ADDR_3', + 'regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_ADDR_4', + 'regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_ADDR_5', + 'regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_ADDR_6', + 'regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_ADDR_7', + 'regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_DATA_0', + 'regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_DATA_1', + 'regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_DATA_2', + 'regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_DATA_3', + 'regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_DATA_4', + 'regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_DATA_5', + 'regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_DATA_6', + 'regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX', + 'regRLC_SRM_INDEX_CNTL_DATA_7', + 'regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX', + 'regRLC_SRM_RLCV_COMMAND', 'regRLC_SRM_RLCV_COMMAND_BASE_IDX', + 'regRLC_SRM_RLCV_COMMAND_STATUS', + 'regRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX', 'regRLC_SRM_STAT', + 'regRLC_SRM_STAT_BASE_IDX', 'regRLC_STAT', + 'regRLC_STATIC_PG_STATUS', 'regRLC_STATIC_PG_STATUS_BASE_IDX', + 'regRLC_STAT_BASE_IDX', 'regRLC_THREAD1_DELAY', + 'regRLC_THREAD1_DELAY_BASE_IDX', 'regRLC_UCODE_CNTL', + 'regRLC_UCODE_CNTL_BASE_IDX', 'regRLC_UE_ERR_STATUS_HIGH', + 'regRLC_UE_ERR_STATUS_HIGH_BASE_IDX', 'regRLC_UE_ERR_STATUS_LOW', + 'regRLC_UE_ERR_STATUS_LOW_BASE_IDX', 'regRLC_UTCL1_STATUS', + 'regRLC_UTCL1_STATUS_2', 'regRLC_UTCL1_STATUS_2_BASE_IDX', + 'regRLC_UTCL1_STATUS_BASE_IDX', 'regRLC_UTCL2_CNTL', + 'regRLC_UTCL2_CNTL_BASE_IDX', 'regRMI_CGTT_SCLK_CTRL', + 'regRMI_CGTT_SCLK_CTRL_BASE_IDX', 'regRMI_CLOCK_CNTRL', + 'regRMI_CLOCK_CNTRL_BASE_IDX', 'regRMI_DEMUX_CNTL', + 'regRMI_DEMUX_CNTL_BASE_IDX', 'regRMI_GENERAL_CNTL', + 'regRMI_GENERAL_CNTL1', 'regRMI_GENERAL_CNTL1_BASE_IDX', + 'regRMI_GENERAL_CNTL_BASE_IDX', 'regRMI_GENERAL_STATUS', + 'regRMI_GENERAL_STATUS_BASE_IDX', 'regRMI_PERFCOUNTER0_HI', + 'regRMI_PERFCOUNTER0_HI_BASE_IDX', 'regRMI_PERFCOUNTER0_LO', + 'regRMI_PERFCOUNTER0_LO_BASE_IDX', 'regRMI_PERFCOUNTER0_SELECT', + 'regRMI_PERFCOUNTER0_SELECT1', + 'regRMI_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regRMI_PERFCOUNTER0_SELECT_BASE_IDX', 'regRMI_PERFCOUNTER1_HI', + 'regRMI_PERFCOUNTER1_HI_BASE_IDX', 'regRMI_PERFCOUNTER1_LO', + 'regRMI_PERFCOUNTER1_LO_BASE_IDX', 'regRMI_PERFCOUNTER1_SELECT', + 'regRMI_PERFCOUNTER1_SELECT_BASE_IDX', 'regRMI_PERFCOUNTER2_HI', + 'regRMI_PERFCOUNTER2_HI_BASE_IDX', 'regRMI_PERFCOUNTER2_LO', + 'regRMI_PERFCOUNTER2_LO_BASE_IDX', 'regRMI_PERFCOUNTER2_SELECT', + 'regRMI_PERFCOUNTER2_SELECT1', + 'regRMI_PERFCOUNTER2_SELECT1_BASE_IDX', + 'regRMI_PERFCOUNTER2_SELECT_BASE_IDX', 'regRMI_PERFCOUNTER3_HI', + 'regRMI_PERFCOUNTER3_HI_BASE_IDX', 'regRMI_PERFCOUNTER3_LO', + 'regRMI_PERFCOUNTER3_LO_BASE_IDX', 'regRMI_PERFCOUNTER3_SELECT', + 'regRMI_PERFCOUNTER3_SELECT_BASE_IDX', 'regRMI_PERF_COUNTER_CNTL', + 'regRMI_PERF_COUNTER_CNTL_BASE_IDX', + 'regRMI_PROBE_POP_LOGIC_CNTL', + 'regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX', 'regRMI_SCOREBOARD_CNTL', + 'regRMI_SCOREBOARD_CNTL_BASE_IDX', 'regRMI_SCOREBOARD_STATUS0', + 'regRMI_SCOREBOARD_STATUS0_BASE_IDX', 'regRMI_SCOREBOARD_STATUS1', + 'regRMI_SCOREBOARD_STATUS1_BASE_IDX', 'regRMI_SCOREBOARD_STATUS2', + 'regRMI_SCOREBOARD_STATUS2_BASE_IDX', 'regRMI_SPARE', + 'regRMI_SPARE_1', 'regRMI_SPARE_1_BASE_IDX', 'regRMI_SPARE_2', + 'regRMI_SPARE_2_BASE_IDX', 'regRMI_SPARE_BASE_IDX', + 'regRMI_SUBBLOCK_STATUS0', 'regRMI_SUBBLOCK_STATUS0_BASE_IDX', + 'regRMI_SUBBLOCK_STATUS1', 'regRMI_SUBBLOCK_STATUS1_BASE_IDX', + 'regRMI_SUBBLOCK_STATUS2', 'regRMI_SUBBLOCK_STATUS2_BASE_IDX', + 'regRMI_SUBBLOCK_STATUS3', 'regRMI_SUBBLOCK_STATUS3_BASE_IDX', + 'regRMI_TCIW_FORMATTER0_CNTL', + 'regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX', + 'regRMI_TCIW_FORMATTER1_CNTL', + 'regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX', 'regRMI_UTCL1_CNTL1', + 'regRMI_UTCL1_CNTL1_BASE_IDX', 'regRMI_UTCL1_CNTL2', + 'regRMI_UTCL1_CNTL2_BASE_IDX', 'regRMI_UTCL1_STATUS', + 'regRMI_UTCL1_STATUS_BASE_IDX', 'regRMI_UTC_UNIT_CONFIG', + 'regRMI_UTC_UNIT_CONFIG_BASE_IDX', 'regRMI_UTC_XNACK_N_MISC_CNTL', + 'regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX', + 'regRMI_XBAR_ARBITER_CONFIG', 'regRMI_XBAR_ARBITER_CONFIG_1', + 'regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX', + 'regRMI_XBAR_ARBITER_CONFIG_BASE_IDX', 'regRMI_XBAR_CONFIG', + 'regRMI_XBAR_CONFIG_BASE_IDX', 'regRMI_XNACK_DEBUG', + 'regRMI_XNACK_DEBUG_BASE_IDX', 'regSCRATCH_ADDR', + 'regSCRATCH_ADDR_BASE_IDX', 'regSCRATCH_REG0', + 'regSCRATCH_REG0_BASE_IDX', 'regSCRATCH_REG1', + 'regSCRATCH_REG1_BASE_IDX', 'regSCRATCH_REG2', + 'regSCRATCH_REG2_BASE_IDX', 'regSCRATCH_REG3', + 'regSCRATCH_REG3_BASE_IDX', 'regSCRATCH_REG4', + 'regSCRATCH_REG4_BASE_IDX', 'regSCRATCH_REG5', + 'regSCRATCH_REG5_BASE_IDX', 'regSCRATCH_REG6', + 'regSCRATCH_REG6_BASE_IDX', 'regSCRATCH_REG7', + 'regSCRATCH_REG7_BASE_IDX', 'regSCRATCH_UMSK', + 'regSCRATCH_UMSK_BASE_IDX', 'regSH_CAC_CONFIG', + 'regSH_CAC_CONFIG_BASE_IDX', 'regSH_MEM_BASES', + 'regSH_MEM_BASES_BASE_IDX', 'regSH_MEM_CONFIG', + 'regSH_MEM_CONFIG_BASE_IDX', 'regSMU_RLC_RESPONSE', + 'regSMU_RLC_RESPONSE_BASE_IDX', 'regSP0_CE_ERR_STATUS_HI', + 'regSP0_CE_ERR_STATUS_HI_BASE_IDX', 'regSP0_CE_ERR_STATUS_LO', + 'regSP0_CE_ERR_STATUS_LO_BASE_IDX', 'regSP0_UE_ERR_STATUS_HI', + 'regSP0_UE_ERR_STATUS_HI_BASE_IDX', 'regSP0_UE_ERR_STATUS_LO', + 'regSP0_UE_ERR_STATUS_LO_BASE_IDX', 'regSP1_CE_ERR_STATUS_HI', + 'regSP1_CE_ERR_STATUS_HI_BASE_IDX', 'regSP1_CE_ERR_STATUS_LO', + 'regSP1_CE_ERR_STATUS_LO_BASE_IDX', 'regSP1_UE_ERR_STATUS_HI', + 'regSP1_UE_ERR_STATUS_HI_BASE_IDX', 'regSP1_UE_ERR_STATUS_LO', + 'regSP1_UE_ERR_STATUS_LO_BASE_IDX', 'regSPIS_DEBUG_READ', + 'regSPIS_DEBUG_READ_BASE_IDX', 'regSPI_ARB_CNTL_0', + 'regSPI_ARB_CNTL_0_BASE_IDX', 'regSPI_ARB_CYCLES_0', + 'regSPI_ARB_CYCLES_0_BASE_IDX', 'regSPI_ARB_CYCLES_1', + 'regSPI_ARB_CYCLES_1_BASE_IDX', 'regSPI_ARB_PRIORITY', + 'regSPI_ARB_PRIORITY_BASE_IDX', 'regSPI_BARYC_CNTL', + 'regSPI_BARYC_CNTL_BASE_IDX', 'regSPI_CDBG_SYS_CS0', + 'regSPI_CDBG_SYS_CS0_BASE_IDX', 'regSPI_CDBG_SYS_CS1', + 'regSPI_CDBG_SYS_CS1_BASE_IDX', 'regSPI_CDBG_SYS_GFX', + 'regSPI_CDBG_SYS_GFX_BASE_IDX', 'regSPI_CDBG_SYS_HP3D', + 'regSPI_CDBG_SYS_HP3D_BASE_IDX', 'regSPI_CE_ERR_STATUS_HI', + 'regSPI_CE_ERR_STATUS_HI_BASE_IDX', 'regSPI_CE_ERR_STATUS_LO', + 'regSPI_CE_ERR_STATUS_LO_BASE_IDX', 'regSPI_COMPUTE_QUEUE_RESET', + 'regSPI_COMPUTE_QUEUE_RESET_BASE_IDX', + 'regSPI_COMPUTE_WF_CTX_SAVE', + 'regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX', 'regSPI_CONFIG_CNTL', + 'regSPI_CONFIG_CNTL_1', 'regSPI_CONFIG_CNTL_1_BASE_IDX', + 'regSPI_CONFIG_CNTL_2', 'regSPI_CONFIG_CNTL_2_BASE_IDX', + 'regSPI_CONFIG_CNTL_BASE_IDX', 'regSPI_CONFIG_PS_CU_EN', + 'regSPI_CONFIG_PS_CU_EN_BASE_IDX', 'regSPI_CSQ_WF_ACTIVE_COUNT_0', + 'regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX', + 'regSPI_CSQ_WF_ACTIVE_COUNT_1', + 'regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX', + 'regSPI_CSQ_WF_ACTIVE_COUNT_2', + 'regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX', + 'regSPI_CSQ_WF_ACTIVE_COUNT_3', + 'regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX', + 'regSPI_CSQ_WF_ACTIVE_COUNT_4', + 'regSPI_CSQ_WF_ACTIVE_COUNT_4_BASE_IDX', + 'regSPI_CSQ_WF_ACTIVE_COUNT_5', + 'regSPI_CSQ_WF_ACTIVE_COUNT_5_BASE_IDX', + 'regSPI_CSQ_WF_ACTIVE_COUNT_6', + 'regSPI_CSQ_WF_ACTIVE_COUNT_6_BASE_IDX', + 'regSPI_CSQ_WF_ACTIVE_COUNT_7', + 'regSPI_CSQ_WF_ACTIVE_COUNT_7_BASE_IDX', + 'regSPI_CSQ_WF_ACTIVE_STATUS', + 'regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX', 'regSPI_DEBUG_BUSY', + 'regSPI_DEBUG_BUSY_BASE_IDX', 'regSPI_DEBUG_READ', + 'regSPI_DEBUG_READ_BASE_IDX', 'regSPI_DSM_CNTL', + 'regSPI_DSM_CNTL2', 'regSPI_DSM_CNTL2_BASE_IDX', + 'regSPI_DSM_CNTL_BASE_IDX', 'regSPI_EDC_CNT', + 'regSPI_EDC_CNT_BASE_IDX', 'regSPI_GDBG_PER_VMID_CNTL', + 'regSPI_GDBG_PER_VMID_CNTL_BASE_IDX', 'regSPI_GDBG_TRAP_CONFIG', + 'regSPI_GDBG_TRAP_CONFIG_BASE_IDX', 'regSPI_GDBG_WAVE_CNTL', + 'regSPI_GDBG_WAVE_CNTL3', 'regSPI_GDBG_WAVE_CNTL3_BASE_IDX', + 'regSPI_GDBG_WAVE_CNTL_BASE_IDX', 'regSPI_GDS_CREDITS', + 'regSPI_GDS_CREDITS_BASE_IDX', 'regSPI_GFX_CNTL', + 'regSPI_GFX_CNTL_BASE_IDX', 'regSPI_INTERP_CONTROL_0', + 'regSPI_INTERP_CONTROL_0_BASE_IDX', 'regSPI_LB_CTR_CTRL', + 'regSPI_LB_CTR_CTRL_BASE_IDX', 'regSPI_LB_CU_MASK', + 'regSPI_LB_CU_MASK_BASE_IDX', 'regSPI_LB_DATA_PERCU_WAVE_CS', + 'regSPI_LB_DATA_PERCU_WAVE_CS_BASE_IDX', + 'regSPI_LB_DATA_PERCU_WAVE_HSGS', + 'regSPI_LB_DATA_PERCU_WAVE_HSGS_BASE_IDX', + 'regSPI_LB_DATA_PERCU_WAVE_VSPS', + 'regSPI_LB_DATA_PERCU_WAVE_VSPS_BASE_IDX', 'regSPI_LB_DATA_REG', + 'regSPI_LB_DATA_REG_BASE_IDX', 'regSPI_LB_DATA_WAVES', + 'regSPI_LB_DATA_WAVES_BASE_IDX', 'regSPI_P0_TRAP_SCREEN_GPR_MIN', + 'regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX', + 'regSPI_P0_TRAP_SCREEN_PSBA_HI', + 'regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX', + 'regSPI_P0_TRAP_SCREEN_PSBA_LO', + 'regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX', + 'regSPI_P0_TRAP_SCREEN_PSMA_HI', + 'regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX', + 'regSPI_P0_TRAP_SCREEN_PSMA_LO', + 'regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX', + 'regSPI_P1_TRAP_SCREEN_GPR_MIN', + 'regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX', + 'regSPI_P1_TRAP_SCREEN_PSBA_HI', + 'regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX', + 'regSPI_P1_TRAP_SCREEN_PSBA_LO', + 'regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX', + 'regSPI_P1_TRAP_SCREEN_PSMA_HI', + 'regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX', + 'regSPI_P1_TRAP_SCREEN_PSMA_LO', + 'regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX', + 'regSPI_PERFCOUNTER0_HI', 'regSPI_PERFCOUNTER0_HI_BASE_IDX', + 'regSPI_PERFCOUNTER0_LO', 'regSPI_PERFCOUNTER0_LO_BASE_IDX', + 'regSPI_PERFCOUNTER0_SELECT', 'regSPI_PERFCOUNTER0_SELECT1', + 'regSPI_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regSPI_PERFCOUNTER0_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER1_HI', + 'regSPI_PERFCOUNTER1_HI_BASE_IDX', 'regSPI_PERFCOUNTER1_LO', + 'regSPI_PERFCOUNTER1_LO_BASE_IDX', 'regSPI_PERFCOUNTER1_SELECT', + 'regSPI_PERFCOUNTER1_SELECT1', + 'regSPI_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regSPI_PERFCOUNTER1_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER2_HI', + 'regSPI_PERFCOUNTER2_HI_BASE_IDX', 'regSPI_PERFCOUNTER2_LO', + 'regSPI_PERFCOUNTER2_LO_BASE_IDX', 'regSPI_PERFCOUNTER2_SELECT', + 'regSPI_PERFCOUNTER2_SELECT1', + 'regSPI_PERFCOUNTER2_SELECT1_BASE_IDX', + 'regSPI_PERFCOUNTER2_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER3_HI', + 'regSPI_PERFCOUNTER3_HI_BASE_IDX', 'regSPI_PERFCOUNTER3_LO', + 'regSPI_PERFCOUNTER3_LO_BASE_IDX', 'regSPI_PERFCOUNTER3_SELECT', + 'regSPI_PERFCOUNTER3_SELECT1', + 'regSPI_PERFCOUNTER3_SELECT1_BASE_IDX', + 'regSPI_PERFCOUNTER3_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER4_HI', + 'regSPI_PERFCOUNTER4_HI_BASE_IDX', 'regSPI_PERFCOUNTER4_LO', + 'regSPI_PERFCOUNTER4_LO_BASE_IDX', 'regSPI_PERFCOUNTER4_SELECT', + 'regSPI_PERFCOUNTER4_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER5_HI', + 'regSPI_PERFCOUNTER5_HI_BASE_IDX', 'regSPI_PERFCOUNTER5_LO', + 'regSPI_PERFCOUNTER5_LO_BASE_IDX', 'regSPI_PERFCOUNTER5_SELECT', + 'regSPI_PERFCOUNTER5_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER_BINS', + 'regSPI_PERFCOUNTER_BINS_BASE_IDX', + 'regSPI_PG_ENABLE_STATIC_CU_MASK', + 'regSPI_PG_ENABLE_STATIC_CU_MASK_BASE_IDX', + 'regSPI_PS_INPUT_ADDR', 'regSPI_PS_INPUT_ADDR_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_0', 'regSPI_PS_INPUT_CNTL_0_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_1', 'regSPI_PS_INPUT_CNTL_10', + 'regSPI_PS_INPUT_CNTL_10_BASE_IDX', 'regSPI_PS_INPUT_CNTL_11', + 'regSPI_PS_INPUT_CNTL_11_BASE_IDX', 'regSPI_PS_INPUT_CNTL_12', + 'regSPI_PS_INPUT_CNTL_12_BASE_IDX', 'regSPI_PS_INPUT_CNTL_13', + 'regSPI_PS_INPUT_CNTL_13_BASE_IDX', 'regSPI_PS_INPUT_CNTL_14', + 'regSPI_PS_INPUT_CNTL_14_BASE_IDX', 'regSPI_PS_INPUT_CNTL_15', + 'regSPI_PS_INPUT_CNTL_15_BASE_IDX', 'regSPI_PS_INPUT_CNTL_16', + 'regSPI_PS_INPUT_CNTL_16_BASE_IDX', 'regSPI_PS_INPUT_CNTL_17', + 'regSPI_PS_INPUT_CNTL_17_BASE_IDX', 'regSPI_PS_INPUT_CNTL_18', + 'regSPI_PS_INPUT_CNTL_18_BASE_IDX', 'regSPI_PS_INPUT_CNTL_19', + 'regSPI_PS_INPUT_CNTL_19_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_1_BASE_IDX', 'regSPI_PS_INPUT_CNTL_2', + 'regSPI_PS_INPUT_CNTL_20', 'regSPI_PS_INPUT_CNTL_20_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_21', 'regSPI_PS_INPUT_CNTL_21_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_22', 'regSPI_PS_INPUT_CNTL_22_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_23', 'regSPI_PS_INPUT_CNTL_23_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_24', 'regSPI_PS_INPUT_CNTL_24_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_25', 'regSPI_PS_INPUT_CNTL_25_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_26', 'regSPI_PS_INPUT_CNTL_26_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_27', 'regSPI_PS_INPUT_CNTL_27_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_28', 'regSPI_PS_INPUT_CNTL_28_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_29', 'regSPI_PS_INPUT_CNTL_29_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_2_BASE_IDX', 'regSPI_PS_INPUT_CNTL_3', + 'regSPI_PS_INPUT_CNTL_30', 'regSPI_PS_INPUT_CNTL_30_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_31', 'regSPI_PS_INPUT_CNTL_31_BASE_IDX', + 'regSPI_PS_INPUT_CNTL_3_BASE_IDX', 'regSPI_PS_INPUT_CNTL_4', + 'regSPI_PS_INPUT_CNTL_4_BASE_IDX', 'regSPI_PS_INPUT_CNTL_5', + 'regSPI_PS_INPUT_CNTL_5_BASE_IDX', 'regSPI_PS_INPUT_CNTL_6', + 'regSPI_PS_INPUT_CNTL_6_BASE_IDX', 'regSPI_PS_INPUT_CNTL_7', + 'regSPI_PS_INPUT_CNTL_7_BASE_IDX', 'regSPI_PS_INPUT_CNTL_8', + 'regSPI_PS_INPUT_CNTL_8_BASE_IDX', 'regSPI_PS_INPUT_CNTL_9', + 'regSPI_PS_INPUT_CNTL_9_BASE_IDX', 'regSPI_PS_INPUT_ENA', + 'regSPI_PS_INPUT_ENA_BASE_IDX', 'regSPI_PS_IN_CONTROL', + 'regSPI_PS_IN_CONTROL_BASE_IDX', 'regSPI_PS_MAX_WAVE_ID', + 'regSPI_PS_MAX_WAVE_ID_BASE_IDX', 'regSPI_RESET_DEBUG', + 'regSPI_RESET_DEBUG_BASE_IDX', 'regSPI_RESOURCE_RESERVE_CU_0', + 'regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_1', 'regSPI_RESOURCE_RESERVE_CU_10', + 'regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_11', + 'regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_12', + 'regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_13', + 'regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_14', + 'regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_15', + 'regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_2', + 'regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_3', + 'regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_4', + 'regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_5', + 'regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_6', + 'regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_7', + 'regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_8', + 'regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_CU_9', + 'regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_0', + 'regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_1', + 'regSPI_RESOURCE_RESERVE_EN_CU_10', + 'regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_11', + 'regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_12', + 'regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_13', + 'regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_14', + 'regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_15', + 'regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_2', + 'regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_3', + 'regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_4', + 'regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_5', + 'regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_6', + 'regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_7', + 'regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_8', + 'regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX', + 'regSPI_RESOURCE_RESERVE_EN_CU_9', + 'regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX', + 'regSPI_SCRATCH_ADDR_CHECK', 'regSPI_SCRATCH_ADDR_CHECK_BASE_IDX', + 'regSPI_SCRATCH_ADDR_STATUS', + 'regSPI_SCRATCH_ADDR_STATUS_BASE_IDX', 'regSPI_SHADER_COL_FORMAT', + 'regSPI_SHADER_COL_FORMAT_BASE_IDX', + 'regSPI_SHADER_LATE_ALLOC_VS', + 'regSPI_SHADER_LATE_ALLOC_VS_BASE_IDX', 'regSPI_SHADER_PGM_HI_ES', + 'regSPI_SHADER_PGM_HI_ES_BASE_IDX', 'regSPI_SHADER_PGM_HI_GS', + 'regSPI_SHADER_PGM_HI_GS_BASE_IDX', 'regSPI_SHADER_PGM_HI_HS', + 'regSPI_SHADER_PGM_HI_HS_BASE_IDX', 'regSPI_SHADER_PGM_HI_LS', + 'regSPI_SHADER_PGM_HI_LS_BASE_IDX', 'regSPI_SHADER_PGM_HI_PS', + 'regSPI_SHADER_PGM_HI_PS_BASE_IDX', 'regSPI_SHADER_PGM_HI_VS', + 'regSPI_SHADER_PGM_HI_VS_BASE_IDX', 'regSPI_SHADER_PGM_LO_ES', + 'regSPI_SHADER_PGM_LO_ES_BASE_IDX', 'regSPI_SHADER_PGM_LO_GS', + 'regSPI_SHADER_PGM_LO_GS_BASE_IDX', 'regSPI_SHADER_PGM_LO_HS', + 'regSPI_SHADER_PGM_LO_HS_BASE_IDX', 'regSPI_SHADER_PGM_LO_LS', + 'regSPI_SHADER_PGM_LO_LS_BASE_IDX', 'regSPI_SHADER_PGM_LO_PS', + 'regSPI_SHADER_PGM_LO_PS_BASE_IDX', 'regSPI_SHADER_PGM_LO_VS', + 'regSPI_SHADER_PGM_LO_VS_BASE_IDX', 'regSPI_SHADER_PGM_RSRC1_GS', + 'regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC1_HS', + 'regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC1_PS', + 'regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC1_VS', + 'regSPI_SHADER_PGM_RSRC1_VS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC2_GS', + 'regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC2_GS_VS', + 'regSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC2_HS', + 'regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC2_PS', + 'regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC2_VS', + 'regSPI_SHADER_PGM_RSRC2_VS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC3_GS', + 'regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC3_HS', + 'regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC3_PS', + 'regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC3_VS', + 'regSPI_SHADER_PGM_RSRC3_VS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC4_GS', + 'regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX', + 'regSPI_SHADER_PGM_RSRC4_HS', + 'regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX', 'regSPI_SHADER_POS_FORMAT', + 'regSPI_SHADER_POS_FORMAT_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ADDR_HI_GS', + 'regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ADDR_HI_HS', + 'regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ADDR_LO_GS', + 'regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ADDR_LO_HS', + 'regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_0', + 'regSPI_SHADER_USER_DATA_COMMON_0_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_1', + 'regSPI_SHADER_USER_DATA_COMMON_10', + 'regSPI_SHADER_USER_DATA_COMMON_10_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_11', + 'regSPI_SHADER_USER_DATA_COMMON_11_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_12', + 'regSPI_SHADER_USER_DATA_COMMON_12_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_13', + 'regSPI_SHADER_USER_DATA_COMMON_13_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_14', + 'regSPI_SHADER_USER_DATA_COMMON_14_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_15', + 'regSPI_SHADER_USER_DATA_COMMON_15_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_16', + 'regSPI_SHADER_USER_DATA_COMMON_16_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_17', + 'regSPI_SHADER_USER_DATA_COMMON_17_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_18', + 'regSPI_SHADER_USER_DATA_COMMON_18_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_19', + 'regSPI_SHADER_USER_DATA_COMMON_19_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_1_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_2', + 'regSPI_SHADER_USER_DATA_COMMON_20', + 'regSPI_SHADER_USER_DATA_COMMON_20_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_21', + 'regSPI_SHADER_USER_DATA_COMMON_21_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_22', + 'regSPI_SHADER_USER_DATA_COMMON_22_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_23', + 'regSPI_SHADER_USER_DATA_COMMON_23_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_24', + 'regSPI_SHADER_USER_DATA_COMMON_24_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_25', + 'regSPI_SHADER_USER_DATA_COMMON_25_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_26', + 'regSPI_SHADER_USER_DATA_COMMON_26_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_27', + 'regSPI_SHADER_USER_DATA_COMMON_27_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_28', + 'regSPI_SHADER_USER_DATA_COMMON_28_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_29', + 'regSPI_SHADER_USER_DATA_COMMON_29_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_2_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_3', + 'regSPI_SHADER_USER_DATA_COMMON_30', + 'regSPI_SHADER_USER_DATA_COMMON_30_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_31', + 'regSPI_SHADER_USER_DATA_COMMON_31_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_3_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_4', + 'regSPI_SHADER_USER_DATA_COMMON_4_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_5', + 'regSPI_SHADER_USER_DATA_COMMON_5_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_6', + 'regSPI_SHADER_USER_DATA_COMMON_6_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_7', + 'regSPI_SHADER_USER_DATA_COMMON_7_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_8', + 'regSPI_SHADER_USER_DATA_COMMON_8_BASE_IDX', + 'regSPI_SHADER_USER_DATA_COMMON_9', + 'regSPI_SHADER_USER_DATA_COMMON_9_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_0', + 'regSPI_SHADER_USER_DATA_ES_0_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_1', 'regSPI_SHADER_USER_DATA_ES_10', + 'regSPI_SHADER_USER_DATA_ES_10_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_11', + 'regSPI_SHADER_USER_DATA_ES_11_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_12', + 'regSPI_SHADER_USER_DATA_ES_12_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_13', + 'regSPI_SHADER_USER_DATA_ES_13_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_14', + 'regSPI_SHADER_USER_DATA_ES_14_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_15', + 'regSPI_SHADER_USER_DATA_ES_15_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_16', + 'regSPI_SHADER_USER_DATA_ES_16_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_17', + 'regSPI_SHADER_USER_DATA_ES_17_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_18', + 'regSPI_SHADER_USER_DATA_ES_18_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_19', + 'regSPI_SHADER_USER_DATA_ES_19_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_1_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_2', 'regSPI_SHADER_USER_DATA_ES_20', + 'regSPI_SHADER_USER_DATA_ES_20_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_21', + 'regSPI_SHADER_USER_DATA_ES_21_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_22', + 'regSPI_SHADER_USER_DATA_ES_22_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_23', + 'regSPI_SHADER_USER_DATA_ES_23_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_24', + 'regSPI_SHADER_USER_DATA_ES_24_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_25', + 'regSPI_SHADER_USER_DATA_ES_25_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_26', + 'regSPI_SHADER_USER_DATA_ES_26_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_27', + 'regSPI_SHADER_USER_DATA_ES_27_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_28', + 'regSPI_SHADER_USER_DATA_ES_28_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_29', + 'regSPI_SHADER_USER_DATA_ES_29_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_2_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_3', 'regSPI_SHADER_USER_DATA_ES_30', + 'regSPI_SHADER_USER_DATA_ES_30_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_31', + 'regSPI_SHADER_USER_DATA_ES_31_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_3_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_4', + 'regSPI_SHADER_USER_DATA_ES_4_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_5', + 'regSPI_SHADER_USER_DATA_ES_5_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_6', + 'regSPI_SHADER_USER_DATA_ES_6_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_7', + 'regSPI_SHADER_USER_DATA_ES_7_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_8', + 'regSPI_SHADER_USER_DATA_ES_8_BASE_IDX', + 'regSPI_SHADER_USER_DATA_ES_9', + 'regSPI_SHADER_USER_DATA_ES_9_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_0', + 'regSPI_SHADER_USER_DATA_LS_0_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_1', 'regSPI_SHADER_USER_DATA_LS_10', + 'regSPI_SHADER_USER_DATA_LS_10_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_11', + 'regSPI_SHADER_USER_DATA_LS_11_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_12', + 'regSPI_SHADER_USER_DATA_LS_12_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_13', + 'regSPI_SHADER_USER_DATA_LS_13_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_14', + 'regSPI_SHADER_USER_DATA_LS_14_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_15', + 'regSPI_SHADER_USER_DATA_LS_15_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_16', + 'regSPI_SHADER_USER_DATA_LS_16_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_17', + 'regSPI_SHADER_USER_DATA_LS_17_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_18', + 'regSPI_SHADER_USER_DATA_LS_18_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_19', + 'regSPI_SHADER_USER_DATA_LS_19_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_1_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_2', 'regSPI_SHADER_USER_DATA_LS_20', + 'regSPI_SHADER_USER_DATA_LS_20_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_21', + 'regSPI_SHADER_USER_DATA_LS_21_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_22', + 'regSPI_SHADER_USER_DATA_LS_22_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_23', + 'regSPI_SHADER_USER_DATA_LS_23_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_24', + 'regSPI_SHADER_USER_DATA_LS_24_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_25', + 'regSPI_SHADER_USER_DATA_LS_25_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_26', + 'regSPI_SHADER_USER_DATA_LS_26_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_27', + 'regSPI_SHADER_USER_DATA_LS_27_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_28', + 'regSPI_SHADER_USER_DATA_LS_28_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_29', + 'regSPI_SHADER_USER_DATA_LS_29_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_2_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_3', 'regSPI_SHADER_USER_DATA_LS_30', + 'regSPI_SHADER_USER_DATA_LS_30_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_31', + 'regSPI_SHADER_USER_DATA_LS_31_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_3_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_4', + 'regSPI_SHADER_USER_DATA_LS_4_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_5', + 'regSPI_SHADER_USER_DATA_LS_5_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_6', + 'regSPI_SHADER_USER_DATA_LS_6_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_7', + 'regSPI_SHADER_USER_DATA_LS_7_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_8', + 'regSPI_SHADER_USER_DATA_LS_8_BASE_IDX', + 'regSPI_SHADER_USER_DATA_LS_9', + 'regSPI_SHADER_USER_DATA_LS_9_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_0', + 'regSPI_SHADER_USER_DATA_PS_0_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_1', 'regSPI_SHADER_USER_DATA_PS_10', + 'regSPI_SHADER_USER_DATA_PS_10_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_11', + 'regSPI_SHADER_USER_DATA_PS_11_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_12', + 'regSPI_SHADER_USER_DATA_PS_12_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_13', + 'regSPI_SHADER_USER_DATA_PS_13_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_14', + 'regSPI_SHADER_USER_DATA_PS_14_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_15', + 'regSPI_SHADER_USER_DATA_PS_15_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_16', + 'regSPI_SHADER_USER_DATA_PS_16_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_17', + 'regSPI_SHADER_USER_DATA_PS_17_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_18', + 'regSPI_SHADER_USER_DATA_PS_18_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_19', + 'regSPI_SHADER_USER_DATA_PS_19_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_1_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_2', 'regSPI_SHADER_USER_DATA_PS_20', + 'regSPI_SHADER_USER_DATA_PS_20_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_21', + 'regSPI_SHADER_USER_DATA_PS_21_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_22', + 'regSPI_SHADER_USER_DATA_PS_22_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_23', + 'regSPI_SHADER_USER_DATA_PS_23_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_24', + 'regSPI_SHADER_USER_DATA_PS_24_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_25', + 'regSPI_SHADER_USER_DATA_PS_25_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_26', + 'regSPI_SHADER_USER_DATA_PS_26_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_27', + 'regSPI_SHADER_USER_DATA_PS_27_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_28', + 'regSPI_SHADER_USER_DATA_PS_28_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_29', + 'regSPI_SHADER_USER_DATA_PS_29_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_2_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_3', 'regSPI_SHADER_USER_DATA_PS_30', + 'regSPI_SHADER_USER_DATA_PS_30_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_31', + 'regSPI_SHADER_USER_DATA_PS_31_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_3_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_4', + 'regSPI_SHADER_USER_DATA_PS_4_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_5', + 'regSPI_SHADER_USER_DATA_PS_5_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_6', + 'regSPI_SHADER_USER_DATA_PS_6_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_7', + 'regSPI_SHADER_USER_DATA_PS_7_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_8', + 'regSPI_SHADER_USER_DATA_PS_8_BASE_IDX', + 'regSPI_SHADER_USER_DATA_PS_9', + 'regSPI_SHADER_USER_DATA_PS_9_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_0', + 'regSPI_SHADER_USER_DATA_VS_0_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_1', 'regSPI_SHADER_USER_DATA_VS_10', + 'regSPI_SHADER_USER_DATA_VS_10_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_11', + 'regSPI_SHADER_USER_DATA_VS_11_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_12', + 'regSPI_SHADER_USER_DATA_VS_12_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_13', + 'regSPI_SHADER_USER_DATA_VS_13_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_14', + 'regSPI_SHADER_USER_DATA_VS_14_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_15', + 'regSPI_SHADER_USER_DATA_VS_15_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_16', + 'regSPI_SHADER_USER_DATA_VS_16_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_17', + 'regSPI_SHADER_USER_DATA_VS_17_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_18', + 'regSPI_SHADER_USER_DATA_VS_18_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_19', + 'regSPI_SHADER_USER_DATA_VS_19_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_1_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_2', 'regSPI_SHADER_USER_DATA_VS_20', + 'regSPI_SHADER_USER_DATA_VS_20_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_21', + 'regSPI_SHADER_USER_DATA_VS_21_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_22', + 'regSPI_SHADER_USER_DATA_VS_22_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_23', + 'regSPI_SHADER_USER_DATA_VS_23_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_24', + 'regSPI_SHADER_USER_DATA_VS_24_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_25', + 'regSPI_SHADER_USER_DATA_VS_25_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_26', + 'regSPI_SHADER_USER_DATA_VS_26_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_27', + 'regSPI_SHADER_USER_DATA_VS_27_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_28', + 'regSPI_SHADER_USER_DATA_VS_28_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_29', + 'regSPI_SHADER_USER_DATA_VS_29_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_2_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_3', 'regSPI_SHADER_USER_DATA_VS_30', + 'regSPI_SHADER_USER_DATA_VS_30_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_31', + 'regSPI_SHADER_USER_DATA_VS_31_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_3_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_4', + 'regSPI_SHADER_USER_DATA_VS_4_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_5', + 'regSPI_SHADER_USER_DATA_VS_5_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_6', + 'regSPI_SHADER_USER_DATA_VS_6_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_7', + 'regSPI_SHADER_USER_DATA_VS_7_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_8', + 'regSPI_SHADER_USER_DATA_VS_8_BASE_IDX', + 'regSPI_SHADER_USER_DATA_VS_9', + 'regSPI_SHADER_USER_DATA_VS_9_BASE_IDX', 'regSPI_SHADER_Z_FORMAT', + 'regSPI_SHADER_Z_FORMAT_BASE_IDX', 'regSPI_START_PHASE', + 'regSPI_START_PHASE_BASE_IDX', 'regSPI_SX_EXPORT_BUFFER_SIZES', + 'regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX', + 'regSPI_SX_SCOREBOARD_BUFFER_SIZES', + 'regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX', + 'regSPI_TMPRING_SIZE', 'regSPI_TMPRING_SIZE_BASE_IDX', + 'regSPI_UE_ERR_STATUS_HI', 'regSPI_UE_ERR_STATUS_HI_BASE_IDX', + 'regSPI_UE_ERR_STATUS_LO', 'regSPI_UE_ERR_STATUS_LO_BASE_IDX', + 'regSPI_VS_OUT_CONFIG', 'regSPI_VS_OUT_CONFIG_BASE_IDX', + 'regSPI_WAVE_LIMIT_CNTL', 'regSPI_WAVE_LIMIT_CNTL_BASE_IDX', + 'regSPI_WCL_PIPE_PERCENT_CS0', + 'regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX', + 'regSPI_WCL_PIPE_PERCENT_CS1', + 'regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX', + 'regSPI_WCL_PIPE_PERCENT_CS2', + 'regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX', + 'regSPI_WCL_PIPE_PERCENT_CS3', + 'regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX', + 'regSPI_WCL_PIPE_PERCENT_CS4', + 'regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX', + 'regSPI_WCL_PIPE_PERCENT_CS5', + 'regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX', + 'regSPI_WCL_PIPE_PERCENT_CS6', + 'regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX', + 'regSPI_WCL_PIPE_PERCENT_CS7', + 'regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX', + 'regSPI_WCL_PIPE_PERCENT_GFX', + 'regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX', + 'regSPI_WCL_PIPE_PERCENT_HP3D', + 'regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX', + 'regSPI_WF_LIFETIME_CNTL', 'regSPI_WF_LIFETIME_CNTL_BASE_IDX', + 'regSPI_WF_LIFETIME_DEBUG', 'regSPI_WF_LIFETIME_DEBUG_BASE_IDX', + 'regSPI_WF_LIFETIME_LIMIT_0', + 'regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX', + 'regSPI_WF_LIFETIME_LIMIT_1', + 'regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX', + 'regSPI_WF_LIFETIME_LIMIT_2', + 'regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX', + 'regSPI_WF_LIFETIME_LIMIT_3', + 'regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX', + 'regSPI_WF_LIFETIME_LIMIT_4', + 'regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX', + 'regSPI_WF_LIFETIME_LIMIT_5', + 'regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX', + 'regSPI_WF_LIFETIME_LIMIT_6', + 'regSPI_WF_LIFETIME_LIMIT_6_BASE_IDX', + 'regSPI_WF_LIFETIME_LIMIT_7', + 'regSPI_WF_LIFETIME_LIMIT_7_BASE_IDX', + 'regSPI_WF_LIFETIME_LIMIT_8', + 'regSPI_WF_LIFETIME_LIMIT_8_BASE_IDX', + 'regSPI_WF_LIFETIME_LIMIT_9', + 'regSPI_WF_LIFETIME_LIMIT_9_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_0', + 'regSPI_WF_LIFETIME_STATUS_0_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_1', 'regSPI_WF_LIFETIME_STATUS_10', + 'regSPI_WF_LIFETIME_STATUS_10_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_11', + 'regSPI_WF_LIFETIME_STATUS_11_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_12', + 'regSPI_WF_LIFETIME_STATUS_12_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_13', + 'regSPI_WF_LIFETIME_STATUS_13_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_14', + 'regSPI_WF_LIFETIME_STATUS_14_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_15', + 'regSPI_WF_LIFETIME_STATUS_15_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_16', + 'regSPI_WF_LIFETIME_STATUS_16_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_17', + 'regSPI_WF_LIFETIME_STATUS_17_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_18', + 'regSPI_WF_LIFETIME_STATUS_18_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_19', + 'regSPI_WF_LIFETIME_STATUS_19_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_1_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_2', 'regSPI_WF_LIFETIME_STATUS_20', + 'regSPI_WF_LIFETIME_STATUS_20_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_2_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_3', + 'regSPI_WF_LIFETIME_STATUS_3_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_4', + 'regSPI_WF_LIFETIME_STATUS_4_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_5', + 'regSPI_WF_LIFETIME_STATUS_5_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_6', + 'regSPI_WF_LIFETIME_STATUS_6_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_7', + 'regSPI_WF_LIFETIME_STATUS_7_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_8', + 'regSPI_WF_LIFETIME_STATUS_8_BASE_IDX', + 'regSPI_WF_LIFETIME_STATUS_9', + 'regSPI_WF_LIFETIME_STATUS_9_BASE_IDX', + 'regSP_MFMA_PORTD_RD_CONFIG', + 'regSP_MFMA_PORTD_RD_CONFIG_BASE_IDX', 'regSQC_CACHES', + 'regSQC_CACHES_BASE_IDX', 'regSQC_CE_EDC_HI', + 'regSQC_CE_EDC_HI_BASE_IDX', 'regSQC_CE_EDC_LO', + 'regSQC_CE_EDC_LO_BASE_IDX', 'regSQC_CONFIG', + 'regSQC_CONFIG_BASE_IDX', 'regSQC_DCACHE_UTCL1_CNTL1', + 'regSQC_DCACHE_UTCL1_CNTL1_BASE_IDX', 'regSQC_DCACHE_UTCL1_CNTL2', + 'regSQC_DCACHE_UTCL1_CNTL2_BASE_IDX', + 'regSQC_DCACHE_UTCL1_STATUS', + 'regSQC_DCACHE_UTCL1_STATUS_BASE_IDX', 'regSQC_DSM_CNTL', + 'regSQC_DSM_CNTL2', 'regSQC_DSM_CNTL2A', + 'regSQC_DSM_CNTL2A_BASE_IDX', 'regSQC_DSM_CNTL2B', + 'regSQC_DSM_CNTL2B_BASE_IDX', 'regSQC_DSM_CNTL2E', + 'regSQC_DSM_CNTL2E_BASE_IDX', 'regSQC_DSM_CNTL2_BASE_IDX', + 'regSQC_DSM_CNTLA', 'regSQC_DSM_CNTLA_BASE_IDX', + 'regSQC_DSM_CNTLB', 'regSQC_DSM_CNTLB_BASE_IDX', + 'regSQC_DSM_CNTL_BASE_IDX', 'regSQC_EDC_CNT', 'regSQC_EDC_CNT2', + 'regSQC_EDC_CNT2_BASE_IDX', 'regSQC_EDC_CNT3', + 'regSQC_EDC_CNT3_BASE_IDX', 'regSQC_EDC_CNT_BASE_IDX', + 'regSQC_EDC_FUE_CNTL', 'regSQC_EDC_FUE_CNTL_BASE_IDX', + 'regSQC_EDC_PARITY_CNT3', 'regSQC_EDC_PARITY_CNT3_BASE_IDX', + 'regSQC_ICACHE_UTCL1_CNTL1', 'regSQC_ICACHE_UTCL1_CNTL1_BASE_IDX', + 'regSQC_ICACHE_UTCL1_CNTL2', 'regSQC_ICACHE_UTCL1_CNTL2_BASE_IDX', + 'regSQC_ICACHE_UTCL1_STATUS', + 'regSQC_ICACHE_UTCL1_STATUS_BASE_IDX', 'regSQC_UE_EDC_HI', + 'regSQC_UE_EDC_HI_BASE_IDX', 'regSQC_UE_EDC_LO', + 'regSQC_UE_EDC_LO_BASE_IDX', 'regSQC_WRITEBACK', + 'regSQC_WRITEBACK_BASE_IDX', 'regSQ_ALU_CLK_CTRL', + 'regSQ_ALU_CLK_CTRL_BASE_IDX', 'regSQ_BUF_RSRC_WORD0', + 'regSQ_BUF_RSRC_WORD0_BASE_IDX', 'regSQ_BUF_RSRC_WORD1', + 'regSQ_BUF_RSRC_WORD1_BASE_IDX', 'regSQ_BUF_RSRC_WORD2', + 'regSQ_BUF_RSRC_WORD2_BASE_IDX', 'regSQ_BUF_RSRC_WORD3', + 'regSQ_BUF_RSRC_WORD3_BASE_IDX', 'regSQ_CE_ERR_STATUS_HI', + 'regSQ_CE_ERR_STATUS_HI_BASE_IDX', 'regSQ_CE_ERR_STATUS_LO', + 'regSQ_CE_ERR_STATUS_LO_BASE_IDX', 'regSQ_CGTS_CONFIG', + 'regSQ_CGTS_CONFIG_BASE_IDX', 'regSQ_CMD', 'regSQ_CMD_BASE_IDX', + 'regSQ_CMD_TIMESTAMP', 'regSQ_CMD_TIMESTAMP_BASE_IDX', + 'regSQ_CONFIG', 'regSQ_CONFIG1', 'regSQ_CONFIG1_BASE_IDX', + 'regSQ_CONFIG_BASE_IDX', 'regSQ_DEBUG', 'regSQ_DEBUG_BASE_IDX', + 'regSQ_DEBUG_FOR_INTERNAL_CTRL', + 'regSQ_DEBUG_FOR_INTERNAL_CTRL_BASE_IDX', + 'regSQ_DEBUG_PERFCOUNT_TRAP', + 'regSQ_DEBUG_PERFCOUNT_TRAP_BASE_IDX', 'regSQ_DEBUG_STS_GLOBAL', + 'regSQ_DEBUG_STS_GLOBAL2', 'regSQ_DEBUG_STS_GLOBAL2_BASE_IDX', + 'regSQ_DEBUG_STS_GLOBAL3', 'regSQ_DEBUG_STS_GLOBAL3_BASE_IDX', + 'regSQ_DEBUG_STS_GLOBAL_BASE_IDX', 'regSQ_DSM_CNTL', + 'regSQ_DSM_CNTL2', 'regSQ_DSM_CNTL2_BASE_IDX', + 'regSQ_DSM_CNTL_BASE_IDX', 'regSQ_DS_0', 'regSQ_DS_0_BASE_IDX', + 'regSQ_DS_1', 'regSQ_DS_1_BASE_IDX', 'regSQ_EDC_CNT', + 'regSQ_EDC_CNT_BASE_IDX', 'regSQ_EDC_DED_CNT', + 'regSQ_EDC_DED_CNT_BASE_IDX', 'regSQ_EDC_FUE_CNTL', + 'regSQ_EDC_FUE_CNTL_BASE_IDX', 'regSQ_EDC_INFO', + 'regSQ_EDC_INFO_BASE_IDX', 'regSQ_EDC_SEC_CNT', + 'regSQ_EDC_SEC_CNT_BASE_IDX', 'regSQ_EXP_0', + 'regSQ_EXP_0_BASE_IDX', 'regSQ_EXP_1', 'regSQ_EXP_1_BASE_IDX', + 'regSQ_FED_INTERRUPT_STATUS', + 'regSQ_FED_INTERRUPT_STATUS_BASE_IDX', 'regSQ_FIFO_SIZES', + 'regSQ_FIFO_SIZES_BASE_IDX', 'regSQ_FLAT_0', + 'regSQ_FLAT_0_BASE_IDX', 'regSQ_FLAT_1', 'regSQ_FLAT_1_BASE_IDX', + 'regSQ_FLAT_SCRATCH_WORD0', 'regSQ_FLAT_SCRATCH_WORD0_BASE_IDX', + 'regSQ_FLAT_SCRATCH_WORD1', 'regSQ_FLAT_SCRATCH_WORD1_BASE_IDX', + 'regSQ_GLBL_0', 'regSQ_GLBL_0_BASE_IDX', 'regSQ_GLBL_1', + 'regSQ_GLBL_1_BASE_IDX', 'regSQ_HOSTTRAP_STATUS', + 'regSQ_HOSTTRAP_STATUS_BASE_IDX', 'regSQ_IMG_RSRC_WORD0', + 'regSQ_IMG_RSRC_WORD0_BASE_IDX', 'regSQ_IMG_RSRC_WORD1', + 'regSQ_IMG_RSRC_WORD1_BASE_IDX', 'regSQ_IMG_RSRC_WORD2', + 'regSQ_IMG_RSRC_WORD2_BASE_IDX', 'regSQ_IMG_RSRC_WORD3', + 'regSQ_IMG_RSRC_WORD3_BASE_IDX', 'regSQ_IMG_RSRC_WORD4', + 'regSQ_IMG_RSRC_WORD4_BASE_IDX', 'regSQ_IMG_RSRC_WORD5', + 'regSQ_IMG_RSRC_WORD5_BASE_IDX', 'regSQ_IMG_RSRC_WORD6', + 'regSQ_IMG_RSRC_WORD6_BASE_IDX', 'regSQ_IMG_RSRC_WORD7', + 'regSQ_IMG_RSRC_WORD7_BASE_IDX', 'regSQ_IMG_SAMP_WORD0', + 'regSQ_IMG_SAMP_WORD0_BASE_IDX', 'regSQ_IMG_SAMP_WORD1', + 'regSQ_IMG_SAMP_WORD1_BASE_IDX', 'regSQ_IMG_SAMP_WORD2', + 'regSQ_IMG_SAMP_WORD2_BASE_IDX', 'regSQ_IMG_SAMP_WORD3', + 'regSQ_IMG_SAMP_WORD3_BASE_IDX', 'regSQ_IND_DATA', + 'regSQ_IND_DATA_BASE_IDX', 'regSQ_IND_INDEX', + 'regSQ_IND_INDEX_BASE_IDX', 'regSQ_INST', 'regSQ_INST_BASE_IDX', + 'regSQ_INTERRUPT_AUTO_MASK', 'regSQ_INTERRUPT_AUTO_MASK_BASE_IDX', + 'regSQ_INTERRUPT_MSG_CTRL', 'regSQ_INTERRUPT_MSG_CTRL_BASE_IDX', + 'regSQ_LB_CTR0_CU', 'regSQ_LB_CTR0_CU_BASE_IDX', + 'regSQ_LB_CTR1_CU', 'regSQ_LB_CTR1_CU_BASE_IDX', + 'regSQ_LB_CTR2_CU', 'regSQ_LB_CTR2_CU_BASE_IDX', + 'regSQ_LB_CTR3_CU', 'regSQ_LB_CTR3_CU_BASE_IDX', + 'regSQ_LB_CTR_CTRL', 'regSQ_LB_CTR_CTRL_BASE_IDX', + 'regSQ_LB_CTR_SEL', 'regSQ_LB_CTR_SEL_BASE_IDX', 'regSQ_LB_DATA0', + 'regSQ_LB_DATA0_BASE_IDX', 'regSQ_LB_DATA1', + 'regSQ_LB_DATA1_BASE_IDX', 'regSQ_LB_DATA2', + 'regSQ_LB_DATA2_BASE_IDX', 'regSQ_LB_DATA3', + 'regSQ_LB_DATA3_BASE_IDX', 'regSQ_LDS_CLK_CTRL', + 'regSQ_LDS_CLK_CTRL_BASE_IDX', 'regSQ_M0_GPR_IDX_WORD', + 'regSQ_M0_GPR_IDX_WORD_BASE_IDX', 'regSQ_MIMG_0', + 'regSQ_MIMG_0_BASE_IDX', 'regSQ_MIMG_1', 'regSQ_MIMG_1_BASE_IDX', + 'regSQ_MTBUF_0', 'regSQ_MTBUF_0_BASE_IDX', 'regSQ_MTBUF_1', + 'regSQ_MTBUF_1_BASE_IDX', 'regSQ_MUBUF_0', + 'regSQ_MUBUF_0_BASE_IDX', 'regSQ_MUBUF_1', + 'regSQ_MUBUF_1_BASE_IDX', 'regSQ_PERFCOUNTER0_HI', + 'regSQ_PERFCOUNTER0_HI_BASE_IDX', 'regSQ_PERFCOUNTER0_LO', + 'regSQ_PERFCOUNTER0_LO_BASE_IDX', 'regSQ_PERFCOUNTER0_SELECT', + 'regSQ_PERFCOUNTER0_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER10_HI', + 'regSQ_PERFCOUNTER10_HI_BASE_IDX', 'regSQ_PERFCOUNTER10_LO', + 'regSQ_PERFCOUNTER10_LO_BASE_IDX', 'regSQ_PERFCOUNTER10_SELECT', + 'regSQ_PERFCOUNTER10_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER11_HI', + 'regSQ_PERFCOUNTER11_HI_BASE_IDX', 'regSQ_PERFCOUNTER11_LO', + 'regSQ_PERFCOUNTER11_LO_BASE_IDX', 'regSQ_PERFCOUNTER11_SELECT', + 'regSQ_PERFCOUNTER11_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER12_HI', + 'regSQ_PERFCOUNTER12_HI_BASE_IDX', 'regSQ_PERFCOUNTER12_LO', + 'regSQ_PERFCOUNTER12_LO_BASE_IDX', 'regSQ_PERFCOUNTER12_SELECT', + 'regSQ_PERFCOUNTER12_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER13_HI', + 'regSQ_PERFCOUNTER13_HI_BASE_IDX', 'regSQ_PERFCOUNTER13_LO', + 'regSQ_PERFCOUNTER13_LO_BASE_IDX', 'regSQ_PERFCOUNTER13_SELECT', + 'regSQ_PERFCOUNTER13_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER14_HI', + 'regSQ_PERFCOUNTER14_HI_BASE_IDX', 'regSQ_PERFCOUNTER14_LO', + 'regSQ_PERFCOUNTER14_LO_BASE_IDX', 'regSQ_PERFCOUNTER14_SELECT', + 'regSQ_PERFCOUNTER14_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER15_HI', + 'regSQ_PERFCOUNTER15_HI_BASE_IDX', 'regSQ_PERFCOUNTER15_LO', + 'regSQ_PERFCOUNTER15_LO_BASE_IDX', 'regSQ_PERFCOUNTER15_SELECT', + 'regSQ_PERFCOUNTER15_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER1_HI', + 'regSQ_PERFCOUNTER1_HI_BASE_IDX', 'regSQ_PERFCOUNTER1_LO', + 'regSQ_PERFCOUNTER1_LO_BASE_IDX', 'regSQ_PERFCOUNTER1_SELECT', + 'regSQ_PERFCOUNTER1_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER2_HI', + 'regSQ_PERFCOUNTER2_HI_BASE_IDX', 'regSQ_PERFCOUNTER2_LO', + 'regSQ_PERFCOUNTER2_LO_BASE_IDX', 'regSQ_PERFCOUNTER2_SELECT', + 'regSQ_PERFCOUNTER2_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER3_HI', + 'regSQ_PERFCOUNTER3_HI_BASE_IDX', 'regSQ_PERFCOUNTER3_LO', + 'regSQ_PERFCOUNTER3_LO_BASE_IDX', 'regSQ_PERFCOUNTER3_SELECT', + 'regSQ_PERFCOUNTER3_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER4_HI', + 'regSQ_PERFCOUNTER4_HI_BASE_IDX', 'regSQ_PERFCOUNTER4_LO', + 'regSQ_PERFCOUNTER4_LO_BASE_IDX', 'regSQ_PERFCOUNTER4_SELECT', + 'regSQ_PERFCOUNTER4_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER5_HI', + 'regSQ_PERFCOUNTER5_HI_BASE_IDX', 'regSQ_PERFCOUNTER5_LO', + 'regSQ_PERFCOUNTER5_LO_BASE_IDX', 'regSQ_PERFCOUNTER5_SELECT', + 'regSQ_PERFCOUNTER5_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER6_HI', + 'regSQ_PERFCOUNTER6_HI_BASE_IDX', 'regSQ_PERFCOUNTER6_LO', + 'regSQ_PERFCOUNTER6_LO_BASE_IDX', 'regSQ_PERFCOUNTER6_SELECT', + 'regSQ_PERFCOUNTER6_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER7_HI', + 'regSQ_PERFCOUNTER7_HI_BASE_IDX', 'regSQ_PERFCOUNTER7_LO', + 'regSQ_PERFCOUNTER7_LO_BASE_IDX', 'regSQ_PERFCOUNTER7_SELECT', + 'regSQ_PERFCOUNTER7_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER8_HI', + 'regSQ_PERFCOUNTER8_HI_BASE_IDX', 'regSQ_PERFCOUNTER8_LO', + 'regSQ_PERFCOUNTER8_LO_BASE_IDX', 'regSQ_PERFCOUNTER8_SELECT', + 'regSQ_PERFCOUNTER8_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER9_HI', + 'regSQ_PERFCOUNTER9_HI_BASE_IDX', 'regSQ_PERFCOUNTER9_LO', + 'regSQ_PERFCOUNTER9_LO_BASE_IDX', 'regSQ_PERFCOUNTER9_SELECT', + 'regSQ_PERFCOUNTER9_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER_CTRL', + 'regSQ_PERFCOUNTER_CTRL2', 'regSQ_PERFCOUNTER_CTRL2_BASE_IDX', + 'regSQ_PERFCOUNTER_CTRL_BASE_IDX', 'regSQ_PERFCOUNTER_MASK', + 'regSQ_PERFCOUNTER_MASK_BASE_IDX', 'regSQ_PERF_SNAPSHOT_CTRL', + 'regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX', 'regSQ_POWER_THROTTLE', + 'regSQ_POWER_THROTTLE2', 'regSQ_POWER_THROTTLE2_BASE_IDX', + 'regSQ_POWER_THROTTLE_BASE_IDX', 'regSQ_RANDOM_WAVE_PRI', + 'regSQ_RANDOM_WAVE_PRI_BASE_IDX', 'regSQ_REG_CREDITS', + 'regSQ_REG_CREDITS_BASE_IDX', 'regSQ_REG_TIMESTAMP', + 'regSQ_REG_TIMESTAMP_BASE_IDX', 'regSQ_RUNTIME_CONFIG', + 'regSQ_RUNTIME_CONFIG_BASE_IDX', 'regSQ_SCRATCH_0', + 'regSQ_SCRATCH_0_BASE_IDX', 'regSQ_SCRATCH_1', + 'regSQ_SCRATCH_1_BASE_IDX', 'regSQ_SHADER_TBA_HI', + 'regSQ_SHADER_TBA_HI_BASE_IDX', 'regSQ_SHADER_TBA_LO', + 'regSQ_SHADER_TBA_LO_BASE_IDX', 'regSQ_SHADER_TMA_HI', + 'regSQ_SHADER_TMA_HI_BASE_IDX', 'regSQ_SHADER_TMA_LO', + 'regSQ_SHADER_TMA_LO_BASE_IDX', 'regSQ_SMEM_0', + 'regSQ_SMEM_0_BASE_IDX', 'regSQ_SMEM_1', 'regSQ_SMEM_1_BASE_IDX', + 'regSQ_SOP1', 'regSQ_SOP1_BASE_IDX', 'regSQ_SOP2', + 'regSQ_SOP2_BASE_IDX', 'regSQ_SOPC', 'regSQ_SOPC_BASE_IDX', + 'regSQ_SOPK', 'regSQ_SOPK_BASE_IDX', 'regSQ_SOPP', + 'regSQ_SOPP_BASE_IDX', 'regSQ_TEX_CLK_CTRL', + 'regSQ_TEX_CLK_CTRL_BASE_IDX', 'regSQ_THREAD_TRACE_BASE', + 'regSQ_THREAD_TRACE_BASE2', 'regSQ_THREAD_TRACE_BASE2_BASE_IDX', + 'regSQ_THREAD_TRACE_BASE_BASE_IDX', 'regSQ_THREAD_TRACE_CNTR', + 'regSQ_THREAD_TRACE_CNTR_BASE_IDX', 'regSQ_THREAD_TRACE_CTRL', + 'regSQ_THREAD_TRACE_CTRL_BASE_IDX', 'regSQ_THREAD_TRACE_HIWATER', + 'regSQ_THREAD_TRACE_HIWATER_BASE_IDX', 'regSQ_THREAD_TRACE_MASK', + 'regSQ_THREAD_TRACE_MASK_BASE_IDX', 'regSQ_THREAD_TRACE_MODE', + 'regSQ_THREAD_TRACE_MODE_BASE_IDX', + 'regSQ_THREAD_TRACE_PERF_MASK', + 'regSQ_THREAD_TRACE_PERF_MASK_BASE_IDX', + 'regSQ_THREAD_TRACE_SIZE', 'regSQ_THREAD_TRACE_SIZE_BASE_IDX', + 'regSQ_THREAD_TRACE_STATUS', 'regSQ_THREAD_TRACE_STATUS_BASE_IDX', + 'regSQ_THREAD_TRACE_TOKEN_MASK', 'regSQ_THREAD_TRACE_TOKEN_MASK2', + 'regSQ_THREAD_TRACE_TOKEN_MASK2_BASE_IDX', + 'regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX', + 'regSQ_THREAD_TRACE_USERDATA_0', + 'regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX', + 'regSQ_THREAD_TRACE_USERDATA_1', + 'regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX', + 'regSQ_THREAD_TRACE_USERDATA_2', + 'regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX', + 'regSQ_THREAD_TRACE_USERDATA_3', + 'regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX', + 'regSQ_THREAD_TRACE_WORD_CMN', + 'regSQ_THREAD_TRACE_WORD_CMN_BASE_IDX', + 'regSQ_THREAD_TRACE_WORD_EVENT', + 'regSQ_THREAD_TRACE_WORD_EVENT_BASE_IDX', + 'regSQ_THREAD_TRACE_WORD_INST', + 'regSQ_THREAD_TRACE_WORD_INST_BASE_IDX', + 'regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2', + 'regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_BASE_IDX', + 'regSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2', + 'regSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_BASE_IDX', + 'regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2', + 'regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_BASE_IDX', + 'regSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2', + 'regSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_BASE_IDX', + 'regSQ_THREAD_TRACE_WORD_ISSUE', + 'regSQ_THREAD_TRACE_WORD_ISSUE_BASE_IDX', + 'regSQ_THREAD_TRACE_WORD_MISC', + 'regSQ_THREAD_TRACE_WORD_MISC_BASE_IDX', + 'regSQ_THREAD_TRACE_WORD_PERF_1_OF_2', + 'regSQ_THREAD_TRACE_WORD_PERF_1_OF_2_BASE_IDX', + 'regSQ_THREAD_TRACE_WORD_PERF_2_OF_2', + 'regSQ_THREAD_TRACE_WORD_PERF_2_OF_2_BASE_IDX', + 'regSQ_THREAD_TRACE_WORD_REG_1_OF_2', + 'regSQ_THREAD_TRACE_WORD_REG_1_OF_2_BASE_IDX', + 'regSQ_THREAD_TRACE_WORD_REG_2_OF_2', + 'regSQ_THREAD_TRACE_WORD_REG_2_OF_2_BASE_IDX', + 'regSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2', + 'regSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_BASE_IDX', + 'regSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2', + 'regSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_BASE_IDX', + 'regSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2', + 'regSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_BASE_IDX', + 'regSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2', + 'regSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_BASE_IDX', + 'regSQ_THREAD_TRACE_WORD_WAVE', + 'regSQ_THREAD_TRACE_WORD_WAVE_BASE_IDX', + 'regSQ_THREAD_TRACE_WORD_WAVE_START', + 'regSQ_THREAD_TRACE_WORD_WAVE_START_BASE_IDX', + 'regSQ_THREAD_TRACE_WPTR', 'regSQ_THREAD_TRACE_WPTR_BASE_IDX', + 'regSQ_TIMEOUT_CONFIG', 'regSQ_TIMEOUT_CONFIG_BASE_IDX', + 'regSQ_TIMEOUT_STATUS', 'regSQ_TIMEOUT_STATUS_BASE_IDX', + 'regSQ_TIME_HI', 'regSQ_TIME_HI_BASE_IDX', 'regSQ_TIME_LO', + 'regSQ_TIME_LO_BASE_IDX', 'regSQ_UE_ERR_STATUS_HI', + 'regSQ_UE_ERR_STATUS_HI_BASE_IDX', 'regSQ_UE_ERR_STATUS_LO', + 'regSQ_UE_ERR_STATUS_LO_BASE_IDX', 'regSQ_UTCL1_CNTL1', + 'regSQ_UTCL1_CNTL1_BASE_IDX', 'regSQ_UTCL1_CNTL2', + 'regSQ_UTCL1_CNTL2_BASE_IDX', 'regSQ_UTCL1_STATUS', + 'regSQ_UTCL1_STATUS_BASE_IDX', 'regSQ_VINTRP', + 'regSQ_VINTRP_BASE_IDX', 'regSQ_VOP1', 'regSQ_VOP1_BASE_IDX', + 'regSQ_VOP2', 'regSQ_VOP2_BASE_IDX', 'regSQ_VOP3P_0', + 'regSQ_VOP3P_0_BASE_IDX', 'regSQ_VOP3P_1', + 'regSQ_VOP3P_1_BASE_IDX', 'regSQ_VOP3P_MFMA_0', + 'regSQ_VOP3P_MFMA_0_BASE_IDX', 'regSQ_VOP3P_MFMA_1', + 'regSQ_VOP3P_MFMA_1_BASE_IDX', 'regSQ_VOP3_0', + 'regSQ_VOP3_0_BASE_IDX', 'regSQ_VOP3_0_SDST_ENC', + 'regSQ_VOP3_0_SDST_ENC_BASE_IDX', 'regSQ_VOP3_1', + 'regSQ_VOP3_1_BASE_IDX', 'regSQ_VOPC', 'regSQ_VOPC_BASE_IDX', + 'regSQ_VOP_DPP', 'regSQ_VOP_DPP_BASE_IDX', 'regSQ_VOP_SDWA', + 'regSQ_VOP_SDWA_BASE_IDX', 'regSQ_VOP_SDWA_SDST_ENC', + 'regSQ_VOP_SDWA_SDST_ENC_BASE_IDX', 'regSQ_WREXEC_EXEC_HI', + 'regSQ_WREXEC_EXEC_HI_BASE_IDX', 'regSQ_WREXEC_EXEC_LO', + 'regSQ_WREXEC_EXEC_LO_BASE_IDX', 'regSX_DEBUG_1', + 'regSX_DEBUG_1_BASE_IDX', 'regSX_DEBUG_BUSY', + 'regSX_DEBUG_BUSY_BASE_IDX', 'regSX_PERFCOUNTER0_HI', + 'regSX_PERFCOUNTER0_HI_BASE_IDX', 'regSX_PERFCOUNTER0_LO', + 'regSX_PERFCOUNTER0_LO_BASE_IDX', 'regSX_PERFCOUNTER0_SELECT', + 'regSX_PERFCOUNTER0_SELECT1', + 'regSX_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regSX_PERFCOUNTER0_SELECT_BASE_IDX', 'regSX_PERFCOUNTER1_HI', + 'regSX_PERFCOUNTER1_HI_BASE_IDX', 'regSX_PERFCOUNTER1_LO', + 'regSX_PERFCOUNTER1_LO_BASE_IDX', 'regSX_PERFCOUNTER1_SELECT', + 'regSX_PERFCOUNTER1_SELECT1', + 'regSX_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regSX_PERFCOUNTER1_SELECT_BASE_IDX', 'regSX_PERFCOUNTER2_HI', + 'regSX_PERFCOUNTER2_HI_BASE_IDX', 'regSX_PERFCOUNTER2_LO', + 'regSX_PERFCOUNTER2_LO_BASE_IDX', 'regSX_PERFCOUNTER2_SELECT', + 'regSX_PERFCOUNTER2_SELECT_BASE_IDX', 'regSX_PERFCOUNTER3_HI', + 'regSX_PERFCOUNTER3_HI_BASE_IDX', 'regSX_PERFCOUNTER3_LO', + 'regSX_PERFCOUNTER3_LO_BASE_IDX', 'regSX_PERFCOUNTER3_SELECT', + 'regSX_PERFCOUNTER3_SELECT_BASE_IDX', 'regTA_CE_EDC_HI', + 'regTA_CE_EDC_HI_BASE_IDX', 'regTA_CE_EDC_LO', + 'regTA_CE_EDC_LO_BASE_IDX', 'regTA_CGTT_CTRL', + 'regTA_CGTT_CTRL_BASE_IDX', 'regTA_CNTL', 'regTA_CNTL_AUX', + 'regTA_CNTL_AUX_BASE_IDX', 'regTA_CNTL_BASE_IDX', + 'regTA_DSM_CNTL', 'regTA_DSM_CNTL2', 'regTA_DSM_CNTL2_BASE_IDX', + 'regTA_DSM_CNTL_BASE_IDX', 'regTA_FEATURE_CNTL', + 'regTA_FEATURE_CNTL_BASE_IDX', 'regTA_PERFCOUNTER0_HI', + 'regTA_PERFCOUNTER0_HI_BASE_IDX', 'regTA_PERFCOUNTER0_LO', + 'regTA_PERFCOUNTER0_LO_BASE_IDX', 'regTA_PERFCOUNTER0_SELECT', + 'regTA_PERFCOUNTER0_SELECT1', + 'regTA_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regTA_PERFCOUNTER0_SELECT_BASE_IDX', 'regTA_PERFCOUNTER1_HI', + 'regTA_PERFCOUNTER1_HI_BASE_IDX', 'regTA_PERFCOUNTER1_LO', + 'regTA_PERFCOUNTER1_LO_BASE_IDX', 'regTA_PERFCOUNTER1_SELECT', + 'regTA_PERFCOUNTER1_SELECT_BASE_IDX', 'regTA_POWER_CNTL', + 'regTA_POWER_CNTL_BASE_IDX', 'regTA_SCRATCH', + 'regTA_SCRATCH_BASE_IDX', 'regTA_STATUS', 'regTA_STATUS_BASE_IDX', + 'regTA_UE_EDC_HI', 'regTA_UE_EDC_HI_BASE_IDX', 'regTA_UE_EDC_LO', + 'regTA_UE_EDC_LO_BASE_IDX', 'regTCA_BURST_CTRL', + 'regTCA_BURST_CTRL_BASE_IDX', 'regTCA_BURST_MASK', + 'regTCA_BURST_MASK_BASE_IDX', 'regTCA_CGTT_SCLK_CTRL', + 'regTCA_CGTT_SCLK_CTRL_BASE_IDX', 'regTCA_CTRL', + 'regTCA_CTRL_BASE_IDX', 'regTCA_DSM_CNTL', 'regTCA_DSM_CNTL2', + 'regTCA_DSM_CNTL2_BASE_IDX', 'regTCA_DSM_CNTL_BASE_IDX', + 'regTCA_PERFCOUNTER0_HI', 'regTCA_PERFCOUNTER0_HI_BASE_IDX', + 'regTCA_PERFCOUNTER0_LO', 'regTCA_PERFCOUNTER0_LO_BASE_IDX', + 'regTCA_PERFCOUNTER0_SELECT', 'regTCA_PERFCOUNTER0_SELECT1', + 'regTCA_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regTCA_PERFCOUNTER0_SELECT_BASE_IDX', 'regTCA_PERFCOUNTER1_HI', + 'regTCA_PERFCOUNTER1_HI_BASE_IDX', 'regTCA_PERFCOUNTER1_LO', + 'regTCA_PERFCOUNTER1_LO_BASE_IDX', 'regTCA_PERFCOUNTER1_SELECT', + 'regTCA_PERFCOUNTER1_SELECT1', + 'regTCA_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regTCA_PERFCOUNTER1_SELECT_BASE_IDX', 'regTCA_PERFCOUNTER2_HI', + 'regTCA_PERFCOUNTER2_HI_BASE_IDX', 'regTCA_PERFCOUNTER2_LO', + 'regTCA_PERFCOUNTER2_LO_BASE_IDX', 'regTCA_PERFCOUNTER2_SELECT', + 'regTCA_PERFCOUNTER2_SELECT_BASE_IDX', 'regTCA_PERFCOUNTER3_HI', + 'regTCA_PERFCOUNTER3_HI_BASE_IDX', 'regTCA_PERFCOUNTER3_LO', + 'regTCA_PERFCOUNTER3_LO_BASE_IDX', 'regTCA_PERFCOUNTER3_SELECT', + 'regTCA_PERFCOUNTER3_SELECT_BASE_IDX', 'regTCA_UE_ERR_STATUS_HI', + 'regTCA_UE_ERR_STATUS_HI_BASE_IDX', 'regTCA_UE_ERR_STATUS_LO', + 'regTCA_UE_ERR_STATUS_LO_BASE_IDX', 'regTCC_CE_ERR_STATUS_HI', + 'regTCC_CE_ERR_STATUS_HI_BASE_IDX', 'regTCC_CE_ERR_STATUS_LO', + 'regTCC_CE_ERR_STATUS_LO_BASE_IDX', 'regTCC_CGTT_SCLK_CTRL', + 'regTCC_CGTT_SCLK_CTRL2', 'regTCC_CGTT_SCLK_CTRL2_BASE_IDX', + 'regTCC_CGTT_SCLK_CTRL3', 'regTCC_CGTT_SCLK_CTRL3_BASE_IDX', + 'regTCC_CGTT_SCLK_CTRL_BASE_IDX', 'regTCC_CTRL', 'regTCC_CTRL2', + 'regTCC_CTRL2_BASE_IDX', 'regTCC_CTRL_BASE_IDX', + 'regTCC_DSM_CNTL', 'regTCC_DSM_CNTL2', 'regTCC_DSM_CNTL2A', + 'regTCC_DSM_CNTL2A_BASE_IDX', 'regTCC_DSM_CNTL2B', + 'regTCC_DSM_CNTL2B_BASE_IDX', 'regTCC_DSM_CNTL2_BASE_IDX', + 'regTCC_DSM_CNTL3', 'regTCC_DSM_CNTL3_BASE_IDX', + 'regTCC_DSM_CNTLA', 'regTCC_DSM_CNTLA_BASE_IDX', + 'regTCC_DSM_CNTL_BASE_IDX', 'regTCC_PERFCOUNTER0_HI', + 'regTCC_PERFCOUNTER0_HI_BASE_IDX', 'regTCC_PERFCOUNTER0_LO', + 'regTCC_PERFCOUNTER0_LO_BASE_IDX', 'regTCC_PERFCOUNTER0_SELECT', + 'regTCC_PERFCOUNTER0_SELECT1', + 'regTCC_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regTCC_PERFCOUNTER0_SELECT_BASE_IDX', 'regTCC_PERFCOUNTER1_HI', + 'regTCC_PERFCOUNTER1_HI_BASE_IDX', 'regTCC_PERFCOUNTER1_LO', + 'regTCC_PERFCOUNTER1_LO_BASE_IDX', 'regTCC_PERFCOUNTER1_SELECT', + 'regTCC_PERFCOUNTER1_SELECT1', + 'regTCC_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regTCC_PERFCOUNTER1_SELECT_BASE_IDX', 'regTCC_PERFCOUNTER2_HI', + 'regTCC_PERFCOUNTER2_HI_BASE_IDX', 'regTCC_PERFCOUNTER2_LO', + 'regTCC_PERFCOUNTER2_LO_BASE_IDX', 'regTCC_PERFCOUNTER2_SELECT', + 'regTCC_PERFCOUNTER2_SELECT_BASE_IDX', 'regTCC_PERFCOUNTER3_HI', + 'regTCC_PERFCOUNTER3_HI_BASE_IDX', 'regTCC_PERFCOUNTER3_LO', + 'regTCC_PERFCOUNTER3_LO_BASE_IDX', 'regTCC_PERFCOUNTER3_SELECT', + 'regTCC_PERFCOUNTER3_SELECT_BASE_IDX', 'regTCC_SOFT_RESET', + 'regTCC_SOFT_RESET_BASE_IDX', 'regTCC_UE_ERR_STATUS_HI', + 'regTCC_UE_ERR_STATUS_HI_BASE_IDX', 'regTCC_UE_ERR_STATUS_LO', + 'regTCC_UE_ERR_STATUS_LO_BASE_IDX', 'regTCC_WBINVL2', + 'regTCC_WBINVL2_BASE_IDX', 'regTCI_CE_EDC_HI_REG', + 'regTCI_CE_EDC_HI_REG_BASE_IDX', 'regTCI_CE_EDC_LO_REG', + 'regTCI_CE_EDC_LO_REG_BASE_IDX', 'regTCI_CNTL_1', + 'regTCI_CNTL_1_BASE_IDX', 'regTCI_CNTL_2', + 'regTCI_CNTL_2_BASE_IDX', 'regTCI_CNTL_3', + 'regTCI_CNTL_3_BASE_IDX', 'regTCI_DSM_CNTL', 'regTCI_DSM_CNTL2', + 'regTCI_DSM_CNTL2_BASE_IDX', 'regTCI_DSM_CNTL_BASE_IDX', + 'regTCI_MISC', 'regTCI_MISC_BASE_IDX', 'regTCI_STATUS', + 'regTCI_STATUS_BASE_IDX', 'regTCI_UE_EDC_HI_REG', + 'regTCI_UE_EDC_HI_REG_BASE_IDX', 'regTCI_UE_EDC_LO_REG', + 'regTCI_UE_EDC_LO_REG_BASE_IDX', 'regTCP_ADDR_CONFIG', + 'regTCP_ADDR_CONFIG_BASE_IDX', 'regTCP_ATC_EDC_GATCL1_CNT', + 'regTCP_ATC_EDC_GATCL1_CNT_BASE_IDX', + 'regTCP_BUFFER_ADDR_HASH_CNTL', + 'regTCP_BUFFER_ADDR_HASH_CNTL_BASE_IDX', 'regTCP_CE_EDC_HI_REG', + 'regTCP_CE_EDC_HI_REG_BASE_IDX', 'regTCP_CE_EDC_LO_REG', + 'regTCP_CE_EDC_LO_REG_BASE_IDX', 'regTCP_CHAN_STEER_0', + 'regTCP_CHAN_STEER_0_BASE_IDX', 'regTCP_CHAN_STEER_1', + 'regTCP_CHAN_STEER_1_BASE_IDX', 'regTCP_CNTL', 'regTCP_CNTL2', + 'regTCP_CNTL2_BASE_IDX', 'regTCP_CNTL_BASE_IDX', 'regTCP_CREDIT', + 'regTCP_CREDIT_BASE_IDX', 'regTCP_DSM_CNTL', 'regTCP_DSM_CNTL2', + 'regTCP_DSM_CNTL2_BASE_IDX', 'regTCP_DSM_CNTL_BASE_IDX', + 'regTCP_GATCL1_CNTL', 'regTCP_GATCL1_CNTL_BASE_IDX', + 'regTCP_GATCL1_DSM_CNTL', 'regTCP_GATCL1_DSM_CNTL_BASE_IDX', + 'regTCP_INVALIDATE', 'regTCP_INVALIDATE_BASE_IDX', + 'regTCP_PERFCOUNTER0_HI', 'regTCP_PERFCOUNTER0_HI_BASE_IDX', + 'regTCP_PERFCOUNTER0_LO', 'regTCP_PERFCOUNTER0_LO_BASE_IDX', + 'regTCP_PERFCOUNTER0_SELECT', 'regTCP_PERFCOUNTER0_SELECT1', + 'regTCP_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regTCP_PERFCOUNTER0_SELECT_BASE_IDX', 'regTCP_PERFCOUNTER1_HI', + 'regTCP_PERFCOUNTER1_HI_BASE_IDX', 'regTCP_PERFCOUNTER1_LO', + 'regTCP_PERFCOUNTER1_LO_BASE_IDX', 'regTCP_PERFCOUNTER1_SELECT', + 'regTCP_PERFCOUNTER1_SELECT1', + 'regTCP_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regTCP_PERFCOUNTER1_SELECT_BASE_IDX', 'regTCP_PERFCOUNTER2_HI', + 'regTCP_PERFCOUNTER2_HI_BASE_IDX', 'regTCP_PERFCOUNTER2_LO', + 'regTCP_PERFCOUNTER2_LO_BASE_IDX', 'regTCP_PERFCOUNTER2_SELECT', + 'regTCP_PERFCOUNTER2_SELECT_BASE_IDX', 'regTCP_PERFCOUNTER3_HI', + 'regTCP_PERFCOUNTER3_HI_BASE_IDX', 'regTCP_PERFCOUNTER3_LO', + 'regTCP_PERFCOUNTER3_LO_BASE_IDX', 'regTCP_PERFCOUNTER3_SELECT', + 'regTCP_PERFCOUNTER3_SELECT_BASE_IDX', + 'regTCP_PERFCOUNTER_FILTER', 'regTCP_PERFCOUNTER_FILTER_BASE_IDX', + 'regTCP_PERFCOUNTER_FILTER_EN', + 'regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX', 'regTCP_STATUS', + 'regTCP_STATUS_BASE_IDX', 'regTCP_UE_EDC_HI_REG', + 'regTCP_UE_EDC_HI_REG_BASE_IDX', 'regTCP_UE_EDC_LO_REG', + 'regTCP_UE_EDC_LO_REG_BASE_IDX', 'regTCP_UTCL1_CNTL1', + 'regTCP_UTCL1_CNTL1_BASE_IDX', 'regTCP_UTCL1_CNTL2', + 'regTCP_UTCL1_CNTL2_BASE_IDX', 'regTCP_UTCL1_STATUS', + 'regTCP_UTCL1_STATUS_BASE_IDX', 'regTCP_WATCH0_ADDR_H', + 'regTCP_WATCH0_ADDR_H_BASE_IDX', 'regTCP_WATCH0_ADDR_L', + 'regTCP_WATCH0_ADDR_L_BASE_IDX', 'regTCP_WATCH0_CNTL', + 'regTCP_WATCH0_CNTL_BASE_IDX', 'regTCP_WATCH1_ADDR_H', + 'regTCP_WATCH1_ADDR_H_BASE_IDX', 'regTCP_WATCH1_ADDR_L', + 'regTCP_WATCH1_ADDR_L_BASE_IDX', 'regTCP_WATCH1_CNTL', + 'regTCP_WATCH1_CNTL_BASE_IDX', 'regTCP_WATCH2_ADDR_H', + 'regTCP_WATCH2_ADDR_H_BASE_IDX', 'regTCP_WATCH2_ADDR_L', + 'regTCP_WATCH2_ADDR_L_BASE_IDX', 'regTCP_WATCH2_CNTL', + 'regTCP_WATCH2_CNTL_BASE_IDX', 'regTCP_WATCH3_ADDR_H', + 'regTCP_WATCH3_ADDR_H_BASE_IDX', 'regTCP_WATCH3_ADDR_L', + 'regTCP_WATCH3_ADDR_L_BASE_IDX', 'regTCP_WATCH3_CNTL', + 'regTCP_WATCH3_CNTL_BASE_IDX', 'regTCX_CE_ERR_STATUS_HI', + 'regTCX_CE_ERR_STATUS_HI_BASE_IDX', 'regTCX_CE_ERR_STATUS_LO', + 'regTCX_CE_ERR_STATUS_LO_BASE_IDX', 'regTCX_CGTT_SCLK_CTRL', + 'regTCX_CGTT_SCLK_CTRL_BASE_IDX', 'regTCX_CTRL', + 'regTCX_CTRL_BASE_IDX', 'regTCX_DSM_CNTL', 'regTCX_DSM_CNTL2', + 'regTCX_DSM_CNTL2_BASE_IDX', 'regTCX_DSM_CNTL_BASE_IDX', + 'regTCX_UE_ERR_STATUS_HI', 'regTCX_UE_ERR_STATUS_HI_BASE_IDX', + 'regTCX_UE_ERR_STATUS_LO', 'regTCX_UE_ERR_STATUS_LO_BASE_IDX', + 'regTC_CFG_L1_LOAD_POLICY0', 'regTC_CFG_L1_LOAD_POLICY0_BASE_IDX', + 'regTC_CFG_L1_LOAD_POLICY1', 'regTC_CFG_L1_LOAD_POLICY1_BASE_IDX', + 'regTC_CFG_L1_STORE_POLICY', 'regTC_CFG_L1_STORE_POLICY_BASE_IDX', + 'regTC_CFG_L1_VOLATILE', 'regTC_CFG_L1_VOLATILE_BASE_IDX', + 'regTC_CFG_L2_ATOMIC_POLICY', + 'regTC_CFG_L2_ATOMIC_POLICY_BASE_IDX', + 'regTC_CFG_L2_LOAD_POLICY0', 'regTC_CFG_L2_LOAD_POLICY0_BASE_IDX', + 'regTC_CFG_L2_LOAD_POLICY1', 'regTC_CFG_L2_LOAD_POLICY1_BASE_IDX', + 'regTC_CFG_L2_STORE_POLICY0', + 'regTC_CFG_L2_STORE_POLICY0_BASE_IDX', + 'regTC_CFG_L2_STORE_POLICY1', + 'regTC_CFG_L2_STORE_POLICY1_BASE_IDX', 'regTC_CFG_L2_VOLATILE', + 'regTC_CFG_L2_VOLATILE_BASE_IDX', 'regTD_CE_EDC_HI', + 'regTD_CE_EDC_HI_BASE_IDX', 'regTD_CE_EDC_LO', + 'regTD_CE_EDC_LO_BASE_IDX', 'regTD_CGTT_CTRL', + 'regTD_CGTT_CTRL_BASE_IDX', 'regTD_CNTL', 'regTD_CNTL_BASE_IDX', + 'regTD_DSM_CNTL', 'regTD_DSM_CNTL2', 'regTD_DSM_CNTL2_BASE_IDX', + 'regTD_DSM_CNTL_BASE_IDX', 'regTD_PERFCOUNTER0_HI', + 'regTD_PERFCOUNTER0_HI_BASE_IDX', 'regTD_PERFCOUNTER0_LO', + 'regTD_PERFCOUNTER0_LO_BASE_IDX', 'regTD_PERFCOUNTER0_SELECT', + 'regTD_PERFCOUNTER0_SELECT1', + 'regTD_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regTD_PERFCOUNTER0_SELECT_BASE_IDX', 'regTD_PERFCOUNTER1_HI', + 'regTD_PERFCOUNTER1_HI_BASE_IDX', 'regTD_PERFCOUNTER1_LO', + 'regTD_PERFCOUNTER1_LO_BASE_IDX', 'regTD_PERFCOUNTER1_SELECT', + 'regTD_PERFCOUNTER1_SELECT_BASE_IDX', 'regTD_POWER_CNTL', + 'regTD_POWER_CNTL_BASE_IDX', 'regTD_SCRATCH', + 'regTD_SCRATCH_BASE_IDX', 'regTD_STATUS', 'regTD_STATUS_BASE_IDX', + 'regTD_UE_EDC_HI', 'regTD_UE_EDC_HI_BASE_IDX', 'regTD_UE_EDC_LO', + 'regTD_UE_EDC_LO_BASE_IDX', 'regUTCL2_CE_ERR_STATUS_HI', + 'regUTCL2_CE_ERR_STATUS_HI_BASE_IDX', 'regUTCL2_CE_ERR_STATUS_LO', + 'regUTCL2_CE_ERR_STATUS_LO_BASE_IDX', 'regUTCL2_CGTT_CLK_CTRL', + 'regUTCL2_CGTT_CLK_CTRL_BASE_IDX', 'regUTCL2_EDC_CONFIG', + 'regUTCL2_EDC_CONFIG_BASE_IDX', 'regUTCL2_EDC_MODE', + 'regUTCL2_EDC_MODE_BASE_IDX', 'regUTCL2_MEM_ECC_CNTL', + 'regUTCL2_MEM_ECC_CNTL_BASE_IDX', 'regUTCL2_MEM_ECC_INDEX', + 'regUTCL2_MEM_ECC_INDEX_BASE_IDX', 'regUTCL2_MEM_ECC_STATUS', + 'regUTCL2_MEM_ECC_STATUS_BASE_IDX', 'regUTCL2_UE_ERR_STATUS_HI', + 'regUTCL2_UE_ERR_STATUS_HI_BASE_IDX', 'regUTCL2_UE_ERR_STATUS_LO', + 'regUTCL2_UE_ERR_STATUS_LO_BASE_IDX', + 'regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI', + 'regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX', + 'regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO', + 'regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX', + 'regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI', + 'regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX', + 'regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO', + 'regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX', + 'regVGT_CACHE_INVALIDATION', 'regVGT_CACHE_INVALIDATION_BASE_IDX', + 'regVGT_CNTL_STATUS', 'regVGT_CNTL_STATUS_BASE_IDX', + 'regVGT_DISPATCH_DRAW_INDEX', + 'regVGT_DISPATCH_DRAW_INDEX_BASE_IDX', 'regVGT_DMA_BASE', + 'regVGT_DMA_BASE_BASE_IDX', 'regVGT_DMA_BASE_HI', + 'regVGT_DMA_BASE_HI_BASE_IDX', 'regVGT_DMA_CONTROL', + 'regVGT_DMA_CONTROL_BASE_IDX', 'regVGT_DMA_DATA_FIFO_DEPTH', + 'regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX', + 'regVGT_DMA_EVENT_INITIATOR', + 'regVGT_DMA_EVENT_INITIATOR_BASE_IDX', 'regVGT_DMA_INDEX_TYPE', + 'regVGT_DMA_INDEX_TYPE_BASE_IDX', 'regVGT_DMA_LS_HS_CONFIG', + 'regVGT_DMA_LS_HS_CONFIG_BASE_IDX', 'regVGT_DMA_MAX_SIZE', + 'regVGT_DMA_MAX_SIZE_BASE_IDX', 'regVGT_DMA_NUM_INSTANCES', + 'regVGT_DMA_NUM_INSTANCES_BASE_IDX', 'regVGT_DMA_PRIMITIVE_TYPE', + 'regVGT_DMA_PRIMITIVE_TYPE_BASE_IDX', 'regVGT_DMA_REQ_FIFO_DEPTH', + 'regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX', 'regVGT_DMA_SIZE', + 'regVGT_DMA_SIZE_BASE_IDX', 'regVGT_DRAW_INITIATOR', + 'regVGT_DRAW_INITIATOR_BASE_IDX', 'regVGT_DRAW_INIT_FIFO_DEPTH', + 'regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX', + 'regVGT_DRAW_PAYLOAD_CNTL', 'regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX', + 'regVGT_ENHANCE', 'regVGT_ENHANCE_BASE_IDX', + 'regVGT_ESGS_RING_ITEMSIZE', 'regVGT_ESGS_RING_ITEMSIZE_BASE_IDX', + 'regVGT_ES_PER_GS', 'regVGT_ES_PER_GS_BASE_IDX', + 'regVGT_EVENT_ADDRESS_REG', 'regVGT_EVENT_ADDRESS_REG_BASE_IDX', + 'regVGT_EVENT_INITIATOR', 'regVGT_EVENT_INITIATOR_BASE_IDX', + 'regVGT_FIFO_DEPTHS', 'regVGT_FIFO_DEPTHS_BASE_IDX', + 'regVGT_GROUP_DECR', 'regVGT_GROUP_DECR_BASE_IDX', + 'regVGT_GROUP_FIRST_DECR', 'regVGT_GROUP_FIRST_DECR_BASE_IDX', + 'regVGT_GROUP_PRIM_TYPE', 'regVGT_GROUP_PRIM_TYPE_BASE_IDX', + 'regVGT_GROUP_VECT_0_CNTL', 'regVGT_GROUP_VECT_0_CNTL_BASE_IDX', + 'regVGT_GROUP_VECT_0_FMT_CNTL', + 'regVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX', + 'regVGT_GROUP_VECT_1_CNTL', 'regVGT_GROUP_VECT_1_CNTL_BASE_IDX', + 'regVGT_GROUP_VECT_1_FMT_CNTL', + 'regVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX', + 'regVGT_GSVS_RING_ITEMSIZE', 'regVGT_GSVS_RING_ITEMSIZE_BASE_IDX', + 'regVGT_GSVS_RING_OFFSET_1', 'regVGT_GSVS_RING_OFFSET_1_BASE_IDX', + 'regVGT_GSVS_RING_OFFSET_2', 'regVGT_GSVS_RING_OFFSET_2_BASE_IDX', + 'regVGT_GSVS_RING_OFFSET_3', 'regVGT_GSVS_RING_OFFSET_3_BASE_IDX', + 'regVGT_GSVS_RING_SIZE', 'regVGT_GSVS_RING_SIZE_BASE_IDX', + 'regVGT_GS_INSTANCE_CNT', 'regVGT_GS_INSTANCE_CNT_BASE_IDX', + 'regVGT_GS_MAX_PRIMS_PER_SUBGROUP', + 'regVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX', + 'regVGT_GS_MAX_VERT_OUT', 'regVGT_GS_MAX_VERT_OUT_BASE_IDX', + 'regVGT_GS_MAX_WAVE_ID', 'regVGT_GS_MAX_WAVE_ID_BASE_IDX', + 'regVGT_GS_MODE', 'regVGT_GS_MODE_BASE_IDX', + 'regVGT_GS_ONCHIP_CNTL', 'regVGT_GS_ONCHIP_CNTL_BASE_IDX', + 'regVGT_GS_OUT_PRIM_TYPE', 'regVGT_GS_OUT_PRIM_TYPE_BASE_IDX', + 'regVGT_GS_PER_ES', 'regVGT_GS_PER_ES_BASE_IDX', + 'regVGT_GS_PER_VS', 'regVGT_GS_PER_VS_BASE_IDX', + 'regVGT_GS_VERTEX_REUSE', 'regVGT_GS_VERTEX_REUSE_BASE_IDX', + 'regVGT_GS_VERT_ITEMSIZE', 'regVGT_GS_VERT_ITEMSIZE_1', + 'regVGT_GS_VERT_ITEMSIZE_1_BASE_IDX', 'regVGT_GS_VERT_ITEMSIZE_2', + 'regVGT_GS_VERT_ITEMSIZE_2_BASE_IDX', 'regVGT_GS_VERT_ITEMSIZE_3', + 'regVGT_GS_VERT_ITEMSIZE_3_BASE_IDX', + 'regVGT_GS_VERT_ITEMSIZE_BASE_IDX', 'regVGT_HOS_CNTL', + 'regVGT_HOS_CNTL_BASE_IDX', 'regVGT_HOS_MAX_TESS_LEVEL', + 'regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX', 'regVGT_HOS_MIN_TESS_LEVEL', + 'regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX', 'regVGT_HOS_REUSE_DEPTH', + 'regVGT_HOS_REUSE_DEPTH_BASE_IDX', 'regVGT_HS_OFFCHIP_PARAM', + 'regVGT_HS_OFFCHIP_PARAM_BASE_IDX', 'regVGT_IMMED_DATA', + 'regVGT_IMMED_DATA_BASE_IDX', 'regVGT_INDEX_TYPE', + 'regVGT_INDEX_TYPE_BASE_IDX', 'regVGT_INDX_OFFSET', + 'regVGT_INDX_OFFSET_BASE_IDX', 'regVGT_INSTANCE_BASE_ID', + 'regVGT_INSTANCE_BASE_ID_BASE_IDX', 'regVGT_INSTANCE_STEP_RATE_0', + 'regVGT_INSTANCE_STEP_RATE_0_BASE_IDX', + 'regVGT_INSTANCE_STEP_RATE_1', + 'regVGT_INSTANCE_STEP_RATE_1_BASE_IDX', 'regVGT_LAST_COPY_STATE', + 'regVGT_LAST_COPY_STATE_BASE_IDX', 'regVGT_LS_HS_CONFIG', + 'regVGT_LS_HS_CONFIG_BASE_IDX', 'regVGT_MAX_VTX_INDX', + 'regVGT_MAX_VTX_INDX_BASE_IDX', 'regVGT_MC_LAT_CNTL', + 'regVGT_MC_LAT_CNTL_BASE_IDX', 'regVGT_MIN_VTX_INDX', + 'regVGT_MIN_VTX_INDX_BASE_IDX', 'regVGT_MULTI_PRIM_IB_RESET_EN', + 'regVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX', + 'regVGT_MULTI_PRIM_IB_RESET_INDX', + 'regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX', 'regVGT_NUM_INDICES', + 'regVGT_NUM_INDICES_BASE_IDX', 'regVGT_NUM_INSTANCES', + 'regVGT_NUM_INSTANCES_BASE_IDX', 'regVGT_OUTPUT_PATH_CNTL', + 'regVGT_OUTPUT_PATH_CNTL_BASE_IDX', 'regVGT_OUT_DEALLOC_CNTL', + 'regVGT_OUT_DEALLOC_CNTL_BASE_IDX', 'regVGT_PERFCOUNTER0_HI', + 'regVGT_PERFCOUNTER0_HI_BASE_IDX', 'regVGT_PERFCOUNTER0_LO', + 'regVGT_PERFCOUNTER0_LO_BASE_IDX', 'regVGT_PERFCOUNTER0_SELECT', + 'regVGT_PERFCOUNTER0_SELECT1', + 'regVGT_PERFCOUNTER0_SELECT1_BASE_IDX', + 'regVGT_PERFCOUNTER0_SELECT_BASE_IDX', 'regVGT_PERFCOUNTER1_HI', + 'regVGT_PERFCOUNTER1_HI_BASE_IDX', 'regVGT_PERFCOUNTER1_LO', + 'regVGT_PERFCOUNTER1_LO_BASE_IDX', 'regVGT_PERFCOUNTER1_SELECT', + 'regVGT_PERFCOUNTER1_SELECT1', + 'regVGT_PERFCOUNTER1_SELECT1_BASE_IDX', + 'regVGT_PERFCOUNTER1_SELECT_BASE_IDX', 'regVGT_PERFCOUNTER2_HI', + 'regVGT_PERFCOUNTER2_HI_BASE_IDX', 'regVGT_PERFCOUNTER2_LO', + 'regVGT_PERFCOUNTER2_LO_BASE_IDX', 'regVGT_PERFCOUNTER2_SELECT', + 'regVGT_PERFCOUNTER2_SELECT_BASE_IDX', 'regVGT_PERFCOUNTER3_HI', + 'regVGT_PERFCOUNTER3_HI_BASE_IDX', 'regVGT_PERFCOUNTER3_LO', + 'regVGT_PERFCOUNTER3_LO_BASE_IDX', 'regVGT_PERFCOUNTER3_SELECT', + 'regVGT_PERFCOUNTER3_SELECT_BASE_IDX', + 'regVGT_PERFCOUNTER_SEID_MASK', + 'regVGT_PERFCOUNTER_SEID_MASK_BASE_IDX', 'regVGT_PRIMITIVEID_EN', + 'regVGT_PRIMITIVEID_EN_BASE_IDX', 'regVGT_PRIMITIVEID_RESET', + 'regVGT_PRIMITIVEID_RESET_BASE_IDX', 'regVGT_PRIMITIVE_TYPE', + 'regVGT_PRIMITIVE_TYPE_BASE_IDX', 'regVGT_RESET_DEBUG', + 'regVGT_RESET_DEBUG_BASE_IDX', 'regVGT_REUSE_OFF', + 'regVGT_REUSE_OFF_BASE_IDX', 'regVGT_SHADER_STAGES_EN', + 'regVGT_SHADER_STAGES_EN_BASE_IDX', + 'regVGT_STRMOUT_BUFFER_CONFIG', + 'regVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX', + 'regVGT_STRMOUT_BUFFER_FILLED_SIZE_0', + 'regVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX', + 'regVGT_STRMOUT_BUFFER_FILLED_SIZE_1', + 'regVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX', + 'regVGT_STRMOUT_BUFFER_FILLED_SIZE_2', + 'regVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX', + 'regVGT_STRMOUT_BUFFER_FILLED_SIZE_3', + 'regVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX', + 'regVGT_STRMOUT_BUFFER_OFFSET_0', + 'regVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX', + 'regVGT_STRMOUT_BUFFER_OFFSET_1', + 'regVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX', + 'regVGT_STRMOUT_BUFFER_OFFSET_2', + 'regVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX', + 'regVGT_STRMOUT_BUFFER_OFFSET_3', + 'regVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX', + 'regVGT_STRMOUT_BUFFER_SIZE_0', + 'regVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX', + 'regVGT_STRMOUT_BUFFER_SIZE_1', + 'regVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX', + 'regVGT_STRMOUT_BUFFER_SIZE_2', + 'regVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX', + 'regVGT_STRMOUT_BUFFER_SIZE_3', + 'regVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX', 'regVGT_STRMOUT_CONFIG', + 'regVGT_STRMOUT_CONFIG_BASE_IDX', 'regVGT_STRMOUT_DELAY', + 'regVGT_STRMOUT_DELAY_BASE_IDX', + 'regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE', + 'regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX', + 'regVGT_STRMOUT_DRAW_OPAQUE_OFFSET', + 'regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX', + 'regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE', + 'regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX', + 'regVGT_STRMOUT_VTX_STRIDE_0', + 'regVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX', + 'regVGT_STRMOUT_VTX_STRIDE_1', + 'regVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX', + 'regVGT_STRMOUT_VTX_STRIDE_2', + 'regVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX', + 'regVGT_STRMOUT_VTX_STRIDE_3', + 'regVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX', 'regVGT_SYS_CONFIG', + 'regVGT_SYS_CONFIG_BASE_IDX', 'regVGT_TESS_DISTRIBUTION', + 'regVGT_TESS_DISTRIBUTION_BASE_IDX', 'regVGT_TF_MEMORY_BASE', + 'regVGT_TF_MEMORY_BASE_BASE_IDX', 'regVGT_TF_MEMORY_BASE_HI', + 'regVGT_TF_MEMORY_BASE_HI_BASE_IDX', 'regVGT_TF_PARAM', + 'regVGT_TF_PARAM_BASE_IDX', 'regVGT_TF_RING_SIZE', + 'regVGT_TF_RING_SIZE_BASE_IDX', 'regVGT_VERTEX_REUSE_BLOCK_CNTL', + 'regVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX', + 'regVGT_VS_MAX_WAVE_ID', 'regVGT_VS_MAX_WAVE_ID_BASE_IDX', + 'regVGT_VTX_CNT_EN', 'regVGT_VTX_CNT_EN_BASE_IDX', + 'regVGT_VTX_VECT_EJECT_REG', 'regVGT_VTX_VECT_EJECT_REG_BASE_IDX', + 'regVIOLATION_DATA_ASYNC_VF_PROG', + 'regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX', + 'regVML2_CE_ERR_STATUS_HI', 'regVML2_CE_ERR_STATUS_HI_BASE_IDX', + 'regVML2_CE_ERR_STATUS_LO', 'regVML2_CE_ERR_STATUS_LO_BASE_IDX', + 'regVML2_MEM_ECC_CNTL', 'regVML2_MEM_ECC_CNTL_BASE_IDX', + 'regVML2_MEM_ECC_INDEX', 'regVML2_MEM_ECC_INDEX_BASE_IDX', + 'regVML2_MEM_ECC_STATUS', 'regVML2_MEM_ECC_STATUS_BASE_IDX', + 'regVML2_UE_ERR_STATUS_HI', 'regVML2_UE_ERR_STATUS_HI_BASE_IDX', + 'regVML2_UE_ERR_STATUS_LO', 'regVML2_UE_ERR_STATUS_LO_BASE_IDX', + 'regVML2_WALKER_CE_ERR_STATUS_HI', + 'regVML2_WALKER_CE_ERR_STATUS_HI_BASE_IDX', + 'regVML2_WALKER_CE_ERR_STATUS_LO', + 'regVML2_WALKER_CE_ERR_STATUS_LO_BASE_IDX', + 'regVML2_WALKER_MEM_ECC_CNTL', + 'regVML2_WALKER_MEM_ECC_CNTL_BASE_IDX', + 'regVML2_WALKER_MEM_ECC_INDEX', + 'regVML2_WALKER_MEM_ECC_INDEX_BASE_IDX', + 'regVML2_WALKER_MEM_ECC_STATUS', + 'regVML2_WALKER_MEM_ECC_STATUS_BASE_IDX', + 'regVML2_WALKER_UE_ERR_STATUS_HI', + 'regVML2_WALKER_UE_ERR_STATUS_HI_BASE_IDX', + 'regVML2_WALKER_UE_ERR_STATUS_LO', + 'regVML2_WALKER_UE_ERR_STATUS_LO_BASE_IDX', 'regVM_CONTEXT0_CNTL', + 'regVM_CONTEXT0_CNTL_BASE_IDX', + 'regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32', + 'regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32', + 'regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32', + 'regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32', + 'regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32', + 'regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32', + 'regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT10_CNTL', 'regVM_CONTEXT10_CNTL_BASE_IDX', + 'regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32', + 'regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32', + 'regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32', + 'regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32', + 'regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32', + 'regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32', + 'regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT11_CNTL', 'regVM_CONTEXT11_CNTL_BASE_IDX', + 'regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32', + 'regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32', + 'regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32', + 'regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32', + 'regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32', + 'regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32', + 'regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT12_CNTL', 'regVM_CONTEXT12_CNTL_BASE_IDX', + 'regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32', + 'regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32', + 'regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32', + 'regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32', + 'regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32', + 'regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32', + 'regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT13_CNTL', 'regVM_CONTEXT13_CNTL_BASE_IDX', + 'regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32', + 'regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32', + 'regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32', + 'regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32', + 'regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32', + 'regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32', + 'regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT14_CNTL', 'regVM_CONTEXT14_CNTL_BASE_IDX', + 'regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32', + 'regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32', + 'regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32', + 'regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32', + 'regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32', + 'regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32', + 'regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT15_CNTL', 'regVM_CONTEXT15_CNTL_BASE_IDX', + 'regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32', + 'regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32', + 'regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32', + 'regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32', + 'regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32', + 'regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32', + 'regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT1_CNTL', 'regVM_CONTEXT1_CNTL_BASE_IDX', + 'regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32', + 'regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32', + 'regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32', + 'regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32', + 'regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32', + 'regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32', + 'regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT2_CNTL', 'regVM_CONTEXT2_CNTL_BASE_IDX', + 'regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32', + 'regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32', + 'regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32', + 'regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32', + 'regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32', + 'regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32', + 'regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT3_CNTL', 'regVM_CONTEXT3_CNTL_BASE_IDX', + 'regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32', + 'regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32', + 'regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32', + 'regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32', + 'regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32', + 'regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32', + 'regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT4_CNTL', 'regVM_CONTEXT4_CNTL_BASE_IDX', + 'regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32', + 'regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32', + 'regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32', + 'regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32', + 'regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32', + 'regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32', + 'regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT5_CNTL', 'regVM_CONTEXT5_CNTL_BASE_IDX', + 'regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32', + 'regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32', + 'regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32', + 'regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32', + 'regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32', + 'regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32', + 'regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT6_CNTL', 'regVM_CONTEXT6_CNTL_BASE_IDX', + 'regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32', + 'regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32', + 'regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32', + 'regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32', + 'regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32', + 'regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32', + 'regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT7_CNTL', 'regVM_CONTEXT7_CNTL_BASE_IDX', + 'regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32', + 'regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32', + 'regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32', + 'regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32', + 'regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32', + 'regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32', + 'regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT8_CNTL', 'regVM_CONTEXT8_CNTL_BASE_IDX', + 'regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32', + 'regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32', + 'regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32', + 'regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32', + 'regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32', + 'regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32', + 'regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT9_CNTL', 'regVM_CONTEXT9_CNTL_BASE_IDX', + 'regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32', + 'regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32', + 'regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32', + 'regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32', + 'regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32', + 'regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32', + 'regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regVM_CONTEXTS_DISABLE', 'regVM_CONTEXTS_DISABLE_BASE_IDX', + 'regVM_DUMMY_PAGE_FAULT_ADDR_HI32', + 'regVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX', + 'regVM_DUMMY_PAGE_FAULT_ADDR_LO32', + 'regVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX', + 'regVM_DUMMY_PAGE_FAULT_CNTL', + 'regVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX', + 'regVM_INVALIDATE_ENG0_ACK', 'regVM_INVALIDATE_ENG0_ACK_BASE_IDX', + 'regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32', + 'regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX', + 'regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32', + 'regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX', + 'regVM_INVALIDATE_ENG0_REQ', 'regVM_INVALIDATE_ENG0_REQ_BASE_IDX', + 'regVM_INVALIDATE_ENG0_SEM', 'regVM_INVALIDATE_ENG0_SEM_BASE_IDX', + 'regVM_INVALIDATE_ENG10_ACK', + 'regVM_INVALIDATE_ENG10_ACK_BASE_IDX', + 'regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32', + 'regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX', + 'regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32', + 'regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX', + 'regVM_INVALIDATE_ENG10_REQ', + 'regVM_INVALIDATE_ENG10_REQ_BASE_IDX', + 'regVM_INVALIDATE_ENG10_SEM', + 'regVM_INVALIDATE_ENG10_SEM_BASE_IDX', + 'regVM_INVALIDATE_ENG11_ACK', + 'regVM_INVALIDATE_ENG11_ACK_BASE_IDX', + 'regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32', + 'regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX', + 'regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32', + 'regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX', + 'regVM_INVALIDATE_ENG11_REQ', + 'regVM_INVALIDATE_ENG11_REQ_BASE_IDX', + 'regVM_INVALIDATE_ENG11_SEM', + 'regVM_INVALIDATE_ENG11_SEM_BASE_IDX', + 'regVM_INVALIDATE_ENG12_ACK', + 'regVM_INVALIDATE_ENG12_ACK_BASE_IDX', + 'regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32', + 'regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX', + 'regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32', + 'regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX', + 'regVM_INVALIDATE_ENG12_REQ', + 'regVM_INVALIDATE_ENG12_REQ_BASE_IDX', + 'regVM_INVALIDATE_ENG12_SEM', + 'regVM_INVALIDATE_ENG12_SEM_BASE_IDX', + 'regVM_INVALIDATE_ENG13_ACK', + 'regVM_INVALIDATE_ENG13_ACK_BASE_IDX', + 'regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32', + 'regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX', + 'regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32', + 'regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX', + 'regVM_INVALIDATE_ENG13_REQ', + 'regVM_INVALIDATE_ENG13_REQ_BASE_IDX', + 'regVM_INVALIDATE_ENG13_SEM', + 'regVM_INVALIDATE_ENG13_SEM_BASE_IDX', + 'regVM_INVALIDATE_ENG14_ACK', + 'regVM_INVALIDATE_ENG14_ACK_BASE_IDX', + 'regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32', + 'regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX', + 'regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32', + 'regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX', + 'regVM_INVALIDATE_ENG14_REQ', + 'regVM_INVALIDATE_ENG14_REQ_BASE_IDX', + 'regVM_INVALIDATE_ENG14_SEM', + 'regVM_INVALIDATE_ENG14_SEM_BASE_IDX', + 'regVM_INVALIDATE_ENG15_ACK', + 'regVM_INVALIDATE_ENG15_ACK_BASE_IDX', + 'regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32', + 'regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX', + 'regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32', + 'regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX', + 'regVM_INVALIDATE_ENG15_REQ', + 'regVM_INVALIDATE_ENG15_REQ_BASE_IDX', + 'regVM_INVALIDATE_ENG15_SEM', + 'regVM_INVALIDATE_ENG15_SEM_BASE_IDX', + 'regVM_INVALIDATE_ENG16_ACK', + 'regVM_INVALIDATE_ENG16_ACK_BASE_IDX', + 'regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32', + 'regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX', + 'regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32', + 'regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX', + 'regVM_INVALIDATE_ENG16_REQ', + 'regVM_INVALIDATE_ENG16_REQ_BASE_IDX', + 'regVM_INVALIDATE_ENG16_SEM', + 'regVM_INVALIDATE_ENG16_SEM_BASE_IDX', + 'regVM_INVALIDATE_ENG17_ACK', + 'regVM_INVALIDATE_ENG17_ACK_BASE_IDX', + 'regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32', + 'regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX', + 'regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32', + 'regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX', + 'regVM_INVALIDATE_ENG17_REQ', + 'regVM_INVALIDATE_ENG17_REQ_BASE_IDX', + 'regVM_INVALIDATE_ENG17_SEM', + 'regVM_INVALIDATE_ENG17_SEM_BASE_IDX', + 'regVM_INVALIDATE_ENG1_ACK', 'regVM_INVALIDATE_ENG1_ACK_BASE_IDX', + 'regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32', + 'regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX', + 'regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32', + 'regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX', + 'regVM_INVALIDATE_ENG1_REQ', 'regVM_INVALIDATE_ENG1_REQ_BASE_IDX', + 'regVM_INVALIDATE_ENG1_SEM', 'regVM_INVALIDATE_ENG1_SEM_BASE_IDX', + 'regVM_INVALIDATE_ENG2_ACK', 'regVM_INVALIDATE_ENG2_ACK_BASE_IDX', + 'regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32', + 'regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX', + 'regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32', + 'regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX', + 'regVM_INVALIDATE_ENG2_REQ', 'regVM_INVALIDATE_ENG2_REQ_BASE_IDX', + 'regVM_INVALIDATE_ENG2_SEM', 'regVM_INVALIDATE_ENG2_SEM_BASE_IDX', + 'regVM_INVALIDATE_ENG3_ACK', 'regVM_INVALIDATE_ENG3_ACK_BASE_IDX', + 'regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32', + 'regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX', + 'regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32', + 'regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX', + 'regVM_INVALIDATE_ENG3_REQ', 'regVM_INVALIDATE_ENG3_REQ_BASE_IDX', + 'regVM_INVALIDATE_ENG3_SEM', 'regVM_INVALIDATE_ENG3_SEM_BASE_IDX', + 'regVM_INVALIDATE_ENG4_ACK', 'regVM_INVALIDATE_ENG4_ACK_BASE_IDX', + 'regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32', + 'regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX', + 'regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32', + 'regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX', + 'regVM_INVALIDATE_ENG4_REQ', 'regVM_INVALIDATE_ENG4_REQ_BASE_IDX', + 'regVM_INVALIDATE_ENG4_SEM', 'regVM_INVALIDATE_ENG4_SEM_BASE_IDX', + 'regVM_INVALIDATE_ENG5_ACK', 'regVM_INVALIDATE_ENG5_ACK_BASE_IDX', + 'regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32', + 'regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX', + 'regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32', + 'regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX', + 'regVM_INVALIDATE_ENG5_REQ', 'regVM_INVALIDATE_ENG5_REQ_BASE_IDX', + 'regVM_INVALIDATE_ENG5_SEM', 'regVM_INVALIDATE_ENG5_SEM_BASE_IDX', + 'regVM_INVALIDATE_ENG6_ACK', 'regVM_INVALIDATE_ENG6_ACK_BASE_IDX', + 'regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32', + 'regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX', + 'regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32', + 'regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX', + 'regVM_INVALIDATE_ENG6_REQ', 'regVM_INVALIDATE_ENG6_REQ_BASE_IDX', + 'regVM_INVALIDATE_ENG6_SEM', 'regVM_INVALIDATE_ENG6_SEM_BASE_IDX', + 'regVM_INVALIDATE_ENG7_ACK', 'regVM_INVALIDATE_ENG7_ACK_BASE_IDX', + 'regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32', + 'regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX', + 'regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32', + 'regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX', + 'regVM_INVALIDATE_ENG7_REQ', 'regVM_INVALIDATE_ENG7_REQ_BASE_IDX', + 'regVM_INVALIDATE_ENG7_SEM', 'regVM_INVALIDATE_ENG7_SEM_BASE_IDX', + 'regVM_INVALIDATE_ENG8_ACK', 'regVM_INVALIDATE_ENG8_ACK_BASE_IDX', + 'regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32', + 'regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX', + 'regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32', + 'regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX', + 'regVM_INVALIDATE_ENG8_REQ', 'regVM_INVALIDATE_ENG8_REQ_BASE_IDX', + 'regVM_INVALIDATE_ENG8_SEM', 'regVM_INVALIDATE_ENG8_SEM_BASE_IDX', + 'regVM_INVALIDATE_ENG9_ACK', 'regVM_INVALIDATE_ENG9_ACK_BASE_IDX', + 'regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32', + 'regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX', + 'regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32', + 'regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX', + 'regVM_INVALIDATE_ENG9_REQ', 'regVM_INVALIDATE_ENG9_REQ_BASE_IDX', + 'regVM_INVALIDATE_ENG9_SEM', 'regVM_INVALIDATE_ENG9_SEM_BASE_IDX', + 'regVM_IOMMU_CONTROL_REGISTER', + 'regVM_IOMMU_CONTROL_REGISTER_BASE_IDX', + 'regVM_IOMMU_MMIO_CNTRL_1', 'regVM_IOMMU_MMIO_CNTRL_1_BASE_IDX', + 'regVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER', + 'regVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX', + 'regVM_L2_BANK_SELECT_RESERVED_CID', + 'regVM_L2_BANK_SELECT_RESERVED_CID2', + 'regVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX', + 'regVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX', + 'regVM_L2_CACHE_PARITY_CNTL', + 'regVM_L2_CACHE_PARITY_CNTL_BASE_IDX', 'regVM_L2_CGTT_BUSY_CTRL', + 'regVM_L2_CGTT_BUSY_CTRL_BASE_IDX', 'regVM_L2_CGTT_CLK_CTRL', + 'regVM_L2_CGTT_CLK_CTRL_BASE_IDX', 'regVM_L2_CNTL', + 'regVM_L2_CNTL2', 'regVM_L2_CNTL2_BASE_IDX', 'regVM_L2_CNTL3', + 'regVM_L2_CNTL3_BASE_IDX', 'regVM_L2_CNTL4', + 'regVM_L2_CNTL4_BASE_IDX', 'regVM_L2_CNTL5', + 'regVM_L2_CNTL5_BASE_IDX', 'regVM_L2_CNTL_BASE_IDX', + 'regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32', + 'regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX', + 'regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32', + 'regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX', + 'regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32', + 'regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX', + 'regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32', + 'regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX', + 'regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32', + 'regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX', + 'regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32', + 'regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX', + 'regVM_L2_MM_GROUP_RT_CLASSES', + 'regVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX', + 'regVM_L2_PROTECTION_FAULT_ADDR_HI32', + 'regVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX', + 'regVM_L2_PROTECTION_FAULT_ADDR_LO32', + 'regVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX', + 'regVM_L2_PROTECTION_FAULT_CNTL', + 'regVM_L2_PROTECTION_FAULT_CNTL2', + 'regVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX', + 'regVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX', + 'regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32', + 'regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX', + 'regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32', + 'regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX', + 'regVM_L2_PROTECTION_FAULT_MM_CNTL3', + 'regVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX', + 'regVM_L2_PROTECTION_FAULT_MM_CNTL4', + 'regVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX', + 'regVM_L2_PROTECTION_FAULT_STATUS', + 'regVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX', 'regVM_L2_STATUS', + 'regVM_L2_STATUS_BASE_IDX', 'regVM_PCIE_ATS_CNTL', + 'regVM_PCIE_ATS_CNTL_BASE_IDX', 'regVM_PCIE_ATS_CNTL_VF_0', + 'regVM_PCIE_ATS_CNTL_VF_0_BASE_IDX', 'regVM_PCIE_ATS_CNTL_VF_1', + 'regVM_PCIE_ATS_CNTL_VF_10', 'regVM_PCIE_ATS_CNTL_VF_10_BASE_IDX', + 'regVM_PCIE_ATS_CNTL_VF_11', 'regVM_PCIE_ATS_CNTL_VF_11_BASE_IDX', + 'regVM_PCIE_ATS_CNTL_VF_12', 'regVM_PCIE_ATS_CNTL_VF_12_BASE_IDX', + 'regVM_PCIE_ATS_CNTL_VF_13', 'regVM_PCIE_ATS_CNTL_VF_13_BASE_IDX', + 'regVM_PCIE_ATS_CNTL_VF_14', 'regVM_PCIE_ATS_CNTL_VF_14_BASE_IDX', + 'regVM_PCIE_ATS_CNTL_VF_15', 'regVM_PCIE_ATS_CNTL_VF_15_BASE_IDX', + 'regVM_PCIE_ATS_CNTL_VF_1_BASE_IDX', 'regVM_PCIE_ATS_CNTL_VF_2', + 'regVM_PCIE_ATS_CNTL_VF_2_BASE_IDX', 'regVM_PCIE_ATS_CNTL_VF_3', + 'regVM_PCIE_ATS_CNTL_VF_3_BASE_IDX', 'regVM_PCIE_ATS_CNTL_VF_4', + 'regVM_PCIE_ATS_CNTL_VF_4_BASE_IDX', 'regVM_PCIE_ATS_CNTL_VF_5', + 'regVM_PCIE_ATS_CNTL_VF_5_BASE_IDX', 'regVM_PCIE_ATS_CNTL_VF_6', + 'regVM_PCIE_ATS_CNTL_VF_6_BASE_IDX', 'regVM_PCIE_ATS_CNTL_VF_7', + 'regVM_PCIE_ATS_CNTL_VF_7_BASE_IDX', 'regVM_PCIE_ATS_CNTL_VF_8', + 'regVM_PCIE_ATS_CNTL_VF_8_BASE_IDX', 'regVM_PCIE_ATS_CNTL_VF_9', + 'regVM_PCIE_ATS_CNTL_VF_9_BASE_IDX', 'regWD_BUF_RESOURCE_1', + 'regWD_BUF_RESOURCE_1_BASE_IDX', 'regWD_BUF_RESOURCE_2', + 'regWD_BUF_RESOURCE_2_BASE_IDX', 'regWD_CNTL_SB_BUF_BASE', + 'regWD_CNTL_SB_BUF_BASE_BASE_IDX', 'regWD_CNTL_SB_BUF_BASE_HI', + 'regWD_CNTL_SB_BUF_BASE_HI_BASE_IDX', 'regWD_CNTL_STATUS', + 'regWD_CNTL_STATUS_BASE_IDX', 'regWD_ENHANCE', + 'regWD_ENHANCE_BASE_IDX', 'regWD_INDEX_BUF_BASE', + 'regWD_INDEX_BUF_BASE_BASE_IDX', 'regWD_INDEX_BUF_BASE_HI', + 'regWD_INDEX_BUF_BASE_HI_BASE_IDX', 'regWD_PERFCOUNTER0_HI', + 'regWD_PERFCOUNTER0_HI_BASE_IDX', 'regWD_PERFCOUNTER0_LO', + 'regWD_PERFCOUNTER0_LO_BASE_IDX', 'regWD_PERFCOUNTER0_SELECT', + 'regWD_PERFCOUNTER0_SELECT_BASE_IDX', 'regWD_PERFCOUNTER1_HI', + 'regWD_PERFCOUNTER1_HI_BASE_IDX', 'regWD_PERFCOUNTER1_LO', + 'regWD_PERFCOUNTER1_LO_BASE_IDX', 'regWD_PERFCOUNTER1_SELECT', + 'regWD_PERFCOUNTER1_SELECT_BASE_IDX', 'regWD_PERFCOUNTER2_HI', + 'regWD_PERFCOUNTER2_HI_BASE_IDX', 'regWD_PERFCOUNTER2_LO', + 'regWD_PERFCOUNTER2_LO_BASE_IDX', 'regWD_PERFCOUNTER2_SELECT', + 'regWD_PERFCOUNTER2_SELECT_BASE_IDX', 'regWD_PERFCOUNTER3_HI', + 'regWD_PERFCOUNTER3_HI_BASE_IDX', 'regWD_PERFCOUNTER3_LO', + 'regWD_PERFCOUNTER3_LO_BASE_IDX', 'regWD_PERFCOUNTER3_SELECT', + 'regWD_PERFCOUNTER3_SELECT_BASE_IDX', 'regWD_POS_BUF_BASE', + 'regWD_POS_BUF_BASE_BASE_IDX', 'regWD_POS_BUF_BASE_HI', + 'regWD_POS_BUF_BASE_HI_BASE_IDX', 'regWD_QOS', + 'regWD_QOS_BASE_IDX', 'regWD_UTCL1_CNTL', + 'regWD_UTCL1_CNTL_BASE_IDX', 'regWD_UTCL1_STATUS', + 'regWD_UTCL1_STATUS_BASE_IDX'] diff --git a/tinygrad/runtime/autogen/am/nbio_7_9_0.py b/tinygrad/runtime/autogen/am/nbio_7_9_0.py new file mode 100644 index 0000000000..0cd019a358 --- /dev/null +++ b/tinygrad/runtime/autogen/am/nbio_7_9_0.py @@ -0,0 +1,84562 @@ +# mypy: ignore-errors +# -*- coding: utf-8 -*- +# +# TARGET arch is: [] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes + + + + +_nbio_7_9_0_OFFSET_HEADER = True # macro +regBIF_BX0_PCIE_INDEX = 0x000c # macro +regBIF_BX0_PCIE_INDEX_BASE_IDX = 0 # macro +regBIF_BX0_PCIE_DATA = 0x000d # macro +regBIF_BX0_PCIE_DATA_BASE_IDX = 0 # macro +regBIF_BX0_PCIE_INDEX2 = 0x000e # macro +regBIF_BX0_PCIE_INDEX2_BASE_IDX = 0 # macro +regBIF_BX0_PCIE_DATA2 = 0x000f # macro +regBIF_BX0_PCIE_DATA2_BASE_IDX = 0 # macro +regBIF_BX0_PCIE_INDEX_HI = 0x0010 # macro +regBIF_BX0_PCIE_INDEX_HI_BASE_IDX = 0 # macro +regBIF_BX0_PCIE_INDEX2_HI = 0x0011 # macro +regBIF_BX0_PCIE_INDEX2_HI_BASE_IDX = 0 # macro +regBIF_BX0_SBIOS_SCRATCH_0 = 0x0034 # macro +regBIF_BX0_SBIOS_SCRATCH_0_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_1 = 0x0035 # macro +regBIF_BX0_SBIOS_SCRATCH_1_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_2 = 0x0036 # macro +regBIF_BX0_SBIOS_SCRATCH_2_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_3 = 0x0037 # macro +regBIF_BX0_SBIOS_SCRATCH_3_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_0 = 0x0038 # macro +regBIF_BX0_BIOS_SCRATCH_0_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_1 = 0x0039 # macro +regBIF_BX0_BIOS_SCRATCH_1_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_2 = 0x003a # macro +regBIF_BX0_BIOS_SCRATCH_2_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_3 = 0x003b # macro +regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_4 = 0x003c # macro +regBIF_BX0_BIOS_SCRATCH_4_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_5 = 0x003d # macro +regBIF_BX0_BIOS_SCRATCH_5_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_6 = 0x003e # macro +regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_7 = 0x003f # macro +regBIF_BX0_BIOS_SCRATCH_7_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_8 = 0x0040 # macro +regBIF_BX0_BIOS_SCRATCH_8_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_9 = 0x0041 # macro +regBIF_BX0_BIOS_SCRATCH_9_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_10 = 0x0042 # macro +regBIF_BX0_BIOS_SCRATCH_10_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_11 = 0x0043 # macro +regBIF_BX0_BIOS_SCRATCH_11_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_12 = 0x0044 # macro +regBIF_BX0_BIOS_SCRATCH_12_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_13 = 0x0045 # macro +regBIF_BX0_BIOS_SCRATCH_13_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_14 = 0x0046 # macro +regBIF_BX0_BIOS_SCRATCH_14_BASE_IDX = 1 # macro +regBIF_BX0_BIOS_SCRATCH_15 = 0x0047 # macro +regBIF_BX0_BIOS_SCRATCH_15_BASE_IDX = 1 # macro +regBIF_BX0_BIF_RLC_INTR_CNTL = 0x004c # macro +regBIF_BX0_BIF_RLC_INTR_CNTL_BASE_IDX = 1 # macro +regBIF_BX0_BIF_VCE_INTR_CNTL = 0x004d # macro +regBIF_BX0_BIF_VCE_INTR_CNTL_BASE_IDX = 1 # macro +regBIF_BX0_BIF_UVD_INTR_CNTL = 0x004e # macro +regBIF_BX0_BIF_UVD_INTR_CNTL_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR0 = 0x006c # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR0_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 = 0x006d # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR1 = 0x006e # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR1_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 = 0x006f # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR2 = 0x0070 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR2_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 = 0x0071 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR3 = 0x0072 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR3_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 = 0x0073 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR4 = 0x0074 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR4_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 = 0x0075 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR5 = 0x0076 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR5_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 = 0x0077 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR6 = 0x0078 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR6_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 = 0x0079 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR7 = 0x007a # macro +regBIF_BX0_GFX_MMIOREG_CAM_ADDR7_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 = 0x007b # macro +regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_CNTL = 0x007c # macro +regBIF_BX0_GFX_MMIOREG_CAM_CNTL_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL = 0x007d # macro +regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL = 0x007e # macro +regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX = 1 # macro +regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL = 0x007f # macro +regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_0 = 0x0080 # macro +regBIF_BX0_DRIVER_SCRATCH_0_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_1 = 0x0081 # macro +regBIF_BX0_DRIVER_SCRATCH_1_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_2 = 0x0082 # macro +regBIF_BX0_DRIVER_SCRATCH_2_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_3 = 0x0083 # macro +regBIF_BX0_DRIVER_SCRATCH_3_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_4 = 0x0084 # macro +regBIF_BX0_DRIVER_SCRATCH_4_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_5 = 0x0085 # macro +regBIF_BX0_DRIVER_SCRATCH_5_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_6 = 0x0086 # macro +regBIF_BX0_DRIVER_SCRATCH_6_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_7 = 0x0087 # macro +regBIF_BX0_DRIVER_SCRATCH_7_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_8 = 0x0088 # macro +regBIF_BX0_DRIVER_SCRATCH_8_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_9 = 0x0089 # macro +regBIF_BX0_DRIVER_SCRATCH_9_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_10 = 0x008a # macro +regBIF_BX0_DRIVER_SCRATCH_10_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_11 = 0x008b # macro +regBIF_BX0_DRIVER_SCRATCH_11_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_12 = 0x008c # macro +regBIF_BX0_DRIVER_SCRATCH_12_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_13 = 0x008d # macro +regBIF_BX0_DRIVER_SCRATCH_13_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_14 = 0x008e # macro +regBIF_BX0_DRIVER_SCRATCH_14_BASE_IDX = 1 # macro +regBIF_BX0_DRIVER_SCRATCH_15 = 0x008f # macro +regBIF_BX0_DRIVER_SCRATCH_15_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_0 = 0x0090 # macro +regBIF_BX0_FW_SCRATCH_0_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_1 = 0x0091 # macro +regBIF_BX0_FW_SCRATCH_1_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_2 = 0x0092 # macro +regBIF_BX0_FW_SCRATCH_2_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_3 = 0x0093 # macro +regBIF_BX0_FW_SCRATCH_3_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_4 = 0x0094 # macro +regBIF_BX0_FW_SCRATCH_4_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_5 = 0x0095 # macro +regBIF_BX0_FW_SCRATCH_5_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_6 = 0x0096 # macro +regBIF_BX0_FW_SCRATCH_6_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_7 = 0x0097 # macro +regBIF_BX0_FW_SCRATCH_7_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_8 = 0x0098 # macro +regBIF_BX0_FW_SCRATCH_8_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_9 = 0x0099 # macro +regBIF_BX0_FW_SCRATCH_9_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_10 = 0x009a # macro +regBIF_BX0_FW_SCRATCH_10_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_11 = 0x009b # macro +regBIF_BX0_FW_SCRATCH_11_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_12 = 0x009c # macro +regBIF_BX0_FW_SCRATCH_12_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_13 = 0x009d # macro +regBIF_BX0_FW_SCRATCH_13_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_14 = 0x009e # macro +regBIF_BX0_FW_SCRATCH_14_BASE_IDX = 1 # macro +regBIF_BX0_FW_SCRATCH_15 = 0x009f # macro +regBIF_BX0_FW_SCRATCH_15_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_4 = 0x00a0 # macro +regBIF_BX0_SBIOS_SCRATCH_4_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_5 = 0x00a1 # macro +regBIF_BX0_SBIOS_SCRATCH_5_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_6 = 0x00a2 # macro +regBIF_BX0_SBIOS_SCRATCH_6_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_7 = 0x00a3 # macro +regBIF_BX0_SBIOS_SCRATCH_7_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_8 = 0x00a4 # macro +regBIF_BX0_SBIOS_SCRATCH_8_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_9 = 0x00a5 # macro +regBIF_BX0_SBIOS_SCRATCH_9_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_10 = 0x00a6 # macro +regBIF_BX0_SBIOS_SCRATCH_10_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_11 = 0x00a7 # macro +regBIF_BX0_SBIOS_SCRATCH_11_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_12 = 0x00a8 # macro +regBIF_BX0_SBIOS_SCRATCH_12_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_13 = 0x00a9 # macro +regBIF_BX0_SBIOS_SCRATCH_13_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_14 = 0x00aa # macro +regBIF_BX0_SBIOS_SCRATCH_14_BASE_IDX = 1 # macro +regBIF_BX0_SBIOS_SCRATCH_15 = 0x00ab # macro +regBIF_BX0_SBIOS_SCRATCH_15_BASE_IDX = 1 # macro +regRCC_DWN_DEV0_0_DN_PCIE_RESERVED = 0x0060 # macro +regRCC_DWN_DEV0_0_DN_PCIE_RESERVED_BASE_IDX = 2 # macro +regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH = 0x0061 # macro +regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_BASE_IDX = 2 # macro +regRCC_DWN_DEV0_0_DN_PCIE_CNTL = 0x0063 # macro +regRCC_DWN_DEV0_0_DN_PCIE_CNTL_BASE_IDX = 2 # macro +regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL = 0x0064 # macro +regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_BASE_IDX = 2 # macro +regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 = 0x0065 # macro +regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_BASE_IDX = 2 # macro +regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL = 0x0066 # macro +regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_BASE_IDX = 2 # macro +regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL = 0x0067 # macro +regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_BASE_IDX = 2 # macro +regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 = 0x0068 # macro +regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_BASE_IDX = 2 # macro +regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC = 0x0069 # macro +regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_BASE_IDX = 2 # macro +regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 = 0x006a # macro +regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_BASE_IDX = 2 # macro +regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL = 0x006c # macro +regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_BASE_IDX = 2 # macro +regRCC_DWNP_DEV0_0_PCIE_RX_CNTL = 0x006d # macro +regRCC_DWNP_DEV0_0_PCIE_RX_CNTL_BASE_IDX = 2 # macro +regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL = 0x006e # macro +regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_BASE_IDX = 2 # macro +regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2 = 0x006f # macro +regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_BASE_IDX = 2 # macro +regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC = 0x0070 # macro +regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_BASE_IDX = 2 # macro +regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP = 0x0071 # macro +regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_SCRATCH = 0x0040 # macro +regRCC_EP_DEV0_0_EP_PCIE_SCRATCH_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_CNTL = 0x0042 # macro +regRCC_EP_DEV0_0_EP_PCIE_CNTL_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL = 0x0043 # macro +regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS = 0x0044 # macro +regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 = 0x0045 # macro +regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL = 0x0046 # macro +regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL = 0x0047 # macro +regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL = 0x0049 # macro +regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 = 0x004a # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 = 0x004a # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 = 0x004a # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 = 0x004a # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 = 0x004b # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 = 0x004b # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 = 0x004b # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 = 0x004b # macro +regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC = 0x004c # macro +regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 = 0x004d # macro +regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP = 0x004f # macro +regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR = 0x0050 # macro +regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL = 0x0050 # macro +regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 = 0x0050 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 = 0x0051 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 = 0x0051 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 = 0x0051 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 = 0x0051 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 = 0x0052 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 = 0x0052 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 = 0x0052 # macro +regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL = 0x0052 # macro +regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIEP_RESERVED = 0x0053 # macro +regRCC_EP_DEV0_0_EP_PCIEP_RESERVED_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL = 0x0055 # macro +regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID = 0x0056 # macro +regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL = 0x0057 # macro +regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL = 0x0058 # macro +regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_BASE_IDX = 2 # macro +regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL = 0x0059 # macro +regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_BASE_IDX = 2 # macro +regBIF_BX_PF0_MM_INDEX = 0x0000 # macro +regBIF_BX_PF0_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_PF0_MM_DATA = 0x0001 # macro +regBIF_BX_PF0_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_PF0_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_PF0_MM_INDEX_HI_BASE_IDX = 0 # macro +regBIF_BX_PF0_RSMU_INDEX = 0x0000 # macro +regBIF_BX_PF0_RSMU_INDEX_BASE_IDX = 1 # macro +regBIF_BX_PF0_RSMU_DATA = 0x0001 # macro +regBIF_BX_PF0_RSMU_DATA_BASE_IDX = 1 # macro +regBIF_BX_PF0_RSMU_INDEX_HI = 0x0002 # macro +regBIF_BX_PF0_RSMU_INDEX_HI_BASE_IDX = 1 # macro +regBIF_BX0_CC_BIF_BX_STRAP0 = 0x00e2 # macro +regBIF_BX0_CC_BIF_BX_STRAP0_BASE_IDX = 2 # macro +regBIF_BX0_CC_BIF_BX_PINSTRAP0 = 0x00e4 # macro +regBIF_BX0_CC_BIF_BX_PINSTRAP0_BASE_IDX = 2 # macro +regBIF_BX0_BIF_MM_INDACCESS_CNTL = 0x00e6 # macro +regBIF_BX0_BIF_MM_INDACCESS_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BUS_CNTL = 0x00e7 # macro +regBIF_BX0_BUS_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BIF_SCRATCH0 = 0x00e8 # macro +regBIF_BX0_BIF_SCRATCH0_BASE_IDX = 2 # macro +regBIF_BX0_BIF_SCRATCH1 = 0x00e9 # macro +regBIF_BX0_BIF_SCRATCH1_BASE_IDX = 2 # macro +regBIF_BX0_BX_RESET_EN = 0x00ed # macro +regBIF_BX0_BX_RESET_EN_BASE_IDX = 2 # macro +regBIF_BX0_MM_CFGREGS_CNTL = 0x00ee # macro +regBIF_BX0_MM_CFGREGS_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BX_RESET_CNTL = 0x00f0 # macro +regBIF_BX0_BX_RESET_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_INTERRUPT_CNTL = 0x00f1 # macro +regBIF_BX0_INTERRUPT_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_INTERRUPT_CNTL2 = 0x00f2 # macro +regBIF_BX0_INTERRUPT_CNTL2_BASE_IDX = 2 # macro +regBIF_BX0_CLKREQB_PAD_CNTL = 0x00f8 # macro +regBIF_BX0_CLKREQB_PAD_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BIF_FEATURES_CONTROL_MISC = 0x00fb # macro +regBIF_BX0_BIF_FEATURES_CONTROL_MISC_BASE_IDX = 2 # macro +regBIF_BX0_HDP_ATOMIC_CONTROL_MISC = 0x00fc # macro +regBIF_BX0_HDP_ATOMIC_CONTROL_MISC_BASE_IDX = 2 # macro +regBIF_BX0_BIF_DOORBELL_CNTL = 0x00fd # macro +regBIF_BX0_BIF_DOORBELL_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BIF_DOORBELL_INT_CNTL = 0x00fe # macro +regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BIF_FB_EN = 0x0100 # macro +regBIF_BX0_BIF_FB_EN_BASE_IDX = 2 # macro +regBIF_BX0_BIF_INTR_CNTL = 0x0101 # macro +regBIF_BX0_BIF_INTR_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BIF_MST_TRANS_PENDING_VF = 0x0109 # macro +regBIF_BX0_BIF_MST_TRANS_PENDING_VF_BASE_IDX = 2 # macro +regBIF_BX0_BIF_SLV_TRANS_PENDING_VF = 0x010a # macro +regBIF_BX0_BIF_SLV_TRANS_PENDING_VF_BASE_IDX = 2 # macro +regBIF_BX0_BACO_CNTL = 0x010b # macro +regBIF_BX0_BACO_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BIF_BACO_EXIT_TIME0 = 0x010c # macro +regBIF_BX0_BIF_BACO_EXIT_TIME0_BASE_IDX = 2 # macro +regBIF_BX0_BIF_BACO_EXIT_TIMER1 = 0x010d # macro +regBIF_BX0_BIF_BACO_EXIT_TIMER1_BASE_IDX = 2 # macro +regBIF_BX0_BIF_BACO_EXIT_TIMER2 = 0x010e # macro +regBIF_BX0_BIF_BACO_EXIT_TIMER2_BASE_IDX = 2 # macro +regBIF_BX0_BIF_BACO_EXIT_TIMER3 = 0x010f # macro +regBIF_BX0_BIF_BACO_EXIT_TIMER3_BASE_IDX = 2 # macro +regBIF_BX0_BIF_BACO_EXIT_TIMER4 = 0x0110 # macro +regBIF_BX0_BIF_BACO_EXIT_TIMER4_BASE_IDX = 2 # macro +regBIF_BX0_MEM_TYPE_CNTL = 0x0111 # macro +regBIF_BX0_MEM_TYPE_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL = 0x0113 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_0 = 0x0114 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_0_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_1 = 0x0115 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_1_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_2 = 0x0116 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_2_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_3 = 0x0117 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_3_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_4 = 0x0118 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_4_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_5 = 0x0119 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_5_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_6 = 0x011a # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_6_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_7 = 0x011b # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_7_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_8 = 0x011c # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_8_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_9 = 0x011d # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_9_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_10 = 0x011e # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_10_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_11 = 0x011f # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_11_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_12 = 0x0120 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_12_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_13 = 0x0121 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_13_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_14 = 0x0122 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_14_BASE_IDX = 2 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_15 = 0x0123 # macro +regBIF_BX0_NBIF_GFX_ADDR_LUT_15_BASE_IDX = 2 # macro +regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL = 0x012d # macro +regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL = 0x012e # macro +regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BIF_RB_CNTL = 0x012f # macro +regBIF_BX0_BIF_RB_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BIF_RB_BASE = 0x0130 # macro +regBIF_BX0_BIF_RB_BASE_BASE_IDX = 2 # macro +regBIF_BX0_BIF_RB_RPTR = 0x0131 # macro +regBIF_BX0_BIF_RB_RPTR_BASE_IDX = 2 # macro +regBIF_BX0_BIF_RB_WPTR = 0x0132 # macro +regBIF_BX0_BIF_RB_WPTR_BASE_IDX = 2 # macro +regBIF_BX0_BIF_RB_WPTR_ADDR_HI = 0x0133 # macro +regBIF_BX0_BIF_RB_WPTR_ADDR_HI_BASE_IDX = 2 # macro +regBIF_BX0_BIF_RB_WPTR_ADDR_LO = 0x0134 # macro +regBIF_BX0_BIF_RB_WPTR_ADDR_LO_BASE_IDX = 2 # macro +regBIF_BX0_MAILBOX_INDEX = 0x0135 # macro +regBIF_BX0_MAILBOX_INDEX_BASE_IDX = 2 # macro +regBIF_BX0_BIF_MP1_INTR_CTRL = 0x0142 # macro +regBIF_BX0_BIF_MP1_INTR_CTRL_BASE_IDX = 2 # macro +regBIF_BX0_BIF_PERSTB_PAD_CNTL = 0x0146 # macro +regBIF_BX0_BIF_PERSTB_PAD_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BIF_PX_EN_PAD_CNTL = 0x0147 # macro +regBIF_BX0_BIF_PX_EN_PAD_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BIF_REFPADKIN_PAD_CNTL = 0x0148 # macro +regBIF_BX0_BIF_REFPADKIN_PAD_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BIF_CLKREQB_PAD_CNTL = 0x0149 # macro +regBIF_BX0_BIF_CLKREQB_PAD_CNTL_BASE_IDX = 2 # macro +regBIF_BX0_BIF_PWRBRK_PAD_CNTL = 0x014a # macro +regBIF_BX0_BIF_PWRBRK_PAD_CNTL_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_ERR_INT_CNTL = 0x0086 # macro +regRCC_DEV0_0_RCC_ERR_INT_CNTL_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_BACO_CNTL_MISC = 0x0087 # macro +regRCC_DEV0_0_RCC_BACO_CNTL_MISC_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_RESET_EN = 0x0088 # macro +regRCC_DEV0_0_RCC_RESET_EN_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_VDM_SUPPORT = 0x0089 # macro +regRCC_DEV0_0_RCC_VDM_SUPPORT_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 = 0x008a # macro +regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 = 0x008b # macro +regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_GPUIOV_REGION = 0x008c # macro +regRCC_DEV0_0_RCC_GPUIOV_REGION_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_GPU_HOSTVM_EN = 0x008d # macro +regRCC_DEV0_0_RCC_GPU_HOSTVM_EN_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL = 0x008e # macro +regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET = 0x008f # macro +regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE = 0x008f # macro +regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_PEER_REG_RANGE0 = 0x00be # macro +regRCC_DEV0_0_RCC_PEER_REG_RANGE0_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_PEER_REG_RANGE1 = 0x00bf # macro +regRCC_DEV0_0_RCC_PEER_REG_RANGE1_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_BUS_CNTL = 0x00c1 # macro +regRCC_DEV0_0_RCC_BUS_CNTL_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_CONFIG_CNTL = 0x00c2 # macro +regRCC_DEV0_0_RCC_CONFIG_CNTL_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_CONFIG_F0_BASE = 0x00c6 # macro +regRCC_DEV0_0_RCC_CONFIG_F0_BASE_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_CONFIG_APER_SIZE = 0x00c7 # macro +regRCC_DEV0_0_RCC_CONFIG_APER_SIZE_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE = 0x00c8 # macro +regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_XDMA_LO = 0x00c9 # macro +regRCC_DEV0_0_RCC_XDMA_LO_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_XDMA_HI = 0x00ca # macro +regRCC_DEV0_0_RCC_XDMA_HI_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC = 0x00cb # macro +regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_BUSNUM_CNTL1 = 0x00cc # macro +regRCC_DEV0_0_RCC_BUSNUM_CNTL1_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_BUSNUM_LIST0 = 0x00cd # macro +regRCC_DEV0_0_RCC_BUSNUM_LIST0_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_BUSNUM_LIST1 = 0x00ce # macro +regRCC_DEV0_0_RCC_BUSNUM_LIST1_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_BUSNUM_CNTL2 = 0x00cf # macro +regRCC_DEV0_0_RCC_BUSNUM_CNTL2_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM = 0x00d0 # macro +regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_HOST_BUSNUM = 0x00d1 # macro +regRCC_DEV0_0_RCC_HOST_BUSNUM_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI = 0x00d2 # macro +regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO = 0x00d3 # macro +regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI = 0x00d4 # macro +regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO = 0x00d5 # macro +regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI = 0x00d6 # macro +regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO = 0x00d7 # macro +regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI = 0x00d8 # macro +regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO = 0x00d9 # macro +regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0 = 0x00da # macro +regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1 = 0x00db # macro +regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_DEV0_LINK_CNTL = 0x00dd # macro +regRCC_DEV0_0_RCC_DEV0_LINK_CNTL_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_CMN_LINK_CNTL = 0x00de # macro +regRCC_DEV0_0_RCC_CMN_LINK_CNTL_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE = 0x00df # macro +regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL = 0x00e0 # macro +regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_BASE_IDX = 2 # macro +regRCC_DEV0_0_RCC_MH_ARB_CNTL = 0x00e1 # macro +regRCC_DEV0_0_RCC_MH_ARB_CNTL_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_GFXMSIX_PBA_BASE_IDX = 4 # macro +regRCC_STRAP0_RCC_BIF_STRAP0 = 0x0000 # macro +regRCC_STRAP0_RCC_BIF_STRAP0_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_BIF_STRAP1 = 0x0001 # macro +regRCC_STRAP0_RCC_BIF_STRAP1_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_BIF_STRAP2 = 0x0002 # macro +regRCC_STRAP0_RCC_BIF_STRAP2_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_BIF_STRAP3 = 0x0003 # macro +regRCC_STRAP0_RCC_BIF_STRAP3_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_BIF_STRAP4 = 0x0004 # macro +regRCC_STRAP0_RCC_BIF_STRAP4_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_BIF_STRAP5 = 0x0005 # macro +regRCC_STRAP0_RCC_BIF_STRAP5_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_BIF_STRAP6 = 0x0006 # macro +regRCC_STRAP0_RCC_BIF_STRAP6_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP0 = 0x0007 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP0_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP1 = 0x0008 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP1_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP10 = 0x0009 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP10_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP11 = 0x000a # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP11_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP12 = 0x000b # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP12_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP13 = 0x000c # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP13_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP14 = 0x000d # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP14_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP2 = 0x000e # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP2_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP3 = 0x000f # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP3_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP4 = 0x0010 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP4_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP5 = 0x0011 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP5_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP6 = 0x0012 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP6_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP7 = 0x0013 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP7_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP8 = 0x0014 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP8_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP9 = 0x0015 # macro +regRCC_STRAP0_RCC_DEV0_PORT_STRAP9_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0 = 0x0016 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1 = 0x0017 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13 = 0x0018 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14 = 0x0019 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15 = 0x001a # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16 = 0x001b # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17 = 0x001c # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18 = 0x001d # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2 = 0x001e # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26 = 0x001f # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3 = 0x0020 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4 = 0x0021 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5 = 0x0022 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8 = 0x0024 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9 = 0x0025 # macro +regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0 = 0x0026 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2 = 0x0032 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20 = 0x0033 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21 = 0x0034 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22 = 0x0035 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23 = 0x0036 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24 = 0x0037 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25 = 0x0038 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3 = 0x0039 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4 = 0x003a # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5 = 0x003b # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6 = 0x003c # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_BASE_IDX = 2 # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7 = 0x003d # macro +regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_BASE_IDX = 2 # macro +regBIF_BX_PF0_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_PF0_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_PF0_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_PF0_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_PF0_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_PF0_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_PF0_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_PF0_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_PF0_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_PF0_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_PF0_PARTITION_COMPUTE_CAP = 0x0161 # macro +regBIF_BX_PF0_PARTITION_COMPUTE_CAP_BASE_IDX = 2 # macro +regBIF_BX_PF0_PARTITION_MEM_CAP = 0x0162 # macro +regBIF_BX_PF0_PARTITION_MEM_CAP_BASE_IDX = 2 # macro +regBIF_BX_PF0_PARTITION_COMPUTE_STATUS = 0x0163 # macro +regBIF_BX_PF0_PARTITION_COMPUTE_STATUS_BASE_IDX = 2 # macro +regBIF_BX_PF0_PARTITION_MEM_STATUS = 0x0164 # macro +regBIF_BX_PF0_PARTITION_MEM_STATUS_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regGDC0_A2S_CNTL_CL0 = 0x0000 # macro +regGDC0_A2S_CNTL_CL0_BASE_IDX = 3 # macro +regGDC0_A2S_CNTL_CL1 = 0x0001 # macro +regGDC0_A2S_CNTL_CL1_BASE_IDX = 3 # macro +regGDC0_A2S_CNTL3_CL0 = 0x0018 # macro +regGDC0_A2S_CNTL3_CL0_BASE_IDX = 3 # macro +regGDC0_A2S_CNTL3_CL1 = 0x0019 # macro +regGDC0_A2S_CNTL3_CL1_BASE_IDX = 3 # macro +regGDC0_A2S_CNTL_SW0 = 0x0030 # macro +regGDC0_A2S_CNTL_SW0_BASE_IDX = 3 # macro +regGDC0_A2S_CNTL_SW1 = 0x0031 # macro +regGDC0_A2S_CNTL_SW1_BASE_IDX = 3 # macro +regGDC0_A2S_CNTL_SW2 = 0x0032 # macro +regGDC0_A2S_CNTL_SW2_BASE_IDX = 3 # macro +regGDC0_A2S_TAG_ALLOC_0 = 0x003d # macro +regGDC0_A2S_TAG_ALLOC_0_BASE_IDX = 3 # macro +regGDC0_A2S_TAG_ALLOC_1 = 0x003e # macro +regGDC0_A2S_TAG_ALLOC_1_BASE_IDX = 3 # macro +regGDC0_A2S_MISC_CNTL = 0x0041 # macro +regGDC0_A2S_MISC_CNTL_BASE_IDX = 3 # macro +regGDC0_SHUB_REGS_IF_CTL = 0x0043 # macro +regGDC0_SHUB_REGS_IF_CTL_BASE_IDX = 3 # macro +regGDC0_NGDC_MGCG_CTRL = 0x004a # macro +regGDC0_NGDC_MGCG_CTRL_BASE_IDX = 3 # macro +regGDC0_NGDC_RESERVED_0 = 0x004b # macro +regGDC0_NGDC_RESERVED_0_BASE_IDX = 3 # macro +regGDC0_NGDC_RESERVED_1 = 0x004c # macro +regGDC0_NGDC_RESERVED_1_BASE_IDX = 3 # macro +regGDC0_NBIF_GFX_DOORBELL_STATUS = 0x004f # macro +regGDC0_NBIF_GFX_DOORBELL_STATUS_BASE_IDX = 3 # macro +regGDC0_ATDMA_MISC_CNTL = 0x005d # macro +regGDC0_ATDMA_MISC_CNTL_BASE_IDX = 3 # macro +regGDC0_S2A_MISC_CNTL = 0x005f # macro +regGDC0_S2A_MISC_CNTL_BASE_IDX = 3 # macro +regGDC0_NGDC_PG_MISC_CTRL = 0x0078 # macro +regGDC0_NGDC_PG_MISC_CTRL_BASE_IDX = 3 # macro +regGDC0_NGDC_PGMST_CTRL = 0x0079 # macro +regGDC0_NGDC_PGMST_CTRL_BASE_IDX = 3 # macro +regGDC0_NGDC_PGSLV_CTRL = 0x007a # macro +regGDC0_NGDC_PGSLV_CTRL_BASE_IDX = 3 # macro +cfgBIF_CFG_DEV0_EPF0_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST = 0x0048 # macro +cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID_W = 0x004c # macro +cfgBIF_CFG_DEV0_EPF0_PMI_CAP_LIST = 0x0050 # macro +cfgBIF_CFG_DEV0_EPF0_PMI_CAP = 0x0052 # macro +cfgBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL = 0x0054 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST = 0x0110 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 = 0x0114 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 = 0x0118 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL = 0x011c # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS = 0x011e # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP = 0x0120 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL = 0x0124 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS = 0x012a # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP = 0x012c # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL = 0x0130 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS = 0x0136 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST = 0x0140 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 = 0x0144 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 = 0x0148 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST = 0x0200 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP = 0x0204 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL = 0x0208 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP = 0x020c # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL = 0x0210 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP = 0x0214 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL = 0x0218 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP = 0x021c # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL = 0x0220 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP = 0x0224 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL = 0x0228 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP = 0x022c # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL = 0x0230 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST = 0x0240 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT = 0x0244 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA = 0x0248 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP = 0x024c # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST = 0x0250 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP = 0x0254 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR = 0x0258 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS = 0x025c # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL = 0x025e # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 = 0x0260 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 = 0x0261 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 = 0x0262 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 = 0x0263 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 = 0x0264 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 = 0x0265 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 = 0x0266 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 = 0x0267 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST = 0x0270 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 = 0x0274 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS = 0x0278 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL = 0x027c # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL = 0x027e # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL = 0x0280 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL = 0x0282 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL = 0x0284 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL = 0x0286 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL = 0x0288 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL = 0x028a # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL = 0x028c # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL = 0x028e # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL = 0x0290 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL = 0x0292 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL = 0x0294 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL = 0x0296 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL = 0x0298 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL = 0x029a # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST = 0x02a0 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP = 0x02a4 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL = 0x02a6 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST = 0x02b0 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CAP = 0x02b4 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL = 0x02b6 # macro +cfgPCIE_PAGE_REQ_ENH_CAP_LIST = 0x02c0 # macro +cfgPCIE_PAGE_REQ_CNTL = 0x02c4 # macro +cfgPCIE_PAGE_REQ_STATUS = 0x02c6 # macro +cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY = 0x02c8 # macro +cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC = 0x02cc # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST = 0x02d0 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP = 0x02d4 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL = 0x02d6 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST = 0x02f0 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CAP = 0x02f4 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL = 0x02f6 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0 = 0x02f8 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1 = 0x02fc # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0 = 0x0300 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1 = 0x0304 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0 = 0x0308 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1 = 0x030c # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0 = 0x0310 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1 = 0x0314 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST = 0x0320 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP = 0x0324 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL = 0x032e # macro +cfgPCIE_SRIOV_ENH_CAP_LIST = 0x0330 # macro +cfgPCIE_SRIOV_CAP = 0x0334 # macro +cfgPCIE_SRIOV_CONTROL = 0x0338 # macro +cfgPCIE_SRIOV_STATUS = 0x033a # macro +cfgPCIE_SRIOV_INITIAL_VFS = 0x033c # macro +cfgPCIE_SRIOV_TOTAL_VFS = 0x033e # macro +cfgPCIE_SRIOV_NUM_VFS = 0x0340 # macro +cfgPCIE_SRIOV_FUNC_DEP_LINK = 0x0342 # macro +cfgPCIE_SRIOV_FIRST_VF_OFFSET = 0x0344 # macro +cfgPCIE_SRIOV_VF_STRIDE = 0x0346 # macro +cfgPCIE_SRIOV_VF_DEVICE_ID = 0x034a # macro +cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE = 0x034c # macro +cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE = 0x0350 # macro +cfgPCIE_SRIOV_VF_BASE_ADDR_0 = 0x0354 # macro +cfgPCIE_SRIOV_VF_BASE_ADDR_1 = 0x0358 # macro +cfgPCIE_SRIOV_VF_BASE_ADDR_2 = 0x035c # macro +cfgPCIE_SRIOV_VF_BASE_ADDR_3 = 0x0360 # macro +cfgPCIE_SRIOV_VF_BASE_ADDR_4 = 0x0364 # macro +cfgPCIE_SRIOV_VF_BASE_ADDR_5 = 0x0368 # macro +cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET = 0x036c # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST = 0x0400 # macro +cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP = 0x0404 # macro +cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS = 0x0408 # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST = 0x0410 # macro +cfgBIF_CFG_DEV0_EPF0_LINK_CAP_16GT = 0x0414 # macro +cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT = 0x0418 # macro +cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT = 0x041c # macro +cfgBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT = 0x0420 # macro +cfgBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT = 0x0424 # macro +cfgBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT = 0x0428 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT = 0x0430 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT = 0x0431 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT = 0x0432 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT = 0x0433 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT = 0x0434 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT = 0x0435 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT = 0x0436 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT = 0x0437 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT = 0x0438 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT = 0x0439 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT = 0x043a # macro +cfgBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT = 0x043b # macro +cfgBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT = 0x043c # macro +cfgBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT = 0x043d # macro +cfgBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT = 0x043e # macro +cfgBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT = 0x043f # macro +cfgBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST = 0x0450 # macro +cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP = 0x0454 # macro +cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS = 0x0456 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL = 0x0458 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS = 0x045a # macro +cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL = 0x045c # macro +cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS = 0x045e # macro +cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL = 0x0460 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS = 0x0462 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL = 0x0464 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS = 0x0466 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL = 0x0468 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS = 0x046a # macro +cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL = 0x046c # macro +cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS = 0x046e # macro +cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL = 0x0470 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS = 0x0472 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL = 0x0474 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS = 0x0476 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL = 0x0478 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS = 0x047a # macro +cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL = 0x047c # macro +cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS = 0x047e # macro +cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL = 0x0480 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS = 0x0482 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL = 0x0484 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS = 0x0486 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL = 0x0488 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS = 0x048a # macro +cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL = 0x048c # macro +cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS = 0x048e # macro +cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL = 0x0490 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS = 0x0492 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL = 0x0494 # macro +cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS = 0x0496 # macro +cfgBIF_CFG_DEV0_EPF0_LINK_CAP_32GT = 0x0504 # macro +cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT = 0x0508 # macro +cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT = 0x050c # macro +cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV = 0x0700 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV = 0x0704 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW = 0x0708 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE = 0x070c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS = 0x0710 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL = 0x0714 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 = 0x0718 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 = 0x071c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 = 0x0720 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT = 0x0724 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB = 0x0728 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION = 0x0730 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE = 0x0734 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB = 0x0738 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB = 0x073c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB = 0x0740 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB = 0x0744 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB = 0x0748 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB = 0x074c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB = 0x0750 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB = 0x0754 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB = 0x0758 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB = 0x075c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB = 0x0760 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB = 0x0764 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB = 0x0768 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB = 0x076c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB = 0x0770 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB = 0x0774 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB = 0x0778 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB = 0x077c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB = 0x0780 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB = 0x0784 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB = 0x0788 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB = 0x078c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB = 0x0790 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB = 0x0794 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB = 0x0798 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB = 0x079c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB = 0x07a0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB = 0x07a4 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB = 0x07a8 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB = 0x07ac # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB = 0x07b0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS = 0x07c0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 = 0x07c4 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 = 0x07c8 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 = 0x07cc # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 = 0x07d0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0 = 0x07f0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1 = 0x07f4 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2 = 0x07f8 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3 = 0x07fc # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4 = 0x0800 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5 = 0x0804 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6 = 0x0808 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7 = 0x080c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8 = 0x0810 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 = 0x0820 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 = 0x0824 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 = 0x0828 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 = 0x082c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 = 0x0830 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 = 0x0834 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 = 0x0838 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 = 0x083c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 = 0x0840 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0 = 0x0850 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1 = 0x0854 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2 = 0x0858 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3 = 0x085c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4 = 0x0860 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5 = 0x0864 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6 = 0x0868 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7 = 0x086c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8 = 0x0870 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0 = 0x0880 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1 = 0x0884 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2 = 0x0888 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3 = 0x088c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4 = 0x0890 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5 = 0x0894 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6 = 0x0898 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7 = 0x089c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8 = 0x08a0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0 = 0x08b0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1 = 0x08b4 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2 = 0x08b8 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3 = 0x08bc # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4 = 0x08c0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5 = 0x08c4 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6 = 0x08c8 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7 = 0x08cc # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8 = 0x08d0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0 = 0x08e0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1 = 0x08e4 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2 = 0x08e8 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3 = 0x08ec # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4 = 0x08f0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5 = 0x08f4 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6 = 0x08f8 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7 = 0x08fc # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8 = 0x0900 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0 = 0x0910 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1 = 0x0914 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2 = 0x0918 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3 = 0x091c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4 = 0x0920 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5 = 0x0924 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6 = 0x0928 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7 = 0x092c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8 = 0x0930 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0 = 0x0940 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1 = 0x0944 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2 = 0x0948 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3 = 0x094c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4 = 0x0950 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5 = 0x0954 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6 = 0x0958 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7 = 0x095c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8 = 0x0960 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0 = 0x0970 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1 = 0x0974 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2 = 0x0978 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3 = 0x097c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4 = 0x0980 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5 = 0x0984 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6 = 0x0988 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7 = 0x098c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8 = 0x0990 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0 = 0x09a0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1 = 0x09a4 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2 = 0x09a8 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3 = 0x09ac # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4 = 0x09b0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5 = 0x09b4 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6 = 0x09b8 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7 = 0x09bc # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8 = 0x09c0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0 = 0x09d0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1 = 0x09d4 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2 = 0x09d8 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3 = 0x09dc # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4 = 0x09e0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5 = 0x09e4 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6 = 0x09e8 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7 = 0x09ec # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8 = 0x09f0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0 = 0x0a00 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1 = 0x0a04 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2 = 0x0a08 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3 = 0x0a0c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4 = 0x0a10 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5 = 0x0a14 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6 = 0x0a18 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7 = 0x0a1c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8 = 0x0a20 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0 = 0x0a30 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1 = 0x0a34 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2 = 0x0a38 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3 = 0x0a3c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4 = 0x0a40 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5 = 0x0a44 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6 = 0x0a48 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7 = 0x0a4c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8 = 0x0a50 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0 = 0x0a60 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1 = 0x0a64 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2 = 0x0a68 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3 = 0x0a6c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4 = 0x0a70 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5 = 0x0a74 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6 = 0x0a78 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7 = 0x0a7c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8 = 0x0a80 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0 = 0x0a90 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1 = 0x0a94 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2 = 0x0a98 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3 = 0x0a9c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4 = 0x0aa0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5 = 0x0aa4 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6 = 0x0aa8 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7 = 0x0aac # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8 = 0x0ab0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0 = 0x0ac0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1 = 0x0ac4 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2 = 0x0ac8 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3 = 0x0acc # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4 = 0x0ad0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5 = 0x0ad4 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6 = 0x0ad8 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7 = 0x0adc # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8 = 0x0ae0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0 = 0x0af0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1 = 0x0af4 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2 = 0x0af8 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3 = 0x0afc # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4 = 0x0b00 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5 = 0x0b04 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6 = 0x0b08 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7 = 0x0b0c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8 = 0x0b10 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0 = 0x0b20 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1 = 0x0b24 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2 = 0x0b28 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3 = 0x0b2c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4 = 0x0b30 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5 = 0x0b34 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6 = 0x0b38 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7 = 0x0b3c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8 = 0x0b40 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0 = 0x0b50 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1 = 0x0b54 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2 = 0x0b58 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3 = 0x0b5c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4 = 0x0b60 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5 = 0x0b64 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6 = 0x0b68 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7 = 0x0b6c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8 = 0x0b70 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0 = 0x0b80 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1 = 0x0b84 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2 = 0x0b88 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3 = 0x0b8c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4 = 0x0b90 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5 = 0x0b94 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6 = 0x0b98 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7 = 0x0b9c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8 = 0x0ba0 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE = 0x0c00 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE = 0x0c04 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE = 0x0c08 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE = 0x0c0c # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS = 0x0c10 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS = 0x0c14 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS = 0x0c18 # macro +cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS = 0x0c1c # macro +cfgBIF_CFG_DEV0_EPF1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST = 0x0048 # macro +cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID_W = 0x004c # macro +cfgBIF_CFG_DEV0_EPF1_PMI_CAP_LIST = 0x0050 # macro +cfgBIF_CFG_DEV0_EPF1_PMI_CAP = 0x0052 # macro +cfgBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL = 0x0054 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST = 0x0200 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP = 0x0204 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL = 0x0208 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP = 0x020c # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL = 0x0210 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP = 0x0214 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL = 0x0218 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP = 0x021c # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL = 0x0220 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP = 0x0224 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL = 0x0228 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP = 0x022c # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL = 0x0230 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST = 0x0240 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT = 0x0244 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA = 0x0248 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP = 0x024c # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST = 0x0250 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP = 0x0254 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR = 0x0258 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS = 0x025c # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL = 0x025e # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 = 0x0260 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 = 0x0261 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 = 0x0262 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 = 0x0263 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 = 0x0264 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 = 0x0265 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 = 0x0266 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 = 0x0267 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST = 0x02a0 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP = 0x02a4 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL = 0x02a6 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST = 0x02d0 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP = 0x02d4 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL = 0x02d6 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL = 0x032e # macro +regBIF_CFG_DEV0_RC0_VENDOR_ID = 0x0000 # macro +regBIF_CFG_DEV0_RC0_VENDOR_ID_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_DEVICE_ID = 0x0000 # macro +regBIF_CFG_DEV0_RC0_DEVICE_ID_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_COMMAND = 0x0001 # macro +regBIF_CFG_DEV0_RC0_COMMAND_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_STATUS = 0x0001 # macro +regBIF_CFG_DEV0_RC0_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_REVISION_ID = 0x0002 # macro +regBIF_CFG_DEV0_RC0_REVISION_ID_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PROG_INTERFACE = 0x0002 # macro +regBIF_CFG_DEV0_RC0_PROG_INTERFACE_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_SUB_CLASS = 0x0002 # macro +regBIF_CFG_DEV0_RC0_SUB_CLASS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_BASE_CLASS = 0x0002 # macro +regBIF_CFG_DEV0_RC0_BASE_CLASS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_CACHE_LINE = 0x0003 # macro +regBIF_CFG_DEV0_RC0_CACHE_LINE_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LATENCY = 0x0003 # macro +regBIF_CFG_DEV0_RC0_LATENCY_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_HEADER = 0x0003 # macro +regBIF_CFG_DEV0_RC0_HEADER_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_BIST = 0x0003 # macro +regBIF_CFG_DEV0_RC0_BIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_BASE_ADDR_1 = 0x0004 # macro +regBIF_CFG_DEV0_RC0_BASE_ADDR_1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_BASE_ADDR_2 = 0x0005 # macro +regBIF_CFG_DEV0_RC0_BASE_ADDR_2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY = 0x0006 # macro +regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT = 0x0007 # macro +regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_SECONDARY_STATUS = 0x0007 # macro +regBIF_CFG_DEV0_RC0_SECONDARY_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT = 0x0008 # macro +regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT = 0x0009 # macro +regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER = 0x000a # macro +regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER = 0x000b # macro +regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI = 0x000c # macro +regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_CAP_PTR = 0x000d # macro +regBIF_CFG_DEV0_RC0_CAP_PTR_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR = 0x000e # macro +regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_INTERRUPT_LINE = 0x000f # macro +regBIF_CFG_DEV0_RC0_INTERRUPT_LINE_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_INTERRUPT_PIN = 0x000f # macro +regBIF_CFG_DEV0_RC0_INTERRUPT_PIN_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL = 0x000f # macro +regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL = 0x0010 # macro +regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PMI_CAP_LIST = 0x0014 # macro +regBIF_CFG_DEV0_RC0_PMI_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PMI_CAP = 0x0014 # macro +regBIF_CFG_DEV0_RC0_PMI_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL = 0x0015 # macro +regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST = 0x0016 # macro +regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_CAP = 0x0016 # macro +regBIF_CFG_DEV0_RC0_PCIE_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_DEVICE_CAP = 0x0017 # macro +regBIF_CFG_DEV0_RC0_DEVICE_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_DEVICE_CNTL = 0x0018 # macro +regBIF_CFG_DEV0_RC0_DEVICE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_DEVICE_STATUS = 0x0018 # macro +regBIF_CFG_DEV0_RC0_DEVICE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LINK_CAP = 0x0019 # macro +regBIF_CFG_DEV0_RC0_LINK_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LINK_CNTL = 0x001a # macro +regBIF_CFG_DEV0_RC0_LINK_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LINK_STATUS = 0x001a # macro +regBIF_CFG_DEV0_RC0_LINK_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_SLOT_CAP = 0x001b # macro +regBIF_CFG_DEV0_RC0_SLOT_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_SLOT_CNTL = 0x001c # macro +regBIF_CFG_DEV0_RC0_SLOT_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_SLOT_STATUS = 0x001c # macro +regBIF_CFG_DEV0_RC0_SLOT_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_ROOT_CNTL = 0x001d # macro +regBIF_CFG_DEV0_RC0_ROOT_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_ROOT_CAP = 0x001d # macro +regBIF_CFG_DEV0_RC0_ROOT_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_ROOT_STATUS = 0x001e # macro +regBIF_CFG_DEV0_RC0_ROOT_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_DEVICE_CAP2 = 0x001f # macro +regBIF_CFG_DEV0_RC0_DEVICE_CAP2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_DEVICE_CNTL2 = 0x0020 # macro +regBIF_CFG_DEV0_RC0_DEVICE_CNTL2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_DEVICE_STATUS2 = 0x0020 # macro +regBIF_CFG_DEV0_RC0_DEVICE_STATUS2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LINK_CAP2 = 0x0021 # macro +regBIF_CFG_DEV0_RC0_LINK_CAP2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LINK_CNTL2 = 0x0022 # macro +regBIF_CFG_DEV0_RC0_LINK_CNTL2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LINK_STATUS2 = 0x0022 # macro +regBIF_CFG_DEV0_RC0_LINK_STATUS2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_SLOT_CAP2 = 0x0023 # macro +regBIF_CFG_DEV0_RC0_SLOT_CAP2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_SLOT_CNTL2 = 0x0024 # macro +regBIF_CFG_DEV0_RC0_SLOT_CNTL2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_SLOT_STATUS2 = 0x0024 # macro +regBIF_CFG_DEV0_RC0_SLOT_STATUS2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_MSI_CAP_LIST = 0x0028 # macro +regBIF_CFG_DEV0_RC0_MSI_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL = 0x0028 # macro +regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO = 0x0029 # macro +regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI = 0x002a # macro +regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_MSI_MSG_DATA = 0x002a # macro +regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA = 0x002a # macro +regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 = 0x002b # macro +regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64 = 0x002b # macro +regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_SSID_CAP_LIST = 0x0030 # macro +regBIF_CFG_DEV0_RC0_SSID_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_SSID_CAP = 0x0031 # macro +regBIF_CFG_DEV0_RC0_SSID_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0040 # macro +regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR = 0x0041 # macro +regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 = 0x0042 # macro +regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 = 0x0043 # macro +regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST = 0x0044 # macro +regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 = 0x0045 # macro +regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 = 0x0046 # macro +regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL = 0x0047 # macro +regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS = 0x0047 # macro +regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP = 0x0048 # macro +regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL = 0x0049 # macro +regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS = 0x004a # macro +regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP = 0x004b # macro +regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL = 0x004c # macro +regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS = 0x004d # macro +regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST = 0x0050 # macro +regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 = 0x0051 # macro +regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 = 0x0052 # macro +regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0054 # macro +regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS = 0x0055 # macro +regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK = 0x0056 # macro +regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY = 0x0057 # macro +regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS = 0x0058 # macro +regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK = 0x0059 # macro +regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL = 0x005a # macro +regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 = 0x005b # macro +regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 = 0x005c # macro +regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 = 0x005d # macro +regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 = 0x005e # macro +regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD = 0x005f # macro +regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS = 0x0060 # macro +regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID = 0x0061 # macro +regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 = 0x0062 # macro +regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 = 0x0063 # macro +regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 = 0x0064 # macro +regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 = 0x0065 # macro +regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST = 0x009c # macro +regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 = 0x009d # macro +regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS = 0x009e # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL = 0x009f # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL = 0x009f # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL = 0x00a0 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL = 0x00a0 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL = 0x00a1 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL = 0x00a1 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL = 0x00a2 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL = 0x00a2 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL = 0x00a3 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL = 0x00a3 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL = 0x00a4 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL = 0x00a4 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL = 0x00a5 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL = 0x00a5 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL = 0x00a6 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL = 0x00a6 # macro +regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST = 0x00a8 # macro +regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP = 0x00a9 # macro +regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL = 0x00a9 # macro +regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST = 0x0100 # macro +regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP = 0x0101 # macro +regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS = 0x0102 # macro +regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST = 0x0104 # macro +regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LINK_CAP_16GT = 0x0105 # macro +regBIF_CFG_DEV0_RC0_LINK_CAP_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT = 0x0106 # macro +regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT = 0x0107 # macro +regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT = 0x0108 # macro +regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT = 0x0109 # macro +regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT = 0x010a # macro +regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT = 0x010c # macro +regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT = 0x010c # macro +regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT = 0x010c # macro +regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT = 0x010c # macro +regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT = 0x010d # macro +regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT = 0x010d # macro +regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT = 0x010d # macro +regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT = 0x010d # macro +regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT = 0x010e # macro +regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT = 0x010e # macro +regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT = 0x010e # macro +regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT = 0x010e # macro +regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT = 0x010f # macro +regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT = 0x010f # macro +regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT = 0x010f # macro +regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT = 0x010f # macro +regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST = 0x0114 # macro +regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP = 0x0115 # macro +regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS = 0x0115 # macro +regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL = 0x0116 # macro +regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS = 0x0116 # macro +regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL = 0x0117 # macro +regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS = 0x0117 # macro +regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL = 0x0118 # macro +regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS = 0x0118 # macro +regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL = 0x0119 # macro +regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS = 0x0119 # macro +regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL = 0x011a # macro +regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS = 0x011a # macro +regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL = 0x011b # macro +regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS = 0x011b # macro +regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL = 0x011c # macro +regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS = 0x011c # macro +regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL = 0x011d # macro +regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS = 0x011d # macro +regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL = 0x011e # macro +regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS = 0x011e # macro +regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL = 0x011f # macro +regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS = 0x011f # macro +regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL = 0x0120 # macro +regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS = 0x0120 # macro +regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL = 0x0121 # macro +regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS = 0x0121 # macro +regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL = 0x0122 # macro +regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS = 0x0122 # macro +regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL = 0x0123 # macro +regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS = 0x0123 # macro +regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL = 0x0124 # macro +regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS = 0x0124 # macro +regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL = 0x0125 # macro +regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS = 0x0125 # macro +regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LINK_CAP_32GT = 0x0141 # macro +regBIF_CFG_DEV0_RC0_LINK_CAP_32GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LINK_CNTL_32GT = 0x0142 # macro +regBIF_CFG_DEV0_RC0_LINK_CNTL_32GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_RC0_LINK_STATUS_32GT = 0x0143 # macro +regBIF_CFG_DEV0_RC0_LINK_STATUS_32GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_VENDOR_ID = 0x10000 # macro +regBIF_CFG_DEV0_EPF0_0_VENDOR_ID_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_DEVICE_ID = 0x10000 # macro +regBIF_CFG_DEV0_EPF0_0_DEVICE_ID_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_COMMAND = 0x10001 # macro +regBIF_CFG_DEV0_EPF0_0_COMMAND_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_STATUS = 0x10001 # macro +regBIF_CFG_DEV0_EPF0_0_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_REVISION_ID = 0x10002 # macro +regBIF_CFG_DEV0_EPF0_0_REVISION_ID_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE = 0x10002 # macro +regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_SUB_CLASS = 0x10002 # macro +regBIF_CFG_DEV0_EPF0_0_SUB_CLASS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_BASE_CLASS = 0x10002 # macro +regBIF_CFG_DEV0_EPF0_0_BASE_CLASS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_CACHE_LINE = 0x10003 # macro +regBIF_CFG_DEV0_EPF0_0_CACHE_LINE_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LATENCY = 0x10003 # macro +regBIF_CFG_DEV0_EPF0_0_LATENCY_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_HEADER = 0x10003 # macro +regBIF_CFG_DEV0_EPF0_0_HEADER_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_BIST = 0x10003 # macro +regBIF_CFG_DEV0_EPF0_0_BIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 = 0x10004 # macro +regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 = 0x10005 # macro +regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 = 0x10006 # macro +regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 = 0x10007 # macro +regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 = 0x10008 # macro +regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 = 0x10009 # macro +regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR = 0x1000a # macro +regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID = 0x1000b # macro +regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR = 0x1000c # macro +regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_CAP_PTR = 0x1000d # macro +regBIF_CFG_DEV0_EPF0_0_CAP_PTR_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE = 0x1000f # macro +regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN = 0x1000f # macro +regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_MIN_GRANT = 0x1000f # macro +regBIF_CFG_DEV0_EPF0_0_MIN_GRANT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY = 0x1000f # macro +regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST = 0x10012 # macro +regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W = 0x10013 # macro +regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST = 0x10014 # macro +regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PMI_CAP = 0x10014 # macro +regBIF_CFG_DEV0_EPF0_0_PMI_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL = 0x10015 # macro +regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST = 0x10019 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_CAP = 0x10019 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP = 0x1001a # macro +regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL = 0x1001b # macro +regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS = 0x1001b # macro +regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LINK_CAP = 0x1001c # macro +regBIF_CFG_DEV0_EPF0_0_LINK_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LINK_CNTL = 0x1001d # macro +regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LINK_STATUS = 0x1001d # macro +regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 = 0x10022 # macro +regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 = 0x10023 # macro +regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 = 0x10023 # macro +regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LINK_CAP2 = 0x10024 # macro +regBIF_CFG_DEV0_EPF0_0_LINK_CAP2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 = 0x10025 # macro +regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 = 0x10025 # macro +regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST = 0x10028 # macro +regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL = 0x10028 # macro +regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO = 0x10029 # macro +regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI = 0x1002a # macro +regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA = 0x1002a # macro +regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA = 0x1002a # macro +regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_MSI_MASK = 0x1002b # macro +regBIF_CFG_DEV0_EPF0_0_MSI_MASK_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 = 0x1002b # macro +regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64 = 0x1002b # macro +regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 = 0x1002c # macro +regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_MSI_PENDING = 0x1002c # macro +regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 = 0x1002d # macro +regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST = 0x10030 # macro +regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL = 0x10030 # macro +regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE = 0x10031 # macro +regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_MSIX_PBA = 0x10032 # macro +regBIF_CFG_DEV0_EPF0_0_MSIX_PBA_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x10040 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR = 0x10041 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 = 0x10042 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 = 0x10043 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST = 0x10044 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 = 0x10045 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 = 0x10046 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL = 0x10047 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS = 0x10047 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP = 0x10048 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL = 0x10049 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS = 0x1004a # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP = 0x1004b # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL = 0x1004c # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS = 0x1004d # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST = 0x10050 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 = 0x10051 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 = 0x10052 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x10054 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS = 0x10055 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK = 0x10056 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY = 0x10057 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS = 0x10058 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK = 0x10059 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL = 0x1005a # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 = 0x1005b # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 = 0x1005c # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 = 0x1005d # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 = 0x1005e # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 = 0x10062 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 = 0x10063 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 = 0x10064 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 = 0x10065 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST = 0x10080 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP = 0x10081 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL = 0x10082 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP = 0x10083 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL = 0x10084 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP = 0x10085 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL = 0x10086 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP = 0x10087 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL = 0x10088 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP = 0x10089 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL = 0x1008a # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP = 0x1008b # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL = 0x1008c # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST = 0x10090 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT = 0x10091 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA = 0x10092 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP = 0x10093 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST = 0x10094 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP = 0x10095 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR = 0x10096 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS = 0x10097 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL = 0x10097 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 = 0x10098 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 = 0x10098 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 = 0x10098 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 = 0x10098 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 = 0x10099 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 = 0x10099 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 = 0x10099 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 = 0x10099 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST = 0x1009c # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 = 0x1009d # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS = 0x1009e # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL = 0x1009f # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL = 0x1009f # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL = 0x100a0 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL = 0x100a0 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL = 0x100a1 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL = 0x100a1 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL = 0x100a2 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL = 0x100a2 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL = 0x100a3 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL = 0x100a3 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL = 0x100a4 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL = 0x100a4 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL = 0x100a5 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL = 0x100a5 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL = 0x100a6 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL = 0x100a6 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST = 0x100a8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP = 0x100a9 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL = 0x100a9 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST = 0x100ac # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP = 0x100ad # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL = 0x100ad # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST = 0x100b0 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL = 0x100b1 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS = 0x100b1 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY = 0x100b2 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC = 0x100b3 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST = 0x100b4 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP = 0x100b5 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL = 0x100b5 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST = 0x100bc # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP = 0x100bd # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL = 0x100bd # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 = 0x100be # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 = 0x100bf # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 = 0x100c0 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 = 0x100c1 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 = 0x100c2 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 = 0x100c3 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 = 0x100c4 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 = 0x100c5 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST = 0x100c8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP = 0x100c9 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST = 0x100ca # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP = 0x100cb # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL = 0x100cb # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST = 0x100cc # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP = 0x100cd # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL = 0x100ce # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS = 0x100ce # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS = 0x100cf # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS = 0x100cf # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS = 0x100d0 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK = 0x100d0 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET = 0x100d1 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE = 0x100d1 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID = 0x100d2 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE = 0x100d3 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE = 0x100d4 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 = 0x100d5 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 = 0x100d6 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 = 0x100d7 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 = 0x100d8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 = 0x100d9 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 = 0x100da # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET = 0x100db # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST = 0x10100 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP = 0x10101 # macro +regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS = 0x10102 # macro +regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST = 0x10104 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT = 0x10105 # macro +regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT = 0x10106 # macro +regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT = 0x10107 # macro +regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT = 0x10108 # macro +regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT = 0x10109 # macro +regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT = 0x1010a # macro +regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT = 0x1010c # macro +regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT = 0x1010c # macro +regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT = 0x1010c # macro +regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT = 0x1010c # macro +regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT = 0x1010d # macro +regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT = 0x1010d # macro +regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT = 0x1010d # macro +regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT = 0x1010d # macro +regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT = 0x1010e # macro +regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT = 0x1010e # macro +regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT = 0x1010e # macro +regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT = 0x1010e # macro +regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT = 0x1010f # macro +regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT = 0x1010f # macro +regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT = 0x1010f # macro +regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT = 0x1010f # macro +regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST = 0x10114 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP = 0x10115 # macro +regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS = 0x10115 # macro +regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL = 0x10116 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS = 0x10116 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL = 0x10117 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS = 0x10117 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL = 0x10118 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS = 0x10118 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL = 0x10119 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS = 0x10119 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL = 0x1011a # macro +regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS = 0x1011a # macro +regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL = 0x1011b # macro +regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS = 0x1011b # macro +regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL = 0x1011c # macro +regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS = 0x1011c # macro +regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL = 0x1011d # macro +regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS = 0x1011d # macro +regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL = 0x1011e # macro +regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS = 0x1011e # macro +regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL = 0x1011f # macro +regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS = 0x1011f # macro +regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL = 0x10120 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS = 0x10120 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL = 0x10121 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS = 0x10121 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL = 0x10122 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS = 0x10122 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL = 0x10123 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS = 0x10123 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL = 0x10124 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS = 0x10124 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL = 0x10125 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS = 0x10125 # macro +regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT = 0x10141 # macro +regBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT = 0x10142 # macro +regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT = 0x10143 # macro +regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV = 0x101c0 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV = 0x101c1 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW = 0x101c2 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE = 0x101c3 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS = 0x101c4 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL = 0x101c5 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 = 0x101c6 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 = 0x101c7 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 = 0x101c8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT = 0x101c9 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB = 0x101ca # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION = 0x101cc # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE = 0x101cd # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB = 0x101ce # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB = 0x101cf # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB = 0x101d0 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB = 0x101d1 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB = 0x101d2 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB = 0x101d3 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB = 0x101d4 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB = 0x101d5 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB = 0x101d6 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB = 0x101d7 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB = 0x101d8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB = 0x101d9 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB = 0x101da # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB = 0x101db # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB = 0x101dc # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB = 0x101dd # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB = 0x101de # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB = 0x101df # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB = 0x101e0 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB = 0x101e1 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB = 0x101e2 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB = 0x101e3 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB = 0x101e4 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB = 0x101e5 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB = 0x101e6 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB = 0x101e7 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB = 0x101e8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB = 0x101e9 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB = 0x101ea # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB = 0x101eb # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB = 0x101ec # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS = 0x101f0 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 = 0x101f1 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 = 0x101f2 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 = 0x101f3 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 = 0x101f4 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0 = 0x101fc # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1 = 0x101fd # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2 = 0x101fe # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3 = 0x101ff # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4 = 0x10200 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5 = 0x10201 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6 = 0x10202 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7 = 0x10203 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8 = 0x10204 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 = 0x10208 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 = 0x10209 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 = 0x1020a # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 = 0x1020b # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 = 0x1020c # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 = 0x1020d # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 = 0x1020e # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 = 0x1020f # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 = 0x10210 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0 = 0x10214 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1 = 0x10215 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2 = 0x10216 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3 = 0x10217 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4 = 0x10218 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5 = 0x10219 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6 = 0x1021a # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7 = 0x1021b # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8 = 0x1021c # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0 = 0x10220 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1 = 0x10221 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2 = 0x10222 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3 = 0x10223 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4 = 0x10224 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5 = 0x10225 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6 = 0x10226 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7 = 0x10227 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8 = 0x10228 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0 = 0x1022c # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1 = 0x1022d # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2 = 0x1022e # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3 = 0x1022f # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4 = 0x10230 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5 = 0x10231 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6 = 0x10232 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7 = 0x10233 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8 = 0x10234 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0 = 0x10238 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1 = 0x10239 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2 = 0x1023a # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3 = 0x1023b # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4 = 0x1023c # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5 = 0x1023d # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6 = 0x1023e # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7 = 0x1023f # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8 = 0x10240 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0 = 0x10244 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1 = 0x10245 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2 = 0x10246 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3 = 0x10247 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4 = 0x10248 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5 = 0x10249 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6 = 0x1024a # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7 = 0x1024b # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8 = 0x1024c # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0 = 0x10250 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1 = 0x10251 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2 = 0x10252 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3 = 0x10253 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4 = 0x10254 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5 = 0x10255 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6 = 0x10256 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7 = 0x10257 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8 = 0x10258 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0 = 0x1025c # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1 = 0x1025d # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2 = 0x1025e # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3 = 0x1025f # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4 = 0x10260 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5 = 0x10261 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6 = 0x10262 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7 = 0x10263 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8 = 0x10264 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0 = 0x10268 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1 = 0x10269 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2 = 0x1026a # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3 = 0x1026b # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4 = 0x1026c # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5 = 0x1026d # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6 = 0x1026e # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7 = 0x1026f # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8 = 0x10270 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0 = 0x10274 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1 = 0x10275 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2 = 0x10276 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3 = 0x10277 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4 = 0x10278 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5 = 0x10279 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6 = 0x1027a # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7 = 0x1027b # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8 = 0x1027c # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0 = 0x10280 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1 = 0x10281 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2 = 0x10282 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3 = 0x10283 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4 = 0x10284 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5 = 0x10285 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6 = 0x10286 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7 = 0x10287 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8 = 0x10288 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0 = 0x1028c # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1 = 0x1028d # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2 = 0x1028e # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3 = 0x1028f # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4 = 0x10290 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5 = 0x10291 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6 = 0x10292 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7 = 0x10293 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8 = 0x10294 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0 = 0x10298 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1 = 0x10299 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2 = 0x1029a # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3 = 0x1029b # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4 = 0x1029c # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5 = 0x1029d # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6 = 0x1029e # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7 = 0x1029f # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8 = 0x102a0 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0 = 0x102a4 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1 = 0x102a5 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2 = 0x102a6 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3 = 0x102a7 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4 = 0x102a8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5 = 0x102a9 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6 = 0x102aa # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7 = 0x102ab # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8 = 0x102ac # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0 = 0x102b0 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1 = 0x102b1 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2 = 0x102b2 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3 = 0x102b3 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4 = 0x102b4 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5 = 0x102b5 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6 = 0x102b6 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7 = 0x102b7 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8 = 0x102b8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0 = 0x102bc # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1 = 0x102bd # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2 = 0x102be # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3 = 0x102bf # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4 = 0x102c0 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5 = 0x102c1 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6 = 0x102c2 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7 = 0x102c3 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8 = 0x102c4 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0 = 0x102c8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1 = 0x102c9 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2 = 0x102ca # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3 = 0x102cb # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4 = 0x102cc # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5 = 0x102cd # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6 = 0x102ce # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7 = 0x102cf # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8 = 0x102d0 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0 = 0x102d4 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1 = 0x102d5 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2 = 0x102d6 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3 = 0x102d7 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4 = 0x102d8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5 = 0x102d9 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6 = 0x102da # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7 = 0x102db # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8 = 0x102dc # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0 = 0x102e0 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1 = 0x102e1 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2 = 0x102e2 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3 = 0x102e3 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4 = 0x102e4 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5 = 0x102e5 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6 = 0x102e6 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7 = 0x102e7 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8 = 0x102e8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE = 0x10300 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE = 0x10301 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE = 0x10302 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE = 0x10303 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS = 0x10304 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS = 0x10305 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS = 0x10306 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS = 0x10307 # macro +regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_VENDOR_ID = 0x10400 # macro +regBIF_CFG_DEV0_EPF1_0_VENDOR_ID_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_DEVICE_ID = 0x10400 # macro +regBIF_CFG_DEV0_EPF1_0_DEVICE_ID_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_COMMAND = 0x10401 # macro +regBIF_CFG_DEV0_EPF1_0_COMMAND_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_STATUS = 0x10401 # macro +regBIF_CFG_DEV0_EPF1_0_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_REVISION_ID = 0x10402 # macro +regBIF_CFG_DEV0_EPF1_0_REVISION_ID_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE = 0x10402 # macro +regBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_SUB_CLASS = 0x10402 # macro +regBIF_CFG_DEV0_EPF1_0_SUB_CLASS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_BASE_CLASS = 0x10402 # macro +regBIF_CFG_DEV0_EPF1_0_BASE_CLASS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_CACHE_LINE = 0x10403 # macro +regBIF_CFG_DEV0_EPF1_0_CACHE_LINE_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_LATENCY = 0x10403 # macro +regBIF_CFG_DEV0_EPF1_0_LATENCY_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_HEADER = 0x10403 # macro +regBIF_CFG_DEV0_EPF1_0_HEADER_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_BIST = 0x10403 # macro +regBIF_CFG_DEV0_EPF1_0_BIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 = 0x10404 # macro +regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 = 0x10405 # macro +regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 = 0x10406 # macro +regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 = 0x10407 # macro +regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 = 0x10408 # macro +regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 = 0x10409 # macro +regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR = 0x1040a # macro +regBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID = 0x1040b # macro +regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR = 0x1040c # macro +regBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_CAP_PTR = 0x1040d # macro +regBIF_CFG_DEV0_EPF1_0_CAP_PTR_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE = 0x1040f # macro +regBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN = 0x1040f # macro +regBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_MIN_GRANT = 0x1040f # macro +regBIF_CFG_DEV0_EPF1_0_MIN_GRANT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_MAX_LATENCY = 0x1040f # macro +regBIF_CFG_DEV0_EPF1_0_MAX_LATENCY_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST = 0x10412 # macro +regBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W = 0x10413 # macro +regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST = 0x10414 # macro +regBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PMI_CAP = 0x10414 # macro +regBIF_CFG_DEV0_EPF1_0_PMI_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL = 0x10415 # macro +regBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST = 0x10419 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_CAP = 0x10419 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP = 0x1041a # macro +regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL = 0x1041b # macro +regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS = 0x1041b # macro +regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_LINK_CAP = 0x1041c # macro +regBIF_CFG_DEV0_EPF1_0_LINK_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_LINK_CNTL = 0x1041d # macro +regBIF_CFG_DEV0_EPF1_0_LINK_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_LINK_STATUS = 0x1041d # macro +regBIF_CFG_DEV0_EPF1_0_LINK_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 = 0x10422 # macro +regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 = 0x10423 # macro +regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 = 0x10423 # macro +regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_LINK_CAP2 = 0x10424 # macro +regBIF_CFG_DEV0_EPF1_0_LINK_CAP2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 = 0x10425 # macro +regBIF_CFG_DEV0_EPF1_0_LINK_CNTL2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 = 0x10425 # macro +regBIF_CFG_DEV0_EPF1_0_LINK_STATUS2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST = 0x10428 # macro +regBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL = 0x10428 # macro +regBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO = 0x10429 # macro +regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI = 0x1042a # macro +regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA = 0x1042a # macro +regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA = 0x1042a # macro +regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_MSI_MASK = 0x1042b # macro +regBIF_CFG_DEV0_EPF1_0_MSI_MASK_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 = 0x1042b # macro +regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64 = 0x1042b # macro +regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 = 0x1042c # macro +regBIF_CFG_DEV0_EPF1_0_MSI_MASK_64_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_MSI_PENDING = 0x1042c # macro +regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 = 0x1042d # macro +regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST = 0x10430 # macro +regBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL = 0x10430 # macro +regBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_MSIX_TABLE = 0x10431 # macro +regBIF_CFG_DEV0_EPF1_0_MSIX_TABLE_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_MSIX_PBA = 0x10432 # macro +regBIF_CFG_DEV0_EPF1_0_MSIX_PBA_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x10440 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR = 0x10441 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 = 0x10442 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 = 0x10443 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x10454 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS = 0x10455 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK = 0x10456 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY = 0x10457 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS = 0x10458 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK = 0x10459 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL = 0x1045a # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 = 0x1045b # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 = 0x1045c # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 = 0x1045d # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 = 0x1045e # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 = 0x10462 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 = 0x10463 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 = 0x10464 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 = 0x10465 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST = 0x10480 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP = 0x10481 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL = 0x10482 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP = 0x10483 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL = 0x10484 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP = 0x10485 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL = 0x10486 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP = 0x10487 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL = 0x10488 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP = 0x10489 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL = 0x1048a # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP = 0x1048b # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL = 0x1048c # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST = 0x10490 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT = 0x10491 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA = 0x10492 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP = 0x10493 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST = 0x10494 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP = 0x10495 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR = 0x10496 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS = 0x10497 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL = 0x10497 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 = 0x10498 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 = 0x10498 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 = 0x10498 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 = 0x10498 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 = 0x10499 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 = 0x10499 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 = 0x10499 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 = 0x10499 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST = 0x104a8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP = 0x104a9 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL = 0x104a9 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST = 0x104b4 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP = 0x104b5 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL = 0x104b5 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST = 0x104ca # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP = 0x104cb # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP_BASE_IDX = 8 # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL = 0x104cb # macro +regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_VDM_SUPPORT = 0xc440 # macro +regRCC_DEV0_1_RCC_VDM_SUPPORT_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_BUS_CNTL = 0xc441 # macro +regRCC_DEV0_1_RCC_BUS_CNTL_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC = 0xc442 # macro +regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_DEV0_LINK_CNTL = 0xc443 # macro +regRCC_DEV0_1_RCC_DEV0_LINK_CNTL_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_CMN_LINK_CNTL = 0xc444 # macro +regRCC_DEV0_1_RCC_CMN_LINK_CNTL_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE = 0xc445 # macro +regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL = 0xc446 # macro +regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_MH_ARB_CNTL = 0xc447 # macro +regRCC_DEV0_1_RCC_MH_ARB_CNTL_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 = 0xc448 # macro +regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 = 0xc449 # macro +regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_EP_PCIE_SCRATCH = 0xc44c # macro +regRCC_EP_DEV0_1_EP_PCIE_SCRATCH_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_EP_PCIE_CNTL = 0xc44e # macro +regRCC_EP_DEV0_1_EP_PCIE_CNTL_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL = 0xc44f # macro +regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS = 0xc450 # macro +regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 = 0xc451 # macro +regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL = 0xc452 # macro +regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL = 0xc453 # macro +regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL = 0xc454 # macro +regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC = 0xc455 # macro +regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 = 0xc456 # macro +regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP = 0xc457 # macro +regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR = 0xc458 # macro +regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL = 0xc458 # macro +regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 = 0xc458 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 = 0xc459 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 = 0xc459 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 = 0xc459 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 = 0xc459 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 = 0xc45a # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 = 0xc45a # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 = 0xc45a # macro +regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL = 0xc45c # macro +regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_EP_PCIEP_RESERVED = 0xc45d # macro +regRCC_EP_DEV0_1_EP_PCIEP_RESERVED_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL = 0xc45f # macro +regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID = 0xc460 # macro +regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL = 0xc461 # macro +regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL = 0xc462 # macro +regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL = 0xc463 # macro +regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_BASE_IDX = 8 # macro +regRCC_DWN_DEV0_1_DN_PCIE_RESERVED = 0xc468 # macro +regRCC_DWN_DEV0_1_DN_PCIE_RESERVED_BASE_IDX = 8 # macro +regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH = 0xc469 # macro +regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_BASE_IDX = 8 # macro +regRCC_DWN_DEV0_1_DN_PCIE_CNTL = 0xc46b # macro +regRCC_DWN_DEV0_1_DN_PCIE_CNTL_BASE_IDX = 8 # macro +regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL = 0xc46c # macro +regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_BASE_IDX = 8 # macro +regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 = 0xc46d # macro +regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_BASE_IDX = 8 # macro +regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL = 0xc46e # macro +regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_BASE_IDX = 8 # macro +regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL = 0xc46f # macro +regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_BASE_IDX = 8 # macro +regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 = 0xc470 # macro +regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_BASE_IDX = 8 # macro +regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC = 0xc471 # macro +regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_BASE_IDX = 8 # macro +regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 = 0xc472 # macro +regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_BASE_IDX = 8 # macro +regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL = 0xc475 # macro +regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_BASE_IDX = 8 # macro +regRCC_DWNP_DEV0_1_PCIE_RX_CNTL = 0xc476 # macro +regRCC_DWNP_DEV0_1_PCIE_RX_CNTL_BASE_IDX = 8 # macro +regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL = 0xc477 # macro +regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_BASE_IDX = 8 # macro +regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2 = 0xc478 # macro +regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_BASE_IDX = 8 # macro +regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC = 0xc479 # macro +regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_BASE_IDX = 8 # macro +regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP = 0xc47a # macro +regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_BASE_IDX = 8 # macro +regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL = 0xd040 # macro +regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL_BASE_IDX = 8 # macro +regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE = 0xd041 # macro +regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE_BASE_IDX = 8 # macro +regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0 = 0xd042 # macro +regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0_BASE_IDX = 8 # macro +regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1 = 0xd043 # macro +regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1_BASE_IDX = 8 # macro +regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2 = 0xd044 # macro +regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2_BASE_IDX = 8 # macro +regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3 = 0xd045 # macro +regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3_BASE_IDX = 8 # macro +regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4 = 0xd046 # macro +regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4_BASE_IDX = 8 # macro +regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5 = 0xd047 # macro +regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5_BASE_IDX = 8 # macro +regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL = 0xd048 # macro +regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT0_ADDR_LO = 0x1a000 # macro +regPCIEMSIX_VECT0_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT0_ADDR_HI = 0x1a001 # macro +regPCIEMSIX_VECT0_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT0_MSG_DATA = 0x1a002 # macro +regPCIEMSIX_VECT0_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT0_CONTROL = 0x1a003 # macro +regPCIEMSIX_VECT0_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT1_ADDR_LO = 0x1a004 # macro +regPCIEMSIX_VECT1_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT1_ADDR_HI = 0x1a005 # macro +regPCIEMSIX_VECT1_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT1_MSG_DATA = 0x1a006 # macro +regPCIEMSIX_VECT1_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT1_CONTROL = 0x1a007 # macro +regPCIEMSIX_VECT1_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT2_ADDR_LO = 0x1a008 # macro +regPCIEMSIX_VECT2_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT2_ADDR_HI = 0x1a009 # macro +regPCIEMSIX_VECT2_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT2_MSG_DATA = 0x1a00a # macro +regPCIEMSIX_VECT2_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT2_CONTROL = 0x1a00b # macro +regPCIEMSIX_VECT2_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT3_ADDR_LO = 0x1a00c # macro +regPCIEMSIX_VECT3_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT3_ADDR_HI = 0x1a00d # macro +regPCIEMSIX_VECT3_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT3_MSG_DATA = 0x1a00e # macro +regPCIEMSIX_VECT3_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT3_CONTROL = 0x1a00f # macro +regPCIEMSIX_VECT3_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT4_ADDR_LO = 0x1a010 # macro +regPCIEMSIX_VECT4_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT4_ADDR_HI = 0x1a011 # macro +regPCIEMSIX_VECT4_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT4_MSG_DATA = 0x1a012 # macro +regPCIEMSIX_VECT4_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT4_CONTROL = 0x1a013 # macro +regPCIEMSIX_VECT4_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT5_ADDR_LO = 0x1a014 # macro +regPCIEMSIX_VECT5_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT5_ADDR_HI = 0x1a015 # macro +regPCIEMSIX_VECT5_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT5_MSG_DATA = 0x1a016 # macro +regPCIEMSIX_VECT5_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT5_CONTROL = 0x1a017 # macro +regPCIEMSIX_VECT5_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT6_ADDR_LO = 0x1a018 # macro +regPCIEMSIX_VECT6_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT6_ADDR_HI = 0x1a019 # macro +regPCIEMSIX_VECT6_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT6_MSG_DATA = 0x1a01a # macro +regPCIEMSIX_VECT6_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT6_CONTROL = 0x1a01b # macro +regPCIEMSIX_VECT6_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT7_ADDR_LO = 0x1a01c # macro +regPCIEMSIX_VECT7_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT7_ADDR_HI = 0x1a01d # macro +regPCIEMSIX_VECT7_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT7_MSG_DATA = 0x1a01e # macro +regPCIEMSIX_VECT7_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT7_CONTROL = 0x1a01f # macro +regPCIEMSIX_VECT7_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT8_ADDR_LO = 0x1a020 # macro +regPCIEMSIX_VECT8_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT8_ADDR_HI = 0x1a021 # macro +regPCIEMSIX_VECT8_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT8_MSG_DATA = 0x1a022 # macro +regPCIEMSIX_VECT8_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT8_CONTROL = 0x1a023 # macro +regPCIEMSIX_VECT8_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT9_ADDR_LO = 0x1a024 # macro +regPCIEMSIX_VECT9_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT9_ADDR_HI = 0x1a025 # macro +regPCIEMSIX_VECT9_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT9_MSG_DATA = 0x1a026 # macro +regPCIEMSIX_VECT9_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT9_CONTROL = 0x1a027 # macro +regPCIEMSIX_VECT9_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT10_ADDR_LO = 0x1a028 # macro +regPCIEMSIX_VECT10_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT10_ADDR_HI = 0x1a029 # macro +regPCIEMSIX_VECT10_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT10_MSG_DATA = 0x1a02a # macro +regPCIEMSIX_VECT10_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT10_CONTROL = 0x1a02b # macro +regPCIEMSIX_VECT10_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT11_ADDR_LO = 0x1a02c # macro +regPCIEMSIX_VECT11_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT11_ADDR_HI = 0x1a02d # macro +regPCIEMSIX_VECT11_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT11_MSG_DATA = 0x1a02e # macro +regPCIEMSIX_VECT11_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT11_CONTROL = 0x1a02f # macro +regPCIEMSIX_VECT11_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT12_ADDR_LO = 0x1a030 # macro +regPCIEMSIX_VECT12_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT12_ADDR_HI = 0x1a031 # macro +regPCIEMSIX_VECT12_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT12_MSG_DATA = 0x1a032 # macro +regPCIEMSIX_VECT12_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT12_CONTROL = 0x1a033 # macro +regPCIEMSIX_VECT12_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT13_ADDR_LO = 0x1a034 # macro +regPCIEMSIX_VECT13_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT13_ADDR_HI = 0x1a035 # macro +regPCIEMSIX_VECT13_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT13_MSG_DATA = 0x1a036 # macro +regPCIEMSIX_VECT13_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT13_CONTROL = 0x1a037 # macro +regPCIEMSIX_VECT13_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT14_ADDR_LO = 0x1a038 # macro +regPCIEMSIX_VECT14_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT14_ADDR_HI = 0x1a039 # macro +regPCIEMSIX_VECT14_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT14_MSG_DATA = 0x1a03a # macro +regPCIEMSIX_VECT14_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT14_CONTROL = 0x1a03b # macro +regPCIEMSIX_VECT14_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT15_ADDR_LO = 0x1a03c # macro +regPCIEMSIX_VECT15_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT15_ADDR_HI = 0x1a03d # macro +regPCIEMSIX_VECT15_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT15_MSG_DATA = 0x1a03e # macro +regPCIEMSIX_VECT15_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT15_CONTROL = 0x1a03f # macro +regPCIEMSIX_VECT15_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT16_ADDR_LO = 0x1a040 # macro +regPCIEMSIX_VECT16_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT16_ADDR_HI = 0x1a041 # macro +regPCIEMSIX_VECT16_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT16_MSG_DATA = 0x1a042 # macro +regPCIEMSIX_VECT16_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT16_CONTROL = 0x1a043 # macro +regPCIEMSIX_VECT16_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT17_ADDR_LO = 0x1a044 # macro +regPCIEMSIX_VECT17_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT17_ADDR_HI = 0x1a045 # macro +regPCIEMSIX_VECT17_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT17_MSG_DATA = 0x1a046 # macro +regPCIEMSIX_VECT17_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT17_CONTROL = 0x1a047 # macro +regPCIEMSIX_VECT17_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT18_ADDR_LO = 0x1a048 # macro +regPCIEMSIX_VECT18_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT18_ADDR_HI = 0x1a049 # macro +regPCIEMSIX_VECT18_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT18_MSG_DATA = 0x1a04a # macro +regPCIEMSIX_VECT18_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT18_CONTROL = 0x1a04b # macro +regPCIEMSIX_VECT18_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT19_ADDR_LO = 0x1a04c # macro +regPCIEMSIX_VECT19_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT19_ADDR_HI = 0x1a04d # macro +regPCIEMSIX_VECT19_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT19_MSG_DATA = 0x1a04e # macro +regPCIEMSIX_VECT19_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT19_CONTROL = 0x1a04f # macro +regPCIEMSIX_VECT19_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT20_ADDR_LO = 0x1a050 # macro +regPCIEMSIX_VECT20_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT20_ADDR_HI = 0x1a051 # macro +regPCIEMSIX_VECT20_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT20_MSG_DATA = 0x1a052 # macro +regPCIEMSIX_VECT20_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT20_CONTROL = 0x1a053 # macro +regPCIEMSIX_VECT20_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT21_ADDR_LO = 0x1a054 # macro +regPCIEMSIX_VECT21_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT21_ADDR_HI = 0x1a055 # macro +regPCIEMSIX_VECT21_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT21_MSG_DATA = 0x1a056 # macro +regPCIEMSIX_VECT21_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT21_CONTROL = 0x1a057 # macro +regPCIEMSIX_VECT21_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT22_ADDR_LO = 0x1a058 # macro +regPCIEMSIX_VECT22_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT22_ADDR_HI = 0x1a059 # macro +regPCIEMSIX_VECT22_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT22_MSG_DATA = 0x1a05a # macro +regPCIEMSIX_VECT22_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT22_CONTROL = 0x1a05b # macro +regPCIEMSIX_VECT22_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT23_ADDR_LO = 0x1a05c # macro +regPCIEMSIX_VECT23_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT23_ADDR_HI = 0x1a05d # macro +regPCIEMSIX_VECT23_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT23_MSG_DATA = 0x1a05e # macro +regPCIEMSIX_VECT23_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT23_CONTROL = 0x1a05f # macro +regPCIEMSIX_VECT23_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT24_ADDR_LO = 0x1a060 # macro +regPCIEMSIX_VECT24_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT24_ADDR_HI = 0x1a061 # macro +regPCIEMSIX_VECT24_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT24_MSG_DATA = 0x1a062 # macro +regPCIEMSIX_VECT24_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT24_CONTROL = 0x1a063 # macro +regPCIEMSIX_VECT24_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT25_ADDR_LO = 0x1a064 # macro +regPCIEMSIX_VECT25_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT25_ADDR_HI = 0x1a065 # macro +regPCIEMSIX_VECT25_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT25_MSG_DATA = 0x1a066 # macro +regPCIEMSIX_VECT25_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT25_CONTROL = 0x1a067 # macro +regPCIEMSIX_VECT25_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT26_ADDR_LO = 0x1a068 # macro +regPCIEMSIX_VECT26_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT26_ADDR_HI = 0x1a069 # macro +regPCIEMSIX_VECT26_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT26_MSG_DATA = 0x1a06a # macro +regPCIEMSIX_VECT26_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT26_CONTROL = 0x1a06b # macro +regPCIEMSIX_VECT26_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT27_ADDR_LO = 0x1a06c # macro +regPCIEMSIX_VECT27_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT27_ADDR_HI = 0x1a06d # macro +regPCIEMSIX_VECT27_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT27_MSG_DATA = 0x1a06e # macro +regPCIEMSIX_VECT27_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT27_CONTROL = 0x1a06f # macro +regPCIEMSIX_VECT27_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT28_ADDR_LO = 0x1a070 # macro +regPCIEMSIX_VECT28_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT28_ADDR_HI = 0x1a071 # macro +regPCIEMSIX_VECT28_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT28_MSG_DATA = 0x1a072 # macro +regPCIEMSIX_VECT28_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT28_CONTROL = 0x1a073 # macro +regPCIEMSIX_VECT28_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT29_ADDR_LO = 0x1a074 # macro +regPCIEMSIX_VECT29_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT29_ADDR_HI = 0x1a075 # macro +regPCIEMSIX_VECT29_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT29_MSG_DATA = 0x1a076 # macro +regPCIEMSIX_VECT29_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT29_CONTROL = 0x1a077 # macro +regPCIEMSIX_VECT29_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT30_ADDR_LO = 0x1a078 # macro +regPCIEMSIX_VECT30_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT30_ADDR_HI = 0x1a079 # macro +regPCIEMSIX_VECT30_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT30_MSG_DATA = 0x1a07a # macro +regPCIEMSIX_VECT30_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT30_CONTROL = 0x1a07b # macro +regPCIEMSIX_VECT30_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT31_ADDR_LO = 0x1a07c # macro +regPCIEMSIX_VECT31_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT31_ADDR_HI = 0x1a07d # macro +regPCIEMSIX_VECT31_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT31_MSG_DATA = 0x1a07e # macro +regPCIEMSIX_VECT31_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT31_CONTROL = 0x1a07f # macro +regPCIEMSIX_VECT31_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT32_ADDR_LO = 0x1a080 # macro +regPCIEMSIX_VECT32_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT32_ADDR_HI = 0x1a081 # macro +regPCIEMSIX_VECT32_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT32_MSG_DATA = 0x1a082 # macro +regPCIEMSIX_VECT32_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT32_CONTROL = 0x1a083 # macro +regPCIEMSIX_VECT32_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT33_ADDR_LO = 0x1a084 # macro +regPCIEMSIX_VECT33_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT33_ADDR_HI = 0x1a085 # macro +regPCIEMSIX_VECT33_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT33_MSG_DATA = 0x1a086 # macro +regPCIEMSIX_VECT33_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT33_CONTROL = 0x1a087 # macro +regPCIEMSIX_VECT33_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT34_ADDR_LO = 0x1a088 # macro +regPCIEMSIX_VECT34_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT34_ADDR_HI = 0x1a089 # macro +regPCIEMSIX_VECT34_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT34_MSG_DATA = 0x1a08a # macro +regPCIEMSIX_VECT34_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT34_CONTROL = 0x1a08b # macro +regPCIEMSIX_VECT34_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT35_ADDR_LO = 0x1a08c # macro +regPCIEMSIX_VECT35_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT35_ADDR_HI = 0x1a08d # macro +regPCIEMSIX_VECT35_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT35_MSG_DATA = 0x1a08e # macro +regPCIEMSIX_VECT35_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT35_CONTROL = 0x1a08f # macro +regPCIEMSIX_VECT35_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT36_ADDR_LO = 0x1a090 # macro +regPCIEMSIX_VECT36_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT36_ADDR_HI = 0x1a091 # macro +regPCIEMSIX_VECT36_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT36_MSG_DATA = 0x1a092 # macro +regPCIEMSIX_VECT36_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT36_CONTROL = 0x1a093 # macro +regPCIEMSIX_VECT36_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT37_ADDR_LO = 0x1a094 # macro +regPCIEMSIX_VECT37_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT37_ADDR_HI = 0x1a095 # macro +regPCIEMSIX_VECT37_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT37_MSG_DATA = 0x1a096 # macro +regPCIEMSIX_VECT37_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT37_CONTROL = 0x1a097 # macro +regPCIEMSIX_VECT37_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT38_ADDR_LO = 0x1a098 # macro +regPCIEMSIX_VECT38_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT38_ADDR_HI = 0x1a099 # macro +regPCIEMSIX_VECT38_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT38_MSG_DATA = 0x1a09a # macro +regPCIEMSIX_VECT38_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT38_CONTROL = 0x1a09b # macro +regPCIEMSIX_VECT38_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT39_ADDR_LO = 0x1a09c # macro +regPCIEMSIX_VECT39_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT39_ADDR_HI = 0x1a09d # macro +regPCIEMSIX_VECT39_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT39_MSG_DATA = 0x1a09e # macro +regPCIEMSIX_VECT39_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT39_CONTROL = 0x1a09f # macro +regPCIEMSIX_VECT39_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT40_ADDR_LO = 0x1a0a0 # macro +regPCIEMSIX_VECT40_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT40_ADDR_HI = 0x1a0a1 # macro +regPCIEMSIX_VECT40_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT40_MSG_DATA = 0x1a0a2 # macro +regPCIEMSIX_VECT40_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT40_CONTROL = 0x1a0a3 # macro +regPCIEMSIX_VECT40_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT41_ADDR_LO = 0x1a0a4 # macro +regPCIEMSIX_VECT41_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT41_ADDR_HI = 0x1a0a5 # macro +regPCIEMSIX_VECT41_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT41_MSG_DATA = 0x1a0a6 # macro +regPCIEMSIX_VECT41_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT41_CONTROL = 0x1a0a7 # macro +regPCIEMSIX_VECT41_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT42_ADDR_LO = 0x1a0a8 # macro +regPCIEMSIX_VECT42_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT42_ADDR_HI = 0x1a0a9 # macro +regPCIEMSIX_VECT42_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT42_MSG_DATA = 0x1a0aa # macro +regPCIEMSIX_VECT42_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT42_CONTROL = 0x1a0ab # macro +regPCIEMSIX_VECT42_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT43_ADDR_LO = 0x1a0ac # macro +regPCIEMSIX_VECT43_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT43_ADDR_HI = 0x1a0ad # macro +regPCIEMSIX_VECT43_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT43_MSG_DATA = 0x1a0ae # macro +regPCIEMSIX_VECT43_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT43_CONTROL = 0x1a0af # macro +regPCIEMSIX_VECT43_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT44_ADDR_LO = 0x1a0b0 # macro +regPCIEMSIX_VECT44_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT44_ADDR_HI = 0x1a0b1 # macro +regPCIEMSIX_VECT44_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT44_MSG_DATA = 0x1a0b2 # macro +regPCIEMSIX_VECT44_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT44_CONTROL = 0x1a0b3 # macro +regPCIEMSIX_VECT44_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT45_ADDR_LO = 0x1a0b4 # macro +regPCIEMSIX_VECT45_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT45_ADDR_HI = 0x1a0b5 # macro +regPCIEMSIX_VECT45_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT45_MSG_DATA = 0x1a0b6 # macro +regPCIEMSIX_VECT45_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT45_CONTROL = 0x1a0b7 # macro +regPCIEMSIX_VECT45_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT46_ADDR_LO = 0x1a0b8 # macro +regPCIEMSIX_VECT46_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT46_ADDR_HI = 0x1a0b9 # macro +regPCIEMSIX_VECT46_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT46_MSG_DATA = 0x1a0ba # macro +regPCIEMSIX_VECT46_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT46_CONTROL = 0x1a0bb # macro +regPCIEMSIX_VECT46_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT47_ADDR_LO = 0x1a0bc # macro +regPCIEMSIX_VECT47_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT47_ADDR_HI = 0x1a0bd # macro +regPCIEMSIX_VECT47_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT47_MSG_DATA = 0x1a0be # macro +regPCIEMSIX_VECT47_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT47_CONTROL = 0x1a0bf # macro +regPCIEMSIX_VECT47_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT48_ADDR_LO = 0x1a0c0 # macro +regPCIEMSIX_VECT48_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT48_ADDR_HI = 0x1a0c1 # macro +regPCIEMSIX_VECT48_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT48_MSG_DATA = 0x1a0c2 # macro +regPCIEMSIX_VECT48_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT48_CONTROL = 0x1a0c3 # macro +regPCIEMSIX_VECT48_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT49_ADDR_LO = 0x1a0c4 # macro +regPCIEMSIX_VECT49_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT49_ADDR_HI = 0x1a0c5 # macro +regPCIEMSIX_VECT49_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT49_MSG_DATA = 0x1a0c6 # macro +regPCIEMSIX_VECT49_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT49_CONTROL = 0x1a0c7 # macro +regPCIEMSIX_VECT49_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT50_ADDR_LO = 0x1a0c8 # macro +regPCIEMSIX_VECT50_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT50_ADDR_HI = 0x1a0c9 # macro +regPCIEMSIX_VECT50_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT50_MSG_DATA = 0x1a0ca # macro +regPCIEMSIX_VECT50_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT50_CONTROL = 0x1a0cb # macro +regPCIEMSIX_VECT50_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT51_ADDR_LO = 0x1a0cc # macro +regPCIEMSIX_VECT51_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT51_ADDR_HI = 0x1a0cd # macro +regPCIEMSIX_VECT51_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT51_MSG_DATA = 0x1a0ce # macro +regPCIEMSIX_VECT51_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT51_CONTROL = 0x1a0cf # macro +regPCIEMSIX_VECT51_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT52_ADDR_LO = 0x1a0d0 # macro +regPCIEMSIX_VECT52_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT52_ADDR_HI = 0x1a0d1 # macro +regPCIEMSIX_VECT52_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT52_MSG_DATA = 0x1a0d2 # macro +regPCIEMSIX_VECT52_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT52_CONTROL = 0x1a0d3 # macro +regPCIEMSIX_VECT52_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT53_ADDR_LO = 0x1a0d4 # macro +regPCIEMSIX_VECT53_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT53_ADDR_HI = 0x1a0d5 # macro +regPCIEMSIX_VECT53_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT53_MSG_DATA = 0x1a0d6 # macro +regPCIEMSIX_VECT53_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT53_CONTROL = 0x1a0d7 # macro +regPCIEMSIX_VECT53_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT54_ADDR_LO = 0x1a0d8 # macro +regPCIEMSIX_VECT54_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT54_ADDR_HI = 0x1a0d9 # macro +regPCIEMSIX_VECT54_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT54_MSG_DATA = 0x1a0da # macro +regPCIEMSIX_VECT54_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT54_CONTROL = 0x1a0db # macro +regPCIEMSIX_VECT54_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT55_ADDR_LO = 0x1a0dc # macro +regPCIEMSIX_VECT55_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT55_ADDR_HI = 0x1a0dd # macro +regPCIEMSIX_VECT55_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT55_MSG_DATA = 0x1a0de # macro +regPCIEMSIX_VECT55_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT55_CONTROL = 0x1a0df # macro +regPCIEMSIX_VECT55_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT56_ADDR_LO = 0x1a0e0 # macro +regPCIEMSIX_VECT56_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT56_ADDR_HI = 0x1a0e1 # macro +regPCIEMSIX_VECT56_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT56_MSG_DATA = 0x1a0e2 # macro +regPCIEMSIX_VECT56_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT56_CONTROL = 0x1a0e3 # macro +regPCIEMSIX_VECT56_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT57_ADDR_LO = 0x1a0e4 # macro +regPCIEMSIX_VECT57_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT57_ADDR_HI = 0x1a0e5 # macro +regPCIEMSIX_VECT57_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT57_MSG_DATA = 0x1a0e6 # macro +regPCIEMSIX_VECT57_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT57_CONTROL = 0x1a0e7 # macro +regPCIEMSIX_VECT57_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT58_ADDR_LO = 0x1a0e8 # macro +regPCIEMSIX_VECT58_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT58_ADDR_HI = 0x1a0e9 # macro +regPCIEMSIX_VECT58_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT58_MSG_DATA = 0x1a0ea # macro +regPCIEMSIX_VECT58_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT58_CONTROL = 0x1a0eb # macro +regPCIEMSIX_VECT58_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT59_ADDR_LO = 0x1a0ec # macro +regPCIEMSIX_VECT59_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT59_ADDR_HI = 0x1a0ed # macro +regPCIEMSIX_VECT59_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT59_MSG_DATA = 0x1a0ee # macro +regPCIEMSIX_VECT59_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT59_CONTROL = 0x1a0ef # macro +regPCIEMSIX_VECT59_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT60_ADDR_LO = 0x1a0f0 # macro +regPCIEMSIX_VECT60_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT60_ADDR_HI = 0x1a0f1 # macro +regPCIEMSIX_VECT60_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT60_MSG_DATA = 0x1a0f2 # macro +regPCIEMSIX_VECT60_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT60_CONTROL = 0x1a0f3 # macro +regPCIEMSIX_VECT60_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT61_ADDR_LO = 0x1a0f4 # macro +regPCIEMSIX_VECT61_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT61_ADDR_HI = 0x1a0f5 # macro +regPCIEMSIX_VECT61_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT61_MSG_DATA = 0x1a0f6 # macro +regPCIEMSIX_VECT61_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT61_CONTROL = 0x1a0f7 # macro +regPCIEMSIX_VECT61_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT62_ADDR_LO = 0x1a0f8 # macro +regPCIEMSIX_VECT62_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT62_ADDR_HI = 0x1a0f9 # macro +regPCIEMSIX_VECT62_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT62_MSG_DATA = 0x1a0fa # macro +regPCIEMSIX_VECT62_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT62_CONTROL = 0x1a0fb # macro +regPCIEMSIX_VECT62_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT63_ADDR_LO = 0x1a0fc # macro +regPCIEMSIX_VECT63_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT63_ADDR_HI = 0x1a0fd # macro +regPCIEMSIX_VECT63_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT63_MSG_DATA = 0x1a0fe # macro +regPCIEMSIX_VECT63_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT63_CONTROL = 0x1a0ff # macro +regPCIEMSIX_VECT63_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT64_ADDR_LO = 0x1a100 # macro +regPCIEMSIX_VECT64_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT64_ADDR_HI = 0x1a101 # macro +regPCIEMSIX_VECT64_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT64_MSG_DATA = 0x1a102 # macro +regPCIEMSIX_VECT64_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT64_CONTROL = 0x1a103 # macro +regPCIEMSIX_VECT64_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT65_ADDR_LO = 0x1a104 # macro +regPCIEMSIX_VECT65_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT65_ADDR_HI = 0x1a105 # macro +regPCIEMSIX_VECT65_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT65_MSG_DATA = 0x1a106 # macro +regPCIEMSIX_VECT65_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT65_CONTROL = 0x1a107 # macro +regPCIEMSIX_VECT65_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT66_ADDR_LO = 0x1a108 # macro +regPCIEMSIX_VECT66_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT66_ADDR_HI = 0x1a109 # macro +regPCIEMSIX_VECT66_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT66_MSG_DATA = 0x1a10a # macro +regPCIEMSIX_VECT66_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT66_CONTROL = 0x1a10b # macro +regPCIEMSIX_VECT66_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT67_ADDR_LO = 0x1a10c # macro +regPCIEMSIX_VECT67_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT67_ADDR_HI = 0x1a10d # macro +regPCIEMSIX_VECT67_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT67_MSG_DATA = 0x1a10e # macro +regPCIEMSIX_VECT67_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT67_CONTROL = 0x1a10f # macro +regPCIEMSIX_VECT67_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT68_ADDR_LO = 0x1a110 # macro +regPCIEMSIX_VECT68_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT68_ADDR_HI = 0x1a111 # macro +regPCIEMSIX_VECT68_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT68_MSG_DATA = 0x1a112 # macro +regPCIEMSIX_VECT68_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT68_CONTROL = 0x1a113 # macro +regPCIEMSIX_VECT68_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT69_ADDR_LO = 0x1a114 # macro +regPCIEMSIX_VECT69_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT69_ADDR_HI = 0x1a115 # macro +regPCIEMSIX_VECT69_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT69_MSG_DATA = 0x1a116 # macro +regPCIEMSIX_VECT69_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT69_CONTROL = 0x1a117 # macro +regPCIEMSIX_VECT69_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT70_ADDR_LO = 0x1a118 # macro +regPCIEMSIX_VECT70_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT70_ADDR_HI = 0x1a119 # macro +regPCIEMSIX_VECT70_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT70_MSG_DATA = 0x1a11a # macro +regPCIEMSIX_VECT70_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT70_CONTROL = 0x1a11b # macro +regPCIEMSIX_VECT70_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT71_ADDR_LO = 0x1a11c # macro +regPCIEMSIX_VECT71_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT71_ADDR_HI = 0x1a11d # macro +regPCIEMSIX_VECT71_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT71_MSG_DATA = 0x1a11e # macro +regPCIEMSIX_VECT71_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT71_CONTROL = 0x1a11f # macro +regPCIEMSIX_VECT71_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT72_ADDR_LO = 0x1a120 # macro +regPCIEMSIX_VECT72_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT72_ADDR_HI = 0x1a121 # macro +regPCIEMSIX_VECT72_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT72_MSG_DATA = 0x1a122 # macro +regPCIEMSIX_VECT72_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT72_CONTROL = 0x1a123 # macro +regPCIEMSIX_VECT72_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT73_ADDR_LO = 0x1a124 # macro +regPCIEMSIX_VECT73_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT73_ADDR_HI = 0x1a125 # macro +regPCIEMSIX_VECT73_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT73_MSG_DATA = 0x1a126 # macro +regPCIEMSIX_VECT73_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT73_CONTROL = 0x1a127 # macro +regPCIEMSIX_VECT73_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT74_ADDR_LO = 0x1a128 # macro +regPCIEMSIX_VECT74_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT74_ADDR_HI = 0x1a129 # macro +regPCIEMSIX_VECT74_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT74_MSG_DATA = 0x1a12a # macro +regPCIEMSIX_VECT74_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT74_CONTROL = 0x1a12b # macro +regPCIEMSIX_VECT74_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT75_ADDR_LO = 0x1a12c # macro +regPCIEMSIX_VECT75_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT75_ADDR_HI = 0x1a12d # macro +regPCIEMSIX_VECT75_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT75_MSG_DATA = 0x1a12e # macro +regPCIEMSIX_VECT75_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT75_CONTROL = 0x1a12f # macro +regPCIEMSIX_VECT75_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT76_ADDR_LO = 0x1a130 # macro +regPCIEMSIX_VECT76_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT76_ADDR_HI = 0x1a131 # macro +regPCIEMSIX_VECT76_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT76_MSG_DATA = 0x1a132 # macro +regPCIEMSIX_VECT76_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT76_CONTROL = 0x1a133 # macro +regPCIEMSIX_VECT76_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT77_ADDR_LO = 0x1a134 # macro +regPCIEMSIX_VECT77_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT77_ADDR_HI = 0x1a135 # macro +regPCIEMSIX_VECT77_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT77_MSG_DATA = 0x1a136 # macro +regPCIEMSIX_VECT77_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT77_CONTROL = 0x1a137 # macro +regPCIEMSIX_VECT77_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT78_ADDR_LO = 0x1a138 # macro +regPCIEMSIX_VECT78_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT78_ADDR_HI = 0x1a139 # macro +regPCIEMSIX_VECT78_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT78_MSG_DATA = 0x1a13a # macro +regPCIEMSIX_VECT78_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT78_CONTROL = 0x1a13b # macro +regPCIEMSIX_VECT78_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT79_ADDR_LO = 0x1a13c # macro +regPCIEMSIX_VECT79_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT79_ADDR_HI = 0x1a13d # macro +regPCIEMSIX_VECT79_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT79_MSG_DATA = 0x1a13e # macro +regPCIEMSIX_VECT79_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT79_CONTROL = 0x1a13f # macro +regPCIEMSIX_VECT79_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT80_ADDR_LO = 0x1a140 # macro +regPCIEMSIX_VECT80_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT80_ADDR_HI = 0x1a141 # macro +regPCIEMSIX_VECT80_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT80_MSG_DATA = 0x1a142 # macro +regPCIEMSIX_VECT80_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT80_CONTROL = 0x1a143 # macro +regPCIEMSIX_VECT80_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT81_ADDR_LO = 0x1a144 # macro +regPCIEMSIX_VECT81_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT81_ADDR_HI = 0x1a145 # macro +regPCIEMSIX_VECT81_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT81_MSG_DATA = 0x1a146 # macro +regPCIEMSIX_VECT81_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT81_CONTROL = 0x1a147 # macro +regPCIEMSIX_VECT81_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT82_ADDR_LO = 0x1a148 # macro +regPCIEMSIX_VECT82_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT82_ADDR_HI = 0x1a149 # macro +regPCIEMSIX_VECT82_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT82_MSG_DATA = 0x1a14a # macro +regPCIEMSIX_VECT82_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT82_CONTROL = 0x1a14b # macro +regPCIEMSIX_VECT82_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT83_ADDR_LO = 0x1a14c # macro +regPCIEMSIX_VECT83_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT83_ADDR_HI = 0x1a14d # macro +regPCIEMSIX_VECT83_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT83_MSG_DATA = 0x1a14e # macro +regPCIEMSIX_VECT83_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT83_CONTROL = 0x1a14f # macro +regPCIEMSIX_VECT83_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT84_ADDR_LO = 0x1a150 # macro +regPCIEMSIX_VECT84_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT84_ADDR_HI = 0x1a151 # macro +regPCIEMSIX_VECT84_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT84_MSG_DATA = 0x1a152 # macro +regPCIEMSIX_VECT84_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT84_CONTROL = 0x1a153 # macro +regPCIEMSIX_VECT84_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT85_ADDR_LO = 0x1a154 # macro +regPCIEMSIX_VECT85_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT85_ADDR_HI = 0x1a155 # macro +regPCIEMSIX_VECT85_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT85_MSG_DATA = 0x1a156 # macro +regPCIEMSIX_VECT85_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT85_CONTROL = 0x1a157 # macro +regPCIEMSIX_VECT85_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT86_ADDR_LO = 0x1a158 # macro +regPCIEMSIX_VECT86_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT86_ADDR_HI = 0x1a159 # macro +regPCIEMSIX_VECT86_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT86_MSG_DATA = 0x1a15a # macro +regPCIEMSIX_VECT86_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT86_CONTROL = 0x1a15b # macro +regPCIEMSIX_VECT86_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT87_ADDR_LO = 0x1a15c # macro +regPCIEMSIX_VECT87_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT87_ADDR_HI = 0x1a15d # macro +regPCIEMSIX_VECT87_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT87_MSG_DATA = 0x1a15e # macro +regPCIEMSIX_VECT87_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT87_CONTROL = 0x1a15f # macro +regPCIEMSIX_VECT87_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT88_ADDR_LO = 0x1a160 # macro +regPCIEMSIX_VECT88_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT88_ADDR_HI = 0x1a161 # macro +regPCIEMSIX_VECT88_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT88_MSG_DATA = 0x1a162 # macro +regPCIEMSIX_VECT88_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT88_CONTROL = 0x1a163 # macro +regPCIEMSIX_VECT88_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT89_ADDR_LO = 0x1a164 # macro +regPCIEMSIX_VECT89_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT89_ADDR_HI = 0x1a165 # macro +regPCIEMSIX_VECT89_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT89_MSG_DATA = 0x1a166 # macro +regPCIEMSIX_VECT89_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT89_CONTROL = 0x1a167 # macro +regPCIEMSIX_VECT89_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT90_ADDR_LO = 0x1a168 # macro +regPCIEMSIX_VECT90_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT90_ADDR_HI = 0x1a169 # macro +regPCIEMSIX_VECT90_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT90_MSG_DATA = 0x1a16a # macro +regPCIEMSIX_VECT90_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT90_CONTROL = 0x1a16b # macro +regPCIEMSIX_VECT90_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT91_ADDR_LO = 0x1a16c # macro +regPCIEMSIX_VECT91_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT91_ADDR_HI = 0x1a16d # macro +regPCIEMSIX_VECT91_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT91_MSG_DATA = 0x1a16e # macro +regPCIEMSIX_VECT91_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT91_CONTROL = 0x1a16f # macro +regPCIEMSIX_VECT91_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT92_ADDR_LO = 0x1a170 # macro +regPCIEMSIX_VECT92_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT92_ADDR_HI = 0x1a171 # macro +regPCIEMSIX_VECT92_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT92_MSG_DATA = 0x1a172 # macro +regPCIEMSIX_VECT92_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT92_CONTROL = 0x1a173 # macro +regPCIEMSIX_VECT92_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT93_ADDR_LO = 0x1a174 # macro +regPCIEMSIX_VECT93_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT93_ADDR_HI = 0x1a175 # macro +regPCIEMSIX_VECT93_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT93_MSG_DATA = 0x1a176 # macro +regPCIEMSIX_VECT93_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT93_CONTROL = 0x1a177 # macro +regPCIEMSIX_VECT93_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT94_ADDR_LO = 0x1a178 # macro +regPCIEMSIX_VECT94_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT94_ADDR_HI = 0x1a179 # macro +regPCIEMSIX_VECT94_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT94_MSG_DATA = 0x1a17a # macro +regPCIEMSIX_VECT94_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT94_CONTROL = 0x1a17b # macro +regPCIEMSIX_VECT94_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT95_ADDR_LO = 0x1a17c # macro +regPCIEMSIX_VECT95_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT95_ADDR_HI = 0x1a17d # macro +regPCIEMSIX_VECT95_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT95_MSG_DATA = 0x1a17e # macro +regPCIEMSIX_VECT95_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT95_CONTROL = 0x1a17f # macro +regPCIEMSIX_VECT95_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT96_ADDR_LO = 0x1a180 # macro +regPCIEMSIX_VECT96_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT96_ADDR_HI = 0x1a181 # macro +regPCIEMSIX_VECT96_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT96_MSG_DATA = 0x1a182 # macro +regPCIEMSIX_VECT96_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT96_CONTROL = 0x1a183 # macro +regPCIEMSIX_VECT96_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT97_ADDR_LO = 0x1a184 # macro +regPCIEMSIX_VECT97_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT97_ADDR_HI = 0x1a185 # macro +regPCIEMSIX_VECT97_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT97_MSG_DATA = 0x1a186 # macro +regPCIEMSIX_VECT97_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT97_CONTROL = 0x1a187 # macro +regPCIEMSIX_VECT97_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT98_ADDR_LO = 0x1a188 # macro +regPCIEMSIX_VECT98_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT98_ADDR_HI = 0x1a189 # macro +regPCIEMSIX_VECT98_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT98_MSG_DATA = 0x1a18a # macro +regPCIEMSIX_VECT98_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT98_CONTROL = 0x1a18b # macro +regPCIEMSIX_VECT98_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT99_ADDR_LO = 0x1a18c # macro +regPCIEMSIX_VECT99_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT99_ADDR_HI = 0x1a18d # macro +regPCIEMSIX_VECT99_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT99_MSG_DATA = 0x1a18e # macro +regPCIEMSIX_VECT99_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT99_CONTROL = 0x1a18f # macro +regPCIEMSIX_VECT99_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT100_ADDR_LO = 0x1a190 # macro +regPCIEMSIX_VECT100_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT100_ADDR_HI = 0x1a191 # macro +regPCIEMSIX_VECT100_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT100_MSG_DATA = 0x1a192 # macro +regPCIEMSIX_VECT100_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT100_CONTROL = 0x1a193 # macro +regPCIEMSIX_VECT100_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT101_ADDR_LO = 0x1a194 # macro +regPCIEMSIX_VECT101_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT101_ADDR_HI = 0x1a195 # macro +regPCIEMSIX_VECT101_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT101_MSG_DATA = 0x1a196 # macro +regPCIEMSIX_VECT101_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT101_CONTROL = 0x1a197 # macro +regPCIEMSIX_VECT101_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT102_ADDR_LO = 0x1a198 # macro +regPCIEMSIX_VECT102_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT102_ADDR_HI = 0x1a199 # macro +regPCIEMSIX_VECT102_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT102_MSG_DATA = 0x1a19a # macro +regPCIEMSIX_VECT102_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT102_CONTROL = 0x1a19b # macro +regPCIEMSIX_VECT102_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT103_ADDR_LO = 0x1a19c # macro +regPCIEMSIX_VECT103_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT103_ADDR_HI = 0x1a19d # macro +regPCIEMSIX_VECT103_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT103_MSG_DATA = 0x1a19e # macro +regPCIEMSIX_VECT103_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT103_CONTROL = 0x1a19f # macro +regPCIEMSIX_VECT103_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT104_ADDR_LO = 0x1a1a0 # macro +regPCIEMSIX_VECT104_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT104_ADDR_HI = 0x1a1a1 # macro +regPCIEMSIX_VECT104_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT104_MSG_DATA = 0x1a1a2 # macro +regPCIEMSIX_VECT104_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT104_CONTROL = 0x1a1a3 # macro +regPCIEMSIX_VECT104_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT105_ADDR_LO = 0x1a1a4 # macro +regPCIEMSIX_VECT105_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT105_ADDR_HI = 0x1a1a5 # macro +regPCIEMSIX_VECT105_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT105_MSG_DATA = 0x1a1a6 # macro +regPCIEMSIX_VECT105_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT105_CONTROL = 0x1a1a7 # macro +regPCIEMSIX_VECT105_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT106_ADDR_LO = 0x1a1a8 # macro +regPCIEMSIX_VECT106_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT106_ADDR_HI = 0x1a1a9 # macro +regPCIEMSIX_VECT106_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT106_MSG_DATA = 0x1a1aa # macro +regPCIEMSIX_VECT106_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT106_CONTROL = 0x1a1ab # macro +regPCIEMSIX_VECT106_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT107_ADDR_LO = 0x1a1ac # macro +regPCIEMSIX_VECT107_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT107_ADDR_HI = 0x1a1ad # macro +regPCIEMSIX_VECT107_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT107_MSG_DATA = 0x1a1ae # macro +regPCIEMSIX_VECT107_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT107_CONTROL = 0x1a1af # macro +regPCIEMSIX_VECT107_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT108_ADDR_LO = 0x1a1b0 # macro +regPCIEMSIX_VECT108_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT108_ADDR_HI = 0x1a1b1 # macro +regPCIEMSIX_VECT108_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT108_MSG_DATA = 0x1a1b2 # macro +regPCIEMSIX_VECT108_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT108_CONTROL = 0x1a1b3 # macro +regPCIEMSIX_VECT108_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT109_ADDR_LO = 0x1a1b4 # macro +regPCIEMSIX_VECT109_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT109_ADDR_HI = 0x1a1b5 # macro +regPCIEMSIX_VECT109_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT109_MSG_DATA = 0x1a1b6 # macro +regPCIEMSIX_VECT109_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT109_CONTROL = 0x1a1b7 # macro +regPCIEMSIX_VECT109_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT110_ADDR_LO = 0x1a1b8 # macro +regPCIEMSIX_VECT110_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT110_ADDR_HI = 0x1a1b9 # macro +regPCIEMSIX_VECT110_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT110_MSG_DATA = 0x1a1ba # macro +regPCIEMSIX_VECT110_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT110_CONTROL = 0x1a1bb # macro +regPCIEMSIX_VECT110_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT111_ADDR_LO = 0x1a1bc # macro +regPCIEMSIX_VECT111_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT111_ADDR_HI = 0x1a1bd # macro +regPCIEMSIX_VECT111_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT111_MSG_DATA = 0x1a1be # macro +regPCIEMSIX_VECT111_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT111_CONTROL = 0x1a1bf # macro +regPCIEMSIX_VECT111_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT112_ADDR_LO = 0x1a1c0 # macro +regPCIEMSIX_VECT112_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT112_ADDR_HI = 0x1a1c1 # macro +regPCIEMSIX_VECT112_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT112_MSG_DATA = 0x1a1c2 # macro +regPCIEMSIX_VECT112_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT112_CONTROL = 0x1a1c3 # macro +regPCIEMSIX_VECT112_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT113_ADDR_LO = 0x1a1c4 # macro +regPCIEMSIX_VECT113_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT113_ADDR_HI = 0x1a1c5 # macro +regPCIEMSIX_VECT113_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT113_MSG_DATA = 0x1a1c6 # macro +regPCIEMSIX_VECT113_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT113_CONTROL = 0x1a1c7 # macro +regPCIEMSIX_VECT113_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT114_ADDR_LO = 0x1a1c8 # macro +regPCIEMSIX_VECT114_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT114_ADDR_HI = 0x1a1c9 # macro +regPCIEMSIX_VECT114_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT114_MSG_DATA = 0x1a1ca # macro +regPCIEMSIX_VECT114_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT114_CONTROL = 0x1a1cb # macro +regPCIEMSIX_VECT114_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT115_ADDR_LO = 0x1a1cc # macro +regPCIEMSIX_VECT115_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT115_ADDR_HI = 0x1a1cd # macro +regPCIEMSIX_VECT115_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT115_MSG_DATA = 0x1a1ce # macro +regPCIEMSIX_VECT115_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT115_CONTROL = 0x1a1cf # macro +regPCIEMSIX_VECT115_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT116_ADDR_LO = 0x1a1d0 # macro +regPCIEMSIX_VECT116_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT116_ADDR_HI = 0x1a1d1 # macro +regPCIEMSIX_VECT116_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT116_MSG_DATA = 0x1a1d2 # macro +regPCIEMSIX_VECT116_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT116_CONTROL = 0x1a1d3 # macro +regPCIEMSIX_VECT116_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT117_ADDR_LO = 0x1a1d4 # macro +regPCIEMSIX_VECT117_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT117_ADDR_HI = 0x1a1d5 # macro +regPCIEMSIX_VECT117_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT117_MSG_DATA = 0x1a1d6 # macro +regPCIEMSIX_VECT117_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT117_CONTROL = 0x1a1d7 # macro +regPCIEMSIX_VECT117_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT118_ADDR_LO = 0x1a1d8 # macro +regPCIEMSIX_VECT118_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT118_ADDR_HI = 0x1a1d9 # macro +regPCIEMSIX_VECT118_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT118_MSG_DATA = 0x1a1da # macro +regPCIEMSIX_VECT118_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT118_CONTROL = 0x1a1db # macro +regPCIEMSIX_VECT118_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT119_ADDR_LO = 0x1a1dc # macro +regPCIEMSIX_VECT119_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT119_ADDR_HI = 0x1a1dd # macro +regPCIEMSIX_VECT119_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT119_MSG_DATA = 0x1a1de # macro +regPCIEMSIX_VECT119_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT119_CONTROL = 0x1a1df # macro +regPCIEMSIX_VECT119_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT120_ADDR_LO = 0x1a1e0 # macro +regPCIEMSIX_VECT120_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT120_ADDR_HI = 0x1a1e1 # macro +regPCIEMSIX_VECT120_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT120_MSG_DATA = 0x1a1e2 # macro +regPCIEMSIX_VECT120_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT120_CONTROL = 0x1a1e3 # macro +regPCIEMSIX_VECT120_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT121_ADDR_LO = 0x1a1e4 # macro +regPCIEMSIX_VECT121_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT121_ADDR_HI = 0x1a1e5 # macro +regPCIEMSIX_VECT121_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT121_MSG_DATA = 0x1a1e6 # macro +regPCIEMSIX_VECT121_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT121_CONTROL = 0x1a1e7 # macro +regPCIEMSIX_VECT121_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT122_ADDR_LO = 0x1a1e8 # macro +regPCIEMSIX_VECT122_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT122_ADDR_HI = 0x1a1e9 # macro +regPCIEMSIX_VECT122_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT122_MSG_DATA = 0x1a1ea # macro +regPCIEMSIX_VECT122_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT122_CONTROL = 0x1a1eb # macro +regPCIEMSIX_VECT122_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT123_ADDR_LO = 0x1a1ec # macro +regPCIEMSIX_VECT123_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT123_ADDR_HI = 0x1a1ed # macro +regPCIEMSIX_VECT123_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT123_MSG_DATA = 0x1a1ee # macro +regPCIEMSIX_VECT123_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT123_CONTROL = 0x1a1ef # macro +regPCIEMSIX_VECT123_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT124_ADDR_LO = 0x1a1f0 # macro +regPCIEMSIX_VECT124_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT124_ADDR_HI = 0x1a1f1 # macro +regPCIEMSIX_VECT124_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT124_MSG_DATA = 0x1a1f2 # macro +regPCIEMSIX_VECT124_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT124_CONTROL = 0x1a1f3 # macro +regPCIEMSIX_VECT124_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT125_ADDR_LO = 0x1a1f4 # macro +regPCIEMSIX_VECT125_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT125_ADDR_HI = 0x1a1f5 # macro +regPCIEMSIX_VECT125_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT125_MSG_DATA = 0x1a1f6 # macro +regPCIEMSIX_VECT125_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT125_CONTROL = 0x1a1f7 # macro +regPCIEMSIX_VECT125_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT126_ADDR_LO = 0x1a1f8 # macro +regPCIEMSIX_VECT126_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT126_ADDR_HI = 0x1a1f9 # macro +regPCIEMSIX_VECT126_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT126_MSG_DATA = 0x1a1fa # macro +regPCIEMSIX_VECT126_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT126_CONTROL = 0x1a1fb # macro +regPCIEMSIX_VECT126_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT127_ADDR_LO = 0x1a1fc # macro +regPCIEMSIX_VECT127_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT127_ADDR_HI = 0x1a1fd # macro +regPCIEMSIX_VECT127_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT127_MSG_DATA = 0x1a1fe # macro +regPCIEMSIX_VECT127_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT127_CONTROL = 0x1a1ff # macro +regPCIEMSIX_VECT127_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT128_ADDR_LO = 0x1a200 # macro +regPCIEMSIX_VECT128_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT128_ADDR_HI = 0x1a201 # macro +regPCIEMSIX_VECT128_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT128_MSG_DATA = 0x1a202 # macro +regPCIEMSIX_VECT128_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT128_CONTROL = 0x1a203 # macro +regPCIEMSIX_VECT128_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT129_ADDR_LO = 0x1a204 # macro +regPCIEMSIX_VECT129_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT129_ADDR_HI = 0x1a205 # macro +regPCIEMSIX_VECT129_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT129_MSG_DATA = 0x1a206 # macro +regPCIEMSIX_VECT129_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT129_CONTROL = 0x1a207 # macro +regPCIEMSIX_VECT129_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT130_ADDR_LO = 0x1a208 # macro +regPCIEMSIX_VECT130_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT130_ADDR_HI = 0x1a209 # macro +regPCIEMSIX_VECT130_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT130_MSG_DATA = 0x1a20a # macro +regPCIEMSIX_VECT130_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT130_CONTROL = 0x1a20b # macro +regPCIEMSIX_VECT130_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT131_ADDR_LO = 0x1a20c # macro +regPCIEMSIX_VECT131_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT131_ADDR_HI = 0x1a20d # macro +regPCIEMSIX_VECT131_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT131_MSG_DATA = 0x1a20e # macro +regPCIEMSIX_VECT131_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT131_CONTROL = 0x1a20f # macro +regPCIEMSIX_VECT131_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT132_ADDR_LO = 0x1a210 # macro +regPCIEMSIX_VECT132_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT132_ADDR_HI = 0x1a211 # macro +regPCIEMSIX_VECT132_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT132_MSG_DATA = 0x1a212 # macro +regPCIEMSIX_VECT132_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT132_CONTROL = 0x1a213 # macro +regPCIEMSIX_VECT132_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT133_ADDR_LO = 0x1a214 # macro +regPCIEMSIX_VECT133_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT133_ADDR_HI = 0x1a215 # macro +regPCIEMSIX_VECT133_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT133_MSG_DATA = 0x1a216 # macro +regPCIEMSIX_VECT133_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT133_CONTROL = 0x1a217 # macro +regPCIEMSIX_VECT133_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT134_ADDR_LO = 0x1a218 # macro +regPCIEMSIX_VECT134_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT134_ADDR_HI = 0x1a219 # macro +regPCIEMSIX_VECT134_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT134_MSG_DATA = 0x1a21a # macro +regPCIEMSIX_VECT134_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT134_CONTROL = 0x1a21b # macro +regPCIEMSIX_VECT134_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT135_ADDR_LO = 0x1a21c # macro +regPCIEMSIX_VECT135_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT135_ADDR_HI = 0x1a21d # macro +regPCIEMSIX_VECT135_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT135_MSG_DATA = 0x1a21e # macro +regPCIEMSIX_VECT135_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT135_CONTROL = 0x1a21f # macro +regPCIEMSIX_VECT135_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT136_ADDR_LO = 0x1a220 # macro +regPCIEMSIX_VECT136_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT136_ADDR_HI = 0x1a221 # macro +regPCIEMSIX_VECT136_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT136_MSG_DATA = 0x1a222 # macro +regPCIEMSIX_VECT136_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT136_CONTROL = 0x1a223 # macro +regPCIEMSIX_VECT136_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT137_ADDR_LO = 0x1a224 # macro +regPCIEMSIX_VECT137_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT137_ADDR_HI = 0x1a225 # macro +regPCIEMSIX_VECT137_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT137_MSG_DATA = 0x1a226 # macro +regPCIEMSIX_VECT137_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT137_CONTROL = 0x1a227 # macro +regPCIEMSIX_VECT137_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT138_ADDR_LO = 0x1a228 # macro +regPCIEMSIX_VECT138_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT138_ADDR_HI = 0x1a229 # macro +regPCIEMSIX_VECT138_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT138_MSG_DATA = 0x1a22a # macro +regPCIEMSIX_VECT138_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT138_CONTROL = 0x1a22b # macro +regPCIEMSIX_VECT138_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT139_ADDR_LO = 0x1a22c # macro +regPCIEMSIX_VECT139_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT139_ADDR_HI = 0x1a22d # macro +regPCIEMSIX_VECT139_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT139_MSG_DATA = 0x1a22e # macro +regPCIEMSIX_VECT139_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT139_CONTROL = 0x1a22f # macro +regPCIEMSIX_VECT139_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT140_ADDR_LO = 0x1a230 # macro +regPCIEMSIX_VECT140_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT140_ADDR_HI = 0x1a231 # macro +regPCIEMSIX_VECT140_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT140_MSG_DATA = 0x1a232 # macro +regPCIEMSIX_VECT140_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT140_CONTROL = 0x1a233 # macro +regPCIEMSIX_VECT140_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT141_ADDR_LO = 0x1a234 # macro +regPCIEMSIX_VECT141_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT141_ADDR_HI = 0x1a235 # macro +regPCIEMSIX_VECT141_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT141_MSG_DATA = 0x1a236 # macro +regPCIEMSIX_VECT141_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT141_CONTROL = 0x1a237 # macro +regPCIEMSIX_VECT141_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT142_ADDR_LO = 0x1a238 # macro +regPCIEMSIX_VECT142_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT142_ADDR_HI = 0x1a239 # macro +regPCIEMSIX_VECT142_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT142_MSG_DATA = 0x1a23a # macro +regPCIEMSIX_VECT142_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT142_CONTROL = 0x1a23b # macro +regPCIEMSIX_VECT142_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT143_ADDR_LO = 0x1a23c # macro +regPCIEMSIX_VECT143_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT143_ADDR_HI = 0x1a23d # macro +regPCIEMSIX_VECT143_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT143_MSG_DATA = 0x1a23e # macro +regPCIEMSIX_VECT143_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT143_CONTROL = 0x1a23f # macro +regPCIEMSIX_VECT143_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT144_ADDR_LO = 0x1a240 # macro +regPCIEMSIX_VECT144_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT144_ADDR_HI = 0x1a241 # macro +regPCIEMSIX_VECT144_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT144_MSG_DATA = 0x1a242 # macro +regPCIEMSIX_VECT144_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT144_CONTROL = 0x1a243 # macro +regPCIEMSIX_VECT144_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT145_ADDR_LO = 0x1a244 # macro +regPCIEMSIX_VECT145_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT145_ADDR_HI = 0x1a245 # macro +regPCIEMSIX_VECT145_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT145_MSG_DATA = 0x1a246 # macro +regPCIEMSIX_VECT145_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT145_CONTROL = 0x1a247 # macro +regPCIEMSIX_VECT145_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT146_ADDR_LO = 0x1a248 # macro +regPCIEMSIX_VECT146_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT146_ADDR_HI = 0x1a249 # macro +regPCIEMSIX_VECT146_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT146_MSG_DATA = 0x1a24a # macro +regPCIEMSIX_VECT146_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT146_CONTROL = 0x1a24b # macro +regPCIEMSIX_VECT146_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT147_ADDR_LO = 0x1a24c # macro +regPCIEMSIX_VECT147_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT147_ADDR_HI = 0x1a24d # macro +regPCIEMSIX_VECT147_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT147_MSG_DATA = 0x1a24e # macro +regPCIEMSIX_VECT147_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT147_CONTROL = 0x1a24f # macro +regPCIEMSIX_VECT147_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT148_ADDR_LO = 0x1a250 # macro +regPCIEMSIX_VECT148_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT148_ADDR_HI = 0x1a251 # macro +regPCIEMSIX_VECT148_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT148_MSG_DATA = 0x1a252 # macro +regPCIEMSIX_VECT148_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT148_CONTROL = 0x1a253 # macro +regPCIEMSIX_VECT148_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT149_ADDR_LO = 0x1a254 # macro +regPCIEMSIX_VECT149_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT149_ADDR_HI = 0x1a255 # macro +regPCIEMSIX_VECT149_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT149_MSG_DATA = 0x1a256 # macro +regPCIEMSIX_VECT149_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT149_CONTROL = 0x1a257 # macro +regPCIEMSIX_VECT149_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT150_ADDR_LO = 0x1a258 # macro +regPCIEMSIX_VECT150_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT150_ADDR_HI = 0x1a259 # macro +regPCIEMSIX_VECT150_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT150_MSG_DATA = 0x1a25a # macro +regPCIEMSIX_VECT150_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT150_CONTROL = 0x1a25b # macro +regPCIEMSIX_VECT150_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT151_ADDR_LO = 0x1a25c # macro +regPCIEMSIX_VECT151_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT151_ADDR_HI = 0x1a25d # macro +regPCIEMSIX_VECT151_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT151_MSG_DATA = 0x1a25e # macro +regPCIEMSIX_VECT151_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT151_CONTROL = 0x1a25f # macro +regPCIEMSIX_VECT151_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT152_ADDR_LO = 0x1a260 # macro +regPCIEMSIX_VECT152_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT152_ADDR_HI = 0x1a261 # macro +regPCIEMSIX_VECT152_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT152_MSG_DATA = 0x1a262 # macro +regPCIEMSIX_VECT152_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT152_CONTROL = 0x1a263 # macro +regPCIEMSIX_VECT152_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT153_ADDR_LO = 0x1a264 # macro +regPCIEMSIX_VECT153_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT153_ADDR_HI = 0x1a265 # macro +regPCIEMSIX_VECT153_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT153_MSG_DATA = 0x1a266 # macro +regPCIEMSIX_VECT153_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT153_CONTROL = 0x1a267 # macro +regPCIEMSIX_VECT153_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT154_ADDR_LO = 0x1a268 # macro +regPCIEMSIX_VECT154_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT154_ADDR_HI = 0x1a269 # macro +regPCIEMSIX_VECT154_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT154_MSG_DATA = 0x1a26a # macro +regPCIEMSIX_VECT154_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT154_CONTROL = 0x1a26b # macro +regPCIEMSIX_VECT154_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT155_ADDR_LO = 0x1a26c # macro +regPCIEMSIX_VECT155_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT155_ADDR_HI = 0x1a26d # macro +regPCIEMSIX_VECT155_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT155_MSG_DATA = 0x1a26e # macro +regPCIEMSIX_VECT155_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT155_CONTROL = 0x1a26f # macro +regPCIEMSIX_VECT155_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT156_ADDR_LO = 0x1a270 # macro +regPCIEMSIX_VECT156_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT156_ADDR_HI = 0x1a271 # macro +regPCIEMSIX_VECT156_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT156_MSG_DATA = 0x1a272 # macro +regPCIEMSIX_VECT156_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT156_CONTROL = 0x1a273 # macro +regPCIEMSIX_VECT156_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT157_ADDR_LO = 0x1a274 # macro +regPCIEMSIX_VECT157_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT157_ADDR_HI = 0x1a275 # macro +regPCIEMSIX_VECT157_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT157_MSG_DATA = 0x1a276 # macro +regPCIEMSIX_VECT157_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT157_CONTROL = 0x1a277 # macro +regPCIEMSIX_VECT157_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT158_ADDR_LO = 0x1a278 # macro +regPCIEMSIX_VECT158_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT158_ADDR_HI = 0x1a279 # macro +regPCIEMSIX_VECT158_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT158_MSG_DATA = 0x1a27a # macro +regPCIEMSIX_VECT158_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT158_CONTROL = 0x1a27b # macro +regPCIEMSIX_VECT158_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT159_ADDR_LO = 0x1a27c # macro +regPCIEMSIX_VECT159_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT159_ADDR_HI = 0x1a27d # macro +regPCIEMSIX_VECT159_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT159_MSG_DATA = 0x1a27e # macro +regPCIEMSIX_VECT159_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT159_CONTROL = 0x1a27f # macro +regPCIEMSIX_VECT159_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT160_ADDR_LO = 0x1a280 # macro +regPCIEMSIX_VECT160_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT160_ADDR_HI = 0x1a281 # macro +regPCIEMSIX_VECT160_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT160_MSG_DATA = 0x1a282 # macro +regPCIEMSIX_VECT160_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT160_CONTROL = 0x1a283 # macro +regPCIEMSIX_VECT160_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT161_ADDR_LO = 0x1a284 # macro +regPCIEMSIX_VECT161_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT161_ADDR_HI = 0x1a285 # macro +regPCIEMSIX_VECT161_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT161_MSG_DATA = 0x1a286 # macro +regPCIEMSIX_VECT161_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT161_CONTROL = 0x1a287 # macro +regPCIEMSIX_VECT161_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT162_ADDR_LO = 0x1a288 # macro +regPCIEMSIX_VECT162_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT162_ADDR_HI = 0x1a289 # macro +regPCIEMSIX_VECT162_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT162_MSG_DATA = 0x1a28a # macro +regPCIEMSIX_VECT162_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT162_CONTROL = 0x1a28b # macro +regPCIEMSIX_VECT162_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT163_ADDR_LO = 0x1a28c # macro +regPCIEMSIX_VECT163_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT163_ADDR_HI = 0x1a28d # macro +regPCIEMSIX_VECT163_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT163_MSG_DATA = 0x1a28e # macro +regPCIEMSIX_VECT163_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT163_CONTROL = 0x1a28f # macro +regPCIEMSIX_VECT163_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT164_ADDR_LO = 0x1a290 # macro +regPCIEMSIX_VECT164_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT164_ADDR_HI = 0x1a291 # macro +regPCIEMSIX_VECT164_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT164_MSG_DATA = 0x1a292 # macro +regPCIEMSIX_VECT164_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT164_CONTROL = 0x1a293 # macro +regPCIEMSIX_VECT164_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT165_ADDR_LO = 0x1a294 # macro +regPCIEMSIX_VECT165_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT165_ADDR_HI = 0x1a295 # macro +regPCIEMSIX_VECT165_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT165_MSG_DATA = 0x1a296 # macro +regPCIEMSIX_VECT165_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT165_CONTROL = 0x1a297 # macro +regPCIEMSIX_VECT165_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT166_ADDR_LO = 0x1a298 # macro +regPCIEMSIX_VECT166_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT166_ADDR_HI = 0x1a299 # macro +regPCIEMSIX_VECT166_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT166_MSG_DATA = 0x1a29a # macro +regPCIEMSIX_VECT166_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT166_CONTROL = 0x1a29b # macro +regPCIEMSIX_VECT166_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT167_ADDR_LO = 0x1a29c # macro +regPCIEMSIX_VECT167_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT167_ADDR_HI = 0x1a29d # macro +regPCIEMSIX_VECT167_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT167_MSG_DATA = 0x1a29e # macro +regPCIEMSIX_VECT167_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT167_CONTROL = 0x1a29f # macro +regPCIEMSIX_VECT167_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT168_ADDR_LO = 0x1a2a0 # macro +regPCIEMSIX_VECT168_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT168_ADDR_HI = 0x1a2a1 # macro +regPCIEMSIX_VECT168_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT168_MSG_DATA = 0x1a2a2 # macro +regPCIEMSIX_VECT168_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT168_CONTROL = 0x1a2a3 # macro +regPCIEMSIX_VECT168_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT169_ADDR_LO = 0x1a2a4 # macro +regPCIEMSIX_VECT169_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT169_ADDR_HI = 0x1a2a5 # macro +regPCIEMSIX_VECT169_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT169_MSG_DATA = 0x1a2a6 # macro +regPCIEMSIX_VECT169_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT169_CONTROL = 0x1a2a7 # macro +regPCIEMSIX_VECT169_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT170_ADDR_LO = 0x1a2a8 # macro +regPCIEMSIX_VECT170_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT170_ADDR_HI = 0x1a2a9 # macro +regPCIEMSIX_VECT170_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT170_MSG_DATA = 0x1a2aa # macro +regPCIEMSIX_VECT170_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT170_CONTROL = 0x1a2ab # macro +regPCIEMSIX_VECT170_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT171_ADDR_LO = 0x1a2ac # macro +regPCIEMSIX_VECT171_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT171_ADDR_HI = 0x1a2ad # macro +regPCIEMSIX_VECT171_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT171_MSG_DATA = 0x1a2ae # macro +regPCIEMSIX_VECT171_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT171_CONTROL = 0x1a2af # macro +regPCIEMSIX_VECT171_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT172_ADDR_LO = 0x1a2b0 # macro +regPCIEMSIX_VECT172_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT172_ADDR_HI = 0x1a2b1 # macro +regPCIEMSIX_VECT172_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT172_MSG_DATA = 0x1a2b2 # macro +regPCIEMSIX_VECT172_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT172_CONTROL = 0x1a2b3 # macro +regPCIEMSIX_VECT172_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT173_ADDR_LO = 0x1a2b4 # macro +regPCIEMSIX_VECT173_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT173_ADDR_HI = 0x1a2b5 # macro +regPCIEMSIX_VECT173_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT173_MSG_DATA = 0x1a2b6 # macro +regPCIEMSIX_VECT173_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT173_CONTROL = 0x1a2b7 # macro +regPCIEMSIX_VECT173_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT174_ADDR_LO = 0x1a2b8 # macro +regPCIEMSIX_VECT174_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT174_ADDR_HI = 0x1a2b9 # macro +regPCIEMSIX_VECT174_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT174_MSG_DATA = 0x1a2ba # macro +regPCIEMSIX_VECT174_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT174_CONTROL = 0x1a2bb # macro +regPCIEMSIX_VECT174_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT175_ADDR_LO = 0x1a2bc # macro +regPCIEMSIX_VECT175_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT175_ADDR_HI = 0x1a2bd # macro +regPCIEMSIX_VECT175_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT175_MSG_DATA = 0x1a2be # macro +regPCIEMSIX_VECT175_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT175_CONTROL = 0x1a2bf # macro +regPCIEMSIX_VECT175_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT176_ADDR_LO = 0x1a2c0 # macro +regPCIEMSIX_VECT176_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT176_ADDR_HI = 0x1a2c1 # macro +regPCIEMSIX_VECT176_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT176_MSG_DATA = 0x1a2c2 # macro +regPCIEMSIX_VECT176_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT176_CONTROL = 0x1a2c3 # macro +regPCIEMSIX_VECT176_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT177_ADDR_LO = 0x1a2c4 # macro +regPCIEMSIX_VECT177_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT177_ADDR_HI = 0x1a2c5 # macro +regPCIEMSIX_VECT177_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT177_MSG_DATA = 0x1a2c6 # macro +regPCIEMSIX_VECT177_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT177_CONTROL = 0x1a2c7 # macro +regPCIEMSIX_VECT177_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT178_ADDR_LO = 0x1a2c8 # macro +regPCIEMSIX_VECT178_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT178_ADDR_HI = 0x1a2c9 # macro +regPCIEMSIX_VECT178_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT178_MSG_DATA = 0x1a2ca # macro +regPCIEMSIX_VECT178_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT178_CONTROL = 0x1a2cb # macro +regPCIEMSIX_VECT178_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT179_ADDR_LO = 0x1a2cc # macro +regPCIEMSIX_VECT179_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT179_ADDR_HI = 0x1a2cd # macro +regPCIEMSIX_VECT179_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT179_MSG_DATA = 0x1a2ce # macro +regPCIEMSIX_VECT179_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT179_CONTROL = 0x1a2cf # macro +regPCIEMSIX_VECT179_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT180_ADDR_LO = 0x1a2d0 # macro +regPCIEMSIX_VECT180_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT180_ADDR_HI = 0x1a2d1 # macro +regPCIEMSIX_VECT180_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT180_MSG_DATA = 0x1a2d2 # macro +regPCIEMSIX_VECT180_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT180_CONTROL = 0x1a2d3 # macro +regPCIEMSIX_VECT180_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT181_ADDR_LO = 0x1a2d4 # macro +regPCIEMSIX_VECT181_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT181_ADDR_HI = 0x1a2d5 # macro +regPCIEMSIX_VECT181_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT181_MSG_DATA = 0x1a2d6 # macro +regPCIEMSIX_VECT181_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT181_CONTROL = 0x1a2d7 # macro +regPCIEMSIX_VECT181_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT182_ADDR_LO = 0x1a2d8 # macro +regPCIEMSIX_VECT182_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT182_ADDR_HI = 0x1a2d9 # macro +regPCIEMSIX_VECT182_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT182_MSG_DATA = 0x1a2da # macro +regPCIEMSIX_VECT182_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT182_CONTROL = 0x1a2db # macro +regPCIEMSIX_VECT182_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT183_ADDR_LO = 0x1a2dc # macro +regPCIEMSIX_VECT183_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT183_ADDR_HI = 0x1a2dd # macro +regPCIEMSIX_VECT183_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT183_MSG_DATA = 0x1a2de # macro +regPCIEMSIX_VECT183_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT183_CONTROL = 0x1a2df # macro +regPCIEMSIX_VECT183_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT184_ADDR_LO = 0x1a2e0 # macro +regPCIEMSIX_VECT184_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT184_ADDR_HI = 0x1a2e1 # macro +regPCIEMSIX_VECT184_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT184_MSG_DATA = 0x1a2e2 # macro +regPCIEMSIX_VECT184_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT184_CONTROL = 0x1a2e3 # macro +regPCIEMSIX_VECT184_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT185_ADDR_LO = 0x1a2e4 # macro +regPCIEMSIX_VECT185_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT185_ADDR_HI = 0x1a2e5 # macro +regPCIEMSIX_VECT185_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT185_MSG_DATA = 0x1a2e6 # macro +regPCIEMSIX_VECT185_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT185_CONTROL = 0x1a2e7 # macro +regPCIEMSIX_VECT185_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT186_ADDR_LO = 0x1a2e8 # macro +regPCIEMSIX_VECT186_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT186_ADDR_HI = 0x1a2e9 # macro +regPCIEMSIX_VECT186_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT186_MSG_DATA = 0x1a2ea # macro +regPCIEMSIX_VECT186_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT186_CONTROL = 0x1a2eb # macro +regPCIEMSIX_VECT186_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT187_ADDR_LO = 0x1a2ec # macro +regPCIEMSIX_VECT187_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT187_ADDR_HI = 0x1a2ed # macro +regPCIEMSIX_VECT187_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT187_MSG_DATA = 0x1a2ee # macro +regPCIEMSIX_VECT187_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT187_CONTROL = 0x1a2ef # macro +regPCIEMSIX_VECT187_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT188_ADDR_LO = 0x1a2f0 # macro +regPCIEMSIX_VECT188_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT188_ADDR_HI = 0x1a2f1 # macro +regPCIEMSIX_VECT188_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT188_MSG_DATA = 0x1a2f2 # macro +regPCIEMSIX_VECT188_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT188_CONTROL = 0x1a2f3 # macro +regPCIEMSIX_VECT188_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT189_ADDR_LO = 0x1a2f4 # macro +regPCIEMSIX_VECT189_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT189_ADDR_HI = 0x1a2f5 # macro +regPCIEMSIX_VECT189_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT189_MSG_DATA = 0x1a2f6 # macro +regPCIEMSIX_VECT189_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT189_CONTROL = 0x1a2f7 # macro +regPCIEMSIX_VECT189_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT190_ADDR_LO = 0x1a2f8 # macro +regPCIEMSIX_VECT190_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT190_ADDR_HI = 0x1a2f9 # macro +regPCIEMSIX_VECT190_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT190_MSG_DATA = 0x1a2fa # macro +regPCIEMSIX_VECT190_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT190_CONTROL = 0x1a2fb # macro +regPCIEMSIX_VECT190_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT191_ADDR_LO = 0x1a2fc # macro +regPCIEMSIX_VECT191_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT191_ADDR_HI = 0x1a2fd # macro +regPCIEMSIX_VECT191_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT191_MSG_DATA = 0x1a2fe # macro +regPCIEMSIX_VECT191_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT191_CONTROL = 0x1a2ff # macro +regPCIEMSIX_VECT191_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT192_ADDR_LO = 0x1a300 # macro +regPCIEMSIX_VECT192_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT192_ADDR_HI = 0x1a301 # macro +regPCIEMSIX_VECT192_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT192_MSG_DATA = 0x1a302 # macro +regPCIEMSIX_VECT192_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT192_CONTROL = 0x1a303 # macro +regPCIEMSIX_VECT192_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT193_ADDR_LO = 0x1a304 # macro +regPCIEMSIX_VECT193_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT193_ADDR_HI = 0x1a305 # macro +regPCIEMSIX_VECT193_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT193_MSG_DATA = 0x1a306 # macro +regPCIEMSIX_VECT193_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT193_CONTROL = 0x1a307 # macro +regPCIEMSIX_VECT193_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT194_ADDR_LO = 0x1a308 # macro +regPCIEMSIX_VECT194_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT194_ADDR_HI = 0x1a309 # macro +regPCIEMSIX_VECT194_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT194_MSG_DATA = 0x1a30a # macro +regPCIEMSIX_VECT194_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT194_CONTROL = 0x1a30b # macro +regPCIEMSIX_VECT194_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT195_ADDR_LO = 0x1a30c # macro +regPCIEMSIX_VECT195_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT195_ADDR_HI = 0x1a30d # macro +regPCIEMSIX_VECT195_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT195_MSG_DATA = 0x1a30e # macro +regPCIEMSIX_VECT195_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT195_CONTROL = 0x1a30f # macro +regPCIEMSIX_VECT195_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT196_ADDR_LO = 0x1a310 # macro +regPCIEMSIX_VECT196_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT196_ADDR_HI = 0x1a311 # macro +regPCIEMSIX_VECT196_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT196_MSG_DATA = 0x1a312 # macro +regPCIEMSIX_VECT196_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT196_CONTROL = 0x1a313 # macro +regPCIEMSIX_VECT196_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT197_ADDR_LO = 0x1a314 # macro +regPCIEMSIX_VECT197_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT197_ADDR_HI = 0x1a315 # macro +regPCIEMSIX_VECT197_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT197_MSG_DATA = 0x1a316 # macro +regPCIEMSIX_VECT197_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT197_CONTROL = 0x1a317 # macro +regPCIEMSIX_VECT197_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT198_ADDR_LO = 0x1a318 # macro +regPCIEMSIX_VECT198_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT198_ADDR_HI = 0x1a319 # macro +regPCIEMSIX_VECT198_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT198_MSG_DATA = 0x1a31a # macro +regPCIEMSIX_VECT198_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT198_CONTROL = 0x1a31b # macro +regPCIEMSIX_VECT198_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT199_ADDR_LO = 0x1a31c # macro +regPCIEMSIX_VECT199_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT199_ADDR_HI = 0x1a31d # macro +regPCIEMSIX_VECT199_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT199_MSG_DATA = 0x1a31e # macro +regPCIEMSIX_VECT199_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT199_CONTROL = 0x1a31f # macro +regPCIEMSIX_VECT199_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT200_ADDR_LO = 0x1a320 # macro +regPCIEMSIX_VECT200_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT200_ADDR_HI = 0x1a321 # macro +regPCIEMSIX_VECT200_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT200_MSG_DATA = 0x1a322 # macro +regPCIEMSIX_VECT200_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT200_CONTROL = 0x1a323 # macro +regPCIEMSIX_VECT200_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT201_ADDR_LO = 0x1a324 # macro +regPCIEMSIX_VECT201_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT201_ADDR_HI = 0x1a325 # macro +regPCIEMSIX_VECT201_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT201_MSG_DATA = 0x1a326 # macro +regPCIEMSIX_VECT201_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT201_CONTROL = 0x1a327 # macro +regPCIEMSIX_VECT201_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT202_ADDR_LO = 0x1a328 # macro +regPCIEMSIX_VECT202_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT202_ADDR_HI = 0x1a329 # macro +regPCIEMSIX_VECT202_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT202_MSG_DATA = 0x1a32a # macro +regPCIEMSIX_VECT202_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT202_CONTROL = 0x1a32b # macro +regPCIEMSIX_VECT202_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT203_ADDR_LO = 0x1a32c # macro +regPCIEMSIX_VECT203_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT203_ADDR_HI = 0x1a32d # macro +regPCIEMSIX_VECT203_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT203_MSG_DATA = 0x1a32e # macro +regPCIEMSIX_VECT203_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT203_CONTROL = 0x1a32f # macro +regPCIEMSIX_VECT203_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT204_ADDR_LO = 0x1a330 # macro +regPCIEMSIX_VECT204_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT204_ADDR_HI = 0x1a331 # macro +regPCIEMSIX_VECT204_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT204_MSG_DATA = 0x1a332 # macro +regPCIEMSIX_VECT204_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT204_CONTROL = 0x1a333 # macro +regPCIEMSIX_VECT204_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT205_ADDR_LO = 0x1a334 # macro +regPCIEMSIX_VECT205_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT205_ADDR_HI = 0x1a335 # macro +regPCIEMSIX_VECT205_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT205_MSG_DATA = 0x1a336 # macro +regPCIEMSIX_VECT205_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT205_CONTROL = 0x1a337 # macro +regPCIEMSIX_VECT205_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT206_ADDR_LO = 0x1a338 # macro +regPCIEMSIX_VECT206_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT206_ADDR_HI = 0x1a339 # macro +regPCIEMSIX_VECT206_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT206_MSG_DATA = 0x1a33a # macro +regPCIEMSIX_VECT206_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT206_CONTROL = 0x1a33b # macro +regPCIEMSIX_VECT206_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT207_ADDR_LO = 0x1a33c # macro +regPCIEMSIX_VECT207_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT207_ADDR_HI = 0x1a33d # macro +regPCIEMSIX_VECT207_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT207_MSG_DATA = 0x1a33e # macro +regPCIEMSIX_VECT207_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT207_CONTROL = 0x1a33f # macro +regPCIEMSIX_VECT207_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT208_ADDR_LO = 0x1a340 # macro +regPCIEMSIX_VECT208_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT208_ADDR_HI = 0x1a341 # macro +regPCIEMSIX_VECT208_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT208_MSG_DATA = 0x1a342 # macro +regPCIEMSIX_VECT208_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT208_CONTROL = 0x1a343 # macro +regPCIEMSIX_VECT208_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT209_ADDR_LO = 0x1a344 # macro +regPCIEMSIX_VECT209_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT209_ADDR_HI = 0x1a345 # macro +regPCIEMSIX_VECT209_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT209_MSG_DATA = 0x1a346 # macro +regPCIEMSIX_VECT209_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT209_CONTROL = 0x1a347 # macro +regPCIEMSIX_VECT209_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT210_ADDR_LO = 0x1a348 # macro +regPCIEMSIX_VECT210_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT210_ADDR_HI = 0x1a349 # macro +regPCIEMSIX_VECT210_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT210_MSG_DATA = 0x1a34a # macro +regPCIEMSIX_VECT210_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT210_CONTROL = 0x1a34b # macro +regPCIEMSIX_VECT210_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT211_ADDR_LO = 0x1a34c # macro +regPCIEMSIX_VECT211_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT211_ADDR_HI = 0x1a34d # macro +regPCIEMSIX_VECT211_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT211_MSG_DATA = 0x1a34e # macro +regPCIEMSIX_VECT211_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT211_CONTROL = 0x1a34f # macro +regPCIEMSIX_VECT211_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT212_ADDR_LO = 0x1a350 # macro +regPCIEMSIX_VECT212_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT212_ADDR_HI = 0x1a351 # macro +regPCIEMSIX_VECT212_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT212_MSG_DATA = 0x1a352 # macro +regPCIEMSIX_VECT212_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT212_CONTROL = 0x1a353 # macro +regPCIEMSIX_VECT212_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT213_ADDR_LO = 0x1a354 # macro +regPCIEMSIX_VECT213_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT213_ADDR_HI = 0x1a355 # macro +regPCIEMSIX_VECT213_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT213_MSG_DATA = 0x1a356 # macro +regPCIEMSIX_VECT213_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT213_CONTROL = 0x1a357 # macro +regPCIEMSIX_VECT213_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT214_ADDR_LO = 0x1a358 # macro +regPCIEMSIX_VECT214_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT214_ADDR_HI = 0x1a359 # macro +regPCIEMSIX_VECT214_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT214_MSG_DATA = 0x1a35a # macro +regPCIEMSIX_VECT214_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT214_CONTROL = 0x1a35b # macro +regPCIEMSIX_VECT214_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT215_ADDR_LO = 0x1a35c # macro +regPCIEMSIX_VECT215_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT215_ADDR_HI = 0x1a35d # macro +regPCIEMSIX_VECT215_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT215_MSG_DATA = 0x1a35e # macro +regPCIEMSIX_VECT215_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT215_CONTROL = 0x1a35f # macro +regPCIEMSIX_VECT215_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT216_ADDR_LO = 0x1a360 # macro +regPCIEMSIX_VECT216_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT216_ADDR_HI = 0x1a361 # macro +regPCIEMSIX_VECT216_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT216_MSG_DATA = 0x1a362 # macro +regPCIEMSIX_VECT216_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT216_CONTROL = 0x1a363 # macro +regPCIEMSIX_VECT216_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT217_ADDR_LO = 0x1a364 # macro +regPCIEMSIX_VECT217_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT217_ADDR_HI = 0x1a365 # macro +regPCIEMSIX_VECT217_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT217_MSG_DATA = 0x1a366 # macro +regPCIEMSIX_VECT217_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT217_CONTROL = 0x1a367 # macro +regPCIEMSIX_VECT217_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT218_ADDR_LO = 0x1a368 # macro +regPCIEMSIX_VECT218_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT218_ADDR_HI = 0x1a369 # macro +regPCIEMSIX_VECT218_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT218_MSG_DATA = 0x1a36a # macro +regPCIEMSIX_VECT218_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT218_CONTROL = 0x1a36b # macro +regPCIEMSIX_VECT218_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT219_ADDR_LO = 0x1a36c # macro +regPCIEMSIX_VECT219_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT219_ADDR_HI = 0x1a36d # macro +regPCIEMSIX_VECT219_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT219_MSG_DATA = 0x1a36e # macro +regPCIEMSIX_VECT219_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT219_CONTROL = 0x1a36f # macro +regPCIEMSIX_VECT219_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT220_ADDR_LO = 0x1a370 # macro +regPCIEMSIX_VECT220_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT220_ADDR_HI = 0x1a371 # macro +regPCIEMSIX_VECT220_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT220_MSG_DATA = 0x1a372 # macro +regPCIEMSIX_VECT220_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT220_CONTROL = 0x1a373 # macro +regPCIEMSIX_VECT220_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT221_ADDR_LO = 0x1a374 # macro +regPCIEMSIX_VECT221_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT221_ADDR_HI = 0x1a375 # macro +regPCIEMSIX_VECT221_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT221_MSG_DATA = 0x1a376 # macro +regPCIEMSIX_VECT221_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT221_CONTROL = 0x1a377 # macro +regPCIEMSIX_VECT221_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT222_ADDR_LO = 0x1a378 # macro +regPCIEMSIX_VECT222_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT222_ADDR_HI = 0x1a379 # macro +regPCIEMSIX_VECT222_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT222_MSG_DATA = 0x1a37a # macro +regPCIEMSIX_VECT222_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT222_CONTROL = 0x1a37b # macro +regPCIEMSIX_VECT222_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT223_ADDR_LO = 0x1a37c # macro +regPCIEMSIX_VECT223_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT223_ADDR_HI = 0x1a37d # macro +regPCIEMSIX_VECT223_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT223_MSG_DATA = 0x1a37e # macro +regPCIEMSIX_VECT223_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT223_CONTROL = 0x1a37f # macro +regPCIEMSIX_VECT223_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT224_ADDR_LO = 0x1a380 # macro +regPCIEMSIX_VECT224_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT224_ADDR_HI = 0x1a381 # macro +regPCIEMSIX_VECT224_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT224_MSG_DATA = 0x1a382 # macro +regPCIEMSIX_VECT224_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT224_CONTROL = 0x1a383 # macro +regPCIEMSIX_VECT224_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT225_ADDR_LO = 0x1a384 # macro +regPCIEMSIX_VECT225_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT225_ADDR_HI = 0x1a385 # macro +regPCIEMSIX_VECT225_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT225_MSG_DATA = 0x1a386 # macro +regPCIEMSIX_VECT225_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT225_CONTROL = 0x1a387 # macro +regPCIEMSIX_VECT225_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT226_ADDR_LO = 0x1a388 # macro +regPCIEMSIX_VECT226_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT226_ADDR_HI = 0x1a389 # macro +regPCIEMSIX_VECT226_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT226_MSG_DATA = 0x1a38a # macro +regPCIEMSIX_VECT226_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT226_CONTROL = 0x1a38b # macro +regPCIEMSIX_VECT226_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT227_ADDR_LO = 0x1a38c # macro +regPCIEMSIX_VECT227_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT227_ADDR_HI = 0x1a38d # macro +regPCIEMSIX_VECT227_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT227_MSG_DATA = 0x1a38e # macro +regPCIEMSIX_VECT227_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT227_CONTROL = 0x1a38f # macro +regPCIEMSIX_VECT227_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT228_ADDR_LO = 0x1a390 # macro +regPCIEMSIX_VECT228_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT228_ADDR_HI = 0x1a391 # macro +regPCIEMSIX_VECT228_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT228_MSG_DATA = 0x1a392 # macro +regPCIEMSIX_VECT228_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT228_CONTROL = 0x1a393 # macro +regPCIEMSIX_VECT228_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT229_ADDR_LO = 0x1a394 # macro +regPCIEMSIX_VECT229_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT229_ADDR_HI = 0x1a395 # macro +regPCIEMSIX_VECT229_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT229_MSG_DATA = 0x1a396 # macro +regPCIEMSIX_VECT229_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT229_CONTROL = 0x1a397 # macro +regPCIEMSIX_VECT229_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT230_ADDR_LO = 0x1a398 # macro +regPCIEMSIX_VECT230_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT230_ADDR_HI = 0x1a399 # macro +regPCIEMSIX_VECT230_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT230_MSG_DATA = 0x1a39a # macro +regPCIEMSIX_VECT230_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT230_CONTROL = 0x1a39b # macro +regPCIEMSIX_VECT230_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT231_ADDR_LO = 0x1a39c # macro +regPCIEMSIX_VECT231_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT231_ADDR_HI = 0x1a39d # macro +regPCIEMSIX_VECT231_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT231_MSG_DATA = 0x1a39e # macro +regPCIEMSIX_VECT231_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT231_CONTROL = 0x1a39f # macro +regPCIEMSIX_VECT231_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT232_ADDR_LO = 0x1a3a0 # macro +regPCIEMSIX_VECT232_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT232_ADDR_HI = 0x1a3a1 # macro +regPCIEMSIX_VECT232_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT232_MSG_DATA = 0x1a3a2 # macro +regPCIEMSIX_VECT232_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT232_CONTROL = 0x1a3a3 # macro +regPCIEMSIX_VECT232_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT233_ADDR_LO = 0x1a3a4 # macro +regPCIEMSIX_VECT233_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT233_ADDR_HI = 0x1a3a5 # macro +regPCIEMSIX_VECT233_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT233_MSG_DATA = 0x1a3a6 # macro +regPCIEMSIX_VECT233_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT233_CONTROL = 0x1a3a7 # macro +regPCIEMSIX_VECT233_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT234_ADDR_LO = 0x1a3a8 # macro +regPCIEMSIX_VECT234_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT234_ADDR_HI = 0x1a3a9 # macro +regPCIEMSIX_VECT234_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT234_MSG_DATA = 0x1a3aa # macro +regPCIEMSIX_VECT234_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT234_CONTROL = 0x1a3ab # macro +regPCIEMSIX_VECT234_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT235_ADDR_LO = 0x1a3ac # macro +regPCIEMSIX_VECT235_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT235_ADDR_HI = 0x1a3ad # macro +regPCIEMSIX_VECT235_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT235_MSG_DATA = 0x1a3ae # macro +regPCIEMSIX_VECT235_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT235_CONTROL = 0x1a3af # macro +regPCIEMSIX_VECT235_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT236_ADDR_LO = 0x1a3b0 # macro +regPCIEMSIX_VECT236_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT236_ADDR_HI = 0x1a3b1 # macro +regPCIEMSIX_VECT236_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT236_MSG_DATA = 0x1a3b2 # macro +regPCIEMSIX_VECT236_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT236_CONTROL = 0x1a3b3 # macro +regPCIEMSIX_VECT236_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT237_ADDR_LO = 0x1a3b4 # macro +regPCIEMSIX_VECT237_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT237_ADDR_HI = 0x1a3b5 # macro +regPCIEMSIX_VECT237_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT237_MSG_DATA = 0x1a3b6 # macro +regPCIEMSIX_VECT237_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT237_CONTROL = 0x1a3b7 # macro +regPCIEMSIX_VECT237_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT238_ADDR_LO = 0x1a3b8 # macro +regPCIEMSIX_VECT238_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT238_ADDR_HI = 0x1a3b9 # macro +regPCIEMSIX_VECT238_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT238_MSG_DATA = 0x1a3ba # macro +regPCIEMSIX_VECT238_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT238_CONTROL = 0x1a3bb # macro +regPCIEMSIX_VECT238_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT239_ADDR_LO = 0x1a3bc # macro +regPCIEMSIX_VECT239_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT239_ADDR_HI = 0x1a3bd # macro +regPCIEMSIX_VECT239_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT239_MSG_DATA = 0x1a3be # macro +regPCIEMSIX_VECT239_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT239_CONTROL = 0x1a3bf # macro +regPCIEMSIX_VECT239_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT240_ADDR_LO = 0x1a3c0 # macro +regPCIEMSIX_VECT240_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT240_ADDR_HI = 0x1a3c1 # macro +regPCIEMSIX_VECT240_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT240_MSG_DATA = 0x1a3c2 # macro +regPCIEMSIX_VECT240_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT240_CONTROL = 0x1a3c3 # macro +regPCIEMSIX_VECT240_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT241_ADDR_LO = 0x1a3c4 # macro +regPCIEMSIX_VECT241_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT241_ADDR_HI = 0x1a3c5 # macro +regPCIEMSIX_VECT241_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT241_MSG_DATA = 0x1a3c6 # macro +regPCIEMSIX_VECT241_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT241_CONTROL = 0x1a3c7 # macro +regPCIEMSIX_VECT241_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT242_ADDR_LO = 0x1a3c8 # macro +regPCIEMSIX_VECT242_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT242_ADDR_HI = 0x1a3c9 # macro +regPCIEMSIX_VECT242_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT242_MSG_DATA = 0x1a3ca # macro +regPCIEMSIX_VECT242_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT242_CONTROL = 0x1a3cb # macro +regPCIEMSIX_VECT242_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT243_ADDR_LO = 0x1a3cc # macro +regPCIEMSIX_VECT243_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT243_ADDR_HI = 0x1a3cd # macro +regPCIEMSIX_VECT243_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT243_MSG_DATA = 0x1a3ce # macro +regPCIEMSIX_VECT243_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT243_CONTROL = 0x1a3cf # macro +regPCIEMSIX_VECT243_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT244_ADDR_LO = 0x1a3d0 # macro +regPCIEMSIX_VECT244_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT244_ADDR_HI = 0x1a3d1 # macro +regPCIEMSIX_VECT244_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT244_MSG_DATA = 0x1a3d2 # macro +regPCIEMSIX_VECT244_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT244_CONTROL = 0x1a3d3 # macro +regPCIEMSIX_VECT244_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT245_ADDR_LO = 0x1a3d4 # macro +regPCIEMSIX_VECT245_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT245_ADDR_HI = 0x1a3d5 # macro +regPCIEMSIX_VECT245_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT245_MSG_DATA = 0x1a3d6 # macro +regPCIEMSIX_VECT245_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT245_CONTROL = 0x1a3d7 # macro +regPCIEMSIX_VECT245_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT246_ADDR_LO = 0x1a3d8 # macro +regPCIEMSIX_VECT246_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT246_ADDR_HI = 0x1a3d9 # macro +regPCIEMSIX_VECT246_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT246_MSG_DATA = 0x1a3da # macro +regPCIEMSIX_VECT246_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT246_CONTROL = 0x1a3db # macro +regPCIEMSIX_VECT246_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT247_ADDR_LO = 0x1a3dc # macro +regPCIEMSIX_VECT247_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT247_ADDR_HI = 0x1a3dd # macro +regPCIEMSIX_VECT247_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT247_MSG_DATA = 0x1a3de # macro +regPCIEMSIX_VECT247_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT247_CONTROL = 0x1a3df # macro +regPCIEMSIX_VECT247_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT248_ADDR_LO = 0x1a3e0 # macro +regPCIEMSIX_VECT248_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT248_ADDR_HI = 0x1a3e1 # macro +regPCIEMSIX_VECT248_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT248_MSG_DATA = 0x1a3e2 # macro +regPCIEMSIX_VECT248_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT248_CONTROL = 0x1a3e3 # macro +regPCIEMSIX_VECT248_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT249_ADDR_LO = 0x1a3e4 # macro +regPCIEMSIX_VECT249_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT249_ADDR_HI = 0x1a3e5 # macro +regPCIEMSIX_VECT249_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT249_MSG_DATA = 0x1a3e6 # macro +regPCIEMSIX_VECT249_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT249_CONTROL = 0x1a3e7 # macro +regPCIEMSIX_VECT249_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT250_ADDR_LO = 0x1a3e8 # macro +regPCIEMSIX_VECT250_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT250_ADDR_HI = 0x1a3e9 # macro +regPCIEMSIX_VECT250_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT250_MSG_DATA = 0x1a3ea # macro +regPCIEMSIX_VECT250_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT250_CONTROL = 0x1a3eb # macro +regPCIEMSIX_VECT250_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT251_ADDR_LO = 0x1a3ec # macro +regPCIEMSIX_VECT251_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT251_ADDR_HI = 0x1a3ed # macro +regPCIEMSIX_VECT251_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT251_MSG_DATA = 0x1a3ee # macro +regPCIEMSIX_VECT251_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT251_CONTROL = 0x1a3ef # macro +regPCIEMSIX_VECT251_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT252_ADDR_LO = 0x1a3f0 # macro +regPCIEMSIX_VECT252_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT252_ADDR_HI = 0x1a3f1 # macro +regPCIEMSIX_VECT252_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT252_MSG_DATA = 0x1a3f2 # macro +regPCIEMSIX_VECT252_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT252_CONTROL = 0x1a3f3 # macro +regPCIEMSIX_VECT252_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT253_ADDR_LO = 0x1a3f4 # macro +regPCIEMSIX_VECT253_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT253_ADDR_HI = 0x1a3f5 # macro +regPCIEMSIX_VECT253_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT253_MSG_DATA = 0x1a3f6 # macro +regPCIEMSIX_VECT253_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT253_CONTROL = 0x1a3f7 # macro +regPCIEMSIX_VECT253_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT254_ADDR_LO = 0x1a3f8 # macro +regPCIEMSIX_VECT254_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT254_ADDR_HI = 0x1a3f9 # macro +regPCIEMSIX_VECT254_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT254_MSG_DATA = 0x1a3fa # macro +regPCIEMSIX_VECT254_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT254_CONTROL = 0x1a3fb # macro +regPCIEMSIX_VECT254_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_VECT255_ADDR_LO = 0x1a3fc # macro +regPCIEMSIX_VECT255_ADDR_LO_BASE_IDX = 8 # macro +regPCIEMSIX_VECT255_ADDR_HI = 0x1a3fd # macro +regPCIEMSIX_VECT255_ADDR_HI_BASE_IDX = 8 # macro +regPCIEMSIX_VECT255_MSG_DATA = 0x1a3fe # macro +regPCIEMSIX_VECT255_MSG_DATA_BASE_IDX = 8 # macro +regPCIEMSIX_VECT255_CONTROL = 0x1a3ff # macro +regPCIEMSIX_VECT255_CONTROL_BASE_IDX = 8 # macro +regPCIEMSIX_PBA_0 = 0x1a400 # macro +regPCIEMSIX_PBA_0_BASE_IDX = 8 # macro +regPCIEMSIX_PBA_1 = 0x1a401 # macro +regPCIEMSIX_PBA_1_BASE_IDX = 8 # macro +regPCIEMSIX_PBA_2 = 0x1a402 # macro +regPCIEMSIX_PBA_2_BASE_IDX = 8 # macro +regPCIEMSIX_PBA_3 = 0x1a403 # macro +regPCIEMSIX_PBA_3_BASE_IDX = 8 # macro +regPCIEMSIX_PBA_4 = 0x1a404 # macro +regPCIEMSIX_PBA_4_BASE_IDX = 8 # macro +regPCIEMSIX_PBA_5 = 0x1a405 # macro +regPCIEMSIX_PBA_5_BASE_IDX = 8 # macro +regPCIEMSIX_PBA_6 = 0x1a406 # macro +regPCIEMSIX_PBA_6_BASE_IDX = 8 # macro +regPCIEMSIX_PBA_7 = 0x1a407 # macro +regPCIEMSIX_PBA_7_BASE_IDX = 8 # macro +regSUM_INDEX = 0xec38 # macro +regSUM_INDEX_BASE_IDX = 8 # macro +regSUM_DATA = 0xec39 # macro +regSUM_DATA_BASE_IDX = 8 # macro +regSUM_INDEX_HI = 0xec3b # macro +regSUM_INDEX_HI_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP0 = 0xc400 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP0_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP1 = 0xc401 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP1_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP2 = 0xc402 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP2_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP3 = 0xc403 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP3_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP4 = 0xc404 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP4_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP5 = 0xc405 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP5_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP6 = 0xc406 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP6_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP7 = 0xc407 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP7_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP8 = 0xc408 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP8_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP9 = 0xc409 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP9_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP10 = 0xc40a # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP10_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP11 = 0xc40b # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP11_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP12 = 0xc40c # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP12_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP13 = 0xc40d # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP13_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP14 = 0xc40e # macro +regRCC_STRAP1_RCC_DEV0_PORT_STRAP14_BASE_IDX = 8 # macro +regRCC_DEV1_PORT_STRAP0 = 0xc480 # macro +regRCC_DEV1_PORT_STRAP0_BASE_IDX = 8 # macro +regRCC_DEV1_PORT_STRAP1 = 0xc481 # macro +regRCC_DEV1_PORT_STRAP1_BASE_IDX = 8 # macro +regRCC_DEV1_PORT_STRAP2 = 0xc482 # macro +regRCC_DEV1_PORT_STRAP2_BASE_IDX = 8 # macro +regRCC_DEV1_PORT_STRAP3 = 0xc483 # macro +regRCC_DEV1_PORT_STRAP3_BASE_IDX = 8 # macro +regRCC_DEV1_PORT_STRAP4 = 0xc484 # macro +regRCC_DEV1_PORT_STRAP4_BASE_IDX = 8 # macro +regRCC_DEV1_PORT_STRAP5 = 0xc485 # macro +regRCC_DEV1_PORT_STRAP5_BASE_IDX = 8 # macro +regRCC_DEV1_PORT_STRAP6 = 0xc486 # macro +regRCC_DEV1_PORT_STRAP6_BASE_IDX = 8 # macro +regRCC_DEV1_PORT_STRAP7 = 0xc487 # macro +regRCC_DEV1_PORT_STRAP7_BASE_IDX = 8 # macro +regRCC_DEV1_PORT_STRAP8 = 0xc488 # macro +regRCC_DEV1_PORT_STRAP8_BASE_IDX = 8 # macro +regRCC_DEV1_PORT_STRAP9 = 0xc489 # macro +regRCC_DEV1_PORT_STRAP9_BASE_IDX = 8 # macro +regRCC_DEV1_PORT_STRAP10 = 0xc48a # macro +regRCC_DEV1_PORT_STRAP10_BASE_IDX = 8 # macro +regRCC_DEV1_PORT_STRAP11 = 0xc48b # macro +regRCC_DEV1_PORT_STRAP11_BASE_IDX = 8 # macro +regRCC_DEV1_PORT_STRAP12 = 0xc48c # macro +regRCC_DEV1_PORT_STRAP12_BASE_IDX = 8 # macro +regRCC_DEV1_PORT_STRAP13 = 0xc48d # macro +regRCC_DEV1_PORT_STRAP13_BASE_IDX = 8 # macro +regRCC_DEV1_PORT_STRAP14 = 0xc48e # macro +regRCC_DEV1_PORT_STRAP14_BASE_IDX = 8 # macro +regRCC_DEV2_PORT_STRAP0 = 0xc500 # macro +regRCC_DEV2_PORT_STRAP0_BASE_IDX = 8 # macro +regRCC_DEV2_PORT_STRAP1 = 0xc501 # macro +regRCC_DEV2_PORT_STRAP1_BASE_IDX = 8 # macro +regRCC_DEV2_PORT_STRAP2 = 0xc502 # macro +regRCC_DEV2_PORT_STRAP2_BASE_IDX = 8 # macro +regRCC_DEV2_PORT_STRAP3 = 0xc503 # macro +regRCC_DEV2_PORT_STRAP3_BASE_IDX = 8 # macro +regRCC_DEV2_PORT_STRAP4 = 0xc504 # macro +regRCC_DEV2_PORT_STRAP4_BASE_IDX = 8 # macro +regRCC_DEV2_PORT_STRAP5 = 0xc505 # macro +regRCC_DEV2_PORT_STRAP5_BASE_IDX = 8 # macro +regRCC_DEV2_PORT_STRAP6 = 0xc506 # macro +regRCC_DEV2_PORT_STRAP6_BASE_IDX = 8 # macro +regRCC_DEV2_PORT_STRAP7 = 0xc507 # macro +regRCC_DEV2_PORT_STRAP7_BASE_IDX = 8 # macro +regRCC_DEV2_PORT_STRAP8 = 0xc508 # macro +regRCC_DEV2_PORT_STRAP8_BASE_IDX = 8 # macro +regRCC_DEV2_PORT_STRAP9 = 0xc509 # macro +regRCC_DEV2_PORT_STRAP9_BASE_IDX = 8 # macro +regRCC_DEV2_PORT_STRAP10 = 0xc50a # macro +regRCC_DEV2_PORT_STRAP10_BASE_IDX = 8 # macro +regRCC_DEV2_PORT_STRAP11 = 0xc50b # macro +regRCC_DEV2_PORT_STRAP11_BASE_IDX = 8 # macro +regRCC_DEV2_PORT_STRAP12 = 0xc50c # macro +regRCC_DEV2_PORT_STRAP12_BASE_IDX = 8 # macro +regRCC_DEV2_PORT_STRAP13 = 0xc50d # macro +regRCC_DEV2_PORT_STRAP13_BASE_IDX = 8 # macro +regRCC_DEV2_PORT_STRAP14 = 0xc50e # macro +regRCC_DEV2_PORT_STRAP14_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_BIF_STRAP0 = 0xc600 # macro +regRCC_STRAP1_RCC_BIF_STRAP0_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_BIF_STRAP1 = 0xc601 # macro +regRCC_STRAP1_RCC_BIF_STRAP1_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_BIF_STRAP2 = 0xc602 # macro +regRCC_STRAP1_RCC_BIF_STRAP2_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_BIF_STRAP3 = 0xc603 # macro +regRCC_STRAP1_RCC_BIF_STRAP3_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_BIF_STRAP4 = 0xc604 # macro +regRCC_STRAP1_RCC_BIF_STRAP4_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_BIF_STRAP5 = 0xc605 # macro +regRCC_STRAP1_RCC_BIF_STRAP5_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_BIF_STRAP6 = 0xc606 # macro +regRCC_STRAP1_RCC_BIF_STRAP6_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0 = 0xd000 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1 = 0xd001 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2 = 0xd002 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3 = 0xd003 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4 = 0xd004 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5 = 0xd005 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8 = 0xd008 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9 = 0xd009 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13 = 0xd00d # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14 = 0xd00e # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15 = 0xd00f # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16 = 0xd010 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17 = 0xd011 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18 = 0xd012 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26 = 0xd01a # macro +regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0 = 0xd080 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2 = 0xd082 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3 = 0xd083 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4 = 0xd084 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5 = 0xd085 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6 = 0xd086 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7 = 0xd087 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20 = 0xd094 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21 = 0xd095 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22 = 0xd096 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23 = 0xd097 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24 = 0xd098 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24_BASE_IDX = 8 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25 = 0xd099 # macro +regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25_BASE_IDX = 8 # macro +regRCC_DEV0_EPF2_STRAP0 = 0xd100 # macro +regRCC_DEV0_EPF2_STRAP0_BASE_IDX = 8 # macro +regRCC_DEV0_EPF2_STRAP2 = 0xd102 # macro +regRCC_DEV0_EPF2_STRAP2_BASE_IDX = 8 # macro +regRCC_DEV0_EPF2_STRAP3 = 0xd103 # macro +regRCC_DEV0_EPF2_STRAP3_BASE_IDX = 8 # macro +regRCC_DEV0_EPF2_STRAP4 = 0xd104 # macro +regRCC_DEV0_EPF2_STRAP4_BASE_IDX = 8 # macro +regRCC_DEV0_EPF2_STRAP5 = 0xd105 # macro +regRCC_DEV0_EPF2_STRAP5_BASE_IDX = 8 # macro +regRCC_DEV0_EPF2_STRAP6 = 0xd106 # macro +regRCC_DEV0_EPF2_STRAP6_BASE_IDX = 8 # macro +regRCC_DEV0_EPF2_STRAP7 = 0xd107 # macro +regRCC_DEV0_EPF2_STRAP7_BASE_IDX = 8 # macro +regRCC_DEV0_EPF2_STRAP10 = 0xd10a # macro +regRCC_DEV0_EPF2_STRAP10_BASE_IDX = 8 # macro +regRCC_DEV0_EPF2_STRAP11 = 0xd10b # macro +regRCC_DEV0_EPF2_STRAP11_BASE_IDX = 8 # macro +regRCC_DEV0_EPF2_STRAP12 = 0xd10c # macro +regRCC_DEV0_EPF2_STRAP12_BASE_IDX = 8 # macro +regRCC_DEV0_EPF2_STRAP13 = 0xd10d # macro +regRCC_DEV0_EPF2_STRAP13_BASE_IDX = 8 # macro +regRCC_DEV0_EPF2_STRAP14 = 0xd10e # macro +regRCC_DEV0_EPF2_STRAP14_BASE_IDX = 8 # macro +regRCC_DEV0_EPF2_STRAP20 = 0xd114 # macro +regRCC_DEV0_EPF2_STRAP20_BASE_IDX = 8 # macro +regRCC_DEV0_EPF3_STRAP0 = 0xd180 # macro +regRCC_DEV0_EPF3_STRAP0_BASE_IDX = 8 # macro +regRCC_DEV0_EPF3_STRAP2 = 0xd182 # macro +regRCC_DEV0_EPF3_STRAP2_BASE_IDX = 8 # macro +regRCC_DEV0_EPF3_STRAP3 = 0xd183 # macro +regRCC_DEV0_EPF3_STRAP3_BASE_IDX = 8 # macro +regRCC_DEV0_EPF3_STRAP4 = 0xd184 # macro +regRCC_DEV0_EPF3_STRAP4_BASE_IDX = 8 # macro +regRCC_DEV0_EPF3_STRAP5 = 0xd185 # macro +regRCC_DEV0_EPF3_STRAP5_BASE_IDX = 8 # macro +regRCC_DEV0_EPF3_STRAP6 = 0xd186 # macro +regRCC_DEV0_EPF3_STRAP6_BASE_IDX = 8 # macro +regRCC_DEV0_EPF3_STRAP7 = 0xd187 # macro +regRCC_DEV0_EPF3_STRAP7_BASE_IDX = 8 # macro +regRCC_DEV0_EPF3_STRAP10 = 0xd18a # macro +regRCC_DEV0_EPF3_STRAP10_BASE_IDX = 8 # macro +regRCC_DEV0_EPF3_STRAP11 = 0xd18b # macro +regRCC_DEV0_EPF3_STRAP11_BASE_IDX = 8 # macro +regRCC_DEV0_EPF3_STRAP12 = 0xd18c # macro +regRCC_DEV0_EPF3_STRAP12_BASE_IDX = 8 # macro +regRCC_DEV0_EPF3_STRAP13 = 0xd18d # macro +regRCC_DEV0_EPF3_STRAP13_BASE_IDX = 8 # macro +regRCC_DEV0_EPF3_STRAP14 = 0xd18e # macro +regRCC_DEV0_EPF3_STRAP14_BASE_IDX = 8 # macro +regRCC_DEV0_EPF3_STRAP20 = 0xd194 # macro +regRCC_DEV0_EPF3_STRAP20_BASE_IDX = 8 # macro +regRCC_DEV0_EPF4_STRAP0 = 0xd200 # macro +regRCC_DEV0_EPF4_STRAP0_BASE_IDX = 8 # macro +regRCC_DEV0_EPF4_STRAP2 = 0xd202 # macro +regRCC_DEV0_EPF4_STRAP2_BASE_IDX = 8 # macro +regRCC_DEV0_EPF4_STRAP3 = 0xd203 # macro +regRCC_DEV0_EPF4_STRAP3_BASE_IDX = 8 # macro +regRCC_DEV0_EPF4_STRAP4 = 0xd204 # macro +regRCC_DEV0_EPF4_STRAP4_BASE_IDX = 8 # macro +regRCC_DEV0_EPF4_STRAP5 = 0xd205 # macro +regRCC_DEV0_EPF4_STRAP5_BASE_IDX = 8 # macro +regRCC_DEV0_EPF4_STRAP6 = 0xd206 # macro +regRCC_DEV0_EPF4_STRAP6_BASE_IDX = 8 # macro +regRCC_DEV0_EPF4_STRAP7 = 0xd207 # macro +regRCC_DEV0_EPF4_STRAP7_BASE_IDX = 8 # macro +regRCC_DEV0_EPF4_STRAP13 = 0xd20d # macro +regRCC_DEV0_EPF4_STRAP13_BASE_IDX = 8 # macro +regRCC_DEV0_EPF4_STRAP14 = 0xd20e # macro +regRCC_DEV0_EPF4_STRAP14_BASE_IDX = 8 # macro +regRCC_DEV0_EPF5_STRAP0 = 0xd280 # macro +regRCC_DEV0_EPF5_STRAP0_BASE_IDX = 8 # macro +regRCC_DEV0_EPF5_STRAP2 = 0xd282 # macro +regRCC_DEV0_EPF5_STRAP2_BASE_IDX = 8 # macro +regRCC_DEV0_EPF5_STRAP3 = 0xd283 # macro +regRCC_DEV0_EPF5_STRAP3_BASE_IDX = 8 # macro +regRCC_DEV0_EPF5_STRAP4 = 0xd284 # macro +regRCC_DEV0_EPF5_STRAP4_BASE_IDX = 8 # macro +regRCC_DEV0_EPF5_STRAP5 = 0xd285 # macro +regRCC_DEV0_EPF5_STRAP5_BASE_IDX = 8 # macro +regRCC_DEV0_EPF5_STRAP6 = 0xd286 # macro +regRCC_DEV0_EPF5_STRAP6_BASE_IDX = 8 # macro +regRCC_DEV0_EPF5_STRAP7 = 0xd287 # macro +regRCC_DEV0_EPF5_STRAP7_BASE_IDX = 8 # macro +regRCC_DEV0_EPF5_STRAP13 = 0xd28d # macro +regRCC_DEV0_EPF5_STRAP13_BASE_IDX = 8 # macro +regRCC_DEV0_EPF5_STRAP14 = 0xd28e # macro +regRCC_DEV0_EPF5_STRAP14_BASE_IDX = 8 # macro +regRCC_DEV0_EPF6_STRAP0 = 0xd300 # macro +regRCC_DEV0_EPF6_STRAP0_BASE_IDX = 8 # macro +regRCC_DEV0_EPF6_STRAP2 = 0xd302 # macro +regRCC_DEV0_EPF6_STRAP2_BASE_IDX = 8 # macro +regRCC_DEV0_EPF6_STRAP3 = 0xd303 # macro +regRCC_DEV0_EPF6_STRAP3_BASE_IDX = 8 # macro +regRCC_DEV0_EPF6_STRAP4 = 0xd304 # macro +regRCC_DEV0_EPF6_STRAP4_BASE_IDX = 8 # macro +regRCC_DEV0_EPF6_STRAP5 = 0xd305 # macro +regRCC_DEV0_EPF6_STRAP5_BASE_IDX = 8 # macro +regRCC_DEV0_EPF6_STRAP6 = 0xd306 # macro +regRCC_DEV0_EPF6_STRAP6_BASE_IDX = 8 # macro +regRCC_DEV0_EPF6_STRAP13 = 0xd30d # macro +regRCC_DEV0_EPF6_STRAP13_BASE_IDX = 8 # macro +regRCC_DEV0_EPF6_STRAP14 = 0xd30e # macro +regRCC_DEV0_EPF6_STRAP14_BASE_IDX = 8 # macro +regRCC_DEV0_EPF7_STRAP0 = 0xd380 # macro +regRCC_DEV0_EPF7_STRAP0_BASE_IDX = 8 # macro +regRCC_DEV0_EPF7_STRAP2 = 0xd382 # macro +regRCC_DEV0_EPF7_STRAP2_BASE_IDX = 8 # macro +regRCC_DEV0_EPF7_STRAP3 = 0xd383 # macro +regRCC_DEV0_EPF7_STRAP3_BASE_IDX = 8 # macro +regRCC_DEV0_EPF7_STRAP4 = 0xd384 # macro +regRCC_DEV0_EPF7_STRAP4_BASE_IDX = 8 # macro +regRCC_DEV0_EPF7_STRAP5 = 0xd385 # macro +regRCC_DEV0_EPF7_STRAP5_BASE_IDX = 8 # macro +regRCC_DEV0_EPF7_STRAP6 = 0xd386 # macro +regRCC_DEV0_EPF7_STRAP6_BASE_IDX = 8 # macro +regRCC_DEV0_EPF7_STRAP7 = 0xd387 # macro +regRCC_DEV0_EPF7_STRAP7_BASE_IDX = 8 # macro +regRCC_DEV0_EPF7_STRAP13 = 0xd38d # macro +regRCC_DEV0_EPF7_STRAP13_BASE_IDX = 8 # macro +regRCC_DEV0_EPF7_STRAP14 = 0xd38e # macro +regRCC_DEV0_EPF7_STRAP14_BASE_IDX = 8 # macro +regRCC_DEV1_EPF0_STRAP0 = 0xd400 # macro +regRCC_DEV1_EPF0_STRAP0_BASE_IDX = 8 # macro +regRCC_DEV1_EPF0_STRAP2 = 0xd402 # macro +regRCC_DEV1_EPF0_STRAP2_BASE_IDX = 8 # macro +regRCC_DEV1_EPF0_STRAP3 = 0xd403 # macro +regRCC_DEV1_EPF0_STRAP3_BASE_IDX = 8 # macro +regRCC_DEV1_EPF0_STRAP4 = 0xd404 # macro +regRCC_DEV1_EPF0_STRAP4_BASE_IDX = 8 # macro +regRCC_DEV1_EPF0_STRAP5 = 0xd405 # macro +regRCC_DEV1_EPF0_STRAP5_BASE_IDX = 8 # macro +regRCC_DEV1_EPF0_STRAP6 = 0xd406 # macro +regRCC_DEV1_EPF0_STRAP6_BASE_IDX = 8 # macro +regRCC_DEV1_EPF0_STRAP7 = 0xd407 # macro +regRCC_DEV1_EPF0_STRAP7_BASE_IDX = 8 # macro +regRCC_DEV1_EPF0_STRAP13 = 0xd40d # macro +regRCC_DEV1_EPF0_STRAP13_BASE_IDX = 8 # macro +regRCC_DEV1_EPF0_STRAP14 = 0xd40e # macro +regRCC_DEV1_EPF0_STRAP14_BASE_IDX = 8 # macro +regRCC_DEV1_EPF1_STRAP0 = 0xd480 # macro +regRCC_DEV1_EPF1_STRAP0_BASE_IDX = 8 # macro +regRCC_DEV1_EPF1_STRAP2 = 0xd482 # macro +regRCC_DEV1_EPF1_STRAP2_BASE_IDX = 8 # macro +regRCC_DEV1_EPF1_STRAP3 = 0xd483 # macro +regRCC_DEV1_EPF1_STRAP3_BASE_IDX = 8 # macro +regRCC_DEV1_EPF1_STRAP4 = 0xd484 # macro +regRCC_DEV1_EPF1_STRAP4_BASE_IDX = 8 # macro +regRCC_DEV1_EPF1_STRAP5 = 0xd485 # macro +regRCC_DEV1_EPF1_STRAP5_BASE_IDX = 8 # macro +regRCC_DEV1_EPF1_STRAP6 = 0xd486 # macro +regRCC_DEV1_EPF1_STRAP6_BASE_IDX = 8 # macro +regRCC_DEV1_EPF1_STRAP7 = 0xd487 # macro +regRCC_DEV1_EPF1_STRAP7_BASE_IDX = 8 # macro +regRCC_DEV1_EPF1_STRAP13 = 0xd48d # macro +regRCC_DEV1_EPF1_STRAP13_BASE_IDX = 8 # macro +regRCC_DEV1_EPF1_STRAP14 = 0xd48e # macro +regRCC_DEV1_EPF1_STRAP14_BASE_IDX = 8 # macro +regRCC_DEV2_EPF0_STRAP0 = 0xd800 # macro +regRCC_DEV2_EPF0_STRAP0_BASE_IDX = 8 # macro +regRCC_DEV2_EPF0_STRAP2 = 0xd802 # macro +regRCC_DEV2_EPF0_STRAP2_BASE_IDX = 8 # macro +regRCC_DEV2_EPF0_STRAP3 = 0xd803 # macro +regRCC_DEV2_EPF0_STRAP3_BASE_IDX = 8 # macro +regRCC_DEV2_EPF0_STRAP4 = 0xd804 # macro +regRCC_DEV2_EPF0_STRAP4_BASE_IDX = 8 # macro +regRCC_DEV2_EPF0_STRAP5 = 0xd805 # macro +regRCC_DEV2_EPF0_STRAP5_BASE_IDX = 8 # macro +regRCC_DEV2_EPF0_STRAP6 = 0xd806 # macro +regRCC_DEV2_EPF0_STRAP6_BASE_IDX = 8 # macro +regRCC_DEV2_EPF0_STRAP7 = 0xd807 # macro +regRCC_DEV2_EPF0_STRAP7_BASE_IDX = 8 # macro +regRCC_DEV2_EPF0_STRAP13 = 0xd80d # macro +regRCC_DEV2_EPF0_STRAP13_BASE_IDX = 8 # macro +regRCC_DEV2_EPF0_STRAP14 = 0xd80e # macro +regRCC_DEV2_EPF0_STRAP14_BASE_IDX = 8 # macro +regRCC_DEV2_EPF1_STRAP0 = 0xd880 # macro +regRCC_DEV2_EPF1_STRAP0_BASE_IDX = 8 # macro +regRCC_DEV2_EPF1_STRAP2 = 0xd882 # macro +regRCC_DEV2_EPF1_STRAP2_BASE_IDX = 8 # macro +regRCC_DEV2_EPF1_STRAP3 = 0xd883 # macro +regRCC_DEV2_EPF1_STRAP3_BASE_IDX = 8 # macro +regRCC_DEV2_EPF1_STRAP4 = 0xd884 # macro +regRCC_DEV2_EPF1_STRAP4_BASE_IDX = 8 # macro +regRCC_DEV2_EPF1_STRAP5 = 0xd885 # macro +regRCC_DEV2_EPF1_STRAP5_BASE_IDX = 8 # macro +regRCC_DEV2_EPF1_STRAP6 = 0xd886 # macro +regRCC_DEV2_EPF1_STRAP6_BASE_IDX = 8 # macro +regRCC_DEV2_EPF1_STRAP13 = 0xd88d # macro +regRCC_DEV2_EPF1_STRAP13_BASE_IDX = 8 # macro +regRCC_DEV2_EPF1_STRAP14 = 0xd88e # macro +regRCC_DEV2_EPF1_STRAP14_BASE_IDX = 8 # macro +regRCC_DEV2_EPF2_STRAP0 = 0xd900 # macro +regRCC_DEV2_EPF2_STRAP0_BASE_IDX = 8 # macro +regRCC_DEV2_EPF2_STRAP2 = 0xd902 # macro +regRCC_DEV2_EPF2_STRAP2_BASE_IDX = 8 # macro +regRCC_DEV2_EPF2_STRAP3 = 0xd903 # macro +regRCC_DEV2_EPF2_STRAP3_BASE_IDX = 8 # macro +regRCC_DEV2_EPF2_STRAP4 = 0xd904 # macro +regRCC_DEV2_EPF2_STRAP4_BASE_IDX = 8 # macro +regRCC_DEV2_EPF2_STRAP5 = 0xd905 # macro +regRCC_DEV2_EPF2_STRAP5_BASE_IDX = 8 # macro +regRCC_DEV2_EPF2_STRAP6 = 0xd906 # macro +regRCC_DEV2_EPF2_STRAP6_BASE_IDX = 8 # macro +regRCC_DEV2_EPF2_STRAP13 = 0xd90d # macro +regRCC_DEV2_EPF2_STRAP13_BASE_IDX = 8 # macro +regRCC_DEV2_EPF2_STRAP14 = 0xd90e # macro +regRCC_DEV2_EPF2_STRAP14_BASE_IDX = 8 # macro +regHARD_RST_CTRL = 0xe000 # macro +regHARD_RST_CTRL_BASE_IDX = 8 # macro +regSELF_SOFT_RST = 0xe002 # macro +regSELF_SOFT_RST_BASE_IDX = 8 # macro +regBIF_GFX_DRV_VPU_RST = 0xe003 # macro +regBIF_GFX_DRV_VPU_RST_BASE_IDX = 8 # macro +regBIF_RST_MISC_CTRL = 0xe004 # macro +regBIF_RST_MISC_CTRL_BASE_IDX = 8 # macro +regBIF_RST_MISC_CTRL2 = 0xe005 # macro +regBIF_RST_MISC_CTRL2_BASE_IDX = 8 # macro +regBIF_RST_MISC_CTRL3 = 0xe006 # macro +regBIF_RST_MISC_CTRL3_BASE_IDX = 8 # macro +regDEV0_PF0_FLR_RST_CTRL = 0xe008 # macro +regDEV0_PF0_FLR_RST_CTRL_BASE_IDX = 8 # macro +regDEV0_PF1_FLR_RST_CTRL = 0xe009 # macro +regDEV0_PF1_FLR_RST_CTRL_BASE_IDX = 8 # macro +regBIF_INST_RESET_INTR_STS = 0xe010 # macro +regBIF_INST_RESET_INTR_STS_BASE_IDX = 8 # macro +regBIF_PF_FLR_INTR_STS = 0xe011 # macro +regBIF_PF_FLR_INTR_STS_BASE_IDX = 8 # macro +regBIF_D3HOTD0_INTR_STS = 0xe012 # macro +regBIF_D3HOTD0_INTR_STS_BASE_IDX = 8 # macro +regBIF_POWER_INTR_STS = 0xe014 # macro +regBIF_POWER_INTR_STS_BASE_IDX = 8 # macro +regBIF_PF_DSTATE_INTR_STS = 0xe015 # macro +regBIF_PF_DSTATE_INTR_STS_BASE_IDX = 8 # macro +regSELF_SOFT_RST_2 = 0xe016 # macro +regSELF_SOFT_RST_2_BASE_IDX = 8 # macro +regBIF_INST_RESET_INTR_MASK = 0xe020 # macro +regBIF_INST_RESET_INTR_MASK_BASE_IDX = 8 # macro +regBIF_PF_FLR_INTR_MASK = 0xe021 # macro +regBIF_PF_FLR_INTR_MASK_BASE_IDX = 8 # macro +regBIF_D3HOTD0_INTR_MASK = 0xe022 # macro +regBIF_D3HOTD0_INTR_MASK_BASE_IDX = 8 # macro +regBIF_POWER_INTR_MASK = 0xe024 # macro +regBIF_POWER_INTR_MASK_BASE_IDX = 8 # macro +regBIF_PF_DSTATE_INTR_MASK = 0xe025 # macro +regBIF_PF_DSTATE_INTR_MASK_BASE_IDX = 8 # macro +regBIF_PF_FLR_RST = 0xe040 # macro +regBIF_PF_FLR_RST_BASE_IDX = 8 # macro +regBIF_DEV0_PF0_DSTATE_VALUE = 0xe050 # macro +regBIF_DEV0_PF0_DSTATE_VALUE_BASE_IDX = 8 # macro +regBIF_DEV0_PF1_DSTATE_VALUE = 0xe051 # macro +regBIF_DEV0_PF1_DSTATE_VALUE_BASE_IDX = 8 # macro +regDEV0_PF0_D3HOTD0_RST_CTRL = 0xe078 # macro +regDEV0_PF0_D3HOTD0_RST_CTRL_BASE_IDX = 8 # macro +regDEV0_PF1_D3HOTD0_RST_CTRL = 0xe079 # macro +regDEV0_PF1_D3HOTD0_RST_CTRL_BASE_IDX = 8 # macro +regBIF_PORT0_DSTATE_VALUE = 0xe230 # macro +regBIF_PORT0_DSTATE_VALUE_BASE_IDX = 8 # macro +regREGS_ROM_OFFSET_CTRL = 0xcc23 # macro +regREGS_ROM_OFFSET_CTRL_BASE_IDX = 8 # macro +regNBIF_STRAP_BIOS_CNTL = 0xcc81 # macro +regNBIF_STRAP_BIOS_CNTL_BASE_IDX = 8 # macro +regDOORBELL0_CTRL_ENTRY_0 = 0xcd00 # macro +regDOORBELL0_CTRL_ENTRY_0_BASE_IDX = 8 # macro +regDOORBELL0_CTRL_ENTRY_1 = 0xcd01 # macro +regDOORBELL0_CTRL_ENTRY_1_BASE_IDX = 8 # macro +regDOORBELL0_CTRL_ENTRY_2 = 0xcd02 # macro +regDOORBELL0_CTRL_ENTRY_2_BASE_IDX = 8 # macro +regDOORBELL0_CTRL_ENTRY_3 = 0xcd03 # macro +regDOORBELL0_CTRL_ENTRY_3_BASE_IDX = 8 # macro +regDOORBELL0_CTRL_ENTRY_4 = 0xcd04 # macro +regDOORBELL0_CTRL_ENTRY_4_BASE_IDX = 8 # macro +regDOORBELL0_CTRL_ENTRY_5 = 0xcd05 # macro +regDOORBELL0_CTRL_ENTRY_5_BASE_IDX = 8 # macro +regDOORBELL0_CTRL_ENTRY_6 = 0xcd06 # macro +regDOORBELL0_CTRL_ENTRY_6_BASE_IDX = 8 # macro +regDOORBELL0_CTRL_ENTRY_7 = 0xcd07 # macro +regDOORBELL0_CTRL_ENTRY_7_BASE_IDX = 8 # macro +regDOORBELL0_CTRL_ENTRY_8 = 0xcd08 # macro +regDOORBELL0_CTRL_ENTRY_8_BASE_IDX = 8 # macro +regDOORBELL0_CTRL_ENTRY_9 = 0xcd09 # macro +regDOORBELL0_CTRL_ENTRY_9_BASE_IDX = 8 # macro +regDOORBELL0_CTRL_ENTRY_10 = 0xcd0a # macro +regDOORBELL0_CTRL_ENTRY_10_BASE_IDX = 8 # macro +regDOORBELL0_CTRL_ENTRY_11 = 0xcd0b # macro +regDOORBELL0_CTRL_ENTRY_11_BASE_IDX = 8 # macro +regDOORBELL0_CTRL_ENTRY_12 = 0xcd0c # macro +regDOORBELL0_CTRL_ENTRY_12_BASE_IDX = 8 # macro +regDOORBELL0_CTRL_ENTRY_13 = 0xcd0d # macro +regDOORBELL0_CTRL_ENTRY_13_BASE_IDX = 8 # macro +regDOORBELL0_CTRL_ENTRY_14 = 0xcd0e # macro +regDOORBELL0_CTRL_ENTRY_14_BASE_IDX = 8 # macro +regDOORBELL0_CTRL_ENTRY_15 = 0xcd0f # macro +regDOORBELL0_CTRL_ENTRY_15_BASE_IDX = 8 # macro +regDOORBELL0_CTRL_ENTRY_16 = 0xcd10 # macro +regDOORBELL0_CTRL_ENTRY_16_BASE_IDX = 8 # macro +regDOORBELL0_CTRL_ENTRY_17 = 0xcd11 # macro +regDOORBELL0_CTRL_ENTRY_17_BASE_IDX = 8 # macro +regDOORBELL0_CTRL_ENTRY_18 = 0xcd12 # macro +regDOORBELL0_CTRL_ENTRY_18_BASE_IDX = 8 # macro +regDOORBELL0_CTRL_ENTRY_19 = 0xcd13 # macro +regDOORBELL0_CTRL_ENTRY_19_BASE_IDX = 8 # macro +regDOORBELL0_CTRL_ENTRY_20 = 0xcd14 # macro +regDOORBELL0_CTRL_ENTRY_20_BASE_IDX = 8 # macro +regAID0_VF0_BASE_ADDR = 0xcd40 # macro +regAID0_VF0_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_VF0_BASE_ADDR = 0xcd41 # macro +regAID1_VF0_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_VF0_BASE_ADDR = 0xcd42 # macro +regAID2_VF0_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_VF0_BASE_ADDR = 0xcd43 # macro +regAID3_VF0_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_XCC0_VF0_BASE_ADDR = 0xcd44 # macro +regAID0_XCC0_VF0_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_XCC1_VF0_BASE_ADDR = 0xcd45 # macro +regAID0_XCC1_VF0_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_XCC0_VF0_BASE_ADDR = 0xcd46 # macro +regAID1_XCC0_VF0_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_XCC1_VF0_BASE_ADDR = 0xcd47 # macro +regAID1_XCC1_VF0_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_XCC0_VF0_BASE_ADDR = 0xcd48 # macro +regAID2_XCC0_VF0_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_XCC1_VF0_BASE_ADDR = 0xcd49 # macro +regAID2_XCC1_VF0_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_XCC0_VF0_BASE_ADDR = 0xcd4a # macro +regAID3_XCC0_VF0_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_XCC1_VF0_BASE_ADDR = 0xcd4b # macro +regAID3_XCC1_VF0_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_NBIF_VF0_BASE_ADDR = 0xcd4c # macro +regAID0_NBIF_VF0_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_ATHUB_VF0_BASE_ADDR = 0xcd4d # macro +regAID0_ATHUB_VF0_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_IH_VF0_BASE_ADDR = 0xcd4e # macro +regAID0_IH_VF0_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_HDP_VF0_BASE_ADDR = 0xcd4f # macro +regAID0_HDP_VF0_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_VF1_BASE_ADDR = 0xcd50 # macro +regAID0_VF1_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_VF1_BASE_ADDR = 0xcd51 # macro +regAID1_VF1_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_VF1_BASE_ADDR = 0xcd52 # macro +regAID2_VF1_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_VF1_BASE_ADDR = 0xcd53 # macro +regAID3_VF1_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_XCC0_VF1_BASE_ADDR = 0xcd54 # macro +regAID0_XCC0_VF1_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_XCC1_VF1_BASE_ADDR = 0xcd55 # macro +regAID0_XCC1_VF1_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_XCC0_VF1_BASE_ADDR = 0xcd56 # macro +regAID1_XCC0_VF1_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_XCC1_VF1_BASE_ADDR = 0xcd57 # macro +regAID1_XCC1_VF1_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_XCC0_VF1_BASE_ADDR = 0xcd58 # macro +regAID2_XCC0_VF1_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_XCC1_VF1_BASE_ADDR = 0xcd59 # macro +regAID2_XCC1_VF1_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_XCC0_VF1_BASE_ADDR = 0xcd5a # macro +regAID3_XCC0_VF1_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_XCC1_VF1_BASE_ADDR = 0xcd5b # macro +regAID3_XCC1_VF1_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_NBIF_VF1_BASE_ADDR = 0xcd5c # macro +regAID0_NBIF_VF1_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_ATHUB_VF1_BASE_ADDR = 0xcd5d # macro +regAID0_ATHUB_VF1_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_IH_VF1_BASE_ADDR = 0xcd5e # macro +regAID0_IH_VF1_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_HDP_VF1_BASE_ADDR = 0xcd5f # macro +regAID0_HDP_VF1_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_VF2_BASE_ADDR = 0xcd60 # macro +regAID0_VF2_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_VF2_BASE_ADDR = 0xcd61 # macro +regAID1_VF2_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_VF2_BASE_ADDR = 0xcd62 # macro +regAID2_VF2_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_VF2_BASE_ADDR = 0xcd63 # macro +regAID3_VF2_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_XCC0_VF2_BASE_ADDR = 0xcd64 # macro +regAID0_XCC0_VF2_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_XCC1_VF2_BASE_ADDR = 0xcd65 # macro +regAID0_XCC1_VF2_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_XCC0_VF2_BASE_ADDR = 0xcd66 # macro +regAID1_XCC0_VF2_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_XCC1_VF2_BASE_ADDR = 0xcd67 # macro +regAID1_XCC1_VF2_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_XCC0_VF2_BASE_ADDR = 0xcd68 # macro +regAID2_XCC0_VF2_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_XCC1_VF2_BASE_ADDR = 0xcd69 # macro +regAID2_XCC1_VF2_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_XCC0_VF2_BASE_ADDR = 0xcd6a # macro +regAID3_XCC0_VF2_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_XCC1_VF2_BASE_ADDR = 0xcd6b # macro +regAID3_XCC1_VF2_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_NBIF_VF2_BASE_ADDR = 0xcd6c # macro +regAID0_NBIF_VF2_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_ATHUB_VF2_BASE_ADDR = 0xcd6d # macro +regAID0_ATHUB_VF2_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_IH_VF2_BASE_ADDR = 0xcd6e # macro +regAID0_IH_VF2_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_HDP_VF2_BASE_ADDR = 0xcd6f # macro +regAID0_HDP_VF2_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_VF3_BASE_ADDR = 0xcd70 # macro +regAID0_VF3_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_VF3_BASE_ADDR = 0xcd71 # macro +regAID1_VF3_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_VF3_BASE_ADDR = 0xcd72 # macro +regAID2_VF3_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_VF3_BASE_ADDR = 0xcd73 # macro +regAID3_VF3_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_XCC0_VF3_BASE_ADDR = 0xcd74 # macro +regAID0_XCC0_VF3_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_XCC1_VF3_BASE_ADDR = 0xcd75 # macro +regAID0_XCC1_VF3_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_XCC0_VF3_BASE_ADDR = 0xcd76 # macro +regAID1_XCC0_VF3_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_XCC1_VF3_BASE_ADDR = 0xcd77 # macro +regAID1_XCC1_VF3_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_XCC0_VF3_BASE_ADDR = 0xcd78 # macro +regAID2_XCC0_VF3_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_XCC1_VF3_BASE_ADDR = 0xcd79 # macro +regAID2_XCC1_VF3_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_XCC0_VF3_BASE_ADDR = 0xcd7a # macro +regAID3_XCC0_VF3_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_XCC1_VF3_BASE_ADDR = 0xcd7b # macro +regAID3_XCC1_VF3_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_NBIF_VF3_BASE_ADDR = 0xcd7c # macro +regAID0_NBIF_VF3_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_ATHUB_VF3_BASE_ADDR = 0xcd7d # macro +regAID0_ATHUB_VF3_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_IH_VF3_BASE_ADDR = 0xcd7e # macro +regAID0_IH_VF3_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_HDP_VF3_BASE_ADDR = 0xcd7f # macro +regAID0_HDP_VF3_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_VF4_BASE_ADDR = 0xcd80 # macro +regAID0_VF4_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_VF4_BASE_ADDR = 0xcd81 # macro +regAID1_VF4_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_VF4_BASE_ADDR = 0xcd82 # macro +regAID2_VF4_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_VF4_BASE_ADDR = 0xcd83 # macro +regAID3_VF4_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_XCC0_VF4_BASE_ADDR = 0xcd84 # macro +regAID0_XCC0_VF4_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_XCC1_VF4_BASE_ADDR = 0xcd85 # macro +regAID0_XCC1_VF4_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_XCC0_VF4_BASE_ADDR = 0xcd86 # macro +regAID1_XCC0_VF4_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_XCC1_VF4_BASE_ADDR = 0xcd87 # macro +regAID1_XCC1_VF4_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_XCC0_VF4_BASE_ADDR = 0xcd88 # macro +regAID2_XCC0_VF4_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_XCC1_VF4_BASE_ADDR = 0xcd89 # macro +regAID2_XCC1_VF4_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_XCC0_VF4_BASE_ADDR = 0xcd8a # macro +regAID3_XCC0_VF4_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_XCC1_VF4_BASE_ADDR = 0xcd8b # macro +regAID3_XCC1_VF4_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_NBIF_VF4_BASE_ADDR = 0xcd8c # macro +regAID0_NBIF_VF4_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_ATHUB_VF4_BASE_ADDR = 0xcd8d # macro +regAID0_ATHUB_VF4_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_IH_VF4_BASE_ADDR = 0xcd8e # macro +regAID0_IH_VF4_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_HDP_VF4_BASE_ADDR = 0xcd8f # macro +regAID0_HDP_VF4_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_VF5_BASE_ADDR = 0xcd90 # macro +regAID0_VF5_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_VF5_BASE_ADDR = 0xcd91 # macro +regAID1_VF5_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_VF5_BASE_ADDR = 0xcd92 # macro +regAID2_VF5_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_VF5_BASE_ADDR = 0xcd93 # macro +regAID3_VF5_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_XCC0_VF5_BASE_ADDR = 0xcd94 # macro +regAID0_XCC0_VF5_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_XCC1_VF5_BASE_ADDR = 0xcd95 # macro +regAID0_XCC1_VF5_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_XCC0_VF5_BASE_ADDR = 0xcd96 # macro +regAID1_XCC0_VF5_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_XCC1_VF5_BASE_ADDR = 0xcd97 # macro +regAID1_XCC1_VF5_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_XCC0_VF5_BASE_ADDR = 0xcd98 # macro +regAID2_XCC0_VF5_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_XCC1_VF5_BASE_ADDR = 0xcd99 # macro +regAID2_XCC1_VF5_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_XCC0_VF5_BASE_ADDR = 0xcd9a # macro +regAID3_XCC0_VF5_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_XCC1_VF5_BASE_ADDR = 0xcd9b # macro +regAID3_XCC1_VF5_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_NBIF_VF5_BASE_ADDR = 0xcd9c # macro +regAID0_NBIF_VF5_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_ATHUB_VF5_BASE_ADDR = 0xcd9d # macro +regAID0_ATHUB_VF5_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_IH_VF5_BASE_ADDR = 0xcd9e # macro +regAID0_IH_VF5_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_HDP_VF5_BASE_ADDR = 0xcd9f # macro +regAID0_HDP_VF5_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_VF6_BASE_ADDR = 0xcda0 # macro +regAID0_VF6_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_VF6_BASE_ADDR = 0xcda1 # macro +regAID1_VF6_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_VF6_BASE_ADDR = 0xcda2 # macro +regAID2_VF6_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_VF6_BASE_ADDR = 0xcda3 # macro +regAID3_VF6_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_XCC0_VF6_BASE_ADDR = 0xcda4 # macro +regAID0_XCC0_VF6_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_XCC1_VF6_BASE_ADDR = 0xcda5 # macro +regAID0_XCC1_VF6_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_XCC0_VF6_BASE_ADDR = 0xcda6 # macro +regAID1_XCC0_VF6_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_XCC1_VF6_BASE_ADDR = 0xcda7 # macro +regAID1_XCC1_VF6_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_XCC0_VF6_BASE_ADDR = 0xcda8 # macro +regAID2_XCC0_VF6_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_XCC1_VF6_BASE_ADDR = 0xcda9 # macro +regAID2_XCC1_VF6_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_XCC0_VF6_BASE_ADDR = 0xcdaa # macro +regAID3_XCC0_VF6_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_XCC1_VF6_BASE_ADDR = 0xcdab # macro +regAID3_XCC1_VF6_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_NBIF_VF6_BASE_ADDR = 0xcdac # macro +regAID0_NBIF_VF6_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_ATHUB_VF6_BASE_ADDR = 0xcdad # macro +regAID0_ATHUB_VF6_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_IH_VF6_BASE_ADDR = 0xcdae # macro +regAID0_IH_VF6_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_HDP_VF6_BASE_ADDR = 0xcdaf # macro +regAID0_HDP_VF6_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_VF7_BASE_ADDR = 0xcdb0 # macro +regAID0_VF7_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_VF7_BASE_ADDR = 0xcdb1 # macro +regAID1_VF7_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_VF7_BASE_ADDR = 0xcdb2 # macro +regAID2_VF7_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_VF7_BASE_ADDR = 0xcdb3 # macro +regAID3_VF7_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_XCC0_VF7_BASE_ADDR = 0xcdb4 # macro +regAID0_XCC0_VF7_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_XCC1_VF7_BASE_ADDR = 0xcdb5 # macro +regAID0_XCC1_VF7_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_XCC0_VF7_BASE_ADDR = 0xcdb6 # macro +regAID1_XCC0_VF7_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_XCC1_VF7_BASE_ADDR = 0xcdb7 # macro +regAID1_XCC1_VF7_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_XCC0_VF7_BASE_ADDR = 0xcdb8 # macro +regAID2_XCC0_VF7_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_XCC1_VF7_BASE_ADDR = 0xcdb9 # macro +regAID2_XCC1_VF7_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_XCC0_VF7_BASE_ADDR = 0xcdba # macro +regAID3_XCC0_VF7_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_XCC1_VF7_BASE_ADDR = 0xcdbb # macro +regAID3_XCC1_VF7_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_NBIF_VF7_BASE_ADDR = 0xcdbc # macro +regAID0_NBIF_VF7_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_ATHUB_VF7_BASE_ADDR = 0xcdbd # macro +regAID0_ATHUB_VF7_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_IH_VF7_BASE_ADDR = 0xcdbe # macro +regAID0_IH_VF7_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_HDP_VF7_BASE_ADDR = 0xcdbf # macro +regAID0_HDP_VF7_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_PF_BASE_ADDR = 0xcdc0 # macro +regAID0_PF_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_XCC0_PF_BASE_ADDR = 0xcdc1 # macro +regAID0_XCC0_PF_BASE_ADDR_BASE_IDX = 8 # macro +regAID0_XCC1_PF_BASE_ADDR = 0xcdc2 # macro +regAID0_XCC1_PF_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_PF_BASE_ADDR = 0xcdc3 # macro +regAID1_PF_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_XCC0_PF_BASE_ADDR = 0xcdc4 # macro +regAID1_XCC0_PF_BASE_ADDR_BASE_IDX = 8 # macro +regAID1_XCC1_PF_BASE_ADDR = 0xcdc5 # macro +regAID1_XCC1_PF_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_PF_BASE_ADDR = 0xcdc6 # macro +regAID2_PF_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_XCC0_PF_BASE_ADDR = 0xcdc7 # macro +regAID2_XCC0_PF_BASE_ADDR_BASE_IDX = 8 # macro +regAID2_XCC1_PF_BASE_ADDR = 0xcdc8 # macro +regAID2_XCC1_PF_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_PF_BASE_ADDR = 0xcdc9 # macro +regAID3_PF_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_XCC0_PF_BASE_ADDR = 0xcdca # macro +regAID3_XCC0_PF_BASE_ADDR_BASE_IDX = 8 # macro +regAID3_XCC1_PF_BASE_ADDR = 0xcdcb # macro +regAID3_XCC1_PF_BASE_ADDR_BASE_IDX = 8 # macro +regNBIF_RRMT_CNTL = 0xcddc # macro +regNBIF_RRMT_CNTL_BASE_IDX = 8 # macro +regBIFC_DOORBELL_ACCESS_EN_PF = 0xcf6e # macro +regBIFC_DOORBELL_ACCESS_EN_PF_BASE_IDX = 8 # macro +regBIFC_DOORBELL_ACCESS_EN_VF0 = 0xcf6f # macro +regBIFC_DOORBELL_ACCESS_EN_VF0_BASE_IDX = 8 # macro +regBIFC_DOORBELL_ACCESS_EN_VF1 = 0xcf70 # macro +regBIFC_DOORBELL_ACCESS_EN_VF1_BASE_IDX = 8 # macro +regBIFC_DOORBELL_ACCESS_EN_VF2 = 0xcf71 # macro +regBIFC_DOORBELL_ACCESS_EN_VF2_BASE_IDX = 8 # macro +regBIFC_DOORBELL_ACCESS_EN_VF3 = 0xcf72 # macro +regBIFC_DOORBELL_ACCESS_EN_VF3_BASE_IDX = 8 # macro +regBIFC_DOORBELL_ACCESS_EN_VF4 = 0xcf73 # macro +regBIFC_DOORBELL_ACCESS_EN_VF4_BASE_IDX = 8 # macro +regBIFC_DOORBELL_ACCESS_EN_VF5 = 0xcf74 # macro +regBIFC_DOORBELL_ACCESS_EN_VF5_BASE_IDX = 8 # macro +regBIFC_DOORBELL_ACCESS_EN_VF6 = 0xcf75 # macro +regBIFC_DOORBELL_ACCESS_EN_VF6_BASE_IDX = 8 # macro +regBIFC_DOORBELL_ACCESS_EN_VF7 = 0xcf76 # macro +regBIFC_DOORBELL_ACCESS_EN_VF7_BASE_IDX = 8 # macro +regMISC_SCRATCH = 0xe800 # macro +regMISC_SCRATCH_BASE_IDX = 8 # macro +regINTR_LINE_POLARITY = 0xe801 # macro +regINTR_LINE_POLARITY_BASE_IDX = 8 # macro +regINTR_LINE_ENABLE = 0xe802 # macro +regINTR_LINE_ENABLE_BASE_IDX = 8 # macro +regOUTSTANDING_VC_ALLOC = 0xe803 # macro +regOUTSTANDING_VC_ALLOC_BASE_IDX = 8 # macro +regBIFC_MISC_CTRL0 = 0xe804 # macro +regBIFC_MISC_CTRL0_BASE_IDX = 8 # macro +regBIFC_MISC_CTRL1 = 0xe805 # macro +regBIFC_MISC_CTRL1_BASE_IDX = 8 # macro +regBIFC_BME_ERR_LOG_LB = 0xe806 # macro +regBIFC_BME_ERR_LOG_LB_BASE_IDX = 8 # macro +regBIFC_LC_TIMER_CTRL = 0xe807 # macro +regBIFC_LC_TIMER_CTRL_BASE_IDX = 8 # macro +regBIFC_RCCBIH_BME_ERR_LOG0 = 0xe808 # macro +regBIFC_RCCBIH_BME_ERR_LOG0_BASE_IDX = 8 # macro +regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 = 0xe80a # macro +regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_BASE_IDX = 8 # macro +regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 = 0xe80b # macro +regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_BASE_IDX = 8 # macro +regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 = 0xe80c # macro +regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_BASE_IDX = 8 # macro +regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 = 0xe80d # macro +regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_BASE_IDX = 8 # macro +regBIFC_DMA_ATTR_CNTL2_DEV0 = 0xe81a # macro +regBIFC_DMA_ATTR_CNTL2_DEV0_BASE_IDX = 8 # macro +regBME_DUMMY_CNTL_0 = 0xe825 # macro +regBME_DUMMY_CNTL_0_BASE_IDX = 8 # macro +regBIFC_THT_CNTL = 0xe827 # macro +regBIFC_THT_CNTL_BASE_IDX = 8 # macro +regBIFC_HSTARB_CNTL = 0xe828 # macro +regBIFC_HSTARB_CNTL_BASE_IDX = 8 # macro +regBIFC_GSI_CNTL = 0xe829 # macro +regBIFC_GSI_CNTL_BASE_IDX = 8 # macro +regBIFC_PCIEFUNC_CNTL = 0xe82a # macro +regBIFC_PCIEFUNC_CNTL_BASE_IDX = 8 # macro +regBIFC_PASID_CHECK_DIS = 0xe82b # macro +regBIFC_PASID_CHECK_DIS_BASE_IDX = 8 # macro +regBIFC_SDP_CNTL_0 = 0xe82c # macro +regBIFC_SDP_CNTL_0_BASE_IDX = 8 # macro +regBIFC_SDP_CNTL_1 = 0xe82d # macro +regBIFC_SDP_CNTL_1_BASE_IDX = 8 # macro +regBIFC_PASID_STS = 0xe82e # macro +regBIFC_PASID_STS_BASE_IDX = 8 # macro +regBIFC_ATHUB_ACT_CNTL = 0xe82f # macro +regBIFC_ATHUB_ACT_CNTL_BASE_IDX = 8 # macro +regBIFC_PERF_CNTL_0 = 0xe830 # macro +regBIFC_PERF_CNTL_0_BASE_IDX = 8 # macro +regBIFC_PERF_CNTL_1 = 0xe831 # macro +regBIFC_PERF_CNTL_1_BASE_IDX = 8 # macro +regBIFC_PERF_CNT_MMIO_RD_L32BIT = 0xe832 # macro +regBIFC_PERF_CNT_MMIO_RD_L32BIT_BASE_IDX = 8 # macro +regBIFC_PERF_CNT_MMIO_WR_L32BIT = 0xe833 # macro +regBIFC_PERF_CNT_MMIO_WR_L32BIT_BASE_IDX = 8 # macro +regBIFC_PERF_CNT_DMA_RD_L32BIT = 0xe834 # macro +regBIFC_PERF_CNT_DMA_RD_L32BIT_BASE_IDX = 8 # macro +regBIFC_PERF_CNT_DMA_WR_L32BIT = 0xe835 # macro +regBIFC_PERF_CNT_DMA_WR_L32BIT_BASE_IDX = 8 # macro +regNBIF_REGIF_ERRSET_CTRL = 0xe836 # macro +regNBIF_REGIF_ERRSET_CTRL_BASE_IDX = 8 # macro +regBIFC_SDP_CNTL_2 = 0xe837 # macro +regBIFC_SDP_CNTL_2_BASE_IDX = 8 # macro +regNBIF_PGMST_CTRL = 0xe838 # macro +regNBIF_PGMST_CTRL_BASE_IDX = 8 # macro +regNBIF_PGSLV_CTRL = 0xe839 # macro +regNBIF_PGSLV_CTRL_BASE_IDX = 8 # macro +regNBIF_PG_MISC_CTRL = 0xe83a # macro +regNBIF_PG_MISC_CTRL_BASE_IDX = 8 # macro +regSMN_MST_EP_CNTL3 = 0xe83c # macro +regSMN_MST_EP_CNTL3_BASE_IDX = 8 # macro +regSMN_MST_EP_CNTL4 = 0xe83d # macro +regSMN_MST_EP_CNTL4_BASE_IDX = 8 # macro +regSMN_MST_CNTL1 = 0xe83e # macro +regSMN_MST_CNTL1_BASE_IDX = 8 # macro +regSMN_MST_EP_CNTL5 = 0xe83f # macro +regSMN_MST_EP_CNTL5_BASE_IDX = 8 # macro +regBIF_SELFRING_BUFFER_VID = 0xe840 # macro +regBIF_SELFRING_BUFFER_VID_BASE_IDX = 8 # macro +regBIF_SELFRING_VECTOR_CNTL = 0xe841 # macro +regBIF_SELFRING_VECTOR_CNTL_BASE_IDX = 8 # macro +regNBIF_STRAP_WRITE_CTRL = 0xe845 # macro +regNBIF_STRAP_WRITE_CTRL_BASE_IDX = 8 # macro +regNBIF_INTX_DSTATE_MISC_CNTL = 0xe846 # macro +regNBIF_INTX_DSTATE_MISC_CNTL_BASE_IDX = 8 # macro +regNBIF_PENDING_MISC_CNTL = 0xe847 # macro +regNBIF_PENDING_MISC_CNTL_BASE_IDX = 8 # macro +regBIF_GMI_WRR_WEIGHT = 0xe848 # macro +regBIF_GMI_WRR_WEIGHT_BASE_IDX = 8 # macro +regBIF_GMI_WRR_WEIGHT2 = 0xe849 # macro +regBIF_GMI_WRR_WEIGHT2_BASE_IDX = 8 # macro +regBIF_GMI_WRR_WEIGHT3 = 0xe84a # macro +regBIF_GMI_WRR_WEIGHT3_BASE_IDX = 8 # macro +regNBIF_PWRBRK_REQUEST = 0xe84c # macro +regNBIF_PWRBRK_REQUEST_BASE_IDX = 8 # macro +regBIF_ATOMIC_ERR_LOG_DEV0_F0 = 0xe850 # macro +regBIF_ATOMIC_ERR_LOG_DEV0_F0_BASE_IDX = 8 # macro +regBIF_ATOMIC_ERR_LOG_DEV0_F1 = 0xe851 # macro +regBIF_ATOMIC_ERR_LOG_DEV0_F1_BASE_IDX = 8 # macro +regBIF_DMA_MP4_ERR_LOG = 0xe870 # macro +regBIF_DMA_MP4_ERR_LOG_BASE_IDX = 8 # macro +regBIF_PASID_ERR_LOG = 0xe871 # macro +regBIF_PASID_ERR_LOG_BASE_IDX = 8 # macro +regBIF_PASID_ERR_CLR = 0xe872 # macro +regBIF_PASID_ERR_CLR_BASE_IDX = 8 # macro +regNBIF_VWIRE_CTRL = 0xe880 # macro +regNBIF_VWIRE_CTRL_BASE_IDX = 8 # macro +regNBIF_SMN_VWR_VCHG_DIS_CTRL = 0xe881 # macro +regNBIF_SMN_VWR_VCHG_DIS_CTRL_BASE_IDX = 8 # macro +regNBIF_SMN_VWR_VCHG_RST_CTRL0 = 0xe882 # macro +regNBIF_SMN_VWR_VCHG_RST_CTRL0_BASE_IDX = 8 # macro +regNBIF_SMN_VWR_VCHG_TRIG = 0xe884 # macro +regNBIF_SMN_VWR_VCHG_TRIG_BASE_IDX = 8 # macro +regNBIF_SMN_VWR_WTRIG_CNTL = 0xe885 # macro +regNBIF_SMN_VWR_WTRIG_CNTL_BASE_IDX = 8 # macro +regNBIF_SMN_VWR_VCHG_DIS_CTRL_1 = 0xe886 # macro +regNBIF_SMN_VWR_VCHG_DIS_CTRL_1_BASE_IDX = 8 # macro +regNBIF_MGCG_CTRL_LCLK = 0xe887 # macro +regNBIF_MGCG_CTRL_LCLK_BASE_IDX = 8 # macro +regNBIF_DS_CTRL_LCLK = 0xe888 # macro +regNBIF_DS_CTRL_LCLK_BASE_IDX = 8 # macro +regSMN_MST_CNTL0 = 0xe889 # macro +regSMN_MST_CNTL0_BASE_IDX = 8 # macro +regSMN_MST_EP_CNTL1 = 0xe88a # macro +regSMN_MST_EP_CNTL1_BASE_IDX = 8 # macro +regSMN_MST_EP_CNTL2 = 0xe88b # macro +regSMN_MST_EP_CNTL2_BASE_IDX = 8 # macro +regNBIF_SDP_VWR_VCHG_DIS_CTRL = 0xe88c # macro +regNBIF_SDP_VWR_VCHG_DIS_CTRL_BASE_IDX = 8 # macro +regNBIF_SDP_VWR_VCHG_RST_CTRL0 = 0xe88d # macro +regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX = 8 # macro +regNBIF_SDP_VWR_VCHG_RST_CTRL1 = 0xe88e # macro +regNBIF_SDP_VWR_VCHG_RST_CTRL1_BASE_IDX = 8 # macro +regNBIF_SDP_VWR_VCHG_TRIG = 0xe88f # macro +regNBIF_SDP_VWR_VCHG_TRIG_BASE_IDX = 8 # macro +regNBIF_SHUB_TODET_CTRL = 0xe898 # macro +regNBIF_SHUB_TODET_CTRL_BASE_IDX = 8 # macro +regNBIF_SHUB_TODET_CLIENT_CTRL = 0xe899 # macro +regNBIF_SHUB_TODET_CLIENT_CTRL_BASE_IDX = 8 # macro +regNBIF_SHUB_TODET_CLIENT_STATUS = 0xe89a # macro +regNBIF_SHUB_TODET_CLIENT_STATUS_BASE_IDX = 8 # macro +regNBIF_SHUB_TODET_SYNCFLOOD_CTRL = 0xe89b # macro +regNBIF_SHUB_TODET_SYNCFLOOD_CTRL_BASE_IDX = 8 # macro +regNBIF_SHUB_TODET_CLIENT_CTRL2 = 0xe89c # macro +regNBIF_SHUB_TODET_CLIENT_CTRL2_BASE_IDX = 8 # macro +regNBIF_SHUB_TODET_CLIENT_STATUS2 = 0xe89d # macro +regNBIF_SHUB_TODET_CLIENT_STATUS2_BASE_IDX = 8 # macro +regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2 = 0xe89e # macro +regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2_BASE_IDX = 8 # macro +regBIFC_BME_ERR_LOG_HB = 0xe8ab # macro +regBIFC_BME_ERR_LOG_HB_BASE_IDX = 8 # macro +regBIFC_GFX_INT_MONITOR_MASK = 0xe8ad # macro +regBIFC_GFX_INT_MONITOR_MASK_BASE_IDX = 8 # macro +regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC = 0xe8c0 # macro +regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC_BASE_IDX = 8 # macro +regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC = 0xe8c1 # macro +regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC_BASE_IDX = 8 # macro +regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC = 0xe8c2 # macro +regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX = 8 # macro +regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC = 0xe8c3 # macro +regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX = 8 # macro +regDISCON_HYSTERESIS_HEAD_CTRL = 0xe8c6 # macro +regDISCON_HYSTERESIS_HEAD_CTRL_BASE_IDX = 8 # macro +regBIFC_EARLY_WAKEUP_CNTL = 0xe8d2 # macro +regBIFC_EARLY_WAKEUP_CNTL_BASE_IDX = 8 # macro +regBIFC_PERF_CNT_MMIO_RD_H16BIT = 0xe8f0 # macro +regBIFC_PERF_CNT_MMIO_RD_H16BIT_BASE_IDX = 8 # macro +regBIFC_PERF_CNT_MMIO_WR_H16BIT = 0xe8f1 # macro +regBIFC_PERF_CNT_MMIO_WR_H16BIT_BASE_IDX = 8 # macro +regBIFC_PERF_CNT_DMA_RD_H16BIT = 0xe8f2 # macro +regBIFC_PERF_CNT_DMA_RD_H16BIT_BASE_IDX = 8 # macro +regBIFC_PERF_CNT_DMA_WR_H16BIT = 0xe8f3 # macro +regBIFC_PERF_CNT_DMA_WR_H16BIT_BASE_IDX = 8 # macro +regBIFC_A2S_SDP_PORT_CTRL = 0xeb00 # macro +regBIFC_A2S_SDP_PORT_CTRL_BASE_IDX = 8 # macro +regBIFC_A2S_CNTL_SW0 = 0xeb01 # macro +regBIFC_A2S_CNTL_SW0_BASE_IDX = 8 # macro +regBIFC_A2S_MISC_CNTL = 0xeb02 # macro +regBIFC_A2S_MISC_CNTL_BASE_IDX = 8 # macro +regBIFC_A2S_TAG_ALLOC_0 = 0xeb03 # macro +regBIFC_A2S_TAG_ALLOC_0_BASE_IDX = 8 # macro +regBIFC_A2S_TAG_ALLOC_1 = 0xeb04 # macro +regBIFC_A2S_TAG_ALLOC_1_BASE_IDX = 8 # macro +regBIFC_A2S_CNTL_CL0 = 0xeb05 # macro +regBIFC_A2S_CNTL_CL0_BASE_IDX = 8 # macro +regRCC_DWN_DEV0_2_DN_PCIE_RESERVED = 0x8d80 # macro +regRCC_DWN_DEV0_2_DN_PCIE_RESERVED_BASE_IDX = 8 # macro +regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH = 0x8d81 # macro +regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH_BASE_IDX = 8 # macro +regRCC_DWN_DEV0_2_DN_PCIE_CNTL = 0x8d83 # macro +regRCC_DWN_DEV0_2_DN_PCIE_CNTL_BASE_IDX = 8 # macro +regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL = 0x8d84 # macro +regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL_BASE_IDX = 8 # macro +regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 = 0x8d85 # macro +regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2_BASE_IDX = 8 # macro +regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL = 0x8d86 # macro +regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL_BASE_IDX = 8 # macro +regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL = 0x8d87 # macro +regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL_BASE_IDX = 8 # macro +regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0 = 0x8d88 # macro +regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0_BASE_IDX = 8 # macro +regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC = 0x8d89 # macro +regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC_BASE_IDX = 8 # macro +regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2 = 0x8d8a # macro +regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2_BASE_IDX = 8 # macro +regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL = 0x8d8c # macro +regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL_BASE_IDX = 8 # macro +regRCC_DWNP_DEV0_2_PCIE_RX_CNTL = 0x8d8d # macro +regRCC_DWNP_DEV0_2_PCIE_RX_CNTL_BASE_IDX = 8 # macro +regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL = 0x8d8e # macro +regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL_BASE_IDX = 8 # macro +regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2 = 0x8d8f # macro +regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2_BASE_IDX = 8 # macro +regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC = 0x8d90 # macro +regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC_BASE_IDX = 8 # macro +regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP = 0x8d91 # macro +regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_EP_PCIE_SCRATCH = 0x8d60 # macro +regRCC_EP_DEV0_2_EP_PCIE_SCRATCH_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_EP_PCIE_CNTL = 0x8d62 # macro +regRCC_EP_DEV0_2_EP_PCIE_CNTL_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL = 0x8d63 # macro +regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS = 0x8d64 # macro +regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 = 0x8d65 # macro +regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL = 0x8d66 # macro +regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL = 0x8d67 # macro +regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL = 0x8d69 # macro +regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 = 0x8d6a # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 = 0x8d6a # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 = 0x8d6a # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 = 0x8d6a # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 = 0x8d6b # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 = 0x8d6b # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 = 0x8d6b # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX = 8 # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 = 0x8d6b # macro +regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC = 0x8d6c # macro +regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2 = 0x8d6d # macro +regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP = 0x8d6f # macro +regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR = 0x8d70 # macro +regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL = 0x8d70 # macro +regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 = 0x8d70 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 = 0x8d71 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 = 0x8d71 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 = 0x8d71 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 = 0x8d71 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 = 0x8d72 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 = 0x8d72 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 = 0x8d72 # macro +regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL = 0x8d72 # macro +regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_EP_PCIEP_RESERVED = 0x8d73 # macro +regRCC_EP_DEV0_2_EP_PCIEP_RESERVED_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL = 0x8d75 # macro +regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID = 0x8d76 # macro +regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL = 0x8d77 # macro +regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL = 0x8d78 # macro +regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL_BASE_IDX = 8 # macro +regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL = 0x8d79 # macro +regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_ERR_INT_CNTL = 0x8da6 # macro +regRCC_DEV0_1_RCC_ERR_INT_CNTL_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_BACO_CNTL_MISC = 0x8da7 # macro +regRCC_DEV0_1_RCC_BACO_CNTL_MISC_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_RESET_EN = 0x8da8 # macro +regRCC_DEV0_1_RCC_RESET_EN_BASE_IDX = 8 # macro +regRCC_DEV0_2_RCC_VDM_SUPPORT = 0x8da9 # macro +regRCC_DEV0_2_RCC_VDM_SUPPORT_BASE_IDX = 8 # macro +regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0 = 0x8daa # macro +regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0_BASE_IDX = 8 # macro +regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1 = 0x8dab # macro +regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_GPUIOV_REGION = 0x8dac # macro +regRCC_DEV0_1_RCC_GPUIOV_REGION_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_GPU_HOSTVM_EN = 0x8dad # macro +regRCC_DEV0_1_RCC_GPU_HOSTVM_EN_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL = 0x8dae # macro +regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET = 0x8daf # macro +regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE = 0x8daf # macro +regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_PEER_REG_RANGE0 = 0x8dde # macro +regRCC_DEV0_1_RCC_PEER_REG_RANGE0_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_PEER_REG_RANGE1 = 0x8ddf # macro +regRCC_DEV0_1_RCC_PEER_REG_RANGE1_BASE_IDX = 8 # macro +regRCC_DEV0_2_RCC_BUS_CNTL = 0x8de1 # macro +regRCC_DEV0_2_RCC_BUS_CNTL_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_CONFIG_CNTL = 0x8de2 # macro +regRCC_DEV0_1_RCC_CONFIG_CNTL_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_CONFIG_F0_BASE = 0x8de6 # macro +regRCC_DEV0_1_RCC_CONFIG_F0_BASE_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_CONFIG_APER_SIZE = 0x8de7 # macro +regRCC_DEV0_1_RCC_CONFIG_APER_SIZE_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE = 0x8de8 # macro +regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_XDMA_LO = 0x8de9 # macro +regRCC_DEV0_1_RCC_XDMA_LO_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_XDMA_HI = 0x8dea # macro +regRCC_DEV0_1_RCC_XDMA_HI_BASE_IDX = 8 # macro +regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC = 0x8deb # macro +regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_BUSNUM_CNTL1 = 0x8dec # macro +regRCC_DEV0_1_RCC_BUSNUM_CNTL1_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_BUSNUM_LIST0 = 0x8ded # macro +regRCC_DEV0_1_RCC_BUSNUM_LIST0_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_BUSNUM_LIST1 = 0x8dee # macro +regRCC_DEV0_1_RCC_BUSNUM_LIST1_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_BUSNUM_CNTL2 = 0x8def # macro +regRCC_DEV0_1_RCC_BUSNUM_CNTL2_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM = 0x8df0 # macro +regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_HOST_BUSNUM = 0x8df1 # macro +regRCC_DEV0_1_RCC_HOST_BUSNUM_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI = 0x8df2 # macro +regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO = 0x8df3 # macro +regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI = 0x8df4 # macro +regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO = 0x8df5 # macro +regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI = 0x8df6 # macro +regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO = 0x8df7 # macro +regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI = 0x8df8 # macro +regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO = 0x8df9 # macro +regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0 = 0x8dfa # macro +regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0_BASE_IDX = 8 # macro +regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1 = 0x8dfb # macro +regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1_BASE_IDX = 8 # macro +regRCC_DEV0_2_RCC_DEV0_LINK_CNTL = 0x8dfd # macro +regRCC_DEV0_2_RCC_DEV0_LINK_CNTL_BASE_IDX = 8 # macro +regRCC_DEV0_2_RCC_CMN_LINK_CNTL = 0x8dfe # macro +regRCC_DEV0_2_RCC_CMN_LINK_CNTL_BASE_IDX = 8 # macro +regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE = 0x8dff # macro +regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE_BASE_IDX = 8 # macro +regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL = 0x8e00 # macro +regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL_BASE_IDX = 8 # macro +regRCC_DEV0_2_RCC_MH_ARB_CNTL = 0x8e01 # macro +regRCC_DEV0_2_RCC_MH_ARB_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_PCIE_INDEX = 0x800c # macro +regBIF_BX1_PCIE_INDEX_BASE_IDX = 8 # macro +regBIF_BX1_PCIE_DATA = 0x800d # macro +regBIF_BX1_PCIE_DATA_BASE_IDX = 8 # macro +regBIF_BX1_PCIE_INDEX2 = 0x800e # macro +regBIF_BX1_PCIE_INDEX2_BASE_IDX = 8 # macro +regBIF_BX1_PCIE_DATA2 = 0x800f # macro +regBIF_BX1_PCIE_DATA2_BASE_IDX = 8 # macro +regBIF_BX1_PCIE_INDEX_HI = 0x8010 # macro +regBIF_BX1_PCIE_INDEX_HI_BASE_IDX = 8 # macro +regBIF_BX1_PCIE_INDEX2_HI = 0x8011 # macro +regBIF_BX1_PCIE_INDEX2_HI_BASE_IDX = 8 # macro +regBIF_BX1_SBIOS_SCRATCH_0 = 0x8048 # macro +regBIF_BX1_SBIOS_SCRATCH_0_BASE_IDX = 8 # macro +regBIF_BX1_SBIOS_SCRATCH_1 = 0x8049 # macro +regBIF_BX1_SBIOS_SCRATCH_1_BASE_IDX = 8 # macro +regBIF_BX1_SBIOS_SCRATCH_2 = 0x804a # macro +regBIF_BX1_SBIOS_SCRATCH_2_BASE_IDX = 8 # macro +regBIF_BX1_SBIOS_SCRATCH_3 = 0x804b # macro +regBIF_BX1_SBIOS_SCRATCH_3_BASE_IDX = 8 # macro +regBIF_BX1_BIOS_SCRATCH_0 = 0x804c # macro +regBIF_BX1_BIOS_SCRATCH_0_BASE_IDX = 8 # macro +regBIF_BX1_BIOS_SCRATCH_1 = 0x804d # macro +regBIF_BX1_BIOS_SCRATCH_1_BASE_IDX = 8 # macro +regBIF_BX1_BIOS_SCRATCH_2 = 0x804e # macro +regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX = 8 # macro +regBIF_BX1_BIOS_SCRATCH_3 = 0x804f # macro +regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX = 8 # macro +regBIF_BX1_BIOS_SCRATCH_4 = 0x8050 # macro +regBIF_BX1_BIOS_SCRATCH_4_BASE_IDX = 8 # macro +regBIF_BX1_BIOS_SCRATCH_5 = 0x8051 # macro +regBIF_BX1_BIOS_SCRATCH_5_BASE_IDX = 8 # macro +regBIF_BX1_BIOS_SCRATCH_6 = 0x8052 # macro +regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX = 8 # macro +regBIF_BX1_BIOS_SCRATCH_7 = 0x8053 # macro +regBIF_BX1_BIOS_SCRATCH_7_BASE_IDX = 8 # macro +regBIF_BX1_BIOS_SCRATCH_8 = 0x8054 # macro +regBIF_BX1_BIOS_SCRATCH_8_BASE_IDX = 8 # macro +regBIF_BX1_BIOS_SCRATCH_9 = 0x8055 # macro +regBIF_BX1_BIOS_SCRATCH_9_BASE_IDX = 8 # macro +regBIF_BX1_BIOS_SCRATCH_10 = 0x8056 # macro +regBIF_BX1_BIOS_SCRATCH_10_BASE_IDX = 8 # macro +regBIF_BX1_BIOS_SCRATCH_11 = 0x8057 # macro +regBIF_BX1_BIOS_SCRATCH_11_BASE_IDX = 8 # macro +regBIF_BX1_BIOS_SCRATCH_12 = 0x8058 # macro +regBIF_BX1_BIOS_SCRATCH_12_BASE_IDX = 8 # macro +regBIF_BX1_BIOS_SCRATCH_13 = 0x8059 # macro +regBIF_BX1_BIOS_SCRATCH_13_BASE_IDX = 8 # macro +regBIF_BX1_BIOS_SCRATCH_14 = 0x805a # macro +regBIF_BX1_BIOS_SCRATCH_14_BASE_IDX = 8 # macro +regBIF_BX1_BIOS_SCRATCH_15 = 0x805b # macro +regBIF_BX1_BIOS_SCRATCH_15_BASE_IDX = 8 # macro +regBIF_BX1_BIF_RLC_INTR_CNTL = 0x8060 # macro +regBIF_BX1_BIF_RLC_INTR_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_BIF_VCE_INTR_CNTL = 0x8061 # macro +regBIF_BX1_BIF_VCE_INTR_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_BIF_UVD_INTR_CNTL = 0x8062 # macro +regBIF_BX1_BIF_UVD_INTR_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR0 = 0x8080 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR0_BASE_IDX = 8 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 = 0x8081 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX = 8 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR1 = 0x8082 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR1_BASE_IDX = 8 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 = 0x8083 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX = 8 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR2 = 0x8084 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR2_BASE_IDX = 8 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 = 0x8085 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX = 8 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR3 = 0x8086 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR3_BASE_IDX = 8 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 = 0x8087 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX = 8 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR4 = 0x8088 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR4_BASE_IDX = 8 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 = 0x8089 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX = 8 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR5 = 0x808a # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR5_BASE_IDX = 8 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 = 0x808b # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX = 8 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR6 = 0x808c # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR6_BASE_IDX = 8 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 = 0x808d # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX = 8 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR7 = 0x808e # macro +regBIF_BX1_GFX_MMIOREG_CAM_ADDR7_BASE_IDX = 8 # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 = 0x808f # macro +regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX = 8 # macro +regBIF_BX1_GFX_MMIOREG_CAM_CNTL = 0x8090 # macro +regBIF_BX1_GFX_MMIOREG_CAM_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL = 0x8091 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX = 8 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL = 0x8092 # macro +regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX = 8 # macro +regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL = 0x8093 # macro +regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX = 8 # macro +regBIF_BX1_DRIVER_SCRATCH_0 = 0x8094 # macro +regBIF_BX1_DRIVER_SCRATCH_0_BASE_IDX = 8 # macro +regBIF_BX1_DRIVER_SCRATCH_1 = 0x8095 # macro +regBIF_BX1_DRIVER_SCRATCH_1_BASE_IDX = 8 # macro +regBIF_BX1_DRIVER_SCRATCH_2 = 0x8096 # macro +regBIF_BX1_DRIVER_SCRATCH_2_BASE_IDX = 8 # macro +regBIF_BX1_DRIVER_SCRATCH_3 = 0x8097 # macro +regBIF_BX1_DRIVER_SCRATCH_3_BASE_IDX = 8 # macro +regBIF_BX1_DRIVER_SCRATCH_4 = 0x8098 # macro +regBIF_BX1_DRIVER_SCRATCH_4_BASE_IDX = 8 # macro +regBIF_BX1_DRIVER_SCRATCH_5 = 0x8099 # macro +regBIF_BX1_DRIVER_SCRATCH_5_BASE_IDX = 8 # macro +regBIF_BX1_DRIVER_SCRATCH_6 = 0x809a # macro +regBIF_BX1_DRIVER_SCRATCH_6_BASE_IDX = 8 # macro +regBIF_BX1_DRIVER_SCRATCH_7 = 0x809b # macro +regBIF_BX1_DRIVER_SCRATCH_7_BASE_IDX = 8 # macro +regBIF_BX1_DRIVER_SCRATCH_8 = 0x809c # macro +regBIF_BX1_DRIVER_SCRATCH_8_BASE_IDX = 8 # macro +regBIF_BX1_DRIVER_SCRATCH_9 = 0x809d # macro +regBIF_BX1_DRIVER_SCRATCH_9_BASE_IDX = 8 # macro +regBIF_BX1_DRIVER_SCRATCH_10 = 0x809e # macro +regBIF_BX1_DRIVER_SCRATCH_10_BASE_IDX = 8 # macro +regBIF_BX1_DRIVER_SCRATCH_11 = 0x809f # macro +regBIF_BX1_DRIVER_SCRATCH_11_BASE_IDX = 8 # macro +regBIF_BX1_DRIVER_SCRATCH_12 = 0x80a0 # macro +regBIF_BX1_DRIVER_SCRATCH_12_BASE_IDX = 8 # macro +regBIF_BX1_DRIVER_SCRATCH_13 = 0x80a1 # macro +regBIF_BX1_DRIVER_SCRATCH_13_BASE_IDX = 8 # macro +regBIF_BX1_DRIVER_SCRATCH_14 = 0x80a2 # macro +regBIF_BX1_DRIVER_SCRATCH_14_BASE_IDX = 8 # macro +regBIF_BX1_DRIVER_SCRATCH_15 = 0x80a3 # macro +regBIF_BX1_DRIVER_SCRATCH_15_BASE_IDX = 8 # macro +regBIF_BX1_FW_SCRATCH_0 = 0x80a4 # macro +regBIF_BX1_FW_SCRATCH_0_BASE_IDX = 8 # macro +regBIF_BX1_FW_SCRATCH_1 = 0x80a5 # macro +regBIF_BX1_FW_SCRATCH_1_BASE_IDX = 8 # macro +regBIF_BX1_FW_SCRATCH_2 = 0x80a6 # macro +regBIF_BX1_FW_SCRATCH_2_BASE_IDX = 8 # macro +regBIF_BX1_FW_SCRATCH_3 = 0x80a7 # macro +regBIF_BX1_FW_SCRATCH_3_BASE_IDX = 8 # macro +regBIF_BX1_FW_SCRATCH_4 = 0x80a8 # macro +regBIF_BX1_FW_SCRATCH_4_BASE_IDX = 8 # macro +regBIF_BX1_FW_SCRATCH_5 = 0x80a9 # macro +regBIF_BX1_FW_SCRATCH_5_BASE_IDX = 8 # macro +regBIF_BX1_FW_SCRATCH_6 = 0x80aa # macro +regBIF_BX1_FW_SCRATCH_6_BASE_IDX = 8 # macro +regBIF_BX1_FW_SCRATCH_7 = 0x80ab # macro +regBIF_BX1_FW_SCRATCH_7_BASE_IDX = 8 # macro +regBIF_BX1_FW_SCRATCH_8 = 0x80ac # macro +regBIF_BX1_FW_SCRATCH_8_BASE_IDX = 8 # macro +regBIF_BX1_FW_SCRATCH_9 = 0x80ad # macro +regBIF_BX1_FW_SCRATCH_9_BASE_IDX = 8 # macro +regBIF_BX1_FW_SCRATCH_10 = 0x80ae # macro +regBIF_BX1_FW_SCRATCH_10_BASE_IDX = 8 # macro +regBIF_BX1_FW_SCRATCH_11 = 0x80af # macro +regBIF_BX1_FW_SCRATCH_11_BASE_IDX = 8 # macro +regBIF_BX1_FW_SCRATCH_12 = 0x80b0 # macro +regBIF_BX1_FW_SCRATCH_12_BASE_IDX = 8 # macro +regBIF_BX1_FW_SCRATCH_13 = 0x80b1 # macro +regBIF_BX1_FW_SCRATCH_13_BASE_IDX = 8 # macro +regBIF_BX1_FW_SCRATCH_14 = 0x80b2 # macro +regBIF_BX1_FW_SCRATCH_14_BASE_IDX = 8 # macro +regBIF_BX1_FW_SCRATCH_15 = 0x80b3 # macro +regBIF_BX1_FW_SCRATCH_15_BASE_IDX = 8 # macro +regBIF_BX1_SBIOS_SCRATCH_4 = 0x80b4 # macro +regBIF_BX1_SBIOS_SCRATCH_4_BASE_IDX = 8 # macro +regBIF_BX1_SBIOS_SCRATCH_5 = 0x80b5 # macro +regBIF_BX1_SBIOS_SCRATCH_5_BASE_IDX = 8 # macro +regBIF_BX1_SBIOS_SCRATCH_6 = 0x80b6 # macro +regBIF_BX1_SBIOS_SCRATCH_6_BASE_IDX = 8 # macro +regBIF_BX1_SBIOS_SCRATCH_7 = 0x80b7 # macro +regBIF_BX1_SBIOS_SCRATCH_7_BASE_IDX = 8 # macro +regBIF_BX1_SBIOS_SCRATCH_8 = 0x80b8 # macro +regBIF_BX1_SBIOS_SCRATCH_8_BASE_IDX = 8 # macro +regBIF_BX1_SBIOS_SCRATCH_9 = 0x80b9 # macro +regBIF_BX1_SBIOS_SCRATCH_9_BASE_IDX = 8 # macro +regBIF_BX1_SBIOS_SCRATCH_10 = 0x80ba # macro +regBIF_BX1_SBIOS_SCRATCH_10_BASE_IDX = 8 # macro +regBIF_BX1_SBIOS_SCRATCH_11 = 0x80bb # macro +regBIF_BX1_SBIOS_SCRATCH_11_BASE_IDX = 8 # macro +regBIF_BX1_SBIOS_SCRATCH_12 = 0x80bc # macro +regBIF_BX1_SBIOS_SCRATCH_12_BASE_IDX = 8 # macro +regBIF_BX1_SBIOS_SCRATCH_13 = 0x80bd # macro +regBIF_BX1_SBIOS_SCRATCH_13_BASE_IDX = 8 # macro +regBIF_BX1_SBIOS_SCRATCH_14 = 0x80be # macro +regBIF_BX1_SBIOS_SCRATCH_14_BASE_IDX = 8 # macro +regBIF_BX1_SBIOS_SCRATCH_15 = 0x80bf # macro +regBIF_BX1_SBIOS_SCRATCH_15_BASE_IDX = 8 # macro +regBIF_BX_PF1_MM_INDEX = 0x8000 # macro +regBIF_BX_PF1_MM_INDEX_BASE_IDX = 8 # macro +regBIF_BX_PF1_MM_DATA = 0x8001 # macro +regBIF_BX_PF1_MM_DATA_BASE_IDX = 8 # macro +regBIF_BX_PF1_MM_INDEX_HI = 0x8006 # macro +regBIF_BX_PF1_MM_INDEX_HI_BASE_IDX = 8 # macro +regBIF_BX1_CC_BIF_BX_STRAP0 = 0x8e02 # macro +regBIF_BX1_CC_BIF_BX_STRAP0_BASE_IDX = 8 # macro +regBIF_BX1_CC_BIF_BX_PINSTRAP0 = 0x8e04 # macro +regBIF_BX1_CC_BIF_BX_PINSTRAP0_BASE_IDX = 8 # macro +regBIF_BX1_BIF_MM_INDACCESS_CNTL = 0x8e06 # macro +regBIF_BX1_BIF_MM_INDACCESS_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_BUS_CNTL = 0x8e07 # macro +regBIF_BX1_BUS_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_BIF_SCRATCH0 = 0x8e08 # macro +regBIF_BX1_BIF_SCRATCH0_BASE_IDX = 8 # macro +regBIF_BX1_BIF_SCRATCH1 = 0x8e09 # macro +regBIF_BX1_BIF_SCRATCH1_BASE_IDX = 8 # macro +regBIF_BX1_BX_RESET_EN = 0x8e0d # macro +regBIF_BX1_BX_RESET_EN_BASE_IDX = 8 # macro +regBIF_BX1_MM_CFGREGS_CNTL = 0x8e0e # macro +regBIF_BX1_MM_CFGREGS_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_BX_RESET_CNTL = 0x8e10 # macro +regBIF_BX1_BX_RESET_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_INTERRUPT_CNTL = 0x8e11 # macro +regBIF_BX1_INTERRUPT_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_INTERRUPT_CNTL2 = 0x8e12 # macro +regBIF_BX1_INTERRUPT_CNTL2_BASE_IDX = 8 # macro +regBIF_BX1_CLKREQB_PAD_CNTL = 0x8e18 # macro +regBIF_BX1_CLKREQB_PAD_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_BIF_FEATURES_CONTROL_MISC = 0x8e1b # macro +regBIF_BX1_BIF_FEATURES_CONTROL_MISC_BASE_IDX = 8 # macro +regBIF_BX1_HDP_ATOMIC_CONTROL_MISC = 0x8e1c # macro +regBIF_BX1_HDP_ATOMIC_CONTROL_MISC_BASE_IDX = 8 # macro +regBIF_BX1_BIF_DOORBELL_CNTL = 0x8e1d # macro +regBIF_BX1_BIF_DOORBELL_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_BIF_DOORBELL_INT_CNTL = 0x8e1e # macro +regBIF_BX1_BIF_DOORBELL_INT_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_BIF_FB_EN = 0x8e20 # macro +regBIF_BX1_BIF_FB_EN_BASE_IDX = 8 # macro +regBIF_BX1_BIF_INTR_CNTL = 0x8e21 # macro +regBIF_BX1_BIF_INTR_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_BIF_MST_TRANS_PENDING_VF = 0x8e29 # macro +regBIF_BX1_BIF_MST_TRANS_PENDING_VF_BASE_IDX = 8 # macro +regBIF_BX1_BIF_SLV_TRANS_PENDING_VF = 0x8e2a # macro +regBIF_BX1_BIF_SLV_TRANS_PENDING_VF_BASE_IDX = 8 # macro +regBIF_BX1_BACO_CNTL = 0x8e2b # macro +regBIF_BX1_BACO_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_BIF_BACO_EXIT_TIME0 = 0x8e2c # macro +regBIF_BX1_BIF_BACO_EXIT_TIME0_BASE_IDX = 8 # macro +regBIF_BX1_BIF_BACO_EXIT_TIMER1 = 0x8e2d # macro +regBIF_BX1_BIF_BACO_EXIT_TIMER1_BASE_IDX = 8 # macro +regBIF_BX1_BIF_BACO_EXIT_TIMER2 = 0x8e2e # macro +regBIF_BX1_BIF_BACO_EXIT_TIMER2_BASE_IDX = 8 # macro +regBIF_BX1_BIF_BACO_EXIT_TIMER3 = 0x8e2f # macro +regBIF_BX1_BIF_BACO_EXIT_TIMER3_BASE_IDX = 8 # macro +regBIF_BX1_BIF_BACO_EXIT_TIMER4 = 0x8e30 # macro +regBIF_BX1_BIF_BACO_EXIT_TIMER4_BASE_IDX = 8 # macro +regBIF_BX1_MEM_TYPE_CNTL = 0x8e31 # macro +regBIF_BX1_MEM_TYPE_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL = 0x8e33 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_0 = 0x8e34 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_0_BASE_IDX = 8 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_1 = 0x8e35 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_1_BASE_IDX = 8 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_2 = 0x8e36 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_2_BASE_IDX = 8 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_3 = 0x8e37 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_3_BASE_IDX = 8 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_4 = 0x8e38 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_4_BASE_IDX = 8 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_5 = 0x8e39 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_5_BASE_IDX = 8 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_6 = 0x8e3a # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_6_BASE_IDX = 8 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_7 = 0x8e3b # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_7_BASE_IDX = 8 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_8 = 0x8e3c # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_8_BASE_IDX = 8 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_9 = 0x8e3d # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_9_BASE_IDX = 8 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_10 = 0x8e3e # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_10_BASE_IDX = 8 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_11 = 0x8e3f # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_11_BASE_IDX = 8 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_12 = 0x8e40 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_12_BASE_IDX = 8 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_13 = 0x8e41 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_13_BASE_IDX = 8 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_14 = 0x8e42 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_14_BASE_IDX = 8 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_15 = 0x8e43 # macro +regBIF_BX1_NBIF_GFX_ADDR_LUT_15_BASE_IDX = 8 # macro +regBIF_BX1_VF_REGWR_EN = 0x8e44 # macro +regBIF_BX1_VF_REGWR_EN_BASE_IDX = 8 # macro +regBIF_BX1_VF_DOORBELL_EN = 0x8e45 # macro +regBIF_BX1_VF_DOORBELL_EN_BASE_IDX = 8 # macro +regBIF_BX1_VF_FB_EN = 0x8e46 # macro +regBIF_BX1_VF_FB_EN_BASE_IDX = 8 # macro +regBIF_BX1_VF_REGWR_STATUS = 0x8e47 # macro +regBIF_BX1_VF_REGWR_STATUS_BASE_IDX = 8 # macro +regBIF_BX1_VF_DOORBELL_STATUS = 0x8e48 # macro +regBIF_BX1_VF_DOORBELL_STATUS_BASE_IDX = 8 # macro +regBIF_BX1_VF_FB_STATUS = 0x8e49 # macro +regBIF_BX1_VF_FB_STATUS_BASE_IDX = 8 # macro +regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL = 0x8e4d # macro +regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL = 0x8e4e # macro +regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_BIF_RB_CNTL = 0x8e4f # macro +regBIF_BX1_BIF_RB_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_BIF_RB_BASE = 0x8e50 # macro +regBIF_BX1_BIF_RB_BASE_BASE_IDX = 8 # macro +regBIF_BX1_BIF_RB_RPTR = 0x8e51 # macro +regBIF_BX1_BIF_RB_RPTR_BASE_IDX = 8 # macro +regBIF_BX1_BIF_RB_WPTR = 0x8e52 # macro +regBIF_BX1_BIF_RB_WPTR_BASE_IDX = 8 # macro +regBIF_BX1_BIF_RB_WPTR_ADDR_HI = 0x8e53 # macro +regBIF_BX1_BIF_RB_WPTR_ADDR_HI_BASE_IDX = 8 # macro +regBIF_BX1_BIF_RB_WPTR_ADDR_LO = 0x8e54 # macro +regBIF_BX1_BIF_RB_WPTR_ADDR_LO_BASE_IDX = 8 # macro +regBIF_BX1_MAILBOX_INDEX = 0x8e55 # macro +regBIF_BX1_MAILBOX_INDEX_BASE_IDX = 8 # macro +regBIF_BX1_BIF_MP1_INTR_CTRL = 0x8e62 # macro +regBIF_BX1_BIF_MP1_INTR_CTRL_BASE_IDX = 8 # macro +regBIF_BX1_BIF_PERSTB_PAD_CNTL = 0x8e66 # macro +regBIF_BX1_BIF_PERSTB_PAD_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_BIF_PX_EN_PAD_CNTL = 0x8e67 # macro +regBIF_BX1_BIF_PX_EN_PAD_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_BIF_REFPADKIN_PAD_CNTL = 0x8e68 # macro +regBIF_BX1_BIF_REFPADKIN_PAD_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_BIF_CLKREQB_PAD_CNTL = 0x8e69 # macro +regBIF_BX1_BIF_CLKREQB_PAD_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_BIF_PWRBRK_PAD_CNTL = 0x8e6a # macro +regBIF_BX1_BIF_PWRBRK_PAD_CNTL_BASE_IDX = 8 # macro +regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE = 0x8e6b # macro +regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE_BASE_IDX = 8 # macro +regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE = 0x8e6c # macro +regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE_BASE_IDX = 8 # macro +regBIF_BX_PF1_BIF_BME_STATUS = 0x8e0b # macro +regBIF_BX_PF1_BIF_BME_STATUS_BASE_IDX = 8 # macro +regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG = 0x8e0c # macro +regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_BASE_IDX = 8 # macro +regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x8e13 # macro +regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 8 # macro +regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x8e14 # macro +regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 8 # macro +regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL = 0x8e15 # macro +regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 8 # macro +regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL = 0x8e16 # macro +regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 8 # macro +regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x8e17 # macro +regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 8 # macro +regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x8e19 # macro +regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 8 # macro +regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x8e1a # macro +regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 8 # macro +regBIF_BX_PF1_GPU_HDP_FLUSH_REQ = 0x8e26 # macro +regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_BASE_IDX = 8 # macro +regBIF_BX_PF1_GPU_HDP_FLUSH_DONE = 0x8e27 # macro +regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_BASE_IDX = 8 # macro +regBIF_BX_PF1_BIF_TRANS_PENDING = 0x8e28 # macro +regBIF_BX_PF1_BIF_TRANS_PENDING_BASE_IDX = 8 # macro +regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS = 0x8e32 # macro +regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 8 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 = 0x8e56 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 8 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 = 0x8e57 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 8 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 = 0x8e58 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 8 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 = 0x8e59 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 8 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 = 0x8e5a # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 8 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 = 0x8e5b # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 8 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 = 0x8e5c # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 8 # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 = 0x8e5d # macro +regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 8 # macro +regBIF_BX_PF1_MAILBOX_CONTROL = 0x8e5e # macro +regBIF_BX_PF1_MAILBOX_CONTROL_BASE_IDX = 8 # macro +regBIF_BX_PF1_MAILBOX_INT_CNTL = 0x8e5f # macro +regBIF_BX_PF1_MAILBOX_INT_CNTL_BASE_IDX = 8 # macro +regBIF_BX_PF1_BIF_VMHV_MAILBOX = 0x8e60 # macro +regBIF_BX_PF1_BIF_VMHV_MAILBOX_BASE_IDX = 8 # macro +regBIF_BX_PF1_PARTITION_COMPUTE_CAP = 0x8e81 # macro +regBIF_BX_PF1_PARTITION_COMPUTE_CAP_BASE_IDX = 8 # macro +regBIF_BX_PF1_PARTITION_MEM_CAP = 0x8e82 # macro +regBIF_BX_PF1_PARTITION_MEM_CAP_BASE_IDX = 8 # macro +regBIF_BX_PF1_PARTITION_COMPUTE_STATUS = 0x8e83 # macro +regBIF_BX_PF1_PARTITION_COMPUTE_STATUS_BASE_IDX = 8 # macro +regBIF_BX_PF1_PARTITION_MEM_STATUS = 0x8e84 # macro +regBIF_BX_PF1_PARTITION_MEM_STATUS_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_BIF_STRAP0 = 0x8d20 # macro +regRCC_STRAP2_RCC_BIF_STRAP0_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_BIF_STRAP1 = 0x8d21 # macro +regRCC_STRAP2_RCC_BIF_STRAP1_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_BIF_STRAP2 = 0x8d22 # macro +regRCC_STRAP2_RCC_BIF_STRAP2_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_BIF_STRAP3 = 0x8d23 # macro +regRCC_STRAP2_RCC_BIF_STRAP3_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_BIF_STRAP4 = 0x8d24 # macro +regRCC_STRAP2_RCC_BIF_STRAP4_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_BIF_STRAP5 = 0x8d25 # macro +regRCC_STRAP2_RCC_BIF_STRAP5_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_BIF_STRAP6 = 0x8d26 # macro +regRCC_STRAP2_RCC_BIF_STRAP6_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP0 = 0x8d27 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP0_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP1 = 0x8d28 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP1_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP10 = 0x8d29 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP10_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP11 = 0x8d2a # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP11_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP12 = 0x8d2b # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP12_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP13 = 0x8d2c # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP13_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP14 = 0x8d2d # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP14_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP2 = 0x8d2e # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP2_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP3 = 0x8d2f # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP3_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP4 = 0x8d30 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP4_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP5 = 0x8d31 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP5_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP6 = 0x8d32 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP6_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP7 = 0x8d33 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP7_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP8 = 0x8d34 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP8_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP9 = 0x8d35 # macro +regRCC_STRAP2_RCC_DEV0_PORT_STRAP9_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0 = 0x8d36 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1 = 0x8d37 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13 = 0x8d38 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14 = 0x8d39 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15 = 0x8d3a # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16 = 0x8d3b # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17 = 0x8d3c # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18 = 0x8d3d # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2 = 0x8d3e # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26 = 0x8d3f # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3 = 0x8d40 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4 = 0x8d41 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5 = 0x8d42 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8 = 0x8d44 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9 = 0x8d45 # macro +regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0 = 0x8d46 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2 = 0x8d52 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20 = 0x8d53 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21 = 0x8d54 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22 = 0x8d55 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23 = 0x8d56 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24 = 0x8d57 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25 = 0x8d58 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3 = 0x8d59 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4 = 0x8d5a # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5 = 0x8d5b # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6 = 0x8d5c # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6_BASE_IDX = 8 # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7 = 0x8d5d # macro +regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7_BASE_IDX = 8 # macro +regS2A_DOORBELL_ENTRY_0_CTRL = 0x7a80 # macro +regS2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX = 5 # macro +regS2A_DOORBELL_ENTRY_1_CTRL = 0x7a81 # macro +regS2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX = 5 # macro +regS2A_DOORBELL_ENTRY_2_CTRL = 0x7a82 # macro +regS2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX = 5 # macro +regS2A_DOORBELL_ENTRY_3_CTRL = 0x7a83 # macro +regS2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX = 5 # macro +regS2A_DOORBELL_ENTRY_4_CTRL = 0x7a84 # macro +regS2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX = 5 # macro +regS2A_DOORBELL_ENTRY_5_CTRL = 0x7a85 # macro +regS2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX = 5 # macro +regS2A_DOORBELL_ENTRY_6_CTRL = 0x7a86 # macro +regS2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX = 5 # macro +regS2A_DOORBELL_ENTRY_7_CTRL = 0x7a87 # macro +regS2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX = 5 # macro +regS2A_DOORBELL_ENTRY_8_CTRL = 0x7a88 # macro +regS2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX = 5 # macro +regS2A_DOORBELL_ENTRY_9_CTRL = 0x7a89 # macro +regS2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX = 5 # macro +regS2A_DOORBELL_ENTRY_10_CTRL = 0x7a8a # macro +regS2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX = 5 # macro +regS2A_DOORBELL_ENTRY_11_CTRL = 0x7a8b # macro +regS2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX = 5 # macro +regS2A_DOORBELL_ENTRY_12_CTRL = 0x7a8c # macro +regS2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX = 5 # macro +regS2A_DOORBELL_ENTRY_13_CTRL = 0x7a8d # macro +regS2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX = 5 # macro +regS2A_DOORBELL_ENTRY_14_CTRL = 0x7a8e # macro +regS2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX = 5 # macro +regS2A_DOORBELL_ENTRY_15_CTRL = 0x7a8f # macro +regS2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX = 5 # macro +regS2A_DOORBELL_COMMON_CTRL_REG = 0x7a90 # macro +regS2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX = 5 # macro +regGDC1_A2S_CNTL_CL0 = 0x0ea0 # macro +regGDC1_A2S_CNTL_CL0_BASE_IDX = 5 # macro +regGDC1_A2S_CNTL_CL1 = 0x0ea1 # macro +regGDC1_A2S_CNTL_CL1_BASE_IDX = 5 # macro +regGDC1_A2S_CNTL3_CL0 = 0x0eb8 # macro +regGDC1_A2S_CNTL3_CL0_BASE_IDX = 5 # macro +regGDC1_A2S_CNTL3_CL1 = 0x0eb9 # macro +regGDC1_A2S_CNTL3_CL1_BASE_IDX = 5 # macro +regGDC1_A2S_CNTL_SW0 = 0x0ed0 # macro +regGDC1_A2S_CNTL_SW0_BASE_IDX = 5 # macro +regGDC1_A2S_CNTL_SW1 = 0x0ed1 # macro +regGDC1_A2S_CNTL_SW1_BASE_IDX = 5 # macro +regGDC1_A2S_CNTL_SW2 = 0x0ed2 # macro +regGDC1_A2S_CNTL_SW2_BASE_IDX = 5 # macro +regGDC1_A2S_TAG_ALLOC_0 = 0x0edd # macro +regGDC1_A2S_TAG_ALLOC_0_BASE_IDX = 5 # macro +regGDC1_A2S_TAG_ALLOC_1 = 0x0ede # macro +regGDC1_A2S_TAG_ALLOC_1_BASE_IDX = 5 # macro +regGDC1_A2S_MISC_CNTL = 0x0ee1 # macro +regGDC1_A2S_MISC_CNTL_BASE_IDX = 5 # macro +regGDC1_SHUB_REGS_IF_CTL = 0x0ee3 # macro +regGDC1_SHUB_REGS_IF_CTL_BASE_IDX = 5 # macro +regGDC1_NGDC_MGCG_CTRL = 0x0eea # macro +regGDC1_NGDC_MGCG_CTRL_BASE_IDX = 5 # macro +regGDC1_NGDC_RESERVED_0 = 0x0eeb # macro +regGDC1_NGDC_RESERVED_0_BASE_IDX = 5 # macro +regGDC1_NGDC_RESERVED_1 = 0x0eec # macro +regGDC1_NGDC_RESERVED_1_BASE_IDX = 5 # macro +regGDC1_NBIF_GFX_DOORBELL_STATUS = 0x0eef # macro +regGDC1_NBIF_GFX_DOORBELL_STATUS_BASE_IDX = 5 # macro +regGDC1_ATDMA_MISC_CNTL = 0x0efd # macro +regGDC1_ATDMA_MISC_CNTL_BASE_IDX = 5 # macro +regGDC1_S2A_MISC_CNTL = 0x0eff # macro +regGDC1_S2A_MISC_CNTL_BASE_IDX = 5 # macro +regGDC1_NGDC_EARLY_WAKEUP_CTRL = 0x0f01 # macro +regGDC1_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX = 5 # macro +regGDC1_NGDC_PG_MISC_CTRL = 0x0f18 # macro +regGDC1_NGDC_PG_MISC_CTRL_BASE_IDX = 5 # macro +regGDC1_NGDC_PGMST_CTRL = 0x0f19 # macro +regGDC1_NGDC_PGMST_CTRL_BASE_IDX = 5 # macro +regGDC1_NGDC_PGSLV_CTRL = 0x0f1a # macro +regGDC1_NGDC_PGSLV_CTRL_BASE_IDX = 5 # macro +regXCC_DOORBELL_FENCE = 0x740c # macro +regXCC_DOORBELL_FENCE_BASE_IDX = 5 # macro +regSHUB_PF_FLR_RST = 0x7c00 # macro +regSHUB_PF_FLR_RST_BASE_IDX = 5 # macro +regSHUB_GFX_DRV_VPU_RST = 0x7c01 # macro +regSHUB_GFX_DRV_VPU_RST_BASE_IDX = 5 # macro +regSHUB_LINK_RESET = 0x7c02 # macro +regSHUB_LINK_RESET_BASE_IDX = 5 # macro +regSHUB_HARD_RST_CTRL = 0x7c10 # macro +regSHUB_HARD_RST_CTRL_BASE_IDX = 5 # macro +regSHUB_SOFT_RST_CTRL = 0x7c11 # macro +regSHUB_SOFT_RST_CTRL_BASE_IDX = 5 # macro +regSHUB_SDP_PORT_RST = 0x7c12 # macro +regSHUB_SDP_PORT_RST_BASE_IDX = 5 # macro +regSHUB_RST_MISC_TRL = 0x7c13 # macro +regSHUB_RST_MISC_TRL_BASE_IDX = 5 # macro +regHST_CLK0_SW0_CL0_CNTL = 0x4140 # macro +regHST_CLK0_SW0_CL0_CNTL_BASE_IDX = 5 # macro +regHST_CLK0_SW1_CL0_CNTL = 0x4160 # macro +regHST_CLK0_SW1_CL0_CNTL_BASE_IDX = 5 # macro +regHST_CLK0_SW1_CL1_CNTL = 0x4161 # macro +regHST_CLK0_SW1_CL1_CNTL_BASE_IDX = 5 # macro +regHST_CLK0_SW1_CL2_CNTL = 0x4162 # macro +regHST_CLK0_SW1_CL2_CNTL_BASE_IDX = 5 # macro +regDMA_CLK0_SW0_CL0_CNTL = 0x4240 # macro +regDMA_CLK0_SW0_CL0_CNTL_BASE_IDX = 5 # macro +regDMA_CLK0_SW0_CL1_CNTL = 0x4241 # macro +regDMA_CLK0_SW0_CL1_CNTL_BASE_IDX = 5 # macro +regNIC400_1_ASIB_0_FN_MOD = 0xc042 # macro +regNIC400_1_ASIB_0_FN_MOD_BASE_IDX = 5 # macro +regNIC400_1_IB_0_FN_MOD = 0xfc42 # macro +regNIC400_1_IB_0_FN_MOD_BASE_IDX = 5 # macro +regNIC400_2_ASIB_0_FN_MOD = 0x10c42 # macro +regNIC400_2_ASIB_0_FN_MOD_BASE_IDX = 5 # macro +regNIC400_2_ASIB_0_QOS_CNTL = 0x10c43 # macro +regNIC400_2_ASIB_0_QOS_CNTL_BASE_IDX = 5 # macro +regNIC400_2_ASIB_0_MAX_OT = 0x10c44 # macro +regNIC400_2_ASIB_0_MAX_OT_BASE_IDX = 5 # macro +regNIC400_2_ASIB_0_MAX_COMB_OT = 0x10c45 # macro +regNIC400_2_ASIB_0_MAX_COMB_OT_BASE_IDX = 5 # macro +regNIC400_2_ASIB_0_AW_P = 0x10c46 # macro +regNIC400_2_ASIB_0_AW_P_BASE_IDX = 5 # macro +regNIC400_2_ASIB_0_AW_B = 0x10c47 # macro +regNIC400_2_ASIB_0_AW_B_BASE_IDX = 5 # macro +regNIC400_2_ASIB_0_AW_R = 0x10c48 # macro +regNIC400_2_ASIB_0_AW_R_BASE_IDX = 5 # macro +regNIC400_2_ASIB_0_AR_P = 0x10c49 # macro +regNIC400_2_ASIB_0_AR_P_BASE_IDX = 5 # macro +regNIC400_2_ASIB_0_AR_B = 0x10c4a # macro +regNIC400_2_ASIB_0_AR_B_BASE_IDX = 5 # macro +regNIC400_2_ASIB_0_AR_R = 0x10c4b # macro +regNIC400_2_ASIB_0_AR_R_BASE_IDX = 5 # macro +regNIC400_2_ASIB_0_TARGET_FC = 0x10c4c # macro +regNIC400_2_ASIB_0_TARGET_FC_BASE_IDX = 5 # macro +regNIC400_2_ASIB_0_KI_FC = 0x10c4d # macro +regNIC400_2_ASIB_0_KI_FC_BASE_IDX = 5 # macro +regNIC400_2_ASIB_0_QOS_RANGE = 0x10c4e # macro +regNIC400_2_ASIB_0_QOS_RANGE_BASE_IDX = 5 # macro +regNIC400_2_ASIB_1_FN_MOD = 0x11042 # macro +regNIC400_2_ASIB_1_FN_MOD_BASE_IDX = 5 # macro +regNIC400_2_ASIB_1_QOS_CNTL = 0x11043 # macro +regNIC400_2_ASIB_1_QOS_CNTL_BASE_IDX = 5 # macro +regNIC400_2_ASIB_1_MAX_OT = 0x11044 # macro +regNIC400_2_ASIB_1_MAX_OT_BASE_IDX = 5 # macro +regNIC400_2_ASIB_1_MAX_COMB_OT = 0x11045 # macro +regNIC400_2_ASIB_1_MAX_COMB_OT_BASE_IDX = 5 # macro +regNIC400_2_ASIB_1_AW_P = 0x11046 # macro +regNIC400_2_ASIB_1_AW_P_BASE_IDX = 5 # macro +regNIC400_2_ASIB_1_AW_B = 0x11047 # macro +regNIC400_2_ASIB_1_AW_B_BASE_IDX = 5 # macro +regNIC400_2_ASIB_1_AW_R = 0x11048 # macro +regNIC400_2_ASIB_1_AW_R_BASE_IDX = 5 # macro +regNIC400_2_ASIB_1_AR_P = 0x11049 # macro +regNIC400_2_ASIB_1_AR_P_BASE_IDX = 5 # macro +regNIC400_2_ASIB_1_AR_B = 0x1104a # macro +regNIC400_2_ASIB_1_AR_B_BASE_IDX = 5 # macro +regNIC400_2_ASIB_1_AR_R = 0x1104b # macro +regNIC400_2_ASIB_1_AR_R_BASE_IDX = 5 # macro +regNIC400_2_ASIB_1_TARGET_FC = 0x1104c # macro +regNIC400_2_ASIB_1_TARGET_FC_BASE_IDX = 5 # macro +regNIC400_2_ASIB_1_KI_FC = 0x1104d # macro +regNIC400_2_ASIB_1_KI_FC_BASE_IDX = 5 # macro +regNIC400_2_ASIB_1_QOS_RANGE = 0x1104e # macro +regNIC400_2_ASIB_1_QOS_RANGE_BASE_IDX = 5 # macro +regNIC400_2_IB_0_FN_MOD = 0x13c42 # macro +regNIC400_2_IB_0_FN_MOD_BASE_IDX = 5 # macro +regNB_NBCFG0_NBCFG_SCRATCH_4 = 0xe8001e # macro +regNB_NBCFG0_NBCFG_SCRATCH_4_BASE_IDX = 8 # macro +regNB_CNTL = 0xe84000 # macro +regNB_CNTL_BASE_IDX = 8 # macro +regNB_SPARE1 = 0xe84003 # macro +regNB_SPARE1_BASE_IDX = 8 # macro +regNB_SPARE2 = 0xe84004 # macro +regNB_SPARE2_BASE_IDX = 8 # macro +regNB_REVID = 0xe84005 # macro +regNB_REVID_BASE_IDX = 8 # macro +regNBIO_LCLK_DS_MASK = 0xe84009 # macro +regNBIO_LCLK_DS_MASK_BASE_IDX = 8 # macro +regNB_BUS_NUM_CNTL = 0xe84011 # macro +regNB_BUS_NUM_CNTL_BASE_IDX = 8 # macro +regNB_MMIOBASE = 0xe84017 # macro +regNB_MMIOBASE_BASE_IDX = 8 # macro +regNB_MMIOLIMIT = 0xe84018 # macro +regNB_MMIOLIMIT_BASE_IDX = 8 # macro +regNB_LOWER_TOP_OF_DRAM2 = 0xe84019 # macro +regNB_LOWER_TOP_OF_DRAM2_BASE_IDX = 8 # macro +regNB_UPPER_TOP_OF_DRAM2 = 0xe8401a # macro +regNB_UPPER_TOP_OF_DRAM2_BASE_IDX = 8 # macro +regNB_LOWER_DRAM2_BASE = 0xe8401b # macro +regNB_LOWER_DRAM2_BASE_BASE_IDX = 8 # macro +regNB_UPPER_DRAM2_BASE = 0xe8401c # macro +regNB_UPPER_DRAM2_BASE_BASE_IDX = 8 # macro +regSB_LOCATION = 0xe8401f # macro +regSB_LOCATION_BASE_IDX = 8 # macro +regSW_US_LOCATION = 0xe84020 # macro +regSW_US_LOCATION_BASE_IDX = 8 # macro +regNB_PROG_DEVICE_REMAP_PBr0 = 0xe8402e # macro +regNB_PROG_DEVICE_REMAP_PBr0_BASE_IDX = 8 # macro +regNB_PROG_DEVICE_REMAP_PBr1 = 0xe8402f # macro +regNB_PROG_DEVICE_REMAP_PBr1_BASE_IDX = 8 # macro +regNB_PROG_DEVICE_REMAP_PBr2 = 0xe84030 # macro +regNB_PROG_DEVICE_REMAP_PBr2_BASE_IDX = 8 # macro +regNB_PROG_DEVICE_REMAP_PBr3 = 0xe84031 # macro +regNB_PROG_DEVICE_REMAP_PBr3_BASE_IDX = 8 # macro +regNB_PROG_DEVICE_REMAP_PBr4 = 0xe84032 # macro +regNB_PROG_DEVICE_REMAP_PBr4_BASE_IDX = 8 # macro +regNB_PROG_DEVICE_REMAP_PBr5 = 0xe84033 # macro +regNB_PROG_DEVICE_REMAP_PBr5_BASE_IDX = 8 # macro +regNB_PROG_DEVICE_REMAP_PBr6 = 0xe84034 # macro +regNB_PROG_DEVICE_REMAP_PBr6_BASE_IDX = 8 # macro +regNB_PROG_DEVICE_REMAP_PBr7 = 0xe84035 # macro +regNB_PROG_DEVICE_REMAP_PBr7_BASE_IDX = 8 # macro +regNB_PROG_DEVICE_REMAP_PBr8 = 0xe84036 # macro +regNB_PROG_DEVICE_REMAP_PBr8_BASE_IDX = 8 # macro +regNB_PROG_DEVICE_REMAP_PBr10 = 0xe84038 # macro +regNB_PROG_DEVICE_REMAP_PBr10_BASE_IDX = 8 # macro +regNB_PROG_DEVICE_REMAP_PBr11 = 0xe84039 # macro +regNB_PROG_DEVICE_REMAP_PBr11_BASE_IDX = 8 # macro +regNB_PROG_DEVICE_REMAP_PBr12 = 0xe8403a # macro +regNB_PROG_DEVICE_REMAP_PBr12_BASE_IDX = 8 # macro +regNB_PROG_DEVICE_REMAP_PBr13 = 0xe8403b # macro +regNB_PROG_DEVICE_REMAP_PBr13_BASE_IDX = 8 # macro +regSW_NMI_CNTL = 0xe84042 # macro +regSW_NMI_CNTL_BASE_IDX = 8 # macro +regSW_SMI_CNTL = 0xe84043 # macro +regSW_SMI_CNTL_BASE_IDX = 8 # macro +regSW_SCI_CNTL = 0xe84044 # macro +regSW_SCI_CNTL_BASE_IDX = 8 # macro +regAPML_SW_STATUS = 0xe84045 # macro +regAPML_SW_STATUS_BASE_IDX = 8 # macro +regSW_GIC_SPI_CNTL = 0xe84047 # macro +regSW_GIC_SPI_CNTL_BASE_IDX = 8 # macro +regSW_SYNCFLOOD_CNTL = 0xe84049 # macro +regSW_SYNCFLOOD_CNTL_BASE_IDX = 8 # macro +regNB_TOP_OF_DRAM3 = 0xe8404e # macro +regNB_TOP_OF_DRAM3_BASE_IDX = 8 # macro +regCAM_CONTROL = 0xe84052 # macro +regCAM_CONTROL_BASE_IDX = 8 # macro +regCAM_TARGET_INDEX_ADDR_BOTTOM = 0xe84053 # macro +regCAM_TARGET_INDEX_ADDR_BOTTOM_BASE_IDX = 8 # macro +regCAM_TARGET_INDEX_ADDR_TOP = 0xe84054 # macro +regCAM_TARGET_INDEX_ADDR_TOP_BASE_IDX = 8 # macro +regCAM_TARGET_INDEX_DATA = 0xe84055 # macro +regCAM_TARGET_INDEX_DATA_BASE_IDX = 8 # macro +regCAM_TARGET_INDEX_DATA_MASK = 0xe84056 # macro +regCAM_TARGET_INDEX_DATA_MASK_BASE_IDX = 8 # macro +regCAM_TARGET_DATA_ADDR_BOTTOM = 0xe84057 # macro +regCAM_TARGET_DATA_ADDR_BOTTOM_BASE_IDX = 8 # macro +regCAM_TARGET_DATA_ADDR_TOP = 0xe84059 # macro +regCAM_TARGET_DATA_ADDR_TOP_BASE_IDX = 8 # macro +regCAM_TARGET_DATA = 0xe8405a # macro +regCAM_TARGET_DATA_BASE_IDX = 8 # macro +regCAM_TARGET_DATA_MASK = 0xe8405b # macro +regCAM_TARGET_DATA_MASK_BASE_IDX = 8 # macro +regP_DMA_DROPPED_LOG_LOWER = 0xe84060 # macro +regP_DMA_DROPPED_LOG_LOWER_BASE_IDX = 8 # macro +regP_DMA_DROPPED_LOG_UPPER = 0xe84061 # macro +regP_DMA_DROPPED_LOG_UPPER_BASE_IDX = 8 # macro +regNP_DMA_DROPPED_LOG_LOWER = 0xe84062 # macro +regNP_DMA_DROPPED_LOG_LOWER_BASE_IDX = 8 # macro +regNP_DMA_DROPPED_LOG_UPPER = 0xe84063 # macro +regNP_DMA_DROPPED_LOG_UPPER_BASE_IDX = 8 # macro +regPCIE_VDM_NODE0_CTRL4 = 0xe84064 # macro +regPCIE_VDM_NODE0_CTRL4_BASE_IDX = 8 # macro +regPCIE_VDM_CNTL2 = 0xe8408c # macro +regPCIE_VDM_CNTL2_BASE_IDX = 8 # macro +regPCIE_VDM_CNTL3 = 0xe8408d # macro +regPCIE_VDM_CNTL3_BASE_IDX = 8 # macro +regSTALL_CONTROL_XBARPORT0_0 = 0xe84090 # macro +regSTALL_CONTROL_XBARPORT0_0_BASE_IDX = 8 # macro +regSTALL_CONTROL_XBARPORT0_1 = 0xe84091 # macro +regSTALL_CONTROL_XBARPORT0_1_BASE_IDX = 8 # macro +regSTALL_CONTROL_XBARPORT1_0 = 0xe84093 # macro +regSTALL_CONTROL_XBARPORT1_0_BASE_IDX = 8 # macro +regSTALL_CONTROL_XBARPORT1_1 = 0xe84094 # macro +regSTALL_CONTROL_XBARPORT1_1_BASE_IDX = 8 # macro +regSTALL_CONTROL_XBARPORT2_0 = 0xe84096 # macro +regSTALL_CONTROL_XBARPORT2_0_BASE_IDX = 8 # macro +regSTALL_CONTROL_XBARPORT2_1 = 0xe84097 # macro +regSTALL_CONTROL_XBARPORT2_1_BASE_IDX = 8 # macro +regSTALL_CONTROL_XBARPORT3_0 = 0xe84099 # macro +regSTALL_CONTROL_XBARPORT3_0_BASE_IDX = 8 # macro +regSTALL_CONTROL_XBARPORT3_1 = 0xe8409a # macro +regSTALL_CONTROL_XBARPORT3_1_BASE_IDX = 8 # macro +regSTALL_CONTROL_XBARPORT4_0 = 0xe8409c # macro +regSTALL_CONTROL_XBARPORT4_0_BASE_IDX = 8 # macro +regSTALL_CONTROL_XBARPORT4_1 = 0xe8409d # macro +regSTALL_CONTROL_XBARPORT4_1_BASE_IDX = 8 # macro +regSTALL_CONTROL_XBARPORT5_0 = 0xe8409f # macro +regSTALL_CONTROL_XBARPORT5_0_BASE_IDX = 8 # macro +regSTALL_CONTROL_XBARPORT5_1 = 0xe840a0 # macro +regSTALL_CONTROL_XBARPORT5_1_BASE_IDX = 8 # macro +regNB_DRAM3_BASE = 0xe840b1 # macro +regNB_DRAM3_BASE_BASE_IDX = 8 # macro +regPSP_BASE_ADDR_LO = 0xe840b8 # macro +regPSP_BASE_ADDR_LO_BASE_IDX = 8 # macro +regPSP_BASE_ADDR_HI = 0xe840b9 # macro +regPSP_BASE_ADDR_HI_BASE_IDX = 8 # macro +regSMU_BASE_ADDR_LO = 0xe840ba # macro +regSMU_BASE_ADDR_LO_BASE_IDX = 8 # macro +regSMU_BASE_ADDR_HI = 0xe840bb # macro +regSMU_BASE_ADDR_HI_BASE_IDX = 8 # macro +regSCRATCH_4 = 0xe840fc # macro +regSCRATCH_4_BASE_IDX = 8 # macro +regSCRATCH_5 = 0xe840fd # macro +regSCRATCH_5_BASE_IDX = 8 # macro +regSMU_BLOCK_CPU = 0xe840fe # macro +regSMU_BLOCK_CPU_BASE_IDX = 8 # macro +regSMU_BLOCK_CPU_STATUS = 0xe840ff # macro +regSMU_BLOCK_CPU_STATUS_BASE_IDX = 8 # macro +regTRAP_STATUS = 0xe84100 # macro +regTRAP_STATUS_BASE_IDX = 8 # macro +regTRAP_REQUEST0 = 0xe84101 # macro +regTRAP_REQUEST0_BASE_IDX = 8 # macro +regTRAP_REQUEST1 = 0xe84102 # macro +regTRAP_REQUEST1_BASE_IDX = 8 # macro +regTRAP_REQUEST2 = 0xe84103 # macro +regTRAP_REQUEST2_BASE_IDX = 8 # macro +regTRAP_REQUEST3 = 0xe84104 # macro +regTRAP_REQUEST3_BASE_IDX = 8 # macro +regTRAP_REQUEST4 = 0xe84105 # macro +regTRAP_REQUEST4_BASE_IDX = 8 # macro +regTRAP_REQUEST5 = 0xe84106 # macro +regTRAP_REQUEST5_BASE_IDX = 8 # macro +regTRAP_REQUEST_DATASTRB0 = 0xe84108 # macro +regTRAP_REQUEST_DATASTRB0_BASE_IDX = 8 # macro +regTRAP_REQUEST_DATASTRB1 = 0xe84109 # macro +regTRAP_REQUEST_DATASTRB1_BASE_IDX = 8 # macro +regTRAP_REQUEST_DATA0 = 0xe84110 # macro +regTRAP_REQUEST_DATA0_BASE_IDX = 8 # macro +regTRAP_REQUEST_DATA1 = 0xe84111 # macro +regTRAP_REQUEST_DATA1_BASE_IDX = 8 # macro +regTRAP_REQUEST_DATA2 = 0xe84112 # macro +regTRAP_REQUEST_DATA2_BASE_IDX = 8 # macro +regTRAP_REQUEST_DATA3 = 0xe84113 # macro +regTRAP_REQUEST_DATA3_BASE_IDX = 8 # macro +regTRAP_REQUEST_DATA4 = 0xe84114 # macro +regTRAP_REQUEST_DATA4_BASE_IDX = 8 # macro +regTRAP_REQUEST_DATA5 = 0xe84115 # macro +regTRAP_REQUEST_DATA5_BASE_IDX = 8 # macro +regTRAP_REQUEST_DATA6 = 0xe84116 # macro +regTRAP_REQUEST_DATA6_BASE_IDX = 8 # macro +regTRAP_REQUEST_DATA7 = 0xe84117 # macro +regTRAP_REQUEST_DATA7_BASE_IDX = 8 # macro +regTRAP_REQUEST_DATA8 = 0xe84118 # macro +regTRAP_REQUEST_DATA8_BASE_IDX = 8 # macro +regTRAP_REQUEST_DATA9 = 0xe84119 # macro +regTRAP_REQUEST_DATA9_BASE_IDX = 8 # macro +regTRAP_REQUEST_DATA10 = 0xe8411a # macro +regTRAP_REQUEST_DATA10_BASE_IDX = 8 # macro +regTRAP_REQUEST_DATA11 = 0xe8411b # macro +regTRAP_REQUEST_DATA11_BASE_IDX = 8 # macro +regTRAP_REQUEST_DATA12 = 0xe8411c # macro +regTRAP_REQUEST_DATA12_BASE_IDX = 8 # macro +regTRAP_REQUEST_DATA13 = 0xe8411d # macro +regTRAP_REQUEST_DATA13_BASE_IDX = 8 # macro +regTRAP_REQUEST_DATA14 = 0xe8411e # macro +regTRAP_REQUEST_DATA14_BASE_IDX = 8 # macro +regTRAP_REQUEST_DATA15 = 0xe8411f # macro +regTRAP_REQUEST_DATA15_BASE_IDX = 8 # macro +regTRAP_RESPONSE_CONTROL = 0xe84130 # macro +regTRAP_RESPONSE_CONTROL_BASE_IDX = 8 # macro +regTRAP_RESPONSE0 = 0xe84131 # macro +regTRAP_RESPONSE0_BASE_IDX = 8 # macro +regTRAP_RESPONSE_DATA0 = 0xe84140 # macro +regTRAP_RESPONSE_DATA0_BASE_IDX = 8 # macro +regTRAP_RESPONSE_DATA1 = 0xe84141 # macro +regTRAP_RESPONSE_DATA1_BASE_IDX = 8 # macro +regTRAP_RESPONSE_DATA2 = 0xe84142 # macro +regTRAP_RESPONSE_DATA2_BASE_IDX = 8 # macro +regTRAP_RESPONSE_DATA3 = 0xe84143 # macro +regTRAP_RESPONSE_DATA3_BASE_IDX = 8 # macro +regTRAP_RESPONSE_DATA4 = 0xe84144 # macro +regTRAP_RESPONSE_DATA4_BASE_IDX = 8 # macro +regTRAP_RESPONSE_DATA5 = 0xe84145 # macro +regTRAP_RESPONSE_DATA5_BASE_IDX = 8 # macro +regTRAP_RESPONSE_DATA6 = 0xe84146 # macro +regTRAP_RESPONSE_DATA6_BASE_IDX = 8 # macro +regTRAP_RESPONSE_DATA7 = 0xe84147 # macro +regTRAP_RESPONSE_DATA7_BASE_IDX = 8 # macro +regTRAP_RESPONSE_DATA8 = 0xe84148 # macro +regTRAP_RESPONSE_DATA8_BASE_IDX = 8 # macro +regTRAP_RESPONSE_DATA9 = 0xe84149 # macro +regTRAP_RESPONSE_DATA9_BASE_IDX = 8 # macro +regTRAP_RESPONSE_DATA10 = 0xe8414a # macro +regTRAP_RESPONSE_DATA10_BASE_IDX = 8 # macro +regTRAP_RESPONSE_DATA11 = 0xe8414b # macro +regTRAP_RESPONSE_DATA11_BASE_IDX = 8 # macro +regTRAP_RESPONSE_DATA12 = 0xe8414c # macro +regTRAP_RESPONSE_DATA12_BASE_IDX = 8 # macro +regTRAP_RESPONSE_DATA13 = 0xe8414d # macro +regTRAP_RESPONSE_DATA13_BASE_IDX = 8 # macro +regTRAP_RESPONSE_DATA14 = 0xe8414e # macro +regTRAP_RESPONSE_DATA14_BASE_IDX = 8 # macro +regTRAP_RESPONSE_DATA15 = 0xe8414f # macro +regTRAP_RESPONSE_DATA15_BASE_IDX = 8 # macro +regTRAP0_CONTROL0 = 0xe84200 # macro +regTRAP0_CONTROL0_BASE_IDX = 8 # macro +regTRAP0_ADDRESS_LO = 0xe84202 # macro +regTRAP0_ADDRESS_LO_BASE_IDX = 8 # macro +regTRAP0_ADDRESS_HI = 0xe84203 # macro +regTRAP0_ADDRESS_HI_BASE_IDX = 8 # macro +regTRAP0_COMMAND = 0xe84204 # macro +regTRAP0_COMMAND_BASE_IDX = 8 # macro +regTRAP0_ADDRESS_LO_MASK = 0xe84206 # macro +regTRAP0_ADDRESS_LO_MASK_BASE_IDX = 8 # macro +regTRAP0_ADDRESS_HI_MASK = 0xe84207 # macro +regTRAP0_ADDRESS_HI_MASK_BASE_IDX = 8 # macro +regTRAP0_COMMAND_MASK = 0xe84208 # macro +regTRAP0_COMMAND_MASK_BASE_IDX = 8 # macro +regTRAP1_CONTROL0 = 0xe84210 # macro +regTRAP1_CONTROL0_BASE_IDX = 8 # macro +regTRAP1_ADDRESS_LO = 0xe84212 # macro +regTRAP1_ADDRESS_LO_BASE_IDX = 8 # macro +regTRAP1_ADDRESS_HI = 0xe84213 # macro +regTRAP1_ADDRESS_HI_BASE_IDX = 8 # macro +regTRAP1_COMMAND = 0xe84214 # macro +regTRAP1_COMMAND_BASE_IDX = 8 # macro +regTRAP1_ADDRESS_LO_MASK = 0xe84216 # macro +regTRAP1_ADDRESS_LO_MASK_BASE_IDX = 8 # macro +regTRAP1_ADDRESS_HI_MASK = 0xe84217 # macro +regTRAP1_ADDRESS_HI_MASK_BASE_IDX = 8 # macro +regTRAP1_COMMAND_MASK = 0xe84218 # macro +regTRAP1_COMMAND_MASK_BASE_IDX = 8 # macro +regTRAP2_CONTROL0 = 0xe84220 # macro +regTRAP2_CONTROL0_BASE_IDX = 8 # macro +regTRAP2_ADDRESS_LO = 0xe84222 # macro +regTRAP2_ADDRESS_LO_BASE_IDX = 8 # macro +regTRAP2_ADDRESS_HI = 0xe84223 # macro +regTRAP2_ADDRESS_HI_BASE_IDX = 8 # macro +regTRAP2_COMMAND = 0xe84224 # macro +regTRAP2_COMMAND_BASE_IDX = 8 # macro +regTRAP2_ADDRESS_LO_MASK = 0xe84226 # macro +regTRAP2_ADDRESS_LO_MASK_BASE_IDX = 8 # macro +regTRAP2_ADDRESS_HI_MASK = 0xe84227 # macro +regTRAP2_ADDRESS_HI_MASK_BASE_IDX = 8 # macro +regTRAP2_COMMAND_MASK = 0xe84228 # macro +regTRAP2_COMMAND_MASK_BASE_IDX = 8 # macro +regTRAP3_CONTROL0 = 0xe84230 # macro +regTRAP3_CONTROL0_BASE_IDX = 8 # macro +regTRAP3_ADDRESS_LO = 0xe84232 # macro +regTRAP3_ADDRESS_LO_BASE_IDX = 8 # macro +regTRAP3_ADDRESS_HI = 0xe84233 # macro +regTRAP3_ADDRESS_HI_BASE_IDX = 8 # macro +regTRAP3_COMMAND = 0xe84234 # macro +regTRAP3_COMMAND_BASE_IDX = 8 # macro +regTRAP3_ADDRESS_LO_MASK = 0xe84236 # macro +regTRAP3_ADDRESS_LO_MASK_BASE_IDX = 8 # macro +regTRAP3_ADDRESS_HI_MASK = 0xe84237 # macro +regTRAP3_ADDRESS_HI_MASK_BASE_IDX = 8 # macro +regTRAP3_COMMAND_MASK = 0xe84238 # macro +regTRAP3_COMMAND_MASK_BASE_IDX = 8 # macro +regTRAP4_CONTROL0 = 0xe84240 # macro +regTRAP4_CONTROL0_BASE_IDX = 8 # macro +regTRAP4_ADDRESS_LO = 0xe84242 # macro +regTRAP4_ADDRESS_LO_BASE_IDX = 8 # macro +regTRAP4_ADDRESS_HI = 0xe84243 # macro +regTRAP4_ADDRESS_HI_BASE_IDX = 8 # macro +regTRAP4_COMMAND = 0xe84244 # macro +regTRAP4_COMMAND_BASE_IDX = 8 # macro +regTRAP4_ADDRESS_LO_MASK = 0xe84246 # macro +regTRAP4_ADDRESS_LO_MASK_BASE_IDX = 8 # macro +regTRAP4_ADDRESS_HI_MASK = 0xe84247 # macro +regTRAP4_ADDRESS_HI_MASK_BASE_IDX = 8 # macro +regTRAP4_COMMAND_MASK = 0xe84248 # macro +regTRAP4_COMMAND_MASK_BASE_IDX = 8 # macro +regTRAP5_CONTROL0 = 0xe84250 # macro +regTRAP5_CONTROL0_BASE_IDX = 8 # macro +regTRAP5_ADDRESS_LO = 0xe84252 # macro +regTRAP5_ADDRESS_LO_BASE_IDX = 8 # macro +regTRAP5_ADDRESS_HI = 0xe84253 # macro +regTRAP5_ADDRESS_HI_BASE_IDX = 8 # macro +regTRAP5_COMMAND = 0xe84254 # macro +regTRAP5_COMMAND_BASE_IDX = 8 # macro +regTRAP5_ADDRESS_LO_MASK = 0xe84256 # macro +regTRAP5_ADDRESS_LO_MASK_BASE_IDX = 8 # macro +regTRAP5_ADDRESS_HI_MASK = 0xe84257 # macro +regTRAP5_ADDRESS_HI_MASK_BASE_IDX = 8 # macro +regTRAP5_COMMAND_MASK = 0xe84258 # macro +regTRAP5_COMMAND_MASK_BASE_IDX = 8 # macro +regTRAP6_CONTROL0 = 0xe84260 # macro +regTRAP6_CONTROL0_BASE_IDX = 8 # macro +regTRAP6_ADDRESS_LO = 0xe84262 # macro +regTRAP6_ADDRESS_LO_BASE_IDX = 8 # macro +regTRAP6_ADDRESS_HI = 0xe84263 # macro +regTRAP6_ADDRESS_HI_BASE_IDX = 8 # macro +regTRAP6_COMMAND = 0xe84264 # macro +regTRAP6_COMMAND_BASE_IDX = 8 # macro +regTRAP6_ADDRESS_LO_MASK = 0xe84266 # macro +regTRAP6_ADDRESS_LO_MASK_BASE_IDX = 8 # macro +regTRAP6_ADDRESS_HI_MASK = 0xe84267 # macro +regTRAP6_ADDRESS_HI_MASK_BASE_IDX = 8 # macro +regTRAP6_COMMAND_MASK = 0xe84268 # macro +regTRAP6_COMMAND_MASK_BASE_IDX = 8 # macro +regTRAP7_CONTROL0 = 0xe84270 # macro +regTRAP7_CONTROL0_BASE_IDX = 8 # macro +regTRAP7_ADDRESS_LO = 0xe84272 # macro +regTRAP7_ADDRESS_LO_BASE_IDX = 8 # macro +regTRAP7_ADDRESS_HI = 0xe84273 # macro +regTRAP7_ADDRESS_HI_BASE_IDX = 8 # macro +regTRAP7_COMMAND = 0xe84274 # macro +regTRAP7_COMMAND_BASE_IDX = 8 # macro +regTRAP7_ADDRESS_LO_MASK = 0xe84276 # macro +regTRAP7_ADDRESS_LO_MASK_BASE_IDX = 8 # macro +regTRAP7_ADDRESS_HI_MASK = 0xe84277 # macro +regTRAP7_ADDRESS_HI_MASK_BASE_IDX = 8 # macro +regTRAP7_COMMAND_MASK = 0xe84278 # macro +regTRAP7_COMMAND_MASK_BASE_IDX = 8 # macro +regTRAP8_CONTROL0 = 0xe84280 # macro +regTRAP8_CONTROL0_BASE_IDX = 8 # macro +regTRAP8_ADDRESS_LO = 0xe84282 # macro +regTRAP8_ADDRESS_LO_BASE_IDX = 8 # macro +regTRAP8_ADDRESS_HI = 0xe84283 # macro +regTRAP8_ADDRESS_HI_BASE_IDX = 8 # macro +regTRAP8_COMMAND = 0xe84284 # macro +regTRAP8_COMMAND_BASE_IDX = 8 # macro +regTRAP8_ADDRESS_LO_MASK = 0xe84286 # macro +regTRAP8_ADDRESS_LO_MASK_BASE_IDX = 8 # macro +regTRAP8_ADDRESS_HI_MASK = 0xe84287 # macro +regTRAP8_ADDRESS_HI_MASK_BASE_IDX = 8 # macro +regTRAP8_COMMAND_MASK = 0xe84288 # macro +regTRAP8_COMMAND_MASK_BASE_IDX = 8 # macro +regTRAP9_CONTROL0 = 0xe84290 # macro +regTRAP9_CONTROL0_BASE_IDX = 8 # macro +regTRAP9_ADDRESS_LO = 0xe84292 # macro +regTRAP9_ADDRESS_LO_BASE_IDX = 8 # macro +regTRAP9_ADDRESS_HI = 0xe84293 # macro +regTRAP9_ADDRESS_HI_BASE_IDX = 8 # macro +regTRAP9_COMMAND = 0xe84294 # macro +regTRAP9_COMMAND_BASE_IDX = 8 # macro +regTRAP9_ADDRESS_LO_MASK = 0xe84296 # macro +regTRAP9_ADDRESS_LO_MASK_BASE_IDX = 8 # macro +regTRAP9_ADDRESS_HI_MASK = 0xe84297 # macro +regTRAP9_ADDRESS_HI_MASK_BASE_IDX = 8 # macro +regTRAP9_COMMAND_MASK = 0xe84298 # macro +regTRAP9_COMMAND_MASK_BASE_IDX = 8 # macro +regTRAP10_CONTROL0 = 0xe842a0 # macro +regTRAP10_CONTROL0_BASE_IDX = 8 # macro +regTRAP10_ADDRESS_LO = 0xe842a2 # macro +regTRAP10_ADDRESS_LO_BASE_IDX = 8 # macro +regTRAP10_ADDRESS_HI = 0xe842a3 # macro +regTRAP10_ADDRESS_HI_BASE_IDX = 8 # macro +regTRAP10_COMMAND = 0xe842a4 # macro +regTRAP10_COMMAND_BASE_IDX = 8 # macro +regTRAP10_ADDRESS_LO_MASK = 0xe842a6 # macro +regTRAP10_ADDRESS_LO_MASK_BASE_IDX = 8 # macro +regTRAP10_ADDRESS_HI_MASK = 0xe842a7 # macro +regTRAP10_ADDRESS_HI_MASK_BASE_IDX = 8 # macro +regTRAP10_COMMAND_MASK = 0xe842a8 # macro +regTRAP10_COMMAND_MASK_BASE_IDX = 8 # macro +regTRAP11_CONTROL0 = 0xe842b0 # macro +regTRAP11_CONTROL0_BASE_IDX = 8 # macro +regTRAP11_ADDRESS_LO = 0xe842b2 # macro +regTRAP11_ADDRESS_LO_BASE_IDX = 8 # macro +regTRAP11_ADDRESS_HI = 0xe842b3 # macro +regTRAP11_ADDRESS_HI_BASE_IDX = 8 # macro +regTRAP11_COMMAND = 0xe842b4 # macro +regTRAP11_COMMAND_BASE_IDX = 8 # macro +regTRAP11_ADDRESS_LO_MASK = 0xe842b6 # macro +regTRAP11_ADDRESS_LO_MASK_BASE_IDX = 8 # macro +regTRAP11_ADDRESS_HI_MASK = 0xe842b7 # macro +regTRAP11_ADDRESS_HI_MASK_BASE_IDX = 8 # macro +regTRAP11_COMMAND_MASK = 0xe842b8 # macro +regTRAP11_COMMAND_MASK_BASE_IDX = 8 # macro +regTRAP12_CONTROL0 = 0xe842c0 # macro +regTRAP12_CONTROL0_BASE_IDX = 8 # macro +regTRAP12_ADDRESS_LO = 0xe842c2 # macro +regTRAP12_ADDRESS_LO_BASE_IDX = 8 # macro +regTRAP12_ADDRESS_HI = 0xe842c3 # macro +regTRAP12_ADDRESS_HI_BASE_IDX = 8 # macro +regTRAP12_COMMAND = 0xe842c4 # macro +regTRAP12_COMMAND_BASE_IDX = 8 # macro +regTRAP12_ADDRESS_LO_MASK = 0xe842c6 # macro +regTRAP12_ADDRESS_LO_MASK_BASE_IDX = 8 # macro +regTRAP12_ADDRESS_HI_MASK = 0xe842c7 # macro +regTRAP12_ADDRESS_HI_MASK_BASE_IDX = 8 # macro +regTRAP12_COMMAND_MASK = 0xe842c8 # macro +regTRAP12_COMMAND_MASK_BASE_IDX = 8 # macro +regTRAP13_CONTROL0 = 0xe842d0 # macro +regTRAP13_CONTROL0_BASE_IDX = 8 # macro +regTRAP13_ADDRESS_LO = 0xe842d2 # macro +regTRAP13_ADDRESS_LO_BASE_IDX = 8 # macro +regTRAP13_ADDRESS_HI = 0xe842d3 # macro +regTRAP13_ADDRESS_HI_BASE_IDX = 8 # macro +regTRAP13_COMMAND = 0xe842d4 # macro +regTRAP13_COMMAND_BASE_IDX = 8 # macro +regTRAP13_ADDRESS_LO_MASK = 0xe842d6 # macro +regTRAP13_ADDRESS_LO_MASK_BASE_IDX = 8 # macro +regTRAP13_ADDRESS_HI_MASK = 0xe842d7 # macro +regTRAP13_ADDRESS_HI_MASK_BASE_IDX = 8 # macro +regTRAP13_COMMAND_MASK = 0xe842d8 # macro +regTRAP13_COMMAND_MASK_BASE_IDX = 8 # macro +regTRAP14_CONTROL0 = 0xe842e0 # macro +regTRAP14_CONTROL0_BASE_IDX = 8 # macro +regTRAP14_ADDRESS_LO = 0xe842e2 # macro +regTRAP14_ADDRESS_LO_BASE_IDX = 8 # macro +regTRAP14_ADDRESS_HI = 0xe842e3 # macro +regTRAP14_ADDRESS_HI_BASE_IDX = 8 # macro +regTRAP14_COMMAND = 0xe842e4 # macro +regTRAP14_COMMAND_BASE_IDX = 8 # macro +regTRAP14_ADDRESS_LO_MASK = 0xe842e6 # macro +regTRAP14_ADDRESS_LO_MASK_BASE_IDX = 8 # macro +regTRAP14_ADDRESS_HI_MASK = 0xe842e7 # macro +regTRAP14_ADDRESS_HI_MASK_BASE_IDX = 8 # macro +regTRAP14_COMMAND_MASK = 0xe842e8 # macro +regTRAP14_COMMAND_MASK_BASE_IDX = 8 # macro +regTRAP15_CONTROL0 = 0xe842f0 # macro +regTRAP15_CONTROL0_BASE_IDX = 8 # macro +regTRAP15_ADDRESS_LO = 0xe842f2 # macro +regTRAP15_ADDRESS_LO_BASE_IDX = 8 # macro +regTRAP15_ADDRESS_HI = 0xe842f3 # macro +regTRAP15_ADDRESS_HI_BASE_IDX = 8 # macro +regTRAP15_COMMAND = 0xe842f4 # macro +regTRAP15_COMMAND_BASE_IDX = 8 # macro +regTRAP15_ADDRESS_LO_MASK = 0xe842f6 # macro +regTRAP15_ADDRESS_LO_MASK_BASE_IDX = 8 # macro +regTRAP15_ADDRESS_HI_MASK = 0xe842f7 # macro +regTRAP15_ADDRESS_HI_MASK_BASE_IDX = 8 # macro +regTRAP15_COMMAND_MASK = 0xe842f8 # macro +regTRAP15_COMMAND_MASK_BASE_IDX = 8 # macro +regSB_COMMAND = 0xe85000 # macro +regSB_COMMAND_BASE_IDX = 8 # macro +regSB_SUB_BUS_NUMBER_LATENCY = 0xe85001 # macro +regSB_SUB_BUS_NUMBER_LATENCY_BASE_IDX = 8 # macro +regSB_IO_BASE_LIMIT = 0xe85002 # macro +regSB_IO_BASE_LIMIT_BASE_IDX = 8 # macro +regSB_MEM_BASE_LIMIT = 0xe85003 # macro +regSB_MEM_BASE_LIMIT_BASE_IDX = 8 # macro +regSB_PREF_BASE_LIMIT = 0xe85004 # macro +regSB_PREF_BASE_LIMIT_BASE_IDX = 8 # macro +regSB_PREF_BASE_UPPER = 0xe85005 # macro +regSB_PREF_BASE_UPPER_BASE_IDX = 8 # macro +regSB_PREF_LIMIT_UPPER = 0xe85006 # macro +regSB_PREF_LIMIT_UPPER_BASE_IDX = 8 # macro +regSB_IO_BASE_LIMIT_HI = 0xe85007 # macro +regSB_IO_BASE_LIMIT_HI_BASE_IDX = 8 # macro +regSB_IRQ_BRIDGE_CNTL = 0xe85008 # macro +regSB_IRQ_BRIDGE_CNTL_BASE_IDX = 8 # macro +regSB_EXT_BRIDGE_CNTL = 0xe85009 # macro +regSB_EXT_BRIDGE_CNTL_BASE_IDX = 8 # macro +regSB_PMI_STATUS_CNTL = 0xe8500a # macro +regSB_PMI_STATUS_CNTL_BASE_IDX = 8 # macro +regSB_SLOT_CAP = 0xe8500b # macro +regSB_SLOT_CAP_BASE_IDX = 8 # macro +regSB_ROOT_CNTL = 0xe8500c # macro +regSB_ROOT_CNTL_BASE_IDX = 8 # macro +regSB_DEVICE_CNTL2 = 0xe8500d # macro +regSB_DEVICE_CNTL2_BASE_IDX = 8 # macro +regMCA_SMN_INT_REQ_ADDR = 0xe85020 # macro +regMCA_SMN_INT_REQ_ADDR_BASE_IDX = 8 # macro +regMCA_SMN_INT_MCM_ADDR = 0xe85021 # macro +regMCA_SMN_INT_MCM_ADDR_BASE_IDX = 8 # macro +regMCA_SMN_INT_APERTUREID = 0xe85022 # macro +regMCA_SMN_INT_APERTUREID_BASE_IDX = 8 # macro +regMCA_SMN_INT_CONTROL = 0xe85023 # macro +regMCA_SMN_INT_CONTROL_BASE_IDX = 8 # macro +regPARITY_CONTROL_0 = 0xe88000 # macro +regPARITY_CONTROL_0_BASE_IDX = 8 # macro +regPARITY_CONTROL_1 = 0xe88001 # macro +regPARITY_CONTROL_1_BASE_IDX = 8 # macro +regPARITY_SEVERITY_CONTROL_UNCORR_0 = 0xe88002 # macro +regPARITY_SEVERITY_CONTROL_UNCORR_0_BASE_IDX = 8 # macro +regPARITY_SEVERITY_CONTROL_CORR_0 = 0xe88004 # macro +regPARITY_SEVERITY_CONTROL_CORR_0_BASE_IDX = 8 # macro +regPARITY_SEVERITY_CONTROL_UCP_0 = 0xe88006 # macro +regPARITY_SEVERITY_CONTROL_UCP_0_BASE_IDX = 8 # macro +regRAS_GLOBAL_STATUS_LO = 0xe88008 # macro +regRAS_GLOBAL_STATUS_LO_BASE_IDX = 8 # macro +regRAS_GLOBAL_STATUS_HI = 0xe88009 # macro +regRAS_GLOBAL_STATUS_HI_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP0 = 0xe8800a # macro +regPARITY_ERROR_STATUS_UNCORR_GRP0_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP1 = 0xe8800b # macro +regPARITY_ERROR_STATUS_UNCORR_GRP1_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP2 = 0xe8800c # macro +regPARITY_ERROR_STATUS_UNCORR_GRP2_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP3 = 0xe8800d # macro +regPARITY_ERROR_STATUS_UNCORR_GRP3_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP4 = 0xe8800e # macro +regPARITY_ERROR_STATUS_UNCORR_GRP4_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP5 = 0xe8800f # macro +regPARITY_ERROR_STATUS_UNCORR_GRP5_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP6 = 0xe88010 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP6_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP7 = 0xe88011 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP7_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP10 = 0xe88014 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP10_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP11 = 0xe88015 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP11_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP12 = 0xe88016 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP12_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP13 = 0xe88017 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP13_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP14 = 0xe88018 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP14_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP15 = 0xe88019 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP15_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UNCORR_GRP16 = 0xe8801a # macro +regPARITY_ERROR_STATUS_UNCORR_GRP16_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_CORR_GRP0 = 0xe8801b # macro +regPARITY_ERROR_STATUS_CORR_GRP0_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_CORR_GRP1 = 0xe8801c # macro +regPARITY_ERROR_STATUS_CORR_GRP1_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_CORR_GRP2 = 0xe8801d # macro +regPARITY_ERROR_STATUS_CORR_GRP2_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_CORR_GRP3 = 0xe8801e # macro +regPARITY_ERROR_STATUS_CORR_GRP3_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_CORR_GRP4 = 0xe8801f # macro +regPARITY_ERROR_STATUS_CORR_GRP4_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_CORR_GRP5 = 0xe88020 # macro +regPARITY_ERROR_STATUS_CORR_GRP5_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_CORR_GRP6 = 0xe88021 # macro +regPARITY_ERROR_STATUS_CORR_GRP6_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_CORR_GRP7 = 0xe88022 # macro +regPARITY_ERROR_STATUS_CORR_GRP7_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_CORR_GRP10 = 0xe88025 # macro +regPARITY_ERROR_STATUS_CORR_GRP10_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_CORR_GRP11 = 0xe88026 # macro +regPARITY_ERROR_STATUS_CORR_GRP11_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_CORR_GRP12 = 0xe88027 # macro +regPARITY_ERROR_STATUS_CORR_GRP12_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_CORR_GRP13 = 0xe88028 # macro +regPARITY_ERROR_STATUS_CORR_GRP13_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_CORR_GRP14 = 0xe88029 # macro +regPARITY_ERROR_STATUS_CORR_GRP14_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_CORR_GRP15 = 0xe8802a # macro +regPARITY_ERROR_STATUS_CORR_GRP15_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_CORR_GRP16 = 0xe8802b # macro +regPARITY_ERROR_STATUS_CORR_GRP16_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_CORR_GRP17 = 0xe8802c # macro +regPARITY_ERROR_STATUS_CORR_GRP17_BASE_IDX = 8 # macro +regPARITY_COUNTER_CORR_GRP0 = 0xe8802d # macro +regPARITY_COUNTER_CORR_GRP0_BASE_IDX = 8 # macro +regPARITY_COUNTER_CORR_GRP1 = 0xe8802e # macro +regPARITY_COUNTER_CORR_GRP1_BASE_IDX = 8 # macro +regPARITY_COUNTER_CORR_GRP2 = 0xe8802f # macro +regPARITY_COUNTER_CORR_GRP2_BASE_IDX = 8 # macro +regPARITY_COUNTER_CORR_GRP3 = 0xe88030 # macro +regPARITY_COUNTER_CORR_GRP3_BASE_IDX = 8 # macro +regPARITY_COUNTER_CORR_GRP4 = 0xe88031 # macro +regPARITY_COUNTER_CORR_GRP4_BASE_IDX = 8 # macro +regPARITY_COUNTER_CORR_GRP5 = 0xe88032 # macro +regPARITY_COUNTER_CORR_GRP5_BASE_IDX = 8 # macro +regPARITY_COUNTER_CORR_GRP6 = 0xe88033 # macro +regPARITY_COUNTER_CORR_GRP6_BASE_IDX = 8 # macro +regPARITY_COUNTER_CORR_GRP7 = 0xe88034 # macro +regPARITY_COUNTER_CORR_GRP7_BASE_IDX = 8 # macro +regPARITY_COUNTER_CORR_GRP10 = 0xe88037 # macro +regPARITY_COUNTER_CORR_GRP10_BASE_IDX = 8 # macro +regPARITY_COUNTER_CORR_GRP11 = 0xe88038 # macro +regPARITY_COUNTER_CORR_GRP11_BASE_IDX = 8 # macro +regPARITY_COUNTER_CORR_GRP12 = 0xe88039 # macro +regPARITY_COUNTER_CORR_GRP12_BASE_IDX = 8 # macro +regPARITY_COUNTER_CORR_GRP13 = 0xe8803a # macro +regPARITY_COUNTER_CORR_GRP13_BASE_IDX = 8 # macro +regPARITY_COUNTER_CORR_GRP14 = 0xe8803b # macro +regPARITY_COUNTER_CORR_GRP14_BASE_IDX = 8 # macro +regPARITY_COUNTER_CORR_GRP15 = 0xe8803c # macro +regPARITY_COUNTER_CORR_GRP15_BASE_IDX = 8 # macro +regPARITY_COUNTER_CORR_GRP16 = 0xe8803d # macro +regPARITY_COUNTER_CORR_GRP16_BASE_IDX = 8 # macro +regPARITY_COUNTER_CORR_GRP17 = 0xe8803e # macro +regPARITY_COUNTER_CORR_GRP17_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UCP_GRP0 = 0xe8803f # macro +regPARITY_ERROR_STATUS_UCP_GRP0_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UCP_GRP1 = 0xe88040 # macro +regPARITY_ERROR_STATUS_UCP_GRP1_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UCP_GRP2 = 0xe88041 # macro +regPARITY_ERROR_STATUS_UCP_GRP2_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UCP_GRP3 = 0xe88042 # macro +regPARITY_ERROR_STATUS_UCP_GRP3_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UCP_GRP4 = 0xe88043 # macro +regPARITY_ERROR_STATUS_UCP_GRP4_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UCP_GRP5 = 0xe88044 # macro +regPARITY_ERROR_STATUS_UCP_GRP5_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UCP_GRP6 = 0xe88045 # macro +regPARITY_ERROR_STATUS_UCP_GRP6_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UCP_GRP7 = 0xe88046 # macro +regPARITY_ERROR_STATUS_UCP_GRP7_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UCP_GRP10 = 0xe88049 # macro +regPARITY_ERROR_STATUS_UCP_GRP10_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UCP_GRP11 = 0xe8804a # macro +regPARITY_ERROR_STATUS_UCP_GRP11_BASE_IDX = 8 # macro +regPARITY_ERROR_STATUS_UCP_GRP12 = 0xe8804b # macro +regPARITY_ERROR_STATUS_UCP_GRP12_BASE_IDX = 8 # macro +regPARITY_COUNTER_UCP_GRP0 = 0xe8804c # macro +regPARITY_COUNTER_UCP_GRP0_BASE_IDX = 8 # macro +regPARITY_COUNTER_UCP_GRP1 = 0xe8804d # macro +regPARITY_COUNTER_UCP_GRP1_BASE_IDX = 8 # macro +regPARITY_COUNTER_UCP_GRP2 = 0xe8804e # macro +regPARITY_COUNTER_UCP_GRP2_BASE_IDX = 8 # macro +regPARITY_COUNTER_UCP_GRP3 = 0xe8804f # macro +regPARITY_COUNTER_UCP_GRP3_BASE_IDX = 8 # macro +regPARITY_COUNTER_UCP_GRP4 = 0xe88050 # macro +regPARITY_COUNTER_UCP_GRP4_BASE_IDX = 8 # macro +regPARITY_COUNTER_UCP_GRP5 = 0xe88051 # macro +regPARITY_COUNTER_UCP_GRP5_BASE_IDX = 8 # macro +regPARITY_COUNTER_UCP_GRP6 = 0xe88052 # macro +regPARITY_COUNTER_UCP_GRP6_BASE_IDX = 8 # macro +regPARITY_COUNTER_UCP_GRP7 = 0xe88053 # macro +regPARITY_COUNTER_UCP_GRP7_BASE_IDX = 8 # macro +regPARITY_COUNTER_UCP_GRP10 = 0xe88056 # macro +regPARITY_COUNTER_UCP_GRP10_BASE_IDX = 8 # macro +regPARITY_COUNTER_UCP_GRP11 = 0xe88057 # macro +regPARITY_COUNTER_UCP_GRP11_BASE_IDX = 8 # macro +regPARITY_COUNTER_UCP_GRP12 = 0xe88058 # macro +regPARITY_COUNTER_UCP_GRP12_BASE_IDX = 8 # macro +regMISC_SEVERITY_CONTROL = 0xe88059 # macro +regMISC_SEVERITY_CONTROL_BASE_IDX = 8 # macro +regMISC_RAS_CONTROL = 0xe8805a # macro +regMISC_RAS_CONTROL_BASE_IDX = 8 # macro +regRAS_SCRATCH_0 = 0xe8805b # macro +regRAS_SCRATCH_0_BASE_IDX = 8 # macro +regRAS_SCRATCH_1 = 0xe8805c # macro +regRAS_SCRATCH_1_BASE_IDX = 8 # macro +regErrEvent_ACTION_CONTROL = 0xe8805d # macro +regErrEvent_ACTION_CONTROL_BASE_IDX = 8 # macro +regParitySerr_ACTION_CONTROL = 0xe8805e # macro +regParitySerr_ACTION_CONTROL_BASE_IDX = 8 # macro +regParityFatal_ACTION_CONTROL = 0xe8805f # macro +regParityFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regParityNonFatal_ACTION_CONTROL = 0xe88060 # macro +regParityNonFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regParityCorr_ACTION_CONTROL = 0xe88061 # macro +regParityCorr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortASerr_ACTION_CONTROL = 0xe88062 # macro +regPCIE0PortASerr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortAIntFatal_ACTION_CONTROL = 0xe88063 # macro +regPCIE0PortAIntFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortAIntNonFatal_ACTION_CONTROL = 0xe88064 # macro +regPCIE0PortAIntNonFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortAIntCorr_ACTION_CONTROL = 0xe88065 # macro +regPCIE0PortAIntCorr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortAExtFatal_ACTION_CONTROL = 0xe88066 # macro +regPCIE0PortAExtFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortAExtNonFatal_ACTION_CONTROL = 0xe88067 # macro +regPCIE0PortAExtNonFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortAExtCorr_ACTION_CONTROL = 0xe88068 # macro +regPCIE0PortAExtCorr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortAParityErr_ACTION_CONTROL = 0xe88069 # macro +regPCIE0PortAParityErr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortBSerr_ACTION_CONTROL = 0xe8806a # macro +regPCIE0PortBSerr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortBIntFatal_ACTION_CONTROL = 0xe8806b # macro +regPCIE0PortBIntFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortBIntNonFatal_ACTION_CONTROL = 0xe8806c # macro +regPCIE0PortBIntNonFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortBIntCorr_ACTION_CONTROL = 0xe8806d # macro +regPCIE0PortBIntCorr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortBExtFatal_ACTION_CONTROL = 0xe8806e # macro +regPCIE0PortBExtFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortBExtNonFatal_ACTION_CONTROL = 0xe8806f # macro +regPCIE0PortBExtNonFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortBExtCorr_ACTION_CONTROL = 0xe88070 # macro +regPCIE0PortBExtCorr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortBParityErr_ACTION_CONTROL = 0xe88071 # macro +regPCIE0PortBParityErr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortCSerr_ACTION_CONTROL = 0xe88072 # macro +regPCIE0PortCSerr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortCIntFatal_ACTION_CONTROL = 0xe88073 # macro +regPCIE0PortCIntFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortCIntNonFatal_ACTION_CONTROL = 0xe88074 # macro +regPCIE0PortCIntNonFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortCIntCorr_ACTION_CONTROL = 0xe88075 # macro +regPCIE0PortCIntCorr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortCExtFatal_ACTION_CONTROL = 0xe88076 # macro +regPCIE0PortCExtFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortCExtNonFatal_ACTION_CONTROL = 0xe88077 # macro +regPCIE0PortCExtNonFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortCExtCorr_ACTION_CONTROL = 0xe88078 # macro +regPCIE0PortCExtCorr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortCParityErr_ACTION_CONTROL = 0xe88079 # macro +regPCIE0PortCParityErr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortDSerr_ACTION_CONTROL = 0xe8807a # macro +regPCIE0PortDSerr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortDIntFatal_ACTION_CONTROL = 0xe8807b # macro +regPCIE0PortDIntFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortDIntNonFatal_ACTION_CONTROL = 0xe8807c # macro +regPCIE0PortDIntNonFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortDIntCorr_ACTION_CONTROL = 0xe8807d # macro +regPCIE0PortDIntCorr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortDExtFatal_ACTION_CONTROL = 0xe8807e # macro +regPCIE0PortDExtFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortDExtNonFatal_ACTION_CONTROL = 0xe8807f # macro +regPCIE0PortDExtNonFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortDExtCorr_ACTION_CONTROL = 0xe88080 # macro +regPCIE0PortDExtCorr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortDParityErr_ACTION_CONTROL = 0xe88081 # macro +regPCIE0PortDParityErr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortESerr_ACTION_CONTROL = 0xe88082 # macro +regPCIE0PortESerr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortEIntFatal_ACTION_CONTROL = 0xe88083 # macro +regPCIE0PortEIntFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortEIntNonFatal_ACTION_CONTROL = 0xe88084 # macro +regPCIE0PortEIntNonFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortEIntCorr_ACTION_CONTROL = 0xe88085 # macro +regPCIE0PortEIntCorr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortEExtFatal_ACTION_CONTROL = 0xe88086 # macro +regPCIE0PortEExtFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortEExtNonFatal_ACTION_CONTROL = 0xe88087 # macro +regPCIE0PortEExtNonFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortEExtCorr_ACTION_CONTROL = 0xe88088 # macro +regPCIE0PortEExtCorr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortEParityErr_ACTION_CONTROL = 0xe88089 # macro +regPCIE0PortEParityErr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortFSerr_ACTION_CONTROL = 0xe8808a # macro +regPCIE0PortFSerr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortFIntFatal_ACTION_CONTROL = 0xe8808b # macro +regPCIE0PortFIntFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortFIntNonFatal_ACTION_CONTROL = 0xe8808c # macro +regPCIE0PortFIntNonFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortFIntCorr_ACTION_CONTROL = 0xe8808d # macro +regPCIE0PortFIntCorr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortFExtFatal_ACTION_CONTROL = 0xe8808e # macro +regPCIE0PortFExtFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortFExtNonFatal_ACTION_CONTROL = 0xe8808f # macro +regPCIE0PortFExtNonFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortFExtCorr_ACTION_CONTROL = 0xe88090 # macro +regPCIE0PortFExtCorr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortFParityErr_ACTION_CONTROL = 0xe88091 # macro +regPCIE0PortFParityErr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortGSerr_ACTION_CONTROL = 0xe88092 # macro +regPCIE0PortGSerr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortGIntFatal_ACTION_CONTROL = 0xe88093 # macro +regPCIE0PortGIntFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortGIntNonFatal_ACTION_CONTROL = 0xe88094 # macro +regPCIE0PortGIntNonFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortGIntCorr_ACTION_CONTROL = 0xe88095 # macro +regPCIE0PortGIntCorr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortGExtFatal_ACTION_CONTROL = 0xe88096 # macro +regPCIE0PortGExtFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortGExtNonFatal_ACTION_CONTROL = 0xe88097 # macro +regPCIE0PortGExtNonFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortGExtCorr_ACTION_CONTROL = 0xe88098 # macro +regPCIE0PortGExtCorr_ACTION_CONTROL_BASE_IDX = 8 # macro +regPCIE0PortGParityErr_ACTION_CONTROL = 0xe88099 # macro +regPCIE0PortGParityErr_ACTION_CONTROL_BASE_IDX = 8 # macro +regNBIF1PortASerr_ACTION_CONTROL = 0xe880ca # macro +regNBIF1PortASerr_ACTION_CONTROL_BASE_IDX = 8 # macro +regNBIF1PortAIntFatal_ACTION_CONTROL = 0xe880cb # macro +regNBIF1PortAIntFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regNBIF1PortAIntNonFatal_ACTION_CONTROL = 0xe880cc # macro +regNBIF1PortAIntNonFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regNBIF1PortAIntCorr_ACTION_CONTROL = 0xe880cd # macro +regNBIF1PortAIntCorr_ACTION_CONTROL_BASE_IDX = 8 # macro +regNBIF1PortAExtFatal_ACTION_CONTROL = 0xe880ce # macro +regNBIF1PortAExtFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regNBIF1PortAExtNonFatal_ACTION_CONTROL = 0xe880cf # macro +regNBIF1PortAExtNonFatal_ACTION_CONTROL_BASE_IDX = 8 # macro +regNBIF1PortAExtCorr_ACTION_CONTROL = 0xe880d0 # macro +regNBIF1PortAExtCorr_ACTION_CONTROL_BASE_IDX = 8 # macro +regNBIF1PortAParityErr_ACTION_CONTROL = 0xe880d1 # macro +regNBIF1PortAParityErr_ACTION_CONTROL_BASE_IDX = 8 # macro +regSYNCFLOOD_STATUS = 0xe88200 # macro +regSYNCFLOOD_STATUS_BASE_IDX = 8 # macro +regNMI_STATUS = 0xe88201 # macro +regNMI_STATUS_BASE_IDX = 8 # macro +regPOISON_ACTION_CONTROL = 0xe88205 # macro +regPOISON_ACTION_CONTROL_BASE_IDX = 8 # macro +regINTERNAL_POISON_STATUS = 0xe88206 # macro +regINTERNAL_POISON_STATUS_BASE_IDX = 8 # macro +regINTERNAL_POISON_MASK = 0xe88207 # macro +regINTERNAL_POISON_MASK_BASE_IDX = 8 # macro +regEGRESS_POISON_STATUS_LO = 0xe88208 # macro +regEGRESS_POISON_STATUS_LO_BASE_IDX = 8 # macro +regEGRESS_POISON_STATUS_HI = 0xe88209 # macro +regEGRESS_POISON_STATUS_HI_BASE_IDX = 8 # macro +regEGRESS_POISON_MASK_LO = 0xe8820a # macro +regEGRESS_POISON_MASK_LO_BASE_IDX = 8 # macro +regEGRESS_POISON_MASK_HI = 0xe8820b # macro +regEGRESS_POISON_MASK_HI_BASE_IDX = 8 # macro +regEGRESS_POISON_SEVERITY_DOWN = 0xe8820c # macro +regEGRESS_POISON_SEVERITY_DOWN_BASE_IDX = 8 # macro +regEGRESS_POISON_SEVERITY_UPPER = 0xe8820d # macro +regEGRESS_POISON_SEVERITY_UPPER_BASE_IDX = 8 # macro +regAPML_STATUS = 0xe88370 # macro +regAPML_STATUS_BASE_IDX = 8 # macro +regAPML_CONTROL = 0xe88371 # macro +regAPML_CONTROL_BASE_IDX = 8 # macro +regAPML_TRIGGER = 0xe88372 # macro +regAPML_TRIGGER_BASE_IDX = 8 # macro +regNB_PCIE0DEVINDCFG0_STEERING_CNTL = 0xe8c403 # macro +regNB_PCIE0DEVINDCFG0_STEERING_CNTL_BASE_IDX = 8 # macro +regNB_PCIE0DEVINDCFG1_STEERING_CNTL = 0xe8c503 # macro +regNB_PCIE0DEVINDCFG1_STEERING_CNTL_BASE_IDX = 8 # macro +regNB_PCIE0DEVINDCFG2_STEERING_CNTL = 0xe8c603 # macro +regNB_PCIE0DEVINDCFG2_STEERING_CNTL_BASE_IDX = 8 # macro +regNB_PCIE0DEVINDCFG3_STEERING_CNTL = 0xe8c703 # macro +regNB_PCIE0DEVINDCFG3_STEERING_CNTL_BASE_IDX = 8 # macro +regNB_PCIE0DEVINDCFG4_STEERING_CNTL = 0xe8c803 # macro +regNB_PCIE0DEVINDCFG4_STEERING_CNTL_BASE_IDX = 8 # macro +regNB_PCIE0DEVINDCFG5_STEERING_CNTL = 0xe8c903 # macro +regNB_PCIE0DEVINDCFG5_STEERING_CNTL_BASE_IDX = 8 # macro +regNB_PCIE0DEVINDCFG6_STEERING_CNTL = 0xe8ca03 # macro +regNB_PCIE0DEVINDCFG6_STEERING_CNTL_BASE_IDX = 8 # macro +regNB_NBIF1DEVINDCFG0_STEERING_CNTL = 0xe8e003 # macro +regNB_NBIF1DEVINDCFG0_STEERING_CNTL_BASE_IDX = 8 # macro +regNB_INTSBDEVINDCFG0_STEERING_CNTL = 0xe8f003 # macro +regNB_INTSBDEVINDCFG0_STEERING_CNTL_BASE_IDX = 8 # macro +regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION = 0xe9f5b7 # macro +regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION_BASE_IDX = 8 # macro +regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX = 0xe9f5b8 # macro +regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_BASE_IDX = 8 # macro +regNB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA = 0xe9f5b9 # macro +regNB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA_BASE_IDX = 8 # macro +regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION = 0xe9f5f7 # macro +regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION_BASE_IDX = 8 # macro +regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX = 0xe9f5f8 # macro +regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_BASE_IDX = 8 # macro +regNB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA = 0xe9f5f9 # macro +regNB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA_BASE_IDX = 8 # macro +regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION = 0xe9f637 # macro +regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION_BASE_IDX = 8 # macro +regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX = 0xe9f638 # macro +regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_BASE_IDX = 8 # macro +regNB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA = 0xe9f639 # macro +regNB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA_BASE_IDX = 8 # macro +regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION = 0xe9f677 # macro +regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION_BASE_IDX = 8 # macro +regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX = 0xe9f678 # macro +regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_BASE_IDX = 8 # macro +regNB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA = 0xe9f679 # macro +regNB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA_BASE_IDX = 8 # macro +regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION = 0xe9f6b7 # macro +regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION_BASE_IDX = 8 # macro +regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX = 0xe9f6b8 # macro +regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_BASE_IDX = 8 # macro +regNB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA = 0xe9f6b9 # macro +regNB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA_BASE_IDX = 8 # macro +regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION = 0xe9f6f7 # macro +regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION_BASE_IDX = 8 # macro +regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX = 0xe9f6f8 # macro +regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_BASE_IDX = 8 # macro +regNB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA = 0xe9f6f9 # macro +regNB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA_BASE_IDX = 8 # macro +regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION = 0xe9f737 # macro +regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION_BASE_IDX = 8 # macro +regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX = 0xe9f738 # macro +regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_BASE_IDX = 8 # macro +regNB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA = 0xe9f739 # macro +regNB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA_BASE_IDX = 8 # macro +regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION = 0xe9fcb7 # macro +regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION_BASE_IDX = 8 # macro +regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX = 0xe9fcb8 # macro +regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_BASE_IDX = 8 # macro +regNB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA = 0xe9fcb9 # macro +regNB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA_BASE_IDX = 8 # macro +regL2_PERF_CNTL_0 = 0x1580000 # macro +regL2_PERF_CNTL_0_BASE_IDX = 8 # macro +regL2_PERF_COUNT_0 = 0x1580001 # macro +regL2_PERF_COUNT_0_BASE_IDX = 8 # macro +regL2_PERF_COUNT_1 = 0x1580002 # macro +regL2_PERF_COUNT_1_BASE_IDX = 8 # macro +regL2_PERF_CNTL_1 = 0x1580003 # macro +regL2_PERF_CNTL_1_BASE_IDX = 8 # macro +regL2_PERF_COUNT_2 = 0x1580004 # macro +regL2_PERF_COUNT_2_BASE_IDX = 8 # macro +regL2_PERF_COUNT_3 = 0x1580005 # macro +regL2_PERF_COUNT_3_BASE_IDX = 8 # macro +regL2_STATUS_0 = 0x1580008 # macro +regL2_STATUS_0_BASE_IDX = 8 # macro +regL2_CONTROL_0 = 0x158000c # macro +regL2_CONTROL_0_BASE_IDX = 8 # macro +regL2_CONTROL_1 = 0x158000d # macro +regL2_CONTROL_1_BASE_IDX = 8 # macro +regL2_DTC_CONTROL = 0x1580010 # macro +regL2_DTC_CONTROL_BASE_IDX = 8 # macro +regL2_DTC_HASH_CONTROL = 0x1580011 # macro +regL2_DTC_HASH_CONTROL_BASE_IDX = 8 # macro +regL2_DTC_WAY_CONTROL = 0x1580012 # macro +regL2_DTC_WAY_CONTROL_BASE_IDX = 8 # macro +regL2_ITC_CONTROL = 0x1580014 # macro +regL2_ITC_CONTROL_BASE_IDX = 8 # macro +regL2_ITC_HASH_CONTROL = 0x1580015 # macro +regL2_ITC_HASH_CONTROL_BASE_IDX = 8 # macro +regL2_ITC_WAY_CONTROL = 0x1580016 # macro +regL2_ITC_WAY_CONTROL_BASE_IDX = 8 # macro +regL2_PTC_A_CONTROL = 0x1580018 # macro +regL2_PTC_A_CONTROL_BASE_IDX = 8 # macro +regL2_PTC_A_HASH_CONTROL = 0x1580019 # macro +regL2_PTC_A_HASH_CONTROL_BASE_IDX = 8 # macro +regL2_PTC_A_WAY_CONTROL = 0x158001a # macro +regL2_PTC_A_WAY_CONTROL_BASE_IDX = 8 # macro +regL2A_UPDATE_FILTER_CNTL = 0x1580022 # macro +regL2A_UPDATE_FILTER_CNTL_BASE_IDX = 8 # macro +regL2_ERR_RULE_CONTROL_3 = 0x1580030 # macro +regL2_ERR_RULE_CONTROL_3_BASE_IDX = 8 # macro +regL2_ERR_RULE_CONTROL_4 = 0x1580031 # macro +regL2_ERR_RULE_CONTROL_4_BASE_IDX = 8 # macro +regL2_ERR_RULE_CONTROL_5 = 0x1580032 # macro +regL2_ERR_RULE_CONTROL_5_BASE_IDX = 8 # macro +regL2_L2A_CK_GATE_CONTROL = 0x1580033 # macro +regL2_L2A_CK_GATE_CONTROL_BASE_IDX = 8 # macro +regL2_L2A_PGSIZE_CONTROL = 0x1580034 # macro +regL2_L2A_PGSIZE_CONTROL_BASE_IDX = 8 # macro +regL2_PWRGATE_CNTRL_REG_0 = 0x158003e # macro +regL2_PWRGATE_CNTRL_REG_0_BASE_IDX = 8 # macro +regL2_PWRGATE_CNTRL_REG_3 = 0x1580041 # macro +regL2_PWRGATE_CNTRL_REG_3_BASE_IDX = 8 # macro +regL2_ECO_CNTRL_0 = 0x1580042 # macro +regL2_ECO_CNTRL_0_BASE_IDX = 8 # macro +regL2_STATUS_1 = 0xf80448 # macro +regL2_STATUS_1_BASE_IDX = 8 # macro +regL2_SB_LOCATION = 0xf8044b # macro +regL2_SB_LOCATION_BASE_IDX = 8 # macro +regL2_CONTROL_5 = 0xf8044c # macro +regL2_CONTROL_5_BASE_IDX = 8 # macro +regL2_CONTROL_6 = 0xf8044f # macro +regL2_CONTROL_6_BASE_IDX = 8 # macro +regL2_PDC_CONTROL = 0xf80450 # macro +regL2_PDC_CONTROL_BASE_IDX = 8 # macro +regL2_PDC_HASH_CONTROL = 0xf80451 # macro +regL2_PDC_HASH_CONTROL_BASE_IDX = 8 # macro +regL2_PDC_WAY_CONTROL = 0xf80452 # macro +regL2_PDC_WAY_CONTROL_BASE_IDX = 8 # macro +regL2B_UPDATE_FILTER_CNTL = 0xf80453 # macro +regL2B_UPDATE_FILTER_CNTL_BASE_IDX = 8 # macro +regL2_TW_CONTROL = 0xf80454 # macro +regL2_TW_CONTROL_BASE_IDX = 8 # macro +regL2_CP_CONTROL = 0xf80456 # macro +regL2_CP_CONTROL_BASE_IDX = 8 # macro +regL2_CP_CONTROL_1 = 0xf80457 # macro +regL2_CP_CONTROL_1_BASE_IDX = 8 # macro +regL2_TW_CONTROL_1 = 0xf8045a # macro +regL2_TW_CONTROL_1_BASE_IDX = 8 # macro +regL2_TW_CONTROL_2 = 0xf80461 # macro +regL2_TW_CONTROL_2_BASE_IDX = 8 # macro +regL2_TW_CONTROL_3 = 0xf80462 # macro +regL2_TW_CONTROL_3_BASE_IDX = 8 # macro +regL2_CREDIT_CONTROL_0 = 0xf80470 # macro +regL2_CREDIT_CONTROL_0_BASE_IDX = 8 # macro +regL2_CREDIT_CONTROL_1 = 0xf80471 # macro +regL2_CREDIT_CONTROL_1_BASE_IDX = 8 # macro +regL2_ERR_RULE_CONTROL_0 = 0xf80480 # macro +regL2_ERR_RULE_CONTROL_0_BASE_IDX = 8 # macro +regL2_ERR_RULE_CONTROL_1 = 0xf80481 # macro +regL2_ERR_RULE_CONTROL_1_BASE_IDX = 8 # macro +regL2_ERR_RULE_CONTROL_2 = 0xf80482 # macro +regL2_ERR_RULE_CONTROL_2_BASE_IDX = 8 # macro +regL2_L2B_CK_GATE_CONTROL = 0xf80490 # macro +regL2_L2B_CK_GATE_CONTROL_BASE_IDX = 8 # macro +regPPR_CONTROL = 0xf80492 # macro +regPPR_CONTROL_BASE_IDX = 8 # macro +regL2_L2B_PGSIZE_CONTROL = 0xf80494 # macro +regL2_L2B_PGSIZE_CONTROL_BASE_IDX = 8 # macro +regL2_PERF_CNTL_2 = 0xf80499 # macro +regL2_PERF_CNTL_2_BASE_IDX = 8 # macro +regL2_PERF_COUNT_4 = 0xf8049a # macro +regL2_PERF_COUNT_4_BASE_IDX = 8 # macro +regL2_PERF_COUNT_5 = 0xf8049b # macro +regL2_PERF_COUNT_5_BASE_IDX = 8 # macro +regL2_PERF_CNTL_3 = 0xf8049c # macro +regL2_PERF_CNTL_3_BASE_IDX = 8 # macro +regL2_PERF_COUNT_6 = 0xf8049d # macro +regL2_PERF_COUNT_6_BASE_IDX = 8 # macro +regL2_PERF_COUNT_7 = 0xf8049e # macro +regL2_PERF_COUNT_7_BASE_IDX = 8 # macro +regL2B_SDP_PARITY_ERROR_EN = 0xf804a2 # macro +regL2B_SDP_PARITY_ERROR_EN_BASE_IDX = 8 # macro +regL2_ECO_CNTRL_1 = 0xf804a3 # macro +regL2_ECO_CNTRL_1_BASE_IDX = 8 # macro +regL2_CP_CONTROL_2 = 0xf804bf # macro +regL2_CP_CONTROL_2_BASE_IDX = 8 # macro +regL2_CP_CONTROL_3 = 0xf804c0 # macro +regL2_CP_CONTROL_3_BASE_IDX = 8 # macro +regFEATURES_ENABLE = 0x1080000 # macro +regFEATURES_ENABLE_BASE_IDX = 8 # macro +cfgBIF_CFG_DEV0_RC_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_RC_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_RC_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_RC_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_RC_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_RC_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_RC_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_RC_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_RC_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_RC_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_RC_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_RC_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_RC_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_RC_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY = 0x0018 # macro +cfgBIF_CFG_DEV0_RC_IO_BASE_LIMIT = 0x001c # macro +cfgBIF_CFG_DEV0_RC_SECONDARY_STATUS = 0x001e # macro +cfgBIF_CFG_DEV0_RC_MEM_BASE_LIMIT = 0x0020 # macro +cfgBIF_CFG_DEV0_RC_PREF_BASE_LIMIT = 0x0024 # macro +cfgBIF_CFG_DEV0_RC_PREF_BASE_UPPER = 0x0028 # macro +cfgBIF_CFG_DEV0_RC_PREF_LIMIT_UPPER = 0x002c # macro +cfgBIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI = 0x0030 # macro +cfgBIF_CFG_DEV0_RC_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_RC_ROM_BASE_ADDR = 0x0038 # macro +cfgBIF_CFG_DEV0_RC_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_RC_INTERRUPT_PIN = 0x003d # macro +cfgIRQ_BRIDGE_CNTL = 0x003e # macro +cfgBIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL = 0x0040 # macro +cfgBIF_CFG_DEV0_RC_PMI_CAP_LIST = 0x0050 # macro +cfgBIF_CFG_DEV0_RC_PMI_CAP = 0x0052 # macro +cfgBIF_CFG_DEV0_RC_PMI_STATUS_CNTL = 0x0054 # macro +cfgBIF_CFG_DEV0_RC_PCIE_CAP_LIST = 0x0058 # macro +cfgBIF_CFG_DEV0_RC_PCIE_CAP = 0x005a # macro +cfgBIF_CFG_DEV0_RC_DEVICE_CAP = 0x005c # macro +cfgBIF_CFG_DEV0_RC_DEVICE_CNTL = 0x0060 # macro +cfgBIF_CFG_DEV0_RC_DEVICE_STATUS = 0x0062 # macro +cfgBIF_CFG_DEV0_RC_LINK_CAP = 0x0064 # macro +cfgBIF_CFG_DEV0_RC_LINK_CNTL = 0x0068 # macro +cfgBIF_CFG_DEV0_RC_LINK_STATUS = 0x006a # macro +cfgBIF_CFG_DEV0_RC_SLOT_CAP = 0x006c # macro +cfgBIF_CFG_DEV0_RC_SLOT_CNTL = 0x0070 # macro +cfgBIF_CFG_DEV0_RC_SLOT_STATUS = 0x0072 # macro +cfgBIF_CFG_DEV0_RC_ROOT_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_RC_ROOT_CAP = 0x0076 # macro +cfgBIF_CFG_DEV0_RC_ROOT_STATUS = 0x0078 # macro +cfgBIF_CFG_DEV0_RC_DEVICE_CAP2 = 0x007c # macro +cfgBIF_CFG_DEV0_RC_DEVICE_CNTL2 = 0x0080 # macro +cfgBIF_CFG_DEV0_RC_DEVICE_STATUS2 = 0x0082 # macro +cfgBIF_CFG_DEV0_RC_LINK_CAP2 = 0x0084 # macro +cfgBIF_CFG_DEV0_RC_LINK_CNTL2 = 0x0088 # macro +cfgBIF_CFG_DEV0_RC_LINK_STATUS2 = 0x008a # macro +cfgBIF_CFG_DEV0_RC_SLOT_CAP2 = 0x008c # macro +cfgBIF_CFG_DEV0_RC_SLOT_CNTL2 = 0x0090 # macro +cfgBIF_CFG_DEV0_RC_SLOT_STATUS2 = 0x0092 # macro +cfgBIF_CFG_DEV0_RC_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_RC_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_RC_SSID_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_RC_SSID_CAP = 0x00c4 # macro +cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST = 0x0110 # macro +cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1 = 0x0114 # macro +cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2 = 0x0118 # macro +cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL = 0x011c # macro +cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS = 0x011e # macro +cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP = 0x0120 # macro +cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL = 0x0124 # macro +cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS = 0x012a # macro +cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP = 0x012c # macro +cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL = 0x0130 # macro +cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS = 0x0136 # macro +cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST = 0x0140 # macro +cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1 = 0x0144 # macro +cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2 = 0x0148 # macro +cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD = 0x017c # macro +cfgBIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS = 0x0180 # macro +cfgBIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID = 0x0184 # macro +cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST = 0x0270 # macro +cfgBIF_CFG_DEV0_RC_PCIE_LINK_CNTL3 = 0x0274 # macro +cfgBIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS = 0x0278 # macro +cfgBIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL = 0x027c # macro +cfgBIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL = 0x027e # macro +cfgBIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL = 0x0280 # macro +cfgBIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL = 0x0282 # macro +cfgBIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL = 0x0284 # macro +cfgBIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL = 0x0286 # macro +cfgBIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL = 0x0288 # macro +cfgBIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL = 0x028a # macro +cfgBIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL = 0x028c # macro +cfgBIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL = 0x028e # macro +cfgBIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL = 0x0290 # macro +cfgBIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL = 0x0292 # macro +cfgBIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL = 0x0294 # macro +cfgBIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL = 0x0296 # macro +cfgBIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL = 0x0298 # macro +cfgBIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL = 0x029a # macro +cfgBIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST = 0x02a0 # macro +cfgBIF_CFG_DEV0_RC_PCIE_ACS_CAP = 0x02a4 # macro +cfgBIF_CFG_DEV0_RC_PCIE_ACS_CNTL = 0x02a6 # macro +cfgBIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST = 0x0400 # macro +cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP = 0x0404 # macro +cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS = 0x0408 # macro +cfgBIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST = 0x0410 # macro +cfgBIF_CFG_DEV0_RC_LINK_CAP_16GT = 0x0414 # macro +cfgBIF_CFG_DEV0_RC_LINK_CNTL_16GT = 0x0418 # macro +cfgBIF_CFG_DEV0_RC_LINK_STATUS_16GT = 0x041c # macro +cfgBIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT = 0x0420 # macro +cfgBIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT = 0x0424 # macro +cfgBIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT = 0x0428 # macro +cfgBIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT = 0x0430 # macro +cfgBIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT = 0x0431 # macro +cfgBIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT = 0x0432 # macro +cfgBIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT = 0x0433 # macro +cfgBIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT = 0x0434 # macro +cfgBIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT = 0x0435 # macro +cfgBIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT = 0x0436 # macro +cfgBIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT = 0x0437 # macro +cfgBIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT = 0x0438 # macro +cfgBIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT = 0x0439 # macro +cfgBIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT = 0x043a # macro +cfgBIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT = 0x043b # macro +cfgBIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT = 0x043c # macro +cfgBIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT = 0x043d # macro +cfgBIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT = 0x043e # macro +cfgBIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT = 0x043f # macro +cfgBIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST = 0x0450 # macro +cfgBIF_CFG_DEV0_RC_MARGINING_PORT_CAP = 0x0454 # macro +cfgBIF_CFG_DEV0_RC_MARGINING_PORT_STATUS = 0x0456 # macro +cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL = 0x0458 # macro +cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS = 0x045a # macro +cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL = 0x045c # macro +cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS = 0x045e # macro +cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL = 0x0460 # macro +cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS = 0x0462 # macro +cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL = 0x0464 # macro +cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS = 0x0466 # macro +cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL = 0x0468 # macro +cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS = 0x046a # macro +cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL = 0x046c # macro +cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS = 0x046e # macro +cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL = 0x0470 # macro +cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS = 0x0472 # macro +cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL = 0x0474 # macro +cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS = 0x0476 # macro +cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL = 0x0478 # macro +cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS = 0x047a # macro +cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL = 0x047c # macro +cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS = 0x047e # macro +cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL = 0x0480 # macro +cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS = 0x0482 # macro +cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL = 0x0484 # macro +cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS = 0x0486 # macro +cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL = 0x0488 # macro +cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS = 0x048a # macro +cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL = 0x048c # macro +cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS = 0x048e # macro +cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL = 0x0490 # macro +cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS = 0x0492 # macro +cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL = 0x0494 # macro +cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS = 0x0496 # macro +cfgBIF_CFG_DEV0_RC_LINK_CAP_32GT = 0x0504 # macro +cfgBIF_CFG_DEV0_RC_LINK_CNTL_32GT = 0x0508 # macro +cfgBIF_CFG_DEV0_RC_LINK_STATUS_32GT = 0x050c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF0_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF0_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST = 0x02b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP = 0x02b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL = 0x02b6 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF1_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF1_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST = 0x02b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP = 0x02b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL = 0x02b6 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF2_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF2_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST = 0x02b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP = 0x02b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL = 0x02b6 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF3_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF3_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST = 0x02b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP = 0x02b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL = 0x02b6 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF4_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF4_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST = 0x02b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP = 0x02b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL = 0x02b6 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF5_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF5_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST = 0x02b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP = 0x02b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL = 0x02b6 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF6_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF6_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST = 0x02b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP = 0x02b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL = 0x02b6 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL = 0x032e # macro +cfgBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID = 0x0000 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID = 0x0002 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_COMMAND = 0x0004 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_STATUS = 0x0006 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_REVISION_ID = 0x0008 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE = 0x0009 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS = 0x000a # macro +cfgBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS = 0x000b # macro +cfgBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE = 0x000c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_LATENCY = 0x000d # macro +cfgBIF_CFG_DEV0_EPF0_VF7_HEADER = 0x000e # macro +cfgBIF_CFG_DEV0_EPF0_VF7_BIST = 0x000f # macro +cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 = 0x0010 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 = 0x0014 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 = 0x0018 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 = 0x001c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 = 0x0020 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 = 0x0024 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR = 0x0028 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID = 0x002c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR = 0x0030 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_CAP_PTR = 0x0034 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE = 0x003c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN = 0x003d # macro +cfgBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT = 0x003e # macro +cfgBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY = 0x003f # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST = 0x0064 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP = 0x0066 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP = 0x0068 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL = 0x006c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS = 0x006e # macro +cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP = 0x0070 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL = 0x0074 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS = 0x0076 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 = 0x0088 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 = 0x008c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 = 0x008e # macro +cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 = 0x0090 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 = 0x0094 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 = 0x0096 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST = 0x00a0 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL = 0x00a2 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO = 0x00a4 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA = 0x00a8 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA = 0x00aa # macro +cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 = 0x00ac # macro +cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 = 0x00ae # macro +cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING = 0x00b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 = 0x00b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST = 0x00c0 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL = 0x00c2 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE = 0x00c4 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA = 0x00c8 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST = 0x0100 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR = 0x0104 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 = 0x0108 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 = 0x010c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST = 0x0150 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS = 0x0154 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK = 0x0158 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY = 0x015c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS = 0x0160 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK = 0x0164 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL = 0x0168 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 = 0x016c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 = 0x0170 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 = 0x0174 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 = 0x0178 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 = 0x0188 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 = 0x018c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 = 0x0190 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 = 0x0194 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST = 0x02b0 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP = 0x02b4 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL = 0x02b6 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST = 0x0328 # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP = 0x032c # macro +cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL = 0x032e # macro +regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF0_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF0_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX = 4 # macro +regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF1_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF1_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX = 4 # macro +regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF2_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF2_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX = 4 # macro +regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF3_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF3_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX = 4 # macro +regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF4_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF4_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX = 4 # macro +regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF5_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF5_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX = 4 # macro +regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF6_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF6_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX = 4 # macro +regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS = 0x00eb # macro +regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG = 0x00ec # macro +regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH = 0x00f3 # macro +regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW = 0x00f4 # macro +regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL = 0x00f5 # macro +regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL = 0x00f6 # macro +regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL = 0x00f7 # macro +regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL = 0x00f9 # macro +regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL = 0x00fa # macro +regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ = 0x0106 # macro +regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE = 0x0107 # macro +regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING = 0x0108 # macro +regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS = 0x0112 # macro +regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 = 0x0136 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 = 0x0137 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 = 0x0138 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 = 0x0139 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 = 0x013a # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 = 0x013b # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 = 0x013c # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 = 0x013d # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL = 0x013e # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL = 0x013f # macro +regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX = 0x0140 # macro +regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX = 2 # macro +regBIF_BX_DEV0_EPF0_VF7_MM_INDEX = 0x0000 # macro +regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF7_MM_DATA = 0x0001 # macro +regBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX = 0 # macro +regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI = 0x0006 # macro +regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX = 0 # macro +regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG = 0x0085 # macro +regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN = 0x00c0 # macro +regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE = 0x00c3 # macro +regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED = 0x00c4 # macro +regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER = 0x00c5 # macro +regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX = 2 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO = 0x0400 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI = 0x0401 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA = 0x0402 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL = 0x0403 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO = 0x0404 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI = 0x0405 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA = 0x0406 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL = 0x0407 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO = 0x0408 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI = 0x0409 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA = 0x040a # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL = 0x040b # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO = 0x040c # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI = 0x040d # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA = 0x040e # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL = 0x040f # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_BASE_IDX = 4 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA = 0x0800 # macro +regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX = 4 # macro +_nbio_7_9_0_SH_MASK_HEADER = True # macro +BIF_BX0_PCIE_INDEX__PCIE_INDEX__SHIFT = 0x0 # macro +BIF_BX0_PCIE_INDEX__PCIE_INDEX_MASK = 0xFFFFFFFF # macro +BIF_BX0_PCIE_DATA__PCIE_DATA__SHIFT = 0x0 # macro +BIF_BX0_PCIE_DATA__PCIE_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX0_PCIE_INDEX2__PCIE_INDEX2__SHIFT = 0x0 # macro +BIF_BX0_PCIE_INDEX2__PCIE_INDEX2_MASK = 0xFFFFFFFF # macro +BIF_BX0_PCIE_DATA2__PCIE_DATA2__SHIFT = 0x0 # macro +BIF_BX0_PCIE_DATA2__PCIE_DATA2_MASK = 0xFFFFFFFF # macro +BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT = 0x0 # macro +BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK = 0x000000FF # macro +BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT = 0x0 # macro +BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK = 0x000000FF # macro +BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT = 0x0 # macro +BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK = 0xFFFFFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK = 0x000FFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK = 0x000000FF # macro +BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK = 0xFFFFFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK = 0xFFFFFFFF # macro +BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT = 0x0 # macro +BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK = 0xFFFFFFFF # macro +BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT = 0x0 # macro +BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14_MASK = 0xFFFFFFFF # macro +BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT = 0x0 # macro +BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK = 0xFFFFFFFF # macro +BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT = 0x0 # macro +BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK = 0xFFFFFFFF # macro +RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT = 0x0 # macro +RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT = 0x0 # macro +RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK = 0xFFFFFFFF # macro +RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT = 0x0 # macro +RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT = 0x7 # macro +RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT = 0x1e # macro +RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK = 0x00000001 # macro +RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK = 0x00000080 # macro +RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK = 0x40000000 # macro +RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT = 0x19 # macro +RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK = 0x06000000 # macro +RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT = 0x1c # macro +RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK = 0x70000000 # macro +RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT = 0x7 # macro +RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT = 0x8 # macro +RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK = 0x00000080 # macro +RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK = 0x00000100 # macro +RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT = 0x0 # macro +RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT = 0x1 # macro +RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT = 0x2 # macro +RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT = 0x3 # macro +RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT = 0x4 # macro +RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK = 0x00000001 # macro +RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK = 0x00000002 # macro +RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK = 0x00000004 # macro +RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK = 0x00000008 # macro +RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK = 0x00000010 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT = 0x0 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT = 0x11 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT = 0x15 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK = 0x00000001 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK = 0x00020000 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK = 0x00E00000 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT = 0x18 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT = 0x1d # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK = 0x01000000 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK = 0x20000000 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT = 0x2 # macro +RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK = 0x00000004 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT = 0x8 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT = 0xb # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT = 0x11 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT = 0x12 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT = 0x13 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT = 0x14 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK = 0x00000001 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK = 0x00000700 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK = 0x00000800 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK = 0x00020000 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK = 0x00040000 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK = 0x00080000 # macro +RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK = 0x00100000 # macro +RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0x8 # macro +RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT = 0x9 # macro +RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT = 0x14 # macro +RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT = 0x15 # macro +RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT = 0x1b # macro +RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00000100 # macro +RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK = 0x00000200 # macro +RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK = 0x00100000 # macro +RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK = 0x00200000 # macro +RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK = 0x08000000 # macro +RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT = 0x1 # macro +RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT = 0x2 # macro +RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT = 0x3 # macro +RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK = 0x00000001 # macro +RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK = 0x00000002 # macro +RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK = 0x00000004 # macro +RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK = 0x00000008 # macro +RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT = 0x1b # macro +RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK = 0x00000001 # macro +RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK = 0x08000000 # macro +RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT = 0xa # macro +RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK = 0x00000400 # macro +RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK = 0xFFFFFFFF # macro +RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK = 0xFFFFFFFF # macro +RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT = 0x7 # macro +RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT = 0x8 # macro +RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT = 0x1e # macro +RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK = 0x00000080 # macro +RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK = 0x00000100 # macro +RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK = 0x40000000 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT = 0x1 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT = 0x2 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT = 0x3 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT = 0x4 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT = 0x6 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK = 0x00000001 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK = 0x00000002 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK = 0x00000004 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK = 0x00000008 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK = 0x00000010 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK = 0x00000040 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT = 0x1 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT = 0x2 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT = 0x3 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT = 0x4 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT = 0x6 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT = 0x7 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK = 0x00000001 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK = 0x00000002 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK = 0x00000004 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK = 0x00000008 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK = 0x00000010 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK = 0x00000040 # macro +RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK = 0x00000080 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK = 0x00000001 # macro +RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT = 0x7 # macro +RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK = 0x00000080 # macro +RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT = 0x1 # macro +RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT = 0x2 # macro +RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT = 0x3 # macro +RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT = 0x4 # macro +RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK = 0x00000001 # macro +RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK = 0x00000002 # macro +RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK = 0x00000004 # macro +RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK = 0x00000008 # macro +RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK = 0x00000010 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT = 0x3 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT = 0x6 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT = 0x7 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT = 0xa # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT = 0xd # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT = 0xe # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT = 0xf # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT = 0x10 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT = 0x11 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK = 0x00000007 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK = 0x00000038 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK = 0x00000040 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK = 0x00000380 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK = 0x00001C00 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK = 0x00002000 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK = 0x00004000 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK = 0x00008000 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK = 0x00010000 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK = 0x00020000 # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT = 0x1d # macro +RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK = 0x20000000 # macro +RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT = 0x4 # macro +RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK = 0x00000010 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0xFF # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT = 0x8 # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK = 0x001F # macro +RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK = 0x0100 # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK = 0x1F # macro +RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT = 0xa # macro +RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT = 0xc # macro +RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT = 0x18 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT = 0x19 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT = 0x1a # macro +RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK = 0x00000C00 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK = 0x00003000 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK = 0x01000000 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK = 0x02000000 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK = 0x04000000 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT = 0x3 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT = 0x8 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK = 0x00000007 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK = 0x000000F8 # macro +RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK = 0x0000FF00 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT = 0x8 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT = 0x11 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT = 0x12 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT = 0x18 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT = 0x19 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT = 0x1a # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT = 0x1b # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT = 0x1c # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT = 0x1d # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT = 0x1e # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT = 0x1f # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK = 0x00000001 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK = 0x00000700 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK = 0x00020000 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK = 0x00040000 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK = 0x01000000 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK = 0x02000000 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK = 0x04000000 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK = 0x08000000 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK = 0x10000000 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK = 0x20000000 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK = 0x40000000 # macro +RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK = 0x80000000 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0x8 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT = 0x9 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT = 0x14 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT = 0x15 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT = 0x16 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT = 0x18 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT = 0x19 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT = 0x1a # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00000100 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK = 0x00000200 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK = 0x00100000 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK = 0x00200000 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK = 0x00400000 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK = 0x01000000 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK = 0x02000000 # macro +RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK = 0x04000000 # macro +RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT = 0x0 # macro +RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT = 0x1 # macro +RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT = 0x2 # macro +RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT = 0x3 # macro +RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK = 0x00000001 # macro +RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK = 0x00000002 # macro +RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK = 0x00000004 # macro +RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK = 0x00000008 # macro +BIF_BX_PF0_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_PF0_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_PF0_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_PF0_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_PF0_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_PF0_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX__SHIFT = 0x0 # macro +BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX_MASK = 0xFFFFFFFF # macro +BIF_BX_PF0_RSMU_DATA__RSMU_DATA__SHIFT = 0x0 # macro +BIF_BX_PF0_RSMU_DATA__RSMU_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF0_RSMU_INDEX_HI__RSMU_INDEX_HI__SHIFT = 0x0 # macro +BIF_BX_PF0_RSMU_INDEX_HI__RSMU_INDEX_HI_MASK = 0x000000FF # macro +BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT = 0x19 # macro +BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK = 0xFE000000 # macro +BIF_BX0_BIF_MM_INDACCESS_CNTL__WRITE_DIS__SHIFT = 0x0 # macro +BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT = 0x1 # macro +BIF_BX0_BIF_MM_INDACCESS_CNTL__WRITE_DIS_MASK = 0x00000001 # macro +BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK = 0x00000002 # macro +BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT = 0x6 # macro +BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT = 0x7 # macro +BIF_BX0_BUS_CNTL__SET_AZ_TC__SHIFT = 0xa # macro +BIF_BX0_BUS_CNTL__SET_MC_TC__SHIFT = 0xd # macro +BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN__SHIFT = 0x10 # macro +BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN__SHIFT = 0x11 # macro +BIF_BX0_BUS_CNTL__RD_STALL_IO_WR__SHIFT = 0x12 # macro +BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT = 0x18 # macro +BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT = 0x19 # macro +BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT = 0x1a # macro +BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT = 0x1b # macro +BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT = 0x1c # macro +BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT = 0x1d # macro +BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT = 0x1e # macro +BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT = 0x1f # macro +BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK = 0x00000040 # macro +BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK = 0x00000080 # macro +BIF_BX0_BUS_CNTL__SET_AZ_TC_MASK = 0x00001C00 # macro +BIF_BX0_BUS_CNTL__SET_MC_TC_MASK = 0x0000E000 # macro +BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN_MASK = 0x00010000 # macro +BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN_MASK = 0x00020000 # macro +BIF_BX0_BUS_CNTL__RD_STALL_IO_WR_MASK = 0x00040000 # macro +BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK = 0x01000000 # macro +BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK = 0x02000000 # macro +BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK = 0x04000000 # macro +BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK = 0x08000000 # macro +BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK = 0x10000000 # macro +BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK = 0x20000000 # macro +BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK = 0x40000000 # macro +BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK = 0x80000000 # macro +BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT = 0x0 # macro +BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT = 0x0 # macro +BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1_MASK = 0xFFFFFFFF # macro +BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT = 0x10 # macro +BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK = 0x00010000 # macro +BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT = 0x0 # macro +BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT = 0x6 # macro +BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT = 0x1f # macro +BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK = 0x00000007 # macro +BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK = 0x000000C0 # macro +BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK = 0x80000000 # macro +BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT = 0x0 # macro +BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN_MASK = 0x00000001 # macro +BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT = 0x0 # macro +BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT = 0x1 # macro +BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT = 0x3 # macro +BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT = 0x4 # macro +BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT = 0x8 # macro +BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT = 0xf # macro +BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT = 0x10 # macro +BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT = 0x11 # macro +BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT = 0x12 # macro +BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK = 0x00000001 # macro +BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK = 0x00000002 # macro +BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK = 0x00000008 # macro +BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK = 0x000000F0 # macro +BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK = 0x00000100 # macro +BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK = 0x00008000 # macro +BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK = 0x00010000 # macro +BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK = 0x00020000 # macro +BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK = 0x00040000 # macro +BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT = 0x0 # macro +BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK = 0xFFFFFFFF # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT = 0x0 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT = 0x1 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT = 0x2 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT = 0x3 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT = 0x5 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT = 0x6 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT = 0x7 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT = 0x8 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT = 0x9 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT = 0xa # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT = 0xb # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT = 0xc # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT = 0xd # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK = 0x00000001 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK = 0x00000002 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK = 0x00000004 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK = 0x00000018 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK = 0x00000020 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK = 0x00000040 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK = 0x00000080 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK = 0x00000100 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK = 0x00000200 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK = 0x00000400 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK = 0x00000800 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK = 0x00001000 # macro +BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK = 0x00002000 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT = 0x0 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT = 0x1 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT = 0x2 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT = 0x3 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT = 0xb # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT = 0xc # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT = 0xd # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS__SHIFT = 0xe # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT = 0xf # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT = 0x10 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT = 0x19 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK = 0x00000001 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK = 0x00000002 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK = 0x00000004 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK = 0x00000008 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK = 0x00000800 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK = 0x00001000 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK = 0x00002000 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS_MASK = 0x00004000 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK = 0x00008000 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK = 0x01FF0000 # macro +BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK = 0x02000000 # macro +BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT = 0x0 # macro +BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK = 0x000000FF # macro +BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT = 0x0 # macro +BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT = 0x1 # macro +BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT = 0x2 # macro +BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT = 0x3 # macro +BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT = 0x4 # macro +BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT = 0x18 # macro +BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT = 0x19 # macro +BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT = 0x1a # macro +BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT = 0x1b # macro +BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK = 0x00000001 # macro +BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK = 0x00000002 # macro +BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK = 0x00000004 # macro +BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK = 0x00000008 # macro +BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK = 0x00000010 # macro +BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK = 0x01000000 # macro +BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK = 0x02000000 # macro +BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK = 0x04000000 # macro +BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK = 0x08000000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT = 0x0 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT = 0x1 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT = 0x2 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT = 0x10 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT = 0x11 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT = 0x12 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT = 0x17 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT = 0x18 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT = 0x19 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT = 0x1a # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT = 0x1c # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT = 0x1d # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT = 0x1e # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT = 0x1f # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK = 0x00000001 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK = 0x00000002 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK = 0x00000004 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK = 0x00010000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK = 0x00020000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK = 0x00040000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK = 0x00800000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK = 0x01000000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK = 0x02000000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK = 0x04000000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK = 0x10000000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK = 0x20000000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK = 0x40000000 # macro +BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK = 0x80000000 # macro +BIF_BX0_BIF_FB_EN__FB_READ_EN__SHIFT = 0x0 # macro +BIF_BX0_BIF_FB_EN__FB_WRITE_EN__SHIFT = 0x1 # macro +BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK = 0x00000001 # macro +BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK = 0x00000002 # macro +BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT = 0x0 # macro +BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK = 0x00000001 # macro +BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK = 0x7FFFFFFF # macro +BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK = 0x7FFFFFFF # macro +BIF_BX0_BACO_CNTL__BACO_EN__SHIFT = 0x0 # macro +BIF_BX0_BACO_CNTL__BACO_DUMMY_EN__SHIFT = 0x2 # macro +BIF_BX0_BACO_CNTL__BACO_POWER_OFF__SHIFT = 0x3 # macro +BIF_BX0_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT = 0x5 # macro +BIF_BX0_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT = 0x6 # macro +BIF_BX0_BACO_CNTL__BACO_MODE__SHIFT = 0x8 # macro +BIF_BX0_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT = 0x9 # macro +BIF_BX0_BACO_CNTL__PWRGOOD_VDDSOC__SHIFT = 0x10 # macro +BIF_BX0_BACO_CNTL__BACO_AUTO_EXIT__SHIFT = 0x1f # macro +BIF_BX0_BACO_CNTL__BACO_EN_MASK = 0x00000001 # macro +BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK = 0x00000004 # macro +BIF_BX0_BACO_CNTL__BACO_POWER_OFF_MASK = 0x00000008 # macro +BIF_BX0_BACO_CNTL__BACO_DSTATE_BYPASS_MASK = 0x00000020 # macro +BIF_BX0_BACO_CNTL__BACO_RST_INTR_MASK_MASK = 0x00000040 # macro +BIF_BX0_BACO_CNTL__BACO_MODE_MASK = 0x00000100 # macro +BIF_BX0_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK = 0x00000200 # macro +BIF_BX0_BACO_CNTL__PWRGOOD_VDDSOC_MASK = 0x00010000 # macro +BIF_BX0_BACO_CNTL__BACO_AUTO_EXIT_MASK = 0x80000000 # macro +BIF_BX0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT = 0x0 # macro +BIF_BX0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK = 0x000FFFFF # macro +BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT = 0x0 # macro +BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT = 0x18 # macro +BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT = 0x1a # macro +BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT = 0x1b # macro +BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT = 0x1c # macro +BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT = 0x1d # macro +BIF_BX0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT = 0x1f # macro +BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK = 0x000FFFFF # macro +BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK = 0x01000000 # macro +BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK = 0x04000000 # macro +BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK = 0x08000000 # macro +BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK = 0x10000000 # macro +BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK = 0x60000000 # macro +BIF_BX0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK = 0x80000000 # macro +BIF_BX0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT = 0x0 # macro +BIF_BX0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK = 0x000FFFFF # macro +BIF_BX0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT = 0x0 # macro +BIF_BX0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK = 0x000FFFFF # macro +BIF_BX0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT = 0x0 # macro +BIF_BX0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK = 0x000FFFFF # macro +BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT = 0x0 # macro +BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK = 0x00000001 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT = 0x1 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT = 0x8 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK = 0x00000001 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK = 0x00000002 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK = 0x00000100 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT = 0x0 # macro +BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT = 0x2 # macro +BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK = 0x0007FFFC # macro +BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT = 0x2 # macro +BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK = 0x0007FFFC # macro +BIF_BX0_BIF_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +BIF_BX0_BIF_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT = 0x8 # macro +BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT = 0x9 # macro +BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT = 0x11 # macro +BIF_BX0_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL__SHIFT = 0x19 # macro +BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT = 0x1a # macro +BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT = 0x1d # macro +BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT = 0x1e # macro +BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT = 0x1f # macro +BIF_BX0_BIF_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +BIF_BX0_BIF_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK = 0x00000100 # macro +BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK = 0x00003E00 # macro +BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN_MASK = 0x00020000 # macro +BIF_BX0_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL_MASK = 0x02000000 # macro +BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK = 0x1C000000 # macro +BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK = 0x20000000 # macro +BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK = 0x40000000 # macro +BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK = 0x80000000 # macro +BIF_BX0_BIF_RB_BASE__ADDR__SHIFT = 0x0 # macro +BIF_BX0_BIF_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +BIF_BX0_BIF_RB_RPTR__OFFSET__SHIFT = 0x2 # macro +BIF_BX0_BIF_RB_RPTR__OFFSET_MASK = 0x0003FFFC # macro +BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT = 0x0 # macro +BIF_BX0_BIF_RB_WPTR__OFFSET__SHIFT = 0x2 # macro +BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK = 0x00000001 # macro +BIF_BX0_BIF_RB_WPTR__OFFSET_MASK = 0x0003FFFC # macro +BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR_MASK = 0x000000FF # macro +BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +BIF_BX0_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT = 0x0 # macro +BIF_BX0_MAILBOX_INDEX__MAILBOX_INDEX_MASK = 0x0000001F # macro +BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT = 0x0 # macro +BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK = 0x00000001 # macro +BIF_BX0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT = 0x0 # macro +BIF_BX0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK = 0x0000FFFF # macro +BIF_BX0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT = 0x0 # macro +BIF_BX0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK = 0x00000FFF # macro +BIF_BX0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT = 0x0 # macro +BIF_BX0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK = 0x000000FF # macro +BIF_BX0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT = 0x0 # macro +BIF_BX0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK = 0x7FFFFFFF # macro +BIF_BX0_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT = 0x0 # macro +BIF_BX0_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK = 0x000000FF # macro +RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT = 0x1 # macro +RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK = 0x00000002 # macro +RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT = 0xf # macro +RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN_MASK = 0x00008000 # macro +RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT = 0x1 # macro +RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT = 0x2 # macro +RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT = 0x3 # macro +RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT = 0x4 # macro +RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK = 0x00000002 # macro +RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK = 0x00000004 # macro +RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK = 0x00000008 # macro +RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK = 0x00000010 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT = 0x1 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT = 0x2 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT = 0x3 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT = 0x4 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT = 0x5 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT = 0xb # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT = 0x12 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT = 0x19 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK = 0x00000002 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK = 0x00000004 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK = 0x00000008 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK = 0x00000010 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK = 0x000007E0 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK = 0x0003F800 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK = 0x01FC0000 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK = 0xFE000000 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT = 0x6 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT = 0xc # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT = 0x11 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK = 0x0000003F # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK = 0x00000FC0 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK = 0x0001F000 # macro +RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK = 0x00FE0000 # macro +RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION__SHIFT = 0x4 # macro +RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION_MASK = 0x0000000F # macro +RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION_MASK = 0x000000F0 # macro +RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT = 0x1 # macro +RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK = 0x00000002 # macro +RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK = 0xFFFF # macro +RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK = 0xFFFF # macro +RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR_MASK = 0x0000FFFF # macro +RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR_MASK = 0xFFFF0000 # macro +RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR_MASK = 0x0000FFFF # macro +RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR_MASK = 0xFFFF0000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT = 0x2 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT = 0x3 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT = 0x4 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT = 0x5 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT = 0x6 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT = 0x7 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT = 0x8 # macro +RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT = 0xc # macro +RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT = 0xd # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT = 0x11 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT = 0x12 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT = 0x13 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT = 0x14 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT = 0x15 # macro +RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT = 0x18 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT = 0x19 # macro +RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT = 0x1c # macro +RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT = 0x1d # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_MASK = 0x00000004 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_MASK = 0x00000008 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS_MASK = 0x00000010 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK = 0x00000020 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK = 0x00000040 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK = 0x00000080 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK = 0x00000100 # macro +RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK = 0x00001000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK = 0x00002000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK = 0x00010000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK = 0x00020000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK = 0x00040000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK = 0x00080000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK = 0x00100000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK = 0x00200000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK = 0x01000000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK = 0x0E000000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK = 0x10000000 # macro +RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK = 0xE0000000 # macro +RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT = 0x2 # macro +RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT = 0x3 # macro +RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK = 0x00000004 # macro +RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK = 0x00000018 # macro +RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK = 0x07FFFFFF # macro +RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT = 0x1f # macro +RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK = 0x7FFFFFFF # macro +RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK = 0x80000000 # macro +RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK = 0x7FFFFFFF # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT = 0x7 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT = 0x8 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT = 0x9 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT = 0xa # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT = 0xb # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT = 0xc # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT = 0xd # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT = 0xe # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT = 0xf # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT = 0x11 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT = 0x12 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT = 0x13 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK = 0x00000080 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK = 0x00000100 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK = 0x00000200 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK = 0x00000400 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK = 0x00000800 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK = 0x00001000 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK = 0x00002000 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK = 0x00004000 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK = 0x00008000 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK = 0x00010000 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK = 0x00020000 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK = 0x00040000 # macro +RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK = 0x00080000 # macro +RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK_MASK = 0x000000FF # macro +RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1__SHIFT = 0x8 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3__SHIFT = 0x18 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0_MASK = 0x000000FF # macro +RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1_MASK = 0x0000FF00 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2_MASK = 0x00FF0000 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3_MASK = 0xFF000000 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5__SHIFT = 0x8 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7__SHIFT = 0x18 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4_MASK = 0x000000FF # macro +RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5_MASK = 0x0000FF00 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6_MASK = 0x00FF0000 # macro +RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7_MASK = 0xFF000000 # macro +RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT = 0x8 # macro +RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT = 0x11 # macro +RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK = 0x000000FF # macro +RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK = 0x00000100 # macro +RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK = 0x00010000 # macro +RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK = 0x00020000 # macro +RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID_MASK = 0x0000FFFF # macro +RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK = 0x000FFFFF # macro +RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT = 0x1f # macro +RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK = 0x000FFFFF # macro +RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK = 0x80000000 # macro +RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK = 0x000FFFFF # macro +RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT = 0x1f # macro +RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK = 0x000FFFFF # macro +RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK = 0x80000000 # macro +RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK = 0x000FFFFF # macro +RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT = 0x1f # macro +RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK = 0x000FFFFF # macro +RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK = 0x80000000 # macro +RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK = 0x000FFFFF # macro +RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT = 0x1f # macro +RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK = 0x000FFFFF # macro +RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK = 0x80000000 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT = 0x8 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT = 0x18 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK = 0x000000FF # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK = 0x0000FF00 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK = 0x00FF0000 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK = 0xFF000000 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT = 0x8 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT = 0x18 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK = 0x000000FF # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK = 0x0000FF00 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK = 0x00FF0000 # macro +RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK = 0xFF000000 # macro +RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT = 0x8 # macro +RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT = 0x11 # macro +RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK = 0x00000100 # macro +RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK = 0x00010000 # macro +RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK = 0x00020000 # macro +RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT = 0x1 # macro +RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT = 0x2 # macro +RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT = 0x3 # macro +RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT = 0x10 # macro +RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK = 0x00000002 # macro +RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK = 0x00000004 # macro +RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK = 0x00000008 # macro +RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK = 0xFFFF0000 # macro +RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT = 0x8 # macro +RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK = 0x000000FF # macro +RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK = 0x00001F00 # macro +RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK = 0x000003FF # macro +RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT = 0x0 # macro +RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT = 0x1 # macro +RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK = 0x00000001 # macro +RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK = 0x00007FFE # macro +RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT = 0x3 # macro +RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK = 0x00000004 # macro +RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK = 0x00000008 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT = 0x1 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT = 0x2 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT = 0x3 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT = 0x6 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT = 0x7 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT = 0x9 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT = 0xa # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT = 0xb # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT = 0xc # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT = 0xd # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0xe # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT = 0xf # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT = 0x11 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT = 0x19 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT = 0x1a # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT = 0x1b # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK = 0x00000001 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK = 0x00000002 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK = 0x00000004 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK = 0x00000038 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK = 0x00000040 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK = 0x00000080 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK = 0x00000100 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK = 0x00000200 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK = 0x00000400 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK = 0x00000800 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK = 0x00001000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK = 0x00002000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00004000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK = 0x00008000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK = 0x00010000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK = 0x00020000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK = 0x000C0000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK = 0x01000000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK = 0x02000000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK = 0x04000000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK = 0x08000000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK = 0x10000000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT = 0x1 # macro +RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT = 0x2 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT = 0x3 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT = 0x5 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT = 0x6 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT = 0x7 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT = 0x9 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT = 0xa # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT = 0xc # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT = 0xd # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT = 0xf # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT = 0x11 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT = 0x13 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT = 0x16 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT = 0x17 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT = 0x19 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT = 0x1a # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT = 0x1b # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK = 0x00000001 # macro +RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK = 0x00000002 # macro +RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE_MASK = 0x00000004 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK = 0x00000008 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK = 0x00000020 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK = 0x00000040 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK = 0x00000080 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK = 0x00000100 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK = 0x00000200 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK = 0x00000C00 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK = 0x00001000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK = 0x00006000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK = 0x00018000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK = 0x00020000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK = 0x00040000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK = 0x00080000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK = 0x00200000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK = 0x00400000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK = 0x00800000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK = 0x01000000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK = 0x02000000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK = 0x04000000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK = 0x18000000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT = 0x3 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT = 0x4 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT = 0x5 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT = 0x6 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN__SHIFT = 0x7 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT = 0x9 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT = 0xa # macro +RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT = 0xd # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT = 0xe # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT = 0xf # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK = 0x00000001 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK = 0x00000008 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK = 0x00000010 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK = 0x00000020 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK = 0x00000040 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN_MASK = 0x00000080 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK = 0x00000100 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK = 0x00000200 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK = 0x00000C00 # macro +RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK = 0x00002000 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK = 0x00004000 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK = 0x00008000 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK = 0x00FF0000 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK = 0x01000000 # macro +RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK = 0xFFFF0000 # macro +RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK = 0xFFFF0000 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT = 0x11 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT = 0x13 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT = 0x16 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x19 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1b # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK = 0x00010000 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK = 0x00020000 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK = 0x00040000 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK = 0x00080000 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK = 0x00200000 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK = 0x00C00000 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK = 0x01000000 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x06000000 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x08000000 # macro +RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK = 0x70000000 # macro +RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT = 0x1 # macro +RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT = 0x2 # macro +RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK = 0x00000001 # macro +RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK = 0x00000002 # macro +RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK = 0x00000004 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT = 0x11 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT = 0x13 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT = 0x19 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK = 0x00010000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK = 0x00020000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK = 0x00040000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK = 0x00080000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK = 0x00E00000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK = 0x01000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK = 0x0E000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK = 0x70000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK = 0xFFFF0000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT = 0x2 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT = 0x3 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT = 0x4 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT = 0x5 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT = 0x6 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK = 0x00000001 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK = 0x00000004 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK = 0x00000008 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK = 0x00000010 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK = 0x00000020 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK = 0x0007FFC0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK = 0x0FFF0000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK = 0x10000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK = 0x00FFFFFF # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT = 0x9 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK = 0x000000FF # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK = 0x00000100 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK = 0x000FFE00 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK = 0xFFF00000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT = 0x2 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT = 0x3 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT = 0x4 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK = 0x00000001 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK = 0x00000004 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK = 0x00000008 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK = 0x00000010 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT = 0x2 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT = 0x3 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT = 0x4 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT = 0x5 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT = 0x6 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT = 0x7 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT = 0x9 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT = 0xc # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT = 0xd # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT = 0xe # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT = 0xf # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT = 0x11 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT = 0x17 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT = 0x1a # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK = 0x00000001 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK = 0x00000004 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK = 0x00000008 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK = 0x00000010 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK = 0x00000020 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK = 0x00000040 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK = 0x00000080 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK = 0x00000100 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK = 0x00000E00 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK = 0x00001000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK = 0x00002000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK = 0x00004000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK = 0x00008000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK = 0x00010000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK = 0x00020000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK = 0x00700000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK = 0x03800000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK = 0x1C000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK = 0xE0000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT = 0x2 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT = 0x3 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT = 0x6 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT = 0x7 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT = 0x9 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT = 0xb # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT = 0xe # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT = 0x19 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT = 0x1b # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK = 0x00000001 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK = 0x00000004 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK = 0x00000038 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK = 0x00000040 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK = 0x00000080 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK = 0x00000100 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK = 0x00000600 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK = 0x00003800 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK = 0x0003C000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK = 0x001C0000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK = 0x01E00000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK = 0x06000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK = 0x18000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK = 0x000000FF # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK = 0x00FF0000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK = 0xFF000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT = 0x11 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT = 0x13 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT = 0x16 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT = 0x17 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT = 0x19 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT = 0x1a # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT = 0x1b # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK = 0x000000FF # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK = 0x00010000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK = 0x00020000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK = 0x00040000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK = 0x00080000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK = 0x00200000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK = 0x00400000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK = 0x00800000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK = 0x01000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK = 0x02000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK = 0x04000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK = 0x08000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK = 0x10000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT = 0x1 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT = 0x2 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT = 0x3 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT = 0x4 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT = 0x5 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT = 0x6 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT = 0x7 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT = 0xc # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT = 0x13 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK = 0x00000001 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK = 0x00000002 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK = 0x00000004 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK = 0x00000008 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK = 0x00000010 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK = 0x00000020 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK = 0x00000040 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK = 0x00000080 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK = 0x00000F00 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK = 0x0000F000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK = 0x00030000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK = 0x00040000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK = 0x00080000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK = 0x00E00000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK = 0x0F000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK = 0xF0000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT = 0xc # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK = 0x000000FF # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK = 0x00000F00 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK = 0x0000F000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK = 0x00FF0000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK = 0x1F000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK = 0xE0000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK = 0x000000FF # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK = 0x00FF0000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK = 0xFF000000 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK = 0x000000FF # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK = 0xFFFF0000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK = 0x000F0000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK = 0x00F00000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK = 0x0F000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK = 0x10000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK = 0xFFFF0000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK = 0x000000FF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK = 0x0000FF00 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK = 0x00FF0000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK = 0xFF000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT = 0xc # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT = 0x19 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK = 0x00FFF000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK = 0x01000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK = 0x3E000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT = 0xc # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK = 0x00FFF000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT = 0xc # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT = 0xd # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK = 0x00001000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK = 0x01FFE000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT = 0x6 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT = 0x7 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT = 0x9 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT = 0xe # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT = 0xf # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT = 0x11 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT = 0x16 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT = 0x17 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT = 0x1b # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK = 0x00000001 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK = 0x00000040 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK = 0x00000080 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK = 0x00000100 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK = 0x00003E00 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK = 0x00004000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK = 0x00008000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK = 0x00010000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK = 0x00020000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK = 0x00040000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK = 0x00200000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK = 0x00400000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK = 0x00800000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK = 0x07000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK = 0x08000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK = 0x10000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT = 0x11 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT = 0x13 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT = 0x1a # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT = 0x1b # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK = 0x00010000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK = 0x00020000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK = 0x00040000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK = 0x00080000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK = 0x00E00000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK = 0x01000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK = 0x04000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK = 0x08000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK = 0x10000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT = 0xa # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT = 0x16 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT = 0x17 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK = 0x000003FF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK = 0x00000400 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK = 0x00200000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK = 0x00400000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK = 0x0F800000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK = 0x70000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT = 0x3 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT = 0x4 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT = 0x7 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT = 0x9 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT = 0xd # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT = 0x13 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT = 0x17 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT = 0x1a # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT = 0x1b # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK = 0x00000007 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK = 0x00000008 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK = 0x00000070 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK = 0x00000080 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK = 0x00000100 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK = 0x00001E00 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK = 0x0000E000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK = 0x00070000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK = 0x00780000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK = 0x03800000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK = 0x04000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK = 0x38000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK = 0xC0000000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT = 0x13 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT = 0x16 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK = 0x00040000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK = 0x00080000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK = 0x00200000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK = 0x00C00000 # macro +RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK = 0x0F000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK = 0x000F0000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK = 0x00F00000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK = 0x10000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT = 0x7 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT = 0x8 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT = 0x9 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT = 0xe # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT = 0x11 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT = 0x17 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK = 0x00000080 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK = 0x00000100 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK = 0x00003E00 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK = 0x00004000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK = 0x00010000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK = 0x00020000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK = 0x00200000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK = 0x00800000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK = 0x07000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK = 0x10000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT = 0x10 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT = 0x11 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT = 0x12 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT = 0x13 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT = 0x18 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT = 0x1a # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT = 0x1b # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT = 0x1d # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK = 0x00010000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK = 0x00020000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK = 0x00040000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK = 0x00080000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK = 0x01000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK = 0x04000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK = 0x08000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK = 0x20000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT = 0x15 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT = 0x16 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT = 0x17 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT = 0x1c # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT = 0x1f # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK = 0x00100000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK = 0x00200000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK = 0x00400000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK = 0x0F800000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK = 0x70000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK = 0x80000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT = 0x1b # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK = 0x38000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT = 0x0 # macro +RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK = 0x00000001 # macro +BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_PF0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT = 0x0 # macro +BIF_BX_PF0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT = 0x1 # macro +BIF_BX_PF0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT = 0x2 # macro +BIF_BX_PF0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT = 0x3 # macro +BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT = 0x4 # macro +BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT = 0xa # macro +BIF_BX_PF0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK = 0x00000001 # macro +BIF_BX_PF0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK = 0x00000002 # macro +BIF_BX_PF0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK = 0x00000004 # macro +BIF_BX_PF0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK = 0x00000008 # macro +BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK = 0x00000010 # macro +BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK = 0x0003FC00 # macro +BIF_BX_PF0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT = 0x0 # macro +BIF_BX_PF0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT = 0x1 # macro +BIF_BX_PF0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT = 0x2 # macro +BIF_BX_PF0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT = 0x3 # macro +BIF_BX_PF0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT = 0x5 # macro +BIF_BX_PF0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT = 0x7 # macro +BIF_BX_PF0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK = 0x00000001 # macro +BIF_BX_PF0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK = 0x00000002 # macro +BIF_BX_PF0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK = 0x00000004 # macro +BIF_BX_PF0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK = 0x00000008 # macro +BIF_BX_PF0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK = 0x00000020 # macro +BIF_BX_PF0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK = 0x00000080 # macro +BIF_BX_PF0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT = 0x4 # macro +BIF_BX_PF0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK = 0x000000F0 # macro +BIF_BX_PF0_PARTITION_MEM_STATUS__CHANGE_STATUE__SHIFT = 0x0 # macro +BIF_BX_PF0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT = 0x4 # macro +BIF_BX_PF0_PARTITION_MEM_STATUS__CHANGE_STATUE_MASK = 0x0000000F # macro +BIF_BX_PF0_PARTITION_MEM_STATUS__NPS_MODE_MASK = 0x00000FF0 # macro +RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +GDC0_A2S_CNTL_CL0__NSNOOP_MAP__SHIFT = 0x0 # macro +GDC0_A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT = 0x2 # macro +GDC0_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT = 0x4 # macro +GDC0_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT = 0x6 # macro +GDC0_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT = 0x8 # macro +GDC0_A2S_CNTL_CL0__BLKLVL_MAP__SHIFT = 0xa # macro +GDC0_A2S_CNTL_CL0__DATERR_MAP__SHIFT = 0xc # macro +GDC0_A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT = 0xe # macro +GDC0_A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT = 0x10 # macro +GDC0_A2S_CNTL_CL0__RESP_WR_MAP__SHIFT = 0x12 # macro +GDC0_A2S_CNTL_CL0__RESP_RD_MAP__SHIFT = 0x14 # macro +GDC0_A2S_CNTL_CL0__RDRSP_ERRMAP__SHIFT = 0x16 # macro +GDC0_A2S_CNTL_CL0__RDRSP_SEL_MODE__SHIFT = 0x18 # macro +GDC0_A2S_CNTL_CL0__STATIC_VC_ENABLE__SHIFT = 0x1b # macro +GDC0_A2S_CNTL_CL0__STATIC_VC_VALUE__SHIFT = 0x1c # macro +GDC0_A2S_CNTL_CL0__NSNOOP_MAP_MASK = 0x00000003 # macro +GDC0_A2S_CNTL_CL0__REQPASSPW_VC0_MAP_MASK = 0x0000000C # macro +GDC0_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP_MASK = 0x00000030 # macro +GDC0_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP_MASK = 0x000000C0 # macro +GDC0_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP_MASK = 0x00000300 # macro +GDC0_A2S_CNTL_CL0__BLKLVL_MAP_MASK = 0x00000C00 # macro +GDC0_A2S_CNTL_CL0__DATERR_MAP_MASK = 0x00003000 # macro +GDC0_A2S_CNTL_CL0__EXOKAY_WR_MAP_MASK = 0x0000C000 # macro +GDC0_A2S_CNTL_CL0__EXOKAY_RD_MAP_MASK = 0x00030000 # macro +GDC0_A2S_CNTL_CL0__RESP_WR_MAP_MASK = 0x000C0000 # macro +GDC0_A2S_CNTL_CL0__RESP_RD_MAP_MASK = 0x00300000 # macro +GDC0_A2S_CNTL_CL0__RDRSP_ERRMAP_MASK = 0x00C00000 # macro +GDC0_A2S_CNTL_CL0__RDRSP_SEL_MODE_MASK = 0x07000000 # macro +GDC0_A2S_CNTL_CL0__STATIC_VC_ENABLE_MASK = 0x08000000 # macro +GDC0_A2S_CNTL_CL0__STATIC_VC_VALUE_MASK = 0x70000000 # macro +GDC0_A2S_CNTL_CL1__NSNOOP_MAP__SHIFT = 0x0 # macro +GDC0_A2S_CNTL_CL1__REQPASSPW_VC0_MAP__SHIFT = 0x2 # macro +GDC0_A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__SHIFT = 0x4 # macro +GDC0_A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__SHIFT = 0x6 # macro +GDC0_A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__SHIFT = 0x8 # macro +GDC0_A2S_CNTL_CL1__BLKLVL_MAP__SHIFT = 0xa # macro +GDC0_A2S_CNTL_CL1__DATERR_MAP__SHIFT = 0xc # macro +GDC0_A2S_CNTL_CL1__EXOKAY_WR_MAP__SHIFT = 0xe # macro +GDC0_A2S_CNTL_CL1__EXOKAY_RD_MAP__SHIFT = 0x10 # macro +GDC0_A2S_CNTL_CL1__RESP_WR_MAP__SHIFT = 0x12 # macro +GDC0_A2S_CNTL_CL1__RESP_RD_MAP__SHIFT = 0x14 # macro +GDC0_A2S_CNTL_CL1__RDRSP_ERRMAP__SHIFT = 0x16 # macro +GDC0_A2S_CNTL_CL1__RDRSP_SEL_MODE__SHIFT = 0x18 # macro +GDC0_A2S_CNTL_CL1__STATIC_VC_ENABLE__SHIFT = 0x1b # macro +GDC0_A2S_CNTL_CL1__STATIC_VC_VALUE__SHIFT = 0x1c # macro +GDC0_A2S_CNTL_CL1__NSNOOP_MAP_MASK = 0x00000003 # macro +GDC0_A2S_CNTL_CL1__REQPASSPW_VC0_MAP_MASK = 0x0000000C # macro +GDC0_A2S_CNTL_CL1__REQPASSPW_NVC0_MAP_MASK = 0x00000030 # macro +GDC0_A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP_MASK = 0x000000C0 # macro +GDC0_A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP_MASK = 0x00000300 # macro +GDC0_A2S_CNTL_CL1__BLKLVL_MAP_MASK = 0x00000C00 # macro +GDC0_A2S_CNTL_CL1__DATERR_MAP_MASK = 0x00003000 # macro +GDC0_A2S_CNTL_CL1__EXOKAY_WR_MAP_MASK = 0x0000C000 # macro +GDC0_A2S_CNTL_CL1__EXOKAY_RD_MAP_MASK = 0x00030000 # macro +GDC0_A2S_CNTL_CL1__RESP_WR_MAP_MASK = 0x000C0000 # macro +GDC0_A2S_CNTL_CL1__RESP_RD_MAP_MASK = 0x00300000 # macro +GDC0_A2S_CNTL_CL1__RDRSP_ERRMAP_MASK = 0x00C00000 # macro +GDC0_A2S_CNTL_CL1__RDRSP_SEL_MODE_MASK = 0x07000000 # macro +GDC0_A2S_CNTL_CL1__STATIC_VC_ENABLE_MASK = 0x08000000 # macro +GDC0_A2S_CNTL_CL1__STATIC_VC_VALUE_MASK = 0x70000000 # macro +GDC0_A2S_CNTL3_CL0__FORCE_WR_PH__SHIFT = 0x0 # macro +GDC0_A2S_CNTL3_CL0__FORCE_WR_STEERING__SHIFT = 0x2 # macro +GDC0_A2S_CNTL3_CL0__WR_ST_TAG_MODE__SHIFT = 0x3 # macro +GDC0_A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY__SHIFT = 0x4 # macro +GDC0_A2S_CNTL3_CL0__FORCE_WR_PH_MASK = 0x00000003 # macro +GDC0_A2S_CNTL3_CL0__FORCE_WR_STEERING_MASK = 0x00000004 # macro +GDC0_A2S_CNTL3_CL0__WR_ST_TAG_MODE_MASK = 0x00000008 # macro +GDC0_A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY_MASK = 0x000003F0 # macro +GDC0_A2S_CNTL3_CL1__FORCE_WR_PH__SHIFT = 0x0 # macro +GDC0_A2S_CNTL3_CL1__FORCE_WR_STEERING__SHIFT = 0x2 # macro +GDC0_A2S_CNTL3_CL1__WR_ST_TAG_MODE__SHIFT = 0x3 # macro +GDC0_A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY__SHIFT = 0x4 # macro +GDC0_A2S_CNTL3_CL1__FORCE_WR_PH_MASK = 0x00000003 # macro +GDC0_A2S_CNTL3_CL1__FORCE_WR_STEERING_MASK = 0x00000004 # macro +GDC0_A2S_CNTL3_CL1__WR_ST_TAG_MODE_MASK = 0x00000008 # macro +GDC0_A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY_MASK = 0x000003F0 # macro +GDC0_A2S_CNTL_SW0__STATIC_VC_ENABLE__SHIFT = 0x0 # macro +GDC0_A2S_CNTL_SW0__STATIC_VC_VALUE__SHIFT = 0x1 # macro +GDC0_A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__SHIFT = 0x6 # macro +GDC0_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT = 0x9 # macro +GDC0_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE__SHIFT = 0xa # macro +GDC0_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT = 0xb # macro +GDC0_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT = 0xc # macro +GDC0_A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT = 0x10 # macro +GDC0_A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT = 0x18 # macro +GDC0_A2S_CNTL_SW0__STATIC_VC_ENABLE_MASK = 0x00000001 # macro +GDC0_A2S_CNTL_SW0__STATIC_VC_VALUE_MASK = 0x0000000E # macro +GDC0_A2S_CNTL_SW0__FORCE_RSP_REORDER_EN_MASK = 0x00000040 # macro +GDC0_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK = 0x00000200 # macro +GDC0_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE_MASK = 0x00000400 # macro +GDC0_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE_MASK = 0x00000800 # macro +GDC0_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK = 0x00001000 # macro +GDC0_A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK = 0x00FF0000 # macro +GDC0_A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK = 0xFF000000 # macro +GDC0_A2S_CNTL_SW1__STATIC_VC_ENABLE__SHIFT = 0x0 # macro +GDC0_A2S_CNTL_SW1__STATIC_VC_VALUE__SHIFT = 0x1 # macro +GDC0_A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__SHIFT = 0x6 # macro +GDC0_A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT = 0x9 # macro +GDC0_A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE__SHIFT = 0xa # macro +GDC0_A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT = 0xb # macro +GDC0_A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT = 0xc # macro +GDC0_A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT = 0x10 # macro +GDC0_A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT = 0x18 # macro +GDC0_A2S_CNTL_SW1__STATIC_VC_ENABLE_MASK = 0x00000001 # macro +GDC0_A2S_CNTL_SW1__STATIC_VC_VALUE_MASK = 0x0000000E # macro +GDC0_A2S_CNTL_SW1__FORCE_RSP_REORDER_EN_MASK = 0x00000040 # macro +GDC0_A2S_CNTL_SW1__SDP_WR_CHAIN_DIS_MASK = 0x00000200 # macro +GDC0_A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE_MASK = 0x00000400 # macro +GDC0_A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE_MASK = 0x00000800 # macro +GDC0_A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK = 0x00001000 # macro +GDC0_A2S_CNTL_SW1__WRR_RD_WEIGHT_MASK = 0x00FF0000 # macro +GDC0_A2S_CNTL_SW1__WRR_WR_WEIGHT_MASK = 0xFF000000 # macro +GDC0_A2S_CNTL_SW2__STATIC_VC_ENABLE__SHIFT = 0x0 # macro +GDC0_A2S_CNTL_SW2__STATIC_VC_VALUE__SHIFT = 0x1 # macro +GDC0_A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__SHIFT = 0x6 # macro +GDC0_A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__SHIFT = 0x9 # macro +GDC0_A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE__SHIFT = 0xa # macro +GDC0_A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT = 0xb # macro +GDC0_A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT = 0xc # macro +GDC0_A2S_CNTL_SW2__WRR_RD_WEIGHT__SHIFT = 0x10 # macro +GDC0_A2S_CNTL_SW2__WRR_WR_WEIGHT__SHIFT = 0x18 # macro +GDC0_A2S_CNTL_SW2__STATIC_VC_ENABLE_MASK = 0x00000001 # macro +GDC0_A2S_CNTL_SW2__STATIC_VC_VALUE_MASK = 0x0000000E # macro +GDC0_A2S_CNTL_SW2__FORCE_RSP_REORDER_EN_MASK = 0x00000040 # macro +GDC0_A2S_CNTL_SW2__SDP_WR_CHAIN_DIS_MASK = 0x00000200 # macro +GDC0_A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE_MASK = 0x00000400 # macro +GDC0_A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE_MASK = 0x00000800 # macro +GDC0_A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK = 0x00001000 # macro +GDC0_A2S_CNTL_SW2__WRR_RD_WEIGHT_MASK = 0x00FF0000 # macro +GDC0_A2S_CNTL_SW2__WRR_WR_WEIGHT_MASK = 0xFF000000 # macro +GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT = 0x0 # macro +GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT = 0x8 # macro +GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT = 0x10 # macro +GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK = 0x000000FF # macro +GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK = 0x0000FF00 # macro +GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK = 0x00FF0000 # macro +GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT = 0x0 # macro +GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT = 0x10 # macro +GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT = 0x18 # macro +GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK = 0x000000FF # macro +GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK = 0x00FF0000 # macro +GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK = 0xFF000000 # macro +GDC0_A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT = 0x0 # macro +GDC0_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT = 0x2 # macro +GDC0_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE__SHIFT = 0x3 # macro +GDC0_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN__SHIFT = 0x4 # macro +GDC0_A2S_MISC_CNTL__RSP_REORDER_DIS__SHIFT = 0x5 # macro +GDC0_A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT = 0x6 # macro +GDC0_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT = 0x7 # macro +GDC0_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT = 0x8 # macro +GDC0_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY__SHIFT = 0x9 # macro +GDC0_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT = 0xa # macro +GDC0_A2S_MISC_CNTL__WR_TAG_SET_MIN__SHIFT = 0x10 # macro +GDC0_A2S_MISC_CNTL__RD_TAG_SET_MIN__SHIFT = 0x15 # macro +GDC0_A2S_MISC_CNTL__WRR_LRG_MODE__SHIFT = 0x1a # macro +GDC0_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE__SHIFT = 0x1b # macro +GDC0_A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK = 0x00000003 # macro +GDC0_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS_MASK = 0x00000004 # macro +GDC0_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE_MASK = 0x00000008 # macro +GDC0_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN_MASK = 0x00000010 # macro +GDC0_A2S_MISC_CNTL__RSP_REORDER_DIS_MASK = 0x00000020 # macro +GDC0_A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK = 0x00000040 # macro +GDC0_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS_MASK = 0x00000080 # macro +GDC0_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS_MASK = 0x00000100 # macro +GDC0_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY_MASK = 0x00000200 # macro +GDC0_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK = 0x00000400 # macro +GDC0_A2S_MISC_CNTL__WR_TAG_SET_MIN_MASK = 0x001F0000 # macro +GDC0_A2S_MISC_CNTL__RD_TAG_SET_MIN_MASK = 0x03E00000 # macro +GDC0_A2S_MISC_CNTL__WRR_LRG_MODE_MASK = 0x04000000 # macro +GDC0_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE_MASK = 0x08000000 # macro +GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT = 0x0 # macro +GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS__SHIFT = 0x1 # macro +GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK = 0x00000001 # macro +GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS_MASK = 0x00000002 # macro +GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT = 0x0 # macro +GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT = 0x1 # macro +GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT = 0x2 # macro +GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT = 0xa # macro +GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT = 0xb # macro +GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT = 0xc # macro +GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT = 0xd # macro +GDC0_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN__SHIFT = 0xe # macro +GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK = 0x00000001 # macro +GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK = 0x00000002 # macro +GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK = 0x000003FC # macro +GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK = 0x00000400 # macro +GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK = 0x00000800 # macro +GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK = 0x00001000 # macro +GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK = 0x00002000 # macro +GDC0_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN_MASK = 0x00004000 # macro +GDC0_NGDC_RESERVED_0__RESERVED__SHIFT = 0x0 # macro +GDC0_NGDC_RESERVED_0__RESERVED_MASK = 0xFFFFFFFF # macro +GDC0_NGDC_RESERVED_1__RESERVED__SHIFT = 0x0 # macro +GDC0_NGDC_RESERVED_1__RESERVED_MASK = 0xFFFFFFFF # macro +GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT = 0x0 # macro +GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK = 0x0000FFFF # macro +GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT = 0x0 # macro +GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT = 0x1 # macro +GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT = 0x2 # macro +GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT = 0x8 # macro +GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT = 0x10 # macro +GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT = 0x18 # macro +GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK = 0x00000001 # macro +GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK = 0x00000002 # macro +GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK = 0x0000000C # macro +GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK = 0x0000FF00 # macro +GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK = 0x00FF0000 # macro +GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK = 0xFF000000 # macro +GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT = 0x3 # macro +GDC0_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT = 0x8 # macro +GDC0_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT = 0xa # macro +GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT = 0xc # macro +GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT = 0xf # macro +GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT = 0x10 # macro +GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK = 0x00000008 # macro +GDC0_S2A_MISC_CNTL__ATM_ARB_MODE_MASK = 0x00000300 # macro +GDC0_S2A_MISC_CNTL__RB_ARB_MODE_MASK = 0x00000C00 # macro +GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK = 0x00003000 # macro +GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK = 0x00008000 # macro +GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK = 0x000F0000 # macro +GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY__SHIFT = 0xa # macro +GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1__SHIFT = 0xd # macro +GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS__SHIFT = 0xe # macro +GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2__SHIFT = 0x10 # macro +GDC0_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT = 0x18 # macro +GDC0_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE__SHIFT = 0x1f # macro +GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY_MASK = 0x00000400 # macro +GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1_MASK = 0x00002000 # macro +GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS_MASK = 0x00004000 # macro +GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2_MASK = 0x00010000 # macro +GDC0_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS_MASK = 0x3F000000 # macro +GDC0_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE_MASK = 0x80000000 # macro +GDC0_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS__SHIFT = 0x0 # macro +GDC0_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN__SHIFT = 0x8 # macro +GDC0_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN__SHIFT = 0xa # macro +GDC0_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN__SHIFT = 0xe # macro +GDC0_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS_MASK = 0x000000FF # macro +GDC0_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN_MASK = 0x00000100 # macro +GDC0_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN_MASK = 0x00003C00 # macro +GDC0_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN_MASK = 0x0000C000 # macro +GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT = 0x0 # macro +GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT = 0x5 # macro +GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS__SHIFT = 0xa # macro +GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK = 0x0000001F # macro +GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK = 0x000003E0 # macro +GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS_MASK = 0x00007C00 # macro +BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK = 0x00000070 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x003F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK = 0x001C0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK = 0x01 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK = 0x8000 # macro +PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT = 0x0 # macro +PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT = 0x1 # macro +PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK = 0x0001 # macro +PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK = 0x0002 # macro +PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT = 0x0 # macro +PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT = 0x1 # macro +PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT = 0x8 # macro +PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT = 0xf # macro +PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK = 0x0001 # macro +PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK = 0x0002 # macro +PCIE_PAGE_REQ_STATUS__STOPPED_MASK = 0x0100 # macro +PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK = 0x8000 # macro +PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT = 0x0 # macro +PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK = 0xFFFFFFFF # macro +PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT = 0x0 # macro +PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK = 0x1F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP_MASK = 0x003F # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK = 0x3F00 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK = 0x003F # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK = 0x0000003F # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK = 0xFFFFF000 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK = 0x000003FF # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK = 0x03FF0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK = 0x1C000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT = 0x0 # macro +PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT = 0x1 # macro +PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x2 # macro +PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT = 0x15 # macro +PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK = 0x00000001 # macro +PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK = 0x00000002 # macro +PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00000004 # macro +PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK = 0xFFE00000 # macro +PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT = 0x0 # macro +PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT = 0x1 # macro +PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT = 0x2 # macro +PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT = 0x3 # macro +PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT = 0x4 # macro +PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0x5 # macro +PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK = 0x0001 # macro +PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK = 0x0002 # macro +PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK = 0x0004 # macro +PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK = 0x0008 # macro +PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK = 0x0010 # macro +PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x0020 # macro +PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT = 0x0 # macro +PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK = 0x0001 # macro +PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT = 0x0 # macro +PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK = 0xFFFF # macro +PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT = 0x0 # macro +PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK = 0xFFFF # macro +PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT = 0x0 # macro +PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK = 0xFFFF # macro +PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT = 0x0 # macro +PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK = 0xFF # macro +PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT = 0x0 # macro +PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK = 0xFFFF # macro +PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT = 0x0 # macro +PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK = 0xFFFF # macro +PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT = 0x0 # macro +PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK = 0xFFFF # macro +PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT = 0x0 # macro +PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK = 0xFFFFFFFF # macro +PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT = 0x0 # macro +PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK = 0xFFFFFFFF # macro +PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT = 0x0 # macro +PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT = 0x0 # macro +PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT = 0x0 # macro +PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT = 0x0 # macro +PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT = 0x0 # macro +PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT = 0x0 # macro +PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT = 0x0 # macro +PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT = 0x3 # macro +PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK = 0x00000007 # macro +PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK = 0x007FFFFF # macro +BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK = 0x007FFFFF # macro +BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK = 0x0000F800 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK = 0x00000700 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK = 0x000000C0 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK = 0x00000400 # macro +PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT = 0x14 # macro +PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK = 0x000F0000 # macro +PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK = 0xFFF00000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT = 0x14 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK = 0x000F0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK = 0xFFF00000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x18 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x19 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x01000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x02000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT = 0x18 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT = 0x19 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK = 0x01000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK = 0x02000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK = 0x0001 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT = 0x8 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT = 0xf # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT = 0x18 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK = 0x000000FF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK = 0x00000F00 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK = 0x00008000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK = 0x000F0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK = 0x01000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT = 0x1 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT = 0x2 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT = 0x3 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT = 0x4 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT = 0x5 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT = 0x6 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT = 0x7 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT = 0x8 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT = 0x9 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT = 0xa # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT = 0xb # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT = 0xc # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT = 0xd # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT = 0xe # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT = 0xf # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT = 0x11 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT = 0x12 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT = 0x13 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT = 0x14 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT = 0x15 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT = 0x16 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT = 0x17 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT = 0x18 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT = 0x19 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT = 0x1a # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT = 0x1b # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT = 0x1c # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT = 0x1d # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT = 0x1e # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT = 0x1f # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK = 0x00000001 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK = 0x00000002 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK = 0x00000004 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK = 0x00000008 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK = 0x00000010 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK = 0x00000020 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK = 0x00000040 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK = 0x00000080 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK = 0x00000100 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK = 0x00000200 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK = 0x00000400 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK = 0x00000800 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK = 0x00001000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK = 0x00002000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK = 0x00004000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK = 0x00008000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK = 0x00010000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK = 0x00020000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK = 0x00040000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK = 0x00080000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK = 0x00100000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK = 0x00200000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK = 0x00400000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK = 0x00800000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK = 0x01000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK = 0x02000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK = 0x04000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK = 0x08000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK = 0x10000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK = 0x20000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK = 0x40000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK = 0x80000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT = 0x1 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT = 0x2 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT = 0x3 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT = 0x4 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT = 0x5 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT = 0x6 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT = 0x7 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT = 0x8 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT = 0x9 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT = 0xa # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT = 0xb # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT = 0xc # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT = 0xd # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT = 0xe # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT = 0xf # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT = 0x11 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT = 0x12 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT = 0x13 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT = 0x14 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT = 0x15 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT = 0x16 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT = 0x17 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT = 0x18 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT = 0x19 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT = 0x1a # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT = 0x1b # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT = 0x1c # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT = 0x1d # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT = 0x1e # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT = 0x1f # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK = 0x00000001 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK = 0x00000002 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK = 0x00000004 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK = 0x00000008 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK = 0x00000010 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK = 0x00000020 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK = 0x00000040 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK = 0x00000080 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK = 0x00000100 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK = 0x00000200 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK = 0x00000400 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK = 0x00000800 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK = 0x00001000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK = 0x00002000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK = 0x00004000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK = 0x00008000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK = 0x00010000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK = 0x00020000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK = 0x00040000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK = 0x00080000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK = 0x00100000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK = 0x00200000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK = 0x00400000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK = 0x00800000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK = 0x01000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK = 0x02000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK = 0x04000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK = 0x08000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK = 0x10000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK = 0x20000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK = 0x40000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK = 0x80000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT = 0x7 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT = 0xa # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK = 0x0000007F # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK = 0x00000080 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK = 0xFFFFFC00 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT = 0x4 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK = 0x0000000F # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK = 0x000000F0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT = 0x1f # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK = 0x7FFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK = 0x80000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK = 0x0000FFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK = 0xFFFF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET__SHIFT = 0x8 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN2SCH_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN3SCH_OFFSET__SHIFT = 0x18 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET_MASK = 0x000000FF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET_MASK = 0x0000FF00 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN2SCH_OFFSET_MASK = 0x00FF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN3SCH_OFFSET_MASK = 0xFF000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN4SCH_OFFSET__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN5SCH_OFFSET__SHIFT = 0x8 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN6SCH_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN7SCH_OFFSET__SHIFT = 0x18 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN4SCH_OFFSET_MASK = 0x000000FF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN5SCH_OFFSET_MASK = 0x0000FF00 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN6SCH_OFFSET_MASK = 0x00FF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN7SCH_OFFSET_MASK = 0xFF000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN8SCH_OFFSET__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN9SCH_OFFSET__SHIFT = 0x8 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN10SCH_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN11SCH_OFFSET__SHIFT = 0x18 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN8SCH_OFFSET_MASK = 0x000000FF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN9SCH_OFFSET_MASK = 0x0000FF00 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN10SCH_OFFSET_MASK = 0x00FF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN11SCH_OFFSET_MASK = 0xFF000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX0SCH_OFFSET__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX1SCH_OFFSET__SHIFT = 0x8 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX2SCH_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX3SCH_OFFSET__SHIFT = 0x18 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX0SCH_OFFSET_MASK = 0x000000FF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX1SCH_OFFSET_MASK = 0x0000FF00 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX2SCH_OFFSET_MASK = 0x00FF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX3SCH_OFFSET_MASK = 0xFF000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX4SCH_OFFSET__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX5SCH_OFFSET__SHIFT = 0x8 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX6SCH_OFFSET__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX7SCH_OFFSET__SHIFT = 0x18 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX4SCH_OFFSET_MASK = 0x000000FF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX5SCH_OFFSET_MASK = 0x0000FF00 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX6SCH_OFFSET_MASK = 0x00FF0000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX7SCH_OFFSET_MASK = 0xFF000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0__DW0__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1__DW1__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2__DW2__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3__DW3__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4__DW4__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5__DW5__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6__DW6__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7__DW7__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8__DW8__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0__DW0__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1__DW1__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2__DW2__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3__DW3__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4__DW4__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5__DW5__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6__DW6__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7__DW7__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8__DW8__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0__DW0__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1__DW1__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2__DW2__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3__DW3__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4__DW4__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5__DW5__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6__DW6__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7__DW7__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8__DW8__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0__DW0__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1__DW1__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2__DW2__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3__DW3__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4__DW4__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5__DW5__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6__DW6__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7__DW7__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8__DW8__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0__DW0__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1__DW1__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2__DW2__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3__DW3__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4__DW4__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5__DW5__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6__DW6__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7__DW7__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8__DW8__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0__DW0__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1__DW1__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2__DW2__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3__DW3__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4__DW4__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5__DW5__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6__DW6__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7__DW7__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8__DW8__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0__DW0__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1__DW1__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2__DW2__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3__DW3__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4__DW4__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5__DW5__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6__DW6__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7__DW7__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8__DW8__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0__DW0__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1__DW1__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2__DW2__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3__DW3__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4__DW4__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5__DW5__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6__DW6__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7__DW7__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8__DW8__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0__DW0__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1__DW1__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2__DW2__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3__DW3__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4__DW4__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5__DW5__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6__DW6__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7__DW7__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8__DW8__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0__DW0__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1__DW1__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2__DW2__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3__DW3__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4__DW4__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5__DW5__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6__DW6__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7__DW7__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8__DW8__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0__DW0__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1__DW1__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2__DW2__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3__DW3__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4__DW4__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5__DW5__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6__DW6__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7__DW7__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8__DW8__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0__DW0__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1__DW1__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2__DW2__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3__DW3__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4__DW4__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5__DW5__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6__DW6__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7__DW7__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8__DW8__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0__DW0__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1__DW1__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2__DW2__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3__DW3__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4__DW4__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5__DW5__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6__DW6__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7__DW7__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8__DW8__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0__DW0__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1__DW1__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2__DW2__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3__DW3__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4__DW4__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5__DW5__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6__DW6__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7__DW7__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8__DW8__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0__DW0__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1__DW1__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2__DW2__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3__DW3__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4__DW4__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5__DW5__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6__DW6__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7__DW7__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8__DW8__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0__DW0__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1__DW1__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2__DW2__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3__DW3__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4__DW4__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5__DW5__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6__DW6__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7__DW7__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8__DW8__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0__DW0__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1__DW1__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2__DW2__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3__DW3__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4__DW4__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5__DW5__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6__DW6__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7__DW7__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8__DW8__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0__DW0__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1__DW1__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2__DW2__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3__DW3__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4__DW4__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5__DW5__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6__DW6__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7__DW7__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8__DW8__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0__DW0__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1__DW1__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2__DW2__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3__DW3__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4__DW4__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5__DW5__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6__DW6__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7__DW7__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8__DW8__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_CMD_COMPLETE_INTR_EN__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x1 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_NEED_FLR_INTR_EN__SHIFT = 0x2 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x3 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_CMD_COMPLETE_INTR_EN__SHIFT = 0x4 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x5 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_NEED_FLR_INTR_EN__SHIFT = 0x6 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x7 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_CMD_COMPLETE_INTR_EN__SHIFT = 0x8 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x9 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_NEED_FLR_INTR_EN__SHIFT = 0xa # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0xb # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_CMD_COMPLETE_INTR_EN__SHIFT = 0xc # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0xd # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_NEED_FLR_INTR_EN__SHIFT = 0xe # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0xf # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_CMD_COMPLETE_INTR_EN__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x11 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_NEED_FLR_INTR_EN__SHIFT = 0x12 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x13 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_CMD_COMPLETE_INTR_EN__SHIFT = 0x14 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x15 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_NEED_FLR_INTR_EN__SHIFT = 0x16 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x17 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_CMD_COMPLETE_INTR_EN__SHIFT = 0x18 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x19 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_NEED_FLR_INTR_EN__SHIFT = 0x1a # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x1b # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_CMD_COMPLETE_INTR_EN__SHIFT = 0x1c # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x1d # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_NEED_FLR_INTR_EN__SHIFT = 0x1e # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x1f # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_CMD_COMPLETE_INTR_EN_MASK = 0x00000001 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00000002 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_NEED_FLR_INTR_EN_MASK = 0x00000004 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00000008 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_CMD_COMPLETE_INTR_EN_MASK = 0x00000010 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00000020 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_NEED_FLR_INTR_EN_MASK = 0x00000040 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00000080 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_CMD_COMPLETE_INTR_EN_MASK = 0x00000100 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00000200 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_NEED_FLR_INTR_EN_MASK = 0x00000400 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00000800 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_CMD_COMPLETE_INTR_EN_MASK = 0x00001000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00002000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_NEED_FLR_INTR_EN_MASK = 0x00004000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00008000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_CMD_COMPLETE_INTR_EN_MASK = 0x00010000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00020000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_NEED_FLR_INTR_EN_MASK = 0x00040000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00080000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_CMD_COMPLETE_INTR_EN_MASK = 0x00100000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00200000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_NEED_FLR_INTR_EN_MASK = 0x00400000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00800000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_CMD_COMPLETE_INTR_EN_MASK = 0x01000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x02000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_NEED_FLR_INTR_EN_MASK = 0x04000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x08000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_CMD_COMPLETE_INTR_EN_MASK = 0x10000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x20000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_NEED_FLR_INTR_EN_MASK = 0x40000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x80000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_CMD_COMPLETE_INTR_EN__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x1 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_NEED_FLR_INTR_EN__SHIFT = 0x2 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x3 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_CMD_COMPLETE_INTR_EN__SHIFT = 0x4 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x5 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_NEED_FLR_INTR_EN__SHIFT = 0x6 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x7 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_CMD_COMPLETE_INTR_EN__SHIFT = 0x8 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x9 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_NEED_FLR_INTR_EN__SHIFT = 0xa # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0xb # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_CMD_COMPLETE_INTR_EN__SHIFT = 0xc # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0xd # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_NEED_FLR_INTR_EN__SHIFT = 0xe # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0xf # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_CMD_COMPLETE_INTR_EN__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x11 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_NEED_FLR_INTR_EN__SHIFT = 0x12 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x13 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_CMD_COMPLETE_INTR_EN__SHIFT = 0x14 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x15 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_NEED_FLR_INTR_EN__SHIFT = 0x16 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x17 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_CMD_COMPLETE_INTR_EN__SHIFT = 0x18 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x19 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_NEED_FLR_INTR_EN__SHIFT = 0x1a # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x1b # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_CMD_COMPLETE_INTR_EN__SHIFT = 0x1c # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x1d # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_NEED_FLR_INTR_EN__SHIFT = 0x1e # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x1f # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_CMD_COMPLETE_INTR_EN_MASK = 0x00000001 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00000002 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_NEED_FLR_INTR_EN_MASK = 0x00000004 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00000008 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_CMD_COMPLETE_INTR_EN_MASK = 0x00000010 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00000020 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_NEED_FLR_INTR_EN_MASK = 0x00000040 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00000080 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_CMD_COMPLETE_INTR_EN_MASK = 0x00000100 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00000200 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_NEED_FLR_INTR_EN_MASK = 0x00000400 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00000800 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_CMD_COMPLETE_INTR_EN_MASK = 0x00001000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00002000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_NEED_FLR_INTR_EN_MASK = 0x00004000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00008000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_CMD_COMPLETE_INTR_EN_MASK = 0x00010000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00020000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_NEED_FLR_INTR_EN_MASK = 0x00040000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00080000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_CMD_COMPLETE_INTR_EN_MASK = 0x00100000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00200000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_NEED_FLR_INTR_EN_MASK = 0x00400000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00800000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_CMD_COMPLETE_INTR_EN_MASK = 0x01000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x02000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_NEED_FLR_INTR_EN_MASK = 0x04000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x08000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_CMD_COMPLETE_INTR_EN_MASK = 0x10000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x20000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_NEED_FLR_INTR_EN_MASK = 0x40000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x80000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_CMD_COMPLETE_INTR_EN__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x1 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_NEED_FLR_INTR_EN__SHIFT = 0x2 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x3 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_CMD_COMPLETE_INTR_EN__SHIFT = 0x4 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x5 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_NEED_FLR_INTR_EN__SHIFT = 0x6 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x7 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_CMD_COMPLETE_INTR_EN__SHIFT = 0x8 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x9 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_NEED_FLR_INTR_EN__SHIFT = 0xa # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0xb # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_CMD_COMPLETE_INTR_EN__SHIFT = 0xc # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0xd # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_NEED_FLR_INTR_EN__SHIFT = 0xe # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0xf # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_CMD_COMPLETE_INTR_EN_MASK = 0x00000001 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00000002 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_NEED_FLR_INTR_EN_MASK = 0x00000004 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00000008 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_CMD_COMPLETE_INTR_EN_MASK = 0x00000010 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00000020 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_NEED_FLR_INTR_EN_MASK = 0x00000040 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00000080 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_CMD_COMPLETE_INTR_EN_MASK = 0x00000100 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00000200 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_NEED_FLR_INTR_EN_MASK = 0x00000400 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00000800 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_CMD_COMPLETE_INTR_EN_MASK = 0x00001000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00002000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_NEED_FLR_INTR_EN_MASK = 0x00004000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00008000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x1 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x2 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x3 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x4 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x5 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x6 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x7 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x8 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x9 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0xa # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0xb # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_CMD_COMPLETE_INTR_STATUS__SHIFT = 0xc # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0xd # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0xe # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0xf # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x11 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x12 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x13 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x14 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x15 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x16 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x17 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x18 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x19 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x1a # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x1b # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x1c # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x1d # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x1e # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x1f # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_CMD_COMPLETE_INTR_STATUS_MASK = 0x00000001 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00000002 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00000004 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00000008 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_CMD_COMPLETE_INTR_STATUS_MASK = 0x00000010 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00000020 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00000040 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00000080 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_CMD_COMPLETE_INTR_STATUS_MASK = 0x00000100 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00000200 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00000400 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00000800 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_CMD_COMPLETE_INTR_STATUS_MASK = 0x00001000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00002000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00004000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00008000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_CMD_COMPLETE_INTR_STATUS_MASK = 0x00010000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00020000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00040000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00080000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_CMD_COMPLETE_INTR_STATUS_MASK = 0x00100000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00200000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00400000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00800000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_CMD_COMPLETE_INTR_STATUS_MASK = 0x01000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x02000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_NEED_FLR_INTR_STATUS_MASK = 0x04000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x08000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_CMD_COMPLETE_INTR_STATUS_MASK = 0x10000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x20000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_NEED_FLR_INTR_STATUS_MASK = 0x40000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x80000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x1 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x2 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x3 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x4 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x5 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x6 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x7 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x8 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x9 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0xa # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0xb # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_CMD_COMPLETE_INTR_STATUS__SHIFT = 0xc # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0xd # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0xe # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0xf # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x10 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x11 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x12 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x13 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x14 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x15 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x16 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x17 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x18 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x19 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x1a # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x1b # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x1c # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x1d # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x1e # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x1f # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_CMD_COMPLETE_INTR_STATUS_MASK = 0x00000001 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00000002 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00000004 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00000008 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_CMD_COMPLETE_INTR_STATUS_MASK = 0x00000010 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00000020 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00000040 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00000080 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_CMD_COMPLETE_INTR_STATUS_MASK = 0x00000100 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00000200 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00000400 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00000800 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_CMD_COMPLETE_INTR_STATUS_MASK = 0x00001000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00002000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00004000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00008000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_CMD_COMPLETE_INTR_STATUS_MASK = 0x00010000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00020000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00040000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00080000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_CMD_COMPLETE_INTR_STATUS_MASK = 0x00100000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00200000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00400000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00800000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_CMD_COMPLETE_INTR_STATUS_MASK = 0x01000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x02000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_NEED_FLR_INTR_STATUS_MASK = 0x04000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x08000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_CMD_COMPLETE_INTR_STATUS_MASK = 0x10000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x20000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_NEED_FLR_INTR_STATUS_MASK = 0x40000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x80000000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x0 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x1 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x2 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x3 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x4 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x5 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x6 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x7 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x8 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x9 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0xa # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0xb # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_CMD_COMPLETE_INTR_STATUS__SHIFT = 0xc # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0xd # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0xe # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0xf # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_CMD_COMPLETE_INTR_STATUS_MASK = 0x00000001 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00000002 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00000004 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00000008 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_CMD_COMPLETE_INTR_STATUS_MASK = 0x00000010 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00000020 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00000040 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00000080 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_CMD_COMPLETE_INTR_STATUS_MASK = 0x00000100 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00000200 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00000400 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00000800 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_CMD_COMPLETE_INTR_STATUS_MASK = 0x00001000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00002000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00004000 # macro +PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK = 0x001C0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK = 0x01 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK = 0x1F00 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_RC0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_RC0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK = 0x000000FF # macro +BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK = 0xF000 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK = 0x0000000F # macro +BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK = 0x0000FFF0 # macro +BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK = 0x0000000F # macro +BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK = 0x0000FFF0 # macro +BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK = 0x01 # macro +BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_PMI_CAP__VERSION_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT = 0x13 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK = 0x00007F80 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK = 0x00018000 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK = 0x00040000 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK = 0xFFF80000 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__INBAND_PD_DISABLE__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK = 0x00C0 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK = 0x2000 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL__INBAND_PD_DISABLE_MASK = 0x4000 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK = 0x00000070 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK = 0x00000300 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK = 0x000E # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x003F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK = 0x00000004 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT = 0x1b # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK = 0x00000004 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK = 0x00000008 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS_MASK = 0x00000180 # macro +BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK = 0xF8000000 # macro +BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK = 0x007FFFFF # macro +BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK = 0x007FFFFF # macro +BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK = 0x00000400 # macro +BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK = 0x0000F800 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK = 0x00000700 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK = 0x000000C0 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK = 0x00000200 # macro +BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK = 0x00000070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x003F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK = 0x001C0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK = 0x01 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK = 0x1F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK = 0x003F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK = 0x3F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK = 0x003F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK = 0x0000003F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK = 0xFFFFF000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK = 0x000003FF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK = 0x03FF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK = 0x1C000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK = 0xFFE00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK = 0x007FFFFF # macro +BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK = 0x007FFFFF # macro +BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK = 0x0000F800 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK = 0x00000700 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK = 0x000000C0 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT = 0x1b # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT = 0x1d # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT = 0x1e # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK = 0x08000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK = 0x20000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK = 0x40000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT = 0x1b # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT = 0x1d # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT = 0x1e # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK = 0x08000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK = 0x20000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK = 0x40000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK = 0x0000007F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK = 0xFFFFFC00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK = 0x7FFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN2SCH_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN3SCH_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN2SCH_OFFSET_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN3SCH_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN4SCH_OFFSET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN5SCH_OFFSET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN6SCH_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN7SCH_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN4SCH_OFFSET_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN5SCH_OFFSET_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN6SCH_OFFSET_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN7SCH_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN8SCH_OFFSET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN9SCH_OFFSET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN10SCH_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN11SCH_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN8SCH_OFFSET_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN9SCH_OFFSET_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN10SCH_OFFSET_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN11SCH_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX0SCH_OFFSET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX1SCH_OFFSET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX2SCH_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX3SCH_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX0SCH_OFFSET_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX1SCH_OFFSET_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX2SCH_OFFSET_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX3SCH_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX4SCH_OFFSET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX5SCH_OFFSET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX6SCH_OFFSET__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX7SCH_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX4SCH_OFFSET_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX5SCH_OFFSET_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX6SCH_OFFSET_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX7SCH_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0__DW0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1__DW1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2__DW2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3__DW3__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4__DW4__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5__DW5__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6__DW6__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7__DW7__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8__DW8__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0__DW0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1__DW1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2__DW2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3__DW3__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4__DW4__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5__DW5__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6__DW6__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7__DW7__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8__DW8__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0__DW0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1__DW1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2__DW2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3__DW3__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4__DW4__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5__DW5__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6__DW6__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7__DW7__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8__DW8__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0__DW0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1__DW1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2__DW2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3__DW3__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4__DW4__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5__DW5__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6__DW6__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7__DW7__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8__DW8__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0__DW0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1__DW1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2__DW2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3__DW3__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4__DW4__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5__DW5__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6__DW6__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7__DW7__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8__DW8__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0__DW0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1__DW1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2__DW2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3__DW3__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4__DW4__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5__DW5__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6__DW6__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7__DW7__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8__DW8__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0__DW0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1__DW1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2__DW2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3__DW3__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4__DW4__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5__DW5__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6__DW6__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7__DW7__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8__DW8__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0__DW0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1__DW1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2__DW2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3__DW3__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4__DW4__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5__DW5__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6__DW6__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7__DW7__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8__DW8__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0__DW0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1__DW1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2__DW2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3__DW3__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4__DW4__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5__DW5__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6__DW6__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7__DW7__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8__DW8__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0__DW0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1__DW1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2__DW2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3__DW3__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4__DW4__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5__DW5__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6__DW6__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7__DW7__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8__DW8__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0__DW0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1__DW1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2__DW2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3__DW3__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4__DW4__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5__DW5__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6__DW6__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7__DW7__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8__DW8__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0__DW0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1__DW1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2__DW2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3__DW3__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4__DW4__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5__DW5__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6__DW6__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7__DW7__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8__DW8__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0__DW0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1__DW1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2__DW2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3__DW3__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4__DW4__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5__DW5__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6__DW6__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7__DW7__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8__DW8__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0__DW0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1__DW1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2__DW2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3__DW3__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4__DW4__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5__DW5__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6__DW6__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7__DW7__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8__DW8__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0__DW0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1__DW1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2__DW2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3__DW3__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4__DW4__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5__DW5__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6__DW6__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7__DW7__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8__DW8__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0__DW0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1__DW1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2__DW2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3__DW3__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4__DW4__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5__DW5__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6__DW6__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7__DW7__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8__DW8__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0__DW0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1__DW1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2__DW2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3__DW3__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4__DW4__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5__DW5__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6__DW6__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7__DW7__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8__DW8__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0__DW0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1__DW1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2__DW2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3__DW3__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4__DW4__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5__DW5__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6__DW6__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7__DW7__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8__DW8__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0__DW0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0__DW0_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1__DW1__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1__DW1_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2__DW2__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2__DW2_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3__DW3__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3__DW3_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4__DW4__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4__DW4_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5__DW5__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5__DW5_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6__DW6__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6__DW6_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7__DW7__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7__DW7_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8__DW8__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8__DW8_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_CMD_COMPLETE_INTR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_NEED_FLR_INTR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_CMD_COMPLETE_INTR_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_NEED_FLR_INTR_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_CMD_COMPLETE_INTR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_NEED_FLR_INTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_CMD_COMPLETE_INTR_EN__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_NEED_FLR_INTR_EN__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_CMD_COMPLETE_INTR_EN__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_NEED_FLR_INTR_EN__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_CMD_COMPLETE_INTR_EN__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_NEED_FLR_INTR_EN__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_CMD_COMPLETE_INTR_EN__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_NEED_FLR_INTR_EN__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x1b # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_CMD_COMPLETE_INTR_EN__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x1d # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_NEED_FLR_INTR_EN__SHIFT = 0x1e # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_CMD_COMPLETE_INTR_EN_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_NEED_FLR_INTR_EN_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_CMD_COMPLETE_INTR_EN_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_NEED_FLR_INTR_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_CMD_COMPLETE_INTR_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_NEED_FLR_INTR_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_CMD_COMPLETE_INTR_EN_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_NEED_FLR_INTR_EN_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_CMD_COMPLETE_INTR_EN_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_NEED_FLR_INTR_EN_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_CMD_COMPLETE_INTR_EN_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_NEED_FLR_INTR_EN_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_CMD_COMPLETE_INTR_EN_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_NEED_FLR_INTR_EN_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x08000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_CMD_COMPLETE_INTR_EN_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x20000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_NEED_FLR_INTR_EN_MASK = 0x40000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_CMD_COMPLETE_INTR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_NEED_FLR_INTR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_CMD_COMPLETE_INTR_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_NEED_FLR_INTR_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_CMD_COMPLETE_INTR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_NEED_FLR_INTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_CMD_COMPLETE_INTR_EN__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_NEED_FLR_INTR_EN__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_CMD_COMPLETE_INTR_EN__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_NEED_FLR_INTR_EN__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_CMD_COMPLETE_INTR_EN__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_NEED_FLR_INTR_EN__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_CMD_COMPLETE_INTR_EN__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_NEED_FLR_INTR_EN__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x1b # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_CMD_COMPLETE_INTR_EN__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x1d # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_NEED_FLR_INTR_EN__SHIFT = 0x1e # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_CMD_COMPLETE_INTR_EN_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_NEED_FLR_INTR_EN_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_CMD_COMPLETE_INTR_EN_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_NEED_FLR_INTR_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_CMD_COMPLETE_INTR_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_NEED_FLR_INTR_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_CMD_COMPLETE_INTR_EN_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_NEED_FLR_INTR_EN_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_CMD_COMPLETE_INTR_EN_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_NEED_FLR_INTR_EN_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_CMD_COMPLETE_INTR_EN_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_NEED_FLR_INTR_EN_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_CMD_COMPLETE_INTR_EN_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_NEED_FLR_INTR_EN_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x08000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_CMD_COMPLETE_INTR_EN_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x20000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_NEED_FLR_INTR_EN_MASK = 0x40000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_CMD_COMPLETE_INTR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_NEED_FLR_INTR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_CMD_COMPLETE_INTR_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_NEED_FLR_INTR_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_CMD_COMPLETE_INTR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_NEED_FLR_INTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_CMD_COMPLETE_INTR_EN__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_SELF_RECOVERED_INTR_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_NEED_FLR_INTR_EN__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_VM_BUSY_TRANSITION_INTR_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_CMD_COMPLETE_INTR_EN_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_NEED_FLR_INTR_EN_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_CMD_COMPLETE_INTR_EN_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_NEED_FLR_INTR_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_CMD_COMPLETE_INTR_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_NEED_FLR_INTR_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_CMD_COMPLETE_INTR_EN_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_SELF_RECOVERED_INTR_EN_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_NEED_FLR_INTR_EN_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_VM_BUSY_TRANSITION_INTR_EN_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_CMD_COMPLETE_INTR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x1b # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x1d # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x1e # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_CMD_COMPLETE_INTR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_CMD_COMPLETE_INTR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_CMD_COMPLETE_INTR_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_CMD_COMPLETE_INTR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_CMD_COMPLETE_INTR_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_CMD_COMPLETE_INTR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_CMD_COMPLETE_INTR_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_NEED_FLR_INTR_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x08000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_CMD_COMPLETE_INTR_STATUS_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x20000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_NEED_FLR_INTR_STATUS_MASK = 0x40000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_CMD_COMPLETE_INTR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x1b # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x1d # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x1e # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_CMD_COMPLETE_INTR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_CMD_COMPLETE_INTR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_CMD_COMPLETE_INTR_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_CMD_COMPLETE_INTR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_CMD_COMPLETE_INTR_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_CMD_COMPLETE_INTR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_CMD_COMPLETE_INTR_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_NEED_FLR_INTR_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x08000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_CMD_COMPLETE_INTR_STATUS_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x20000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_NEED_FLR_INTR_STATUS_MASK = 0x40000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_CMD_COMPLETE_INTR_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_CMD_COMPLETE_INTR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_NEED_FLR_INTR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_CMD_COMPLETE_INTR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00000002 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00000004 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_CMD_COMPLETE_INTR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_CMD_COMPLETE_INTR_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_CMD_COMPLETE_INTR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_SELF_RECOVERED_INTR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_NEED_FLR_INTR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_VM_BUSY_TRANSITION_INTR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION_MASK = 0x0007 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK = 0xFFFFFFF0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK = 0x000000E0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK = 0x00003F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK = 0x00001C00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK = 0x001C0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK = 0x01 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0x000000FF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK = 0x1F00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT = 0x1 # macro +RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT = 0x2 # macro +RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT = 0x3 # macro +RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT = 0x4 # macro +RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK = 0x00000002 # macro +RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK = 0x00000004 # macro +RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK = 0x00000008 # macro +RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK = 0x00000010 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT = 0x2 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT = 0x3 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT = 0x4 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT = 0x5 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT = 0x6 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT = 0x7 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT = 0x8 # macro +RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT = 0xc # macro +RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT = 0xd # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT = 0x11 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT = 0x12 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT = 0x13 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT = 0x14 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT = 0x15 # macro +RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT = 0x18 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT = 0x19 # macro +RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT = 0x1c # macro +RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT = 0x1d # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_MASK = 0x00000004 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_MASK = 0x00000008 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS_MASK = 0x00000010 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK = 0x00000020 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK = 0x00000040 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK = 0x00000080 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK = 0x00000100 # macro +RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK = 0x00001000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK = 0x00002000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK = 0x00010000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK = 0x00020000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK = 0x00040000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK = 0x00080000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK = 0x00100000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK = 0x00200000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK = 0x01000000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK = 0x0E000000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK = 0x10000000 # macro +RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK = 0xE0000000 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT = 0x7 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT = 0x8 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT = 0x9 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT = 0xa # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT = 0xb # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT = 0xc # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT = 0xd # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT = 0xe # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT = 0xf # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT = 0x11 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT = 0x12 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT = 0x13 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK = 0x00000080 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK = 0x00000100 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK = 0x00000200 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK = 0x00000400 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK = 0x00000800 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK = 0x00001000 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK = 0x00002000 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK = 0x00004000 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK = 0x00008000 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK = 0x00010000 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK = 0x00020000 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK = 0x00040000 # macro +RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK = 0x00080000 # macro +RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT = 0x8 # macro +RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT = 0x11 # macro +RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK = 0x00000100 # macro +RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK = 0x00010000 # macro +RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK = 0x00020000 # macro +RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT = 0x1 # macro +RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT = 0x2 # macro +RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT = 0x3 # macro +RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK = 0x00000002 # macro +RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK = 0x00000004 # macro +RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK = 0x00000008 # macro +RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK = 0xFFFF0000 # macro +RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT = 0x8 # macro +RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK = 0x000000FF # macro +RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK = 0x00001F00 # macro +RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK = 0x000003FF # macro +RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT = 0x1 # macro +RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK = 0x00007FFE # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT = 0x1 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT = 0x2 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT = 0x3 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT = 0x4 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT = 0x5 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT = 0xb # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT = 0x12 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT = 0x19 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK = 0x00000002 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK = 0x00000004 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK = 0x00000008 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK = 0x00000010 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK = 0x000007E0 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK = 0x0003F800 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK = 0x01FC0000 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK = 0xFE000000 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT = 0x6 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT = 0xc # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT = 0x11 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK = 0x0000003F # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK = 0x00000FC0 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK = 0x0001F000 # macro +RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK = 0x00FE0000 # macro +RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK = 0xFFFFFFFF # macro +RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT = 0x7 # macro +RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT = 0x8 # macro +RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT = 0x1e # macro +RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK = 0x00000080 # macro +RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK = 0x00000100 # macro +RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK = 0x40000000 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT = 0x1 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT = 0x2 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT = 0x3 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT = 0x4 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT = 0x6 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK = 0x00000001 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK = 0x00000002 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK = 0x00000004 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK = 0x00000008 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK = 0x00000010 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK = 0x00000040 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT = 0x1 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT = 0x2 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT = 0x3 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT = 0x4 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT = 0x6 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT = 0x7 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK = 0x00000001 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK = 0x00000002 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK = 0x00000004 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK = 0x00000008 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK = 0x00000010 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK = 0x00000040 # macro +RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK = 0x00000080 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK = 0x00000001 # macro +RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT = 0x7 # macro +RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK = 0x00000080 # macro +RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT = 0x1 # macro +RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT = 0x2 # macro +RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT = 0x3 # macro +RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT = 0x4 # macro +RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK = 0x00000001 # macro +RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK = 0x00000002 # macro +RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK = 0x00000004 # macro +RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK = 0x00000008 # macro +RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK = 0x00000010 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT = 0x3 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT = 0x6 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT = 0x7 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT = 0xa # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT = 0xd # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT = 0xe # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT = 0xf # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT = 0x10 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT = 0x11 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK = 0x00000007 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK = 0x00000038 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK = 0x00000040 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK = 0x00000380 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK = 0x00001C00 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK = 0x00002000 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK = 0x00004000 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK = 0x00008000 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK = 0x00010000 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK = 0x00020000 # macro +RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT = 0x1d # macro +RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK = 0x20000000 # macro +RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT = 0x4 # macro +RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK = 0x00000010 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0xFF # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT = 0x8 # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK = 0x001F # macro +RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK = 0x0100 # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK = 0x1F # macro +RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT = 0xa # macro +RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT = 0xc # macro +RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT = 0x18 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT = 0x19 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT = 0x1a # macro +RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK = 0x00000C00 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK = 0x00003000 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK = 0x01000000 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK = 0x02000000 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK = 0x04000000 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT = 0x3 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT = 0x8 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK = 0x00000007 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK = 0x000000F8 # macro +RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK = 0x0000FF00 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT = 0x8 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT = 0x11 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT = 0x12 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT = 0x18 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT = 0x19 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT = 0x1a # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT = 0x1b # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT = 0x1c # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT = 0x1d # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT = 0x1e # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT = 0x1f # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK = 0x00000001 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK = 0x00000700 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK = 0x00020000 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK = 0x00040000 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK = 0x01000000 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK = 0x02000000 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK = 0x04000000 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK = 0x08000000 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK = 0x10000000 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK = 0x20000000 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK = 0x40000000 # macro +RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK = 0x80000000 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0x8 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT = 0x9 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT = 0x14 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT = 0x15 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT = 0x16 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT = 0x18 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT = 0x19 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT = 0x1a # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00000100 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK = 0x00000200 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK = 0x00100000 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK = 0x00200000 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK = 0x00400000 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK = 0x01000000 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK = 0x02000000 # macro +RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK = 0x04000000 # macro +RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT = 0x1 # macro +RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT = 0x2 # macro +RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT = 0x3 # macro +RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK = 0x00000001 # macro +RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK = 0x00000002 # macro +RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK = 0x00000004 # macro +RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK = 0x00000008 # macro +RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT = 0x0 # macro +RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT = 0x0 # macro +RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK = 0xFFFFFFFF # macro +RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT = 0x0 # macro +RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT = 0x7 # macro +RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT = 0x1e # macro +RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK = 0x00000001 # macro +RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK = 0x00000080 # macro +RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK = 0x40000000 # macro +RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT = 0x19 # macro +RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK = 0x06000000 # macro +RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT = 0x1c # macro +RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK = 0x70000000 # macro +RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT = 0x7 # macro +RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT = 0x8 # macro +RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK = 0x00000080 # macro +RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK = 0x00000100 # macro +RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT = 0x0 # macro +RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT = 0x1 # macro +RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT = 0x2 # macro +RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT = 0x3 # macro +RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT = 0x4 # macro +RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK = 0x00000001 # macro +RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK = 0x00000002 # macro +RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK = 0x00000004 # macro +RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK = 0x00000008 # macro +RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK = 0x00000010 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT = 0x0 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT = 0x11 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT = 0x15 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK = 0x00000001 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK = 0x00020000 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK = 0x00E00000 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT = 0x18 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT = 0x1d # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK = 0x01000000 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK = 0x20000000 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT = 0x2 # macro +RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK = 0x00000004 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT = 0x8 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT = 0xb # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT = 0x11 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT = 0x12 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT = 0x13 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT = 0x14 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK = 0x00000001 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK = 0x00000700 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK = 0x00000800 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK = 0x00020000 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK = 0x00040000 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK = 0x00080000 # macro +RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK = 0x00100000 # macro +RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0x8 # macro +RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT = 0x9 # macro +RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT = 0x14 # macro +RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT = 0x15 # macro +RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT = 0x1b # macro +RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00000100 # macro +RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK = 0x00000200 # macro +RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK = 0x00100000 # macro +RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK = 0x00200000 # macro +RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK = 0x08000000 # macro +RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT = 0x1 # macro +RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT = 0x2 # macro +RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT = 0x3 # macro +RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK = 0x00000001 # macro +RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK = 0x00000002 # macro +RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK = 0x00000004 # macro +RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK = 0x00000008 # macro +RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT = 0x1b # macro +RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK = 0x00000001 # macro +RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK = 0x08000000 # macro +RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT = 0xa # macro +RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK = 0x00000400 # macro +RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK = 0xFFFFFFFF # macro +RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT = 0x0 # macro +RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT = 0xa # macro +RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT = 0xf # macro +RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT = 0x10 # macro +RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT = 0x1a # macro +RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT = 0x1f # macro +RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK = 0x000003FF # macro +RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK = 0x00001C00 # macro +RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK = 0x00008000 # macro +RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK = 0x03FF0000 # macro +RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK = 0x1C000000 # macro +RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK = 0x80000000 # macro +RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT = 0x0 # macro +RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT = 0x8 # macro +RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK = 0x00000001 # macro +RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK = 0x00000100 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT = 0x0 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT = 0x1 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT = 0x2 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT = 0x3 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT = 0x4 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT = 0x5 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT = 0x6 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0x7 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK = 0x00000001 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK = 0x00000002 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK = 0x00000004 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK = 0x00000008 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK = 0x00000010 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK = 0x00000020 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK = 0x00000040 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00000080 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT = 0x0 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK = 0xFFFFFFFF # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT = 0x0 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK = 0xFFFFFFFF # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT = 0x0 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK = 0xFFFFFFFF # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT = 0x0 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK = 0xFFFFFFFF # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT = 0x0 # macro +RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK = 0xFFFFFFFF # macro +RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT = 0x0 # macro +RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT = 0x3 # macro +RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK = 0x00000007 # macro +RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK = 0x00000008 # macro +PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT32_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT32_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT32_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT32_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT33_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT33_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT33_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT33_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT34_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT34_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT34_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT34_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT35_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT35_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT35_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT35_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT36_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT36_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT36_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT36_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT37_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT37_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT37_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT37_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT38_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT38_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT38_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT38_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT39_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT39_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT39_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT39_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT40_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT40_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT40_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT40_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT41_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT41_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT41_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT41_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT42_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT42_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT42_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT42_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT43_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT43_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT43_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT43_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT44_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT44_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT44_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT44_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT45_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT45_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT45_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT45_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT46_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT46_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT46_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT46_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT47_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT47_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT47_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT47_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT48_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT48_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT48_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT48_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT49_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT49_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT49_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT49_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT50_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT50_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT50_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT50_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT51_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT51_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT51_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT51_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT52_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT52_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT52_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT52_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT53_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT53_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT53_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT53_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT54_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT54_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT54_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT54_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT55_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT55_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT55_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT55_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT56_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT56_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT56_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT56_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT57_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT57_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT57_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT57_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT58_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT58_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT58_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT58_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT59_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT59_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT59_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT59_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT60_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT60_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT60_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT60_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT61_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT61_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT61_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT61_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT62_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT62_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT62_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT62_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT63_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT63_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT63_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT63_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT64_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT64_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT64_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT64_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT65_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT65_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT65_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT65_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT66_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT66_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT66_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT66_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT67_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT67_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT67_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT67_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT68_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT68_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT68_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT68_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT69_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT69_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT69_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT69_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT70_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT70_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT70_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT70_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT71_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT71_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT71_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT71_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT72_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT72_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT72_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT72_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT73_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT73_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT73_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT73_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT74_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT74_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT74_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT74_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT75_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT75_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT75_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT75_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT76_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT76_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT76_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT76_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT77_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT77_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT77_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT77_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT78_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT78_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT78_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT78_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT79_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT79_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT79_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT79_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT80_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT80_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT80_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT80_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT81_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT81_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT81_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT81_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT82_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT82_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT82_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT82_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT83_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT83_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT83_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT83_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT84_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT84_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT84_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT84_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT85_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT85_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT85_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT85_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT86_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT86_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT86_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT86_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT87_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT87_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT87_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT87_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT88_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT88_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT88_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT88_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT89_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT89_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT89_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT89_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT90_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT90_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT90_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT90_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT91_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT91_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT91_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT91_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT92_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT92_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT92_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT92_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT93_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT93_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT93_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT93_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT94_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT94_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT94_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT94_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT95_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT95_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT95_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT95_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT96_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT96_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT96_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT96_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT97_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT97_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT97_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT97_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT98_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT98_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT98_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT98_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT99_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT99_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT99_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT99_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT100_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT100_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT100_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT100_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT101_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT101_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT101_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT101_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT102_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT102_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT102_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT102_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT103_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT103_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT103_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT103_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT104_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT104_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT104_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT104_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT105_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT105_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT105_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT105_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT106_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT106_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT106_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT106_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT107_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT107_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT107_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT107_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT108_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT108_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT108_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT108_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT109_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT109_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT109_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT109_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT110_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT110_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT110_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT110_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT111_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT111_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT111_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT111_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT112_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT112_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT112_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT112_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT113_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT113_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT113_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT113_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT114_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT114_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT114_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT114_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT115_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT115_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT115_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT115_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT116_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT116_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT116_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT116_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT117_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT117_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT117_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT117_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT118_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT118_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT118_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT118_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT119_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT119_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT119_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT119_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT120_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT120_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT120_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT120_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT121_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT121_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT121_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT121_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT122_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT122_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT122_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT122_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT123_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT123_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT123_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT123_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT124_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT124_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT124_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT124_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT125_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT125_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT125_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT125_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT126_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT126_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT126_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT126_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT127_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT127_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT127_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT127_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT128_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT128_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT128_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT128_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT129_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT129_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT129_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT129_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT130_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT130_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT130_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT130_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT131_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT131_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT131_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT131_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT132_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT132_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT132_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT132_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT133_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT133_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT133_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT133_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT134_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT134_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT134_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT134_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT135_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT135_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT135_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT135_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT136_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT136_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT136_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT136_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT137_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT137_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT137_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT137_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT138_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT138_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT138_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT138_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT139_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT139_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT139_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT139_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT140_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT140_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT140_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT140_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT141_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT141_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT141_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT141_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT142_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT142_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT142_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT142_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT143_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT143_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT143_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT143_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT144_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT144_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT144_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT144_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT145_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT145_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT145_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT145_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT146_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT146_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT146_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT146_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT147_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT147_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT147_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT147_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT148_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT148_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT148_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT148_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT149_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT149_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT149_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT149_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT150_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT150_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT150_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT150_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT151_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT151_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT151_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT151_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT152_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT152_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT152_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT152_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT153_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT153_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT153_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT153_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT154_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT154_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT154_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT154_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT155_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT155_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT155_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT155_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT156_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT156_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT156_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT156_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT157_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT157_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT157_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT157_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT158_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT158_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT158_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT158_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT159_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT159_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT159_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT159_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT160_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT160_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT160_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT160_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT161_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT161_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT161_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT161_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT162_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT162_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT162_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT162_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT163_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT163_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT163_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT163_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT164_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT164_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT164_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT164_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT165_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT165_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT165_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT165_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT166_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT166_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT166_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT166_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT167_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT167_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT167_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT167_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT168_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT168_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT168_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT168_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT169_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT169_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT169_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT169_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT170_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT170_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT170_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT170_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT171_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT171_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT171_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT171_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT172_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT172_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT172_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT172_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT173_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT173_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT173_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT173_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT174_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT174_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT174_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT174_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT175_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT175_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT175_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT175_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT176_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT176_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT176_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT176_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT177_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT177_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT177_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT177_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT178_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT178_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT178_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT178_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT179_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT179_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT179_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT179_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT180_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT180_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT180_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT180_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT181_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT181_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT181_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT181_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT182_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT182_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT182_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT182_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT183_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT183_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT183_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT183_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT184_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT184_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT184_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT184_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT185_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT185_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT185_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT185_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT186_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT186_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT186_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT186_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT187_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT187_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT187_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT187_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT188_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT188_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT188_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT188_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT189_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT189_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT189_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT189_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT190_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT190_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT190_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT190_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT191_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT191_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT191_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT191_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT192_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT192_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT192_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT192_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT193_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT193_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT193_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT193_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT194_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT194_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT194_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT194_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT195_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT195_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT195_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT195_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT196_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT196_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT196_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT196_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT197_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT197_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT197_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT197_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT198_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT198_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT198_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT198_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT199_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT199_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT199_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT199_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT200_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT200_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT200_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT200_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT201_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT201_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT201_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT201_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT202_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT202_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT202_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT202_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT203_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT203_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT203_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT203_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT204_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT204_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT204_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT204_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT205_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT205_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT205_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT205_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT206_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT206_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT206_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT206_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT207_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT207_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT207_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT207_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT208_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT208_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT208_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT208_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT209_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT209_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT209_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT209_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT210_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT210_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT210_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT210_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT211_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT211_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT211_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT211_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT212_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT212_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT212_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT212_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT213_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT213_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT213_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT213_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT214_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT214_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT214_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT214_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT215_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT215_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT215_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT215_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT216_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT216_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT216_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT216_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT217_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT217_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT217_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT217_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT218_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT218_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT218_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT218_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT219_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT219_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT219_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT219_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT220_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT220_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT220_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT220_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT221_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT221_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT221_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT221_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT222_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT222_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT222_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT222_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT223_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT223_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT223_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT223_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT224_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT224_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT224_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT224_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT225_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT225_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT225_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT225_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT226_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT226_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT226_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT226_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT227_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT227_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT227_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT227_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT228_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT228_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT228_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT228_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT229_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT229_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT229_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT229_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT230_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT230_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT230_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT230_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT231_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT231_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT231_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT231_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT232_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT232_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT232_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT232_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT233_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT233_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT233_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT233_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT234_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT234_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT234_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT234_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT235_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT235_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT235_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT235_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT236_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT236_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT236_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT236_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT237_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT237_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT237_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT237_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT238_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT238_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT238_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT238_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT239_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT239_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT239_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT239_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT240_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT240_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT240_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT240_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT241_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT241_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT241_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT241_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT242_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT242_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT242_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT242_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT243_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT243_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT243_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT243_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT244_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT244_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT244_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT244_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT245_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT245_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT245_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT245_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT246_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT246_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT246_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT246_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT247_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT247_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT247_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT247_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT248_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT248_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT248_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT248_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT249_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT249_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT249_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT249_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT250_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT250_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT250_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT250_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT251_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT251_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT251_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT251_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT252_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT252_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT252_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT252_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT253_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT253_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT253_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT253_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT254_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT254_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT254_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT254_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT255_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +PCIEMSIX_VECT255_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +PCIEMSIX_VECT255_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +PCIEMSIX_VECT255_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +PCIEMSIX_PBA_0__MSIX_PENDING_BITS__SHIFT = 0x0 # macro +PCIEMSIX_PBA_0__MSIX_PENDING_BITS_MASK = 0xFFFFFFFF # macro +PCIEMSIX_PBA_1__MSIX_PENDING_BITS__SHIFT = 0x0 # macro +PCIEMSIX_PBA_1__MSIX_PENDING_BITS_MASK = 0xFFFFFFFF # macro +PCIEMSIX_PBA_2__MSIX_PENDING_BITS__SHIFT = 0x0 # macro +PCIEMSIX_PBA_2__MSIX_PENDING_BITS_MASK = 0xFFFFFFFF # macro +PCIEMSIX_PBA_3__MSIX_PENDING_BITS__SHIFT = 0x0 # macro +PCIEMSIX_PBA_3__MSIX_PENDING_BITS_MASK = 0xFFFFFFFF # macro +PCIEMSIX_PBA_4__MSIX_PENDING_BITS__SHIFT = 0x0 # macro +PCIEMSIX_PBA_4__MSIX_PENDING_BITS_MASK = 0xFFFFFFFF # macro +PCIEMSIX_PBA_5__MSIX_PENDING_BITS__SHIFT = 0x0 # macro +PCIEMSIX_PBA_5__MSIX_PENDING_BITS_MASK = 0xFFFFFFFF # macro +PCIEMSIX_PBA_6__MSIX_PENDING_BITS__SHIFT = 0x0 # macro +PCIEMSIX_PBA_6__MSIX_PENDING_BITS_MASK = 0xFFFFFFFF # macro +PCIEMSIX_PBA_7__MSIX_PENDING_BITS__SHIFT = 0x0 # macro +PCIEMSIX_PBA_7__MSIX_PENDING_BITS_MASK = 0xFFFFFFFF # macro +SUM_INDEX__SUM_INDEX__SHIFT = 0x0 # macro +SUM_INDEX__SUM_INDEX_MASK = 0xFFFFFFFF # macro +SUM_DATA__SUM_DATA__SHIFT = 0x0 # macro +SUM_DATA__SUM_DATA_MASK = 0xFFFFFFFF # macro +SUM_INDEX_HI__SUM_INDEX_HI__SHIFT = 0x0 # macro +SUM_INDEX_HI__SUM_INDEX_HI_MASK = 0x000000FF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT = 0x11 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT = 0x13 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT = 0x19 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK = 0x00010000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK = 0x00020000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK = 0x00040000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK = 0x00080000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK = 0x00E00000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK = 0x01000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK = 0x0E000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK = 0x70000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK = 0xFFFF0000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT = 0x2 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT = 0x3 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT = 0x4 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT = 0x5 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT = 0x6 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT = 0x7 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT = 0x9 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT = 0xc # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT = 0xd # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT = 0xe # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT = 0xf # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT = 0x11 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT = 0x17 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT = 0x1a # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK = 0x00000001 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK = 0x00000004 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK = 0x00000008 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK = 0x00000010 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK = 0x00000020 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK = 0x00000040 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK = 0x00000080 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK = 0x00000100 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK = 0x00000E00 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK = 0x00001000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK = 0x00002000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK = 0x00004000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK = 0x00008000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK = 0x00010000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK = 0x00020000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK = 0x00700000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK = 0x03800000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK = 0x1C000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK = 0xE0000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT = 0x2 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT = 0x3 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT = 0x6 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT = 0x7 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT = 0x9 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT = 0xb # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT = 0xe # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT = 0x19 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT = 0x1b # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK = 0x00000001 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK = 0x00000004 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK = 0x00000038 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK = 0x00000040 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK = 0x00000080 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK = 0x00000100 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK = 0x00000600 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK = 0x00003800 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK = 0x0003C000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK = 0x001C0000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK = 0x01E00000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK = 0x06000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK = 0x18000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK = 0x000000FF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK = 0x00FF0000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK = 0xFF000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT = 0x11 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT = 0x13 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT = 0x16 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT = 0x17 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT = 0x19 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT = 0x1a # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT = 0x1b # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK = 0x000000FF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK = 0x00010000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK = 0x00020000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK = 0x00040000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK = 0x00080000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK = 0x00200000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK = 0x00400000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK = 0x00800000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK = 0x01000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK = 0x02000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK = 0x04000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK = 0x08000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK = 0x10000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT = 0x1 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT = 0x2 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT = 0x3 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT = 0x4 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT = 0x5 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT = 0x6 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT = 0x7 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT = 0xc # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT = 0x13 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK = 0x00000001 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK = 0x00000002 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK = 0x00000004 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK = 0x00000008 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK = 0x00000010 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK = 0x00000020 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK = 0x00000040 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK = 0x00000080 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK = 0x00000F00 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK = 0x0000F000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK = 0x00030000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK = 0x00040000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK = 0x00080000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK = 0x00E00000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK = 0x0F000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK = 0xF0000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT = 0xc # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK = 0x000000FF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK = 0x00000F00 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK = 0x0000F000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK = 0x00FF0000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK = 0x1F000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK = 0xE0000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK = 0x000000FF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK = 0x00FF0000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK = 0xFF000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK = 0x000000FF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK = 0xFFFF0000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT = 0x2 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT = 0x3 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT = 0x4 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT = 0x5 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT = 0x6 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK = 0x00000001 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK = 0x00000004 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK = 0x00000008 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK = 0x00000010 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK = 0x00000020 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK = 0x0007FFC0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK = 0x0FFF0000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK = 0x10000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK = 0x00FFFFFF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT = 0x9 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK = 0x000000FF # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK = 0x00000100 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK = 0x000FFE00 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK = 0xFFF00000 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT = 0x2 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT = 0x3 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT = 0x4 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK = 0x00000001 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK = 0x00000004 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK = 0x00000008 # macro +RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK = 0x00000010 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT = 0x1 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT = 0x2 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT = 0x3 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT = 0x6 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT = 0x7 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT = 0x9 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT = 0xa # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT = 0xb # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT = 0xc # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT = 0xd # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0xe # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT = 0xf # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT = 0x11 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT = 0x19 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT = 0x1a # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT = 0x1b # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK = 0x00000001 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK = 0x00000002 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK = 0x00000004 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK = 0x00000038 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK = 0x00000040 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK = 0x00000080 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK = 0x00000100 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK = 0x00000200 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK = 0x00000400 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK = 0x00000800 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK = 0x00001000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK = 0x00002000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00004000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK = 0x00008000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK = 0x00010000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK = 0x00020000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK = 0x000C0000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK = 0x01000000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK = 0x02000000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK = 0x04000000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK = 0x08000000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK = 0x10000000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT = 0x1 # macro +RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT = 0x2 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT = 0x3 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT = 0x5 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT = 0x6 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT = 0x7 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT = 0x9 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT = 0xa # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT = 0xc # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT = 0xd # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT = 0xf # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT = 0x11 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT = 0x13 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT = 0x16 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT = 0x17 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT = 0x19 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT = 0x1a # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT = 0x1b # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK = 0x00000001 # macro +RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK = 0x00000002 # macro +RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE_MASK = 0x00000004 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK = 0x00000008 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK = 0x00000020 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK = 0x00000040 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK = 0x00000080 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK = 0x00000100 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK = 0x00000200 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK = 0x00000C00 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK = 0x00001000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK = 0x00006000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK = 0x00018000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK = 0x00020000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK = 0x00040000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK = 0x00080000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK = 0x00200000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK = 0x00400000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK = 0x00800000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK = 0x01000000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK = 0x02000000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK = 0x04000000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK = 0x18000000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT = 0x3 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT = 0x4 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT = 0x5 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT = 0x6 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN__SHIFT = 0x7 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT = 0x9 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT = 0xa # macro +RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT = 0xd # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT = 0xe # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT = 0xf # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK = 0x00000001 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK = 0x00000008 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK = 0x00000010 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK = 0x00000020 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK = 0x00000040 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN_MASK = 0x00000080 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK = 0x00000100 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK = 0x00000200 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK = 0x00000C00 # macro +RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK = 0x00002000 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK = 0x00004000 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK = 0x00008000 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK = 0x00FF0000 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK = 0x01000000 # macro +RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK = 0xFFFF0000 # macro +RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK = 0xFFFF0000 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT = 0x11 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT = 0x13 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT = 0x16 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x19 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1b # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK = 0x00010000 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK = 0x00020000 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK = 0x00040000 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK = 0x00080000 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK = 0x00200000 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK = 0x00C00000 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK = 0x01000000 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x06000000 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x08000000 # macro +RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK = 0x70000000 # macro +RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT = 0x1 # macro +RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT = 0x2 # macro +RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK = 0x00000001 # macro +RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK = 0x00000002 # macro +RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK = 0x00000004 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK = 0x000F0000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK = 0x00F00000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK = 0x0F000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK = 0x10000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK = 0xFFFF0000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT = 0x6 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT = 0x7 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT = 0x9 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT = 0xe # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT = 0xf # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT = 0x11 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT = 0x16 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT = 0x17 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT = 0x1b # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK = 0x00000001 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK = 0x00000040 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK = 0x00000080 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK = 0x00000100 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK = 0x00003E00 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK = 0x00004000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK = 0x00008000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK = 0x00010000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK = 0x00020000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK = 0x00040000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK = 0x00200000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK = 0x00400000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK = 0x00800000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK = 0x07000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK = 0x08000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK = 0x10000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT = 0x11 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT = 0x13 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT = 0x1a # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT = 0x1b # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK = 0x00010000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK = 0x00020000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK = 0x00040000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK = 0x00080000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK = 0x00E00000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK = 0x01000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK = 0x04000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK = 0x08000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK = 0x10000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT = 0xa # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT = 0x16 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT = 0x17 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK = 0x000003FF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK = 0x00000400 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK = 0x00200000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK = 0x00400000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK = 0x0F800000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK = 0x70000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT = 0x3 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT = 0x4 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT = 0x7 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT = 0x9 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT = 0xd # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT = 0x13 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT = 0x17 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT = 0x1a # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT = 0x1b # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK = 0x00000007 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK = 0x00000008 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK = 0x00000070 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK = 0x00000080 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK = 0x00000100 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK = 0x00001E00 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK = 0x0000E000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK = 0x00070000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK = 0x00780000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK = 0x03800000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK = 0x04000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK = 0x38000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK = 0xC0000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT = 0x13 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT = 0x16 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK = 0x00040000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK = 0x00080000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK = 0x00200000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK = 0x00C00000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK = 0x0F000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK = 0x000000FF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK = 0x0000FF00 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK = 0x00FF0000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK = 0xFF000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT = 0xc # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT = 0x19 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK = 0x00FFF000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK = 0x01000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK = 0x3E000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT = 0xc # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK = 0x00FFF000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT = 0xc # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT = 0xd # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK = 0x00001000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK = 0x01FFE000 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK = 0x000F0000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK = 0x00F00000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK = 0x10000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT = 0x7 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT = 0x8 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT = 0x9 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT = 0xe # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT = 0x11 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT = 0x17 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK = 0x00000080 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK = 0x00000100 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK = 0x00003E00 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK = 0x00004000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK = 0x00010000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK = 0x00020000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK = 0x00200000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK = 0x00800000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK = 0x07000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK = 0x10000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT = 0x10 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT = 0x11 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT = 0x12 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT = 0x13 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT = 0x18 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT = 0x1a # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT = 0x1b # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT = 0x1d # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK = 0x00010000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK = 0x00020000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK = 0x00040000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK = 0x00080000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK = 0x01000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK = 0x04000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK = 0x08000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK = 0x20000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT = 0x15 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT = 0x16 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT = 0x17 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT = 0x1c # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT = 0x1f # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK = 0x00100000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK = 0x00200000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK = 0x00400000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK = 0x0F800000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK = 0x70000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK = 0x80000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT = 0x1b # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK = 0x38000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT = 0x0 # macro +RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK = 0x00000001 # macro +HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT = 0x0 # macro +HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT = 0x1 # macro +HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT = 0x2 # macro +HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT = 0x3 # macro +HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT = 0x4 # macro +HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT = 0x5 # macro +HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT = 0x6 # macro +HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT = 0x7 # macro +HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT = 0x9 # macro +HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT = 0xa # macro +HARD_RST_CTRL__STRAP_RST_EN__SHIFT = 0x17 # macro +HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT = 0x1d # macro +HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT = 0x1e # macro +HARD_RST_CTRL__CORE_RST_EN__SHIFT = 0x1f # macro +HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK = 0x00000001 # macro +HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK = 0x00000002 # macro +HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK = 0x00000004 # macro +HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK = 0x00000008 # macro +HARD_RST_CTRL__EP_CFG_RST_EN_MASK = 0x00000010 # macro +HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK = 0x00000020 # macro +HARD_RST_CTRL__EP_PRV_RST_EN_MASK = 0x00000040 # macro +HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK = 0x00000080 # macro +HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK = 0x00000200 # macro +HARD_RST_CTRL__SION_AON_RESET_EN_MASK = 0x00000400 # macro +HARD_RST_CTRL__STRAP_RST_EN_MASK = 0x00800000 # macro +HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK = 0x20000000 # macro +HARD_RST_CTRL__RELOAD_STRAP_EN_MASK = 0x40000000 # macro +HARD_RST_CTRL__CORE_RST_EN_MASK = 0x80000000 # macro +SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT = 0x0 # macro +SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT = 0x1 # macro +SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT = 0x2 # macro +SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT = 0x3 # macro +SELF_SOFT_RST__EP0_CFG_RST__SHIFT = 0x4 # macro +SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT = 0x5 # macro +SELF_SOFT_RST__EP0_PRV_RST__SHIFT = 0x6 # macro +SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT = 0x7 # macro +SELF_SOFT_RST__HRPU_SDP_PORT_RST__SHIFT = 0x18 # macro +SELF_SOFT_RST__GSID_SDP_PORT_RST__SHIFT = 0x19 # macro +SELF_SOFT_RST__GMIU_SDP_PORT_RST__SHIFT = 0x1a # macro +SELF_SOFT_RST__GMID_SDP_PORT_RST__SHIFT = 0x1b # macro +SELF_SOFT_RST__CORE_STICKY_RST__SHIFT = 0x1d # macro +SELF_SOFT_RST__RELOAD_STRAP__SHIFT = 0x1e # macro +SELF_SOFT_RST__CORE_RST__SHIFT = 0x1f # macro +SELF_SOFT_RST__DSPT0_CFG_RST_MASK = 0x00000001 # macro +SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK = 0x00000002 # macro +SELF_SOFT_RST__DSPT0_PRV_RST_MASK = 0x00000004 # macro +SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK = 0x00000008 # macro +SELF_SOFT_RST__EP0_CFG_RST_MASK = 0x00000010 # macro +SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK = 0x00000020 # macro +SELF_SOFT_RST__EP0_PRV_RST_MASK = 0x00000040 # macro +SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK = 0x00000080 # macro +SELF_SOFT_RST__HRPU_SDP_PORT_RST_MASK = 0x01000000 # macro +SELF_SOFT_RST__GSID_SDP_PORT_RST_MASK = 0x02000000 # macro +SELF_SOFT_RST__GMIU_SDP_PORT_RST_MASK = 0x04000000 # macro +SELF_SOFT_RST__GMID_SDP_PORT_RST_MASK = 0x08000000 # macro +SELF_SOFT_RST__CORE_STICKY_RST_MASK = 0x20000000 # macro +SELF_SOFT_RST__RELOAD_STRAP_MASK = 0x40000000 # macro +SELF_SOFT_RST__CORE_RST_MASK = 0x80000000 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT = 0x0 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT = 0x1 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT = 0x2 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT = 0x3 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT = 0x4 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT = 0x5 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT = 0x6 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT = 0x7 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK = 0x00000001 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK = 0x00000002 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK = 0x00000004 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK = 0x00000008 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK = 0x00000010 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK = 0x00000020 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK = 0x00000040 # macro +BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK = 0x00000080 # macro +BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT = 0x0 # macro +BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT = 0x2 # macro +BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT = 0x4 # macro +BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT = 0x5 # macro +BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT = 0x6 # macro +BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT = 0x8 # macro +BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT = 0x9 # macro +BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT = 0xa # macro +BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT = 0xd # macro +BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT = 0xf # macro +BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT = 0x11 # macro +BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT = 0x17 # macro +BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT = 0x18 # macro +BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK = 0x00000001 # macro +BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK = 0x0000000C # macro +BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK = 0x00000010 # macro +BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK = 0x00000020 # macro +BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK = 0x00000040 # macro +BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK = 0x00000100 # macro +BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK = 0x00000200 # macro +BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK = 0x00001C00 # macro +BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK = 0x00006000 # macro +BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK = 0x00018000 # macro +BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK = 0x000E0000 # macro +BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK = 0x00800000 # macro +BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK = 0x03000000 # macro +BIF_RST_MISC_CTRL2__SWUS_LNK_RST_PROTECT__SHIFT = 0x0 # macro +BIF_RST_MISC_CTRL2__SWDS_LNK_RST_PROTECT__SHIFT = 0x1 # macro +BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_PROTECT__SHIFT = 0x2 # macro +BIF_RST_MISC_CTRL2__ALL_RST_PROTECT__SHIFT = 0xf # macro +BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT = 0x10 # macro +BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT = 0x11 # macro +BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT = 0x12 # macro +BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_DIS__SHIFT = 0x1e # macro +BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT = 0x1f # macro +BIF_RST_MISC_CTRL2__SWUS_LNK_RST_PROTECT_MASK = 0x00000001 # macro +BIF_RST_MISC_CTRL2__SWDS_LNK_RST_PROTECT_MASK = 0x00000002 # macro +BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_PROTECT_MASK = 0x00000004 # macro +BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_MASK = 0x00008000 # macro +BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK = 0x00010000 # macro +BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK = 0x00020000 # macro +BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK = 0x00040000 # macro +BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_DIS_MASK = 0x40000000 # macro +BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK = 0x80000000 # macro +BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT = 0x0 # macro +BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT = 0x4 # macro +BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT = 0x6 # macro +BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT = 0x7 # macro +BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT = 0xa # macro +BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT = 0xd # macro +BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK = 0x0000000F # macro +BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK = 0x00000030 # macro +BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK = 0x00000040 # macro +BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK = 0x00000380 # macro +BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK = 0x00001C00 # macro +BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK = 0x0000E000 # macro +DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT = 0x0 # macro +DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT = 0x1 # macro +DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT = 0x2 # macro +DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT = 0x3 # macro +DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT = 0x4 # macro +DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT = 0x5 # macro +DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT = 0x6 # macro +DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT = 0x7 # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT = 0x8 # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT = 0x9 # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT = 0xa # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT = 0xb # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT = 0xc # macro +DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT = 0xd # macro +DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT = 0xe # macro +DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT = 0xf # macro +DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT = 0x10 # macro +DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT = 0x11 # macro +DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT = 0x12 # macro +DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT = 0x17 # macro +DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT = 0x19 # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT = 0x1f # macro +DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK = 0x00000001 # macro +DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK = 0x00000002 # macro +DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK = 0x00000004 # macro +DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK = 0x00000008 # macro +DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK = 0x00000010 # macro +DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN_MASK = 0x00000020 # macro +DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN_MASK = 0x00000040 # macro +DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN_MASK = 0x00000080 # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK = 0x00000100 # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK = 0x00000200 # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK = 0x00000400 # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK = 0x00000800 # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK = 0x00001000 # macro +DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN_MASK = 0x00002000 # macro +DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN_MASK = 0x00004000 # macro +DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN_MASK = 0x00008000 # macro +DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK = 0x00010000 # macro +DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK = 0x00020000 # macro +DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK = 0x001C0000 # macro +DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK = 0x01800000 # macro +DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK = 0x06000000 # macro +DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK = 0x80000000 # macro +DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT = 0x0 # macro +DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT = 0x1 # macro +DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT = 0x2 # macro +DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT = 0x3 # macro +DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT = 0x4 # macro +DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT = 0x11 # macro +DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT = 0x12 # macro +DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT = 0x17 # macro +DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT = 0x19 # macro +DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK = 0x00000001 # macro +DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK = 0x00000002 # macro +DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK = 0x00000004 # macro +DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK = 0x00000008 # macro +DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK = 0x00000010 # macro +DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK = 0x00020000 # macro +DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK = 0x001C0000 # macro +DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK = 0x01800000 # macro +DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK = 0x06000000 # macro +BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT = 0x0 # macro +BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT = 0x1 # macro +BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT = 0x2 # macro +BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT = 0x3 # macro +BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT = 0x4 # macro +BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK = 0x00000001 # macro +BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK = 0x00000002 # macro +BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK = 0x00000004 # macro +BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK = 0x00000008 # macro +BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK = 0x00000010 # macro +BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT = 0x0 # macro +BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT = 0x1 # macro +BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK = 0x00000001 # macro +BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK = 0x00000002 # macro +BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT = 0x0 # macro +BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT = 0x1 # macro +BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK = 0x00000001 # macro +BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK = 0x00000002 # macro +BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT = 0x0 # macro +BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT = 0x10 # macro +BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK = 0x00000001 # macro +BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK = 0x00010000 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT = 0x0 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT = 0x1 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT = 0x2 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT = 0x3 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT = 0x4 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT = 0x5 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT = 0x6 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT = 0x7 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK = 0x00000001 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK = 0x00000002 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK = 0x00000004 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK = 0x00000008 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK = 0x00000010 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK = 0x00000020 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK = 0x00000040 # macro +BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK = 0x00000080 # macro +SELF_SOFT_RST_2__DSPT3_CFG_RST__SHIFT = 0x0 # macro +SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST__SHIFT = 0x1 # macro +SELF_SOFT_RST_2__DSPT3_PRV_RST__SHIFT = 0x2 # macro +SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST__SHIFT = 0x3 # macro +SELF_SOFT_RST_2__EP3_CFG_RST__SHIFT = 0x4 # macro +SELF_SOFT_RST_2__EP3_CFG_STICKY_RST__SHIFT = 0x5 # macro +SELF_SOFT_RST_2__EP3_PRV_RST__SHIFT = 0x6 # macro +SELF_SOFT_RST_2__EP3_PRV_STICKY_RST__SHIFT = 0x7 # macro +SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST__SHIFT = 0x18 # macro +SELF_SOFT_RST_2__STRAP_RST__SHIFT = 0x19 # macro +SELF_SOFT_RST_2__DSPT3_CFG_RST_MASK = 0x00000001 # macro +SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST_MASK = 0x00000002 # macro +SELF_SOFT_RST_2__DSPT3_PRV_RST_MASK = 0x00000004 # macro +SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST_MASK = 0x00000008 # macro +SELF_SOFT_RST_2__EP3_CFG_RST_MASK = 0x00000010 # macro +SELF_SOFT_RST_2__EP3_CFG_STICKY_RST_MASK = 0x00000020 # macro +SELF_SOFT_RST_2__EP3_PRV_RST_MASK = 0x00000040 # macro +SELF_SOFT_RST_2__EP3_PRV_STICKY_RST_MASK = 0x00000080 # macro +SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST_MASK = 0x01000000 # macro +SELF_SOFT_RST_2__STRAP_RST_MASK = 0x02000000 # macro +BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT = 0x0 # macro +BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT = 0x1 # macro +BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT = 0x2 # macro +BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT = 0x3 # macro +BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT = 0x4 # macro +BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK = 0x00000001 # macro +BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK = 0x00000002 # macro +BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK = 0x00000004 # macro +BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK = 0x00000008 # macro +BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK = 0x00000010 # macro +BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT = 0x0 # macro +BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT = 0x1 # macro +BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK = 0x00000001 # macro +BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK = 0x00000002 # macro +BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT = 0x0 # macro +BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT = 0x1 # macro +BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK = 0x00000001 # macro +BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK = 0x00000002 # macro +BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT = 0x0 # macro +BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT = 0x10 # macro +BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK = 0x00000001 # macro +BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK = 0x00010000 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT = 0x0 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT = 0x1 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT = 0x2 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT = 0x3 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT = 0x4 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT = 0x5 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT = 0x6 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT = 0x7 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK = 0x00000001 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK = 0x00000002 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK = 0x00000004 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK = 0x00000008 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK = 0x00000010 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK = 0x00000020 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK = 0x00000040 # macro +BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK = 0x00000080 # macro +BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT = 0x0 # macro +BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT = 0x1 # macro +BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK = 0x00000001 # macro +BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK = 0x00000002 # macro +BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT = 0x0 # macro +BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT = 0x2 # macro +BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT = 0x10 # macro +BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK = 0x00000003 # macro +BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK = 0x00000004 # macro +BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK = 0x00030000 # macro +BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT = 0x0 # macro +BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT = 0x2 # macro +BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT = 0x10 # macro +BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK = 0x00000003 # macro +BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK = 0x00000004 # macro +BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK = 0x00030000 # macro +DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT = 0x0 # macro +DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT = 0x1 # macro +DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT = 0x2 # macro +DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT = 0x3 # macro +DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT = 0x4 # macro +DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK = 0x00000001 # macro +DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK = 0x00000002 # macro +DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK = 0x00000004 # macro +DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK = 0x00000008 # macro +DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK = 0x00000010 # macro +DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT = 0x0 # macro +DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT = 0x1 # macro +DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT = 0x2 # macro +DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT = 0x3 # macro +DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT = 0x4 # macro +DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK = 0x00000001 # macro +DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK = 0x00000002 # macro +DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK = 0x00000004 # macro +DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK = 0x00000008 # macro +DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK = 0x00000010 # macro +BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT = 0x0 # macro +BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT = 0x10 # macro +BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK = 0x00000003 # macro +BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK = 0x00030000 # macro +REGS_ROM_OFFSET_CTRL__ROM_OFFSET__SHIFT = 0x0 # macro +REGS_ROM_OFFSET_CTRL__ROM_OFFSET_MASK = 0x7F # macro +NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN__SHIFT = 0x0 # macro +NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN__SHIFT = 0x1 # macro +NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN_MASK = 0x00000001 # macro +NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN_MASK = 0x00000002 # macro +DOORBELL0_CTRL_ENTRY_0__BIF_DOORBELL0_RANGE_OFFSET_ENTRY__SHIFT = 0x0 # macro +DOORBELL0_CTRL_ENTRY_0__BIF_DOORBELL0_RANGE_SIZE_ENTRY__SHIFT = 0xa # macro +DOORBELL0_CTRL_ENTRY_0__DOORBELL0_FENCE_ENABLE_ENTRY__SHIFT = 0x10 # macro +DOORBELL0_CTRL_ENTRY_0__BIF_DOORBELL0_RANGE_OFFSET_ENTRY_MASK = 0x000003FF # macro +DOORBELL0_CTRL_ENTRY_0__BIF_DOORBELL0_RANGE_SIZE_ENTRY_MASK = 0x00007C00 # macro +DOORBELL0_CTRL_ENTRY_0__DOORBELL0_FENCE_ENABLE_ENTRY_MASK = 0x001F0000 # macro +DOORBELL0_CTRL_ENTRY_1__BIF_DOORBELL1_RANGE_OFFSET_ENTRY__SHIFT = 0x0 # macro +DOORBELL0_CTRL_ENTRY_1__BIF_DOORBELL1_RANGE_SIZE_ENTRY__SHIFT = 0xa # macro +DOORBELL0_CTRL_ENTRY_1__DOORBELL1_FENCE_ENABLE_ENTRY__SHIFT = 0x10 # macro +DOORBELL0_CTRL_ENTRY_1__BIF_DOORBELL1_RANGE_OFFSET_ENTRY_MASK = 0x000003FF # macro +DOORBELL0_CTRL_ENTRY_1__BIF_DOORBELL1_RANGE_SIZE_ENTRY_MASK = 0x00007C00 # macro +DOORBELL0_CTRL_ENTRY_1__DOORBELL1_FENCE_ENABLE_ENTRY_MASK = 0x001F0000 # macro +DOORBELL0_CTRL_ENTRY_2__BIF_DOORBELL2_RANGE_OFFSET_ENTRY__SHIFT = 0x0 # macro +DOORBELL0_CTRL_ENTRY_2__BIF_DOORBELL2_RANGE_SIZE_ENTRY__SHIFT = 0xa # macro +DOORBELL0_CTRL_ENTRY_2__DOORBELL2_FENCE_ENABLE_ENTRY__SHIFT = 0x10 # macro +DOORBELL0_CTRL_ENTRY_2__BIF_DOORBELL2_RANGE_OFFSET_ENTRY_MASK = 0x000003FF # macro +DOORBELL0_CTRL_ENTRY_2__BIF_DOORBELL2_RANGE_SIZE_ENTRY_MASK = 0x00007C00 # macro +DOORBELL0_CTRL_ENTRY_2__DOORBELL2_FENCE_ENABLE_ENTRY_MASK = 0x001F0000 # macro +DOORBELL0_CTRL_ENTRY_3__BIF_DOORBELL3_RANGE_OFFSET_ENTRY__SHIFT = 0x0 # macro +DOORBELL0_CTRL_ENTRY_3__BIF_DOORBELL3_RANGE_SIZE_ENTRY__SHIFT = 0xa # macro +DOORBELL0_CTRL_ENTRY_3__DOORBELL3_FENCE_ENABLE_ENTRY__SHIFT = 0x10 # macro +DOORBELL0_CTRL_ENTRY_3__BIF_DOORBELL3_RANGE_OFFSET_ENTRY_MASK = 0x000003FF # macro +DOORBELL0_CTRL_ENTRY_3__BIF_DOORBELL3_RANGE_SIZE_ENTRY_MASK = 0x00007C00 # macro +DOORBELL0_CTRL_ENTRY_3__DOORBELL3_FENCE_ENABLE_ENTRY_MASK = 0x001F0000 # macro +DOORBELL0_CTRL_ENTRY_4__BIF_DOORBELL4_RANGE_OFFSET_ENTRY__SHIFT = 0x0 # macro +DOORBELL0_CTRL_ENTRY_4__BIF_DOORBELL4_RANGE_SIZE_ENTRY__SHIFT = 0xa # macro +DOORBELL0_CTRL_ENTRY_4__DOORBELL4_FENCE_ENABLE_ENTRY__SHIFT = 0x10 # macro +DOORBELL0_CTRL_ENTRY_4__BIF_DOORBELL4_RANGE_OFFSET_ENTRY_MASK = 0x000003FF # macro +DOORBELL0_CTRL_ENTRY_4__BIF_DOORBELL4_RANGE_SIZE_ENTRY_MASK = 0x00007C00 # macro +DOORBELL0_CTRL_ENTRY_4__DOORBELL4_FENCE_ENABLE_ENTRY_MASK = 0x001F0000 # macro +DOORBELL0_CTRL_ENTRY_5__BIF_DOORBELL5_RANGE_OFFSET_ENTRY__SHIFT = 0x0 # macro +DOORBELL0_CTRL_ENTRY_5__BIF_DOORBELL5_RANGE_SIZE_ENTRY__SHIFT = 0xa # macro +DOORBELL0_CTRL_ENTRY_5__DOORBELL5_FENCE_ENABLE_ENTRY__SHIFT = 0x10 # macro +DOORBELL0_CTRL_ENTRY_5__BIF_DOORBELL5_RANGE_OFFSET_ENTRY_MASK = 0x000003FF # macro +DOORBELL0_CTRL_ENTRY_5__BIF_DOORBELL5_RANGE_SIZE_ENTRY_MASK = 0x00007C00 # macro +DOORBELL0_CTRL_ENTRY_5__DOORBELL5_FENCE_ENABLE_ENTRY_MASK = 0x001F0000 # macro +DOORBELL0_CTRL_ENTRY_6__BIF_DOORBELL6_RANGE_OFFSET_ENTRY__SHIFT = 0x0 # macro +DOORBELL0_CTRL_ENTRY_6__BIF_DOORBELL6_RANGE_SIZE_ENTRY__SHIFT = 0xa # macro +DOORBELL0_CTRL_ENTRY_6__DOORBELL6_FENCE_ENABLE_ENTRY__SHIFT = 0x10 # macro +DOORBELL0_CTRL_ENTRY_6__BIF_DOORBELL6_RANGE_OFFSET_ENTRY_MASK = 0x000003FF # macro +DOORBELL0_CTRL_ENTRY_6__BIF_DOORBELL6_RANGE_SIZE_ENTRY_MASK = 0x00007C00 # macro +DOORBELL0_CTRL_ENTRY_6__DOORBELL6_FENCE_ENABLE_ENTRY_MASK = 0x001F0000 # macro +DOORBELL0_CTRL_ENTRY_7__BIF_DOORBELL7_RANGE_OFFSET_ENTRY__SHIFT = 0x0 # macro +DOORBELL0_CTRL_ENTRY_7__BIF_DOORBELL7_RANGE_SIZE_ENTRY__SHIFT = 0xa # macro +DOORBELL0_CTRL_ENTRY_7__DOORBELL7_FENCE_ENABLE_ENTRY__SHIFT = 0x10 # macro +DOORBELL0_CTRL_ENTRY_7__BIF_DOORBELL7_RANGE_OFFSET_ENTRY_MASK = 0x000003FF # macro +DOORBELL0_CTRL_ENTRY_7__BIF_DOORBELL7_RANGE_SIZE_ENTRY_MASK = 0x00007C00 # macro +DOORBELL0_CTRL_ENTRY_7__DOORBELL7_FENCE_ENABLE_ENTRY_MASK = 0x001F0000 # macro +DOORBELL0_CTRL_ENTRY_8__BIF_DOORBELL8_RANGE_OFFSET_ENTRY__SHIFT = 0x0 # macro +DOORBELL0_CTRL_ENTRY_8__BIF_DOORBELL8_RANGE_SIZE_ENTRY__SHIFT = 0xa # macro +DOORBELL0_CTRL_ENTRY_8__DOORBELL8_FENCE_ENABLE_ENTRY__SHIFT = 0x10 # macro +DOORBELL0_CTRL_ENTRY_8__BIF_DOORBELL8_RANGE_OFFSET_ENTRY_MASK = 0x000003FF # macro +DOORBELL0_CTRL_ENTRY_8__BIF_DOORBELL8_RANGE_SIZE_ENTRY_MASK = 0x00007C00 # macro +DOORBELL0_CTRL_ENTRY_8__DOORBELL8_FENCE_ENABLE_ENTRY_MASK = 0x001F0000 # macro +DOORBELL0_CTRL_ENTRY_9__BIF_DOORBELL9_RANGE_OFFSET_ENTRY__SHIFT = 0x0 # macro +DOORBELL0_CTRL_ENTRY_9__BIF_DOORBELL9_RANGE_SIZE_ENTRY__SHIFT = 0xa # macro +DOORBELL0_CTRL_ENTRY_9__DOORBELL9_FENCE_ENABLE_ENTRY__SHIFT = 0x10 # macro +DOORBELL0_CTRL_ENTRY_9__BIF_DOORBELL9_RANGE_OFFSET_ENTRY_MASK = 0x000003FF # macro +DOORBELL0_CTRL_ENTRY_9__BIF_DOORBELL9_RANGE_SIZE_ENTRY_MASK = 0x00007C00 # macro +DOORBELL0_CTRL_ENTRY_9__DOORBELL9_FENCE_ENABLE_ENTRY_MASK = 0x001F0000 # macro +DOORBELL0_CTRL_ENTRY_10__BIF_DOORBELL10_RANGE_OFFSET_ENTRY__SHIFT = 0x0 # macro +DOORBELL0_CTRL_ENTRY_10__BIF_DOORBELL10_RANGE_SIZE_ENTRY__SHIFT = 0xa # macro +DOORBELL0_CTRL_ENTRY_10__DOORBELL10_FENCE_ENABLE_ENTRY__SHIFT = 0x10 # macro +DOORBELL0_CTRL_ENTRY_10__BIF_DOORBELL10_RANGE_OFFSET_ENTRY_MASK = 0x000003FF # macro +DOORBELL0_CTRL_ENTRY_10__BIF_DOORBELL10_RANGE_SIZE_ENTRY_MASK = 0x00007C00 # macro +DOORBELL0_CTRL_ENTRY_10__DOORBELL10_FENCE_ENABLE_ENTRY_MASK = 0x001F0000 # macro +DOORBELL0_CTRL_ENTRY_11__BIF_DOORBELL11_RANGE_OFFSET_ENTRY__SHIFT = 0x0 # macro +DOORBELL0_CTRL_ENTRY_11__BIF_DOORBELL11_RANGE_SIZE_ENTRY__SHIFT = 0xa # macro +DOORBELL0_CTRL_ENTRY_11__DOORBELL11_FENCE_ENABLE_ENTRY__SHIFT = 0x10 # macro +DOORBELL0_CTRL_ENTRY_11__BIF_DOORBELL11_RANGE_OFFSET_ENTRY_MASK = 0x000003FF # macro +DOORBELL0_CTRL_ENTRY_11__BIF_DOORBELL11_RANGE_SIZE_ENTRY_MASK = 0x00007C00 # macro +DOORBELL0_CTRL_ENTRY_11__DOORBELL11_FENCE_ENABLE_ENTRY_MASK = 0x001F0000 # macro +DOORBELL0_CTRL_ENTRY_12__BIF_DOORBELL12_RANGE_OFFSET_ENTRY__SHIFT = 0x0 # macro +DOORBELL0_CTRL_ENTRY_12__BIF_DOORBELL12_RANGE_SIZE_ENTRY__SHIFT = 0xa # macro +DOORBELL0_CTRL_ENTRY_12__DOORBELL12_FENCE_ENABLE_ENTRY__SHIFT = 0x10 # macro +DOORBELL0_CTRL_ENTRY_12__BIF_DOORBELL12_RANGE_OFFSET_ENTRY_MASK = 0x000003FF # macro +DOORBELL0_CTRL_ENTRY_12__BIF_DOORBELL12_RANGE_SIZE_ENTRY_MASK = 0x00007C00 # macro +DOORBELL0_CTRL_ENTRY_12__DOORBELL12_FENCE_ENABLE_ENTRY_MASK = 0x001F0000 # macro +DOORBELL0_CTRL_ENTRY_13__BIF_DOORBELL13_RANGE_OFFSET_ENTRY__SHIFT = 0x0 # macro +DOORBELL0_CTRL_ENTRY_13__BIF_DOORBELL13_RANGE_SIZE_ENTRY__SHIFT = 0xa # macro +DOORBELL0_CTRL_ENTRY_13__DOORBELL13_FENCE_ENABLE_ENTRY__SHIFT = 0x10 # macro +DOORBELL0_CTRL_ENTRY_13__BIF_DOORBELL13_RANGE_OFFSET_ENTRY_MASK = 0x000003FF # macro +DOORBELL0_CTRL_ENTRY_13__BIF_DOORBELL13_RANGE_SIZE_ENTRY_MASK = 0x00007C00 # macro +DOORBELL0_CTRL_ENTRY_13__DOORBELL13_FENCE_ENABLE_ENTRY_MASK = 0x001F0000 # macro +DOORBELL0_CTRL_ENTRY_14__BIF_DOORBELL14_RANGE_OFFSET_ENTRY__SHIFT = 0x0 # macro +DOORBELL0_CTRL_ENTRY_14__BIF_DOORBELL14_RANGE_SIZE_ENTRY__SHIFT = 0xa # macro +DOORBELL0_CTRL_ENTRY_14__DOORBELL14_FENCE_ENABLE_ENTRY__SHIFT = 0x10 # macro +DOORBELL0_CTRL_ENTRY_14__BIF_DOORBELL14_RANGE_OFFSET_ENTRY_MASK = 0x000003FF # macro +DOORBELL0_CTRL_ENTRY_14__BIF_DOORBELL14_RANGE_SIZE_ENTRY_MASK = 0x00007C00 # macro +DOORBELL0_CTRL_ENTRY_14__DOORBELL14_FENCE_ENABLE_ENTRY_MASK = 0x001F0000 # macro +DOORBELL0_CTRL_ENTRY_15__BIF_DOORBELL15_RANGE_OFFSET_ENTRY__SHIFT = 0x0 # macro +DOORBELL0_CTRL_ENTRY_15__BIF_DOORBELL15_RANGE_SIZE_ENTRY__SHIFT = 0xa # macro +DOORBELL0_CTRL_ENTRY_15__DOORBELL15_FENCE_ENABLE_ENTRY__SHIFT = 0x10 # macro +DOORBELL0_CTRL_ENTRY_15__BIF_DOORBELL15_RANGE_OFFSET_ENTRY_MASK = 0x000003FF # macro +DOORBELL0_CTRL_ENTRY_15__BIF_DOORBELL15_RANGE_SIZE_ENTRY_MASK = 0x00007C00 # macro +DOORBELL0_CTRL_ENTRY_15__DOORBELL15_FENCE_ENABLE_ENTRY_MASK = 0x001F0000 # macro +DOORBELL0_CTRL_ENTRY_16__BIF_DOORBELL16_RANGE_OFFSET_ENTRY__SHIFT = 0x0 # macro +DOORBELL0_CTRL_ENTRY_16__BIF_DOORBELL16_RANGE_SIZE_ENTRY__SHIFT = 0xa # macro +DOORBELL0_CTRL_ENTRY_16__DOORBELL16_FENCE_ENABLE_ENTRY__SHIFT = 0x10 # macro +DOORBELL0_CTRL_ENTRY_16__BIF_DOORBELL16_RANGE_OFFSET_ENTRY_MASK = 0x000003FF # macro +DOORBELL0_CTRL_ENTRY_16__BIF_DOORBELL16_RANGE_SIZE_ENTRY_MASK = 0x00007C00 # macro +DOORBELL0_CTRL_ENTRY_16__DOORBELL16_FENCE_ENABLE_ENTRY_MASK = 0x001F0000 # macro +DOORBELL0_CTRL_ENTRY_17__BIF_DOORBELL17_RANGE_OFFSET_ENTRY__SHIFT = 0x0 # macro +DOORBELL0_CTRL_ENTRY_17__BIF_DOORBELL17_RANGE_SIZE_ENTRY__SHIFT = 0xa # macro +DOORBELL0_CTRL_ENTRY_17__DOORBELL17_FENCE_ENABLE_ENTRY__SHIFT = 0x10 # macro +DOORBELL0_CTRL_ENTRY_17__BIF_DOORBELL17_RANGE_OFFSET_ENTRY_MASK = 0x000003FF # macro +DOORBELL0_CTRL_ENTRY_17__BIF_DOORBELL17_RANGE_SIZE_ENTRY_MASK = 0x00007C00 # macro +DOORBELL0_CTRL_ENTRY_17__DOORBELL17_FENCE_ENABLE_ENTRY_MASK = 0x001F0000 # macro +DOORBELL0_CTRL_ENTRY_18__BIF_DOORBELL18_RANGE_OFFSET_ENTRY__SHIFT = 0x0 # macro +DOORBELL0_CTRL_ENTRY_18__BIF_DOORBELL18_RANGE_SIZE_ENTRY__SHIFT = 0xa # macro +DOORBELL0_CTRL_ENTRY_18__DOORBELL18_FENCE_ENABLE_ENTRY__SHIFT = 0x10 # macro +DOORBELL0_CTRL_ENTRY_18__BIF_DOORBELL18_RANGE_OFFSET_ENTRY_MASK = 0x000003FF # macro +DOORBELL0_CTRL_ENTRY_18__BIF_DOORBELL18_RANGE_SIZE_ENTRY_MASK = 0x00007C00 # macro +DOORBELL0_CTRL_ENTRY_18__DOORBELL18_FENCE_ENABLE_ENTRY_MASK = 0x001F0000 # macro +DOORBELL0_CTRL_ENTRY_19__BIF_DOORBELL19_RANGE_OFFSET_ENTRY__SHIFT = 0x0 # macro +DOORBELL0_CTRL_ENTRY_19__BIF_DOORBELL19_RANGE_SIZE_ENTRY__SHIFT = 0xa # macro +DOORBELL0_CTRL_ENTRY_19__DOORBELL19_FENCE_ENABLE_ENTRY__SHIFT = 0x10 # macro +DOORBELL0_CTRL_ENTRY_19__BIF_DOORBELL19_RANGE_OFFSET_ENTRY_MASK = 0x000003FF # macro +DOORBELL0_CTRL_ENTRY_19__BIF_DOORBELL19_RANGE_SIZE_ENTRY_MASK = 0x00007C00 # macro +DOORBELL0_CTRL_ENTRY_19__DOORBELL19_FENCE_ENABLE_ENTRY_MASK = 0x001F0000 # macro +DOORBELL0_CTRL_ENTRY_20__BIF_DOORBELL20_RANGE_OFFSET_ENTRY__SHIFT = 0x0 # macro +DOORBELL0_CTRL_ENTRY_20__BIF_DOORBELL20_RANGE_SIZE_ENTRY__SHIFT = 0xa # macro +DOORBELL0_CTRL_ENTRY_20__DOORBELL20_FENCE_ENABLE_ENTRY__SHIFT = 0x10 # macro +DOORBELL0_CTRL_ENTRY_20__BIF_DOORBELL20_RANGE_OFFSET_ENTRY_MASK = 0x000003FF # macro +DOORBELL0_CTRL_ENTRY_20__BIF_DOORBELL20_RANGE_SIZE_ENTRY_MASK = 0x00007C00 # macro +DOORBELL0_CTRL_ENTRY_20__DOORBELL20_FENCE_ENABLE_ENTRY_MASK = 0x001F0000 # macro +AID0_VF0_BASE_ADDR__AID0_VF0_BASE_ADDR__SHIFT = 0x0 # macro +AID0_VF0_BASE_ADDR__AID0_VF0_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_VF0_BASE_ADDR__AID1_VF0_BASE_ADDR__SHIFT = 0x0 # macro +AID1_VF0_BASE_ADDR__AID1_VF0_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_VF0_BASE_ADDR__AID2_VF0_BASE_ADDR__SHIFT = 0x0 # macro +AID2_VF0_BASE_ADDR__AID2_VF0_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_VF0_BASE_ADDR__AID3_VF0_BASE_ADDR__SHIFT = 0x0 # macro +AID3_VF0_BASE_ADDR__AID3_VF0_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_XCC0_VF0_BASE_ADDR__AID0_XCC0_VF0_BASE_ADDR__SHIFT = 0x0 # macro +AID0_XCC0_VF0_BASE_ADDR__AID0_XCC0_VF0_BASE_ADDR_MASK = 0x0001FFFF # macro +AID0_XCC1_VF0_BASE_ADDR__AID0_XCC1_VF0_BASE_ADDR__SHIFT = 0x0 # macro +AID0_XCC1_VF0_BASE_ADDR__AID0_XCC1_VF0_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_XCC0_VF0_BASE_ADDR__AID1_XCC0_VF0_BASE_ADDR__SHIFT = 0x0 # macro +AID1_XCC0_VF0_BASE_ADDR__AID1_XCC0_VF0_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_XCC1_VF0_BASE_ADDR__AID1_XCC1_VF0_BASE_ADDR__SHIFT = 0x0 # macro +AID1_XCC1_VF0_BASE_ADDR__AID1_XCC1_VF0_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_XCC0_VF0_BASE_ADDR__AID2_XCC0_VF0_BASE_ADDR__SHIFT = 0x0 # macro +AID2_XCC0_VF0_BASE_ADDR__AID2_XCC0_VF0_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_XCC1_VF0_BASE_ADDR__AID2_XCC1_VF0_BASE_ADDR__SHIFT = 0x0 # macro +AID2_XCC1_VF0_BASE_ADDR__AID2_XCC1_VF0_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_XCC0_VF0_BASE_ADDR__AID3_XCC0_VF0_BASE_ADDR__SHIFT = 0x0 # macro +AID3_XCC0_VF0_BASE_ADDR__AID3_XCC0_VF0_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_XCC1_VF0_BASE_ADDR__AID3_XCC1_VF0_BASE_ADDR__SHIFT = 0x0 # macro +AID3_XCC1_VF0_BASE_ADDR__AID3_XCC1_VF0_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_NBIF_VF0_BASE_ADDR__AID0_NBIF_VF0_BASE_ADDR__SHIFT = 0x0 # macro +AID0_NBIF_VF0_BASE_ADDR__AID0_NBIF_VF0_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_ATHUB_VF0_BASE_ADDR__AID0_ATHUB_VF0_BASE_ADDR__SHIFT = 0x0 # macro +AID0_ATHUB_VF0_BASE_ADDR__AID0_ATHUB_VF0_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_IH_VF0_BASE_ADDR__AID0_IH_VF0_BASE_ADDR__SHIFT = 0x0 # macro +AID0_IH_VF0_BASE_ADDR__AID0_IH_VF0_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_HDP_VF0_BASE_ADDR__AID0_HDP_VF0_BASE_ADDR__SHIFT = 0x0 # macro +AID0_HDP_VF0_BASE_ADDR__AID0_HDP_VF0_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_VF1_BASE_ADDR__AID0_VF1_BASE_ADDR__SHIFT = 0x0 # macro +AID0_VF1_BASE_ADDR__AID0_VF1_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_VF1_BASE_ADDR__AID1_VF1_BASE_ADDR__SHIFT = 0x0 # macro +AID1_VF1_BASE_ADDR__AID1_VF1_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_VF1_BASE_ADDR__AID2_VF1_BASE_ADDR__SHIFT = 0x0 # macro +AID2_VF1_BASE_ADDR__AID2_VF1_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_VF1_BASE_ADDR__AID3_VF1_BASE_ADDR__SHIFT = 0x0 # macro +AID3_VF1_BASE_ADDR__AID3_VF1_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_XCC0_VF1_BASE_ADDR__AID0_XCC0_VF1_BASE_ADDR__SHIFT = 0x0 # macro +AID0_XCC0_VF1_BASE_ADDR__AID0_XCC0_VF1_BASE_ADDR_MASK = 0x0001FFFF # macro +AID0_XCC1_VF1_BASE_ADDR__AID0_XCC1_VF1_BASE_ADDR__SHIFT = 0x0 # macro +AID0_XCC1_VF1_BASE_ADDR__AID0_XCC1_VF1_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_XCC0_VF1_BASE_ADDR__AID1_XCC0_VF1_BASE_ADDR__SHIFT = 0x0 # macro +AID1_XCC0_VF1_BASE_ADDR__AID1_XCC0_VF1_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_XCC1_VF1_BASE_ADDR__AID1_XCC1_VF1_BASE_ADDR__SHIFT = 0x0 # macro +AID1_XCC1_VF1_BASE_ADDR__AID1_XCC1_VF1_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_XCC0_VF1_BASE_ADDR__AID2_XCC0_VF1_BASE_ADDR__SHIFT = 0x0 # macro +AID2_XCC0_VF1_BASE_ADDR__AID2_XCC0_VF1_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_XCC1_VF1_BASE_ADDR__AID2_XCC1_VF1_BASE_ADDR__SHIFT = 0x0 # macro +AID2_XCC1_VF1_BASE_ADDR__AID2_XCC1_VF1_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_XCC0_VF1_BASE_ADDR__AID3_XCC0_VF1_BASE_ADDR__SHIFT = 0x0 # macro +AID3_XCC0_VF1_BASE_ADDR__AID3_XCC0_VF1_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_XCC1_VF1_BASE_ADDR__AID3_XCC1_VF1_BASE_ADDR__SHIFT = 0x0 # macro +AID3_XCC1_VF1_BASE_ADDR__AID3_XCC1_VF1_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_NBIF_VF1_BASE_ADDR__AID0_NBIF_VF1_BASE_ADDR__SHIFT = 0x0 # macro +AID0_NBIF_VF1_BASE_ADDR__AID0_NBIF_VF1_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_ATHUB_VF1_BASE_ADDR__AID0_ATHUB_VF1_BASE_ADDR__SHIFT = 0x0 # macro +AID0_ATHUB_VF1_BASE_ADDR__AID0_ATHUB_VF1_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_IH_VF1_BASE_ADDR__AID0_IH_VF1_BASE_ADDR__SHIFT = 0x0 # macro +AID0_IH_VF1_BASE_ADDR__AID0_IH_VF1_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_HDP_VF1_BASE_ADDR__AID0_HDP_VF1_BASE_ADDR__SHIFT = 0x0 # macro +AID0_HDP_VF1_BASE_ADDR__AID0_HDP_VF1_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_VF2_BASE_ADDR__AID0_VF2_BASE_ADDR__SHIFT = 0x0 # macro +AID0_VF2_BASE_ADDR__AID0_VF2_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_VF2_BASE_ADDR__AID1_VF2_BASE_ADDR__SHIFT = 0x0 # macro +AID1_VF2_BASE_ADDR__AID1_VF2_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_VF2_BASE_ADDR__AID2_VF2_BASE_ADDR__SHIFT = 0x0 # macro +AID2_VF2_BASE_ADDR__AID2_VF2_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_VF2_BASE_ADDR__AID3_VF2_BASE_ADDR__SHIFT = 0x0 # macro +AID3_VF2_BASE_ADDR__AID3_VF2_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_XCC0_VF2_BASE_ADDR__AID0_XCC0_VF2_BASE_ADDR__SHIFT = 0x0 # macro +AID0_XCC0_VF2_BASE_ADDR__AID0_XCC0_VF2_BASE_ADDR_MASK = 0x0001FFFF # macro +AID0_XCC1_VF2_BASE_ADDR__AID0_XCC1_VF2_BASE_ADDR__SHIFT = 0x0 # macro +AID0_XCC1_VF2_BASE_ADDR__AID0_XCC1_VF2_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_XCC0_VF2_BASE_ADDR__AID1_XCC0_VF2_BASE_ADDR__SHIFT = 0x0 # macro +AID1_XCC0_VF2_BASE_ADDR__AID1_XCC0_VF2_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_XCC1_VF2_BASE_ADDR__AID1_XCC1_VF2_BASE_ADDR__SHIFT = 0x0 # macro +AID1_XCC1_VF2_BASE_ADDR__AID1_XCC1_VF2_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_XCC0_VF2_BASE_ADDR__AID2_XCC0_VF2_BASE_ADDR__SHIFT = 0x0 # macro +AID2_XCC0_VF2_BASE_ADDR__AID2_XCC0_VF2_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_XCC1_VF2_BASE_ADDR__AID2_XCC1_VF2_BASE_ADDR__SHIFT = 0x0 # macro +AID2_XCC1_VF2_BASE_ADDR__AID2_XCC1_VF2_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_XCC0_VF2_BASE_ADDR__AID3_XCC0_VF2_BASE_ADDR__SHIFT = 0x0 # macro +AID3_XCC0_VF2_BASE_ADDR__AID3_XCC0_VF2_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_XCC1_VF2_BASE_ADDR__AID3_XCC1_VF2_BASE_ADDR__SHIFT = 0x0 # macro +AID3_XCC1_VF2_BASE_ADDR__AID3_XCC1_VF2_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_NBIF_VF2_BASE_ADDR__AID0_NBIF_VF2_BASE_ADDR__SHIFT = 0x0 # macro +AID0_NBIF_VF2_BASE_ADDR__AID0_NBIF_VF2_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_ATHUB_VF2_BASE_ADDR__AID0_ATHUB_VF2_BASE_ADDR__SHIFT = 0x0 # macro +AID0_ATHUB_VF2_BASE_ADDR__AID0_ATHUB_VF2_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_IH_VF2_BASE_ADDR__AID0_IH_VF2_BASE_ADDR__SHIFT = 0x0 # macro +AID0_IH_VF2_BASE_ADDR__AID0_IH_VF2_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_HDP_VF2_BASE_ADDR__AID0_HDP_VF2_BASE_ADDR__SHIFT = 0x0 # macro +AID0_HDP_VF2_BASE_ADDR__AID0_HDP_VF2_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_VF3_BASE_ADDR__AID0_VF3_BASE_ADDR__SHIFT = 0x0 # macro +AID0_VF3_BASE_ADDR__AID0_VF3_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_VF3_BASE_ADDR__AID1_VF3_BASE_ADDR__SHIFT = 0x0 # macro +AID1_VF3_BASE_ADDR__AID1_VF3_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_VF3_BASE_ADDR__AID2_VF3_BASE_ADDR__SHIFT = 0x0 # macro +AID2_VF3_BASE_ADDR__AID2_VF3_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_VF3_BASE_ADDR__AID3_VF3_BASE_ADDR__SHIFT = 0x0 # macro +AID3_VF3_BASE_ADDR__AID3_VF3_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_XCC0_VF3_BASE_ADDR__AID0_XCC0_VF3_BASE_ADDR__SHIFT = 0x0 # macro +AID0_XCC0_VF3_BASE_ADDR__AID0_XCC0_VF3_BASE_ADDR_MASK = 0x0001FFFF # macro +AID0_XCC1_VF3_BASE_ADDR__AID0_XCC1_VF3_BASE_ADDR__SHIFT = 0x0 # macro +AID0_XCC1_VF3_BASE_ADDR__AID0_XCC1_VF3_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_XCC0_VF3_BASE_ADDR__AID1_XCC0_VF3_BASE_ADDR__SHIFT = 0x0 # macro +AID1_XCC0_VF3_BASE_ADDR__AID1_XCC0_VF3_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_XCC1_VF3_BASE_ADDR__AID1_XCC1_VF3_BASE_ADDR__SHIFT = 0x0 # macro +AID1_XCC1_VF3_BASE_ADDR__AID1_XCC1_VF3_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_XCC0_VF3_BASE_ADDR__AID2_XCC0_VF3_BASE_ADDR__SHIFT = 0x0 # macro +AID2_XCC0_VF3_BASE_ADDR__AID2_XCC0_VF3_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_XCC1_VF3_BASE_ADDR__AID2_XCC1_VF3_BASE_ADDR__SHIFT = 0x0 # macro +AID2_XCC1_VF3_BASE_ADDR__AID2_XCC1_VF3_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_XCC0_VF3_BASE_ADDR__AID3_XCC0_VF3_BASE_ADDR__SHIFT = 0x0 # macro +AID3_XCC0_VF3_BASE_ADDR__AID3_XCC0_VF3_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_XCC1_VF3_BASE_ADDR__AID3_XCC1_VF3_BASE_ADDR__SHIFT = 0x0 # macro +AID3_XCC1_VF3_BASE_ADDR__AID3_XCC1_VF3_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_NBIF_VF3_BASE_ADDR__AID0_NBIF_VF3_BASE_ADDR__SHIFT = 0x0 # macro +AID0_NBIF_VF3_BASE_ADDR__AID0_NBIF_VF3_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_ATHUB_VF3_BASE_ADDR__AID0_ATHUB_VF3_BASE_ADDR__SHIFT = 0x0 # macro +AID0_ATHUB_VF3_BASE_ADDR__AID0_ATHUB_VF3_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_IH_VF3_BASE_ADDR__AID0_IH_VF3_BASE_ADDR__SHIFT = 0x0 # macro +AID0_IH_VF3_BASE_ADDR__AID0_IH_VF3_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_HDP_VF3_BASE_ADDR__AID0_HDP_VF3_BASE_ADDR__SHIFT = 0x0 # macro +AID0_HDP_VF3_BASE_ADDR__AID0_HDP_VF3_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_VF4_BASE_ADDR__AID0_VF4_BASE_ADDR__SHIFT = 0x0 # macro +AID0_VF4_BASE_ADDR__AID0_VF4_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_VF4_BASE_ADDR__AID1_VF4_BASE_ADDR__SHIFT = 0x0 # macro +AID1_VF4_BASE_ADDR__AID1_VF4_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_VF4_BASE_ADDR__AID2_VF4_BASE_ADDR__SHIFT = 0x0 # macro +AID2_VF4_BASE_ADDR__AID2_VF4_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_VF4_BASE_ADDR__AID3_VF4_BASE_ADDR__SHIFT = 0x0 # macro +AID3_VF4_BASE_ADDR__AID3_VF4_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_XCC0_VF4_BASE_ADDR__AID0_XCC0_VF4_BASE_ADDR__SHIFT = 0x0 # macro +AID0_XCC0_VF4_BASE_ADDR__AID0_XCC0_VF4_BASE_ADDR_MASK = 0x0001FFFF # macro +AID0_XCC1_VF4_BASE_ADDR__AID0_XCC1_VF4_BASE_ADDR__SHIFT = 0x0 # macro +AID0_XCC1_VF4_BASE_ADDR__AID0_XCC1_VF4_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_XCC0_VF4_BASE_ADDR__AID1_XCC0_VF4_BASE_ADDR__SHIFT = 0x0 # macro +AID1_XCC0_VF4_BASE_ADDR__AID1_XCC0_VF4_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_XCC1_VF4_BASE_ADDR__AID1_XCC1_VF4_BASE_ADDR__SHIFT = 0x0 # macro +AID1_XCC1_VF4_BASE_ADDR__AID1_XCC1_VF4_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_XCC0_VF4_BASE_ADDR__AID2_XCC0_VF4_BASE_ADDR__SHIFT = 0x0 # macro +AID2_XCC0_VF4_BASE_ADDR__AID2_XCC0_VF4_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_XCC1_VF4_BASE_ADDR__AID2_XCC1_VF4_BASE_ADDR__SHIFT = 0x0 # macro +AID2_XCC1_VF4_BASE_ADDR__AID2_XCC1_VF4_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_XCC0_VF4_BASE_ADDR__AID3_XCC0_VF4_BASE_ADDR__SHIFT = 0x0 # macro +AID3_XCC0_VF4_BASE_ADDR__AID3_XCC0_VF4_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_XCC1_VF4_BASE_ADDR__AID3_XCC1_VF4_BASE_ADDR__SHIFT = 0x0 # macro +AID3_XCC1_VF4_BASE_ADDR__AID3_XCC1_VF4_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_NBIF_VF4_BASE_ADDR__AID0_NBIF_VF4_BASE_ADDR__SHIFT = 0x0 # macro +AID0_NBIF_VF4_BASE_ADDR__AID0_NBIF_VF4_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_ATHUB_VF4_BASE_ADDR__AID0_ATHUB_VF4_BASE_ADDR__SHIFT = 0x0 # macro +AID0_ATHUB_VF4_BASE_ADDR__AID0_ATHUB_VF4_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_IH_VF4_BASE_ADDR__AID0_IH_VF4_BASE_ADDR__SHIFT = 0x0 # macro +AID0_IH_VF4_BASE_ADDR__AID0_IH_VF4_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_HDP_VF4_BASE_ADDR__AID0_HDP_VF4_BASE_ADDR__SHIFT = 0x0 # macro +AID0_HDP_VF4_BASE_ADDR__AID0_HDP_VF4_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_VF5_BASE_ADDR__AID0_VF5_BASE_ADDR__SHIFT = 0x0 # macro +AID0_VF5_BASE_ADDR__AID0_VF5_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_VF5_BASE_ADDR__AID1_VF5_BASE_ADDR__SHIFT = 0x0 # macro +AID1_VF5_BASE_ADDR__AID1_VF5_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_VF5_BASE_ADDR__AID2_VF5_BASE_ADDR__SHIFT = 0x0 # macro +AID2_VF5_BASE_ADDR__AID2_VF5_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_VF5_BASE_ADDR__AID3_VF5_BASE_ADDR__SHIFT = 0x0 # macro +AID3_VF5_BASE_ADDR__AID3_VF5_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_XCC0_VF5_BASE_ADDR__AID0_XCC0_VF5_BASE_ADDR__SHIFT = 0x0 # macro +AID0_XCC0_VF5_BASE_ADDR__AID0_XCC0_VF5_BASE_ADDR_MASK = 0x0001FFFF # macro +AID0_XCC1_VF5_BASE_ADDR__AID0_XCC1_VF5_BASE_ADDR__SHIFT = 0x0 # macro +AID0_XCC1_VF5_BASE_ADDR__AID0_XCC1_VF5_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_XCC0_VF5_BASE_ADDR__AID1_XCC0_VF5_BASE_ADDR__SHIFT = 0x0 # macro +AID1_XCC0_VF5_BASE_ADDR__AID1_XCC0_VF5_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_XCC1_VF5_BASE_ADDR__AID1_XCC1_VF5_BASE_ADDR__SHIFT = 0x0 # macro +AID1_XCC1_VF5_BASE_ADDR__AID1_XCC1_VF5_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_XCC0_VF5_BASE_ADDR__AID2_XCC0_VF5_BASE_ADDR__SHIFT = 0x0 # macro +AID2_XCC0_VF5_BASE_ADDR__AID2_XCC0_VF5_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_XCC1_VF5_BASE_ADDR__AID2_XCC1_VF5_BASE_ADDR__SHIFT = 0x0 # macro +AID2_XCC1_VF5_BASE_ADDR__AID2_XCC1_VF5_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_XCC0_VF5_BASE_ADDR__AID3_XCC0_VF5_BASE_ADDR__SHIFT = 0x0 # macro +AID3_XCC0_VF5_BASE_ADDR__AID3_XCC0_VF5_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_XCC1_VF5_BASE_ADDR__AID3_XCC1_VF5_BASE_ADDR__SHIFT = 0x0 # macro +AID3_XCC1_VF5_BASE_ADDR__AID3_XCC1_VF5_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_NBIF_VF5_BASE_ADDR__AID0_NBIF_VF5_BASE_ADDR__SHIFT = 0x0 # macro +AID0_NBIF_VF5_BASE_ADDR__AID0_NBIF_VF5_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_ATHUB_VF5_BASE_ADDR__AID0_ATHUB_VF5_BASE_ADDR__SHIFT = 0x0 # macro +AID0_ATHUB_VF5_BASE_ADDR__AID0_ATHUB_VF5_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_IH_VF5_BASE_ADDR__AID0_IH_VF5_BASE_ADDR__SHIFT = 0x0 # macro +AID0_IH_VF5_BASE_ADDR__AID0_IH_VF5_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_HDP_VF5_BASE_ADDR__AID0_HDP_VF5_BASE_ADDR__SHIFT = 0x0 # macro +AID0_HDP_VF5_BASE_ADDR__AID0_HDP_VF5_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_VF6_BASE_ADDR__AID0_VF6_BASE_ADDR__SHIFT = 0x0 # macro +AID0_VF6_BASE_ADDR__AID0_VF6_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_VF6_BASE_ADDR__AID1_VF6_BASE_ADDR__SHIFT = 0x0 # macro +AID1_VF6_BASE_ADDR__AID1_VF6_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_VF6_BASE_ADDR__AID2_VF6_BASE_ADDR__SHIFT = 0x0 # macro +AID2_VF6_BASE_ADDR__AID2_VF6_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_VF6_BASE_ADDR__AID3_VF6_BASE_ADDR__SHIFT = 0x0 # macro +AID3_VF6_BASE_ADDR__AID3_VF6_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_XCC0_VF6_BASE_ADDR__AID0_XCC0_VF6_BASE_ADDR__SHIFT = 0x0 # macro +AID0_XCC0_VF6_BASE_ADDR__AID0_XCC0_VF6_BASE_ADDR_MASK = 0x0001FFFF # macro +AID0_XCC1_VF6_BASE_ADDR__AID0_XCC1_VF6_BASE_ADDR__SHIFT = 0x0 # macro +AID0_XCC1_VF6_BASE_ADDR__AID0_XCC1_VF6_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_XCC0_VF6_BASE_ADDR__AID1_XCC0_VF6_BASE_ADDR__SHIFT = 0x0 # macro +AID1_XCC0_VF6_BASE_ADDR__AID1_XCC0_VF6_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_XCC1_VF6_BASE_ADDR__AID1_XCC1_VF6_BASE_ADDR__SHIFT = 0x0 # macro +AID1_XCC1_VF6_BASE_ADDR__AID1_XCC1_VF6_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_XCC0_VF6_BASE_ADDR__AID2_XCC0_VF6_BASE_ADDR__SHIFT = 0x0 # macro +AID2_XCC0_VF6_BASE_ADDR__AID2_XCC0_VF6_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_XCC1_VF6_BASE_ADDR__AID2_XCC1_VF6_BASE_ADDR__SHIFT = 0x0 # macro +AID2_XCC1_VF6_BASE_ADDR__AID2_XCC1_VF6_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_XCC0_VF6_BASE_ADDR__AID3_XCC0_VF6_BASE_ADDR__SHIFT = 0x0 # macro +AID3_XCC0_VF6_BASE_ADDR__AID3_XCC0_VF6_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_XCC1_VF6_BASE_ADDR__AID3_XCC1_VF6_BASE_ADDR__SHIFT = 0x0 # macro +AID3_XCC1_VF6_BASE_ADDR__AID3_XCC1_VF6_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_NBIF_VF6_BASE_ADDR__AID0_NBIF_VF6_BASE_ADDR__SHIFT = 0x0 # macro +AID0_NBIF_VF6_BASE_ADDR__AID0_NBIF_VF6_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_ATHUB_VF6_BASE_ADDR__AID0_ATHUB_VF6_BASE_ADDR__SHIFT = 0x0 # macro +AID0_ATHUB_VF6_BASE_ADDR__AID0_ATHUB_VF6_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_IH_VF6_BASE_ADDR__AID0_IH_VF6_BASE_ADDR__SHIFT = 0x0 # macro +AID0_IH_VF6_BASE_ADDR__AID0_IH_VF6_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_HDP_VF6_BASE_ADDR__AID0_HDP_VF6_BASE_ADDR__SHIFT = 0x0 # macro +AID0_HDP_VF6_BASE_ADDR__AID0_HDP_VF6_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_VF7_BASE_ADDR__AID0_VF7_BASE_ADDR__SHIFT = 0x0 # macro +AID0_VF7_BASE_ADDR__AID0_VF7_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_VF7_BASE_ADDR__AID1_VF7_BASE_ADDR__SHIFT = 0x0 # macro +AID1_VF7_BASE_ADDR__AID1_VF7_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_VF7_BASE_ADDR__AID2_VF7_BASE_ADDR__SHIFT = 0x0 # macro +AID2_VF7_BASE_ADDR__AID2_VF7_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_VF7_BASE_ADDR__AID3_VF7_BASE_ADDR__SHIFT = 0x0 # macro +AID3_VF7_BASE_ADDR__AID3_VF7_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_XCC0_VF7_BASE_ADDR__AID0_XCC0_VF7_BASE_ADDR__SHIFT = 0x0 # macro +AID0_XCC0_VF7_BASE_ADDR__AID0_XCC0_VF7_BASE_ADDR_MASK = 0x0001FFFF # macro +AID0_XCC1_VF7_BASE_ADDR__AID0_XCC1_VF7_BASE_ADDR__SHIFT = 0x0 # macro +AID0_XCC1_VF7_BASE_ADDR__AID0_XCC1_VF7_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_XCC0_VF7_BASE_ADDR__AID1_XCC0_VF7_BASE_ADDR__SHIFT = 0x0 # macro +AID1_XCC0_VF7_BASE_ADDR__AID1_XCC0_VF7_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_XCC1_VF7_BASE_ADDR__AID1_XCC1_VF7_BASE_ADDR__SHIFT = 0x0 # macro +AID1_XCC1_VF7_BASE_ADDR__AID1_XCC1_VF7_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_XCC0_VF7_BASE_ADDR__AID2_XCC0_VF7_BASE_ADDR__SHIFT = 0x0 # macro +AID2_XCC0_VF7_BASE_ADDR__AID2_XCC0_VF7_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_XCC1_VF7_BASE_ADDR__AID2_XCC1_VF7_BASE_ADDR__SHIFT = 0x0 # macro +AID2_XCC1_VF7_BASE_ADDR__AID2_XCC1_VF7_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_XCC0_VF7_BASE_ADDR__AID3_XCC0_VF7_BASE_ADDR__SHIFT = 0x0 # macro +AID3_XCC0_VF7_BASE_ADDR__AID3_XCC0_VF7_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_XCC1_VF7_BASE_ADDR__AID3_XCC1_VF7_BASE_ADDR__SHIFT = 0x0 # macro +AID3_XCC1_VF7_BASE_ADDR__AID3_XCC1_VF7_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_NBIF_VF7_BASE_ADDR__AID0_NBIF_VF7_BASE_ADDR__SHIFT = 0x0 # macro +AID0_NBIF_VF7_BASE_ADDR__AID0_NBIF_VF7_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_ATHUB_VF7_BASE_ADDR__AID0_ATHUB_VF7_BASE_ADDR__SHIFT = 0x0 # macro +AID0_ATHUB_VF7_BASE_ADDR__AID0_ATHUB_VF7_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_IH_VF7_BASE_ADDR__AID0_IH_VF7_BASE_ADDR__SHIFT = 0x0 # macro +AID0_IH_VF7_BASE_ADDR__AID0_IH_VF7_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_HDP_VF7_BASE_ADDR__AID0_HDP_VF7_BASE_ADDR__SHIFT = 0x0 # macro +AID0_HDP_VF7_BASE_ADDR__AID0_HDP_VF7_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_PF_BASE_ADDR__AID0_PF_BASE_ADDR__SHIFT = 0x0 # macro +AID0_PF_BASE_ADDR__AID0_PF_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_XCC0_PF_BASE_ADDR__AID0_XCC0_PF_BASE_ADDR__SHIFT = 0x0 # macro +AID0_XCC0_PF_BASE_ADDR__AID0_XCC0_PF_BASE_ADDR_MASK = 0x0000FFFF # macro +AID0_XCC1_PF_BASE_ADDR__AID0_XCC1_PF_BASE_ADDR__SHIFT = 0x0 # macro +AID0_XCC1_PF_BASE_ADDR__AID0_XCC1_PF_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_PF_BASE_ADDR__AID1_PF_BASE_ADDR__SHIFT = 0x0 # macro +AID1_PF_BASE_ADDR__AID1_PF_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_XCC0_PF_BASE_ADDR__AID1_XCC0_PF_BASE_ADDR__SHIFT = 0x0 # macro +AID1_XCC0_PF_BASE_ADDR__AID1_XCC0_PF_BASE_ADDR_MASK = 0x0000FFFF # macro +AID1_XCC1_PF_BASE_ADDR__AID1_XCC1_PF_BASE_ADDR__SHIFT = 0x0 # macro +AID1_XCC1_PF_BASE_ADDR__AID1_XCC1_PF_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_PF_BASE_ADDR__AID2_PF_BASE_ADDR__SHIFT = 0x0 # macro +AID2_PF_BASE_ADDR__AID2_PF_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_XCC0_PF_BASE_ADDR__AID2_XCC0_PF_BASE_ADDR__SHIFT = 0x0 # macro +AID2_XCC0_PF_BASE_ADDR__AID2_XCC0_PF_BASE_ADDR_MASK = 0x0000FFFF # macro +AID2_XCC1_PF_BASE_ADDR__AID2_XCC1_PF_BASE_ADDR__SHIFT = 0x0 # macro +AID2_XCC1_PF_BASE_ADDR__AID2_XCC1_PF_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_PF_BASE_ADDR__AID3_PF_BASE_ADDR__SHIFT = 0x0 # macro +AID3_PF_BASE_ADDR__AID3_PF_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_XCC0_PF_BASE_ADDR__AID3_XCC0_PF_BASE_ADDR__SHIFT = 0x0 # macro +AID3_XCC0_PF_BASE_ADDR__AID3_XCC0_PF_BASE_ADDR_MASK = 0x0000FFFF # macro +AID3_XCC1_PF_BASE_ADDR__AID3_XCC1_PF_BASE_ADDR__SHIFT = 0x0 # macro +AID3_XCC1_PF_BASE_ADDR__AID3_XCC1_PF_BASE_ADDR_MASK = 0x0000FFFF # macro +NBIF_RRMT_CNTL__PARTITION_MODE__SHIFT = 0x0 # macro +NBIF_RRMT_CNTL__AID_DIE_ID__SHIFT = 0x4 # macro +NBIF_RRMT_CNTL__RRMT_ENABLE__SHIFT = 0x8 # macro +NBIF_RRMT_CNTL__RRMT_Invalid_Address_H__SHIFT = 0x18 # macro +NBIF_RRMT_CNTL__PARTITION_MODE_MASK = 0x00000007 # macro +NBIF_RRMT_CNTL__AID_DIE_ID_MASK = 0x00000030 # macro +NBIF_RRMT_CNTL__RRMT_ENABLE_MASK = 0x00000100 # macro +NBIF_RRMT_CNTL__RRMT_Invalid_Address_H_MASK = 0xFF000000 # macro +BIFC_DOORBELL_ACCESS_EN_PF__BIFC_DOORBELL_ACCESS_EN_PF__SHIFT = 0x0 # macro +BIFC_DOORBELL_ACCESS_EN_PF__BIFC_DOORBELL_ACCESS_EN_PF_MASK = 0x000FFFFF # macro +BIFC_DOORBELL_ACCESS_EN_VF0__BIFC_DOORBELL_ACCESS_EN_VF0__SHIFT = 0x0 # macro +BIFC_DOORBELL_ACCESS_EN_VF0__BIFC_DOORBELL_ACCESS_EN_VF0_MASK = 0x000FFFFF # macro +BIFC_DOORBELL_ACCESS_EN_VF1__BIFC_DOORBELL_ACCESS_EN_VF1__SHIFT = 0x0 # macro +BIFC_DOORBELL_ACCESS_EN_VF1__BIFC_DOORBELL_ACCESS_EN_VF1_MASK = 0x000FFFFF # macro +BIFC_DOORBELL_ACCESS_EN_VF2__BIFC_DOORBELL_ACCESS_EN_VF2__SHIFT = 0x0 # macro +BIFC_DOORBELL_ACCESS_EN_VF2__BIFC_DOORBELL_ACCESS_EN_VF2_MASK = 0x000FFFFF # macro +BIFC_DOORBELL_ACCESS_EN_VF3__BIFC_DOORBELL_ACCESS_EN_VF3__SHIFT = 0x0 # macro +BIFC_DOORBELL_ACCESS_EN_VF3__BIFC_DOORBELL_ACCESS_EN_VF3_MASK = 0x000FFFFF # macro +BIFC_DOORBELL_ACCESS_EN_VF4__BIFC_DOORBELL_ACCESS_EN_VF4__SHIFT = 0x0 # macro +BIFC_DOORBELL_ACCESS_EN_VF4__BIFC_DOORBELL_ACCESS_EN_VF4_MASK = 0x000FFFFF # macro +BIFC_DOORBELL_ACCESS_EN_VF5__BIFC_DOORBELL_ACCESS_EN_VF5__SHIFT = 0x0 # macro +BIFC_DOORBELL_ACCESS_EN_VF5__BIFC_DOORBELL_ACCESS_EN_VF5_MASK = 0x000FFFFF # macro +BIFC_DOORBELL_ACCESS_EN_VF6__BIFC_DOORBELL_ACCESS_EN_VF6__SHIFT = 0x0 # macro +BIFC_DOORBELL_ACCESS_EN_VF6__BIFC_DOORBELL_ACCESS_EN_VF6_MASK = 0x000FFFFF # macro +BIFC_DOORBELL_ACCESS_EN_VF7__BIFC_DOORBELL_ACCESS_EN_VF7__SHIFT = 0x0 # macro +BIFC_DOORBELL_ACCESS_EN_VF7__BIFC_DOORBELL_ACCESS_EN_VF7_MASK = 0x000FFFFF # macro +MISC_SCRATCH__MISC_SCRATCH0__SHIFT = 0x0 # macro +MISC_SCRATCH__MISC_SCRATCH0_MASK = 0xFFFFFFFF # macro +INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT = 0x0 # macro +INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK = 0x000000FF # macro +INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT = 0x0 # macro +INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK = 0x000000FF # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT = 0x0 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT = 0x2 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT = 0x4 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT = 0x6 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT = 0x8 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT = 0xa # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT = 0xc # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT = 0xe # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT = 0x10 # macro +OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT = 0x18 # macro +OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT = 0x1a # macro +OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT = 0x1c # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK = 0x00000003 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK = 0x0000000C # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK = 0x00000030 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK = 0x000000C0 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK = 0x00000300 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK = 0x00000C00 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK = 0x00003000 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK = 0x0000C000 # macro +OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK = 0x000F0000 # macro +OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK = 0x03000000 # macro +OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK = 0x0C000000 # macro +OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK = 0xF0000000 # macro +BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT = 0x0 # macro +BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT = 0x1 # macro +BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS__SHIFT = 0x4 # macro +BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT = 0x8 # macro +BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P__SHIFT = 0x9 # macro +BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT = 0xb # macro +BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT = 0xc # macro +BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS__SHIFT = 0xd # macro +BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP__SHIFT = 0xe # macro +BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE__SHIFT = 0xf # macro +BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT = 0x10 # macro +BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT = 0x11 # macro +BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT = 0x12 # macro +BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT = 0x13 # macro +BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT = 0x14 # macro +BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN__SHIFT = 0x15 # macro +BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN__SHIFT = 0x16 # macro +BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST__SHIFT = 0x17 # macro +BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT = 0x18 # macro +BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST__SHIFT = 0x19 # macro +BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT = 0x1a # macro +BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT = 0x1b # macro +BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT = 0x1c # macro +BIFC_MISC_CTRL0__DMA_ALL_RST_PROTECT_STS_SEL__SHIFT = 0x1d # macro +BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST__SHIFT = 0x1e # macro +BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT = 0x1f # macro +BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN_MASK = 0x00000001 # macro +BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN_MASK = 0x00000006 # macro +BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS_MASK = 0x000000F0 # macro +BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK = 0x00000100 # macro +BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P_MASK = 0x00000200 # macro +BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK = 0x00000800 # macro +BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK = 0x00001000 # macro +BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS_MASK = 0x00002000 # macro +BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP_MASK = 0x00004000 # macro +BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE_MASK = 0x00008000 # macro +BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK = 0x00010000 # macro +BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK = 0x00020000 # macro +BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK = 0x00040000 # macro +BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK = 0x00080000 # macro +BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK = 0x00100000 # macro +BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN_MASK = 0x00200000 # macro +BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN_MASK = 0x00400000 # macro +BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST_MASK = 0x00800000 # macro +BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK = 0x01000000 # macro +BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST_MASK = 0x02000000 # macro +BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK = 0x04000000 # macro +BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK = 0x08000000 # macro +BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK = 0x10000000 # macro +BIFC_MISC_CTRL0__DMA_ALL_RST_PROTECT_STS_SEL_MASK = 0x20000000 # macro +BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST_MASK = 0x40000000 # macro +BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK = 0x80000000 # macro +BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT = 0x0 # macro +BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT = 0x1 # macro +BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT = 0x2 # macro +BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT = 0x3 # macro +BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT = 0x4 # macro +BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT = 0x5 # macro +BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT = 0x6 # macro +BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP__SHIFT = 0x7 # macro +BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT = 0x8 # macro +BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT = 0xa # macro +BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT = 0xc # macro +BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT = 0xd # macro +BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT = 0xe # macro +BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT = 0xf # macro +BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT = 0x10 # macro +BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT = 0x11 # macro +BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT = 0x12 # macro +BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT = 0x13 # macro +BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT = 0x14 # macro +BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE__SHIFT = 0x15 # macro +BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE__SHIFT = 0x16 # macro +BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG__SHIFT = 0x17 # macro +BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT = 0x18 # macro +BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT = 0x19 # macro +BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT = 0x1a # macro +BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT = 0x1b # macro +BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT = 0x1c # macro +BIFC_MISC_CTRL1__GMI_CPLBUF_EN__SHIFT = 0x1d # macro +BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT = 0x1e # macro +BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK = 0x00000001 # macro +BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK = 0x00000002 # macro +BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK = 0x00000004 # macro +BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK = 0x00000008 # macro +BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK = 0x00000010 # macro +BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK = 0x00000020 # macro +BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK = 0x00000040 # macro +BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP_MASK = 0x00000080 # macro +BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK = 0x00000300 # macro +BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK = 0x00000C00 # macro +BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK = 0x00001000 # macro +BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK = 0x00002000 # macro +BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK = 0x00004000 # macro +BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK = 0x00008000 # macro +BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK = 0x00010000 # macro +BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK = 0x00020000 # macro +BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK = 0x00040000 # macro +BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK = 0x00080000 # macro +BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK = 0x00100000 # macro +BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_MASK = 0x00200000 # macro +BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE_MASK = 0x00400000 # macro +BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG_MASK = 0x00800000 # macro +BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK = 0x01000000 # macro +BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK = 0x02000000 # macro +BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK = 0x04000000 # macro +BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK = 0x08000000 # macro +BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK = 0x10000000 # macro +BIFC_MISC_CTRL1__GMI_CPLBUF_EN_MASK = 0x20000000 # macro +BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK = 0xC0000000 # macro +BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0__SHIFT = 0x0 # macro +BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1__SHIFT = 0x1 # macro +BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT = 0x10 # macro +BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT = 0x11 # macro +BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0_MASK = 0x00000001 # macro +BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1_MASK = 0x00000002 # macro +BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK = 0x00010000 # macro +BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1_MASK = 0x00020000 # macro +BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE__SHIFT = 0x0 # macro +BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE__SHIFT = 0x10 # macro +BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE_MASK = 0x0000FFFF # macro +BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE_MASK = 0xFFFF0000 # macro +BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT = 0x0 # macro +BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT = 0x1 # macro +BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT = 0x10 # macro +BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT = 0x11 # macro +BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0_MASK = 0x00000001 # macro +BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1_MASK = 0x00000002 # macro +BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK = 0x00010000 # macro +BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK = 0x00020000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT = 0x0 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT = 0x2 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0__SHIFT = 0x4 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT = 0x6 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT = 0x8 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT = 0xa # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT = 0xc # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0__SHIFT = 0xe # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT = 0x10 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT = 0x12 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1__SHIFT = 0x14 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT = 0x16 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT = 0x18 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT = 0x1a # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT = 0x1c # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1__SHIFT = 0x1e # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK = 0x00000003 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK = 0x0000000C # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0_MASK = 0x00000030 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK = 0x000000C0 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK = 0x00000300 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK = 0x00000C00 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK = 0x00003000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0_MASK = 0x0000C000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK = 0x00030000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK = 0x000C0000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1_MASK = 0x00300000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK = 0x00C00000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK = 0x03000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK = 0x0C000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK = 0x30000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1_MASK = 0xC0000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT = 0x0 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT = 0x2 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2__SHIFT = 0x4 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT = 0x6 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT = 0x8 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT = 0xa # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT = 0xc # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2__SHIFT = 0xe # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT = 0x10 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT = 0x12 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3__SHIFT = 0x14 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT = 0x16 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT = 0x18 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT = 0x1a # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT = 0x1c # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3__SHIFT = 0x1e # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK = 0x00000003 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK = 0x0000000C # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2_MASK = 0x00000030 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK = 0x000000C0 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK = 0x00000300 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK = 0x00000C00 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK = 0x00003000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2_MASK = 0x0000C000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK = 0x00030000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK = 0x000C0000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3_MASK = 0x00300000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK = 0x00C00000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK = 0x03000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK = 0x0C000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK = 0x30000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3_MASK = 0xC0000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT = 0x0 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT = 0x2 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4__SHIFT = 0x4 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT = 0x6 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT = 0x8 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT = 0xa # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT = 0xc # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4__SHIFT = 0xe # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT = 0x10 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT = 0x12 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5__SHIFT = 0x14 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT = 0x16 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT = 0x18 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT = 0x1a # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT = 0x1c # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5__SHIFT = 0x1e # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK = 0x00000003 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK = 0x0000000C # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4_MASK = 0x00000030 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK = 0x000000C0 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK = 0x00000300 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK = 0x00000C00 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK = 0x00003000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4_MASK = 0x0000C000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK = 0x00030000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK = 0x000C0000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5_MASK = 0x00300000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK = 0x00C00000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK = 0x03000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK = 0x0C000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK = 0x30000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5_MASK = 0xC0000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT = 0x0 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT = 0x2 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6__SHIFT = 0x4 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT = 0x6 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT = 0x8 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT = 0xa # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT = 0xc # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6__SHIFT = 0xe # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT = 0x10 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT = 0x12 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7__SHIFT = 0x14 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT = 0x16 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT = 0x18 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT = 0x1a # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT = 0x1c # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7__SHIFT = 0x1e # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK = 0x00000003 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK = 0x0000000C # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6_MASK = 0x00000030 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK = 0x000000C0 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK = 0x00000300 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK = 0x00000C00 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK = 0x00003000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6_MASK = 0x0000C000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK = 0x00030000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK = 0x000C0000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7_MASK = 0x00300000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK = 0x00C00000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK = 0x03000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK = 0x0C000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK = 0x30000000 # macro +BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7_MASK = 0xC0000000 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0__SHIFT = 0x0 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1__SHIFT = 0x4 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2__SHIFT = 0x8 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3__SHIFT = 0xc # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4__SHIFT = 0x10 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5__SHIFT = 0x14 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6__SHIFT = 0x18 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7__SHIFT = 0x1c # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0_MASK = 0x00000001 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1_MASK = 0x00000010 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2_MASK = 0x00000100 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3_MASK = 0x00001000 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4_MASK = 0x00010000 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5_MASK = 0x00100000 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6_MASK = 0x01000000 # macro +BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7_MASK = 0x10000000 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT = 0x0 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT = 0x2 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT = 0x4 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT = 0x6 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT = 0x8 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT = 0xa # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT = 0xc # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT = 0xe # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK = 0x00000003 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK = 0x0000000C # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK = 0x00000030 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK = 0x000000C0 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK = 0x00000300 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK = 0x00000C00 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK = 0x00003000 # macro +BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK = 0x0000C000 # macro +BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT = 0x0 # macro +BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT = 0x4 # macro +BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT = 0x8 # macro +BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT = 0x10 # macro +BIFC_THT_CNTL__THT_NTB_VC0_APER0_ADSC_PUSH_DIS__SHIFT = 0x18 # macro +BIFC_THT_CNTL__THT_NTB_VC0_OTHAPER_ADSC_PUSH_DIS__SHIFT = 0x19 # macro +BIFC_THT_CNTL__THT_NTB_VC1_APER0_ADSC_PUSH_DIS__SHIFT = 0x1a # macro +BIFC_THT_CNTL__THT_NTB_VC1_OTHAPER_ADSC_PUSH_DIS__SHIFT = 0x1b # macro +BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0_MASK = 0x0000000F # macro +BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0_MASK = 0x000000F0 # macro +BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1_MASK = 0x00000F00 # macro +BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN_MASK = 0x00010000 # macro +BIFC_THT_CNTL__THT_NTB_VC0_APER0_ADSC_PUSH_DIS_MASK = 0x01000000 # macro +BIFC_THT_CNTL__THT_NTB_VC0_OTHAPER_ADSC_PUSH_DIS_MASK = 0x02000000 # macro +BIFC_THT_CNTL__THT_NTB_VC1_APER0_ADSC_PUSH_DIS_MASK = 0x04000000 # macro +BIFC_THT_CNTL__THT_NTB_VC1_OTHAPER_ADSC_PUSH_DIS_MASK = 0x08000000 # macro +BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT = 0x0 # macro +BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN__SHIFT = 0x8 # macro +BIFC_HSTARB_CNTL__SLVARB_MODE_MASK = 0x00000003 # macro +BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN_MASK = 0x00000100 # macro +BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT = 0x0 # macro +BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT = 0x2 # macro +BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT = 0x5 # macro +BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT = 0x6 # macro +BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT = 0x7 # macro +BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT = 0x8 # macro +BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT = 0xa # macro +BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT = 0xc # macro +BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK__SHIFT = 0xf # macro +BIFC_GSI_CNTL__GSI_SMN_BURST_EN__SHIFT = 0x10 # macro +BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN__SHIFT = 0x11 # macro +BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE__SHIFT = 0x1b # macro +BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH__SHIFT = 0x1c # macro +BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH__SHIFT = 0x1d # macro +BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD__SHIFT = 0x1e # macro +BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL__SHIFT = 0x1f # macro +BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK = 0x00000003 # macro +BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK = 0x0000001C # macro +BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK = 0x00000020 # macro +BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK = 0x00000040 # macro +BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK = 0x00000080 # macro +BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK = 0x00000100 # macro +BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK = 0x00000C00 # macro +BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK = 0x00003000 # macro +BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK_MASK = 0x00008000 # macro +BIFC_GSI_CNTL__GSI_SMN_BURST_EN_MASK = 0x00010000 # macro +BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN_MASK = 0x00020000 # macro +BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE_MASK = 0x08000000 # macro +BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH_MASK = 0x10000000 # macro +BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH_MASK = 0x20000000 # macro +BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD_MASK = 0x40000000 # macro +BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL_MASK = 0x80000000 # macro +BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT = 0x0 # macro +BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK = 0x0000FFFF # macro +BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0__SHIFT = 0x0 # macro +BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1__SHIFT = 0x1 # macro +BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0_MASK = 0x00000001 # macro +BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1_MASK = 0x00000002 # macro +BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT = 0x0 # macro +BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT = 0x8 # macro +BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT = 0x10 # macro +BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT = 0x18 # macro +BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK = 0x000000FF # macro +BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK = 0x0000FF00 # macro +BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK = 0x00FF0000 # macro +BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK = 0xFF000000 # macro +BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT = 0x0 # macro +BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT = 0x1 # macro +BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT = 0x2 # macro +BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT = 0x3 # macro +BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT = 0x4 # macro +BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P__SHIFT = 0x5 # macro +BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT = 0x7 # macro +BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN__SHIFT = 0x8 # macro +BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT = 0x9 # macro +BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK = 0x00000001 # macro +BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK = 0x00000002 # macro +BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK = 0x00000004 # macro +BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK = 0x00000008 # macro +BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK = 0x00000010 # macro +BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P_MASK = 0x00000020 # macro +BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK = 0x00000080 # macro +BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN_MASK = 0x00000100 # macro +BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK = 0x00000200 # macro +BIFC_PASID_STS__PASID_STS__SHIFT = 0x0 # macro +BIFC_PASID_STS__PASID_STS_MASK = 0x0000000F # macro +BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE__SHIFT = 0x0 # macro +BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE__SHIFT = 0x3 # macro +BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS__SHIFT = 0x8 # macro +BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT = 0x9 # macro +BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT = 0xa # macro +BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE_MASK = 0x00000007 # macro +BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE_MASK = 0x00000038 # macro +BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS_MASK = 0x00000100 # macro +BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER_MASK = 0x00000200 # macro +BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER_MASK = 0x00000400 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT = 0x0 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT = 0x1 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT = 0x8 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT = 0x9 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT = 0x10 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT = 0x18 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK = 0x00000001 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK = 0x00000002 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK = 0x00000100 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK = 0x00000200 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK = 0x007F0000 # macro +BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK = 0x7F000000 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT = 0x0 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT = 0x1 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT = 0x4 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT = 0x5 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT = 0x8 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT = 0x10 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK = 0x00000001 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK = 0x00000002 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK = 0x00000010 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK = 0x00000020 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK = 0x0000FF00 # macro +BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK = 0x01FF0000 # macro +BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT__SHIFT = 0x0 # macro +BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT_MASK = 0xFFFFFFFF # macro +BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT__SHIFT = 0x0 # macro +BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT_MASK = 0xFFFFFFFF # macro +BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT__SHIFT = 0x0 # macro +BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT_MASK = 0xFFFFFFFF # macro +BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT__SHIFT = 0x0 # macro +BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT_MASK = 0xFFFFFFFF # macro +NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT = 0x0 # macro +NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK = 0x00000001 # macro +BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS__SHIFT = 0x0 # macro +BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H__SHIFT = 0x8 # macro +BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H__SHIFT = 0x10 # macro +BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H__SHIFT = 0x18 # macro +BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_MASK = 0x000000FF # macro +BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H_MASK = 0x00000F00 # macro +BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H_MASK = 0x000F0000 # macro +BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H_MASK = 0x0F000000 # macro +NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS__SHIFT = 0x0 # macro +NBIF_PGMST_CTRL__NBIF_CFG_PG_EN__SHIFT = 0x8 # macro +NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN__SHIFT = 0xa # macro +NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN__SHIFT = 0xe # macro +NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS_MASK = 0x000000FF # macro +NBIF_PGMST_CTRL__NBIF_CFG_PG_EN_MASK = 0x00000100 # macro +NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN_MASK = 0x00003C00 # macro +NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN_MASK = 0x0000C000 # macro +NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS__SHIFT = 0x0 # macro +NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS_MASK = 0x0000001F # macro +NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT = 0x0 # macro +NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT = 0x5 # macro +NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY__SHIFT = 0xa # macro +NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1__SHIFT = 0xd # macro +NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS__SHIFT = 0xe # macro +NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2__SHIFT = 0x10 # macro +NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT = 0x18 # macro +NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK__SHIFT = 0x1e # macro +NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE__SHIFT = 0x1f # macro +NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK = 0x0000001F # macro +NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK = 0x000003E0 # macro +NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY_MASK = 0x00000400 # macro +NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1_MASK = 0x00002000 # macro +NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS_MASK = 0x00004000 # macro +NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2_MASK = 0x00010000 # macro +NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS_MASK = 0x3F000000 # macro +NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK_MASK = 0x40000000 # macro +NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE_MASK = 0x80000000 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT = 0x0 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT = 0x1 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT = 0x2 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT = 0x3 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT = 0x4 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT = 0x5 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT = 0x6 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT = 0x7 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK = 0x00000001 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK = 0x00000002 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK = 0x00000004 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK = 0x00000008 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK = 0x00000010 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK = 0x00000020 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK = 0x00000040 # macro +SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK = 0x00000080 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT = 0x0 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT = 0x1 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT = 0x2 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT = 0x3 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT = 0x4 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT = 0x5 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT = 0x6 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT = 0x7 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK = 0x00000001 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK = 0x00000002 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK = 0x00000004 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK = 0x00000008 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK = 0x00000010 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK = 0x00000020 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK = 0x00000040 # macro +SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK = 0x00000080 # macro +SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT = 0x0 # macro +SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT = 0x10 # macro +SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK = 0x00000001 # macro +SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK = 0x00010000 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT = 0x0 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT = 0x1 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT = 0x2 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT = 0x3 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT = 0x4 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT = 0x5 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT = 0x6 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT = 0x7 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK = 0x00000001 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK = 0x00000002 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK = 0x00000004 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK = 0x00000008 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK = 0x00000010 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK = 0x00000020 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK = 0x00000040 # macro +SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK = 0x00000080 # macro +BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT = 0x0 # macro +BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID__SHIFT = 0x8 # macro +BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID__SHIFT = 0x10 # macro +BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK = 0x000000FF # macro +BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID_MASK = 0x0000FF00 # macro +BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID_MASK = 0x00FF0000 # macro +BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT = 0x0 # macro +BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT = 0x1 # macro +BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK = 0x00000001 # macro +BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK = 0x00000002 # macro +NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT = 0x0 # macro +NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE_MASK = 0x00000001 # macro +NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT = 0x0 # macro +NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT = 0x1 # macro +NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT = 0x2 # macro +NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT = 0x3 # macro +NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT = 0x4 # macro +NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP__SHIFT = 0x5 # macro +NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN__SHIFT = 0x6 # macro +NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS__SHIFT = 0x7 # macro +NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK = 0x00000001 # macro +NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK = 0x00000002 # macro +NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK = 0x00000004 # macro +NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK = 0x00000008 # macro +NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK = 0x00000010 # macro +NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP_MASK = 0x00000020 # macro +NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN_MASK = 0x00000040 # macro +NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS_MASK = 0x00000080 # macro +NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS__SHIFT = 0x0 # macro +NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS__SHIFT = 0x1 # macro +NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS_MASK = 0x00000001 # macro +NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS_MASK = 0x00000002 # macro +BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE__SHIFT = 0x1d # macro +BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE__SHIFT = 0x1e # macro +BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE__SHIFT = 0x1f # macro +BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE_MASK = 0x20000000 # macro +BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE_MASK = 0x40000000 # macro +BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE_MASK = 0x80000000 # macro +BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT__SHIFT = 0x0 # macro +BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT__SHIFT = 0x8 # macro +BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT__SHIFT = 0x10 # macro +BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT__SHIFT = 0x18 # macro +BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT_MASK = 0x000000FF # macro +BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT_MASK = 0x0000FF00 # macro +BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT_MASK = 0x00FF0000 # macro +BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT_MASK = 0xFF000000 # macro +BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT__SHIFT = 0x0 # macro +BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT__SHIFT = 0x8 # macro +BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT__SHIFT = 0x10 # macro +BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT__SHIFT = 0x18 # macro +BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT_MASK = 0x000000FF # macro +BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT_MASK = 0x0000FF00 # macro +BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT_MASK = 0x00FF0000 # macro +BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT_MASK = 0xFF000000 # macro +NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST__SHIFT = 0x0 # macro +NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST_MASK = 0x00000001 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0__SHIFT = 0x0 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT = 0x1 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0__SHIFT = 0x2 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0__SHIFT = 0x3 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0__SHIFT = 0x10 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT = 0x11 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0__SHIFT = 0x12 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0__SHIFT = 0x13 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0_MASK = 0x00000001 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK = 0x00000002 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0_MASK = 0x00000004 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0_MASK = 0x00000008 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_MASK = 0x00010000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK = 0x00020000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_MASK = 0x00040000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0_MASK = 0x00080000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1__SHIFT = 0x0 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT = 0x1 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1__SHIFT = 0x2 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1__SHIFT = 0x3 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1__SHIFT = 0x10 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT = 0x11 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1__SHIFT = 0x12 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1__SHIFT = 0x13 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1_MASK = 0x00000001 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK = 0x00000002 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1_MASK = 0x00000004 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1_MASK = 0x00000008 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1_MASK = 0x00010000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK = 0x00020000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1_MASK = 0x00040000 # macro +BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1_MASK = 0x00080000 # macro +BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR__SHIFT = 0x0 # macro +BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT = 0x1 # macro +BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR__SHIFT = 0x10 # macro +BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT = 0x11 # macro +BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR_MASK = 0x00000001 # macro +BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK = 0x00000002 # macro +BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR_MASK = 0x00010000 # macro +BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK = 0x00020000 # macro +BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0__SHIFT = 0x0 # macro +BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1__SHIFT = 0x1 # macro +BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0_MASK = 0x00000001 # macro +BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1_MASK = 0x00000002 # macro +BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0__SHIFT = 0x0 # macro +BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1__SHIFT = 0x1 # macro +BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0_MASK = 0x00000001 # macro +BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1_MASK = 0x00000002 # macro +NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS__SHIFT = 0x0 # macro +NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT = 0x4 # macro +NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT = 0x8 # macro +NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS__SHIFT = 0x10 # macro +NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT = 0x14 # macro +NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT = 0x1a # macro +NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS_MASK = 0x00000001 # macro +NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK = 0x000000F0 # macro +NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK = 0x00000100 # macro +NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS_MASK = 0x00010000 # macro +NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK = 0x00F00000 # macro +NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK = 0x0C000000 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT = 0x0 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT = 0x1 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT = 0x2 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT = 0x3 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT = 0x4 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT = 0x5 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT = 0x6 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS_MASK = 0x00000001 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS_MASK = 0x00000002 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS_MASK = 0x00000004 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS_MASK = 0x00000008 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS_MASK = 0x00000010 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS_MASK = 0x00000020 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS_MASK = 0x00000040 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT = 0x0 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT = 0x1 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT = 0x2 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT = 0x3 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT = 0x4 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT = 0x5 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT = 0x6 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV_MASK = 0x00000001 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV_MASK = 0x00000002 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV_MASK = 0x00000004 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV_MASK = 0x00000008 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV_MASK = 0x00000010 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV_MASK = 0x00000020 # macro +NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV_MASK = 0x00000040 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT = 0x0 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT = 0x1 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT = 0x2 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT = 0x3 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT = 0x4 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT = 0x5 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT = 0x6 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG_MASK = 0x00000001 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG_MASK = 0x00000002 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG_MASK = 0x00000004 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG_MASK = 0x00000008 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG_MASK = 0x00000010 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG_MASK = 0x00000020 # macro +NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG_MASK = 0x00000040 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT = 0x0 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT = 0x1 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT = 0x2 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT = 0x3 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT = 0x4 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT = 0x5 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT = 0x6 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS_MASK = 0x00000001 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS_MASK = 0x00000002 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS_MASK = 0x00000004 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS_MASK = 0x00000008 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS_MASK = 0x00000010 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS_MASK = 0x00000020 # macro +NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS_MASK = 0x00000040 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT = 0x0 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT = 0x1 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT = 0x2 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT = 0x3 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT = 0x4 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT = 0x5 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT = 0x6 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV_MASK = 0x00000001 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV_MASK = 0x00000002 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV_MASK = 0x00000004 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV_MASK = 0x00000008 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV_MASK = 0x00000010 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV_MASK = 0x00000020 # macro +NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV_MASK = 0x00000040 # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT = 0x0 # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT = 0x1 # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT = 0x2 # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT = 0xa # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT = 0xb # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK__SHIFT = 0xc # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT = 0xd # macro +NBIF_MGCG_CTRL_LCLK__NBIF_SRAM_FGCG_EN_LCLK__SHIFT = 0xe # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK = 0x00000001 # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK = 0x00000002 # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK = 0x000003FC # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK = 0x00000400 # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK = 0x00000800 # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK = 0x00001000 # macro +NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK = 0x00002000 # macro +NBIF_MGCG_CTRL_LCLK__NBIF_SRAM_FGCG_EN_LCLK_MASK = 0x00004000 # macro +NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT = 0x0 # macro +NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT = 0x1 # macro +NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT = 0x10 # macro +NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK = 0x00000001 # macro +NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE_MASK = 0x00000002 # macro +NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK = 0xFFFF0000 # macro +SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT = 0x0 # macro +SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT = 0x8 # macro +SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT = 0x9 # macro +SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT = 0xa # macro +SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT = 0xb # macro +SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT = 0x10 # macro +SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT = 0x14 # macro +SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT = 0x18 # macro +SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT = 0x1c # macro +SMN_MST_CNTL0__SMN_ARB_MODE_MASK = 0x00000003 # macro +SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK = 0x00000100 # macro +SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK = 0x00000200 # macro +SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK = 0x00000400 # macro +SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK = 0x00000800 # macro +SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK = 0x00010000 # macro +SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK = 0x00100000 # macro +SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK = 0x01000000 # macro +SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK = 0x10000000 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT = 0x0 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT = 0x1 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT = 0x2 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT = 0x3 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT = 0x4 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT = 0x5 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT = 0x6 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT = 0x7 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK = 0x00000001 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK = 0x00000002 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK = 0x00000004 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK = 0x00000008 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK = 0x00000010 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK = 0x00000020 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK = 0x00000040 # macro +SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK = 0x00000080 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT = 0x0 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT = 0x1 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT = 0x2 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT = 0x3 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT = 0x4 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT = 0x5 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT = 0x6 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT = 0x7 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK = 0x00000001 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK = 0x00000002 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK = 0x00000004 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK = 0x00000008 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK = 0x00000010 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK = 0x00000020 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK = 0x00000040 # macro +SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK = 0x00000080 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT = 0x0 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT = 0x1 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT = 0x2 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT = 0x3 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT = 0x4 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT = 0x5 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT = 0x6 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT = 0x7 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT = 0x18 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK = 0x00000001 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK = 0x00000002 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK = 0x00000004 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK = 0x00000008 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK = 0x00000010 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK = 0x00000020 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK = 0x00000040 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK = 0x00000080 # macro +NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK = 0x01000000 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT = 0x0 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT = 0x1 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT = 0x2 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT = 0x3 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT = 0x4 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT = 0x5 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT = 0x6 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT = 0x7 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT = 0x18 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK = 0x00000001 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK = 0x00000002 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK = 0x00000004 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK = 0x00000008 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK = 0x00000010 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK = 0x00000020 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK = 0x00000040 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK = 0x00000080 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK = 0x01000000 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT = 0x0 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT = 0x1 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT = 0x2 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT = 0x3 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT = 0x4 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT = 0x5 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT = 0x6 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT = 0x7 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT = 0x18 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK = 0x00000001 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK = 0x00000002 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK = 0x00000004 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK = 0x00000008 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK = 0x00000010 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK = 0x00000020 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK = 0x00000040 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK = 0x00000080 # macro +NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK = 0x01000000 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT = 0x0 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT = 0x1 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT = 0x2 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT = 0x3 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT = 0x4 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT = 0x5 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT = 0x6 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT = 0x7 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT = 0x18 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK = 0x00000001 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK = 0x00000002 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK = 0x00000004 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK = 0x00000008 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK = 0x00000010 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK = 0x00000020 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK = 0x00000040 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK = 0x00000080 # macro +NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK = 0x01000000 # macro +NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN__SHIFT = 0x0 # macro +NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN__SHIFT = 0x1 # macro +NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT__SHIFT = 0x8 # macro +NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT__SHIFT = 0x10 # macro +NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN_MASK = 0x00000001 # macro +NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN_MASK = 0x00000002 # macro +NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT_MASK = 0x00000700 # macro +NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT_MASK = 0xFFFF0000 # macro +NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN__SHIFT = 0x0 # macro +NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN_MASK = 0xFFFFFFFF # macro +NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS__SHIFT = 0x0 # macro +NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS_MASK = 0xFFFFFFFF # macro +NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN__SHIFT = 0x0 # macro +NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN_MASK = 0xFFFFFFFF # macro +NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2__SHIFT = 0x0 # macro +NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2_MASK = 0xFFFFFFFF # macro +NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2__SHIFT = 0x0 # macro +NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2_MASK = 0xFFFFFFFF # macro +NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2__SHIFT = 0x0 # macro +NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2_MASK = 0xFFFFFFFF # macro +BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT = 0x0 # macro +BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT = 0x4 # macro +BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK = 0x0000000F # macro +BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK = 0x000000F0 # macro +BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT = 0x0 # macro +BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT = 0x4 # macro +BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK = 0x0000000F # macro +BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK = 0x000000F0 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC__SHIFT = 0x0 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC__SHIFT = 0x4 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC__SHIFT = 0x8 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC__SHIFT = 0xc # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC__SHIFT = 0x10 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC__SHIFT = 0x14 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC__SHIFT = 0x18 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC__SHIFT = 0x1c # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC_MASK = 0x0000000F # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC_MASK = 0x000000F0 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC_MASK = 0x00000F00 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC_MASK = 0x0000F000 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC_MASK = 0x000F0000 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC_MASK = 0x00F00000 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC_MASK = 0x0F000000 # macro +BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC_MASK = 0xF0000000 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC__SHIFT = 0x0 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC__SHIFT = 0x4 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC__SHIFT = 0x8 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC__SHIFT = 0xc # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC__SHIFT = 0x10 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC__SHIFT = 0x14 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC__SHIFT = 0x18 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC__SHIFT = 0x1c # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC_MASK = 0x0000000F # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC_MASK = 0x000000F0 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC_MASK = 0x00000F00 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC_MASK = 0x0000F000 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC_MASK = 0x000F0000 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC_MASK = 0x00F00000 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC_MASK = 0x0F000000 # macro +BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC_MASK = 0xF0000000 # macro +DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H__SHIFT = 0x0 # macro +DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H__SHIFT = 0x8 # macro +DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H_MASK = 0x0000000F # macro +DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H_MASK = 0x00000F00 # macro +BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT = 0x0 # macro +BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT = 0x1 # macro +BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT = 0x2 # macro +BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK = 0x00000001 # macro +BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK = 0x00000002 # macro +BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK = 0x00000004 # macro +BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT__SHIFT = 0x0 # macro +BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT_MASK = 0x0000FFFF # macro +BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT__SHIFT = 0x0 # macro +BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT_MASK = 0x0000FFFF # macro +BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT__SHIFT = 0x0 # macro +BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT_MASK = 0x0000FFFF # macro +BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT__SHIFT = 0x0 # macro +BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT_MASK = 0x0000FFFF # macro +BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT = 0x0 # macro +BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H__SHIFT = 0x8 # macro +BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_DIS__SHIFT = 0xc # macro +BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK = 0x000000FF # macro +BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H_MASK = 0x00000F00 # macro +BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_DIS_MASK = 0x00001000 # macro +BIFC_A2S_CNTL_SW0__RDRSP_ERRMAP__SHIFT = 0x0 # macro +BIFC_A2S_CNTL_SW0__RDRSP_SEL_MODE__SHIFT = 0x2 # macro +BIFC_A2S_CNTL_SW0__STATIC_VC_ENABLE__SHIFT = 0x5 # macro +BIFC_A2S_CNTL_SW0__STATIC_VC_VALUE__SHIFT = 0x6 # macro +BIFC_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT = 0x9 # macro +BIFC_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE__SHIFT = 0xa # macro +BIFC_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT = 0xb # macro +BIFC_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT = 0xc # macro +BIFC_A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT = 0x10 # macro +BIFC_A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT = 0x18 # macro +BIFC_A2S_CNTL_SW0__RDRSP_ERRMAP_MASK = 0x00000003 # macro +BIFC_A2S_CNTL_SW0__RDRSP_SEL_MODE_MASK = 0x0000001C # macro +BIFC_A2S_CNTL_SW0__STATIC_VC_ENABLE_MASK = 0x00000020 # macro +BIFC_A2S_CNTL_SW0__STATIC_VC_VALUE_MASK = 0x000001C0 # macro +BIFC_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK = 0x00000200 # macro +BIFC_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE_MASK = 0x00000400 # macro +BIFC_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE_MASK = 0x00000800 # macro +BIFC_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK = 0x00001000 # macro +BIFC_A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK = 0x00FF0000 # macro +BIFC_A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK = 0xFF000000 # macro +BIFC_A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT = 0x0 # macro +BIFC_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT = 0x2 # macro +BIFC_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE__SHIFT = 0x3 # macro +BIFC_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN__SHIFT = 0x4 # macro +BIFC_A2S_MISC_CNTL__RSP_REORDER_DIS__SHIFT = 0x5 # macro +BIFC_A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT = 0x6 # macro +BIFC_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT = 0x7 # macro +BIFC_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT = 0x8 # macro +BIFC_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY__SHIFT = 0x9 # macro +BIFC_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT = 0xa # macro +BIFC_A2S_MISC_CNTL__WR_TAG_SET_MIN__SHIFT = 0x10 # macro +BIFC_A2S_MISC_CNTL__RD_TAG_SET_MIN__SHIFT = 0x15 # macro +BIFC_A2S_MISC_CNTL__WRR_LRG_MODE__SHIFT = 0x1a # macro +BIFC_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE__SHIFT = 0x1b # macro +BIFC_A2S_MISC_CNTL__BYPASS_OVERRIDE_EN__SHIFT = 0x1c # macro +BIFC_A2S_MISC_CNTL__BYPASS_OVERRIDE_VALUE__SHIFT = 0x1d # macro +BIFC_A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK = 0x00000003 # macro +BIFC_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS_MASK = 0x00000004 # macro +BIFC_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE_MASK = 0x00000008 # macro +BIFC_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN_MASK = 0x00000010 # macro +BIFC_A2S_MISC_CNTL__RSP_REORDER_DIS_MASK = 0x00000020 # macro +BIFC_A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK = 0x00000040 # macro +BIFC_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS_MASK = 0x00000080 # macro +BIFC_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS_MASK = 0x00000100 # macro +BIFC_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY_MASK = 0x00000200 # macro +BIFC_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK = 0x00000400 # macro +BIFC_A2S_MISC_CNTL__WR_TAG_SET_MIN_MASK = 0x001F0000 # macro +BIFC_A2S_MISC_CNTL__RD_TAG_SET_MIN_MASK = 0x03E00000 # macro +BIFC_A2S_MISC_CNTL__WRR_LRG_MODE_MASK = 0x04000000 # macro +BIFC_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE_MASK = 0x08000000 # macro +BIFC_A2S_MISC_CNTL__BYPASS_OVERRIDE_EN_MASK = 0x10000000 # macro +BIFC_A2S_MISC_CNTL__BYPASS_OVERRIDE_VALUE_MASK = 0x20000000 # macro +BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT = 0x0 # macro +BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT = 0x8 # macro +BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT = 0x10 # macro +BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK = 0x000000FF # macro +BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK = 0x0000FF00 # macro +BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK = 0x00FF0000 # macro +BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT = 0x0 # macro +BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT = 0x10 # macro +BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT = 0x18 # macro +BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK = 0x000000FF # macro +BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK = 0x00FF0000 # macro +BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK = 0xFF000000 # macro +BIFC_A2S_CNTL_CL0__NSNOOP_MAP__SHIFT = 0x0 # macro +BIFC_A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT = 0x2 # macro +BIFC_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT = 0x4 # macro +BIFC_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT = 0x6 # macro +BIFC_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT = 0x8 # macro +BIFC_A2S_CNTL_CL0__BLKLVL_MAP__SHIFT = 0xa # macro +BIFC_A2S_CNTL_CL0__DATERR_MAP__SHIFT = 0xc # macro +BIFC_A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT = 0xe # macro +BIFC_A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT = 0x10 # macro +BIFC_A2S_CNTL_CL0__RESP_WR_MAP__SHIFT = 0x12 # macro +BIFC_A2S_CNTL_CL0__RESP_RD_MAP__SHIFT = 0x14 # macro +BIFC_A2S_CNTL_CL0__NSNOOP_MAP_MASK = 0x00000003 # macro +BIFC_A2S_CNTL_CL0__REQPASSPW_VC0_MAP_MASK = 0x0000000C # macro +BIFC_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP_MASK = 0x00000030 # macro +BIFC_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP_MASK = 0x000000C0 # macro +BIFC_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP_MASK = 0x00000300 # macro +BIFC_A2S_CNTL_CL0__BLKLVL_MAP_MASK = 0x00000C00 # macro +BIFC_A2S_CNTL_CL0__DATERR_MAP_MASK = 0x00003000 # macro +BIFC_A2S_CNTL_CL0__EXOKAY_WR_MAP_MASK = 0x0000C000 # macro +BIFC_A2S_CNTL_CL0__EXOKAY_RD_MAP_MASK = 0x00030000 # macro +BIFC_A2S_CNTL_CL0__RESP_WR_MAP_MASK = 0x000C0000 # macro +BIFC_A2S_CNTL_CL0__RESP_RD_MAP_MASK = 0x00300000 # macro +RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT = 0x0 # macro +RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT = 0x0 # macro +RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK = 0xFFFFFFFF # macro +RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT = 0x0 # macro +RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT = 0x7 # macro +RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT = 0x1e # macro +RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK = 0x00000001 # macro +RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK = 0x00000080 # macro +RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK = 0x40000000 # macro +RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT = 0x19 # macro +RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK = 0x06000000 # macro +RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT = 0x1c # macro +RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK = 0x70000000 # macro +RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT = 0x7 # macro +RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT = 0x8 # macro +RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK = 0x00000080 # macro +RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK = 0x00000100 # macro +RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT = 0x0 # macro +RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT = 0x1 # macro +RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT = 0x2 # macro +RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT = 0x3 # macro +RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT = 0x4 # macro +RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK = 0x00000001 # macro +RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK = 0x00000002 # macro +RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK = 0x00000004 # macro +RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK = 0x00000008 # macro +RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK = 0x00000010 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT = 0x0 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT = 0x11 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT = 0x15 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK = 0x00000001 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK = 0x00020000 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK = 0x00E00000 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT = 0x18 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT = 0x1d # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK = 0x01000000 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK = 0x20000000 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT = 0x2 # macro +RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK = 0x00000004 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT = 0x8 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT = 0xb # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT = 0x11 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT = 0x12 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT = 0x13 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT = 0x14 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK = 0x00000001 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK = 0x00000700 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK = 0x00000800 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK = 0x00020000 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK = 0x00040000 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK = 0x00080000 # macro +RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK = 0x00100000 # macro +RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0x8 # macro +RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT = 0x9 # macro +RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT = 0x14 # macro +RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT = 0x15 # macro +RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT = 0x1b # macro +RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00000100 # macro +RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK = 0x00000200 # macro +RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK = 0x00100000 # macro +RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK = 0x00200000 # macro +RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK = 0x08000000 # macro +RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT = 0x1 # macro +RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT = 0x2 # macro +RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT = 0x3 # macro +RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK = 0x00000001 # macro +RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK = 0x00000002 # macro +RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK = 0x00000004 # macro +RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK = 0x00000008 # macro +RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT = 0x1b # macro +RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK = 0x00000001 # macro +RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK = 0x08000000 # macro +RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT = 0xa # macro +RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK = 0x00000400 # macro +RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT = 0x0 # macro +RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK = 0xFFFFFFFF # macro +RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK = 0xFFFFFFFF # macro +RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT = 0x7 # macro +RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT = 0x8 # macro +RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT = 0x1e # macro +RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK = 0x00000080 # macro +RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK = 0x00000100 # macro +RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK = 0x40000000 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT = 0x1 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT = 0x2 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT = 0x3 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT = 0x4 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT = 0x6 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK = 0x00000001 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK = 0x00000002 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK = 0x00000004 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK = 0x00000008 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK = 0x00000010 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK = 0x00000040 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT = 0x1 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT = 0x2 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT = 0x3 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT = 0x4 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT = 0x6 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT = 0x7 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK = 0x00000001 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK = 0x00000002 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK = 0x00000004 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK = 0x00000008 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK = 0x00000010 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK = 0x00000040 # macro +RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK = 0x00000080 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK = 0x00000001 # macro +RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT = 0x7 # macro +RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK = 0x00000080 # macro +RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT = 0x1 # macro +RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT = 0x2 # macro +RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT = 0x3 # macro +RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT = 0x4 # macro +RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK = 0x00000001 # macro +RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK = 0x00000002 # macro +RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK = 0x00000004 # macro +RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK = 0x00000008 # macro +RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK = 0x00000010 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT = 0x3 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT = 0x6 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT = 0x7 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT = 0xa # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT = 0xd # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT = 0xe # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT = 0xf # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT = 0x10 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT = 0x11 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK = 0x00000007 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK = 0x00000038 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK = 0x00000040 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK = 0x00000380 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK = 0x00001C00 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK = 0x00002000 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK = 0x00004000 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK = 0x00008000 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK = 0x00010000 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK = 0x00020000 # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT = 0x1d # macro +RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK = 0x20000000 # macro +RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT = 0x4 # macro +RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK = 0x00000010 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT = 0x8 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT = 0xc # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT = 0x10 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT = 0x18 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK = 0x00000300 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK = 0x00003000 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK = 0x00FF0000 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK = 0xFF000000 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK = 0xFF # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT = 0x8 # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK = 0x001F # macro +RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK = 0x0100 # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK = 0xFF # macro +RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK = 0x1F # macro +RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT = 0xa # macro +RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT = 0xc # macro +RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT = 0x18 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT = 0x19 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT = 0x1a # macro +RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK = 0x00000C00 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK = 0x00003000 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK = 0x01000000 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK = 0x02000000 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK = 0x04000000 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT = 0x3 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT = 0x8 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK = 0x00000007 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK = 0x000000F8 # macro +RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK = 0x0000FF00 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT = 0x8 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT = 0x11 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT = 0x12 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT = 0x18 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT = 0x19 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT = 0x1a # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT = 0x1b # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT = 0x1c # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT = 0x1d # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT = 0x1e # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT = 0x1f # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK = 0x00000001 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK = 0x00000700 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK = 0x00020000 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK = 0x00040000 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK = 0x01000000 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK = 0x02000000 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK = 0x04000000 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK = 0x08000000 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK = 0x10000000 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK = 0x20000000 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK = 0x40000000 # macro +RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK = 0x80000000 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0x8 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT = 0x9 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT = 0x14 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT = 0x15 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT = 0x16 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT = 0x18 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT = 0x19 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT = 0x1a # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00000100 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK = 0x00000200 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK = 0x00100000 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK = 0x00200000 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK = 0x00400000 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK = 0x01000000 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK = 0x02000000 # macro +RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK = 0x04000000 # macro +RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT = 0x0 # macro +RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT = 0x1 # macro +RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT = 0x2 # macro +RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT = 0x3 # macro +RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK = 0x00000001 # macro +RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK = 0x00000002 # macro +RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK = 0x00000004 # macro +RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK = 0x00000008 # macro +RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT = 0x1 # macro +RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK = 0x00000002 # macro +RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT = 0xf # macro +RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN_MASK = 0x00008000 # macro +RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT = 0x0 # macro +RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT = 0x1 # macro +RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT = 0x2 # macro +RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT = 0x3 # macro +RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT = 0x4 # macro +RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK = 0x00000001 # macro +RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK = 0x00000002 # macro +RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK = 0x00000004 # macro +RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK = 0x00000008 # macro +RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK = 0x00000010 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT = 0x0 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT = 0x1 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT = 0x2 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT = 0x3 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT = 0x4 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT = 0x5 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT = 0xb # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT = 0x12 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT = 0x19 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK = 0x00000001 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK = 0x00000002 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK = 0x00000004 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK = 0x00000008 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK = 0x00000010 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK = 0x000007E0 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK = 0x0003F800 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK = 0x01FC0000 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK = 0xFE000000 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT = 0x0 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT = 0x6 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT = 0xc # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT = 0x11 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK = 0x0000003F # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK = 0x00000FC0 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK = 0x0001F000 # macro +RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK = 0x00FE0000 # macro +RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION__SHIFT = 0x4 # macro +RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION_MASK = 0x0000000F # macro +RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION_MASK = 0x000000F0 # macro +RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT = 0x1 # macro +RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK = 0x00000002 # macro +RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK = 0xFFFF # macro +RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK = 0xFFFF # macro +RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR_MASK = 0x0000FFFF # macro +RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR_MASK = 0xFFFF0000 # macro +RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR_MASK = 0x0000FFFF # macro +RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR_MASK = 0xFFFF0000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT = 0x2 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT = 0x3 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT = 0x4 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT = 0x5 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT = 0x6 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT = 0x7 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT = 0x8 # macro +RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT = 0xc # macro +RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT = 0xd # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT = 0x10 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT = 0x11 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT = 0x12 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT = 0x13 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT = 0x14 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT = 0x15 # macro +RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT = 0x18 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT = 0x19 # macro +RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT = 0x1c # macro +RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT = 0x1d # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_MASK = 0x00000004 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_MASK = 0x00000008 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS_MASK = 0x00000010 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK = 0x00000020 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK = 0x00000040 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK = 0x00000080 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK = 0x00000100 # macro +RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK = 0x00001000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK = 0x00002000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK = 0x00010000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK = 0x00020000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK = 0x00040000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK = 0x00080000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK = 0x00100000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK = 0x00200000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK = 0x01000000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK = 0x0E000000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK = 0x10000000 # macro +RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK = 0xE0000000 # macro +RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT = 0x2 # macro +RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT = 0x3 # macro +RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK = 0x00000004 # macro +RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK = 0x00000018 # macro +RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK = 0x07FFFFFF # macro +RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT = 0x1f # macro +RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK = 0x7FFFFFFF # macro +RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK = 0x80000000 # macro +RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK = 0x7FFFFFFF # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT = 0x7 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT = 0x8 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT = 0x9 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT = 0xa # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT = 0xb # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT = 0xc # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT = 0xd # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT = 0xe # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT = 0xf # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT = 0x10 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT = 0x11 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT = 0x12 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT = 0x13 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK = 0x00000080 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK = 0x00000100 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK = 0x00000200 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK = 0x00000400 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK = 0x00000800 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK = 0x00001000 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK = 0x00002000 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK = 0x00004000 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK = 0x00008000 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK = 0x00010000 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK = 0x00020000 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK = 0x00040000 # macro +RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK = 0x00080000 # macro +RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK_MASK = 0x000000FF # macro +RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1__SHIFT = 0x8 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3__SHIFT = 0x18 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0_MASK = 0x000000FF # macro +RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1_MASK = 0x0000FF00 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2_MASK = 0x00FF0000 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3_MASK = 0xFF000000 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5__SHIFT = 0x8 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7__SHIFT = 0x18 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4_MASK = 0x000000FF # macro +RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5_MASK = 0x0000FF00 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6_MASK = 0x00FF0000 # macro +RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7_MASK = 0xFF000000 # macro +RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT = 0x8 # macro +RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT = 0x11 # macro +RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK = 0x000000FF # macro +RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK = 0x00000100 # macro +RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK = 0x00010000 # macro +RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK = 0x00020000 # macro +RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK = 0x00000001 # macro +RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID_MASK = 0x0000FFFF # macro +RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK = 0x000FFFFF # macro +RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT = 0x1f # macro +RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK = 0x000FFFFF # macro +RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK = 0x80000000 # macro +RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK = 0x000FFFFF # macro +RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT = 0x1f # macro +RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK = 0x000FFFFF # macro +RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK = 0x80000000 # macro +RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK = 0x000FFFFF # macro +RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT = 0x1f # macro +RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK = 0x000FFFFF # macro +RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK = 0x80000000 # macro +RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK = 0x000FFFFF # macro +RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT = 0x1f # macro +RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK = 0x000FFFFF # macro +RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK = 0x80000000 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT = 0x8 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT = 0x18 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK = 0x000000FF # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK = 0x0000FF00 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK = 0x00FF0000 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK = 0xFF000000 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT = 0x0 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT = 0x8 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT = 0x10 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT = 0x18 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK = 0x000000FF # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK = 0x0000FF00 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK = 0x00FF0000 # macro +RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK = 0xFF000000 # macro +RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT = 0x0 # macro +RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT = 0x8 # macro +RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT = 0x10 # macro +RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT = 0x11 # macro +RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK = 0x00000001 # macro +RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK = 0x00000100 # macro +RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK = 0x00010000 # macro +RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK = 0x00020000 # macro +RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT = 0x0 # macro +RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT = 0x1 # macro +RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT = 0x2 # macro +RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT = 0x3 # macro +RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT = 0x10 # macro +RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK = 0x00000001 # macro +RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK = 0x00000002 # macro +RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK = 0x00000004 # macro +RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK = 0x00000008 # macro +RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK = 0xFFFF0000 # macro +RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT = 0x0 # macro +RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT = 0x8 # macro +RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK = 0x000000FF # macro +RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK = 0x00001F00 # macro +RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT = 0x0 # macro +RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK = 0x000003FF # macro +RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT = 0x0 # macro +RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT = 0x1 # macro +RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK = 0x00000001 # macro +RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK = 0x00007FFE # macro +BIF_BX1_PCIE_INDEX__PCIE_INDEX__SHIFT = 0x0 # macro +BIF_BX1_PCIE_INDEX__PCIE_INDEX_MASK = 0xFFFFFFFF # macro +BIF_BX1_PCIE_DATA__PCIE_DATA__SHIFT = 0x0 # macro +BIF_BX1_PCIE_DATA__PCIE_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX1_PCIE_INDEX2__PCIE_INDEX2__SHIFT = 0x0 # macro +BIF_BX1_PCIE_INDEX2__PCIE_INDEX2_MASK = 0xFFFFFFFF # macro +BIF_BX1_PCIE_DATA2__PCIE_DATA2__SHIFT = 0x0 # macro +BIF_BX1_PCIE_DATA2__PCIE_DATA2_MASK = 0xFFFFFFFF # macro +BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT = 0x0 # macro +BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK = 0x000000FF # macro +BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT = 0x0 # macro +BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK = 0x000000FF # macro +BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT = 0x0 # macro +BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK = 0xFFFFFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK = 0x000FFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK = 0x000000FF # macro +BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK = 0xFFFFFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK = 0xFFFFFFFF # macro +BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT = 0x0 # macro +BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK = 0xFFFFFFFF # macro +BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT = 0x0 # macro +BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14_MASK = 0xFFFFFFFF # macro +BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT = 0x0 # macro +BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK = 0xFFFFFFFF # macro +BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT = 0x0 # macro +BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_PF1_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_PF1_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_PF1_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_PF1_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_PF1_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT = 0x19 # macro +BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK = 0xFE000000 # macro +BIF_BX1_BIF_MM_INDACCESS_CNTL__WRITE_DIS__SHIFT = 0x0 # macro +BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT = 0x1 # macro +BIF_BX1_BIF_MM_INDACCESS_CNTL__WRITE_DIS_MASK = 0x00000001 # macro +BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK = 0x00000002 # macro +BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT = 0x6 # macro +BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT = 0x7 # macro +BIF_BX1_BUS_CNTL__SET_AZ_TC__SHIFT = 0xa # macro +BIF_BX1_BUS_CNTL__SET_MC_TC__SHIFT = 0xd # macro +BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN__SHIFT = 0x10 # macro +BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN__SHIFT = 0x11 # macro +BIF_BX1_BUS_CNTL__RD_STALL_IO_WR__SHIFT = 0x12 # macro +BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT = 0x18 # macro +BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT = 0x19 # macro +BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT = 0x1a # macro +BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT = 0x1b # macro +BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT = 0x1c # macro +BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT = 0x1d # macro +BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT = 0x1e # macro +BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT = 0x1f # macro +BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK = 0x00000040 # macro +BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK = 0x00000080 # macro +BIF_BX1_BUS_CNTL__SET_AZ_TC_MASK = 0x00001C00 # macro +BIF_BX1_BUS_CNTL__SET_MC_TC_MASK = 0x0000E000 # macro +BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN_MASK = 0x00010000 # macro +BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN_MASK = 0x00020000 # macro +BIF_BX1_BUS_CNTL__RD_STALL_IO_WR_MASK = 0x00040000 # macro +BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK = 0x01000000 # macro +BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK = 0x02000000 # macro +BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK = 0x04000000 # macro +BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK = 0x08000000 # macro +BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK = 0x10000000 # macro +BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK = 0x20000000 # macro +BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK = 0x40000000 # macro +BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK = 0x80000000 # macro +BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT = 0x0 # macro +BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT = 0x0 # macro +BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1_MASK = 0xFFFFFFFF # macro +BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT = 0x10 # macro +BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK = 0x00010000 # macro +BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT = 0x0 # macro +BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT = 0x6 # macro +BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT = 0x1f # macro +BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK = 0x00000007 # macro +BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK = 0x000000C0 # macro +BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK = 0x80000000 # macro +BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT = 0x0 # macro +BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN_MASK = 0x00000001 # macro +BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT = 0x0 # macro +BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT = 0x1 # macro +BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT = 0x3 # macro +BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT = 0x4 # macro +BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT = 0x8 # macro +BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT = 0xf # macro +BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT = 0x10 # macro +BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT = 0x11 # macro +BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT = 0x12 # macro +BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK = 0x00000001 # macro +BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK = 0x00000002 # macro +BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK = 0x00000008 # macro +BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK = 0x000000F0 # macro +BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK = 0x00000100 # macro +BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK = 0x00008000 # macro +BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK = 0x00010000 # macro +BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK = 0x00020000 # macro +BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK = 0x00040000 # macro +BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT = 0x0 # macro +BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK = 0xFFFFFFFF # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT = 0x0 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT = 0x1 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT = 0x2 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT = 0x3 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT = 0x5 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT = 0x6 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT = 0x7 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT = 0x8 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT = 0x9 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT = 0xa # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT = 0xb # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT = 0xc # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT = 0xd # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK = 0x00000001 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK = 0x00000002 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK = 0x00000004 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK = 0x00000018 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK = 0x00000020 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK = 0x00000040 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK = 0x00000080 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK = 0x00000100 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK = 0x00000200 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK = 0x00000400 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK = 0x00000800 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK = 0x00001000 # macro +BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK = 0x00002000 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT = 0x0 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT = 0x1 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT = 0x2 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT = 0x3 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT = 0xb # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT = 0xc # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT = 0xd # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS__SHIFT = 0xe # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT = 0xf # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT = 0x10 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT = 0x19 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK = 0x00000001 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK = 0x00000002 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK = 0x00000004 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK = 0x00000008 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK = 0x00000800 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK = 0x00001000 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK = 0x00002000 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS_MASK = 0x00004000 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK = 0x00008000 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK = 0x01FF0000 # macro +BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK = 0x02000000 # macro +BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT = 0x0 # macro +BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK = 0x000000FF # macro +BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT = 0x0 # macro +BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT = 0x1 # macro +BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT = 0x2 # macro +BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT = 0x3 # macro +BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT = 0x4 # macro +BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT = 0x18 # macro +BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT = 0x19 # macro +BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT = 0x1a # macro +BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT = 0x1b # macro +BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK = 0x00000001 # macro +BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK = 0x00000002 # macro +BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK = 0x00000004 # macro +BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK = 0x00000008 # macro +BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK = 0x00000010 # macro +BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK = 0x01000000 # macro +BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK = 0x02000000 # macro +BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK = 0x04000000 # macro +BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK = 0x08000000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT = 0x0 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT = 0x1 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT = 0x2 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT = 0x10 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT = 0x11 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT = 0x12 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT = 0x17 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT = 0x18 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT = 0x19 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT = 0x1a # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT = 0x1c # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT = 0x1d # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT = 0x1e # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT = 0x1f # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK = 0x00000001 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK = 0x00000002 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK = 0x00000004 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK = 0x00010000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK = 0x00020000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK = 0x00040000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK = 0x00800000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK = 0x01000000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK = 0x02000000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK = 0x04000000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK = 0x10000000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK = 0x20000000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK = 0x40000000 # macro +BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK = 0x80000000 # macro +BIF_BX1_BIF_FB_EN__FB_READ_EN__SHIFT = 0x0 # macro +BIF_BX1_BIF_FB_EN__FB_WRITE_EN__SHIFT = 0x1 # macro +BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK = 0x00000001 # macro +BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK = 0x00000002 # macro +BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT = 0x0 # macro +BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK = 0x00000001 # macro +BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK = 0x7FFFFFFF # macro +BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK = 0x7FFFFFFF # macro +BIF_BX1_BACO_CNTL__BACO_EN__SHIFT = 0x0 # macro +BIF_BX1_BACO_CNTL__BACO_DUMMY_EN__SHIFT = 0x2 # macro +BIF_BX1_BACO_CNTL__BACO_POWER_OFF__SHIFT = 0x3 # macro +BIF_BX1_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT = 0x5 # macro +BIF_BX1_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT = 0x6 # macro +BIF_BX1_BACO_CNTL__BACO_MODE__SHIFT = 0x8 # macro +BIF_BX1_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT = 0x9 # macro +BIF_BX1_BACO_CNTL__PWRGOOD_VDDSOC__SHIFT = 0x10 # macro +BIF_BX1_BACO_CNTL__BACO_AUTO_EXIT__SHIFT = 0x1f # macro +BIF_BX1_BACO_CNTL__BACO_EN_MASK = 0x00000001 # macro +BIF_BX1_BACO_CNTL__BACO_DUMMY_EN_MASK = 0x00000004 # macro +BIF_BX1_BACO_CNTL__BACO_POWER_OFF_MASK = 0x00000008 # macro +BIF_BX1_BACO_CNTL__BACO_DSTATE_BYPASS_MASK = 0x00000020 # macro +BIF_BX1_BACO_CNTL__BACO_RST_INTR_MASK_MASK = 0x00000040 # macro +BIF_BX1_BACO_CNTL__BACO_MODE_MASK = 0x00000100 # macro +BIF_BX1_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK = 0x00000200 # macro +BIF_BX1_BACO_CNTL__PWRGOOD_VDDSOC_MASK = 0x00010000 # macro +BIF_BX1_BACO_CNTL__BACO_AUTO_EXIT_MASK = 0x80000000 # macro +BIF_BX1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT = 0x0 # macro +BIF_BX1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK = 0x000FFFFF # macro +BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT = 0x0 # macro +BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT = 0x18 # macro +BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT = 0x1a # macro +BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT = 0x1b # macro +BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT = 0x1c # macro +BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT = 0x1d # macro +BIF_BX1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT = 0x1f # macro +BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK = 0x000FFFFF # macro +BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK = 0x01000000 # macro +BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK = 0x04000000 # macro +BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK = 0x08000000 # macro +BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK = 0x10000000 # macro +BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK = 0x60000000 # macro +BIF_BX1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK = 0x80000000 # macro +BIF_BX1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT = 0x0 # macro +BIF_BX1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK = 0x000FFFFF # macro +BIF_BX1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT = 0x0 # macro +BIF_BX1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK = 0x000FFFFF # macro +BIF_BX1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT = 0x0 # macro +BIF_BX1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK = 0x000FFFFF # macro +BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT = 0x0 # macro +BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK = 0x00000001 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT = 0x1 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT = 0x8 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK = 0x00000001 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK = 0x00000002 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK = 0x00000100 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT = 0x0 # macro +BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR_MASK = 0x00FFFFFF # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0__SHIFT = 0x0 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1__SHIFT = 0x1 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2__SHIFT = 0x2 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3__SHIFT = 0x3 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4__SHIFT = 0x4 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5__SHIFT = 0x5 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6__SHIFT = 0x6 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7__SHIFT = 0x7 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8__SHIFT = 0x8 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9__SHIFT = 0x9 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10__SHIFT = 0xa # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11__SHIFT = 0xb # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12__SHIFT = 0xc # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13__SHIFT = 0xd # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14__SHIFT = 0xe # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15__SHIFT = 0xf # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16__SHIFT = 0x10 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17__SHIFT = 0x11 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18__SHIFT = 0x12 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19__SHIFT = 0x13 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20__SHIFT = 0x14 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21__SHIFT = 0x15 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22__SHIFT = 0x16 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23__SHIFT = 0x17 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24__SHIFT = 0x18 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25__SHIFT = 0x19 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26__SHIFT = 0x1a # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27__SHIFT = 0x1b # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28__SHIFT = 0x1c # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29__SHIFT = 0x1d # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30__SHIFT = 0x1e # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0_MASK = 0x00000001 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1_MASK = 0x00000002 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2_MASK = 0x00000004 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3_MASK = 0x00000008 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4_MASK = 0x00000010 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5_MASK = 0x00000020 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6_MASK = 0x00000040 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7_MASK = 0x00000080 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8_MASK = 0x00000100 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9_MASK = 0x00000200 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10_MASK = 0x00000400 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11_MASK = 0x00000800 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12_MASK = 0x00001000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13_MASK = 0x00002000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14_MASK = 0x00004000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15_MASK = 0x00008000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16_MASK = 0x00010000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17_MASK = 0x00020000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18_MASK = 0x00040000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19_MASK = 0x00080000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20_MASK = 0x00100000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21_MASK = 0x00200000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22_MASK = 0x00400000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23_MASK = 0x00800000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24_MASK = 0x01000000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25_MASK = 0x02000000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26_MASK = 0x04000000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27_MASK = 0x08000000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28_MASK = 0x10000000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29_MASK = 0x20000000 # macro +BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30_MASK = 0x40000000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0__SHIFT = 0x0 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1__SHIFT = 0x1 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2__SHIFT = 0x2 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3__SHIFT = 0x3 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4__SHIFT = 0x4 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5__SHIFT = 0x5 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6__SHIFT = 0x6 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7__SHIFT = 0x7 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8__SHIFT = 0x8 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9__SHIFT = 0x9 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10__SHIFT = 0xa # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11__SHIFT = 0xb # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12__SHIFT = 0xc # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13__SHIFT = 0xd # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14__SHIFT = 0xe # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15__SHIFT = 0xf # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16__SHIFT = 0x10 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17__SHIFT = 0x11 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18__SHIFT = 0x12 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19__SHIFT = 0x13 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20__SHIFT = 0x14 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21__SHIFT = 0x15 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22__SHIFT = 0x16 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23__SHIFT = 0x17 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24__SHIFT = 0x18 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25__SHIFT = 0x19 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26__SHIFT = 0x1a # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27__SHIFT = 0x1b # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28__SHIFT = 0x1c # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29__SHIFT = 0x1d # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30__SHIFT = 0x1e # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS__SHIFT = 0x1f # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0_MASK = 0x00000001 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1_MASK = 0x00000002 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2_MASK = 0x00000004 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3_MASK = 0x00000008 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4_MASK = 0x00000010 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5_MASK = 0x00000020 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6_MASK = 0x00000040 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7_MASK = 0x00000080 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8_MASK = 0x00000100 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9_MASK = 0x00000200 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10_MASK = 0x00000400 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11_MASK = 0x00000800 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12_MASK = 0x00001000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13_MASK = 0x00002000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14_MASK = 0x00004000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15_MASK = 0x00008000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16_MASK = 0x00010000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17_MASK = 0x00020000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18_MASK = 0x00040000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19_MASK = 0x00080000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20_MASK = 0x00100000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21_MASK = 0x00200000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22_MASK = 0x00400000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23_MASK = 0x00800000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24_MASK = 0x01000000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25_MASK = 0x02000000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26_MASK = 0x04000000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27_MASK = 0x08000000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28_MASK = 0x10000000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29_MASK = 0x20000000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30_MASK = 0x40000000 # macro +BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS_MASK = 0x80000000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF0__SHIFT = 0x0 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF1__SHIFT = 0x1 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF2__SHIFT = 0x2 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF3__SHIFT = 0x3 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF4__SHIFT = 0x4 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF5__SHIFT = 0x5 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF6__SHIFT = 0x6 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF7__SHIFT = 0x7 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF8__SHIFT = 0x8 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF9__SHIFT = 0x9 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF10__SHIFT = 0xa # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF11__SHIFT = 0xb # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF12__SHIFT = 0xc # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF13__SHIFT = 0xd # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF14__SHIFT = 0xe # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF15__SHIFT = 0xf # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF16__SHIFT = 0x10 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF17__SHIFT = 0x11 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF18__SHIFT = 0x12 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF19__SHIFT = 0x13 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF20__SHIFT = 0x14 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF21__SHIFT = 0x15 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF22__SHIFT = 0x16 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF23__SHIFT = 0x17 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF24__SHIFT = 0x18 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF25__SHIFT = 0x19 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF26__SHIFT = 0x1a # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF27__SHIFT = 0x1b # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF28__SHIFT = 0x1c # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF29__SHIFT = 0x1d # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF30__SHIFT = 0x1e # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF0_MASK = 0x00000001 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF1_MASK = 0x00000002 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF2_MASK = 0x00000004 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF3_MASK = 0x00000008 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF4_MASK = 0x00000010 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF5_MASK = 0x00000020 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF6_MASK = 0x00000040 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF7_MASK = 0x00000080 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF8_MASK = 0x00000100 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF9_MASK = 0x00000200 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF10_MASK = 0x00000400 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF11_MASK = 0x00000800 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF12_MASK = 0x00001000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF13_MASK = 0x00002000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF14_MASK = 0x00004000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF15_MASK = 0x00008000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF16_MASK = 0x00010000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF17_MASK = 0x00020000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF18_MASK = 0x00040000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF19_MASK = 0x00080000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF20_MASK = 0x00100000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF21_MASK = 0x00200000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF22_MASK = 0x00400000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF23_MASK = 0x00800000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF24_MASK = 0x01000000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF25_MASK = 0x02000000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF26_MASK = 0x04000000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF27_MASK = 0x08000000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF28_MASK = 0x10000000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF29_MASK = 0x20000000 # macro +BIF_BX1_VF_FB_EN__VF_FB_EN_VF30_MASK = 0x40000000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0__SHIFT = 0x0 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1__SHIFT = 0x1 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2__SHIFT = 0x2 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3__SHIFT = 0x3 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4__SHIFT = 0x4 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5__SHIFT = 0x5 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6__SHIFT = 0x6 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7__SHIFT = 0x7 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8__SHIFT = 0x8 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9__SHIFT = 0x9 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10__SHIFT = 0xa # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11__SHIFT = 0xb # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12__SHIFT = 0xc # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13__SHIFT = 0xd # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14__SHIFT = 0xe # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15__SHIFT = 0xf # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16__SHIFT = 0x10 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17__SHIFT = 0x11 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18__SHIFT = 0x12 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19__SHIFT = 0x13 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20__SHIFT = 0x14 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21__SHIFT = 0x15 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22__SHIFT = 0x16 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23__SHIFT = 0x17 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24__SHIFT = 0x18 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25__SHIFT = 0x19 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26__SHIFT = 0x1a # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27__SHIFT = 0x1b # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28__SHIFT = 0x1c # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29__SHIFT = 0x1d # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30__SHIFT = 0x1e # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0_MASK = 0x00000001 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1_MASK = 0x00000002 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2_MASK = 0x00000004 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3_MASK = 0x00000008 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4_MASK = 0x00000010 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5_MASK = 0x00000020 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6_MASK = 0x00000040 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7_MASK = 0x00000080 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8_MASK = 0x00000100 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9_MASK = 0x00000200 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10_MASK = 0x00000400 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11_MASK = 0x00000800 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12_MASK = 0x00001000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13_MASK = 0x00002000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14_MASK = 0x00004000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15_MASK = 0x00008000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16_MASK = 0x00010000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17_MASK = 0x00020000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18_MASK = 0x00040000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19_MASK = 0x00080000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20_MASK = 0x00100000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21_MASK = 0x00200000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22_MASK = 0x00400000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23_MASK = 0x00800000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24_MASK = 0x01000000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25_MASK = 0x02000000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26_MASK = 0x04000000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27_MASK = 0x08000000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28_MASK = 0x10000000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29_MASK = 0x20000000 # macro +BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30_MASK = 0x40000000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0__SHIFT = 0x0 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1__SHIFT = 0x1 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2__SHIFT = 0x2 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3__SHIFT = 0x3 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4__SHIFT = 0x4 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5__SHIFT = 0x5 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6__SHIFT = 0x6 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7__SHIFT = 0x7 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8__SHIFT = 0x8 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9__SHIFT = 0x9 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10__SHIFT = 0xa # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11__SHIFT = 0xb # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12__SHIFT = 0xc # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13__SHIFT = 0xd # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14__SHIFT = 0xe # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15__SHIFT = 0xf # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16__SHIFT = 0x10 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17__SHIFT = 0x11 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18__SHIFT = 0x12 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19__SHIFT = 0x13 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20__SHIFT = 0x14 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21__SHIFT = 0x15 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22__SHIFT = 0x16 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23__SHIFT = 0x17 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24__SHIFT = 0x18 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25__SHIFT = 0x19 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26__SHIFT = 0x1a # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27__SHIFT = 0x1b # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28__SHIFT = 0x1c # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29__SHIFT = 0x1d # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30__SHIFT = 0x1e # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0_MASK = 0x00000001 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1_MASK = 0x00000002 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2_MASK = 0x00000004 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3_MASK = 0x00000008 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4_MASK = 0x00000010 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5_MASK = 0x00000020 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6_MASK = 0x00000040 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7_MASK = 0x00000080 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8_MASK = 0x00000100 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9_MASK = 0x00000200 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10_MASK = 0x00000400 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11_MASK = 0x00000800 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12_MASK = 0x00001000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13_MASK = 0x00002000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14_MASK = 0x00004000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15_MASK = 0x00008000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16_MASK = 0x00010000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17_MASK = 0x00020000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18_MASK = 0x00040000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19_MASK = 0x00080000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20_MASK = 0x00100000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21_MASK = 0x00200000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22_MASK = 0x00400000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23_MASK = 0x00800000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24_MASK = 0x01000000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25_MASK = 0x02000000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26_MASK = 0x04000000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27_MASK = 0x08000000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28_MASK = 0x10000000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29_MASK = 0x20000000 # macro +BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30_MASK = 0x40000000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0__SHIFT = 0x0 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1__SHIFT = 0x1 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2__SHIFT = 0x2 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3__SHIFT = 0x3 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4__SHIFT = 0x4 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5__SHIFT = 0x5 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6__SHIFT = 0x6 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7__SHIFT = 0x7 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8__SHIFT = 0x8 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9__SHIFT = 0x9 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10__SHIFT = 0xa # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11__SHIFT = 0xb # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12__SHIFT = 0xc # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13__SHIFT = 0xd # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14__SHIFT = 0xe # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15__SHIFT = 0xf # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16__SHIFT = 0x10 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17__SHIFT = 0x11 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18__SHIFT = 0x12 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19__SHIFT = 0x13 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20__SHIFT = 0x14 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21__SHIFT = 0x15 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22__SHIFT = 0x16 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23__SHIFT = 0x17 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24__SHIFT = 0x18 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25__SHIFT = 0x19 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26__SHIFT = 0x1a # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27__SHIFT = 0x1b # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28__SHIFT = 0x1c # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29__SHIFT = 0x1d # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30__SHIFT = 0x1e # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0_MASK = 0x00000001 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1_MASK = 0x00000002 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2_MASK = 0x00000004 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3_MASK = 0x00000008 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4_MASK = 0x00000010 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5_MASK = 0x00000020 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6_MASK = 0x00000040 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7_MASK = 0x00000080 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8_MASK = 0x00000100 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9_MASK = 0x00000200 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10_MASK = 0x00000400 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11_MASK = 0x00000800 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12_MASK = 0x00001000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13_MASK = 0x00002000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14_MASK = 0x00004000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15_MASK = 0x00008000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16_MASK = 0x00010000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17_MASK = 0x00020000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18_MASK = 0x00040000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19_MASK = 0x00080000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20_MASK = 0x00100000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21_MASK = 0x00200000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22_MASK = 0x00400000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23_MASK = 0x00800000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24_MASK = 0x01000000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25_MASK = 0x02000000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26_MASK = 0x04000000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27_MASK = 0x08000000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28_MASK = 0x10000000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29_MASK = 0x20000000 # macro +BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30_MASK = 0x40000000 # macro +BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT = 0x2 # macro +BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK = 0x0007FFFC # macro +BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT = 0x2 # macro +BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK = 0x0007FFFC # macro +BIF_BX1_BIF_RB_CNTL__RB_ENABLE__SHIFT = 0x0 # macro +BIF_BX1_BIF_RB_CNTL__RB_SIZE__SHIFT = 0x1 # macro +BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT = 0x8 # macro +BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT = 0x9 # macro +BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT = 0x11 # macro +BIF_BX1_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL__SHIFT = 0x19 # macro +BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT = 0x1a # macro +BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT = 0x1d # macro +BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT = 0x1e # macro +BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT = 0x1f # macro +BIF_BX1_BIF_RB_CNTL__RB_ENABLE_MASK = 0x00000001 # macro +BIF_BX1_BIF_RB_CNTL__RB_SIZE_MASK = 0x0000003E # macro +BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK = 0x00000100 # macro +BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK = 0x00003E00 # macro +BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN_MASK = 0x00020000 # macro +BIF_BX1_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL_MASK = 0x02000000 # macro +BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK = 0x1C000000 # macro +BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK = 0x20000000 # macro +BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK = 0x40000000 # macro +BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK = 0x80000000 # macro +BIF_BX1_BIF_RB_BASE__ADDR__SHIFT = 0x0 # macro +BIF_BX1_BIF_RB_BASE__ADDR_MASK = 0xFFFFFFFF # macro +BIF_BX1_BIF_RB_RPTR__OFFSET__SHIFT = 0x2 # macro +BIF_BX1_BIF_RB_RPTR__OFFSET_MASK = 0x0003FFFC # macro +BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT = 0x0 # macro +BIF_BX1_BIF_RB_WPTR__OFFSET__SHIFT = 0x2 # macro +BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK = 0x00000001 # macro +BIF_BX1_BIF_RB_WPTR__OFFSET_MASK = 0x0003FFFC # macro +BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT = 0x0 # macro +BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR_MASK = 0x000000FF # macro +BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT = 0x2 # macro +BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR_MASK = 0xFFFFFFFC # macro +BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT = 0x0 # macro +BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX_MASK = 0x0000001F # macro +BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT = 0x0 # macro +BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK = 0x00000001 # macro +BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT = 0x0 # macro +BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK = 0x0000FFFF # macro +BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT = 0x0 # macro +BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK = 0x00000FFF # macro +BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT = 0x0 # macro +BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK = 0x000000FF # macro +BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT = 0x0 # macro +BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK = 0x7FFFFFFF # macro +BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT = 0x0 # macro +BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK = 0x000000FF # macro +BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE__SHIFT = 0x0 # macro +BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE_MASK = 0x0000000F # macro +BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE__SHIFT = 0x0 # macro +BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE_MASK = 0x0000000F # macro +BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_PF1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT = 0x0 # macro +BIF_BX_PF1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT = 0x1 # macro +BIF_BX_PF1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT = 0x2 # macro +BIF_BX_PF1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT = 0x3 # macro +BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT = 0x4 # macro +BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT = 0xa # macro +BIF_BX_PF1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK = 0x00000001 # macro +BIF_BX_PF1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK = 0x00000002 # macro +BIF_BX_PF1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK = 0x00000004 # macro +BIF_BX_PF1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK = 0x00000008 # macro +BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK = 0x00000010 # macro +BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK = 0x0003FC00 # macro +BIF_BX_PF1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT = 0x0 # macro +BIF_BX_PF1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT = 0x1 # macro +BIF_BX_PF1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT = 0x2 # macro +BIF_BX_PF1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT = 0x3 # macro +BIF_BX_PF1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT = 0x5 # macro +BIF_BX_PF1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT = 0x7 # macro +BIF_BX_PF1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK = 0x00000001 # macro +BIF_BX_PF1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK = 0x00000002 # macro +BIF_BX_PF1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK = 0x00000004 # macro +BIF_BX_PF1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK = 0x00000008 # macro +BIF_BX_PF1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK = 0x00000020 # macro +BIF_BX_PF1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK = 0x00000080 # macro +BIF_BX_PF1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT = 0x4 # macro +BIF_BX_PF1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK = 0x000000F0 # macro +BIF_BX_PF1_PARTITION_MEM_STATUS__CHANGE_STATUE__SHIFT = 0x0 # macro +BIF_BX_PF1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT = 0x4 # macro +BIF_BX_PF1_PARTITION_MEM_STATUS__CHANGE_STATUE_MASK = 0x0000000F # macro +BIF_BX_PF1_PARTITION_MEM_STATUS__NPS_MODE_MASK = 0x00000FF0 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT = 0x1 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT = 0x2 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT = 0x3 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT = 0x6 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT = 0x7 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT = 0x9 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT = 0xa # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT = 0xb # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT = 0xc # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT = 0xd # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT = 0xe # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT = 0xf # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT = 0x11 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT = 0x19 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT = 0x1a # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT = 0x1b # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK = 0x00000001 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK = 0x00000002 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK = 0x00000004 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK = 0x00000038 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK = 0x00000040 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK = 0x00000080 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK = 0x00000100 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK = 0x00000200 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK = 0x00000400 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK = 0x00000800 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK = 0x00001000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK = 0x00002000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK = 0x00004000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK = 0x00008000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK = 0x00010000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK = 0x00020000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK = 0x000C0000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK = 0x01000000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK = 0x02000000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK = 0x04000000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK = 0x08000000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK = 0x10000000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT = 0x1 # macro +RCC_STRAP2_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT = 0x2 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT = 0x3 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT = 0x5 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT = 0x6 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT = 0x7 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT = 0x9 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT = 0xa # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT = 0xc # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT = 0xd # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT = 0xf # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT = 0x11 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT = 0x13 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT = 0x16 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT = 0x17 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT = 0x19 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT = 0x1a # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT = 0x1b # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK = 0x00000001 # macro +RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK = 0x00000002 # macro +RCC_STRAP2_RCC_BIF_STRAP1__WRITE_DISABLE_MASK = 0x00000004 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK = 0x00000008 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK = 0x00000020 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK = 0x00000040 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK = 0x00000080 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK = 0x00000100 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK = 0x00000200 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK = 0x00000C00 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK = 0x00001000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK = 0x00006000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK = 0x00018000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK = 0x00020000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK = 0x00040000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK = 0x00080000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK = 0x00200000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK = 0x00400000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK = 0x00800000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK = 0x01000000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK = 0x02000000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK = 0x04000000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK = 0x18000000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT = 0x3 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT = 0x4 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT = 0x5 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT = 0x6 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN__SHIFT = 0x7 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT = 0x9 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT = 0xa # macro +RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT = 0xd # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT = 0xe # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT = 0xf # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK = 0x00000001 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK = 0x00000008 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK = 0x00000010 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK = 0x00000020 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK = 0x00000040 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN_MASK = 0x00000080 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK = 0x00000100 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK = 0x00000200 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK = 0x00000C00 # macro +RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK = 0x00002000 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK = 0x00004000 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK = 0x00008000 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK = 0x00FF0000 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK = 0x01000000 # macro +RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK = 0xFFFF0000 # macro +RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK = 0xFFFF0000 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT = 0x11 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT = 0x13 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT = 0x16 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x19 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1b # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK = 0x00010000 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK = 0x00020000 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK = 0x00040000 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK = 0x00080000 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK = 0x00200000 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK = 0x00C00000 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK = 0x01000000 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x06000000 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x08000000 # macro +RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK = 0x70000000 # macro +RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT = 0x1 # macro +RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT = 0x2 # macro +RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK = 0x00000001 # macro +RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK = 0x00000002 # macro +RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK = 0x00000004 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT = 0x11 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT = 0x13 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT = 0x19 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK = 0x00010000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK = 0x00020000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK = 0x00040000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK = 0x00080000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK = 0x00E00000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK = 0x01000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK = 0x0E000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK = 0x70000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK = 0xFFFF0000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT = 0x2 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT = 0x3 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT = 0x4 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT = 0x5 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT = 0x6 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK = 0x00000001 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK = 0x00000004 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK = 0x00000008 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK = 0x00000010 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK = 0x00000020 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK = 0x0007FFC0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK = 0x0FFF0000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK = 0x10000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK = 0x00FFFFFF # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT = 0x9 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK = 0x000000FF # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK = 0x00000100 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK = 0x000FFE00 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK = 0xFFF00000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT = 0x2 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT = 0x3 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT = 0x4 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK = 0x00000001 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK = 0x00000004 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK = 0x00000008 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK = 0x00000010 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT = 0x2 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT = 0x3 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT = 0x4 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT = 0x5 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT = 0x6 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT = 0x7 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT = 0x9 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT = 0xc # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT = 0xd # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT = 0xe # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT = 0xf # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT = 0x11 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT = 0x17 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT = 0x1a # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK = 0x00000001 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK = 0x00000004 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK = 0x00000008 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK = 0x00000010 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK = 0x00000020 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK = 0x00000040 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK = 0x00000080 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK = 0x00000100 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK = 0x00000E00 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK = 0x00001000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK = 0x00002000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK = 0x00004000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK = 0x00008000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK = 0x00010000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK = 0x00020000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK = 0x00700000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK = 0x03800000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK = 0x1C000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK = 0xE0000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT = 0x1 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT = 0x2 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT = 0x3 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT = 0x6 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT = 0x7 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT = 0x9 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT = 0xb # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT = 0xe # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT = 0x19 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT = 0x1b # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK = 0x00000001 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK = 0x00000002 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK = 0x00000004 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK = 0x00000038 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK = 0x00000040 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK = 0x00000080 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK = 0x00000100 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK = 0x00000600 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK = 0x00003800 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK = 0x0003C000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK = 0x001C0000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK = 0x01E00000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK = 0x06000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK = 0x18000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK = 0x000000FF # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK = 0x00FF0000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK = 0xFF000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT = 0x11 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT = 0x13 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT = 0x16 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT = 0x17 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT = 0x19 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT = 0x1a # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT = 0x1b # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK = 0x000000FF # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK = 0x00010000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK = 0x00020000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK = 0x00040000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK = 0x00080000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK = 0x00200000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK = 0x00400000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK = 0x00800000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK = 0x01000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK = 0x02000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK = 0x04000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK = 0x08000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK = 0x10000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT = 0x1 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT = 0x2 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT = 0x3 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT = 0x4 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT = 0x5 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT = 0x6 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT = 0x7 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT = 0xc # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT = 0x13 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK = 0x00000001 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK = 0x00000002 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK = 0x00000004 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK = 0x00000008 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK = 0x00000010 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK = 0x00000020 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK = 0x00000040 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK = 0x00000080 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK = 0x00000F00 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK = 0x0000F000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK = 0x00030000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK = 0x00040000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK = 0x00080000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK = 0x00E00000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK = 0x0F000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK = 0xF0000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT = 0xc # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK = 0x000000FF # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK = 0x00000F00 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK = 0x0000F000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK = 0x00FF0000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK = 0x1F000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK = 0xE0000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK = 0x000000FF # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK = 0x00FF0000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK = 0xFF000000 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK = 0x000000FF # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK = 0x0000FF00 # macro +RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK = 0xFFFF0000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK = 0x000F0000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK = 0x00F00000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK = 0x0F000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK = 0x10000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK = 0xFFFF0000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK = 0x000000FF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK = 0x0000FF00 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK = 0x00FF0000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK = 0xFF000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT = 0xc # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT = 0x19 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK = 0x00FFF000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK = 0x01000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK = 0x3E000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT = 0xc # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK = 0x00FFF000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT = 0xc # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT = 0xd # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK = 0x00001000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK = 0x01FFE000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT = 0x6 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT = 0x7 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT = 0x9 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT = 0xe # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT = 0xf # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT = 0x11 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT = 0x16 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT = 0x17 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT = 0x1b # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK = 0x00000001 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK = 0x00000040 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK = 0x00000080 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK = 0x00000100 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK = 0x00003E00 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK = 0x00004000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK = 0x00008000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK = 0x00010000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK = 0x00020000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK = 0x00040000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK = 0x00200000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK = 0x00400000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK = 0x00800000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK = 0x07000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK = 0x08000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK = 0x10000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK = 0x00000FFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT = 0x11 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT = 0x13 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT = 0x1a # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT = 0x1b # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK = 0x00010000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK = 0x00020000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK = 0x00040000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK = 0x00080000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK = 0x00E00000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK = 0x01000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK = 0x04000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK = 0x08000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK = 0x10000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT = 0xa # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT = 0x16 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT = 0x17 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK = 0x000003FF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK = 0x00000400 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK = 0x00200000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK = 0x00400000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK = 0x0F800000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK = 0x70000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT = 0x3 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT = 0x4 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT = 0x7 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT = 0x9 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT = 0xd # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT = 0x13 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT = 0x17 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT = 0x1a # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT = 0x1b # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK = 0x00000007 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK = 0x00000008 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK = 0x00000070 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK = 0x00000080 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK = 0x00000100 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK = 0x00001E00 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK = 0x0000E000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK = 0x00070000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK = 0x00780000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK = 0x03800000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK = 0x04000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK = 0x38000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK = 0xC0000000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT = 0x13 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT = 0x16 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK = 0x00040000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK = 0x00080000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK = 0x00200000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK = 0x00C00000 # macro +RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK = 0x0F000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK = 0x000F0000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK = 0x00F00000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK = 0x10000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT = 0x7 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT = 0x8 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT = 0x9 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT = 0xe # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT = 0x11 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT = 0x17 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK = 0x00000080 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK = 0x00000100 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK = 0x00003E00 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK = 0x00004000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK = 0x00010000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK = 0x00020000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK = 0x00200000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK = 0x00800000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK = 0x07000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK = 0x10000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT = 0x10 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT = 0x11 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT = 0x12 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT = 0x13 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT = 0x18 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT = 0x1a # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT = 0x1b # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT = 0x1d # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK = 0x00010000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK = 0x00020000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK = 0x00040000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK = 0x00080000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK = 0x01000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK = 0x04000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK = 0x08000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK = 0x20000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT = 0x14 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT = 0x15 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT = 0x16 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT = 0x17 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT = 0x1c # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT = 0x1f # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK = 0x00100000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK = 0x00200000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK = 0x00400000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK = 0x0F800000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK = 0x70000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK = 0x80000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT = 0x1b # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT = 0x1e # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK = 0x0000FFFF # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK = 0x38000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK = 0x40000000 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT = 0x0 # macro +RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE__SHIFT = 0x0 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID__SHIFT = 0x1 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE__SHIFT = 0x6 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET__SHIFT = 0x7 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE__SHIFT = 0x11 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS__SHIFT = 0x19 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET__SHIFT = 0x1a # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE__SHIFT = 0x1c # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE_MASK = 0x00000001 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID_MASK = 0x0000003E # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE_MASK = 0x00000040 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET_MASK = 0x0001FF80 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE_MASK = 0x01FE0000 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS_MASK = 0x02000000 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET_MASK = 0x04000000 # macro +S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE_MASK = 0xF0000000 # macro +S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT = 0x0 # macro +S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK = 0x00000001 # macro +GDC1_A2S_CNTL_CL0__NSNOOP_MAP__SHIFT = 0x0 # macro +GDC1_A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT = 0x2 # macro +GDC1_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT = 0x4 # macro +GDC1_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT = 0x6 # macro +GDC1_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT = 0x8 # macro +GDC1_A2S_CNTL_CL0__BLKLVL_MAP__SHIFT = 0xa # macro +GDC1_A2S_CNTL_CL0__DATERR_MAP__SHIFT = 0xc # macro +GDC1_A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT = 0xe # macro +GDC1_A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT = 0x10 # macro +GDC1_A2S_CNTL_CL0__RESP_WR_MAP__SHIFT = 0x12 # macro +GDC1_A2S_CNTL_CL0__RESP_RD_MAP__SHIFT = 0x14 # macro +GDC1_A2S_CNTL_CL0__RDRSP_ERRMAP__SHIFT = 0x16 # macro +GDC1_A2S_CNTL_CL0__RDRSP_SEL_MODE__SHIFT = 0x18 # macro +GDC1_A2S_CNTL_CL0__STATIC_VC_ENABLE__SHIFT = 0x1b # macro +GDC1_A2S_CNTL_CL0__STATIC_VC_VALUE__SHIFT = 0x1c # macro +GDC1_A2S_CNTL_CL0__NSNOOP_MAP_MASK = 0x00000003 # macro +GDC1_A2S_CNTL_CL0__REQPASSPW_VC0_MAP_MASK = 0x0000000C # macro +GDC1_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP_MASK = 0x00000030 # macro +GDC1_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP_MASK = 0x000000C0 # macro +GDC1_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP_MASK = 0x00000300 # macro +GDC1_A2S_CNTL_CL0__BLKLVL_MAP_MASK = 0x00000C00 # macro +GDC1_A2S_CNTL_CL0__DATERR_MAP_MASK = 0x00003000 # macro +GDC1_A2S_CNTL_CL0__EXOKAY_WR_MAP_MASK = 0x0000C000 # macro +GDC1_A2S_CNTL_CL0__EXOKAY_RD_MAP_MASK = 0x00030000 # macro +GDC1_A2S_CNTL_CL0__RESP_WR_MAP_MASK = 0x000C0000 # macro +GDC1_A2S_CNTL_CL0__RESP_RD_MAP_MASK = 0x00300000 # macro +GDC1_A2S_CNTL_CL0__RDRSP_ERRMAP_MASK = 0x00C00000 # macro +GDC1_A2S_CNTL_CL0__RDRSP_SEL_MODE_MASK = 0x07000000 # macro +GDC1_A2S_CNTL_CL0__STATIC_VC_ENABLE_MASK = 0x08000000 # macro +GDC1_A2S_CNTL_CL0__STATIC_VC_VALUE_MASK = 0x70000000 # macro +GDC1_A2S_CNTL_CL1__NSNOOP_MAP__SHIFT = 0x0 # macro +GDC1_A2S_CNTL_CL1__REQPASSPW_VC0_MAP__SHIFT = 0x2 # macro +GDC1_A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__SHIFT = 0x4 # macro +GDC1_A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__SHIFT = 0x6 # macro +GDC1_A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__SHIFT = 0x8 # macro +GDC1_A2S_CNTL_CL1__BLKLVL_MAP__SHIFT = 0xa # macro +GDC1_A2S_CNTL_CL1__DATERR_MAP__SHIFT = 0xc # macro +GDC1_A2S_CNTL_CL1__EXOKAY_WR_MAP__SHIFT = 0xe # macro +GDC1_A2S_CNTL_CL1__EXOKAY_RD_MAP__SHIFT = 0x10 # macro +GDC1_A2S_CNTL_CL1__RESP_WR_MAP__SHIFT = 0x12 # macro +GDC1_A2S_CNTL_CL1__RESP_RD_MAP__SHIFT = 0x14 # macro +GDC1_A2S_CNTL_CL1__RDRSP_ERRMAP__SHIFT = 0x16 # macro +GDC1_A2S_CNTL_CL1__RDRSP_SEL_MODE__SHIFT = 0x18 # macro +GDC1_A2S_CNTL_CL1__STATIC_VC_ENABLE__SHIFT = 0x1b # macro +GDC1_A2S_CNTL_CL1__STATIC_VC_VALUE__SHIFT = 0x1c # macro +GDC1_A2S_CNTL_CL1__NSNOOP_MAP_MASK = 0x00000003 # macro +GDC1_A2S_CNTL_CL1__REQPASSPW_VC0_MAP_MASK = 0x0000000C # macro +GDC1_A2S_CNTL_CL1__REQPASSPW_NVC0_MAP_MASK = 0x00000030 # macro +GDC1_A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP_MASK = 0x000000C0 # macro +GDC1_A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP_MASK = 0x00000300 # macro +GDC1_A2S_CNTL_CL1__BLKLVL_MAP_MASK = 0x00000C00 # macro +GDC1_A2S_CNTL_CL1__DATERR_MAP_MASK = 0x00003000 # macro +GDC1_A2S_CNTL_CL1__EXOKAY_WR_MAP_MASK = 0x0000C000 # macro +GDC1_A2S_CNTL_CL1__EXOKAY_RD_MAP_MASK = 0x00030000 # macro +GDC1_A2S_CNTL_CL1__RESP_WR_MAP_MASK = 0x000C0000 # macro +GDC1_A2S_CNTL_CL1__RESP_RD_MAP_MASK = 0x00300000 # macro +GDC1_A2S_CNTL_CL1__RDRSP_ERRMAP_MASK = 0x00C00000 # macro +GDC1_A2S_CNTL_CL1__RDRSP_SEL_MODE_MASK = 0x07000000 # macro +GDC1_A2S_CNTL_CL1__STATIC_VC_ENABLE_MASK = 0x08000000 # macro +GDC1_A2S_CNTL_CL1__STATIC_VC_VALUE_MASK = 0x70000000 # macro +GDC1_A2S_CNTL3_CL0__FORCE_WR_PH__SHIFT = 0x0 # macro +GDC1_A2S_CNTL3_CL0__FORCE_WR_STEERING__SHIFT = 0x2 # macro +GDC1_A2S_CNTL3_CL0__WR_ST_TAG_MODE__SHIFT = 0x3 # macro +GDC1_A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY__SHIFT = 0x4 # macro +GDC1_A2S_CNTL3_CL0__FORCE_WR_PH_MASK = 0x00000003 # macro +GDC1_A2S_CNTL3_CL0__FORCE_WR_STEERING_MASK = 0x00000004 # macro +GDC1_A2S_CNTL3_CL0__WR_ST_TAG_MODE_MASK = 0x00000008 # macro +GDC1_A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY_MASK = 0x000003F0 # macro +GDC1_A2S_CNTL3_CL1__FORCE_WR_PH__SHIFT = 0x0 # macro +GDC1_A2S_CNTL3_CL1__FORCE_WR_STEERING__SHIFT = 0x2 # macro +GDC1_A2S_CNTL3_CL1__WR_ST_TAG_MODE__SHIFT = 0x3 # macro +GDC1_A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY__SHIFT = 0x4 # macro +GDC1_A2S_CNTL3_CL1__FORCE_WR_PH_MASK = 0x00000003 # macro +GDC1_A2S_CNTL3_CL1__FORCE_WR_STEERING_MASK = 0x00000004 # macro +GDC1_A2S_CNTL3_CL1__WR_ST_TAG_MODE_MASK = 0x00000008 # macro +GDC1_A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY_MASK = 0x000003F0 # macro +GDC1_A2S_CNTL_SW0__STATIC_VC_ENABLE__SHIFT = 0x0 # macro +GDC1_A2S_CNTL_SW0__STATIC_VC_VALUE__SHIFT = 0x1 # macro +GDC1_A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__SHIFT = 0x6 # macro +GDC1_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT = 0x9 # macro +GDC1_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE__SHIFT = 0xa # macro +GDC1_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT = 0xb # macro +GDC1_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT = 0xc # macro +GDC1_A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT = 0x10 # macro +GDC1_A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT = 0x18 # macro +GDC1_A2S_CNTL_SW0__STATIC_VC_ENABLE_MASK = 0x00000001 # macro +GDC1_A2S_CNTL_SW0__STATIC_VC_VALUE_MASK = 0x0000000E # macro +GDC1_A2S_CNTL_SW0__FORCE_RSP_REORDER_EN_MASK = 0x00000040 # macro +GDC1_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK = 0x00000200 # macro +GDC1_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE_MASK = 0x00000400 # macro +GDC1_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE_MASK = 0x00000800 # macro +GDC1_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK = 0x00001000 # macro +GDC1_A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK = 0x00FF0000 # macro +GDC1_A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK = 0xFF000000 # macro +GDC1_A2S_CNTL_SW1__STATIC_VC_ENABLE__SHIFT = 0x0 # macro +GDC1_A2S_CNTL_SW1__STATIC_VC_VALUE__SHIFT = 0x1 # macro +GDC1_A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__SHIFT = 0x6 # macro +GDC1_A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT = 0x9 # macro +GDC1_A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE__SHIFT = 0xa # macro +GDC1_A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT = 0xb # macro +GDC1_A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT = 0xc # macro +GDC1_A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT = 0x10 # macro +GDC1_A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT = 0x18 # macro +GDC1_A2S_CNTL_SW1__STATIC_VC_ENABLE_MASK = 0x00000001 # macro +GDC1_A2S_CNTL_SW1__STATIC_VC_VALUE_MASK = 0x0000000E # macro +GDC1_A2S_CNTL_SW1__FORCE_RSP_REORDER_EN_MASK = 0x00000040 # macro +GDC1_A2S_CNTL_SW1__SDP_WR_CHAIN_DIS_MASK = 0x00000200 # macro +GDC1_A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE_MASK = 0x00000400 # macro +GDC1_A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE_MASK = 0x00000800 # macro +GDC1_A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK = 0x00001000 # macro +GDC1_A2S_CNTL_SW1__WRR_RD_WEIGHT_MASK = 0x00FF0000 # macro +GDC1_A2S_CNTL_SW1__WRR_WR_WEIGHT_MASK = 0xFF000000 # macro +GDC1_A2S_CNTL_SW2__STATIC_VC_ENABLE__SHIFT = 0x0 # macro +GDC1_A2S_CNTL_SW2__STATIC_VC_VALUE__SHIFT = 0x1 # macro +GDC1_A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__SHIFT = 0x6 # macro +GDC1_A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__SHIFT = 0x9 # macro +GDC1_A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE__SHIFT = 0xa # macro +GDC1_A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT = 0xb # macro +GDC1_A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT = 0xc # macro +GDC1_A2S_CNTL_SW2__WRR_RD_WEIGHT__SHIFT = 0x10 # macro +GDC1_A2S_CNTL_SW2__WRR_WR_WEIGHT__SHIFT = 0x18 # macro +GDC1_A2S_CNTL_SW2__STATIC_VC_ENABLE_MASK = 0x00000001 # macro +GDC1_A2S_CNTL_SW2__STATIC_VC_VALUE_MASK = 0x0000000E # macro +GDC1_A2S_CNTL_SW2__FORCE_RSP_REORDER_EN_MASK = 0x00000040 # macro +GDC1_A2S_CNTL_SW2__SDP_WR_CHAIN_DIS_MASK = 0x00000200 # macro +GDC1_A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE_MASK = 0x00000400 # macro +GDC1_A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE_MASK = 0x00000800 # macro +GDC1_A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK = 0x00001000 # macro +GDC1_A2S_CNTL_SW2__WRR_RD_WEIGHT_MASK = 0x00FF0000 # macro +GDC1_A2S_CNTL_SW2__WRR_WR_WEIGHT_MASK = 0xFF000000 # macro +GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT = 0x0 # macro +GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT = 0x8 # macro +GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT = 0x10 # macro +GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK = 0x000000FF # macro +GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK = 0x0000FF00 # macro +GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK = 0x00FF0000 # macro +GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT = 0x0 # macro +GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT = 0x10 # macro +GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT = 0x18 # macro +GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK = 0x000000FF # macro +GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK = 0x00FF0000 # macro +GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK = 0xFF000000 # macro +GDC1_A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT = 0x0 # macro +GDC1_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT = 0x2 # macro +GDC1_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE__SHIFT = 0x3 # macro +GDC1_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN__SHIFT = 0x4 # macro +GDC1_A2S_MISC_CNTL__RSP_REORDER_DIS__SHIFT = 0x5 # macro +GDC1_A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT = 0x6 # macro +GDC1_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT = 0x7 # macro +GDC1_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT = 0x8 # macro +GDC1_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY__SHIFT = 0x9 # macro +GDC1_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT = 0xa # macro +GDC1_A2S_MISC_CNTL__WR_TAG_SET_MIN__SHIFT = 0x10 # macro +GDC1_A2S_MISC_CNTL__RD_TAG_SET_MIN__SHIFT = 0x15 # macro +GDC1_A2S_MISC_CNTL__WRR_LRG_MODE__SHIFT = 0x1a # macro +GDC1_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE__SHIFT = 0x1b # macro +GDC1_A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK = 0x00000003 # macro +GDC1_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS_MASK = 0x00000004 # macro +GDC1_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE_MASK = 0x00000008 # macro +GDC1_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN_MASK = 0x00000010 # macro +GDC1_A2S_MISC_CNTL__RSP_REORDER_DIS_MASK = 0x00000020 # macro +GDC1_A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK = 0x00000040 # macro +GDC1_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS_MASK = 0x00000080 # macro +GDC1_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS_MASK = 0x00000100 # macro +GDC1_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY_MASK = 0x00000200 # macro +GDC1_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK = 0x00000400 # macro +GDC1_A2S_MISC_CNTL__WR_TAG_SET_MIN_MASK = 0x001F0000 # macro +GDC1_A2S_MISC_CNTL__RD_TAG_SET_MIN_MASK = 0x03E00000 # macro +GDC1_A2S_MISC_CNTL__WRR_LRG_MODE_MASK = 0x04000000 # macro +GDC1_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE_MASK = 0x08000000 # macro +GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT = 0x0 # macro +GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS__SHIFT = 0x1 # macro +GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK = 0x00000001 # macro +GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS_MASK = 0x00000002 # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT = 0x0 # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT = 0x1 # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT = 0x2 # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT = 0xa # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT = 0xb # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT = 0xc # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT = 0xd # macro +GDC1_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN__SHIFT = 0xe # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK = 0x00000001 # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK = 0x00000002 # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK = 0x000003FC # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK = 0x00000400 # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK = 0x00000800 # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK = 0x00001000 # macro +GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK = 0x00002000 # macro +GDC1_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN_MASK = 0x00004000 # macro +GDC1_NGDC_RESERVED_0__RESERVED__SHIFT = 0x0 # macro +GDC1_NGDC_RESERVED_0__RESERVED_MASK = 0xFFFFFFFF # macro +GDC1_NGDC_RESERVED_1__RESERVED__SHIFT = 0x0 # macro +GDC1_NGDC_RESERVED_1__RESERVED_MASK = 0xFFFFFFFF # macro +GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT = 0x0 # macro +GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK = 0x0000FFFF # macro +GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT = 0x0 # macro +GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT = 0x1 # macro +GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT = 0x2 # macro +GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT = 0x8 # macro +GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT = 0x10 # macro +GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT = 0x18 # macro +GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK = 0x00000001 # macro +GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK = 0x00000002 # macro +GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK = 0x0000000C # macro +GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK = 0x0000FF00 # macro +GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK = 0x00FF0000 # macro +GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK = 0xFF000000 # macro +GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT = 0x3 # macro +GDC1_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT = 0x8 # macro +GDC1_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT = 0xa # macro +GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT = 0xc # macro +GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT = 0xf # macro +GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT = 0x10 # macro +GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK = 0x00000008 # macro +GDC1_S2A_MISC_CNTL__ATM_ARB_MODE_MASK = 0x00000300 # macro +GDC1_S2A_MISC_CNTL__RB_ARB_MODE_MASK = 0x00000C00 # macro +GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK = 0x00003000 # macro +GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK = 0x00008000 # macro +GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK = 0x000F0000 # macro +GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT = 0x0 # macro +GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT = 0x1 # macro +GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT = 0x2 # macro +GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK = 0x00000001 # macro +GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK = 0x00000002 # macro +GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK = 0x00000004 # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY__SHIFT = 0xa # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1__SHIFT = 0xd # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS__SHIFT = 0xe # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2__SHIFT = 0x10 # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT = 0x18 # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE__SHIFT = 0x1f # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY_MASK = 0x00000400 # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1_MASK = 0x00002000 # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS_MASK = 0x00004000 # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2_MASK = 0x00010000 # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS_MASK = 0x3F000000 # macro +GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE_MASK = 0x80000000 # macro +GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS__SHIFT = 0x0 # macro +GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN__SHIFT = 0x8 # macro +GDC1_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN__SHIFT = 0xa # macro +GDC1_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN__SHIFT = 0xe # macro +GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS_MASK = 0x000000FF # macro +GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN_MASK = 0x00000100 # macro +GDC1_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN_MASK = 0x00003C00 # macro +GDC1_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN_MASK = 0x0000C000 # macro +GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT = 0x0 # macro +GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT = 0x5 # macro +GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS__SHIFT = 0xa # macro +GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK = 0x0000001F # macro +GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK = 0x000003E0 # macro +GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS_MASK = 0x00007C00 # macro +XCC_DOORBELL_FENCE__XCC_0_DOORBELL_FENCE__SHIFT = 0x0 # macro +XCC_DOORBELL_FENCE__XCC_1_DOORBELL_FENCE__SHIFT = 0x1 # macro +XCC_DOORBELL_FENCE__XCC_2_DOORBELL_FENCE__SHIFT = 0x2 # macro +XCC_DOORBELL_FENCE__XCC_3_DOORBELL_FENCE__SHIFT = 0x3 # macro +XCC_DOORBELL_FENCE__XCC_4_DOORBELL_FENCE__SHIFT = 0x4 # macro +XCC_DOORBELL_FENCE__XCC_5_DOORBELL_FENCE__SHIFT = 0x5 # macro +XCC_DOORBELL_FENCE__XCC_6_DOORBELL_FENCE__SHIFT = 0x6 # macro +XCC_DOORBELL_FENCE__XCC_7_DOORBELL_FENCE__SHIFT = 0x7 # macro +XCC_DOORBELL_FENCE__SHUB_SLV_MODE__SHIFT = 0x10 # macro +XCC_DOORBELL_FENCE__RMOTE_CP_SENT__SHIFT = 0x11 # macro +XCC_DOORBELL_FENCE__CP_0_SENT__SHIFT = 0x12 # macro +XCC_DOORBELL_FENCE__CP_1_SENT__SHIFT = 0x13 # macro +XCC_DOORBELL_FENCE__CP_2_SENT__SHIFT = 0x14 # macro +XCC_DOORBELL_FENCE__CP_3_SENT__SHIFT = 0x15 # macro +XCC_DOORBELL_FENCE__CP_4_SENT__SHIFT = 0x16 # macro +XCC_DOORBELL_FENCE__CP_5_SENT__SHIFT = 0x17 # macro +XCC_DOORBELL_FENCE__CP_6_SENT__SHIFT = 0x18 # macro +XCC_DOORBELL_FENCE__CP_7_SENT__SHIFT = 0x19 # macro +XCC_DOORBELL_FENCE__REMOTE_CLIENT_SENT__SHIFT = 0x1a # macro +XCC_DOORBELL_FENCE__REMOTE_CLIENT_CLR_PENDING__SHIFT = 0x1b # macro +XCC_DOORBELL_FENCE__XCC_0_DOORBELL_FENCE_MASK = 0x00000001 # macro +XCC_DOORBELL_FENCE__XCC_1_DOORBELL_FENCE_MASK = 0x00000002 # macro +XCC_DOORBELL_FENCE__XCC_2_DOORBELL_FENCE_MASK = 0x00000004 # macro +XCC_DOORBELL_FENCE__XCC_3_DOORBELL_FENCE_MASK = 0x00000008 # macro +XCC_DOORBELL_FENCE__XCC_4_DOORBELL_FENCE_MASK = 0x00000010 # macro +XCC_DOORBELL_FENCE__XCC_5_DOORBELL_FENCE_MASK = 0x00000020 # macro +XCC_DOORBELL_FENCE__XCC_6_DOORBELL_FENCE_MASK = 0x00000040 # macro +XCC_DOORBELL_FENCE__XCC_7_DOORBELL_FENCE_MASK = 0x00000080 # macro +XCC_DOORBELL_FENCE__SHUB_SLV_MODE_MASK = 0x00010000 # macro +XCC_DOORBELL_FENCE__RMOTE_CP_SENT_MASK = 0x00020000 # macro +XCC_DOORBELL_FENCE__CP_0_SENT_MASK = 0x00040000 # macro +XCC_DOORBELL_FENCE__CP_1_SENT_MASK = 0x00080000 # macro +XCC_DOORBELL_FENCE__CP_2_SENT_MASK = 0x00100000 # macro +XCC_DOORBELL_FENCE__CP_3_SENT_MASK = 0x00200000 # macro +XCC_DOORBELL_FENCE__CP_4_SENT_MASK = 0x00400000 # macro +XCC_DOORBELL_FENCE__CP_5_SENT_MASK = 0x00800000 # macro +XCC_DOORBELL_FENCE__CP_6_SENT_MASK = 0x01000000 # macro +XCC_DOORBELL_FENCE__CP_7_SENT_MASK = 0x02000000 # macro +XCC_DOORBELL_FENCE__REMOTE_CLIENT_SENT_MASK = 0x04000000 # macro +XCC_DOORBELL_FENCE__REMOTE_CLIENT_CLR_PENDING_MASK = 0x08000000 # macro +SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT = 0x0 # macro +SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT = 0x1 # macro +SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK = 0x00000001 # macro +SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK = 0x00000002 # macro +SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST__SHIFT = 0x0 # macro +SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST_MASK = 0x00000001 # macro +SHUB_LINK_RESET__LINK_P0_RESET__SHIFT = 0x0 # macro +SHUB_LINK_RESET__LINK_P1_RESET__SHIFT = 0x1 # macro +SHUB_LINK_RESET__LINK_P2_RESET__SHIFT = 0x2 # macro +SHUB_LINK_RESET__LINK_P3_RESET__SHIFT = 0x3 # macro +SHUB_LINK_RESET__LINK_P0_RESET_MASK = 0x00000001 # macro +SHUB_LINK_RESET__LINK_P1_RESET_MASK = 0x00000002 # macro +SHUB_LINK_RESET__LINK_P2_RESET_MASK = 0x00000004 # macro +SHUB_LINK_RESET__LINK_P3_RESET_MASK = 0x00000008 # macro +SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT = 0x0 # macro +SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT = 0x1 # macro +SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT = 0x2 # macro +SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT = 0x3 # macro +SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT = 0x4 # macro +SHUB_HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT = 0x5 # macro +SHUB_HARD_RST_CTRL__COR_RESET_EN_MASK = 0x00000001 # macro +SHUB_HARD_RST_CTRL__REG_RESET_EN_MASK = 0x00000002 # macro +SHUB_HARD_RST_CTRL__STY_RESET_EN_MASK = 0x00000004 # macro +SHUB_HARD_RST_CTRL__NIC400_RESET_EN_MASK = 0x00000008 # macro +SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK = 0x00000010 # macro +SHUB_HARD_RST_CTRL__SION_AON_RESET_EN_MASK = 0x00000020 # macro +SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT = 0x0 # macro +SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT = 0x1 # macro +SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT = 0x2 # macro +SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT = 0x3 # macro +SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT = 0x4 # macro +SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN__SHIFT = 0x5 # macro +SHUB_SOFT_RST_CTRL__COR_RESET_EN_MASK = 0x00000001 # macro +SHUB_SOFT_RST_CTRL__REG_RESET_EN_MASK = 0x00000002 # macro +SHUB_SOFT_RST_CTRL__STY_RESET_EN_MASK = 0x00000004 # macro +SHUB_SOFT_RST_CTRL__NIC400_RESET_EN_MASK = 0x00000008 # macro +SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK = 0x00000010 # macro +SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN_MASK = 0x00000020 # macro +SHUB_SDP_PORT_RST__A2S_SDP_PORT_RST__SHIFT = 0x0 # macro +SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST__SHIFT = 0x1 # macro +SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST__SHIFT = 0x2 # macro +SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST__SHIFT = 0x3 # macro +SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST__SHIFT = 0x4 # macro +SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST__SHIFT = 0x6 # macro +SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST__SHIFT = 0x8 # macro +SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST__SHIFT = 0x9 # macro +SHUB_SDP_PORT_RST__MPDMATF_DMA_SDP_PORT_RST__SHIFT = 0xa # macro +SHUB_SDP_PORT_RST__MPDMAPM_DMA_SDP_PORT_RST__SHIFT = 0xb # macro +SHUB_SDP_PORT_RST__MPDMATF_HST_SDP_PORT_RST__SHIFT = 0xc # macro +SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST__SHIFT = 0xd # macro +SHUB_SDP_PORT_RST__SION_AON_RST__SHIFT = 0x18 # macro +SHUB_SDP_PORT_RST__A2S_SDP_PORT_RST_MASK = 0x00000001 # macro +SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST_MASK = 0x00000002 # macro +SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST_MASK = 0x00000004 # macro +SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST_MASK = 0x00000008 # macro +SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST_MASK = 0x00000010 # macro +SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST_MASK = 0x00000040 # macro +SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST_MASK = 0x00000100 # macro +SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST_MASK = 0x00000200 # macro +SHUB_SDP_PORT_RST__MPDMATF_DMA_SDP_PORT_RST_MASK = 0x00000400 # macro +SHUB_SDP_PORT_RST__MPDMAPM_DMA_SDP_PORT_RST_MASK = 0x00000800 # macro +SHUB_SDP_PORT_RST__MPDMATF_HST_SDP_PORT_RST_MASK = 0x00001000 # macro +SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST_MASK = 0x00002000 # macro +SHUB_SDP_PORT_RST__SION_AON_RST_MASK = 0x01000000 # macro +HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT = 0x0 # macro +HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT = 0x1 # macro +HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK = 0x00000001 # macro +HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK = 0x00000002 # macro +HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT = 0x0 # macro +HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT = 0x1 # macro +HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK = 0x00000001 # macro +HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK = 0x00000002 # macro +HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT = 0x0 # macro +HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT = 0x1 # macro +HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK = 0x00000001 # macro +HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK = 0x00000002 # macro +HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT = 0x0 # macro +HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT = 0x1 # macro +HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK = 0x00000001 # macro +HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK = 0x00000002 # macro +DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT = 0x0 # macro +DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT = 0x1 # macro +DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT = 0x8 # macro +DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT = 0x9 # macro +DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT = 0x10 # macro +DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT = 0x18 # macro +DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK = 0x00000001 # macro +DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK = 0x00000002 # macro +DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK = 0x00000100 # macro +DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK = 0x00001E00 # macro +DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK = 0x00FF0000 # macro +DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK = 0xFF000000 # macro +DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT = 0x0 # macro +DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT = 0x1 # macro +DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT = 0x8 # macro +DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT = 0x9 # macro +DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT = 0x10 # macro +DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT = 0x18 # macro +DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK = 0x00000001 # macro +DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK = 0x00000002 # macro +DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK = 0x00000100 # macro +DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK = 0x00001E00 # macro +DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK = 0x00FF0000 # macro +DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK = 0xFF000000 # macro +NIC400_1_ASIB_0_FN_MOD__read_iss_override__SHIFT = 0x0 # macro +NIC400_1_ASIB_0_FN_MOD__write_iss_override__SHIFT = 0x1 # macro +NIC400_1_ASIB_0_FN_MOD__read_iss_override_MASK = 0x00000001 # macro +NIC400_1_ASIB_0_FN_MOD__write_iss_override_MASK = 0x00000002 # macro +NIC400_1_IB_0_FN_MOD__read_iss_override__SHIFT = 0x0 # macro +NIC400_1_IB_0_FN_MOD__write_iss_override__SHIFT = 0x1 # macro +NIC400_1_IB_0_FN_MOD__read_iss_override_MASK = 0x00000001 # macro +NIC400_1_IB_0_FN_MOD__write_iss_override_MASK = 0x00000002 # macro +NIC400_2_ASIB_0_FN_MOD__read_iss_override__SHIFT = 0x0 # macro +NIC400_2_ASIB_0_FN_MOD__write_iss_override__SHIFT = 0x1 # macro +NIC400_2_ASIB_0_FN_MOD__read_iss_override_MASK = 0x00000001 # macro +NIC400_2_ASIB_0_FN_MOD__write_iss_override_MASK = 0x00000002 # macro +NIC400_2_ASIB_0_QOS_CNTL__en_aw_rate__SHIFT = 0x0 # macro +NIC400_2_ASIB_0_QOS_CNTL__en_ar_rate__SHIFT = 0x1 # macro +NIC400_2_ASIB_0_QOS_CNTL__en_awar_rate__SHIFT = 0x2 # macro +NIC400_2_ASIB_0_QOS_CNTL__en_aw_fc__SHIFT = 0x3 # macro +NIC400_2_ASIB_0_QOS_CNTL__en_ar_fc__SHIFT = 0x4 # macro +NIC400_2_ASIB_0_QOS_CNTL__en_aw_ot__SHIFT = 0x5 # macro +NIC400_2_ASIB_0_QOS_CNTL__en_ar_ot__SHIFT = 0x6 # macro +NIC400_2_ASIB_0_QOS_CNTL__en_awar_ot__SHIFT = 0x7 # macro +NIC400_2_ASIB_0_QOS_CNTL__mode_aw_fc__SHIFT = 0x10 # macro +NIC400_2_ASIB_0_QOS_CNTL__mode_ar_fc__SHIFT = 0x14 # macro +NIC400_2_ASIB_0_QOS_CNTL__en_aw_rate_MASK = 0x00000001 # macro +NIC400_2_ASIB_0_QOS_CNTL__en_ar_rate_MASK = 0x00000002 # macro +NIC400_2_ASIB_0_QOS_CNTL__en_awar_rate_MASK = 0x00000004 # macro +NIC400_2_ASIB_0_QOS_CNTL__en_aw_fc_MASK = 0x00000008 # macro +NIC400_2_ASIB_0_QOS_CNTL__en_ar_fc_MASK = 0x00000010 # macro +NIC400_2_ASIB_0_QOS_CNTL__en_aw_ot_MASK = 0x00000020 # macro +NIC400_2_ASIB_0_QOS_CNTL__en_ar_ot_MASK = 0x00000040 # macro +NIC400_2_ASIB_0_QOS_CNTL__en_awar_ot_MASK = 0x00000080 # macro +NIC400_2_ASIB_0_QOS_CNTL__mode_aw_fc_MASK = 0x00010000 # macro +NIC400_2_ASIB_0_QOS_CNTL__mode_ar_fc_MASK = 0x00100000 # macro +NIC400_2_ASIB_0_MAX_OT__aw_max_otf__SHIFT = 0x0 # macro +NIC400_2_ASIB_0_MAX_OT__aw_max_oti__SHIFT = 0x8 # macro +NIC400_2_ASIB_0_MAX_OT__ar_max_otf__SHIFT = 0x10 # macro +NIC400_2_ASIB_0_MAX_OT__ar_max_oti__SHIFT = 0x18 # macro +NIC400_2_ASIB_0_MAX_OT__aw_max_otf_MASK = 0x000000FF # macro +NIC400_2_ASIB_0_MAX_OT__aw_max_oti_MASK = 0x00003F00 # macro +NIC400_2_ASIB_0_MAX_OT__ar_max_otf_MASK = 0x00FF0000 # macro +NIC400_2_ASIB_0_MAX_OT__ar_max_oti_MASK = 0x3F000000 # macro +NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_otf__SHIFT = 0x0 # macro +NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_oti__SHIFT = 0x8 # macro +NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_otf_MASK = 0x000000FF # macro +NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_oti_MASK = 0x00007F00 # macro +NIC400_2_ASIB_0_AW_P__aw_p__SHIFT = 0x18 # macro +NIC400_2_ASIB_0_AW_P__aw_p_MASK = 0xFF000000 # macro +NIC400_2_ASIB_0_AW_B__aw_b__SHIFT = 0x0 # macro +NIC400_2_ASIB_0_AW_B__aw_b_MASK = 0x0000FFFF # macro +NIC400_2_ASIB_0_AW_R__aw_r__SHIFT = 0x14 # macro +NIC400_2_ASIB_0_AW_R__aw_r_MASK = 0xFFF00000 # macro +NIC400_2_ASIB_0_AR_P__ar_p__SHIFT = 0x18 # macro +NIC400_2_ASIB_0_AR_P__ar_p_MASK = 0xFF000000 # macro +NIC400_2_ASIB_0_AR_B__ar_b__SHIFT = 0x0 # macro +NIC400_2_ASIB_0_AR_B__ar_b_MASK = 0x0000FFFF # macro +NIC400_2_ASIB_0_AR_R__ar_r__SHIFT = 0x14 # macro +NIC400_2_ASIB_0_AR_R__ar_r_MASK = 0xFFF00000 # macro +NIC400_2_ASIB_0_TARGET_FC__aw_tgt_latency__SHIFT = 0x0 # macro +NIC400_2_ASIB_0_TARGET_FC__ar_tgt_latency__SHIFT = 0x10 # macro +NIC400_2_ASIB_0_TARGET_FC__aw_tgt_latency_MASK = 0x00000FFF # macro +NIC400_2_ASIB_0_TARGET_FC__ar_tgt_latency_MASK = 0x0FFF0000 # macro +NIC400_2_ASIB_0_KI_FC__aw_tgt_latency__SHIFT = 0x0 # macro +NIC400_2_ASIB_0_KI_FC__ar_tgt_latency__SHIFT = 0x8 # macro +NIC400_2_ASIB_0_KI_FC__aw_tgt_latency_MASK = 0x00000007 # macro +NIC400_2_ASIB_0_KI_FC__ar_tgt_latency_MASK = 0x00000700 # macro +NIC400_2_ASIB_0_QOS_RANGE__aw_min_qos__SHIFT = 0x0 # macro +NIC400_2_ASIB_0_QOS_RANGE__aw_max_qos__SHIFT = 0x8 # macro +NIC400_2_ASIB_0_QOS_RANGE__ar_min_qos__SHIFT = 0x10 # macro +NIC400_2_ASIB_0_QOS_RANGE__ar_max_qos__SHIFT = 0x18 # macro +NIC400_2_ASIB_0_QOS_RANGE__aw_min_qos_MASK = 0x0000000F # macro +NIC400_2_ASIB_0_QOS_RANGE__aw_max_qos_MASK = 0x00000F00 # macro +NIC400_2_ASIB_0_QOS_RANGE__ar_min_qos_MASK = 0x000F0000 # macro +NIC400_2_ASIB_0_QOS_RANGE__ar_max_qos_MASK = 0x0F000000 # macro +NIC400_2_ASIB_1_FN_MOD__read_iss_override__SHIFT = 0x0 # macro +NIC400_2_ASIB_1_FN_MOD__write_iss_override__SHIFT = 0x1 # macro +NIC400_2_ASIB_1_FN_MOD__read_iss_override_MASK = 0x00000001 # macro +NIC400_2_ASIB_1_FN_MOD__write_iss_override_MASK = 0x00000002 # macro +NIC400_2_ASIB_1_QOS_CNTL__en_aw_rate__SHIFT = 0x0 # macro +NIC400_2_ASIB_1_QOS_CNTL__en_ar_rate__SHIFT = 0x1 # macro +NIC400_2_ASIB_1_QOS_CNTL__en_awar_rate__SHIFT = 0x2 # macro +NIC400_2_ASIB_1_QOS_CNTL__en_aw_fc__SHIFT = 0x3 # macro +NIC400_2_ASIB_1_QOS_CNTL__en_ar_fc__SHIFT = 0x4 # macro +NIC400_2_ASIB_1_QOS_CNTL__en_aw_ot__SHIFT = 0x5 # macro +NIC400_2_ASIB_1_QOS_CNTL__en_ar_ot__SHIFT = 0x6 # macro +NIC400_2_ASIB_1_QOS_CNTL__en_awar_ot__SHIFT = 0x7 # macro +NIC400_2_ASIB_1_QOS_CNTL__mode_aw_fc__SHIFT = 0x10 # macro +NIC400_2_ASIB_1_QOS_CNTL__mode_ar_fc__SHIFT = 0x14 # macro +NIC400_2_ASIB_1_QOS_CNTL__en_aw_rate_MASK = 0x00000001 # macro +NIC400_2_ASIB_1_QOS_CNTL__en_ar_rate_MASK = 0x00000002 # macro +NIC400_2_ASIB_1_QOS_CNTL__en_awar_rate_MASK = 0x00000004 # macro +NIC400_2_ASIB_1_QOS_CNTL__en_aw_fc_MASK = 0x00000008 # macro +NIC400_2_ASIB_1_QOS_CNTL__en_ar_fc_MASK = 0x00000010 # macro +NIC400_2_ASIB_1_QOS_CNTL__en_aw_ot_MASK = 0x00000020 # macro +NIC400_2_ASIB_1_QOS_CNTL__en_ar_ot_MASK = 0x00000040 # macro +NIC400_2_ASIB_1_QOS_CNTL__en_awar_ot_MASK = 0x00000080 # macro +NIC400_2_ASIB_1_QOS_CNTL__mode_aw_fc_MASK = 0x00010000 # macro +NIC400_2_ASIB_1_QOS_CNTL__mode_ar_fc_MASK = 0x00100000 # macro +NIC400_2_ASIB_1_MAX_OT__aw_max_otf__SHIFT = 0x0 # macro +NIC400_2_ASIB_1_MAX_OT__aw_max_oti__SHIFT = 0x8 # macro +NIC400_2_ASIB_1_MAX_OT__ar_max_otf__SHIFT = 0x10 # macro +NIC400_2_ASIB_1_MAX_OT__ar_max_oti__SHIFT = 0x18 # macro +NIC400_2_ASIB_1_MAX_OT__aw_max_otf_MASK = 0x000000FF # macro +NIC400_2_ASIB_1_MAX_OT__aw_max_oti_MASK = 0x00003F00 # macro +NIC400_2_ASIB_1_MAX_OT__ar_max_otf_MASK = 0x00FF0000 # macro +NIC400_2_ASIB_1_MAX_OT__ar_max_oti_MASK = 0x3F000000 # macro +NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_otf__SHIFT = 0x0 # macro +NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_oti__SHIFT = 0x8 # macro +NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_otf_MASK = 0x000000FF # macro +NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_oti_MASK = 0x00007F00 # macro +NIC400_2_ASIB_1_AW_P__aw_p__SHIFT = 0x18 # macro +NIC400_2_ASIB_1_AW_P__aw_p_MASK = 0xFF000000 # macro +NIC400_2_ASIB_1_AW_B__aw_b__SHIFT = 0x0 # macro +NIC400_2_ASIB_1_AW_B__aw_b_MASK = 0x0000FFFF # macro +NIC400_2_ASIB_1_AW_R__aw_r__SHIFT = 0x14 # macro +NIC400_2_ASIB_1_AW_R__aw_r_MASK = 0xFFF00000 # macro +NIC400_2_ASIB_1_AR_P__ar_p__SHIFT = 0x18 # macro +NIC400_2_ASIB_1_AR_P__ar_p_MASK = 0xFF000000 # macro +NIC400_2_ASIB_1_AR_B__ar_b__SHIFT = 0x0 # macro +NIC400_2_ASIB_1_AR_B__ar_b_MASK = 0x0000FFFF # macro +NIC400_2_ASIB_1_AR_R__ar_r__SHIFT = 0x14 # macro +NIC400_2_ASIB_1_AR_R__ar_r_MASK = 0xFFF00000 # macro +NIC400_2_ASIB_1_TARGET_FC__aw_tgt_latency__SHIFT = 0x0 # macro +NIC400_2_ASIB_1_TARGET_FC__ar_tgt_latency__SHIFT = 0x10 # macro +NIC400_2_ASIB_1_TARGET_FC__aw_tgt_latency_MASK = 0x00000FFF # macro +NIC400_2_ASIB_1_TARGET_FC__ar_tgt_latency_MASK = 0x0FFF0000 # macro +NIC400_2_ASIB_1_KI_FC__aw_tgt_latency__SHIFT = 0x0 # macro +NIC400_2_ASIB_1_KI_FC__ar_tgt_latency__SHIFT = 0x8 # macro +NIC400_2_ASIB_1_KI_FC__aw_tgt_latency_MASK = 0x00000007 # macro +NIC400_2_ASIB_1_KI_FC__ar_tgt_latency_MASK = 0x00000700 # macro +NIC400_2_ASIB_1_QOS_RANGE__aw_min_qos__SHIFT = 0x0 # macro +NIC400_2_ASIB_1_QOS_RANGE__aw_max_qos__SHIFT = 0x8 # macro +NIC400_2_ASIB_1_QOS_RANGE__ar_min_qos__SHIFT = 0x10 # macro +NIC400_2_ASIB_1_QOS_RANGE__ar_max_qos__SHIFT = 0x18 # macro +NIC400_2_ASIB_1_QOS_RANGE__aw_min_qos_MASK = 0x0000000F # macro +NIC400_2_ASIB_1_QOS_RANGE__aw_max_qos_MASK = 0x00000F00 # macro +NIC400_2_ASIB_1_QOS_RANGE__ar_min_qos_MASK = 0x000F0000 # macro +NIC400_2_ASIB_1_QOS_RANGE__ar_max_qos_MASK = 0x0F000000 # macro +NIC400_2_IB_0_FN_MOD__read_iss_override__SHIFT = 0x0 # macro +NIC400_2_IB_0_FN_MOD__write_iss_override__SHIFT = 0x1 # macro +NIC400_2_IB_0_FN_MOD__read_iss_override_MASK = 0x00000001 # macro +NIC400_2_IB_0_FN_MOD__write_iss_override_MASK = 0x00000002 # macro +NB_NBCFG0_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4__SHIFT = 0x0 # macro +NB_NBCFG0_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4_MASK = 0xFFFFFFFF # macro +NB_CNTL__HWINIT_WR_LOCK__SHIFT = 0x7 # macro +NB_CNTL__HWINIT_WR_LOCK_MASK = 0x00000080 # macro +NB_SPARE1__NB_SPARE1_RW__SHIFT = 0x0 # macro +NB_SPARE1__NB_SPARE1_RW_MASK = 0xFFFFFFFF # macro +NB_SPARE2__NB_SPARE2_RW1C_0__SHIFT = 0x0 # macro +NB_SPARE2__NB_SPARE2_RW1C_1__SHIFT = 0x1 # macro +NB_SPARE2__NB_SPARE2_RW1C_2__SHIFT = 0x2 # macro +NB_SPARE2__NB_SPARE2_RW1C_3__SHIFT = 0x3 # macro +NB_SPARE2__NB_SPARE2_RW1C_4__SHIFT = 0x4 # macro +NB_SPARE2__NB_SPARE2_RW1C_5__SHIFT = 0x5 # macro +NB_SPARE2__NB_SPARE2_RW1C_6__SHIFT = 0x6 # macro +NB_SPARE2__NB_SPARE2_RW1C_7__SHIFT = 0x7 # macro +NB_SPARE2__NB_SPARE2_RW1C_8__SHIFT = 0x8 # macro +NB_SPARE2__NB_SPARE2_RW1C_9__SHIFT = 0x9 # macro +NB_SPARE2__NB_SPARE2_RW1C_10__SHIFT = 0xa # macro +NB_SPARE2__NB_SPARE2_RW1C_11__SHIFT = 0xb # macro +NB_SPARE2__NB_SPARE2_RW1C_12__SHIFT = 0xc # macro +NB_SPARE2__NB_SPARE2_RW1C_13__SHIFT = 0xd # macro +NB_SPARE2__NB_SPARE2_RW1C_14__SHIFT = 0xe # macro +NB_SPARE2__NB_SPARE2_RW1C_15__SHIFT = 0xf # macro +NB_SPARE2__NB_SPARE2_RW1C_16__SHIFT = 0x10 # macro +NB_SPARE2__NB_SPARE2_RW1C_17__SHIFT = 0x11 # macro +NB_SPARE2__NB_SPARE2_RW1C_18__SHIFT = 0x12 # macro +NB_SPARE2__NB_SPARE2_RW1C_19__SHIFT = 0x13 # macro +NB_SPARE2__NB_SPARE2_RW1C_20__SHIFT = 0x14 # macro +NB_SPARE2__NB_SPARE2_RW1C_21__SHIFT = 0x15 # macro +NB_SPARE2__NB_SPARE2_RW1C_22__SHIFT = 0x16 # macro +NB_SPARE2__NB_SPARE2_RW1C_23__SHIFT = 0x17 # macro +NB_SPARE2__NB_SPARE2_RW1C_24__SHIFT = 0x18 # macro +NB_SPARE2__NB_SPARE2_RW1C_25__SHIFT = 0x19 # macro +NB_SPARE2__NB_SPARE2_RW1C_26__SHIFT = 0x1a # macro +NB_SPARE2__NB_SPARE2_RW1C_27__SHIFT = 0x1b # macro +NB_SPARE2__NB_SPARE2_RW1C_28__SHIFT = 0x1c # macro +NB_SPARE2__NB_SPARE2_RW1C_29__SHIFT = 0x1d # macro +NB_SPARE2__NB_SPARE2_RW1C_30__SHIFT = 0x1e # macro +NB_SPARE2__NB_SPARE2_RW1C_31__SHIFT = 0x1f # macro +NB_SPARE2__NB_SPARE2_RW1C_0_MASK = 0x00000001 # macro +NB_SPARE2__NB_SPARE2_RW1C_1_MASK = 0x00000002 # macro +NB_SPARE2__NB_SPARE2_RW1C_2_MASK = 0x00000004 # macro +NB_SPARE2__NB_SPARE2_RW1C_3_MASK = 0x00000008 # macro +NB_SPARE2__NB_SPARE2_RW1C_4_MASK = 0x00000010 # macro +NB_SPARE2__NB_SPARE2_RW1C_5_MASK = 0x00000020 # macro +NB_SPARE2__NB_SPARE2_RW1C_6_MASK = 0x00000040 # macro +NB_SPARE2__NB_SPARE2_RW1C_7_MASK = 0x00000080 # macro +NB_SPARE2__NB_SPARE2_RW1C_8_MASK = 0x00000100 # macro +NB_SPARE2__NB_SPARE2_RW1C_9_MASK = 0x00000200 # macro +NB_SPARE2__NB_SPARE2_RW1C_10_MASK = 0x00000400 # macro +NB_SPARE2__NB_SPARE2_RW1C_11_MASK = 0x00000800 # macro +NB_SPARE2__NB_SPARE2_RW1C_12_MASK = 0x00001000 # macro +NB_SPARE2__NB_SPARE2_RW1C_13_MASK = 0x00002000 # macro +NB_SPARE2__NB_SPARE2_RW1C_14_MASK = 0x00004000 # macro +NB_SPARE2__NB_SPARE2_RW1C_15_MASK = 0x00008000 # macro +NB_SPARE2__NB_SPARE2_RW1C_16_MASK = 0x00010000 # macro +NB_SPARE2__NB_SPARE2_RW1C_17_MASK = 0x00020000 # macro +NB_SPARE2__NB_SPARE2_RW1C_18_MASK = 0x00040000 # macro +NB_SPARE2__NB_SPARE2_RW1C_19_MASK = 0x00080000 # macro +NB_SPARE2__NB_SPARE2_RW1C_20_MASK = 0x00100000 # macro +NB_SPARE2__NB_SPARE2_RW1C_21_MASK = 0x00200000 # macro +NB_SPARE2__NB_SPARE2_RW1C_22_MASK = 0x00400000 # macro +NB_SPARE2__NB_SPARE2_RW1C_23_MASK = 0x00800000 # macro +NB_SPARE2__NB_SPARE2_RW1C_24_MASK = 0x01000000 # macro +NB_SPARE2__NB_SPARE2_RW1C_25_MASK = 0x02000000 # macro +NB_SPARE2__NB_SPARE2_RW1C_26_MASK = 0x04000000 # macro +NB_SPARE2__NB_SPARE2_RW1C_27_MASK = 0x08000000 # macro +NB_SPARE2__NB_SPARE2_RW1C_28_MASK = 0x10000000 # macro +NB_SPARE2__NB_SPARE2_RW1C_29_MASK = 0x20000000 # macro +NB_SPARE2__NB_SPARE2_RW1C_30_MASK = 0x40000000 # macro +NB_SPARE2__NB_SPARE2_RW1C_31_MASK = 0x80000000 # macro +NB_REVID__REVISION_ID__SHIFT = 0x0 # macro +NB_REVID__REVISION_ID_MASK = 0x000003FF # macro +NBIO_LCLK_DS_MASK__LCLK_DS_MASK__SHIFT = 0x0 # macro +NBIO_LCLK_DS_MASK__LCLK_DS_MASK_MASK = 0xFFFFFFFF # macro +NB_BUS_NUM_CNTL__NB_BUS_NUM__SHIFT = 0x0 # macro +NB_BUS_NUM_CNTL__NB_BUS_LAT_Mode__SHIFT = 0x8 # macro +NB_BUS_NUM_CNTL__NB_SEGMENT__SHIFT = 0x10 # macro +NB_BUS_NUM_CNTL__NB_BUS_NUM_MASK = 0x000000FF # macro +NB_BUS_NUM_CNTL__NB_BUS_LAT_Mode_MASK = 0x00000100 # macro +NB_BUS_NUM_CNTL__NB_SEGMENT_MASK = 0x00FF0000 # macro +NB_MMIOBASE__MMIOBASE__SHIFT = 0x0 # macro +NB_MMIOBASE__MMIOBASE_MASK = 0xFFFFFFFF # macro +NB_MMIOLIMIT__MMIOLIMIT__SHIFT = 0x0 # macro +NB_MMIOLIMIT__MMIOLIMIT_MASK = 0xFFFFFFFF # macro +NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT = 0x0 # macro +NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT = 0x17 # macro +NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK = 0x00000001 # macro +NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK = 0xFF800000 # macro +NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT = 0x0 # macro +NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK = 0x000001FF # macro +NB_LOWER_DRAM2_BASE__LOWER_DRAM2_BASE__SHIFT = 0x17 # macro +NB_LOWER_DRAM2_BASE__LOWER_DRAM2_BASE_MASK = 0xFF800000 # macro +NB_UPPER_DRAM2_BASE__UPPER_DRAM2_BASE__SHIFT = 0x0 # macro +NB_UPPER_DRAM2_BASE__UPPER_DRAM2_BASE_MASK = 0x000001FF # macro +SB_LOCATION__SBlocated_Port__SHIFT = 0x0 # macro +SB_LOCATION__SBlocated_Core__SHIFT = 0x10 # macro +SB_LOCATION__SBlocated_Port_MASK = 0x0000FFFF # macro +SB_LOCATION__SBlocated_Core_MASK = 0xFFFF0000 # macro +SW_US_LOCATION__SW_USlocated_Port__SHIFT = 0x0 # macro +SW_US_LOCATION__SW_USlocated_Core__SHIFT = 0x10 # macro +SW_US_LOCATION__SW_USlocated_Port_MASK = 0x0000FFFF # macro +SW_US_LOCATION__SW_USlocated_Core_MASK = 0xFFFF0000 # macro +NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap__SHIFT = 0x0 # macro +NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap_MASK = 0x000000FF # macro +NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap__SHIFT = 0x0 # macro +NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap_MASK = 0x000000FF # macro +NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap__SHIFT = 0x0 # macro +NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap_MASK = 0x000000FF # macro +NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap__SHIFT = 0x0 # macro +NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap_MASK = 0x000000FF # macro +NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap__SHIFT = 0x0 # macro +NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap_MASK = 0x000000FF # macro +NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap__SHIFT = 0x0 # macro +NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap_MASK = 0x000000FF # macro +NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap__SHIFT = 0x0 # macro +NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap_MASK = 0x000000FF # macro +NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap__SHIFT = 0x0 # macro +NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap_MASK = 0x000000FF # macro +NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap__SHIFT = 0x0 # macro +NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap_MASK = 0x000000FF # macro +NB_PROG_DEVICE_REMAP_PBr10__PBr10_DevFnMap__SHIFT = 0x0 # macro +NB_PROG_DEVICE_REMAP_PBr10__PBr10_DevFnMap_MASK = 0x000000FF # macro +NB_PROG_DEVICE_REMAP_PBr11__PBr11_DevFnMap__SHIFT = 0x0 # macro +NB_PROG_DEVICE_REMAP_PBr11__PBr11_DevFnMap_MASK = 0x000000FF # macro +NB_PROG_DEVICE_REMAP_PBr12__PBr12_DevFnMap__SHIFT = 0x0 # macro +NB_PROG_DEVICE_REMAP_PBr12__PBr12_DevFnMap_MASK = 0x000000FF # macro +NB_PROG_DEVICE_REMAP_PBr13__PBr13_DevFnMap__SHIFT = 0x0 # macro +NB_PROG_DEVICE_REMAP_PBr13__PBr13_DevFnMap_MASK = 0x000000FF # macro +SW_NMI_CNTL__SW_NMI_Status__SHIFT = 0x0 # macro +SW_NMI_CNTL__SW_NMI_Status_MASK = 0xFFFFFFFF # macro +SW_SMI_CNTL__SW_SMI_Status__SHIFT = 0x0 # macro +SW_SMI_CNTL__SW_SMI_Status_MASK = 0xFFFFFFFF # macro +SW_SCI_CNTL__SW_SCI_Status__SHIFT = 0x0 # macro +SW_SCI_CNTL__SW_SCI_Status_MASK = 0xFFFFFFFF # macro +APML_SW_STATUS__APML_NMI_STATUS__SHIFT = 0x0 # macro +APML_SW_STATUS__APML_NMI_STATUS_MASK = 0x00000001 # macro +SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector__SHIFT = 0x0 # macro +SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector__SHIFT = 0x8 # macro +SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector__SHIFT = 0x10 # macro +SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector_MASK = 0x000000FF # macro +SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector_MASK = 0x0000FF00 # macro +SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector_MASK = 0x00FF0000 # macro +SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE__SHIFT = 0x0 # macro +SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML__SHIFT = 0x1 # macro +SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE_MASK = 0x00000001 # macro +SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML_MASK = 0x00000002 # macro +NB_TOP_OF_DRAM3__TOM3_LIMIT__SHIFT = 0x0 # macro +NB_TOP_OF_DRAM3__TOM3_ENABLE__SHIFT = 0x1f # macro +NB_TOP_OF_DRAM3__TOM3_LIMIT_MASK = 0x3FFFFFFF # macro +NB_TOP_OF_DRAM3__TOM3_ENABLE_MASK = 0x80000000 # macro +CAM_CONTROL__CAM_En__SHIFT = 0x0 # macro +CAM_CONTROL__Op__SHIFT = 0x1 # macro +CAM_CONTROL__AccessType__SHIFT = 0x2 # macro +CAM_CONTROL__DataMatchEn__SHIFT = 0x3 # macro +CAM_CONTROL__VC__SHIFT = 0x4 # macro +CAM_CONTROL__CrossTrigger__SHIFT = 0x8 # macro +CAM_CONTROL__CAM_En_MASK = 0x00000001 # macro +CAM_CONTROL__Op_MASK = 0x00000002 # macro +CAM_CONTROL__AccessType_MASK = 0x00000004 # macro +CAM_CONTROL__DataMatchEn_MASK = 0x00000008 # macro +CAM_CONTROL__VC_MASK = 0x00000070 # macro +CAM_CONTROL__CrossTrigger_MASK = 0x00000F00 # macro +CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom__SHIFT = 0x0 # macro +CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom_MASK = 0xFFFFFFFF # macro +CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop__SHIFT = 0x0 # macro +CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop_MASK = 0xFFFFFFFF # macro +CAM_TARGET_INDEX_DATA__IndexData__SHIFT = 0x0 # macro +CAM_TARGET_INDEX_DATA__IndexData_MASK = 0xFFFFFFFF # macro +CAM_TARGET_INDEX_DATA_MASK__IndexDataMask__SHIFT = 0x0 # macro +CAM_TARGET_INDEX_DATA_MASK__IndexDataMask_MASK = 0xFFFFFFFF # macro +CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom__SHIFT = 0x0 # macro +CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom_MASK = 0xFFFFFFFF # macro +CAM_TARGET_DATA_ADDR_TOP__DataAddrTop__SHIFT = 0x0 # macro +CAM_TARGET_DATA_ADDR_TOP__DataAddrTop_MASK = 0xFFFFFFFF # macro +CAM_TARGET_DATA__Data__SHIFT = 0x0 # macro +CAM_TARGET_DATA__Data_MASK = 0xFFFFFFFF # macro +CAM_TARGET_DATA_MASK__DataMask__SHIFT = 0x0 # macro +CAM_TARGET_DATA_MASK__DataMask_MASK = 0xFFFFFFFF # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_0__SHIFT = 0x0 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_1__SHIFT = 0x1 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_2__SHIFT = 0x2 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_3__SHIFT = 0x3 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_4__SHIFT = 0x4 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_5__SHIFT = 0x5 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_6__SHIFT = 0x6 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_7__SHIFT = 0x7 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_8__SHIFT = 0x8 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_9__SHIFT = 0x9 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_10__SHIFT = 0xa # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_11__SHIFT = 0xb # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_12__SHIFT = 0xc # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_13__SHIFT = 0xd # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_14__SHIFT = 0xe # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_15__SHIFT = 0xf # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_16__SHIFT = 0x10 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_17__SHIFT = 0x11 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_18__SHIFT = 0x12 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_19__SHIFT = 0x13 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_20__SHIFT = 0x14 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_21__SHIFT = 0x15 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_22__SHIFT = 0x16 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_23__SHIFT = 0x17 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_24__SHIFT = 0x18 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_25__SHIFT = 0x19 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_26__SHIFT = 0x1a # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_27__SHIFT = 0x1b # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_28__SHIFT = 0x1c # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_29__SHIFT = 0x1d # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_30__SHIFT = 0x1e # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_31__SHIFT = 0x1f # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_0_MASK = 0x00000001 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_1_MASK = 0x00000002 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_2_MASK = 0x00000004 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_3_MASK = 0x00000008 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_4_MASK = 0x00000010 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_5_MASK = 0x00000020 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_6_MASK = 0x00000040 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_7_MASK = 0x00000080 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_8_MASK = 0x00000100 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_9_MASK = 0x00000200 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_10_MASK = 0x00000400 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_11_MASK = 0x00000800 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_12_MASK = 0x00001000 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_13_MASK = 0x00002000 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_14_MASK = 0x00004000 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_15_MASK = 0x00008000 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_16_MASK = 0x00010000 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_17_MASK = 0x00020000 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_18_MASK = 0x00040000 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_19_MASK = 0x00080000 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_20_MASK = 0x00100000 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_21_MASK = 0x00200000 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_22_MASK = 0x00400000 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_23_MASK = 0x00800000 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_24_MASK = 0x01000000 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_25_MASK = 0x02000000 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_26_MASK = 0x04000000 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_27_MASK = 0x08000000 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_28_MASK = 0x10000000 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_29_MASK = 0x20000000 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_30_MASK = 0x40000000 # macro +P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_31_MASK = 0x80000000 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_0__SHIFT = 0x0 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_1__SHIFT = 0x1 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_2__SHIFT = 0x2 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_3__SHIFT = 0x3 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_4__SHIFT = 0x4 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_5__SHIFT = 0x5 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_6__SHIFT = 0x6 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_7__SHIFT = 0x7 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_8__SHIFT = 0x8 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_9__SHIFT = 0x9 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_10__SHIFT = 0xa # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_11__SHIFT = 0xb # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_12__SHIFT = 0xc # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_13__SHIFT = 0xd # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_14__SHIFT = 0xe # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_15__SHIFT = 0xf # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_16__SHIFT = 0x10 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_17__SHIFT = 0x11 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_18__SHIFT = 0x12 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_19__SHIFT = 0x13 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_20__SHIFT = 0x14 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_21__SHIFT = 0x15 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_22__SHIFT = 0x16 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_23__SHIFT = 0x17 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_24__SHIFT = 0x18 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_25__SHIFT = 0x19 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_26__SHIFT = 0x1a # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_27__SHIFT = 0x1b # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_28__SHIFT = 0x1c # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_29__SHIFT = 0x1d # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_30__SHIFT = 0x1e # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_31__SHIFT = 0x1f # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_0_MASK = 0x00000001 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_1_MASK = 0x00000002 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_2_MASK = 0x00000004 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_3_MASK = 0x00000008 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_4_MASK = 0x00000010 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_5_MASK = 0x00000020 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_6_MASK = 0x00000040 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_7_MASK = 0x00000080 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_8_MASK = 0x00000100 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_9_MASK = 0x00000200 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_10_MASK = 0x00000400 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_11_MASK = 0x00000800 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_12_MASK = 0x00001000 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_13_MASK = 0x00002000 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_14_MASK = 0x00004000 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_15_MASK = 0x00008000 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_16_MASK = 0x00010000 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_17_MASK = 0x00020000 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_18_MASK = 0x00040000 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_19_MASK = 0x00080000 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_20_MASK = 0x00100000 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_21_MASK = 0x00200000 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_22_MASK = 0x00400000 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_23_MASK = 0x00800000 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_24_MASK = 0x01000000 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_25_MASK = 0x02000000 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_26_MASK = 0x04000000 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_27_MASK = 0x08000000 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_28_MASK = 0x10000000 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_29_MASK = 0x20000000 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_30_MASK = 0x40000000 # macro +P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_31_MASK = 0x80000000 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_0__SHIFT = 0x0 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_1__SHIFT = 0x1 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_2__SHIFT = 0x2 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_3__SHIFT = 0x3 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_4__SHIFT = 0x4 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_5__SHIFT = 0x5 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_6__SHIFT = 0x6 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_7__SHIFT = 0x7 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_8__SHIFT = 0x8 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_9__SHIFT = 0x9 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_10__SHIFT = 0xa # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_11__SHIFT = 0xb # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_12__SHIFT = 0xc # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_13__SHIFT = 0xd # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_14__SHIFT = 0xe # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_15__SHIFT = 0xf # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_16__SHIFT = 0x10 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_17__SHIFT = 0x11 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_18__SHIFT = 0x12 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_19__SHIFT = 0x13 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_20__SHIFT = 0x14 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_21__SHIFT = 0x15 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_22__SHIFT = 0x16 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_23__SHIFT = 0x17 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_24__SHIFT = 0x18 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_25__SHIFT = 0x19 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_26__SHIFT = 0x1a # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_27__SHIFT = 0x1b # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_28__SHIFT = 0x1c # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_29__SHIFT = 0x1d # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_30__SHIFT = 0x1e # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_31__SHIFT = 0x1f # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_0_MASK = 0x00000001 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_1_MASK = 0x00000002 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_2_MASK = 0x00000004 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_3_MASK = 0x00000008 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_4_MASK = 0x00000010 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_5_MASK = 0x00000020 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_6_MASK = 0x00000040 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_7_MASK = 0x00000080 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_8_MASK = 0x00000100 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_9_MASK = 0x00000200 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_10_MASK = 0x00000400 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_11_MASK = 0x00000800 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_12_MASK = 0x00001000 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_13_MASK = 0x00002000 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_14_MASK = 0x00004000 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_15_MASK = 0x00008000 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_16_MASK = 0x00010000 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_17_MASK = 0x00020000 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_18_MASK = 0x00040000 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_19_MASK = 0x00080000 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_20_MASK = 0x00100000 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_21_MASK = 0x00200000 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_22_MASK = 0x00400000 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_23_MASK = 0x00800000 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_24_MASK = 0x01000000 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_25_MASK = 0x02000000 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_26_MASK = 0x04000000 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_27_MASK = 0x08000000 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_28_MASK = 0x10000000 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_29_MASK = 0x20000000 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_30_MASK = 0x40000000 # macro +NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_31_MASK = 0x80000000 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_0__SHIFT = 0x0 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_1__SHIFT = 0x1 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_2__SHIFT = 0x2 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_3__SHIFT = 0x3 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_4__SHIFT = 0x4 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_5__SHIFT = 0x5 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_6__SHIFT = 0x6 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_7__SHIFT = 0x7 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_8__SHIFT = 0x8 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_9__SHIFT = 0x9 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_10__SHIFT = 0xa # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_11__SHIFT = 0xb # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_12__SHIFT = 0xc # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_13__SHIFT = 0xd # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_14__SHIFT = 0xe # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_15__SHIFT = 0xf # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_16__SHIFT = 0x10 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_17__SHIFT = 0x11 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_18__SHIFT = 0x12 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_19__SHIFT = 0x13 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_20__SHIFT = 0x14 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_21__SHIFT = 0x15 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_22__SHIFT = 0x16 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_23__SHIFT = 0x17 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_24__SHIFT = 0x18 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_25__SHIFT = 0x19 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_26__SHIFT = 0x1a # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_27__SHIFT = 0x1b # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_28__SHIFT = 0x1c # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_29__SHIFT = 0x1d # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_30__SHIFT = 0x1e # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_31__SHIFT = 0x1f # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_0_MASK = 0x00000001 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_1_MASK = 0x00000002 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_2_MASK = 0x00000004 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_3_MASK = 0x00000008 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_4_MASK = 0x00000010 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_5_MASK = 0x00000020 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_6_MASK = 0x00000040 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_7_MASK = 0x00000080 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_8_MASK = 0x00000100 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_9_MASK = 0x00000200 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_10_MASK = 0x00000400 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_11_MASK = 0x00000800 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_12_MASK = 0x00001000 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_13_MASK = 0x00002000 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_14_MASK = 0x00004000 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_15_MASK = 0x00008000 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_16_MASK = 0x00010000 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_17_MASK = 0x00020000 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_18_MASK = 0x00040000 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_19_MASK = 0x00080000 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_20_MASK = 0x00100000 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_21_MASK = 0x00200000 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_22_MASK = 0x00400000 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_23_MASK = 0x00800000 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_24_MASK = 0x01000000 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_25_MASK = 0x02000000 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_26_MASK = 0x04000000 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_27_MASK = 0x08000000 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_28_MASK = 0x10000000 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_29_MASK = 0x20000000 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_30_MASK = 0x40000000 # macro +NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_31_MASK = 0x80000000 # macro +PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE__SHIFT = 0x0 # macro +PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT__SHIFT = 0x8 # macro +PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT__SHIFT = 0x1f # macro +PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE_MASK = 0x000000FF # macro +PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT_MASK = 0x0000FF00 # macro +PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT_MASK = 0x80000000 # macro +PCIE_VDM_CNTL2__VdmP2pMode__SHIFT = 0x0 # macro +PCIE_VDM_CNTL2__MCTPEndpointEn__SHIFT = 0x2 # macro +PCIE_VDM_CNTL2__MCTPMultiSegEn__SHIFT = 0x3 # macro +PCIE_VDM_CNTL2__MCTPT2SMUEn__SHIFT = 0x4 # macro +PCIE_VDM_CNTL2__AMDVDM2SMUEn__SHIFT = 0x5 # macro +PCIE_VDM_CNTL2__OtherVDM2SMUEn__SHIFT = 0x6 # macro +PCIE_VDM_CNTL2__RouteAllToMCTPMaster__SHIFT = 0x7 # macro +PCIE_VDM_CNTL2__MCTPMasterSeg__SHIFT = 0x8 # macro +PCIE_VDM_CNTL2__MCTPMasterID__SHIFT = 0x10 # macro +PCIE_VDM_CNTL2__VdmP2pMode_MASK = 0x00000003 # macro +PCIE_VDM_CNTL2__MCTPEndpointEn_MASK = 0x00000004 # macro +PCIE_VDM_CNTL2__MCTPMultiSegEn_MASK = 0x00000008 # macro +PCIE_VDM_CNTL2__MCTPT2SMUEn_MASK = 0x00000010 # macro +PCIE_VDM_CNTL2__AMDVDM2SMUEn_MASK = 0x00000020 # macro +PCIE_VDM_CNTL2__OtherVDM2SMUEn_MASK = 0x00000040 # macro +PCIE_VDM_CNTL2__RouteAllToMCTPMaster_MASK = 0x00000080 # macro +PCIE_VDM_CNTL2__MCTPMasterSeg_MASK = 0x0000FF00 # macro +PCIE_VDM_CNTL2__MCTPMasterID_MASK = 0xFFFF0000 # macro +PCIE_VDM_CNTL3__APMTPMasterValid__SHIFT = 0xf # macro +PCIE_VDM_CNTL3__APMTPMasterID__SHIFT = 0x10 # macro +PCIE_VDM_CNTL3__APMTPMasterValid_MASK = 0x00008000 # macro +PCIE_VDM_CNTL3__APMTPMasterID_MASK = 0xFFFF0000 # macro +STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn__SHIFT = 0x0 # macro +STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn__SHIFT = 0x4 # macro +STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn__SHIFT = 0x8 # macro +STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn__SHIFT = 0xc # macro +STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn__SHIFT = 0x10 # macro +STALL_CONTROL_XBARPORT0_0__StallVC5ReqEn__SHIFT = 0x14 # macro +STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn__SHIFT = 0x1c # macro +STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn_MASK = 0x00000003 # macro +STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn_MASK = 0x00000030 # macro +STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn_MASK = 0x00000300 # macro +STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn_MASK = 0x00003000 # macro +STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn_MASK = 0x00030000 # macro +STALL_CONTROL_XBARPORT0_0__StallVC5ReqEn_MASK = 0x00300000 # macro +STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn_MASK = 0x30000000 # macro +STALL_CONTROL_XBARPORT0_1__StallVC0RspEn__SHIFT = 0x0 # macro +STALL_CONTROL_XBARPORT0_1__StallVC1RspEn__SHIFT = 0x4 # macro +STALL_CONTROL_XBARPORT0_1__StallVC2RspEn__SHIFT = 0x8 # macro +STALL_CONTROL_XBARPORT0_1__StallVC3RspEn__SHIFT = 0xc # macro +STALL_CONTROL_XBARPORT0_1__StallVC4RspEn__SHIFT = 0x10 # macro +STALL_CONTROL_XBARPORT0_1__StallVC5RspEn__SHIFT = 0x14 # macro +STALL_CONTROL_XBARPORT0_1__StallVC7RspEn__SHIFT = 0x1c # macro +STALL_CONTROL_XBARPORT0_1__StallVC0RspEn_MASK = 0x00000003 # macro +STALL_CONTROL_XBARPORT0_1__StallVC1RspEn_MASK = 0x00000030 # macro +STALL_CONTROL_XBARPORT0_1__StallVC2RspEn_MASK = 0x00000300 # macro +STALL_CONTROL_XBARPORT0_1__StallVC3RspEn_MASK = 0x00003000 # macro +STALL_CONTROL_XBARPORT0_1__StallVC4RspEn_MASK = 0x00030000 # macro +STALL_CONTROL_XBARPORT0_1__StallVC5RspEn_MASK = 0x00300000 # macro +STALL_CONTROL_XBARPORT0_1__StallVC7RspEn_MASK = 0x30000000 # macro +STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn__SHIFT = 0x0 # macro +STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn__SHIFT = 0x4 # macro +STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn__SHIFT = 0x8 # macro +STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn__SHIFT = 0xc # macro +STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn__SHIFT = 0x10 # macro +STALL_CONTROL_XBARPORT1_0__StallVC5ReqEn__SHIFT = 0x14 # macro +STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn__SHIFT = 0x1c # macro +STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn_MASK = 0x00000003 # macro +STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn_MASK = 0x00000030 # macro +STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn_MASK = 0x00000300 # macro +STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn_MASK = 0x00003000 # macro +STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn_MASK = 0x00030000 # macro +STALL_CONTROL_XBARPORT1_0__StallVC5ReqEn_MASK = 0x00300000 # macro +STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn_MASK = 0x30000000 # macro +STALL_CONTROL_XBARPORT1_1__StallVC0RspEn__SHIFT = 0x0 # macro +STALL_CONTROL_XBARPORT1_1__StallVC1RspEn__SHIFT = 0x4 # macro +STALL_CONTROL_XBARPORT1_1__StallVC2RspEn__SHIFT = 0x8 # macro +STALL_CONTROL_XBARPORT1_1__StallVC3RspEn__SHIFT = 0xc # macro +STALL_CONTROL_XBARPORT1_1__StallVC4RspEn__SHIFT = 0x10 # macro +STALL_CONTROL_XBARPORT1_1__StallVC5RspEn__SHIFT = 0x14 # macro +STALL_CONTROL_XBARPORT1_1__StallVC7RspEn__SHIFT = 0x1c # macro +STALL_CONTROL_XBARPORT1_1__StallVC0RspEn_MASK = 0x00000003 # macro +STALL_CONTROL_XBARPORT1_1__StallVC1RspEn_MASK = 0x00000030 # macro +STALL_CONTROL_XBARPORT1_1__StallVC2RspEn_MASK = 0x00000300 # macro +STALL_CONTROL_XBARPORT1_1__StallVC3RspEn_MASK = 0x00003000 # macro +STALL_CONTROL_XBARPORT1_1__StallVC4RspEn_MASK = 0x00030000 # macro +STALL_CONTROL_XBARPORT1_1__StallVC5RspEn_MASK = 0x00300000 # macro +STALL_CONTROL_XBARPORT1_1__StallVC7RspEn_MASK = 0x30000000 # macro +STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn__SHIFT = 0x0 # macro +STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn__SHIFT = 0x4 # macro +STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn__SHIFT = 0x8 # macro +STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn__SHIFT = 0xc # macro +STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn__SHIFT = 0x10 # macro +STALL_CONTROL_XBARPORT2_0__StallVC5ReqEn__SHIFT = 0x14 # macro +STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn__SHIFT = 0x1c # macro +STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn_MASK = 0x00000003 # macro +STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn_MASK = 0x00000030 # macro +STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn_MASK = 0x00000300 # macro +STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn_MASK = 0x00003000 # macro +STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn_MASK = 0x00030000 # macro +STALL_CONTROL_XBARPORT2_0__StallVC5ReqEn_MASK = 0x00300000 # macro +STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn_MASK = 0x30000000 # macro +STALL_CONTROL_XBARPORT2_1__StallVC0RspEn__SHIFT = 0x0 # macro +STALL_CONTROL_XBARPORT2_1__StallVC1RspEn__SHIFT = 0x4 # macro +STALL_CONTROL_XBARPORT2_1__StallVC2RspEn__SHIFT = 0x8 # macro +STALL_CONTROL_XBARPORT2_1__StallVC3RspEn__SHIFT = 0xc # macro +STALL_CONTROL_XBARPORT2_1__StallVC4RspEn__SHIFT = 0x10 # macro +STALL_CONTROL_XBARPORT2_1__StallVC5RspEn__SHIFT = 0x14 # macro +STALL_CONTROL_XBARPORT2_1__StallVC7RspEn__SHIFT = 0x1c # macro +STALL_CONTROL_XBARPORT2_1__StallVC0RspEn_MASK = 0x00000003 # macro +STALL_CONTROL_XBARPORT2_1__StallVC1RspEn_MASK = 0x00000030 # macro +STALL_CONTROL_XBARPORT2_1__StallVC2RspEn_MASK = 0x00000300 # macro +STALL_CONTROL_XBARPORT2_1__StallVC3RspEn_MASK = 0x00003000 # macro +STALL_CONTROL_XBARPORT2_1__StallVC4RspEn_MASK = 0x00030000 # macro +STALL_CONTROL_XBARPORT2_1__StallVC5RspEn_MASK = 0x00300000 # macro +STALL_CONTROL_XBARPORT2_1__StallVC7RspEn_MASK = 0x30000000 # macro +STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn__SHIFT = 0x0 # macro +STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn__SHIFT = 0x4 # macro +STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn__SHIFT = 0x8 # macro +STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn__SHIFT = 0xc # macro +STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn__SHIFT = 0x10 # macro +STALL_CONTROL_XBARPORT3_0__StallVC5ReqEn__SHIFT = 0x14 # macro +STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn__SHIFT = 0x1c # macro +STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn_MASK = 0x00000003 # macro +STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn_MASK = 0x00000030 # macro +STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn_MASK = 0x00000300 # macro +STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn_MASK = 0x00003000 # macro +STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn_MASK = 0x00030000 # macro +STALL_CONTROL_XBARPORT3_0__StallVC5ReqEn_MASK = 0x00300000 # macro +STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn_MASK = 0x30000000 # macro +STALL_CONTROL_XBARPORT3_1__StallVC0RspEn__SHIFT = 0x0 # macro +STALL_CONTROL_XBARPORT3_1__StallVC1RspEn__SHIFT = 0x4 # macro +STALL_CONTROL_XBARPORT3_1__StallVC2RspEn__SHIFT = 0x8 # macro +STALL_CONTROL_XBARPORT3_1__StallVC3RspEn__SHIFT = 0xc # macro +STALL_CONTROL_XBARPORT3_1__StallVC4RspEn__SHIFT = 0x10 # macro +STALL_CONTROL_XBARPORT3_1__StallVC5RspEn__SHIFT = 0x14 # macro +STALL_CONTROL_XBARPORT3_1__StallVC7RspEn__SHIFT = 0x1c # macro +STALL_CONTROL_XBARPORT3_1__StallVC0RspEn_MASK = 0x00000003 # macro +STALL_CONTROL_XBARPORT3_1__StallVC1RspEn_MASK = 0x00000030 # macro +STALL_CONTROL_XBARPORT3_1__StallVC2RspEn_MASK = 0x00000300 # macro +STALL_CONTROL_XBARPORT3_1__StallVC3RspEn_MASK = 0x00003000 # macro +STALL_CONTROL_XBARPORT3_1__StallVC4RspEn_MASK = 0x00030000 # macro +STALL_CONTROL_XBARPORT3_1__StallVC5RspEn_MASK = 0x00300000 # macro +STALL_CONTROL_XBARPORT3_1__StallVC7RspEn_MASK = 0x30000000 # macro +STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn__SHIFT = 0x0 # macro +STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn__SHIFT = 0x4 # macro +STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn__SHIFT = 0x8 # macro +STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn__SHIFT = 0xc # macro +STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn__SHIFT = 0x10 # macro +STALL_CONTROL_XBARPORT4_0__StallVC5ReqEn__SHIFT = 0x14 # macro +STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn__SHIFT = 0x1c # macro +STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn_MASK = 0x00000003 # macro +STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn_MASK = 0x00000030 # macro +STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn_MASK = 0x00000300 # macro +STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn_MASK = 0x00003000 # macro +STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn_MASK = 0x00030000 # macro +STALL_CONTROL_XBARPORT4_0__StallVC5ReqEn_MASK = 0x00300000 # macro +STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn_MASK = 0x30000000 # macro +STALL_CONTROL_XBARPORT4_1__StallVC0RspEn__SHIFT = 0x0 # macro +STALL_CONTROL_XBARPORT4_1__StallVC1RspEn__SHIFT = 0x4 # macro +STALL_CONTROL_XBARPORT4_1__StallVC2RspEn__SHIFT = 0x8 # macro +STALL_CONTROL_XBARPORT4_1__StallVC3RspEn__SHIFT = 0xc # macro +STALL_CONTROL_XBARPORT4_1__StallVC4RspEn__SHIFT = 0x10 # macro +STALL_CONTROL_XBARPORT4_1__StallVC5RspEn__SHIFT = 0x14 # macro +STALL_CONTROL_XBARPORT4_1__StallVC7RspEn__SHIFT = 0x1c # macro +STALL_CONTROL_XBARPORT4_1__StallVC0RspEn_MASK = 0x00000003 # macro +STALL_CONTROL_XBARPORT4_1__StallVC1RspEn_MASK = 0x00000030 # macro +STALL_CONTROL_XBARPORT4_1__StallVC2RspEn_MASK = 0x00000300 # macro +STALL_CONTROL_XBARPORT4_1__StallVC3RspEn_MASK = 0x00003000 # macro +STALL_CONTROL_XBARPORT4_1__StallVC4RspEn_MASK = 0x00030000 # macro +STALL_CONTROL_XBARPORT4_1__StallVC5RspEn_MASK = 0x00300000 # macro +STALL_CONTROL_XBARPORT4_1__StallVC7RspEn_MASK = 0x30000000 # macro +STALL_CONTROL_XBARPORT5_0__StallVC0ReqEn__SHIFT = 0x0 # macro +STALL_CONTROL_XBARPORT5_0__StallVC1ReqEn__SHIFT = 0x4 # macro +STALL_CONTROL_XBARPORT5_0__StallVC2ReqEn__SHIFT = 0x8 # macro +STALL_CONTROL_XBARPORT5_0__StallVC3ReqEn__SHIFT = 0xc # macro +STALL_CONTROL_XBARPORT5_0__StallVC4ReqEn__SHIFT = 0x10 # macro +STALL_CONTROL_XBARPORT5_0__StallVC5ReqEn__SHIFT = 0x14 # macro +STALL_CONTROL_XBARPORT5_0__StallVC7ReqEn__SHIFT = 0x1c # macro +STALL_CONTROL_XBARPORT5_0__StallVC0ReqEn_MASK = 0x00000003 # macro +STALL_CONTROL_XBARPORT5_0__StallVC1ReqEn_MASK = 0x00000030 # macro +STALL_CONTROL_XBARPORT5_0__StallVC2ReqEn_MASK = 0x00000300 # macro +STALL_CONTROL_XBARPORT5_0__StallVC3ReqEn_MASK = 0x00003000 # macro +STALL_CONTROL_XBARPORT5_0__StallVC4ReqEn_MASK = 0x00030000 # macro +STALL_CONTROL_XBARPORT5_0__StallVC5ReqEn_MASK = 0x00300000 # macro +STALL_CONTROL_XBARPORT5_0__StallVC7ReqEn_MASK = 0x30000000 # macro +STALL_CONTROL_XBARPORT5_1__StallVC0RspEn__SHIFT = 0x0 # macro +STALL_CONTROL_XBARPORT5_1__StallVC1RspEn__SHIFT = 0x4 # macro +STALL_CONTROL_XBARPORT5_1__StallVC2RspEn__SHIFT = 0x8 # macro +STALL_CONTROL_XBARPORT5_1__StallVC3RspEn__SHIFT = 0xc # macro +STALL_CONTROL_XBARPORT5_1__StallVC4RspEn__SHIFT = 0x10 # macro +STALL_CONTROL_XBARPORT5_1__StallVC5RspEn__SHIFT = 0x14 # macro +STALL_CONTROL_XBARPORT5_1__StallVC7RspEn__SHIFT = 0x1c # macro +STALL_CONTROL_XBARPORT5_1__StallVC0RspEn_MASK = 0x00000003 # macro +STALL_CONTROL_XBARPORT5_1__StallVC1RspEn_MASK = 0x00000030 # macro +STALL_CONTROL_XBARPORT5_1__StallVC2RspEn_MASK = 0x00000300 # macro +STALL_CONTROL_XBARPORT5_1__StallVC3RspEn_MASK = 0x00003000 # macro +STALL_CONTROL_XBARPORT5_1__StallVC4RspEn_MASK = 0x00030000 # macro +STALL_CONTROL_XBARPORT5_1__StallVC5RspEn_MASK = 0x00300000 # macro +STALL_CONTROL_XBARPORT5_1__StallVC7RspEn_MASK = 0x30000000 # macro +NB_DRAM3_BASE__DRAM3_BASE__SHIFT = 0x0 # macro +NB_DRAM3_BASE__DRAM3_BASE_MASK = 0x3FFFFFFF # macro +PSP_BASE_ADDR_LO__PSP_MMIO_EN__SHIFT = 0x0 # macro +PSP_BASE_ADDR_LO__PSP_MMIO_LOCK__SHIFT = 0x8 # macro +PSP_BASE_ADDR_LO__PSP_BASE_ADDR_LO__SHIFT = 0x14 # macro +PSP_BASE_ADDR_LO__PSP_MMIO_EN_MASK = 0x00000001 # macro +PSP_BASE_ADDR_LO__PSP_MMIO_LOCK_MASK = 0x00000100 # macro +PSP_BASE_ADDR_LO__PSP_BASE_ADDR_LO_MASK = 0xFFF00000 # macro +PSP_BASE_ADDR_HI__PSP_BASE_ADDR_HI__SHIFT = 0x0 # macro +PSP_BASE_ADDR_HI__PSP_BASE_ADDR_HI_MASK = 0x0000FFFF # macro +SMU_BASE_ADDR_LO__SMU_MMIO_EN__SHIFT = 0x0 # macro +SMU_BASE_ADDR_LO__SMU_MMIO_LOCK__SHIFT = 0x1 # macro +SMU_BASE_ADDR_LO__SMU_BASE_ADDR_LO__SHIFT = 0x14 # macro +SMU_BASE_ADDR_LO__SMU_MMIO_EN_MASK = 0x00000001 # macro +SMU_BASE_ADDR_LO__SMU_MMIO_LOCK_MASK = 0x00000002 # macro +SMU_BASE_ADDR_LO__SMU_BASE_ADDR_LO_MASK = 0xFFF00000 # macro +SMU_BASE_ADDR_HI__SMU_BASE_ADDR_HI__SHIFT = 0x0 # macro +SMU_BASE_ADDR_HI__SMU_BASE_ADDR_HI_MASK = 0x0000FFFF # macro +SCRATCH_4__SCRATCH_4__SHIFT = 0x0 # macro +SCRATCH_4__SCRATCH_4_MASK = 0xFFFFFFFF # macro +SCRATCH_5__SCRATCH_5__SHIFT = 0x0 # macro +SCRATCH_5__SCRATCH_5_MASK = 0xFFFFFFFF # macro +SMU_BLOCK_CPU__SMUBlockCPU_Valid__SHIFT = 0x0 # macro +SMU_BLOCK_CPU__SMUBlockCPU_Valid_MASK = 0x00000001 # macro +SMU_BLOCK_CPU_STATUS__SMUBlockCPU_Status__SHIFT = 0x0 # macro +SMU_BLOCK_CPU_STATUS__SMUBlockCPU_Status_MASK = 0x00000001 # macro +TRAP_STATUS__TrapReqValid__SHIFT = 0x0 # macro +TRAP_STATUS__TrapNumber__SHIFT = 0x8 # macro +TRAP_STATUS__TrapS2Vld__SHIFT = 0xc # macro +TRAP_STATUS__TrapS2Number__SHIFT = 0x10 # macro +TRAP_STATUS__TrapReqValid_MASK = 0x00000001 # macro +TRAP_STATUS__TrapNumber_MASK = 0x00000F00 # macro +TRAP_STATUS__TrapS2Vld_MASK = 0x00001000 # macro +TRAP_STATUS__TrapS2Number_MASK = 0x03FF0000 # macro +TRAP_REQUEST0__TrapReqAddrLo__SHIFT = 0x2 # macro +TRAP_REQUEST0__TrapReqAddrLo_MASK = 0xFFFFFFFC # macro +TRAP_REQUEST1__TrapReqAddrHi__SHIFT = 0x0 # macro +TRAP_REQUEST1__TrapReqAddrHi_MASK = 0xFFFFFFFF # macro +TRAP_REQUEST2__TrapReqCmd__SHIFT = 0x0 # macro +TRAP_REQUEST2__TrapAttr__SHIFT = 0x8 # macro +TRAP_REQUEST2__TrapReqLen__SHIFT = 0x10 # macro +TRAP_REQUEST2__TrapReqCmd_MASK = 0x0000003F # macro +TRAP_REQUEST2__TrapAttr_MASK = 0x0000FF00 # macro +TRAP_REQUEST2__TrapReqLen_MASK = 0x003F0000 # macro +TRAP_REQUEST3__TrapReqVC__SHIFT = 0x0 # macro +TRAP_REQUEST3__TrapReqBlockLevel__SHIFT = 0x4 # macro +TRAP_REQUEST3__TrapReqChain__SHIFT = 0x6 # macro +TRAP_REQUEST3__TrapReqIO__SHIFT = 0x7 # macro +TRAP_REQUEST3__TrapReqPassPW__SHIFT = 0x8 # macro +TRAP_REQUEST3__TrapReqRspPassPW__SHIFT = 0x9 # macro +TRAP_REQUEST3__TrapReqUnitID__SHIFT = 0x10 # macro +TRAP_REQUEST3__TrapReqVC_MASK = 0x00000007 # macro +TRAP_REQUEST3__TrapReqBlockLevel_MASK = 0x00000030 # macro +TRAP_REQUEST3__TrapReqChain_MASK = 0x00000040 # macro +TRAP_REQUEST3__TrapReqIO_MASK = 0x00000080 # macro +TRAP_REQUEST3__TrapReqPassPW_MASK = 0x00000100 # macro +TRAP_REQUEST3__TrapReqRspPassPW_MASK = 0x00000200 # macro +TRAP_REQUEST3__TrapReqUnitID_MASK = 0x003F0000 # macro +TRAP_REQUEST4__TrapReqSecLevel__SHIFT = 0x0 # macro +TRAP_REQUEST4__TrapReqSecLevel_MASK = 0x0000000F # macro +TRAP_REQUEST5__TrapReqDataVC__SHIFT = 0x0 # macro +TRAP_REQUEST5__TrapReqDataErr__SHIFT = 0x4 # macro +TRAP_REQUEST5__TrapReqDataParity__SHIFT = 0x8 # macro +TRAP_REQUEST5__TrapReqDataVC_MASK = 0x00000007 # macro +TRAP_REQUEST5__TrapReqDataErr_MASK = 0x00000010 # macro +TRAP_REQUEST5__TrapReqDataParity_MASK = 0x0000FF00 # macro +TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0__SHIFT = 0x0 # macro +TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0_MASK = 0xFFFFFFFF # macro +TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1__SHIFT = 0x0 # macro +TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1_MASK = 0xFFFFFFFF # macro +TRAP_REQUEST_DATA0__TrapReqData0__SHIFT = 0x0 # macro +TRAP_REQUEST_DATA0__TrapReqData0_MASK = 0xFFFFFFFF # macro +TRAP_REQUEST_DATA1__TrapReqData1__SHIFT = 0x0 # macro +TRAP_REQUEST_DATA1__TrapReqData1_MASK = 0xFFFFFFFF # macro +TRAP_REQUEST_DATA2__TrapReqData2__SHIFT = 0x0 # macro +TRAP_REQUEST_DATA2__TrapReqData2_MASK = 0xFFFFFFFF # macro +TRAP_REQUEST_DATA3__TrapReqData3__SHIFT = 0x0 # macro +TRAP_REQUEST_DATA3__TrapReqData3_MASK = 0xFFFFFFFF # macro +TRAP_REQUEST_DATA4__TrapReqData4__SHIFT = 0x0 # macro +TRAP_REQUEST_DATA4__TrapReqData4_MASK = 0xFFFFFFFF # macro +TRAP_REQUEST_DATA5__TrapReqData5__SHIFT = 0x0 # macro +TRAP_REQUEST_DATA5__TrapReqData5_MASK = 0xFFFFFFFF # macro +TRAP_REQUEST_DATA6__TrapReqData6__SHIFT = 0x0 # macro +TRAP_REQUEST_DATA6__TrapReqData6_MASK = 0xFFFFFFFF # macro +TRAP_REQUEST_DATA7__TrapReqData7__SHIFT = 0x0 # macro +TRAP_REQUEST_DATA7__TrapReqData7_MASK = 0xFFFFFFFF # macro +TRAP_REQUEST_DATA8__TrapReqData8__SHIFT = 0x0 # macro +TRAP_REQUEST_DATA8__TrapReqData8_MASK = 0xFFFFFFFF # macro +TRAP_REQUEST_DATA9__TrapReqData9__SHIFT = 0x0 # macro +TRAP_REQUEST_DATA9__TrapReqData9_MASK = 0xFFFFFFFF # macro +TRAP_REQUEST_DATA10__TrapReqData10__SHIFT = 0x0 # macro +TRAP_REQUEST_DATA10__TrapReqData10_MASK = 0xFFFFFFFF # macro +TRAP_REQUEST_DATA11__TrapReqData11__SHIFT = 0x0 # macro +TRAP_REQUEST_DATA11__TrapReqData11_MASK = 0xFFFFFFFF # macro +TRAP_REQUEST_DATA12__TrapReqData12__SHIFT = 0x0 # macro +TRAP_REQUEST_DATA12__TrapReqData12_MASK = 0xFFFFFFFF # macro +TRAP_REQUEST_DATA13__TrapReqData13__SHIFT = 0x0 # macro +TRAP_REQUEST_DATA13__TrapReqData13_MASK = 0xFFFFFFFF # macro +TRAP_REQUEST_DATA14__TrapReqData14__SHIFT = 0x0 # macro +TRAP_REQUEST_DATA14__TrapReqData14_MASK = 0xFFFFFFFF # macro +TRAP_REQUEST_DATA15__TrapReqData15__SHIFT = 0x0 # macro +TRAP_REQUEST_DATA15__TrapReqData15_MASK = 0xFFFFFFFF # macro +TRAP_RESPONSE_CONTROL__TrapRspTrigger__SHIFT = 0x0 # macro +TRAP_RESPONSE_CONTROL__TrapRspReqPassthru__SHIFT = 0x1 # macro +TRAP_RESPONSE_CONTROL__TrapRspTrigger_MASK = 0x00000001 # macro +TRAP_RESPONSE_CONTROL__TrapRspReqPassthru_MASK = 0x00000002 # macro +TRAP_RESPONSE0__TrapRspPassPW__SHIFT = 0x0 # macro +TRAP_RESPONSE0__TrapRspStatus__SHIFT = 0x4 # macro +TRAP_RESPONSE0__TrapRspDataStatus__SHIFT = 0x10 # macro +TRAP_RESPONSE0__TrapRspPassPW_MASK = 0x00000001 # macro +TRAP_RESPONSE0__TrapRspStatus_MASK = 0x000000F0 # macro +TRAP_RESPONSE0__TrapRspDataStatus_MASK = 0x00FF0000 # macro +TRAP_RESPONSE_DATA0__TrapRdRspData0__SHIFT = 0x0 # macro +TRAP_RESPONSE_DATA0__TrapRdRspData0_MASK = 0xFFFFFFFF # macro +TRAP_RESPONSE_DATA1__TrapRdRspData1__SHIFT = 0x0 # macro +TRAP_RESPONSE_DATA1__TrapRdRspData1_MASK = 0xFFFFFFFF # macro +TRAP_RESPONSE_DATA2__TrapRdRspData2__SHIFT = 0x0 # macro +TRAP_RESPONSE_DATA2__TrapRdRspData2_MASK = 0xFFFFFFFF # macro +TRAP_RESPONSE_DATA3__TrapRdRspData3__SHIFT = 0x0 # macro +TRAP_RESPONSE_DATA3__TrapRdRspData3_MASK = 0xFFFFFFFF # macro +TRAP_RESPONSE_DATA4__TrapRdRspData4__SHIFT = 0x0 # macro +TRAP_RESPONSE_DATA4__TrapRdRspData4_MASK = 0xFFFFFFFF # macro +TRAP_RESPONSE_DATA5__TrapRdRspData5__SHIFT = 0x0 # macro +TRAP_RESPONSE_DATA5__TrapRdRspData5_MASK = 0xFFFFFFFF # macro +TRAP_RESPONSE_DATA6__TrapRdRspData6__SHIFT = 0x0 # macro +TRAP_RESPONSE_DATA6__TrapRdRspData6_MASK = 0xFFFFFFFF # macro +TRAP_RESPONSE_DATA7__TrapRdRspData7__SHIFT = 0x0 # macro +TRAP_RESPONSE_DATA7__TrapRdRspData7_MASK = 0xFFFFFFFF # macro +TRAP_RESPONSE_DATA8__TrapRdRspData8__SHIFT = 0x0 # macro +TRAP_RESPONSE_DATA8__TrapRdRspData8_MASK = 0xFFFFFFFF # macro +TRAP_RESPONSE_DATA9__TrapRdRspData9__SHIFT = 0x0 # macro +TRAP_RESPONSE_DATA9__TrapRdRspData9_MASK = 0xFFFFFFFF # macro +TRAP_RESPONSE_DATA10__TrapRdRspData10__SHIFT = 0x0 # macro +TRAP_RESPONSE_DATA10__TrapRdRspData10_MASK = 0xFFFFFFFF # macro +TRAP_RESPONSE_DATA11__TrapRdRspData11__SHIFT = 0x0 # macro +TRAP_RESPONSE_DATA11__TrapRdRspData11_MASK = 0xFFFFFFFF # macro +TRAP_RESPONSE_DATA12__TrapRdRspData12__SHIFT = 0x0 # macro +TRAP_RESPONSE_DATA12__TrapRdRspData12_MASK = 0xFFFFFFFF # macro +TRAP_RESPONSE_DATA13__TrapRdRspData13__SHIFT = 0x0 # macro +TRAP_RESPONSE_DATA13__TrapRdRspData13_MASK = 0xFFFFFFFF # macro +TRAP_RESPONSE_DATA14__TrapRdRspData14__SHIFT = 0x0 # macro +TRAP_RESPONSE_DATA14__TrapRdRspData14_MASK = 0xFFFFFFFF # macro +TRAP_RESPONSE_DATA15__TrapRdRspData15__SHIFT = 0x0 # macro +TRAP_RESPONSE_DATA15__TrapRdRspData15_MASK = 0xFFFFFFFF # macro +TRAP0_CONTROL0__Trap0En__SHIFT = 0x0 # macro +TRAP0_CONTROL0__Trap0SMUIntr__SHIFT = 0x3 # macro +TRAP0_CONTROL0__Trap0Stage2Ptr__SHIFT = 0xe # macro +TRAP0_CONTROL0__Trap0CrossTrigger__SHIFT = 0x18 # macro +TRAP0_CONTROL0__Trap0Stage2En__SHIFT = 0x1f # macro +TRAP0_CONTROL0__Trap0En_MASK = 0x00000001 # macro +TRAP0_CONTROL0__Trap0SMUIntr_MASK = 0x00000008 # macro +TRAP0_CONTROL0__Trap0Stage2Ptr_MASK = 0x00FFC000 # macro +TRAP0_CONTROL0__Trap0CrossTrigger_MASK = 0x0F000000 # macro +TRAP0_CONTROL0__Trap0Stage2En_MASK = 0x80000000 # macro +TRAP0_ADDRESS_LO__Trap0AddrLo__SHIFT = 0x2 # macro +TRAP0_ADDRESS_LO__Trap0AddrLo_MASK = 0xFFFFFFFC # macro +TRAP0_ADDRESS_HI__Trap0AddrHi__SHIFT = 0x0 # macro +TRAP0_ADDRESS_HI__Trap0AddrHi_MASK = 0xFFFFFFFF # macro +TRAP0_COMMAND__Trap0Cmd0__SHIFT = 0x0 # macro +TRAP0_COMMAND__Trap0Cmd1__SHIFT = 0x8 # macro +TRAP0_COMMAND__Trap0Cmd0_MASK = 0x0000003F # macro +TRAP0_COMMAND__Trap0Cmd1_MASK = 0x00003F00 # macro +TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask__SHIFT = 0x2 # macro +TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask_MASK = 0xFFFFFFFC # macro +TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask__SHIFT = 0x0 # macro +TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask_MASK = 0xFFFFFFFF # macro +TRAP0_COMMAND_MASK__Trap0Cmd0Mask__SHIFT = 0x0 # macro +TRAP0_COMMAND_MASK__Trap0Cmd1Mask__SHIFT = 0x8 # macro +TRAP0_COMMAND_MASK__Trap0Cmd0Mask_MASK = 0x0000003F # macro +TRAP0_COMMAND_MASK__Trap0Cmd1Mask_MASK = 0x00003F00 # macro +TRAP1_CONTROL0__Trap1En__SHIFT = 0x0 # macro +TRAP1_CONTROL0__Trap1SMUIntr__SHIFT = 0x3 # macro +TRAP1_CONTROL0__Trap1Stage2Ptr__SHIFT = 0xe # macro +TRAP1_CONTROL0__Trap1CrossTrigger__SHIFT = 0x18 # macro +TRAP1_CONTROL0__Trap1Stage2En__SHIFT = 0x1f # macro +TRAP1_CONTROL0__Trap1En_MASK = 0x00000001 # macro +TRAP1_CONTROL0__Trap1SMUIntr_MASK = 0x00000008 # macro +TRAP1_CONTROL0__Trap1Stage2Ptr_MASK = 0x00FFC000 # macro +TRAP1_CONTROL0__Trap1CrossTrigger_MASK = 0x0F000000 # macro +TRAP1_CONTROL0__Trap1Stage2En_MASK = 0x80000000 # macro +TRAP1_ADDRESS_LO__Trap1AddrLo__SHIFT = 0x2 # macro +TRAP1_ADDRESS_LO__Trap1AddrLo_MASK = 0xFFFFFFFC # macro +TRAP1_ADDRESS_HI__Trap1AddrHi__SHIFT = 0x0 # macro +TRAP1_ADDRESS_HI__Trap1AddrHi_MASK = 0xFFFFFFFF # macro +TRAP1_COMMAND__Trap1Cmd0__SHIFT = 0x0 # macro +TRAP1_COMMAND__Trap1Cmd1__SHIFT = 0x8 # macro +TRAP1_COMMAND__Trap1Cmd0_MASK = 0x0000003F # macro +TRAP1_COMMAND__Trap1Cmd1_MASK = 0x00003F00 # macro +TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask__SHIFT = 0x2 # macro +TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask_MASK = 0xFFFFFFFC # macro +TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask__SHIFT = 0x0 # macro +TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask_MASK = 0xFFFFFFFF # macro +TRAP1_COMMAND_MASK__Trap1Cmd0Mask__SHIFT = 0x0 # macro +TRAP1_COMMAND_MASK__Trap1Cmd1Mask__SHIFT = 0x8 # macro +TRAP1_COMMAND_MASK__Trap1Cmd0Mask_MASK = 0x0000003F # macro +TRAP1_COMMAND_MASK__Trap1Cmd1Mask_MASK = 0x00003F00 # macro +TRAP2_CONTROL0__Trap2En__SHIFT = 0x0 # macro +TRAP2_CONTROL0__Trap2SMUIntr__SHIFT = 0x3 # macro +TRAP2_CONTROL0__Trap2Stage2Ptr__SHIFT = 0xe # macro +TRAP2_CONTROL0__Trap2CrossTrigger__SHIFT = 0x18 # macro +TRAP2_CONTROL0__Trap2Stage2En__SHIFT = 0x1f # macro +TRAP2_CONTROL0__Trap2En_MASK = 0x00000001 # macro +TRAP2_CONTROL0__Trap2SMUIntr_MASK = 0x00000008 # macro +TRAP2_CONTROL0__Trap2Stage2Ptr_MASK = 0x00FFC000 # macro +TRAP2_CONTROL0__Trap2CrossTrigger_MASK = 0x0F000000 # macro +TRAP2_CONTROL0__Trap2Stage2En_MASK = 0x80000000 # macro +TRAP2_ADDRESS_LO__Trap2AddrLo__SHIFT = 0x2 # macro +TRAP2_ADDRESS_LO__Trap2AddrLo_MASK = 0xFFFFFFFC # macro +TRAP2_ADDRESS_HI__Trap2AddrHi__SHIFT = 0x0 # macro +TRAP2_ADDRESS_HI__Trap2AddrHi_MASK = 0xFFFFFFFF # macro +TRAP2_COMMAND__Trap2Cmd0__SHIFT = 0x0 # macro +TRAP2_COMMAND__Trap2Cmd1__SHIFT = 0x8 # macro +TRAP2_COMMAND__Trap2Cmd0_MASK = 0x0000003F # macro +TRAP2_COMMAND__Trap2Cmd1_MASK = 0x00003F00 # macro +TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask__SHIFT = 0x2 # macro +TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask_MASK = 0xFFFFFFFC # macro +TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask__SHIFT = 0x0 # macro +TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask_MASK = 0xFFFFFFFF # macro +TRAP2_COMMAND_MASK__Trap2Cmd0Mask__SHIFT = 0x0 # macro +TRAP2_COMMAND_MASK__Trap2Cmd1Mask__SHIFT = 0x8 # macro +TRAP2_COMMAND_MASK__Trap2Cmd0Mask_MASK = 0x0000003F # macro +TRAP2_COMMAND_MASK__Trap2Cmd1Mask_MASK = 0x00003F00 # macro +TRAP3_CONTROL0__Trap3En__SHIFT = 0x0 # macro +TRAP3_CONTROL0__Trap3SMUIntr__SHIFT = 0x3 # macro +TRAP3_CONTROL0__Trap3Stage2Ptr__SHIFT = 0xe # macro +TRAP3_CONTROL0__Trap3CrossTrigger__SHIFT = 0x18 # macro +TRAP3_CONTROL0__Trap3Stage2En__SHIFT = 0x1f # macro +TRAP3_CONTROL0__Trap3En_MASK = 0x00000001 # macro +TRAP3_CONTROL0__Trap3SMUIntr_MASK = 0x00000008 # macro +TRAP3_CONTROL0__Trap3Stage2Ptr_MASK = 0x00FFC000 # macro +TRAP3_CONTROL0__Trap3CrossTrigger_MASK = 0x0F000000 # macro +TRAP3_CONTROL0__Trap3Stage2En_MASK = 0x80000000 # macro +TRAP3_ADDRESS_LO__Trap3AddrLo__SHIFT = 0x2 # macro +TRAP3_ADDRESS_LO__Trap3AddrLo_MASK = 0xFFFFFFFC # macro +TRAP3_ADDRESS_HI__Trap3AddrHi__SHIFT = 0x0 # macro +TRAP3_ADDRESS_HI__Trap3AddrHi_MASK = 0xFFFFFFFF # macro +TRAP3_COMMAND__Trap3Cmd0__SHIFT = 0x0 # macro +TRAP3_COMMAND__Trap3Cmd1__SHIFT = 0x8 # macro +TRAP3_COMMAND__Trap3Cmd0_MASK = 0x0000003F # macro +TRAP3_COMMAND__Trap3Cmd1_MASK = 0x00003F00 # macro +TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask__SHIFT = 0x2 # macro +TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask_MASK = 0xFFFFFFFC # macro +TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask__SHIFT = 0x0 # macro +TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask_MASK = 0xFFFFFFFF # macro +TRAP3_COMMAND_MASK__Trap3Cmd0Mask__SHIFT = 0x0 # macro +TRAP3_COMMAND_MASK__Trap3Cmd1Mask__SHIFT = 0x8 # macro +TRAP3_COMMAND_MASK__Trap3Cmd0Mask_MASK = 0x0000003F # macro +TRAP3_COMMAND_MASK__Trap3Cmd1Mask_MASK = 0x00003F00 # macro +TRAP4_CONTROL0__Trap4En__SHIFT = 0x0 # macro +TRAP4_CONTROL0__Trap4SMUIntr__SHIFT = 0x3 # macro +TRAP4_CONTROL0__Trap4Stage2Ptr__SHIFT = 0xe # macro +TRAP4_CONTROL0__Trap4CrossTrigger__SHIFT = 0x18 # macro +TRAP4_CONTROL0__Trap4Stage2En__SHIFT = 0x1f # macro +TRAP4_CONTROL0__Trap4En_MASK = 0x00000001 # macro +TRAP4_CONTROL0__Trap4SMUIntr_MASK = 0x00000008 # macro +TRAP4_CONTROL0__Trap4Stage2Ptr_MASK = 0x00FFC000 # macro +TRAP4_CONTROL0__Trap4CrossTrigger_MASK = 0x0F000000 # macro +TRAP4_CONTROL0__Trap4Stage2En_MASK = 0x80000000 # macro +TRAP4_ADDRESS_LO__Trap4AddrLo__SHIFT = 0x2 # macro +TRAP4_ADDRESS_LO__Trap4AddrLo_MASK = 0xFFFFFFFC # macro +TRAP4_ADDRESS_HI__Trap4AddrHi__SHIFT = 0x0 # macro +TRAP4_ADDRESS_HI__Trap4AddrHi_MASK = 0xFFFFFFFF # macro +TRAP4_COMMAND__Trap4Cmd0__SHIFT = 0x0 # macro +TRAP4_COMMAND__Trap4Cmd1__SHIFT = 0x8 # macro +TRAP4_COMMAND__Trap4Cmd0_MASK = 0x0000003F # macro +TRAP4_COMMAND__Trap4Cmd1_MASK = 0x00003F00 # macro +TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask__SHIFT = 0x2 # macro +TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask_MASK = 0xFFFFFFFC # macro +TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask__SHIFT = 0x0 # macro +TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask_MASK = 0xFFFFFFFF # macro +TRAP4_COMMAND_MASK__Trap4Cmd0Mask__SHIFT = 0x0 # macro +TRAP4_COMMAND_MASK__Trap4Cmd1Mask__SHIFT = 0x8 # macro +TRAP4_COMMAND_MASK__Trap4Cmd0Mask_MASK = 0x0000003F # macro +TRAP4_COMMAND_MASK__Trap4Cmd1Mask_MASK = 0x00003F00 # macro +TRAP5_CONTROL0__Trap5En__SHIFT = 0x0 # macro +TRAP5_CONTROL0__Trap5SMUIntr__SHIFT = 0x3 # macro +TRAP5_CONTROL0__Trap5Stage2Ptr__SHIFT = 0xe # macro +TRAP5_CONTROL0__Trap5CrossTrigger__SHIFT = 0x18 # macro +TRAP5_CONTROL0__Trap5Stage2En__SHIFT = 0x1f # macro +TRAP5_CONTROL0__Trap5En_MASK = 0x00000001 # macro +TRAP5_CONTROL0__Trap5SMUIntr_MASK = 0x00000008 # macro +TRAP5_CONTROL0__Trap5Stage2Ptr_MASK = 0x00FFC000 # macro +TRAP5_CONTROL0__Trap5CrossTrigger_MASK = 0x0F000000 # macro +TRAP5_CONTROL0__Trap5Stage2En_MASK = 0x80000000 # macro +TRAP5_ADDRESS_LO__Trap5AddrLo__SHIFT = 0x2 # macro +TRAP5_ADDRESS_LO__Trap5AddrLo_MASK = 0xFFFFFFFC # macro +TRAP5_ADDRESS_HI__Trap5AddrHi__SHIFT = 0x0 # macro +TRAP5_ADDRESS_HI__Trap5AddrHi_MASK = 0xFFFFFFFF # macro +TRAP5_COMMAND__Trap5Cmd0__SHIFT = 0x0 # macro +TRAP5_COMMAND__Trap5Cmd1__SHIFT = 0x8 # macro +TRAP5_COMMAND__Trap5Cmd0_MASK = 0x0000003F # macro +TRAP5_COMMAND__Trap5Cmd1_MASK = 0x00003F00 # macro +TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask__SHIFT = 0x2 # macro +TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask_MASK = 0xFFFFFFFC # macro +TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask__SHIFT = 0x0 # macro +TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask_MASK = 0xFFFFFFFF # macro +TRAP5_COMMAND_MASK__Trap5Cmd0Mask__SHIFT = 0x0 # macro +TRAP5_COMMAND_MASK__Trap5Cmd1Mask__SHIFT = 0x8 # macro +TRAP5_COMMAND_MASK__Trap5Cmd0Mask_MASK = 0x0000003F # macro +TRAP5_COMMAND_MASK__Trap5Cmd1Mask_MASK = 0x00003F00 # macro +TRAP6_CONTROL0__Trap6En__SHIFT = 0x0 # macro +TRAP6_CONTROL0__Trap6SMUIntr__SHIFT = 0x3 # macro +TRAP6_CONTROL0__Trap6Stage2Ptr__SHIFT = 0xe # macro +TRAP6_CONTROL0__Trap6CrossTrigger__SHIFT = 0x18 # macro +TRAP6_CONTROL0__Trap6Stage2En__SHIFT = 0x1f # macro +TRAP6_CONTROL0__Trap6En_MASK = 0x00000001 # macro +TRAP6_CONTROL0__Trap6SMUIntr_MASK = 0x00000008 # macro +TRAP6_CONTROL0__Trap6Stage2Ptr_MASK = 0x00FFC000 # macro +TRAP6_CONTROL0__Trap6CrossTrigger_MASK = 0x0F000000 # macro +TRAP6_CONTROL0__Trap6Stage2En_MASK = 0x80000000 # macro +TRAP6_ADDRESS_LO__Trap6AddrLo__SHIFT = 0x2 # macro +TRAP6_ADDRESS_LO__Trap6AddrLo_MASK = 0xFFFFFFFC # macro +TRAP6_ADDRESS_HI__Trap6AddrHi__SHIFT = 0x0 # macro +TRAP6_ADDRESS_HI__Trap6AddrHi_MASK = 0xFFFFFFFF # macro +TRAP6_COMMAND__Trap6Cmd0__SHIFT = 0x0 # macro +TRAP6_COMMAND__Trap6Cmd1__SHIFT = 0x8 # macro +TRAP6_COMMAND__Trap6Cmd0_MASK = 0x0000003F # macro +TRAP6_COMMAND__Trap6Cmd1_MASK = 0x00003F00 # macro +TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask__SHIFT = 0x2 # macro +TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask_MASK = 0xFFFFFFFC # macro +TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask__SHIFT = 0x0 # macro +TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask_MASK = 0xFFFFFFFF # macro +TRAP6_COMMAND_MASK__Trap6Cmd0Mask__SHIFT = 0x0 # macro +TRAP6_COMMAND_MASK__Trap6Cmd1Mask__SHIFT = 0x8 # macro +TRAP6_COMMAND_MASK__Trap6Cmd0Mask_MASK = 0x0000003F # macro +TRAP6_COMMAND_MASK__Trap6Cmd1Mask_MASK = 0x00003F00 # macro +TRAP7_CONTROL0__Trap7En__SHIFT = 0x0 # macro +TRAP7_CONTROL0__Trap7SMUIntr__SHIFT = 0x3 # macro +TRAP7_CONTROL0__Trap7Stage2Ptr__SHIFT = 0xe # macro +TRAP7_CONTROL0__Trap7CrossTrigger__SHIFT = 0x18 # macro +TRAP7_CONTROL0__Trap7Stage2En__SHIFT = 0x1f # macro +TRAP7_CONTROL0__Trap7En_MASK = 0x00000001 # macro +TRAP7_CONTROL0__Trap7SMUIntr_MASK = 0x00000008 # macro +TRAP7_CONTROL0__Trap7Stage2Ptr_MASK = 0x00FFC000 # macro +TRAP7_CONTROL0__Trap7CrossTrigger_MASK = 0x0F000000 # macro +TRAP7_CONTROL0__Trap7Stage2En_MASK = 0x80000000 # macro +TRAP7_ADDRESS_LO__Trap7AddrLo__SHIFT = 0x2 # macro +TRAP7_ADDRESS_LO__Trap7AddrLo_MASK = 0xFFFFFFFC # macro +TRAP7_ADDRESS_HI__Trap7AddrHi__SHIFT = 0x0 # macro +TRAP7_ADDRESS_HI__Trap7AddrHi_MASK = 0xFFFFFFFF # macro +TRAP7_COMMAND__Trap7Cmd0__SHIFT = 0x0 # macro +TRAP7_COMMAND__Trap7Cmd1__SHIFT = 0x8 # macro +TRAP7_COMMAND__Trap7Cmd0_MASK = 0x0000003F # macro +TRAP7_COMMAND__Trap7Cmd1_MASK = 0x00003F00 # macro +TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask__SHIFT = 0x2 # macro +TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask_MASK = 0xFFFFFFFC # macro +TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask__SHIFT = 0x0 # macro +TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask_MASK = 0xFFFFFFFF # macro +TRAP7_COMMAND_MASK__Trap7Cmd0Mask__SHIFT = 0x0 # macro +TRAP7_COMMAND_MASK__Trap7Cmd1Mask__SHIFT = 0x8 # macro +TRAP7_COMMAND_MASK__Trap7Cmd0Mask_MASK = 0x0000003F # macro +TRAP7_COMMAND_MASK__Trap7Cmd1Mask_MASK = 0x00003F00 # macro +TRAP8_CONTROL0__Trap8En__SHIFT = 0x0 # macro +TRAP8_CONTROL0__Trap8SMUIntr__SHIFT = 0x3 # macro +TRAP8_CONTROL0__Trap8Stage2Ptr__SHIFT = 0xe # macro +TRAP8_CONTROL0__Trap8CrossTrigger__SHIFT = 0x18 # macro +TRAP8_CONTROL0__Trap8Stage2En__SHIFT = 0x1f # macro +TRAP8_CONTROL0__Trap8En_MASK = 0x00000001 # macro +TRAP8_CONTROL0__Trap8SMUIntr_MASK = 0x00000008 # macro +TRAP8_CONTROL0__Trap8Stage2Ptr_MASK = 0x00FFC000 # macro +TRAP8_CONTROL0__Trap8CrossTrigger_MASK = 0x0F000000 # macro +TRAP8_CONTROL0__Trap8Stage2En_MASK = 0x80000000 # macro +TRAP8_ADDRESS_LO__Trap8AddrLo__SHIFT = 0x2 # macro +TRAP8_ADDRESS_LO__Trap8AddrLo_MASK = 0xFFFFFFFC # macro +TRAP8_ADDRESS_HI__Trap8AddrHi__SHIFT = 0x0 # macro +TRAP8_ADDRESS_HI__Trap8AddrHi_MASK = 0xFFFFFFFF # macro +TRAP8_COMMAND__Trap8Cmd0__SHIFT = 0x0 # macro +TRAP8_COMMAND__Trap8Cmd1__SHIFT = 0x8 # macro +TRAP8_COMMAND__Trap8Cmd0_MASK = 0x0000003F # macro +TRAP8_COMMAND__Trap8Cmd1_MASK = 0x00003F00 # macro +TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask__SHIFT = 0x2 # macro +TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask_MASK = 0xFFFFFFFC # macro +TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask__SHIFT = 0x0 # macro +TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask_MASK = 0xFFFFFFFF # macro +TRAP8_COMMAND_MASK__Trap8Cmd0Mask__SHIFT = 0x0 # macro +TRAP8_COMMAND_MASK__Trap8Cmd1Mask__SHIFT = 0x8 # macro +TRAP8_COMMAND_MASK__Trap8Cmd0Mask_MASK = 0x0000003F # macro +TRAP8_COMMAND_MASK__Trap8Cmd1Mask_MASK = 0x00003F00 # macro +TRAP9_CONTROL0__Trap9En__SHIFT = 0x0 # macro +TRAP9_CONTROL0__Trap9SMUIntr__SHIFT = 0x3 # macro +TRAP9_CONTROL0__Trap9Stage2Ptr__SHIFT = 0xe # macro +TRAP9_CONTROL0__Trap9CrossTrigger__SHIFT = 0x18 # macro +TRAP9_CONTROL0__Trap9Stage2En__SHIFT = 0x1f # macro +TRAP9_CONTROL0__Trap9En_MASK = 0x00000001 # macro +TRAP9_CONTROL0__Trap9SMUIntr_MASK = 0x00000008 # macro +TRAP9_CONTROL0__Trap9Stage2Ptr_MASK = 0x00FFC000 # macro +TRAP9_CONTROL0__Trap9CrossTrigger_MASK = 0x0F000000 # macro +TRAP9_CONTROL0__Trap9Stage2En_MASK = 0x80000000 # macro +TRAP9_ADDRESS_LO__Trap9AddrLo__SHIFT = 0x2 # macro +TRAP9_ADDRESS_LO__Trap9AddrLo_MASK = 0xFFFFFFFC # macro +TRAP9_ADDRESS_HI__Trap9AddrHi__SHIFT = 0x0 # macro +TRAP9_ADDRESS_HI__Trap9AddrHi_MASK = 0xFFFFFFFF # macro +TRAP9_COMMAND__Trap9Cmd0__SHIFT = 0x0 # macro +TRAP9_COMMAND__Trap9Cmd1__SHIFT = 0x8 # macro +TRAP9_COMMAND__Trap9Cmd0_MASK = 0x0000003F # macro +TRAP9_COMMAND__Trap9Cmd1_MASK = 0x00003F00 # macro +TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask__SHIFT = 0x2 # macro +TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask_MASK = 0xFFFFFFFC # macro +TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask__SHIFT = 0x0 # macro +TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask_MASK = 0xFFFFFFFF # macro +TRAP9_COMMAND_MASK__Trap9Cmd0Mask__SHIFT = 0x0 # macro +TRAP9_COMMAND_MASK__Trap9Cmd1Mask__SHIFT = 0x8 # macro +TRAP9_COMMAND_MASK__Trap9Cmd0Mask_MASK = 0x0000003F # macro +TRAP9_COMMAND_MASK__Trap9Cmd1Mask_MASK = 0x00003F00 # macro +TRAP10_CONTROL0__Trap10En__SHIFT = 0x0 # macro +TRAP10_CONTROL0__Trap10SMUIntr__SHIFT = 0x3 # macro +TRAP10_CONTROL0__Trap10Stage2Ptr__SHIFT = 0xe # macro +TRAP10_CONTROL0__Trap10CrossTrigger__SHIFT = 0x18 # macro +TRAP10_CONTROL0__Trap10Stage2En__SHIFT = 0x1f # macro +TRAP10_CONTROL0__Trap10En_MASK = 0x00000001 # macro +TRAP10_CONTROL0__Trap10SMUIntr_MASK = 0x00000008 # macro +TRAP10_CONTROL0__Trap10Stage2Ptr_MASK = 0x00FFC000 # macro +TRAP10_CONTROL0__Trap10CrossTrigger_MASK = 0x0F000000 # macro +TRAP10_CONTROL0__Trap10Stage2En_MASK = 0x80000000 # macro +TRAP10_ADDRESS_LO__Trap10AddrLo__SHIFT = 0x2 # macro +TRAP10_ADDRESS_LO__Trap10AddrLo_MASK = 0xFFFFFFFC # macro +TRAP10_ADDRESS_HI__Trap10AddrHi__SHIFT = 0x0 # macro +TRAP10_ADDRESS_HI__Trap10AddrHi_MASK = 0xFFFFFFFF # macro +TRAP10_COMMAND__Trap10Cmd0__SHIFT = 0x0 # macro +TRAP10_COMMAND__Trap10Cmd1__SHIFT = 0x8 # macro +TRAP10_COMMAND__Trap10Cmd0_MASK = 0x0000003F # macro +TRAP10_COMMAND__Trap10Cmd1_MASK = 0x00003F00 # macro +TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask__SHIFT = 0x2 # macro +TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask_MASK = 0xFFFFFFFC # macro +TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask__SHIFT = 0x0 # macro +TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask_MASK = 0xFFFFFFFF # macro +TRAP10_COMMAND_MASK__Trap10Cmd0Mask__SHIFT = 0x0 # macro +TRAP10_COMMAND_MASK__Trap10Cmd1Mask__SHIFT = 0x8 # macro +TRAP10_COMMAND_MASK__Trap10Cmd0Mask_MASK = 0x0000003F # macro +TRAP10_COMMAND_MASK__Trap10Cmd1Mask_MASK = 0x00003F00 # macro +TRAP11_CONTROL0__Trap11En__SHIFT = 0x0 # macro +TRAP11_CONTROL0__Trap11SMUIntr__SHIFT = 0x3 # macro +TRAP11_CONTROL0__Trap11Stage2Ptr__SHIFT = 0xe # macro +TRAP11_CONTROL0__Trap11CrossTrigger__SHIFT = 0x18 # macro +TRAP11_CONTROL0__Trap11Stage2En__SHIFT = 0x1f # macro +TRAP11_CONTROL0__Trap11En_MASK = 0x00000001 # macro +TRAP11_CONTROL0__Trap11SMUIntr_MASK = 0x00000008 # macro +TRAP11_CONTROL0__Trap11Stage2Ptr_MASK = 0x00FFC000 # macro +TRAP11_CONTROL0__Trap11CrossTrigger_MASK = 0x0F000000 # macro +TRAP11_CONTROL0__Trap11Stage2En_MASK = 0x80000000 # macro +TRAP11_ADDRESS_LO__Trap11AddrLo__SHIFT = 0x2 # macro +TRAP11_ADDRESS_LO__Trap11AddrLo_MASK = 0xFFFFFFFC # macro +TRAP11_ADDRESS_HI__Trap11AddrHi__SHIFT = 0x0 # macro +TRAP11_ADDRESS_HI__Trap11AddrHi_MASK = 0xFFFFFFFF # macro +TRAP11_COMMAND__Trap11Cmd0__SHIFT = 0x0 # macro +TRAP11_COMMAND__Trap11Cmd1__SHIFT = 0x8 # macro +TRAP11_COMMAND__Trap11Cmd0_MASK = 0x0000003F # macro +TRAP11_COMMAND__Trap11Cmd1_MASK = 0x00003F00 # macro +TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask__SHIFT = 0x2 # macro +TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask_MASK = 0xFFFFFFFC # macro +TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask__SHIFT = 0x0 # macro +TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask_MASK = 0xFFFFFFFF # macro +TRAP11_COMMAND_MASK__Trap11Cmd0Mask__SHIFT = 0x0 # macro +TRAP11_COMMAND_MASK__Trap11Cmd1Mask__SHIFT = 0x8 # macro +TRAP11_COMMAND_MASK__Trap11Cmd0Mask_MASK = 0x0000003F # macro +TRAP11_COMMAND_MASK__Trap11Cmd1Mask_MASK = 0x00003F00 # macro +TRAP12_CONTROL0__Trap12En__SHIFT = 0x0 # macro +TRAP12_CONTROL0__Trap12SMUIntr__SHIFT = 0x3 # macro +TRAP12_CONTROL0__Trap12Stage2Ptr__SHIFT = 0xe # macro +TRAP12_CONTROL0__Trap12CrossTrigger__SHIFT = 0x18 # macro +TRAP12_CONTROL0__Trap12Stage2En__SHIFT = 0x1f # macro +TRAP12_CONTROL0__Trap12En_MASK = 0x00000001 # macro +TRAP12_CONTROL0__Trap12SMUIntr_MASK = 0x00000008 # macro +TRAP12_CONTROL0__Trap12Stage2Ptr_MASK = 0x00FFC000 # macro +TRAP12_CONTROL0__Trap12CrossTrigger_MASK = 0x0F000000 # macro +TRAP12_CONTROL0__Trap12Stage2En_MASK = 0x80000000 # macro +TRAP12_ADDRESS_LO__Trap12AddrLo__SHIFT = 0x2 # macro +TRAP12_ADDRESS_LO__Trap12AddrLo_MASK = 0xFFFFFFFC # macro +TRAP12_ADDRESS_HI__Trap12AddrHi__SHIFT = 0x0 # macro +TRAP12_ADDRESS_HI__Trap12AddrHi_MASK = 0xFFFFFFFF # macro +TRAP12_COMMAND__Trap12Cmd0__SHIFT = 0x0 # macro +TRAP12_COMMAND__Trap12Cmd1__SHIFT = 0x8 # macro +TRAP12_COMMAND__Trap12Cmd0_MASK = 0x0000003F # macro +TRAP12_COMMAND__Trap12Cmd1_MASK = 0x00003F00 # macro +TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask__SHIFT = 0x2 # macro +TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask_MASK = 0xFFFFFFFC # macro +TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask__SHIFT = 0x0 # macro +TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask_MASK = 0xFFFFFFFF # macro +TRAP12_COMMAND_MASK__Trap12Cmd0Mask__SHIFT = 0x0 # macro +TRAP12_COMMAND_MASK__Trap12Cmd1Mask__SHIFT = 0x8 # macro +TRAP12_COMMAND_MASK__Trap12Cmd0Mask_MASK = 0x0000003F # macro +TRAP12_COMMAND_MASK__Trap12Cmd1Mask_MASK = 0x00003F00 # macro +TRAP13_CONTROL0__Trap13En__SHIFT = 0x0 # macro +TRAP13_CONTROL0__Trap13SMUIntr__SHIFT = 0x3 # macro +TRAP13_CONTROL0__Trap13Stage2Ptr__SHIFT = 0xe # macro +TRAP13_CONTROL0__Trap13CrossTrigger__SHIFT = 0x18 # macro +TRAP13_CONTROL0__Trap13Stage2En__SHIFT = 0x1f # macro +TRAP13_CONTROL0__Trap13En_MASK = 0x00000001 # macro +TRAP13_CONTROL0__Trap13SMUIntr_MASK = 0x00000008 # macro +TRAP13_CONTROL0__Trap13Stage2Ptr_MASK = 0x00FFC000 # macro +TRAP13_CONTROL0__Trap13CrossTrigger_MASK = 0x0F000000 # macro +TRAP13_CONTROL0__Trap13Stage2En_MASK = 0x80000000 # macro +TRAP13_ADDRESS_LO__Trap13AddrLo__SHIFT = 0x2 # macro +TRAP13_ADDRESS_LO__Trap13AddrLo_MASK = 0xFFFFFFFC # macro +TRAP13_ADDRESS_HI__Trap13AddrHi__SHIFT = 0x0 # macro +TRAP13_ADDRESS_HI__Trap13AddrHi_MASK = 0xFFFFFFFF # macro +TRAP13_COMMAND__Trap13Cmd0__SHIFT = 0x0 # macro +TRAP13_COMMAND__Trap13Cmd1__SHIFT = 0x8 # macro +TRAP13_COMMAND__Trap13Cmd0_MASK = 0x0000003F # macro +TRAP13_COMMAND__Trap13Cmd1_MASK = 0x00003F00 # macro +TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask__SHIFT = 0x2 # macro +TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask_MASK = 0xFFFFFFFC # macro +TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask__SHIFT = 0x0 # macro +TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask_MASK = 0xFFFFFFFF # macro +TRAP13_COMMAND_MASK__Trap13Cmd0Mask__SHIFT = 0x0 # macro +TRAP13_COMMAND_MASK__Trap13Cmd1Mask__SHIFT = 0x8 # macro +TRAP13_COMMAND_MASK__Trap13Cmd0Mask_MASK = 0x0000003F # macro +TRAP13_COMMAND_MASK__Trap13Cmd1Mask_MASK = 0x00003F00 # macro +TRAP14_CONTROL0__Trap14En__SHIFT = 0x0 # macro +TRAP14_CONTROL0__Trap14SMUIntr__SHIFT = 0x3 # macro +TRAP14_CONTROL0__Trap14Stage2Ptr__SHIFT = 0xe # macro +TRAP14_CONTROL0__Trap14CrossTrigger__SHIFT = 0x18 # macro +TRAP14_CONTROL0__Trap14Stage2En__SHIFT = 0x1f # macro +TRAP14_CONTROL0__Trap14En_MASK = 0x00000001 # macro +TRAP14_CONTROL0__Trap14SMUIntr_MASK = 0x00000008 # macro +TRAP14_CONTROL0__Trap14Stage2Ptr_MASK = 0x00FFC000 # macro +TRAP14_CONTROL0__Trap14CrossTrigger_MASK = 0x0F000000 # macro +TRAP14_CONTROL0__Trap14Stage2En_MASK = 0x80000000 # macro +TRAP14_ADDRESS_LO__Trap14AddrLo__SHIFT = 0x2 # macro +TRAP14_ADDRESS_LO__Trap14AddrLo_MASK = 0xFFFFFFFC # macro +TRAP14_ADDRESS_HI__Trap14AddrHi__SHIFT = 0x0 # macro +TRAP14_ADDRESS_HI__Trap14AddrHi_MASK = 0xFFFFFFFF # macro +TRAP14_COMMAND__Trap14Cmd0__SHIFT = 0x0 # macro +TRAP14_COMMAND__Trap14Cmd1__SHIFT = 0x8 # macro +TRAP14_COMMAND__Trap14Cmd0_MASK = 0x0000003F # macro +TRAP14_COMMAND__Trap14Cmd1_MASK = 0x00003F00 # macro +TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask__SHIFT = 0x2 # macro +TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask_MASK = 0xFFFFFFFC # macro +TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask__SHIFT = 0x0 # macro +TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask_MASK = 0xFFFFFFFF # macro +TRAP14_COMMAND_MASK__Trap14Cmd0Mask__SHIFT = 0x0 # macro +TRAP14_COMMAND_MASK__Trap14Cmd1Mask__SHIFT = 0x8 # macro +TRAP14_COMMAND_MASK__Trap14Cmd0Mask_MASK = 0x0000003F # macro +TRAP14_COMMAND_MASK__Trap14Cmd1Mask_MASK = 0x00003F00 # macro +TRAP15_CONTROL0__Trap15En__SHIFT = 0x0 # macro +TRAP15_CONTROL0__Trap15SMUIntr__SHIFT = 0x3 # macro +TRAP15_CONTROL0__Trap15Stage2Ptr__SHIFT = 0xe # macro +TRAP15_CONTROL0__Trap15CrossTrigger__SHIFT = 0x18 # macro +TRAP15_CONTROL0__Trap15Stage2En__SHIFT = 0x1f # macro +TRAP15_CONTROL0__Trap15En_MASK = 0x00000001 # macro +TRAP15_CONTROL0__Trap15SMUIntr_MASK = 0x00000008 # macro +TRAP15_CONTROL0__Trap15Stage2Ptr_MASK = 0x00FFC000 # macro +TRAP15_CONTROL0__Trap15CrossTrigger_MASK = 0x0F000000 # macro +TRAP15_CONTROL0__Trap15Stage2En_MASK = 0x80000000 # macro +TRAP15_ADDRESS_LO__Trap15AddrLo__SHIFT = 0x2 # macro +TRAP15_ADDRESS_LO__Trap15AddrLo_MASK = 0xFFFFFFFC # macro +TRAP15_ADDRESS_HI__Trap15AddrHi__SHIFT = 0x0 # macro +TRAP15_ADDRESS_HI__Trap15AddrHi_MASK = 0xFFFFFFFF # macro +TRAP15_COMMAND__Trap15Cmd0__SHIFT = 0x0 # macro +TRAP15_COMMAND__Trap15Cmd1__SHIFT = 0x8 # macro +TRAP15_COMMAND__Trap15Cmd0_MASK = 0x0000003F # macro +TRAP15_COMMAND__Trap15Cmd1_MASK = 0x00003F00 # macro +TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask__SHIFT = 0x2 # macro +TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask_MASK = 0xFFFFFFFC # macro +TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask__SHIFT = 0x0 # macro +TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask_MASK = 0xFFFFFFFF # macro +TRAP15_COMMAND_MASK__Trap15Cmd0Mask__SHIFT = 0x0 # macro +TRAP15_COMMAND_MASK__Trap15Cmd1Mask__SHIFT = 0x8 # macro +TRAP15_COMMAND_MASK__Trap15Cmd0Mask_MASK = 0x0000003F # macro +TRAP15_COMMAND_MASK__Trap15Cmd1Mask_MASK = 0x00003F00 # macro +SB_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +SB_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +SB_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +SB_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +SB_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +SB_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT = 0x8 # macro +SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT = 0x10 # macro +SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK = 0x0000FF00 # macro +SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK = 0x00FF0000 # macro +SB_IO_BASE_LIMIT__IO_BASE__SHIFT = 0x4 # macro +SB_IO_BASE_LIMIT__IO_LIMIT__SHIFT = 0xc # macro +SB_IO_BASE_LIMIT__IO_BASE_MASK = 0x00F0 # macro +SB_IO_BASE_LIMIT__IO_LIMIT_MASK = 0xF000 # macro +SB_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT = 0x4 # macro +SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT = 0x14 # macro +SB_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK = 0x0000FFF0 # macro +SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK = 0xFFF00000 # macro +SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT = 0x4 # macro +SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT = 0x14 # macro +SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK = 0x0000FFF0 # macro +SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK = 0xFFF00000 # macro +SB_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT = 0x0 # macro +SB_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK = 0xFFFFFFFF # macro +SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT = 0x0 # macro +SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK = 0xFFFFFFFF # macro +SB_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT = 0x0 # macro +SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT = 0x10 # macro +SB_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK = 0x0000FFFF # macro +SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK = 0xFFFF0000 # macro +SB_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT = 0x2 # macro +SB_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT = 0x3 # macro +SB_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT = 0x4 # macro +SB_IRQ_BRIDGE_CNTL__ISA_EN_MASK = 0x0004 # macro +SB_IRQ_BRIDGE_CNTL__VGA_EN_MASK = 0x0008 # macro +SB_IRQ_BRIDGE_CNTL__VGA_DEC_MASK = 0x0010 # macro +SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT = 0x0 # macro +SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK = 0x01 # macro +SB_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +SB_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x03 # macro +SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT = 0x7 # macro +SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT = 0xf # macro +SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK = 0x00007F80 # macro +SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK = 0x00018000 # macro +SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT = 0x4 # macro +SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK = 0x0010 # macro +SB_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +SB_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +MCA_SMN_INT_REQ_ADDR__SMN_INT_REQ_ADDR__SHIFT = 0x0 # macro +MCA_SMN_INT_REQ_ADDR__SMN_INT_REQ_ADDR_MASK = 0x000FFFFF # macro +MCA_SMN_INT_MCM_ADDR__SMN_INT_MCM_ADDR__SHIFT = 0x0 # macro +MCA_SMN_INT_MCM_ADDR__SMN_INT_MCM_ADDR_MASK = 0x000000FF # macro +MCA_SMN_INT_APERTUREID__SMN_INT_APERTUREID__SHIFT = 0x0 # macro +MCA_SMN_INT_APERTUREID__SMN_INT_APERTUREID_MASK = 0x00000FFF # macro +MCA_SMN_INT_CONTROL__MCACrossTrigger__SHIFT = 0x0 # macro +MCA_SMN_INT_CONTROL__MCACrossTrigger_MASK = 0x0000000F # macro +PARITY_CONTROL_0__ParityCorrThreshold__SHIFT = 0x0 # macro +PARITY_CONTROL_0__ParityUCPThreshold__SHIFT = 0x10 # macro +PARITY_CONTROL_0__ParityCorrThreshold_MASK = 0x0000FFFF # macro +PARITY_CONTROL_0__ParityUCPThreshold_MASK = 0xFFFF0000 # macro +PARITY_CONTROL_1__ParityErrGenGroupSel__SHIFT = 0x0 # macro +PARITY_CONTROL_1__ParityErrGenGroupTypeSel__SHIFT = 0x8 # macro +PARITY_CONTROL_1__ParityErrGenIdSel__SHIFT = 0xb # macro +PARITY_CONTROL_1__ParityErrGenCmd__SHIFT = 0x10 # macro +PARITY_CONTROL_1__ParityErrGenTrigger__SHIFT = 0x1e # macro +PARITY_CONTROL_1__ParityErrGenInjectAllow__SHIFT = 0x1f # macro +PARITY_CONTROL_1__ParityErrGenGroupSel_MASK = 0x000000FF # macro +PARITY_CONTROL_1__ParityErrGenGroupTypeSel_MASK = 0x00000100 # macro +PARITY_CONTROL_1__ParityErrGenIdSel_MASK = 0x0000F800 # macro +PARITY_CONTROL_1__ParityErrGenCmd_MASK = 0x000F0000 # macro +PARITY_CONTROL_1__ParityErrGenTrigger_MASK = 0x40000000 # macro +PARITY_CONTROL_1__ParityErrGenInjectAllow_MASK = 0x80000000 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0__SHIFT = 0x0 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1__SHIFT = 0x2 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2__SHIFT = 0x4 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3__SHIFT = 0x6 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4__SHIFT = 0x8 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp5__SHIFT = 0xa # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp6__SHIFT = 0xc # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp7__SHIFT = 0xe # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp8__SHIFT = 0x10 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp9__SHIFT = 0x12 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp10__SHIFT = 0x14 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp11__SHIFT = 0x16 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp12__SHIFT = 0x18 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp13__SHIFT = 0x1a # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp14__SHIFT = 0x1c # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp15__SHIFT = 0x1e # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0_MASK = 0x00000003 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1_MASK = 0x0000000C # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2_MASK = 0x00000030 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3_MASK = 0x000000C0 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4_MASK = 0x00000300 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp5_MASK = 0x00000C00 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp6_MASK = 0x00003000 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp7_MASK = 0x0000C000 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp8_MASK = 0x00030000 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp9_MASK = 0x000C0000 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp10_MASK = 0x00300000 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp11_MASK = 0x00C00000 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp12_MASK = 0x03000000 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp13_MASK = 0x0C000000 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp14_MASK = 0x30000000 # macro +PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp15_MASK = 0xC0000000 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0__SHIFT = 0x0 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1__SHIFT = 0x2 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2__SHIFT = 0x4 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3__SHIFT = 0x6 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4__SHIFT = 0x8 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp5__SHIFT = 0xa # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp6__SHIFT = 0xc # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp7__SHIFT = 0xe # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp8__SHIFT = 0x10 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp9__SHIFT = 0x12 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp10__SHIFT = 0x14 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp11__SHIFT = 0x16 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp12__SHIFT = 0x18 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp13__SHIFT = 0x1a # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp14__SHIFT = 0x1c # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp15__SHIFT = 0x1e # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0_MASK = 0x00000003 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1_MASK = 0x0000000C # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2_MASK = 0x00000030 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3_MASK = 0x000000C0 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4_MASK = 0x00000300 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp5_MASK = 0x00000C00 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp6_MASK = 0x00003000 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp7_MASK = 0x0000C000 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp8_MASK = 0x00030000 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp9_MASK = 0x000C0000 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp10_MASK = 0x00300000 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp11_MASK = 0x00C00000 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp12_MASK = 0x03000000 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp13_MASK = 0x0C000000 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp14_MASK = 0x30000000 # macro +PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp15_MASK = 0xC0000000 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0__SHIFT = 0x0 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1__SHIFT = 0x2 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2__SHIFT = 0x4 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3__SHIFT = 0x6 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4__SHIFT = 0x8 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp5__SHIFT = 0xa # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp6__SHIFT = 0xc # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp7__SHIFT = 0xe # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp8__SHIFT = 0x10 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp9__SHIFT = 0x12 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp10__SHIFT = 0x14 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp11__SHIFT = 0x16 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp12__SHIFT = 0x18 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0_MASK = 0x00000003 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1_MASK = 0x0000000C # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2_MASK = 0x00000030 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3_MASK = 0x000000C0 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4_MASK = 0x00000300 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp5_MASK = 0x00000C00 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp6_MASK = 0x00003000 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp7_MASK = 0x0000C000 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp8_MASK = 0x00030000 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp9_MASK = 0x000C0000 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp10_MASK = 0x00300000 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp11_MASK = 0x00C00000 # macro +PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp12_MASK = 0x03000000 # macro +RAS_GLOBAL_STATUS_LO__ParityErrCorr__SHIFT = 0x0 # macro +RAS_GLOBAL_STATUS_LO__ParityErrNonFatal__SHIFT = 0x1 # macro +RAS_GLOBAL_STATUS_LO__ParityErrFatal__SHIFT = 0x2 # macro +RAS_GLOBAL_STATUS_LO__ParityErrSerr__SHIFT = 0x3 # macro +RAS_GLOBAL_STATUS_LO__HPLGWA_NMI__SHIFT = 0x6 # macro +RAS_GLOBAL_STATUS_LO__HPLGWA_SCI__SHIFT = 0x7 # macro +RAS_GLOBAL_STATUS_LO__HPLGWA_SMI__SHIFT = 0x8 # macro +RAS_GLOBAL_STATUS_LO__SW_SMI__SHIFT = 0x9 # macro +RAS_GLOBAL_STATUS_LO__SW_SCI__SHIFT = 0xa # macro +RAS_GLOBAL_STATUS_LO__SW_NMI__SHIFT = 0xb # macro +RAS_GLOBAL_STATUS_LO__APML_NMI__SHIFT = 0xc # macro +RAS_GLOBAL_STATUS_LO__APML_SyncFld__SHIFT = 0xd # macro +RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI__SHIFT = 0xe # macro +RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private__SHIFT = 0xf # macro +RAS_GLOBAL_STATUS_LO__ParityErrCorr_MASK = 0x00000001 # macro +RAS_GLOBAL_STATUS_LO__ParityErrNonFatal_MASK = 0x00000002 # macro +RAS_GLOBAL_STATUS_LO__ParityErrFatal_MASK = 0x00000004 # macro +RAS_GLOBAL_STATUS_LO__ParityErrSerr_MASK = 0x00000008 # macro +RAS_GLOBAL_STATUS_LO__HPLGWA_NMI_MASK = 0x00000040 # macro +RAS_GLOBAL_STATUS_LO__HPLGWA_SCI_MASK = 0x00000080 # macro +RAS_GLOBAL_STATUS_LO__HPLGWA_SMI_MASK = 0x00000100 # macro +RAS_GLOBAL_STATUS_LO__SW_SMI_MASK = 0x00000200 # macro +RAS_GLOBAL_STATUS_LO__SW_SCI_MASK = 0x00000400 # macro +RAS_GLOBAL_STATUS_LO__SW_NMI_MASK = 0x00000800 # macro +RAS_GLOBAL_STATUS_LO__APML_NMI_MASK = 0x00001000 # macro +RAS_GLOBAL_STATUS_LO__APML_SyncFld_MASK = 0x00002000 # macro +RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI_MASK = 0x00004000 # macro +RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private_MASK = 0x00008000 # macro +RAS_GLOBAL_STATUS_HI__PCIE0PortAErr__SHIFT = 0x0 # macro +RAS_GLOBAL_STATUS_HI__PCIE0PortBErr__SHIFT = 0x1 # macro +RAS_GLOBAL_STATUS_HI__PCIE0PortCErr__SHIFT = 0x2 # macro +RAS_GLOBAL_STATUS_HI__PCIE0PortDErr__SHIFT = 0x3 # macro +RAS_GLOBAL_STATUS_HI__PCIE0PortEErr__SHIFT = 0x4 # macro +RAS_GLOBAL_STATUS_HI__PCIE0PortFErr__SHIFT = 0x5 # macro +RAS_GLOBAL_STATUS_HI__PCIE0PortGErr__SHIFT = 0x6 # macro +RAS_GLOBAL_STATUS_HI__PCIE0PortHErr__SHIFT = 0x7 # macro +RAS_GLOBAL_STATUS_HI__PCIE0PortIErr__SHIFT = 0x8 # macro +RAS_GLOBAL_STATUS_HI__PCIE1PortAErr__SHIFT = 0x9 # macro +RAS_GLOBAL_STATUS_HI__PCIE1PortBErr__SHIFT = 0xa # macro +RAS_GLOBAL_STATUS_HI__PCIE1PortCErr__SHIFT = 0xb # macro +RAS_GLOBAL_STATUS_HI__PCIE1PortDErr__SHIFT = 0xc # macro +RAS_GLOBAL_STATUS_HI__NBIF1PortAErr__SHIFT = 0xd # macro +RAS_GLOBAL_STATUS_HI__PCIE0PortAErr_MASK = 0x00000001 # macro +RAS_GLOBAL_STATUS_HI__PCIE0PortBErr_MASK = 0x00000002 # macro +RAS_GLOBAL_STATUS_HI__PCIE0PortCErr_MASK = 0x00000004 # macro +RAS_GLOBAL_STATUS_HI__PCIE0PortDErr_MASK = 0x00000008 # macro +RAS_GLOBAL_STATUS_HI__PCIE0PortEErr_MASK = 0x00000010 # macro +RAS_GLOBAL_STATUS_HI__PCIE0PortFErr_MASK = 0x00000020 # macro +RAS_GLOBAL_STATUS_HI__PCIE0PortGErr_MASK = 0x00000040 # macro +RAS_GLOBAL_STATUS_HI__PCIE0PortHErr_MASK = 0x00000080 # macro +RAS_GLOBAL_STATUS_HI__PCIE0PortIErr_MASK = 0x00000100 # macro +RAS_GLOBAL_STATUS_HI__PCIE1PortAErr_MASK = 0x00000200 # macro +RAS_GLOBAL_STATUS_HI__PCIE1PortBErr_MASK = 0x00000400 # macro +RAS_GLOBAL_STATUS_HI__PCIE1PortCErr_MASK = 0x00000800 # macro +RAS_GLOBAL_STATUS_HI__PCIE1PortDErr_MASK = 0x00001000 # macro +RAS_GLOBAL_STATUS_HI__NBIF1PortAErr_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_COUNTER_CORR_GRP0__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_CORR_GRP0__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_CORR_GRP0__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_CORR_GRP0__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_CORR_GRP1__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_CORR_GRP1__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_CORR_GRP1__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_CORR_GRP1__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_CORR_GRP2__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_CORR_GRP2__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_CORR_GRP2__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_CORR_GRP2__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_CORR_GRP3__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_CORR_GRP3__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_CORR_GRP3__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_CORR_GRP3__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_CORR_GRP4__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_CORR_GRP4__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_CORR_GRP4__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_CORR_GRP4__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_CORR_GRP5__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_CORR_GRP5__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_CORR_GRP5__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_CORR_GRP5__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_CORR_GRP6__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_CORR_GRP6__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_CORR_GRP6__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_CORR_GRP6__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_CORR_GRP7__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_CORR_GRP7__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_CORR_GRP7__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_CORR_GRP7__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_CORR_GRP10__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_CORR_GRP10__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_CORR_GRP10__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_CORR_GRP10__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_CORR_GRP11__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_CORR_GRP11__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_CORR_GRP11__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_CORR_GRP11__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_CORR_GRP12__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_CORR_GRP12__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_CORR_GRP12__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_CORR_GRP12__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_CORR_GRP13__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_CORR_GRP13__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_CORR_GRP13__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_CORR_GRP13__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_CORR_GRP14__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_CORR_GRP14__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_CORR_GRP14__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_CORR_GRP14__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_CORR_GRP15__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_CORR_GRP15__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_CORR_GRP15__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_CORR_GRP15__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_CORR_GRP16__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_CORR_GRP16__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_CORR_GRP16__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_CORR_GRP16__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_CORR_GRP17__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_CORR_GRP17__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_CORR_GRP17__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_CORR_GRP17__ResetEn_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id0__SHIFT = 0x0 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id1__SHIFT = 0x1 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id2__SHIFT = 0x2 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id3__SHIFT = 0x3 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id4__SHIFT = 0x4 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id5__SHIFT = 0x5 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id6__SHIFT = 0x6 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id7__SHIFT = 0x7 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id8__SHIFT = 0x8 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id9__SHIFT = 0x9 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id10__SHIFT = 0xa # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id11__SHIFT = 0xb # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id12__SHIFT = 0xc # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id13__SHIFT = 0xd # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id14__SHIFT = 0xe # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id15__SHIFT = 0xf # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id16__SHIFT = 0x10 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id17__SHIFT = 0x11 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id18__SHIFT = 0x12 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id19__SHIFT = 0x13 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id20__SHIFT = 0x14 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id21__SHIFT = 0x15 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id22__SHIFT = 0x16 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id23__SHIFT = 0x17 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id24__SHIFT = 0x18 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id25__SHIFT = 0x19 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id26__SHIFT = 0x1a # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id27__SHIFT = 0x1b # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id28__SHIFT = 0x1c # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id29__SHIFT = 0x1d # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id30__SHIFT = 0x1e # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id31__SHIFT = 0x1f # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id0_MASK = 0x00000001 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id1_MASK = 0x00000002 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id2_MASK = 0x00000004 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id3_MASK = 0x00000008 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id4_MASK = 0x00000010 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id5_MASK = 0x00000020 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id6_MASK = 0x00000040 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id7_MASK = 0x00000080 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id8_MASK = 0x00000100 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id9_MASK = 0x00000200 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id10_MASK = 0x00000400 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id11_MASK = 0x00000800 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id12_MASK = 0x00001000 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id13_MASK = 0x00002000 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id14_MASK = 0x00004000 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id15_MASK = 0x00008000 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id16_MASK = 0x00010000 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id17_MASK = 0x00020000 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id18_MASK = 0x00040000 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id19_MASK = 0x00080000 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id20_MASK = 0x00100000 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id21_MASK = 0x00200000 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id22_MASK = 0x00400000 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id23_MASK = 0x00800000 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id24_MASK = 0x01000000 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id25_MASK = 0x02000000 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id26_MASK = 0x04000000 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id27_MASK = 0x08000000 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id28_MASK = 0x10000000 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id29_MASK = 0x20000000 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id30_MASK = 0x40000000 # macro +PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id31_MASK = 0x80000000 # macro +PARITY_COUNTER_UCP_GRP0__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_UCP_GRP0__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_UCP_GRP0__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_UCP_GRP0__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_UCP_GRP1__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_UCP_GRP1__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_UCP_GRP1__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_UCP_GRP1__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_UCP_GRP2__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_UCP_GRP2__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_UCP_GRP2__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_UCP_GRP2__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_UCP_GRP3__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_UCP_GRP3__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_UCP_GRP3__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_UCP_GRP3__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_UCP_GRP4__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_UCP_GRP4__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_UCP_GRP4__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_UCP_GRP4__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_UCP_GRP5__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_UCP_GRP5__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_UCP_GRP5__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_UCP_GRP5__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_UCP_GRP6__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_UCP_GRP6__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_UCP_GRP6__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_UCP_GRP6__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_UCP_GRP7__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_UCP_GRP7__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_UCP_GRP7__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_UCP_GRP7__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_UCP_GRP10__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_UCP_GRP10__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_UCP_GRP10__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_UCP_GRP10__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_UCP_GRP11__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_UCP_GRP11__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_UCP_GRP11__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_UCP_GRP11__ResetEn_MASK = 0x80000000 # macro +PARITY_COUNTER_UCP_GRP12__ThresholdCounter__SHIFT = 0x0 # macro +PARITY_COUNTER_UCP_GRP12__ResetEn__SHIFT = 0x1f # macro +PARITY_COUNTER_UCP_GRP12__ThresholdCounter_MASK = 0x0000FFFF # macro +PARITY_COUNTER_UCP_GRP12__ResetEn_MASK = 0x80000000 # macro +MISC_SEVERITY_CONTROL__ErrEventErrSev__SHIFT = 0x4 # macro +MISC_SEVERITY_CONTROL__PcieParityErrSev__SHIFT = 0x6 # macro +MISC_SEVERITY_CONTROL__ErrEventErrSev_MASK = 0x00000030 # macro +MISC_SEVERITY_CONTROL__PcieParityErrSev_MASK = 0x000000C0 # macro +MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En__SHIFT = 0x2 # macro +MISC_RAS_CONTROL__GNB_SB_LinkNeverDis__SHIFT = 0x3 # macro +MISC_RAS_CONTROL__InterruptOutputDis__SHIFT = 0x9 # macro +MISC_RAS_CONTROL__LinkDisOutputDis__SHIFT = 0xa # macro +MISC_RAS_CONTROL__SyncFldOutputDis__SHIFT = 0xb # macro +MISC_RAS_CONTROL__PCIe_NMI_En__SHIFT = 0xc # macro +MISC_RAS_CONTROL__PCIe_SCI_En__SHIFT = 0xd # macro +MISC_RAS_CONTROL__PCIe_SMI_En__SHIFT = 0xe # macro +MISC_RAS_CONTROL__SW_SCI_En__SHIFT = 0xf # macro +MISC_RAS_CONTROL__SW_SMI_En__SHIFT = 0x10 # macro +MISC_RAS_CONTROL__SW_NMI_En__SHIFT = 0x11 # macro +MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En_MASK = 0x00000004 # macro +MISC_RAS_CONTROL__GNB_SB_LinkNeverDis_MASK = 0x00000008 # macro +MISC_RAS_CONTROL__InterruptOutputDis_MASK = 0x00000200 # macro +MISC_RAS_CONTROL__LinkDisOutputDis_MASK = 0x00000400 # macro +MISC_RAS_CONTROL__SyncFldOutputDis_MASK = 0x00000800 # macro +MISC_RAS_CONTROL__PCIe_NMI_En_MASK = 0x00001000 # macro +MISC_RAS_CONTROL__PCIe_SCI_En_MASK = 0x00002000 # macro +MISC_RAS_CONTROL__PCIe_SMI_En_MASK = 0x00004000 # macro +MISC_RAS_CONTROL__SW_SCI_En_MASK = 0x00008000 # macro +MISC_RAS_CONTROL__SW_SMI_En_MASK = 0x00010000 # macro +MISC_RAS_CONTROL__SW_NMI_En_MASK = 0x00020000 # macro +RAS_SCRATCH_0__SCRATCH_0__SHIFT = 0x0 # macro +RAS_SCRATCH_0__SCRATCH_0_MASK = 0xFFFFFFFF # macro +RAS_SCRATCH_1__SCRATCH_1__SHIFT = 0x0 # macro +RAS_SCRATCH_1__SCRATCH_1_MASK = 0xFFFFFFFF # macro +ErrEvent_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +ErrEvent_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +ErrEvent_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +ErrEvent_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +ErrEvent_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +ErrEvent_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +ErrEvent_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +ErrEvent_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +ParitySerr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +ParitySerr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +ParitySerr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +ParitySerr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +ParitySerr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +ParitySerr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +ParitySerr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +ParitySerr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +ParityFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +ParityFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +ParityFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +ParityFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +ParityFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +ParityFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +ParityFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +ParityFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +ParityNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +ParityNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +ParityNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +ParityNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +ParityNonFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +ParityNonFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +ParityNonFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +ParityNonFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +ParityCorr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +ParityCorr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +ParityCorr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +ParityCorr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +ParityCorr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +ParityCorr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +ParityCorr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +ParityCorr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortASerr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortASerr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortASerr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortASerr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortASerr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortASerr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortASerr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortASerr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortAIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortAIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortAIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortAIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortAIntFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortAIntFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortAIntFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortAIntFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortAIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortAIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortAIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortAIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortAIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortAIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortAIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortAIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortAIntCorr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortAIntCorr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortAIntCorr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortAIntCorr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortAExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortAExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortAExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortAExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortAExtFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortAExtFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortAExtFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortAExtFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortAExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortAExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortAExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortAExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortAExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortAExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortAExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortAExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortAExtCorr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortAExtCorr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortAExtCorr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortAExtCorr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortAParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortAParityErr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortAParityErr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortAParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortAParityErr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortAParityErr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortAParityErr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortAParityErr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortBSerr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortBSerr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortBSerr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortBSerr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortBSerr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortBSerr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortBSerr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortBSerr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortBIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortBIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortBIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortBIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortBIntFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortBIntFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortBIntFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortBIntFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortBIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortBIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortBIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortBIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortBIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortBIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortBIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortBIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortBIntCorr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortBIntCorr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortBIntCorr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortBIntCorr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortBExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortBExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortBExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortBExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortBExtFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortBExtFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortBExtFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortBExtFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortBExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortBExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortBExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortBExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortBExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortBExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortBExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortBExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortBExtCorr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortBExtCorr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortBExtCorr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortBExtCorr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortBParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortBParityErr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortBParityErr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortBParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortBParityErr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortBParityErr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortBParityErr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortBParityErr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortCSerr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortCSerr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortCSerr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortCSerr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortCSerr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortCSerr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortCSerr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortCSerr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortCIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortCIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortCIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortCIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortCIntFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortCIntFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortCIntFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortCIntFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortCIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortCIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortCIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortCIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortCIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortCIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortCIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortCIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortCIntCorr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortCIntCorr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortCIntCorr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortCIntCorr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortCExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortCExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortCExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortCExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortCExtFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortCExtFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortCExtFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortCExtFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortCExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortCExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortCExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortCExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortCExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortCExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortCExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortCExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortCExtCorr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortCExtCorr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortCExtCorr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortCExtCorr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortCParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortCParityErr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortCParityErr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortCParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortCParityErr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortCParityErr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortCParityErr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortCParityErr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortDSerr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortDSerr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortDSerr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortDSerr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortDSerr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortDSerr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortDSerr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortDSerr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortDIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortDIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortDIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortDIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortDIntFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortDIntFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortDIntFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortDIntFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortDIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortDIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortDIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortDIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortDIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortDIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortDIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortDIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortDIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortDIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortDIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortDIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortDIntCorr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortDIntCorr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortDIntCorr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortDIntCorr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortDExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortDExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortDExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortDExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortDExtFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortDExtFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortDExtFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortDExtFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortDExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortDExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortDExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortDExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortDExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortDExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortDExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortDExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortDExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortDExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortDExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortDExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortDExtCorr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortDExtCorr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortDExtCorr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortDExtCorr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortDParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortDParityErr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortDParityErr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortDParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortDParityErr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortDParityErr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortDParityErr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortDParityErr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortESerr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortESerr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortESerr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortESerr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortESerr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortESerr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortESerr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortESerr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortEIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortEIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortEIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortEIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortEIntFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortEIntFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortEIntFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortEIntFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortEIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortEIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortEIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortEIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortEIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortEIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortEIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortEIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortEIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortEIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortEIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortEIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortEIntCorr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortEIntCorr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortEIntCorr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortEIntCorr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortEExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortEExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortEExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortEExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortEExtFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortEExtFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortEExtFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortEExtFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortEExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortEExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortEExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortEExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortEExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortEExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortEExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortEExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortEExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortEExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortEExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortEExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortEExtCorr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortEExtCorr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortEExtCorr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortEExtCorr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortEParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortEParityErr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortEParityErr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortEParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortEParityErr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortEParityErr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortEParityErr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortEParityErr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortFSerr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortFSerr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortFSerr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortFSerr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortFSerr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortFSerr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortFSerr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortFSerr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortFIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortFIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortFIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortFIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortFIntFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortFIntFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortFIntFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortFIntFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortFIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortFIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortFIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortFIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortFIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortFIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortFIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortFIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortFIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortFIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortFIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortFIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortFIntCorr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortFIntCorr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortFIntCorr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortFIntCorr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortFExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortFExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortFExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortFExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortFExtFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortFExtFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortFExtFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortFExtFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortFExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortFExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortFExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortFExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortFExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortFExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortFExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortFExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortFExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortFExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortFExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortFExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortFExtCorr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortFExtCorr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortFExtCorr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortFExtCorr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortFParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortFParityErr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortFParityErr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortFParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortFParityErr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortFParityErr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortFParityErr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortFParityErr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortGSerr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortGSerr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortGSerr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortGSerr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortGSerr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortGSerr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortGSerr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortGSerr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortGIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortGIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortGIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortGIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortGIntFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortGIntFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortGIntFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortGIntFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortGIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortGIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortGIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortGIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortGIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortGIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortGIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortGIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortGIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortGIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortGIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortGIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortGIntCorr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortGIntCorr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortGIntCorr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortGIntCorr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortGExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortGExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortGExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortGExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortGExtFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortGExtFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortGExtFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortGExtFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortGExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortGExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortGExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortGExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortGExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortGExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortGExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortGExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortGExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortGExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortGExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortGExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortGExtCorr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortGExtCorr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortGExtCorr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortGExtCorr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +PCIE0PortGParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +PCIE0PortGParityErr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +PCIE0PortGParityErr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +PCIE0PortGParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +PCIE0PortGParityErr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +PCIE0PortGParityErr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +PCIE0PortGParityErr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +PCIE0PortGParityErr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +NBIF1PortASerr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +NBIF1PortASerr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +NBIF1PortASerr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +NBIF1PortASerr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +NBIF1PortASerr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +NBIF1PortASerr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +NBIF1PortASerr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +NBIF1PortASerr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +NBIF1PortAIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +NBIF1PortAIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +NBIF1PortAIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +NBIF1PortAIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +NBIF1PortAIntFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +NBIF1PortAIntFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +NBIF1PortAIntFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +NBIF1PortAIntFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +NBIF1PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +NBIF1PortAIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +NBIF1PortAIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +NBIF1PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +NBIF1PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +NBIF1PortAIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +NBIF1PortAIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +NBIF1PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +NBIF1PortAIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +NBIF1PortAIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +NBIF1PortAIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +NBIF1PortAIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +NBIF1PortAIntCorr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +NBIF1PortAIntCorr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +NBIF1PortAIntCorr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +NBIF1PortAIntCorr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +NBIF1PortAExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +NBIF1PortAExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +NBIF1PortAExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +NBIF1PortAExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +NBIF1PortAExtFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +NBIF1PortAExtFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +NBIF1PortAExtFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +NBIF1PortAExtFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +NBIF1PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +NBIF1PortAExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +NBIF1PortAExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +NBIF1PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +NBIF1PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +NBIF1PortAExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +NBIF1PortAExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +NBIF1PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +NBIF1PortAExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +NBIF1PortAExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +NBIF1PortAExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +NBIF1PortAExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +NBIF1PortAExtCorr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +NBIF1PortAExtCorr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +NBIF1PortAExtCorr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +NBIF1PortAExtCorr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +NBIF1PortAParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT = 0x0 # macro +NBIF1PortAParityErr_ACTION_CONTROL__IntrGenSel__SHIFT = 0x1 # macro +NBIF1PortAParityErr_ACTION_CONTROL__LinkDis_En__SHIFT = 0x3 # macro +NBIF1PortAParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT = 0x4 # macro +NBIF1PortAParityErr_ACTION_CONTROL__APML_ERR_En_MASK = 0x00000001 # macro +NBIF1PortAParityErr_ACTION_CONTROL__IntrGenSel_MASK = 0x00000006 # macro +NBIF1PortAParityErr_ACTION_CONTROL__LinkDis_En_MASK = 0x00000008 # macro +NBIF1PortAParityErr_ACTION_CONTROL__SyncFlood_En_MASK = 0x00000010 # macro +SYNCFLOOD_STATUS__SyncfloodFromRASCntl__SHIFT = 0x0 # macro +SYNCFLOOD_STATUS__SyncfloodFromAPML__SHIFT = 0x1 # macro +SYNCFLOOD_STATUS__SyncfloodFromPin__SHIFT = 0x2 # macro +SYNCFLOOD_STATUS__SyncfloodFromPrivate__SHIFT = 0x4 # macro +SYNCFLOOD_STATUS__SyncfloodFromMCA__SHIFT = 0x5 # macro +SYNCFLOOD_STATUS__SyncfloodFromRASCntl_MASK = 0x00000001 # macro +SYNCFLOOD_STATUS__SyncfloodFromAPML_MASK = 0x00000002 # macro +SYNCFLOOD_STATUS__SyncfloodFromPin_MASK = 0x00000004 # macro +SYNCFLOOD_STATUS__SyncfloodFromPrivate_MASK = 0x00000010 # macro +SYNCFLOOD_STATUS__SyncfloodFromMCA_MASK = 0x00000020 # macro +NMI_STATUS__NMIFromPin__SHIFT = 0x0 # macro +NMI_STATUS__NMIFromPin_MASK = 0x00000001 # macro +POISON_ACTION_CONTROL__IntPoisonAPMLErrEn__SHIFT = 0x0 # macro +POISON_ACTION_CONTROL__IntPoisonIntrGenSel__SHIFT = 0x1 # macro +POISON_ACTION_CONTROL__IntPoisonLinkDisEn__SHIFT = 0x3 # macro +POISON_ACTION_CONTROL__IntPoisonSyncFloodEn__SHIFT = 0x4 # macro +POISON_ACTION_CONTROL__EgressPoisonLSAPMLErrEn__SHIFT = 0x8 # macro +POISON_ACTION_CONTROL__EgressPoisonLSIntrGenSel__SHIFT = 0x9 # macro +POISON_ACTION_CONTROL__EgressPoisonLSLinkDisEn__SHIFT = 0xb # macro +POISON_ACTION_CONTROL__EgressPoisonLSSyncFloodEn__SHIFT = 0xc # macro +POISON_ACTION_CONTROL__EgressPoisonHSAPMLErrEn__SHIFT = 0x10 # macro +POISON_ACTION_CONTROL__EgressPoisonHSIntrGenSel__SHIFT = 0x11 # macro +POISON_ACTION_CONTROL__EgressPoisonHSLinkDisEn__SHIFT = 0x13 # macro +POISON_ACTION_CONTROL__EgressPoisonHSSyncFloodEn__SHIFT = 0x14 # macro +POISON_ACTION_CONTROL__IntPoisonAPMLErrEn_MASK = 0x00000001 # macro +POISON_ACTION_CONTROL__IntPoisonIntrGenSel_MASK = 0x00000006 # macro +POISON_ACTION_CONTROL__IntPoisonLinkDisEn_MASK = 0x00000008 # macro +POISON_ACTION_CONTROL__IntPoisonSyncFloodEn_MASK = 0x00000010 # macro +POISON_ACTION_CONTROL__EgressPoisonLSAPMLErrEn_MASK = 0x00000100 # macro +POISON_ACTION_CONTROL__EgressPoisonLSIntrGenSel_MASK = 0x00000600 # macro +POISON_ACTION_CONTROL__EgressPoisonLSLinkDisEn_MASK = 0x00000800 # macro +POISON_ACTION_CONTROL__EgressPoisonLSSyncFloodEn_MASK = 0x00001000 # macro +POISON_ACTION_CONTROL__EgressPoisonHSAPMLErrEn_MASK = 0x00010000 # macro +POISON_ACTION_CONTROL__EgressPoisonHSIntrGenSel_MASK = 0x00060000 # macro +POISON_ACTION_CONTROL__EgressPoisonHSLinkDisEn_MASK = 0x00080000 # macro +POISON_ACTION_CONTROL__EgressPoisonHSSyncFloodEn_MASK = 0x00100000 # macro +INTERNAL_POISON_STATUS__IntPoisonStatus_0__SHIFT = 0x0 # macro +INTERNAL_POISON_STATUS__IntPoisonStatus_1__SHIFT = 0x1 # macro +INTERNAL_POISON_STATUS__IntPoisonStatus_2__SHIFT = 0x2 # macro +INTERNAL_POISON_STATUS__IntPoisonStatus_3__SHIFT = 0x3 # macro +INTERNAL_POISON_STATUS__IntPoisonStatus_4__SHIFT = 0x4 # macro +INTERNAL_POISON_STATUS__IntPoisonStatus_5__SHIFT = 0x5 # macro +INTERNAL_POISON_STATUS__IntPoisonStatus_6__SHIFT = 0x6 # macro +INTERNAL_POISON_STATUS__IntPoisonStatus_7__SHIFT = 0x7 # macro +INTERNAL_POISON_STATUS__IntPoisonStatus_0_MASK = 0x00000001 # macro +INTERNAL_POISON_STATUS__IntPoisonStatus_1_MASK = 0x00000002 # macro +INTERNAL_POISON_STATUS__IntPoisonStatus_2_MASK = 0x00000004 # macro +INTERNAL_POISON_STATUS__IntPoisonStatus_3_MASK = 0x00000008 # macro +INTERNAL_POISON_STATUS__IntPoisonStatus_4_MASK = 0x00000010 # macro +INTERNAL_POISON_STATUS__IntPoisonStatus_5_MASK = 0x00000020 # macro +INTERNAL_POISON_STATUS__IntPoisonStatus_6_MASK = 0x00000040 # macro +INTERNAL_POISON_STATUS__IntPoisonStatus_7_MASK = 0x00000080 # macro +INTERNAL_POISON_MASK__IntPoisonMask__SHIFT = 0x0 # macro +INTERNAL_POISON_MASK__IntPoisonMask_MASK = 0x000000FF # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0__SHIFT = 0x0 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1__SHIFT = 0x1 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2__SHIFT = 0x2 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3__SHIFT = 0x3 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4__SHIFT = 0x4 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5__SHIFT = 0x5 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6__SHIFT = 0x6 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7__SHIFT = 0x7 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8__SHIFT = 0x8 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9__SHIFT = 0x9 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10__SHIFT = 0xa # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11__SHIFT = 0xb # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12__SHIFT = 0xc # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13__SHIFT = 0xd # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14__SHIFT = 0xe # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15__SHIFT = 0xf # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16__SHIFT = 0x10 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17__SHIFT = 0x11 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18__SHIFT = 0x12 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19__SHIFT = 0x13 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20__SHIFT = 0x14 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21__SHIFT = 0x15 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22__SHIFT = 0x16 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23__SHIFT = 0x17 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24__SHIFT = 0x18 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25__SHIFT = 0x19 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26__SHIFT = 0x1a # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27__SHIFT = 0x1b # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28__SHIFT = 0x1c # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29__SHIFT = 0x1d # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30__SHIFT = 0x1e # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31__SHIFT = 0x1f # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0_MASK = 0x00000001 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1_MASK = 0x00000002 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2_MASK = 0x00000004 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3_MASK = 0x00000008 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4_MASK = 0x00000010 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5_MASK = 0x00000020 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6_MASK = 0x00000040 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7_MASK = 0x00000080 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8_MASK = 0x00000100 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9_MASK = 0x00000200 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10_MASK = 0x00000400 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11_MASK = 0x00000800 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12_MASK = 0x00001000 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13_MASK = 0x00002000 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14_MASK = 0x00004000 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15_MASK = 0x00008000 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16_MASK = 0x00010000 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17_MASK = 0x00020000 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18_MASK = 0x00040000 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19_MASK = 0x00080000 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20_MASK = 0x00100000 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21_MASK = 0x00200000 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22_MASK = 0x00400000 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23_MASK = 0x00800000 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24_MASK = 0x01000000 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25_MASK = 0x02000000 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26_MASK = 0x04000000 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27_MASK = 0x08000000 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28_MASK = 0x10000000 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29_MASK = 0x20000000 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30_MASK = 0x40000000 # macro +EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31_MASK = 0x80000000 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0__SHIFT = 0x0 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1__SHIFT = 0x1 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2__SHIFT = 0x2 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3__SHIFT = 0x3 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4__SHIFT = 0x4 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5__SHIFT = 0x5 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6__SHIFT = 0x6 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7__SHIFT = 0x7 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8__SHIFT = 0x8 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9__SHIFT = 0x9 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10__SHIFT = 0xa # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11__SHIFT = 0xb # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12__SHIFT = 0xc # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13__SHIFT = 0xd # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14__SHIFT = 0xe # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15__SHIFT = 0xf # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16__SHIFT = 0x10 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17__SHIFT = 0x11 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18__SHIFT = 0x12 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19__SHIFT = 0x13 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20__SHIFT = 0x14 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21__SHIFT = 0x15 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22__SHIFT = 0x16 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23__SHIFT = 0x17 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24__SHIFT = 0x18 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25__SHIFT = 0x19 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26__SHIFT = 0x1a # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27__SHIFT = 0x1b # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28__SHIFT = 0x1c # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29__SHIFT = 0x1d # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30__SHIFT = 0x1e # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31__SHIFT = 0x1f # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0_MASK = 0x00000001 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1_MASK = 0x00000002 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2_MASK = 0x00000004 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3_MASK = 0x00000008 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4_MASK = 0x00000010 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5_MASK = 0x00000020 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6_MASK = 0x00000040 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7_MASK = 0x00000080 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8_MASK = 0x00000100 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9_MASK = 0x00000200 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10_MASK = 0x00000400 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11_MASK = 0x00000800 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12_MASK = 0x00001000 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13_MASK = 0x00002000 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14_MASK = 0x00004000 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15_MASK = 0x00008000 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16_MASK = 0x00010000 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17_MASK = 0x00020000 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18_MASK = 0x00040000 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19_MASK = 0x00080000 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20_MASK = 0x00100000 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21_MASK = 0x00200000 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22_MASK = 0x00400000 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23_MASK = 0x00800000 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24_MASK = 0x01000000 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25_MASK = 0x02000000 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26_MASK = 0x04000000 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27_MASK = 0x08000000 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28_MASK = 0x10000000 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29_MASK = 0x20000000 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30_MASK = 0x40000000 # macro +EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31_MASK = 0x80000000 # macro +EGRESS_POISON_MASK_LO__EgressPoisonMaskLo__SHIFT = 0x0 # macro +EGRESS_POISON_MASK_LO__EgressPoisonMaskLo_MASK = 0xFFFFFFFF # macro +EGRESS_POISON_MASK_HI__EgressPoisonMaskHi__SHIFT = 0x0 # macro +EGRESS_POISON_MASK_HI__EgressPoisonMaskHi_MASK = 0xFFFFFFFF # macro +EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown__SHIFT = 0x0 # macro +EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown_MASK = 0xFFFFFFFF # macro +EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper__SHIFT = 0x0 # macro +EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper_MASK = 0xFFFFFFFF # macro +APML_STATUS__APML_Corr__SHIFT = 0x0 # macro +APML_STATUS__APML_NonFatal__SHIFT = 0x1 # macro +APML_STATUS__APML_Fatal__SHIFT = 0x2 # macro +APML_STATUS__APML_Serr__SHIFT = 0x3 # macro +APML_STATUS__APML_IntPoisonErr__SHIFT = 0x4 # macro +APML_STATUS__APML_EgressPoisonErrLo__SHIFT = 0x5 # macro +APML_STATUS__APML_EgressPoisonErrHi__SHIFT = 0x6 # macro +APML_STATUS__APML_Corr_MASK = 0x00000001 # macro +APML_STATUS__APML_NonFatal_MASK = 0x00000002 # macro +APML_STATUS__APML_Fatal_MASK = 0x00000004 # macro +APML_STATUS__APML_Serr_MASK = 0x00000008 # macro +APML_STATUS__APML_IntPoisonErr_MASK = 0x00000010 # macro +APML_STATUS__APML_EgressPoisonErrLo_MASK = 0x00000020 # macro +APML_STATUS__APML_EgressPoisonErrHi_MASK = 0x00000040 # macro +APML_CONTROL__APML_NMI_En__SHIFT = 0x0 # macro +APML_CONTROL__APML_SyncFlood_En__SHIFT = 0x1 # macro +APML_CONTROL__APML_OutputDis__SHIFT = 0x8 # macro +APML_CONTROL__APML_NMI_En_MASK = 0x00000001 # macro +APML_CONTROL__APML_SyncFlood_En_MASK = 0x00000002 # macro +APML_CONTROL__APML_OutputDis_MASK = 0x00000100 # macro +APML_TRIGGER__APML_NMI_TRIGGER__SHIFT = 0x0 # macro +APML_TRIGGER__APML_NMI_TRIGGER_MASK = 0x00000001 # macro +NB_PCIE0DEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT = 0x0 # macro +NB_PCIE0DEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT = 0x8 # macro +NB_PCIE0DEVINDCFG0_STEERING_CNTL__ForceSteering_MASK = 0x00000001 # macro +NB_PCIE0DEVINDCFG0_STEERING_CNTL__SteeringValue_MASK = 0x0000FF00 # macro +NB_PCIE0DEVINDCFG1_STEERING_CNTL__ForceSteering__SHIFT = 0x0 # macro +NB_PCIE0DEVINDCFG1_STEERING_CNTL__SteeringValue__SHIFT = 0x8 # macro +NB_PCIE0DEVINDCFG1_STEERING_CNTL__ForceSteering_MASK = 0x00000001 # macro +NB_PCIE0DEVINDCFG1_STEERING_CNTL__SteeringValue_MASK = 0x0000FF00 # macro +NB_PCIE0DEVINDCFG2_STEERING_CNTL__ForceSteering__SHIFT = 0x0 # macro +NB_PCIE0DEVINDCFG2_STEERING_CNTL__SteeringValue__SHIFT = 0x8 # macro +NB_PCIE0DEVINDCFG2_STEERING_CNTL__ForceSteering_MASK = 0x00000001 # macro +NB_PCIE0DEVINDCFG2_STEERING_CNTL__SteeringValue_MASK = 0x0000FF00 # macro +NB_PCIE0DEVINDCFG3_STEERING_CNTL__ForceSteering__SHIFT = 0x0 # macro +NB_PCIE0DEVINDCFG3_STEERING_CNTL__SteeringValue__SHIFT = 0x8 # macro +NB_PCIE0DEVINDCFG3_STEERING_CNTL__ForceSteering_MASK = 0x00000001 # macro +NB_PCIE0DEVINDCFG3_STEERING_CNTL__SteeringValue_MASK = 0x0000FF00 # macro +NB_PCIE0DEVINDCFG4_STEERING_CNTL__ForceSteering__SHIFT = 0x0 # macro +NB_PCIE0DEVINDCFG4_STEERING_CNTL__SteeringValue__SHIFT = 0x8 # macro +NB_PCIE0DEVINDCFG4_STEERING_CNTL__ForceSteering_MASK = 0x00000001 # macro +NB_PCIE0DEVINDCFG4_STEERING_CNTL__SteeringValue_MASK = 0x0000FF00 # macro +NB_PCIE0DEVINDCFG5_STEERING_CNTL__ForceSteering__SHIFT = 0x0 # macro +NB_PCIE0DEVINDCFG5_STEERING_CNTL__SteeringValue__SHIFT = 0x8 # macro +NB_PCIE0DEVINDCFG5_STEERING_CNTL__ForceSteering_MASK = 0x00000001 # macro +NB_PCIE0DEVINDCFG5_STEERING_CNTL__SteeringValue_MASK = 0x0000FF00 # macro +NB_PCIE0DEVINDCFG6_STEERING_CNTL__ForceSteering__SHIFT = 0x0 # macro +NB_PCIE0DEVINDCFG6_STEERING_CNTL__SteeringValue__SHIFT = 0x8 # macro +NB_PCIE0DEVINDCFG6_STEERING_CNTL__ForceSteering_MASK = 0x00000001 # macro +NB_PCIE0DEVINDCFG6_STEERING_CNTL__SteeringValue_MASK = 0x0000FF00 # macro +NB_NBIF1DEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT = 0x0 # macro +NB_NBIF1DEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT = 0x8 # macro +NB_NBIF1DEVINDCFG0_STEERING_CNTL__ForceSteering_MASK = 0x00000001 # macro +NB_NBIF1DEVINDCFG0_STEERING_CNTL__SteeringValue_MASK = 0x0000FF00 # macro +NB_INTSBDEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT = 0x0 # macro +NB_INTSBDEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT = 0x8 # macro +NB_INTSBDEVINDCFG0_STEERING_CNTL__ForceSteering_MASK = 0x00000001 # macro +NB_INTSBDEVINDCFG0_STEERING_CNTL__SteeringValue_MASK = 0x0000FF00 # macro +NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT = 0x0 # macro +NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK = 0x000000FF # macro +NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT = 0x0 # macro +NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX_MASK = 0xFFFFFFFF # macro +NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA__SHIFT = 0x0 # macro +NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA_MASK = 0xFFFFFFFF # macro +NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT = 0x0 # macro +NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK = 0x000000FF # macro +NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT = 0x0 # macro +NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX_MASK = 0xFFFFFFFF # macro +NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA__SHIFT = 0x0 # macro +NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA_MASK = 0xFFFFFFFF # macro +NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT = 0x0 # macro +NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK = 0x000000FF # macro +NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT = 0x0 # macro +NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX__RC_SMN_INDEX_MASK = 0xFFFFFFFF # macro +NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA__RC_SMN_DATA__SHIFT = 0x0 # macro +NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA__RC_SMN_DATA_MASK = 0xFFFFFFFF # macro +NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT = 0x0 # macro +NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK = 0x000000FF # macro +NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT = 0x0 # macro +NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX__RC_SMN_INDEX_MASK = 0xFFFFFFFF # macro +NB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA__RC_SMN_DATA__SHIFT = 0x0 # macro +NB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA__RC_SMN_DATA_MASK = 0xFFFFFFFF # macro +NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT = 0x0 # macro +NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK = 0x000000FF # macro +NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT = 0x0 # macro +NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX__RC_SMN_INDEX_MASK = 0xFFFFFFFF # macro +NB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA__RC_SMN_DATA__SHIFT = 0x0 # macro +NB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA__RC_SMN_DATA_MASK = 0xFFFFFFFF # macro +NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT = 0x0 # macro +NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK = 0x000000FF # macro +NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT = 0x0 # macro +NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX__RC_SMN_INDEX_MASK = 0xFFFFFFFF # macro +NB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA__RC_SMN_DATA__SHIFT = 0x0 # macro +NB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA__RC_SMN_DATA_MASK = 0xFFFFFFFF # macro +NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT = 0x0 # macro +NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK = 0x000000FF # macro +NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT = 0x0 # macro +NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX__RC_SMN_INDEX_MASK = 0xFFFFFFFF # macro +NB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA__RC_SMN_DATA__SHIFT = 0x0 # macro +NB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA__RC_SMN_DATA_MASK = 0xFFFFFFFF # macro +NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT = 0x0 # macro +NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK = 0x000000FF # macro +NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT = 0x0 # macro +NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX_MASK = 0xFFFFFFFF # macro +NB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA__SHIFT = 0x0 # macro +NB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA_MASK = 0xFFFFFFFF # macro +L2_PERF_CNTL_0__L2PerfEvent0__SHIFT = 0x0 # macro +L2_PERF_CNTL_0__L2PerfEvent1__SHIFT = 0x8 # macro +L2_PERF_CNTL_0__L2PerfCountUpper0__SHIFT = 0x10 # macro +L2_PERF_CNTL_0__L2PerfCountUpper1__SHIFT = 0x18 # macro +L2_PERF_CNTL_0__L2PerfEvent0_MASK = 0x000000FF # macro +L2_PERF_CNTL_0__L2PerfEvent1_MASK = 0x0000FF00 # macro +L2_PERF_CNTL_0__L2PerfCountUpper0_MASK = 0x00FF0000 # macro +L2_PERF_CNTL_0__L2PerfCountUpper1_MASK = 0xFF000000 # macro +L2_PERF_COUNT_0__L2PerfCount0__SHIFT = 0x0 # macro +L2_PERF_COUNT_0__L2PerfCount0_MASK = 0xFFFFFFFF # macro +L2_PERF_COUNT_1__L2PerfCount1__SHIFT = 0x0 # macro +L2_PERF_COUNT_1__L2PerfCount1_MASK = 0xFFFFFFFF # macro +L2_PERF_CNTL_1__L2PerfEvent2__SHIFT = 0x0 # macro +L2_PERF_CNTL_1__L2PerfEvent3__SHIFT = 0x8 # macro +L2_PERF_CNTL_1__L2PerfCountUpper2__SHIFT = 0x10 # macro +L2_PERF_CNTL_1__L2PerfCountUpper3__SHIFT = 0x18 # macro +L2_PERF_CNTL_1__L2PerfEvent2_MASK = 0x000000FF # macro +L2_PERF_CNTL_1__L2PerfEvent3_MASK = 0x0000FF00 # macro +L2_PERF_CNTL_1__L2PerfCountUpper2_MASK = 0x00FF0000 # macro +L2_PERF_CNTL_1__L2PerfCountUpper3_MASK = 0xFF000000 # macro +L2_PERF_COUNT_2__L2PerfCount2__SHIFT = 0x0 # macro +L2_PERF_COUNT_2__L2PerfCount2_MASK = 0xFFFFFFFF # macro +L2_PERF_COUNT_3__L2PerfCount3__SHIFT = 0x0 # macro +L2_PERF_COUNT_3__L2PerfCount3_MASK = 0xFFFFFFFF # macro +L2_STATUS_0__L2STATUS0__SHIFT = 0x0 # macro +L2_STATUS_0__L2STATUS0_MASK = 0xFFFFFFFF # macro +L2_CONTROL_0__AllowL1CacheVZero__SHIFT = 0x1 # macro +L2_CONTROL_0__AllowL1CacheATSRsp__SHIFT = 0x2 # macro +L2_CONTROL_0__DTCHitVZeroOrIVZero__SHIFT = 0x3 # macro +L2_CONTROL_0__SIDEPTEOnUntransExcl__SHIFT = 0xa # macro +L2_CONTROL_0__SIDEPTEOnAddrTransExcl__SHIFT = 0xb # macro +L2_CONTROL_0__AllowL1CacheLargePagemode0__SHIFT = 0x13 # macro +L2_CONTROL_0__IFifoBurstLength__SHIFT = 0x14 # macro +L2_CONTROL_0__IFifoClientPriority__SHIFT = 0x18 # macro +L2_CONTROL_0__AllowL1CacheVZero_MASK = 0x00000002 # macro +L2_CONTROL_0__AllowL1CacheATSRsp_MASK = 0x00000004 # macro +L2_CONTROL_0__DTCHitVZeroOrIVZero_MASK = 0x00000008 # macro +L2_CONTROL_0__SIDEPTEOnUntransExcl_MASK = 0x00000400 # macro +L2_CONTROL_0__SIDEPTEOnAddrTransExcl_MASK = 0x00000800 # macro +L2_CONTROL_0__AllowL1CacheLargePagemode0_MASK = 0x00080000 # macro +L2_CONTROL_0__IFifoBurstLength_MASK = 0x00F00000 # macro +L2_CONTROL_0__IFifoClientPriority_MASK = 0xFF000000 # macro +L2_CONTROL_1__SeqInvBurstLimitInv__SHIFT = 0x0 # macro +L2_CONTROL_1__SeqInvBurstLimitL2Req__SHIFT = 0x8 # macro +L2_CONTROL_1__SeqInvBurstLimitEn__SHIFT = 0x10 # macro +L2_CONTROL_1__DBUSDis__SHIFT = 0x11 # macro +L2_CONTROL_1__PerfThreshold__SHIFT = 0x18 # macro +L2_CONTROL_1__SeqInvBurstLimitInv_MASK = 0x000000FF # macro +L2_CONTROL_1__SeqInvBurstLimitL2Req_MASK = 0x0000FF00 # macro +L2_CONTROL_1__SeqInvBurstLimitEn_MASK = 0x00010000 # macro +L2_CONTROL_1__DBUSDis_MASK = 0x00020000 # macro +L2_CONTROL_1__PerfThreshold_MASK = 0xFF000000 # macro +L2_DTC_CONTROL__DTCLRUUpdatePri__SHIFT = 0x3 # macro +L2_DTC_CONTROL__DTCParityEn__SHIFT = 0x4 # macro +L2_DTC_CONTROL__DTCInvalidationSel__SHIFT = 0x8 # macro +L2_DTC_CONTROL__DTCSoftInvalidate__SHIFT = 0xa # macro +L2_DTC_CONTROL__DTCBypass__SHIFT = 0xd # macro +L2_DTC_CONTROL__DTCParitySupport__SHIFT = 0xf # macro +L2_DTC_CONTROL__DTCWays__SHIFT = 0x10 # macro +L2_DTC_CONTROL__DTCEntries__SHIFT = 0x1c # macro +L2_DTC_CONTROL__DTCLRUUpdatePri_MASK = 0x00000008 # macro +L2_DTC_CONTROL__DTCParityEn_MASK = 0x00000010 # macro +L2_DTC_CONTROL__DTCInvalidationSel_MASK = 0x00000300 # macro +L2_DTC_CONTROL__DTCSoftInvalidate_MASK = 0x00000400 # macro +L2_DTC_CONTROL__DTCBypass_MASK = 0x00002000 # macro +L2_DTC_CONTROL__DTCParitySupport_MASK = 0x00008000 # macro +L2_DTC_CONTROL__DTCWays_MASK = 0x00FF0000 # macro +L2_DTC_CONTROL__DTCEntries_MASK = 0xF0000000 # macro +L2_DTC_HASH_CONTROL__DTCAddressMask__SHIFT = 0x10 # macro +L2_DTC_HASH_CONTROL__DTCAddressMask_MASK = 0xFFFF0000 # macro +L2_DTC_WAY_CONTROL__DTCWayDisable__SHIFT = 0x0 # macro +L2_DTC_WAY_CONTROL__DTCWayAccessDisable__SHIFT = 0x10 # macro +L2_DTC_WAY_CONTROL__DTCWayDisable_MASK = 0x0000FFFF # macro +L2_DTC_WAY_CONTROL__DTCWayAccessDisable_MASK = 0xFFFF0000 # macro +L2_ITC_CONTROL__ITCLRUUpdatePri__SHIFT = 0x3 # macro +L2_ITC_CONTROL__ITCParityEn__SHIFT = 0x4 # macro +L2_ITC_CONTROL__ITCInvalidationSel__SHIFT = 0x8 # macro +L2_ITC_CONTROL__ITCSoftInvalidate__SHIFT = 0xa # macro +L2_ITC_CONTROL__ITCBypass__SHIFT = 0xd # macro +L2_ITC_CONTROL__ITCParitySupport__SHIFT = 0xf # macro +L2_ITC_CONTROL__ITCWays__SHIFT = 0x10 # macro +L2_ITC_CONTROL__ITCEntries__SHIFT = 0x1c # macro +L2_ITC_CONTROL__ITCLRUUpdatePri_MASK = 0x00000008 # macro +L2_ITC_CONTROL__ITCParityEn_MASK = 0x00000010 # macro +L2_ITC_CONTROL__ITCInvalidationSel_MASK = 0x00000300 # macro +L2_ITC_CONTROL__ITCSoftInvalidate_MASK = 0x00000400 # macro +L2_ITC_CONTROL__ITCBypass_MASK = 0x00002000 # macro +L2_ITC_CONTROL__ITCParitySupport_MASK = 0x00008000 # macro +L2_ITC_CONTROL__ITCWays_MASK = 0x00FF0000 # macro +L2_ITC_CONTROL__ITCEntries_MASK = 0xF0000000 # macro +L2_ITC_HASH_CONTROL__ITCAddressMask__SHIFT = 0x10 # macro +L2_ITC_HASH_CONTROL__ITCAddressMask_MASK = 0xFFFF0000 # macro +L2_ITC_WAY_CONTROL__ITCWayDisable__SHIFT = 0x0 # macro +L2_ITC_WAY_CONTROL__ITCWayAccessDisable__SHIFT = 0x10 # macro +L2_ITC_WAY_CONTROL__ITCWayDisable_MASK = 0x0000FFFF # macro +L2_ITC_WAY_CONTROL__ITCWayAccessDisable_MASK = 0xFFFF0000 # macro +L2_PTC_A_CONTROL__PTCAStoreFinalATSeperate__SHIFT = 0x1 # macro +L2_PTC_A_CONTROL__PTCAStorePartialATSeperate__SHIFT = 0x2 # macro +L2_PTC_A_CONTROL__PTCALRUUpdatePri__SHIFT = 0x3 # macro +L2_PTC_A_CONTROL__PTCAParityEn__SHIFT = 0x4 # macro +L2_PTC_A_CONTROL__PTCAInvalidationSel__SHIFT = 0x8 # macro +L2_PTC_A_CONTROL__PTCASoftInvalidate__SHIFT = 0xa # macro +L2_PTC_A_CONTROL__PTCA2MMode__SHIFT = 0xb # macro +L2_PTC_A_CONTROL__PCTA_Inv_Overlapping_Pages__SHIFT = 0xc # macro +L2_PTC_A_CONTROL__PTCABypass__SHIFT = 0xd # macro +L2_PTC_A_CONTROL__PTCAFastInvalidateGuest__SHIFT = 0xe # macro +L2_PTC_A_CONTROL__PTCAParitySupport__SHIFT = 0xf # macro +L2_PTC_A_CONTROL__PTCAWays__SHIFT = 0x10 # macro +L2_PTC_A_CONTROL__PTCAEntries__SHIFT = 0x1c # macro +L2_PTC_A_CONTROL__PTCAStoreFinalATSeperate_MASK = 0x00000002 # macro +L2_PTC_A_CONTROL__PTCAStorePartialATSeperate_MASK = 0x00000004 # macro +L2_PTC_A_CONTROL__PTCALRUUpdatePri_MASK = 0x00000008 # macro +L2_PTC_A_CONTROL__PTCAParityEn_MASK = 0x00000010 # macro +L2_PTC_A_CONTROL__PTCAInvalidationSel_MASK = 0x00000300 # macro +L2_PTC_A_CONTROL__PTCASoftInvalidate_MASK = 0x00000400 # macro +L2_PTC_A_CONTROL__PTCA2MMode_MASK = 0x00000800 # macro +L2_PTC_A_CONTROL__PCTA_Inv_Overlapping_Pages_MASK = 0x00001000 # macro +L2_PTC_A_CONTROL__PTCABypass_MASK = 0x00002000 # macro +L2_PTC_A_CONTROL__PTCAFastInvalidateGuest_MASK = 0x00004000 # macro +L2_PTC_A_CONTROL__PTCAParitySupport_MASK = 0x00008000 # macro +L2_PTC_A_CONTROL__PTCAWays_MASK = 0x00FF0000 # macro +L2_PTC_A_CONTROL__PTCAEntries_MASK = 0xF0000000 # macro +L2_PTC_A_HASH_CONTROL__PTCAAddressMask__SHIFT = 0x10 # macro +L2_PTC_A_HASH_CONTROL__PTCAAddressMask_MASK = 0xFFFF0000 # macro +L2_PTC_A_WAY_CONTROL__PTCAWayDisable__SHIFT = 0x0 # macro +L2_PTC_A_WAY_CONTROL__PTCAWayAccessDisable__SHIFT = 0x10 # macro +L2_PTC_A_WAY_CONTROL__PTCAWayDisable_MASK = 0x0000FFFF # macro +L2_PTC_A_WAY_CONTROL__PTCAWayAccessDisable_MASK = 0xFFFF0000 # macro +L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_Bypass__SHIFT = 0x0 # macro +L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_RdLatency__SHIFT = 0x1 # macro +L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_Bypass_MASK = 0x00000001 # macro +L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_RdLatency_MASK = 0x0000001E # macro +L2_ERR_RULE_CONTROL_3__ERRRuleLock1__SHIFT = 0x0 # macro +L2_ERR_RULE_CONTROL_3__ERRRuleDisable3__SHIFT = 0x4 # macro +L2_ERR_RULE_CONTROL_3__ERRRuleLock1_MASK = 0x00000001 # macro +L2_ERR_RULE_CONTROL_3__ERRRuleDisable3_MASK = 0xFFFFFFF0 # macro +L2_ERR_RULE_CONTROL_4__ERRRuleDisable4__SHIFT = 0x0 # macro +L2_ERR_RULE_CONTROL_4__ERRRuleDisable4_MASK = 0xFFFFFFFF # macro +L2_ERR_RULE_CONTROL_5__ERRRuleDisable5__SHIFT = 0x0 # macro +L2_ERR_RULE_CONTROL_5__ERRRuleDisable5_MASK = 0xFFFFFFFF # macro +L2_L2A_CK_GATE_CONTROL__CKGateL2ARegsDisable__SHIFT = 0x0 # macro +L2_L2A_CK_GATE_CONTROL__CKGateL2ADynamicDisable__SHIFT = 0x1 # macro +L2_L2A_CK_GATE_CONTROL__CKGateL2ACacheDisable__SHIFT = 0x2 # macro +L2_L2A_CK_GATE_CONTROL__CKGateL2APerfDisable__SHIFT = 0x3 # macro +L2_L2A_CK_GATE_CONTROL__CKGateL2ALength__SHIFT = 0x10 # macro +L2_L2A_CK_GATE_CONTROL__CKGateL2AStop__SHIFT = 0x12 # macro +L2_L2A_CK_GATE_CONTROL__CKGateL2APortClkDis__SHIFT = 0x14 # macro +L2_L2A_CK_GATE_CONTROL__Reserved__SHIFT = 0x15 # macro +L2_L2A_CK_GATE_CONTROL__CKGateL2ARegsDisable_MASK = 0x00000001 # macro +L2_L2A_CK_GATE_CONTROL__CKGateL2ADynamicDisable_MASK = 0x00000002 # macro +L2_L2A_CK_GATE_CONTROL__CKGateL2ACacheDisable_MASK = 0x00000004 # macro +L2_L2A_CK_GATE_CONTROL__CKGateL2APerfDisable_MASK = 0x00000008 # macro +L2_L2A_CK_GATE_CONTROL__CKGateL2ALength_MASK = 0x00030000 # macro +L2_L2A_CK_GATE_CONTROL__CKGateL2AStop_MASK = 0x000C0000 # macro +L2_L2A_CK_GATE_CONTROL__CKGateL2APortClkDis_MASK = 0x00100000 # macro +L2_L2A_CK_GATE_CONTROL__Reserved_MASK = 0xFFE00000 # macro +L2_L2A_PGSIZE_CONTROL__L2AREG_GST_PGSIZE__SHIFT = 0x0 # macro +L2_L2A_PGSIZE_CONTROL__L2AREG_HOST_PGSIZE__SHIFT = 0x8 # macro +L2_L2A_PGSIZE_CONTROL__L2AREG_PTCSCAN_MODE__SHIFT = 0x11 # macro +L2_L2A_PGSIZE_CONTROL__L2AREG_GST_PGSIZE_MASK = 0x0000007F # macro +L2_L2A_PGSIZE_CONTROL__L2AREG_HOST_PGSIZE_MASK = 0x00007F00 # macro +L2_L2A_PGSIZE_CONTROL__L2AREG_PTCSCAN_MODE_MASK = 0x000E0000 # macro +L2_PWRGATE_CNTRL_REG_0__IP_PG_thres__SHIFT = 0x0 # macro +L2_PWRGATE_CNTRL_REG_0__IP_PG_thres_MASK = 0xFFFFFFFF # macro +L2_PWRGATE_CNTRL_REG_3__IP_PG_en__SHIFT = 0x0 # macro +L2_PWRGATE_CNTRL_REG_3__IP_PG_busy__SHIFT = 0x1 # macro +L2_PWRGATE_CNTRL_REG_3__L2_PG_STATUS__SHIFT = 0x2 # macro +L2_PWRGATE_CNTRL_REG_3__CFG_FW_PG_EXIT_EN__SHIFT = 0x3 # macro +L2_PWRGATE_CNTRL_REG_3__IP_PG_en_MASK = 0x00000001 # macro +L2_PWRGATE_CNTRL_REG_3__IP_PG_busy_MASK = 0x00000002 # macro +L2_PWRGATE_CNTRL_REG_3__L2_PG_STATUS_MASK = 0x00000004 # macro +L2_PWRGATE_CNTRL_REG_3__CFG_FW_PG_EXIT_EN_MASK = 0x00000018 # macro +L2_ECO_CNTRL_0__L2_ECO_0__SHIFT = 0x0 # macro +L2_ECO_CNTRL_0__L2_ECO_0_MASK = 0xFFFFFFFF # macro +L2_STATUS_1__L2STATUS1__SHIFT = 0x0 # macro +L2_STATUS_1__L2STATUS1_MASK = 0xFFFFFFFF # macro +L2_SB_LOCATION__SBlocated_Port__SHIFT = 0x0 # macro +L2_SB_LOCATION__SBlocated_Core__SHIFT = 0x10 # macro +L2_SB_LOCATION__SBlocated_Port_MASK = 0x0000FFFF # macro +L2_SB_LOCATION__SBlocated_Core_MASK = 0xFFFF0000 # macro +L2_CONTROL_5__QueueArbFBPri__SHIFT = 0x0 # macro +L2_CONTROL_5__FC1Dis__SHIFT = 0x2 # macro +L2_CONTROL_5__DTCUpdateVOneIVZero__SHIFT = 0x3 # macro +L2_CONTROL_5__DTCUpdateVZeroIVOne__SHIFT = 0x4 # macro +L2_CONTROL_5__FC3Dis__SHIFT = 0x6 # macro +L2_CONTROL_5__ForceTWonVCQoS__SHIFT = 0xb # macro +L2_CONTROL_5__GST_partial_ptc_cntrl__SHIFT = 0xc # macro +L2_CONTROL_5__STORE_PDPE_QOS_PTC__SHIFT = 0x14 # macro +L2_CONTROL_5__DTCUpdatePri__SHIFT = 0x19 # macro +L2_CONTROL_5__L2B_L2A_v1_trans_credits__SHIFT = 0x1a # macro +L2_CONTROL_5__QueueArbFBPri_MASK = 0x00000001 # macro +L2_CONTROL_5__FC1Dis_MASK = 0x00000004 # macro +L2_CONTROL_5__DTCUpdateVOneIVZero_MASK = 0x00000008 # macro +L2_CONTROL_5__DTCUpdateVZeroIVOne_MASK = 0x00000010 # macro +L2_CONTROL_5__FC3Dis_MASK = 0x00000040 # macro +L2_CONTROL_5__ForceTWonVCQoS_MASK = 0x00000800 # macro +L2_CONTROL_5__GST_partial_ptc_cntrl_MASK = 0x0007F000 # macro +L2_CONTROL_5__STORE_PDPE_QOS_PTC_MASK = 0x00100000 # macro +L2_CONTROL_5__DTCUpdatePri_MASK = 0x02000000 # macro +L2_CONTROL_5__L2B_L2A_v1_trans_credits_MASK = 0xFC000000 # macro +L2_CONTROL_6__SeqInvBurstLimitInv__SHIFT = 0x0 # macro +L2_CONTROL_6__SeqInvBurstLimitPDCReq__SHIFT = 0x8 # macro +L2_CONTROL_6__SeqInvBurstLimitEn__SHIFT = 0x10 # macro +L2_CONTROL_6__Perf2Threshold__SHIFT = 0x18 # macro +L2_CONTROL_6__SeqInvBurstLimitInv_MASK = 0x000000FF # macro +L2_CONTROL_6__SeqInvBurstLimitPDCReq_MASK = 0x0000FF00 # macro +L2_CONTROL_6__SeqInvBurstLimitEn_MASK = 0x00010000 # macro +L2_CONTROL_6__Perf2Threshold_MASK = 0xFF000000 # macro +L2_PDC_CONTROL__PDCLRUUpdatePri__SHIFT = 0x3 # macro +L2_PDC_CONTROL__PDCParityEn__SHIFT = 0x4 # macro +L2_PDC_CONTROL__PDCInvalidationSel__SHIFT = 0x8 # macro +L2_PDC_CONTROL__PDCSoftInvalidate__SHIFT = 0xa # macro +L2_PDC_CONTROL__PDC_Inv_Overlapping_Pages__SHIFT = 0xb # macro +L2_PDC_CONTROL__PDCSearchDirection__SHIFT = 0xc # macro +L2_PDC_CONTROL__PDCBypass__SHIFT = 0xd # macro +L2_PDC_CONTROL__PDCModeLookupFix__SHIFT = 0xe # macro +L2_PDC_CONTROL__PDCParitySupport__SHIFT = 0xf # macro +L2_PDC_CONTROL__PDCWays__SHIFT = 0x10 # macro +L2_PDC_CONTROL__PDCEntries__SHIFT = 0x1c # macro +L2_PDC_CONTROL__PDCLRUUpdatePri_MASK = 0x00000008 # macro +L2_PDC_CONTROL__PDCParityEn_MASK = 0x00000010 # macro +L2_PDC_CONTROL__PDCInvalidationSel_MASK = 0x00000300 # macro +L2_PDC_CONTROL__PDCSoftInvalidate_MASK = 0x00000400 # macro +L2_PDC_CONTROL__PDC_Inv_Overlapping_Pages_MASK = 0x00000800 # macro +L2_PDC_CONTROL__PDCSearchDirection_MASK = 0x00001000 # macro +L2_PDC_CONTROL__PDCBypass_MASK = 0x00002000 # macro +L2_PDC_CONTROL__PDCModeLookupFix_MASK = 0x00004000 # macro +L2_PDC_CONTROL__PDCParitySupport_MASK = 0x00008000 # macro +L2_PDC_CONTROL__PDCWays_MASK = 0x00FF0000 # macro +L2_PDC_CONTROL__PDCEntries_MASK = 0xF0000000 # macro +L2_PDC_HASH_CONTROL__PDCAddressMask__SHIFT = 0x10 # macro +L2_PDC_HASH_CONTROL__PDCAddressMask_MASK = 0xFFFF0000 # macro +L2_PDC_WAY_CONTROL__PDCWayDisable__SHIFT = 0x0 # macro +L2_PDC_WAY_CONTROL__PDCWayAccessDisable__SHIFT = 0x10 # macro +L2_PDC_WAY_CONTROL__PDCWayDisable_MASK = 0x0000FFFF # macro +L2_PDC_WAY_CONTROL__PDCWayAccessDisable_MASK = 0xFFFF0000 # macro +L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_Bypass__SHIFT = 0x0 # macro +L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_RdLatency__SHIFT = 0x1 # macro +L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_Bypass_MASK = 0x00000001 # macro +L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_RdLatency_MASK = 0x0000001E # macro +L2_TW_CONTROL__RESERVED__SHIFT = 0x0 # macro +L2_TW_CONTROL__TWForceCoherent__SHIFT = 0x6 # macro +L2_TW_CONTROL__TWPrefetchEn__SHIFT = 0x8 # macro +L2_TW_CONTROL__TWPrefetchOnly4KDis__SHIFT = 0x9 # macro +L2_TW_CONTROL__TWPTEOnUntransExcl__SHIFT = 0xa # macro +L2_TW_CONTROL__TWPTEOnAddrTransExcl__SHIFT = 0xb # macro +L2_TW_CONTROL__TWPrefetchRange__SHIFT = 0xc # macro +L2_TW_CONTROL__TWFilter_Dis__SHIFT = 0x10 # macro +L2_TW_CONTROL__TWFilter_64B_Dis__SHIFT = 0x11 # macro +L2_TW_CONTROL__TWContWalkOnPErrDis__SHIFT = 0x12 # macro +L2_TW_CONTROL__TWSetAccessBit_Dis__SHIFT = 0x13 # macro +L2_TW_CONTROL__TWClearAPBit_Dis__SHIFT = 0x14 # macro +L2_TW_CONTROL__TWCacheNestedPTE__SHIFT = 0x19 # macro +L2_TW_CONTROL__RESERVED_MASK = 0x0000003F # macro +L2_TW_CONTROL__TWForceCoherent_MASK = 0x00000040 # macro +L2_TW_CONTROL__TWPrefetchEn_MASK = 0x00000100 # macro +L2_TW_CONTROL__TWPrefetchOnly4KDis_MASK = 0x00000200 # macro +L2_TW_CONTROL__TWPTEOnUntransExcl_MASK = 0x00000400 # macro +L2_TW_CONTROL__TWPTEOnAddrTransExcl_MASK = 0x00000800 # macro +L2_TW_CONTROL__TWPrefetchRange_MASK = 0x00007000 # macro +L2_TW_CONTROL__TWFilter_Dis_MASK = 0x00010000 # macro +L2_TW_CONTROL__TWFilter_64B_Dis_MASK = 0x00020000 # macro +L2_TW_CONTROL__TWContWalkOnPErrDis_MASK = 0x00040000 # macro +L2_TW_CONTROL__TWSetAccessBit_Dis_MASK = 0x00080000 # macro +L2_TW_CONTROL__TWClearAPBit_Dis_MASK = 0x00100000 # macro +L2_TW_CONTROL__TWCacheNestedPTE_MASK = 0x02000000 # macro +L2_CP_CONTROL__CPPrefetchDis__SHIFT = 0x0 # macro +L2_CP_CONTROL__CPFlushOnWait__SHIFT = 0x1 # macro +L2_CP_CONTROL__CPFlushOnInv__SHIFT = 0x2 # macro +L2_CP_CONTROL__CPStallCmdErrForIOTLBCmpl__SHIFT = 0x3 # macro +L2_CP_CONTROL__CPForceReqPassPW__SHIFT = 0x4 # macro +L2_CP_CONTROL__CPForceOneOutstandingCommand__SHIFT = 0x5 # macro +L2_CP_CONTROL__CPRdDelay__SHIFT = 0x10 # macro +L2_CP_CONTROL__CPPrefetchDis_MASK = 0x00000001 # macro +L2_CP_CONTROL__CPFlushOnWait_MASK = 0x00000002 # macro +L2_CP_CONTROL__CPFlushOnInv_MASK = 0x00000004 # macro +L2_CP_CONTROL__CPStallCmdErrForIOTLBCmpl_MASK = 0x00000008 # macro +L2_CP_CONTROL__CPForceReqPassPW_MASK = 0x00000010 # macro +L2_CP_CONTROL__CPForceOneOutstandingCommand_MASK = 0x00000020 # macro +L2_CP_CONTROL__CPRdDelay_MASK = 0xFFFF0000 # macro +L2_CP_CONTROL_1__CPL1Off__SHIFT = 0x0 # macro +L2_CP_CONTROL_1__Reserved__SHIFT = 0x10 # macro +L2_CP_CONTROL_1__CPL1Off_MASK = 0x0000FFFF # macro +L2_CP_CONTROL_1__Reserved_MASK = 0xFFFF0000 # macro +L2_TW_CONTROL_1__TWTraceEn__SHIFT = 0x0 # macro +L2_TW_CONTROL_1__TWTraceNoWrap__SHIFT = 0x1 # macro +L2_TW_CONTROL_1__TWTraceForceDisable__SHIFT = 0x2 # macro +L2_TW_CONTROL_1__TWTraceMask__SHIFT = 0xf # macro +L2_TW_CONTROL_1__TWTraceEn_MASK = 0x00000001 # macro +L2_TW_CONTROL_1__TWTraceNoWrap_MASK = 0x00000002 # macro +L2_TW_CONTROL_1__TWTraceForceDisable_MASK = 0x00000004 # macro +L2_TW_CONTROL_1__TWTraceMask_MASK = 0xFFFF8000 # macro +L2_TW_CONTROL_2__TWTraceAddrLo__SHIFT = 0xc # macro +L2_TW_CONTROL_2__TWTraceAddrLo_MASK = 0xFFFFF000 # macro +L2_TW_CONTROL_3__TWTraceAddrHi__SHIFT = 0x0 # macro +L2_TW_CONTROL_3__TWTraceAddrHi_MASK = 0xFFFFFFFF # macro +L2_CREDIT_CONTROL_0__FC1Credits__SHIFT = 0x0 # macro +L2_CREDIT_CONTROL_0__FC1Override__SHIFT = 0x7 # macro +L2_CREDIT_CONTROL_0__FC3Credits__SHIFT = 0xf # macro +L2_CREDIT_CONTROL_0__FC3Override__SHIFT = 0x15 # macro +L2_CREDIT_CONTROL_0__FC1Credits_MASK = 0x0000007F # macro +L2_CREDIT_CONTROL_0__FC1Override_MASK = 0x00000080 # macro +L2_CREDIT_CONTROL_0__FC3Credits_MASK = 0x001F8000 # macro +L2_CREDIT_CONTROL_0__FC3Override_MASK = 0x00200000 # macro +L2_CREDIT_CONTROL_1__CP_PREFETCH_credits__SHIFT = 0x10 # macro +L2_CREDIT_CONTROL_1__PPR_MCIF_credits__SHIFT = 0x14 # macro +L2_CREDIT_CONTROL_1__CP_PREFETCH_credits_MASK = 0x000F0000 # macro +L2_CREDIT_CONTROL_1__PPR_MCIF_credits_MASK = 0x00F00000 # macro +L2_ERR_RULE_CONTROL_0__ERRRuleLock0__SHIFT = 0x0 # macro +L2_ERR_RULE_CONTROL_0__ERRRuleDisable0__SHIFT = 0x1 # macro +L2_ERR_RULE_CONTROL_0__ERRRuleLock0_MASK = 0x00000001 # macro +L2_ERR_RULE_CONTROL_0__ERRRuleDisable0_MASK = 0xFFFFFFFE # macro +L2_ERR_RULE_CONTROL_1__ERRRuleDisable1__SHIFT = 0x0 # macro +L2_ERR_RULE_CONTROL_1__ERRRuleDisable1_MASK = 0xFFFFFFFF # macro +L2_ERR_RULE_CONTROL_2__ERRRuleDisable2__SHIFT = 0x0 # macro +L2_ERR_RULE_CONTROL_2__ERRRuleDisable2_MASK = 0xFFFFFFFF # macro +L2_L2B_CK_GATE_CONTROL__CKGateL2BRegsDisable__SHIFT = 0x0 # macro +L2_L2B_CK_GATE_CONTROL__CKGateL2BDynamicDisable__SHIFT = 0x1 # macro +L2_L2B_CK_GATE_CONTROL__CKGateL2BMiscDisable__SHIFT = 0x2 # macro +L2_L2B_CK_GATE_CONTROL__CKGateL2BCacheDisable__SHIFT = 0x3 # macro +L2_L2B_CK_GATE_CONTROL__CKGateL2BAPCDisable__SHIFT = 0x4 # macro +L2_L2B_CK_GATE_CONTROL__CKGateL2BPerfDisable__SHIFT = 0x5 # macro +L2_L2B_CK_GATE_CONTROL__CKGateL2BPortClkDis__SHIFT = 0x6 # macro +L2_L2B_CK_GATE_CONTROL__CKGateL2BLength__SHIFT = 0x10 # macro +L2_L2B_CK_GATE_CONTROL__CKGateL2BStop__SHIFT = 0x12 # macro +L2_L2B_CK_GATE_CONTROL__Reserved__SHIFT = 0x14 # macro +L2_L2B_CK_GATE_CONTROL__CKGateL2BRegsDisable_MASK = 0x00000001 # macro +L2_L2B_CK_GATE_CONTROL__CKGateL2BDynamicDisable_MASK = 0x00000002 # macro +L2_L2B_CK_GATE_CONTROL__CKGateL2BMiscDisable_MASK = 0x00000004 # macro +L2_L2B_CK_GATE_CONTROL__CKGateL2BCacheDisable_MASK = 0x00000008 # macro +L2_L2B_CK_GATE_CONTROL__CKGateL2BAPCDisable_MASK = 0x00000010 # macro +L2_L2B_CK_GATE_CONTROL__CKGateL2BPerfDisable_MASK = 0x00000020 # macro +L2_L2B_CK_GATE_CONTROL__CKGateL2BPortClkDis_MASK = 0x00000040 # macro +L2_L2B_CK_GATE_CONTROL__CKGateL2BLength_MASK = 0x00030000 # macro +L2_L2B_CK_GATE_CONTROL__CKGateL2BStop_MASK = 0x000C0000 # macro +L2_L2B_CK_GATE_CONTROL__Reserved_MASK = 0xFFF00000 # macro +PPR_CONTROL__PPR_IntTimeDelay__SHIFT = 0x0 # macro +PPR_CONTROL__PPR_IntReqDelay__SHIFT = 0x8 # macro +PPR_CONTROL__PPR_IntCoallesce_En__SHIFT = 0x10 # macro +PPR_CONTROL__PPR_IntTimeDelay_MASK = 0x000000FF # macro +PPR_CONTROL__PPR_IntReqDelay_MASK = 0x0000FF00 # macro +PPR_CONTROL__PPR_IntCoallesce_En_MASK = 0x00010000 # macro +L2_L2B_PGSIZE_CONTROL__L2BREG_GST_PGSIZE__SHIFT = 0x0 # macro +L2_L2B_PGSIZE_CONTROL__L2BREG_HOST_PGSIZE__SHIFT = 0x8 # macro +L2_L2B_PGSIZE_CONTROL__L2BREG_GST_PGSIZE_MASK = 0x0000007F # macro +L2_L2B_PGSIZE_CONTROL__L2BREG_HOST_PGSIZE_MASK = 0x00007F00 # macro +L2_PERF_CNTL_2__L2PerfEvent4__SHIFT = 0x0 # macro +L2_PERF_CNTL_2__L2PerfEvent5__SHIFT = 0x8 # macro +L2_PERF_CNTL_2__L2PerfCountUpper4__SHIFT = 0x10 # macro +L2_PERF_CNTL_2__L2PerfCountUpper5__SHIFT = 0x18 # macro +L2_PERF_CNTL_2__L2PerfEvent4_MASK = 0x000000FF # macro +L2_PERF_CNTL_2__L2PerfEvent5_MASK = 0x0000FF00 # macro +L2_PERF_CNTL_2__L2PerfCountUpper4_MASK = 0x00FF0000 # macro +L2_PERF_CNTL_2__L2PerfCountUpper5_MASK = 0xFF000000 # macro +L2_PERF_COUNT_4__L2PerfCount4__SHIFT = 0x0 # macro +L2_PERF_COUNT_4__L2PerfCount4_MASK = 0xFFFFFFFF # macro +L2_PERF_COUNT_5__L2PerfCount5__SHIFT = 0x0 # macro +L2_PERF_COUNT_5__L2PerfCount5_MASK = 0xFFFFFFFF # macro +L2_PERF_CNTL_3__L2PerfEvent6__SHIFT = 0x0 # macro +L2_PERF_CNTL_3__L2PerfEvent7__SHIFT = 0x8 # macro +L2_PERF_CNTL_3__L2PerfCountUpper6__SHIFT = 0x10 # macro +L2_PERF_CNTL_3__L2PerfCountUpper7__SHIFT = 0x18 # macro +L2_PERF_CNTL_3__L2PerfEvent6_MASK = 0x000000FF # macro +L2_PERF_CNTL_3__L2PerfEvent7_MASK = 0x0000FF00 # macro +L2_PERF_CNTL_3__L2PerfCountUpper6_MASK = 0x00FF0000 # macro +L2_PERF_CNTL_3__L2PerfCountUpper7_MASK = 0xFF000000 # macro +L2_PERF_COUNT_6__L2PerfCount6__SHIFT = 0x0 # macro +L2_PERF_COUNT_6__L2PerfCount6_MASK = 0xFFFFFFFF # macro +L2_PERF_COUNT_7__L2PerfCount7__SHIFT = 0x0 # macro +L2_PERF_COUNT_7__L2PerfCount7_MASK = 0xFFFFFFFF # macro +L2B_SDP_PARITY_ERROR_EN__DVM_PARITY_ERROR_EN__SHIFT = 0x0 # macro +L2B_SDP_PARITY_ERROR_EN__CP_PARITY_ERROR_EN__SHIFT = 0x1 # macro +L2B_SDP_PARITY_ERROR_EN__TWW_PARITY_ERROR_EN__SHIFT = 0x2 # macro +L2B_SDP_PARITY_ERROR_EN__VFMMIO_PARITY_ERROR_EN__SHIFT = 0x3 # macro +L2B_SDP_PARITY_ERROR_EN__MSG_PARITY_ERROR_EN__SHIFT = 0x4 # macro +L2B_SDP_PARITY_ERROR_EN__DVM_PARITY_ERROR_EN_MASK = 0x00000001 # macro +L2B_SDP_PARITY_ERROR_EN__CP_PARITY_ERROR_EN_MASK = 0x00000002 # macro +L2B_SDP_PARITY_ERROR_EN__TWW_PARITY_ERROR_EN_MASK = 0x00000004 # macro +L2B_SDP_PARITY_ERROR_EN__VFMMIO_PARITY_ERROR_EN_MASK = 0x00000008 # macro +L2B_SDP_PARITY_ERROR_EN__MSG_PARITY_ERROR_EN_MASK = 0x00000010 # macro +L2_ECO_CNTRL_1__L2_ECO_1__SHIFT = 0x0 # macro +L2_ECO_CNTRL_1__L2_ECO_1_MASK = 0xFFFFFFFF # macro +L2_CP_CONTROL_2__OVERCONSTRAIN_CMD_WQ_ON_INV__SHIFT = 0x0 # macro +L2_CP_CONTROL_2__LEGACY_CWWB_PATH__SHIFT = 0x1 # macro +L2_CP_CONTROL_2__gstcp_always_refetch_v1__SHIFT = 0x2 # macro +L2_CP_CONTROL_2__inv_waitcmpl_mode__SHIFT = 0x16 # macro +L2_CP_CONTROL_2__inv_dvmsync_mode__SHIFT = 0x18 # macro +L2_CP_CONTROL_2__inv_pspflush_mode__SHIFT = 0x1a # macro +L2_CP_CONTROL_2__wqmask_propagation_latency__SHIFT = 0x1c # macro +L2_CP_CONTROL_2__OVERCONSTRAIN_CMD_WQ_ON_INV_MASK = 0x00000001 # macro +L2_CP_CONTROL_2__LEGACY_CWWB_PATH_MASK = 0x00000002 # macro +L2_CP_CONTROL_2__gstcp_always_refetch_v1_MASK = 0x00000004 # macro +L2_CP_CONTROL_2__inv_waitcmpl_mode_MASK = 0x00C00000 # macro +L2_CP_CONTROL_2__inv_dvmsync_mode_MASK = 0x03000000 # macro +L2_CP_CONTROL_2__inv_pspflush_mode_MASK = 0x0C000000 # macro +L2_CP_CONTROL_2__wqmask_propagation_latency_MASK = 0xF0000000 # macro +L2_CP_CONTROL_3__INV_CMD_PRIORITY__SHIFT = 0x0 # macro +L2_CP_CONTROL_3__WAIT_CMD_PRIORITY__SHIFT = 0x4 # macro +L2_CP_CONTROL_3__SYNC_CMD_PRIORITY__SHIFT = 0x8 # macro +L2_CP_CONTROL_3__PSP_CMD_PRIORITY__SHIFT = 0xc # macro +L2_CP_CONTROL_3__INV_CMD_PRIORITY_MASK = 0x0000000F # macro +L2_CP_CONTROL_3__WAIT_CMD_PRIORITY_MASK = 0x000000F0 # macro +L2_CP_CONTROL_3__SYNC_CMD_PRIORITY_MASK = 0x00000F00 # macro +L2_CP_CONTROL_3__PSP_CMD_PRIORITY_MASK = 0x0000F000 # macro +FEATURES_ENABLE__Ioapic_id_ext_en__SHIFT = 0x2 # macro +FEATURES_ENABLE__Ioapic_sb_feature_en__SHIFT = 0x4 # macro +FEATURES_ENABLE__Ioapic_secondary_en__SHIFT = 0x5 # macro +FEATURES_ENABLE__Ioapic_processor_mode__SHIFT = 0x8 # macro +FEATURES_ENABLE__INTx_LevelOnlyMode__SHIFT = 0x9 # macro +FEATURES_ENABLE__Ioapic_id_ext_en_MASK = 0x00000004 # macro +FEATURES_ENABLE__Ioapic_sb_feature_en_MASK = 0x00000010 # macro +FEATURES_ENABLE__Ioapic_secondary_en_MASK = 0x00000020 # macro +FEATURES_ENABLE__Ioapic_processor_mode_MASK = 0x00000100 # macro +FEATURES_ENABLE__INTx_LevelOnlyMode_MASK = 0x00000200 # macro +BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC_COMMAND__IOEN_DN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC_COMMAND__IOEN_DN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_RC_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_RC_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_RC_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_RC_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_RC_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_RC_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK = 0x000000FF # macro +BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK = 0x0000FF00 # macro +BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK = 0x00FF0000 # macro +BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_MASK = 0xF000 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK = 0x0000000F # macro +BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK = 0x0000FFF0 # macro +BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK = 0x0000000F # macro +BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK = 0x0000FFF0 # macro +BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT = 0x0 # macro +IRQ_BRIDGE_CNTL__SERR_EN__SHIFT = 0x1 # macro +IRQ_BRIDGE_CNTL__ISA_EN__SHIFT = 0x2 # macro +IRQ_BRIDGE_CNTL__VGA_EN__SHIFT = 0x3 # macro +IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT = 0x4 # macro +IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT = 0x5 # macro +IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT = 0x6 # macro +IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT = 0x7 # macro +IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT = 0x8 # macro +IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT = 0x9 # macro +IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT = 0xa # macro +IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT = 0xb # macro +IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK = 0x0001 # macro +IRQ_BRIDGE_CNTL__SERR_EN_MASK = 0x0002 # macro +IRQ_BRIDGE_CNTL__ISA_EN_MASK = 0x0004 # macro +IRQ_BRIDGE_CNTL__VGA_EN_MASK = 0x0008 # macro +IRQ_BRIDGE_CNTL__VGA_DEC_MASK = 0x0010 # macro +IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK = 0x0020 # macro +IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK = 0x0040 # macro +IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK = 0x0080 # macro +IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK = 0x0100 # macro +IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK = 0x0200 # macro +IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK = 0x0400 # macro +IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK = 0x01 # macro +BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_PMI_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC_PMI_CAP__VERSION_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT_MASK = 0x01C0 # macro +BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT_MASK = 0xF800 # macro +BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT = 0x17 # macro +BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE_MASK = 0x00000003 # macro +BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK = 0x00000008 # macro +BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT_MASK = 0x00001E00 # macro +BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE_MASK = 0x00006000 # macro +BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK = 0x00400000 # macro +BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN_MASK = 0x00800000 # macro +BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT = 0x13 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__MRL_SENSOR_PRESENT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_SURPRISE_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_CAPABLE_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK = 0x00007F80 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK = 0x00018000 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK = 0x00040000 # macro +BIF_CFG_DEV0_RC_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK = 0xFFF80000 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__INBAND_PD_DISABLE__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__HOTPLUG_INTR_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK = 0x00C0 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK = 0x2000 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL__INBAND_PD_DISABLE_MASK = 0x4000 # macro +BIF_CFG_DEV0_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_SLOT_STATUS__COMMAND_COMPLETED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC_SLOT_STATUS__DL_STATE_CHANGED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC_SLOT_STATUS__PWR_FAULT_DETECTED_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC_SLOT_STATUS__COMMAND_COMPLETED_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_STATE_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC_SLOT_STATUS__DL_STATE_CHANGED_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC_ROOT_CNTL__PM_INTERRUPT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_ROOT_STATUS__PME_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_ROOT_STATUS__PME_PENDING__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC_ROOT_STATUS__PME_REQUESTOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC_ROOT_STATUS__PME_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC_ROOT_STATUS__PME_PENDING_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_RC_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_SLOT_CNTL2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC_SLOT_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_SLOT_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK = 0x00000070 # macro +BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK = 0x00000300 # macro +BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK = 0x000E # macro +BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK = 0x000000FF # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK = 0x003F0000 # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK = 0x000000FE # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK = 0x000E0000 # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK = 0x07000000 # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK = 0x00000004 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT = 0x1b # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK = 0x00000004 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK = 0x00000008 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK = 0x00000040 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS_MASK = 0x00000180 # macro +BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK = 0xF8000000 # macro +BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK = 0x000F # macro +BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x0070 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK = 0x0F00 # macro +BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK = 0x7000 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT = 0xc # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK = 0x0080 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0300 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK = 0x0C00 # macro +BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK = 0x1000 # macro +BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK = 0x007FFFFF # macro +BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT = 0x1f # macro +BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK = 0x007FFFFF # macro +BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK = 0x80000000 # macro +BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK = 0x0F # macro +BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK = 0xF0 # macro +BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY_MASK = 0x0001 # macro +BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK = 0x0002 # macro +BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK = 0x0007 # macro +BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK = 0x0038 # macro +BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK = 0x0040 # macro +BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK = 0xFF00 # macro +BIF_CFG_DEV0_RC_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT = 0xb # macro +BIF_CFG_DEV0_RC_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK = 0x00000400 # macro +BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK = 0x0000F800 # macro +BIF_CFG_DEV0_RC_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK = 0x00000700 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT = 0x6 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT = 0x8 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT = 0x9 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT = 0xa # macro +BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK = 0x00000001 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK = 0x00000002 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK = 0x00000004 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK = 0x00000008 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK = 0x00000010 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK = 0x000000C0 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK = 0x00000100 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK = 0x00000200 # macro +BIF_CFG_DEV0_RC_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__STU__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__STU_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__STU__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__STU_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__ATC_ENABLE_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__STU__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__STU_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__ATC_ENABLE_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__STU__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__STU_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__ATC_ENABLE_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__STU__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__STU_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__ATC_ENABLE_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__STU__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__STU_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__ATC_ENABLE_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__STU__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__STU_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__ATC_ENABLE_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING_MASK = 0x0600 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID_MASK = 0xF0 # macro +BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE_MASK = 0x7F # macro +BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP_MASK = 0x0F # macro +BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT_MASK = 0x40 # macro +BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP_MASK = 0x80 # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID_MASK = 0xFFFF0000 # macro +BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK = 0x0000000E # macro +BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK = 0x000000F0 # macro +BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR_MASK = 0xFFFFF800 # macro +BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT_MASK = 0xFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE_MASK = 0x00F0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM_MASK = 0x3E00 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE__SHIFT = 0x1c # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC_MASK = 0x00000018 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK = 0x000001C0 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK = 0x00000E00 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK = 0x03FC0000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK = 0x0C000000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE_MASK = 0x10000000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK = 0x00E0 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH_MASK = 0x000003F0 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT_MASK = 0x00000C00 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY_MASK = 0x00007000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY_MASK = 0x00038000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER_MASK = 0xFF000000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL_MASK = 0x0003 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK = 0xC000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK = 0x03F0 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE_MASK = 0x2000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK = 0x0000000F # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK = 0x00003000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS_MASK = 0x0000C000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED_MASK = 0x000C0000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK = 0x00C00000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK = 0x03000000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK = 0x1000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN_MASK = 0x6000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED__SHIFT = 0x1f # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK = 0x000000FE # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK = 0x0000FE00 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK = 0x007F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED_MASK = 0x80000000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED_MASK = 0x000F # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN_MASK = 0x0380 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS_MASK = 0x0800 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK = 0xF000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK = 0x0004 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK = 0x0008 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK = 0x0010 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK = 0x0300 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK = 0x7000 # macro +BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK = 0x000E # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN_MASK = 0x0070 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK = 0x0100 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK = 0x0200 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK = 0x0400 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT = 0x2 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK = 0xFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID_MASK = 0x00FF # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK = 0x07FF # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK = 0x4000 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT = 0x3 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR_MASK = 0x00000007 # macro +BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET_MASK = 0xFFFFFFF8 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT = 0x11 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT = 0x12 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT = 0x13 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT = 0x15 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT = 0x16 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT = 0x17 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x18 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT = 0x19 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT = 0x1a # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK = 0x00000010 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK = 0x00010000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK = 0x00020000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK = 0x00040000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK = 0x00080000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK = 0x00100000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK = 0x00200000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK = 0x00400000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK = 0x00800000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK = 0x01000000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK = 0x02000000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK = 0x04000000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT = 0xd # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT = 0xe # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK = 0x00000001 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK = 0x00002000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK = 0x00004000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK = 0x00008000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT = 0x9 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT = 0xa # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT = 0xb # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT = 0xc # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK = 0x0000001F # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK = 0x00000020 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK = 0x00000040 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK = 0x00000080 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK = 0x00000100 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK = 0x00000200 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK = 0x00000400 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK = 0x00000800 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK = 0x00001000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK = 0xFFFFFFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT = 0x5 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT = 0x6 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT = 0x7 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK = 0x0020 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK = 0x0040 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK = 0x0080 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__STU__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT = 0xf # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__STU_MASK = 0x001F # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__ATC_ENABLE_MASK = 0x8000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT = 0x10 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT = 0x14 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK = 0x0000FFFF # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK = 0x000F0000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK = 0xFFF00000 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT = 0x8 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK = 0xFF00 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT = 0x0 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT = 0x1 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT = 0x4 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK = 0x0001 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK = 0x0002 # macro +BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK = 0x0070 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK = 0x000FFF00 # macro +BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2__SHIFT = 0x2 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3__SHIFT = 0x3 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4__SHIFT = 0x4 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5__SHIFT = 0x5 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6__SHIFT = 0x6 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7__SHIFT = 0x7 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT = 0xa # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT = 0xb # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT = 0xc # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT = 0xd # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT = 0xe # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT = 0x11 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT = 0x12 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT = 0x13 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT = 0x14 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT = 0x15 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT = 0x16 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT = 0x1a # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT = 0x1b # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT = 0x1c # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT = 0x1d # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT = 0x1e # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2_MASK = 0x00000004 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3_MASK = 0x00000008 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4_MASK = 0x00000010 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5_MASK = 0x00000020 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6_MASK = 0x00000040 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7_MASK = 0x00000080 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0_MASK = 0x00000400 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1_MASK = 0x00000800 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK = 0x00001000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK = 0x00002000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK = 0x00004000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK = 0x00010000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK = 0x00020000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK = 0x00040000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK = 0x00080000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK = 0x00100000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK = 0x00200000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK = 0x00400000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK = 0x04000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK = 0x08000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK = 0x10000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK = 0x20000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK = 0x40000000 # macro +BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT = 0x9 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID_MASK = 0x00000100 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK_MASK = 0x00000200 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT = 0x1 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT = 0x8 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT = 0xf # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT = 0x10 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT = 0x17 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT = 0x18 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT = 0x19 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK = 0x00000001 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK = 0x00000002 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK = 0x00000F00 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK = 0x00008000 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK = 0x000F0000 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK = 0x00800000 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK = 0x01000000 # macro +BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK = 0x02000000 # macro +BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER__SHIFT = 0x1f # macro +BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET_MASK = 0x7FFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER_MASK = 0x80000000 # macro +BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA_MASK = 0xFFFFFFFF # macro +BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI__SHIFT = 0x0 # macro +BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK = 0x00000002 # macro +RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT = 0x1f # macro +RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK = 0x80000000 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT = 0x2 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK = 0xFFFFFFFC # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK = 0xFFFFFFFF # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT = 0x0 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT = 0x1 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK = 0x00000001 # macro +RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK = 0x00000002 # macro +__all__ = \ + ['AID0_ATHUB_VF0_BASE_ADDR__AID0_ATHUB_VF0_BASE_ADDR_MASK', + 'AID0_ATHUB_VF0_BASE_ADDR__AID0_ATHUB_VF0_BASE_ADDR__SHIFT', + 'AID0_ATHUB_VF1_BASE_ADDR__AID0_ATHUB_VF1_BASE_ADDR_MASK', + 'AID0_ATHUB_VF1_BASE_ADDR__AID0_ATHUB_VF1_BASE_ADDR__SHIFT', + 'AID0_ATHUB_VF2_BASE_ADDR__AID0_ATHUB_VF2_BASE_ADDR_MASK', + 'AID0_ATHUB_VF2_BASE_ADDR__AID0_ATHUB_VF2_BASE_ADDR__SHIFT', + 'AID0_ATHUB_VF3_BASE_ADDR__AID0_ATHUB_VF3_BASE_ADDR_MASK', + 'AID0_ATHUB_VF3_BASE_ADDR__AID0_ATHUB_VF3_BASE_ADDR__SHIFT', + 'AID0_ATHUB_VF4_BASE_ADDR__AID0_ATHUB_VF4_BASE_ADDR_MASK', + 'AID0_ATHUB_VF4_BASE_ADDR__AID0_ATHUB_VF4_BASE_ADDR__SHIFT', + 'AID0_ATHUB_VF5_BASE_ADDR__AID0_ATHUB_VF5_BASE_ADDR_MASK', + 'AID0_ATHUB_VF5_BASE_ADDR__AID0_ATHUB_VF5_BASE_ADDR__SHIFT', + 'AID0_ATHUB_VF6_BASE_ADDR__AID0_ATHUB_VF6_BASE_ADDR_MASK', + 'AID0_ATHUB_VF6_BASE_ADDR__AID0_ATHUB_VF6_BASE_ADDR__SHIFT', + 'AID0_ATHUB_VF7_BASE_ADDR__AID0_ATHUB_VF7_BASE_ADDR_MASK', + 'AID0_ATHUB_VF7_BASE_ADDR__AID0_ATHUB_VF7_BASE_ADDR__SHIFT', + 'AID0_HDP_VF0_BASE_ADDR__AID0_HDP_VF0_BASE_ADDR_MASK', + 'AID0_HDP_VF0_BASE_ADDR__AID0_HDP_VF0_BASE_ADDR__SHIFT', + 'AID0_HDP_VF1_BASE_ADDR__AID0_HDP_VF1_BASE_ADDR_MASK', + 'AID0_HDP_VF1_BASE_ADDR__AID0_HDP_VF1_BASE_ADDR__SHIFT', + 'AID0_HDP_VF2_BASE_ADDR__AID0_HDP_VF2_BASE_ADDR_MASK', + 'AID0_HDP_VF2_BASE_ADDR__AID0_HDP_VF2_BASE_ADDR__SHIFT', + 'AID0_HDP_VF3_BASE_ADDR__AID0_HDP_VF3_BASE_ADDR_MASK', + 'AID0_HDP_VF3_BASE_ADDR__AID0_HDP_VF3_BASE_ADDR__SHIFT', + 'AID0_HDP_VF4_BASE_ADDR__AID0_HDP_VF4_BASE_ADDR_MASK', + 'AID0_HDP_VF4_BASE_ADDR__AID0_HDP_VF4_BASE_ADDR__SHIFT', + 'AID0_HDP_VF5_BASE_ADDR__AID0_HDP_VF5_BASE_ADDR_MASK', + 'AID0_HDP_VF5_BASE_ADDR__AID0_HDP_VF5_BASE_ADDR__SHIFT', + 'AID0_HDP_VF6_BASE_ADDR__AID0_HDP_VF6_BASE_ADDR_MASK', + 'AID0_HDP_VF6_BASE_ADDR__AID0_HDP_VF6_BASE_ADDR__SHIFT', + 'AID0_HDP_VF7_BASE_ADDR__AID0_HDP_VF7_BASE_ADDR_MASK', + 'AID0_HDP_VF7_BASE_ADDR__AID0_HDP_VF7_BASE_ADDR__SHIFT', + 'AID0_IH_VF0_BASE_ADDR__AID0_IH_VF0_BASE_ADDR_MASK', + 'AID0_IH_VF0_BASE_ADDR__AID0_IH_VF0_BASE_ADDR__SHIFT', + 'AID0_IH_VF1_BASE_ADDR__AID0_IH_VF1_BASE_ADDR_MASK', + 'AID0_IH_VF1_BASE_ADDR__AID0_IH_VF1_BASE_ADDR__SHIFT', + 'AID0_IH_VF2_BASE_ADDR__AID0_IH_VF2_BASE_ADDR_MASK', + 'AID0_IH_VF2_BASE_ADDR__AID0_IH_VF2_BASE_ADDR__SHIFT', + 'AID0_IH_VF3_BASE_ADDR__AID0_IH_VF3_BASE_ADDR_MASK', + 'AID0_IH_VF3_BASE_ADDR__AID0_IH_VF3_BASE_ADDR__SHIFT', + 'AID0_IH_VF4_BASE_ADDR__AID0_IH_VF4_BASE_ADDR_MASK', + 'AID0_IH_VF4_BASE_ADDR__AID0_IH_VF4_BASE_ADDR__SHIFT', + 'AID0_IH_VF5_BASE_ADDR__AID0_IH_VF5_BASE_ADDR_MASK', + 'AID0_IH_VF5_BASE_ADDR__AID0_IH_VF5_BASE_ADDR__SHIFT', + 'AID0_IH_VF6_BASE_ADDR__AID0_IH_VF6_BASE_ADDR_MASK', + 'AID0_IH_VF6_BASE_ADDR__AID0_IH_VF6_BASE_ADDR__SHIFT', + 'AID0_IH_VF7_BASE_ADDR__AID0_IH_VF7_BASE_ADDR_MASK', + 'AID0_IH_VF7_BASE_ADDR__AID0_IH_VF7_BASE_ADDR__SHIFT', + 'AID0_NBIF_VF0_BASE_ADDR__AID0_NBIF_VF0_BASE_ADDR_MASK', + 'AID0_NBIF_VF0_BASE_ADDR__AID0_NBIF_VF0_BASE_ADDR__SHIFT', + 'AID0_NBIF_VF1_BASE_ADDR__AID0_NBIF_VF1_BASE_ADDR_MASK', + 'AID0_NBIF_VF1_BASE_ADDR__AID0_NBIF_VF1_BASE_ADDR__SHIFT', + 'AID0_NBIF_VF2_BASE_ADDR__AID0_NBIF_VF2_BASE_ADDR_MASK', + 'AID0_NBIF_VF2_BASE_ADDR__AID0_NBIF_VF2_BASE_ADDR__SHIFT', + 'AID0_NBIF_VF3_BASE_ADDR__AID0_NBIF_VF3_BASE_ADDR_MASK', + 'AID0_NBIF_VF3_BASE_ADDR__AID0_NBIF_VF3_BASE_ADDR__SHIFT', + 'AID0_NBIF_VF4_BASE_ADDR__AID0_NBIF_VF4_BASE_ADDR_MASK', + 'AID0_NBIF_VF4_BASE_ADDR__AID0_NBIF_VF4_BASE_ADDR__SHIFT', + 'AID0_NBIF_VF5_BASE_ADDR__AID0_NBIF_VF5_BASE_ADDR_MASK', + 'AID0_NBIF_VF5_BASE_ADDR__AID0_NBIF_VF5_BASE_ADDR__SHIFT', + 'AID0_NBIF_VF6_BASE_ADDR__AID0_NBIF_VF6_BASE_ADDR_MASK', + 'AID0_NBIF_VF6_BASE_ADDR__AID0_NBIF_VF6_BASE_ADDR__SHIFT', + 'AID0_NBIF_VF7_BASE_ADDR__AID0_NBIF_VF7_BASE_ADDR_MASK', + 'AID0_NBIF_VF7_BASE_ADDR__AID0_NBIF_VF7_BASE_ADDR__SHIFT', + 'AID0_PF_BASE_ADDR__AID0_PF_BASE_ADDR_MASK', + 'AID0_PF_BASE_ADDR__AID0_PF_BASE_ADDR__SHIFT', + 'AID0_VF0_BASE_ADDR__AID0_VF0_BASE_ADDR_MASK', + 'AID0_VF0_BASE_ADDR__AID0_VF0_BASE_ADDR__SHIFT', + 'AID0_VF1_BASE_ADDR__AID0_VF1_BASE_ADDR_MASK', + 'AID0_VF1_BASE_ADDR__AID0_VF1_BASE_ADDR__SHIFT', + 'AID0_VF2_BASE_ADDR__AID0_VF2_BASE_ADDR_MASK', + 'AID0_VF2_BASE_ADDR__AID0_VF2_BASE_ADDR__SHIFT', + 'AID0_VF3_BASE_ADDR__AID0_VF3_BASE_ADDR_MASK', + 'AID0_VF3_BASE_ADDR__AID0_VF3_BASE_ADDR__SHIFT', + 'AID0_VF4_BASE_ADDR__AID0_VF4_BASE_ADDR_MASK', + 'AID0_VF4_BASE_ADDR__AID0_VF4_BASE_ADDR__SHIFT', + 'AID0_VF5_BASE_ADDR__AID0_VF5_BASE_ADDR_MASK', + 'AID0_VF5_BASE_ADDR__AID0_VF5_BASE_ADDR__SHIFT', + 'AID0_VF6_BASE_ADDR__AID0_VF6_BASE_ADDR_MASK', + 'AID0_VF6_BASE_ADDR__AID0_VF6_BASE_ADDR__SHIFT', + 'AID0_VF7_BASE_ADDR__AID0_VF7_BASE_ADDR_MASK', + 'AID0_VF7_BASE_ADDR__AID0_VF7_BASE_ADDR__SHIFT', + 'AID0_XCC0_PF_BASE_ADDR__AID0_XCC0_PF_BASE_ADDR_MASK', + 'AID0_XCC0_PF_BASE_ADDR__AID0_XCC0_PF_BASE_ADDR__SHIFT', + 'AID0_XCC0_VF0_BASE_ADDR__AID0_XCC0_VF0_BASE_ADDR_MASK', + 'AID0_XCC0_VF0_BASE_ADDR__AID0_XCC0_VF0_BASE_ADDR__SHIFT', + 'AID0_XCC0_VF1_BASE_ADDR__AID0_XCC0_VF1_BASE_ADDR_MASK', + 'AID0_XCC0_VF1_BASE_ADDR__AID0_XCC0_VF1_BASE_ADDR__SHIFT', + 'AID0_XCC0_VF2_BASE_ADDR__AID0_XCC0_VF2_BASE_ADDR_MASK', + 'AID0_XCC0_VF2_BASE_ADDR__AID0_XCC0_VF2_BASE_ADDR__SHIFT', + 'AID0_XCC0_VF3_BASE_ADDR__AID0_XCC0_VF3_BASE_ADDR_MASK', + 'AID0_XCC0_VF3_BASE_ADDR__AID0_XCC0_VF3_BASE_ADDR__SHIFT', + 'AID0_XCC0_VF4_BASE_ADDR__AID0_XCC0_VF4_BASE_ADDR_MASK', + 'AID0_XCC0_VF4_BASE_ADDR__AID0_XCC0_VF4_BASE_ADDR__SHIFT', + 'AID0_XCC0_VF5_BASE_ADDR__AID0_XCC0_VF5_BASE_ADDR_MASK', + 'AID0_XCC0_VF5_BASE_ADDR__AID0_XCC0_VF5_BASE_ADDR__SHIFT', + 'AID0_XCC0_VF6_BASE_ADDR__AID0_XCC0_VF6_BASE_ADDR_MASK', + 'AID0_XCC0_VF6_BASE_ADDR__AID0_XCC0_VF6_BASE_ADDR__SHIFT', + 'AID0_XCC0_VF7_BASE_ADDR__AID0_XCC0_VF7_BASE_ADDR_MASK', + 'AID0_XCC0_VF7_BASE_ADDR__AID0_XCC0_VF7_BASE_ADDR__SHIFT', + 'AID0_XCC1_PF_BASE_ADDR__AID0_XCC1_PF_BASE_ADDR_MASK', + 'AID0_XCC1_PF_BASE_ADDR__AID0_XCC1_PF_BASE_ADDR__SHIFT', + 'AID0_XCC1_VF0_BASE_ADDR__AID0_XCC1_VF0_BASE_ADDR_MASK', + 'AID0_XCC1_VF0_BASE_ADDR__AID0_XCC1_VF0_BASE_ADDR__SHIFT', + 'AID0_XCC1_VF1_BASE_ADDR__AID0_XCC1_VF1_BASE_ADDR_MASK', + 'AID0_XCC1_VF1_BASE_ADDR__AID0_XCC1_VF1_BASE_ADDR__SHIFT', + 'AID0_XCC1_VF2_BASE_ADDR__AID0_XCC1_VF2_BASE_ADDR_MASK', + 'AID0_XCC1_VF2_BASE_ADDR__AID0_XCC1_VF2_BASE_ADDR__SHIFT', + 'AID0_XCC1_VF3_BASE_ADDR__AID0_XCC1_VF3_BASE_ADDR_MASK', + 'AID0_XCC1_VF3_BASE_ADDR__AID0_XCC1_VF3_BASE_ADDR__SHIFT', + 'AID0_XCC1_VF4_BASE_ADDR__AID0_XCC1_VF4_BASE_ADDR_MASK', + 'AID0_XCC1_VF4_BASE_ADDR__AID0_XCC1_VF4_BASE_ADDR__SHIFT', + 'AID0_XCC1_VF5_BASE_ADDR__AID0_XCC1_VF5_BASE_ADDR_MASK', + 'AID0_XCC1_VF5_BASE_ADDR__AID0_XCC1_VF5_BASE_ADDR__SHIFT', + 'AID0_XCC1_VF6_BASE_ADDR__AID0_XCC1_VF6_BASE_ADDR_MASK', + 'AID0_XCC1_VF6_BASE_ADDR__AID0_XCC1_VF6_BASE_ADDR__SHIFT', + 'AID0_XCC1_VF7_BASE_ADDR__AID0_XCC1_VF7_BASE_ADDR_MASK', + 'AID0_XCC1_VF7_BASE_ADDR__AID0_XCC1_VF7_BASE_ADDR__SHIFT', + 'AID1_PF_BASE_ADDR__AID1_PF_BASE_ADDR_MASK', + 'AID1_PF_BASE_ADDR__AID1_PF_BASE_ADDR__SHIFT', + 'AID1_VF0_BASE_ADDR__AID1_VF0_BASE_ADDR_MASK', + 'AID1_VF0_BASE_ADDR__AID1_VF0_BASE_ADDR__SHIFT', + 'AID1_VF1_BASE_ADDR__AID1_VF1_BASE_ADDR_MASK', + 'AID1_VF1_BASE_ADDR__AID1_VF1_BASE_ADDR__SHIFT', + 'AID1_VF2_BASE_ADDR__AID1_VF2_BASE_ADDR_MASK', + 'AID1_VF2_BASE_ADDR__AID1_VF2_BASE_ADDR__SHIFT', + 'AID1_VF3_BASE_ADDR__AID1_VF3_BASE_ADDR_MASK', + 'AID1_VF3_BASE_ADDR__AID1_VF3_BASE_ADDR__SHIFT', + 'AID1_VF4_BASE_ADDR__AID1_VF4_BASE_ADDR_MASK', + 'AID1_VF4_BASE_ADDR__AID1_VF4_BASE_ADDR__SHIFT', + 'AID1_VF5_BASE_ADDR__AID1_VF5_BASE_ADDR_MASK', + 'AID1_VF5_BASE_ADDR__AID1_VF5_BASE_ADDR__SHIFT', + 'AID1_VF6_BASE_ADDR__AID1_VF6_BASE_ADDR_MASK', + 'AID1_VF6_BASE_ADDR__AID1_VF6_BASE_ADDR__SHIFT', + 'AID1_VF7_BASE_ADDR__AID1_VF7_BASE_ADDR_MASK', + 'AID1_VF7_BASE_ADDR__AID1_VF7_BASE_ADDR__SHIFT', + 'AID1_XCC0_PF_BASE_ADDR__AID1_XCC0_PF_BASE_ADDR_MASK', + 'AID1_XCC0_PF_BASE_ADDR__AID1_XCC0_PF_BASE_ADDR__SHIFT', + 'AID1_XCC0_VF0_BASE_ADDR__AID1_XCC0_VF0_BASE_ADDR_MASK', + 'AID1_XCC0_VF0_BASE_ADDR__AID1_XCC0_VF0_BASE_ADDR__SHIFT', + 'AID1_XCC0_VF1_BASE_ADDR__AID1_XCC0_VF1_BASE_ADDR_MASK', + 'AID1_XCC0_VF1_BASE_ADDR__AID1_XCC0_VF1_BASE_ADDR__SHIFT', + 'AID1_XCC0_VF2_BASE_ADDR__AID1_XCC0_VF2_BASE_ADDR_MASK', + 'AID1_XCC0_VF2_BASE_ADDR__AID1_XCC0_VF2_BASE_ADDR__SHIFT', + 'AID1_XCC0_VF3_BASE_ADDR__AID1_XCC0_VF3_BASE_ADDR_MASK', + 'AID1_XCC0_VF3_BASE_ADDR__AID1_XCC0_VF3_BASE_ADDR__SHIFT', + 'AID1_XCC0_VF4_BASE_ADDR__AID1_XCC0_VF4_BASE_ADDR_MASK', + 'AID1_XCC0_VF4_BASE_ADDR__AID1_XCC0_VF4_BASE_ADDR__SHIFT', + 'AID1_XCC0_VF5_BASE_ADDR__AID1_XCC0_VF5_BASE_ADDR_MASK', + 'AID1_XCC0_VF5_BASE_ADDR__AID1_XCC0_VF5_BASE_ADDR__SHIFT', + 'AID1_XCC0_VF6_BASE_ADDR__AID1_XCC0_VF6_BASE_ADDR_MASK', + 'AID1_XCC0_VF6_BASE_ADDR__AID1_XCC0_VF6_BASE_ADDR__SHIFT', + 'AID1_XCC0_VF7_BASE_ADDR__AID1_XCC0_VF7_BASE_ADDR_MASK', + 'AID1_XCC0_VF7_BASE_ADDR__AID1_XCC0_VF7_BASE_ADDR__SHIFT', + 'AID1_XCC1_PF_BASE_ADDR__AID1_XCC1_PF_BASE_ADDR_MASK', + 'AID1_XCC1_PF_BASE_ADDR__AID1_XCC1_PF_BASE_ADDR__SHIFT', + 'AID1_XCC1_VF0_BASE_ADDR__AID1_XCC1_VF0_BASE_ADDR_MASK', + 'AID1_XCC1_VF0_BASE_ADDR__AID1_XCC1_VF0_BASE_ADDR__SHIFT', + 'AID1_XCC1_VF1_BASE_ADDR__AID1_XCC1_VF1_BASE_ADDR_MASK', + 'AID1_XCC1_VF1_BASE_ADDR__AID1_XCC1_VF1_BASE_ADDR__SHIFT', + 'AID1_XCC1_VF2_BASE_ADDR__AID1_XCC1_VF2_BASE_ADDR_MASK', + 'AID1_XCC1_VF2_BASE_ADDR__AID1_XCC1_VF2_BASE_ADDR__SHIFT', + 'AID1_XCC1_VF3_BASE_ADDR__AID1_XCC1_VF3_BASE_ADDR_MASK', + 'AID1_XCC1_VF3_BASE_ADDR__AID1_XCC1_VF3_BASE_ADDR__SHIFT', + 'AID1_XCC1_VF4_BASE_ADDR__AID1_XCC1_VF4_BASE_ADDR_MASK', + 'AID1_XCC1_VF4_BASE_ADDR__AID1_XCC1_VF4_BASE_ADDR__SHIFT', + 'AID1_XCC1_VF5_BASE_ADDR__AID1_XCC1_VF5_BASE_ADDR_MASK', + 'AID1_XCC1_VF5_BASE_ADDR__AID1_XCC1_VF5_BASE_ADDR__SHIFT', + 'AID1_XCC1_VF6_BASE_ADDR__AID1_XCC1_VF6_BASE_ADDR_MASK', + 'AID1_XCC1_VF6_BASE_ADDR__AID1_XCC1_VF6_BASE_ADDR__SHIFT', + 'AID1_XCC1_VF7_BASE_ADDR__AID1_XCC1_VF7_BASE_ADDR_MASK', + 'AID1_XCC1_VF7_BASE_ADDR__AID1_XCC1_VF7_BASE_ADDR__SHIFT', + 'AID2_PF_BASE_ADDR__AID2_PF_BASE_ADDR_MASK', + 'AID2_PF_BASE_ADDR__AID2_PF_BASE_ADDR__SHIFT', + 'AID2_VF0_BASE_ADDR__AID2_VF0_BASE_ADDR_MASK', + 'AID2_VF0_BASE_ADDR__AID2_VF0_BASE_ADDR__SHIFT', + 'AID2_VF1_BASE_ADDR__AID2_VF1_BASE_ADDR_MASK', + 'AID2_VF1_BASE_ADDR__AID2_VF1_BASE_ADDR__SHIFT', + 'AID2_VF2_BASE_ADDR__AID2_VF2_BASE_ADDR_MASK', + 'AID2_VF2_BASE_ADDR__AID2_VF2_BASE_ADDR__SHIFT', + 'AID2_VF3_BASE_ADDR__AID2_VF3_BASE_ADDR_MASK', + 'AID2_VF3_BASE_ADDR__AID2_VF3_BASE_ADDR__SHIFT', + 'AID2_VF4_BASE_ADDR__AID2_VF4_BASE_ADDR_MASK', + 'AID2_VF4_BASE_ADDR__AID2_VF4_BASE_ADDR__SHIFT', + 'AID2_VF5_BASE_ADDR__AID2_VF5_BASE_ADDR_MASK', + 'AID2_VF5_BASE_ADDR__AID2_VF5_BASE_ADDR__SHIFT', + 'AID2_VF6_BASE_ADDR__AID2_VF6_BASE_ADDR_MASK', + 'AID2_VF6_BASE_ADDR__AID2_VF6_BASE_ADDR__SHIFT', + 'AID2_VF7_BASE_ADDR__AID2_VF7_BASE_ADDR_MASK', + 'AID2_VF7_BASE_ADDR__AID2_VF7_BASE_ADDR__SHIFT', + 'AID2_XCC0_PF_BASE_ADDR__AID2_XCC0_PF_BASE_ADDR_MASK', + 'AID2_XCC0_PF_BASE_ADDR__AID2_XCC0_PF_BASE_ADDR__SHIFT', + 'AID2_XCC0_VF0_BASE_ADDR__AID2_XCC0_VF0_BASE_ADDR_MASK', + 'AID2_XCC0_VF0_BASE_ADDR__AID2_XCC0_VF0_BASE_ADDR__SHIFT', + 'AID2_XCC0_VF1_BASE_ADDR__AID2_XCC0_VF1_BASE_ADDR_MASK', + 'AID2_XCC0_VF1_BASE_ADDR__AID2_XCC0_VF1_BASE_ADDR__SHIFT', + 'AID2_XCC0_VF2_BASE_ADDR__AID2_XCC0_VF2_BASE_ADDR_MASK', + 'AID2_XCC0_VF2_BASE_ADDR__AID2_XCC0_VF2_BASE_ADDR__SHIFT', + 'AID2_XCC0_VF3_BASE_ADDR__AID2_XCC0_VF3_BASE_ADDR_MASK', + 'AID2_XCC0_VF3_BASE_ADDR__AID2_XCC0_VF3_BASE_ADDR__SHIFT', + 'AID2_XCC0_VF4_BASE_ADDR__AID2_XCC0_VF4_BASE_ADDR_MASK', + 'AID2_XCC0_VF4_BASE_ADDR__AID2_XCC0_VF4_BASE_ADDR__SHIFT', + 'AID2_XCC0_VF5_BASE_ADDR__AID2_XCC0_VF5_BASE_ADDR_MASK', + 'AID2_XCC0_VF5_BASE_ADDR__AID2_XCC0_VF5_BASE_ADDR__SHIFT', + 'AID2_XCC0_VF6_BASE_ADDR__AID2_XCC0_VF6_BASE_ADDR_MASK', + 'AID2_XCC0_VF6_BASE_ADDR__AID2_XCC0_VF6_BASE_ADDR__SHIFT', + 'AID2_XCC0_VF7_BASE_ADDR__AID2_XCC0_VF7_BASE_ADDR_MASK', + 'AID2_XCC0_VF7_BASE_ADDR__AID2_XCC0_VF7_BASE_ADDR__SHIFT', + 'AID2_XCC1_PF_BASE_ADDR__AID2_XCC1_PF_BASE_ADDR_MASK', + 'AID2_XCC1_PF_BASE_ADDR__AID2_XCC1_PF_BASE_ADDR__SHIFT', + 'AID2_XCC1_VF0_BASE_ADDR__AID2_XCC1_VF0_BASE_ADDR_MASK', + 'AID2_XCC1_VF0_BASE_ADDR__AID2_XCC1_VF0_BASE_ADDR__SHIFT', + 'AID2_XCC1_VF1_BASE_ADDR__AID2_XCC1_VF1_BASE_ADDR_MASK', + 'AID2_XCC1_VF1_BASE_ADDR__AID2_XCC1_VF1_BASE_ADDR__SHIFT', + 'AID2_XCC1_VF2_BASE_ADDR__AID2_XCC1_VF2_BASE_ADDR_MASK', + 'AID2_XCC1_VF2_BASE_ADDR__AID2_XCC1_VF2_BASE_ADDR__SHIFT', + 'AID2_XCC1_VF3_BASE_ADDR__AID2_XCC1_VF3_BASE_ADDR_MASK', + 'AID2_XCC1_VF3_BASE_ADDR__AID2_XCC1_VF3_BASE_ADDR__SHIFT', + 'AID2_XCC1_VF4_BASE_ADDR__AID2_XCC1_VF4_BASE_ADDR_MASK', + 'AID2_XCC1_VF4_BASE_ADDR__AID2_XCC1_VF4_BASE_ADDR__SHIFT', + 'AID2_XCC1_VF5_BASE_ADDR__AID2_XCC1_VF5_BASE_ADDR_MASK', + 'AID2_XCC1_VF5_BASE_ADDR__AID2_XCC1_VF5_BASE_ADDR__SHIFT', + 'AID2_XCC1_VF6_BASE_ADDR__AID2_XCC1_VF6_BASE_ADDR_MASK', + 'AID2_XCC1_VF6_BASE_ADDR__AID2_XCC1_VF6_BASE_ADDR__SHIFT', + 'AID2_XCC1_VF7_BASE_ADDR__AID2_XCC1_VF7_BASE_ADDR_MASK', + 'AID2_XCC1_VF7_BASE_ADDR__AID2_XCC1_VF7_BASE_ADDR__SHIFT', + 'AID3_PF_BASE_ADDR__AID3_PF_BASE_ADDR_MASK', + 'AID3_PF_BASE_ADDR__AID3_PF_BASE_ADDR__SHIFT', + 'AID3_VF0_BASE_ADDR__AID3_VF0_BASE_ADDR_MASK', + 'AID3_VF0_BASE_ADDR__AID3_VF0_BASE_ADDR__SHIFT', + 'AID3_VF1_BASE_ADDR__AID3_VF1_BASE_ADDR_MASK', + 'AID3_VF1_BASE_ADDR__AID3_VF1_BASE_ADDR__SHIFT', + 'AID3_VF2_BASE_ADDR__AID3_VF2_BASE_ADDR_MASK', + 'AID3_VF2_BASE_ADDR__AID3_VF2_BASE_ADDR__SHIFT', + 'AID3_VF3_BASE_ADDR__AID3_VF3_BASE_ADDR_MASK', + 'AID3_VF3_BASE_ADDR__AID3_VF3_BASE_ADDR__SHIFT', + 'AID3_VF4_BASE_ADDR__AID3_VF4_BASE_ADDR_MASK', + 'AID3_VF4_BASE_ADDR__AID3_VF4_BASE_ADDR__SHIFT', + 'AID3_VF5_BASE_ADDR__AID3_VF5_BASE_ADDR_MASK', + 'AID3_VF5_BASE_ADDR__AID3_VF5_BASE_ADDR__SHIFT', + 'AID3_VF6_BASE_ADDR__AID3_VF6_BASE_ADDR_MASK', + 'AID3_VF6_BASE_ADDR__AID3_VF6_BASE_ADDR__SHIFT', + 'AID3_VF7_BASE_ADDR__AID3_VF7_BASE_ADDR_MASK', + 'AID3_VF7_BASE_ADDR__AID3_VF7_BASE_ADDR__SHIFT', + 'AID3_XCC0_PF_BASE_ADDR__AID3_XCC0_PF_BASE_ADDR_MASK', + 'AID3_XCC0_PF_BASE_ADDR__AID3_XCC0_PF_BASE_ADDR__SHIFT', + 'AID3_XCC0_VF0_BASE_ADDR__AID3_XCC0_VF0_BASE_ADDR_MASK', + 'AID3_XCC0_VF0_BASE_ADDR__AID3_XCC0_VF0_BASE_ADDR__SHIFT', + 'AID3_XCC0_VF1_BASE_ADDR__AID3_XCC0_VF1_BASE_ADDR_MASK', + 'AID3_XCC0_VF1_BASE_ADDR__AID3_XCC0_VF1_BASE_ADDR__SHIFT', + 'AID3_XCC0_VF2_BASE_ADDR__AID3_XCC0_VF2_BASE_ADDR_MASK', + 'AID3_XCC0_VF2_BASE_ADDR__AID3_XCC0_VF2_BASE_ADDR__SHIFT', + 'AID3_XCC0_VF3_BASE_ADDR__AID3_XCC0_VF3_BASE_ADDR_MASK', + 'AID3_XCC0_VF3_BASE_ADDR__AID3_XCC0_VF3_BASE_ADDR__SHIFT', + 'AID3_XCC0_VF4_BASE_ADDR__AID3_XCC0_VF4_BASE_ADDR_MASK', + 'AID3_XCC0_VF4_BASE_ADDR__AID3_XCC0_VF4_BASE_ADDR__SHIFT', + 'AID3_XCC0_VF5_BASE_ADDR__AID3_XCC0_VF5_BASE_ADDR_MASK', + 'AID3_XCC0_VF5_BASE_ADDR__AID3_XCC0_VF5_BASE_ADDR__SHIFT', + 'AID3_XCC0_VF6_BASE_ADDR__AID3_XCC0_VF6_BASE_ADDR_MASK', + 'AID3_XCC0_VF6_BASE_ADDR__AID3_XCC0_VF6_BASE_ADDR__SHIFT', + 'AID3_XCC0_VF7_BASE_ADDR__AID3_XCC0_VF7_BASE_ADDR_MASK', + 'AID3_XCC0_VF7_BASE_ADDR__AID3_XCC0_VF7_BASE_ADDR__SHIFT', + 'AID3_XCC1_PF_BASE_ADDR__AID3_XCC1_PF_BASE_ADDR_MASK', + 'AID3_XCC1_PF_BASE_ADDR__AID3_XCC1_PF_BASE_ADDR__SHIFT', + 'AID3_XCC1_VF0_BASE_ADDR__AID3_XCC1_VF0_BASE_ADDR_MASK', + 'AID3_XCC1_VF0_BASE_ADDR__AID3_XCC1_VF0_BASE_ADDR__SHIFT', + 'AID3_XCC1_VF1_BASE_ADDR__AID3_XCC1_VF1_BASE_ADDR_MASK', + 'AID3_XCC1_VF1_BASE_ADDR__AID3_XCC1_VF1_BASE_ADDR__SHIFT', + 'AID3_XCC1_VF2_BASE_ADDR__AID3_XCC1_VF2_BASE_ADDR_MASK', + 'AID3_XCC1_VF2_BASE_ADDR__AID3_XCC1_VF2_BASE_ADDR__SHIFT', + 'AID3_XCC1_VF3_BASE_ADDR__AID3_XCC1_VF3_BASE_ADDR_MASK', + 'AID3_XCC1_VF3_BASE_ADDR__AID3_XCC1_VF3_BASE_ADDR__SHIFT', + 'AID3_XCC1_VF4_BASE_ADDR__AID3_XCC1_VF4_BASE_ADDR_MASK', + 'AID3_XCC1_VF4_BASE_ADDR__AID3_XCC1_VF4_BASE_ADDR__SHIFT', + 'AID3_XCC1_VF5_BASE_ADDR__AID3_XCC1_VF5_BASE_ADDR_MASK', + 'AID3_XCC1_VF5_BASE_ADDR__AID3_XCC1_VF5_BASE_ADDR__SHIFT', + 'AID3_XCC1_VF6_BASE_ADDR__AID3_XCC1_VF6_BASE_ADDR_MASK', + 'AID3_XCC1_VF6_BASE_ADDR__AID3_XCC1_VF6_BASE_ADDR__SHIFT', + 'AID3_XCC1_VF7_BASE_ADDR__AID3_XCC1_VF7_BASE_ADDR_MASK', + 'AID3_XCC1_VF7_BASE_ADDR__AID3_XCC1_VF7_BASE_ADDR__SHIFT', + 'APML_CONTROL__APML_NMI_En_MASK', + 'APML_CONTROL__APML_NMI_En__SHIFT', + 'APML_CONTROL__APML_OutputDis_MASK', + 'APML_CONTROL__APML_OutputDis__SHIFT', + 'APML_CONTROL__APML_SyncFlood_En_MASK', + 'APML_CONTROL__APML_SyncFlood_En__SHIFT', + 'APML_STATUS__APML_Corr_MASK', 'APML_STATUS__APML_Corr__SHIFT', + 'APML_STATUS__APML_EgressPoisonErrHi_MASK', + 'APML_STATUS__APML_EgressPoisonErrHi__SHIFT', + 'APML_STATUS__APML_EgressPoisonErrLo_MASK', + 'APML_STATUS__APML_EgressPoisonErrLo__SHIFT', + 'APML_STATUS__APML_Fatal_MASK', 'APML_STATUS__APML_Fatal__SHIFT', + 'APML_STATUS__APML_IntPoisonErr_MASK', + 'APML_STATUS__APML_IntPoisonErr__SHIFT', + 'APML_STATUS__APML_NonFatal_MASK', + 'APML_STATUS__APML_NonFatal__SHIFT', + 'APML_STATUS__APML_Serr_MASK', 'APML_STATUS__APML_Serr__SHIFT', + 'APML_SW_STATUS__APML_NMI_STATUS_MASK', + 'APML_SW_STATUS__APML_NMI_STATUS__SHIFT', + 'APML_TRIGGER__APML_NMI_TRIGGER_MASK', + 'APML_TRIGGER__APML_NMI_TRIGGER__SHIFT', + 'BIFC_A2S_CNTL_CL0__BLKLVL_MAP_MASK', + 'BIFC_A2S_CNTL_CL0__BLKLVL_MAP__SHIFT', + 'BIFC_A2S_CNTL_CL0__DATERR_MAP_MASK', + 'BIFC_A2S_CNTL_CL0__DATERR_MAP__SHIFT', + 'BIFC_A2S_CNTL_CL0__EXOKAY_RD_MAP_MASK', + 'BIFC_A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT', + 'BIFC_A2S_CNTL_CL0__EXOKAY_WR_MAP_MASK', + 'BIFC_A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT', + 'BIFC_A2S_CNTL_CL0__NSNOOP_MAP_MASK', + 'BIFC_A2S_CNTL_CL0__NSNOOP_MAP__SHIFT', + 'BIFC_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP_MASK', + 'BIFC_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT', + 'BIFC_A2S_CNTL_CL0__REQPASSPW_VC0_MAP_MASK', + 'BIFC_A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT', + 'BIFC_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP_MASK', + 'BIFC_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT', + 'BIFC_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP_MASK', + 'BIFC_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT', + 'BIFC_A2S_CNTL_CL0__RESP_RD_MAP_MASK', + 'BIFC_A2S_CNTL_CL0__RESP_RD_MAP__SHIFT', + 'BIFC_A2S_CNTL_CL0__RESP_WR_MAP_MASK', + 'BIFC_A2S_CNTL_CL0__RESP_WR_MAP__SHIFT', + 'BIFC_A2S_CNTL_SW0__RDRSP_ERRMAP_MASK', + 'BIFC_A2S_CNTL_SW0__RDRSP_ERRMAP__SHIFT', + 'BIFC_A2S_CNTL_SW0__RDRSP_SEL_MODE_MASK', + 'BIFC_A2S_CNTL_SW0__RDRSP_SEL_MODE__SHIFT', + 'BIFC_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK', + 'BIFC_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT', + 'BIFC_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK', + 'BIFC_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT', + 'BIFC_A2S_CNTL_SW0__STATIC_VC_ENABLE_MASK', + 'BIFC_A2S_CNTL_SW0__STATIC_VC_ENABLE__SHIFT', + 'BIFC_A2S_CNTL_SW0__STATIC_VC_VALUE_MASK', + 'BIFC_A2S_CNTL_SW0__STATIC_VC_VALUE__SHIFT', + 'BIFC_A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK', + 'BIFC_A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT', + 'BIFC_A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK', + 'BIFC_A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT', + 'BIFC_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE_MASK', + 'BIFC_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE__SHIFT', + 'BIFC_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE_MASK', + 'BIFC_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT', + 'BIFC_A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK', + 'BIFC_A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT', + 'BIFC_A2S_MISC_CNTL__BYPASS_OVERRIDE_EN_MASK', + 'BIFC_A2S_MISC_CNTL__BYPASS_OVERRIDE_EN__SHIFT', + 'BIFC_A2S_MISC_CNTL__BYPASS_OVERRIDE_VALUE_MASK', + 'BIFC_A2S_MISC_CNTL__BYPASS_OVERRIDE_VALUE__SHIFT', + 'BIFC_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN_MASK', + 'BIFC_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN__SHIFT', + 'BIFC_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK', + 'BIFC_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT', + 'BIFC_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY_MASK', + 'BIFC_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY__SHIFT', + 'BIFC_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS_MASK', + 'BIFC_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT', + 'BIFC_A2S_MISC_CNTL__RD_TAG_SET_MIN_MASK', + 'BIFC_A2S_MISC_CNTL__RD_TAG_SET_MIN__SHIFT', + 'BIFC_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS_MASK', + 'BIFC_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT', + 'BIFC_A2S_MISC_CNTL__RSP_REORDER_DIS_MASK', + 'BIFC_A2S_MISC_CNTL__RSP_REORDER_DIS__SHIFT', + 'BIFC_A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK', + 'BIFC_A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT', + 'BIFC_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS_MASK', + 'BIFC_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT', + 'BIFC_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE_MASK', + 'BIFC_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE__SHIFT', + 'BIFC_A2S_MISC_CNTL__WRR_LRG_MODE_MASK', + 'BIFC_A2S_MISC_CNTL__WRR_LRG_MODE__SHIFT', + 'BIFC_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE_MASK', + 'BIFC_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE__SHIFT', + 'BIFC_A2S_MISC_CNTL__WR_TAG_SET_MIN_MASK', + 'BIFC_A2S_MISC_CNTL__WR_TAG_SET_MIN__SHIFT', + 'BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_DIS_MASK', + 'BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_DIS__SHIFT', + 'BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H_MASK', + 'BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H__SHIFT', + 'BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK', + 'BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT', + 'BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK', + 'BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT', + 'BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK', + 'BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT', + 'BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK', + 'BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT', + 'BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK', + 'BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT', + 'BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK', + 'BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT', + 'BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK', + 'BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT', + 'BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS_MASK', + 'BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS__SHIFT', + 'BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE_MASK', + 'BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE__SHIFT', + 'BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE_MASK', + 'BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE__SHIFT', + 'BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER_MASK', + 'BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT', + 'BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER_MASK', + 'BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT', + 'BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK', + 'BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT', + 'BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1_MASK', + 'BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT', + 'BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0_MASK', + 'BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0__SHIFT', + 'BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1_MASK', + 'BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1__SHIFT', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0_MASK', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0__SHIFT', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1_MASK', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1__SHIFT', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2_MASK', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2__SHIFT', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3_MASK', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3__SHIFT', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4_MASK', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4__SHIFT', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5_MASK', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5__SHIFT', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6_MASK', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6__SHIFT', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7_MASK', + 'BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK', + 'BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT', + 'BIFC_DOORBELL_ACCESS_EN_PF__BIFC_DOORBELL_ACCESS_EN_PF_MASK', + 'BIFC_DOORBELL_ACCESS_EN_PF__BIFC_DOORBELL_ACCESS_EN_PF__SHIFT', + 'BIFC_DOORBELL_ACCESS_EN_VF0__BIFC_DOORBELL_ACCESS_EN_VF0_MASK', + 'BIFC_DOORBELL_ACCESS_EN_VF0__BIFC_DOORBELL_ACCESS_EN_VF0__SHIFT', + 'BIFC_DOORBELL_ACCESS_EN_VF1__BIFC_DOORBELL_ACCESS_EN_VF1_MASK', + 'BIFC_DOORBELL_ACCESS_EN_VF1__BIFC_DOORBELL_ACCESS_EN_VF1__SHIFT', + 'BIFC_DOORBELL_ACCESS_EN_VF2__BIFC_DOORBELL_ACCESS_EN_VF2_MASK', + 'BIFC_DOORBELL_ACCESS_EN_VF2__BIFC_DOORBELL_ACCESS_EN_VF2__SHIFT', + 'BIFC_DOORBELL_ACCESS_EN_VF3__BIFC_DOORBELL_ACCESS_EN_VF3_MASK', + 'BIFC_DOORBELL_ACCESS_EN_VF3__BIFC_DOORBELL_ACCESS_EN_VF3__SHIFT', + 'BIFC_DOORBELL_ACCESS_EN_VF4__BIFC_DOORBELL_ACCESS_EN_VF4_MASK', + 'BIFC_DOORBELL_ACCESS_EN_VF4__BIFC_DOORBELL_ACCESS_EN_VF4__SHIFT', + 'BIFC_DOORBELL_ACCESS_EN_VF5__BIFC_DOORBELL_ACCESS_EN_VF5_MASK', + 'BIFC_DOORBELL_ACCESS_EN_VF5__BIFC_DOORBELL_ACCESS_EN_VF5__SHIFT', + 'BIFC_DOORBELL_ACCESS_EN_VF6__BIFC_DOORBELL_ACCESS_EN_VF6_MASK', + 'BIFC_DOORBELL_ACCESS_EN_VF6__BIFC_DOORBELL_ACCESS_EN_VF6__SHIFT', + 'BIFC_DOORBELL_ACCESS_EN_VF7__BIFC_DOORBELL_ACCESS_EN_VF7_MASK', + 'BIFC_DOORBELL_ACCESS_EN_VF7__BIFC_DOORBELL_ACCESS_EN_VF7__SHIFT', + 'BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK', + 'BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT', + 'BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK', + 'BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT', + 'BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK', + 'BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC_MASK', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC__SHIFT', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC_MASK', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC__SHIFT', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC_MASK', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC__SHIFT', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC_MASK', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC__SHIFT', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC_MASK', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC__SHIFT', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC_MASK', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC__SHIFT', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC_MASK', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC__SHIFT', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC_MASK', + 'BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC__SHIFT', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC_MASK', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC__SHIFT', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC_MASK', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC__SHIFT', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC_MASK', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC__SHIFT', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC_MASK', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC__SHIFT', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC_MASK', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC__SHIFT', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC_MASK', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC__SHIFT', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC_MASK', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC__SHIFT', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC_MASK', + 'BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC__SHIFT', + 'BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK', + 'BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT', + 'BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK', + 'BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT', + 'BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK', + 'BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT', + 'BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK', + 'BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT', + 'BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK', + 'BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT', + 'BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK', + 'BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT', + 'BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK', + 'BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT', + 'BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN_MASK', + 'BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN__SHIFT', + 'BIFC_GSI_CNTL__GSI_SMN_BURST_EN_MASK', + 'BIFC_GSI_CNTL__GSI_SMN_BURST_EN__SHIFT', + 'BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK_MASK', + 'BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK__SHIFT', + 'BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK', + 'BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT', + 'BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL_MASK', + 'BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL__SHIFT', + 'BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH_MASK', + 'BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH__SHIFT', + 'BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH_MASK', + 'BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH__SHIFT', + 'BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD_MASK', + 'BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD__SHIFT', + 'BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE_MASK', + 'BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE__SHIFT', + 'BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK', + 'BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT', + 'BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK', + 'BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT', + 'BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK', + 'BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT', + 'BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK', + 'BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT', + 'BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN_MASK', + 'BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN__SHIFT', + 'BIFC_HSTARB_CNTL__SLVARB_MODE_MASK', + 'BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT', + 'BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE_MASK', + 'BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE__SHIFT', + 'BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE_MASK', + 'BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE__SHIFT', + 'BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST_MASK', + 'BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST__SHIFT', + 'BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK', + 'BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT', + 'BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK', + 'BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT', + 'BIFC_MISC_CTRL0__DMA_ALL_RST_PROTECT_STS_SEL_MASK', + 'BIFC_MISC_CTRL0__DMA_ALL_RST_PROTECT_STS_SEL__SHIFT', + 'BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK', + 'BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT', + 'BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK', + 'BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT', + 'BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK', + 'BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT', + 'BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK', + 'BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT', + 'BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS_MASK', + 'BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS__SHIFT', + 'BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK', + 'BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT', + 'BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK', + 'BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT', + 'BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS_MASK', + 'BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS__SHIFT', + 'BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST_MASK', + 'BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST__SHIFT', + 'BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE_MASK', + 'BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE__SHIFT', + 'BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP_MASK', + 'BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP__SHIFT', + 'BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P_MASK', + 'BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P__SHIFT', + 'BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN_MASK', + 'BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN__SHIFT', + 'BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN_MASK', + 'BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN__SHIFT', + 'BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK', + 'BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT', + 'BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK', + 'BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT', + 'BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK', + 'BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT', + 'BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK', + 'BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT', + 'BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK', + 'BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT', + 'BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST_MASK', + 'BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST__SHIFT', + 'BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN_MASK', + 'BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT', + 'BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN_MASK', + 'BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT', + 'BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK', + 'BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK', + 'BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT', + 'BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT', + 'BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_MASK', + 'BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE_MASK', + 'BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE__SHIFT', + 'BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE__SHIFT', + 'BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK', + 'BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT', + 'BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK', + 'BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT', + 'BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK', + 'BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT', + 'BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK', + 'BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT', + 'BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP_MASK', + 'BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP__SHIFT', + 'BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG_MASK', + 'BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG__SHIFT', + 'BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK', + 'BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT', + 'BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK', + 'BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT', + 'BIFC_MISC_CTRL1__GMI_CPLBUF_EN_MASK', + 'BIFC_MISC_CTRL1__GMI_CPLBUF_EN__SHIFT', + 'BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK', + 'BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT', + 'BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK', + 'BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT', + 'BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK', + 'BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT', + 'BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK', + 'BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT', + 'BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK', + 'BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT', + 'BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK', + 'BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT', + 'BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK', + 'BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT', + 'BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK', + 'BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT', + 'BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK', + 'BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT', + 'BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK', + 'BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT', + 'BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK', + 'BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT', + 'BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK', + 'BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT', + 'BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK', + 'BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT', + 'BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK', + 'BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT', + 'BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK', + 'BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT', + 'BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK', + 'BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT', + 'BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0_MASK', + 'BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0__SHIFT', + 'BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1_MASK', + 'BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1__SHIFT', + 'BIFC_PASID_STS__PASID_STS_MASK', + 'BIFC_PASID_STS__PASID_STS__SHIFT', + 'BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK', + 'BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK', + 'BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK', + 'BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT', + 'BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT_MASK', + 'BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT__SHIFT', + 'BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT_MASK', + 'BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT__SHIFT', + 'BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT_MASK', + 'BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT__SHIFT', + 'BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT_MASK', + 'BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT__SHIFT', + 'BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT_MASK', + 'BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT__SHIFT', + 'BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT_MASK', + 'BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT__SHIFT', + 'BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT_MASK', + 'BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT__SHIFT', + 'BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT_MASK', + 'BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT__SHIFT', + 'BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK', + 'BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT', + 'BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK', + 'BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT', + 'BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0_MASK', + 'BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT', + 'BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1_MASK', + 'BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT', + 'BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK', + 'BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT', + 'BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK', + 'BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT', + 'BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK', + 'BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT', + 'BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK', + 'BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT', + 'BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN_MASK', + 'BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN__SHIFT', + 'BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK', + 'BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT', + 'BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK', + 'BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT', + 'BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK', + 'BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT', + 'BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK', + 'BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT', + 'BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK', + 'BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT', + 'BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK', + 'BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT', + 'BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P_MASK', + 'BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P__SHIFT', + 'BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK', + 'BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT', + 'BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H_MASK', + 'BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H__SHIFT', + 'BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H_MASK', + 'BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H__SHIFT', + 'BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H_MASK', + 'BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H__SHIFT', + 'BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_MASK', + 'BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS__SHIFT', + 'BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0_MASK', + 'BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT', + 'BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0_MASK', + 'BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT', + 'BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1_MASK', + 'BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT', + 'BIFC_THT_CNTL__THT_NTB_VC0_APER0_ADSC_PUSH_DIS_MASK', + 'BIFC_THT_CNTL__THT_NTB_VC0_APER0_ADSC_PUSH_DIS__SHIFT', + 'BIFC_THT_CNTL__THT_NTB_VC0_OTHAPER_ADSC_PUSH_DIS_MASK', + 'BIFC_THT_CNTL__THT_NTB_VC0_OTHAPER_ADSC_PUSH_DIS__SHIFT', + 'BIFC_THT_CNTL__THT_NTB_VC1_APER0_ADSC_PUSH_DIS_MASK', + 'BIFC_THT_CNTL__THT_NTB_VC1_APER0_ADSC_PUSH_DIS__SHIFT', + 'BIFC_THT_CNTL__THT_NTB_VC1_OTHAPER_ADSC_PUSH_DIS_MASK', + 'BIFC_THT_CNTL__THT_NTB_VC1_OTHAPER_ADSC_PUSH_DIS__SHIFT', + 'BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN_MASK', + 'BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1__SHIFT', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK', + 'BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT', + 'BIF_BX0_BACO_CNTL__BACO_AUTO_EXIT_MASK', + 'BIF_BX0_BACO_CNTL__BACO_AUTO_EXIT__SHIFT', + 'BIF_BX0_BACO_CNTL__BACO_DSTATE_BYPASS_MASK', + 'BIF_BX0_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT', + 'BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK', + 'BIF_BX0_BACO_CNTL__BACO_DUMMY_EN__SHIFT', + 'BIF_BX0_BACO_CNTL__BACO_EN_MASK', + 'BIF_BX0_BACO_CNTL__BACO_EN__SHIFT', + 'BIF_BX0_BACO_CNTL__BACO_MODE_MASK', + 'BIF_BX0_BACO_CNTL__BACO_MODE__SHIFT', + 'BIF_BX0_BACO_CNTL__BACO_POWER_OFF_MASK', + 'BIF_BX0_BACO_CNTL__BACO_POWER_OFF__SHIFT', + 'BIF_BX0_BACO_CNTL__BACO_RST_INTR_MASK_MASK', + 'BIF_BX0_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT', + 'BIF_BX0_BACO_CNTL__PWRGOOD_VDDSOC_MASK', + 'BIF_BX0_BACO_CNTL__PWRGOOD_VDDSOC__SHIFT', + 'BIF_BX0_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK', + 'BIF_BX0_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT', + 'BIF_BX0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK', + 'BIF_BX0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT', + 'BIF_BX0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK', + 'BIF_BX0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT', + 'BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK', + 'BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT', + 'BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK', + 'BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT', + 'BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK', + 'BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT', + 'BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK', + 'BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT', + 'BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK', + 'BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT', + 'BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK', + 'BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT', + 'BIF_BX0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK', + 'BIF_BX0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT', + 'BIF_BX0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK', + 'BIF_BX0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT', + 'BIF_BX0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK', + 'BIF_BX0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT', + 'BIF_BX0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK', + 'BIF_BX0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT', + 'BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK', + 'BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT', + 'BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK', + 'BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT', + 'BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK', + 'BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT', + 'BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK', + 'BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT', + 'BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK', + 'BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT', + 'BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK', + 'BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT', + 'BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK', + 'BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT', + 'BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK', + 'BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT', + 'BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK', + 'BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK', + 'BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT', + 'BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK', + 'BIF_BX0_BIF_FB_EN__FB_READ_EN__SHIFT', + 'BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK', + 'BIF_BX0_BIF_FB_EN__FB_WRITE_EN__SHIFT', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS_MASK', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS__SHIFT', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK', + 'BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT', + 'BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK', + 'BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT', + 'BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK', + 'BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT', + 'BIF_BX0_BIF_MM_INDACCESS_CNTL__WRITE_DIS_MASK', + 'BIF_BX0_BIF_MM_INDACCESS_CNTL__WRITE_DIS__SHIFT', + 'BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK', + 'BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT', + 'BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK', + 'BIF_BX0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT', + 'BIF_BX0_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK', + 'BIF_BX0_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT', + 'BIF_BX0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK', + 'BIF_BX0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT', + 'BIF_BX0_BIF_RB_BASE__ADDR_MASK', + 'BIF_BX0_BIF_RB_BASE__ADDR__SHIFT', + 'BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN_MASK', + 'BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT', + 'BIF_BX0_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL_MASK', + 'BIF_BX0_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL__SHIFT', + 'BIF_BX0_BIF_RB_CNTL__RB_ENABLE_MASK', + 'BIF_BX0_BIF_RB_CNTL__RB_ENABLE__SHIFT', + 'BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK', + 'BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT', + 'BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK', + 'BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT', + 'BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK', + 'BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT', + 'BIF_BX0_BIF_RB_CNTL__RB_SIZE_MASK', + 'BIF_BX0_BIF_RB_CNTL__RB_SIZE__SHIFT', + 'BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK', + 'BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT', + 'BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK', + 'BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT', + 'BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK', + 'BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT', + 'BIF_BX0_BIF_RB_RPTR__OFFSET_MASK', + 'BIF_BX0_BIF_RB_RPTR__OFFSET__SHIFT', + 'BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR_MASK', + 'BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT', + 'BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR_MASK', + 'BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT', + 'BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK', + 'BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT', + 'BIF_BX0_BIF_RB_WPTR__OFFSET_MASK', + 'BIF_BX0_BIF_RB_WPTR__OFFSET__SHIFT', + 'BIF_BX0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK', + 'BIF_BX0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT', + 'BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0_MASK', + 'BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT', + 'BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1_MASK', + 'BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT', + 'BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK', + 'BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK', + 'BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK', + 'BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK', + 'BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK', + 'BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK', + 'BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK', + 'BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK', + 'BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK', + 'BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK', + 'BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK', + 'BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK', + 'BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK', + 'BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK', + 'BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK', + 'BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT', + 'BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK', + 'BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT', + 'BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK', + 'BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT', + 'BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK', + 'BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT', + 'BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK', + 'BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT', + 'BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK', + 'BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT', + 'BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK', + 'BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT', + 'BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK', + 'BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT', + 'BIF_BX0_BUS_CNTL__RD_STALL_IO_WR_MASK', + 'BIF_BX0_BUS_CNTL__RD_STALL_IO_WR__SHIFT', + 'BIF_BX0_BUS_CNTL__SET_AZ_TC_MASK', + 'BIF_BX0_BUS_CNTL__SET_AZ_TC__SHIFT', + 'BIF_BX0_BUS_CNTL__SET_MC_TC_MASK', + 'BIF_BX0_BUS_CNTL__SET_MC_TC__SHIFT', + 'BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK', + 'BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT', + 'BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK', + 'BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT', + 'BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK', + 'BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT', + 'BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK', + 'BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT', + 'BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN_MASK', + 'BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN__SHIFT', + 'BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN_MASK', + 'BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN__SHIFT', + 'BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN_MASK', + 'BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT', + 'BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK', + 'BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT', + 'BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK', + 'BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK', + 'BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK', + 'BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK', + 'BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK', + 'BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK', + 'BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK', + 'BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK', + 'BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK', + 'BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK', + 'BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK', + 'BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK', + 'BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK', + 'BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK', + 'BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK', + 'BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK', + 'BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK', + 'BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT', + 'BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK', + 'BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT', + 'BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0_MASK', + 'BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT', + 'BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10_MASK', + 'BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT', + 'BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11_MASK', + 'BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT', + 'BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12_MASK', + 'BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT', + 'BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13_MASK', + 'BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT', + 'BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14_MASK', + 'BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT', + 'BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15_MASK', + 'BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT', + 'BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1_MASK', + 'BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT', + 'BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2_MASK', + 'BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT', + 'BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3_MASK', + 'BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT', + 'BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4_MASK', + 'BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT', + 'BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5_MASK', + 'BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT', + 'BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6_MASK', + 'BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT', + 'BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7_MASK', + 'BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT', + 'BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8_MASK', + 'BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT', + 'BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9_MASK', + 'BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT', + 'BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK', + 'BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT', + 'BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK', + 'BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT', + 'BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK', + 'BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT', + 'BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK', + 'BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT', + 'BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK', + 'BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT', + 'BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK', + 'BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT', + 'BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK', + 'BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT', + 'BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK', + 'BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT', + 'BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK', + 'BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT', + 'BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK', + 'BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT', + 'BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK', + 'BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT', + 'BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK', + 'BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT', + 'BIF_BX0_MAILBOX_INDEX__MAILBOX_INDEX_MASK', + 'BIF_BX0_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT', + 'BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK', + 'BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT', + 'BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK', + 'BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT', + 'BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK', + 'BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT', + 'BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK', + 'BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK', + 'BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT', + 'BIF_BX0_PCIE_DATA2__PCIE_DATA2_MASK', + 'BIF_BX0_PCIE_DATA2__PCIE_DATA2__SHIFT', + 'BIF_BX0_PCIE_DATA__PCIE_DATA_MASK', + 'BIF_BX0_PCIE_DATA__PCIE_DATA__SHIFT', + 'BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK', + 'BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT', + 'BIF_BX0_PCIE_INDEX2__PCIE_INDEX2_MASK', + 'BIF_BX0_PCIE_INDEX2__PCIE_INDEX2__SHIFT', + 'BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK', + 'BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT', + 'BIF_BX0_PCIE_INDEX__PCIE_INDEX_MASK', + 'BIF_BX0_PCIE_INDEX__PCIE_INDEX__SHIFT', + 'BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK', + 'BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT', + 'BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK', + 'BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK', + 'BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK', + 'BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK', + 'BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK', + 'BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK', + 'BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK', + 'BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK', + 'BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK', + 'BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK', + 'BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK', + 'BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK', + 'BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK', + 'BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK', + 'BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK', + 'BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK', + 'BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT', + 'BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK', + 'BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT', + 'BIF_BX1_BACO_CNTL__BACO_AUTO_EXIT_MASK', + 'BIF_BX1_BACO_CNTL__BACO_AUTO_EXIT__SHIFT', + 'BIF_BX1_BACO_CNTL__BACO_DSTATE_BYPASS_MASK', + 'BIF_BX1_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT', + 'BIF_BX1_BACO_CNTL__BACO_DUMMY_EN_MASK', + 'BIF_BX1_BACO_CNTL__BACO_DUMMY_EN__SHIFT', + 'BIF_BX1_BACO_CNTL__BACO_EN_MASK', + 'BIF_BX1_BACO_CNTL__BACO_EN__SHIFT', + 'BIF_BX1_BACO_CNTL__BACO_MODE_MASK', + 'BIF_BX1_BACO_CNTL__BACO_MODE__SHIFT', + 'BIF_BX1_BACO_CNTL__BACO_POWER_OFF_MASK', + 'BIF_BX1_BACO_CNTL__BACO_POWER_OFF__SHIFT', + 'BIF_BX1_BACO_CNTL__BACO_RST_INTR_MASK_MASK', + 'BIF_BX1_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT', + 'BIF_BX1_BACO_CNTL__PWRGOOD_VDDSOC_MASK', + 'BIF_BX1_BACO_CNTL__PWRGOOD_VDDSOC__SHIFT', + 'BIF_BX1_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK', + 'BIF_BX1_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT', + 'BIF_BX1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK', + 'BIF_BX1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT', + 'BIF_BX1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK', + 'BIF_BX1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT', + 'BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK', + 'BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT', + 'BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK', + 'BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT', + 'BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK', + 'BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT', + 'BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK', + 'BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT', + 'BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK', + 'BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT', + 'BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK', + 'BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT', + 'BIF_BX1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK', + 'BIF_BX1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT', + 'BIF_BX1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK', + 'BIF_BX1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT', + 'BIF_BX1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK', + 'BIF_BX1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT', + 'BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK', + 'BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT', + 'BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK', + 'BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT', + 'BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK', + 'BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT', + 'BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK', + 'BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT', + 'BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK', + 'BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT', + 'BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK', + 'BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT', + 'BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK', + 'BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT', + 'BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK', + 'BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT', + 'BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK', + 'BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT', + 'BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK', + 'BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK', + 'BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT', + 'BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK', + 'BIF_BX1_BIF_FB_EN__FB_READ_EN__SHIFT', + 'BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK', + 'BIF_BX1_BIF_FB_EN__FB_WRITE_EN__SHIFT', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS_MASK', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS__SHIFT', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK', + 'BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT', + 'BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK', + 'BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT', + 'BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK', + 'BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT', + 'BIF_BX1_BIF_MM_INDACCESS_CNTL__WRITE_DIS_MASK', + 'BIF_BX1_BIF_MM_INDACCESS_CNTL__WRITE_DIS__SHIFT', + 'BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK', + 'BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT', + 'BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK', + 'BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT', + 'BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK', + 'BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT', + 'BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK', + 'BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT', + 'BIF_BX1_BIF_RB_BASE__ADDR_MASK', + 'BIF_BX1_BIF_RB_BASE__ADDR__SHIFT', + 'BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN_MASK', + 'BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT', + 'BIF_BX1_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL_MASK', + 'BIF_BX1_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL__SHIFT', + 'BIF_BX1_BIF_RB_CNTL__RB_ENABLE_MASK', + 'BIF_BX1_BIF_RB_CNTL__RB_ENABLE__SHIFT', + 'BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK', + 'BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT', + 'BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK', + 'BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT', + 'BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK', + 'BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT', + 'BIF_BX1_BIF_RB_CNTL__RB_SIZE_MASK', + 'BIF_BX1_BIF_RB_CNTL__RB_SIZE__SHIFT', + 'BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK', + 'BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT', + 'BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK', + 'BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT', + 'BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK', + 'BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT', + 'BIF_BX1_BIF_RB_RPTR__OFFSET_MASK', + 'BIF_BX1_BIF_RB_RPTR__OFFSET__SHIFT', + 'BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR_MASK', + 'BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT', + 'BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR_MASK', + 'BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT', + 'BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK', + 'BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT', + 'BIF_BX1_BIF_RB_WPTR__OFFSET_MASK', + 'BIF_BX1_BIF_RB_WPTR__OFFSET__SHIFT', + 'BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK', + 'BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT', + 'BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0_MASK', + 'BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT', + 'BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1_MASK', + 'BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT', + 'BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE_MASK', + 'BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE__SHIFT', + 'BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE_MASK', + 'BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK', + 'BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK', + 'BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK', + 'BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK', + 'BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK', + 'BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK', + 'BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK', + 'BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK', + 'BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK', + 'BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK', + 'BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK', + 'BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK', + 'BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK', + 'BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK', + 'BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK', + 'BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT', + 'BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK', + 'BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT', + 'BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK', + 'BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT', + 'BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK', + 'BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT', + 'BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK', + 'BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT', + 'BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK', + 'BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT', + 'BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK', + 'BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT', + 'BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK', + 'BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT', + 'BIF_BX1_BUS_CNTL__RD_STALL_IO_WR_MASK', + 'BIF_BX1_BUS_CNTL__RD_STALL_IO_WR__SHIFT', + 'BIF_BX1_BUS_CNTL__SET_AZ_TC_MASK', + 'BIF_BX1_BUS_CNTL__SET_AZ_TC__SHIFT', + 'BIF_BX1_BUS_CNTL__SET_MC_TC_MASK', + 'BIF_BX1_BUS_CNTL__SET_MC_TC__SHIFT', + 'BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK', + 'BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT', + 'BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK', + 'BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT', + 'BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK', + 'BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT', + 'BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK', + 'BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT', + 'BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN_MASK', + 'BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN__SHIFT', + 'BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN_MASK', + 'BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN__SHIFT', + 'BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN_MASK', + 'BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT', + 'BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK', + 'BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT', + 'BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK', + 'BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK', + 'BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK', + 'BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK', + 'BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK', + 'BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK', + 'BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK', + 'BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK', + 'BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK', + 'BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK', + 'BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK', + 'BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK', + 'BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK', + 'BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK', + 'BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK', + 'BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK', + 'BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK', + 'BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT', + 'BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK', + 'BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT', + 'BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0_MASK', + 'BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT', + 'BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10_MASK', + 'BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT', + 'BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11_MASK', + 'BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT', + 'BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12_MASK', + 'BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT', + 'BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13_MASK', + 'BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT', + 'BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14_MASK', + 'BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT', + 'BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15_MASK', + 'BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT', + 'BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1_MASK', + 'BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT', + 'BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2_MASK', + 'BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT', + 'BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3_MASK', + 'BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT', + 'BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4_MASK', + 'BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT', + 'BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5_MASK', + 'BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT', + 'BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6_MASK', + 'BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT', + 'BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7_MASK', + 'BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT', + 'BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8_MASK', + 'BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT', + 'BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9_MASK', + 'BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT', + 'BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK', + 'BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT', + 'BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK', + 'BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT', + 'BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK', + 'BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT', + 'BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK', + 'BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT', + 'BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK', + 'BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT', + 'BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK', + 'BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT', + 'BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK', + 'BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT', + 'BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK', + 'BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT', + 'BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK', + 'BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT', + 'BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK', + 'BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT', + 'BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK', + 'BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT', + 'BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK', + 'BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT', + 'BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX_MASK', + 'BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT', + 'BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK', + 'BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT', + 'BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK', + 'BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT', + 'BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK', + 'BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT', + 'BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK', + 'BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK', + 'BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT', + 'BIF_BX1_PCIE_DATA2__PCIE_DATA2_MASK', + 'BIF_BX1_PCIE_DATA2__PCIE_DATA2__SHIFT', + 'BIF_BX1_PCIE_DATA__PCIE_DATA_MASK', + 'BIF_BX1_PCIE_DATA__PCIE_DATA__SHIFT', + 'BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK', + 'BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT', + 'BIF_BX1_PCIE_INDEX2__PCIE_INDEX2_MASK', + 'BIF_BX1_PCIE_INDEX2__PCIE_INDEX2__SHIFT', + 'BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK', + 'BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT', + 'BIF_BX1_PCIE_INDEX__PCIE_INDEX_MASK', + 'BIF_BX1_PCIE_INDEX__PCIE_INDEX__SHIFT', + 'BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK', + 'BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT', + 'BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK', + 'BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK', + 'BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK', + 'BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK', + 'BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK', + 'BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK', + 'BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK', + 'BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK', + 'BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK', + 'BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK', + 'BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK', + 'BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK', + 'BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK', + 'BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK', + 'BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK', + 'BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK', + 'BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT', + 'BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK', + 'BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9__SHIFT', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS_MASK', + 'BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8__SHIFT', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9_MASK', + 'BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF0_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF0__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF10_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF10__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF11_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF11__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF12_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF12__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF13_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF13__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF14_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF14__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF15_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF15__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF16_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF16__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF17_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF17__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF18_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF18__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF19_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF19__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF1_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF1__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF20_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF20__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF21_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF21__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF22_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF22__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF23_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF23__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF24_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF24__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF25_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF25__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF26_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF26__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF27_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF27__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF28_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF28__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF29_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF29__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF2_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF2__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF30_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF30__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF3_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF3__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF4_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF4__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF5_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF5__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF6_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF6__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF7_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF7__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF8_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF8__SHIFT', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF9_MASK', + 'BIF_BX1_VF_FB_EN__VF_FB_EN_VF9__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8__SHIFT', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9_MASK', + 'BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8__SHIFT', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9_MASK', + 'BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8__SHIFT', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9_MASK', + 'BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF0_MM_DATA__MM_DATA_MASK', + 'BIF_BX_PF0_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_PF0_MM_INDEX__MM_APER_MASK', + 'BIF_BX_PF0_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_PF0_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_PF0_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK', + 'BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT', + 'BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK', + 'BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT', + 'BIF_BX_PF0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK', + 'BIF_BX_PF0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT', + 'BIF_BX_PF0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK', + 'BIF_BX_PF0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT', + 'BIF_BX_PF0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK', + 'BIF_BX_PF0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT', + 'BIF_BX_PF0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK', + 'BIF_BX_PF0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT', + 'BIF_BX_PF0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK', + 'BIF_BX_PF0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT', + 'BIF_BX_PF0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK', + 'BIF_BX_PF0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT', + 'BIF_BX_PF0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK', + 'BIF_BX_PF0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT', + 'BIF_BX_PF0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK', + 'BIF_BX_PF0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT', + 'BIF_BX_PF0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK', + 'BIF_BX_PF0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT', + 'BIF_BX_PF0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK', + 'BIF_BX_PF0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT', + 'BIF_BX_PF0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK', + 'BIF_BX_PF0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT', + 'BIF_BX_PF0_PARTITION_MEM_STATUS__CHANGE_STATUE_MASK', + 'BIF_BX_PF0_PARTITION_MEM_STATUS__CHANGE_STATUE__SHIFT', + 'BIF_BX_PF0_PARTITION_MEM_STATUS__NPS_MODE_MASK', + 'BIF_BX_PF0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT', + 'BIF_BX_PF0_RSMU_DATA__RSMU_DATA_MASK', + 'BIF_BX_PF0_RSMU_DATA__RSMU_DATA__SHIFT', + 'BIF_BX_PF0_RSMU_INDEX_HI__RSMU_INDEX_HI_MASK', + 'BIF_BX_PF0_RSMU_INDEX_HI__RSMU_INDEX_HI__SHIFT', + 'BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX_MASK', + 'BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX__SHIFT', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK', + 'BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT', + 'BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK', + 'BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK', + 'BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT', + 'BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK', + 'BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT', + 'BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK', + 'BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK', + 'BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT', + 'BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK', + 'BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT', + 'BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK', + 'BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT', + 'BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK', + 'BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT', + 'BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK', + 'BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT', + 'BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK', + 'BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK', + 'BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT', + 'BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK', + 'BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT', + 'BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK', + 'BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT', + 'BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK', + 'BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT', + 'BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK', + 'BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT', + 'BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK', + 'BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT', + 'BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK', + 'BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT', + 'BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK', + 'BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT', + 'BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK', + 'BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT', + 'BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK', + 'BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT', + 'BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK', + 'BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT', + 'BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK', + 'BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK', + 'BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK', + 'BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK', + 'BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT', + 'BIF_BX_PF1_MM_DATA__MM_DATA_MASK', + 'BIF_BX_PF1_MM_DATA__MM_DATA__SHIFT', + 'BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI_MASK', + 'BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT', + 'BIF_BX_PF1_MM_INDEX__MM_APER_MASK', + 'BIF_BX_PF1_MM_INDEX__MM_APER__SHIFT', + 'BIF_BX_PF1_MM_INDEX__MM_OFFSET_MASK', + 'BIF_BX_PF1_MM_INDEX__MM_OFFSET__SHIFT', + 'BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK', + 'BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT', + 'BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK', + 'BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT', + 'BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK', + 'BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT', + 'BIF_BX_PF1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK', + 'BIF_BX_PF1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT', + 'BIF_BX_PF1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK', + 'BIF_BX_PF1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT', + 'BIF_BX_PF1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK', + 'BIF_BX_PF1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT', + 'BIF_BX_PF1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK', + 'BIF_BX_PF1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT', + 'BIF_BX_PF1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK', + 'BIF_BX_PF1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT', + 'BIF_BX_PF1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK', + 'BIF_BX_PF1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT', + 'BIF_BX_PF1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK', + 'BIF_BX_PF1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT', + 'BIF_BX_PF1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK', + 'BIF_BX_PF1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT', + 'BIF_BX_PF1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK', + 'BIF_BX_PF1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT', + 'BIF_BX_PF1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK', + 'BIF_BX_PF1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT', + 'BIF_BX_PF1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK', + 'BIF_BX_PF1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT', + 'BIF_BX_PF1_PARTITION_MEM_STATUS__CHANGE_STATUE_MASK', + 'BIF_BX_PF1_PARTITION_MEM_STATUS__CHANGE_STATUE__SHIFT', + 'BIF_BX_PF1_PARTITION_MEM_STATUS__NPS_MODE_MASK', + 'BIF_BX_PF1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK', + 'BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK', + 'BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK', + 'BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_CMD_COMPLETE_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_CMD_COMPLETE_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_NEED_FLR_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_NEED_FLR_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_CMD_COMPLETE_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_CMD_COMPLETE_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_NEED_FLR_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_NEED_FLR_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_CMD_COMPLETE_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_CMD_COMPLETE_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_NEED_FLR_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_NEED_FLR_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_CMD_COMPLETE_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_CMD_COMPLETE_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_NEED_FLR_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_NEED_FLR_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_CMD_COMPLETE_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_CMD_COMPLETE_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_NEED_FLR_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_NEED_FLR_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_CMD_COMPLETE_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_CMD_COMPLETE_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_NEED_FLR_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_NEED_FLR_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_CMD_COMPLETE_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_CMD_COMPLETE_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_NEED_FLR_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_NEED_FLR_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_CMD_COMPLETE_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_CMD_COMPLETE_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_NEED_FLR_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_NEED_FLR_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_CMD_COMPLETE_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_NEED_FLR_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_CMD_COMPLETE_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_NEED_FLR_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_CMD_COMPLETE_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_NEED_FLR_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_CMD_COMPLETE_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_NEED_FLR_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_CMD_COMPLETE_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_NEED_FLR_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_CMD_COMPLETE_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_NEED_FLR_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_CMD_COMPLETE_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_NEED_FLR_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_CMD_COMPLETE_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_NEED_FLR_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_CMD_COMPLETE_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_CMD_COMPLETE_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_NEED_FLR_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_NEED_FLR_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_CMD_COMPLETE_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_CMD_COMPLETE_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_NEED_FLR_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_NEED_FLR_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_CMD_COMPLETE_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_CMD_COMPLETE_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_NEED_FLR_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_NEED_FLR_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_CMD_COMPLETE_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_CMD_COMPLETE_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_NEED_FLR_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_NEED_FLR_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_CMD_COMPLETE_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_CMD_COMPLETE_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_NEED_FLR_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_NEED_FLR_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_CMD_COMPLETE_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_CMD_COMPLETE_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_NEED_FLR_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_NEED_FLR_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_CMD_COMPLETE_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_CMD_COMPLETE_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_NEED_FLR_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_NEED_FLR_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_CMD_COMPLETE_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_CMD_COMPLETE_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_NEED_FLR_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_NEED_FLR_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_CMD_COMPLETE_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_NEED_FLR_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_CMD_COMPLETE_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_NEED_FLR_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_CMD_COMPLETE_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_NEED_FLR_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_CMD_COMPLETE_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_NEED_FLR_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_CMD_COMPLETE_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_NEED_FLR_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_CMD_COMPLETE_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_NEED_FLR_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_CMD_COMPLETE_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_NEED_FLR_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_CMD_COMPLETE_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_NEED_FLR_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_CMD_COMPLETE_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_CMD_COMPLETE_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_NEED_FLR_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_NEED_FLR_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_CMD_COMPLETE_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_CMD_COMPLETE_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_NEED_FLR_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_NEED_FLR_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_CMD_COMPLETE_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_CMD_COMPLETE_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_NEED_FLR_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_NEED_FLR_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_CMD_COMPLETE_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_CMD_COMPLETE_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_NEED_FLR_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_NEED_FLR_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_CMD_COMPLETE_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_NEED_FLR_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_CMD_COMPLETE_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_NEED_FLR_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_CMD_COMPLETE_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_NEED_FLR_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_CMD_COMPLETE_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_NEED_FLR_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0__DW0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0__DW0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1__DW1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1__DW1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2__DW2_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2__DW2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3__DW3_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3__DW3__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4__DW4_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4__DW4__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5__DW5_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5__DW5__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6__DW6_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6__DW6__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7__DW7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7__DW7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8__DW8_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8__DW8__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0__DW0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0__DW0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1__DW1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1__DW1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2__DW2_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2__DW2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3__DW3_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3__DW3__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4__DW4_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4__DW4__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5__DW5_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5__DW5__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6__DW6_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6__DW6__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7__DW7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7__DW7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8__DW8_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8__DW8__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0__DW0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0__DW0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1__DW1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1__DW1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2__DW2_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2__DW2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3__DW3_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3__DW3__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4__DW4_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4__DW4__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5__DW5_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5__DW5__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6__DW6_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6__DW6__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7__DW7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7__DW7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8__DW8_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8__DW8__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0__DW0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0__DW0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1__DW1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1__DW1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2__DW2_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2__DW2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3__DW3_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3__DW3__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4__DW4_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4__DW4__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5__DW5_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5__DW5__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6__DW6_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6__DW6__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7__DW7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7__DW7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8__DW8_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8__DW8__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0__DW0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0__DW0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1__DW1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1__DW1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2__DW2_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2__DW2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3__DW3_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3__DW3__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4__DW4_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4__DW4__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5__DW5_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5__DW5__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6__DW6_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6__DW6__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7__DW7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7__DW7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8__DW8_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8__DW8__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0__DW0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0__DW0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1__DW1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1__DW1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2__DW2_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2__DW2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3__DW3_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3__DW3__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4__DW4_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4__DW4__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5__DW5_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5__DW5__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6__DW6_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6__DW6__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7__DW7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7__DW7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8__DW8_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8__DW8__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0__DW0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0__DW0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1__DW1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1__DW1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2__DW2_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2__DW2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3__DW3_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3__DW3__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4__DW4_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4__DW4__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5__DW5_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5__DW5__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6__DW6_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6__DW6__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7__DW7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7__DW7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8__DW8_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8__DW8__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0__DW0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0__DW0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1__DW1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1__DW1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2__DW2_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2__DW2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3__DW3_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3__DW3__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4__DW4_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4__DW4__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5__DW5_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5__DW5__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6__DW6_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6__DW6__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7__DW7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7__DW7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8__DW8_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8__DW8__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN4SCH_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN4SCH_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN5SCH_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN5SCH_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN6SCH_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN6SCH_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN7SCH_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN7SCH_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN10SCH_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN10SCH_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN11SCH_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN11SCH_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN8SCH_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN8SCH_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN9SCH_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN9SCH_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX0SCH_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX0SCH_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX1SCH_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX1SCH_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX2SCH_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX2SCH_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX3SCH_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX3SCH_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX4SCH_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX4SCH_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX5SCH_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX5SCH_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX6SCH_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX6SCH_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX7SCH_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX7SCH_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN2SCH_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN2SCH_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN3SCH_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN3SCH_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0__DW0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0__DW0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1__DW1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1__DW1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2__DW2_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2__DW2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3__DW3_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3__DW3__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4__DW4_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4__DW4__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5__DW5_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5__DW5__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6__DW6_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6__DW6__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7__DW7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7__DW7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8__DW8_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8__DW8__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0__DW0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0__DW0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1__DW1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1__DW1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2__DW2_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2__DW2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3__DW3_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3__DW3__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4__DW4_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4__DW4__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5__DW5_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5__DW5__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6__DW6_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6__DW6__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7__DW7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7__DW7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8__DW8_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8__DW8__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0__DW0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0__DW0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1__DW1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1__DW1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2__DW2_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2__DW2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3__DW3_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3__DW3__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4__DW4_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4__DW4__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5__DW5_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5__DW5__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6__DW6_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6__DW6__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7__DW7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7__DW7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8__DW8_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8__DW8__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0__DW0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0__DW0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1__DW1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1__DW1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2__DW2_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2__DW2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3__DW3_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3__DW3__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4__DW4_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4__DW4__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5__DW5_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5__DW5__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6__DW6_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6__DW6__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7__DW7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7__DW7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8__DW8_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8__DW8__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0__DW0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0__DW0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1__DW1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1__DW1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2__DW2_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2__DW2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3__DW3_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3__DW3__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4__DW4_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4__DW4__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5__DW5_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5__DW5__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6__DW6_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6__DW6__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7__DW7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7__DW7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8__DW8_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8__DW8__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0__DW0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0__DW0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1__DW1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1__DW1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2__DW2_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2__DW2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3__DW3_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3__DW3__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4__DW4_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4__DW4__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5__DW5_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5__DW5__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6__DW6_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6__DW6__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7__DW7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7__DW7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8__DW8_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8__DW8__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0__DW0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0__DW0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1__DW1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1__DW1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2__DW2_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2__DW2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3__DW3_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3__DW3__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4__DW4_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4__DW4__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5__DW5_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5__DW5__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6__DW6_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6__DW6__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7__DW7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7__DW7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8__DW8_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8__DW8__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0__DW0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0__DW0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1__DW1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1__DW1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2__DW2_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2__DW2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3__DW3_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3__DW3__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4__DW4_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4__DW4__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5__DW5_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5__DW5__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6__DW6_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6__DW6__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7__DW7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7__DW7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8__DW8_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8__DW8__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0__DW0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0__DW0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1__DW1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1__DW1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2__DW2_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2__DW2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3__DW3_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3__DW3__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4__DW4_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4__DW4__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5__DW5_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5__DW5__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6__DW6_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6__DW6__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7__DW7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7__DW7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8__DW8_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8__DW8__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0__DW0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0__DW0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1__DW1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1__DW1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2__DW2_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2__DW2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3__DW3_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3__DW3__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4__DW4_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4__DW4__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5__DW5_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5__DW5__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6__DW6_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6__DW6__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7__DW7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7__DW7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8__DW8_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8__DW8__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0__DW0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0__DW0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1__DW1_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1__DW1__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2__DW2_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2__DW2__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3__DW3_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3__DW3__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4__DW4_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4__DW4__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5__DW5_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5__DW5__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6__DW6_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6__DW6__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7__DW7_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7__DW7__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8__DW8_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8__DW8__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK', + 'BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT', + 'BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK', + 'BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT', + 'BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK', + 'BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT', + 'BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK', + 'BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT', + 'BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__STU_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__STU__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__ATC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__STU_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__STU__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__ATC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__STU_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__STU__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__ATC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__STU_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__STU__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__ATC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__STU_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__STU__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__ATC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__STU_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__STU__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__ATC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__STU_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__STU__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__ATC_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__STU_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__STU__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK', + 'BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF1_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_EPF1_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_EPF1_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_EPF1_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT_MASK', + 'BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT__SHIFT', + 'BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT_MASK', + 'BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN_MASK', + 'BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR_MASK', + 'BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK', + 'BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT', + 'BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING_MASK', + 'BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH_MASK', + 'BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH__SHIFT', + 'BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_RC0_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_RC0_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_RC0_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_RC0_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_RC0_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK', + 'BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK', + 'BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT', + 'BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK', + 'BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_MASK', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK', + 'BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK', + 'BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT', + 'BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK', + 'BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT', + 'BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK', + 'BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT', + 'BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK', + 'BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT', + 'BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK', + 'BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT', + 'BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT_MASK', + 'BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK_MASK', + 'BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_RC0_PMI_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN_MASK', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK', + 'BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT', + 'BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK', + 'BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT', + 'BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK', + 'BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK', + 'BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT', + 'BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK', + 'BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT', + 'BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK', + 'BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT', + 'BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK', + 'BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK', + 'BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING_MASK', + 'BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING__SHIFT', + 'BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK', + 'BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__INBAND_PD_DISABLE_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__INBAND_PD_DISABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK', + 'BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT', + 'BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK', + 'BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT', + 'BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK', + 'BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT', + 'BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK', + 'BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT', + 'BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS_MASK', + 'BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS__SHIFT', + 'BIF_CFG_DEV0_RC_BIST__BIST_CAP_MASK', + 'BIF_CFG_DEV0_RC_BIST__BIST_CAP__SHIFT', + 'BIF_CFG_DEV0_RC_BIST__BIST_COMP_MASK', + 'BIF_CFG_DEV0_RC_BIST__BIST_COMP__SHIFT', + 'BIF_CFG_DEV0_RC_BIST__BIST_STRT_MASK', + 'BIF_CFG_DEV0_RC_BIST__BIST_STRT__SHIFT', + 'BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE_MASK', + 'BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE__SHIFT', + 'BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR_MASK', + 'BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR__SHIFT', + 'BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING_MASK', + 'BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING__SHIFT', + 'BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN_MASK', + 'BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN__SHIFT', + 'BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN_MASK', + 'BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN__SHIFT', + 'BIF_CFG_DEV0_RC_COMMAND__INT_DIS_MASK', + 'BIF_CFG_DEV0_RC_COMMAND__INT_DIS__SHIFT', + 'BIF_CFG_DEV0_RC_COMMAND__IOEN_DN_MASK', + 'BIF_CFG_DEV0_RC_COMMAND__IOEN_DN__SHIFT', + 'BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN_MASK', + 'BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN__SHIFT', + 'BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK', + 'BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT', + 'BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_RC_COMMAND__PARITY_ERROR_RESPONSE_MASK', + 'BIF_CFG_DEV0_RC_COMMAND__PARITY_ERROR_RESPONSE__SHIFT', + 'BIF_CFG_DEV0_RC_COMMAND__SERR_EN_MASK', + 'BIF_CFG_DEV0_RC_COMMAND__SERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN_MASK', + 'BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN__SHIFT', + 'BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK', + 'BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK', + 'BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT', + 'BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT', + 'BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED_MASK', + 'BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK', + 'BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT', + 'BIF_CFG_DEV0_RC_HEADER__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_RC_HEADER__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_HEADER__HEADER_TYPE_MASK', + 'BIF_CFG_DEV0_RC_HEADER__HEADER_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE_MASK', + 'BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT', + 'BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN_MASK', + 'BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_MASK', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE_MASK', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE__SHIFT', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_MASK', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK', + 'BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK', + 'BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK', + 'BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK', + 'BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK', + 'BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK_MASK', + 'BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT', + 'BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG_MASK', + 'BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT', + 'BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK', + 'BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT', + 'BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY_MASK', + 'BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT', + 'BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK', + 'BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT', + 'BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK', + 'BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT', + 'BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK', + 'BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK', + 'BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT', + 'BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK', + 'BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK', + 'BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT', + 'BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK', + 'BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT', + 'BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK', + 'BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT', + 'BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK', + 'BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT', + 'BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT_MASK', + 'BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT__SHIFT', + 'BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN_MASK', + 'BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN__SHIFT', + 'BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK', + 'BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT', + 'BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK', + 'BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT', + 'BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK', + 'BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT', + 'BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN_MASK', + 'BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT', + 'BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK', + 'BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT', + 'BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64_MASK', + 'BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT', + 'BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA_MASK', + 'BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK', + 'BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK', + 'BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR_MASK', + 'BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR_MASK', + 'BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR_MASK', + 'BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR_MASK', + 'BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK', + 'BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK', + 'BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK', + 'BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK', + 'BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK', + 'BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT', + 'BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK', + 'BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT', + 'BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT_MASK', + 'BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT__SHIFT', + 'BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT_MASK', + 'BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT', + 'BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK', + 'BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT', + 'BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK_MASK', + 'BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK__SHIFT', + 'BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC_PMI_CAP__VERSION_MASK', + 'BIF_CFG_DEV0_RC_PMI_CAP__VERSION__SHIFT', + 'BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK', + 'BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT', + 'BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN_MASK', + 'BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT', + 'BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE_MASK', + 'BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE__SHIFT', + 'BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT_MASK', + 'BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT__SHIFT', + 'BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK', + 'BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT', + 'BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN_MASK', + 'BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN__SHIFT', + 'BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS_MASK', + 'BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA_MASK', + 'BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA__SHIFT', + 'BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK', + 'BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT', + 'BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK', + 'BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK', + 'BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT', + 'BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK', + 'BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT', + 'BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK', + 'BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT', + 'BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK', + 'BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT', + 'BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE_MASK', + 'BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE__SHIFT', + 'BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID_MASK', + 'BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID_MASK', + 'BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID__SHIFT', + 'BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR_MASK', + 'BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR__SHIFT', + 'BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_ENABLE_MASK', + 'BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_ENABLE__SHIFT', + 'BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK', + 'BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT', + 'BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK', + 'BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK', + 'BIF_CFG_DEV0_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT', + 'BIF_CFG_DEV0_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK', + 'BIF_CFG_DEV0_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT', + 'BIF_CFG_DEV0_RC_ROOT_CNTL__PM_INTERRUPT_EN_MASK', + 'BIF_CFG_DEV0_RC_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT', + 'BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK', + 'BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK', + 'BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT', + 'BIF_CFG_DEV0_RC_ROOT_STATUS__PME_PENDING_MASK', + 'BIF_CFG_DEV0_RC_ROOT_STATUS__PME_PENDING__SHIFT', + 'BIF_CFG_DEV0_RC_ROOT_STATUS__PME_REQUESTOR_ID_MASK', + 'BIF_CFG_DEV0_RC_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT', + 'BIF_CFG_DEV0_RC_ROOT_STATUS__PME_STATUS_MASK', + 'BIF_CFG_DEV0_RC_ROOT_STATUS__PME_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK', + 'BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_SURPRISE_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CAP__MRL_SENSOR_PRESENT_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CNTL2__RESERVED_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CNTL2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__HOTPLUG_INTR_EN_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__INBAND_PD_DISABLE_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__INBAND_PD_DISABLE__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK', + 'BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_STATUS2__RESERVED_MASK', + 'BIF_CFG_DEV0_RC_SLOT_STATUS2__RESERVED__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK', + 'BIF_CFG_DEV0_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_STATUS__COMMAND_COMPLETED_MASK', + 'BIF_CFG_DEV0_RC_SLOT_STATUS__COMMAND_COMPLETED__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_STATUS__DL_STATE_CHANGED_MASK', + 'BIF_CFG_DEV0_RC_SLOT_STATUS__DL_STATE_CHANGED__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK', + 'BIF_CFG_DEV0_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK', + 'BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_STATE_MASK', + 'BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK', + 'BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK', + 'BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT', + 'BIF_CFG_DEV0_RC_SLOT_STATUS__PWR_FAULT_DETECTED_MASK', + 'BIF_CFG_DEV0_RC_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT', + 'BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID_MASK', + 'BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID__SHIFT', + 'BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR_MASK', + 'BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR__SHIFT', + 'BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID_MASK', + 'BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID__SHIFT', + 'BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK', + 'BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT', + 'BIF_CFG_DEV0_RC_STATUS__CAP_LIST_MASK', + 'BIF_CFG_DEV0_RC_STATUS__CAP_LIST__SHIFT', + 'BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING_MASK', + 'BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING__SHIFT', + 'BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE_MASK', + 'BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE__SHIFT', + 'BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS_MASK', + 'BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS__SHIFT', + 'BIF_CFG_DEV0_RC_STATUS__INT_STATUS_MASK', + 'BIF_CFG_DEV0_RC_STATUS__INT_STATUS__SHIFT', + 'BIF_CFG_DEV0_RC_STATUS__MASTER_DATA_PARITY_ERROR_MASK', + 'BIF_CFG_DEV0_RC_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT', + 'BIF_CFG_DEV0_RC_STATUS__PARITY_ERROR_DETECTED_MASK', + 'BIF_CFG_DEV0_RC_STATUS__PARITY_ERROR_DETECTED__SHIFT', + 'BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP_MASK', + 'BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP__SHIFT', + 'BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT_MASK', + 'BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR_MASK', + 'BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT', + 'BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT_MASK', + 'BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT__SHIFT', + 'BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK', + 'BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT', + 'BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK', + 'BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT', + 'BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK', + 'BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT', + 'BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK', + 'BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT', + 'BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS_MASK', + 'BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS__SHIFT', + 'BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID_MASK', + 'BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID__SHIFT', + 'BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK', + 'BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT', + 'BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK', + 'BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT', + 'BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK', + 'BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT', + 'BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK', + 'BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT', + 'BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK', + 'BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT', + 'BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK', + 'BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT', + 'BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK', + 'BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT', + 'BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK', + 'BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT', + 'BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK', + 'BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT', + 'BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK', + 'BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT', + 'BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK', + 'BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT', + 'BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR_MASK', + 'BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR__SHIFT', + 'BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK', + 'BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT', + 'BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR_MASK', + 'BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR__SHIFT', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK', + 'BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT', + 'BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT_MASK', + 'BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT__SHIFT', + 'BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT_MASK', + 'BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT__SHIFT', + 'BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT_MASK', + 'BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT__SHIFT', + 'BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT_MASK', + 'BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT__SHIFT', + 'BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT_MASK', + 'BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT__SHIFT', + 'BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT_MASK', + 'BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT__SHIFT', + 'BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT_MASK', + 'BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT__SHIFT', + 'BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT_MASK', + 'BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT__SHIFT', + 'BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE_MASK', + 'BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE__SHIFT', + 'BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE_MASK', + 'BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE__SHIFT', + 'BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE_MASK', + 'BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE__SHIFT', + 'BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK', + 'BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT', + 'BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK', + 'BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT', + 'BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK', + 'BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT', + 'BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK', + 'BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT', + 'BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK', + 'BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT', + 'BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK', + 'BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT', + 'BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK', + 'BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT', + 'BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK', + 'BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT', + 'BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK', + 'BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT', + 'BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK', + 'BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT', + 'BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0_MASK', + 'BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0__SHIFT', + 'BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1_MASK', + 'BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1__SHIFT', + 'BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0_MASK', + 'BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0__SHIFT', + 'BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1_MASK', + 'BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1__SHIFT', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK', + 'BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK', + 'BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT', + 'BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK', + 'BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT', + 'BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK', + 'BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT', + 'BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK', + 'BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT', + 'BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK', + 'BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT', + 'BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK', + 'BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT', + 'BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK', + 'BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT', + 'BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK', + 'BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT', + 'BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK', + 'BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT', + 'BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK', + 'BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT', + 'BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK', + 'BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT', + 'BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK', + 'BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT', + 'BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK', + 'BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT', + 'BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_DIS_MASK', + 'BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_DIS__SHIFT', + 'BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_MASK', + 'BIF_RST_MISC_CTRL2__ALL_RST_PROTECT__SHIFT', + 'BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK', + 'BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT', + 'BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_PROTECT_MASK', + 'BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_PROTECT__SHIFT', + 'BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK', + 'BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT', + 'BIF_RST_MISC_CTRL2__SWDS_LNK_RST_PROTECT_MASK', + 'BIF_RST_MISC_CTRL2__SWDS_LNK_RST_PROTECT__SHIFT', + 'BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK', + 'BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT', + 'BIF_RST_MISC_CTRL2__SWUS_LNK_RST_PROTECT_MASK', + 'BIF_RST_MISC_CTRL2__SWUS_LNK_RST_PROTECT__SHIFT', + 'BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK', + 'BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT', + 'BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK', + 'BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT', + 'BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK', + 'BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT', + 'BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK', + 'BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT', + 'BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK', + 'BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT', + 'BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK', + 'BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT', + 'BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK', + 'BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT', + 'BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK', + 'BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT', + 'BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK', + 'BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT', + 'BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK', + 'BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT', + 'BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK', + 'BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT', + 'BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK', + 'BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT', + 'BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK', + 'BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT', + 'BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK', + 'BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT', + 'BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK', + 'BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT', + 'BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK', + 'BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT', + 'BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK', + 'BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT', + 'BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK', + 'BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT', + 'BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK', + 'BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT', + 'BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK', + 'BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT', + 'BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK', + 'BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT', + 'BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID_MASK', + 'BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID__SHIFT', + 'BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID_MASK', + 'BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID__SHIFT', + 'BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK', + 'BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT', + 'BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK', + 'BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK', + 'BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT', + 'CAM_CONTROL__AccessType_MASK', 'CAM_CONTROL__AccessType__SHIFT', + 'CAM_CONTROL__CAM_En_MASK', 'CAM_CONTROL__CAM_En__SHIFT', + 'CAM_CONTROL__CrossTrigger_MASK', + 'CAM_CONTROL__CrossTrigger__SHIFT', + 'CAM_CONTROL__DataMatchEn_MASK', + 'CAM_CONTROL__DataMatchEn__SHIFT', 'CAM_CONTROL__Op_MASK', + 'CAM_CONTROL__Op__SHIFT', 'CAM_CONTROL__VC_MASK', + 'CAM_CONTROL__VC__SHIFT', + 'CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom_MASK', + 'CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom__SHIFT', + 'CAM_TARGET_DATA_ADDR_TOP__DataAddrTop_MASK', + 'CAM_TARGET_DATA_ADDR_TOP__DataAddrTop__SHIFT', + 'CAM_TARGET_DATA_MASK__DataMask_MASK', + 'CAM_TARGET_DATA_MASK__DataMask__SHIFT', + 'CAM_TARGET_DATA__Data_MASK', 'CAM_TARGET_DATA__Data__SHIFT', + 'CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom_MASK', + 'CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom__SHIFT', + 'CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop_MASK', + 'CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop__SHIFT', + 'CAM_TARGET_INDEX_DATA_MASK__IndexDataMask_MASK', + 'CAM_TARGET_INDEX_DATA_MASK__IndexDataMask__SHIFT', + 'CAM_TARGET_INDEX_DATA__IndexData_MASK', + 'CAM_TARGET_INDEX_DATA__IndexData__SHIFT', + 'DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK', + 'DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT', + 'DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK', + 'DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT', + 'DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK', + 'DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT', + 'DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK', + 'DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT', + 'DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK', + 'DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK', + 'DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK', + 'DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK', + 'DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK', + 'DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT', + 'DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN_MASK', + 'DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT', + 'DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK', + 'DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT', + 'DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK', + 'DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT', + 'DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK', + 'DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT', + 'DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK', + 'DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT', + 'DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK', + 'DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT', + 'DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK', + 'DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT', + 'DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK', + 'DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT', + 'DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK', + 'DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT', + 'DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK', + 'DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT', + 'DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK', + 'DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT', + 'DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK', + 'DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT', + 'DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK', + 'DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT', + 'DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK', + 'DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT', + 'DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK', + 'DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT', + 'DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H_MASK', + 'DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H__SHIFT', + 'DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H_MASK', + 'DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H__SHIFT', + 'DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK', + 'DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT', + 'DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK', + 'DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT', + 'DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK', + 'DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT', + 'DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK', + 'DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT', + 'DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK', + 'DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT', + 'DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK', + 'DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT', + 'DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK', + 'DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT', + 'DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK', + 'DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT', + 'DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK', + 'DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT', + 'DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK', + 'DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT', + 'DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK', + 'DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT', + 'DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK', + 'DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT', + 'DOORBELL0_CTRL_ENTRY_0__BIF_DOORBELL0_RANGE_OFFSET_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_0__BIF_DOORBELL0_RANGE_OFFSET_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_0__BIF_DOORBELL0_RANGE_SIZE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_0__BIF_DOORBELL0_RANGE_SIZE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_0__DOORBELL0_FENCE_ENABLE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_0__DOORBELL0_FENCE_ENABLE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_10__BIF_DOORBELL10_RANGE_OFFSET_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_10__BIF_DOORBELL10_RANGE_OFFSET_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_10__BIF_DOORBELL10_RANGE_SIZE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_10__BIF_DOORBELL10_RANGE_SIZE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_10__DOORBELL10_FENCE_ENABLE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_10__DOORBELL10_FENCE_ENABLE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_11__BIF_DOORBELL11_RANGE_OFFSET_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_11__BIF_DOORBELL11_RANGE_OFFSET_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_11__BIF_DOORBELL11_RANGE_SIZE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_11__BIF_DOORBELL11_RANGE_SIZE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_11__DOORBELL11_FENCE_ENABLE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_11__DOORBELL11_FENCE_ENABLE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_12__BIF_DOORBELL12_RANGE_OFFSET_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_12__BIF_DOORBELL12_RANGE_OFFSET_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_12__BIF_DOORBELL12_RANGE_SIZE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_12__BIF_DOORBELL12_RANGE_SIZE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_12__DOORBELL12_FENCE_ENABLE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_12__DOORBELL12_FENCE_ENABLE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_13__BIF_DOORBELL13_RANGE_OFFSET_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_13__BIF_DOORBELL13_RANGE_OFFSET_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_13__BIF_DOORBELL13_RANGE_SIZE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_13__BIF_DOORBELL13_RANGE_SIZE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_13__DOORBELL13_FENCE_ENABLE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_13__DOORBELL13_FENCE_ENABLE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_14__BIF_DOORBELL14_RANGE_OFFSET_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_14__BIF_DOORBELL14_RANGE_OFFSET_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_14__BIF_DOORBELL14_RANGE_SIZE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_14__BIF_DOORBELL14_RANGE_SIZE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_14__DOORBELL14_FENCE_ENABLE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_14__DOORBELL14_FENCE_ENABLE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_15__BIF_DOORBELL15_RANGE_OFFSET_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_15__BIF_DOORBELL15_RANGE_OFFSET_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_15__BIF_DOORBELL15_RANGE_SIZE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_15__BIF_DOORBELL15_RANGE_SIZE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_15__DOORBELL15_FENCE_ENABLE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_15__DOORBELL15_FENCE_ENABLE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_16__BIF_DOORBELL16_RANGE_OFFSET_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_16__BIF_DOORBELL16_RANGE_OFFSET_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_16__BIF_DOORBELL16_RANGE_SIZE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_16__BIF_DOORBELL16_RANGE_SIZE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_16__DOORBELL16_FENCE_ENABLE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_16__DOORBELL16_FENCE_ENABLE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_17__BIF_DOORBELL17_RANGE_OFFSET_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_17__BIF_DOORBELL17_RANGE_OFFSET_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_17__BIF_DOORBELL17_RANGE_SIZE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_17__BIF_DOORBELL17_RANGE_SIZE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_17__DOORBELL17_FENCE_ENABLE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_17__DOORBELL17_FENCE_ENABLE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_18__BIF_DOORBELL18_RANGE_OFFSET_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_18__BIF_DOORBELL18_RANGE_OFFSET_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_18__BIF_DOORBELL18_RANGE_SIZE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_18__BIF_DOORBELL18_RANGE_SIZE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_18__DOORBELL18_FENCE_ENABLE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_18__DOORBELL18_FENCE_ENABLE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_19__BIF_DOORBELL19_RANGE_OFFSET_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_19__BIF_DOORBELL19_RANGE_OFFSET_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_19__BIF_DOORBELL19_RANGE_SIZE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_19__BIF_DOORBELL19_RANGE_SIZE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_19__DOORBELL19_FENCE_ENABLE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_19__DOORBELL19_FENCE_ENABLE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_1__BIF_DOORBELL1_RANGE_OFFSET_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_1__BIF_DOORBELL1_RANGE_OFFSET_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_1__BIF_DOORBELL1_RANGE_SIZE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_1__BIF_DOORBELL1_RANGE_SIZE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_1__DOORBELL1_FENCE_ENABLE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_1__DOORBELL1_FENCE_ENABLE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_20__BIF_DOORBELL20_RANGE_OFFSET_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_20__BIF_DOORBELL20_RANGE_OFFSET_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_20__BIF_DOORBELL20_RANGE_SIZE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_20__BIF_DOORBELL20_RANGE_SIZE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_20__DOORBELL20_FENCE_ENABLE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_20__DOORBELL20_FENCE_ENABLE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_2__BIF_DOORBELL2_RANGE_OFFSET_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_2__BIF_DOORBELL2_RANGE_OFFSET_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_2__BIF_DOORBELL2_RANGE_SIZE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_2__BIF_DOORBELL2_RANGE_SIZE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_2__DOORBELL2_FENCE_ENABLE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_2__DOORBELL2_FENCE_ENABLE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_3__BIF_DOORBELL3_RANGE_OFFSET_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_3__BIF_DOORBELL3_RANGE_OFFSET_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_3__BIF_DOORBELL3_RANGE_SIZE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_3__BIF_DOORBELL3_RANGE_SIZE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_3__DOORBELL3_FENCE_ENABLE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_3__DOORBELL3_FENCE_ENABLE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_4__BIF_DOORBELL4_RANGE_OFFSET_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_4__BIF_DOORBELL4_RANGE_OFFSET_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_4__BIF_DOORBELL4_RANGE_SIZE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_4__BIF_DOORBELL4_RANGE_SIZE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_4__DOORBELL4_FENCE_ENABLE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_4__DOORBELL4_FENCE_ENABLE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_5__BIF_DOORBELL5_RANGE_OFFSET_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_5__BIF_DOORBELL5_RANGE_OFFSET_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_5__BIF_DOORBELL5_RANGE_SIZE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_5__BIF_DOORBELL5_RANGE_SIZE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_5__DOORBELL5_FENCE_ENABLE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_5__DOORBELL5_FENCE_ENABLE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_6__BIF_DOORBELL6_RANGE_OFFSET_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_6__BIF_DOORBELL6_RANGE_OFFSET_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_6__BIF_DOORBELL6_RANGE_SIZE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_6__BIF_DOORBELL6_RANGE_SIZE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_6__DOORBELL6_FENCE_ENABLE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_6__DOORBELL6_FENCE_ENABLE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_7__BIF_DOORBELL7_RANGE_OFFSET_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_7__BIF_DOORBELL7_RANGE_OFFSET_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_7__BIF_DOORBELL7_RANGE_SIZE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_7__BIF_DOORBELL7_RANGE_SIZE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_7__DOORBELL7_FENCE_ENABLE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_7__DOORBELL7_FENCE_ENABLE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_8__BIF_DOORBELL8_RANGE_OFFSET_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_8__BIF_DOORBELL8_RANGE_OFFSET_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_8__BIF_DOORBELL8_RANGE_SIZE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_8__BIF_DOORBELL8_RANGE_SIZE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_8__DOORBELL8_FENCE_ENABLE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_8__DOORBELL8_FENCE_ENABLE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_9__BIF_DOORBELL9_RANGE_OFFSET_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_9__BIF_DOORBELL9_RANGE_OFFSET_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_9__BIF_DOORBELL9_RANGE_SIZE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_9__BIF_DOORBELL9_RANGE_SIZE_ENTRY__SHIFT', + 'DOORBELL0_CTRL_ENTRY_9__DOORBELL9_FENCE_ENABLE_ENTRY_MASK', + 'DOORBELL0_CTRL_ENTRY_9__DOORBELL9_FENCE_ENABLE_ENTRY__SHIFT', + 'EGRESS_POISON_MASK_HI__EgressPoisonMaskHi_MASK', + 'EGRESS_POISON_MASK_HI__EgressPoisonMaskHi__SHIFT', + 'EGRESS_POISON_MASK_LO__EgressPoisonMaskLo_MASK', + 'EGRESS_POISON_MASK_LO__EgressPoisonMaskLo__SHIFT', + 'EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown_MASK', + 'EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown__SHIFT', + 'EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper_MASK', + 'EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8__SHIFT', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9_MASK', + 'EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8__SHIFT', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9_MASK', + 'EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9__SHIFT', + 'ErrEvent_ACTION_CONTROL__APML_ERR_En_MASK', + 'ErrEvent_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'ErrEvent_ACTION_CONTROL__IntrGenSel_MASK', + 'ErrEvent_ACTION_CONTROL__IntrGenSel__SHIFT', + 'ErrEvent_ACTION_CONTROL__LinkDis_En_MASK', + 'ErrEvent_ACTION_CONTROL__LinkDis_En__SHIFT', + 'ErrEvent_ACTION_CONTROL__SyncFlood_En_MASK', + 'ErrEvent_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'FEATURES_ENABLE__INTx_LevelOnlyMode_MASK', + 'FEATURES_ENABLE__INTx_LevelOnlyMode__SHIFT', + 'FEATURES_ENABLE__Ioapic_id_ext_en_MASK', + 'FEATURES_ENABLE__Ioapic_id_ext_en__SHIFT', + 'FEATURES_ENABLE__Ioapic_processor_mode_MASK', + 'FEATURES_ENABLE__Ioapic_processor_mode__SHIFT', + 'FEATURES_ENABLE__Ioapic_sb_feature_en_MASK', + 'FEATURES_ENABLE__Ioapic_sb_feature_en__SHIFT', + 'FEATURES_ENABLE__Ioapic_secondary_en_MASK', + 'FEATURES_ENABLE__Ioapic_secondary_en__SHIFT', + 'GDC0_A2S_CNTL3_CL0__FORCE_WR_PH_MASK', + 'GDC0_A2S_CNTL3_CL0__FORCE_WR_PH__SHIFT', + 'GDC0_A2S_CNTL3_CL0__FORCE_WR_STEERING_MASK', + 'GDC0_A2S_CNTL3_CL0__FORCE_WR_STEERING__SHIFT', + 'GDC0_A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY_MASK', + 'GDC0_A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY__SHIFT', + 'GDC0_A2S_CNTL3_CL0__WR_ST_TAG_MODE_MASK', + 'GDC0_A2S_CNTL3_CL0__WR_ST_TAG_MODE__SHIFT', + 'GDC0_A2S_CNTL3_CL1__FORCE_WR_PH_MASK', + 'GDC0_A2S_CNTL3_CL1__FORCE_WR_PH__SHIFT', + 'GDC0_A2S_CNTL3_CL1__FORCE_WR_STEERING_MASK', + 'GDC0_A2S_CNTL3_CL1__FORCE_WR_STEERING__SHIFT', + 'GDC0_A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY_MASK', + 'GDC0_A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY__SHIFT', + 'GDC0_A2S_CNTL3_CL1__WR_ST_TAG_MODE_MASK', + 'GDC0_A2S_CNTL3_CL1__WR_ST_TAG_MODE__SHIFT', + 'GDC0_A2S_CNTL_CL0__BLKLVL_MAP_MASK', + 'GDC0_A2S_CNTL_CL0__BLKLVL_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL0__DATERR_MAP_MASK', + 'GDC0_A2S_CNTL_CL0__DATERR_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL0__EXOKAY_RD_MAP_MASK', + 'GDC0_A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL0__EXOKAY_WR_MAP_MASK', + 'GDC0_A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL0__NSNOOP_MAP_MASK', + 'GDC0_A2S_CNTL_CL0__NSNOOP_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL0__RDRSP_ERRMAP_MASK', + 'GDC0_A2S_CNTL_CL0__RDRSP_ERRMAP__SHIFT', + 'GDC0_A2S_CNTL_CL0__RDRSP_SEL_MODE_MASK', + 'GDC0_A2S_CNTL_CL0__RDRSP_SEL_MODE__SHIFT', + 'GDC0_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP_MASK', + 'GDC0_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL0__REQPASSPW_VC0_MAP_MASK', + 'GDC0_A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP_MASK', + 'GDC0_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP_MASK', + 'GDC0_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL0__RESP_RD_MAP_MASK', + 'GDC0_A2S_CNTL_CL0__RESP_RD_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL0__RESP_WR_MAP_MASK', + 'GDC0_A2S_CNTL_CL0__RESP_WR_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL0__STATIC_VC_ENABLE_MASK', + 'GDC0_A2S_CNTL_CL0__STATIC_VC_ENABLE__SHIFT', + 'GDC0_A2S_CNTL_CL0__STATIC_VC_VALUE_MASK', + 'GDC0_A2S_CNTL_CL0__STATIC_VC_VALUE__SHIFT', + 'GDC0_A2S_CNTL_CL1__BLKLVL_MAP_MASK', + 'GDC0_A2S_CNTL_CL1__BLKLVL_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL1__DATERR_MAP_MASK', + 'GDC0_A2S_CNTL_CL1__DATERR_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL1__EXOKAY_RD_MAP_MASK', + 'GDC0_A2S_CNTL_CL1__EXOKAY_RD_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL1__EXOKAY_WR_MAP_MASK', + 'GDC0_A2S_CNTL_CL1__EXOKAY_WR_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL1__NSNOOP_MAP_MASK', + 'GDC0_A2S_CNTL_CL1__NSNOOP_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL1__RDRSP_ERRMAP_MASK', + 'GDC0_A2S_CNTL_CL1__RDRSP_ERRMAP__SHIFT', + 'GDC0_A2S_CNTL_CL1__RDRSP_SEL_MODE_MASK', + 'GDC0_A2S_CNTL_CL1__RDRSP_SEL_MODE__SHIFT', + 'GDC0_A2S_CNTL_CL1__REQPASSPW_NVC0_MAP_MASK', + 'GDC0_A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL1__REQPASSPW_VC0_MAP_MASK', + 'GDC0_A2S_CNTL_CL1__REQPASSPW_VC0_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP_MASK', + 'GDC0_A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP_MASK', + 'GDC0_A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL1__RESP_RD_MAP_MASK', + 'GDC0_A2S_CNTL_CL1__RESP_RD_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL1__RESP_WR_MAP_MASK', + 'GDC0_A2S_CNTL_CL1__RESP_WR_MAP__SHIFT', + 'GDC0_A2S_CNTL_CL1__STATIC_VC_ENABLE_MASK', + 'GDC0_A2S_CNTL_CL1__STATIC_VC_ENABLE__SHIFT', + 'GDC0_A2S_CNTL_CL1__STATIC_VC_VALUE_MASK', + 'GDC0_A2S_CNTL_CL1__STATIC_VC_VALUE__SHIFT', + 'GDC0_A2S_CNTL_SW0__FORCE_RSP_REORDER_EN_MASK', + 'GDC0_A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__SHIFT', + 'GDC0_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK', + 'GDC0_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT', + 'GDC0_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK', + 'GDC0_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT', + 'GDC0_A2S_CNTL_SW0__STATIC_VC_ENABLE_MASK', + 'GDC0_A2S_CNTL_SW0__STATIC_VC_ENABLE__SHIFT', + 'GDC0_A2S_CNTL_SW0__STATIC_VC_VALUE_MASK', + 'GDC0_A2S_CNTL_SW0__STATIC_VC_VALUE__SHIFT', + 'GDC0_A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK', + 'GDC0_A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT', + 'GDC0_A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK', + 'GDC0_A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT', + 'GDC0_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE_MASK', + 'GDC0_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE__SHIFT', + 'GDC0_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE_MASK', + 'GDC0_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT', + 'GDC0_A2S_CNTL_SW1__FORCE_RSP_REORDER_EN_MASK', + 'GDC0_A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__SHIFT', + 'GDC0_A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK', + 'GDC0_A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT', + 'GDC0_A2S_CNTL_SW1__SDP_WR_CHAIN_DIS_MASK', + 'GDC0_A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT', + 'GDC0_A2S_CNTL_SW1__STATIC_VC_ENABLE_MASK', + 'GDC0_A2S_CNTL_SW1__STATIC_VC_ENABLE__SHIFT', + 'GDC0_A2S_CNTL_SW1__STATIC_VC_VALUE_MASK', + 'GDC0_A2S_CNTL_SW1__STATIC_VC_VALUE__SHIFT', + 'GDC0_A2S_CNTL_SW1__WRR_RD_WEIGHT_MASK', + 'GDC0_A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT', + 'GDC0_A2S_CNTL_SW1__WRR_WR_WEIGHT_MASK', + 'GDC0_A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT', + 'GDC0_A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE_MASK', + 'GDC0_A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE__SHIFT', + 'GDC0_A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE_MASK', + 'GDC0_A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT', + 'GDC0_A2S_CNTL_SW2__FORCE_RSP_REORDER_EN_MASK', + 'GDC0_A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__SHIFT', + 'GDC0_A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK', + 'GDC0_A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT', + 'GDC0_A2S_CNTL_SW2__SDP_WR_CHAIN_DIS_MASK', + 'GDC0_A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__SHIFT', + 'GDC0_A2S_CNTL_SW2__STATIC_VC_ENABLE_MASK', + 'GDC0_A2S_CNTL_SW2__STATIC_VC_ENABLE__SHIFT', + 'GDC0_A2S_CNTL_SW2__STATIC_VC_VALUE_MASK', + 'GDC0_A2S_CNTL_SW2__STATIC_VC_VALUE__SHIFT', + 'GDC0_A2S_CNTL_SW2__WRR_RD_WEIGHT_MASK', + 'GDC0_A2S_CNTL_SW2__WRR_RD_WEIGHT__SHIFT', + 'GDC0_A2S_CNTL_SW2__WRR_WR_WEIGHT_MASK', + 'GDC0_A2S_CNTL_SW2__WRR_WR_WEIGHT__SHIFT', + 'GDC0_A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE_MASK', + 'GDC0_A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE__SHIFT', + 'GDC0_A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE_MASK', + 'GDC0_A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT', + 'GDC0_A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK', + 'GDC0_A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT', + 'GDC0_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN_MASK', + 'GDC0_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN__SHIFT', + 'GDC0_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK', + 'GDC0_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT', + 'GDC0_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY_MASK', + 'GDC0_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY__SHIFT', + 'GDC0_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS_MASK', + 'GDC0_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT', + 'GDC0_A2S_MISC_CNTL__RD_TAG_SET_MIN_MASK', + 'GDC0_A2S_MISC_CNTL__RD_TAG_SET_MIN__SHIFT', + 'GDC0_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS_MASK', + 'GDC0_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT', + 'GDC0_A2S_MISC_CNTL__RSP_REORDER_DIS_MASK', + 'GDC0_A2S_MISC_CNTL__RSP_REORDER_DIS__SHIFT', + 'GDC0_A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK', + 'GDC0_A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT', + 'GDC0_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS_MASK', + 'GDC0_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT', + 'GDC0_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE_MASK', + 'GDC0_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE__SHIFT', + 'GDC0_A2S_MISC_CNTL__WRR_LRG_MODE_MASK', + 'GDC0_A2S_MISC_CNTL__WRR_LRG_MODE__SHIFT', + 'GDC0_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE_MASK', + 'GDC0_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE__SHIFT', + 'GDC0_A2S_MISC_CNTL__WR_TAG_SET_MIN_MASK', + 'GDC0_A2S_MISC_CNTL__WR_TAG_SET_MIN__SHIFT', + 'GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK', + 'GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT', + 'GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK', + 'GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT', + 'GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK', + 'GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT', + 'GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK', + 'GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT', + 'GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK', + 'GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT', + 'GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK', + 'GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT', + 'GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK', + 'GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT', + 'GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK', + 'GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT', + 'GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK', + 'GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT', + 'GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK', + 'GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT', + 'GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK', + 'GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT', + 'GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK', + 'GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT', + 'GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK', + 'GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT', + 'GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK', + 'GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT', + 'GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK', + 'GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT', + 'GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK', + 'GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT', + 'GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK', + 'GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT', + 'GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK', + 'GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT', + 'GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK', + 'GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT', + 'GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK', + 'GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT', + 'GDC0_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN_MASK', + 'GDC0_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN__SHIFT', + 'GDC0_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN_MASK', + 'GDC0_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN__SHIFT', + 'GDC0_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN_MASK', + 'GDC0_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN__SHIFT', + 'GDC0_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN_MASK', + 'GDC0_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN__SHIFT', + 'GDC0_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS_MASK', + 'GDC0_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS__SHIFT', + 'GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS_MASK', + 'GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS__SHIFT', + 'GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK', + 'GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT', + 'GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK', + 'GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT', + 'GDC0_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE_MASK', + 'GDC0_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE__SHIFT', + 'GDC0_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS_MASK', + 'GDC0_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT', + 'GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1_MASK', + 'GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1__SHIFT', + 'GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2_MASK', + 'GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2__SHIFT', + 'GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS_MASK', + 'GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS__SHIFT', + 'GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY_MASK', + 'GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY__SHIFT', + 'GDC0_NGDC_RESERVED_0__RESERVED_MASK', + 'GDC0_NGDC_RESERVED_0__RESERVED__SHIFT', + 'GDC0_NGDC_RESERVED_1__RESERVED_MASK', + 'GDC0_NGDC_RESERVED_1__RESERVED__SHIFT', + 'GDC0_S2A_MISC_CNTL__ATM_ARB_MODE_MASK', + 'GDC0_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT', + 'GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK', + 'GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT', + 'GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK', + 'GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT', + 'GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK', + 'GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT', + 'GDC0_S2A_MISC_CNTL__RB_ARB_MODE_MASK', + 'GDC0_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT', + 'GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK', + 'GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT', + 'GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK', + 'GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT', + 'GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS_MASK', + 'GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS__SHIFT', + 'GDC1_A2S_CNTL3_CL0__FORCE_WR_PH_MASK', + 'GDC1_A2S_CNTL3_CL0__FORCE_WR_PH__SHIFT', + 'GDC1_A2S_CNTL3_CL0__FORCE_WR_STEERING_MASK', + 'GDC1_A2S_CNTL3_CL0__FORCE_WR_STEERING__SHIFT', + 'GDC1_A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY_MASK', + 'GDC1_A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY__SHIFT', + 'GDC1_A2S_CNTL3_CL0__WR_ST_TAG_MODE_MASK', + 'GDC1_A2S_CNTL3_CL0__WR_ST_TAG_MODE__SHIFT', + 'GDC1_A2S_CNTL3_CL1__FORCE_WR_PH_MASK', + 'GDC1_A2S_CNTL3_CL1__FORCE_WR_PH__SHIFT', + 'GDC1_A2S_CNTL3_CL1__FORCE_WR_STEERING_MASK', + 'GDC1_A2S_CNTL3_CL1__FORCE_WR_STEERING__SHIFT', + 'GDC1_A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY_MASK', + 'GDC1_A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY__SHIFT', + 'GDC1_A2S_CNTL3_CL1__WR_ST_TAG_MODE_MASK', + 'GDC1_A2S_CNTL3_CL1__WR_ST_TAG_MODE__SHIFT', + 'GDC1_A2S_CNTL_CL0__BLKLVL_MAP_MASK', + 'GDC1_A2S_CNTL_CL0__BLKLVL_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL0__DATERR_MAP_MASK', + 'GDC1_A2S_CNTL_CL0__DATERR_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL0__EXOKAY_RD_MAP_MASK', + 'GDC1_A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL0__EXOKAY_WR_MAP_MASK', + 'GDC1_A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL0__NSNOOP_MAP_MASK', + 'GDC1_A2S_CNTL_CL0__NSNOOP_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL0__RDRSP_ERRMAP_MASK', + 'GDC1_A2S_CNTL_CL0__RDRSP_ERRMAP__SHIFT', + 'GDC1_A2S_CNTL_CL0__RDRSP_SEL_MODE_MASK', + 'GDC1_A2S_CNTL_CL0__RDRSP_SEL_MODE__SHIFT', + 'GDC1_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP_MASK', + 'GDC1_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL0__REQPASSPW_VC0_MAP_MASK', + 'GDC1_A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP_MASK', + 'GDC1_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP_MASK', + 'GDC1_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL0__RESP_RD_MAP_MASK', + 'GDC1_A2S_CNTL_CL0__RESP_RD_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL0__RESP_WR_MAP_MASK', + 'GDC1_A2S_CNTL_CL0__RESP_WR_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL0__STATIC_VC_ENABLE_MASK', + 'GDC1_A2S_CNTL_CL0__STATIC_VC_ENABLE__SHIFT', + 'GDC1_A2S_CNTL_CL0__STATIC_VC_VALUE_MASK', + 'GDC1_A2S_CNTL_CL0__STATIC_VC_VALUE__SHIFT', + 'GDC1_A2S_CNTL_CL1__BLKLVL_MAP_MASK', + 'GDC1_A2S_CNTL_CL1__BLKLVL_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL1__DATERR_MAP_MASK', + 'GDC1_A2S_CNTL_CL1__DATERR_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL1__EXOKAY_RD_MAP_MASK', + 'GDC1_A2S_CNTL_CL1__EXOKAY_RD_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL1__EXOKAY_WR_MAP_MASK', + 'GDC1_A2S_CNTL_CL1__EXOKAY_WR_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL1__NSNOOP_MAP_MASK', + 'GDC1_A2S_CNTL_CL1__NSNOOP_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL1__RDRSP_ERRMAP_MASK', + 'GDC1_A2S_CNTL_CL1__RDRSP_ERRMAP__SHIFT', + 'GDC1_A2S_CNTL_CL1__RDRSP_SEL_MODE_MASK', + 'GDC1_A2S_CNTL_CL1__RDRSP_SEL_MODE__SHIFT', + 'GDC1_A2S_CNTL_CL1__REQPASSPW_NVC0_MAP_MASK', + 'GDC1_A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL1__REQPASSPW_VC0_MAP_MASK', + 'GDC1_A2S_CNTL_CL1__REQPASSPW_VC0_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP_MASK', + 'GDC1_A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP_MASK', + 'GDC1_A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL1__RESP_RD_MAP_MASK', + 'GDC1_A2S_CNTL_CL1__RESP_RD_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL1__RESP_WR_MAP_MASK', + 'GDC1_A2S_CNTL_CL1__RESP_WR_MAP__SHIFT', + 'GDC1_A2S_CNTL_CL1__STATIC_VC_ENABLE_MASK', + 'GDC1_A2S_CNTL_CL1__STATIC_VC_ENABLE__SHIFT', + 'GDC1_A2S_CNTL_CL1__STATIC_VC_VALUE_MASK', + 'GDC1_A2S_CNTL_CL1__STATIC_VC_VALUE__SHIFT', + 'GDC1_A2S_CNTL_SW0__FORCE_RSP_REORDER_EN_MASK', + 'GDC1_A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__SHIFT', + 'GDC1_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK', + 'GDC1_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT', + 'GDC1_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK', + 'GDC1_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT', + 'GDC1_A2S_CNTL_SW0__STATIC_VC_ENABLE_MASK', + 'GDC1_A2S_CNTL_SW0__STATIC_VC_ENABLE__SHIFT', + 'GDC1_A2S_CNTL_SW0__STATIC_VC_VALUE_MASK', + 'GDC1_A2S_CNTL_SW0__STATIC_VC_VALUE__SHIFT', + 'GDC1_A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK', + 'GDC1_A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT', + 'GDC1_A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK', + 'GDC1_A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT', + 'GDC1_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE_MASK', + 'GDC1_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE__SHIFT', + 'GDC1_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE_MASK', + 'GDC1_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT', + 'GDC1_A2S_CNTL_SW1__FORCE_RSP_REORDER_EN_MASK', + 'GDC1_A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__SHIFT', + 'GDC1_A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK', + 'GDC1_A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT', + 'GDC1_A2S_CNTL_SW1__SDP_WR_CHAIN_DIS_MASK', + 'GDC1_A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT', + 'GDC1_A2S_CNTL_SW1__STATIC_VC_ENABLE_MASK', + 'GDC1_A2S_CNTL_SW1__STATIC_VC_ENABLE__SHIFT', + 'GDC1_A2S_CNTL_SW1__STATIC_VC_VALUE_MASK', + 'GDC1_A2S_CNTL_SW1__STATIC_VC_VALUE__SHIFT', + 'GDC1_A2S_CNTL_SW1__WRR_RD_WEIGHT_MASK', + 'GDC1_A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT', + 'GDC1_A2S_CNTL_SW1__WRR_WR_WEIGHT_MASK', + 'GDC1_A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT', + 'GDC1_A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE_MASK', + 'GDC1_A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE__SHIFT', + 'GDC1_A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE_MASK', + 'GDC1_A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT', + 'GDC1_A2S_CNTL_SW2__FORCE_RSP_REORDER_EN_MASK', + 'GDC1_A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__SHIFT', + 'GDC1_A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK', + 'GDC1_A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT', + 'GDC1_A2S_CNTL_SW2__SDP_WR_CHAIN_DIS_MASK', + 'GDC1_A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__SHIFT', + 'GDC1_A2S_CNTL_SW2__STATIC_VC_ENABLE_MASK', + 'GDC1_A2S_CNTL_SW2__STATIC_VC_ENABLE__SHIFT', + 'GDC1_A2S_CNTL_SW2__STATIC_VC_VALUE_MASK', + 'GDC1_A2S_CNTL_SW2__STATIC_VC_VALUE__SHIFT', + 'GDC1_A2S_CNTL_SW2__WRR_RD_WEIGHT_MASK', + 'GDC1_A2S_CNTL_SW2__WRR_RD_WEIGHT__SHIFT', + 'GDC1_A2S_CNTL_SW2__WRR_WR_WEIGHT_MASK', + 'GDC1_A2S_CNTL_SW2__WRR_WR_WEIGHT__SHIFT', + 'GDC1_A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE_MASK', + 'GDC1_A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE__SHIFT', + 'GDC1_A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE_MASK', + 'GDC1_A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT', + 'GDC1_A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK', + 'GDC1_A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT', + 'GDC1_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN_MASK', + 'GDC1_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN__SHIFT', + 'GDC1_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK', + 'GDC1_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT', + 'GDC1_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY_MASK', + 'GDC1_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY__SHIFT', + 'GDC1_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS_MASK', + 'GDC1_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT', + 'GDC1_A2S_MISC_CNTL__RD_TAG_SET_MIN_MASK', + 'GDC1_A2S_MISC_CNTL__RD_TAG_SET_MIN__SHIFT', + 'GDC1_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS_MASK', + 'GDC1_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT', + 'GDC1_A2S_MISC_CNTL__RSP_REORDER_DIS_MASK', + 'GDC1_A2S_MISC_CNTL__RSP_REORDER_DIS__SHIFT', + 'GDC1_A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK', + 'GDC1_A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT', + 'GDC1_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS_MASK', + 'GDC1_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT', + 'GDC1_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE_MASK', + 'GDC1_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE__SHIFT', + 'GDC1_A2S_MISC_CNTL__WRR_LRG_MODE_MASK', + 'GDC1_A2S_MISC_CNTL__WRR_LRG_MODE__SHIFT', + 'GDC1_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE_MASK', + 'GDC1_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE__SHIFT', + 'GDC1_A2S_MISC_CNTL__WR_TAG_SET_MIN_MASK', + 'GDC1_A2S_MISC_CNTL__WR_TAG_SET_MIN__SHIFT', + 'GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK', + 'GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT', + 'GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK', + 'GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT', + 'GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK', + 'GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT', + 'GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK', + 'GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT', + 'GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK', + 'GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT', + 'GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK', + 'GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT', + 'GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK', + 'GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT', + 'GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK', + 'GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT', + 'GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK', + 'GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT', + 'GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK', + 'GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT', + 'GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK', + 'GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT', + 'GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK', + 'GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT', + 'GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK', + 'GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT', + 'GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK', + 'GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT', + 'GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK', + 'GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT', + 'GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK', + 'GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK', + 'GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT', + 'GDC1_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN_MASK', + 'GDC1_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN__SHIFT', + 'GDC1_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN_MASK', + 'GDC1_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN__SHIFT', + 'GDC1_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN_MASK', + 'GDC1_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN__SHIFT', + 'GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN_MASK', + 'GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN__SHIFT', + 'GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS_MASK', + 'GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS__SHIFT', + 'GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS_MASK', + 'GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS__SHIFT', + 'GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK', + 'GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT', + 'GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK', + 'GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE_MASK', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE__SHIFT', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS_MASK', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1_MASK', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1__SHIFT', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2_MASK', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2__SHIFT', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS_MASK', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS__SHIFT', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY_MASK', + 'GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY__SHIFT', + 'GDC1_NGDC_RESERVED_0__RESERVED_MASK', + 'GDC1_NGDC_RESERVED_0__RESERVED__SHIFT', + 'GDC1_NGDC_RESERVED_1__RESERVED_MASK', + 'GDC1_NGDC_RESERVED_1__RESERVED__SHIFT', + 'GDC1_S2A_MISC_CNTL__ATM_ARB_MODE_MASK', + 'GDC1_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT', + 'GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK', + 'GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT', + 'GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK', + 'GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT', + 'GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK', + 'GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT', + 'GDC1_S2A_MISC_CNTL__RB_ARB_MODE_MASK', + 'GDC1_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT', + 'GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK', + 'GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT', + 'GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK', + 'GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT', + 'GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS_MASK', + 'GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS__SHIFT', + 'HARD_RST_CTRL__CORE_RST_EN_MASK', + 'HARD_RST_CTRL__CORE_RST_EN__SHIFT', + 'HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK', + 'HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT', + 'HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK', + 'HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT', + 'HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK', + 'HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT', + 'HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK', + 'HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT', + 'HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK', + 'HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT', + 'HARD_RST_CTRL__EP_CFG_RST_EN_MASK', + 'HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT', + 'HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK', + 'HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT', + 'HARD_RST_CTRL__EP_PRV_RST_EN_MASK', + 'HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT', + 'HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK', + 'HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT', + 'HARD_RST_CTRL__RELOAD_STRAP_EN_MASK', + 'HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT', + 'HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK', + 'HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT', + 'HARD_RST_CTRL__SION_AON_RESET_EN_MASK', + 'HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT', + 'HARD_RST_CTRL__STRAP_RST_EN_MASK', + 'HARD_RST_CTRL__STRAP_RST_EN__SHIFT', + 'HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK', + 'HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT', + 'HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK', + 'HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT', + 'HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK', + 'HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT', + 'HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK', + 'HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT', + 'HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK', + 'HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT', + 'HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK', + 'HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT', + 'HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK', + 'HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT', + 'HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK', + 'HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT', + 'INTERNAL_POISON_MASK__IntPoisonMask_MASK', + 'INTERNAL_POISON_MASK__IntPoisonMask__SHIFT', + 'INTERNAL_POISON_STATUS__IntPoisonStatus_0_MASK', + 'INTERNAL_POISON_STATUS__IntPoisonStatus_0__SHIFT', + 'INTERNAL_POISON_STATUS__IntPoisonStatus_1_MASK', + 'INTERNAL_POISON_STATUS__IntPoisonStatus_1__SHIFT', + 'INTERNAL_POISON_STATUS__IntPoisonStatus_2_MASK', + 'INTERNAL_POISON_STATUS__IntPoisonStatus_2__SHIFT', + 'INTERNAL_POISON_STATUS__IntPoisonStatus_3_MASK', + 'INTERNAL_POISON_STATUS__IntPoisonStatus_3__SHIFT', + 'INTERNAL_POISON_STATUS__IntPoisonStatus_4_MASK', + 'INTERNAL_POISON_STATUS__IntPoisonStatus_4__SHIFT', + 'INTERNAL_POISON_STATUS__IntPoisonStatus_5_MASK', + 'INTERNAL_POISON_STATUS__IntPoisonStatus_5__SHIFT', + 'INTERNAL_POISON_STATUS__IntPoisonStatus_6_MASK', + 'INTERNAL_POISON_STATUS__IntPoisonStatus_6__SHIFT', + 'INTERNAL_POISON_STATUS__IntPoisonStatus_7_MASK', + 'INTERNAL_POISON_STATUS__IntPoisonStatus_7__SHIFT', + 'INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK', + 'INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT', + 'INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK', + 'INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT', + 'IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK', + 'IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT', + 'IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK', + 'IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT', + 'IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK', + 'IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT', + 'IRQ_BRIDGE_CNTL__ISA_EN_MASK', 'IRQ_BRIDGE_CNTL__ISA_EN__SHIFT', + 'IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK', + 'IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT', + 'IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK', + 'IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT', + 'IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK', + 'IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT', + 'IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK', + 'IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT', + 'IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK', + 'IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT', + 'IRQ_BRIDGE_CNTL__SERR_EN_MASK', + 'IRQ_BRIDGE_CNTL__SERR_EN__SHIFT', + 'IRQ_BRIDGE_CNTL__VGA_DEC_MASK', + 'IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT', 'IRQ_BRIDGE_CNTL__VGA_EN_MASK', + 'IRQ_BRIDGE_CNTL__VGA_EN__SHIFT', + 'L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_Bypass_MASK', + 'L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_Bypass__SHIFT', + 'L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_RdLatency_MASK', + 'L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_RdLatency__SHIFT', + 'L2B_SDP_PARITY_ERROR_EN__CP_PARITY_ERROR_EN_MASK', + 'L2B_SDP_PARITY_ERROR_EN__CP_PARITY_ERROR_EN__SHIFT', + 'L2B_SDP_PARITY_ERROR_EN__DVM_PARITY_ERROR_EN_MASK', + 'L2B_SDP_PARITY_ERROR_EN__DVM_PARITY_ERROR_EN__SHIFT', + 'L2B_SDP_PARITY_ERROR_EN__MSG_PARITY_ERROR_EN_MASK', + 'L2B_SDP_PARITY_ERROR_EN__MSG_PARITY_ERROR_EN__SHIFT', + 'L2B_SDP_PARITY_ERROR_EN__TWW_PARITY_ERROR_EN_MASK', + 'L2B_SDP_PARITY_ERROR_EN__TWW_PARITY_ERROR_EN__SHIFT', + 'L2B_SDP_PARITY_ERROR_EN__VFMMIO_PARITY_ERROR_EN_MASK', + 'L2B_SDP_PARITY_ERROR_EN__VFMMIO_PARITY_ERROR_EN__SHIFT', + 'L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_Bypass_MASK', + 'L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_Bypass__SHIFT', + 'L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_RdLatency_MASK', + 'L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_RdLatency__SHIFT', + 'L2_CONTROL_0__AllowL1CacheATSRsp_MASK', + 'L2_CONTROL_0__AllowL1CacheATSRsp__SHIFT', + 'L2_CONTROL_0__AllowL1CacheLargePagemode0_MASK', + 'L2_CONTROL_0__AllowL1CacheLargePagemode0__SHIFT', + 'L2_CONTROL_0__AllowL1CacheVZero_MASK', + 'L2_CONTROL_0__AllowL1CacheVZero__SHIFT', + 'L2_CONTROL_0__DTCHitVZeroOrIVZero_MASK', + 'L2_CONTROL_0__DTCHitVZeroOrIVZero__SHIFT', + 'L2_CONTROL_0__IFifoBurstLength_MASK', + 'L2_CONTROL_0__IFifoBurstLength__SHIFT', + 'L2_CONTROL_0__IFifoClientPriority_MASK', + 'L2_CONTROL_0__IFifoClientPriority__SHIFT', + 'L2_CONTROL_0__SIDEPTEOnAddrTransExcl_MASK', + 'L2_CONTROL_0__SIDEPTEOnAddrTransExcl__SHIFT', + 'L2_CONTROL_0__SIDEPTEOnUntransExcl_MASK', + 'L2_CONTROL_0__SIDEPTEOnUntransExcl__SHIFT', + 'L2_CONTROL_1__DBUSDis_MASK', 'L2_CONTROL_1__DBUSDis__SHIFT', + 'L2_CONTROL_1__PerfThreshold_MASK', + 'L2_CONTROL_1__PerfThreshold__SHIFT', + 'L2_CONTROL_1__SeqInvBurstLimitEn_MASK', + 'L2_CONTROL_1__SeqInvBurstLimitEn__SHIFT', + 'L2_CONTROL_1__SeqInvBurstLimitInv_MASK', + 'L2_CONTROL_1__SeqInvBurstLimitInv__SHIFT', + 'L2_CONTROL_1__SeqInvBurstLimitL2Req_MASK', + 'L2_CONTROL_1__SeqInvBurstLimitL2Req__SHIFT', + 'L2_CONTROL_5__DTCUpdatePri_MASK', + 'L2_CONTROL_5__DTCUpdatePri__SHIFT', + 'L2_CONTROL_5__DTCUpdateVOneIVZero_MASK', + 'L2_CONTROL_5__DTCUpdateVOneIVZero__SHIFT', + 'L2_CONTROL_5__DTCUpdateVZeroIVOne_MASK', + 'L2_CONTROL_5__DTCUpdateVZeroIVOne__SHIFT', + 'L2_CONTROL_5__FC1Dis_MASK', 'L2_CONTROL_5__FC1Dis__SHIFT', + 'L2_CONTROL_5__FC3Dis_MASK', 'L2_CONTROL_5__FC3Dis__SHIFT', + 'L2_CONTROL_5__ForceTWonVCQoS_MASK', + 'L2_CONTROL_5__ForceTWonVCQoS__SHIFT', + 'L2_CONTROL_5__GST_partial_ptc_cntrl_MASK', + 'L2_CONTROL_5__GST_partial_ptc_cntrl__SHIFT', + 'L2_CONTROL_5__L2B_L2A_v1_trans_credits_MASK', + 'L2_CONTROL_5__L2B_L2A_v1_trans_credits__SHIFT', + 'L2_CONTROL_5__QueueArbFBPri_MASK', + 'L2_CONTROL_5__QueueArbFBPri__SHIFT', + 'L2_CONTROL_5__STORE_PDPE_QOS_PTC_MASK', + 'L2_CONTROL_5__STORE_PDPE_QOS_PTC__SHIFT', + 'L2_CONTROL_6__Perf2Threshold_MASK', + 'L2_CONTROL_6__Perf2Threshold__SHIFT', + 'L2_CONTROL_6__SeqInvBurstLimitEn_MASK', + 'L2_CONTROL_6__SeqInvBurstLimitEn__SHIFT', + 'L2_CONTROL_6__SeqInvBurstLimitInv_MASK', + 'L2_CONTROL_6__SeqInvBurstLimitInv__SHIFT', + 'L2_CONTROL_6__SeqInvBurstLimitPDCReq_MASK', + 'L2_CONTROL_6__SeqInvBurstLimitPDCReq__SHIFT', + 'L2_CP_CONTROL_1__CPL1Off_MASK', + 'L2_CP_CONTROL_1__CPL1Off__SHIFT', + 'L2_CP_CONTROL_1__Reserved_MASK', + 'L2_CP_CONTROL_1__Reserved__SHIFT', + 'L2_CP_CONTROL_2__LEGACY_CWWB_PATH_MASK', + 'L2_CP_CONTROL_2__LEGACY_CWWB_PATH__SHIFT', + 'L2_CP_CONTROL_2__OVERCONSTRAIN_CMD_WQ_ON_INV_MASK', + 'L2_CP_CONTROL_2__OVERCONSTRAIN_CMD_WQ_ON_INV__SHIFT', + 'L2_CP_CONTROL_2__gstcp_always_refetch_v1_MASK', + 'L2_CP_CONTROL_2__gstcp_always_refetch_v1__SHIFT', + 'L2_CP_CONTROL_2__inv_dvmsync_mode_MASK', + 'L2_CP_CONTROL_2__inv_dvmsync_mode__SHIFT', + 'L2_CP_CONTROL_2__inv_pspflush_mode_MASK', + 'L2_CP_CONTROL_2__inv_pspflush_mode__SHIFT', + 'L2_CP_CONTROL_2__inv_waitcmpl_mode_MASK', + 'L2_CP_CONTROL_2__inv_waitcmpl_mode__SHIFT', + 'L2_CP_CONTROL_2__wqmask_propagation_latency_MASK', + 'L2_CP_CONTROL_2__wqmask_propagation_latency__SHIFT', + 'L2_CP_CONTROL_3__INV_CMD_PRIORITY_MASK', + 'L2_CP_CONTROL_3__INV_CMD_PRIORITY__SHIFT', + 'L2_CP_CONTROL_3__PSP_CMD_PRIORITY_MASK', + 'L2_CP_CONTROL_3__PSP_CMD_PRIORITY__SHIFT', + 'L2_CP_CONTROL_3__SYNC_CMD_PRIORITY_MASK', + 'L2_CP_CONTROL_3__SYNC_CMD_PRIORITY__SHIFT', + 'L2_CP_CONTROL_3__WAIT_CMD_PRIORITY_MASK', + 'L2_CP_CONTROL_3__WAIT_CMD_PRIORITY__SHIFT', + 'L2_CP_CONTROL__CPFlushOnInv_MASK', + 'L2_CP_CONTROL__CPFlushOnInv__SHIFT', + 'L2_CP_CONTROL__CPFlushOnWait_MASK', + 'L2_CP_CONTROL__CPFlushOnWait__SHIFT', + 'L2_CP_CONTROL__CPForceOneOutstandingCommand_MASK', + 'L2_CP_CONTROL__CPForceOneOutstandingCommand__SHIFT', + 'L2_CP_CONTROL__CPForceReqPassPW_MASK', + 'L2_CP_CONTROL__CPForceReqPassPW__SHIFT', + 'L2_CP_CONTROL__CPPrefetchDis_MASK', + 'L2_CP_CONTROL__CPPrefetchDis__SHIFT', + 'L2_CP_CONTROL__CPRdDelay_MASK', + 'L2_CP_CONTROL__CPRdDelay__SHIFT', + 'L2_CP_CONTROL__CPStallCmdErrForIOTLBCmpl_MASK', + 'L2_CP_CONTROL__CPStallCmdErrForIOTLBCmpl__SHIFT', + 'L2_CREDIT_CONTROL_0__FC1Credits_MASK', + 'L2_CREDIT_CONTROL_0__FC1Credits__SHIFT', + 'L2_CREDIT_CONTROL_0__FC1Override_MASK', + 'L2_CREDIT_CONTROL_0__FC1Override__SHIFT', + 'L2_CREDIT_CONTROL_0__FC3Credits_MASK', + 'L2_CREDIT_CONTROL_0__FC3Credits__SHIFT', + 'L2_CREDIT_CONTROL_0__FC3Override_MASK', + 'L2_CREDIT_CONTROL_0__FC3Override__SHIFT', + 'L2_CREDIT_CONTROL_1__CP_PREFETCH_credits_MASK', + 'L2_CREDIT_CONTROL_1__CP_PREFETCH_credits__SHIFT', + 'L2_CREDIT_CONTROL_1__PPR_MCIF_credits_MASK', + 'L2_CREDIT_CONTROL_1__PPR_MCIF_credits__SHIFT', + 'L2_DTC_CONTROL__DTCBypass_MASK', + 'L2_DTC_CONTROL__DTCBypass__SHIFT', + 'L2_DTC_CONTROL__DTCEntries_MASK', + 'L2_DTC_CONTROL__DTCEntries__SHIFT', + 'L2_DTC_CONTROL__DTCInvalidationSel_MASK', + 'L2_DTC_CONTROL__DTCInvalidationSel__SHIFT', + 'L2_DTC_CONTROL__DTCLRUUpdatePri_MASK', + 'L2_DTC_CONTROL__DTCLRUUpdatePri__SHIFT', + 'L2_DTC_CONTROL__DTCParityEn_MASK', + 'L2_DTC_CONTROL__DTCParityEn__SHIFT', + 'L2_DTC_CONTROL__DTCParitySupport_MASK', + 'L2_DTC_CONTROL__DTCParitySupport__SHIFT', + 'L2_DTC_CONTROL__DTCSoftInvalidate_MASK', + 'L2_DTC_CONTROL__DTCSoftInvalidate__SHIFT', + 'L2_DTC_CONTROL__DTCWays_MASK', 'L2_DTC_CONTROL__DTCWays__SHIFT', + 'L2_DTC_HASH_CONTROL__DTCAddressMask_MASK', + 'L2_DTC_HASH_CONTROL__DTCAddressMask__SHIFT', + 'L2_DTC_WAY_CONTROL__DTCWayAccessDisable_MASK', + 'L2_DTC_WAY_CONTROL__DTCWayAccessDisable__SHIFT', + 'L2_DTC_WAY_CONTROL__DTCWayDisable_MASK', + 'L2_DTC_WAY_CONTROL__DTCWayDisable__SHIFT', + 'L2_ECO_CNTRL_0__L2_ECO_0_MASK', + 'L2_ECO_CNTRL_0__L2_ECO_0__SHIFT', + 'L2_ECO_CNTRL_1__L2_ECO_1_MASK', + 'L2_ECO_CNTRL_1__L2_ECO_1__SHIFT', + 'L2_ERR_RULE_CONTROL_0__ERRRuleDisable0_MASK', + 'L2_ERR_RULE_CONTROL_0__ERRRuleDisable0__SHIFT', + 'L2_ERR_RULE_CONTROL_0__ERRRuleLock0_MASK', + 'L2_ERR_RULE_CONTROL_0__ERRRuleLock0__SHIFT', + 'L2_ERR_RULE_CONTROL_1__ERRRuleDisable1_MASK', + 'L2_ERR_RULE_CONTROL_1__ERRRuleDisable1__SHIFT', + 'L2_ERR_RULE_CONTROL_2__ERRRuleDisable2_MASK', + 'L2_ERR_RULE_CONTROL_2__ERRRuleDisable2__SHIFT', + 'L2_ERR_RULE_CONTROL_3__ERRRuleDisable3_MASK', + 'L2_ERR_RULE_CONTROL_3__ERRRuleDisable3__SHIFT', + 'L2_ERR_RULE_CONTROL_3__ERRRuleLock1_MASK', + 'L2_ERR_RULE_CONTROL_3__ERRRuleLock1__SHIFT', + 'L2_ERR_RULE_CONTROL_4__ERRRuleDisable4_MASK', + 'L2_ERR_RULE_CONTROL_4__ERRRuleDisable4__SHIFT', + 'L2_ERR_RULE_CONTROL_5__ERRRuleDisable5_MASK', + 'L2_ERR_RULE_CONTROL_5__ERRRuleDisable5__SHIFT', + 'L2_ITC_CONTROL__ITCBypass_MASK', + 'L2_ITC_CONTROL__ITCBypass__SHIFT', + 'L2_ITC_CONTROL__ITCEntries_MASK', + 'L2_ITC_CONTROL__ITCEntries__SHIFT', + 'L2_ITC_CONTROL__ITCInvalidationSel_MASK', + 'L2_ITC_CONTROL__ITCInvalidationSel__SHIFT', + 'L2_ITC_CONTROL__ITCLRUUpdatePri_MASK', + 'L2_ITC_CONTROL__ITCLRUUpdatePri__SHIFT', + 'L2_ITC_CONTROL__ITCParityEn_MASK', + 'L2_ITC_CONTROL__ITCParityEn__SHIFT', + 'L2_ITC_CONTROL__ITCParitySupport_MASK', + 'L2_ITC_CONTROL__ITCParitySupport__SHIFT', + 'L2_ITC_CONTROL__ITCSoftInvalidate_MASK', + 'L2_ITC_CONTROL__ITCSoftInvalidate__SHIFT', + 'L2_ITC_CONTROL__ITCWays_MASK', 'L2_ITC_CONTROL__ITCWays__SHIFT', + 'L2_ITC_HASH_CONTROL__ITCAddressMask_MASK', + 'L2_ITC_HASH_CONTROL__ITCAddressMask__SHIFT', + 'L2_ITC_WAY_CONTROL__ITCWayAccessDisable_MASK', + 'L2_ITC_WAY_CONTROL__ITCWayAccessDisable__SHIFT', + 'L2_ITC_WAY_CONTROL__ITCWayDisable_MASK', + 'L2_ITC_WAY_CONTROL__ITCWayDisable__SHIFT', + 'L2_L2A_CK_GATE_CONTROL__CKGateL2ACacheDisable_MASK', + 'L2_L2A_CK_GATE_CONTROL__CKGateL2ACacheDisable__SHIFT', + 'L2_L2A_CK_GATE_CONTROL__CKGateL2ADynamicDisable_MASK', + 'L2_L2A_CK_GATE_CONTROL__CKGateL2ADynamicDisable__SHIFT', + 'L2_L2A_CK_GATE_CONTROL__CKGateL2ALength_MASK', + 'L2_L2A_CK_GATE_CONTROL__CKGateL2ALength__SHIFT', + 'L2_L2A_CK_GATE_CONTROL__CKGateL2APerfDisable_MASK', + 'L2_L2A_CK_GATE_CONTROL__CKGateL2APerfDisable__SHIFT', + 'L2_L2A_CK_GATE_CONTROL__CKGateL2APortClkDis_MASK', + 'L2_L2A_CK_GATE_CONTROL__CKGateL2APortClkDis__SHIFT', + 'L2_L2A_CK_GATE_CONTROL__CKGateL2ARegsDisable_MASK', + 'L2_L2A_CK_GATE_CONTROL__CKGateL2ARegsDisable__SHIFT', + 'L2_L2A_CK_GATE_CONTROL__CKGateL2AStop_MASK', + 'L2_L2A_CK_GATE_CONTROL__CKGateL2AStop__SHIFT', + 'L2_L2A_CK_GATE_CONTROL__Reserved_MASK', + 'L2_L2A_CK_GATE_CONTROL__Reserved__SHIFT', + 'L2_L2A_PGSIZE_CONTROL__L2AREG_GST_PGSIZE_MASK', + 'L2_L2A_PGSIZE_CONTROL__L2AREG_GST_PGSIZE__SHIFT', + 'L2_L2A_PGSIZE_CONTROL__L2AREG_HOST_PGSIZE_MASK', + 'L2_L2A_PGSIZE_CONTROL__L2AREG_HOST_PGSIZE__SHIFT', + 'L2_L2A_PGSIZE_CONTROL__L2AREG_PTCSCAN_MODE_MASK', + 'L2_L2A_PGSIZE_CONTROL__L2AREG_PTCSCAN_MODE__SHIFT', + 'L2_L2B_CK_GATE_CONTROL__CKGateL2BAPCDisable_MASK', + 'L2_L2B_CK_GATE_CONTROL__CKGateL2BAPCDisable__SHIFT', + 'L2_L2B_CK_GATE_CONTROL__CKGateL2BCacheDisable_MASK', + 'L2_L2B_CK_GATE_CONTROL__CKGateL2BCacheDisable__SHIFT', + 'L2_L2B_CK_GATE_CONTROL__CKGateL2BDynamicDisable_MASK', + 'L2_L2B_CK_GATE_CONTROL__CKGateL2BDynamicDisable__SHIFT', + 'L2_L2B_CK_GATE_CONTROL__CKGateL2BLength_MASK', + 'L2_L2B_CK_GATE_CONTROL__CKGateL2BLength__SHIFT', + 'L2_L2B_CK_GATE_CONTROL__CKGateL2BMiscDisable_MASK', + 'L2_L2B_CK_GATE_CONTROL__CKGateL2BMiscDisable__SHIFT', + 'L2_L2B_CK_GATE_CONTROL__CKGateL2BPerfDisable_MASK', + 'L2_L2B_CK_GATE_CONTROL__CKGateL2BPerfDisable__SHIFT', + 'L2_L2B_CK_GATE_CONTROL__CKGateL2BPortClkDis_MASK', + 'L2_L2B_CK_GATE_CONTROL__CKGateL2BPortClkDis__SHIFT', + 'L2_L2B_CK_GATE_CONTROL__CKGateL2BRegsDisable_MASK', + 'L2_L2B_CK_GATE_CONTROL__CKGateL2BRegsDisable__SHIFT', + 'L2_L2B_CK_GATE_CONTROL__CKGateL2BStop_MASK', + 'L2_L2B_CK_GATE_CONTROL__CKGateL2BStop__SHIFT', + 'L2_L2B_CK_GATE_CONTROL__Reserved_MASK', + 'L2_L2B_CK_GATE_CONTROL__Reserved__SHIFT', + 'L2_L2B_PGSIZE_CONTROL__L2BREG_GST_PGSIZE_MASK', + 'L2_L2B_PGSIZE_CONTROL__L2BREG_GST_PGSIZE__SHIFT', + 'L2_L2B_PGSIZE_CONTROL__L2BREG_HOST_PGSIZE_MASK', + 'L2_L2B_PGSIZE_CONTROL__L2BREG_HOST_PGSIZE__SHIFT', + 'L2_PDC_CONTROL__PDCBypass_MASK', + 'L2_PDC_CONTROL__PDCBypass__SHIFT', + 'L2_PDC_CONTROL__PDCEntries_MASK', + 'L2_PDC_CONTROL__PDCEntries__SHIFT', + 'L2_PDC_CONTROL__PDCInvalidationSel_MASK', + 'L2_PDC_CONTROL__PDCInvalidationSel__SHIFT', + 'L2_PDC_CONTROL__PDCLRUUpdatePri_MASK', + 'L2_PDC_CONTROL__PDCLRUUpdatePri__SHIFT', + 'L2_PDC_CONTROL__PDCModeLookupFix_MASK', + 'L2_PDC_CONTROL__PDCModeLookupFix__SHIFT', + 'L2_PDC_CONTROL__PDCParityEn_MASK', + 'L2_PDC_CONTROL__PDCParityEn__SHIFT', + 'L2_PDC_CONTROL__PDCParitySupport_MASK', + 'L2_PDC_CONTROL__PDCParitySupport__SHIFT', + 'L2_PDC_CONTROL__PDCSearchDirection_MASK', + 'L2_PDC_CONTROL__PDCSearchDirection__SHIFT', + 'L2_PDC_CONTROL__PDCSoftInvalidate_MASK', + 'L2_PDC_CONTROL__PDCSoftInvalidate__SHIFT', + 'L2_PDC_CONTROL__PDCWays_MASK', 'L2_PDC_CONTROL__PDCWays__SHIFT', + 'L2_PDC_CONTROL__PDC_Inv_Overlapping_Pages_MASK', + 'L2_PDC_CONTROL__PDC_Inv_Overlapping_Pages__SHIFT', + 'L2_PDC_HASH_CONTROL__PDCAddressMask_MASK', + 'L2_PDC_HASH_CONTROL__PDCAddressMask__SHIFT', + 'L2_PDC_WAY_CONTROL__PDCWayAccessDisable_MASK', + 'L2_PDC_WAY_CONTROL__PDCWayAccessDisable__SHIFT', + 'L2_PDC_WAY_CONTROL__PDCWayDisable_MASK', + 'L2_PDC_WAY_CONTROL__PDCWayDisable__SHIFT', + 'L2_PERF_CNTL_0__L2PerfCountUpper0_MASK', + 'L2_PERF_CNTL_0__L2PerfCountUpper0__SHIFT', + 'L2_PERF_CNTL_0__L2PerfCountUpper1_MASK', + 'L2_PERF_CNTL_0__L2PerfCountUpper1__SHIFT', + 'L2_PERF_CNTL_0__L2PerfEvent0_MASK', + 'L2_PERF_CNTL_0__L2PerfEvent0__SHIFT', + 'L2_PERF_CNTL_0__L2PerfEvent1_MASK', + 'L2_PERF_CNTL_0__L2PerfEvent1__SHIFT', + 'L2_PERF_CNTL_1__L2PerfCountUpper2_MASK', + 'L2_PERF_CNTL_1__L2PerfCountUpper2__SHIFT', + 'L2_PERF_CNTL_1__L2PerfCountUpper3_MASK', + 'L2_PERF_CNTL_1__L2PerfCountUpper3__SHIFT', + 'L2_PERF_CNTL_1__L2PerfEvent2_MASK', + 'L2_PERF_CNTL_1__L2PerfEvent2__SHIFT', + 'L2_PERF_CNTL_1__L2PerfEvent3_MASK', + 'L2_PERF_CNTL_1__L2PerfEvent3__SHIFT', + 'L2_PERF_CNTL_2__L2PerfCountUpper4_MASK', + 'L2_PERF_CNTL_2__L2PerfCountUpper4__SHIFT', + 'L2_PERF_CNTL_2__L2PerfCountUpper5_MASK', + 'L2_PERF_CNTL_2__L2PerfCountUpper5__SHIFT', + 'L2_PERF_CNTL_2__L2PerfEvent4_MASK', + 'L2_PERF_CNTL_2__L2PerfEvent4__SHIFT', + 'L2_PERF_CNTL_2__L2PerfEvent5_MASK', + 'L2_PERF_CNTL_2__L2PerfEvent5__SHIFT', + 'L2_PERF_CNTL_3__L2PerfCountUpper6_MASK', + 'L2_PERF_CNTL_3__L2PerfCountUpper6__SHIFT', + 'L2_PERF_CNTL_3__L2PerfCountUpper7_MASK', + 'L2_PERF_CNTL_3__L2PerfCountUpper7__SHIFT', + 'L2_PERF_CNTL_3__L2PerfEvent6_MASK', + 'L2_PERF_CNTL_3__L2PerfEvent6__SHIFT', + 'L2_PERF_CNTL_3__L2PerfEvent7_MASK', + 'L2_PERF_CNTL_3__L2PerfEvent7__SHIFT', + 'L2_PERF_COUNT_0__L2PerfCount0_MASK', + 'L2_PERF_COUNT_0__L2PerfCount0__SHIFT', + 'L2_PERF_COUNT_1__L2PerfCount1_MASK', + 'L2_PERF_COUNT_1__L2PerfCount1__SHIFT', + 'L2_PERF_COUNT_2__L2PerfCount2_MASK', + 'L2_PERF_COUNT_2__L2PerfCount2__SHIFT', + 'L2_PERF_COUNT_3__L2PerfCount3_MASK', + 'L2_PERF_COUNT_3__L2PerfCount3__SHIFT', + 'L2_PERF_COUNT_4__L2PerfCount4_MASK', + 'L2_PERF_COUNT_4__L2PerfCount4__SHIFT', + 'L2_PERF_COUNT_5__L2PerfCount5_MASK', + 'L2_PERF_COUNT_5__L2PerfCount5__SHIFT', + 'L2_PERF_COUNT_6__L2PerfCount6_MASK', + 'L2_PERF_COUNT_6__L2PerfCount6__SHIFT', + 'L2_PERF_COUNT_7__L2PerfCount7_MASK', + 'L2_PERF_COUNT_7__L2PerfCount7__SHIFT', + 'L2_PTC_A_CONTROL__PCTA_Inv_Overlapping_Pages_MASK', + 'L2_PTC_A_CONTROL__PCTA_Inv_Overlapping_Pages__SHIFT', + 'L2_PTC_A_CONTROL__PTCA2MMode_MASK', + 'L2_PTC_A_CONTROL__PTCA2MMode__SHIFT', + 'L2_PTC_A_CONTROL__PTCABypass_MASK', + 'L2_PTC_A_CONTROL__PTCABypass__SHIFT', + 'L2_PTC_A_CONTROL__PTCAEntries_MASK', + 'L2_PTC_A_CONTROL__PTCAEntries__SHIFT', + 'L2_PTC_A_CONTROL__PTCAFastInvalidateGuest_MASK', + 'L2_PTC_A_CONTROL__PTCAFastInvalidateGuest__SHIFT', + 'L2_PTC_A_CONTROL__PTCAInvalidationSel_MASK', + 'L2_PTC_A_CONTROL__PTCAInvalidationSel__SHIFT', + 'L2_PTC_A_CONTROL__PTCALRUUpdatePri_MASK', + 'L2_PTC_A_CONTROL__PTCALRUUpdatePri__SHIFT', + 'L2_PTC_A_CONTROL__PTCAParityEn_MASK', + 'L2_PTC_A_CONTROL__PTCAParityEn__SHIFT', + 'L2_PTC_A_CONTROL__PTCAParitySupport_MASK', + 'L2_PTC_A_CONTROL__PTCAParitySupport__SHIFT', + 'L2_PTC_A_CONTROL__PTCASoftInvalidate_MASK', + 'L2_PTC_A_CONTROL__PTCASoftInvalidate__SHIFT', + 'L2_PTC_A_CONTROL__PTCAStoreFinalATSeperate_MASK', + 'L2_PTC_A_CONTROL__PTCAStoreFinalATSeperate__SHIFT', + 'L2_PTC_A_CONTROL__PTCAStorePartialATSeperate_MASK', + 'L2_PTC_A_CONTROL__PTCAStorePartialATSeperate__SHIFT', + 'L2_PTC_A_CONTROL__PTCAWays_MASK', + 'L2_PTC_A_CONTROL__PTCAWays__SHIFT', + 'L2_PTC_A_HASH_CONTROL__PTCAAddressMask_MASK', + 'L2_PTC_A_HASH_CONTROL__PTCAAddressMask__SHIFT', + 'L2_PTC_A_WAY_CONTROL__PTCAWayAccessDisable_MASK', + 'L2_PTC_A_WAY_CONTROL__PTCAWayAccessDisable__SHIFT', + 'L2_PTC_A_WAY_CONTROL__PTCAWayDisable_MASK', + 'L2_PTC_A_WAY_CONTROL__PTCAWayDisable__SHIFT', + 'L2_PWRGATE_CNTRL_REG_0__IP_PG_thres_MASK', + 'L2_PWRGATE_CNTRL_REG_0__IP_PG_thres__SHIFT', + 'L2_PWRGATE_CNTRL_REG_3__CFG_FW_PG_EXIT_EN_MASK', + 'L2_PWRGATE_CNTRL_REG_3__CFG_FW_PG_EXIT_EN__SHIFT', + 'L2_PWRGATE_CNTRL_REG_3__IP_PG_busy_MASK', + 'L2_PWRGATE_CNTRL_REG_3__IP_PG_busy__SHIFT', + 'L2_PWRGATE_CNTRL_REG_3__IP_PG_en_MASK', + 'L2_PWRGATE_CNTRL_REG_3__IP_PG_en__SHIFT', + 'L2_PWRGATE_CNTRL_REG_3__L2_PG_STATUS_MASK', + 'L2_PWRGATE_CNTRL_REG_3__L2_PG_STATUS__SHIFT', + 'L2_SB_LOCATION__SBlocated_Core_MASK', + 'L2_SB_LOCATION__SBlocated_Core__SHIFT', + 'L2_SB_LOCATION__SBlocated_Port_MASK', + 'L2_SB_LOCATION__SBlocated_Port__SHIFT', + 'L2_STATUS_0__L2STATUS0_MASK', 'L2_STATUS_0__L2STATUS0__SHIFT', + 'L2_STATUS_1__L2STATUS1_MASK', 'L2_STATUS_1__L2STATUS1__SHIFT', + 'L2_TW_CONTROL_1__TWTraceEn_MASK', + 'L2_TW_CONTROL_1__TWTraceEn__SHIFT', + 'L2_TW_CONTROL_1__TWTraceForceDisable_MASK', + 'L2_TW_CONTROL_1__TWTraceForceDisable__SHIFT', + 'L2_TW_CONTROL_1__TWTraceMask_MASK', + 'L2_TW_CONTROL_1__TWTraceMask__SHIFT', + 'L2_TW_CONTROL_1__TWTraceNoWrap_MASK', + 'L2_TW_CONTROL_1__TWTraceNoWrap__SHIFT', + 'L2_TW_CONTROL_2__TWTraceAddrLo_MASK', + 'L2_TW_CONTROL_2__TWTraceAddrLo__SHIFT', + 'L2_TW_CONTROL_3__TWTraceAddrHi_MASK', + 'L2_TW_CONTROL_3__TWTraceAddrHi__SHIFT', + 'L2_TW_CONTROL__RESERVED_MASK', 'L2_TW_CONTROL__RESERVED__SHIFT', + 'L2_TW_CONTROL__TWCacheNestedPTE_MASK', + 'L2_TW_CONTROL__TWCacheNestedPTE__SHIFT', + 'L2_TW_CONTROL__TWClearAPBit_Dis_MASK', + 'L2_TW_CONTROL__TWClearAPBit_Dis__SHIFT', + 'L2_TW_CONTROL__TWContWalkOnPErrDis_MASK', + 'L2_TW_CONTROL__TWContWalkOnPErrDis__SHIFT', + 'L2_TW_CONTROL__TWFilter_64B_Dis_MASK', + 'L2_TW_CONTROL__TWFilter_64B_Dis__SHIFT', + 'L2_TW_CONTROL__TWFilter_Dis_MASK', + 'L2_TW_CONTROL__TWFilter_Dis__SHIFT', + 'L2_TW_CONTROL__TWForceCoherent_MASK', + 'L2_TW_CONTROL__TWForceCoherent__SHIFT', + 'L2_TW_CONTROL__TWPTEOnAddrTransExcl_MASK', + 'L2_TW_CONTROL__TWPTEOnAddrTransExcl__SHIFT', + 'L2_TW_CONTROL__TWPTEOnUntransExcl_MASK', + 'L2_TW_CONTROL__TWPTEOnUntransExcl__SHIFT', + 'L2_TW_CONTROL__TWPrefetchEn_MASK', + 'L2_TW_CONTROL__TWPrefetchEn__SHIFT', + 'L2_TW_CONTROL__TWPrefetchOnly4KDis_MASK', + 'L2_TW_CONTROL__TWPrefetchOnly4KDis__SHIFT', + 'L2_TW_CONTROL__TWPrefetchRange_MASK', + 'L2_TW_CONTROL__TWPrefetchRange__SHIFT', + 'L2_TW_CONTROL__TWSetAccessBit_Dis_MASK', + 'L2_TW_CONTROL__TWSetAccessBit_Dis__SHIFT', + 'MCA_SMN_INT_APERTUREID__SMN_INT_APERTUREID_MASK', + 'MCA_SMN_INT_APERTUREID__SMN_INT_APERTUREID__SHIFT', + 'MCA_SMN_INT_CONTROL__MCACrossTrigger_MASK', + 'MCA_SMN_INT_CONTROL__MCACrossTrigger__SHIFT', + 'MCA_SMN_INT_MCM_ADDR__SMN_INT_MCM_ADDR_MASK', + 'MCA_SMN_INT_MCM_ADDR__SMN_INT_MCM_ADDR__SHIFT', + 'MCA_SMN_INT_REQ_ADDR__SMN_INT_REQ_ADDR_MASK', + 'MCA_SMN_INT_REQ_ADDR__SMN_INT_REQ_ADDR__SHIFT', + 'MISC_RAS_CONTROL__GNB_SB_LinkNeverDis_MASK', + 'MISC_RAS_CONTROL__GNB_SB_LinkNeverDis__SHIFT', + 'MISC_RAS_CONTROL__InterruptOutputDis_MASK', + 'MISC_RAS_CONTROL__InterruptOutputDis__SHIFT', + 'MISC_RAS_CONTROL__LinkDisOutputDis_MASK', + 'MISC_RAS_CONTROL__LinkDisOutputDis__SHIFT', + 'MISC_RAS_CONTROL__PCIe_NMI_En_MASK', + 'MISC_RAS_CONTROL__PCIe_NMI_En__SHIFT', + 'MISC_RAS_CONTROL__PCIe_SCI_En_MASK', + 'MISC_RAS_CONTROL__PCIe_SCI_En__SHIFT', + 'MISC_RAS_CONTROL__PCIe_SMI_En_MASK', + 'MISC_RAS_CONTROL__PCIe_SMI_En__SHIFT', + 'MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En_MASK', + 'MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En__SHIFT', + 'MISC_RAS_CONTROL__SW_NMI_En_MASK', + 'MISC_RAS_CONTROL__SW_NMI_En__SHIFT', + 'MISC_RAS_CONTROL__SW_SCI_En_MASK', + 'MISC_RAS_CONTROL__SW_SCI_En__SHIFT', + 'MISC_RAS_CONTROL__SW_SMI_En_MASK', + 'MISC_RAS_CONTROL__SW_SMI_En__SHIFT', + 'MISC_RAS_CONTROL__SyncFldOutputDis_MASK', + 'MISC_RAS_CONTROL__SyncFldOutputDis__SHIFT', + 'MISC_SCRATCH__MISC_SCRATCH0_MASK', + 'MISC_SCRATCH__MISC_SCRATCH0__SHIFT', + 'MISC_SEVERITY_CONTROL__ErrEventErrSev_MASK', + 'MISC_SEVERITY_CONTROL__ErrEventErrSev__SHIFT', + 'MISC_SEVERITY_CONTROL__PcieParityErrSev_MASK', + 'MISC_SEVERITY_CONTROL__PcieParityErrSev__SHIFT', + 'NBIF1PortAExtCorr_ACTION_CONTROL__APML_ERR_En_MASK', + 'NBIF1PortAExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'NBIF1PortAExtCorr_ACTION_CONTROL__IntrGenSel_MASK', + 'NBIF1PortAExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'NBIF1PortAExtCorr_ACTION_CONTROL__LinkDis_En_MASK', + 'NBIF1PortAExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'NBIF1PortAExtCorr_ACTION_CONTROL__SyncFlood_En_MASK', + 'NBIF1PortAExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'NBIF1PortAExtFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'NBIF1PortAExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'NBIF1PortAExtFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'NBIF1PortAExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'NBIF1PortAExtFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'NBIF1PortAExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'NBIF1PortAExtFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'NBIF1PortAExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'NBIF1PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'NBIF1PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'NBIF1PortAExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'NBIF1PortAExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'NBIF1PortAExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'NBIF1PortAExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'NBIF1PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'NBIF1PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'NBIF1PortAIntCorr_ACTION_CONTROL__APML_ERR_En_MASK', + 'NBIF1PortAIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'NBIF1PortAIntCorr_ACTION_CONTROL__IntrGenSel_MASK', + 'NBIF1PortAIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'NBIF1PortAIntCorr_ACTION_CONTROL__LinkDis_En_MASK', + 'NBIF1PortAIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'NBIF1PortAIntCorr_ACTION_CONTROL__SyncFlood_En_MASK', + 'NBIF1PortAIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'NBIF1PortAIntFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'NBIF1PortAIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'NBIF1PortAIntFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'NBIF1PortAIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'NBIF1PortAIntFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'NBIF1PortAIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'NBIF1PortAIntFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'NBIF1PortAIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'NBIF1PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'NBIF1PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'NBIF1PortAIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'NBIF1PortAIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'NBIF1PortAIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'NBIF1PortAIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'NBIF1PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'NBIF1PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'NBIF1PortAParityErr_ACTION_CONTROL__APML_ERR_En_MASK', + 'NBIF1PortAParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'NBIF1PortAParityErr_ACTION_CONTROL__IntrGenSel_MASK', + 'NBIF1PortAParityErr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'NBIF1PortAParityErr_ACTION_CONTROL__LinkDis_En_MASK', + 'NBIF1PortAParityErr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'NBIF1PortAParityErr_ACTION_CONTROL__SyncFlood_En_MASK', + 'NBIF1PortAParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'NBIF1PortASerr_ACTION_CONTROL__APML_ERR_En_MASK', + 'NBIF1PortASerr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'NBIF1PortASerr_ACTION_CONTROL__IntrGenSel_MASK', + 'NBIF1PortASerr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'NBIF1PortASerr_ACTION_CONTROL__LinkDis_En_MASK', + 'NBIF1PortASerr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'NBIF1PortASerr_ACTION_CONTROL__SyncFlood_En_MASK', + 'NBIF1PortASerr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE_MASK', + 'NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT', + 'NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK', + 'NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT', + 'NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK', + 'NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT', + 'NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK', + 'NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT', + 'NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK', + 'NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT', + 'NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK', + 'NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT', + 'NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK', + 'NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT', + 'NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK', + 'NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT', + 'NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN_MASK', + 'NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN__SHIFT', + 'NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP_MASK', + 'NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP__SHIFT', + 'NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS_MASK', + 'NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS__SHIFT', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK', + 'NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK__SHIFT', + 'NBIF_MGCG_CTRL_LCLK__NBIF_SRAM_FGCG_EN_LCLK_MASK', + 'NBIF_MGCG_CTRL_LCLK__NBIF_SRAM_FGCG_EN_LCLK__SHIFT', + 'NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS_MASK', + 'NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS__SHIFT', + 'NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS_MASK', + 'NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS__SHIFT', + 'NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN_MASK', + 'NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN__SHIFT', + 'NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN_MASK', + 'NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN__SHIFT', + 'NBIF_PGMST_CTRL__NBIF_CFG_PG_EN_MASK', + 'NBIF_PGMST_CTRL__NBIF_CFG_PG_EN__SHIFT', + 'NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS_MASK', + 'NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS__SHIFT', + 'NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS_MASK', + 'NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS__SHIFT', + 'NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE_MASK', + 'NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE__SHIFT', + 'NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS_MASK', + 'NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT', + 'NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK', + 'NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT', + 'NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK', + 'NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT', + 'NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1_MASK', + 'NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1__SHIFT', + 'NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2_MASK', + 'NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2__SHIFT', + 'NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS_MASK', + 'NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS__SHIFT', + 'NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY_MASK', + 'NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY__SHIFT', + 'NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK_MASK', + 'NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK__SHIFT', + 'NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST_MASK', + 'NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST__SHIFT', + 'NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK', + 'NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT', + 'NBIF_RRMT_CNTL__AID_DIE_ID_MASK', + 'NBIF_RRMT_CNTL__AID_DIE_ID__SHIFT', + 'NBIF_RRMT_CNTL__PARTITION_MODE_MASK', + 'NBIF_RRMT_CNTL__PARTITION_MODE__SHIFT', + 'NBIF_RRMT_CNTL__RRMT_ENABLE_MASK', + 'NBIF_RRMT_CNTL__RRMT_ENABLE__SHIFT', + 'NBIF_RRMT_CNTL__RRMT_Invalid_Address_H_MASK', + 'NBIF_RRMT_CNTL__RRMT_Invalid_Address_H__SHIFT', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK', + 'NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK', + 'NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK', + 'NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT', + 'NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2_MASK', + 'NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2__SHIFT', + 'NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN_MASK', + 'NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN__SHIFT', + 'NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2_MASK', + 'NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2__SHIFT', + 'NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS_MASK', + 'NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS__SHIFT', + 'NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT_MASK', + 'NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT__SHIFT', + 'NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN_MASK', + 'NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN__SHIFT', + 'NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN_MASK', + 'NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN__SHIFT', + 'NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT_MASK', + 'NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT__SHIFT', + 'NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2_MASK', + 'NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2__SHIFT', + 'NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN_MASK', + 'NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS_MASK', + 'NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV_MASK', + 'NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG_MASK', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG_MASK', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG_MASK', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG_MASK', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG_MASK', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG_MASK', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG_MASK', + 'NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS_MASK', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS_MASK', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS_MASK', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS_MASK', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS_MASK', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS_MASK', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS_MASK', + 'NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT', + 'NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN_MASK', + 'NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN__SHIFT', + 'NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN_MASK', + 'NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN__SHIFT', + 'NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE_MASK', + 'NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT', + 'NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS_MASK', + 'NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS__SHIFT', + 'NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS_MASK', + 'NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS__SHIFT', + 'NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK', + 'NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT', + 'NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK', + 'NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT', + 'NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK', + 'NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT', + 'NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK', + 'NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT', + 'NBIO_LCLK_DS_MASK__LCLK_DS_MASK_MASK', + 'NBIO_LCLK_DS_MASK__LCLK_DS_MASK__SHIFT', + 'NB_BUS_NUM_CNTL__NB_BUS_LAT_Mode_MASK', + 'NB_BUS_NUM_CNTL__NB_BUS_LAT_Mode__SHIFT', + 'NB_BUS_NUM_CNTL__NB_BUS_NUM_MASK', + 'NB_BUS_NUM_CNTL__NB_BUS_NUM__SHIFT', + 'NB_BUS_NUM_CNTL__NB_SEGMENT_MASK', + 'NB_BUS_NUM_CNTL__NB_SEGMENT__SHIFT', + 'NB_CNTL__HWINIT_WR_LOCK_MASK', 'NB_CNTL__HWINIT_WR_LOCK__SHIFT', + 'NB_DRAM3_BASE__DRAM3_BASE_MASK', + 'NB_DRAM3_BASE__DRAM3_BASE__SHIFT', + 'NB_INTSBDEVINDCFG0_STEERING_CNTL__ForceSteering_MASK', + 'NB_INTSBDEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT', + 'NB_INTSBDEVINDCFG0_STEERING_CNTL__SteeringValue_MASK', + 'NB_INTSBDEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT', + 'NB_LOWER_DRAM2_BASE__LOWER_DRAM2_BASE_MASK', + 'NB_LOWER_DRAM2_BASE__LOWER_DRAM2_BASE__SHIFT', + 'NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK', + 'NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT', + 'NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK', + 'NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT', + 'NB_MMIOBASE__MMIOBASE_MASK', 'NB_MMIOBASE__MMIOBASE__SHIFT', + 'NB_MMIOLIMIT__MMIOLIMIT_MASK', 'NB_MMIOLIMIT__MMIOLIMIT__SHIFT', + 'NB_NBCFG0_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4_MASK', + 'NB_NBCFG0_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4__SHIFT', + 'NB_NBIF1DEVINDCFG0_STEERING_CNTL__ForceSteering_MASK', + 'NB_NBIF1DEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT', + 'NB_NBIF1DEVINDCFG0_STEERING_CNTL__SteeringValue_MASK', + 'NB_NBIF1DEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT', + 'NB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA_MASK', + 'NB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA__SHIFT', + 'NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK', + 'NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT', + 'NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX_MASK', + 'NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT', + 'NB_PCIE0DEVINDCFG0_STEERING_CNTL__ForceSteering_MASK', + 'NB_PCIE0DEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT', + 'NB_PCIE0DEVINDCFG0_STEERING_CNTL__SteeringValue_MASK', + 'NB_PCIE0DEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT', + 'NB_PCIE0DEVINDCFG1_STEERING_CNTL__ForceSteering_MASK', + 'NB_PCIE0DEVINDCFG1_STEERING_CNTL__ForceSteering__SHIFT', + 'NB_PCIE0DEVINDCFG1_STEERING_CNTL__SteeringValue_MASK', + 'NB_PCIE0DEVINDCFG1_STEERING_CNTL__SteeringValue__SHIFT', + 'NB_PCIE0DEVINDCFG2_STEERING_CNTL__ForceSteering_MASK', + 'NB_PCIE0DEVINDCFG2_STEERING_CNTL__ForceSteering__SHIFT', + 'NB_PCIE0DEVINDCFG2_STEERING_CNTL__SteeringValue_MASK', + 'NB_PCIE0DEVINDCFG2_STEERING_CNTL__SteeringValue__SHIFT', + 'NB_PCIE0DEVINDCFG3_STEERING_CNTL__ForceSteering_MASK', + 'NB_PCIE0DEVINDCFG3_STEERING_CNTL__ForceSteering__SHIFT', + 'NB_PCIE0DEVINDCFG3_STEERING_CNTL__SteeringValue_MASK', + 'NB_PCIE0DEVINDCFG3_STEERING_CNTL__SteeringValue__SHIFT', + 'NB_PCIE0DEVINDCFG4_STEERING_CNTL__ForceSteering_MASK', + 'NB_PCIE0DEVINDCFG4_STEERING_CNTL__ForceSteering__SHIFT', + 'NB_PCIE0DEVINDCFG4_STEERING_CNTL__SteeringValue_MASK', + 'NB_PCIE0DEVINDCFG4_STEERING_CNTL__SteeringValue__SHIFT', + 'NB_PCIE0DEVINDCFG5_STEERING_CNTL__ForceSteering_MASK', + 'NB_PCIE0DEVINDCFG5_STEERING_CNTL__ForceSteering__SHIFT', + 'NB_PCIE0DEVINDCFG5_STEERING_CNTL__SteeringValue_MASK', + 'NB_PCIE0DEVINDCFG5_STEERING_CNTL__SteeringValue__SHIFT', + 'NB_PCIE0DEVINDCFG6_STEERING_CNTL__ForceSteering_MASK', + 'NB_PCIE0DEVINDCFG6_STEERING_CNTL__ForceSteering__SHIFT', + 'NB_PCIE0DEVINDCFG6_STEERING_CNTL__SteeringValue_MASK', + 'NB_PCIE0DEVINDCFG6_STEERING_CNTL__SteeringValue__SHIFT', + 'NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA_MASK', + 'NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA__SHIFT', + 'NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK', + 'NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT', + 'NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX_MASK', + 'NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT', + 'NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA_MASK', + 'NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA__SHIFT', + 'NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK', + 'NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT', + 'NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX_MASK', + 'NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT', + 'NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA__RC_SMN_DATA_MASK', + 'NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA__RC_SMN_DATA__SHIFT', + 'NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK', + 'NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT', + 'NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX__RC_SMN_INDEX_MASK', + 'NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT', + 'NB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA__RC_SMN_DATA_MASK', + 'NB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA__RC_SMN_DATA__SHIFT', + 'NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK', + 'NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT', + 'NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX__RC_SMN_INDEX_MASK', + 'NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT', + 'NB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA__RC_SMN_DATA_MASK', + 'NB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA__RC_SMN_DATA__SHIFT', + 'NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK', + 'NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT', + 'NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX__RC_SMN_INDEX_MASK', + 'NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT', + 'NB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA__RC_SMN_DATA_MASK', + 'NB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA__RC_SMN_DATA__SHIFT', + 'NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK', + 'NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT', + 'NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX__RC_SMN_INDEX_MASK', + 'NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT', + 'NB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA__RC_SMN_DATA_MASK', + 'NB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA__RC_SMN_DATA__SHIFT', + 'NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK', + 'NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT', + 'NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX__RC_SMN_INDEX_MASK', + 'NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT', + 'NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap_MASK', + 'NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap__SHIFT', + 'NB_PROG_DEVICE_REMAP_PBr10__PBr10_DevFnMap_MASK', + 'NB_PROG_DEVICE_REMAP_PBr10__PBr10_DevFnMap__SHIFT', + 'NB_PROG_DEVICE_REMAP_PBr11__PBr11_DevFnMap_MASK', + 'NB_PROG_DEVICE_REMAP_PBr11__PBr11_DevFnMap__SHIFT', + 'NB_PROG_DEVICE_REMAP_PBr12__PBr12_DevFnMap_MASK', + 'NB_PROG_DEVICE_REMAP_PBr12__PBr12_DevFnMap__SHIFT', + 'NB_PROG_DEVICE_REMAP_PBr13__PBr13_DevFnMap_MASK', + 'NB_PROG_DEVICE_REMAP_PBr13__PBr13_DevFnMap__SHIFT', + 'NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap_MASK', + 'NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap__SHIFT', + 'NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap_MASK', + 'NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap__SHIFT', + 'NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap_MASK', + 'NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap__SHIFT', + 'NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap_MASK', + 'NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap__SHIFT', + 'NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap_MASK', + 'NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap__SHIFT', + 'NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap_MASK', + 'NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap__SHIFT', + 'NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap_MASK', + 'NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap__SHIFT', + 'NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap_MASK', + 'NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap__SHIFT', + 'NB_REVID__REVISION_ID_MASK', 'NB_REVID__REVISION_ID__SHIFT', + 'NB_SPARE1__NB_SPARE1_RW_MASK', 'NB_SPARE1__NB_SPARE1_RW__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_0_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_0__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_10_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_10__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_11_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_11__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_12_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_12__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_13_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_13__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_14_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_14__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_15_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_15__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_16_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_16__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_17_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_17__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_18_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_18__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_19_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_19__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_1_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_1__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_20_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_20__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_21_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_21__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_22_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_22__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_23_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_23__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_24_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_24__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_25_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_25__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_26_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_26__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_27_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_27__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_28_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_28__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_29_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_29__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_2_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_2__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_30_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_30__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_31_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_31__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_3_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_3__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_4_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_4__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_5_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_5__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_6_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_6__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_7_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_7__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_8_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_8__SHIFT', + 'NB_SPARE2__NB_SPARE2_RW1C_9_MASK', + 'NB_SPARE2__NB_SPARE2_RW1C_9__SHIFT', + 'NB_TOP_OF_DRAM3__TOM3_ENABLE_MASK', + 'NB_TOP_OF_DRAM3__TOM3_ENABLE__SHIFT', + 'NB_TOP_OF_DRAM3__TOM3_LIMIT_MASK', + 'NB_TOP_OF_DRAM3__TOM3_LIMIT__SHIFT', + 'NB_UPPER_DRAM2_BASE__UPPER_DRAM2_BASE_MASK', + 'NB_UPPER_DRAM2_BASE__UPPER_DRAM2_BASE__SHIFT', + 'NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK', + 'NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT', + 'NIC400_1_ASIB_0_FN_MOD__read_iss_override_MASK', + 'NIC400_1_ASIB_0_FN_MOD__read_iss_override__SHIFT', + 'NIC400_1_ASIB_0_FN_MOD__write_iss_override_MASK', + 'NIC400_1_ASIB_0_FN_MOD__write_iss_override__SHIFT', + 'NIC400_1_IB_0_FN_MOD__read_iss_override_MASK', + 'NIC400_1_IB_0_FN_MOD__read_iss_override__SHIFT', + 'NIC400_1_IB_0_FN_MOD__write_iss_override_MASK', + 'NIC400_1_IB_0_FN_MOD__write_iss_override__SHIFT', + 'NIC400_2_ASIB_0_AR_B__ar_b_MASK', + 'NIC400_2_ASIB_0_AR_B__ar_b__SHIFT', + 'NIC400_2_ASIB_0_AR_P__ar_p_MASK', + 'NIC400_2_ASIB_0_AR_P__ar_p__SHIFT', + 'NIC400_2_ASIB_0_AR_R__ar_r_MASK', + 'NIC400_2_ASIB_0_AR_R__ar_r__SHIFT', + 'NIC400_2_ASIB_0_AW_B__aw_b_MASK', + 'NIC400_2_ASIB_0_AW_B__aw_b__SHIFT', + 'NIC400_2_ASIB_0_AW_P__aw_p_MASK', + 'NIC400_2_ASIB_0_AW_P__aw_p__SHIFT', + 'NIC400_2_ASIB_0_AW_R__aw_r_MASK', + 'NIC400_2_ASIB_0_AW_R__aw_r__SHIFT', + 'NIC400_2_ASIB_0_FN_MOD__read_iss_override_MASK', + 'NIC400_2_ASIB_0_FN_MOD__read_iss_override__SHIFT', + 'NIC400_2_ASIB_0_FN_MOD__write_iss_override_MASK', + 'NIC400_2_ASIB_0_FN_MOD__write_iss_override__SHIFT', + 'NIC400_2_ASIB_0_KI_FC__ar_tgt_latency_MASK', + 'NIC400_2_ASIB_0_KI_FC__ar_tgt_latency__SHIFT', + 'NIC400_2_ASIB_0_KI_FC__aw_tgt_latency_MASK', + 'NIC400_2_ASIB_0_KI_FC__aw_tgt_latency__SHIFT', + 'NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_otf_MASK', + 'NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_otf__SHIFT', + 'NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_oti_MASK', + 'NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_oti__SHIFT', + 'NIC400_2_ASIB_0_MAX_OT__ar_max_otf_MASK', + 'NIC400_2_ASIB_0_MAX_OT__ar_max_otf__SHIFT', + 'NIC400_2_ASIB_0_MAX_OT__ar_max_oti_MASK', + 'NIC400_2_ASIB_0_MAX_OT__ar_max_oti__SHIFT', + 'NIC400_2_ASIB_0_MAX_OT__aw_max_otf_MASK', + 'NIC400_2_ASIB_0_MAX_OT__aw_max_otf__SHIFT', + 'NIC400_2_ASIB_0_MAX_OT__aw_max_oti_MASK', + 'NIC400_2_ASIB_0_MAX_OT__aw_max_oti__SHIFT', + 'NIC400_2_ASIB_0_QOS_CNTL__en_ar_fc_MASK', + 'NIC400_2_ASIB_0_QOS_CNTL__en_ar_fc__SHIFT', + 'NIC400_2_ASIB_0_QOS_CNTL__en_ar_ot_MASK', + 'NIC400_2_ASIB_0_QOS_CNTL__en_ar_ot__SHIFT', + 'NIC400_2_ASIB_0_QOS_CNTL__en_ar_rate_MASK', + 'NIC400_2_ASIB_0_QOS_CNTL__en_ar_rate__SHIFT', + 'NIC400_2_ASIB_0_QOS_CNTL__en_aw_fc_MASK', + 'NIC400_2_ASIB_0_QOS_CNTL__en_aw_fc__SHIFT', + 'NIC400_2_ASIB_0_QOS_CNTL__en_aw_ot_MASK', + 'NIC400_2_ASIB_0_QOS_CNTL__en_aw_ot__SHIFT', + 'NIC400_2_ASIB_0_QOS_CNTL__en_aw_rate_MASK', + 'NIC400_2_ASIB_0_QOS_CNTL__en_aw_rate__SHIFT', + 'NIC400_2_ASIB_0_QOS_CNTL__en_awar_ot_MASK', + 'NIC400_2_ASIB_0_QOS_CNTL__en_awar_ot__SHIFT', + 'NIC400_2_ASIB_0_QOS_CNTL__en_awar_rate_MASK', + 'NIC400_2_ASIB_0_QOS_CNTL__en_awar_rate__SHIFT', + 'NIC400_2_ASIB_0_QOS_CNTL__mode_ar_fc_MASK', + 'NIC400_2_ASIB_0_QOS_CNTL__mode_ar_fc__SHIFT', + 'NIC400_2_ASIB_0_QOS_CNTL__mode_aw_fc_MASK', + 'NIC400_2_ASIB_0_QOS_CNTL__mode_aw_fc__SHIFT', + 'NIC400_2_ASIB_0_QOS_RANGE__ar_max_qos_MASK', + 'NIC400_2_ASIB_0_QOS_RANGE__ar_max_qos__SHIFT', + 'NIC400_2_ASIB_0_QOS_RANGE__ar_min_qos_MASK', + 'NIC400_2_ASIB_0_QOS_RANGE__ar_min_qos__SHIFT', + 'NIC400_2_ASIB_0_QOS_RANGE__aw_max_qos_MASK', + 'NIC400_2_ASIB_0_QOS_RANGE__aw_max_qos__SHIFT', + 'NIC400_2_ASIB_0_QOS_RANGE__aw_min_qos_MASK', + 'NIC400_2_ASIB_0_QOS_RANGE__aw_min_qos__SHIFT', + 'NIC400_2_ASIB_0_TARGET_FC__ar_tgt_latency_MASK', + 'NIC400_2_ASIB_0_TARGET_FC__ar_tgt_latency__SHIFT', + 'NIC400_2_ASIB_0_TARGET_FC__aw_tgt_latency_MASK', + 'NIC400_2_ASIB_0_TARGET_FC__aw_tgt_latency__SHIFT', + 'NIC400_2_ASIB_1_AR_B__ar_b_MASK', + 'NIC400_2_ASIB_1_AR_B__ar_b__SHIFT', + 'NIC400_2_ASIB_1_AR_P__ar_p_MASK', + 'NIC400_2_ASIB_1_AR_P__ar_p__SHIFT', + 'NIC400_2_ASIB_1_AR_R__ar_r_MASK', + 'NIC400_2_ASIB_1_AR_R__ar_r__SHIFT', + 'NIC400_2_ASIB_1_AW_B__aw_b_MASK', + 'NIC400_2_ASIB_1_AW_B__aw_b__SHIFT', + 'NIC400_2_ASIB_1_AW_P__aw_p_MASK', + 'NIC400_2_ASIB_1_AW_P__aw_p__SHIFT', + 'NIC400_2_ASIB_1_AW_R__aw_r_MASK', + 'NIC400_2_ASIB_1_AW_R__aw_r__SHIFT', + 'NIC400_2_ASIB_1_FN_MOD__read_iss_override_MASK', + 'NIC400_2_ASIB_1_FN_MOD__read_iss_override__SHIFT', + 'NIC400_2_ASIB_1_FN_MOD__write_iss_override_MASK', + 'NIC400_2_ASIB_1_FN_MOD__write_iss_override__SHIFT', + 'NIC400_2_ASIB_1_KI_FC__ar_tgt_latency_MASK', + 'NIC400_2_ASIB_1_KI_FC__ar_tgt_latency__SHIFT', + 'NIC400_2_ASIB_1_KI_FC__aw_tgt_latency_MASK', + 'NIC400_2_ASIB_1_KI_FC__aw_tgt_latency__SHIFT', + 'NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_otf_MASK', + 'NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_otf__SHIFT', + 'NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_oti_MASK', + 'NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_oti__SHIFT', + 'NIC400_2_ASIB_1_MAX_OT__ar_max_otf_MASK', + 'NIC400_2_ASIB_1_MAX_OT__ar_max_otf__SHIFT', + 'NIC400_2_ASIB_1_MAX_OT__ar_max_oti_MASK', + 'NIC400_2_ASIB_1_MAX_OT__ar_max_oti__SHIFT', + 'NIC400_2_ASIB_1_MAX_OT__aw_max_otf_MASK', + 'NIC400_2_ASIB_1_MAX_OT__aw_max_otf__SHIFT', + 'NIC400_2_ASIB_1_MAX_OT__aw_max_oti_MASK', + 'NIC400_2_ASIB_1_MAX_OT__aw_max_oti__SHIFT', + 'NIC400_2_ASIB_1_QOS_CNTL__en_ar_fc_MASK', + 'NIC400_2_ASIB_1_QOS_CNTL__en_ar_fc__SHIFT', + 'NIC400_2_ASIB_1_QOS_CNTL__en_ar_ot_MASK', + 'NIC400_2_ASIB_1_QOS_CNTL__en_ar_ot__SHIFT', + 'NIC400_2_ASIB_1_QOS_CNTL__en_ar_rate_MASK', + 'NIC400_2_ASIB_1_QOS_CNTL__en_ar_rate__SHIFT', + 'NIC400_2_ASIB_1_QOS_CNTL__en_aw_fc_MASK', + 'NIC400_2_ASIB_1_QOS_CNTL__en_aw_fc__SHIFT', + 'NIC400_2_ASIB_1_QOS_CNTL__en_aw_ot_MASK', + 'NIC400_2_ASIB_1_QOS_CNTL__en_aw_ot__SHIFT', + 'NIC400_2_ASIB_1_QOS_CNTL__en_aw_rate_MASK', + 'NIC400_2_ASIB_1_QOS_CNTL__en_aw_rate__SHIFT', + 'NIC400_2_ASIB_1_QOS_CNTL__en_awar_ot_MASK', + 'NIC400_2_ASIB_1_QOS_CNTL__en_awar_ot__SHIFT', + 'NIC400_2_ASIB_1_QOS_CNTL__en_awar_rate_MASK', + 'NIC400_2_ASIB_1_QOS_CNTL__en_awar_rate__SHIFT', + 'NIC400_2_ASIB_1_QOS_CNTL__mode_ar_fc_MASK', + 'NIC400_2_ASIB_1_QOS_CNTL__mode_ar_fc__SHIFT', + 'NIC400_2_ASIB_1_QOS_CNTL__mode_aw_fc_MASK', + 'NIC400_2_ASIB_1_QOS_CNTL__mode_aw_fc__SHIFT', + 'NIC400_2_ASIB_1_QOS_RANGE__ar_max_qos_MASK', + 'NIC400_2_ASIB_1_QOS_RANGE__ar_max_qos__SHIFT', + 'NIC400_2_ASIB_1_QOS_RANGE__ar_min_qos_MASK', + 'NIC400_2_ASIB_1_QOS_RANGE__ar_min_qos__SHIFT', + 'NIC400_2_ASIB_1_QOS_RANGE__aw_max_qos_MASK', + 'NIC400_2_ASIB_1_QOS_RANGE__aw_max_qos__SHIFT', + 'NIC400_2_ASIB_1_QOS_RANGE__aw_min_qos_MASK', + 'NIC400_2_ASIB_1_QOS_RANGE__aw_min_qos__SHIFT', + 'NIC400_2_ASIB_1_TARGET_FC__ar_tgt_latency_MASK', + 'NIC400_2_ASIB_1_TARGET_FC__ar_tgt_latency__SHIFT', + 'NIC400_2_ASIB_1_TARGET_FC__aw_tgt_latency_MASK', + 'NIC400_2_ASIB_1_TARGET_FC__aw_tgt_latency__SHIFT', + 'NIC400_2_IB_0_FN_MOD__read_iss_override_MASK', + 'NIC400_2_IB_0_FN_MOD__read_iss_override__SHIFT', + 'NIC400_2_IB_0_FN_MOD__write_iss_override_MASK', + 'NIC400_2_IB_0_FN_MOD__write_iss_override__SHIFT', + 'NMI_STATUS__NMIFromPin_MASK', 'NMI_STATUS__NMIFromPin__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_0_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_0__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_10_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_10__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_11_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_11__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_12_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_12__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_13_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_13__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_14_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_14__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_15_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_15__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_16_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_16__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_17_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_17__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_18_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_18__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_19_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_19__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_1_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_1__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_20_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_20__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_21_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_21__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_22_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_22__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_23_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_23__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_24_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_24__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_25_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_25__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_26_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_26__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_27_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_27__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_28_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_28__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_29_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_29__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_2_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_2__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_30_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_30__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_31_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_31__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_3_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_3__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_4_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_4__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_5_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_5__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_6_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_6__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_7_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_7__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_8_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_8__SHIFT', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_9_MASK', + 'NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_9__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_0_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_0__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_10_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_10__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_11_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_11__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_12_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_12__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_13_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_13__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_14_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_14__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_15_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_15__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_16_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_16__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_17_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_17__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_18_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_18__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_19_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_19__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_1_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_1__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_20_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_20__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_21_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_21__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_22_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_22__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_23_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_23__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_24_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_24__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_25_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_25__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_26_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_26__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_27_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_27__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_28_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_28__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_29_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_29__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_2_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_2__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_30_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_30__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_31_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_31__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_3_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_3__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_4_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_4__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_5_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_5__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_6_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_6__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_7_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_7__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_8_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_8__SHIFT', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_9_MASK', + 'NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_9__SHIFT', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK', + 'OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT', + 'OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK', + 'OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT', + 'OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK', + 'OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT', + 'OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK', + 'OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT', + 'PARITY_CONTROL_0__ParityCorrThreshold_MASK', + 'PARITY_CONTROL_0__ParityCorrThreshold__SHIFT', + 'PARITY_CONTROL_0__ParityUCPThreshold_MASK', + 'PARITY_CONTROL_0__ParityUCPThreshold__SHIFT', + 'PARITY_CONTROL_1__ParityErrGenCmd_MASK', + 'PARITY_CONTROL_1__ParityErrGenCmd__SHIFT', + 'PARITY_CONTROL_1__ParityErrGenGroupSel_MASK', + 'PARITY_CONTROL_1__ParityErrGenGroupSel__SHIFT', + 'PARITY_CONTROL_1__ParityErrGenGroupTypeSel_MASK', + 'PARITY_CONTROL_1__ParityErrGenGroupTypeSel__SHIFT', + 'PARITY_CONTROL_1__ParityErrGenIdSel_MASK', + 'PARITY_CONTROL_1__ParityErrGenIdSel__SHIFT', + 'PARITY_CONTROL_1__ParityErrGenInjectAllow_MASK', + 'PARITY_CONTROL_1__ParityErrGenInjectAllow__SHIFT', + 'PARITY_CONTROL_1__ParityErrGenTrigger_MASK', + 'PARITY_CONTROL_1__ParityErrGenTrigger__SHIFT', + 'PARITY_COUNTER_CORR_GRP0__ResetEn_MASK', + 'PARITY_COUNTER_CORR_GRP0__ResetEn__SHIFT', + 'PARITY_COUNTER_CORR_GRP0__ThresholdCounter_MASK', + 'PARITY_COUNTER_CORR_GRP0__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_CORR_GRP10__ResetEn_MASK', + 'PARITY_COUNTER_CORR_GRP10__ResetEn__SHIFT', + 'PARITY_COUNTER_CORR_GRP10__ThresholdCounter_MASK', + 'PARITY_COUNTER_CORR_GRP10__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_CORR_GRP11__ResetEn_MASK', + 'PARITY_COUNTER_CORR_GRP11__ResetEn__SHIFT', + 'PARITY_COUNTER_CORR_GRP11__ThresholdCounter_MASK', + 'PARITY_COUNTER_CORR_GRP11__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_CORR_GRP12__ResetEn_MASK', + 'PARITY_COUNTER_CORR_GRP12__ResetEn__SHIFT', + 'PARITY_COUNTER_CORR_GRP12__ThresholdCounter_MASK', + 'PARITY_COUNTER_CORR_GRP12__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_CORR_GRP13__ResetEn_MASK', + 'PARITY_COUNTER_CORR_GRP13__ResetEn__SHIFT', + 'PARITY_COUNTER_CORR_GRP13__ThresholdCounter_MASK', + 'PARITY_COUNTER_CORR_GRP13__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_CORR_GRP14__ResetEn_MASK', + 'PARITY_COUNTER_CORR_GRP14__ResetEn__SHIFT', + 'PARITY_COUNTER_CORR_GRP14__ThresholdCounter_MASK', + 'PARITY_COUNTER_CORR_GRP14__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_CORR_GRP15__ResetEn_MASK', + 'PARITY_COUNTER_CORR_GRP15__ResetEn__SHIFT', + 'PARITY_COUNTER_CORR_GRP15__ThresholdCounter_MASK', + 'PARITY_COUNTER_CORR_GRP15__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_CORR_GRP16__ResetEn_MASK', + 'PARITY_COUNTER_CORR_GRP16__ResetEn__SHIFT', + 'PARITY_COUNTER_CORR_GRP16__ThresholdCounter_MASK', + 'PARITY_COUNTER_CORR_GRP16__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_CORR_GRP17__ResetEn_MASK', + 'PARITY_COUNTER_CORR_GRP17__ResetEn__SHIFT', + 'PARITY_COUNTER_CORR_GRP17__ThresholdCounter_MASK', + 'PARITY_COUNTER_CORR_GRP17__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_CORR_GRP1__ResetEn_MASK', + 'PARITY_COUNTER_CORR_GRP1__ResetEn__SHIFT', + 'PARITY_COUNTER_CORR_GRP1__ThresholdCounter_MASK', + 'PARITY_COUNTER_CORR_GRP1__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_CORR_GRP2__ResetEn_MASK', + 'PARITY_COUNTER_CORR_GRP2__ResetEn__SHIFT', + 'PARITY_COUNTER_CORR_GRP2__ThresholdCounter_MASK', + 'PARITY_COUNTER_CORR_GRP2__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_CORR_GRP3__ResetEn_MASK', + 'PARITY_COUNTER_CORR_GRP3__ResetEn__SHIFT', + 'PARITY_COUNTER_CORR_GRP3__ThresholdCounter_MASK', + 'PARITY_COUNTER_CORR_GRP3__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_CORR_GRP4__ResetEn_MASK', + 'PARITY_COUNTER_CORR_GRP4__ResetEn__SHIFT', + 'PARITY_COUNTER_CORR_GRP4__ThresholdCounter_MASK', + 'PARITY_COUNTER_CORR_GRP4__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_CORR_GRP5__ResetEn_MASK', + 'PARITY_COUNTER_CORR_GRP5__ResetEn__SHIFT', + 'PARITY_COUNTER_CORR_GRP5__ThresholdCounter_MASK', + 'PARITY_COUNTER_CORR_GRP5__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_CORR_GRP6__ResetEn_MASK', + 'PARITY_COUNTER_CORR_GRP6__ResetEn__SHIFT', + 'PARITY_COUNTER_CORR_GRP6__ThresholdCounter_MASK', + 'PARITY_COUNTER_CORR_GRP6__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_CORR_GRP7__ResetEn_MASK', + 'PARITY_COUNTER_CORR_GRP7__ResetEn__SHIFT', + 'PARITY_COUNTER_CORR_GRP7__ThresholdCounter_MASK', + 'PARITY_COUNTER_CORR_GRP7__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_UCP_GRP0__ResetEn_MASK', + 'PARITY_COUNTER_UCP_GRP0__ResetEn__SHIFT', + 'PARITY_COUNTER_UCP_GRP0__ThresholdCounter_MASK', + 'PARITY_COUNTER_UCP_GRP0__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_UCP_GRP10__ResetEn_MASK', + 'PARITY_COUNTER_UCP_GRP10__ResetEn__SHIFT', + 'PARITY_COUNTER_UCP_GRP10__ThresholdCounter_MASK', + 'PARITY_COUNTER_UCP_GRP10__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_UCP_GRP11__ResetEn_MASK', + 'PARITY_COUNTER_UCP_GRP11__ResetEn__SHIFT', + 'PARITY_COUNTER_UCP_GRP11__ThresholdCounter_MASK', + 'PARITY_COUNTER_UCP_GRP11__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_UCP_GRP12__ResetEn_MASK', + 'PARITY_COUNTER_UCP_GRP12__ResetEn__SHIFT', + 'PARITY_COUNTER_UCP_GRP12__ThresholdCounter_MASK', + 'PARITY_COUNTER_UCP_GRP12__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_UCP_GRP1__ResetEn_MASK', + 'PARITY_COUNTER_UCP_GRP1__ResetEn__SHIFT', + 'PARITY_COUNTER_UCP_GRP1__ThresholdCounter_MASK', + 'PARITY_COUNTER_UCP_GRP1__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_UCP_GRP2__ResetEn_MASK', + 'PARITY_COUNTER_UCP_GRP2__ResetEn__SHIFT', + 'PARITY_COUNTER_UCP_GRP2__ThresholdCounter_MASK', + 'PARITY_COUNTER_UCP_GRP2__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_UCP_GRP3__ResetEn_MASK', + 'PARITY_COUNTER_UCP_GRP3__ResetEn__SHIFT', + 'PARITY_COUNTER_UCP_GRP3__ThresholdCounter_MASK', + 'PARITY_COUNTER_UCP_GRP3__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_UCP_GRP4__ResetEn_MASK', + 'PARITY_COUNTER_UCP_GRP4__ResetEn__SHIFT', + 'PARITY_COUNTER_UCP_GRP4__ThresholdCounter_MASK', + 'PARITY_COUNTER_UCP_GRP4__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_UCP_GRP5__ResetEn_MASK', + 'PARITY_COUNTER_UCP_GRP5__ResetEn__SHIFT', + 'PARITY_COUNTER_UCP_GRP5__ThresholdCounter_MASK', + 'PARITY_COUNTER_UCP_GRP5__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_UCP_GRP6__ResetEn_MASK', + 'PARITY_COUNTER_UCP_GRP6__ResetEn__SHIFT', + 'PARITY_COUNTER_UCP_GRP6__ThresholdCounter_MASK', + 'PARITY_COUNTER_UCP_GRP6__ThresholdCounter__SHIFT', + 'PARITY_COUNTER_UCP_GRP7__ResetEn_MASK', + 'PARITY_COUNTER_UCP_GRP7__ResetEn__SHIFT', + 'PARITY_COUNTER_UCP_GRP7__ThresholdCounter_MASK', + 'PARITY_COUNTER_UCP_GRP7__ThresholdCounter__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id9__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id0_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id0__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id10_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id10__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id11_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id11__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id12_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id12__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id13_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id13__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id14_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id14__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id15_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id15__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id16_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id16__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id17_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id17__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id18_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id18__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id19_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id19__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id1_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id1__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id20_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id20__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id21_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id21__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id22_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id22__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id23_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id23__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id24_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id24__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id25_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id25__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id26_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id26__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id27_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id27__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id28_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id28__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id29_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id29__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id2_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id2__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id30_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id30__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id31_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id31__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id3_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id3__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id4_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id4__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id5_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id5__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id6_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id6__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id7_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id7__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id8_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id8__SHIFT', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id9_MASK', + 'PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id9__SHIFT', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0_MASK', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0__SHIFT', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp10_MASK', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp10__SHIFT', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp11_MASK', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp11__SHIFT', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp12_MASK', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp12__SHIFT', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp13_MASK', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp13__SHIFT', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp14_MASK', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp14__SHIFT', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp15_MASK', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp15__SHIFT', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1_MASK', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1__SHIFT', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2_MASK', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2__SHIFT', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3_MASK', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3__SHIFT', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4_MASK', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4__SHIFT', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp5_MASK', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp5__SHIFT', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp6_MASK', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp6__SHIFT', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp7_MASK', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp7__SHIFT', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp8_MASK', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp8__SHIFT', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp9_MASK', + 'PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp9__SHIFT', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0_MASK', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0__SHIFT', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp10_MASK', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp10__SHIFT', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp11_MASK', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp11__SHIFT', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp12_MASK', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp12__SHIFT', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1_MASK', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1__SHIFT', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2_MASK', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2__SHIFT', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3_MASK', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3__SHIFT', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4_MASK', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4__SHIFT', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp5_MASK', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp5__SHIFT', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp6_MASK', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp6__SHIFT', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp7_MASK', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp7__SHIFT', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp8_MASK', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp8__SHIFT', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp9_MASK', + 'PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp9__SHIFT', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0_MASK', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0__SHIFT', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp10_MASK', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp10__SHIFT', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp11_MASK', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp11__SHIFT', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp12_MASK', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp12__SHIFT', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp13_MASK', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp13__SHIFT', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp14_MASK', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp14__SHIFT', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp15_MASK', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp15__SHIFT', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1_MASK', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1__SHIFT', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2_MASK', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2__SHIFT', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3_MASK', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3__SHIFT', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4_MASK', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4__SHIFT', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp5_MASK', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp5__SHIFT', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp6_MASK', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp6__SHIFT', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp7_MASK', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp7__SHIFT', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp8_MASK', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp8__SHIFT', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp9_MASK', + 'PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp9__SHIFT', + 'PCIE0PortAExtCorr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortAExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortAExtCorr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortAExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortAExtCorr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortAExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortAExtCorr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortAExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortAExtFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortAExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortAExtFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortAExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortAExtFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortAExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortAExtFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortAExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortAExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortAExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortAExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortAExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortAIntCorr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortAIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortAIntCorr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortAIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortAIntCorr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortAIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortAIntCorr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortAIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortAIntFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortAIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortAIntFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortAIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortAIntFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortAIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortAIntFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortAIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortAIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortAIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortAIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortAIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortAParityErr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortAParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortAParityErr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortAParityErr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortAParityErr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortAParityErr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortAParityErr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortAParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortASerr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortASerr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortASerr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortASerr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortASerr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortASerr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortASerr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortASerr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortBExtCorr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortBExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortBExtCorr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortBExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortBExtCorr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortBExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortBExtCorr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortBExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortBExtFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortBExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortBExtFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortBExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortBExtFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortBExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortBExtFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortBExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortBExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortBExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortBExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortBExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortBIntCorr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortBIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortBIntCorr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortBIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortBIntCorr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortBIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortBIntCorr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortBIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortBIntFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortBIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortBIntFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortBIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortBIntFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortBIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortBIntFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortBIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortBIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortBIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortBIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortBIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortBParityErr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortBParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortBParityErr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortBParityErr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortBParityErr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortBParityErr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortBParityErr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortBParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortBSerr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortBSerr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortBSerr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortBSerr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortBSerr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortBSerr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortBSerr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortBSerr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortCExtCorr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortCExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortCExtCorr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortCExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortCExtCorr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortCExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortCExtCorr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortCExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortCExtFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortCExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortCExtFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortCExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortCExtFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortCExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortCExtFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortCExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortCExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortCExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortCExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortCExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortCIntCorr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortCIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortCIntCorr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortCIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortCIntCorr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortCIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortCIntCorr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortCIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortCIntFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortCIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortCIntFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortCIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortCIntFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortCIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortCIntFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortCIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortCIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortCIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortCIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortCIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortCParityErr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortCParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortCParityErr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortCParityErr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortCParityErr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortCParityErr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortCParityErr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortCParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortCSerr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortCSerr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortCSerr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortCSerr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortCSerr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortCSerr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortCSerr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortCSerr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortDExtCorr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortDExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortDExtCorr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortDExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortDExtCorr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortDExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortDExtCorr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortDExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortDExtFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortDExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortDExtFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortDExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortDExtFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortDExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortDExtFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortDExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortDExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortDExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortDExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortDExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortDExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortDExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortDExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortDExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortDIntCorr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortDIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortDIntCorr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortDIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortDIntCorr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortDIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortDIntCorr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortDIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortDIntFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortDIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortDIntFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortDIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortDIntFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortDIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortDIntFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortDIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortDIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortDIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortDIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortDIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortDIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortDIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortDIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortDIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortDParityErr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortDParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortDParityErr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortDParityErr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortDParityErr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortDParityErr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortDParityErr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortDParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortDSerr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortDSerr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortDSerr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortDSerr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortDSerr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortDSerr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortDSerr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortDSerr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortEExtCorr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortEExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortEExtCorr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortEExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortEExtCorr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortEExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortEExtCorr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortEExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortEExtFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortEExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortEExtFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortEExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortEExtFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortEExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortEExtFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortEExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortEExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortEExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortEExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortEExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortEExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortEExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortEExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortEExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortEIntCorr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortEIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortEIntCorr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortEIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortEIntCorr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortEIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortEIntCorr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortEIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortEIntFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortEIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortEIntFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortEIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortEIntFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortEIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortEIntFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortEIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortEIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortEIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortEIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortEIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortEIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortEIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortEIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortEIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortEParityErr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortEParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortEParityErr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortEParityErr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortEParityErr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortEParityErr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortEParityErr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortEParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortESerr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortESerr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortESerr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortESerr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortESerr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortESerr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortESerr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortESerr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortFExtCorr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortFExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortFExtCorr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortFExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortFExtCorr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortFExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortFExtCorr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortFExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortFExtFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortFExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortFExtFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortFExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortFExtFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortFExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortFExtFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortFExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortFExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortFExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortFExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortFExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortFExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortFExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortFExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortFExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortFIntCorr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortFIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortFIntCorr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortFIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortFIntCorr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortFIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortFIntCorr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortFIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortFIntFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortFIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortFIntFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortFIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortFIntFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortFIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortFIntFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortFIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortFIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortFIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortFIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortFIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortFIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortFIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortFIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortFIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortFParityErr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortFParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortFParityErr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortFParityErr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortFParityErr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortFParityErr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortFParityErr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortFParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortFSerr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortFSerr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortFSerr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortFSerr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortFSerr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortFSerr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortFSerr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortFSerr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortGExtCorr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortGExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortGExtCorr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortGExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortGExtCorr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortGExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortGExtCorr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortGExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortGExtFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortGExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortGExtFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortGExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortGExtFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortGExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortGExtFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortGExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortGExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortGExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortGExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortGExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortGExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortGExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortGExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortGExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortGIntCorr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortGIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortGIntCorr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortGIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortGIntCorr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortGIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortGIntCorr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortGIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortGIntFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortGIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortGIntFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortGIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortGIntFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortGIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortGIntFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortGIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortGIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortGIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortGIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortGIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortGIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortGIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortGIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortGIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortGParityErr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortGParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortGParityErr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortGParityErr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortGParityErr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortGParityErr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortGParityErr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortGParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIE0PortGSerr_ACTION_CONTROL__APML_ERR_En_MASK', + 'PCIE0PortGSerr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'PCIE0PortGSerr_ACTION_CONTROL__IntrGenSel_MASK', + 'PCIE0PortGSerr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'PCIE0PortGSerr_ACTION_CONTROL__LinkDis_En_MASK', + 'PCIE0PortGSerr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'PCIE0PortGSerr_ACTION_CONTROL__SyncFlood_En_MASK', + 'PCIE0PortGSerr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'PCIEMSIX_PBA_0__MSIX_PENDING_BITS_MASK', + 'PCIEMSIX_PBA_0__MSIX_PENDING_BITS__SHIFT', + 'PCIEMSIX_PBA_1__MSIX_PENDING_BITS_MASK', + 'PCIEMSIX_PBA_1__MSIX_PENDING_BITS__SHIFT', + 'PCIEMSIX_PBA_2__MSIX_PENDING_BITS_MASK', + 'PCIEMSIX_PBA_2__MSIX_PENDING_BITS__SHIFT', + 'PCIEMSIX_PBA_3__MSIX_PENDING_BITS_MASK', + 'PCIEMSIX_PBA_3__MSIX_PENDING_BITS__SHIFT', + 'PCIEMSIX_PBA_4__MSIX_PENDING_BITS_MASK', + 'PCIEMSIX_PBA_4__MSIX_PENDING_BITS__SHIFT', + 'PCIEMSIX_PBA_5__MSIX_PENDING_BITS_MASK', + 'PCIEMSIX_PBA_5__MSIX_PENDING_BITS__SHIFT', + 'PCIEMSIX_PBA_6__MSIX_PENDING_BITS_MASK', + 'PCIEMSIX_PBA_6__MSIX_PENDING_BITS__SHIFT', + 'PCIEMSIX_PBA_7__MSIX_PENDING_BITS_MASK', + 'PCIEMSIX_PBA_7__MSIX_PENDING_BITS__SHIFT', + 'PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT100_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT100_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT100_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT100_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT101_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT101_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT101_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT101_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT102_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT102_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT102_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT102_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT103_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT103_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT103_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT103_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT104_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT104_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT104_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT104_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT105_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT105_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT105_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT105_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT106_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT106_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT106_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT106_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT107_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT107_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT107_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT107_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT108_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT108_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT108_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT108_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT109_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT109_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT109_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT109_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT110_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT110_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT110_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT110_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT111_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT111_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT111_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT111_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT112_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT112_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT112_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT112_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT113_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT113_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT113_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT113_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT114_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT114_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT114_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT114_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT115_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT115_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT115_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT115_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT116_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT116_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT116_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT116_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT117_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT117_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT117_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT117_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT118_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT118_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT118_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT118_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT119_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT119_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT119_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT119_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT120_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT120_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT120_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT120_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT121_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT121_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT121_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT121_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT122_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT122_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT122_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT122_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT123_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT123_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT123_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT123_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT124_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT124_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT124_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT124_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT125_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT125_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT125_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT125_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT126_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT126_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT126_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT126_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT127_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT127_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT127_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT127_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT128_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT128_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT128_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT128_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT129_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT129_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT129_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT129_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT130_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT130_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT130_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT130_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT131_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT131_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT131_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT131_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT132_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT132_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT132_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT132_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT133_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT133_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT133_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT133_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT134_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT134_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT134_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT134_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT135_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT135_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT135_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT135_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT136_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT136_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT136_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT136_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT137_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT137_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT137_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT137_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT138_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT138_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT138_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT138_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT139_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT139_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT139_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT139_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT140_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT140_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT140_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT140_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT141_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT141_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT141_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT141_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT142_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT142_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT142_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT142_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT143_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT143_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT143_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT143_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT144_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT144_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT144_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT144_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT145_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT145_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT145_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT145_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT146_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT146_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT146_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT146_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT147_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT147_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT147_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT147_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT148_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT148_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT148_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT148_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT149_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT149_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT149_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT149_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT150_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT150_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT150_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT150_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT151_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT151_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT151_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT151_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT152_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT152_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT152_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT152_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT153_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT153_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT153_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT153_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT154_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT154_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT154_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT154_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT155_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT155_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT155_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT155_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT156_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT156_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT156_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT156_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT157_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT157_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT157_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT157_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT158_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT158_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT158_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT158_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT159_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT159_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT159_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT159_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT160_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT160_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT160_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT160_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT161_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT161_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT161_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT161_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT162_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT162_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT162_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT162_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT163_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT163_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT163_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT163_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT164_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT164_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT164_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT164_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT165_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT165_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT165_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT165_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT166_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT166_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT166_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT166_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT167_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT167_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT167_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT167_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT168_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT168_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT168_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT168_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT169_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT169_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT169_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT169_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT170_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT170_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT170_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT170_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT171_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT171_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT171_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT171_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT172_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT172_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT172_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT172_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT173_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT173_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT173_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT173_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT174_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT174_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT174_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT174_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT175_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT175_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT175_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT175_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT176_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT176_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT176_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT176_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT177_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT177_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT177_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT177_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT178_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT178_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT178_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT178_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT179_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT179_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT179_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT179_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT180_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT180_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT180_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT180_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT181_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT181_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT181_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT181_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT182_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT182_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT182_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT182_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT183_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT183_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT183_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT183_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT184_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT184_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT184_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT184_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT185_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT185_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT185_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT185_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT186_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT186_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT186_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT186_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT187_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT187_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT187_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT187_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT188_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT188_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT188_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT188_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT189_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT189_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT189_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT189_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT190_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT190_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT190_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT190_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT191_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT191_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT191_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT191_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT192_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT192_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT192_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT192_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT193_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT193_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT193_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT193_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT194_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT194_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT194_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT194_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT195_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT195_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT195_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT195_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT196_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT196_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT196_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT196_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT197_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT197_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT197_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT197_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT198_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT198_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT198_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT198_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT199_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT199_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT199_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT199_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT200_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT200_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT200_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT200_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT201_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT201_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT201_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT201_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT202_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT202_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT202_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT202_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT203_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT203_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT203_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT203_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT204_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT204_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT204_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT204_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT205_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT205_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT205_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT205_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT206_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT206_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT206_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT206_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT207_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT207_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT207_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT207_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT208_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT208_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT208_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT208_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT209_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT209_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT209_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT209_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT210_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT210_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT210_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT210_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT211_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT211_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT211_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT211_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT212_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT212_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT212_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT212_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT213_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT213_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT213_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT213_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT214_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT214_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT214_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT214_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT215_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT215_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT215_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT215_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT216_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT216_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT216_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT216_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT217_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT217_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT217_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT217_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT218_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT218_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT218_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT218_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT219_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT219_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT219_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT219_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT220_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT220_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT220_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT220_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT221_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT221_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT221_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT221_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT222_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT222_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT222_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT222_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT223_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT223_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT223_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT223_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT224_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT224_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT224_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT224_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT225_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT225_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT225_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT225_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT226_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT226_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT226_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT226_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT227_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT227_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT227_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT227_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT228_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT228_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT228_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT228_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT229_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT229_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT229_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT229_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT230_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT230_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT230_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT230_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT231_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT231_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT231_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT231_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT232_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT232_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT232_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT232_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT233_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT233_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT233_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT233_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT234_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT234_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT234_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT234_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT235_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT235_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT235_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT235_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT236_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT236_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT236_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT236_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT237_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT237_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT237_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT237_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT238_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT238_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT238_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT238_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT239_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT239_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT239_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT239_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT240_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT240_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT240_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT240_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT241_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT241_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT241_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT241_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT242_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT242_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT242_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT242_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT243_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT243_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT243_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT243_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT244_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT244_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT244_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT244_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT245_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT245_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT245_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT245_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT246_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT246_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT246_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT246_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT247_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT247_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT247_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT247_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT248_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT248_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT248_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT248_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT249_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT249_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT249_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT249_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT250_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT250_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT250_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT250_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT251_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT251_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT251_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT251_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT252_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT252_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT252_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT252_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT253_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT253_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT253_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT253_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT254_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT254_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT254_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT254_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT255_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT255_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT255_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT255_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT32_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT32_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT32_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT32_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT33_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT33_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT33_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT33_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT34_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT34_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT34_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT34_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT35_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT35_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT35_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT35_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT36_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT36_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT36_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT36_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT37_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT37_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT37_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT37_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT38_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT38_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT38_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT38_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT39_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT39_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT39_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT39_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT40_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT40_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT40_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT40_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT41_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT41_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT41_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT41_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT42_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT42_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT42_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT42_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT43_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT43_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT43_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT43_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT44_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT44_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT44_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT44_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT45_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT45_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT45_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT45_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT46_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT46_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT46_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT46_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT47_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT47_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT47_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT47_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT48_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT48_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT48_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT48_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT49_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT49_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT49_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT49_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT50_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT50_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT50_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT50_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT51_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT51_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT51_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT51_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT52_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT52_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT52_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT52_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT53_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT53_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT53_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT53_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT54_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT54_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT54_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT54_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT55_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT55_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT55_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT55_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT56_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT56_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT56_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT56_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT57_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT57_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT57_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT57_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT58_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT58_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT58_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT58_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT59_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT59_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT59_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT59_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT60_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT60_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT60_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT60_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT61_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT61_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT61_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT61_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT62_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT62_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT62_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT62_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT63_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT63_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT63_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT63_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT64_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT64_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT64_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT64_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT65_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT65_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT65_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT65_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT66_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT66_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT66_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT66_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT67_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT67_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT67_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT67_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT68_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT68_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT68_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT68_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT69_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT69_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT69_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT69_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT70_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT70_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT70_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT70_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT71_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT71_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT71_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT71_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT72_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT72_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT72_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT72_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT73_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT73_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT73_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT73_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT74_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT74_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT74_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT74_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT75_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT75_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT75_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT75_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT76_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT76_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT76_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT76_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT77_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT77_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT77_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT77_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT78_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT78_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT78_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT78_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT79_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT79_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT79_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT79_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT80_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT80_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT80_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT80_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT81_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT81_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT81_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT81_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT82_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT82_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT82_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT82_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT83_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT83_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT83_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT83_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT84_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT84_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT84_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT84_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT85_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT85_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT85_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT85_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT86_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT86_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT86_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT86_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT87_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT87_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT87_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT87_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT88_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT88_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT88_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT88_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT89_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT89_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT89_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT89_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT90_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT90_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT90_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT90_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT91_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT91_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT91_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT91_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT92_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT92_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT92_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT92_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT93_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT93_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT93_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT93_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT94_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT94_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT94_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT94_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT95_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT95_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT95_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT95_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT96_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT96_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT96_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT96_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT97_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT97_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT97_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT97_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT98_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT98_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT98_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT98_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT99_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT99_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT99_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT99_MSG_DATA__MSG_DATA__SHIFT', + 'PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK', + 'PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK', + 'PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK', + 'PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT', + 'PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK', + 'PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT', + 'PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK', + 'PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT', + 'PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK', + 'PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT', + 'PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK', + 'PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT', + 'PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK', + 'PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT', + 'PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK', + 'PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK', + 'PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK', + 'PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT', + 'PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK', + 'PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT', + 'PCIE_PAGE_REQ_STATUS__STOPPED_MASK', + 'PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT', + 'PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK', + 'PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT', + 'PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK', + 'PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT', + 'PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK', + 'PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT', + 'PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK', + 'PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT', + 'PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK', + 'PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT', + 'PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK', + 'PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT', + 'PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK', + 'PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT', + 'PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK', + 'PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT', + 'PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK', + 'PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT', + 'PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK', + 'PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT', + 'PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK', + 'PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT', + 'PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK', + 'PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT', + 'PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK', + 'PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT', + 'PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK', + 'PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT', + 'PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK', + 'PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT', + 'PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK', + 'PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT', + 'PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK', + 'PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT', + 'PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK', + 'PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT', + 'PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK', + 'PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT', + 'PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK', + 'PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT', + 'PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK', + 'PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT', + 'PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK', + 'PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT', + 'PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK', + 'PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT', + 'PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK', + 'PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT', + 'PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK', + 'PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT', + 'PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK', + 'PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT', + 'PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK', + 'PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT', + 'PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK', + 'PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT', + 'PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK', + 'PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT', + 'PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK', + 'PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT', + 'PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK', + 'PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT', + 'PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK', + 'PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT', + 'PCIE_VDM_CNTL2__AMDVDM2SMUEn_MASK', + 'PCIE_VDM_CNTL2__AMDVDM2SMUEn__SHIFT', + 'PCIE_VDM_CNTL2__MCTPEndpointEn_MASK', + 'PCIE_VDM_CNTL2__MCTPEndpointEn__SHIFT', + 'PCIE_VDM_CNTL2__MCTPMasterID_MASK', + 'PCIE_VDM_CNTL2__MCTPMasterID__SHIFT', + 'PCIE_VDM_CNTL2__MCTPMasterSeg_MASK', + 'PCIE_VDM_CNTL2__MCTPMasterSeg__SHIFT', + 'PCIE_VDM_CNTL2__MCTPMultiSegEn_MASK', + 'PCIE_VDM_CNTL2__MCTPMultiSegEn__SHIFT', + 'PCIE_VDM_CNTL2__MCTPT2SMUEn_MASK', + 'PCIE_VDM_CNTL2__MCTPT2SMUEn__SHIFT', + 'PCIE_VDM_CNTL2__OtherVDM2SMUEn_MASK', + 'PCIE_VDM_CNTL2__OtherVDM2SMUEn__SHIFT', + 'PCIE_VDM_CNTL2__RouteAllToMCTPMaster_MASK', + 'PCIE_VDM_CNTL2__RouteAllToMCTPMaster__SHIFT', + 'PCIE_VDM_CNTL2__VdmP2pMode_MASK', + 'PCIE_VDM_CNTL2__VdmP2pMode__SHIFT', + 'PCIE_VDM_CNTL3__APMTPMasterID_MASK', + 'PCIE_VDM_CNTL3__APMTPMasterID__SHIFT', + 'PCIE_VDM_CNTL3__APMTPMasterValid_MASK', + 'PCIE_VDM_CNTL3__APMTPMasterValid__SHIFT', + 'PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE_MASK', + 'PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE__SHIFT', + 'PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT_MASK', + 'PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT__SHIFT', + 'PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT_MASK', + 'PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT__SHIFT', + 'PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK', + 'PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK', + 'PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT', + 'PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK', + 'PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_CMD_COMPLETE_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_CMD_COMPLETE_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_NEED_FLR_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_NEED_FLR_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_CMD_COMPLETE_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_CMD_COMPLETE_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_NEED_FLR_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_NEED_FLR_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_CMD_COMPLETE_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_CMD_COMPLETE_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_NEED_FLR_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_NEED_FLR_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_CMD_COMPLETE_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_CMD_COMPLETE_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_NEED_FLR_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_NEED_FLR_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_CMD_COMPLETE_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_CMD_COMPLETE_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_NEED_FLR_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_NEED_FLR_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_CMD_COMPLETE_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_CMD_COMPLETE_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_NEED_FLR_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_NEED_FLR_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_CMD_COMPLETE_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_CMD_COMPLETE_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_NEED_FLR_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_NEED_FLR_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_CMD_COMPLETE_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_CMD_COMPLETE_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_NEED_FLR_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_NEED_FLR_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_CMD_COMPLETE_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_NEED_FLR_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_CMD_COMPLETE_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_NEED_FLR_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_CMD_COMPLETE_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_NEED_FLR_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_CMD_COMPLETE_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_NEED_FLR_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_CMD_COMPLETE_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_NEED_FLR_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_CMD_COMPLETE_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_NEED_FLR_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_CMD_COMPLETE_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_NEED_FLR_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_CMD_COMPLETE_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_NEED_FLR_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_CMD_COMPLETE_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_CMD_COMPLETE_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_NEED_FLR_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_NEED_FLR_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_CMD_COMPLETE_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_CMD_COMPLETE_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_NEED_FLR_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_NEED_FLR_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_CMD_COMPLETE_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_CMD_COMPLETE_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_NEED_FLR_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_NEED_FLR_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_CMD_COMPLETE_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_CMD_COMPLETE_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_NEED_FLR_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_NEED_FLR_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_CMD_COMPLETE_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_CMD_COMPLETE_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_NEED_FLR_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_NEED_FLR_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_CMD_COMPLETE_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_CMD_COMPLETE_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_NEED_FLR_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_NEED_FLR_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_CMD_COMPLETE_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_CMD_COMPLETE_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_NEED_FLR_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_NEED_FLR_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_CMD_COMPLETE_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_CMD_COMPLETE_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_NEED_FLR_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_NEED_FLR_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_CMD_COMPLETE_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_NEED_FLR_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_CMD_COMPLETE_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_NEED_FLR_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_CMD_COMPLETE_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_NEED_FLR_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_CMD_COMPLETE_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_NEED_FLR_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_CMD_COMPLETE_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_NEED_FLR_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_CMD_COMPLETE_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_NEED_FLR_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_CMD_COMPLETE_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_NEED_FLR_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_CMD_COMPLETE_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_NEED_FLR_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_CMD_COMPLETE_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_CMD_COMPLETE_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_NEED_FLR_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_NEED_FLR_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_CMD_COMPLETE_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_CMD_COMPLETE_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_NEED_FLR_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_NEED_FLR_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_CMD_COMPLETE_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_CMD_COMPLETE_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_NEED_FLR_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_NEED_FLR_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_CMD_COMPLETE_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_CMD_COMPLETE_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_NEED_FLR_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_NEED_FLR_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_SELF_RECOVERED_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_SELF_RECOVERED_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_VM_BUSY_TRANSITION_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_VM_BUSY_TRANSITION_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_CMD_COMPLETE_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_NEED_FLR_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_CMD_COMPLETE_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_NEED_FLR_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_CMD_COMPLETE_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_NEED_FLR_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_CMD_COMPLETE_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_CMD_COMPLETE_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_NEED_FLR_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_NEED_FLR_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_SELF_RECOVERED_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_VM_BUSY_TRANSITION_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0__DW0_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0__DW0__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1__DW1_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1__DW1__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2__DW2_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2__DW2__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3__DW3_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3__DW3__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4__DW4_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4__DW4__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5__DW5_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5__DW5__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6__DW6_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6__DW6__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7__DW7_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7__DW7__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8__DW8_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8__DW8__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0__DW0_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0__DW0__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1__DW1_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1__DW1__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2__DW2_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2__DW2__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3__DW3_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3__DW3__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4__DW4_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4__DW4__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5__DW5_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5__DW5__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6__DW6_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6__DW6__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7__DW7_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7__DW7__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8__DW8_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8__DW8__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0__DW0_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0__DW0__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1__DW1_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1__DW1__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2__DW2_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2__DW2__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3__DW3_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3__DW3__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4__DW4_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4__DW4__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5__DW5_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5__DW5__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6__DW6_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6__DW6__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7__DW7_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7__DW7__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8__DW8_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8__DW8__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0__DW0_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0__DW0__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1__DW1_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1__DW1__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2__DW2_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2__DW2__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3__DW3_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3__DW3__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4__DW4_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4__DW4__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5__DW5_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5__DW5__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6__DW6_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6__DW6__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7__DW7_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7__DW7__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8__DW8_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8__DW8__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0__DW0_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0__DW0__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1__DW1_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1__DW1__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2__DW2_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2__DW2__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3__DW3_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3__DW3__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4__DW4_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4__DW4__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5__DW5_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5__DW5__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6__DW6_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6__DW6__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7__DW7_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7__DW7__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8__DW8_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8__DW8__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0__DW0_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0__DW0__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1__DW1_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1__DW1__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2__DW2_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2__DW2__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3__DW3_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3__DW3__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4__DW4_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4__DW4__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5__DW5_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5__DW5__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6__DW6_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6__DW6__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7__DW7_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7__DW7__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8__DW8_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8__DW8__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0__DW0_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0__DW0__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1__DW1_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1__DW1__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2__DW2_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2__DW2__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3__DW3_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3__DW3__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4__DW4_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4__DW4__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5__DW5_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5__DW5__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6__DW6_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6__DW6__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7__DW7_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7__DW7__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8__DW8_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8__DW8__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0__DW0_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0__DW0__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1__DW1_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1__DW1__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2__DW2_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2__DW2__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3__DW3_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3__DW3__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4__DW4_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4__DW4__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5__DW5_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5__DW5__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6__DW6_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6__DW6__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7__DW7_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7__DW7__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8__DW8_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8__DW8__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN4SCH_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN4SCH_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN5SCH_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN5SCH_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN6SCH_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN6SCH_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN7SCH_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN7SCH_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN10SCH_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN10SCH_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN11SCH_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN11SCH_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN8SCH_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN8SCH_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN9SCH_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN9SCH_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX0SCH_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX0SCH_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX1SCH_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX1SCH_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX2SCH_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX2SCH_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX3SCH_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX3SCH_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX4SCH_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX4SCH_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX5SCH_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX5SCH_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX6SCH_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX6SCH_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX7SCH_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX7SCH_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN2SCH_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN2SCH_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN3SCH_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN3SCH_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0__DW0_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0__DW0__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1__DW1_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1__DW1__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2__DW2_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2__DW2__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3__DW3_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3__DW3__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4__DW4_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4__DW4__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5__DW5_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5__DW5__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6__DW6_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6__DW6__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7__DW7_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7__DW7__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8__DW8_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8__DW8__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0__DW0_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0__DW0__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1__DW1_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1__DW1__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2__DW2_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2__DW2__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3__DW3_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3__DW3__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4__DW4_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4__DW4__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5__DW5_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5__DW5__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6__DW6_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6__DW6__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7__DW7_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7__DW7__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8__DW8_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8__DW8__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0__DW0_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0__DW0__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1__DW1_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1__DW1__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2__DW2_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2__DW2__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3__DW3_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3__DW3__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4__DW4_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4__DW4__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5__DW5_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5__DW5__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6__DW6_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6__DW6__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7__DW7_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7__DW7__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8__DW8_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8__DW8__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0__DW0_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0__DW0__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1__DW1_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1__DW1__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2__DW2_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2__DW2__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3__DW3_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3__DW3__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4__DW4_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4__DW4__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5__DW5_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5__DW5__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6__DW6_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6__DW6__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7__DW7_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7__DW7__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8__DW8_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8__DW8__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0__DW0_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0__DW0__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1__DW1_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1__DW1__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2__DW2_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2__DW2__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3__DW3_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3__DW3__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4__DW4_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4__DW4__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5__DW5_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5__DW5__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6__DW6_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6__DW6__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7__DW7_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7__DW7__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8__DW8_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8__DW8__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0__DW0_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0__DW0__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1__DW1_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1__DW1__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2__DW2_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2__DW2__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3__DW3_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3__DW3__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4__DW4_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4__DW4__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5__DW5_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5__DW5__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6__DW6_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6__DW6__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7__DW7_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7__DW7__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8__DW8_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8__DW8__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0__DW0_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0__DW0__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1__DW1_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1__DW1__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2__DW2_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2__DW2__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3__DW3_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3__DW3__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4__DW4_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4__DW4__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5__DW5_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5__DW5__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6__DW6_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6__DW6__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7__DW7_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7__DW7__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8__DW8_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8__DW8__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0__DW0_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0__DW0__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1__DW1_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1__DW1__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2__DW2_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2__DW2__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3__DW3_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3__DW3__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4__DW4_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4__DW4__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5__DW5_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5__DW5__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6__DW6_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6__DW6__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7__DW7_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7__DW7__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8__DW8_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8__DW8__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0__DW0_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0__DW0__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1__DW1_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1__DW1__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2__DW2_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2__DW2__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3__DW3_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3__DW3__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4__DW4_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4__DW4__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5__DW5_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5__DW5__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6__DW6_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6__DW6__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7__DW7_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7__DW7__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8__DW8_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8__DW8__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0__DW0_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0__DW0__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1__DW1_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1__DW1__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2__DW2_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2__DW2__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3__DW3_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3__DW3__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4__DW4_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4__DW4__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5__DW5_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5__DW5__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6__DW6_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6__DW6__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7__DW7_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7__DW7__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8__DW8_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8__DW8__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0__DW0_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0__DW0__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1__DW1_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1__DW1__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2__DW2_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2__DW2__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3__DW3_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3__DW3__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4__DW4_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4__DW4__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5__DW5_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5__DW5__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6__DW6_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6__DW6__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7__DW7_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7__DW7__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8__DW8_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8__DW8__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK', + 'PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT', + 'POISON_ACTION_CONTROL__EgressPoisonHSAPMLErrEn_MASK', + 'POISON_ACTION_CONTROL__EgressPoisonHSAPMLErrEn__SHIFT', + 'POISON_ACTION_CONTROL__EgressPoisonHSIntrGenSel_MASK', + 'POISON_ACTION_CONTROL__EgressPoisonHSIntrGenSel__SHIFT', + 'POISON_ACTION_CONTROL__EgressPoisonHSLinkDisEn_MASK', + 'POISON_ACTION_CONTROL__EgressPoisonHSLinkDisEn__SHIFT', + 'POISON_ACTION_CONTROL__EgressPoisonHSSyncFloodEn_MASK', + 'POISON_ACTION_CONTROL__EgressPoisonHSSyncFloodEn__SHIFT', + 'POISON_ACTION_CONTROL__EgressPoisonLSAPMLErrEn_MASK', + 'POISON_ACTION_CONTROL__EgressPoisonLSAPMLErrEn__SHIFT', + 'POISON_ACTION_CONTROL__EgressPoisonLSIntrGenSel_MASK', + 'POISON_ACTION_CONTROL__EgressPoisonLSIntrGenSel__SHIFT', + 'POISON_ACTION_CONTROL__EgressPoisonLSLinkDisEn_MASK', + 'POISON_ACTION_CONTROL__EgressPoisonLSLinkDisEn__SHIFT', + 'POISON_ACTION_CONTROL__EgressPoisonLSSyncFloodEn_MASK', + 'POISON_ACTION_CONTROL__EgressPoisonLSSyncFloodEn__SHIFT', + 'POISON_ACTION_CONTROL__IntPoisonAPMLErrEn_MASK', + 'POISON_ACTION_CONTROL__IntPoisonAPMLErrEn__SHIFT', + 'POISON_ACTION_CONTROL__IntPoisonIntrGenSel_MASK', + 'POISON_ACTION_CONTROL__IntPoisonIntrGenSel__SHIFT', + 'POISON_ACTION_CONTROL__IntPoisonLinkDisEn_MASK', + 'POISON_ACTION_CONTROL__IntPoisonLinkDisEn__SHIFT', + 'POISON_ACTION_CONTROL__IntPoisonSyncFloodEn_MASK', + 'POISON_ACTION_CONTROL__IntPoisonSyncFloodEn__SHIFT', + 'PPR_CONTROL__PPR_IntCoallesce_En_MASK', + 'PPR_CONTROL__PPR_IntCoallesce_En__SHIFT', + 'PPR_CONTROL__PPR_IntReqDelay_MASK', + 'PPR_CONTROL__PPR_IntReqDelay__SHIFT', + 'PPR_CONTROL__PPR_IntTimeDelay_MASK', + 'PPR_CONTROL__PPR_IntTimeDelay__SHIFT', + 'PSP_BASE_ADDR_HI__PSP_BASE_ADDR_HI_MASK', + 'PSP_BASE_ADDR_HI__PSP_BASE_ADDR_HI__SHIFT', + 'PSP_BASE_ADDR_LO__PSP_BASE_ADDR_LO_MASK', + 'PSP_BASE_ADDR_LO__PSP_BASE_ADDR_LO__SHIFT', + 'PSP_BASE_ADDR_LO__PSP_MMIO_EN_MASK', + 'PSP_BASE_ADDR_LO__PSP_MMIO_EN__SHIFT', + 'PSP_BASE_ADDR_LO__PSP_MMIO_LOCK_MASK', + 'PSP_BASE_ADDR_LO__PSP_MMIO_LOCK__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_0_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_0__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_10_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_10__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_11_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_11__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_12_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_12__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_13_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_13__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_14_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_14__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_15_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_15__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_16_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_16__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_17_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_17__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_18_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_18__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_19_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_19__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_1_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_1__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_20_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_20__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_21_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_21__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_22_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_22__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_23_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_23__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_24_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_24__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_25_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_25__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_26_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_26__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_27_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_27__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_28_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_28__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_29_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_29__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_2_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_2__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_30_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_30__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_31_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_31__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_3_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_3__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_4_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_4__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_5_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_5__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_6_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_6__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_7_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_7__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_8_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_8__SHIFT', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_9_MASK', + 'P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_9__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_0_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_0__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_10_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_10__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_11_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_11__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_12_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_12__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_13_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_13__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_14_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_14__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_15_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_15__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_16_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_16__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_17_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_17__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_18_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_18__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_19_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_19__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_1_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_1__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_20_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_20__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_21_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_21__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_22_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_22__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_23_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_23__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_24_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_24__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_25_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_25__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_26_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_26__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_27_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_27__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_28_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_28__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_29_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_29__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_2_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_2__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_30_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_30__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_31_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_31__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_3_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_3__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_4_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_4__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_5_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_5__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_6_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_6__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_7_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_7__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_8_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_8__SHIFT', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_9_MASK', + 'P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_9__SHIFT', + 'ParityCorr_ACTION_CONTROL__APML_ERR_En_MASK', + 'ParityCorr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'ParityCorr_ACTION_CONTROL__IntrGenSel_MASK', + 'ParityCorr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'ParityCorr_ACTION_CONTROL__LinkDis_En_MASK', + 'ParityCorr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'ParityCorr_ACTION_CONTROL__SyncFlood_En_MASK', + 'ParityCorr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'ParityFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'ParityFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'ParityFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'ParityFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'ParityFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'ParityFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'ParityFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'ParityFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'ParityNonFatal_ACTION_CONTROL__APML_ERR_En_MASK', + 'ParityNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'ParityNonFatal_ACTION_CONTROL__IntrGenSel_MASK', + 'ParityNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT', + 'ParityNonFatal_ACTION_CONTROL__LinkDis_En_MASK', + 'ParityNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT', + 'ParityNonFatal_ACTION_CONTROL__SyncFlood_En_MASK', + 'ParityNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'ParitySerr_ACTION_CONTROL__APML_ERR_En_MASK', + 'ParitySerr_ACTION_CONTROL__APML_ERR_En__SHIFT', + 'ParitySerr_ACTION_CONTROL__IntrGenSel_MASK', + 'ParitySerr_ACTION_CONTROL__IntrGenSel__SHIFT', + 'ParitySerr_ACTION_CONTROL__LinkDis_En_MASK', + 'ParitySerr_ACTION_CONTROL__LinkDis_En__SHIFT', + 'ParitySerr_ACTION_CONTROL__SyncFlood_En_MASK', + 'ParitySerr_ACTION_CONTROL__SyncFlood_En__SHIFT', + 'RAS_GLOBAL_STATUS_HI__NBIF1PortAErr_MASK', + 'RAS_GLOBAL_STATUS_HI__NBIF1PortAErr__SHIFT', + 'RAS_GLOBAL_STATUS_HI__PCIE0PortAErr_MASK', + 'RAS_GLOBAL_STATUS_HI__PCIE0PortAErr__SHIFT', + 'RAS_GLOBAL_STATUS_HI__PCIE0PortBErr_MASK', + 'RAS_GLOBAL_STATUS_HI__PCIE0PortBErr__SHIFT', + 'RAS_GLOBAL_STATUS_HI__PCIE0PortCErr_MASK', + 'RAS_GLOBAL_STATUS_HI__PCIE0PortCErr__SHIFT', + 'RAS_GLOBAL_STATUS_HI__PCIE0PortDErr_MASK', + 'RAS_GLOBAL_STATUS_HI__PCIE0PortDErr__SHIFT', + 'RAS_GLOBAL_STATUS_HI__PCIE0PortEErr_MASK', + 'RAS_GLOBAL_STATUS_HI__PCIE0PortEErr__SHIFT', + 'RAS_GLOBAL_STATUS_HI__PCIE0PortFErr_MASK', + 'RAS_GLOBAL_STATUS_HI__PCIE0PortFErr__SHIFT', + 'RAS_GLOBAL_STATUS_HI__PCIE0PortGErr_MASK', + 'RAS_GLOBAL_STATUS_HI__PCIE0PortGErr__SHIFT', + 'RAS_GLOBAL_STATUS_HI__PCIE0PortHErr_MASK', + 'RAS_GLOBAL_STATUS_HI__PCIE0PortHErr__SHIFT', + 'RAS_GLOBAL_STATUS_HI__PCIE0PortIErr_MASK', + 'RAS_GLOBAL_STATUS_HI__PCIE0PortIErr__SHIFT', + 'RAS_GLOBAL_STATUS_HI__PCIE1PortAErr_MASK', + 'RAS_GLOBAL_STATUS_HI__PCIE1PortAErr__SHIFT', + 'RAS_GLOBAL_STATUS_HI__PCIE1PortBErr_MASK', + 'RAS_GLOBAL_STATUS_HI__PCIE1PortBErr__SHIFT', + 'RAS_GLOBAL_STATUS_HI__PCIE1PortCErr_MASK', + 'RAS_GLOBAL_STATUS_HI__PCIE1PortCErr__SHIFT', + 'RAS_GLOBAL_STATUS_HI__PCIE1PortDErr_MASK', + 'RAS_GLOBAL_STATUS_HI__PCIE1PortDErr__SHIFT', + 'RAS_GLOBAL_STATUS_LO__APML_NMI_MASK', + 'RAS_GLOBAL_STATUS_LO__APML_NMI__SHIFT', + 'RAS_GLOBAL_STATUS_LO__APML_SyncFld_MASK', + 'RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private_MASK', + 'RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private__SHIFT', + 'RAS_GLOBAL_STATUS_LO__APML_SyncFld__SHIFT', + 'RAS_GLOBAL_STATUS_LO__HPLGWA_NMI_MASK', + 'RAS_GLOBAL_STATUS_LO__HPLGWA_NMI__SHIFT', + 'RAS_GLOBAL_STATUS_LO__HPLGWA_SCI_MASK', + 'RAS_GLOBAL_STATUS_LO__HPLGWA_SCI__SHIFT', + 'RAS_GLOBAL_STATUS_LO__HPLGWA_SMI_MASK', + 'RAS_GLOBAL_STATUS_LO__HPLGWA_SMI__SHIFT', + 'RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI_MASK', + 'RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI__SHIFT', + 'RAS_GLOBAL_STATUS_LO__ParityErrCorr_MASK', + 'RAS_GLOBAL_STATUS_LO__ParityErrCorr__SHIFT', + 'RAS_GLOBAL_STATUS_LO__ParityErrFatal_MASK', + 'RAS_GLOBAL_STATUS_LO__ParityErrFatal__SHIFT', + 'RAS_GLOBAL_STATUS_LO__ParityErrNonFatal_MASK', + 'RAS_GLOBAL_STATUS_LO__ParityErrNonFatal__SHIFT', + 'RAS_GLOBAL_STATUS_LO__ParityErrSerr_MASK', + 'RAS_GLOBAL_STATUS_LO__ParityErrSerr__SHIFT', + 'RAS_GLOBAL_STATUS_LO__SW_NMI_MASK', + 'RAS_GLOBAL_STATUS_LO__SW_NMI__SHIFT', + 'RAS_GLOBAL_STATUS_LO__SW_SCI_MASK', + 'RAS_GLOBAL_STATUS_LO__SW_SCI__SHIFT', + 'RAS_GLOBAL_STATUS_LO__SW_SMI_MASK', + 'RAS_GLOBAL_STATUS_LO__SW_SMI__SHIFT', + 'RAS_SCRATCH_0__SCRATCH_0_MASK', + 'RAS_SCRATCH_0__SCRATCH_0__SHIFT', + 'RAS_SCRATCH_1__SCRATCH_1_MASK', + 'RAS_SCRATCH_1__SCRATCH_1__SHIFT', + 'RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK', + 'RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT', + 'RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK', + 'RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6__SHIFT', + 'RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7_MASK', + 'RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT', + 'RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK', + 'RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT', + 'RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK', + 'RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT', + 'RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK', + 'RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT', + 'RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK', + 'RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT', + 'RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK', + 'RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT', + 'RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK', + 'RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT', + 'RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK', + 'RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT', + 'RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK', + 'RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT', + 'RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK', + 'RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT', + 'RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK', + 'RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT', + 'RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK', + 'RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT', + 'RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE_MASK', + 'RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT', + 'RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK', + 'RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT', + 'RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK', + 'RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT', + 'RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK', + 'RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT', + 'RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK', + 'RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT', + 'RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK', + 'RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT', + 'RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK', + 'RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT', + 'RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK', + 'RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT', + 'RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK', + 'RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT', + 'RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK', + 'RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK', + 'RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT', + 'RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK', + 'RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT', + 'RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK', + 'RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT', + 'RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK', + 'RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK', + 'RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT', + 'RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION_MASK', + 'RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION__SHIFT', + 'RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION_MASK', + 'RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION__SHIFT', + 'RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK', + 'RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT', + 'RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID_MASK', + 'RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID__SHIFT', + 'RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK', + 'RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK', + 'RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT', + 'RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK', + 'RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT', + 'RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK', + 'RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT', + 'RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK', + 'RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT', + 'RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK', + 'RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT', + 'RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK', + 'RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT', + 'RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK', + 'RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT', + 'RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK', + 'RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT', + 'RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK', + 'RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT', + 'RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK', + 'RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT', + 'RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK', + 'RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT', + 'RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK', + 'RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT', + 'RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK', + 'RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT', + 'RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK', + 'RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT', + 'RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK', + 'RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT', + 'RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR_MASK', + 'RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT', + 'RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR_MASK', + 'RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT', + 'RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR_MASK', + 'RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT', + 'RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR_MASK', + 'RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT', + 'RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN_MASK', + 'RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT', + 'RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK', + 'RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT', + 'RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK', + 'RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT', + 'RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK', + 'RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT', + 'RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK', + 'RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT', + 'RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK', + 'RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT', + 'RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK', + 'RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT', + 'RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK', + 'RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT', + 'RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK', + 'RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT', + 'RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK', + 'RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT', + 'RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK', + 'RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6__SHIFT', + 'RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7_MASK', + 'RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT', + 'RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK', + 'RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT', + 'RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK', + 'RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT', + 'RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK', + 'RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT', + 'RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK', + 'RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT', + 'RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK', + 'RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT', + 'RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK', + 'RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT', + 'RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK', + 'RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT', + 'RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK', + 'RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT', + 'RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK', + 'RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT', + 'RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK', + 'RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT', + 'RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK', + 'RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT', + 'RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE_MASK', + 'RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT', + 'RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK', + 'RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT', + 'RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK', + 'RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT', + 'RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK', + 'RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT', + 'RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK', + 'RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT', + 'RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK', + 'RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT', + 'RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK', + 'RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT', + 'RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK', + 'RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT', + 'RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK', + 'RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT', + 'RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK', + 'RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK', + 'RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT', + 'RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK', + 'RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT', + 'RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK', + 'RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT', + 'RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK', + 'RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK', + 'RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT', + 'RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION_MASK', + 'RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION__SHIFT', + 'RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION_MASK', + 'RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION__SHIFT', + 'RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK', + 'RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT', + 'RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID_MASK', + 'RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID__SHIFT', + 'RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK', + 'RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK', + 'RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT', + 'RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK', + 'RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT', + 'RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK', + 'RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT', + 'RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK', + 'RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT', + 'RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK', + 'RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT', + 'RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK', + 'RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT', + 'RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK', + 'RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT', + 'RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK', + 'RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT', + 'RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK', + 'RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT', + 'RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK', + 'RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT', + 'RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK', + 'RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT', + 'RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK', + 'RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT', + 'RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK', + 'RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT', + 'RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK', + 'RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT', + 'RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK', + 'RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT', + 'RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR_MASK', + 'RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT', + 'RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR_MASK', + 'RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT', + 'RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR_MASK', + 'RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT', + 'RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR_MASK', + 'RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT', + 'RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN_MASK', + 'RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT', + 'RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK', + 'RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT', + 'RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK', + 'RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT', + 'RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK', + 'RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT', + 'RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK', + 'RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT', + 'RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK', + 'RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT', + 'RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK', + 'RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT', + 'RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK', + 'RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT', + 'RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK', + 'RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT', + 'RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK', + 'RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT', + 'RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK', + 'RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT', + 'RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK', + 'RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT', + 'RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK', + 'RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT', + 'RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK', + 'RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT', + 'RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK', + 'RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT', + 'RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK', + 'RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT', + 'RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK', + 'RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT', + 'RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK', + 'RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT', + 'RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK', + 'RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT', + 'RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK', + 'RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT', + 'RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK', + 'RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK', + 'RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT', + 'RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK', + 'RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK', + 'RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT', + 'RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK', + 'RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT', + 'RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK', + 'RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT', + 'RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK', + 'RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT', + 'RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK', + 'RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT', + 'RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK', + 'RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT', + 'RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK', + 'RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT', + 'RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK', + 'RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK', + 'RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT', + 'RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK', + 'RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT', + 'RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK', + 'RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT', + 'RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK', + 'RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT', + 'RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK', + 'RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK', + 'RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT', + 'RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK', + 'RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT', + 'RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK', + 'RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT', + 'RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK', + 'RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT', + 'RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK', + 'RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK', + 'RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK', + 'RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK', + 'RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK', + 'RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK', + 'RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK', + 'RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT', + 'RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK', + 'RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT', + 'RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK', + 'RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT', + 'RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK', + 'RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK', + 'RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK', + 'RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK', + 'RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK', + 'RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK', + 'RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK', + 'RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT', + 'RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK', + 'RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT', + 'RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK', + 'RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT', + 'RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK', + 'RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK', + 'RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK', + 'RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK', + 'RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK', + 'RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK', + 'RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK', + 'RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK', + 'RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT', + 'RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK', + 'RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK', + 'RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK', + 'RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK', + 'RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK', + 'RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT', + 'RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK', + 'RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK', + 'RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT', + 'RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK', + 'RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK', + 'RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT', + 'RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK', + 'RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK', + 'RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK', + 'RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT', + 'RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK', + 'RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK', + 'RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK', + 'RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT', + 'RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK', + 'RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK', + 'RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK', + 'RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP1__WRITE_DISABLE_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT', + 'RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK', + 'RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK', + 'RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK', + 'RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT', + 'REGS_ROM_OFFSET_CTRL__ROM_OFFSET_MASK', + 'REGS_ROM_OFFSET_CTRL__ROM_OFFSET__SHIFT', + 'S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK', + 'S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID_MASK', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID_MASK', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID_MASK', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID_MASK', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID_MASK', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID_MASK', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID_MASK', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID_MASK', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID_MASK', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID_MASK', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID_MASK', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID_MASK', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID_MASK', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID_MASK', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID_MASK', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE__SHIFT', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS_MASK', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS__SHIFT', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE_MASK', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE__SHIFT', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID_MASK', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID__SHIFT', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE_MASK', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE__SHIFT', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET_MASK', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET__SHIFT', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE_MASK', + 'S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE__SHIFT', + 'SB_COMMAND__BUS_MASTER_EN_MASK', + 'SB_COMMAND__BUS_MASTER_EN__SHIFT', + 'SB_COMMAND__IO_ACCESS_EN_MASK', + 'SB_COMMAND__IO_ACCESS_EN__SHIFT', + 'SB_COMMAND__MEM_ACCESS_EN_MASK', + 'SB_COMMAND__MEM_ACCESS_EN__SHIFT', + 'SB_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK', + 'SB_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT', + 'SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK', + 'SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT', + 'SB_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK', + 'SB_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT', + 'SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK', + 'SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT', + 'SB_IO_BASE_LIMIT__IO_BASE_MASK', + 'SB_IO_BASE_LIMIT__IO_BASE__SHIFT', + 'SB_IO_BASE_LIMIT__IO_LIMIT_MASK', + 'SB_IO_BASE_LIMIT__IO_LIMIT__SHIFT', + 'SB_IRQ_BRIDGE_CNTL__ISA_EN_MASK', + 'SB_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT', + 'SB_IRQ_BRIDGE_CNTL__VGA_DEC_MASK', + 'SB_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT', + 'SB_IRQ_BRIDGE_CNTL__VGA_EN_MASK', + 'SB_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT', + 'SB_LOCATION__SBlocated_Core_MASK', + 'SB_LOCATION__SBlocated_Core__SHIFT', + 'SB_LOCATION__SBlocated_Port_MASK', + 'SB_LOCATION__SBlocated_Port__SHIFT', + 'SB_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK', + 'SB_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT', + 'SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK', + 'SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT', + 'SB_PMI_STATUS_CNTL__POWER_STATE_MASK', + 'SB_PMI_STATUS_CNTL__POWER_STATE__SHIFT', + 'SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK', + 'SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT', + 'SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK', + 'SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT', + 'SB_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK', + 'SB_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT', + 'SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK', + 'SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT', + 'SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK', + 'SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT', + 'SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK', + 'SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT', + 'SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK', + 'SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT', + 'SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK', + 'SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT', + 'SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK', + 'SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT', + 'SCRATCH_4__SCRATCH_4_MASK', 'SCRATCH_4__SCRATCH_4__SHIFT', + 'SCRATCH_5__SCRATCH_5_MASK', 'SCRATCH_5__SCRATCH_5__SHIFT', + 'SELF_SOFT_RST_2__DSPT3_CFG_RST_MASK', + 'SELF_SOFT_RST_2__DSPT3_CFG_RST__SHIFT', + 'SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST_MASK', + 'SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST__SHIFT', + 'SELF_SOFT_RST_2__DSPT3_PRV_RST_MASK', + 'SELF_SOFT_RST_2__DSPT3_PRV_RST__SHIFT', + 'SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST_MASK', + 'SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST__SHIFT', + 'SELF_SOFT_RST_2__EP3_CFG_RST_MASK', + 'SELF_SOFT_RST_2__EP3_CFG_RST__SHIFT', + 'SELF_SOFT_RST_2__EP3_CFG_STICKY_RST_MASK', + 'SELF_SOFT_RST_2__EP3_CFG_STICKY_RST__SHIFT', + 'SELF_SOFT_RST_2__EP3_PRV_RST_MASK', + 'SELF_SOFT_RST_2__EP3_PRV_RST__SHIFT', + 'SELF_SOFT_RST_2__EP3_PRV_STICKY_RST_MASK', + 'SELF_SOFT_RST_2__EP3_PRV_STICKY_RST__SHIFT', + 'SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST_MASK', + 'SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST__SHIFT', + 'SELF_SOFT_RST_2__STRAP_RST_MASK', + 'SELF_SOFT_RST_2__STRAP_RST__SHIFT', + 'SELF_SOFT_RST__CORE_RST_MASK', 'SELF_SOFT_RST__CORE_RST__SHIFT', + 'SELF_SOFT_RST__CORE_STICKY_RST_MASK', + 'SELF_SOFT_RST__CORE_STICKY_RST__SHIFT', + 'SELF_SOFT_RST__DSPT0_CFG_RST_MASK', + 'SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT', + 'SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK', + 'SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT', + 'SELF_SOFT_RST__DSPT0_PRV_RST_MASK', + 'SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT', + 'SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK', + 'SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT', + 'SELF_SOFT_RST__EP0_CFG_RST_MASK', + 'SELF_SOFT_RST__EP0_CFG_RST__SHIFT', + 'SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK', + 'SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT', + 'SELF_SOFT_RST__EP0_PRV_RST_MASK', + 'SELF_SOFT_RST__EP0_PRV_RST__SHIFT', + 'SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK', + 'SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT', + 'SELF_SOFT_RST__GMID_SDP_PORT_RST_MASK', + 'SELF_SOFT_RST__GMID_SDP_PORT_RST__SHIFT', + 'SELF_SOFT_RST__GMIU_SDP_PORT_RST_MASK', + 'SELF_SOFT_RST__GMIU_SDP_PORT_RST__SHIFT', + 'SELF_SOFT_RST__GSID_SDP_PORT_RST_MASK', + 'SELF_SOFT_RST__GSID_SDP_PORT_RST__SHIFT', + 'SELF_SOFT_RST__HRPU_SDP_PORT_RST_MASK', + 'SELF_SOFT_RST__HRPU_SDP_PORT_RST__SHIFT', + 'SELF_SOFT_RST__RELOAD_STRAP_MASK', + 'SELF_SOFT_RST__RELOAD_STRAP__SHIFT', + 'SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST_MASK', + 'SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST__SHIFT', + 'SHUB_HARD_RST_CTRL__COR_RESET_EN_MASK', + 'SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT', + 'SHUB_HARD_RST_CTRL__NIC400_RESET_EN_MASK', + 'SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT', + 'SHUB_HARD_RST_CTRL__REG_RESET_EN_MASK', + 'SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT', + 'SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK', + 'SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT', + 'SHUB_HARD_RST_CTRL__SION_AON_RESET_EN_MASK', + 'SHUB_HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT', + 'SHUB_HARD_RST_CTRL__STY_RESET_EN_MASK', + 'SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT', + 'SHUB_LINK_RESET__LINK_P0_RESET_MASK', + 'SHUB_LINK_RESET__LINK_P0_RESET__SHIFT', + 'SHUB_LINK_RESET__LINK_P1_RESET_MASK', + 'SHUB_LINK_RESET__LINK_P1_RESET__SHIFT', + 'SHUB_LINK_RESET__LINK_P2_RESET_MASK', + 'SHUB_LINK_RESET__LINK_P2_RESET__SHIFT', + 'SHUB_LINK_RESET__LINK_P3_RESET_MASK', + 'SHUB_LINK_RESET__LINK_P3_RESET__SHIFT', + 'SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK', + 'SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT', + 'SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK', + 'SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT', + 'SHUB_SDP_PORT_RST__A2S_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__A2S_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__MPDMAPM_DMA_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__MPDMAPM_DMA_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__MPDMATF_DMA_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__MPDMATF_DMA_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__MPDMATF_HST_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__MPDMATF_HST_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST_MASK', + 'SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST__SHIFT', + 'SHUB_SDP_PORT_RST__SION_AON_RST_MASK', + 'SHUB_SDP_PORT_RST__SION_AON_RST__SHIFT', + 'SHUB_SOFT_RST_CTRL__COR_RESET_EN_MASK', + 'SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT', + 'SHUB_SOFT_RST_CTRL__NIC400_RESET_EN_MASK', + 'SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT', + 'SHUB_SOFT_RST_CTRL__REG_RESET_EN_MASK', + 'SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT', + 'SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK', + 'SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT', + 'SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN_MASK', + 'SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN__SHIFT', + 'SHUB_SOFT_RST_CTRL__STY_RESET_EN_MASK', + 'SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT', + 'SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK', + 'SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT', + 'SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK', + 'SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT', + 'SMN_MST_CNTL0__SMN_ARB_MODE_MASK', + 'SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT', + 'SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK', + 'SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT', + 'SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK', + 'SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT', + 'SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK', + 'SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT', + 'SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK', + 'SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT', + 'SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK', + 'SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT', + 'SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK', + 'SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT', + 'SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK', + 'SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT', + 'SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK', + 'SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK', + 'SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK', + 'SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK', + 'SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK', + 'SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK', + 'SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT', + 'SMU_BASE_ADDR_HI__SMU_BASE_ADDR_HI_MASK', + 'SMU_BASE_ADDR_HI__SMU_BASE_ADDR_HI__SHIFT', + 'SMU_BASE_ADDR_LO__SMU_BASE_ADDR_LO_MASK', + 'SMU_BASE_ADDR_LO__SMU_BASE_ADDR_LO__SHIFT', + 'SMU_BASE_ADDR_LO__SMU_MMIO_EN_MASK', + 'SMU_BASE_ADDR_LO__SMU_MMIO_EN__SHIFT', + 'SMU_BASE_ADDR_LO__SMU_MMIO_LOCK_MASK', + 'SMU_BASE_ADDR_LO__SMU_MMIO_LOCK__SHIFT', + 'SMU_BLOCK_CPU_STATUS__SMUBlockCPU_Status_MASK', + 'SMU_BLOCK_CPU_STATUS__SMUBlockCPU_Status__SHIFT', + 'SMU_BLOCK_CPU__SMUBlockCPU_Valid_MASK', + 'SMU_BLOCK_CPU__SMUBlockCPU_Valid__SHIFT', + 'STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn_MASK', + 'STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn_MASK', + 'STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn_MASK', + 'STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn_MASK', + 'STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn_MASK', + 'STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT0_0__StallVC5ReqEn_MASK', + 'STALL_CONTROL_XBARPORT0_0__StallVC5ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn_MASK', + 'STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT0_1__StallVC0RspEn_MASK', + 'STALL_CONTROL_XBARPORT0_1__StallVC0RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT0_1__StallVC1RspEn_MASK', + 'STALL_CONTROL_XBARPORT0_1__StallVC1RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT0_1__StallVC2RspEn_MASK', + 'STALL_CONTROL_XBARPORT0_1__StallVC2RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT0_1__StallVC3RspEn_MASK', + 'STALL_CONTROL_XBARPORT0_1__StallVC3RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT0_1__StallVC4RspEn_MASK', + 'STALL_CONTROL_XBARPORT0_1__StallVC4RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT0_1__StallVC5RspEn_MASK', + 'STALL_CONTROL_XBARPORT0_1__StallVC5RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT0_1__StallVC7RspEn_MASK', + 'STALL_CONTROL_XBARPORT0_1__StallVC7RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn_MASK', + 'STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn_MASK', + 'STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn_MASK', + 'STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn_MASK', + 'STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn_MASK', + 'STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT1_0__StallVC5ReqEn_MASK', + 'STALL_CONTROL_XBARPORT1_0__StallVC5ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn_MASK', + 'STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT1_1__StallVC0RspEn_MASK', + 'STALL_CONTROL_XBARPORT1_1__StallVC0RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT1_1__StallVC1RspEn_MASK', + 'STALL_CONTROL_XBARPORT1_1__StallVC1RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT1_1__StallVC2RspEn_MASK', + 'STALL_CONTROL_XBARPORT1_1__StallVC2RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT1_1__StallVC3RspEn_MASK', + 'STALL_CONTROL_XBARPORT1_1__StallVC3RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT1_1__StallVC4RspEn_MASK', + 'STALL_CONTROL_XBARPORT1_1__StallVC4RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT1_1__StallVC5RspEn_MASK', + 'STALL_CONTROL_XBARPORT1_1__StallVC5RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT1_1__StallVC7RspEn_MASK', + 'STALL_CONTROL_XBARPORT1_1__StallVC7RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn_MASK', + 'STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn_MASK', + 'STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn_MASK', + 'STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn_MASK', + 'STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn_MASK', + 'STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT2_0__StallVC5ReqEn_MASK', + 'STALL_CONTROL_XBARPORT2_0__StallVC5ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn_MASK', + 'STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT2_1__StallVC0RspEn_MASK', + 'STALL_CONTROL_XBARPORT2_1__StallVC0RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT2_1__StallVC1RspEn_MASK', + 'STALL_CONTROL_XBARPORT2_1__StallVC1RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT2_1__StallVC2RspEn_MASK', + 'STALL_CONTROL_XBARPORT2_1__StallVC2RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT2_1__StallVC3RspEn_MASK', + 'STALL_CONTROL_XBARPORT2_1__StallVC3RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT2_1__StallVC4RspEn_MASK', + 'STALL_CONTROL_XBARPORT2_1__StallVC4RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT2_1__StallVC5RspEn_MASK', + 'STALL_CONTROL_XBARPORT2_1__StallVC5RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT2_1__StallVC7RspEn_MASK', + 'STALL_CONTROL_XBARPORT2_1__StallVC7RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn_MASK', + 'STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn_MASK', + 'STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn_MASK', + 'STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn_MASK', + 'STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn_MASK', + 'STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT3_0__StallVC5ReqEn_MASK', + 'STALL_CONTROL_XBARPORT3_0__StallVC5ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn_MASK', + 'STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT3_1__StallVC0RspEn_MASK', + 'STALL_CONTROL_XBARPORT3_1__StallVC0RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT3_1__StallVC1RspEn_MASK', + 'STALL_CONTROL_XBARPORT3_1__StallVC1RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT3_1__StallVC2RspEn_MASK', + 'STALL_CONTROL_XBARPORT3_1__StallVC2RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT3_1__StallVC3RspEn_MASK', + 'STALL_CONTROL_XBARPORT3_1__StallVC3RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT3_1__StallVC4RspEn_MASK', + 'STALL_CONTROL_XBARPORT3_1__StallVC4RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT3_1__StallVC5RspEn_MASK', + 'STALL_CONTROL_XBARPORT3_1__StallVC5RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT3_1__StallVC7RspEn_MASK', + 'STALL_CONTROL_XBARPORT3_1__StallVC7RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn_MASK', + 'STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn_MASK', + 'STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn_MASK', + 'STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn_MASK', + 'STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn_MASK', + 'STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT4_0__StallVC5ReqEn_MASK', + 'STALL_CONTROL_XBARPORT4_0__StallVC5ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn_MASK', + 'STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT4_1__StallVC0RspEn_MASK', + 'STALL_CONTROL_XBARPORT4_1__StallVC0RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT4_1__StallVC1RspEn_MASK', + 'STALL_CONTROL_XBARPORT4_1__StallVC1RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT4_1__StallVC2RspEn_MASK', + 'STALL_CONTROL_XBARPORT4_1__StallVC2RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT4_1__StallVC3RspEn_MASK', + 'STALL_CONTROL_XBARPORT4_1__StallVC3RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT4_1__StallVC4RspEn_MASK', + 'STALL_CONTROL_XBARPORT4_1__StallVC4RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT4_1__StallVC5RspEn_MASK', + 'STALL_CONTROL_XBARPORT4_1__StallVC5RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT4_1__StallVC7RspEn_MASK', + 'STALL_CONTROL_XBARPORT4_1__StallVC7RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT5_0__StallVC0ReqEn_MASK', + 'STALL_CONTROL_XBARPORT5_0__StallVC0ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT5_0__StallVC1ReqEn_MASK', + 'STALL_CONTROL_XBARPORT5_0__StallVC1ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT5_0__StallVC2ReqEn_MASK', + 'STALL_CONTROL_XBARPORT5_0__StallVC2ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT5_0__StallVC3ReqEn_MASK', + 'STALL_CONTROL_XBARPORT5_0__StallVC3ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT5_0__StallVC4ReqEn_MASK', + 'STALL_CONTROL_XBARPORT5_0__StallVC4ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT5_0__StallVC5ReqEn_MASK', + 'STALL_CONTROL_XBARPORT5_0__StallVC5ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT5_0__StallVC7ReqEn_MASK', + 'STALL_CONTROL_XBARPORT5_0__StallVC7ReqEn__SHIFT', + 'STALL_CONTROL_XBARPORT5_1__StallVC0RspEn_MASK', + 'STALL_CONTROL_XBARPORT5_1__StallVC0RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT5_1__StallVC1RspEn_MASK', + 'STALL_CONTROL_XBARPORT5_1__StallVC1RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT5_1__StallVC2RspEn_MASK', + 'STALL_CONTROL_XBARPORT5_1__StallVC2RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT5_1__StallVC3RspEn_MASK', + 'STALL_CONTROL_XBARPORT5_1__StallVC3RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT5_1__StallVC4RspEn_MASK', + 'STALL_CONTROL_XBARPORT5_1__StallVC4RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT5_1__StallVC5RspEn_MASK', + 'STALL_CONTROL_XBARPORT5_1__StallVC5RspEn__SHIFT', + 'STALL_CONTROL_XBARPORT5_1__StallVC7RspEn_MASK', + 'STALL_CONTROL_XBARPORT5_1__StallVC7RspEn__SHIFT', + 'SUM_DATA__SUM_DATA_MASK', 'SUM_DATA__SUM_DATA__SHIFT', + 'SUM_INDEX_HI__SUM_INDEX_HI_MASK', + 'SUM_INDEX_HI__SUM_INDEX_HI__SHIFT', 'SUM_INDEX__SUM_INDEX_MASK', + 'SUM_INDEX__SUM_INDEX__SHIFT', + 'SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector_MASK', + 'SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector__SHIFT', + 'SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector_MASK', + 'SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector__SHIFT', + 'SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector_MASK', + 'SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector__SHIFT', + 'SW_NMI_CNTL__SW_NMI_Status_MASK', + 'SW_NMI_CNTL__SW_NMI_Status__SHIFT', + 'SW_SCI_CNTL__SW_SCI_Status_MASK', + 'SW_SCI_CNTL__SW_SCI_Status__SHIFT', + 'SW_SMI_CNTL__SW_SMI_Status_MASK', + 'SW_SMI_CNTL__SW_SMI_Status__SHIFT', + 'SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML_MASK', + 'SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML__SHIFT', + 'SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE_MASK', + 'SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE__SHIFT', + 'SW_US_LOCATION__SW_USlocated_Core_MASK', + 'SW_US_LOCATION__SW_USlocated_Core__SHIFT', + 'SW_US_LOCATION__SW_USlocated_Port_MASK', + 'SW_US_LOCATION__SW_USlocated_Port__SHIFT', + 'SYNCFLOOD_STATUS__SyncfloodFromAPML_MASK', + 'SYNCFLOOD_STATUS__SyncfloodFromAPML__SHIFT', + 'SYNCFLOOD_STATUS__SyncfloodFromMCA_MASK', + 'SYNCFLOOD_STATUS__SyncfloodFromMCA__SHIFT', + 'SYNCFLOOD_STATUS__SyncfloodFromPin_MASK', + 'SYNCFLOOD_STATUS__SyncfloodFromPin__SHIFT', + 'SYNCFLOOD_STATUS__SyncfloodFromPrivate_MASK', + 'SYNCFLOOD_STATUS__SyncfloodFromPrivate__SHIFT', + 'SYNCFLOOD_STATUS__SyncfloodFromRASCntl_MASK', + 'SYNCFLOOD_STATUS__SyncfloodFromRASCntl__SHIFT', + 'TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask_MASK', + 'TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask__SHIFT', + 'TRAP0_ADDRESS_HI__Trap0AddrHi_MASK', + 'TRAP0_ADDRESS_HI__Trap0AddrHi__SHIFT', + 'TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask_MASK', + 'TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask__SHIFT', + 'TRAP0_ADDRESS_LO__Trap0AddrLo_MASK', + 'TRAP0_ADDRESS_LO__Trap0AddrLo__SHIFT', + 'TRAP0_COMMAND_MASK__Trap0Cmd0Mask_MASK', + 'TRAP0_COMMAND_MASK__Trap0Cmd0Mask__SHIFT', + 'TRAP0_COMMAND_MASK__Trap0Cmd1Mask_MASK', + 'TRAP0_COMMAND_MASK__Trap0Cmd1Mask__SHIFT', + 'TRAP0_COMMAND__Trap0Cmd0_MASK', + 'TRAP0_COMMAND__Trap0Cmd0__SHIFT', + 'TRAP0_COMMAND__Trap0Cmd1_MASK', + 'TRAP0_COMMAND__Trap0Cmd1__SHIFT', + 'TRAP0_CONTROL0__Trap0CrossTrigger_MASK', + 'TRAP0_CONTROL0__Trap0CrossTrigger__SHIFT', + 'TRAP0_CONTROL0__Trap0En_MASK', 'TRAP0_CONTROL0__Trap0En__SHIFT', + 'TRAP0_CONTROL0__Trap0SMUIntr_MASK', + 'TRAP0_CONTROL0__Trap0SMUIntr__SHIFT', + 'TRAP0_CONTROL0__Trap0Stage2En_MASK', + 'TRAP0_CONTROL0__Trap0Stage2En__SHIFT', + 'TRAP0_CONTROL0__Trap0Stage2Ptr_MASK', + 'TRAP0_CONTROL0__Trap0Stage2Ptr__SHIFT', + 'TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask_MASK', + 'TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask__SHIFT', + 'TRAP10_ADDRESS_HI__Trap10AddrHi_MASK', + 'TRAP10_ADDRESS_HI__Trap10AddrHi__SHIFT', + 'TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask_MASK', + 'TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask__SHIFT', + 'TRAP10_ADDRESS_LO__Trap10AddrLo_MASK', + 'TRAP10_ADDRESS_LO__Trap10AddrLo__SHIFT', + 'TRAP10_COMMAND_MASK__Trap10Cmd0Mask_MASK', + 'TRAP10_COMMAND_MASK__Trap10Cmd0Mask__SHIFT', + 'TRAP10_COMMAND_MASK__Trap10Cmd1Mask_MASK', + 'TRAP10_COMMAND_MASK__Trap10Cmd1Mask__SHIFT', + 'TRAP10_COMMAND__Trap10Cmd0_MASK', + 'TRAP10_COMMAND__Trap10Cmd0__SHIFT', + 'TRAP10_COMMAND__Trap10Cmd1_MASK', + 'TRAP10_COMMAND__Trap10Cmd1__SHIFT', + 'TRAP10_CONTROL0__Trap10CrossTrigger_MASK', + 'TRAP10_CONTROL0__Trap10CrossTrigger__SHIFT', + 'TRAP10_CONTROL0__Trap10En_MASK', + 'TRAP10_CONTROL0__Trap10En__SHIFT', + 'TRAP10_CONTROL0__Trap10SMUIntr_MASK', + 'TRAP10_CONTROL0__Trap10SMUIntr__SHIFT', + 'TRAP10_CONTROL0__Trap10Stage2En_MASK', + 'TRAP10_CONTROL0__Trap10Stage2En__SHIFT', + 'TRAP10_CONTROL0__Trap10Stage2Ptr_MASK', + 'TRAP10_CONTROL0__Trap10Stage2Ptr__SHIFT', + 'TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask_MASK', + 'TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask__SHIFT', + 'TRAP11_ADDRESS_HI__Trap11AddrHi_MASK', + 'TRAP11_ADDRESS_HI__Trap11AddrHi__SHIFT', + 'TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask_MASK', + 'TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask__SHIFT', + 'TRAP11_ADDRESS_LO__Trap11AddrLo_MASK', + 'TRAP11_ADDRESS_LO__Trap11AddrLo__SHIFT', + 'TRAP11_COMMAND_MASK__Trap11Cmd0Mask_MASK', + 'TRAP11_COMMAND_MASK__Trap11Cmd0Mask__SHIFT', + 'TRAP11_COMMAND_MASK__Trap11Cmd1Mask_MASK', + 'TRAP11_COMMAND_MASK__Trap11Cmd1Mask__SHIFT', + 'TRAP11_COMMAND__Trap11Cmd0_MASK', + 'TRAP11_COMMAND__Trap11Cmd0__SHIFT', + 'TRAP11_COMMAND__Trap11Cmd1_MASK', + 'TRAP11_COMMAND__Trap11Cmd1__SHIFT', + 'TRAP11_CONTROL0__Trap11CrossTrigger_MASK', + 'TRAP11_CONTROL0__Trap11CrossTrigger__SHIFT', + 'TRAP11_CONTROL0__Trap11En_MASK', + 'TRAP11_CONTROL0__Trap11En__SHIFT', + 'TRAP11_CONTROL0__Trap11SMUIntr_MASK', + 'TRAP11_CONTROL0__Trap11SMUIntr__SHIFT', + 'TRAP11_CONTROL0__Trap11Stage2En_MASK', + 'TRAP11_CONTROL0__Trap11Stage2En__SHIFT', + 'TRAP11_CONTROL0__Trap11Stage2Ptr_MASK', + 'TRAP11_CONTROL0__Trap11Stage2Ptr__SHIFT', + 'TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask_MASK', + 'TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask__SHIFT', + 'TRAP12_ADDRESS_HI__Trap12AddrHi_MASK', + 'TRAP12_ADDRESS_HI__Trap12AddrHi__SHIFT', + 'TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask_MASK', + 'TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask__SHIFT', + 'TRAP12_ADDRESS_LO__Trap12AddrLo_MASK', + 'TRAP12_ADDRESS_LO__Trap12AddrLo__SHIFT', + 'TRAP12_COMMAND_MASK__Trap12Cmd0Mask_MASK', + 'TRAP12_COMMAND_MASK__Trap12Cmd0Mask__SHIFT', + 'TRAP12_COMMAND_MASK__Trap12Cmd1Mask_MASK', + 'TRAP12_COMMAND_MASK__Trap12Cmd1Mask__SHIFT', + 'TRAP12_COMMAND__Trap12Cmd0_MASK', + 'TRAP12_COMMAND__Trap12Cmd0__SHIFT', + 'TRAP12_COMMAND__Trap12Cmd1_MASK', + 'TRAP12_COMMAND__Trap12Cmd1__SHIFT', + 'TRAP12_CONTROL0__Trap12CrossTrigger_MASK', + 'TRAP12_CONTROL0__Trap12CrossTrigger__SHIFT', + 'TRAP12_CONTROL0__Trap12En_MASK', + 'TRAP12_CONTROL0__Trap12En__SHIFT', + 'TRAP12_CONTROL0__Trap12SMUIntr_MASK', + 'TRAP12_CONTROL0__Trap12SMUIntr__SHIFT', + 'TRAP12_CONTROL0__Trap12Stage2En_MASK', + 'TRAP12_CONTROL0__Trap12Stage2En__SHIFT', + 'TRAP12_CONTROL0__Trap12Stage2Ptr_MASK', + 'TRAP12_CONTROL0__Trap12Stage2Ptr__SHIFT', + 'TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask_MASK', + 'TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask__SHIFT', + 'TRAP13_ADDRESS_HI__Trap13AddrHi_MASK', + 'TRAP13_ADDRESS_HI__Trap13AddrHi__SHIFT', + 'TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask_MASK', + 'TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask__SHIFT', + 'TRAP13_ADDRESS_LO__Trap13AddrLo_MASK', + 'TRAP13_ADDRESS_LO__Trap13AddrLo__SHIFT', + 'TRAP13_COMMAND_MASK__Trap13Cmd0Mask_MASK', + 'TRAP13_COMMAND_MASK__Trap13Cmd0Mask__SHIFT', + 'TRAP13_COMMAND_MASK__Trap13Cmd1Mask_MASK', + 'TRAP13_COMMAND_MASK__Trap13Cmd1Mask__SHIFT', + 'TRAP13_COMMAND__Trap13Cmd0_MASK', + 'TRAP13_COMMAND__Trap13Cmd0__SHIFT', + 'TRAP13_COMMAND__Trap13Cmd1_MASK', + 'TRAP13_COMMAND__Trap13Cmd1__SHIFT', + 'TRAP13_CONTROL0__Trap13CrossTrigger_MASK', + 'TRAP13_CONTROL0__Trap13CrossTrigger__SHIFT', + 'TRAP13_CONTROL0__Trap13En_MASK', + 'TRAP13_CONTROL0__Trap13En__SHIFT', + 'TRAP13_CONTROL0__Trap13SMUIntr_MASK', + 'TRAP13_CONTROL0__Trap13SMUIntr__SHIFT', + 'TRAP13_CONTROL0__Trap13Stage2En_MASK', + 'TRAP13_CONTROL0__Trap13Stage2En__SHIFT', + 'TRAP13_CONTROL0__Trap13Stage2Ptr_MASK', + 'TRAP13_CONTROL0__Trap13Stage2Ptr__SHIFT', + 'TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask_MASK', + 'TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask__SHIFT', + 'TRAP14_ADDRESS_HI__Trap14AddrHi_MASK', + 'TRAP14_ADDRESS_HI__Trap14AddrHi__SHIFT', + 'TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask_MASK', + 'TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask__SHIFT', + 'TRAP14_ADDRESS_LO__Trap14AddrLo_MASK', + 'TRAP14_ADDRESS_LO__Trap14AddrLo__SHIFT', + 'TRAP14_COMMAND_MASK__Trap14Cmd0Mask_MASK', + 'TRAP14_COMMAND_MASK__Trap14Cmd0Mask__SHIFT', + 'TRAP14_COMMAND_MASK__Trap14Cmd1Mask_MASK', + 'TRAP14_COMMAND_MASK__Trap14Cmd1Mask__SHIFT', + 'TRAP14_COMMAND__Trap14Cmd0_MASK', + 'TRAP14_COMMAND__Trap14Cmd0__SHIFT', + 'TRAP14_COMMAND__Trap14Cmd1_MASK', + 'TRAP14_COMMAND__Trap14Cmd1__SHIFT', + 'TRAP14_CONTROL0__Trap14CrossTrigger_MASK', + 'TRAP14_CONTROL0__Trap14CrossTrigger__SHIFT', + 'TRAP14_CONTROL0__Trap14En_MASK', + 'TRAP14_CONTROL0__Trap14En__SHIFT', + 'TRAP14_CONTROL0__Trap14SMUIntr_MASK', + 'TRAP14_CONTROL0__Trap14SMUIntr__SHIFT', + 'TRAP14_CONTROL0__Trap14Stage2En_MASK', + 'TRAP14_CONTROL0__Trap14Stage2En__SHIFT', + 'TRAP14_CONTROL0__Trap14Stage2Ptr_MASK', + 'TRAP14_CONTROL0__Trap14Stage2Ptr__SHIFT', + 'TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask_MASK', + 'TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask__SHIFT', + 'TRAP15_ADDRESS_HI__Trap15AddrHi_MASK', + 'TRAP15_ADDRESS_HI__Trap15AddrHi__SHIFT', + 'TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask_MASK', + 'TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask__SHIFT', + 'TRAP15_ADDRESS_LO__Trap15AddrLo_MASK', + 'TRAP15_ADDRESS_LO__Trap15AddrLo__SHIFT', + 'TRAP15_COMMAND_MASK__Trap15Cmd0Mask_MASK', + 'TRAP15_COMMAND_MASK__Trap15Cmd0Mask__SHIFT', + 'TRAP15_COMMAND_MASK__Trap15Cmd1Mask_MASK', + 'TRAP15_COMMAND_MASK__Trap15Cmd1Mask__SHIFT', + 'TRAP15_COMMAND__Trap15Cmd0_MASK', + 'TRAP15_COMMAND__Trap15Cmd0__SHIFT', + 'TRAP15_COMMAND__Trap15Cmd1_MASK', + 'TRAP15_COMMAND__Trap15Cmd1__SHIFT', + 'TRAP15_CONTROL0__Trap15CrossTrigger_MASK', + 'TRAP15_CONTROL0__Trap15CrossTrigger__SHIFT', + 'TRAP15_CONTROL0__Trap15En_MASK', + 'TRAP15_CONTROL0__Trap15En__SHIFT', + 'TRAP15_CONTROL0__Trap15SMUIntr_MASK', + 'TRAP15_CONTROL0__Trap15SMUIntr__SHIFT', + 'TRAP15_CONTROL0__Trap15Stage2En_MASK', + 'TRAP15_CONTROL0__Trap15Stage2En__SHIFT', + 'TRAP15_CONTROL0__Trap15Stage2Ptr_MASK', + 'TRAP15_CONTROL0__Trap15Stage2Ptr__SHIFT', + 'TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask_MASK', + 'TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask__SHIFT', + 'TRAP1_ADDRESS_HI__Trap1AddrHi_MASK', + 'TRAP1_ADDRESS_HI__Trap1AddrHi__SHIFT', + 'TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask_MASK', + 'TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask__SHIFT', + 'TRAP1_ADDRESS_LO__Trap1AddrLo_MASK', + 'TRAP1_ADDRESS_LO__Trap1AddrLo__SHIFT', + 'TRAP1_COMMAND_MASK__Trap1Cmd0Mask_MASK', + 'TRAP1_COMMAND_MASK__Trap1Cmd0Mask__SHIFT', + 'TRAP1_COMMAND_MASK__Trap1Cmd1Mask_MASK', + 'TRAP1_COMMAND_MASK__Trap1Cmd1Mask__SHIFT', + 'TRAP1_COMMAND__Trap1Cmd0_MASK', + 'TRAP1_COMMAND__Trap1Cmd0__SHIFT', + 'TRAP1_COMMAND__Trap1Cmd1_MASK', + 'TRAP1_COMMAND__Trap1Cmd1__SHIFT', + 'TRAP1_CONTROL0__Trap1CrossTrigger_MASK', + 'TRAP1_CONTROL0__Trap1CrossTrigger__SHIFT', + 'TRAP1_CONTROL0__Trap1En_MASK', 'TRAP1_CONTROL0__Trap1En__SHIFT', + 'TRAP1_CONTROL0__Trap1SMUIntr_MASK', + 'TRAP1_CONTROL0__Trap1SMUIntr__SHIFT', + 'TRAP1_CONTROL0__Trap1Stage2En_MASK', + 'TRAP1_CONTROL0__Trap1Stage2En__SHIFT', + 'TRAP1_CONTROL0__Trap1Stage2Ptr_MASK', + 'TRAP1_CONTROL0__Trap1Stage2Ptr__SHIFT', + 'TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask_MASK', + 'TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask__SHIFT', + 'TRAP2_ADDRESS_HI__Trap2AddrHi_MASK', + 'TRAP2_ADDRESS_HI__Trap2AddrHi__SHIFT', + 'TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask_MASK', + 'TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask__SHIFT', + 'TRAP2_ADDRESS_LO__Trap2AddrLo_MASK', + 'TRAP2_ADDRESS_LO__Trap2AddrLo__SHIFT', + 'TRAP2_COMMAND_MASK__Trap2Cmd0Mask_MASK', + 'TRAP2_COMMAND_MASK__Trap2Cmd0Mask__SHIFT', + 'TRAP2_COMMAND_MASK__Trap2Cmd1Mask_MASK', + 'TRAP2_COMMAND_MASK__Trap2Cmd1Mask__SHIFT', + 'TRAP2_COMMAND__Trap2Cmd0_MASK', + 'TRAP2_COMMAND__Trap2Cmd0__SHIFT', + 'TRAP2_COMMAND__Trap2Cmd1_MASK', + 'TRAP2_COMMAND__Trap2Cmd1__SHIFT', + 'TRAP2_CONTROL0__Trap2CrossTrigger_MASK', + 'TRAP2_CONTROL0__Trap2CrossTrigger__SHIFT', + 'TRAP2_CONTROL0__Trap2En_MASK', 'TRAP2_CONTROL0__Trap2En__SHIFT', + 'TRAP2_CONTROL0__Trap2SMUIntr_MASK', + 'TRAP2_CONTROL0__Trap2SMUIntr__SHIFT', + 'TRAP2_CONTROL0__Trap2Stage2En_MASK', + 'TRAP2_CONTROL0__Trap2Stage2En__SHIFT', + 'TRAP2_CONTROL0__Trap2Stage2Ptr_MASK', + 'TRAP2_CONTROL0__Trap2Stage2Ptr__SHIFT', + 'TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask_MASK', + 'TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask__SHIFT', + 'TRAP3_ADDRESS_HI__Trap3AddrHi_MASK', + 'TRAP3_ADDRESS_HI__Trap3AddrHi__SHIFT', + 'TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask_MASK', + 'TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask__SHIFT', + 'TRAP3_ADDRESS_LO__Trap3AddrLo_MASK', + 'TRAP3_ADDRESS_LO__Trap3AddrLo__SHIFT', + 'TRAP3_COMMAND_MASK__Trap3Cmd0Mask_MASK', + 'TRAP3_COMMAND_MASK__Trap3Cmd0Mask__SHIFT', + 'TRAP3_COMMAND_MASK__Trap3Cmd1Mask_MASK', + 'TRAP3_COMMAND_MASK__Trap3Cmd1Mask__SHIFT', + 'TRAP3_COMMAND__Trap3Cmd0_MASK', + 'TRAP3_COMMAND__Trap3Cmd0__SHIFT', + 'TRAP3_COMMAND__Trap3Cmd1_MASK', + 'TRAP3_COMMAND__Trap3Cmd1__SHIFT', + 'TRAP3_CONTROL0__Trap3CrossTrigger_MASK', + 'TRAP3_CONTROL0__Trap3CrossTrigger__SHIFT', + 'TRAP3_CONTROL0__Trap3En_MASK', 'TRAP3_CONTROL0__Trap3En__SHIFT', + 'TRAP3_CONTROL0__Trap3SMUIntr_MASK', + 'TRAP3_CONTROL0__Trap3SMUIntr__SHIFT', + 'TRAP3_CONTROL0__Trap3Stage2En_MASK', + 'TRAP3_CONTROL0__Trap3Stage2En__SHIFT', + 'TRAP3_CONTROL0__Trap3Stage2Ptr_MASK', + 'TRAP3_CONTROL0__Trap3Stage2Ptr__SHIFT', + 'TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask_MASK', + 'TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask__SHIFT', + 'TRAP4_ADDRESS_HI__Trap4AddrHi_MASK', + 'TRAP4_ADDRESS_HI__Trap4AddrHi__SHIFT', + 'TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask_MASK', + 'TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask__SHIFT', + 'TRAP4_ADDRESS_LO__Trap4AddrLo_MASK', + 'TRAP4_ADDRESS_LO__Trap4AddrLo__SHIFT', + 'TRAP4_COMMAND_MASK__Trap4Cmd0Mask_MASK', + 'TRAP4_COMMAND_MASK__Trap4Cmd0Mask__SHIFT', + 'TRAP4_COMMAND_MASK__Trap4Cmd1Mask_MASK', + 'TRAP4_COMMAND_MASK__Trap4Cmd1Mask__SHIFT', + 'TRAP4_COMMAND__Trap4Cmd0_MASK', + 'TRAP4_COMMAND__Trap4Cmd0__SHIFT', + 'TRAP4_COMMAND__Trap4Cmd1_MASK', + 'TRAP4_COMMAND__Trap4Cmd1__SHIFT', + 'TRAP4_CONTROL0__Trap4CrossTrigger_MASK', + 'TRAP4_CONTROL0__Trap4CrossTrigger__SHIFT', + 'TRAP4_CONTROL0__Trap4En_MASK', 'TRAP4_CONTROL0__Trap4En__SHIFT', + 'TRAP4_CONTROL0__Trap4SMUIntr_MASK', + 'TRAP4_CONTROL0__Trap4SMUIntr__SHIFT', + 'TRAP4_CONTROL0__Trap4Stage2En_MASK', + 'TRAP4_CONTROL0__Trap4Stage2En__SHIFT', + 'TRAP4_CONTROL0__Trap4Stage2Ptr_MASK', + 'TRAP4_CONTROL0__Trap4Stage2Ptr__SHIFT', + 'TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask_MASK', + 'TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask__SHIFT', + 'TRAP5_ADDRESS_HI__Trap5AddrHi_MASK', + 'TRAP5_ADDRESS_HI__Trap5AddrHi__SHIFT', + 'TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask_MASK', + 'TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask__SHIFT', + 'TRAP5_ADDRESS_LO__Trap5AddrLo_MASK', + 'TRAP5_ADDRESS_LO__Trap5AddrLo__SHIFT', + 'TRAP5_COMMAND_MASK__Trap5Cmd0Mask_MASK', + 'TRAP5_COMMAND_MASK__Trap5Cmd0Mask__SHIFT', + 'TRAP5_COMMAND_MASK__Trap5Cmd1Mask_MASK', + 'TRAP5_COMMAND_MASK__Trap5Cmd1Mask__SHIFT', + 'TRAP5_COMMAND__Trap5Cmd0_MASK', + 'TRAP5_COMMAND__Trap5Cmd0__SHIFT', + 'TRAP5_COMMAND__Trap5Cmd1_MASK', + 'TRAP5_COMMAND__Trap5Cmd1__SHIFT', + 'TRAP5_CONTROL0__Trap5CrossTrigger_MASK', + 'TRAP5_CONTROL0__Trap5CrossTrigger__SHIFT', + 'TRAP5_CONTROL0__Trap5En_MASK', 'TRAP5_CONTROL0__Trap5En__SHIFT', + 'TRAP5_CONTROL0__Trap5SMUIntr_MASK', + 'TRAP5_CONTROL0__Trap5SMUIntr__SHIFT', + 'TRAP5_CONTROL0__Trap5Stage2En_MASK', + 'TRAP5_CONTROL0__Trap5Stage2En__SHIFT', + 'TRAP5_CONTROL0__Trap5Stage2Ptr_MASK', + 'TRAP5_CONTROL0__Trap5Stage2Ptr__SHIFT', + 'TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask_MASK', + 'TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask__SHIFT', + 'TRAP6_ADDRESS_HI__Trap6AddrHi_MASK', + 'TRAP6_ADDRESS_HI__Trap6AddrHi__SHIFT', + 'TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask_MASK', + 'TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask__SHIFT', + 'TRAP6_ADDRESS_LO__Trap6AddrLo_MASK', + 'TRAP6_ADDRESS_LO__Trap6AddrLo__SHIFT', + 'TRAP6_COMMAND_MASK__Trap6Cmd0Mask_MASK', + 'TRAP6_COMMAND_MASK__Trap6Cmd0Mask__SHIFT', + 'TRAP6_COMMAND_MASK__Trap6Cmd1Mask_MASK', + 'TRAP6_COMMAND_MASK__Trap6Cmd1Mask__SHIFT', + 'TRAP6_COMMAND__Trap6Cmd0_MASK', + 'TRAP6_COMMAND__Trap6Cmd0__SHIFT', + 'TRAP6_COMMAND__Trap6Cmd1_MASK', + 'TRAP6_COMMAND__Trap6Cmd1__SHIFT', + 'TRAP6_CONTROL0__Trap6CrossTrigger_MASK', + 'TRAP6_CONTROL0__Trap6CrossTrigger__SHIFT', + 'TRAP6_CONTROL0__Trap6En_MASK', 'TRAP6_CONTROL0__Trap6En__SHIFT', + 'TRAP6_CONTROL0__Trap6SMUIntr_MASK', + 'TRAP6_CONTROL0__Trap6SMUIntr__SHIFT', + 'TRAP6_CONTROL0__Trap6Stage2En_MASK', + 'TRAP6_CONTROL0__Trap6Stage2En__SHIFT', + 'TRAP6_CONTROL0__Trap6Stage2Ptr_MASK', + 'TRAP6_CONTROL0__Trap6Stage2Ptr__SHIFT', + 'TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask_MASK', + 'TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask__SHIFT', + 'TRAP7_ADDRESS_HI__Trap7AddrHi_MASK', + 'TRAP7_ADDRESS_HI__Trap7AddrHi__SHIFT', + 'TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask_MASK', + 'TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask__SHIFT', + 'TRAP7_ADDRESS_LO__Trap7AddrLo_MASK', + 'TRAP7_ADDRESS_LO__Trap7AddrLo__SHIFT', + 'TRAP7_COMMAND_MASK__Trap7Cmd0Mask_MASK', + 'TRAP7_COMMAND_MASK__Trap7Cmd0Mask__SHIFT', + 'TRAP7_COMMAND_MASK__Trap7Cmd1Mask_MASK', + 'TRAP7_COMMAND_MASK__Trap7Cmd1Mask__SHIFT', + 'TRAP7_COMMAND__Trap7Cmd0_MASK', + 'TRAP7_COMMAND__Trap7Cmd0__SHIFT', + 'TRAP7_COMMAND__Trap7Cmd1_MASK', + 'TRAP7_COMMAND__Trap7Cmd1__SHIFT', + 'TRAP7_CONTROL0__Trap7CrossTrigger_MASK', + 'TRAP7_CONTROL0__Trap7CrossTrigger__SHIFT', + 'TRAP7_CONTROL0__Trap7En_MASK', 'TRAP7_CONTROL0__Trap7En__SHIFT', + 'TRAP7_CONTROL0__Trap7SMUIntr_MASK', + 'TRAP7_CONTROL0__Trap7SMUIntr__SHIFT', + 'TRAP7_CONTROL0__Trap7Stage2En_MASK', + 'TRAP7_CONTROL0__Trap7Stage2En__SHIFT', + 'TRAP7_CONTROL0__Trap7Stage2Ptr_MASK', + 'TRAP7_CONTROL0__Trap7Stage2Ptr__SHIFT', + 'TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask_MASK', + 'TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask__SHIFT', + 'TRAP8_ADDRESS_HI__Trap8AddrHi_MASK', + 'TRAP8_ADDRESS_HI__Trap8AddrHi__SHIFT', + 'TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask_MASK', + 'TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask__SHIFT', + 'TRAP8_ADDRESS_LO__Trap8AddrLo_MASK', + 'TRAP8_ADDRESS_LO__Trap8AddrLo__SHIFT', + 'TRAP8_COMMAND_MASK__Trap8Cmd0Mask_MASK', + 'TRAP8_COMMAND_MASK__Trap8Cmd0Mask__SHIFT', + 'TRAP8_COMMAND_MASK__Trap8Cmd1Mask_MASK', + 'TRAP8_COMMAND_MASK__Trap8Cmd1Mask__SHIFT', + 'TRAP8_COMMAND__Trap8Cmd0_MASK', + 'TRAP8_COMMAND__Trap8Cmd0__SHIFT', + 'TRAP8_COMMAND__Trap8Cmd1_MASK', + 'TRAP8_COMMAND__Trap8Cmd1__SHIFT', + 'TRAP8_CONTROL0__Trap8CrossTrigger_MASK', + 'TRAP8_CONTROL0__Trap8CrossTrigger__SHIFT', + 'TRAP8_CONTROL0__Trap8En_MASK', 'TRAP8_CONTROL0__Trap8En__SHIFT', + 'TRAP8_CONTROL0__Trap8SMUIntr_MASK', + 'TRAP8_CONTROL0__Trap8SMUIntr__SHIFT', + 'TRAP8_CONTROL0__Trap8Stage2En_MASK', + 'TRAP8_CONTROL0__Trap8Stage2En__SHIFT', + 'TRAP8_CONTROL0__Trap8Stage2Ptr_MASK', + 'TRAP8_CONTROL0__Trap8Stage2Ptr__SHIFT', + 'TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask_MASK', + 'TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask__SHIFT', + 'TRAP9_ADDRESS_HI__Trap9AddrHi_MASK', + 'TRAP9_ADDRESS_HI__Trap9AddrHi__SHIFT', + 'TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask_MASK', + 'TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask__SHIFT', + 'TRAP9_ADDRESS_LO__Trap9AddrLo_MASK', + 'TRAP9_ADDRESS_LO__Trap9AddrLo__SHIFT', + 'TRAP9_COMMAND_MASK__Trap9Cmd0Mask_MASK', + 'TRAP9_COMMAND_MASK__Trap9Cmd0Mask__SHIFT', + 'TRAP9_COMMAND_MASK__Trap9Cmd1Mask_MASK', + 'TRAP9_COMMAND_MASK__Trap9Cmd1Mask__SHIFT', + 'TRAP9_COMMAND__Trap9Cmd0_MASK', + 'TRAP9_COMMAND__Trap9Cmd0__SHIFT', + 'TRAP9_COMMAND__Trap9Cmd1_MASK', + 'TRAP9_COMMAND__Trap9Cmd1__SHIFT', + 'TRAP9_CONTROL0__Trap9CrossTrigger_MASK', + 'TRAP9_CONTROL0__Trap9CrossTrigger__SHIFT', + 'TRAP9_CONTROL0__Trap9En_MASK', 'TRAP9_CONTROL0__Trap9En__SHIFT', + 'TRAP9_CONTROL0__Trap9SMUIntr_MASK', + 'TRAP9_CONTROL0__Trap9SMUIntr__SHIFT', + 'TRAP9_CONTROL0__Trap9Stage2En_MASK', + 'TRAP9_CONTROL0__Trap9Stage2En__SHIFT', + 'TRAP9_CONTROL0__Trap9Stage2Ptr_MASK', + 'TRAP9_CONTROL0__Trap9Stage2Ptr__SHIFT', + 'TRAP_REQUEST0__TrapReqAddrLo_MASK', + 'TRAP_REQUEST0__TrapReqAddrLo__SHIFT', + 'TRAP_REQUEST1__TrapReqAddrHi_MASK', + 'TRAP_REQUEST1__TrapReqAddrHi__SHIFT', + 'TRAP_REQUEST2__TrapAttr_MASK', 'TRAP_REQUEST2__TrapAttr__SHIFT', + 'TRAP_REQUEST2__TrapReqCmd_MASK', + 'TRAP_REQUEST2__TrapReqCmd__SHIFT', + 'TRAP_REQUEST2__TrapReqLen_MASK', + 'TRAP_REQUEST2__TrapReqLen__SHIFT', + 'TRAP_REQUEST3__TrapReqBlockLevel_MASK', + 'TRAP_REQUEST3__TrapReqBlockLevel__SHIFT', + 'TRAP_REQUEST3__TrapReqChain_MASK', + 'TRAP_REQUEST3__TrapReqChain__SHIFT', + 'TRAP_REQUEST3__TrapReqIO_MASK', + 'TRAP_REQUEST3__TrapReqIO__SHIFT', + 'TRAP_REQUEST3__TrapReqPassPW_MASK', + 'TRAP_REQUEST3__TrapReqPassPW__SHIFT', + 'TRAP_REQUEST3__TrapReqRspPassPW_MASK', + 'TRAP_REQUEST3__TrapReqRspPassPW__SHIFT', + 'TRAP_REQUEST3__TrapReqUnitID_MASK', + 'TRAP_REQUEST3__TrapReqUnitID__SHIFT', + 'TRAP_REQUEST3__TrapReqVC_MASK', + 'TRAP_REQUEST3__TrapReqVC__SHIFT', + 'TRAP_REQUEST4__TrapReqSecLevel_MASK', + 'TRAP_REQUEST4__TrapReqSecLevel__SHIFT', + 'TRAP_REQUEST5__TrapReqDataErr_MASK', + 'TRAP_REQUEST5__TrapReqDataErr__SHIFT', + 'TRAP_REQUEST5__TrapReqDataParity_MASK', + 'TRAP_REQUEST5__TrapReqDataParity__SHIFT', + 'TRAP_REQUEST5__TrapReqDataVC_MASK', + 'TRAP_REQUEST5__TrapReqDataVC__SHIFT', + 'TRAP_REQUEST_DATA0__TrapReqData0_MASK', + 'TRAP_REQUEST_DATA0__TrapReqData0__SHIFT', + 'TRAP_REQUEST_DATA10__TrapReqData10_MASK', + 'TRAP_REQUEST_DATA10__TrapReqData10__SHIFT', + 'TRAP_REQUEST_DATA11__TrapReqData11_MASK', + 'TRAP_REQUEST_DATA11__TrapReqData11__SHIFT', + 'TRAP_REQUEST_DATA12__TrapReqData12_MASK', + 'TRAP_REQUEST_DATA12__TrapReqData12__SHIFT', + 'TRAP_REQUEST_DATA13__TrapReqData13_MASK', + 'TRAP_REQUEST_DATA13__TrapReqData13__SHIFT', + 'TRAP_REQUEST_DATA14__TrapReqData14_MASK', + 'TRAP_REQUEST_DATA14__TrapReqData14__SHIFT', + 'TRAP_REQUEST_DATA15__TrapReqData15_MASK', + 'TRAP_REQUEST_DATA15__TrapReqData15__SHIFT', + 'TRAP_REQUEST_DATA1__TrapReqData1_MASK', + 'TRAP_REQUEST_DATA1__TrapReqData1__SHIFT', + 'TRAP_REQUEST_DATA2__TrapReqData2_MASK', + 'TRAP_REQUEST_DATA2__TrapReqData2__SHIFT', + 'TRAP_REQUEST_DATA3__TrapReqData3_MASK', + 'TRAP_REQUEST_DATA3__TrapReqData3__SHIFT', + 'TRAP_REQUEST_DATA4__TrapReqData4_MASK', + 'TRAP_REQUEST_DATA4__TrapReqData4__SHIFT', + 'TRAP_REQUEST_DATA5__TrapReqData5_MASK', + 'TRAP_REQUEST_DATA5__TrapReqData5__SHIFT', + 'TRAP_REQUEST_DATA6__TrapReqData6_MASK', + 'TRAP_REQUEST_DATA6__TrapReqData6__SHIFT', + 'TRAP_REQUEST_DATA7__TrapReqData7_MASK', + 'TRAP_REQUEST_DATA7__TrapReqData7__SHIFT', + 'TRAP_REQUEST_DATA8__TrapReqData8_MASK', + 'TRAP_REQUEST_DATA8__TrapReqData8__SHIFT', + 'TRAP_REQUEST_DATA9__TrapReqData9_MASK', + 'TRAP_REQUEST_DATA9__TrapReqData9__SHIFT', + 'TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0_MASK', + 'TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0__SHIFT', + 'TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1_MASK', + 'TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1__SHIFT', + 'TRAP_RESPONSE0__TrapRspDataStatus_MASK', + 'TRAP_RESPONSE0__TrapRspDataStatus__SHIFT', + 'TRAP_RESPONSE0__TrapRspPassPW_MASK', + 'TRAP_RESPONSE0__TrapRspPassPW__SHIFT', + 'TRAP_RESPONSE0__TrapRspStatus_MASK', + 'TRAP_RESPONSE0__TrapRspStatus__SHIFT', + 'TRAP_RESPONSE_CONTROL__TrapRspReqPassthru_MASK', + 'TRAP_RESPONSE_CONTROL__TrapRspReqPassthru__SHIFT', + 'TRAP_RESPONSE_CONTROL__TrapRspTrigger_MASK', + 'TRAP_RESPONSE_CONTROL__TrapRspTrigger__SHIFT', + 'TRAP_RESPONSE_DATA0__TrapRdRspData0_MASK', + 'TRAP_RESPONSE_DATA0__TrapRdRspData0__SHIFT', + 'TRAP_RESPONSE_DATA10__TrapRdRspData10_MASK', + 'TRAP_RESPONSE_DATA10__TrapRdRspData10__SHIFT', + 'TRAP_RESPONSE_DATA11__TrapRdRspData11_MASK', + 'TRAP_RESPONSE_DATA11__TrapRdRspData11__SHIFT', + 'TRAP_RESPONSE_DATA12__TrapRdRspData12_MASK', + 'TRAP_RESPONSE_DATA12__TrapRdRspData12__SHIFT', + 'TRAP_RESPONSE_DATA13__TrapRdRspData13_MASK', + 'TRAP_RESPONSE_DATA13__TrapRdRspData13__SHIFT', + 'TRAP_RESPONSE_DATA14__TrapRdRspData14_MASK', + 'TRAP_RESPONSE_DATA14__TrapRdRspData14__SHIFT', + 'TRAP_RESPONSE_DATA15__TrapRdRspData15_MASK', + 'TRAP_RESPONSE_DATA15__TrapRdRspData15__SHIFT', + 'TRAP_RESPONSE_DATA1__TrapRdRspData1_MASK', + 'TRAP_RESPONSE_DATA1__TrapRdRspData1__SHIFT', + 'TRAP_RESPONSE_DATA2__TrapRdRspData2_MASK', + 'TRAP_RESPONSE_DATA2__TrapRdRspData2__SHIFT', + 'TRAP_RESPONSE_DATA3__TrapRdRspData3_MASK', + 'TRAP_RESPONSE_DATA3__TrapRdRspData3__SHIFT', + 'TRAP_RESPONSE_DATA4__TrapRdRspData4_MASK', + 'TRAP_RESPONSE_DATA4__TrapRdRspData4__SHIFT', + 'TRAP_RESPONSE_DATA5__TrapRdRspData5_MASK', + 'TRAP_RESPONSE_DATA5__TrapRdRspData5__SHIFT', + 'TRAP_RESPONSE_DATA6__TrapRdRspData6_MASK', + 'TRAP_RESPONSE_DATA6__TrapRdRspData6__SHIFT', + 'TRAP_RESPONSE_DATA7__TrapRdRspData7_MASK', + 'TRAP_RESPONSE_DATA7__TrapRdRspData7__SHIFT', + 'TRAP_RESPONSE_DATA8__TrapRdRspData8_MASK', + 'TRAP_RESPONSE_DATA8__TrapRdRspData8__SHIFT', + 'TRAP_RESPONSE_DATA9__TrapRdRspData9_MASK', + 'TRAP_RESPONSE_DATA9__TrapRdRspData9__SHIFT', + 'TRAP_STATUS__TrapNumber_MASK', 'TRAP_STATUS__TrapNumber__SHIFT', + 'TRAP_STATUS__TrapReqValid_MASK', + 'TRAP_STATUS__TrapReqValid__SHIFT', + 'TRAP_STATUS__TrapS2Number_MASK', + 'TRAP_STATUS__TrapS2Number__SHIFT', 'TRAP_STATUS__TrapS2Vld_MASK', + 'TRAP_STATUS__TrapS2Vld__SHIFT', + 'XCC_DOORBELL_FENCE__CP_0_SENT_MASK', + 'XCC_DOORBELL_FENCE__CP_0_SENT__SHIFT', + 'XCC_DOORBELL_FENCE__CP_1_SENT_MASK', + 'XCC_DOORBELL_FENCE__CP_1_SENT__SHIFT', + 'XCC_DOORBELL_FENCE__CP_2_SENT_MASK', + 'XCC_DOORBELL_FENCE__CP_2_SENT__SHIFT', + 'XCC_DOORBELL_FENCE__CP_3_SENT_MASK', + 'XCC_DOORBELL_FENCE__CP_3_SENT__SHIFT', + 'XCC_DOORBELL_FENCE__CP_4_SENT_MASK', + 'XCC_DOORBELL_FENCE__CP_4_SENT__SHIFT', + 'XCC_DOORBELL_FENCE__CP_5_SENT_MASK', + 'XCC_DOORBELL_FENCE__CP_5_SENT__SHIFT', + 'XCC_DOORBELL_FENCE__CP_6_SENT_MASK', + 'XCC_DOORBELL_FENCE__CP_6_SENT__SHIFT', + 'XCC_DOORBELL_FENCE__CP_7_SENT_MASK', + 'XCC_DOORBELL_FENCE__CP_7_SENT__SHIFT', + 'XCC_DOORBELL_FENCE__REMOTE_CLIENT_CLR_PENDING_MASK', + 'XCC_DOORBELL_FENCE__REMOTE_CLIENT_CLR_PENDING__SHIFT', + 'XCC_DOORBELL_FENCE__REMOTE_CLIENT_SENT_MASK', + 'XCC_DOORBELL_FENCE__REMOTE_CLIENT_SENT__SHIFT', + 'XCC_DOORBELL_FENCE__RMOTE_CP_SENT_MASK', + 'XCC_DOORBELL_FENCE__RMOTE_CP_SENT__SHIFT', + 'XCC_DOORBELL_FENCE__SHUB_SLV_MODE_MASK', + 'XCC_DOORBELL_FENCE__SHUB_SLV_MODE__SHIFT', + 'XCC_DOORBELL_FENCE__XCC_0_DOORBELL_FENCE_MASK', + 'XCC_DOORBELL_FENCE__XCC_0_DOORBELL_FENCE__SHIFT', + 'XCC_DOORBELL_FENCE__XCC_1_DOORBELL_FENCE_MASK', + 'XCC_DOORBELL_FENCE__XCC_1_DOORBELL_FENCE__SHIFT', + 'XCC_DOORBELL_FENCE__XCC_2_DOORBELL_FENCE_MASK', + 'XCC_DOORBELL_FENCE__XCC_2_DOORBELL_FENCE__SHIFT', + 'XCC_DOORBELL_FENCE__XCC_3_DOORBELL_FENCE_MASK', + 'XCC_DOORBELL_FENCE__XCC_3_DOORBELL_FENCE__SHIFT', + 'XCC_DOORBELL_FENCE__XCC_4_DOORBELL_FENCE_MASK', + 'XCC_DOORBELL_FENCE__XCC_4_DOORBELL_FENCE__SHIFT', + 'XCC_DOORBELL_FENCE__XCC_5_DOORBELL_FENCE_MASK', + 'XCC_DOORBELL_FENCE__XCC_5_DOORBELL_FENCE__SHIFT', + 'XCC_DOORBELL_FENCE__XCC_6_DOORBELL_FENCE_MASK', + 'XCC_DOORBELL_FENCE__XCC_6_DOORBELL_FENCE__SHIFT', + 'XCC_DOORBELL_FENCE__XCC_7_DOORBELL_FENCE_MASK', + 'XCC_DOORBELL_FENCE__XCC_7_DOORBELL_FENCE__SHIFT', + '_nbio_7_9_0_OFFSET_HEADER', '_nbio_7_9_0_SH_MASK_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID_W', + 'cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_BASE_CLASS', 'cfgBIF_CFG_DEV0_EPF0_BIST', + 'cfgBIF_CFG_DEV0_EPF0_CACHE_LINE', 'cfgBIF_CFG_DEV0_EPF0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_LATENCY', 'cfgBIF_CFG_DEV0_EPF0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_LINK_CAP_16GT', + 'cfgBIF_CFG_DEV0_EPF0_LINK_CAP_32GT', + 'cfgBIF_CFG_DEV0_EPF0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT', + 'cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT', + 'cfgBIF_CFG_DEV0_EPF0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT', + 'cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT', + 'cfgBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT', + 'cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP', + 'cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CAP', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CAP', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_PMI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_PMI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT', + 'cfgBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT', + 'cfgBIF_CFG_DEV0_EPF0_STATUS', 'cfgBIF_CFG_DEV0_EPF0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF0_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF0_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF0_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF0_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF0_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF0_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF1_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF1_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF1_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF1_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF2_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF2_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF2_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF2_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF2_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF2_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF3_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF3_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF3_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF3_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF3_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF3_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF4_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF4_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF4_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF4_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF4_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF4_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF5_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF5_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF5_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF5_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF5_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF5_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF6_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF6_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF6_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF6_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF6_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF6_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF7_BIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF7_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF0_VF7_COMMAND', + 'cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_HEADER', + 'cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF0_VF7_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF0_VF7_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF0_VF7_STATUS', + 'cfgBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID', + 'cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID', + 'cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID_W', + 'cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_2', + 'cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_3', + 'cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_4', + 'cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_5', + 'cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_6', + 'cfgBIF_CFG_DEV0_EPF1_BASE_CLASS', 'cfgBIF_CFG_DEV0_EPF1_BIST', + 'cfgBIF_CFG_DEV0_EPF1_CACHE_LINE', 'cfgBIF_CFG_DEV0_EPF1_CAP_PTR', + 'cfgBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR', + 'cfgBIF_CFG_DEV0_EPF1_COMMAND', 'cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP', + 'cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL2', + 'cfgBIF_CFG_DEV0_EPF1_DEVICE_ID', + 'cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_EPF1_HEADER', + 'cfgBIF_CFG_DEV0_EPF1_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_EPF1_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_EPF1_LATENCY', 'cfgBIF_CFG_DEV0_EPF1_LINK_CAP', + 'cfgBIF_CFG_DEV0_EPF1_LINK_CAP2', + 'cfgBIF_CFG_DEV0_EPF1_LINK_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_EPF1_LINK_STATUS', + 'cfgBIF_CFG_DEV0_EPF1_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_EPF1_MAX_LATENCY', + 'cfgBIF_CFG_DEV0_EPF1_MIN_GRANT', + 'cfgBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_MSIX_PBA', + 'cfgBIF_CFG_DEV0_EPF1_MSIX_TABLE', + 'cfgBIF_CFG_DEV0_EPF1_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF1_MSI_MASK', + 'cfgBIF_CFG_DEV0_EPF1_MSI_MASK_64', + 'cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_EPF1_MSI_PENDING', + 'cfgBIF_CFG_DEV0_EPF1_MSI_PENDING_64', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_CAP', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_EPF1_PMI_CAP', + 'cfgBIF_CFG_DEV0_EPF1_PMI_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL', + 'cfgBIF_CFG_DEV0_EPF1_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_EPF1_REVISION_ID', + 'cfgBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR', + 'cfgBIF_CFG_DEV0_EPF1_STATUS', 'cfgBIF_CFG_DEV0_EPF1_SUB_CLASS', + 'cfgBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST', + 'cfgBIF_CFG_DEV0_EPF1_VENDOR_ID', + 'cfgBIF_CFG_DEV0_RC_BASE_ADDR_1', + 'cfgBIF_CFG_DEV0_RC_BASE_ADDR_2', 'cfgBIF_CFG_DEV0_RC_BASE_CLASS', + 'cfgBIF_CFG_DEV0_RC_BIST', 'cfgBIF_CFG_DEV0_RC_CACHE_LINE', + 'cfgBIF_CFG_DEV0_RC_CAP_PTR', 'cfgBIF_CFG_DEV0_RC_COMMAND', + 'cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP', + 'cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS', + 'cfgBIF_CFG_DEV0_RC_DEVICE_CAP', 'cfgBIF_CFG_DEV0_RC_DEVICE_CAP2', + 'cfgBIF_CFG_DEV0_RC_DEVICE_CNTL', + 'cfgBIF_CFG_DEV0_RC_DEVICE_CNTL2', 'cfgBIF_CFG_DEV0_RC_DEVICE_ID', + 'cfgBIF_CFG_DEV0_RC_DEVICE_STATUS', + 'cfgBIF_CFG_DEV0_RC_DEVICE_STATUS2', + 'cfgBIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL', 'cfgBIF_CFG_DEV0_RC_HEADER', + 'cfgBIF_CFG_DEV0_RC_INTERRUPT_LINE', + 'cfgBIF_CFG_DEV0_RC_INTERRUPT_PIN', + 'cfgBIF_CFG_DEV0_RC_IO_BASE_LIMIT', + 'cfgBIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI', + 'cfgBIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL', + 'cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS', + 'cfgBIF_CFG_DEV0_RC_LATENCY', 'cfgBIF_CFG_DEV0_RC_LINK_CAP', + 'cfgBIF_CFG_DEV0_RC_LINK_CAP2', + 'cfgBIF_CFG_DEV0_RC_LINK_CAP_16GT', + 'cfgBIF_CFG_DEV0_RC_LINK_CAP_32GT', + 'cfgBIF_CFG_DEV0_RC_LINK_CNTL', 'cfgBIF_CFG_DEV0_RC_LINK_CNTL2', + 'cfgBIF_CFG_DEV0_RC_LINK_CNTL_16GT', + 'cfgBIF_CFG_DEV0_RC_LINK_CNTL_32GT', + 'cfgBIF_CFG_DEV0_RC_LINK_STATUS', + 'cfgBIF_CFG_DEV0_RC_LINK_STATUS2', + 'cfgBIF_CFG_DEV0_RC_LINK_STATUS_16GT', + 'cfgBIF_CFG_DEV0_RC_LINK_STATUS_32GT', + 'cfgBIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT', + 'cfgBIF_CFG_DEV0_RC_MARGINING_PORT_CAP', + 'cfgBIF_CFG_DEV0_RC_MARGINING_PORT_STATUS', + 'cfgBIF_CFG_DEV0_RC_MEM_BASE_LIMIT', + 'cfgBIF_CFG_DEV0_RC_MSI_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA', + 'cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI', + 'cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO', + 'cfgBIF_CFG_DEV0_RC_MSI_MSG_CNTL', + 'cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA', + 'cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA_64', + 'cfgBIF_CFG_DEV0_RC_PCIE_ACS_CAP', + 'cfgBIF_CFG_DEV0_RC_PCIE_ACS_CNTL', + 'cfgBIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL', + 'cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC_PCIE_CAP', 'cfgBIF_CFG_DEV0_RC_PCIE_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1', + 'cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2', + 'cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID', + 'cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG0', + 'cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG1', + 'cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG2', + 'cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG3', + 'cfgBIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL', + 'cfgBIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS', + 'cfgBIF_CFG_DEV0_RC_PCIE_LINK_CNTL3', + 'cfgBIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1', + 'cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2', + 'cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL', + 'cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS', + 'cfgBIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD', + 'cfgBIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS', + 'cfgBIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0', + 'cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1', + 'cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2', + 'cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3', + 'cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK', + 'cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY', + 'cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS', + 'cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP', + 'cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL', + 'cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS', + 'cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP', + 'cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL', + 'cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS', + 'cfgBIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1', + 'cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2', + 'cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR', + 'cfgBIF_CFG_DEV0_RC_PMI_CAP', 'cfgBIF_CFG_DEV0_RC_PMI_CAP_LIST', + 'cfgBIF_CFG_DEV0_RC_PMI_STATUS_CNTL', + 'cfgBIF_CFG_DEV0_RC_PREF_BASE_LIMIT', + 'cfgBIF_CFG_DEV0_RC_PREF_BASE_UPPER', + 'cfgBIF_CFG_DEV0_RC_PREF_LIMIT_UPPER', + 'cfgBIF_CFG_DEV0_RC_PROG_INTERFACE', + 'cfgBIF_CFG_DEV0_RC_REVISION_ID', + 'cfgBIF_CFG_DEV0_RC_ROM_BASE_ADDR', 'cfgBIF_CFG_DEV0_RC_ROOT_CAP', + 'cfgBIF_CFG_DEV0_RC_ROOT_CNTL', 'cfgBIF_CFG_DEV0_RC_ROOT_STATUS', + 'cfgBIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT', + 'cfgBIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT', + 'cfgBIF_CFG_DEV0_RC_SECONDARY_STATUS', + 'cfgBIF_CFG_DEV0_RC_SLOT_CAP', 'cfgBIF_CFG_DEV0_RC_SLOT_CAP2', + 'cfgBIF_CFG_DEV0_RC_SLOT_CNTL', 'cfgBIF_CFG_DEV0_RC_SLOT_CNTL2', + 'cfgBIF_CFG_DEV0_RC_SLOT_STATUS', + 'cfgBIF_CFG_DEV0_RC_SLOT_STATUS2', 'cfgBIF_CFG_DEV0_RC_SSID_CAP', + 'cfgBIF_CFG_DEV0_RC_SSID_CAP_LIST', 'cfgBIF_CFG_DEV0_RC_STATUS', + 'cfgBIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY', + 'cfgBIF_CFG_DEV0_RC_SUB_CLASS', 'cfgBIF_CFG_DEV0_RC_VENDOR_ID', + 'cfgIRQ_BRIDGE_CNTL', 'cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC', + 'cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY', 'cfgPCIE_PAGE_REQ_CNTL', + 'cfgPCIE_PAGE_REQ_ENH_CAP_LIST', 'cfgPCIE_PAGE_REQ_STATUS', + 'cfgPCIE_SRIOV_CAP', 'cfgPCIE_SRIOV_CONTROL', + 'cfgPCIE_SRIOV_ENH_CAP_LIST', 'cfgPCIE_SRIOV_FIRST_VF_OFFSET', + 'cfgPCIE_SRIOV_FUNC_DEP_LINK', 'cfgPCIE_SRIOV_INITIAL_VFS', + 'cfgPCIE_SRIOV_NUM_VFS', 'cfgPCIE_SRIOV_STATUS', + 'cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE', + 'cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE', 'cfgPCIE_SRIOV_TOTAL_VFS', + 'cfgPCIE_SRIOV_VF_BASE_ADDR_0', 'cfgPCIE_SRIOV_VF_BASE_ADDR_1', + 'cfgPCIE_SRIOV_VF_BASE_ADDR_2', 'cfgPCIE_SRIOV_VF_BASE_ADDR_3', + 'cfgPCIE_SRIOV_VF_BASE_ADDR_4', 'cfgPCIE_SRIOV_VF_BASE_ADDR_5', + 'cfgPCIE_SRIOV_VF_DEVICE_ID', + 'cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET', + 'cfgPCIE_SRIOV_VF_STRIDE', + 'cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB', + 'cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB', + 'regAID0_ATHUB_VF0_BASE_ADDR', + 'regAID0_ATHUB_VF0_BASE_ADDR_BASE_IDX', + 'regAID0_ATHUB_VF1_BASE_ADDR', + 'regAID0_ATHUB_VF1_BASE_ADDR_BASE_IDX', + 'regAID0_ATHUB_VF2_BASE_ADDR', + 'regAID0_ATHUB_VF2_BASE_ADDR_BASE_IDX', + 'regAID0_ATHUB_VF3_BASE_ADDR', + 'regAID0_ATHUB_VF3_BASE_ADDR_BASE_IDX', + 'regAID0_ATHUB_VF4_BASE_ADDR', + 'regAID0_ATHUB_VF4_BASE_ADDR_BASE_IDX', + 'regAID0_ATHUB_VF5_BASE_ADDR', + 'regAID0_ATHUB_VF5_BASE_ADDR_BASE_IDX', + 'regAID0_ATHUB_VF6_BASE_ADDR', + 'regAID0_ATHUB_VF6_BASE_ADDR_BASE_IDX', + 'regAID0_ATHUB_VF7_BASE_ADDR', + 'regAID0_ATHUB_VF7_BASE_ADDR_BASE_IDX', + 'regAID0_HDP_VF0_BASE_ADDR', 'regAID0_HDP_VF0_BASE_ADDR_BASE_IDX', + 'regAID0_HDP_VF1_BASE_ADDR', 'regAID0_HDP_VF1_BASE_ADDR_BASE_IDX', + 'regAID0_HDP_VF2_BASE_ADDR', 'regAID0_HDP_VF2_BASE_ADDR_BASE_IDX', + 'regAID0_HDP_VF3_BASE_ADDR', 'regAID0_HDP_VF3_BASE_ADDR_BASE_IDX', + 'regAID0_HDP_VF4_BASE_ADDR', 'regAID0_HDP_VF4_BASE_ADDR_BASE_IDX', + 'regAID0_HDP_VF5_BASE_ADDR', 'regAID0_HDP_VF5_BASE_ADDR_BASE_IDX', + 'regAID0_HDP_VF6_BASE_ADDR', 'regAID0_HDP_VF6_BASE_ADDR_BASE_IDX', + 'regAID0_HDP_VF7_BASE_ADDR', 'regAID0_HDP_VF7_BASE_ADDR_BASE_IDX', + 'regAID0_IH_VF0_BASE_ADDR', 'regAID0_IH_VF0_BASE_ADDR_BASE_IDX', + 'regAID0_IH_VF1_BASE_ADDR', 'regAID0_IH_VF1_BASE_ADDR_BASE_IDX', + 'regAID0_IH_VF2_BASE_ADDR', 'regAID0_IH_VF2_BASE_ADDR_BASE_IDX', + 'regAID0_IH_VF3_BASE_ADDR', 'regAID0_IH_VF3_BASE_ADDR_BASE_IDX', + 'regAID0_IH_VF4_BASE_ADDR', 'regAID0_IH_VF4_BASE_ADDR_BASE_IDX', + 'regAID0_IH_VF5_BASE_ADDR', 'regAID0_IH_VF5_BASE_ADDR_BASE_IDX', + 'regAID0_IH_VF6_BASE_ADDR', 'regAID0_IH_VF6_BASE_ADDR_BASE_IDX', + 'regAID0_IH_VF7_BASE_ADDR', 'regAID0_IH_VF7_BASE_ADDR_BASE_IDX', + 'regAID0_NBIF_VF0_BASE_ADDR', + 'regAID0_NBIF_VF0_BASE_ADDR_BASE_IDX', + 'regAID0_NBIF_VF1_BASE_ADDR', + 'regAID0_NBIF_VF1_BASE_ADDR_BASE_IDX', + 'regAID0_NBIF_VF2_BASE_ADDR', + 'regAID0_NBIF_VF2_BASE_ADDR_BASE_IDX', + 'regAID0_NBIF_VF3_BASE_ADDR', + 'regAID0_NBIF_VF3_BASE_ADDR_BASE_IDX', + 'regAID0_NBIF_VF4_BASE_ADDR', + 'regAID0_NBIF_VF4_BASE_ADDR_BASE_IDX', + 'regAID0_NBIF_VF5_BASE_ADDR', + 'regAID0_NBIF_VF5_BASE_ADDR_BASE_IDX', + 'regAID0_NBIF_VF6_BASE_ADDR', + 'regAID0_NBIF_VF6_BASE_ADDR_BASE_IDX', + 'regAID0_NBIF_VF7_BASE_ADDR', + 'regAID0_NBIF_VF7_BASE_ADDR_BASE_IDX', 'regAID0_PF_BASE_ADDR', + 'regAID0_PF_BASE_ADDR_BASE_IDX', 'regAID0_VF0_BASE_ADDR', + 'regAID0_VF0_BASE_ADDR_BASE_IDX', 'regAID0_VF1_BASE_ADDR', + 'regAID0_VF1_BASE_ADDR_BASE_IDX', 'regAID0_VF2_BASE_ADDR', + 'regAID0_VF2_BASE_ADDR_BASE_IDX', 'regAID0_VF3_BASE_ADDR', + 'regAID0_VF3_BASE_ADDR_BASE_IDX', 'regAID0_VF4_BASE_ADDR', + 'regAID0_VF4_BASE_ADDR_BASE_IDX', 'regAID0_VF5_BASE_ADDR', + 'regAID0_VF5_BASE_ADDR_BASE_IDX', 'regAID0_VF6_BASE_ADDR', + 'regAID0_VF6_BASE_ADDR_BASE_IDX', 'regAID0_VF7_BASE_ADDR', + 'regAID0_VF7_BASE_ADDR_BASE_IDX', 'regAID0_XCC0_PF_BASE_ADDR', + 'regAID0_XCC0_PF_BASE_ADDR_BASE_IDX', + 'regAID0_XCC0_VF0_BASE_ADDR', + 'regAID0_XCC0_VF0_BASE_ADDR_BASE_IDX', + 'regAID0_XCC0_VF1_BASE_ADDR', + 'regAID0_XCC0_VF1_BASE_ADDR_BASE_IDX', + 'regAID0_XCC0_VF2_BASE_ADDR', + 'regAID0_XCC0_VF2_BASE_ADDR_BASE_IDX', + 'regAID0_XCC0_VF3_BASE_ADDR', + 'regAID0_XCC0_VF3_BASE_ADDR_BASE_IDX', + 'regAID0_XCC0_VF4_BASE_ADDR', + 'regAID0_XCC0_VF4_BASE_ADDR_BASE_IDX', + 'regAID0_XCC0_VF5_BASE_ADDR', + 'regAID0_XCC0_VF5_BASE_ADDR_BASE_IDX', + 'regAID0_XCC0_VF6_BASE_ADDR', + 'regAID0_XCC0_VF6_BASE_ADDR_BASE_IDX', + 'regAID0_XCC0_VF7_BASE_ADDR', + 'regAID0_XCC0_VF7_BASE_ADDR_BASE_IDX', + 'regAID0_XCC1_PF_BASE_ADDR', 'regAID0_XCC1_PF_BASE_ADDR_BASE_IDX', + 'regAID0_XCC1_VF0_BASE_ADDR', + 'regAID0_XCC1_VF0_BASE_ADDR_BASE_IDX', + 'regAID0_XCC1_VF1_BASE_ADDR', + 'regAID0_XCC1_VF1_BASE_ADDR_BASE_IDX', + 'regAID0_XCC1_VF2_BASE_ADDR', + 'regAID0_XCC1_VF2_BASE_ADDR_BASE_IDX', + 'regAID0_XCC1_VF3_BASE_ADDR', + 'regAID0_XCC1_VF3_BASE_ADDR_BASE_IDX', + 'regAID0_XCC1_VF4_BASE_ADDR', + 'regAID0_XCC1_VF4_BASE_ADDR_BASE_IDX', + 'regAID0_XCC1_VF5_BASE_ADDR', + 'regAID0_XCC1_VF5_BASE_ADDR_BASE_IDX', + 'regAID0_XCC1_VF6_BASE_ADDR', + 'regAID0_XCC1_VF6_BASE_ADDR_BASE_IDX', + 'regAID0_XCC1_VF7_BASE_ADDR', + 'regAID0_XCC1_VF7_BASE_ADDR_BASE_IDX', 'regAID1_PF_BASE_ADDR', + 'regAID1_PF_BASE_ADDR_BASE_IDX', 'regAID1_VF0_BASE_ADDR', + 'regAID1_VF0_BASE_ADDR_BASE_IDX', 'regAID1_VF1_BASE_ADDR', + 'regAID1_VF1_BASE_ADDR_BASE_IDX', 'regAID1_VF2_BASE_ADDR', + 'regAID1_VF2_BASE_ADDR_BASE_IDX', 'regAID1_VF3_BASE_ADDR', + 'regAID1_VF3_BASE_ADDR_BASE_IDX', 'regAID1_VF4_BASE_ADDR', + 'regAID1_VF4_BASE_ADDR_BASE_IDX', 'regAID1_VF5_BASE_ADDR', + 'regAID1_VF5_BASE_ADDR_BASE_IDX', 'regAID1_VF6_BASE_ADDR', + 'regAID1_VF6_BASE_ADDR_BASE_IDX', 'regAID1_VF7_BASE_ADDR', + 'regAID1_VF7_BASE_ADDR_BASE_IDX', 'regAID1_XCC0_PF_BASE_ADDR', + 'regAID1_XCC0_PF_BASE_ADDR_BASE_IDX', + 'regAID1_XCC0_VF0_BASE_ADDR', + 'regAID1_XCC0_VF0_BASE_ADDR_BASE_IDX', + 'regAID1_XCC0_VF1_BASE_ADDR', + 'regAID1_XCC0_VF1_BASE_ADDR_BASE_IDX', + 'regAID1_XCC0_VF2_BASE_ADDR', + 'regAID1_XCC0_VF2_BASE_ADDR_BASE_IDX', + 'regAID1_XCC0_VF3_BASE_ADDR', + 'regAID1_XCC0_VF3_BASE_ADDR_BASE_IDX', + 'regAID1_XCC0_VF4_BASE_ADDR', + 'regAID1_XCC0_VF4_BASE_ADDR_BASE_IDX', + 'regAID1_XCC0_VF5_BASE_ADDR', + 'regAID1_XCC0_VF5_BASE_ADDR_BASE_IDX', + 'regAID1_XCC0_VF6_BASE_ADDR', + 'regAID1_XCC0_VF6_BASE_ADDR_BASE_IDX', + 'regAID1_XCC0_VF7_BASE_ADDR', + 'regAID1_XCC0_VF7_BASE_ADDR_BASE_IDX', + 'regAID1_XCC1_PF_BASE_ADDR', 'regAID1_XCC1_PF_BASE_ADDR_BASE_IDX', + 'regAID1_XCC1_VF0_BASE_ADDR', + 'regAID1_XCC1_VF0_BASE_ADDR_BASE_IDX', + 'regAID1_XCC1_VF1_BASE_ADDR', + 'regAID1_XCC1_VF1_BASE_ADDR_BASE_IDX', + 'regAID1_XCC1_VF2_BASE_ADDR', + 'regAID1_XCC1_VF2_BASE_ADDR_BASE_IDX', + 'regAID1_XCC1_VF3_BASE_ADDR', + 'regAID1_XCC1_VF3_BASE_ADDR_BASE_IDX', + 'regAID1_XCC1_VF4_BASE_ADDR', + 'regAID1_XCC1_VF4_BASE_ADDR_BASE_IDX', + 'regAID1_XCC1_VF5_BASE_ADDR', + 'regAID1_XCC1_VF5_BASE_ADDR_BASE_IDX', + 'regAID1_XCC1_VF6_BASE_ADDR', + 'regAID1_XCC1_VF6_BASE_ADDR_BASE_IDX', + 'regAID1_XCC1_VF7_BASE_ADDR', + 'regAID1_XCC1_VF7_BASE_ADDR_BASE_IDX', 'regAID2_PF_BASE_ADDR', + 'regAID2_PF_BASE_ADDR_BASE_IDX', 'regAID2_VF0_BASE_ADDR', + 'regAID2_VF0_BASE_ADDR_BASE_IDX', 'regAID2_VF1_BASE_ADDR', + 'regAID2_VF1_BASE_ADDR_BASE_IDX', 'regAID2_VF2_BASE_ADDR', + 'regAID2_VF2_BASE_ADDR_BASE_IDX', 'regAID2_VF3_BASE_ADDR', + 'regAID2_VF3_BASE_ADDR_BASE_IDX', 'regAID2_VF4_BASE_ADDR', + 'regAID2_VF4_BASE_ADDR_BASE_IDX', 'regAID2_VF5_BASE_ADDR', + 'regAID2_VF5_BASE_ADDR_BASE_IDX', 'regAID2_VF6_BASE_ADDR', + 'regAID2_VF6_BASE_ADDR_BASE_IDX', 'regAID2_VF7_BASE_ADDR', + 'regAID2_VF7_BASE_ADDR_BASE_IDX', 'regAID2_XCC0_PF_BASE_ADDR', + 'regAID2_XCC0_PF_BASE_ADDR_BASE_IDX', + 'regAID2_XCC0_VF0_BASE_ADDR', + 'regAID2_XCC0_VF0_BASE_ADDR_BASE_IDX', + 'regAID2_XCC0_VF1_BASE_ADDR', + 'regAID2_XCC0_VF1_BASE_ADDR_BASE_IDX', + 'regAID2_XCC0_VF2_BASE_ADDR', + 'regAID2_XCC0_VF2_BASE_ADDR_BASE_IDX', + 'regAID2_XCC0_VF3_BASE_ADDR', + 'regAID2_XCC0_VF3_BASE_ADDR_BASE_IDX', + 'regAID2_XCC0_VF4_BASE_ADDR', + 'regAID2_XCC0_VF4_BASE_ADDR_BASE_IDX', + 'regAID2_XCC0_VF5_BASE_ADDR', + 'regAID2_XCC0_VF5_BASE_ADDR_BASE_IDX', + 'regAID2_XCC0_VF6_BASE_ADDR', + 'regAID2_XCC0_VF6_BASE_ADDR_BASE_IDX', + 'regAID2_XCC0_VF7_BASE_ADDR', + 'regAID2_XCC0_VF7_BASE_ADDR_BASE_IDX', + 'regAID2_XCC1_PF_BASE_ADDR', 'regAID2_XCC1_PF_BASE_ADDR_BASE_IDX', + 'regAID2_XCC1_VF0_BASE_ADDR', + 'regAID2_XCC1_VF0_BASE_ADDR_BASE_IDX', + 'regAID2_XCC1_VF1_BASE_ADDR', + 'regAID2_XCC1_VF1_BASE_ADDR_BASE_IDX', + 'regAID2_XCC1_VF2_BASE_ADDR', + 'regAID2_XCC1_VF2_BASE_ADDR_BASE_IDX', + 'regAID2_XCC1_VF3_BASE_ADDR', + 'regAID2_XCC1_VF3_BASE_ADDR_BASE_IDX', + 'regAID2_XCC1_VF4_BASE_ADDR', + 'regAID2_XCC1_VF4_BASE_ADDR_BASE_IDX', + 'regAID2_XCC1_VF5_BASE_ADDR', + 'regAID2_XCC1_VF5_BASE_ADDR_BASE_IDX', + 'regAID2_XCC1_VF6_BASE_ADDR', + 'regAID2_XCC1_VF6_BASE_ADDR_BASE_IDX', + 'regAID2_XCC1_VF7_BASE_ADDR', + 'regAID2_XCC1_VF7_BASE_ADDR_BASE_IDX', 'regAID3_PF_BASE_ADDR', + 'regAID3_PF_BASE_ADDR_BASE_IDX', 'regAID3_VF0_BASE_ADDR', + 'regAID3_VF0_BASE_ADDR_BASE_IDX', 'regAID3_VF1_BASE_ADDR', + 'regAID3_VF1_BASE_ADDR_BASE_IDX', 'regAID3_VF2_BASE_ADDR', + 'regAID3_VF2_BASE_ADDR_BASE_IDX', 'regAID3_VF3_BASE_ADDR', + 'regAID3_VF3_BASE_ADDR_BASE_IDX', 'regAID3_VF4_BASE_ADDR', + 'regAID3_VF4_BASE_ADDR_BASE_IDX', 'regAID3_VF5_BASE_ADDR', + 'regAID3_VF5_BASE_ADDR_BASE_IDX', 'regAID3_VF6_BASE_ADDR', + 'regAID3_VF6_BASE_ADDR_BASE_IDX', 'regAID3_VF7_BASE_ADDR', + 'regAID3_VF7_BASE_ADDR_BASE_IDX', 'regAID3_XCC0_PF_BASE_ADDR', + 'regAID3_XCC0_PF_BASE_ADDR_BASE_IDX', + 'regAID3_XCC0_VF0_BASE_ADDR', + 'regAID3_XCC0_VF0_BASE_ADDR_BASE_IDX', + 'regAID3_XCC0_VF1_BASE_ADDR', + 'regAID3_XCC0_VF1_BASE_ADDR_BASE_IDX', + 'regAID3_XCC0_VF2_BASE_ADDR', + 'regAID3_XCC0_VF2_BASE_ADDR_BASE_IDX', + 'regAID3_XCC0_VF3_BASE_ADDR', + 'regAID3_XCC0_VF3_BASE_ADDR_BASE_IDX', + 'regAID3_XCC0_VF4_BASE_ADDR', + 'regAID3_XCC0_VF4_BASE_ADDR_BASE_IDX', + 'regAID3_XCC0_VF5_BASE_ADDR', + 'regAID3_XCC0_VF5_BASE_ADDR_BASE_IDX', + 'regAID3_XCC0_VF6_BASE_ADDR', + 'regAID3_XCC0_VF6_BASE_ADDR_BASE_IDX', + 'regAID3_XCC0_VF7_BASE_ADDR', + 'regAID3_XCC0_VF7_BASE_ADDR_BASE_IDX', + 'regAID3_XCC1_PF_BASE_ADDR', 'regAID3_XCC1_PF_BASE_ADDR_BASE_IDX', + 'regAID3_XCC1_VF0_BASE_ADDR', + 'regAID3_XCC1_VF0_BASE_ADDR_BASE_IDX', + 'regAID3_XCC1_VF1_BASE_ADDR', + 'regAID3_XCC1_VF1_BASE_ADDR_BASE_IDX', + 'regAID3_XCC1_VF2_BASE_ADDR', + 'regAID3_XCC1_VF2_BASE_ADDR_BASE_IDX', + 'regAID3_XCC1_VF3_BASE_ADDR', + 'regAID3_XCC1_VF3_BASE_ADDR_BASE_IDX', + 'regAID3_XCC1_VF4_BASE_ADDR', + 'regAID3_XCC1_VF4_BASE_ADDR_BASE_IDX', + 'regAID3_XCC1_VF5_BASE_ADDR', + 'regAID3_XCC1_VF5_BASE_ADDR_BASE_IDX', + 'regAID3_XCC1_VF6_BASE_ADDR', + 'regAID3_XCC1_VF6_BASE_ADDR_BASE_IDX', + 'regAID3_XCC1_VF7_BASE_ADDR', + 'regAID3_XCC1_VF7_BASE_ADDR_BASE_IDX', 'regAPML_CONTROL', + 'regAPML_CONTROL_BASE_IDX', 'regAPML_STATUS', + 'regAPML_STATUS_BASE_IDX', 'regAPML_SW_STATUS', + 'regAPML_SW_STATUS_BASE_IDX', 'regAPML_TRIGGER', + 'regAPML_TRIGGER_BASE_IDX', 'regBIFC_A2S_CNTL_CL0', + 'regBIFC_A2S_CNTL_CL0_BASE_IDX', 'regBIFC_A2S_CNTL_SW0', + 'regBIFC_A2S_CNTL_SW0_BASE_IDX', 'regBIFC_A2S_MISC_CNTL', + 'regBIFC_A2S_MISC_CNTL_BASE_IDX', 'regBIFC_A2S_SDP_PORT_CTRL', + 'regBIFC_A2S_SDP_PORT_CTRL_BASE_IDX', 'regBIFC_A2S_TAG_ALLOC_0', + 'regBIFC_A2S_TAG_ALLOC_0_BASE_IDX', 'regBIFC_A2S_TAG_ALLOC_1', + 'regBIFC_A2S_TAG_ALLOC_1_BASE_IDX', 'regBIFC_ATHUB_ACT_CNTL', + 'regBIFC_ATHUB_ACT_CNTL_BASE_IDX', 'regBIFC_BME_ERR_LOG_HB', + 'regBIFC_BME_ERR_LOG_HB_BASE_IDX', 'regBIFC_BME_ERR_LOG_LB', + 'regBIFC_BME_ERR_LOG_LB_BASE_IDX', 'regBIFC_DMA_ATTR_CNTL2_DEV0', + 'regBIFC_DMA_ATTR_CNTL2_DEV0_BASE_IDX', + 'regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1', + 'regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_BASE_IDX', + 'regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3', + 'regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_BASE_IDX', + 'regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5', + 'regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_BASE_IDX', + 'regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7', + 'regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_BASE_IDX', + 'regBIFC_DOORBELL_ACCESS_EN_PF', + 'regBIFC_DOORBELL_ACCESS_EN_PF_BASE_IDX', + 'regBIFC_DOORBELL_ACCESS_EN_VF0', + 'regBIFC_DOORBELL_ACCESS_EN_VF0_BASE_IDX', + 'regBIFC_DOORBELL_ACCESS_EN_VF1', + 'regBIFC_DOORBELL_ACCESS_EN_VF1_BASE_IDX', + 'regBIFC_DOORBELL_ACCESS_EN_VF2', + 'regBIFC_DOORBELL_ACCESS_EN_VF2_BASE_IDX', + 'regBIFC_DOORBELL_ACCESS_EN_VF3', + 'regBIFC_DOORBELL_ACCESS_EN_VF3_BASE_IDX', + 'regBIFC_DOORBELL_ACCESS_EN_VF4', + 'regBIFC_DOORBELL_ACCESS_EN_VF4_BASE_IDX', + 'regBIFC_DOORBELL_ACCESS_EN_VF5', + 'regBIFC_DOORBELL_ACCESS_EN_VF5_BASE_IDX', + 'regBIFC_DOORBELL_ACCESS_EN_VF6', + 'regBIFC_DOORBELL_ACCESS_EN_VF6_BASE_IDX', + 'regBIFC_DOORBELL_ACCESS_EN_VF7', + 'regBIFC_DOORBELL_ACCESS_EN_VF7_BASE_IDX', + 'regBIFC_EARLY_WAKEUP_CNTL', 'regBIFC_EARLY_WAKEUP_CNTL_BASE_IDX', + 'regBIFC_GFX_INT_MONITOR_MASK', + 'regBIFC_GFX_INT_MONITOR_MASK_BASE_IDX', + 'regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC', + 'regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX', + 'regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC', + 'regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX', 'regBIFC_GSI_CNTL', + 'regBIFC_GSI_CNTL_BASE_IDX', + 'regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC', + 'regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC_BASE_IDX', + 'regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC', + 'regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC_BASE_IDX', + 'regBIFC_HSTARB_CNTL', 'regBIFC_HSTARB_CNTL_BASE_IDX', + 'regBIFC_LC_TIMER_CTRL', 'regBIFC_LC_TIMER_CTRL_BASE_IDX', + 'regBIFC_MISC_CTRL0', 'regBIFC_MISC_CTRL0_BASE_IDX', + 'regBIFC_MISC_CTRL1', 'regBIFC_MISC_CTRL1_BASE_IDX', + 'regBIFC_PASID_CHECK_DIS', 'regBIFC_PASID_CHECK_DIS_BASE_IDX', + 'regBIFC_PASID_STS', 'regBIFC_PASID_STS_BASE_IDX', + 'regBIFC_PCIEFUNC_CNTL', 'regBIFC_PCIEFUNC_CNTL_BASE_IDX', + 'regBIFC_PERF_CNTL_0', 'regBIFC_PERF_CNTL_0_BASE_IDX', + 'regBIFC_PERF_CNTL_1', 'regBIFC_PERF_CNTL_1_BASE_IDX', + 'regBIFC_PERF_CNT_DMA_RD_H16BIT', + 'regBIFC_PERF_CNT_DMA_RD_H16BIT_BASE_IDX', + 'regBIFC_PERF_CNT_DMA_RD_L32BIT', + 'regBIFC_PERF_CNT_DMA_RD_L32BIT_BASE_IDX', + 'regBIFC_PERF_CNT_DMA_WR_H16BIT', + 'regBIFC_PERF_CNT_DMA_WR_H16BIT_BASE_IDX', + 'regBIFC_PERF_CNT_DMA_WR_L32BIT', + 'regBIFC_PERF_CNT_DMA_WR_L32BIT_BASE_IDX', + 'regBIFC_PERF_CNT_MMIO_RD_H16BIT', + 'regBIFC_PERF_CNT_MMIO_RD_H16BIT_BASE_IDX', + 'regBIFC_PERF_CNT_MMIO_RD_L32BIT', + 'regBIFC_PERF_CNT_MMIO_RD_L32BIT_BASE_IDX', + 'regBIFC_PERF_CNT_MMIO_WR_H16BIT', + 'regBIFC_PERF_CNT_MMIO_WR_H16BIT_BASE_IDX', + 'regBIFC_PERF_CNT_MMIO_WR_L32BIT', + 'regBIFC_PERF_CNT_MMIO_WR_L32BIT_BASE_IDX', + 'regBIFC_RCCBIH_BME_ERR_LOG0', + 'regBIFC_RCCBIH_BME_ERR_LOG0_BASE_IDX', 'regBIFC_SDP_CNTL_0', + 'regBIFC_SDP_CNTL_0_BASE_IDX', 'regBIFC_SDP_CNTL_1', + 'regBIFC_SDP_CNTL_1_BASE_IDX', 'regBIFC_SDP_CNTL_2', + 'regBIFC_SDP_CNTL_2_BASE_IDX', 'regBIFC_THT_CNTL', + 'regBIFC_THT_CNTL_BASE_IDX', 'regBIF_ATOMIC_ERR_LOG_DEV0_F0', + 'regBIF_ATOMIC_ERR_LOG_DEV0_F0_BASE_IDX', + 'regBIF_ATOMIC_ERR_LOG_DEV0_F1', + 'regBIF_ATOMIC_ERR_LOG_DEV0_F1_BASE_IDX', 'regBIF_BX0_BACO_CNTL', + 'regBIF_BX0_BACO_CNTL_BASE_IDX', 'regBIF_BX0_BIF_BACO_EXIT_TIME0', + 'regBIF_BX0_BIF_BACO_EXIT_TIME0_BASE_IDX', + 'regBIF_BX0_BIF_BACO_EXIT_TIMER1', + 'regBIF_BX0_BIF_BACO_EXIT_TIMER1_BASE_IDX', + 'regBIF_BX0_BIF_BACO_EXIT_TIMER2', + 'regBIF_BX0_BIF_BACO_EXIT_TIMER2_BASE_IDX', + 'regBIF_BX0_BIF_BACO_EXIT_TIMER3', + 'regBIF_BX0_BIF_BACO_EXIT_TIMER3_BASE_IDX', + 'regBIF_BX0_BIF_BACO_EXIT_TIMER4', + 'regBIF_BX0_BIF_BACO_EXIT_TIMER4_BASE_IDX', + 'regBIF_BX0_BIF_CLKREQB_PAD_CNTL', + 'regBIF_BX0_BIF_CLKREQB_PAD_CNTL_BASE_IDX', + 'regBIF_BX0_BIF_DOORBELL_CNTL', + 'regBIF_BX0_BIF_DOORBELL_CNTL_BASE_IDX', + 'regBIF_BX0_BIF_DOORBELL_INT_CNTL', + 'regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX', + 'regBIF_BX0_BIF_FB_EN', 'regBIF_BX0_BIF_FB_EN_BASE_IDX', + 'regBIF_BX0_BIF_FEATURES_CONTROL_MISC', + 'regBIF_BX0_BIF_FEATURES_CONTROL_MISC_BASE_IDX', + 'regBIF_BX0_BIF_INTR_CNTL', 'regBIF_BX0_BIF_INTR_CNTL_BASE_IDX', + 'regBIF_BX0_BIF_MM_INDACCESS_CNTL', + 'regBIF_BX0_BIF_MM_INDACCESS_CNTL_BASE_IDX', + 'regBIF_BX0_BIF_MP1_INTR_CTRL', + 'regBIF_BX0_BIF_MP1_INTR_CTRL_BASE_IDX', + 'regBIF_BX0_BIF_MST_TRANS_PENDING_VF', + 'regBIF_BX0_BIF_MST_TRANS_PENDING_VF_BASE_IDX', + 'regBIF_BX0_BIF_PERSTB_PAD_CNTL', + 'regBIF_BX0_BIF_PERSTB_PAD_CNTL_BASE_IDX', + 'regBIF_BX0_BIF_PWRBRK_PAD_CNTL', + 'regBIF_BX0_BIF_PWRBRK_PAD_CNTL_BASE_IDX', + 'regBIF_BX0_BIF_PX_EN_PAD_CNTL', + 'regBIF_BX0_BIF_PX_EN_PAD_CNTL_BASE_IDX', + 'regBIF_BX0_BIF_RB_BASE', 'regBIF_BX0_BIF_RB_BASE_BASE_IDX', + 'regBIF_BX0_BIF_RB_CNTL', 'regBIF_BX0_BIF_RB_CNTL_BASE_IDX', + 'regBIF_BX0_BIF_RB_RPTR', 'regBIF_BX0_BIF_RB_RPTR_BASE_IDX', + 'regBIF_BX0_BIF_RB_WPTR', 'regBIF_BX0_BIF_RB_WPTR_ADDR_HI', + 'regBIF_BX0_BIF_RB_WPTR_ADDR_HI_BASE_IDX', + 'regBIF_BX0_BIF_RB_WPTR_ADDR_LO', + 'regBIF_BX0_BIF_RB_WPTR_ADDR_LO_BASE_IDX', + 'regBIF_BX0_BIF_RB_WPTR_BASE_IDX', + 'regBIF_BX0_BIF_REFPADKIN_PAD_CNTL', + 'regBIF_BX0_BIF_REFPADKIN_PAD_CNTL_BASE_IDX', + 'regBIF_BX0_BIF_RLC_INTR_CNTL', + 'regBIF_BX0_BIF_RLC_INTR_CNTL_BASE_IDX', + 'regBIF_BX0_BIF_SCRATCH0', 'regBIF_BX0_BIF_SCRATCH0_BASE_IDX', + 'regBIF_BX0_BIF_SCRATCH1', 'regBIF_BX0_BIF_SCRATCH1_BASE_IDX', + 'regBIF_BX0_BIF_SLV_TRANS_PENDING_VF', + 'regBIF_BX0_BIF_SLV_TRANS_PENDING_VF_BASE_IDX', + 'regBIF_BX0_BIF_UVD_INTR_CNTL', + 'regBIF_BX0_BIF_UVD_INTR_CNTL_BASE_IDX', + 'regBIF_BX0_BIF_VCE_INTR_CNTL', + 'regBIF_BX0_BIF_VCE_INTR_CNTL_BASE_IDX', + 'regBIF_BX0_BIOS_SCRATCH_0', 'regBIF_BX0_BIOS_SCRATCH_0_BASE_IDX', + 'regBIF_BX0_BIOS_SCRATCH_1', 'regBIF_BX0_BIOS_SCRATCH_10', + 'regBIF_BX0_BIOS_SCRATCH_10_BASE_IDX', + 'regBIF_BX0_BIOS_SCRATCH_11', + 'regBIF_BX0_BIOS_SCRATCH_11_BASE_IDX', + 'regBIF_BX0_BIOS_SCRATCH_12', + 'regBIF_BX0_BIOS_SCRATCH_12_BASE_IDX', + 'regBIF_BX0_BIOS_SCRATCH_13', + 'regBIF_BX0_BIOS_SCRATCH_13_BASE_IDX', + 'regBIF_BX0_BIOS_SCRATCH_14', + 'regBIF_BX0_BIOS_SCRATCH_14_BASE_IDX', + 'regBIF_BX0_BIOS_SCRATCH_15', + 'regBIF_BX0_BIOS_SCRATCH_15_BASE_IDX', + 'regBIF_BX0_BIOS_SCRATCH_1_BASE_IDX', 'regBIF_BX0_BIOS_SCRATCH_2', + 'regBIF_BX0_BIOS_SCRATCH_2_BASE_IDX', 'regBIF_BX0_BIOS_SCRATCH_3', + 'regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX', 'regBIF_BX0_BIOS_SCRATCH_4', + 'regBIF_BX0_BIOS_SCRATCH_4_BASE_IDX', 'regBIF_BX0_BIOS_SCRATCH_5', + 'regBIF_BX0_BIOS_SCRATCH_5_BASE_IDX', 'regBIF_BX0_BIOS_SCRATCH_6', + 'regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX', 'regBIF_BX0_BIOS_SCRATCH_7', + 'regBIF_BX0_BIOS_SCRATCH_7_BASE_IDX', 'regBIF_BX0_BIOS_SCRATCH_8', + 'regBIF_BX0_BIOS_SCRATCH_8_BASE_IDX', 'regBIF_BX0_BIOS_SCRATCH_9', + 'regBIF_BX0_BIOS_SCRATCH_9_BASE_IDX', 'regBIF_BX0_BUS_CNTL', + 'regBIF_BX0_BUS_CNTL_BASE_IDX', 'regBIF_BX0_BX_RESET_CNTL', + 'regBIF_BX0_BX_RESET_CNTL_BASE_IDX', 'regBIF_BX0_BX_RESET_EN', + 'regBIF_BX0_BX_RESET_EN_BASE_IDX', + 'regBIF_BX0_CC_BIF_BX_PINSTRAP0', + 'regBIF_BX0_CC_BIF_BX_PINSTRAP0_BASE_IDX', + 'regBIF_BX0_CC_BIF_BX_STRAP0', + 'regBIF_BX0_CC_BIF_BX_STRAP0_BASE_IDX', + 'regBIF_BX0_CLKREQB_PAD_CNTL', + 'regBIF_BX0_CLKREQB_PAD_CNTL_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_0', + 'regBIF_BX0_DRIVER_SCRATCH_0_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_1', 'regBIF_BX0_DRIVER_SCRATCH_10', + 'regBIF_BX0_DRIVER_SCRATCH_10_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_11', + 'regBIF_BX0_DRIVER_SCRATCH_11_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_12', + 'regBIF_BX0_DRIVER_SCRATCH_12_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_13', + 'regBIF_BX0_DRIVER_SCRATCH_13_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_14', + 'regBIF_BX0_DRIVER_SCRATCH_14_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_15', + 'regBIF_BX0_DRIVER_SCRATCH_15_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_1_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_2', + 'regBIF_BX0_DRIVER_SCRATCH_2_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_3', + 'regBIF_BX0_DRIVER_SCRATCH_3_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_4', + 'regBIF_BX0_DRIVER_SCRATCH_4_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_5', + 'regBIF_BX0_DRIVER_SCRATCH_5_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_6', + 'regBIF_BX0_DRIVER_SCRATCH_6_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_7', + 'regBIF_BX0_DRIVER_SCRATCH_7_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_8', + 'regBIF_BX0_DRIVER_SCRATCH_8_BASE_IDX', + 'regBIF_BX0_DRIVER_SCRATCH_9', + 'regBIF_BX0_DRIVER_SCRATCH_9_BASE_IDX', 'regBIF_BX0_FW_SCRATCH_0', + 'regBIF_BX0_FW_SCRATCH_0_BASE_IDX', 'regBIF_BX0_FW_SCRATCH_1', + 'regBIF_BX0_FW_SCRATCH_10', 'regBIF_BX0_FW_SCRATCH_10_BASE_IDX', + 'regBIF_BX0_FW_SCRATCH_11', 'regBIF_BX0_FW_SCRATCH_11_BASE_IDX', + 'regBIF_BX0_FW_SCRATCH_12', 'regBIF_BX0_FW_SCRATCH_12_BASE_IDX', + 'regBIF_BX0_FW_SCRATCH_13', 'regBIF_BX0_FW_SCRATCH_13_BASE_IDX', + 'regBIF_BX0_FW_SCRATCH_14', 'regBIF_BX0_FW_SCRATCH_14_BASE_IDX', + 'regBIF_BX0_FW_SCRATCH_15', 'regBIF_BX0_FW_SCRATCH_15_BASE_IDX', + 'regBIF_BX0_FW_SCRATCH_1_BASE_IDX', 'regBIF_BX0_FW_SCRATCH_2', + 'regBIF_BX0_FW_SCRATCH_2_BASE_IDX', 'regBIF_BX0_FW_SCRATCH_3', + 'regBIF_BX0_FW_SCRATCH_3_BASE_IDX', 'regBIF_BX0_FW_SCRATCH_4', + 'regBIF_BX0_FW_SCRATCH_4_BASE_IDX', 'regBIF_BX0_FW_SCRATCH_5', + 'regBIF_BX0_FW_SCRATCH_5_BASE_IDX', 'regBIF_BX0_FW_SCRATCH_6', + 'regBIF_BX0_FW_SCRATCH_6_BASE_IDX', 'regBIF_BX0_FW_SCRATCH_7', + 'regBIF_BX0_FW_SCRATCH_7_BASE_IDX', 'regBIF_BX0_FW_SCRATCH_8', + 'regBIF_BX0_FW_SCRATCH_8_BASE_IDX', 'regBIF_BX0_FW_SCRATCH_9', + 'regBIF_BX0_FW_SCRATCH_9_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR0', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR0_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR1', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR1_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR2', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR2_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR3', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR3_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR4', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR4_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR5', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR5_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR6', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR6_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR7', + 'regBIF_BX0_GFX_MMIOREG_CAM_ADDR7_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_CNTL', + 'regBIF_BX0_GFX_MMIOREG_CAM_CNTL_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL', + 'regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL', + 'regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7', + 'regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX', + 'regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL', + 'regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX', + 'regBIF_BX0_HDP_ATOMIC_CONTROL_MISC', + 'regBIF_BX0_HDP_ATOMIC_CONTROL_MISC_BASE_IDX', + 'regBIF_BX0_INTERRUPT_CNTL', 'regBIF_BX0_INTERRUPT_CNTL2', + 'regBIF_BX0_INTERRUPT_CNTL2_BASE_IDX', + 'regBIF_BX0_INTERRUPT_CNTL_BASE_IDX', 'regBIF_BX0_MAILBOX_INDEX', + 'regBIF_BX0_MAILBOX_INDEX_BASE_IDX', 'regBIF_BX0_MEM_TYPE_CNTL', + 'regBIF_BX0_MEM_TYPE_CNTL_BASE_IDX', 'regBIF_BX0_MM_CFGREGS_CNTL', + 'regBIF_BX0_MM_CFGREGS_CNTL_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_0', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_0_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_1', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_10', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_10_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_11', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_11_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_12', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_12_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_13', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_13_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_14', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_14_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_15', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_15_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_1_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_2', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_2_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_3', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_3_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_4', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_4_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_5', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_5_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_6', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_6_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_7', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_7_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_8', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_8_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_9', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_9_BASE_IDX', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL', + 'regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX', + 'regBIF_BX0_PCIE_DATA', 'regBIF_BX0_PCIE_DATA2', + 'regBIF_BX0_PCIE_DATA2_BASE_IDX', 'regBIF_BX0_PCIE_DATA_BASE_IDX', + 'regBIF_BX0_PCIE_INDEX', 'regBIF_BX0_PCIE_INDEX2', + 'regBIF_BX0_PCIE_INDEX2_BASE_IDX', 'regBIF_BX0_PCIE_INDEX2_HI', + 'regBIF_BX0_PCIE_INDEX2_HI_BASE_IDX', + 'regBIF_BX0_PCIE_INDEX_BASE_IDX', 'regBIF_BX0_PCIE_INDEX_HI', + 'regBIF_BX0_PCIE_INDEX_HI_BASE_IDX', + 'regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL', + 'regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL', + 'regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_0', + 'regBIF_BX0_SBIOS_SCRATCH_0_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_1', 'regBIF_BX0_SBIOS_SCRATCH_10', + 'regBIF_BX0_SBIOS_SCRATCH_10_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_11', + 'regBIF_BX0_SBIOS_SCRATCH_11_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_12', + 'regBIF_BX0_SBIOS_SCRATCH_12_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_13', + 'regBIF_BX0_SBIOS_SCRATCH_13_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_14', + 'regBIF_BX0_SBIOS_SCRATCH_14_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_15', + 'regBIF_BX0_SBIOS_SCRATCH_15_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_1_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_2', + 'regBIF_BX0_SBIOS_SCRATCH_2_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_3', + 'regBIF_BX0_SBIOS_SCRATCH_3_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_4', + 'regBIF_BX0_SBIOS_SCRATCH_4_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_5', + 'regBIF_BX0_SBIOS_SCRATCH_5_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_6', + 'regBIF_BX0_SBIOS_SCRATCH_6_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_7', + 'regBIF_BX0_SBIOS_SCRATCH_7_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_8', + 'regBIF_BX0_SBIOS_SCRATCH_8_BASE_IDX', + 'regBIF_BX0_SBIOS_SCRATCH_9', + 'regBIF_BX0_SBIOS_SCRATCH_9_BASE_IDX', 'regBIF_BX1_BACO_CNTL', + 'regBIF_BX1_BACO_CNTL_BASE_IDX', 'regBIF_BX1_BIF_BACO_EXIT_TIME0', + 'regBIF_BX1_BIF_BACO_EXIT_TIME0_BASE_IDX', + 'regBIF_BX1_BIF_BACO_EXIT_TIMER1', + 'regBIF_BX1_BIF_BACO_EXIT_TIMER1_BASE_IDX', + 'regBIF_BX1_BIF_BACO_EXIT_TIMER2', + 'regBIF_BX1_BIF_BACO_EXIT_TIMER2_BASE_IDX', + 'regBIF_BX1_BIF_BACO_EXIT_TIMER3', + 'regBIF_BX1_BIF_BACO_EXIT_TIMER3_BASE_IDX', + 'regBIF_BX1_BIF_BACO_EXIT_TIMER4', + 'regBIF_BX1_BIF_BACO_EXIT_TIMER4_BASE_IDX', + 'regBIF_BX1_BIF_CLKREQB_PAD_CNTL', + 'regBIF_BX1_BIF_CLKREQB_PAD_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_DOORBELL_CNTL', + 'regBIF_BX1_BIF_DOORBELL_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_DOORBELL_INT_CNTL', + 'regBIF_BX1_BIF_DOORBELL_INT_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_FB_EN', 'regBIF_BX1_BIF_FB_EN_BASE_IDX', + 'regBIF_BX1_BIF_FEATURES_CONTROL_MISC', + 'regBIF_BX1_BIF_FEATURES_CONTROL_MISC_BASE_IDX', + 'regBIF_BX1_BIF_INTR_CNTL', 'regBIF_BX1_BIF_INTR_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_MM_INDACCESS_CNTL', + 'regBIF_BX1_BIF_MM_INDACCESS_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_MP1_INTR_CTRL', + 'regBIF_BX1_BIF_MP1_INTR_CTRL_BASE_IDX', + 'regBIF_BX1_BIF_MST_TRANS_PENDING_VF', + 'regBIF_BX1_BIF_MST_TRANS_PENDING_VF_BASE_IDX', + 'regBIF_BX1_BIF_PERSTB_PAD_CNTL', + 'regBIF_BX1_BIF_PERSTB_PAD_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_PWRBRK_PAD_CNTL', + 'regBIF_BX1_BIF_PWRBRK_PAD_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_PX_EN_PAD_CNTL', + 'regBIF_BX1_BIF_PX_EN_PAD_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_RB_BASE', 'regBIF_BX1_BIF_RB_BASE_BASE_IDX', + 'regBIF_BX1_BIF_RB_CNTL', 'regBIF_BX1_BIF_RB_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_RB_RPTR', 'regBIF_BX1_BIF_RB_RPTR_BASE_IDX', + 'regBIF_BX1_BIF_RB_WPTR', 'regBIF_BX1_BIF_RB_WPTR_ADDR_HI', + 'regBIF_BX1_BIF_RB_WPTR_ADDR_HI_BASE_IDX', + 'regBIF_BX1_BIF_RB_WPTR_ADDR_LO', + 'regBIF_BX1_BIF_RB_WPTR_ADDR_LO_BASE_IDX', + 'regBIF_BX1_BIF_RB_WPTR_BASE_IDX', + 'regBIF_BX1_BIF_REFPADKIN_PAD_CNTL', + 'regBIF_BX1_BIF_REFPADKIN_PAD_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_RLC_INTR_CNTL', + 'regBIF_BX1_BIF_RLC_INTR_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_SCRATCH0', 'regBIF_BX1_BIF_SCRATCH0_BASE_IDX', + 'regBIF_BX1_BIF_SCRATCH1', 'regBIF_BX1_BIF_SCRATCH1_BASE_IDX', + 'regBIF_BX1_BIF_SLV_TRANS_PENDING_VF', + 'regBIF_BX1_BIF_SLV_TRANS_PENDING_VF_BASE_IDX', + 'regBIF_BX1_BIF_UVD_INTR_CNTL', + 'regBIF_BX1_BIF_UVD_INTR_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_VCE_INTR_CNTL', + 'regBIF_BX1_BIF_VCE_INTR_CNTL_BASE_IDX', + 'regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE', + 'regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE_BASE_IDX', + 'regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE', + 'regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE_BASE_IDX', + 'regBIF_BX1_BIOS_SCRATCH_0', 'regBIF_BX1_BIOS_SCRATCH_0_BASE_IDX', + 'regBIF_BX1_BIOS_SCRATCH_1', 'regBIF_BX1_BIOS_SCRATCH_10', + 'regBIF_BX1_BIOS_SCRATCH_10_BASE_IDX', + 'regBIF_BX1_BIOS_SCRATCH_11', + 'regBIF_BX1_BIOS_SCRATCH_11_BASE_IDX', + 'regBIF_BX1_BIOS_SCRATCH_12', + 'regBIF_BX1_BIOS_SCRATCH_12_BASE_IDX', + 'regBIF_BX1_BIOS_SCRATCH_13', + 'regBIF_BX1_BIOS_SCRATCH_13_BASE_IDX', + 'regBIF_BX1_BIOS_SCRATCH_14', + 'regBIF_BX1_BIOS_SCRATCH_14_BASE_IDX', + 'regBIF_BX1_BIOS_SCRATCH_15', + 'regBIF_BX1_BIOS_SCRATCH_15_BASE_IDX', + 'regBIF_BX1_BIOS_SCRATCH_1_BASE_IDX', 'regBIF_BX1_BIOS_SCRATCH_2', + 'regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX', 'regBIF_BX1_BIOS_SCRATCH_3', + 'regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX', 'regBIF_BX1_BIOS_SCRATCH_4', + 'regBIF_BX1_BIOS_SCRATCH_4_BASE_IDX', 'regBIF_BX1_BIOS_SCRATCH_5', + 'regBIF_BX1_BIOS_SCRATCH_5_BASE_IDX', 'regBIF_BX1_BIOS_SCRATCH_6', + 'regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX', 'regBIF_BX1_BIOS_SCRATCH_7', + 'regBIF_BX1_BIOS_SCRATCH_7_BASE_IDX', 'regBIF_BX1_BIOS_SCRATCH_8', + 'regBIF_BX1_BIOS_SCRATCH_8_BASE_IDX', 'regBIF_BX1_BIOS_SCRATCH_9', + 'regBIF_BX1_BIOS_SCRATCH_9_BASE_IDX', 'regBIF_BX1_BUS_CNTL', + 'regBIF_BX1_BUS_CNTL_BASE_IDX', 'regBIF_BX1_BX_RESET_CNTL', + 'regBIF_BX1_BX_RESET_CNTL_BASE_IDX', 'regBIF_BX1_BX_RESET_EN', + 'regBIF_BX1_BX_RESET_EN_BASE_IDX', + 'regBIF_BX1_CC_BIF_BX_PINSTRAP0', + 'regBIF_BX1_CC_BIF_BX_PINSTRAP0_BASE_IDX', + 'regBIF_BX1_CC_BIF_BX_STRAP0', + 'regBIF_BX1_CC_BIF_BX_STRAP0_BASE_IDX', + 'regBIF_BX1_CLKREQB_PAD_CNTL', + 'regBIF_BX1_CLKREQB_PAD_CNTL_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_0', + 'regBIF_BX1_DRIVER_SCRATCH_0_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_1', 'regBIF_BX1_DRIVER_SCRATCH_10', + 'regBIF_BX1_DRIVER_SCRATCH_10_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_11', + 'regBIF_BX1_DRIVER_SCRATCH_11_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_12', + 'regBIF_BX1_DRIVER_SCRATCH_12_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_13', + 'regBIF_BX1_DRIVER_SCRATCH_13_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_14', + 'regBIF_BX1_DRIVER_SCRATCH_14_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_15', + 'regBIF_BX1_DRIVER_SCRATCH_15_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_1_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_2', + 'regBIF_BX1_DRIVER_SCRATCH_2_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_3', + 'regBIF_BX1_DRIVER_SCRATCH_3_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_4', + 'regBIF_BX1_DRIVER_SCRATCH_4_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_5', + 'regBIF_BX1_DRIVER_SCRATCH_5_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_6', + 'regBIF_BX1_DRIVER_SCRATCH_6_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_7', + 'regBIF_BX1_DRIVER_SCRATCH_7_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_8', + 'regBIF_BX1_DRIVER_SCRATCH_8_BASE_IDX', + 'regBIF_BX1_DRIVER_SCRATCH_9', + 'regBIF_BX1_DRIVER_SCRATCH_9_BASE_IDX', 'regBIF_BX1_FW_SCRATCH_0', + 'regBIF_BX1_FW_SCRATCH_0_BASE_IDX', 'regBIF_BX1_FW_SCRATCH_1', + 'regBIF_BX1_FW_SCRATCH_10', 'regBIF_BX1_FW_SCRATCH_10_BASE_IDX', + 'regBIF_BX1_FW_SCRATCH_11', 'regBIF_BX1_FW_SCRATCH_11_BASE_IDX', + 'regBIF_BX1_FW_SCRATCH_12', 'regBIF_BX1_FW_SCRATCH_12_BASE_IDX', + 'regBIF_BX1_FW_SCRATCH_13', 'regBIF_BX1_FW_SCRATCH_13_BASE_IDX', + 'regBIF_BX1_FW_SCRATCH_14', 'regBIF_BX1_FW_SCRATCH_14_BASE_IDX', + 'regBIF_BX1_FW_SCRATCH_15', 'regBIF_BX1_FW_SCRATCH_15_BASE_IDX', + 'regBIF_BX1_FW_SCRATCH_1_BASE_IDX', 'regBIF_BX1_FW_SCRATCH_2', + 'regBIF_BX1_FW_SCRATCH_2_BASE_IDX', 'regBIF_BX1_FW_SCRATCH_3', + 'regBIF_BX1_FW_SCRATCH_3_BASE_IDX', 'regBIF_BX1_FW_SCRATCH_4', + 'regBIF_BX1_FW_SCRATCH_4_BASE_IDX', 'regBIF_BX1_FW_SCRATCH_5', + 'regBIF_BX1_FW_SCRATCH_5_BASE_IDX', 'regBIF_BX1_FW_SCRATCH_6', + 'regBIF_BX1_FW_SCRATCH_6_BASE_IDX', 'regBIF_BX1_FW_SCRATCH_7', + 'regBIF_BX1_FW_SCRATCH_7_BASE_IDX', 'regBIF_BX1_FW_SCRATCH_8', + 'regBIF_BX1_FW_SCRATCH_8_BASE_IDX', 'regBIF_BX1_FW_SCRATCH_9', + 'regBIF_BX1_FW_SCRATCH_9_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR0', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR0_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR1', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR1_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR2', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR2_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR3', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR3_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR4', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR4_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR5', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR5_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR6', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR6_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR7', + 'regBIF_BX1_GFX_MMIOREG_CAM_ADDR7_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_CNTL', + 'regBIF_BX1_GFX_MMIOREG_CAM_CNTL_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL', + 'regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL', + 'regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7', + 'regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX', + 'regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL', + 'regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX', + 'regBIF_BX1_HDP_ATOMIC_CONTROL_MISC', + 'regBIF_BX1_HDP_ATOMIC_CONTROL_MISC_BASE_IDX', + 'regBIF_BX1_INTERRUPT_CNTL', 'regBIF_BX1_INTERRUPT_CNTL2', + 'regBIF_BX1_INTERRUPT_CNTL2_BASE_IDX', + 'regBIF_BX1_INTERRUPT_CNTL_BASE_IDX', 'regBIF_BX1_MAILBOX_INDEX', + 'regBIF_BX1_MAILBOX_INDEX_BASE_IDX', 'regBIF_BX1_MEM_TYPE_CNTL', + 'regBIF_BX1_MEM_TYPE_CNTL_BASE_IDX', 'regBIF_BX1_MM_CFGREGS_CNTL', + 'regBIF_BX1_MM_CFGREGS_CNTL_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_0', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_0_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_1', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_10', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_10_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_11', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_11_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_12', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_12_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_13', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_13_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_14', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_14_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_15', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_15_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_1_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_2', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_2_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_3', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_3_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_4', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_4_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_5', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_5_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_6', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_6_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_7', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_7_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_8', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_8_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_9', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_9_BASE_IDX', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL', + 'regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX', + 'regBIF_BX1_PCIE_DATA', 'regBIF_BX1_PCIE_DATA2', + 'regBIF_BX1_PCIE_DATA2_BASE_IDX', 'regBIF_BX1_PCIE_DATA_BASE_IDX', + 'regBIF_BX1_PCIE_INDEX', 'regBIF_BX1_PCIE_INDEX2', + 'regBIF_BX1_PCIE_INDEX2_BASE_IDX', 'regBIF_BX1_PCIE_INDEX2_HI', + 'regBIF_BX1_PCIE_INDEX2_HI_BASE_IDX', + 'regBIF_BX1_PCIE_INDEX_BASE_IDX', 'regBIF_BX1_PCIE_INDEX_HI', + 'regBIF_BX1_PCIE_INDEX_HI_BASE_IDX', + 'regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL', + 'regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL', + 'regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_0', + 'regBIF_BX1_SBIOS_SCRATCH_0_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_1', 'regBIF_BX1_SBIOS_SCRATCH_10', + 'regBIF_BX1_SBIOS_SCRATCH_10_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_11', + 'regBIF_BX1_SBIOS_SCRATCH_11_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_12', + 'regBIF_BX1_SBIOS_SCRATCH_12_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_13', + 'regBIF_BX1_SBIOS_SCRATCH_13_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_14', + 'regBIF_BX1_SBIOS_SCRATCH_14_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_15', + 'regBIF_BX1_SBIOS_SCRATCH_15_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_1_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_2', + 'regBIF_BX1_SBIOS_SCRATCH_2_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_3', + 'regBIF_BX1_SBIOS_SCRATCH_3_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_4', + 'regBIF_BX1_SBIOS_SCRATCH_4_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_5', + 'regBIF_BX1_SBIOS_SCRATCH_5_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_6', + 'regBIF_BX1_SBIOS_SCRATCH_6_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_7', + 'regBIF_BX1_SBIOS_SCRATCH_7_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_8', + 'regBIF_BX1_SBIOS_SCRATCH_8_BASE_IDX', + 'regBIF_BX1_SBIOS_SCRATCH_9', + 'regBIF_BX1_SBIOS_SCRATCH_9_BASE_IDX', + 'regBIF_BX1_VF_DOORBELL_EN', 'regBIF_BX1_VF_DOORBELL_EN_BASE_IDX', + 'regBIF_BX1_VF_DOORBELL_STATUS', + 'regBIF_BX1_VF_DOORBELL_STATUS_BASE_IDX', 'regBIF_BX1_VF_FB_EN', + 'regBIF_BX1_VF_FB_EN_BASE_IDX', 'regBIF_BX1_VF_FB_STATUS', + 'regBIF_BX1_VF_FB_STATUS_BASE_IDX', 'regBIF_BX1_VF_REGWR_EN', + 'regBIF_BX1_VF_REGWR_EN_BASE_IDX', 'regBIF_BX1_VF_REGWR_STATUS', + 'regBIF_BX1_VF_REGWR_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS', + 'regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING', + 'regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX', + 'regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MM_DATA', + 'regBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MM_INDEX', + 'regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI', + 'regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_PF0_BIF_BME_STATUS', + 'regBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_PF0_BIF_TRANS_PENDING', + 'regBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_PF0_BIF_VMHV_MAILBOX', + 'regBIF_BX_PF0_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_PF0_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_PF0_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_PF0_MAILBOX_CONTROL', + 'regBIF_BX_PF0_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_PF0_MAILBOX_INT_CNTL', + 'regBIF_BX_PF0_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_PF0_MM_DATA', 'regBIF_BX_PF0_MM_DATA_BASE_IDX', + 'regBIF_BX_PF0_MM_INDEX', 'regBIF_BX_PF0_MM_INDEX_BASE_IDX', + 'regBIF_BX_PF0_MM_INDEX_HI', 'regBIF_BX_PF0_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_PF0_PARTITION_COMPUTE_CAP', + 'regBIF_BX_PF0_PARTITION_COMPUTE_CAP_BASE_IDX', + 'regBIF_BX_PF0_PARTITION_COMPUTE_STATUS', + 'regBIF_BX_PF0_PARTITION_COMPUTE_STATUS_BASE_IDX', + 'regBIF_BX_PF0_PARTITION_MEM_CAP', + 'regBIF_BX_PF0_PARTITION_MEM_CAP_BASE_IDX', + 'regBIF_BX_PF0_PARTITION_MEM_STATUS', + 'regBIF_BX_PF0_PARTITION_MEM_STATUS_BASE_IDX', + 'regBIF_BX_PF0_RSMU_DATA', 'regBIF_BX_PF0_RSMU_DATA_BASE_IDX', + 'regBIF_BX_PF0_RSMU_INDEX', 'regBIF_BX_PF0_RSMU_INDEX_BASE_IDX', + 'regBIF_BX_PF0_RSMU_INDEX_HI', + 'regBIF_BX_PF0_RSMU_INDEX_HI_BASE_IDX', + 'regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG', + 'regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_BASE_IDX', + 'regBIF_BX_PF1_BIF_BME_STATUS', + 'regBIF_BX_PF1_BIF_BME_STATUS_BASE_IDX', + 'regBIF_BX_PF1_BIF_TRANS_PENDING', + 'regBIF_BX_PF1_BIF_TRANS_PENDING_BASE_IDX', + 'regBIF_BX_PF1_BIF_VMHV_MAILBOX', + 'regBIF_BX_PF1_BIF_VMHV_MAILBOX_BASE_IDX', + 'regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH', + 'regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX', + 'regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW', + 'regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX', + 'regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL', + 'regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX', + 'regBIF_BX_PF1_GPU_HDP_FLUSH_DONE', + 'regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_BASE_IDX', + 'regBIF_BX_PF1_GPU_HDP_FLUSH_REQ', + 'regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_BASE_IDX', + 'regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL', + 'regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL', + 'regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX', + 'regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL', + 'regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX', + 'regBIF_BX_PF1_MAILBOX_CONTROL', + 'regBIF_BX_PF1_MAILBOX_CONTROL_BASE_IDX', + 'regBIF_BX_PF1_MAILBOX_INT_CNTL', + 'regBIF_BX_PF1_MAILBOX_INT_CNTL_BASE_IDX', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3', + 'regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX', + 'regBIF_BX_PF1_MM_DATA', 'regBIF_BX_PF1_MM_DATA_BASE_IDX', + 'regBIF_BX_PF1_MM_INDEX', 'regBIF_BX_PF1_MM_INDEX_BASE_IDX', + 'regBIF_BX_PF1_MM_INDEX_HI', 'regBIF_BX_PF1_MM_INDEX_HI_BASE_IDX', + 'regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS', + 'regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX', + 'regBIF_BX_PF1_PARTITION_COMPUTE_CAP', + 'regBIF_BX_PF1_PARTITION_COMPUTE_CAP_BASE_IDX', + 'regBIF_BX_PF1_PARTITION_COMPUTE_STATUS', + 'regBIF_BX_PF1_PARTITION_COMPUTE_STATUS_BASE_IDX', + 'regBIF_BX_PF1_PARTITION_MEM_CAP', + 'regBIF_BX_PF1_PARTITION_MEM_CAP_BASE_IDX', + 'regBIF_BX_PF1_PARTITION_MEM_STATUS', + 'regBIF_BX_PF1_PARTITION_MEM_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W', + 'regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF0_0_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_BIST', + 'regBIF_CFG_DEV0_EPF0_0_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF0_0_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_CAP_PTR', + 'regBIF_CFG_DEV0_EPF0_0_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_COMMAND', + 'regBIF_CFG_DEV0_EPF0_0_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP', + 'regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF0_0_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_HEADER', + 'regBIF_CFG_DEV0_EPF0_0_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LATENCY', + 'regBIF_CFG_DEV0_EPF0_0_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LINK_CAP', + 'regBIF_CFG_DEV0_EPF0_0_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF0_0_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT', + 'regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT', + 'regBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT', + 'regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT', + 'regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT', + 'regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT', + 'regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT', + 'regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP', + 'regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF0_0_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF0_0_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_MSI_MASK', + 'regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3', + 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'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB', + 'regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PMI_CAP', + 'regBIF_CFG_DEV0_EPF0_0_PMI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL', + 'regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_REVISION_ID', + 'regBIF_CFG_DEV0_EPF0_0_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT', + 'regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT', + 'regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_STATUS', + 'regBIF_CFG_DEV0_EPF0_0_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF0_0_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST', + 'regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF0_0_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF0_0_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID', + 'regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W', + 'regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1', + 'regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2', + 'regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3', + 'regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4', + 'regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5', + 'regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6', + 'regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_BASE_CLASS', + 'regBIF_CFG_DEV0_EPF1_0_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_BIST', + 'regBIF_CFG_DEV0_EPF1_0_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_CACHE_LINE', + 'regBIF_CFG_DEV0_EPF1_0_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_CAP_PTR', + 'regBIF_CFG_DEV0_EPF1_0_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR', + 'regBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_COMMAND', + 'regBIF_CFG_DEV0_EPF1_0_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP', + 'regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2', + 'regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL', + 'regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_DEVICE_ID', + 'regBIF_CFG_DEV0_EPF1_0_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS', + 'regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_HEADER', + 'regBIF_CFG_DEV0_EPF1_0_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_LATENCY', + 'regBIF_CFG_DEV0_EPF1_0_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_LINK_CAP', + 'regBIF_CFG_DEV0_EPF1_0_LINK_CAP2', + 'regBIF_CFG_DEV0_EPF1_0_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_LINK_CNTL', + 'regBIF_CFG_DEV0_EPF1_0_LINK_CNTL2', + 'regBIF_CFG_DEV0_EPF1_0_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_LINK_STATUS', + 'regBIF_CFG_DEV0_EPF1_0_LINK_STATUS2', + 'regBIF_CFG_DEV0_EPF1_0_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_MAX_LATENCY', + 'regBIF_CFG_DEV0_EPF1_0_MAX_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_MIN_GRANT', + 'regBIF_CFG_DEV0_EPF1_0_MIN_GRANT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_MSIX_PBA', + 'regBIF_CFG_DEV0_EPF1_0_MSIX_PBA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_MSIX_TABLE', + 'regBIF_CFG_DEV0_EPF1_0_MSIX_TABLE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_MSI_MASK', + 'regBIF_CFG_DEV0_EPF1_0_MSI_MASK_64', + 'regBIF_CFG_DEV0_EPF1_0_MSI_MASK_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_MSI_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_MSI_PENDING', + 'regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64', + 'regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_CAP', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PMI_CAP', + 'regBIF_CFG_DEV0_EPF1_0_PMI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL', + 'regBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE', + 'regBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_REVISION_ID', + 'regBIF_CFG_DEV0_EPF1_0_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_STATUS', + 'regBIF_CFG_DEV0_EPF1_0_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_SUB_CLASS', + 'regBIF_CFG_DEV0_EPF1_0_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST', + 'regBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_EPF1_0_VENDOR_ID', + 'regBIF_CFG_DEV0_EPF1_0_VENDOR_ID_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_BASE_ADDR_1', + 'regBIF_CFG_DEV0_RC0_BASE_ADDR_1_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_BASE_ADDR_2', + 'regBIF_CFG_DEV0_RC0_BASE_ADDR_2_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_BASE_CLASS', + 'regBIF_CFG_DEV0_RC0_BASE_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_BIST', 'regBIF_CFG_DEV0_RC0_BIST_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_CACHE_LINE', + 'regBIF_CFG_DEV0_RC0_CACHE_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_CAP_PTR', + 'regBIF_CFG_DEV0_RC0_CAP_PTR_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_COMMAND', + 'regBIF_CFG_DEV0_RC0_COMMAND_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP', + 'regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS', + 'regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_DEVICE_CAP', + 'regBIF_CFG_DEV0_RC0_DEVICE_CAP2', + 'regBIF_CFG_DEV0_RC0_DEVICE_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_DEVICE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_DEVICE_CNTL', + 'regBIF_CFG_DEV0_RC0_DEVICE_CNTL2', + 'regBIF_CFG_DEV0_RC0_DEVICE_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_DEVICE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_DEVICE_ID', + 'regBIF_CFG_DEV0_RC0_DEVICE_ID_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_DEVICE_STATUS', + 'regBIF_CFG_DEV0_RC0_DEVICE_STATUS2', + 'regBIF_CFG_DEV0_RC0_DEVICE_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_DEVICE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL', + 'regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_HEADER', + 'regBIF_CFG_DEV0_RC0_HEADER_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_INTERRUPT_LINE', + 'regBIF_CFG_DEV0_RC0_INTERRUPT_LINE_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_INTERRUPT_PIN', + 'regBIF_CFG_DEV0_RC0_INTERRUPT_PIN_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT', + 'regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI', + 'regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL', + 'regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT', + 'regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL', + 'regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS', + 'regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LATENCY', + 'regBIF_CFG_DEV0_RC0_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LINK_CAP', 'regBIF_CFG_DEV0_RC0_LINK_CAP2', + 'regBIF_CFG_DEV0_RC0_LINK_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LINK_CAP_16GT', + 'regBIF_CFG_DEV0_RC0_LINK_CAP_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LINK_CAP_32GT', + 'regBIF_CFG_DEV0_RC0_LINK_CAP_32GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LINK_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LINK_CNTL', 'regBIF_CFG_DEV0_RC0_LINK_CNTL2', + 'regBIF_CFG_DEV0_RC0_LINK_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT', + 'regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LINK_CNTL_32GT', + 'regBIF_CFG_DEV0_RC0_LINK_CNTL_32GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LINK_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LINK_STATUS', + 'regBIF_CFG_DEV0_RC0_LINK_STATUS2', + 'regBIF_CFG_DEV0_RC0_LINK_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT', + 'regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LINK_STATUS_32GT', + 'regBIF_CFG_DEV0_RC0_LINK_STATUS_32GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LINK_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT', + 'regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP', + 'regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS', + 'regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT', + 'regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_MSI_CAP_LIST', + 'regBIF_CFG_DEV0_RC0_MSI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA', + 'regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64', + 'regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI', + 'regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO', + 'regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL', + 'regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_MSI_MSG_DATA', + 'regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64', + 'regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP', + 'regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL', + 'regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL', + 'regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_CAP', + 'regBIF_CFG_DEV0_RC0_PCIE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST', + 'regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK', + 'regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS', + 'regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1', + 'regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2', + 'regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID', + 'regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0', + 'regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1', + 'regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2', + 'regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3', + 'regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS', + 'regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3', + 'regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1', + 'regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2', + 'regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL', + 'regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS', + 'regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD', + 'regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS', + 'regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0', + 'regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1', + 'regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2', + 'regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3', + 'regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK', + 'regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY', + 'regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS', + 'regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP', + 'regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL', + 'regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS', + 'regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP', + 'regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL', + 'regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS', + 'regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1', + 'regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2', + 'regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST', + 'regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR', + 'regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PMI_CAP', + 'regBIF_CFG_DEV0_RC0_PMI_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PMI_CAP_LIST', + 'regBIF_CFG_DEV0_RC0_PMI_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL', + 'regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT', + 'regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER', + 'regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER', + 'regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_PROG_INTERFACE', + 'regBIF_CFG_DEV0_RC0_PROG_INTERFACE_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_REVISION_ID', + 'regBIF_CFG_DEV0_RC0_REVISION_ID_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR', + 'regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_ROOT_CAP', + 'regBIF_CFG_DEV0_RC0_ROOT_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_ROOT_CNTL', + 'regBIF_CFG_DEV0_RC0_ROOT_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_ROOT_STATUS', + 'regBIF_CFG_DEV0_RC0_ROOT_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT', + 'regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT', + 'regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_SECONDARY_STATUS', + 'regBIF_CFG_DEV0_RC0_SECONDARY_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_SLOT_CAP', 'regBIF_CFG_DEV0_RC0_SLOT_CAP2', + 'regBIF_CFG_DEV0_RC0_SLOT_CAP2_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_SLOT_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_SLOT_CNTL', 'regBIF_CFG_DEV0_RC0_SLOT_CNTL2', + 'regBIF_CFG_DEV0_RC0_SLOT_CNTL2_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_SLOT_CNTL_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_SLOT_STATUS', + 'regBIF_CFG_DEV0_RC0_SLOT_STATUS2', + 'regBIF_CFG_DEV0_RC0_SLOT_STATUS2_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_SLOT_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_SSID_CAP', + 'regBIF_CFG_DEV0_RC0_SSID_CAP_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_SSID_CAP_LIST', + 'regBIF_CFG_DEV0_RC0_SSID_CAP_LIST_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_STATUS', + 'regBIF_CFG_DEV0_RC0_STATUS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY', + 'regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_SUB_CLASS', + 'regBIF_CFG_DEV0_RC0_SUB_CLASS_BASE_IDX', + 'regBIF_CFG_DEV0_RC0_VENDOR_ID', + 'regBIF_CFG_DEV0_RC0_VENDOR_ID_BASE_IDX', + 'regBIF_D3HOTD0_INTR_MASK', 'regBIF_D3HOTD0_INTR_MASK_BASE_IDX', + 'regBIF_D3HOTD0_INTR_STS', 'regBIF_D3HOTD0_INTR_STS_BASE_IDX', + 'regBIF_DEV0_PF0_DSTATE_VALUE', + 'regBIF_DEV0_PF0_DSTATE_VALUE_BASE_IDX', + 'regBIF_DEV0_PF1_DSTATE_VALUE', + 'regBIF_DEV0_PF1_DSTATE_VALUE_BASE_IDX', 'regBIF_DMA_MP4_ERR_LOG', + 'regBIF_DMA_MP4_ERR_LOG_BASE_IDX', 'regBIF_GFX_DRV_VPU_RST', + 'regBIF_GFX_DRV_VPU_RST_BASE_IDX', 'regBIF_GMI_WRR_WEIGHT', + 'regBIF_GMI_WRR_WEIGHT2', 'regBIF_GMI_WRR_WEIGHT2_BASE_IDX', + 'regBIF_GMI_WRR_WEIGHT3', 'regBIF_GMI_WRR_WEIGHT3_BASE_IDX', + 'regBIF_GMI_WRR_WEIGHT_BASE_IDX', 'regBIF_INST_RESET_INTR_MASK', + 'regBIF_INST_RESET_INTR_MASK_BASE_IDX', + 'regBIF_INST_RESET_INTR_STS', + 'regBIF_INST_RESET_INTR_STS_BASE_IDX', 'regBIF_PASID_ERR_CLR', + 'regBIF_PASID_ERR_CLR_BASE_IDX', 'regBIF_PASID_ERR_LOG', + 'regBIF_PASID_ERR_LOG_BASE_IDX', 'regBIF_PF_DSTATE_INTR_MASK', + 'regBIF_PF_DSTATE_INTR_MASK_BASE_IDX', + 'regBIF_PF_DSTATE_INTR_STS', 'regBIF_PF_DSTATE_INTR_STS_BASE_IDX', + 'regBIF_PF_FLR_INTR_MASK', 'regBIF_PF_FLR_INTR_MASK_BASE_IDX', + 'regBIF_PF_FLR_INTR_STS', 'regBIF_PF_FLR_INTR_STS_BASE_IDX', + 'regBIF_PF_FLR_RST', 'regBIF_PF_FLR_RST_BASE_IDX', + 'regBIF_PORT0_DSTATE_VALUE', 'regBIF_PORT0_DSTATE_VALUE_BASE_IDX', + 'regBIF_POWER_INTR_MASK', 'regBIF_POWER_INTR_MASK_BASE_IDX', + 'regBIF_POWER_INTR_STS', 'regBIF_POWER_INTR_STS_BASE_IDX', + 'regBIF_RST_MISC_CTRL', 'regBIF_RST_MISC_CTRL2', + 'regBIF_RST_MISC_CTRL2_BASE_IDX', 'regBIF_RST_MISC_CTRL3', + 'regBIF_RST_MISC_CTRL3_BASE_IDX', 'regBIF_RST_MISC_CTRL_BASE_IDX', + 'regBIF_SELFRING_BUFFER_VID', + 'regBIF_SELFRING_BUFFER_VID_BASE_IDX', + 'regBIF_SELFRING_VECTOR_CNTL', + 'regBIF_SELFRING_VECTOR_CNTL_BASE_IDX', 'regBME_DUMMY_CNTL_0', + 'regBME_DUMMY_CNTL_0_BASE_IDX', 'regCAM_CONTROL', + 'regCAM_CONTROL_BASE_IDX', 'regCAM_TARGET_DATA', + 'regCAM_TARGET_DATA_ADDR_BOTTOM', + 'regCAM_TARGET_DATA_ADDR_BOTTOM_BASE_IDX', + 'regCAM_TARGET_DATA_ADDR_TOP', + 'regCAM_TARGET_DATA_ADDR_TOP_BASE_IDX', + 'regCAM_TARGET_DATA_BASE_IDX', 'regCAM_TARGET_DATA_MASK', + 'regCAM_TARGET_DATA_MASK_BASE_IDX', + 'regCAM_TARGET_INDEX_ADDR_BOTTOM', + 'regCAM_TARGET_INDEX_ADDR_BOTTOM_BASE_IDX', + 'regCAM_TARGET_INDEX_ADDR_TOP', + 'regCAM_TARGET_INDEX_ADDR_TOP_BASE_IDX', + 'regCAM_TARGET_INDEX_DATA', 'regCAM_TARGET_INDEX_DATA_BASE_IDX', + 'regCAM_TARGET_INDEX_DATA_MASK', + 'regCAM_TARGET_INDEX_DATA_MASK_BASE_IDX', + 'regDEV0_PF0_D3HOTD0_RST_CTRL', + 'regDEV0_PF0_D3HOTD0_RST_CTRL_BASE_IDX', + 'regDEV0_PF0_FLR_RST_CTRL', 'regDEV0_PF0_FLR_RST_CTRL_BASE_IDX', + 'regDEV0_PF1_D3HOTD0_RST_CTRL', + 'regDEV0_PF1_D3HOTD0_RST_CTRL_BASE_IDX', + 'regDEV0_PF1_FLR_RST_CTRL', 'regDEV0_PF1_FLR_RST_CTRL_BASE_IDX', + 'regDISCON_HYSTERESIS_HEAD_CTRL', + 'regDISCON_HYSTERESIS_HEAD_CTRL_BASE_IDX', + 'regDMA_CLK0_SW0_CL0_CNTL', 'regDMA_CLK0_SW0_CL0_CNTL_BASE_IDX', + 'regDMA_CLK0_SW0_CL1_CNTL', 'regDMA_CLK0_SW0_CL1_CNTL_BASE_IDX', + 'regDOORBELL0_CTRL_ENTRY_0', 'regDOORBELL0_CTRL_ENTRY_0_BASE_IDX', + 'regDOORBELL0_CTRL_ENTRY_1', 'regDOORBELL0_CTRL_ENTRY_10', + 'regDOORBELL0_CTRL_ENTRY_10_BASE_IDX', + 'regDOORBELL0_CTRL_ENTRY_11', + 'regDOORBELL0_CTRL_ENTRY_11_BASE_IDX', + 'regDOORBELL0_CTRL_ENTRY_12', + 'regDOORBELL0_CTRL_ENTRY_12_BASE_IDX', + 'regDOORBELL0_CTRL_ENTRY_13', + 'regDOORBELL0_CTRL_ENTRY_13_BASE_IDX', + 'regDOORBELL0_CTRL_ENTRY_14', + 'regDOORBELL0_CTRL_ENTRY_14_BASE_IDX', + 'regDOORBELL0_CTRL_ENTRY_15', + 'regDOORBELL0_CTRL_ENTRY_15_BASE_IDX', + 'regDOORBELL0_CTRL_ENTRY_16', + 'regDOORBELL0_CTRL_ENTRY_16_BASE_IDX', + 'regDOORBELL0_CTRL_ENTRY_17', + 'regDOORBELL0_CTRL_ENTRY_17_BASE_IDX', + 'regDOORBELL0_CTRL_ENTRY_18', + 'regDOORBELL0_CTRL_ENTRY_18_BASE_IDX', + 'regDOORBELL0_CTRL_ENTRY_19', + 'regDOORBELL0_CTRL_ENTRY_19_BASE_IDX', + 'regDOORBELL0_CTRL_ENTRY_1_BASE_IDX', 'regDOORBELL0_CTRL_ENTRY_2', + 'regDOORBELL0_CTRL_ENTRY_20', + 'regDOORBELL0_CTRL_ENTRY_20_BASE_IDX', + 'regDOORBELL0_CTRL_ENTRY_2_BASE_IDX', 'regDOORBELL0_CTRL_ENTRY_3', + 'regDOORBELL0_CTRL_ENTRY_3_BASE_IDX', 'regDOORBELL0_CTRL_ENTRY_4', + 'regDOORBELL0_CTRL_ENTRY_4_BASE_IDX', 'regDOORBELL0_CTRL_ENTRY_5', + 'regDOORBELL0_CTRL_ENTRY_5_BASE_IDX', 'regDOORBELL0_CTRL_ENTRY_6', + 'regDOORBELL0_CTRL_ENTRY_6_BASE_IDX', 'regDOORBELL0_CTRL_ENTRY_7', + 'regDOORBELL0_CTRL_ENTRY_7_BASE_IDX', 'regDOORBELL0_CTRL_ENTRY_8', + 'regDOORBELL0_CTRL_ENTRY_8_BASE_IDX', 'regDOORBELL0_CTRL_ENTRY_9', + 'regDOORBELL0_CTRL_ENTRY_9_BASE_IDX', 'regEGRESS_POISON_MASK_HI', + 'regEGRESS_POISON_MASK_HI_BASE_IDX', 'regEGRESS_POISON_MASK_LO', + 'regEGRESS_POISON_MASK_LO_BASE_IDX', + 'regEGRESS_POISON_SEVERITY_DOWN', + 'regEGRESS_POISON_SEVERITY_DOWN_BASE_IDX', + 'regEGRESS_POISON_SEVERITY_UPPER', + 'regEGRESS_POISON_SEVERITY_UPPER_BASE_IDX', + 'regEGRESS_POISON_STATUS_HI', + 'regEGRESS_POISON_STATUS_HI_BASE_IDX', + 'regEGRESS_POISON_STATUS_LO', + 'regEGRESS_POISON_STATUS_LO_BASE_IDX', + 'regErrEvent_ACTION_CONTROL', + 'regErrEvent_ACTION_CONTROL_BASE_IDX', 'regFEATURES_ENABLE', + 'regFEATURES_ENABLE_BASE_IDX', 'regGDC0_A2S_CNTL3_CL0', + 'regGDC0_A2S_CNTL3_CL0_BASE_IDX', 'regGDC0_A2S_CNTL3_CL1', + 'regGDC0_A2S_CNTL3_CL1_BASE_IDX', 'regGDC0_A2S_CNTL_CL0', + 'regGDC0_A2S_CNTL_CL0_BASE_IDX', 'regGDC0_A2S_CNTL_CL1', + 'regGDC0_A2S_CNTL_CL1_BASE_IDX', 'regGDC0_A2S_CNTL_SW0', + 'regGDC0_A2S_CNTL_SW0_BASE_IDX', 'regGDC0_A2S_CNTL_SW1', + 'regGDC0_A2S_CNTL_SW1_BASE_IDX', 'regGDC0_A2S_CNTL_SW2', + 'regGDC0_A2S_CNTL_SW2_BASE_IDX', 'regGDC0_A2S_MISC_CNTL', + 'regGDC0_A2S_MISC_CNTL_BASE_IDX', 'regGDC0_A2S_TAG_ALLOC_0', + 'regGDC0_A2S_TAG_ALLOC_0_BASE_IDX', 'regGDC0_A2S_TAG_ALLOC_1', + 'regGDC0_A2S_TAG_ALLOC_1_BASE_IDX', 'regGDC0_ATDMA_MISC_CNTL', + 'regGDC0_ATDMA_MISC_CNTL_BASE_IDX', + 'regGDC0_NBIF_GFX_DOORBELL_STATUS', + 'regGDC0_NBIF_GFX_DOORBELL_STATUS_BASE_IDX', + 'regGDC0_NGDC_MGCG_CTRL', 'regGDC0_NGDC_MGCG_CTRL_BASE_IDX', + 'regGDC0_NGDC_PGMST_CTRL', 'regGDC0_NGDC_PGMST_CTRL_BASE_IDX', + 'regGDC0_NGDC_PGSLV_CTRL', 'regGDC0_NGDC_PGSLV_CTRL_BASE_IDX', + 'regGDC0_NGDC_PG_MISC_CTRL', 'regGDC0_NGDC_PG_MISC_CTRL_BASE_IDX', + 'regGDC0_NGDC_RESERVED_0', 'regGDC0_NGDC_RESERVED_0_BASE_IDX', + 'regGDC0_NGDC_RESERVED_1', 'regGDC0_NGDC_RESERVED_1_BASE_IDX', + 'regGDC0_S2A_MISC_CNTL', 'regGDC0_S2A_MISC_CNTL_BASE_IDX', + 'regGDC0_SHUB_REGS_IF_CTL', 'regGDC0_SHUB_REGS_IF_CTL_BASE_IDX', + 'regGDC1_A2S_CNTL3_CL0', 'regGDC1_A2S_CNTL3_CL0_BASE_IDX', + 'regGDC1_A2S_CNTL3_CL1', 'regGDC1_A2S_CNTL3_CL1_BASE_IDX', + 'regGDC1_A2S_CNTL_CL0', 'regGDC1_A2S_CNTL_CL0_BASE_IDX', + 'regGDC1_A2S_CNTL_CL1', 'regGDC1_A2S_CNTL_CL1_BASE_IDX', + 'regGDC1_A2S_CNTL_SW0', 'regGDC1_A2S_CNTL_SW0_BASE_IDX', + 'regGDC1_A2S_CNTL_SW1', 'regGDC1_A2S_CNTL_SW1_BASE_IDX', + 'regGDC1_A2S_CNTL_SW2', 'regGDC1_A2S_CNTL_SW2_BASE_IDX', + 'regGDC1_A2S_MISC_CNTL', 'regGDC1_A2S_MISC_CNTL_BASE_IDX', + 'regGDC1_A2S_TAG_ALLOC_0', 'regGDC1_A2S_TAG_ALLOC_0_BASE_IDX', + 'regGDC1_A2S_TAG_ALLOC_1', 'regGDC1_A2S_TAG_ALLOC_1_BASE_IDX', + 'regGDC1_ATDMA_MISC_CNTL', 'regGDC1_ATDMA_MISC_CNTL_BASE_IDX', + 'regGDC1_NBIF_GFX_DOORBELL_STATUS', + 'regGDC1_NBIF_GFX_DOORBELL_STATUS_BASE_IDX', + 'regGDC1_NGDC_EARLY_WAKEUP_CTRL', + 'regGDC1_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX', + 'regGDC1_NGDC_MGCG_CTRL', 'regGDC1_NGDC_MGCG_CTRL_BASE_IDX', + 'regGDC1_NGDC_PGMST_CTRL', 'regGDC1_NGDC_PGMST_CTRL_BASE_IDX', + 'regGDC1_NGDC_PGSLV_CTRL', 'regGDC1_NGDC_PGSLV_CTRL_BASE_IDX', + 'regGDC1_NGDC_PG_MISC_CTRL', 'regGDC1_NGDC_PG_MISC_CTRL_BASE_IDX', + 'regGDC1_NGDC_RESERVED_0', 'regGDC1_NGDC_RESERVED_0_BASE_IDX', + 'regGDC1_NGDC_RESERVED_1', 'regGDC1_NGDC_RESERVED_1_BASE_IDX', + 'regGDC1_S2A_MISC_CNTL', 'regGDC1_S2A_MISC_CNTL_BASE_IDX', + 'regGDC1_SHUB_REGS_IF_CTL', 'regGDC1_SHUB_REGS_IF_CTL_BASE_IDX', + 'regHARD_RST_CTRL', 'regHARD_RST_CTRL_BASE_IDX', + 'regHST_CLK0_SW0_CL0_CNTL', 'regHST_CLK0_SW0_CL0_CNTL_BASE_IDX', + 'regHST_CLK0_SW1_CL0_CNTL', 'regHST_CLK0_SW1_CL0_CNTL_BASE_IDX', + 'regHST_CLK0_SW1_CL1_CNTL', 'regHST_CLK0_SW1_CL1_CNTL_BASE_IDX', + 'regHST_CLK0_SW1_CL2_CNTL', 'regHST_CLK0_SW1_CL2_CNTL_BASE_IDX', + 'regINTERNAL_POISON_MASK', 'regINTERNAL_POISON_MASK_BASE_IDX', + 'regINTERNAL_POISON_STATUS', 'regINTERNAL_POISON_STATUS_BASE_IDX', + 'regINTR_LINE_ENABLE', 'regINTR_LINE_ENABLE_BASE_IDX', + 'regINTR_LINE_POLARITY', 'regINTR_LINE_POLARITY_BASE_IDX', + 'regL2A_UPDATE_FILTER_CNTL', 'regL2A_UPDATE_FILTER_CNTL_BASE_IDX', + 'regL2B_SDP_PARITY_ERROR_EN', + 'regL2B_SDP_PARITY_ERROR_EN_BASE_IDX', + 'regL2B_UPDATE_FILTER_CNTL', 'regL2B_UPDATE_FILTER_CNTL_BASE_IDX', + 'regL2_CONTROL_0', 'regL2_CONTROL_0_BASE_IDX', 'regL2_CONTROL_1', + 'regL2_CONTROL_1_BASE_IDX', 'regL2_CONTROL_5', + 'regL2_CONTROL_5_BASE_IDX', 'regL2_CONTROL_6', + 'regL2_CONTROL_6_BASE_IDX', 'regL2_CP_CONTROL', + 'regL2_CP_CONTROL_1', 'regL2_CP_CONTROL_1_BASE_IDX', + 'regL2_CP_CONTROL_2', 'regL2_CP_CONTROL_2_BASE_IDX', + 'regL2_CP_CONTROL_3', 'regL2_CP_CONTROL_3_BASE_IDX', + 'regL2_CP_CONTROL_BASE_IDX', 'regL2_CREDIT_CONTROL_0', + 'regL2_CREDIT_CONTROL_0_BASE_IDX', 'regL2_CREDIT_CONTROL_1', + 'regL2_CREDIT_CONTROL_1_BASE_IDX', 'regL2_DTC_CONTROL', + 'regL2_DTC_CONTROL_BASE_IDX', 'regL2_DTC_HASH_CONTROL', + 'regL2_DTC_HASH_CONTROL_BASE_IDX', 'regL2_DTC_WAY_CONTROL', + 'regL2_DTC_WAY_CONTROL_BASE_IDX', 'regL2_ECO_CNTRL_0', + 'regL2_ECO_CNTRL_0_BASE_IDX', 'regL2_ECO_CNTRL_1', + 'regL2_ECO_CNTRL_1_BASE_IDX', 'regL2_ERR_RULE_CONTROL_0', + 'regL2_ERR_RULE_CONTROL_0_BASE_IDX', 'regL2_ERR_RULE_CONTROL_1', + 'regL2_ERR_RULE_CONTROL_1_BASE_IDX', 'regL2_ERR_RULE_CONTROL_2', + 'regL2_ERR_RULE_CONTROL_2_BASE_IDX', 'regL2_ERR_RULE_CONTROL_3', + 'regL2_ERR_RULE_CONTROL_3_BASE_IDX', 'regL2_ERR_RULE_CONTROL_4', + 'regL2_ERR_RULE_CONTROL_4_BASE_IDX', 'regL2_ERR_RULE_CONTROL_5', + 'regL2_ERR_RULE_CONTROL_5_BASE_IDX', 'regL2_ITC_CONTROL', + 'regL2_ITC_CONTROL_BASE_IDX', 'regL2_ITC_HASH_CONTROL', + 'regL2_ITC_HASH_CONTROL_BASE_IDX', 'regL2_ITC_WAY_CONTROL', + 'regL2_ITC_WAY_CONTROL_BASE_IDX', 'regL2_L2A_CK_GATE_CONTROL', + 'regL2_L2A_CK_GATE_CONTROL_BASE_IDX', 'regL2_L2A_PGSIZE_CONTROL', + 'regL2_L2A_PGSIZE_CONTROL_BASE_IDX', 'regL2_L2B_CK_GATE_CONTROL', + 'regL2_L2B_CK_GATE_CONTROL_BASE_IDX', 'regL2_L2B_PGSIZE_CONTROL', + 'regL2_L2B_PGSIZE_CONTROL_BASE_IDX', 'regL2_PDC_CONTROL', + 'regL2_PDC_CONTROL_BASE_IDX', 'regL2_PDC_HASH_CONTROL', + 'regL2_PDC_HASH_CONTROL_BASE_IDX', 'regL2_PDC_WAY_CONTROL', + 'regL2_PDC_WAY_CONTROL_BASE_IDX', 'regL2_PERF_CNTL_0', + 'regL2_PERF_CNTL_0_BASE_IDX', 'regL2_PERF_CNTL_1', + 'regL2_PERF_CNTL_1_BASE_IDX', 'regL2_PERF_CNTL_2', + 'regL2_PERF_CNTL_2_BASE_IDX', 'regL2_PERF_CNTL_3', + 'regL2_PERF_CNTL_3_BASE_IDX', 'regL2_PERF_COUNT_0', + 'regL2_PERF_COUNT_0_BASE_IDX', 'regL2_PERF_COUNT_1', + 'regL2_PERF_COUNT_1_BASE_IDX', 'regL2_PERF_COUNT_2', + 'regL2_PERF_COUNT_2_BASE_IDX', 'regL2_PERF_COUNT_3', + 'regL2_PERF_COUNT_3_BASE_IDX', 'regL2_PERF_COUNT_4', + 'regL2_PERF_COUNT_4_BASE_IDX', 'regL2_PERF_COUNT_5', + 'regL2_PERF_COUNT_5_BASE_IDX', 'regL2_PERF_COUNT_6', + 'regL2_PERF_COUNT_6_BASE_IDX', 'regL2_PERF_COUNT_7', + 'regL2_PERF_COUNT_7_BASE_IDX', 'regL2_PTC_A_CONTROL', + 'regL2_PTC_A_CONTROL_BASE_IDX', 'regL2_PTC_A_HASH_CONTROL', + 'regL2_PTC_A_HASH_CONTROL_BASE_IDX', 'regL2_PTC_A_WAY_CONTROL', + 'regL2_PTC_A_WAY_CONTROL_BASE_IDX', 'regL2_PWRGATE_CNTRL_REG_0', + 'regL2_PWRGATE_CNTRL_REG_0_BASE_IDX', 'regL2_PWRGATE_CNTRL_REG_3', + 'regL2_PWRGATE_CNTRL_REG_3_BASE_IDX', 'regL2_SB_LOCATION', + 'regL2_SB_LOCATION_BASE_IDX', 'regL2_STATUS_0', + 'regL2_STATUS_0_BASE_IDX', 'regL2_STATUS_1', + 'regL2_STATUS_1_BASE_IDX', 'regL2_TW_CONTROL', + 'regL2_TW_CONTROL_1', 'regL2_TW_CONTROL_1_BASE_IDX', + 'regL2_TW_CONTROL_2', 'regL2_TW_CONTROL_2_BASE_IDX', + 'regL2_TW_CONTROL_3', 'regL2_TW_CONTROL_3_BASE_IDX', + 'regL2_TW_CONTROL_BASE_IDX', 'regMCA_SMN_INT_APERTUREID', + 'regMCA_SMN_INT_APERTUREID_BASE_IDX', 'regMCA_SMN_INT_CONTROL', + 'regMCA_SMN_INT_CONTROL_BASE_IDX', 'regMCA_SMN_INT_MCM_ADDR', + 'regMCA_SMN_INT_MCM_ADDR_BASE_IDX', 'regMCA_SMN_INT_REQ_ADDR', + 'regMCA_SMN_INT_REQ_ADDR_BASE_IDX', 'regMISC_RAS_CONTROL', + 'regMISC_RAS_CONTROL_BASE_IDX', 'regMISC_SCRATCH', + 'regMISC_SCRATCH_BASE_IDX', 'regMISC_SEVERITY_CONTROL', + 'regMISC_SEVERITY_CONTROL_BASE_IDX', + 'regNBIF1PortAExtCorr_ACTION_CONTROL', + 'regNBIF1PortAExtCorr_ACTION_CONTROL_BASE_IDX', + 'regNBIF1PortAExtFatal_ACTION_CONTROL', + 'regNBIF1PortAExtFatal_ACTION_CONTROL_BASE_IDX', + 'regNBIF1PortAExtNonFatal_ACTION_CONTROL', + 'regNBIF1PortAExtNonFatal_ACTION_CONTROL_BASE_IDX', + 'regNBIF1PortAIntCorr_ACTION_CONTROL', + 'regNBIF1PortAIntCorr_ACTION_CONTROL_BASE_IDX', + 'regNBIF1PortAIntFatal_ACTION_CONTROL', + 'regNBIF1PortAIntFatal_ACTION_CONTROL_BASE_IDX', + 'regNBIF1PortAIntNonFatal_ACTION_CONTROL', + 'regNBIF1PortAIntNonFatal_ACTION_CONTROL_BASE_IDX', + 'regNBIF1PortAParityErr_ACTION_CONTROL', + 'regNBIF1PortAParityErr_ACTION_CONTROL_BASE_IDX', + 'regNBIF1PortASerr_ACTION_CONTROL', + 'regNBIF1PortASerr_ACTION_CONTROL_BASE_IDX', + 'regNBIF_DS_CTRL_LCLK', 'regNBIF_DS_CTRL_LCLK_BASE_IDX', + 'regNBIF_INTX_DSTATE_MISC_CNTL', + 'regNBIF_INTX_DSTATE_MISC_CNTL_BASE_IDX', + 'regNBIF_MGCG_CTRL_LCLK', 'regNBIF_MGCG_CTRL_LCLK_BASE_IDX', + 'regNBIF_PENDING_MISC_CNTL', 'regNBIF_PENDING_MISC_CNTL_BASE_IDX', + 'regNBIF_PGMST_CTRL', 'regNBIF_PGMST_CTRL_BASE_IDX', + 'regNBIF_PGSLV_CTRL', 'regNBIF_PGSLV_CTRL_BASE_IDX', + 'regNBIF_PG_MISC_CTRL', 'regNBIF_PG_MISC_CTRL_BASE_IDX', + 'regNBIF_PWRBRK_REQUEST', 'regNBIF_PWRBRK_REQUEST_BASE_IDX', + 'regNBIF_REGIF_ERRSET_CTRL', 'regNBIF_REGIF_ERRSET_CTRL_BASE_IDX', + 'regNBIF_RRMT_CNTL', 'regNBIF_RRMT_CNTL_BASE_IDX', + 'regNBIF_SDP_VWR_VCHG_DIS_CTRL', + 'regNBIF_SDP_VWR_VCHG_DIS_CTRL_BASE_IDX', + 'regNBIF_SDP_VWR_VCHG_RST_CTRL0', + 'regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX', + 'regNBIF_SDP_VWR_VCHG_RST_CTRL1', + 'regNBIF_SDP_VWR_VCHG_RST_CTRL1_BASE_IDX', + 'regNBIF_SDP_VWR_VCHG_TRIG', 'regNBIF_SDP_VWR_VCHG_TRIG_BASE_IDX', + 'regNBIF_SHUB_TODET_CLIENT_CTRL', + 'regNBIF_SHUB_TODET_CLIENT_CTRL2', + 'regNBIF_SHUB_TODET_CLIENT_CTRL2_BASE_IDX', + 'regNBIF_SHUB_TODET_CLIENT_CTRL_BASE_IDX', + 'regNBIF_SHUB_TODET_CLIENT_STATUS', + 'regNBIF_SHUB_TODET_CLIENT_STATUS2', + 'regNBIF_SHUB_TODET_CLIENT_STATUS2_BASE_IDX', + 'regNBIF_SHUB_TODET_CLIENT_STATUS_BASE_IDX', + 'regNBIF_SHUB_TODET_CTRL', 'regNBIF_SHUB_TODET_CTRL_BASE_IDX', + 'regNBIF_SHUB_TODET_SYNCFLOOD_CTRL', + 'regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2', + 'regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2_BASE_IDX', + 'regNBIF_SHUB_TODET_SYNCFLOOD_CTRL_BASE_IDX', + 'regNBIF_SMN_VWR_VCHG_DIS_CTRL', + 'regNBIF_SMN_VWR_VCHG_DIS_CTRL_1', + 'regNBIF_SMN_VWR_VCHG_DIS_CTRL_1_BASE_IDX', + 'regNBIF_SMN_VWR_VCHG_DIS_CTRL_BASE_IDX', + 'regNBIF_SMN_VWR_VCHG_RST_CTRL0', + 'regNBIF_SMN_VWR_VCHG_RST_CTRL0_BASE_IDX', + 'regNBIF_SMN_VWR_VCHG_TRIG', 'regNBIF_SMN_VWR_VCHG_TRIG_BASE_IDX', + 'regNBIF_SMN_VWR_WTRIG_CNTL', + 'regNBIF_SMN_VWR_WTRIG_CNTL_BASE_IDX', 'regNBIF_STRAP_BIOS_CNTL', + 'regNBIF_STRAP_BIOS_CNTL_BASE_IDX', 'regNBIF_STRAP_WRITE_CTRL', + 'regNBIF_STRAP_WRITE_CTRL_BASE_IDX', 'regNBIF_VWIRE_CTRL', + 'regNBIF_VWIRE_CTRL_BASE_IDX', 'regNBIO_LCLK_DS_MASK', + 'regNBIO_LCLK_DS_MASK_BASE_IDX', 'regNB_BUS_NUM_CNTL', + 'regNB_BUS_NUM_CNTL_BASE_IDX', 'regNB_CNTL', + 'regNB_CNTL_BASE_IDX', 'regNB_DRAM3_BASE', + 'regNB_DRAM3_BASE_BASE_IDX', + 'regNB_INTSBDEVINDCFG0_STEERING_CNTL', + 'regNB_INTSBDEVINDCFG0_STEERING_CNTL_BASE_IDX', + 'regNB_LOWER_DRAM2_BASE', 'regNB_LOWER_DRAM2_BASE_BASE_IDX', + 'regNB_LOWER_TOP_OF_DRAM2', 'regNB_LOWER_TOP_OF_DRAM2_BASE_IDX', + 'regNB_MMIOBASE', 'regNB_MMIOBASE_BASE_IDX', 'regNB_MMIOLIMIT', + 'regNB_MMIOLIMIT_BASE_IDX', 'regNB_NBCFG0_NBCFG_SCRATCH_4', + 'regNB_NBCFG0_NBCFG_SCRATCH_4_BASE_IDX', + 'regNB_NBIF1DEVINDCFG0_STEERING_CNTL', + 'regNB_NBIF1DEVINDCFG0_STEERING_CNTL_BASE_IDX', + 'regNB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA', + 'regNB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA_BASE_IDX', + 'regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX', + 'regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_BASE_IDX', + 'regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION', + 'regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION_BASE_IDX', + 'regNB_PCIE0DEVINDCFG0_STEERING_CNTL', + 'regNB_PCIE0DEVINDCFG0_STEERING_CNTL_BASE_IDX', + 'regNB_PCIE0DEVINDCFG1_STEERING_CNTL', + 'regNB_PCIE0DEVINDCFG1_STEERING_CNTL_BASE_IDX', + 'regNB_PCIE0DEVINDCFG2_STEERING_CNTL', + 'regNB_PCIE0DEVINDCFG2_STEERING_CNTL_BASE_IDX', + 'regNB_PCIE0DEVINDCFG3_STEERING_CNTL', + 'regNB_PCIE0DEVINDCFG3_STEERING_CNTL_BASE_IDX', + 'regNB_PCIE0DEVINDCFG4_STEERING_CNTL', + 'regNB_PCIE0DEVINDCFG4_STEERING_CNTL_BASE_IDX', + 'regNB_PCIE0DEVINDCFG5_STEERING_CNTL', + 'regNB_PCIE0DEVINDCFG5_STEERING_CNTL_BASE_IDX', + 'regNB_PCIE0DEVINDCFG6_STEERING_CNTL', + 'regNB_PCIE0DEVINDCFG6_STEERING_CNTL_BASE_IDX', + 'regNB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA', + 'regNB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA_BASE_IDX', + 'regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX', + 'regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_BASE_IDX', + 'regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION', + 'regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION_BASE_IDX', + 'regNB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA', + 'regNB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA_BASE_IDX', + 'regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX', + 'regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_BASE_IDX', + 'regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION', + 'regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION_BASE_IDX', + 'regNB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA', + 'regNB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA_BASE_IDX', + 'regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX', + 'regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_BASE_IDX', + 'regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION', + 'regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION_BASE_IDX', + 'regNB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA', + 'regNB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA_BASE_IDX', + 'regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX', + 'regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_BASE_IDX', + 'regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION', + 'regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION_BASE_IDX', + 'regNB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA', + 'regNB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA_BASE_IDX', + 'regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX', + 'regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_BASE_IDX', + 'regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION', + 'regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION_BASE_IDX', + 'regNB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA', + 'regNB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA_BASE_IDX', + 'regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX', + 'regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_BASE_IDX', + 'regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION', + 'regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION_BASE_IDX', + 'regNB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA', + 'regNB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA_BASE_IDX', + 'regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX', + 'regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_BASE_IDX', + 'regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION', + 'regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION_BASE_IDX', + 'regNB_PROG_DEVICE_REMAP_PBr0', + 'regNB_PROG_DEVICE_REMAP_PBr0_BASE_IDX', + 'regNB_PROG_DEVICE_REMAP_PBr1', 'regNB_PROG_DEVICE_REMAP_PBr10', + 'regNB_PROG_DEVICE_REMAP_PBr10_BASE_IDX', + 'regNB_PROG_DEVICE_REMAP_PBr11', + 'regNB_PROG_DEVICE_REMAP_PBr11_BASE_IDX', + 'regNB_PROG_DEVICE_REMAP_PBr12', + 'regNB_PROG_DEVICE_REMAP_PBr12_BASE_IDX', + 'regNB_PROG_DEVICE_REMAP_PBr13', + 'regNB_PROG_DEVICE_REMAP_PBr13_BASE_IDX', + 'regNB_PROG_DEVICE_REMAP_PBr1_BASE_IDX', + 'regNB_PROG_DEVICE_REMAP_PBr2', + 'regNB_PROG_DEVICE_REMAP_PBr2_BASE_IDX', + 'regNB_PROG_DEVICE_REMAP_PBr3', + 'regNB_PROG_DEVICE_REMAP_PBr3_BASE_IDX', + 'regNB_PROG_DEVICE_REMAP_PBr4', + 'regNB_PROG_DEVICE_REMAP_PBr4_BASE_IDX', + 'regNB_PROG_DEVICE_REMAP_PBr5', + 'regNB_PROG_DEVICE_REMAP_PBr5_BASE_IDX', + 'regNB_PROG_DEVICE_REMAP_PBr6', + 'regNB_PROG_DEVICE_REMAP_PBr6_BASE_IDX', + 'regNB_PROG_DEVICE_REMAP_PBr7', + 'regNB_PROG_DEVICE_REMAP_PBr7_BASE_IDX', + 'regNB_PROG_DEVICE_REMAP_PBr8', + 'regNB_PROG_DEVICE_REMAP_PBr8_BASE_IDX', 'regNB_REVID', + 'regNB_REVID_BASE_IDX', 'regNB_SPARE1', 'regNB_SPARE1_BASE_IDX', + 'regNB_SPARE2', 'regNB_SPARE2_BASE_IDX', 'regNB_TOP_OF_DRAM3', + 'regNB_TOP_OF_DRAM3_BASE_IDX', 'regNB_UPPER_DRAM2_BASE', + 'regNB_UPPER_DRAM2_BASE_BASE_IDX', 'regNB_UPPER_TOP_OF_DRAM2', + 'regNB_UPPER_TOP_OF_DRAM2_BASE_IDX', 'regNIC400_1_ASIB_0_FN_MOD', + 'regNIC400_1_ASIB_0_FN_MOD_BASE_IDX', 'regNIC400_1_IB_0_FN_MOD', + 'regNIC400_1_IB_0_FN_MOD_BASE_IDX', 'regNIC400_2_ASIB_0_AR_B', + 'regNIC400_2_ASIB_0_AR_B_BASE_IDX', 'regNIC400_2_ASIB_0_AR_P', + 'regNIC400_2_ASIB_0_AR_P_BASE_IDX', 'regNIC400_2_ASIB_0_AR_R', + 'regNIC400_2_ASIB_0_AR_R_BASE_IDX', 'regNIC400_2_ASIB_0_AW_B', + 'regNIC400_2_ASIB_0_AW_B_BASE_IDX', 'regNIC400_2_ASIB_0_AW_P', + 'regNIC400_2_ASIB_0_AW_P_BASE_IDX', 'regNIC400_2_ASIB_0_AW_R', + 'regNIC400_2_ASIB_0_AW_R_BASE_IDX', 'regNIC400_2_ASIB_0_FN_MOD', + 'regNIC400_2_ASIB_0_FN_MOD_BASE_IDX', 'regNIC400_2_ASIB_0_KI_FC', + 'regNIC400_2_ASIB_0_KI_FC_BASE_IDX', + 'regNIC400_2_ASIB_0_MAX_COMB_OT', + 'regNIC400_2_ASIB_0_MAX_COMB_OT_BASE_IDX', + 'regNIC400_2_ASIB_0_MAX_OT', 'regNIC400_2_ASIB_0_MAX_OT_BASE_IDX', + 'regNIC400_2_ASIB_0_QOS_CNTL', + 'regNIC400_2_ASIB_0_QOS_CNTL_BASE_IDX', + 'regNIC400_2_ASIB_0_QOS_RANGE', + 'regNIC400_2_ASIB_0_QOS_RANGE_BASE_IDX', + 'regNIC400_2_ASIB_0_TARGET_FC', + 'regNIC400_2_ASIB_0_TARGET_FC_BASE_IDX', + 'regNIC400_2_ASIB_1_AR_B', 'regNIC400_2_ASIB_1_AR_B_BASE_IDX', + 'regNIC400_2_ASIB_1_AR_P', 'regNIC400_2_ASIB_1_AR_P_BASE_IDX', + 'regNIC400_2_ASIB_1_AR_R', 'regNIC400_2_ASIB_1_AR_R_BASE_IDX', + 'regNIC400_2_ASIB_1_AW_B', 'regNIC400_2_ASIB_1_AW_B_BASE_IDX', + 'regNIC400_2_ASIB_1_AW_P', 'regNIC400_2_ASIB_1_AW_P_BASE_IDX', + 'regNIC400_2_ASIB_1_AW_R', 'regNIC400_2_ASIB_1_AW_R_BASE_IDX', + 'regNIC400_2_ASIB_1_FN_MOD', 'regNIC400_2_ASIB_1_FN_MOD_BASE_IDX', + 'regNIC400_2_ASIB_1_KI_FC', 'regNIC400_2_ASIB_1_KI_FC_BASE_IDX', + 'regNIC400_2_ASIB_1_MAX_COMB_OT', + 'regNIC400_2_ASIB_1_MAX_COMB_OT_BASE_IDX', + 'regNIC400_2_ASIB_1_MAX_OT', 'regNIC400_2_ASIB_1_MAX_OT_BASE_IDX', + 'regNIC400_2_ASIB_1_QOS_CNTL', + 'regNIC400_2_ASIB_1_QOS_CNTL_BASE_IDX', + 'regNIC400_2_ASIB_1_QOS_RANGE', + 'regNIC400_2_ASIB_1_QOS_RANGE_BASE_IDX', + 'regNIC400_2_ASIB_1_TARGET_FC', + 'regNIC400_2_ASIB_1_TARGET_FC_BASE_IDX', + 'regNIC400_2_IB_0_FN_MOD', 'regNIC400_2_IB_0_FN_MOD_BASE_IDX', + 'regNMI_STATUS', 'regNMI_STATUS_BASE_IDX', + 'regNP_DMA_DROPPED_LOG_LOWER', + 'regNP_DMA_DROPPED_LOG_LOWER_BASE_IDX', + 'regNP_DMA_DROPPED_LOG_UPPER', + 'regNP_DMA_DROPPED_LOG_UPPER_BASE_IDX', 'regOUTSTANDING_VC_ALLOC', + 'regOUTSTANDING_VC_ALLOC_BASE_IDX', 'regPARITY_CONTROL_0', + 'regPARITY_CONTROL_0_BASE_IDX', 'regPARITY_CONTROL_1', + 'regPARITY_CONTROL_1_BASE_IDX', 'regPARITY_COUNTER_CORR_GRP0', + 'regPARITY_COUNTER_CORR_GRP0_BASE_IDX', + 'regPARITY_COUNTER_CORR_GRP1', 'regPARITY_COUNTER_CORR_GRP10', + 'regPARITY_COUNTER_CORR_GRP10_BASE_IDX', + 'regPARITY_COUNTER_CORR_GRP11', + 'regPARITY_COUNTER_CORR_GRP11_BASE_IDX', + 'regPARITY_COUNTER_CORR_GRP12', + 'regPARITY_COUNTER_CORR_GRP12_BASE_IDX', + 'regPARITY_COUNTER_CORR_GRP13', + 'regPARITY_COUNTER_CORR_GRP13_BASE_IDX', + 'regPARITY_COUNTER_CORR_GRP14', + 'regPARITY_COUNTER_CORR_GRP14_BASE_IDX', + 'regPARITY_COUNTER_CORR_GRP15', + 'regPARITY_COUNTER_CORR_GRP15_BASE_IDX', + 'regPARITY_COUNTER_CORR_GRP16', + 'regPARITY_COUNTER_CORR_GRP16_BASE_IDX', + 'regPARITY_COUNTER_CORR_GRP17', + 'regPARITY_COUNTER_CORR_GRP17_BASE_IDX', + 'regPARITY_COUNTER_CORR_GRP1_BASE_IDX', + 'regPARITY_COUNTER_CORR_GRP2', + 'regPARITY_COUNTER_CORR_GRP2_BASE_IDX', + 'regPARITY_COUNTER_CORR_GRP3', + 'regPARITY_COUNTER_CORR_GRP3_BASE_IDX', + 'regPARITY_COUNTER_CORR_GRP4', + 'regPARITY_COUNTER_CORR_GRP4_BASE_IDX', + 'regPARITY_COUNTER_CORR_GRP5', + 'regPARITY_COUNTER_CORR_GRP5_BASE_IDX', + 'regPARITY_COUNTER_CORR_GRP6', + 'regPARITY_COUNTER_CORR_GRP6_BASE_IDX', + 'regPARITY_COUNTER_CORR_GRP7', + 'regPARITY_COUNTER_CORR_GRP7_BASE_IDX', + 'regPARITY_COUNTER_UCP_GRP0', + 'regPARITY_COUNTER_UCP_GRP0_BASE_IDX', + 'regPARITY_COUNTER_UCP_GRP1', 'regPARITY_COUNTER_UCP_GRP10', + 'regPARITY_COUNTER_UCP_GRP10_BASE_IDX', + 'regPARITY_COUNTER_UCP_GRP11', + 'regPARITY_COUNTER_UCP_GRP11_BASE_IDX', + 'regPARITY_COUNTER_UCP_GRP12', + 'regPARITY_COUNTER_UCP_GRP12_BASE_IDX', + 'regPARITY_COUNTER_UCP_GRP1_BASE_IDX', + 'regPARITY_COUNTER_UCP_GRP2', + 'regPARITY_COUNTER_UCP_GRP2_BASE_IDX', + 'regPARITY_COUNTER_UCP_GRP3', + 'regPARITY_COUNTER_UCP_GRP3_BASE_IDX', + 'regPARITY_COUNTER_UCP_GRP4', + 'regPARITY_COUNTER_UCP_GRP4_BASE_IDX', + 'regPARITY_COUNTER_UCP_GRP5', + 'regPARITY_COUNTER_UCP_GRP5_BASE_IDX', + 'regPARITY_COUNTER_UCP_GRP6', + 'regPARITY_COUNTER_UCP_GRP6_BASE_IDX', + 'regPARITY_COUNTER_UCP_GRP7', + 'regPARITY_COUNTER_UCP_GRP7_BASE_IDX', + 'regPARITY_ERROR_STATUS_CORR_GRP0', + 'regPARITY_ERROR_STATUS_CORR_GRP0_BASE_IDX', + 'regPARITY_ERROR_STATUS_CORR_GRP1', + 'regPARITY_ERROR_STATUS_CORR_GRP10', + 'regPARITY_ERROR_STATUS_CORR_GRP10_BASE_IDX', + 'regPARITY_ERROR_STATUS_CORR_GRP11', + 'regPARITY_ERROR_STATUS_CORR_GRP11_BASE_IDX', + 'regPARITY_ERROR_STATUS_CORR_GRP12', + 'regPARITY_ERROR_STATUS_CORR_GRP12_BASE_IDX', + 'regPARITY_ERROR_STATUS_CORR_GRP13', + 'regPARITY_ERROR_STATUS_CORR_GRP13_BASE_IDX', + 'regPARITY_ERROR_STATUS_CORR_GRP14', + 'regPARITY_ERROR_STATUS_CORR_GRP14_BASE_IDX', + 'regPARITY_ERROR_STATUS_CORR_GRP15', + 'regPARITY_ERROR_STATUS_CORR_GRP15_BASE_IDX', + 'regPARITY_ERROR_STATUS_CORR_GRP16', + 'regPARITY_ERROR_STATUS_CORR_GRP16_BASE_IDX', + 'regPARITY_ERROR_STATUS_CORR_GRP17', + 'regPARITY_ERROR_STATUS_CORR_GRP17_BASE_IDX', + 'regPARITY_ERROR_STATUS_CORR_GRP1_BASE_IDX', + 'regPARITY_ERROR_STATUS_CORR_GRP2', + 'regPARITY_ERROR_STATUS_CORR_GRP2_BASE_IDX', + 'regPARITY_ERROR_STATUS_CORR_GRP3', + 'regPARITY_ERROR_STATUS_CORR_GRP3_BASE_IDX', + 'regPARITY_ERROR_STATUS_CORR_GRP4', + 'regPARITY_ERROR_STATUS_CORR_GRP4_BASE_IDX', + 'regPARITY_ERROR_STATUS_CORR_GRP5', + 'regPARITY_ERROR_STATUS_CORR_GRP5_BASE_IDX', + 'regPARITY_ERROR_STATUS_CORR_GRP6', + 'regPARITY_ERROR_STATUS_CORR_GRP6_BASE_IDX', + 'regPARITY_ERROR_STATUS_CORR_GRP7', + 'regPARITY_ERROR_STATUS_CORR_GRP7_BASE_IDX', + 'regPARITY_ERROR_STATUS_UCP_GRP0', + 'regPARITY_ERROR_STATUS_UCP_GRP0_BASE_IDX', + 'regPARITY_ERROR_STATUS_UCP_GRP1', + 'regPARITY_ERROR_STATUS_UCP_GRP10', + 'regPARITY_ERROR_STATUS_UCP_GRP10_BASE_IDX', + 'regPARITY_ERROR_STATUS_UCP_GRP11', + 'regPARITY_ERROR_STATUS_UCP_GRP11_BASE_IDX', + 'regPARITY_ERROR_STATUS_UCP_GRP12', + 'regPARITY_ERROR_STATUS_UCP_GRP12_BASE_IDX', + 'regPARITY_ERROR_STATUS_UCP_GRP1_BASE_IDX', + 'regPARITY_ERROR_STATUS_UCP_GRP2', + 'regPARITY_ERROR_STATUS_UCP_GRP2_BASE_IDX', + 'regPARITY_ERROR_STATUS_UCP_GRP3', + 'regPARITY_ERROR_STATUS_UCP_GRP3_BASE_IDX', + 'regPARITY_ERROR_STATUS_UCP_GRP4', + 'regPARITY_ERROR_STATUS_UCP_GRP4_BASE_IDX', + 'regPARITY_ERROR_STATUS_UCP_GRP5', + 'regPARITY_ERROR_STATUS_UCP_GRP5_BASE_IDX', + 'regPARITY_ERROR_STATUS_UCP_GRP6', + 'regPARITY_ERROR_STATUS_UCP_GRP6_BASE_IDX', + 'regPARITY_ERROR_STATUS_UCP_GRP7', + 'regPARITY_ERROR_STATUS_UCP_GRP7_BASE_IDX', + 'regPARITY_ERROR_STATUS_UNCORR_GRP0', + 'regPARITY_ERROR_STATUS_UNCORR_GRP0_BASE_IDX', + 'regPARITY_ERROR_STATUS_UNCORR_GRP1', + 'regPARITY_ERROR_STATUS_UNCORR_GRP10', + 'regPARITY_ERROR_STATUS_UNCORR_GRP10_BASE_IDX', + 'regPARITY_ERROR_STATUS_UNCORR_GRP11', + 'regPARITY_ERROR_STATUS_UNCORR_GRP11_BASE_IDX', + 'regPARITY_ERROR_STATUS_UNCORR_GRP12', + 'regPARITY_ERROR_STATUS_UNCORR_GRP12_BASE_IDX', + 'regPARITY_ERROR_STATUS_UNCORR_GRP13', + 'regPARITY_ERROR_STATUS_UNCORR_GRP13_BASE_IDX', + 'regPARITY_ERROR_STATUS_UNCORR_GRP14', + 'regPARITY_ERROR_STATUS_UNCORR_GRP14_BASE_IDX', + 'regPARITY_ERROR_STATUS_UNCORR_GRP15', + 'regPARITY_ERROR_STATUS_UNCORR_GRP15_BASE_IDX', + 'regPARITY_ERROR_STATUS_UNCORR_GRP16', + 'regPARITY_ERROR_STATUS_UNCORR_GRP16_BASE_IDX', + 'regPARITY_ERROR_STATUS_UNCORR_GRP1_BASE_IDX', + 'regPARITY_ERROR_STATUS_UNCORR_GRP2', + 'regPARITY_ERROR_STATUS_UNCORR_GRP2_BASE_IDX', + 'regPARITY_ERROR_STATUS_UNCORR_GRP3', + 'regPARITY_ERROR_STATUS_UNCORR_GRP3_BASE_IDX', + 'regPARITY_ERROR_STATUS_UNCORR_GRP4', + 'regPARITY_ERROR_STATUS_UNCORR_GRP4_BASE_IDX', + 'regPARITY_ERROR_STATUS_UNCORR_GRP5', + 'regPARITY_ERROR_STATUS_UNCORR_GRP5_BASE_IDX', + 'regPARITY_ERROR_STATUS_UNCORR_GRP6', + 'regPARITY_ERROR_STATUS_UNCORR_GRP6_BASE_IDX', + 'regPARITY_ERROR_STATUS_UNCORR_GRP7', + 'regPARITY_ERROR_STATUS_UNCORR_GRP7_BASE_IDX', + 'regPARITY_SEVERITY_CONTROL_CORR_0', + 'regPARITY_SEVERITY_CONTROL_CORR_0_BASE_IDX', + 'regPARITY_SEVERITY_CONTROL_UCP_0', + 'regPARITY_SEVERITY_CONTROL_UCP_0_BASE_IDX', + 'regPARITY_SEVERITY_CONTROL_UNCORR_0', + 'regPARITY_SEVERITY_CONTROL_UNCORR_0_BASE_IDX', + 'regPCIE0PortAExtCorr_ACTION_CONTROL', + 'regPCIE0PortAExtCorr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortAExtFatal_ACTION_CONTROL', + 'regPCIE0PortAExtFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortAExtNonFatal_ACTION_CONTROL', + 'regPCIE0PortAExtNonFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortAIntCorr_ACTION_CONTROL', + 'regPCIE0PortAIntCorr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortAIntFatal_ACTION_CONTROL', + 'regPCIE0PortAIntFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortAIntNonFatal_ACTION_CONTROL', + 'regPCIE0PortAIntNonFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortAParityErr_ACTION_CONTROL', + 'regPCIE0PortAParityErr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortASerr_ACTION_CONTROL', + 'regPCIE0PortASerr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortBExtCorr_ACTION_CONTROL', + 'regPCIE0PortBExtCorr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortBExtFatal_ACTION_CONTROL', + 'regPCIE0PortBExtFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortBExtNonFatal_ACTION_CONTROL', + 'regPCIE0PortBExtNonFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortBIntCorr_ACTION_CONTROL', + 'regPCIE0PortBIntCorr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortBIntFatal_ACTION_CONTROL', + 'regPCIE0PortBIntFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortBIntNonFatal_ACTION_CONTROL', + 'regPCIE0PortBIntNonFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortBParityErr_ACTION_CONTROL', + 'regPCIE0PortBParityErr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortBSerr_ACTION_CONTROL', + 'regPCIE0PortBSerr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortCExtCorr_ACTION_CONTROL', + 'regPCIE0PortCExtCorr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortCExtFatal_ACTION_CONTROL', + 'regPCIE0PortCExtFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortCExtNonFatal_ACTION_CONTROL', + 'regPCIE0PortCExtNonFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortCIntCorr_ACTION_CONTROL', + 'regPCIE0PortCIntCorr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortCIntFatal_ACTION_CONTROL', + 'regPCIE0PortCIntFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortCIntNonFatal_ACTION_CONTROL', + 'regPCIE0PortCIntNonFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortCParityErr_ACTION_CONTROL', + 'regPCIE0PortCParityErr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortCSerr_ACTION_CONTROL', + 'regPCIE0PortCSerr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortDExtCorr_ACTION_CONTROL', + 'regPCIE0PortDExtCorr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortDExtFatal_ACTION_CONTROL', + 'regPCIE0PortDExtFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortDExtNonFatal_ACTION_CONTROL', + 'regPCIE0PortDExtNonFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortDIntCorr_ACTION_CONTROL', + 'regPCIE0PortDIntCorr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortDIntFatal_ACTION_CONTROL', + 'regPCIE0PortDIntFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortDIntNonFatal_ACTION_CONTROL', + 'regPCIE0PortDIntNonFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortDParityErr_ACTION_CONTROL', + 'regPCIE0PortDParityErr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortDSerr_ACTION_CONTROL', + 'regPCIE0PortDSerr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortEExtCorr_ACTION_CONTROL', + 'regPCIE0PortEExtCorr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortEExtFatal_ACTION_CONTROL', + 'regPCIE0PortEExtFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortEExtNonFatal_ACTION_CONTROL', + 'regPCIE0PortEExtNonFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortEIntCorr_ACTION_CONTROL', + 'regPCIE0PortEIntCorr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortEIntFatal_ACTION_CONTROL', + 'regPCIE0PortEIntFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortEIntNonFatal_ACTION_CONTROL', + 'regPCIE0PortEIntNonFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortEParityErr_ACTION_CONTROL', + 'regPCIE0PortEParityErr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortESerr_ACTION_CONTROL', + 'regPCIE0PortESerr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortFExtCorr_ACTION_CONTROL', + 'regPCIE0PortFExtCorr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortFExtFatal_ACTION_CONTROL', + 'regPCIE0PortFExtFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortFExtNonFatal_ACTION_CONTROL', + 'regPCIE0PortFExtNonFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortFIntCorr_ACTION_CONTROL', + 'regPCIE0PortFIntCorr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortFIntFatal_ACTION_CONTROL', + 'regPCIE0PortFIntFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortFIntNonFatal_ACTION_CONTROL', + 'regPCIE0PortFIntNonFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortFParityErr_ACTION_CONTROL', + 'regPCIE0PortFParityErr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortFSerr_ACTION_CONTROL', + 'regPCIE0PortFSerr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortGExtCorr_ACTION_CONTROL', + 'regPCIE0PortGExtCorr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortGExtFatal_ACTION_CONTROL', + 'regPCIE0PortGExtFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortGExtNonFatal_ACTION_CONTROL', + 'regPCIE0PortGExtNonFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortGIntCorr_ACTION_CONTROL', + 'regPCIE0PortGIntCorr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortGIntFatal_ACTION_CONTROL', + 'regPCIE0PortGIntFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortGIntNonFatal_ACTION_CONTROL', + 'regPCIE0PortGIntNonFatal_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortGParityErr_ACTION_CONTROL', + 'regPCIE0PortGParityErr_ACTION_CONTROL_BASE_IDX', + 'regPCIE0PortGSerr_ACTION_CONTROL', + 'regPCIE0PortGSerr_ACTION_CONTROL_BASE_IDX', 'regPCIEMSIX_PBA_0', + 'regPCIEMSIX_PBA_0_BASE_IDX', 'regPCIEMSIX_PBA_1', + 'regPCIEMSIX_PBA_1_BASE_IDX', 'regPCIEMSIX_PBA_2', + 'regPCIEMSIX_PBA_2_BASE_IDX', 'regPCIEMSIX_PBA_3', + 'regPCIEMSIX_PBA_3_BASE_IDX', 'regPCIEMSIX_PBA_4', + 'regPCIEMSIX_PBA_4_BASE_IDX', 'regPCIEMSIX_PBA_5', + 'regPCIEMSIX_PBA_5_BASE_IDX', 'regPCIEMSIX_PBA_6', + 'regPCIEMSIX_PBA_6_BASE_IDX', 'regPCIEMSIX_PBA_7', + 'regPCIEMSIX_PBA_7_BASE_IDX', 'regPCIEMSIX_VECT0_ADDR_HI', + 'regPCIEMSIX_VECT0_ADDR_HI_BASE_IDX', 'regPCIEMSIX_VECT0_ADDR_LO', + 'regPCIEMSIX_VECT0_ADDR_LO_BASE_IDX', 'regPCIEMSIX_VECT0_CONTROL', + 'regPCIEMSIX_VECT0_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT0_MSG_DATA', + 'regPCIEMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT100_ADDR_HI', + 'regPCIEMSIX_VECT100_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT100_ADDR_LO', + 'regPCIEMSIX_VECT100_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT100_CONTROL', + 'regPCIEMSIX_VECT100_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT100_MSG_DATA', + 'regPCIEMSIX_VECT100_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT101_ADDR_HI', + 'regPCIEMSIX_VECT101_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT101_ADDR_LO', + 'regPCIEMSIX_VECT101_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT101_CONTROL', + 'regPCIEMSIX_VECT101_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT101_MSG_DATA', + 'regPCIEMSIX_VECT101_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT102_ADDR_HI', + 'regPCIEMSIX_VECT102_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT102_ADDR_LO', + 'regPCIEMSIX_VECT102_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT102_CONTROL', + 'regPCIEMSIX_VECT102_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT102_MSG_DATA', + 'regPCIEMSIX_VECT102_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT103_ADDR_HI', + 'regPCIEMSIX_VECT103_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT103_ADDR_LO', + 'regPCIEMSIX_VECT103_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT103_CONTROL', + 'regPCIEMSIX_VECT103_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT103_MSG_DATA', + 'regPCIEMSIX_VECT103_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT104_ADDR_HI', + 'regPCIEMSIX_VECT104_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT104_ADDR_LO', + 'regPCIEMSIX_VECT104_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT104_CONTROL', + 'regPCIEMSIX_VECT104_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT104_MSG_DATA', + 'regPCIEMSIX_VECT104_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT105_ADDR_HI', + 'regPCIEMSIX_VECT105_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT105_ADDR_LO', + 'regPCIEMSIX_VECT105_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT105_CONTROL', + 'regPCIEMSIX_VECT105_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT105_MSG_DATA', + 'regPCIEMSIX_VECT105_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT106_ADDR_HI', + 'regPCIEMSIX_VECT106_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT106_ADDR_LO', + 'regPCIEMSIX_VECT106_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT106_CONTROL', + 'regPCIEMSIX_VECT106_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT106_MSG_DATA', + 'regPCIEMSIX_VECT106_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT107_ADDR_HI', + 'regPCIEMSIX_VECT107_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT107_ADDR_LO', + 'regPCIEMSIX_VECT107_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT107_CONTROL', + 'regPCIEMSIX_VECT107_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT107_MSG_DATA', + 'regPCIEMSIX_VECT107_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT108_ADDR_HI', + 'regPCIEMSIX_VECT108_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT108_ADDR_LO', + 'regPCIEMSIX_VECT108_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT108_CONTROL', + 'regPCIEMSIX_VECT108_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT108_MSG_DATA', + 'regPCIEMSIX_VECT108_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT109_ADDR_HI', + 'regPCIEMSIX_VECT109_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT109_ADDR_LO', + 'regPCIEMSIX_VECT109_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT109_CONTROL', + 'regPCIEMSIX_VECT109_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT109_MSG_DATA', + 'regPCIEMSIX_VECT109_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT10_ADDR_HI', + 'regPCIEMSIX_VECT10_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT10_ADDR_LO', + 'regPCIEMSIX_VECT10_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT10_CONTROL', + 'regPCIEMSIX_VECT10_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT10_MSG_DATA', + 'regPCIEMSIX_VECT10_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT110_ADDR_HI', + 'regPCIEMSIX_VECT110_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT110_ADDR_LO', + 'regPCIEMSIX_VECT110_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT110_CONTROL', + 'regPCIEMSIX_VECT110_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT110_MSG_DATA', + 'regPCIEMSIX_VECT110_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT111_ADDR_HI', + 'regPCIEMSIX_VECT111_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT111_ADDR_LO', + 'regPCIEMSIX_VECT111_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT111_CONTROL', + 'regPCIEMSIX_VECT111_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT111_MSG_DATA', + 'regPCIEMSIX_VECT111_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT112_ADDR_HI', + 'regPCIEMSIX_VECT112_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT112_ADDR_LO', + 'regPCIEMSIX_VECT112_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT112_CONTROL', + 'regPCIEMSIX_VECT112_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT112_MSG_DATA', + 'regPCIEMSIX_VECT112_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT113_ADDR_HI', + 'regPCIEMSIX_VECT113_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT113_ADDR_LO', + 'regPCIEMSIX_VECT113_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT113_CONTROL', + 'regPCIEMSIX_VECT113_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT113_MSG_DATA', + 'regPCIEMSIX_VECT113_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT114_ADDR_HI', + 'regPCIEMSIX_VECT114_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT114_ADDR_LO', + 'regPCIEMSIX_VECT114_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT114_CONTROL', + 'regPCIEMSIX_VECT114_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT114_MSG_DATA', + 'regPCIEMSIX_VECT114_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT115_ADDR_HI', + 'regPCIEMSIX_VECT115_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT115_ADDR_LO', + 'regPCIEMSIX_VECT115_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT115_CONTROL', + 'regPCIEMSIX_VECT115_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT115_MSG_DATA', + 'regPCIEMSIX_VECT115_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT116_ADDR_HI', + 'regPCIEMSIX_VECT116_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT116_ADDR_LO', + 'regPCIEMSIX_VECT116_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT116_CONTROL', + 'regPCIEMSIX_VECT116_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT116_MSG_DATA', + 'regPCIEMSIX_VECT116_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT117_ADDR_HI', + 'regPCIEMSIX_VECT117_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT117_ADDR_LO', + 'regPCIEMSIX_VECT117_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT117_CONTROL', + 'regPCIEMSIX_VECT117_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT117_MSG_DATA', + 'regPCIEMSIX_VECT117_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT118_ADDR_HI', + 'regPCIEMSIX_VECT118_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT118_ADDR_LO', + 'regPCIEMSIX_VECT118_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT118_CONTROL', + 'regPCIEMSIX_VECT118_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT118_MSG_DATA', + 'regPCIEMSIX_VECT118_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT119_ADDR_HI', + 'regPCIEMSIX_VECT119_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT119_ADDR_LO', + 'regPCIEMSIX_VECT119_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT119_CONTROL', + 'regPCIEMSIX_VECT119_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT119_MSG_DATA', + 'regPCIEMSIX_VECT119_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT11_ADDR_HI', + 'regPCIEMSIX_VECT11_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT11_ADDR_LO', + 'regPCIEMSIX_VECT11_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT11_CONTROL', + 'regPCIEMSIX_VECT11_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT11_MSG_DATA', + 'regPCIEMSIX_VECT11_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT120_ADDR_HI', + 'regPCIEMSIX_VECT120_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT120_ADDR_LO', + 'regPCIEMSIX_VECT120_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT120_CONTROL', + 'regPCIEMSIX_VECT120_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT120_MSG_DATA', + 'regPCIEMSIX_VECT120_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT121_ADDR_HI', + 'regPCIEMSIX_VECT121_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT121_ADDR_LO', + 'regPCIEMSIX_VECT121_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT121_CONTROL', + 'regPCIEMSIX_VECT121_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT121_MSG_DATA', + 'regPCIEMSIX_VECT121_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT122_ADDR_HI', + 'regPCIEMSIX_VECT122_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT122_ADDR_LO', + 'regPCIEMSIX_VECT122_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT122_CONTROL', + 'regPCIEMSIX_VECT122_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT122_MSG_DATA', + 'regPCIEMSIX_VECT122_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT123_ADDR_HI', + 'regPCIEMSIX_VECT123_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT123_ADDR_LO', + 'regPCIEMSIX_VECT123_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT123_CONTROL', + 'regPCIEMSIX_VECT123_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT123_MSG_DATA', + 'regPCIEMSIX_VECT123_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT124_ADDR_HI', + 'regPCIEMSIX_VECT124_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT124_ADDR_LO', + 'regPCIEMSIX_VECT124_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT124_CONTROL', + 'regPCIEMSIX_VECT124_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT124_MSG_DATA', + 'regPCIEMSIX_VECT124_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT125_ADDR_HI', + 'regPCIEMSIX_VECT125_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT125_ADDR_LO', + 'regPCIEMSIX_VECT125_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT125_CONTROL', + 'regPCIEMSIX_VECT125_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT125_MSG_DATA', + 'regPCIEMSIX_VECT125_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT126_ADDR_HI', + 'regPCIEMSIX_VECT126_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT126_ADDR_LO', + 'regPCIEMSIX_VECT126_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT126_CONTROL', + 'regPCIEMSIX_VECT126_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT126_MSG_DATA', + 'regPCIEMSIX_VECT126_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT127_ADDR_HI', + 'regPCIEMSIX_VECT127_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT127_ADDR_LO', + 'regPCIEMSIX_VECT127_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT127_CONTROL', + 'regPCIEMSIX_VECT127_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT127_MSG_DATA', + 'regPCIEMSIX_VECT127_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT128_ADDR_HI', + 'regPCIEMSIX_VECT128_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT128_ADDR_LO', + 'regPCIEMSIX_VECT128_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT128_CONTROL', + 'regPCIEMSIX_VECT128_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT128_MSG_DATA', + 'regPCIEMSIX_VECT128_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT129_ADDR_HI', + 'regPCIEMSIX_VECT129_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT129_ADDR_LO', + 'regPCIEMSIX_VECT129_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT129_CONTROL', + 'regPCIEMSIX_VECT129_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT129_MSG_DATA', + 'regPCIEMSIX_VECT129_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT12_ADDR_HI', + 'regPCIEMSIX_VECT12_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT12_ADDR_LO', + 'regPCIEMSIX_VECT12_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT12_CONTROL', + 'regPCIEMSIX_VECT12_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT12_MSG_DATA', + 'regPCIEMSIX_VECT12_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT130_ADDR_HI', + 'regPCIEMSIX_VECT130_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT130_ADDR_LO', + 'regPCIEMSIX_VECT130_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT130_CONTROL', + 'regPCIEMSIX_VECT130_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT130_MSG_DATA', + 'regPCIEMSIX_VECT130_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT131_ADDR_HI', + 'regPCIEMSIX_VECT131_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT131_ADDR_LO', + 'regPCIEMSIX_VECT131_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT131_CONTROL', + 'regPCIEMSIX_VECT131_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT131_MSG_DATA', + 'regPCIEMSIX_VECT131_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT132_ADDR_HI', + 'regPCIEMSIX_VECT132_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT132_ADDR_LO', + 'regPCIEMSIX_VECT132_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT132_CONTROL', + 'regPCIEMSIX_VECT132_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT132_MSG_DATA', + 'regPCIEMSIX_VECT132_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT133_ADDR_HI', + 'regPCIEMSIX_VECT133_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT133_ADDR_LO', + 'regPCIEMSIX_VECT133_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT133_CONTROL', + 'regPCIEMSIX_VECT133_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT133_MSG_DATA', + 'regPCIEMSIX_VECT133_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT134_ADDR_HI', + 'regPCIEMSIX_VECT134_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT134_ADDR_LO', + 'regPCIEMSIX_VECT134_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT134_CONTROL', + 'regPCIEMSIX_VECT134_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT134_MSG_DATA', + 'regPCIEMSIX_VECT134_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT135_ADDR_HI', + 'regPCIEMSIX_VECT135_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT135_ADDR_LO', + 'regPCIEMSIX_VECT135_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT135_CONTROL', + 'regPCIEMSIX_VECT135_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT135_MSG_DATA', + 'regPCIEMSIX_VECT135_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT136_ADDR_HI', + 'regPCIEMSIX_VECT136_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT136_ADDR_LO', + 'regPCIEMSIX_VECT136_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT136_CONTROL', + 'regPCIEMSIX_VECT136_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT136_MSG_DATA', + 'regPCIEMSIX_VECT136_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT137_ADDR_HI', + 'regPCIEMSIX_VECT137_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT137_ADDR_LO', + 'regPCIEMSIX_VECT137_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT137_CONTROL', + 'regPCIEMSIX_VECT137_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT137_MSG_DATA', + 'regPCIEMSIX_VECT137_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT138_ADDR_HI', + 'regPCIEMSIX_VECT138_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT138_ADDR_LO', + 'regPCIEMSIX_VECT138_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT138_CONTROL', + 'regPCIEMSIX_VECT138_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT138_MSG_DATA', + 'regPCIEMSIX_VECT138_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT139_ADDR_HI', + 'regPCIEMSIX_VECT139_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT139_ADDR_LO', + 'regPCIEMSIX_VECT139_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT139_CONTROL', + 'regPCIEMSIX_VECT139_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT139_MSG_DATA', + 'regPCIEMSIX_VECT139_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT13_ADDR_HI', + 'regPCIEMSIX_VECT13_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT13_ADDR_LO', + 'regPCIEMSIX_VECT13_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT13_CONTROL', + 'regPCIEMSIX_VECT13_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT13_MSG_DATA', + 'regPCIEMSIX_VECT13_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT140_ADDR_HI', + 'regPCIEMSIX_VECT140_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT140_ADDR_LO', + 'regPCIEMSIX_VECT140_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT140_CONTROL', + 'regPCIEMSIX_VECT140_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT140_MSG_DATA', + 'regPCIEMSIX_VECT140_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT141_ADDR_HI', + 'regPCIEMSIX_VECT141_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT141_ADDR_LO', + 'regPCIEMSIX_VECT141_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT141_CONTROL', + 'regPCIEMSIX_VECT141_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT141_MSG_DATA', + 'regPCIEMSIX_VECT141_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT142_ADDR_HI', + 'regPCIEMSIX_VECT142_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT142_ADDR_LO', + 'regPCIEMSIX_VECT142_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT142_CONTROL', + 'regPCIEMSIX_VECT142_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT142_MSG_DATA', + 'regPCIEMSIX_VECT142_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT143_ADDR_HI', + 'regPCIEMSIX_VECT143_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT143_ADDR_LO', + 'regPCIEMSIX_VECT143_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT143_CONTROL', + 'regPCIEMSIX_VECT143_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT143_MSG_DATA', + 'regPCIEMSIX_VECT143_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT144_ADDR_HI', + 'regPCIEMSIX_VECT144_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT144_ADDR_LO', + 'regPCIEMSIX_VECT144_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT144_CONTROL', + 'regPCIEMSIX_VECT144_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT144_MSG_DATA', + 'regPCIEMSIX_VECT144_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT145_ADDR_HI', + 'regPCIEMSIX_VECT145_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT145_ADDR_LO', + 'regPCIEMSIX_VECT145_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT145_CONTROL', + 'regPCIEMSIX_VECT145_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT145_MSG_DATA', + 'regPCIEMSIX_VECT145_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT146_ADDR_HI', + 'regPCIEMSIX_VECT146_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT146_ADDR_LO', + 'regPCIEMSIX_VECT146_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT146_CONTROL', + 'regPCIEMSIX_VECT146_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT146_MSG_DATA', + 'regPCIEMSIX_VECT146_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT147_ADDR_HI', + 'regPCIEMSIX_VECT147_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT147_ADDR_LO', + 'regPCIEMSIX_VECT147_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT147_CONTROL', + 'regPCIEMSIX_VECT147_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT147_MSG_DATA', + 'regPCIEMSIX_VECT147_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT148_ADDR_HI', + 'regPCIEMSIX_VECT148_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT148_ADDR_LO', + 'regPCIEMSIX_VECT148_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT148_CONTROL', + 'regPCIEMSIX_VECT148_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT148_MSG_DATA', + 'regPCIEMSIX_VECT148_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT149_ADDR_HI', + 'regPCIEMSIX_VECT149_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT149_ADDR_LO', + 'regPCIEMSIX_VECT149_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT149_CONTROL', + 'regPCIEMSIX_VECT149_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT149_MSG_DATA', + 'regPCIEMSIX_VECT149_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT14_ADDR_HI', + 'regPCIEMSIX_VECT14_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT14_ADDR_LO', + 'regPCIEMSIX_VECT14_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT14_CONTROL', + 'regPCIEMSIX_VECT14_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT14_MSG_DATA', + 'regPCIEMSIX_VECT14_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT150_ADDR_HI', + 'regPCIEMSIX_VECT150_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT150_ADDR_LO', + 'regPCIEMSIX_VECT150_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT150_CONTROL', + 'regPCIEMSIX_VECT150_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT150_MSG_DATA', + 'regPCIEMSIX_VECT150_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT151_ADDR_HI', + 'regPCIEMSIX_VECT151_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT151_ADDR_LO', + 'regPCIEMSIX_VECT151_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT151_CONTROL', + 'regPCIEMSIX_VECT151_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT151_MSG_DATA', + 'regPCIEMSIX_VECT151_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT152_ADDR_HI', + 'regPCIEMSIX_VECT152_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT152_ADDR_LO', + 'regPCIEMSIX_VECT152_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT152_CONTROL', + 'regPCIEMSIX_VECT152_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT152_MSG_DATA', + 'regPCIEMSIX_VECT152_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT153_ADDR_HI', + 'regPCIEMSIX_VECT153_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT153_ADDR_LO', + 'regPCIEMSIX_VECT153_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT153_CONTROL', + 'regPCIEMSIX_VECT153_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT153_MSG_DATA', + 'regPCIEMSIX_VECT153_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT154_ADDR_HI', + 'regPCIEMSIX_VECT154_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT154_ADDR_LO', + 'regPCIEMSIX_VECT154_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT154_CONTROL', + 'regPCIEMSIX_VECT154_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT154_MSG_DATA', + 'regPCIEMSIX_VECT154_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT155_ADDR_HI', + 'regPCIEMSIX_VECT155_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT155_ADDR_LO', + 'regPCIEMSIX_VECT155_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT155_CONTROL', + 'regPCIEMSIX_VECT155_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT155_MSG_DATA', + 'regPCIEMSIX_VECT155_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT156_ADDR_HI', + 'regPCIEMSIX_VECT156_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT156_ADDR_LO', + 'regPCIEMSIX_VECT156_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT156_CONTROL', + 'regPCIEMSIX_VECT156_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT156_MSG_DATA', + 'regPCIEMSIX_VECT156_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT157_ADDR_HI', + 'regPCIEMSIX_VECT157_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT157_ADDR_LO', + 'regPCIEMSIX_VECT157_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT157_CONTROL', + 'regPCIEMSIX_VECT157_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT157_MSG_DATA', + 'regPCIEMSIX_VECT157_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT158_ADDR_HI', + 'regPCIEMSIX_VECT158_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT158_ADDR_LO', + 'regPCIEMSIX_VECT158_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT158_CONTROL', + 'regPCIEMSIX_VECT158_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT158_MSG_DATA', + 'regPCIEMSIX_VECT158_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT159_ADDR_HI', + 'regPCIEMSIX_VECT159_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT159_ADDR_LO', + 'regPCIEMSIX_VECT159_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT159_CONTROL', + 'regPCIEMSIX_VECT159_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT159_MSG_DATA', + 'regPCIEMSIX_VECT159_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT15_ADDR_HI', + 'regPCIEMSIX_VECT15_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT15_ADDR_LO', + 'regPCIEMSIX_VECT15_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT15_CONTROL', + 'regPCIEMSIX_VECT15_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT15_MSG_DATA', + 'regPCIEMSIX_VECT15_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT160_ADDR_HI', + 'regPCIEMSIX_VECT160_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT160_ADDR_LO', + 'regPCIEMSIX_VECT160_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT160_CONTROL', + 'regPCIEMSIX_VECT160_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT160_MSG_DATA', + 'regPCIEMSIX_VECT160_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT161_ADDR_HI', + 'regPCIEMSIX_VECT161_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT161_ADDR_LO', + 'regPCIEMSIX_VECT161_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT161_CONTROL', + 'regPCIEMSIX_VECT161_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT161_MSG_DATA', + 'regPCIEMSIX_VECT161_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT162_ADDR_HI', + 'regPCIEMSIX_VECT162_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT162_ADDR_LO', + 'regPCIEMSIX_VECT162_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT162_CONTROL', + 'regPCIEMSIX_VECT162_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT162_MSG_DATA', + 'regPCIEMSIX_VECT162_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT163_ADDR_HI', + 'regPCIEMSIX_VECT163_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT163_ADDR_LO', + 'regPCIEMSIX_VECT163_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT163_CONTROL', + 'regPCIEMSIX_VECT163_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT163_MSG_DATA', + 'regPCIEMSIX_VECT163_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT164_ADDR_HI', + 'regPCIEMSIX_VECT164_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT164_ADDR_LO', + 'regPCIEMSIX_VECT164_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT164_CONTROL', + 'regPCIEMSIX_VECT164_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT164_MSG_DATA', + 'regPCIEMSIX_VECT164_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT165_ADDR_HI', + 'regPCIEMSIX_VECT165_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT165_ADDR_LO', + 'regPCIEMSIX_VECT165_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT165_CONTROL', + 'regPCIEMSIX_VECT165_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT165_MSG_DATA', + 'regPCIEMSIX_VECT165_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT166_ADDR_HI', + 'regPCIEMSIX_VECT166_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT166_ADDR_LO', + 'regPCIEMSIX_VECT166_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT166_CONTROL', + 'regPCIEMSIX_VECT166_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT166_MSG_DATA', + 'regPCIEMSIX_VECT166_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT167_ADDR_HI', + 'regPCIEMSIX_VECT167_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT167_ADDR_LO', + 'regPCIEMSIX_VECT167_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT167_CONTROL', + 'regPCIEMSIX_VECT167_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT167_MSG_DATA', + 'regPCIEMSIX_VECT167_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT168_ADDR_HI', + 'regPCIEMSIX_VECT168_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT168_ADDR_LO', + 'regPCIEMSIX_VECT168_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT168_CONTROL', + 'regPCIEMSIX_VECT168_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT168_MSG_DATA', + 'regPCIEMSIX_VECT168_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT169_ADDR_HI', + 'regPCIEMSIX_VECT169_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT169_ADDR_LO', + 'regPCIEMSIX_VECT169_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT169_CONTROL', + 'regPCIEMSIX_VECT169_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT169_MSG_DATA', + 'regPCIEMSIX_VECT169_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT16_ADDR_HI', + 'regPCIEMSIX_VECT16_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT16_ADDR_LO', + 'regPCIEMSIX_VECT16_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT16_CONTROL', + 'regPCIEMSIX_VECT16_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT16_MSG_DATA', + 'regPCIEMSIX_VECT16_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT170_ADDR_HI', + 'regPCIEMSIX_VECT170_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT170_ADDR_LO', + 'regPCIEMSIX_VECT170_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT170_CONTROL', + 'regPCIEMSIX_VECT170_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT170_MSG_DATA', + 'regPCIEMSIX_VECT170_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT171_ADDR_HI', + 'regPCIEMSIX_VECT171_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT171_ADDR_LO', + 'regPCIEMSIX_VECT171_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT171_CONTROL', + 'regPCIEMSIX_VECT171_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT171_MSG_DATA', + 'regPCIEMSIX_VECT171_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT172_ADDR_HI', + 'regPCIEMSIX_VECT172_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT172_ADDR_LO', + 'regPCIEMSIX_VECT172_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT172_CONTROL', + 'regPCIEMSIX_VECT172_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT172_MSG_DATA', + 'regPCIEMSIX_VECT172_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT173_ADDR_HI', + 'regPCIEMSIX_VECT173_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT173_ADDR_LO', + 'regPCIEMSIX_VECT173_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT173_CONTROL', + 'regPCIEMSIX_VECT173_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT173_MSG_DATA', + 'regPCIEMSIX_VECT173_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT174_ADDR_HI', + 'regPCIEMSIX_VECT174_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT174_ADDR_LO', + 'regPCIEMSIX_VECT174_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT174_CONTROL', + 'regPCIEMSIX_VECT174_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT174_MSG_DATA', + 'regPCIEMSIX_VECT174_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT175_ADDR_HI', + 'regPCIEMSIX_VECT175_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT175_ADDR_LO', + 'regPCIEMSIX_VECT175_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT175_CONTROL', + 'regPCIEMSIX_VECT175_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT175_MSG_DATA', + 'regPCIEMSIX_VECT175_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT176_ADDR_HI', + 'regPCIEMSIX_VECT176_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT176_ADDR_LO', + 'regPCIEMSIX_VECT176_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT176_CONTROL', + 'regPCIEMSIX_VECT176_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT176_MSG_DATA', + 'regPCIEMSIX_VECT176_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT177_ADDR_HI', + 'regPCIEMSIX_VECT177_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT177_ADDR_LO', + 'regPCIEMSIX_VECT177_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT177_CONTROL', + 'regPCIEMSIX_VECT177_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT177_MSG_DATA', + 'regPCIEMSIX_VECT177_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT178_ADDR_HI', + 'regPCIEMSIX_VECT178_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT178_ADDR_LO', + 'regPCIEMSIX_VECT178_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT178_CONTROL', + 'regPCIEMSIX_VECT178_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT178_MSG_DATA', + 'regPCIEMSIX_VECT178_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT179_ADDR_HI', + 'regPCIEMSIX_VECT179_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT179_ADDR_LO', + 'regPCIEMSIX_VECT179_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT179_CONTROL', + 'regPCIEMSIX_VECT179_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT179_MSG_DATA', + 'regPCIEMSIX_VECT179_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT17_ADDR_HI', + 'regPCIEMSIX_VECT17_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT17_ADDR_LO', + 'regPCIEMSIX_VECT17_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT17_CONTROL', + 'regPCIEMSIX_VECT17_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT17_MSG_DATA', + 'regPCIEMSIX_VECT17_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT180_ADDR_HI', + 'regPCIEMSIX_VECT180_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT180_ADDR_LO', + 'regPCIEMSIX_VECT180_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT180_CONTROL', + 'regPCIEMSIX_VECT180_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT180_MSG_DATA', + 'regPCIEMSIX_VECT180_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT181_ADDR_HI', + 'regPCIEMSIX_VECT181_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT181_ADDR_LO', + 'regPCIEMSIX_VECT181_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT181_CONTROL', + 'regPCIEMSIX_VECT181_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT181_MSG_DATA', + 'regPCIEMSIX_VECT181_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT182_ADDR_HI', + 'regPCIEMSIX_VECT182_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT182_ADDR_LO', + 'regPCIEMSIX_VECT182_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT182_CONTROL', + 'regPCIEMSIX_VECT182_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT182_MSG_DATA', + 'regPCIEMSIX_VECT182_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT183_ADDR_HI', + 'regPCIEMSIX_VECT183_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT183_ADDR_LO', + 'regPCIEMSIX_VECT183_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT183_CONTROL', + 'regPCIEMSIX_VECT183_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT183_MSG_DATA', + 'regPCIEMSIX_VECT183_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT184_ADDR_HI', + 'regPCIEMSIX_VECT184_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT184_ADDR_LO', + 'regPCIEMSIX_VECT184_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT184_CONTROL', + 'regPCIEMSIX_VECT184_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT184_MSG_DATA', + 'regPCIEMSIX_VECT184_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT185_ADDR_HI', + 'regPCIEMSIX_VECT185_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT185_ADDR_LO', + 'regPCIEMSIX_VECT185_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT185_CONTROL', + 'regPCIEMSIX_VECT185_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT185_MSG_DATA', + 'regPCIEMSIX_VECT185_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT186_ADDR_HI', + 'regPCIEMSIX_VECT186_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT186_ADDR_LO', + 'regPCIEMSIX_VECT186_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT186_CONTROL', + 'regPCIEMSIX_VECT186_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT186_MSG_DATA', + 'regPCIEMSIX_VECT186_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT187_ADDR_HI', + 'regPCIEMSIX_VECT187_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT187_ADDR_LO', + 'regPCIEMSIX_VECT187_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT187_CONTROL', + 'regPCIEMSIX_VECT187_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT187_MSG_DATA', + 'regPCIEMSIX_VECT187_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT188_ADDR_HI', + 'regPCIEMSIX_VECT188_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT188_ADDR_LO', + 'regPCIEMSIX_VECT188_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT188_CONTROL', + 'regPCIEMSIX_VECT188_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT188_MSG_DATA', + 'regPCIEMSIX_VECT188_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT189_ADDR_HI', + 'regPCIEMSIX_VECT189_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT189_ADDR_LO', + 'regPCIEMSIX_VECT189_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT189_CONTROL', + 'regPCIEMSIX_VECT189_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT189_MSG_DATA', + 'regPCIEMSIX_VECT189_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT18_ADDR_HI', + 'regPCIEMSIX_VECT18_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT18_ADDR_LO', + 'regPCIEMSIX_VECT18_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT18_CONTROL', + 'regPCIEMSIX_VECT18_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT18_MSG_DATA', + 'regPCIEMSIX_VECT18_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT190_ADDR_HI', + 'regPCIEMSIX_VECT190_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT190_ADDR_LO', + 'regPCIEMSIX_VECT190_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT190_CONTROL', + 'regPCIEMSIX_VECT190_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT190_MSG_DATA', + 'regPCIEMSIX_VECT190_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT191_ADDR_HI', + 'regPCIEMSIX_VECT191_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT191_ADDR_LO', + 'regPCIEMSIX_VECT191_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT191_CONTROL', + 'regPCIEMSIX_VECT191_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT191_MSG_DATA', + 'regPCIEMSIX_VECT191_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT192_ADDR_HI', + 'regPCIEMSIX_VECT192_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT192_ADDR_LO', + 'regPCIEMSIX_VECT192_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT192_CONTROL', + 'regPCIEMSIX_VECT192_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT192_MSG_DATA', + 'regPCIEMSIX_VECT192_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT193_ADDR_HI', + 'regPCIEMSIX_VECT193_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT193_ADDR_LO', + 'regPCIEMSIX_VECT193_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT193_CONTROL', + 'regPCIEMSIX_VECT193_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT193_MSG_DATA', + 'regPCIEMSIX_VECT193_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT194_ADDR_HI', + 'regPCIEMSIX_VECT194_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT194_ADDR_LO', + 'regPCIEMSIX_VECT194_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT194_CONTROL', + 'regPCIEMSIX_VECT194_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT194_MSG_DATA', + 'regPCIEMSIX_VECT194_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT195_ADDR_HI', + 'regPCIEMSIX_VECT195_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT195_ADDR_LO', + 'regPCIEMSIX_VECT195_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT195_CONTROL', + 'regPCIEMSIX_VECT195_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT195_MSG_DATA', + 'regPCIEMSIX_VECT195_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT196_ADDR_HI', + 'regPCIEMSIX_VECT196_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT196_ADDR_LO', + 'regPCIEMSIX_VECT196_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT196_CONTROL', + 'regPCIEMSIX_VECT196_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT196_MSG_DATA', + 'regPCIEMSIX_VECT196_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT197_ADDR_HI', + 'regPCIEMSIX_VECT197_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT197_ADDR_LO', + 'regPCIEMSIX_VECT197_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT197_CONTROL', + 'regPCIEMSIX_VECT197_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT197_MSG_DATA', + 'regPCIEMSIX_VECT197_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT198_ADDR_HI', + 'regPCIEMSIX_VECT198_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT198_ADDR_LO', + 'regPCIEMSIX_VECT198_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT198_CONTROL', + 'regPCIEMSIX_VECT198_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT198_MSG_DATA', + 'regPCIEMSIX_VECT198_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT199_ADDR_HI', + 'regPCIEMSIX_VECT199_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT199_ADDR_LO', + 'regPCIEMSIX_VECT199_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT199_CONTROL', + 'regPCIEMSIX_VECT199_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT199_MSG_DATA', + 'regPCIEMSIX_VECT199_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT19_ADDR_HI', + 'regPCIEMSIX_VECT19_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT19_ADDR_LO', + 'regPCIEMSIX_VECT19_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT19_CONTROL', + 'regPCIEMSIX_VECT19_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT19_MSG_DATA', + 'regPCIEMSIX_VECT19_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT1_ADDR_HI', 'regPCIEMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT1_ADDR_LO', 'regPCIEMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT1_CONTROL', 'regPCIEMSIX_VECT1_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT1_MSG_DATA', + 'regPCIEMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT200_ADDR_HI', + 'regPCIEMSIX_VECT200_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT200_ADDR_LO', + 'regPCIEMSIX_VECT200_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT200_CONTROL', + 'regPCIEMSIX_VECT200_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT200_MSG_DATA', + 'regPCIEMSIX_VECT200_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT201_ADDR_HI', + 'regPCIEMSIX_VECT201_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT201_ADDR_LO', + 'regPCIEMSIX_VECT201_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT201_CONTROL', + 'regPCIEMSIX_VECT201_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT201_MSG_DATA', + 'regPCIEMSIX_VECT201_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT202_ADDR_HI', + 'regPCIEMSIX_VECT202_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT202_ADDR_LO', + 'regPCIEMSIX_VECT202_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT202_CONTROL', + 'regPCIEMSIX_VECT202_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT202_MSG_DATA', + 'regPCIEMSIX_VECT202_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT203_ADDR_HI', + 'regPCIEMSIX_VECT203_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT203_ADDR_LO', + 'regPCIEMSIX_VECT203_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT203_CONTROL', + 'regPCIEMSIX_VECT203_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT203_MSG_DATA', + 'regPCIEMSIX_VECT203_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT204_ADDR_HI', + 'regPCIEMSIX_VECT204_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT204_ADDR_LO', + 'regPCIEMSIX_VECT204_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT204_CONTROL', + 'regPCIEMSIX_VECT204_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT204_MSG_DATA', + 'regPCIEMSIX_VECT204_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT205_ADDR_HI', + 'regPCIEMSIX_VECT205_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT205_ADDR_LO', + 'regPCIEMSIX_VECT205_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT205_CONTROL', + 'regPCIEMSIX_VECT205_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT205_MSG_DATA', + 'regPCIEMSIX_VECT205_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT206_ADDR_HI', + 'regPCIEMSIX_VECT206_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT206_ADDR_LO', + 'regPCIEMSIX_VECT206_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT206_CONTROL', + 'regPCIEMSIX_VECT206_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT206_MSG_DATA', + 'regPCIEMSIX_VECT206_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT207_ADDR_HI', + 'regPCIEMSIX_VECT207_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT207_ADDR_LO', + 'regPCIEMSIX_VECT207_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT207_CONTROL', + 'regPCIEMSIX_VECT207_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT207_MSG_DATA', + 'regPCIEMSIX_VECT207_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT208_ADDR_HI', + 'regPCIEMSIX_VECT208_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT208_ADDR_LO', + 'regPCIEMSIX_VECT208_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT208_CONTROL', + 'regPCIEMSIX_VECT208_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT208_MSG_DATA', + 'regPCIEMSIX_VECT208_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT209_ADDR_HI', + 'regPCIEMSIX_VECT209_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT209_ADDR_LO', + 'regPCIEMSIX_VECT209_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT209_CONTROL', + 'regPCIEMSIX_VECT209_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT209_MSG_DATA', + 'regPCIEMSIX_VECT209_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT20_ADDR_HI', + 'regPCIEMSIX_VECT20_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT20_ADDR_LO', + 'regPCIEMSIX_VECT20_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT20_CONTROL', + 'regPCIEMSIX_VECT20_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT20_MSG_DATA', + 'regPCIEMSIX_VECT20_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT210_ADDR_HI', + 'regPCIEMSIX_VECT210_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT210_ADDR_LO', + 'regPCIEMSIX_VECT210_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT210_CONTROL', + 'regPCIEMSIX_VECT210_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT210_MSG_DATA', + 'regPCIEMSIX_VECT210_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT211_ADDR_HI', + 'regPCIEMSIX_VECT211_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT211_ADDR_LO', + 'regPCIEMSIX_VECT211_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT211_CONTROL', + 'regPCIEMSIX_VECT211_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT211_MSG_DATA', + 'regPCIEMSIX_VECT211_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT212_ADDR_HI', + 'regPCIEMSIX_VECT212_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT212_ADDR_LO', + 'regPCIEMSIX_VECT212_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT212_CONTROL', + 'regPCIEMSIX_VECT212_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT212_MSG_DATA', + 'regPCIEMSIX_VECT212_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT213_ADDR_HI', + 'regPCIEMSIX_VECT213_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT213_ADDR_LO', + 'regPCIEMSIX_VECT213_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT213_CONTROL', + 'regPCIEMSIX_VECT213_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT213_MSG_DATA', + 'regPCIEMSIX_VECT213_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT214_ADDR_HI', + 'regPCIEMSIX_VECT214_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT214_ADDR_LO', + 'regPCIEMSIX_VECT214_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT214_CONTROL', + 'regPCIEMSIX_VECT214_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT214_MSG_DATA', + 'regPCIEMSIX_VECT214_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT215_ADDR_HI', + 'regPCIEMSIX_VECT215_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT215_ADDR_LO', + 'regPCIEMSIX_VECT215_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT215_CONTROL', + 'regPCIEMSIX_VECT215_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT215_MSG_DATA', + 'regPCIEMSIX_VECT215_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT216_ADDR_HI', + 'regPCIEMSIX_VECT216_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT216_ADDR_LO', + 'regPCIEMSIX_VECT216_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT216_CONTROL', + 'regPCIEMSIX_VECT216_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT216_MSG_DATA', + 'regPCIEMSIX_VECT216_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT217_ADDR_HI', + 'regPCIEMSIX_VECT217_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT217_ADDR_LO', + 'regPCIEMSIX_VECT217_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT217_CONTROL', + 'regPCIEMSIX_VECT217_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT217_MSG_DATA', + 'regPCIEMSIX_VECT217_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT218_ADDR_HI', + 'regPCIEMSIX_VECT218_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT218_ADDR_LO', + 'regPCIEMSIX_VECT218_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT218_CONTROL', + 'regPCIEMSIX_VECT218_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT218_MSG_DATA', + 'regPCIEMSIX_VECT218_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT219_ADDR_HI', + 'regPCIEMSIX_VECT219_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT219_ADDR_LO', + 'regPCIEMSIX_VECT219_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT219_CONTROL', + 'regPCIEMSIX_VECT219_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT219_MSG_DATA', + 'regPCIEMSIX_VECT219_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT21_ADDR_HI', + 'regPCIEMSIX_VECT21_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT21_ADDR_LO', + 'regPCIEMSIX_VECT21_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT21_CONTROL', + 'regPCIEMSIX_VECT21_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT21_MSG_DATA', + 'regPCIEMSIX_VECT21_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT220_ADDR_HI', + 'regPCIEMSIX_VECT220_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT220_ADDR_LO', + 'regPCIEMSIX_VECT220_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT220_CONTROL', + 'regPCIEMSIX_VECT220_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT220_MSG_DATA', + 'regPCIEMSIX_VECT220_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT221_ADDR_HI', + 'regPCIEMSIX_VECT221_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT221_ADDR_LO', + 'regPCIEMSIX_VECT221_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT221_CONTROL', + 'regPCIEMSIX_VECT221_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT221_MSG_DATA', + 'regPCIEMSIX_VECT221_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT222_ADDR_HI', + 'regPCIEMSIX_VECT222_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT222_ADDR_LO', + 'regPCIEMSIX_VECT222_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT222_CONTROL', + 'regPCIEMSIX_VECT222_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT222_MSG_DATA', + 'regPCIEMSIX_VECT222_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT223_ADDR_HI', + 'regPCIEMSIX_VECT223_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT223_ADDR_LO', + 'regPCIEMSIX_VECT223_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT223_CONTROL', + 'regPCIEMSIX_VECT223_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT223_MSG_DATA', + 'regPCIEMSIX_VECT223_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT224_ADDR_HI', + 'regPCIEMSIX_VECT224_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT224_ADDR_LO', + 'regPCIEMSIX_VECT224_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT224_CONTROL', + 'regPCIEMSIX_VECT224_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT224_MSG_DATA', + 'regPCIEMSIX_VECT224_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT225_ADDR_HI', + 'regPCIEMSIX_VECT225_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT225_ADDR_LO', + 'regPCIEMSIX_VECT225_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT225_CONTROL', + 'regPCIEMSIX_VECT225_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT225_MSG_DATA', + 'regPCIEMSIX_VECT225_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT226_ADDR_HI', + 'regPCIEMSIX_VECT226_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT226_ADDR_LO', + 'regPCIEMSIX_VECT226_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT226_CONTROL', + 'regPCIEMSIX_VECT226_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT226_MSG_DATA', + 'regPCIEMSIX_VECT226_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT227_ADDR_HI', + 'regPCIEMSIX_VECT227_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT227_ADDR_LO', + 'regPCIEMSIX_VECT227_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT227_CONTROL', + 'regPCIEMSIX_VECT227_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT227_MSG_DATA', + 'regPCIEMSIX_VECT227_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT228_ADDR_HI', + 'regPCIEMSIX_VECT228_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT228_ADDR_LO', + 'regPCIEMSIX_VECT228_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT228_CONTROL', + 'regPCIEMSIX_VECT228_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT228_MSG_DATA', + 'regPCIEMSIX_VECT228_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT229_ADDR_HI', + 'regPCIEMSIX_VECT229_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT229_ADDR_LO', + 'regPCIEMSIX_VECT229_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT229_CONTROL', + 'regPCIEMSIX_VECT229_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT229_MSG_DATA', + 'regPCIEMSIX_VECT229_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT22_ADDR_HI', + 'regPCIEMSIX_VECT22_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT22_ADDR_LO', + 'regPCIEMSIX_VECT22_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT22_CONTROL', + 'regPCIEMSIX_VECT22_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT22_MSG_DATA', + 'regPCIEMSIX_VECT22_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT230_ADDR_HI', + 'regPCIEMSIX_VECT230_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT230_ADDR_LO', + 'regPCIEMSIX_VECT230_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT230_CONTROL', + 'regPCIEMSIX_VECT230_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT230_MSG_DATA', + 'regPCIEMSIX_VECT230_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT231_ADDR_HI', + 'regPCIEMSIX_VECT231_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT231_ADDR_LO', + 'regPCIEMSIX_VECT231_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT231_CONTROL', + 'regPCIEMSIX_VECT231_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT231_MSG_DATA', + 'regPCIEMSIX_VECT231_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT232_ADDR_HI', + 'regPCIEMSIX_VECT232_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT232_ADDR_LO', + 'regPCIEMSIX_VECT232_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT232_CONTROL', + 'regPCIEMSIX_VECT232_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT232_MSG_DATA', + 'regPCIEMSIX_VECT232_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT233_ADDR_HI', + 'regPCIEMSIX_VECT233_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT233_ADDR_LO', + 'regPCIEMSIX_VECT233_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT233_CONTROL', + 'regPCIEMSIX_VECT233_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT233_MSG_DATA', + 'regPCIEMSIX_VECT233_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT234_ADDR_HI', + 'regPCIEMSIX_VECT234_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT234_ADDR_LO', + 'regPCIEMSIX_VECT234_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT234_CONTROL', + 'regPCIEMSIX_VECT234_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT234_MSG_DATA', + 'regPCIEMSIX_VECT234_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT235_ADDR_HI', + 'regPCIEMSIX_VECT235_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT235_ADDR_LO', + 'regPCIEMSIX_VECT235_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT235_CONTROL', + 'regPCIEMSIX_VECT235_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT235_MSG_DATA', + 'regPCIEMSIX_VECT235_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT236_ADDR_HI', + 'regPCIEMSIX_VECT236_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT236_ADDR_LO', + 'regPCIEMSIX_VECT236_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT236_CONTROL', + 'regPCIEMSIX_VECT236_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT236_MSG_DATA', + 'regPCIEMSIX_VECT236_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT237_ADDR_HI', + 'regPCIEMSIX_VECT237_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT237_ADDR_LO', + 'regPCIEMSIX_VECT237_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT237_CONTROL', + 'regPCIEMSIX_VECT237_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT237_MSG_DATA', + 'regPCIEMSIX_VECT237_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT238_ADDR_HI', + 'regPCIEMSIX_VECT238_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT238_ADDR_LO', + 'regPCIEMSIX_VECT238_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT238_CONTROL', + 'regPCIEMSIX_VECT238_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT238_MSG_DATA', + 'regPCIEMSIX_VECT238_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT239_ADDR_HI', + 'regPCIEMSIX_VECT239_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT239_ADDR_LO', + 'regPCIEMSIX_VECT239_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT239_CONTROL', + 'regPCIEMSIX_VECT239_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT239_MSG_DATA', + 'regPCIEMSIX_VECT239_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT23_ADDR_HI', + 'regPCIEMSIX_VECT23_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT23_ADDR_LO', + 'regPCIEMSIX_VECT23_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT23_CONTROL', + 'regPCIEMSIX_VECT23_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT23_MSG_DATA', + 'regPCIEMSIX_VECT23_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT240_ADDR_HI', + 'regPCIEMSIX_VECT240_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT240_ADDR_LO', + 'regPCIEMSIX_VECT240_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT240_CONTROL', + 'regPCIEMSIX_VECT240_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT240_MSG_DATA', + 'regPCIEMSIX_VECT240_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT241_ADDR_HI', + 'regPCIEMSIX_VECT241_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT241_ADDR_LO', + 'regPCIEMSIX_VECT241_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT241_CONTROL', + 'regPCIEMSIX_VECT241_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT241_MSG_DATA', + 'regPCIEMSIX_VECT241_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT242_ADDR_HI', + 'regPCIEMSIX_VECT242_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT242_ADDR_LO', + 'regPCIEMSIX_VECT242_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT242_CONTROL', + 'regPCIEMSIX_VECT242_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT242_MSG_DATA', + 'regPCIEMSIX_VECT242_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT243_ADDR_HI', + 'regPCIEMSIX_VECT243_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT243_ADDR_LO', + 'regPCIEMSIX_VECT243_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT243_CONTROL', + 'regPCIEMSIX_VECT243_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT243_MSG_DATA', + 'regPCIEMSIX_VECT243_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT244_ADDR_HI', + 'regPCIEMSIX_VECT244_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT244_ADDR_LO', + 'regPCIEMSIX_VECT244_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT244_CONTROL', + 'regPCIEMSIX_VECT244_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT244_MSG_DATA', + 'regPCIEMSIX_VECT244_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT245_ADDR_HI', + 'regPCIEMSIX_VECT245_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT245_ADDR_LO', + 'regPCIEMSIX_VECT245_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT245_CONTROL', + 'regPCIEMSIX_VECT245_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT245_MSG_DATA', + 'regPCIEMSIX_VECT245_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT246_ADDR_HI', + 'regPCIEMSIX_VECT246_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT246_ADDR_LO', + 'regPCIEMSIX_VECT246_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT246_CONTROL', + 'regPCIEMSIX_VECT246_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT246_MSG_DATA', + 'regPCIEMSIX_VECT246_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT247_ADDR_HI', + 'regPCIEMSIX_VECT247_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT247_ADDR_LO', + 'regPCIEMSIX_VECT247_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT247_CONTROL', + 'regPCIEMSIX_VECT247_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT247_MSG_DATA', + 'regPCIEMSIX_VECT247_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT248_ADDR_HI', + 'regPCIEMSIX_VECT248_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT248_ADDR_LO', + 'regPCIEMSIX_VECT248_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT248_CONTROL', + 'regPCIEMSIX_VECT248_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT248_MSG_DATA', + 'regPCIEMSIX_VECT248_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT249_ADDR_HI', + 'regPCIEMSIX_VECT249_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT249_ADDR_LO', + 'regPCIEMSIX_VECT249_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT249_CONTROL', + 'regPCIEMSIX_VECT249_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT249_MSG_DATA', + 'regPCIEMSIX_VECT249_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT24_ADDR_HI', + 'regPCIEMSIX_VECT24_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT24_ADDR_LO', + 'regPCIEMSIX_VECT24_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT24_CONTROL', + 'regPCIEMSIX_VECT24_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT24_MSG_DATA', + 'regPCIEMSIX_VECT24_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT250_ADDR_HI', + 'regPCIEMSIX_VECT250_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT250_ADDR_LO', + 'regPCIEMSIX_VECT250_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT250_CONTROL', + 'regPCIEMSIX_VECT250_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT250_MSG_DATA', + 'regPCIEMSIX_VECT250_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT251_ADDR_HI', + 'regPCIEMSIX_VECT251_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT251_ADDR_LO', + 'regPCIEMSIX_VECT251_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT251_CONTROL', + 'regPCIEMSIX_VECT251_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT251_MSG_DATA', + 'regPCIEMSIX_VECT251_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT252_ADDR_HI', + 'regPCIEMSIX_VECT252_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT252_ADDR_LO', + 'regPCIEMSIX_VECT252_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT252_CONTROL', + 'regPCIEMSIX_VECT252_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT252_MSG_DATA', + 'regPCIEMSIX_VECT252_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT253_ADDR_HI', + 'regPCIEMSIX_VECT253_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT253_ADDR_LO', + 'regPCIEMSIX_VECT253_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT253_CONTROL', + 'regPCIEMSIX_VECT253_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT253_MSG_DATA', + 'regPCIEMSIX_VECT253_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT254_ADDR_HI', + 'regPCIEMSIX_VECT254_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT254_ADDR_LO', + 'regPCIEMSIX_VECT254_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT254_CONTROL', + 'regPCIEMSIX_VECT254_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT254_MSG_DATA', + 'regPCIEMSIX_VECT254_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT255_ADDR_HI', + 'regPCIEMSIX_VECT255_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT255_ADDR_LO', + 'regPCIEMSIX_VECT255_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT255_CONTROL', + 'regPCIEMSIX_VECT255_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT255_MSG_DATA', + 'regPCIEMSIX_VECT255_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT25_ADDR_HI', + 'regPCIEMSIX_VECT25_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT25_ADDR_LO', + 'regPCIEMSIX_VECT25_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT25_CONTROL', + 'regPCIEMSIX_VECT25_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT25_MSG_DATA', + 'regPCIEMSIX_VECT25_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT26_ADDR_HI', + 'regPCIEMSIX_VECT26_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT26_ADDR_LO', + 'regPCIEMSIX_VECT26_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT26_CONTROL', + 'regPCIEMSIX_VECT26_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT26_MSG_DATA', + 'regPCIEMSIX_VECT26_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT27_ADDR_HI', + 'regPCIEMSIX_VECT27_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT27_ADDR_LO', + 'regPCIEMSIX_VECT27_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT27_CONTROL', + 'regPCIEMSIX_VECT27_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT27_MSG_DATA', + 'regPCIEMSIX_VECT27_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT28_ADDR_HI', + 'regPCIEMSIX_VECT28_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT28_ADDR_LO', + 'regPCIEMSIX_VECT28_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT28_CONTROL', + 'regPCIEMSIX_VECT28_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT28_MSG_DATA', + 'regPCIEMSIX_VECT28_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT29_ADDR_HI', + 'regPCIEMSIX_VECT29_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT29_ADDR_LO', + 'regPCIEMSIX_VECT29_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT29_CONTROL', + 'regPCIEMSIX_VECT29_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT29_MSG_DATA', + 'regPCIEMSIX_VECT29_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT2_ADDR_HI', 'regPCIEMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT2_ADDR_LO', 'regPCIEMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT2_CONTROL', 'regPCIEMSIX_VECT2_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT2_MSG_DATA', + 'regPCIEMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT30_ADDR_HI', + 'regPCIEMSIX_VECT30_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT30_ADDR_LO', + 'regPCIEMSIX_VECT30_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT30_CONTROL', + 'regPCIEMSIX_VECT30_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT30_MSG_DATA', + 'regPCIEMSIX_VECT30_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT31_ADDR_HI', + 'regPCIEMSIX_VECT31_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT31_ADDR_LO', + 'regPCIEMSIX_VECT31_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT31_CONTROL', + 'regPCIEMSIX_VECT31_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT31_MSG_DATA', + 'regPCIEMSIX_VECT31_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT32_ADDR_HI', + 'regPCIEMSIX_VECT32_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT32_ADDR_LO', + 'regPCIEMSIX_VECT32_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT32_CONTROL', + 'regPCIEMSIX_VECT32_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT32_MSG_DATA', + 'regPCIEMSIX_VECT32_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT33_ADDR_HI', + 'regPCIEMSIX_VECT33_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT33_ADDR_LO', + 'regPCIEMSIX_VECT33_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT33_CONTROL', + 'regPCIEMSIX_VECT33_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT33_MSG_DATA', + 'regPCIEMSIX_VECT33_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT34_ADDR_HI', + 'regPCIEMSIX_VECT34_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT34_ADDR_LO', + 'regPCIEMSIX_VECT34_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT34_CONTROL', + 'regPCIEMSIX_VECT34_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT34_MSG_DATA', + 'regPCIEMSIX_VECT34_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT35_ADDR_HI', + 'regPCIEMSIX_VECT35_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT35_ADDR_LO', + 'regPCIEMSIX_VECT35_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT35_CONTROL', + 'regPCIEMSIX_VECT35_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT35_MSG_DATA', + 'regPCIEMSIX_VECT35_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT36_ADDR_HI', + 'regPCIEMSIX_VECT36_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT36_ADDR_LO', + 'regPCIEMSIX_VECT36_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT36_CONTROL', + 'regPCIEMSIX_VECT36_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT36_MSG_DATA', + 'regPCIEMSIX_VECT36_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT37_ADDR_HI', + 'regPCIEMSIX_VECT37_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT37_ADDR_LO', + 'regPCIEMSIX_VECT37_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT37_CONTROL', + 'regPCIEMSIX_VECT37_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT37_MSG_DATA', + 'regPCIEMSIX_VECT37_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT38_ADDR_HI', + 'regPCIEMSIX_VECT38_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT38_ADDR_LO', + 'regPCIEMSIX_VECT38_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT38_CONTROL', + 'regPCIEMSIX_VECT38_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT38_MSG_DATA', + 'regPCIEMSIX_VECT38_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT39_ADDR_HI', + 'regPCIEMSIX_VECT39_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT39_ADDR_LO', + 'regPCIEMSIX_VECT39_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT39_CONTROL', + 'regPCIEMSIX_VECT39_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT39_MSG_DATA', + 'regPCIEMSIX_VECT39_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT3_ADDR_HI', 'regPCIEMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT3_ADDR_LO', 'regPCIEMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT3_CONTROL', 'regPCIEMSIX_VECT3_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT3_MSG_DATA', + 'regPCIEMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT40_ADDR_HI', + 'regPCIEMSIX_VECT40_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT40_ADDR_LO', + 'regPCIEMSIX_VECT40_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT40_CONTROL', + 'regPCIEMSIX_VECT40_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT40_MSG_DATA', + 'regPCIEMSIX_VECT40_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT41_ADDR_HI', + 'regPCIEMSIX_VECT41_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT41_ADDR_LO', + 'regPCIEMSIX_VECT41_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT41_CONTROL', + 'regPCIEMSIX_VECT41_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT41_MSG_DATA', + 'regPCIEMSIX_VECT41_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT42_ADDR_HI', + 'regPCIEMSIX_VECT42_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT42_ADDR_LO', + 'regPCIEMSIX_VECT42_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT42_CONTROL', + 'regPCIEMSIX_VECT42_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT42_MSG_DATA', + 'regPCIEMSIX_VECT42_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT43_ADDR_HI', + 'regPCIEMSIX_VECT43_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT43_ADDR_LO', + 'regPCIEMSIX_VECT43_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT43_CONTROL', + 'regPCIEMSIX_VECT43_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT43_MSG_DATA', + 'regPCIEMSIX_VECT43_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT44_ADDR_HI', + 'regPCIEMSIX_VECT44_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT44_ADDR_LO', + 'regPCIEMSIX_VECT44_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT44_CONTROL', + 'regPCIEMSIX_VECT44_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT44_MSG_DATA', + 'regPCIEMSIX_VECT44_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT45_ADDR_HI', + 'regPCIEMSIX_VECT45_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT45_ADDR_LO', + 'regPCIEMSIX_VECT45_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT45_CONTROL', + 'regPCIEMSIX_VECT45_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT45_MSG_DATA', + 'regPCIEMSIX_VECT45_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT46_ADDR_HI', + 'regPCIEMSIX_VECT46_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT46_ADDR_LO', + 'regPCIEMSIX_VECT46_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT46_CONTROL', + 'regPCIEMSIX_VECT46_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT46_MSG_DATA', + 'regPCIEMSIX_VECT46_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT47_ADDR_HI', + 'regPCIEMSIX_VECT47_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT47_ADDR_LO', + 'regPCIEMSIX_VECT47_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT47_CONTROL', + 'regPCIEMSIX_VECT47_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT47_MSG_DATA', + 'regPCIEMSIX_VECT47_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT48_ADDR_HI', + 'regPCIEMSIX_VECT48_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT48_ADDR_LO', + 'regPCIEMSIX_VECT48_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT48_CONTROL', + 'regPCIEMSIX_VECT48_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT48_MSG_DATA', + 'regPCIEMSIX_VECT48_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT49_ADDR_HI', + 'regPCIEMSIX_VECT49_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT49_ADDR_LO', + 'regPCIEMSIX_VECT49_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT49_CONTROL', + 'regPCIEMSIX_VECT49_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT49_MSG_DATA', + 'regPCIEMSIX_VECT49_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT4_ADDR_HI', 'regPCIEMSIX_VECT4_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT4_ADDR_LO', 'regPCIEMSIX_VECT4_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT4_CONTROL', 'regPCIEMSIX_VECT4_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT4_MSG_DATA', + 'regPCIEMSIX_VECT4_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT50_ADDR_HI', + 'regPCIEMSIX_VECT50_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT50_ADDR_LO', + 'regPCIEMSIX_VECT50_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT50_CONTROL', + 'regPCIEMSIX_VECT50_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT50_MSG_DATA', + 'regPCIEMSIX_VECT50_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT51_ADDR_HI', + 'regPCIEMSIX_VECT51_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT51_ADDR_LO', + 'regPCIEMSIX_VECT51_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT51_CONTROL', + 'regPCIEMSIX_VECT51_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT51_MSG_DATA', + 'regPCIEMSIX_VECT51_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT52_ADDR_HI', + 'regPCIEMSIX_VECT52_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT52_ADDR_LO', + 'regPCIEMSIX_VECT52_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT52_CONTROL', + 'regPCIEMSIX_VECT52_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT52_MSG_DATA', + 'regPCIEMSIX_VECT52_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT53_ADDR_HI', + 'regPCIEMSIX_VECT53_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT53_ADDR_LO', + 'regPCIEMSIX_VECT53_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT53_CONTROL', + 'regPCIEMSIX_VECT53_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT53_MSG_DATA', + 'regPCIEMSIX_VECT53_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT54_ADDR_HI', + 'regPCIEMSIX_VECT54_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT54_ADDR_LO', + 'regPCIEMSIX_VECT54_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT54_CONTROL', + 'regPCIEMSIX_VECT54_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT54_MSG_DATA', + 'regPCIEMSIX_VECT54_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT55_ADDR_HI', + 'regPCIEMSIX_VECT55_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT55_ADDR_LO', + 'regPCIEMSIX_VECT55_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT55_CONTROL', + 'regPCIEMSIX_VECT55_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT55_MSG_DATA', + 'regPCIEMSIX_VECT55_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT56_ADDR_HI', + 'regPCIEMSIX_VECT56_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT56_ADDR_LO', + 'regPCIEMSIX_VECT56_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT56_CONTROL', + 'regPCIEMSIX_VECT56_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT56_MSG_DATA', + 'regPCIEMSIX_VECT56_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT57_ADDR_HI', + 'regPCIEMSIX_VECT57_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT57_ADDR_LO', + 'regPCIEMSIX_VECT57_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT57_CONTROL', + 'regPCIEMSIX_VECT57_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT57_MSG_DATA', + 'regPCIEMSIX_VECT57_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT58_ADDR_HI', + 'regPCIEMSIX_VECT58_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT58_ADDR_LO', + 'regPCIEMSIX_VECT58_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT58_CONTROL', + 'regPCIEMSIX_VECT58_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT58_MSG_DATA', + 'regPCIEMSIX_VECT58_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT59_ADDR_HI', + 'regPCIEMSIX_VECT59_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT59_ADDR_LO', + 'regPCIEMSIX_VECT59_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT59_CONTROL', + 'regPCIEMSIX_VECT59_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT59_MSG_DATA', + 'regPCIEMSIX_VECT59_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT5_ADDR_HI', 'regPCIEMSIX_VECT5_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT5_ADDR_LO', 'regPCIEMSIX_VECT5_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT5_CONTROL', 'regPCIEMSIX_VECT5_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT5_MSG_DATA', + 'regPCIEMSIX_VECT5_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT60_ADDR_HI', + 'regPCIEMSIX_VECT60_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT60_ADDR_LO', + 'regPCIEMSIX_VECT60_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT60_CONTROL', + 'regPCIEMSIX_VECT60_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT60_MSG_DATA', + 'regPCIEMSIX_VECT60_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT61_ADDR_HI', + 'regPCIEMSIX_VECT61_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT61_ADDR_LO', + 'regPCIEMSIX_VECT61_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT61_CONTROL', + 'regPCIEMSIX_VECT61_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT61_MSG_DATA', + 'regPCIEMSIX_VECT61_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT62_ADDR_HI', + 'regPCIEMSIX_VECT62_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT62_ADDR_LO', + 'regPCIEMSIX_VECT62_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT62_CONTROL', + 'regPCIEMSIX_VECT62_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT62_MSG_DATA', + 'regPCIEMSIX_VECT62_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT63_ADDR_HI', + 'regPCIEMSIX_VECT63_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT63_ADDR_LO', + 'regPCIEMSIX_VECT63_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT63_CONTROL', + 'regPCIEMSIX_VECT63_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT63_MSG_DATA', + 'regPCIEMSIX_VECT63_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT64_ADDR_HI', + 'regPCIEMSIX_VECT64_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT64_ADDR_LO', + 'regPCIEMSIX_VECT64_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT64_CONTROL', + 'regPCIEMSIX_VECT64_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT64_MSG_DATA', + 'regPCIEMSIX_VECT64_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT65_ADDR_HI', + 'regPCIEMSIX_VECT65_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT65_ADDR_LO', + 'regPCIEMSIX_VECT65_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT65_CONTROL', + 'regPCIEMSIX_VECT65_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT65_MSG_DATA', + 'regPCIEMSIX_VECT65_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT66_ADDR_HI', + 'regPCIEMSIX_VECT66_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT66_ADDR_LO', + 'regPCIEMSIX_VECT66_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT66_CONTROL', + 'regPCIEMSIX_VECT66_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT66_MSG_DATA', + 'regPCIEMSIX_VECT66_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT67_ADDR_HI', + 'regPCIEMSIX_VECT67_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT67_ADDR_LO', + 'regPCIEMSIX_VECT67_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT67_CONTROL', + 'regPCIEMSIX_VECT67_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT67_MSG_DATA', + 'regPCIEMSIX_VECT67_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT68_ADDR_HI', + 'regPCIEMSIX_VECT68_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT68_ADDR_LO', + 'regPCIEMSIX_VECT68_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT68_CONTROL', + 'regPCIEMSIX_VECT68_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT68_MSG_DATA', + 'regPCIEMSIX_VECT68_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT69_ADDR_HI', + 'regPCIEMSIX_VECT69_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT69_ADDR_LO', + 'regPCIEMSIX_VECT69_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT69_CONTROL', + 'regPCIEMSIX_VECT69_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT69_MSG_DATA', + 'regPCIEMSIX_VECT69_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT6_ADDR_HI', 'regPCIEMSIX_VECT6_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT6_ADDR_LO', 'regPCIEMSIX_VECT6_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT6_CONTROL', 'regPCIEMSIX_VECT6_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT6_MSG_DATA', + 'regPCIEMSIX_VECT6_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT70_ADDR_HI', + 'regPCIEMSIX_VECT70_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT70_ADDR_LO', + 'regPCIEMSIX_VECT70_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT70_CONTROL', + 'regPCIEMSIX_VECT70_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT70_MSG_DATA', + 'regPCIEMSIX_VECT70_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT71_ADDR_HI', + 'regPCIEMSIX_VECT71_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT71_ADDR_LO', + 'regPCIEMSIX_VECT71_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT71_CONTROL', + 'regPCIEMSIX_VECT71_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT71_MSG_DATA', + 'regPCIEMSIX_VECT71_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT72_ADDR_HI', + 'regPCIEMSIX_VECT72_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT72_ADDR_LO', + 'regPCIEMSIX_VECT72_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT72_CONTROL', + 'regPCIEMSIX_VECT72_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT72_MSG_DATA', + 'regPCIEMSIX_VECT72_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT73_ADDR_HI', + 'regPCIEMSIX_VECT73_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT73_ADDR_LO', + 'regPCIEMSIX_VECT73_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT73_CONTROL', + 'regPCIEMSIX_VECT73_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT73_MSG_DATA', + 'regPCIEMSIX_VECT73_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT74_ADDR_HI', + 'regPCIEMSIX_VECT74_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT74_ADDR_LO', + 'regPCIEMSIX_VECT74_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT74_CONTROL', + 'regPCIEMSIX_VECT74_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT74_MSG_DATA', + 'regPCIEMSIX_VECT74_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT75_ADDR_HI', + 'regPCIEMSIX_VECT75_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT75_ADDR_LO', + 'regPCIEMSIX_VECT75_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT75_CONTROL', + 'regPCIEMSIX_VECT75_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT75_MSG_DATA', + 'regPCIEMSIX_VECT75_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT76_ADDR_HI', + 'regPCIEMSIX_VECT76_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT76_ADDR_LO', + 'regPCIEMSIX_VECT76_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT76_CONTROL', + 'regPCIEMSIX_VECT76_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT76_MSG_DATA', + 'regPCIEMSIX_VECT76_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT77_ADDR_HI', + 'regPCIEMSIX_VECT77_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT77_ADDR_LO', + 'regPCIEMSIX_VECT77_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT77_CONTROL', + 'regPCIEMSIX_VECT77_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT77_MSG_DATA', + 'regPCIEMSIX_VECT77_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT78_ADDR_HI', + 'regPCIEMSIX_VECT78_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT78_ADDR_LO', + 'regPCIEMSIX_VECT78_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT78_CONTROL', + 'regPCIEMSIX_VECT78_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT78_MSG_DATA', + 'regPCIEMSIX_VECT78_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT79_ADDR_HI', + 'regPCIEMSIX_VECT79_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT79_ADDR_LO', + 'regPCIEMSIX_VECT79_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT79_CONTROL', + 'regPCIEMSIX_VECT79_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT79_MSG_DATA', + 'regPCIEMSIX_VECT79_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT7_ADDR_HI', 'regPCIEMSIX_VECT7_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT7_ADDR_LO', 'regPCIEMSIX_VECT7_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT7_CONTROL', 'regPCIEMSIX_VECT7_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT7_MSG_DATA', + 'regPCIEMSIX_VECT7_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT80_ADDR_HI', + 'regPCIEMSIX_VECT80_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT80_ADDR_LO', + 'regPCIEMSIX_VECT80_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT80_CONTROL', + 'regPCIEMSIX_VECT80_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT80_MSG_DATA', + 'regPCIEMSIX_VECT80_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT81_ADDR_HI', + 'regPCIEMSIX_VECT81_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT81_ADDR_LO', + 'regPCIEMSIX_VECT81_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT81_CONTROL', + 'regPCIEMSIX_VECT81_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT81_MSG_DATA', + 'regPCIEMSIX_VECT81_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT82_ADDR_HI', + 'regPCIEMSIX_VECT82_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT82_ADDR_LO', + 'regPCIEMSIX_VECT82_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT82_CONTROL', + 'regPCIEMSIX_VECT82_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT82_MSG_DATA', + 'regPCIEMSIX_VECT82_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT83_ADDR_HI', + 'regPCIEMSIX_VECT83_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT83_ADDR_LO', + 'regPCIEMSIX_VECT83_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT83_CONTROL', + 'regPCIEMSIX_VECT83_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT83_MSG_DATA', + 'regPCIEMSIX_VECT83_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT84_ADDR_HI', + 'regPCIEMSIX_VECT84_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT84_ADDR_LO', + 'regPCIEMSIX_VECT84_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT84_CONTROL', + 'regPCIEMSIX_VECT84_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT84_MSG_DATA', + 'regPCIEMSIX_VECT84_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT85_ADDR_HI', + 'regPCIEMSIX_VECT85_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT85_ADDR_LO', + 'regPCIEMSIX_VECT85_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT85_CONTROL', + 'regPCIEMSIX_VECT85_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT85_MSG_DATA', + 'regPCIEMSIX_VECT85_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT86_ADDR_HI', + 'regPCIEMSIX_VECT86_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT86_ADDR_LO', + 'regPCIEMSIX_VECT86_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT86_CONTROL', + 'regPCIEMSIX_VECT86_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT86_MSG_DATA', + 'regPCIEMSIX_VECT86_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT87_ADDR_HI', + 'regPCIEMSIX_VECT87_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT87_ADDR_LO', + 'regPCIEMSIX_VECT87_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT87_CONTROL', + 'regPCIEMSIX_VECT87_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT87_MSG_DATA', + 'regPCIEMSIX_VECT87_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT88_ADDR_HI', + 'regPCIEMSIX_VECT88_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT88_ADDR_LO', + 'regPCIEMSIX_VECT88_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT88_CONTROL', + 'regPCIEMSIX_VECT88_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT88_MSG_DATA', + 'regPCIEMSIX_VECT88_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT89_ADDR_HI', + 'regPCIEMSIX_VECT89_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT89_ADDR_LO', + 'regPCIEMSIX_VECT89_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT89_CONTROL', + 'regPCIEMSIX_VECT89_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT89_MSG_DATA', + 'regPCIEMSIX_VECT89_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT8_ADDR_HI', 'regPCIEMSIX_VECT8_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT8_ADDR_LO', 'regPCIEMSIX_VECT8_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT8_CONTROL', 'regPCIEMSIX_VECT8_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT8_MSG_DATA', + 'regPCIEMSIX_VECT8_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT90_ADDR_HI', + 'regPCIEMSIX_VECT90_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT90_ADDR_LO', + 'regPCIEMSIX_VECT90_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT90_CONTROL', + 'regPCIEMSIX_VECT90_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT90_MSG_DATA', + 'regPCIEMSIX_VECT90_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT91_ADDR_HI', + 'regPCIEMSIX_VECT91_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT91_ADDR_LO', + 'regPCIEMSIX_VECT91_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT91_CONTROL', + 'regPCIEMSIX_VECT91_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT91_MSG_DATA', + 'regPCIEMSIX_VECT91_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT92_ADDR_HI', + 'regPCIEMSIX_VECT92_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT92_ADDR_LO', + 'regPCIEMSIX_VECT92_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT92_CONTROL', + 'regPCIEMSIX_VECT92_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT92_MSG_DATA', + 'regPCIEMSIX_VECT92_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT93_ADDR_HI', + 'regPCIEMSIX_VECT93_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT93_ADDR_LO', + 'regPCIEMSIX_VECT93_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT93_CONTROL', + 'regPCIEMSIX_VECT93_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT93_MSG_DATA', + 'regPCIEMSIX_VECT93_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT94_ADDR_HI', + 'regPCIEMSIX_VECT94_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT94_ADDR_LO', + 'regPCIEMSIX_VECT94_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT94_CONTROL', + 'regPCIEMSIX_VECT94_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT94_MSG_DATA', + 'regPCIEMSIX_VECT94_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT95_ADDR_HI', + 'regPCIEMSIX_VECT95_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT95_ADDR_LO', + 'regPCIEMSIX_VECT95_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT95_CONTROL', + 'regPCIEMSIX_VECT95_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT95_MSG_DATA', + 'regPCIEMSIX_VECT95_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT96_ADDR_HI', + 'regPCIEMSIX_VECT96_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT96_ADDR_LO', + 'regPCIEMSIX_VECT96_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT96_CONTROL', + 'regPCIEMSIX_VECT96_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT96_MSG_DATA', + 'regPCIEMSIX_VECT96_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT97_ADDR_HI', + 'regPCIEMSIX_VECT97_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT97_ADDR_LO', + 'regPCIEMSIX_VECT97_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT97_CONTROL', + 'regPCIEMSIX_VECT97_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT97_MSG_DATA', + 'regPCIEMSIX_VECT97_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT98_ADDR_HI', + 'regPCIEMSIX_VECT98_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT98_ADDR_LO', + 'regPCIEMSIX_VECT98_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT98_CONTROL', + 'regPCIEMSIX_VECT98_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT98_MSG_DATA', + 'regPCIEMSIX_VECT98_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT99_ADDR_HI', + 'regPCIEMSIX_VECT99_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT99_ADDR_LO', + 'regPCIEMSIX_VECT99_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT99_CONTROL', + 'regPCIEMSIX_VECT99_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT99_MSG_DATA', + 'regPCIEMSIX_VECT99_MSG_DATA_BASE_IDX', + 'regPCIEMSIX_VECT9_ADDR_HI', 'regPCIEMSIX_VECT9_ADDR_HI_BASE_IDX', + 'regPCIEMSIX_VECT9_ADDR_LO', 'regPCIEMSIX_VECT9_ADDR_LO_BASE_IDX', + 'regPCIEMSIX_VECT9_CONTROL', 'regPCIEMSIX_VECT9_CONTROL_BASE_IDX', + 'regPCIEMSIX_VECT9_MSG_DATA', + 'regPCIEMSIX_VECT9_MSG_DATA_BASE_IDX', 'regPCIE_VDM_CNTL2', + 'regPCIE_VDM_CNTL2_BASE_IDX', 'regPCIE_VDM_CNTL3', + 'regPCIE_VDM_CNTL3_BASE_IDX', 'regPCIE_VDM_NODE0_CTRL4', + 'regPCIE_VDM_NODE0_CTRL4_BASE_IDX', 'regPOISON_ACTION_CONTROL', + 'regPOISON_ACTION_CONTROL_BASE_IDX', 'regPPR_CONTROL', + 'regPPR_CONTROL_BASE_IDX', 'regPSP_BASE_ADDR_HI', + 'regPSP_BASE_ADDR_HI_BASE_IDX', 'regPSP_BASE_ADDR_LO', + 'regPSP_BASE_ADDR_LO_BASE_IDX', 'regP_DMA_DROPPED_LOG_LOWER', + 'regP_DMA_DROPPED_LOG_LOWER_BASE_IDX', + 'regP_DMA_DROPPED_LOG_UPPER', + 'regP_DMA_DROPPED_LOG_UPPER_BASE_IDX', + 'regParityCorr_ACTION_CONTROL', + 'regParityCorr_ACTION_CONTROL_BASE_IDX', + 'regParityFatal_ACTION_CONTROL', + 'regParityFatal_ACTION_CONTROL_BASE_IDX', + 'regParityNonFatal_ACTION_CONTROL', + 'regParityNonFatal_ACTION_CONTROL_BASE_IDX', + 'regParitySerr_ACTION_CONTROL', + 'regParitySerr_ACTION_CONTROL_BASE_IDX', + 'regRAS_GLOBAL_STATUS_HI', 'regRAS_GLOBAL_STATUS_HI_BASE_IDX', + 'regRAS_GLOBAL_STATUS_LO', 'regRAS_GLOBAL_STATUS_LO_BASE_IDX', + 'regRAS_SCRATCH_0', 'regRAS_SCRATCH_0_BASE_IDX', + 'regRAS_SCRATCH_1', 'regRAS_SCRATCH_1_BASE_IDX', + 'regRCC_DEV0_0_RCC_BACO_CNTL_MISC', + 'regRCC_DEV0_0_RCC_BACO_CNTL_MISC_BASE_IDX', + 'regRCC_DEV0_0_RCC_BUSNUM_CNTL1', + 'regRCC_DEV0_0_RCC_BUSNUM_CNTL1_BASE_IDX', + 'regRCC_DEV0_0_RCC_BUSNUM_CNTL2', + 'regRCC_DEV0_0_RCC_BUSNUM_CNTL2_BASE_IDX', + 'regRCC_DEV0_0_RCC_BUSNUM_LIST0', + 'regRCC_DEV0_0_RCC_BUSNUM_LIST0_BASE_IDX', + 'regRCC_DEV0_0_RCC_BUSNUM_LIST1', + 'regRCC_DEV0_0_RCC_BUSNUM_LIST1_BASE_IDX', + 'regRCC_DEV0_0_RCC_BUS_CNTL', + 'regRCC_DEV0_0_RCC_BUS_CNTL_BASE_IDX', + 'regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM', + 'regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX', + 'regRCC_DEV0_0_RCC_CMN_LINK_CNTL', + 'regRCC_DEV0_0_RCC_CMN_LINK_CNTL_BASE_IDX', + 'regRCC_DEV0_0_RCC_CONFIG_APER_SIZE', + 'regRCC_DEV0_0_RCC_CONFIG_APER_SIZE_BASE_IDX', + 'regRCC_DEV0_0_RCC_CONFIG_CNTL', + 'regRCC_DEV0_0_RCC_CONFIG_CNTL_BASE_IDX', + 'regRCC_DEV0_0_RCC_CONFIG_F0_BASE', + 'regRCC_DEV0_0_RCC_CONFIG_F0_BASE_BASE_IDX', + 'regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE', + 'regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE_BASE_IDX', + 'regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET', + 'regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX', + 'regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL', + 'regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX', + 'regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE', + 'regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX', + 'regRCC_DEV0_0_RCC_DEV0_LINK_CNTL', + 'regRCC_DEV0_0_RCC_DEV0_LINK_CNTL_BASE_IDX', + 'regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0', + 'regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0_BASE_IDX', + 'regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1', + 'regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1_BASE_IDX', + 'regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE', + 'regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_BASE_IDX', + 'regRCC_DEV0_0_RCC_ERR_INT_CNTL', + 'regRCC_DEV0_0_RCC_ERR_INT_CNTL_BASE_IDX', + 'regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC', + 'regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_BASE_IDX', + 'regRCC_DEV0_0_RCC_GPUIOV_REGION', + 'regRCC_DEV0_0_RCC_GPUIOV_REGION_BASE_IDX', + 'regRCC_DEV0_0_RCC_GPU_HOSTVM_EN', + 'regRCC_DEV0_0_RCC_GPU_HOSTVM_EN_BASE_IDX', + 'regRCC_DEV0_0_RCC_HOST_BUSNUM', + 'regRCC_DEV0_0_RCC_HOST_BUSNUM_BASE_IDX', + 'regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL', + 'regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_BASE_IDX', + 'regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0', + 'regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_BASE_IDX', + 'regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1', + 'regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_BASE_IDX', + 'regRCC_DEV0_0_RCC_MH_ARB_CNTL', + 'regRCC_DEV0_0_RCC_MH_ARB_CNTL_BASE_IDX', + 'regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI', + 'regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI_BASE_IDX', + 'regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO', + 'regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO_BASE_IDX', + 'regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI', + 'regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI_BASE_IDX', + 'regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO', + 'regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO_BASE_IDX', + 'regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI', + 'regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI_BASE_IDX', + 'regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO', + 'regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO_BASE_IDX', + 'regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI', + 'regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI_BASE_IDX', + 'regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO', + 'regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO_BASE_IDX', + 'regRCC_DEV0_0_RCC_PEER_REG_RANGE0', + 'regRCC_DEV0_0_RCC_PEER_REG_RANGE0_BASE_IDX', + 'regRCC_DEV0_0_RCC_PEER_REG_RANGE1', + 'regRCC_DEV0_0_RCC_PEER_REG_RANGE1_BASE_IDX', + 'regRCC_DEV0_0_RCC_RESET_EN', + 'regRCC_DEV0_0_RCC_RESET_EN_BASE_IDX', + 'regRCC_DEV0_0_RCC_VDM_SUPPORT', + 'regRCC_DEV0_0_RCC_VDM_SUPPORT_BASE_IDX', + 'regRCC_DEV0_0_RCC_XDMA_HI', 'regRCC_DEV0_0_RCC_XDMA_HI_BASE_IDX', + 'regRCC_DEV0_0_RCC_XDMA_LO', 'regRCC_DEV0_0_RCC_XDMA_LO_BASE_IDX', + 'regRCC_DEV0_1_RCC_BACO_CNTL_MISC', + 'regRCC_DEV0_1_RCC_BACO_CNTL_MISC_BASE_IDX', + 'regRCC_DEV0_1_RCC_BUSNUM_CNTL1', + 'regRCC_DEV0_1_RCC_BUSNUM_CNTL1_BASE_IDX', + 'regRCC_DEV0_1_RCC_BUSNUM_CNTL2', + 'regRCC_DEV0_1_RCC_BUSNUM_CNTL2_BASE_IDX', + 'regRCC_DEV0_1_RCC_BUSNUM_LIST0', + 'regRCC_DEV0_1_RCC_BUSNUM_LIST0_BASE_IDX', + 'regRCC_DEV0_1_RCC_BUSNUM_LIST1', + 'regRCC_DEV0_1_RCC_BUSNUM_LIST1_BASE_IDX', + 'regRCC_DEV0_1_RCC_BUS_CNTL', + 'regRCC_DEV0_1_RCC_BUS_CNTL_BASE_IDX', + 'regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM', + 'regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX', + 'regRCC_DEV0_1_RCC_CMN_LINK_CNTL', + 'regRCC_DEV0_1_RCC_CMN_LINK_CNTL_BASE_IDX', + 'regRCC_DEV0_1_RCC_CONFIG_APER_SIZE', + 'regRCC_DEV0_1_RCC_CONFIG_APER_SIZE_BASE_IDX', + 'regRCC_DEV0_1_RCC_CONFIG_CNTL', + 'regRCC_DEV0_1_RCC_CONFIG_CNTL_BASE_IDX', + 'regRCC_DEV0_1_RCC_CONFIG_F0_BASE', + 'regRCC_DEV0_1_RCC_CONFIG_F0_BASE_BASE_IDX', + 'regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE', + 'regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE_BASE_IDX', + 'regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET', + 'regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX', + 'regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL', + 'regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX', + 'regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE', + 'regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX', + 'regRCC_DEV0_1_RCC_DEV0_LINK_CNTL', + 'regRCC_DEV0_1_RCC_DEV0_LINK_CNTL_BASE_IDX', + 'regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0', + 'regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0_BASE_IDX', + 'regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1', + 'regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1_BASE_IDX', + 'regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE', + 'regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_BASE_IDX', + 'regRCC_DEV0_1_RCC_ERR_INT_CNTL', + 'regRCC_DEV0_1_RCC_ERR_INT_CNTL_BASE_IDX', + 'regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC', + 'regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_BASE_IDX', + 'regRCC_DEV0_1_RCC_GPUIOV_REGION', + 'regRCC_DEV0_1_RCC_GPUIOV_REGION_BASE_IDX', + 'regRCC_DEV0_1_RCC_GPU_HOSTVM_EN', + 'regRCC_DEV0_1_RCC_GPU_HOSTVM_EN_BASE_IDX', + 'regRCC_DEV0_1_RCC_HOST_BUSNUM', + 'regRCC_DEV0_1_RCC_HOST_BUSNUM_BASE_IDX', + 'regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL', + 'regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_BASE_IDX', + 'regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0', + 'regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_BASE_IDX', + 'regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1', + 'regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_BASE_IDX', + 'regRCC_DEV0_1_RCC_MH_ARB_CNTL', + 'regRCC_DEV0_1_RCC_MH_ARB_CNTL_BASE_IDX', + 'regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI', + 'regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI_BASE_IDX', + 'regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO', + 'regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO_BASE_IDX', + 'regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI', + 'regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI_BASE_IDX', + 'regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO', + 'regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO_BASE_IDX', + 'regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI', + 'regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI_BASE_IDX', + 'regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO', + 'regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO_BASE_IDX', + 'regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI', + 'regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI_BASE_IDX', + 'regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO', + 'regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO_BASE_IDX', + 'regRCC_DEV0_1_RCC_PEER_REG_RANGE0', + 'regRCC_DEV0_1_RCC_PEER_REG_RANGE0_BASE_IDX', + 'regRCC_DEV0_1_RCC_PEER_REG_RANGE1', + 'regRCC_DEV0_1_RCC_PEER_REG_RANGE1_BASE_IDX', + 'regRCC_DEV0_1_RCC_RESET_EN', + 'regRCC_DEV0_1_RCC_RESET_EN_BASE_IDX', + 'regRCC_DEV0_1_RCC_VDM_SUPPORT', + 'regRCC_DEV0_1_RCC_VDM_SUPPORT_BASE_IDX', + 'regRCC_DEV0_1_RCC_XDMA_HI', 'regRCC_DEV0_1_RCC_XDMA_HI_BASE_IDX', + 'regRCC_DEV0_1_RCC_XDMA_LO', 'regRCC_DEV0_1_RCC_XDMA_LO_BASE_IDX', + 'regRCC_DEV0_2_RCC_BUS_CNTL', + 'regRCC_DEV0_2_RCC_BUS_CNTL_BASE_IDX', + 'regRCC_DEV0_2_RCC_CMN_LINK_CNTL', + 'regRCC_DEV0_2_RCC_CMN_LINK_CNTL_BASE_IDX', + 'regRCC_DEV0_2_RCC_DEV0_LINK_CNTL', + 'regRCC_DEV0_2_RCC_DEV0_LINK_CNTL_BASE_IDX', + 'regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE', + 'regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE_BASE_IDX', + 'regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC', + 'regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC_BASE_IDX', + 'regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL', + 'regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL_BASE_IDX', + 'regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0', + 'regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0_BASE_IDX', + 'regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1', + 'regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1_BASE_IDX', + 'regRCC_DEV0_2_RCC_MH_ARB_CNTL', + 'regRCC_DEV0_2_RCC_MH_ARB_CNTL_BASE_IDX', + 'regRCC_DEV0_2_RCC_VDM_SUPPORT', + 'regRCC_DEV0_2_RCC_VDM_SUPPORT_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA', + 'regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE', + 'regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED', + 'regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN', + 'regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG', + 'regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX', + 'regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER', + 'regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX', + 'regRCC_DEV0_EPF2_STRAP0', 'regRCC_DEV0_EPF2_STRAP0_BASE_IDX', + 'regRCC_DEV0_EPF2_STRAP10', 'regRCC_DEV0_EPF2_STRAP10_BASE_IDX', + 'regRCC_DEV0_EPF2_STRAP11', 'regRCC_DEV0_EPF2_STRAP11_BASE_IDX', + 'regRCC_DEV0_EPF2_STRAP12', 'regRCC_DEV0_EPF2_STRAP12_BASE_IDX', + 'regRCC_DEV0_EPF2_STRAP13', 'regRCC_DEV0_EPF2_STRAP13_BASE_IDX', + 'regRCC_DEV0_EPF2_STRAP14', 'regRCC_DEV0_EPF2_STRAP14_BASE_IDX', + 'regRCC_DEV0_EPF2_STRAP2', 'regRCC_DEV0_EPF2_STRAP20', + 'regRCC_DEV0_EPF2_STRAP20_BASE_IDX', + 'regRCC_DEV0_EPF2_STRAP2_BASE_IDX', 'regRCC_DEV0_EPF2_STRAP3', + 'regRCC_DEV0_EPF2_STRAP3_BASE_IDX', 'regRCC_DEV0_EPF2_STRAP4', + 'regRCC_DEV0_EPF2_STRAP4_BASE_IDX', 'regRCC_DEV0_EPF2_STRAP5', + 'regRCC_DEV0_EPF2_STRAP5_BASE_IDX', 'regRCC_DEV0_EPF2_STRAP6', + 'regRCC_DEV0_EPF2_STRAP6_BASE_IDX', 'regRCC_DEV0_EPF2_STRAP7', + 'regRCC_DEV0_EPF2_STRAP7_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP0', + 'regRCC_DEV0_EPF3_STRAP0_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP10', + 'regRCC_DEV0_EPF3_STRAP10_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP11', + 'regRCC_DEV0_EPF3_STRAP11_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP12', + 'regRCC_DEV0_EPF3_STRAP12_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP13', + 'regRCC_DEV0_EPF3_STRAP13_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP14', + 'regRCC_DEV0_EPF3_STRAP14_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP2', + 'regRCC_DEV0_EPF3_STRAP20', 'regRCC_DEV0_EPF3_STRAP20_BASE_IDX', + 'regRCC_DEV0_EPF3_STRAP2_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP3', + 'regRCC_DEV0_EPF3_STRAP3_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP4', + 'regRCC_DEV0_EPF3_STRAP4_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP5', + 'regRCC_DEV0_EPF3_STRAP5_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP6', + 'regRCC_DEV0_EPF3_STRAP6_BASE_IDX', 'regRCC_DEV0_EPF3_STRAP7', + 'regRCC_DEV0_EPF3_STRAP7_BASE_IDX', 'regRCC_DEV0_EPF4_STRAP0', + 'regRCC_DEV0_EPF4_STRAP0_BASE_IDX', 'regRCC_DEV0_EPF4_STRAP13', + 'regRCC_DEV0_EPF4_STRAP13_BASE_IDX', 'regRCC_DEV0_EPF4_STRAP14', + 'regRCC_DEV0_EPF4_STRAP14_BASE_IDX', 'regRCC_DEV0_EPF4_STRAP2', + 'regRCC_DEV0_EPF4_STRAP2_BASE_IDX', 'regRCC_DEV0_EPF4_STRAP3', + 'regRCC_DEV0_EPF4_STRAP3_BASE_IDX', 'regRCC_DEV0_EPF4_STRAP4', + 'regRCC_DEV0_EPF4_STRAP4_BASE_IDX', 'regRCC_DEV0_EPF4_STRAP5', + 'regRCC_DEV0_EPF4_STRAP5_BASE_IDX', 'regRCC_DEV0_EPF4_STRAP6', + 'regRCC_DEV0_EPF4_STRAP6_BASE_IDX', 'regRCC_DEV0_EPF4_STRAP7', + 'regRCC_DEV0_EPF4_STRAP7_BASE_IDX', 'regRCC_DEV0_EPF5_STRAP0', + 'regRCC_DEV0_EPF5_STRAP0_BASE_IDX', 'regRCC_DEV0_EPF5_STRAP13', + 'regRCC_DEV0_EPF5_STRAP13_BASE_IDX', 'regRCC_DEV0_EPF5_STRAP14', + 'regRCC_DEV0_EPF5_STRAP14_BASE_IDX', 'regRCC_DEV0_EPF5_STRAP2', + 'regRCC_DEV0_EPF5_STRAP2_BASE_IDX', 'regRCC_DEV0_EPF5_STRAP3', + 'regRCC_DEV0_EPF5_STRAP3_BASE_IDX', 'regRCC_DEV0_EPF5_STRAP4', + 'regRCC_DEV0_EPF5_STRAP4_BASE_IDX', 'regRCC_DEV0_EPF5_STRAP5', + 'regRCC_DEV0_EPF5_STRAP5_BASE_IDX', 'regRCC_DEV0_EPF5_STRAP6', + 'regRCC_DEV0_EPF5_STRAP6_BASE_IDX', 'regRCC_DEV0_EPF5_STRAP7', + 'regRCC_DEV0_EPF5_STRAP7_BASE_IDX', 'regRCC_DEV0_EPF6_STRAP0', + 'regRCC_DEV0_EPF6_STRAP0_BASE_IDX', 'regRCC_DEV0_EPF6_STRAP13', + 'regRCC_DEV0_EPF6_STRAP13_BASE_IDX', 'regRCC_DEV0_EPF6_STRAP14', + 'regRCC_DEV0_EPF6_STRAP14_BASE_IDX', 'regRCC_DEV0_EPF6_STRAP2', + 'regRCC_DEV0_EPF6_STRAP2_BASE_IDX', 'regRCC_DEV0_EPF6_STRAP3', + 'regRCC_DEV0_EPF6_STRAP3_BASE_IDX', 'regRCC_DEV0_EPF6_STRAP4', + 'regRCC_DEV0_EPF6_STRAP4_BASE_IDX', 'regRCC_DEV0_EPF6_STRAP5', + 'regRCC_DEV0_EPF6_STRAP5_BASE_IDX', 'regRCC_DEV0_EPF6_STRAP6', + 'regRCC_DEV0_EPF6_STRAP6_BASE_IDX', 'regRCC_DEV0_EPF7_STRAP0', + 'regRCC_DEV0_EPF7_STRAP0_BASE_IDX', 'regRCC_DEV0_EPF7_STRAP13', + 'regRCC_DEV0_EPF7_STRAP13_BASE_IDX', 'regRCC_DEV0_EPF7_STRAP14', + 'regRCC_DEV0_EPF7_STRAP14_BASE_IDX', 'regRCC_DEV0_EPF7_STRAP2', + 'regRCC_DEV0_EPF7_STRAP2_BASE_IDX', 'regRCC_DEV0_EPF7_STRAP3', + 'regRCC_DEV0_EPF7_STRAP3_BASE_IDX', 'regRCC_DEV0_EPF7_STRAP4', + 'regRCC_DEV0_EPF7_STRAP4_BASE_IDX', 'regRCC_DEV0_EPF7_STRAP5', + 'regRCC_DEV0_EPF7_STRAP5_BASE_IDX', 'regRCC_DEV0_EPF7_STRAP6', + 'regRCC_DEV0_EPF7_STRAP6_BASE_IDX', 'regRCC_DEV0_EPF7_STRAP7', + 'regRCC_DEV0_EPF7_STRAP7_BASE_IDX', 'regRCC_DEV1_EPF0_STRAP0', + 'regRCC_DEV1_EPF0_STRAP0_BASE_IDX', 'regRCC_DEV1_EPF0_STRAP13', + 'regRCC_DEV1_EPF0_STRAP13_BASE_IDX', 'regRCC_DEV1_EPF0_STRAP14', + 'regRCC_DEV1_EPF0_STRAP14_BASE_IDX', 'regRCC_DEV1_EPF0_STRAP2', + 'regRCC_DEV1_EPF0_STRAP2_BASE_IDX', 'regRCC_DEV1_EPF0_STRAP3', + 'regRCC_DEV1_EPF0_STRAP3_BASE_IDX', 'regRCC_DEV1_EPF0_STRAP4', + 'regRCC_DEV1_EPF0_STRAP4_BASE_IDX', 'regRCC_DEV1_EPF0_STRAP5', + 'regRCC_DEV1_EPF0_STRAP5_BASE_IDX', 'regRCC_DEV1_EPF0_STRAP6', + 'regRCC_DEV1_EPF0_STRAP6_BASE_IDX', 'regRCC_DEV1_EPF0_STRAP7', + 'regRCC_DEV1_EPF0_STRAP7_BASE_IDX', 'regRCC_DEV1_EPF1_STRAP0', + 'regRCC_DEV1_EPF1_STRAP0_BASE_IDX', 'regRCC_DEV1_EPF1_STRAP13', + 'regRCC_DEV1_EPF1_STRAP13_BASE_IDX', 'regRCC_DEV1_EPF1_STRAP14', + 'regRCC_DEV1_EPF1_STRAP14_BASE_IDX', 'regRCC_DEV1_EPF1_STRAP2', + 'regRCC_DEV1_EPF1_STRAP2_BASE_IDX', 'regRCC_DEV1_EPF1_STRAP3', + 'regRCC_DEV1_EPF1_STRAP3_BASE_IDX', 'regRCC_DEV1_EPF1_STRAP4', + 'regRCC_DEV1_EPF1_STRAP4_BASE_IDX', 'regRCC_DEV1_EPF1_STRAP5', + 'regRCC_DEV1_EPF1_STRAP5_BASE_IDX', 'regRCC_DEV1_EPF1_STRAP6', + 'regRCC_DEV1_EPF1_STRAP6_BASE_IDX', 'regRCC_DEV1_EPF1_STRAP7', + 'regRCC_DEV1_EPF1_STRAP7_BASE_IDX', 'regRCC_DEV1_PORT_STRAP0', + 'regRCC_DEV1_PORT_STRAP0_BASE_IDX', 'regRCC_DEV1_PORT_STRAP1', + 'regRCC_DEV1_PORT_STRAP10', 'regRCC_DEV1_PORT_STRAP10_BASE_IDX', + 'regRCC_DEV1_PORT_STRAP11', 'regRCC_DEV1_PORT_STRAP11_BASE_IDX', + 'regRCC_DEV1_PORT_STRAP12', 'regRCC_DEV1_PORT_STRAP12_BASE_IDX', + 'regRCC_DEV1_PORT_STRAP13', 'regRCC_DEV1_PORT_STRAP13_BASE_IDX', + 'regRCC_DEV1_PORT_STRAP14', 'regRCC_DEV1_PORT_STRAP14_BASE_IDX', + 'regRCC_DEV1_PORT_STRAP1_BASE_IDX', 'regRCC_DEV1_PORT_STRAP2', + 'regRCC_DEV1_PORT_STRAP2_BASE_IDX', 'regRCC_DEV1_PORT_STRAP3', + 'regRCC_DEV1_PORT_STRAP3_BASE_IDX', 'regRCC_DEV1_PORT_STRAP4', + 'regRCC_DEV1_PORT_STRAP4_BASE_IDX', 'regRCC_DEV1_PORT_STRAP5', + 'regRCC_DEV1_PORT_STRAP5_BASE_IDX', 'regRCC_DEV1_PORT_STRAP6', + 'regRCC_DEV1_PORT_STRAP6_BASE_IDX', 'regRCC_DEV1_PORT_STRAP7', + 'regRCC_DEV1_PORT_STRAP7_BASE_IDX', 'regRCC_DEV1_PORT_STRAP8', + 'regRCC_DEV1_PORT_STRAP8_BASE_IDX', 'regRCC_DEV1_PORT_STRAP9', + 'regRCC_DEV1_PORT_STRAP9_BASE_IDX', 'regRCC_DEV2_EPF0_STRAP0', + 'regRCC_DEV2_EPF0_STRAP0_BASE_IDX', 'regRCC_DEV2_EPF0_STRAP13', + 'regRCC_DEV2_EPF0_STRAP13_BASE_IDX', 'regRCC_DEV2_EPF0_STRAP14', + 'regRCC_DEV2_EPF0_STRAP14_BASE_IDX', 'regRCC_DEV2_EPF0_STRAP2', + 'regRCC_DEV2_EPF0_STRAP2_BASE_IDX', 'regRCC_DEV2_EPF0_STRAP3', + 'regRCC_DEV2_EPF0_STRAP3_BASE_IDX', 'regRCC_DEV2_EPF0_STRAP4', + 'regRCC_DEV2_EPF0_STRAP4_BASE_IDX', 'regRCC_DEV2_EPF0_STRAP5', + 'regRCC_DEV2_EPF0_STRAP5_BASE_IDX', 'regRCC_DEV2_EPF0_STRAP6', + 'regRCC_DEV2_EPF0_STRAP6_BASE_IDX', 'regRCC_DEV2_EPF0_STRAP7', + 'regRCC_DEV2_EPF0_STRAP7_BASE_IDX', 'regRCC_DEV2_EPF1_STRAP0', + 'regRCC_DEV2_EPF1_STRAP0_BASE_IDX', 'regRCC_DEV2_EPF1_STRAP13', + 'regRCC_DEV2_EPF1_STRAP13_BASE_IDX', 'regRCC_DEV2_EPF1_STRAP14', + 'regRCC_DEV2_EPF1_STRAP14_BASE_IDX', 'regRCC_DEV2_EPF1_STRAP2', + 'regRCC_DEV2_EPF1_STRAP2_BASE_IDX', 'regRCC_DEV2_EPF1_STRAP3', + 'regRCC_DEV2_EPF1_STRAP3_BASE_IDX', 'regRCC_DEV2_EPF1_STRAP4', + 'regRCC_DEV2_EPF1_STRAP4_BASE_IDX', 'regRCC_DEV2_EPF1_STRAP5', + 'regRCC_DEV2_EPF1_STRAP5_BASE_IDX', 'regRCC_DEV2_EPF1_STRAP6', + 'regRCC_DEV2_EPF1_STRAP6_BASE_IDX', 'regRCC_DEV2_EPF2_STRAP0', + 'regRCC_DEV2_EPF2_STRAP0_BASE_IDX', 'regRCC_DEV2_EPF2_STRAP13', + 'regRCC_DEV2_EPF2_STRAP13_BASE_IDX', 'regRCC_DEV2_EPF2_STRAP14', + 'regRCC_DEV2_EPF2_STRAP14_BASE_IDX', 'regRCC_DEV2_EPF2_STRAP2', + 'regRCC_DEV2_EPF2_STRAP2_BASE_IDX', 'regRCC_DEV2_EPF2_STRAP3', + 'regRCC_DEV2_EPF2_STRAP3_BASE_IDX', 'regRCC_DEV2_EPF2_STRAP4', + 'regRCC_DEV2_EPF2_STRAP4_BASE_IDX', 'regRCC_DEV2_EPF2_STRAP5', + 'regRCC_DEV2_EPF2_STRAP5_BASE_IDX', 'regRCC_DEV2_EPF2_STRAP6', + 'regRCC_DEV2_EPF2_STRAP6_BASE_IDX', 'regRCC_DEV2_PORT_STRAP0', + 'regRCC_DEV2_PORT_STRAP0_BASE_IDX', 'regRCC_DEV2_PORT_STRAP1', + 'regRCC_DEV2_PORT_STRAP10', 'regRCC_DEV2_PORT_STRAP10_BASE_IDX', + 'regRCC_DEV2_PORT_STRAP11', 'regRCC_DEV2_PORT_STRAP11_BASE_IDX', + 'regRCC_DEV2_PORT_STRAP12', 'regRCC_DEV2_PORT_STRAP12_BASE_IDX', + 'regRCC_DEV2_PORT_STRAP13', 'regRCC_DEV2_PORT_STRAP13_BASE_IDX', + 'regRCC_DEV2_PORT_STRAP14', 'regRCC_DEV2_PORT_STRAP14_BASE_IDX', + 'regRCC_DEV2_PORT_STRAP1_BASE_IDX', 'regRCC_DEV2_PORT_STRAP2', + 'regRCC_DEV2_PORT_STRAP2_BASE_IDX', 'regRCC_DEV2_PORT_STRAP3', + 'regRCC_DEV2_PORT_STRAP3_BASE_IDX', 'regRCC_DEV2_PORT_STRAP4', + 'regRCC_DEV2_PORT_STRAP4_BASE_IDX', 'regRCC_DEV2_PORT_STRAP5', + 'regRCC_DEV2_PORT_STRAP5_BASE_IDX', 'regRCC_DEV2_PORT_STRAP6', + 'regRCC_DEV2_PORT_STRAP6_BASE_IDX', 'regRCC_DEV2_PORT_STRAP7', + 'regRCC_DEV2_PORT_STRAP7_BASE_IDX', 'regRCC_DEV2_PORT_STRAP8', + 'regRCC_DEV2_PORT_STRAP8_BASE_IDX', 'regRCC_DEV2_PORT_STRAP9', + 'regRCC_DEV2_PORT_STRAP9_BASE_IDX', + 'regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP', + 'regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_BASE_IDX', + 'regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC', + 'regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_BASE_IDX', + 'regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL', + 'regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_BASE_IDX', + 'regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2', + 'regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_BASE_IDX', + 'regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL', + 'regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_BASE_IDX', + 'regRCC_DWNP_DEV0_0_PCIE_RX_CNTL', + 'regRCC_DWNP_DEV0_0_PCIE_RX_CNTL_BASE_IDX', + 'regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP', + 'regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_BASE_IDX', + 'regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC', + 'regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_BASE_IDX', + 'regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL', + 'regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_BASE_IDX', + 'regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2', + 'regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_BASE_IDX', + 'regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL', + 'regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_BASE_IDX', + 'regRCC_DWNP_DEV0_1_PCIE_RX_CNTL', + 'regRCC_DWNP_DEV0_1_PCIE_RX_CNTL_BASE_IDX', + 'regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP', + 'regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP_BASE_IDX', + 'regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC', + 'regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC_BASE_IDX', + 'regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL', + 'regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL_BASE_IDX', + 'regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2', + 'regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2_BASE_IDX', + 'regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL', + 'regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL_BASE_IDX', + 'regRCC_DWNP_DEV0_2_PCIE_RX_CNTL', + 'regRCC_DWNP_DEV0_2_PCIE_RX_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL', + 'regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL', + 'regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_0_DN_PCIE_CNTL', + 'regRCC_DWN_DEV0_0_DN_PCIE_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL', + 'regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_0_DN_PCIE_RESERVED', + 'regRCC_DWN_DEV0_0_DN_PCIE_RESERVED_BASE_IDX', + 'regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2', + 'regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_BASE_IDX', + 'regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH', + 'regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_BASE_IDX', + 'regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0', + 'regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_BASE_IDX', + 'regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC', + 'regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2', + 'regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_BASE_IDX', + 'regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_BASE_IDX', + 'regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL', + 'regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL', + 'regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_1_DN_PCIE_CNTL', + 'regRCC_DWN_DEV0_1_DN_PCIE_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL', + 'regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_1_DN_PCIE_RESERVED', + 'regRCC_DWN_DEV0_1_DN_PCIE_RESERVED_BASE_IDX', + 'regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2', + 'regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_BASE_IDX', + 'regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH', + 'regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_BASE_IDX', + 'regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0', + 'regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_BASE_IDX', + 'regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC', + 'regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2', + 'regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_BASE_IDX', + 'regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_BASE_IDX', + 'regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL', + 'regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL', + 'regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_2_DN_PCIE_CNTL', + 'regRCC_DWN_DEV0_2_DN_PCIE_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL', + 'regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL_BASE_IDX', + 'regRCC_DWN_DEV0_2_DN_PCIE_RESERVED', + 'regRCC_DWN_DEV0_2_DN_PCIE_RESERVED_BASE_IDX', + 'regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2', + 'regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2_BASE_IDX', + 'regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH', + 'regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH_BASE_IDX', + 'regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0', + 'regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0_BASE_IDX', + 'regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC', + 'regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2', + 'regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2_BASE_IDX', + 'regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIEP_RESERVED', + 'regRCC_EP_DEV0_0_EP_PCIEP_RESERVED_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL', + 'regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL', + 'regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_CNTL', + 'regRCC_EP_DEV0_0_EP_PCIE_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL', + 'regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP', + 'regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL', + 'regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR', + 'regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL', + 'regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS', + 'regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL', + 'regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL', + 'regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL', + 'regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2', + 'regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_SCRATCH', + 'regRCC_EP_DEV0_0_EP_PCIE_SCRATCH_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC', + 'regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2', + 'regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL', + 'regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL', + 'regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID', + 'regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7', + 'regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7', + 'regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIEP_RESERVED', + 'regRCC_EP_DEV0_1_EP_PCIEP_RESERVED_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL', + 'regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL', + 'regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_CNTL', + 'regRCC_EP_DEV0_1_EP_PCIE_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL', + 'regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP', + 'regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL', + 'regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR', + 'regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL', + 'regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS', + 'regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL', + 'regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL', + 'regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL', + 'regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2', + 'regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_SCRATCH', + 'regRCC_EP_DEV0_1_EP_PCIE_SCRATCH_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC', + 'regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2', + 'regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL', + 'regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL', + 'regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID', + 'regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7', + 'regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7', + 'regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIEP_RESERVED', + 'regRCC_EP_DEV0_2_EP_PCIEP_RESERVED_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL', + 'regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL', + 'regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_CNTL', + 'regRCC_EP_DEV0_2_EP_PCIE_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL', + 'regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP', + 'regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL', + 'regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR', + 'regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL', + 'regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS', + 'regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL', + 'regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL', + 'regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL', + 'regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2', + 'regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_SCRATCH', + 'regRCC_EP_DEV0_2_EP_PCIE_SCRATCH_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC', + 'regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2', + 'regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL', + 'regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL', + 'regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL_BASE_IDX', + 'regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID', + 'regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID_BASE_IDX', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7', + 'regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX', + 'regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL', + 'regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL_BASE_IDX', + 'regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL', + 'regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL_BASE_IDX', + 'regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE', + 'regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE_BASE_IDX', + 'regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0', + 'regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0_BASE_IDX', + 'regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1', + 'regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1_BASE_IDX', + 'regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2', + 'regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2_BASE_IDX', + 'regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3', + 'regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3_BASE_IDX', + 'regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4', + 'regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4_BASE_IDX', + 'regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5', + 'regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5_BASE_IDX', + 'regRCC_STRAP0_RCC_BIF_STRAP0', + 'regRCC_STRAP0_RCC_BIF_STRAP0_BASE_IDX', + 'regRCC_STRAP0_RCC_BIF_STRAP1', + 'regRCC_STRAP0_RCC_BIF_STRAP1_BASE_IDX', + 'regRCC_STRAP0_RCC_BIF_STRAP2', + 'regRCC_STRAP0_RCC_BIF_STRAP2_BASE_IDX', + 'regRCC_STRAP0_RCC_BIF_STRAP3', + 'regRCC_STRAP0_RCC_BIF_STRAP3_BASE_IDX', + 'regRCC_STRAP0_RCC_BIF_STRAP4', + 'regRCC_STRAP0_RCC_BIF_STRAP4_BASE_IDX', + 'regRCC_STRAP0_RCC_BIF_STRAP5', + 'regRCC_STRAP0_RCC_BIF_STRAP5_BASE_IDX', + 'regRCC_STRAP0_RCC_BIF_STRAP6', + 'regRCC_STRAP0_RCC_BIF_STRAP6_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9', + 'regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7', + 'regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP0', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP0_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP1', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP10', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP10_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP11', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP11_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP12', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP12_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP13', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP13_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP14', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP14_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP1_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP2', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP2_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP3', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP3_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP4', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP4_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP5', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP5_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP6', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP6_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP7', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP7_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP8', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP8_BASE_IDX', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP9', + 'regRCC_STRAP0_RCC_DEV0_PORT_STRAP9_BASE_IDX', + 'regRCC_STRAP1_RCC_BIF_STRAP0', + 'regRCC_STRAP1_RCC_BIF_STRAP0_BASE_IDX', + 'regRCC_STRAP1_RCC_BIF_STRAP1', + 'regRCC_STRAP1_RCC_BIF_STRAP1_BASE_IDX', + 'regRCC_STRAP1_RCC_BIF_STRAP2', + 'regRCC_STRAP1_RCC_BIF_STRAP2_BASE_IDX', + 'regRCC_STRAP1_RCC_BIF_STRAP3', + 'regRCC_STRAP1_RCC_BIF_STRAP3_BASE_IDX', + 'regRCC_STRAP1_RCC_BIF_STRAP4', + 'regRCC_STRAP1_RCC_BIF_STRAP4_BASE_IDX', + 'regRCC_STRAP1_RCC_BIF_STRAP5', + 'regRCC_STRAP1_RCC_BIF_STRAP5_BASE_IDX', + 'regRCC_STRAP1_RCC_BIF_STRAP6', + 'regRCC_STRAP1_RCC_BIF_STRAP6_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9', + 'regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7', + 'regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP0', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP0_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP1', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP10', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP10_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP11', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP11_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP12', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP12_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP13', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP13_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP14', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP14_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP1_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP2', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP2_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP3', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP3_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP4', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP4_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP5', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP5_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP6', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP6_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP7', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP7_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP8', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP8_BASE_IDX', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP9', + 'regRCC_STRAP1_RCC_DEV0_PORT_STRAP9_BASE_IDX', + 'regRCC_STRAP2_RCC_BIF_STRAP0', + 'regRCC_STRAP2_RCC_BIF_STRAP0_BASE_IDX', + 'regRCC_STRAP2_RCC_BIF_STRAP1', + 'regRCC_STRAP2_RCC_BIF_STRAP1_BASE_IDX', + 'regRCC_STRAP2_RCC_BIF_STRAP2', + 'regRCC_STRAP2_RCC_BIF_STRAP2_BASE_IDX', + 'regRCC_STRAP2_RCC_BIF_STRAP3', + 'regRCC_STRAP2_RCC_BIF_STRAP3_BASE_IDX', + 'regRCC_STRAP2_RCC_BIF_STRAP4', + 'regRCC_STRAP2_RCC_BIF_STRAP4_BASE_IDX', + 'regRCC_STRAP2_RCC_BIF_STRAP5', + 'regRCC_STRAP2_RCC_BIF_STRAP5_BASE_IDX', + 'regRCC_STRAP2_RCC_BIF_STRAP6', + 'regRCC_STRAP2_RCC_BIF_STRAP6_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9', + 'regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7', + 'regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP0', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP0_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP1', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP10', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP10_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP11', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP11_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP12', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP12_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP13', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP13_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP14', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP14_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP1_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP2', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP2_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP3', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP3_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP4', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP4_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP5', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP5_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP6', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP6_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP7', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP7_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP8', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP8_BASE_IDX', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP9', + 'regRCC_STRAP2_RCC_DEV0_PORT_STRAP9_BASE_IDX', + 'regREGS_ROM_OFFSET_CTRL', 'regREGS_ROM_OFFSET_CTRL_BASE_IDX', + 'regS2A_DOORBELL_COMMON_CTRL_REG', + 'regS2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_0_CTRL', + 'regS2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_10_CTRL', + 'regS2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_11_CTRL', + 'regS2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_12_CTRL', + 'regS2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_13_CTRL', + 'regS2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_14_CTRL', + 'regS2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_15_CTRL', + 'regS2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_1_CTRL', + 'regS2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_2_CTRL', + 'regS2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_3_CTRL', + 'regS2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_4_CTRL', + 'regS2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_5_CTRL', + 'regS2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_6_CTRL', + 'regS2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_7_CTRL', + 'regS2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_8_CTRL', + 'regS2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX', + 'regS2A_DOORBELL_ENTRY_9_CTRL', + 'regS2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX', 'regSB_COMMAND', + 'regSB_COMMAND_BASE_IDX', 'regSB_DEVICE_CNTL2', + 'regSB_DEVICE_CNTL2_BASE_IDX', 'regSB_EXT_BRIDGE_CNTL', + 'regSB_EXT_BRIDGE_CNTL_BASE_IDX', 'regSB_IO_BASE_LIMIT', + 'regSB_IO_BASE_LIMIT_BASE_IDX', 'regSB_IO_BASE_LIMIT_HI', + 'regSB_IO_BASE_LIMIT_HI_BASE_IDX', 'regSB_IRQ_BRIDGE_CNTL', + 'regSB_IRQ_BRIDGE_CNTL_BASE_IDX', 'regSB_LOCATION', + 'regSB_LOCATION_BASE_IDX', 'regSB_MEM_BASE_LIMIT', + 'regSB_MEM_BASE_LIMIT_BASE_IDX', 'regSB_PMI_STATUS_CNTL', + 'regSB_PMI_STATUS_CNTL_BASE_IDX', 'regSB_PREF_BASE_LIMIT', + 'regSB_PREF_BASE_LIMIT_BASE_IDX', 'regSB_PREF_BASE_UPPER', + 'regSB_PREF_BASE_UPPER_BASE_IDX', 'regSB_PREF_LIMIT_UPPER', + 'regSB_PREF_LIMIT_UPPER_BASE_IDX', 'regSB_ROOT_CNTL', + 'regSB_ROOT_CNTL_BASE_IDX', 'regSB_SLOT_CAP', + 'regSB_SLOT_CAP_BASE_IDX', 'regSB_SUB_BUS_NUMBER_LATENCY', + 'regSB_SUB_BUS_NUMBER_LATENCY_BASE_IDX', 'regSCRATCH_4', + 'regSCRATCH_4_BASE_IDX', 'regSCRATCH_5', 'regSCRATCH_5_BASE_IDX', + 'regSELF_SOFT_RST', 'regSELF_SOFT_RST_2', + 'regSELF_SOFT_RST_2_BASE_IDX', 'regSELF_SOFT_RST_BASE_IDX', + 'regSHUB_GFX_DRV_VPU_RST', 'regSHUB_GFX_DRV_VPU_RST_BASE_IDX', + 'regSHUB_HARD_RST_CTRL', 'regSHUB_HARD_RST_CTRL_BASE_IDX', + 'regSHUB_LINK_RESET', 'regSHUB_LINK_RESET_BASE_IDX', + 'regSHUB_PF_FLR_RST', 'regSHUB_PF_FLR_RST_BASE_IDX', + 'regSHUB_RST_MISC_TRL', 'regSHUB_RST_MISC_TRL_BASE_IDX', + 'regSHUB_SDP_PORT_RST', 'regSHUB_SDP_PORT_RST_BASE_IDX', + 'regSHUB_SOFT_RST_CTRL', 'regSHUB_SOFT_RST_CTRL_BASE_IDX', + 'regSMN_MST_CNTL0', 'regSMN_MST_CNTL0_BASE_IDX', + 'regSMN_MST_CNTL1', 'regSMN_MST_CNTL1_BASE_IDX', + 'regSMN_MST_EP_CNTL1', 'regSMN_MST_EP_CNTL1_BASE_IDX', + 'regSMN_MST_EP_CNTL2', 'regSMN_MST_EP_CNTL2_BASE_IDX', + 'regSMN_MST_EP_CNTL3', 'regSMN_MST_EP_CNTL3_BASE_IDX', + 'regSMN_MST_EP_CNTL4', 'regSMN_MST_EP_CNTL4_BASE_IDX', + 'regSMN_MST_EP_CNTL5', 'regSMN_MST_EP_CNTL5_BASE_IDX', + 'regSMU_BASE_ADDR_HI', 'regSMU_BASE_ADDR_HI_BASE_IDX', + 'regSMU_BASE_ADDR_LO', 'regSMU_BASE_ADDR_LO_BASE_IDX', + 'regSMU_BLOCK_CPU', 'regSMU_BLOCK_CPU_BASE_IDX', + 'regSMU_BLOCK_CPU_STATUS', 'regSMU_BLOCK_CPU_STATUS_BASE_IDX', + 'regSTALL_CONTROL_XBARPORT0_0', + 'regSTALL_CONTROL_XBARPORT0_0_BASE_IDX', + 'regSTALL_CONTROL_XBARPORT0_1', + 'regSTALL_CONTROL_XBARPORT0_1_BASE_IDX', + 'regSTALL_CONTROL_XBARPORT1_0', + 'regSTALL_CONTROL_XBARPORT1_0_BASE_IDX', + 'regSTALL_CONTROL_XBARPORT1_1', + 'regSTALL_CONTROL_XBARPORT1_1_BASE_IDX', + 'regSTALL_CONTROL_XBARPORT2_0', + 'regSTALL_CONTROL_XBARPORT2_0_BASE_IDX', + 'regSTALL_CONTROL_XBARPORT2_1', + 'regSTALL_CONTROL_XBARPORT2_1_BASE_IDX', + 'regSTALL_CONTROL_XBARPORT3_0', + 'regSTALL_CONTROL_XBARPORT3_0_BASE_IDX', + 'regSTALL_CONTROL_XBARPORT3_1', + 'regSTALL_CONTROL_XBARPORT3_1_BASE_IDX', + 'regSTALL_CONTROL_XBARPORT4_0', + 'regSTALL_CONTROL_XBARPORT4_0_BASE_IDX', + 'regSTALL_CONTROL_XBARPORT4_1', + 'regSTALL_CONTROL_XBARPORT4_1_BASE_IDX', + 'regSTALL_CONTROL_XBARPORT5_0', + 'regSTALL_CONTROL_XBARPORT5_0_BASE_IDX', + 'regSTALL_CONTROL_XBARPORT5_1', + 'regSTALL_CONTROL_XBARPORT5_1_BASE_IDX', 'regSUM_DATA', + 'regSUM_DATA_BASE_IDX', 'regSUM_INDEX', 'regSUM_INDEX_BASE_IDX', + 'regSUM_INDEX_HI', 'regSUM_INDEX_HI_BASE_IDX', + 'regSW_GIC_SPI_CNTL', 'regSW_GIC_SPI_CNTL_BASE_IDX', + 'regSW_NMI_CNTL', 'regSW_NMI_CNTL_BASE_IDX', 'regSW_SCI_CNTL', + 'regSW_SCI_CNTL_BASE_IDX', 'regSW_SMI_CNTL', + 'regSW_SMI_CNTL_BASE_IDX', 'regSW_SYNCFLOOD_CNTL', + 'regSW_SYNCFLOOD_CNTL_BASE_IDX', 'regSW_US_LOCATION', + 'regSW_US_LOCATION_BASE_IDX', 'regSYNCFLOOD_STATUS', + 'regSYNCFLOOD_STATUS_BASE_IDX', 'regTRAP0_ADDRESS_HI', + 'regTRAP0_ADDRESS_HI_BASE_IDX', 'regTRAP0_ADDRESS_HI_MASK', + 'regTRAP0_ADDRESS_HI_MASK_BASE_IDX', 'regTRAP0_ADDRESS_LO', + 'regTRAP0_ADDRESS_LO_BASE_IDX', 'regTRAP0_ADDRESS_LO_MASK', + 'regTRAP0_ADDRESS_LO_MASK_BASE_IDX', 'regTRAP0_COMMAND', + 'regTRAP0_COMMAND_BASE_IDX', 'regTRAP0_COMMAND_MASK', + 'regTRAP0_COMMAND_MASK_BASE_IDX', 'regTRAP0_CONTROL0', + 'regTRAP0_CONTROL0_BASE_IDX', 'regTRAP10_ADDRESS_HI', + 'regTRAP10_ADDRESS_HI_BASE_IDX', 'regTRAP10_ADDRESS_HI_MASK', + 'regTRAP10_ADDRESS_HI_MASK_BASE_IDX', 'regTRAP10_ADDRESS_LO', + 'regTRAP10_ADDRESS_LO_BASE_IDX', 'regTRAP10_ADDRESS_LO_MASK', + 'regTRAP10_ADDRESS_LO_MASK_BASE_IDX', 'regTRAP10_COMMAND', + 'regTRAP10_COMMAND_BASE_IDX', 'regTRAP10_COMMAND_MASK', + 'regTRAP10_COMMAND_MASK_BASE_IDX', 'regTRAP10_CONTROL0', + 'regTRAP10_CONTROL0_BASE_IDX', 'regTRAP11_ADDRESS_HI', + 'regTRAP11_ADDRESS_HI_BASE_IDX', 'regTRAP11_ADDRESS_HI_MASK', + 'regTRAP11_ADDRESS_HI_MASK_BASE_IDX', 'regTRAP11_ADDRESS_LO', + 'regTRAP11_ADDRESS_LO_BASE_IDX', 'regTRAP11_ADDRESS_LO_MASK', + 'regTRAP11_ADDRESS_LO_MASK_BASE_IDX', 'regTRAP11_COMMAND', + 'regTRAP11_COMMAND_BASE_IDX', 'regTRAP11_COMMAND_MASK', + 'regTRAP11_COMMAND_MASK_BASE_IDX', 'regTRAP11_CONTROL0', + 'regTRAP11_CONTROL0_BASE_IDX', 'regTRAP12_ADDRESS_HI', + 'regTRAP12_ADDRESS_HI_BASE_IDX', 'regTRAP12_ADDRESS_HI_MASK', + 'regTRAP12_ADDRESS_HI_MASK_BASE_IDX', 'regTRAP12_ADDRESS_LO', + 'regTRAP12_ADDRESS_LO_BASE_IDX', 'regTRAP12_ADDRESS_LO_MASK', + 'regTRAP12_ADDRESS_LO_MASK_BASE_IDX', 'regTRAP12_COMMAND', + 'regTRAP12_COMMAND_BASE_IDX', 'regTRAP12_COMMAND_MASK', + 'regTRAP12_COMMAND_MASK_BASE_IDX', 'regTRAP12_CONTROL0', + 'regTRAP12_CONTROL0_BASE_IDX', 'regTRAP13_ADDRESS_HI', + 'regTRAP13_ADDRESS_HI_BASE_IDX', 'regTRAP13_ADDRESS_HI_MASK', + 'regTRAP13_ADDRESS_HI_MASK_BASE_IDX', 'regTRAP13_ADDRESS_LO', + 'regTRAP13_ADDRESS_LO_BASE_IDX', 'regTRAP13_ADDRESS_LO_MASK', + 'regTRAP13_ADDRESS_LO_MASK_BASE_IDX', 'regTRAP13_COMMAND', + 'regTRAP13_COMMAND_BASE_IDX', 'regTRAP13_COMMAND_MASK', + 'regTRAP13_COMMAND_MASK_BASE_IDX', 'regTRAP13_CONTROL0', + 'regTRAP13_CONTROL0_BASE_IDX', 'regTRAP14_ADDRESS_HI', + 'regTRAP14_ADDRESS_HI_BASE_IDX', 'regTRAP14_ADDRESS_HI_MASK', + 'regTRAP14_ADDRESS_HI_MASK_BASE_IDX', 'regTRAP14_ADDRESS_LO', + 'regTRAP14_ADDRESS_LO_BASE_IDX', 'regTRAP14_ADDRESS_LO_MASK', + 'regTRAP14_ADDRESS_LO_MASK_BASE_IDX', 'regTRAP14_COMMAND', + 'regTRAP14_COMMAND_BASE_IDX', 'regTRAP14_COMMAND_MASK', + 'regTRAP14_COMMAND_MASK_BASE_IDX', 'regTRAP14_CONTROL0', + 'regTRAP14_CONTROL0_BASE_IDX', 'regTRAP15_ADDRESS_HI', + 'regTRAP15_ADDRESS_HI_BASE_IDX', 'regTRAP15_ADDRESS_HI_MASK', + 'regTRAP15_ADDRESS_HI_MASK_BASE_IDX', 'regTRAP15_ADDRESS_LO', + 'regTRAP15_ADDRESS_LO_BASE_IDX', 'regTRAP15_ADDRESS_LO_MASK', + 'regTRAP15_ADDRESS_LO_MASK_BASE_IDX', 'regTRAP15_COMMAND', + 'regTRAP15_COMMAND_BASE_IDX', 'regTRAP15_COMMAND_MASK', + 'regTRAP15_COMMAND_MASK_BASE_IDX', 'regTRAP15_CONTROL0', + 'regTRAP15_CONTROL0_BASE_IDX', 'regTRAP1_ADDRESS_HI', + 'regTRAP1_ADDRESS_HI_BASE_IDX', 'regTRAP1_ADDRESS_HI_MASK', + 'regTRAP1_ADDRESS_HI_MASK_BASE_IDX', 'regTRAP1_ADDRESS_LO', + 'regTRAP1_ADDRESS_LO_BASE_IDX', 'regTRAP1_ADDRESS_LO_MASK', + 'regTRAP1_ADDRESS_LO_MASK_BASE_IDX', 'regTRAP1_COMMAND', + 'regTRAP1_COMMAND_BASE_IDX', 'regTRAP1_COMMAND_MASK', + 'regTRAP1_COMMAND_MASK_BASE_IDX', 'regTRAP1_CONTROL0', + 'regTRAP1_CONTROL0_BASE_IDX', 'regTRAP2_ADDRESS_HI', + 'regTRAP2_ADDRESS_HI_BASE_IDX', 'regTRAP2_ADDRESS_HI_MASK', + 'regTRAP2_ADDRESS_HI_MASK_BASE_IDX', 'regTRAP2_ADDRESS_LO', + 'regTRAP2_ADDRESS_LO_BASE_IDX', 'regTRAP2_ADDRESS_LO_MASK', + 'regTRAP2_ADDRESS_LO_MASK_BASE_IDX', 'regTRAP2_COMMAND', + 'regTRAP2_COMMAND_BASE_IDX', 'regTRAP2_COMMAND_MASK', + 'regTRAP2_COMMAND_MASK_BASE_IDX', 'regTRAP2_CONTROL0', + 'regTRAP2_CONTROL0_BASE_IDX', 'regTRAP3_ADDRESS_HI', + 'regTRAP3_ADDRESS_HI_BASE_IDX', 'regTRAP3_ADDRESS_HI_MASK', + 'regTRAP3_ADDRESS_HI_MASK_BASE_IDX', 'regTRAP3_ADDRESS_LO', + 'regTRAP3_ADDRESS_LO_BASE_IDX', 'regTRAP3_ADDRESS_LO_MASK', + 'regTRAP3_ADDRESS_LO_MASK_BASE_IDX', 'regTRAP3_COMMAND', + 'regTRAP3_COMMAND_BASE_IDX', 'regTRAP3_COMMAND_MASK', + 'regTRAP3_COMMAND_MASK_BASE_IDX', 'regTRAP3_CONTROL0', + 'regTRAP3_CONTROL0_BASE_IDX', 'regTRAP4_ADDRESS_HI', + 'regTRAP4_ADDRESS_HI_BASE_IDX', 'regTRAP4_ADDRESS_HI_MASK', + 'regTRAP4_ADDRESS_HI_MASK_BASE_IDX', 'regTRAP4_ADDRESS_LO', + 'regTRAP4_ADDRESS_LO_BASE_IDX', 'regTRAP4_ADDRESS_LO_MASK', + 'regTRAP4_ADDRESS_LO_MASK_BASE_IDX', 'regTRAP4_COMMAND', + 'regTRAP4_COMMAND_BASE_IDX', 'regTRAP4_COMMAND_MASK', + 'regTRAP4_COMMAND_MASK_BASE_IDX', 'regTRAP4_CONTROL0', + 'regTRAP4_CONTROL0_BASE_IDX', 'regTRAP5_ADDRESS_HI', + 'regTRAP5_ADDRESS_HI_BASE_IDX', 'regTRAP5_ADDRESS_HI_MASK', + 'regTRAP5_ADDRESS_HI_MASK_BASE_IDX', 'regTRAP5_ADDRESS_LO', + 'regTRAP5_ADDRESS_LO_BASE_IDX', 'regTRAP5_ADDRESS_LO_MASK', + 'regTRAP5_ADDRESS_LO_MASK_BASE_IDX', 'regTRAP5_COMMAND', + 'regTRAP5_COMMAND_BASE_IDX', 'regTRAP5_COMMAND_MASK', + 'regTRAP5_COMMAND_MASK_BASE_IDX', 'regTRAP5_CONTROL0', + 'regTRAP5_CONTROL0_BASE_IDX', 'regTRAP6_ADDRESS_HI', + 'regTRAP6_ADDRESS_HI_BASE_IDX', 'regTRAP6_ADDRESS_HI_MASK', + 'regTRAP6_ADDRESS_HI_MASK_BASE_IDX', 'regTRAP6_ADDRESS_LO', + 'regTRAP6_ADDRESS_LO_BASE_IDX', 'regTRAP6_ADDRESS_LO_MASK', + 'regTRAP6_ADDRESS_LO_MASK_BASE_IDX', 'regTRAP6_COMMAND', + 'regTRAP6_COMMAND_BASE_IDX', 'regTRAP6_COMMAND_MASK', + 'regTRAP6_COMMAND_MASK_BASE_IDX', 'regTRAP6_CONTROL0', + 'regTRAP6_CONTROL0_BASE_IDX', 'regTRAP7_ADDRESS_HI', + 'regTRAP7_ADDRESS_HI_BASE_IDX', 'regTRAP7_ADDRESS_HI_MASK', + 'regTRAP7_ADDRESS_HI_MASK_BASE_IDX', 'regTRAP7_ADDRESS_LO', + 'regTRAP7_ADDRESS_LO_BASE_IDX', 'regTRAP7_ADDRESS_LO_MASK', + 'regTRAP7_ADDRESS_LO_MASK_BASE_IDX', 'regTRAP7_COMMAND', + 'regTRAP7_COMMAND_BASE_IDX', 'regTRAP7_COMMAND_MASK', + 'regTRAP7_COMMAND_MASK_BASE_IDX', 'regTRAP7_CONTROL0', + 'regTRAP7_CONTROL0_BASE_IDX', 'regTRAP8_ADDRESS_HI', + 'regTRAP8_ADDRESS_HI_BASE_IDX', 'regTRAP8_ADDRESS_HI_MASK', + 'regTRAP8_ADDRESS_HI_MASK_BASE_IDX', 'regTRAP8_ADDRESS_LO', + 'regTRAP8_ADDRESS_LO_BASE_IDX', 'regTRAP8_ADDRESS_LO_MASK', + 'regTRAP8_ADDRESS_LO_MASK_BASE_IDX', 'regTRAP8_COMMAND', + 'regTRAP8_COMMAND_BASE_IDX', 'regTRAP8_COMMAND_MASK', + 'regTRAP8_COMMAND_MASK_BASE_IDX', 'regTRAP8_CONTROL0', + 'regTRAP8_CONTROL0_BASE_IDX', 'regTRAP9_ADDRESS_HI', + 'regTRAP9_ADDRESS_HI_BASE_IDX', 'regTRAP9_ADDRESS_HI_MASK', + 'regTRAP9_ADDRESS_HI_MASK_BASE_IDX', 'regTRAP9_ADDRESS_LO', + 'regTRAP9_ADDRESS_LO_BASE_IDX', 'regTRAP9_ADDRESS_LO_MASK', + 'regTRAP9_ADDRESS_LO_MASK_BASE_IDX', 'regTRAP9_COMMAND', + 'regTRAP9_COMMAND_BASE_IDX', 'regTRAP9_COMMAND_MASK', + 'regTRAP9_COMMAND_MASK_BASE_IDX', 'regTRAP9_CONTROL0', + 'regTRAP9_CONTROL0_BASE_IDX', 'regTRAP_REQUEST0', + 'regTRAP_REQUEST0_BASE_IDX', 'regTRAP_REQUEST1', + 'regTRAP_REQUEST1_BASE_IDX', 'regTRAP_REQUEST2', + 'regTRAP_REQUEST2_BASE_IDX', 'regTRAP_REQUEST3', + 'regTRAP_REQUEST3_BASE_IDX', 'regTRAP_REQUEST4', + 'regTRAP_REQUEST4_BASE_IDX', 'regTRAP_REQUEST5', + 'regTRAP_REQUEST5_BASE_IDX', 'regTRAP_REQUEST_DATA0', + 'regTRAP_REQUEST_DATA0_BASE_IDX', 'regTRAP_REQUEST_DATA1', + 'regTRAP_REQUEST_DATA10', 'regTRAP_REQUEST_DATA10_BASE_IDX', + 'regTRAP_REQUEST_DATA11', 'regTRAP_REQUEST_DATA11_BASE_IDX', + 'regTRAP_REQUEST_DATA12', 'regTRAP_REQUEST_DATA12_BASE_IDX', + 'regTRAP_REQUEST_DATA13', 'regTRAP_REQUEST_DATA13_BASE_IDX', + 'regTRAP_REQUEST_DATA14', 'regTRAP_REQUEST_DATA14_BASE_IDX', + 'regTRAP_REQUEST_DATA15', 'regTRAP_REQUEST_DATA15_BASE_IDX', + 'regTRAP_REQUEST_DATA1_BASE_IDX', 'regTRAP_REQUEST_DATA2', + 'regTRAP_REQUEST_DATA2_BASE_IDX', 'regTRAP_REQUEST_DATA3', + 'regTRAP_REQUEST_DATA3_BASE_IDX', 'regTRAP_REQUEST_DATA4', + 'regTRAP_REQUEST_DATA4_BASE_IDX', 'regTRAP_REQUEST_DATA5', + 'regTRAP_REQUEST_DATA5_BASE_IDX', 'regTRAP_REQUEST_DATA6', + 'regTRAP_REQUEST_DATA6_BASE_IDX', 'regTRAP_REQUEST_DATA7', + 'regTRAP_REQUEST_DATA7_BASE_IDX', 'regTRAP_REQUEST_DATA8', + 'regTRAP_REQUEST_DATA8_BASE_IDX', 'regTRAP_REQUEST_DATA9', + 'regTRAP_REQUEST_DATA9_BASE_IDX', 'regTRAP_REQUEST_DATASTRB0', + 'regTRAP_REQUEST_DATASTRB0_BASE_IDX', 'regTRAP_REQUEST_DATASTRB1', + 'regTRAP_REQUEST_DATASTRB1_BASE_IDX', 'regTRAP_RESPONSE0', + 'regTRAP_RESPONSE0_BASE_IDX', 'regTRAP_RESPONSE_CONTROL', + 'regTRAP_RESPONSE_CONTROL_BASE_IDX', 'regTRAP_RESPONSE_DATA0', + 'regTRAP_RESPONSE_DATA0_BASE_IDX', 'regTRAP_RESPONSE_DATA1', + 'regTRAP_RESPONSE_DATA10', 'regTRAP_RESPONSE_DATA10_BASE_IDX', + 'regTRAP_RESPONSE_DATA11', 'regTRAP_RESPONSE_DATA11_BASE_IDX', + 'regTRAP_RESPONSE_DATA12', 'regTRAP_RESPONSE_DATA12_BASE_IDX', + 'regTRAP_RESPONSE_DATA13', 'regTRAP_RESPONSE_DATA13_BASE_IDX', + 'regTRAP_RESPONSE_DATA14', 'regTRAP_RESPONSE_DATA14_BASE_IDX', + 'regTRAP_RESPONSE_DATA15', 'regTRAP_RESPONSE_DATA15_BASE_IDX', + 'regTRAP_RESPONSE_DATA1_BASE_IDX', 'regTRAP_RESPONSE_DATA2', + 'regTRAP_RESPONSE_DATA2_BASE_IDX', 'regTRAP_RESPONSE_DATA3', + 'regTRAP_RESPONSE_DATA3_BASE_IDX', 'regTRAP_RESPONSE_DATA4', + 'regTRAP_RESPONSE_DATA4_BASE_IDX', 'regTRAP_RESPONSE_DATA5', + 'regTRAP_RESPONSE_DATA5_BASE_IDX', 'regTRAP_RESPONSE_DATA6', + 'regTRAP_RESPONSE_DATA6_BASE_IDX', 'regTRAP_RESPONSE_DATA7', + 'regTRAP_RESPONSE_DATA7_BASE_IDX', 'regTRAP_RESPONSE_DATA8', + 'regTRAP_RESPONSE_DATA8_BASE_IDX', 'regTRAP_RESPONSE_DATA9', + 'regTRAP_RESPONSE_DATA9_BASE_IDX', 'regTRAP_STATUS', + 'regTRAP_STATUS_BASE_IDX', 'regXCC_DOORBELL_FENCE', + 'regXCC_DOORBELL_FENCE_BASE_IDX'] diff --git a/tinygrad/runtime/autogen/am/pm4_soc15.py b/tinygrad/runtime/autogen/am/pm4_soc15.py new file mode 100644 index 0000000000..16e9ee3d5e --- /dev/null +++ b/tinygrad/runtime/autogen/am/pm4_soc15.py @@ -0,0 +1,931 @@ +# mypy: ignore-errors +# -*- coding: utf-8 -*- +# +# TARGET arch is: [] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes + + +class AsDictMixin: + @classmethod + def as_dict(cls, self): + result = {} + if not isinstance(self, AsDictMixin): + # not a structure, assume it's already a python object + return self + if not hasattr(cls, "_fields_"): + return result + # sys.version_info >= (3, 5) + # for (field, *_) in cls._fields_: # noqa + for field_tuple in cls._fields_: # noqa + field = field_tuple[0] + if field.startswith('PADDING_'): + continue + value = getattr(self, field) + type_ = type(value) + if hasattr(value, "_length_") and hasattr(value, "_type_"): + # array + if not hasattr(type_, "as_dict"): + value = [v for v in value] + else: + type_ = type_._type_ + value = [type_.as_dict(v) for v in value] + elif hasattr(value, "contents") and hasattr(value, "_type_"): + # pointer + try: + if not hasattr(type_, "as_dict"): + value = value.contents + else: + type_ = type_._type_ + value = type_.as_dict(value.contents) + except ValueError: + # nullptr + value = None + elif isinstance(value, AsDictMixin): + # other structure + value = type_.as_dict(value) + result[field] = value + return result + + +class Structure(ctypes.Structure, AsDictMixin): + + def __init__(self, *args, **kwds): + # We don't want to use positional arguments fill PADDING_* fields + + args = dict(zip(self.__class__._field_names_(), args)) + args.update(kwds) + super(Structure, self).__init__(**args) + + @classmethod + def _field_names_(cls): + if hasattr(cls, '_fields_'): + return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) + else: + return () + + @classmethod + def get_type(cls, field): + for f in cls._fields_: + if f[0] == field: + return f[1] + return None + + @classmethod + def bind(cls, bound_fields): + fields = {} + for name, type_ in cls._fields_: + if hasattr(type_, "restype"): + if name in bound_fields: + if bound_fields[name] is None: + fields[name] = type_() + else: + # use a closure to capture the callback from the loop scope + fields[name] = ( + type_((lambda callback: lambda *args: callback(*args))( + bound_fields[name])) + ) + del bound_fields[name] + else: + # default callback implementation (does nothing) + try: + default_ = type_(0).restype().value + except TypeError: + default_ = None + fields[name] = type_(( + lambda default_: lambda *args: default_)(default_)) + else: + # not a callback function, use default initialization + if name in bound_fields: + fields[name] = bound_fields[name] + del bound_fields[name] + else: + fields[name] = type_() + if len(bound_fields) != 0: + raise ValueError( + "Cannot bind the following unknown callback(s) {}.{}".format( + cls.__name__, bound_fields.keys() + )) + return cls(**fields) + + +class Union(ctypes.Union, AsDictMixin): + pass + + + + + +F32_MES_PM4_PACKETS_H = True # macro +uint32_t = True # macro +int32_t = True # macro +PM4_MES_HEADER_DEFINED = True # macro +PM4_MEC_RELEASE_MEM_DEFINED = True # macro +PM4_MEC_WRITE_DATA_DEFINED = True # macro +class union_PM4_MES_TYPE_3_HEADER(Union): + pass + +class struct_PM4_MES_TYPE_3_HEADER_0(Structure): + pass + +struct_PM4_MES_TYPE_3_HEADER_0._pack_ = 1 # source:False +struct_PM4_MES_TYPE_3_HEADER_0._fields_ = [ + ('reserved1', ctypes.c_uint32, 8), + ('opcode', ctypes.c_uint32, 8), + ('count', ctypes.c_uint32, 14), + ('type', ctypes.c_uint32, 2), +] + +union_PM4_MES_TYPE_3_HEADER._pack_ = 1 # source:False +union_PM4_MES_TYPE_3_HEADER._anonymous_ = ('_0',) +union_PM4_MES_TYPE_3_HEADER._fields_ = [ + ('_0', struct_PM4_MES_TYPE_3_HEADER_0), + ('u32All', ctypes.c_uint32), +] + + +# values for enumeration 'c_uint32' +c_uint32__enumvalues = { + 5: 'event_index__mec_release_mem__end_of_pipe', + 6: 'event_index__mec_release_mem__shader_done', +} +event_index__mec_release_mem__end_of_pipe = 5 +event_index__mec_release_mem__shader_done = 6 +c_uint32 = ctypes.c_uint32 # enum + +# values for enumeration 'c_uint32' +c_uint32__enumvalues = { + 0: 'cache_policy__mec_release_mem__lru', + 1: 'cache_policy__mec_release_mem__stream', +} +cache_policy__mec_release_mem__lru = 0 +cache_policy__mec_release_mem__stream = 1 +c_uint32 = ctypes.c_uint32 # enum + +# values for enumeration 'c_uint32' +c_uint32__enumvalues = { + 0: 'pq_exe_status__mec_release_mem__default', + 1: 'pq_exe_status__mec_release_mem__phase_update', +} +pq_exe_status__mec_release_mem__default = 0 +pq_exe_status__mec_release_mem__phase_update = 1 +c_uint32 = ctypes.c_uint32 # enum + +# values for enumeration 'c_uint32' +c_uint32__enumvalues = { + 0: 'dst_sel__mec_release_mem__memory_controller', + 1: 'dst_sel__mec_release_mem__tc_l2', + 2: 'dst_sel__mec_release_mem__queue_write_pointer_register', + 3: 'dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit', +} +dst_sel__mec_release_mem__memory_controller = 0 +dst_sel__mec_release_mem__tc_l2 = 1 +dst_sel__mec_release_mem__queue_write_pointer_register = 2 +dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = 3 +c_uint32 = ctypes.c_uint32 # enum + +# values for enumeration 'c_uint32' +c_uint32__enumvalues = { + 0: 'int_sel__mec_release_mem__none', + 1: 'int_sel__mec_release_mem__send_interrupt_only', + 2: 'int_sel__mec_release_mem__send_interrupt_after_write_confirm', + 3: 'int_sel__mec_release_mem__send_data_after_write_confirm', + 4: 'int_sel__mec_release_mem__unconditionally_send_int_ctxid', + 5: 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare', + 6: 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare', +} +int_sel__mec_release_mem__none = 0 +int_sel__mec_release_mem__send_interrupt_only = 1 +int_sel__mec_release_mem__send_interrupt_after_write_confirm = 2 +int_sel__mec_release_mem__send_data_after_write_confirm = 3 +int_sel__mec_release_mem__unconditionally_send_int_ctxid = 4 +int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = 5 +int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = 6 +c_uint32 = ctypes.c_uint32 # enum + +# values for enumeration 'c_uint32' +c_uint32__enumvalues = { + 0: 'data_sel__mec_release_mem__none', + 1: 'data_sel__mec_release_mem__send_32_bit_low', + 2: 'data_sel__mec_release_mem__send_64_bit_data', + 3: 'data_sel__mec_release_mem__send_gpu_clock_counter', + 4: 'data_sel__mec_release_mem__send_cp_perfcounter_hi_lo', + 5: 'data_sel__mec_release_mem__store_gds_data_to_memory', +} +data_sel__mec_release_mem__none = 0 +data_sel__mec_release_mem__send_32_bit_low = 1 +data_sel__mec_release_mem__send_64_bit_data = 2 +data_sel__mec_release_mem__send_gpu_clock_counter = 3 +data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = 4 +data_sel__mec_release_mem__store_gds_data_to_memory = 5 +c_uint32 = ctypes.c_uint32 # enum +class struct_pm4_mec_release_mem(Structure): + pass + +class union_pm4_mec_release_mem_0(Union): + pass + +union_pm4_mec_release_mem_0._pack_ = 1 # source:False +union_pm4_mec_release_mem_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', ctypes.c_uint32), +] + +class union_pm4_mec_release_mem_1(Union): + pass + +class struct_pm4_mec_release_mem_1_bitfields2(Structure): + pass + +struct_pm4_mec_release_mem_1_bitfields2._pack_ = 1 # source:False +struct_pm4_mec_release_mem_1_bitfields2._fields_ = [ + ('event_type', ctypes.c_uint32, 6), + ('reserved1', ctypes.c_uint32, 2), + ('event_index', c_uint32, 4), + ('tcl1_vol_action_ena', ctypes.c_uint32, 1), + ('tc_vol_action_ena', ctypes.c_uint32, 1), + ('reserved2', ctypes.c_uint32, 1), + ('tc_wb_action_ena', ctypes.c_uint32, 1), + ('tcl1_action_ena', ctypes.c_uint32, 1), + ('tc_action_ena', ctypes.c_uint32, 1), + ('reserved3', ctypes.c_uint32, 1), + ('tc_nc_action_ena', ctypes.c_uint32, 1), + ('tc_wc_action_ena', ctypes.c_uint32, 1), + ('tc_md_action_ena', ctypes.c_uint32, 1), + ('reserved4', ctypes.c_uint32, 3), + ('cache_policy', c_uint32, 2), + ('reserved5', ctypes.c_uint32, 2), + ('pq_exe_status', c_uint32, 1), + ('reserved6', ctypes.c_uint32, 2), +] + +union_pm4_mec_release_mem_1._pack_ = 1 # source:False +union_pm4_mec_release_mem_1._fields_ = [ + ('bitfields2', struct_pm4_mec_release_mem_1_bitfields2), + ('ordinal2', ctypes.c_uint32), +] + +class union_pm4_mec_release_mem_2(Union): + pass + +class struct_pm4_mec_release_mem_2_bitfields3(Structure): + pass + +struct_pm4_mec_release_mem_2_bitfields3._pack_ = 1 # source:False +struct_pm4_mec_release_mem_2_bitfields3._fields_ = [ + ('reserved7', ctypes.c_uint32, 16), + ('dst_sel', c_uint32, 2), + ('reserved8', ctypes.c_uint32, 6), + ('int_sel', c_uint32, 3), + ('reserved9', ctypes.c_uint32, 2), + ('data_sel', c_uint32, 3), +] + +union_pm4_mec_release_mem_2._pack_ = 1 # source:False +union_pm4_mec_release_mem_2._fields_ = [ + ('bitfields3', struct_pm4_mec_release_mem_2_bitfields3), + ('ordinal3', ctypes.c_uint32), +] + +class union_pm4_mec_release_mem_3(Union): + pass + +class struct_pm4_mec_release_mem_3_bitfields4(Structure): + pass + +struct_pm4_mec_release_mem_3_bitfields4._pack_ = 1 # source:False +struct_pm4_mec_release_mem_3_bitfields4._fields_ = [ + ('reserved10', ctypes.c_uint32, 2), + ('address_lo_32b', ctypes.c_uint32, 30), +] + +class struct_pm4_mec_release_mem_3_bitfields4b(Structure): + pass + +struct_pm4_mec_release_mem_3_bitfields4b._pack_ = 1 # source:False +struct_pm4_mec_release_mem_3_bitfields4b._fields_ = [ + ('reserved11', ctypes.c_uint32, 3), + ('address_lo_64b', ctypes.c_uint32, 29), +] + +union_pm4_mec_release_mem_3._pack_ = 1 # source:False +union_pm4_mec_release_mem_3._fields_ = [ + ('bitfields4', struct_pm4_mec_release_mem_3_bitfields4), + ('bitfields4b', struct_pm4_mec_release_mem_3_bitfields4b), + ('reserved12', ctypes.c_uint32), + ('ordinal4', ctypes.c_uint32), +] + +class union_pm4_mec_release_mem_4(Union): + pass + +union_pm4_mec_release_mem_4._pack_ = 1 # source:False +union_pm4_mec_release_mem_4._fields_ = [ + ('address_hi', ctypes.c_uint32), + ('reserved13', ctypes.c_uint32), + ('ordinal5', ctypes.c_uint32), +] + +class union_pm4_mec_release_mem_5(Union): + pass + +class struct_pm4_mec_release_mem_5_bitfields6c(Structure): + pass + +struct_pm4_mec_release_mem_5_bitfields6c._pack_ = 1 # source:False +struct_pm4_mec_release_mem_5_bitfields6c._fields_ = [ + ('dw_offset', ctypes.c_uint32, 16), + ('num_dwords', ctypes.c_uint32, 16), +] + +union_pm4_mec_release_mem_5._pack_ = 1 # source:False +union_pm4_mec_release_mem_5._fields_ = [ + ('data_lo', ctypes.c_uint32), + ('cmp_data_lo', ctypes.c_uint32), + ('bitfields6c', struct_pm4_mec_release_mem_5_bitfields6c), + ('reserved14', ctypes.c_uint32), + ('ordinal6', ctypes.c_uint32), +] + +class union_pm4_mec_release_mem_6(Union): + pass + +union_pm4_mec_release_mem_6._pack_ = 1 # source:False +union_pm4_mec_release_mem_6._fields_ = [ + ('data_hi', ctypes.c_uint32), + ('cmp_data_hi', ctypes.c_uint32), + ('reserved15', ctypes.c_uint32), + ('reserved16', ctypes.c_uint32), + ('ordinal7', ctypes.c_uint32), +] + +struct_pm4_mec_release_mem._pack_ = 1 # source:False +struct_pm4_mec_release_mem._anonymous_ = ('_0', '_1', '_2', '_3', '_4', '_5', '_6',) +struct_pm4_mec_release_mem._fields_ = [ + ('_0', union_pm4_mec_release_mem_0), + ('_1', union_pm4_mec_release_mem_1), + ('_2', union_pm4_mec_release_mem_2), + ('_3', union_pm4_mec_release_mem_3), + ('_4', union_pm4_mec_release_mem_4), + ('_5', union_pm4_mec_release_mem_5), + ('_6', union_pm4_mec_release_mem_6), + ('int_ctxid', ctypes.c_uint32), +] + + +# values for enumeration 'WRITE_DATA_dst_sel_enum' +WRITE_DATA_dst_sel_enum__enumvalues = { + 0: 'dst_sel___write_data__mem_mapped_register', + 2: 'dst_sel___write_data__tc_l2', + 3: 'dst_sel___write_data__gds', + 5: 'dst_sel___write_data__memory', + 6: 'dst_sel___write_data__memory_mapped_adc_persistent_state', +} +dst_sel___write_data__mem_mapped_register = 0 +dst_sel___write_data__tc_l2 = 2 +dst_sel___write_data__gds = 3 +dst_sel___write_data__memory = 5 +dst_sel___write_data__memory_mapped_adc_persistent_state = 6 +WRITE_DATA_dst_sel_enum = ctypes.c_uint32 # enum + +# values for enumeration 'WRITE_DATA_addr_incr_enum' +WRITE_DATA_addr_incr_enum__enumvalues = { + 0: 'addr_incr___write_data__increment_address', + 1: 'addr_incr___write_data__do_not_increment_address', +} +addr_incr___write_data__increment_address = 0 +addr_incr___write_data__do_not_increment_address = 1 +WRITE_DATA_addr_incr_enum = ctypes.c_uint32 # enum + +# values for enumeration 'WRITE_DATA_wr_confirm_enum' +WRITE_DATA_wr_confirm_enum__enumvalues = { + 0: 'wr_confirm___write_data__do_not_wait_for_write_confirmation', + 1: 'wr_confirm___write_data__wait_for_write_confirmation', +} +wr_confirm___write_data__do_not_wait_for_write_confirmation = 0 +wr_confirm___write_data__wait_for_write_confirmation = 1 +WRITE_DATA_wr_confirm_enum = ctypes.c_uint32 # enum + +# values for enumeration 'WRITE_DATA_cache_policy_enum' +WRITE_DATA_cache_policy_enum__enumvalues = { + 0: 'cache_policy___write_data__lru', + 1: 'cache_policy___write_data__stream', +} +cache_policy___write_data__lru = 0 +cache_policy___write_data__stream = 1 +WRITE_DATA_cache_policy_enum = ctypes.c_uint32 # enum +class struct_pm4_mec_write_data_mmio(Structure): + pass + +class union_pm4_mec_write_data_mmio_0(Union): + pass + +union_pm4_mec_write_data_mmio_0._pack_ = 1 # source:False +union_pm4_mec_write_data_mmio_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', ctypes.c_uint32), +] + +class union_pm4_mec_write_data_mmio_1(Union): + pass + +class struct_pm4_mec_write_data_mmio_1_bitfields2(Structure): + pass + +struct_pm4_mec_write_data_mmio_1_bitfields2._pack_ = 1 # source:False +struct_pm4_mec_write_data_mmio_1_bitfields2._fields_ = [ + ('reserved1', ctypes.c_uint32, 8), + ('dst_sel', ctypes.c_uint32, 4), + ('reserved2', ctypes.c_uint32, 4), + ('addr_incr', ctypes.c_uint32, 1), + ('reserved3', ctypes.c_uint32, 2), + ('resume_vf', ctypes.c_uint32, 1), + ('wr_confirm', ctypes.c_uint32, 1), + ('reserved4', ctypes.c_uint32, 4), + ('cache_policy', ctypes.c_uint32, 2), + ('reserved5', ctypes.c_uint32, 5), +] + +union_pm4_mec_write_data_mmio_1._pack_ = 1 # source:False +union_pm4_mec_write_data_mmio_1._fields_ = [ + ('bitfields2', struct_pm4_mec_write_data_mmio_1_bitfields2), + ('ordinal2', ctypes.c_uint32), +] + +class union_pm4_mec_write_data_mmio_2(Union): + pass + +class struct_pm4_mec_write_data_mmio_2_bitfields3(Structure): + pass + +struct_pm4_mec_write_data_mmio_2_bitfields3._pack_ = 1 # source:False +struct_pm4_mec_write_data_mmio_2_bitfields3._fields_ = [ + ('dst_mmreg_addr', ctypes.c_uint32, 18), + ('reserved6', ctypes.c_uint32, 14), +] + +union_pm4_mec_write_data_mmio_2._pack_ = 1 # source:False +union_pm4_mec_write_data_mmio_2._fields_ = [ + ('bitfields3', struct_pm4_mec_write_data_mmio_2_bitfields3), + ('ordinal3', ctypes.c_uint32), +] + +struct_pm4_mec_write_data_mmio._pack_ = 1 # source:False +struct_pm4_mec_write_data_mmio._anonymous_ = ('_0', '_1', '_2',) +struct_pm4_mec_write_data_mmio._fields_ = [ + ('_0', union_pm4_mec_write_data_mmio_0), + ('_1', union_pm4_mec_write_data_mmio_1), + ('_2', union_pm4_mec_write_data_mmio_2), + ('reserved7', ctypes.c_uint32), + ('data', ctypes.c_uint32), +] + + +# values for enumeration 'c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT' +c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT__enumvalues = { + 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', +} +CACHE_FLUSH_AND_INV_TS_EVENT = 20 +c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT = ctypes.c_uint32 # enum +SOC15_H = True # macro +GFX9_NUM_GFX_RINGS = 1 # macro +GFX9_NUM_COMPUTE_RINGS = 8 # macro +PACKET_TYPE0 = 0 # macro +PACKET_TYPE1 = 1 # macro +PACKET_TYPE2 = 2 # macro +PACKET_TYPE3 = 3 # macro +def CP_PACKET_GET_TYPE(h): # macro + return (((h)>>30)&3) +def CP_PACKET_GET_COUNT(h): # macro + return (((h)>>16)&0x3FFF) +def CP_PACKET0_GET_REG(h): # macro + return ((h)&0xFFFF) +def CP_PACKET3_GET_OPCODE(h): # macro + return (((h)>>8)&0xFF) +def PACKET0(reg, n): # macro + return ((0<<30)|((reg)&0xFFFF)|((n)&0x3FFF)<<16) +CP_PACKET2 = 0x80000000 # macro +PACKET2_PAD_SHIFT = 0 # macro +PACKET2_PAD_MASK = (0x3fffffff<<0) # macro +# def PACKET2(v): # macro +# return (0x80000000|REG_SET(PACKET2_PAD,(v))) +def PACKET3(op, n): # macro + return ((3<<30)|(((op)&0xFF)<<8)|((n)&0x3FFF)<<16) +def PACKET3_COMPUTE(op, n): # macro + return (PACKET3(op,n)|1<<1) +PACKETJ_CONDITION_CHECK0 = 0 # macro +PACKETJ_CONDITION_CHECK1 = 1 # macro +PACKETJ_CONDITION_CHECK2 = 2 # macro +PACKETJ_CONDITION_CHECK3 = 3 # macro +PACKETJ_CONDITION_CHECK4 = 4 # macro +PACKETJ_CONDITION_CHECK5 = 5 # macro +PACKETJ_CONDITION_CHECK6 = 6 # macro +PACKETJ_CONDITION_CHECK7 = 7 # macro +PACKETJ_TYPE0 = 0 # macro +PACKETJ_TYPE1 = 1 # macro +PACKETJ_TYPE2 = 2 # macro +PACKETJ_TYPE3 = 3 # macro +PACKETJ_TYPE4 = 4 # macro +PACKETJ_TYPE5 = 5 # macro +PACKETJ_TYPE6 = 6 # macro +PACKETJ_TYPE7 = 7 # macro +def PACKETJ(reg, r, cond, type): # macro + return ((reg&0x3FFFF)|((r&0x3F)<<18)|((cond&0xF)<<24)|((type&0xF)<<28)) +CP_PACKETJ_NOP = 0x60000000 # macro +def CP_PACKETJ_GET_REG(x): # macro + return ((x)&0x3FFFF) +def CP_PACKETJ_GET_RES(x): # macro + return (((x)>>18)&0x3F) +def CP_PACKETJ_GET_COND(x): # macro + return (((x)>>24)&0xF) +def CP_PACKETJ_GET_TYPE(x): # macro + return (((x)>>28)&0xF) +PACKET3_NOP = 0x10 # macro +PACKET3_SET_BASE = 0x11 # macro +def PACKET3_BASE_INDEX(x): # macro + return ((x)<<0) +CE_PARTITION_BASE = 3 # macro +PACKET3_CLEAR_STATE = 0x12 # macro +PACKET3_INDEX_BUFFER_SIZE = 0x13 # macro +PACKET3_DISPATCH_DIRECT = 0x15 # macro +PACKET3_DISPATCH_INDIRECT = 0x16 # macro +PACKET3_ATOMIC_GDS = 0x1D # macro +PACKET3_ATOMIC_MEM = 0x1E # macro +PACKET3_OCCLUSION_QUERY = 0x1F # macro +PACKET3_SET_PREDICATION = 0x20 # macro +PACKET3_REG_RMW = 0x21 # macro +PACKET3_COND_EXEC = 0x22 # macro +PACKET3_PRED_EXEC = 0x23 # macro +PACKET3_DRAW_INDIRECT = 0x24 # macro +PACKET3_DRAW_INDEX_INDIRECT = 0x25 # macro +PACKET3_INDEX_BASE = 0x26 # macro +PACKET3_DRAW_INDEX_2 = 0x27 # macro +PACKET3_CONTEXT_CONTROL = 0x28 # macro +PACKET3_INDEX_TYPE = 0x2A # macro +PACKET3_DRAW_INDIRECT_MULTI = 0x2C # macro +PACKET3_DRAW_INDEX_AUTO = 0x2D # macro +PACKET3_NUM_INSTANCES = 0x2F # macro +PACKET3_DRAW_INDEX_MULTI_AUTO = 0x30 # macro +PACKET3_INDIRECT_BUFFER_CONST = 0x33 # macro +PACKET3_STRMOUT_BUFFER_UPDATE = 0x34 # macro +PACKET3_DRAW_INDEX_OFFSET_2 = 0x35 # macro +PACKET3_DRAW_PREAMBLE = 0x36 # macro +PACKET3_WRITE_DATA = 0x37 # macro +def WRITE_DATA_DST_SEL(x): # macro + return ((x)<<8) +WR_ONE_ADDR = (1<<16) # macro +WR_CONFIRM = (1<<20) # macro +def WRITE_DATA_CACHE_POLICY(x): # macro + return ((x)<<25) +def WRITE_DATA_ENGINE_SEL(x): # macro + return ((x)<<30) +PACKET3_DRAW_INDEX_INDIRECT_MULTI = 0x38 # macro +PACKET3_MEM_SEMAPHORE = 0x39 # macro +PACKET3_SEM_USE_MAILBOX = (0x1<<16) # macro +PACKET3_SEM_SEL_SIGNAL_TYPE = (0x1<<20) # macro +PACKET3_SEM_SEL_SIGNAL = (0x6<<29) # macro +PACKET3_SEM_SEL_WAIT = (0x7<<29) # macro +PACKET3_WAIT_REG_MEM = 0x3C # macro +def WAIT_REG_MEM_FUNCTION(x): # macro + return ((x)<<0) +def WAIT_REG_MEM_MEM_SPACE(x): # macro + return ((x)<<4) +def WAIT_REG_MEM_OPERATION(x): # macro + return ((x)<<6) +def WAIT_REG_MEM_ENGINE(x): # macro + return ((x)<<8) +PACKET3_INDIRECT_BUFFER = 0x3F # macro +INDIRECT_BUFFER_VALID = (1<<23) # macro +def INDIRECT_BUFFER_CACHE_POLICY(x): # macro + return ((x)<<28) +def INDIRECT_BUFFER_PRE_ENB(x): # macro + return ((x)<<21) +def INDIRECT_BUFFER_PRE_RESUME(x): # macro + return ((x)<<30) +PACKET3_COPY_DATA = 0x40 # macro +PACKET3_PFP_SYNC_ME = 0x42 # macro +PACKET3_COND_WRITE = 0x45 # macro +PACKET3_EVENT_WRITE = 0x46 # macro +def EVENT_TYPE(x): # macro + return ((x)<<0) +def EVENT_INDEX(x): # macro + return ((x)<<8) +PACKET3_RELEASE_MEM = 0x49 # macro +EOP_TCL1_VOL_ACTION_EN = (1<<12) # macro +EOP_TC_VOL_ACTION_EN = (1<<13) # macro +EOP_TC_WB_ACTION_EN = (1<<15) # macro +EOP_TCL1_ACTION_EN = (1<<16) # macro +EOP_TC_ACTION_EN = (1<<17) # macro +EOP_TC_NC_ACTION_EN = (1<<19) # macro +EOP_TC_MD_ACTION_EN = (1<<21) # macro +EOP_EXEC = (1<<28) # macro +def DATA_SEL(x): # macro + return ((x)<<29) +def INT_SEL(x): # macro + return ((x)<<24) +def DST_SEL(x): # macro + return ((x)<<16) +PACKET3_PREAMBLE_CNTL = 0x4A # macro +PACKET3_PREAMBLE_BEGIN_CLEAR_STATE = (2<<28) # macro +PACKET3_PREAMBLE_END_CLEAR_STATE = (3<<28) # macro +PACKET3_DMA_DATA = 0x50 # macro +def PACKET3_DMA_DATA_ENGINE(x): # macro + return ((x)<<0) +def PACKET3_DMA_DATA_SRC_CACHE_POLICY(x): # macro + return ((x)<<13) +def PACKET3_DMA_DATA_DST_SEL(x): # macro + return ((x)<<20) +def PACKET3_DMA_DATA_DST_CACHE_POLICY(x): # macro + return ((x)<<25) +def PACKET3_DMA_DATA_SRC_SEL(x): # macro + return ((x)<<29) +PACKET3_DMA_DATA_CP_SYNC = (1<<31) # macro +PACKET3_DMA_DATA_CMD_SAS = (1<<26) # macro +PACKET3_DMA_DATA_CMD_DAS = (1<<27) # macro +PACKET3_DMA_DATA_CMD_SAIC = (1<<28) # macro +PACKET3_DMA_DATA_CMD_DAIC = (1<<29) # macro +PACKET3_DMA_DATA_CMD_RAW_WAIT = (1<<30) # macro +PACKET3_ACQUIRE_MEM = 0x58 # macro +def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA(x): # macro + return ((x)<<3) +def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WC_ACTION_ENA(x): # macro + return ((x)<<4) +def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_INV_METADATA_ACTION_ENA(x): # macro + return ((x)<<5) +def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_VOL_ACTION_ENA(x): # macro + return ((x)<<15) +def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(x): # macro + return ((x)<<18) +def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(x): # macro + return ((x)<<22) +def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(x): # macro + return ((x)<<23) +def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_CB_ACTION_ENA(x): # macro + return ((x)<<25) +def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_DB_ACTION_ENA(x): # macro + return ((x)<<26) +def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(x): # macro + return ((x)<<27) +def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_VOL_ACTION_ENA(x): # macro + return ((x)<<28) +def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(x): # macro + return ((x)<<29) +def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_WB_ACTION_ENA(x): # macro + return ((x)<<30) +PACKET3_REWIND = 0x59 # macro +PACKET3_LOAD_UCONFIG_REG = 0x5E # macro +PACKET3_LOAD_SH_REG = 0x5F # macro +PACKET3_LOAD_CONFIG_REG = 0x60 # macro +PACKET3_LOAD_CONTEXT_REG = 0x61 # macro +PACKET3_SET_CONFIG_REG = 0x68 # macro +PACKET3_SET_CONFIG_REG_START = 0x00002000 # macro +PACKET3_SET_CONFIG_REG_END = 0x00002c00 # macro +PACKET3_SET_CONTEXT_REG = 0x69 # macro +PACKET3_SET_CONTEXT_REG_START = 0x0000a000 # macro +PACKET3_SET_CONTEXT_REG_END = 0x0000a400 # macro +PACKET3_SET_CONTEXT_REG_INDIRECT = 0x73 # macro +PACKET3_SET_SH_REG = 0x76 # macro +PACKET3_SET_SH_REG_START = 0x00002c00 # macro +PACKET3_SET_SH_REG_END = 0x00003000 # macro +PACKET3_SET_SH_REG_OFFSET = 0x77 # macro +PACKET3_SET_QUEUE_REG = 0x78 # macro +PACKET3_SET_UCONFIG_REG = 0x79 # macro +PACKET3_SET_UCONFIG_REG_START = 0x0000c000 # macro +PACKET3_SET_UCONFIG_REG_END = 0x0000c400 # macro +PACKET3_SET_UCONFIG_REG_INDEX_TYPE = (2<<28) # macro +PACKET3_SCRATCH_RAM_WRITE = 0x7D # macro +PACKET3_SCRATCH_RAM_READ = 0x7E # macro +PACKET3_LOAD_CONST_RAM = 0x80 # macro +PACKET3_WRITE_CONST_RAM = 0x81 # macro +PACKET3_DUMP_CONST_RAM = 0x83 # macro +PACKET3_INCREMENT_CE_COUNTER = 0x84 # macro +PACKET3_INCREMENT_DE_COUNTER = 0x85 # macro +PACKET3_WAIT_ON_CE_COUNTER = 0x86 # macro +PACKET3_WAIT_ON_DE_COUNTER_DIFF = 0x88 # macro +PACKET3_SWITCH_BUFFER = 0x8B # macro +PACKET3_FRAME_CONTROL = 0x90 # macro +FRAME_TMZ = (1<<0) # macro +def FRAME_CMD(x): # macro + return ((x)<<28) +PACKET3_INVALIDATE_TLBS = 0x98 # macro +def PACKET3_INVALIDATE_TLBS_DST_SEL(x): # macro + return ((x)<<0) +def PACKET3_INVALIDATE_TLBS_ALL_HUB(x): # macro + return ((x)<<4) +def PACKET3_INVALIDATE_TLBS_PASID(x): # macro + return ((x)<<5) +def PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x): # macro + return ((x)<<29) +PACKET3_SET_RESOURCES = 0xA0 # macro +def PACKET3_SET_RESOURCES_VMID_MASK(x): # macro + return ((x)<<0) +def PACKET3_SET_RESOURCES_UNMAP_LATENTY(x): # macro + return ((x)<<16) +def PACKET3_SET_RESOURCES_QUEUE_TYPE(x): # macro + return ((x)<<29) +PACKET3_MAP_QUEUES = 0xA2 # macro +def PACKET3_MAP_QUEUES_QUEUE_SEL(x): # macro + return ((x)<<4) +def PACKET3_MAP_QUEUES_VMID(x): # macro + return ((x)<<8) +def PACKET3_MAP_QUEUES_QUEUE(x): # macro + return ((x)<<13) +def PACKET3_MAP_QUEUES_PIPE(x): # macro + return ((x)<<16) +def PACKET3_MAP_QUEUES_ME(x): # macro + return ((x)<<18) +def PACKET3_MAP_QUEUES_QUEUE_TYPE(x): # macro + return ((x)<<21) +def PACKET3_MAP_QUEUES_ALLOC_FORMAT(x): # macro + return ((x)<<24) +def PACKET3_MAP_QUEUES_ENGINE_SEL(x): # macro + return ((x)<<26) +def PACKET3_MAP_QUEUES_NUM_QUEUES(x): # macro + return ((x)<<29) +def PACKET3_MAP_QUEUES_CHECK_DISABLE(x): # macro + return ((x)<<1) +def PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x): # macro + return ((x)<<2) +PACKET3_UNMAP_QUEUES = 0xA3 # macro +def PACKET3_UNMAP_QUEUES_ACTION(x): # macro + return ((x)<<0) +def PACKET3_UNMAP_QUEUES_QUEUE_SEL(x): # macro + return ((x)<<4) +def PACKET3_UNMAP_QUEUES_ENGINE_SEL(x): # macro + return ((x)<<26) +def PACKET3_UNMAP_QUEUES_NUM_QUEUES(x): # macro + return ((x)<<29) +def PACKET3_UNMAP_QUEUES_PASID(x): # macro + return ((x)<<0) +def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x): # macro + return ((x)<<2) +def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x): # macro + return ((x)<<2) +def PACKET3_UNMAP_QUEUES_RB_WPTR(x): # macro + return ((x)<<0) +def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x): # macro + return ((x)<<2) +def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x): # macro + return ((x)<<2) +PACKET3_QUERY_STATUS = 0xA4 # macro +def PACKET3_QUERY_STATUS_CONTEXT_ID(x): # macro + return ((x)<<0) +def PACKET3_QUERY_STATUS_INTERRUPT_SEL(x): # macro + return ((x)<<28) +def PACKET3_QUERY_STATUS_COMMAND(x): # macro + return ((x)<<30) +def PACKET3_QUERY_STATUS_PASID(x): # macro + return ((x)<<0) +def PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x): # macro + return ((x)<<2) +def PACKET3_QUERY_STATUS_ENG_SEL(x): # macro + return ((x)<<25) +PACKET3_RUN_CLEANER_SHADER = 0xD2 # macro +VCE_CMD_NO_OP = 0x00000000 # macro +VCE_CMD_END = 0x00000001 # macro +VCE_CMD_IB = 0x00000002 # macro +VCE_CMD_FENCE = 0x00000003 # macro +VCE_CMD_TRAP = 0x00000004 # macro +VCE_CMD_IB_AUTO = 0x00000005 # macro +VCE_CMD_SEMAPHORE = 0x00000006 # macro +VCE_CMD_IB_VM = 0x00000102 # macro +VCE_CMD_WAIT_GE = 0x00000106 # macro +VCE_CMD_UPDATE_PTB = 0x00000107 # macro +VCE_CMD_FLUSH_TLB = 0x00000108 # macro +VCE_CMD_REG_WRITE = 0x00000109 # macro +VCE_CMD_REG_WAIT = 0x0000010a # macro +HEVC_ENC_CMD_NO_OP = 0x00000000 # macro +HEVC_ENC_CMD_END = 0x00000001 # macro +HEVC_ENC_CMD_FENCE = 0x00000003 # macro +HEVC_ENC_CMD_TRAP = 0x00000004 # macro +HEVC_ENC_CMD_IB_VM = 0x00000102 # macro +HEVC_ENC_CMD_REG_WRITE = 0x00000109 # macro +HEVC_ENC_CMD_REG_WAIT = 0x0000010a # macro +__all__ = \ + ['CACHE_FLUSH_AND_INV_TS_EVENT', 'CE_PARTITION_BASE', + 'CP_PACKET2', 'CP_PACKETJ_NOP', 'EOP_EXEC', 'EOP_TCL1_ACTION_EN', + 'EOP_TCL1_VOL_ACTION_EN', 'EOP_TC_ACTION_EN', + 'EOP_TC_MD_ACTION_EN', 'EOP_TC_NC_ACTION_EN', + 'EOP_TC_VOL_ACTION_EN', 'EOP_TC_WB_ACTION_EN', + 'F32_MES_PM4_PACKETS_H', 'FRAME_TMZ', 'GFX9_NUM_COMPUTE_RINGS', + 'GFX9_NUM_GFX_RINGS', 'HEVC_ENC_CMD_END', 'HEVC_ENC_CMD_FENCE', + 'HEVC_ENC_CMD_IB_VM', 'HEVC_ENC_CMD_NO_OP', + 'HEVC_ENC_CMD_REG_WAIT', 'HEVC_ENC_CMD_REG_WRITE', + 'HEVC_ENC_CMD_TRAP', 'INDIRECT_BUFFER_VALID', 'PACKET2_PAD_MASK', + 'PACKET2_PAD_SHIFT', 'PACKET3_ACQUIRE_MEM', 'PACKET3_ATOMIC_GDS', + 'PACKET3_ATOMIC_MEM', 'PACKET3_CLEAR_STATE', 'PACKET3_COND_EXEC', + 'PACKET3_COND_WRITE', 'PACKET3_CONTEXT_CONTROL', + 'PACKET3_COPY_DATA', 'PACKET3_DISPATCH_DIRECT', + 'PACKET3_DISPATCH_INDIRECT', 'PACKET3_DMA_DATA', + 'PACKET3_DMA_DATA_CMD_DAIC', 'PACKET3_DMA_DATA_CMD_DAS', + 'PACKET3_DMA_DATA_CMD_RAW_WAIT', 'PACKET3_DMA_DATA_CMD_SAIC', + 'PACKET3_DMA_DATA_CMD_SAS', 'PACKET3_DMA_DATA_CP_SYNC', + 'PACKET3_DRAW_INDEX_2', 'PACKET3_DRAW_INDEX_AUTO', + 'PACKET3_DRAW_INDEX_INDIRECT', + 'PACKET3_DRAW_INDEX_INDIRECT_MULTI', + 'PACKET3_DRAW_INDEX_MULTI_AUTO', 'PACKET3_DRAW_INDEX_OFFSET_2', + 'PACKET3_DRAW_INDIRECT', 'PACKET3_DRAW_INDIRECT_MULTI', + 'PACKET3_DRAW_PREAMBLE', 'PACKET3_DUMP_CONST_RAM', + 'PACKET3_EVENT_WRITE', 'PACKET3_FRAME_CONTROL', + 'PACKET3_INCREMENT_CE_COUNTER', 'PACKET3_INCREMENT_DE_COUNTER', + 'PACKET3_INDEX_BASE', 'PACKET3_INDEX_BUFFER_SIZE', + 'PACKET3_INDEX_TYPE', 'PACKET3_INDIRECT_BUFFER', + 'PACKET3_INDIRECT_BUFFER_CONST', 'PACKET3_INVALIDATE_TLBS', + 'PACKET3_LOAD_CONFIG_REG', 'PACKET3_LOAD_CONST_RAM', + 'PACKET3_LOAD_CONTEXT_REG', 'PACKET3_LOAD_SH_REG', + 'PACKET3_LOAD_UCONFIG_REG', 'PACKET3_MAP_QUEUES', + 'PACKET3_MEM_SEMAPHORE', 'PACKET3_NOP', 'PACKET3_NUM_INSTANCES', + 'PACKET3_OCCLUSION_QUERY', 'PACKET3_PFP_SYNC_ME', + 'PACKET3_PREAMBLE_BEGIN_CLEAR_STATE', 'PACKET3_PREAMBLE_CNTL', + 'PACKET3_PREAMBLE_END_CLEAR_STATE', 'PACKET3_PRED_EXEC', + 'PACKET3_QUERY_STATUS', 'PACKET3_REG_RMW', 'PACKET3_RELEASE_MEM', + 'PACKET3_REWIND', 'PACKET3_RUN_CLEANER_SHADER', + 'PACKET3_SCRATCH_RAM_READ', 'PACKET3_SCRATCH_RAM_WRITE', + 'PACKET3_SEM_SEL_SIGNAL', 'PACKET3_SEM_SEL_SIGNAL_TYPE', + 'PACKET3_SEM_SEL_WAIT', 'PACKET3_SEM_USE_MAILBOX', + 'PACKET3_SET_BASE', 'PACKET3_SET_CONFIG_REG', + 'PACKET3_SET_CONFIG_REG_END', 'PACKET3_SET_CONFIG_REG_START', + 'PACKET3_SET_CONTEXT_REG', 'PACKET3_SET_CONTEXT_REG_END', + 'PACKET3_SET_CONTEXT_REG_INDIRECT', + 'PACKET3_SET_CONTEXT_REG_START', 'PACKET3_SET_PREDICATION', + 'PACKET3_SET_QUEUE_REG', 'PACKET3_SET_RESOURCES', + 'PACKET3_SET_SH_REG', 'PACKET3_SET_SH_REG_END', + 'PACKET3_SET_SH_REG_OFFSET', 'PACKET3_SET_SH_REG_START', + 'PACKET3_SET_UCONFIG_REG', 'PACKET3_SET_UCONFIG_REG_END', + 'PACKET3_SET_UCONFIG_REG_INDEX_TYPE', + 'PACKET3_SET_UCONFIG_REG_START', 'PACKET3_STRMOUT_BUFFER_UPDATE', + 'PACKET3_SWITCH_BUFFER', 'PACKET3_UNMAP_QUEUES', + 'PACKET3_WAIT_ON_CE_COUNTER', 'PACKET3_WAIT_ON_DE_COUNTER_DIFF', + 'PACKET3_WAIT_REG_MEM', 'PACKET3_WRITE_CONST_RAM', + 'PACKET3_WRITE_DATA', 'PACKETJ_CONDITION_CHECK0', + 'PACKETJ_CONDITION_CHECK1', 'PACKETJ_CONDITION_CHECK2', + 'PACKETJ_CONDITION_CHECK3', 'PACKETJ_CONDITION_CHECK4', + 'PACKETJ_CONDITION_CHECK5', 'PACKETJ_CONDITION_CHECK6', + 'PACKETJ_CONDITION_CHECK7', 'PACKETJ_TYPE0', 'PACKETJ_TYPE1', + 'PACKETJ_TYPE2', 'PACKETJ_TYPE3', 'PACKETJ_TYPE4', + 'PACKETJ_TYPE5', 'PACKETJ_TYPE6', 'PACKETJ_TYPE7', 'PACKET_TYPE0', + 'PACKET_TYPE1', 'PACKET_TYPE2', 'PACKET_TYPE3', + 'PM4_MEC_RELEASE_MEM_DEFINED', 'PM4_MEC_WRITE_DATA_DEFINED', + 'PM4_MES_HEADER_DEFINED', 'SOC15_H', 'VCE_CMD_END', + 'VCE_CMD_FENCE', 'VCE_CMD_FLUSH_TLB', 'VCE_CMD_IB', + 'VCE_CMD_IB_AUTO', 'VCE_CMD_IB_VM', 'VCE_CMD_NO_OP', + 'VCE_CMD_REG_WAIT', 'VCE_CMD_REG_WRITE', 'VCE_CMD_SEMAPHORE', + 'VCE_CMD_TRAP', 'VCE_CMD_UPDATE_PTB', 'VCE_CMD_WAIT_GE', + 'WRITE_DATA_addr_incr_enum', 'WRITE_DATA_cache_policy_enum', + 'WRITE_DATA_dst_sel_enum', 'WRITE_DATA_wr_confirm_enum', + 'WR_CONFIRM', 'WR_ONE_ADDR', + 'addr_incr___write_data__do_not_increment_address', + 'addr_incr___write_data__increment_address', + 'c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT', 'c_uint32', 'c_uint32', + 'c_uint32', 'c_uint32', 'c_uint32', 'c_uint32', + 'cache_policy___write_data__lru', + 'cache_policy___write_data__stream', + 'cache_policy__mec_release_mem__lru', + 'cache_policy__mec_release_mem__stream', + 'data_sel__mec_release_mem__none', + 'data_sel__mec_release_mem__send_32_bit_low', + 'data_sel__mec_release_mem__send_64_bit_data', + 'data_sel__mec_release_mem__send_cp_perfcounter_hi_lo', + 'data_sel__mec_release_mem__send_gpu_clock_counter', + 'data_sel__mec_release_mem__store_gds_data_to_memory', + 'dst_sel___write_data__gds', + 'dst_sel___write_data__mem_mapped_register', + 'dst_sel___write_data__memory', + 'dst_sel___write_data__memory_mapped_adc_persistent_state', + 'dst_sel___write_data__tc_l2', + 'dst_sel__mec_release_mem__memory_controller', + 'dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit', + 'dst_sel__mec_release_mem__queue_write_pointer_register', + 'dst_sel__mec_release_mem__tc_l2', + 'event_index__mec_release_mem__end_of_pipe', + 'event_index__mec_release_mem__shader_done', 'int32_t', + 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare', + 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare', + 'int_sel__mec_release_mem__none', + 'int_sel__mec_release_mem__send_data_after_write_confirm', + 'int_sel__mec_release_mem__send_interrupt_after_write_confirm', + 'int_sel__mec_release_mem__send_interrupt_only', + 'int_sel__mec_release_mem__unconditionally_send_int_ctxid', + 'pq_exe_status__mec_release_mem__default', + 'pq_exe_status__mec_release_mem__phase_update', + 'struct_PM4_MES_TYPE_3_HEADER_0', 'struct_pm4_mec_release_mem', + 'struct_pm4_mec_release_mem_1_bitfields2', + 'struct_pm4_mec_release_mem_2_bitfields3', + 'struct_pm4_mec_release_mem_3_bitfields4', + 'struct_pm4_mec_release_mem_3_bitfields4b', + 'struct_pm4_mec_release_mem_5_bitfields6c', + 'struct_pm4_mec_write_data_mmio', + 'struct_pm4_mec_write_data_mmio_1_bitfields2', + 'struct_pm4_mec_write_data_mmio_2_bitfields3', 'uint32_t', + 'union_PM4_MES_TYPE_3_HEADER', 'union_pm4_mec_release_mem_0', + 'union_pm4_mec_release_mem_1', 'union_pm4_mec_release_mem_2', + 'union_pm4_mec_release_mem_3', 'union_pm4_mec_release_mem_4', + 'union_pm4_mec_release_mem_5', 'union_pm4_mec_release_mem_6', + 'union_pm4_mec_write_data_mmio_0', + 'union_pm4_mec_write_data_mmio_1', + 'union_pm4_mec_write_data_mmio_2', + 'wr_confirm___write_data__do_not_wait_for_write_confirmation', + 'wr_confirm___write_data__wait_for_write_confirmation'] diff --git a/tinygrad/runtime/autogen/am/sdma_4_0_0.py b/tinygrad/runtime/autogen/am/sdma_4_0_0.py new file mode 100644 index 0000000000..a48adeed78 --- /dev/null +++ b/tinygrad/runtime/autogen/am/sdma_4_0_0.py @@ -0,0 +1,5209 @@ +# mypy: ignore-errors +# -*- coding: utf-8 -*- +# +# TARGET arch is: ['-I/opt/rocm/include', '-x', 'c++'] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes + + +class AsDictMixin: + @classmethod + def as_dict(cls, self): + result = {} + if not isinstance(self, AsDictMixin): + # not a structure, assume it's already a python object + return self + if not hasattr(cls, "_fields_"): + return result + # sys.version_info >= (3, 5) + # for (field, *_) in cls._fields_: # noqa + for field_tuple in cls._fields_: # noqa + field = field_tuple[0] + if field.startswith('PADDING_'): + continue + value = getattr(self, field) + type_ = type(value) + if hasattr(value, "_length_") and hasattr(value, "_type_"): + # array + if not hasattr(type_, "as_dict"): + value = [v for v in value] + else: + type_ = type_._type_ + value = [type_.as_dict(v) for v in value] + elif hasattr(value, "contents") and hasattr(value, "_type_"): + # pointer + try: + if not hasattr(type_, "as_dict"): + value = value.contents + else: + type_ = type_._type_ + value = type_.as_dict(value.contents) + except ValueError: + # nullptr + value = None + elif isinstance(value, AsDictMixin): + # other structure + value = type_.as_dict(value) + result[field] = value + return result + + +class Structure(ctypes.Structure, AsDictMixin): + + def __init__(self, *args, **kwds): + # We don't want to use positional arguments fill PADDING_* fields + + args = dict(zip(self.__class__._field_names_(), args)) + args.update(kwds) + super(Structure, self).__init__(**args) + + @classmethod + def _field_names_(cls): + if hasattr(cls, '_fields_'): + return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) + else: + return () + + @classmethod + def get_type(cls, field): + for f in cls._fields_: + if f[0] == field: + return f[1] + return None + + @classmethod + def bind(cls, bound_fields): + fields = {} + for name, type_ in cls._fields_: + if hasattr(type_, "restype"): + if name in bound_fields: + if bound_fields[name] is None: + fields[name] = type_() + else: + # use a closure to capture the callback from the loop scope + fields[name] = ( + type_((lambda callback: lambda *args: callback(*args))( + bound_fields[name])) + ) + del bound_fields[name] + else: + # default callback implementation (does nothing) + try: + default_ = type_(0).restype().value + except TypeError: + default_ = None + fields[name] = type_(( + lambda default_: lambda *args: default_)(default_)) + else: + # not a callback function, use default initialization + if name in bound_fields: + fields[name] = bound_fields[name] + del bound_fields[name] + else: + fields[name] = type_() + if len(bound_fields) != 0: + raise ValueError( + "Cannot bind the following unknown callback(s) {}.{}".format( + cls.__name__, bound_fields.keys() + )) + return cls(**fields) + + +class Union(ctypes.Union, AsDictMixin): + pass + + + + + +HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_ = True # macro +SDMA_OP_COPY = 1 # macro +SDMA_OP_FENCE = 5 # macro +SDMA_OP_TRAP = 6 # macro +SDMA_OP_POLL_REGMEM = 8 # macro +SDMA_OP_ATOMIC = 10 # macro +SDMA_OP_CONST_FILL = 11 # macro +SDMA_OP_TIMESTAMP = 13 # macro +SDMA_OP_GCR = 17 # Variable ctypes.c_uint32 +SDMA_SUBOP_COPY_LINEAR = 0 # macro +SDMA_SUBOP_COPY_LINEAR_RECT = 4 # Variable ctypes.c_uint32 +SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 # macro +SDMA_SUBOP_USER_GCR = 1 # Variable ctypes.c_uint32 +SDMA_ATOMIC_ADD64 = 47 # Variable ctypes.c_uint32 +class struct_SDMA_PKT_COPY_LINEAR_TAG(Structure): + pass + +class union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_TAG_0_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._fields_ = [ + ('op', ctypes.c_uint32, 8), + ('sub_op', ctypes.c_uint32, 8), + ('extra_info', ctypes.c_uint32, 16), +] + +union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_0_0), + ('DW_0_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_TAG_1_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._fields_ = [ + ('count', ctypes.c_uint32, 22), + ('reserved_0', ctypes.c_uint32, 10), +] + +union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_1_0), + ('DW_1_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_TAG_2_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._fields_ = [ + ('reserved_0', ctypes.c_uint32, 16), + ('dst_swap', ctypes.c_uint32, 2), + ('reserved_1', ctypes.c_uint32, 6), + ('src_swap', ctypes.c_uint32, 2), + ('reserved_2', ctypes.c_uint32, 6), +] + +union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_2_0), + ('DW_2_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_TAG_3_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._fields_ = [ + ('src_addr_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_3_0), + ('DW_3_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_TAG_4_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._fields_ = [ + ('src_addr_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_4_0), + ('DW_4_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_TAG_5_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._fields_ = [ + ('dst_addr_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_5_0), + ('DW_5_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_TAG_6_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._fields_ = [ + ('dst_addr_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_6_0), + ('DW_6_DATA', ctypes.c_uint32), +] + +struct_SDMA_PKT_COPY_LINEAR_TAG._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_TAG._fields_ = [ + ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION), + ('COUNT_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION), + ('PARAMETER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION), + ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION), + ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION), + ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION), + ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION), +] + +SDMA_PKT_COPY_LINEAR = struct_SDMA_PKT_COPY_LINEAR_TAG +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG(Structure): + pass + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._fields_ = [ + ('op', ctypes.c_uint32, 8), + ('sub_op', ctypes.c_uint32, 8), + ('reserved', ctypes.c_uint32, 13), + ('element', ctypes.c_uint32, 3), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0), + ('DW_0_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._fields_ = [ + ('src_addr_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0), + ('DW_1_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._fields_ = [ + ('src_addr_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0), + ('DW_2_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._fields_ = [ + ('src_offset_x', ctypes.c_uint32, 14), + ('reserved_1', ctypes.c_uint32, 2), + ('src_offset_y', ctypes.c_uint32, 14), + ('reserved_2', ctypes.c_uint32, 2), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0), + ('DW_3_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._fields_ = [ + ('src_offset_z', ctypes.c_uint32, 11), + ('reserved_1', ctypes.c_uint32, 2), + ('src_pitch', ctypes.c_uint32, 19), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0), + ('DW_4_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._fields_ = [ + ('src_slice_pitch', ctypes.c_uint32, 28), + ('reserved_1', ctypes.c_uint32, 4), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0), + ('DW_5_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._fields_ = [ + ('dst_addr_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0), + ('DW_6_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._fields_ = [ + ('dst_addr_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0), + ('DW_7_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._fields_ = [ + ('dst_offset_x', ctypes.c_uint32, 14), + ('reserved_1', ctypes.c_uint32, 2), + ('dst_offset_y', ctypes.c_uint32, 14), + ('reserved_2', ctypes.c_uint32, 2), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0), + ('DW_8_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._fields_ = [ + ('dst_offset_z', ctypes.c_uint32, 11), + ('reserved_1', ctypes.c_uint32, 2), + ('dst_pitch', ctypes.c_uint32, 19), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0), + ('DW_9_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._fields_ = [ + ('dst_slice_pitch', ctypes.c_uint32, 28), + ('reserved_1', ctypes.c_uint32, 4), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0), + ('DW_10_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._fields_ = [ + ('rect_x', ctypes.c_uint32, 14), + ('reserved_1', ctypes.c_uint32, 2), + ('rect_y', ctypes.c_uint32, 14), + ('reserved_2', ctypes.c_uint32, 2), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0), + ('DW_11_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._fields_ = [ + ('rect_z', ctypes.c_uint32, 11), + ('reserved_1', ctypes.c_uint32, 5), + ('dst_swap', ctypes.c_uint32, 2), + ('reserved_2', ctypes.c_uint32, 6), + ('src_swap', ctypes.c_uint32, 2), + ('reserved_3', ctypes.c_uint32, 6), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0), + ('DW_12_DATA', ctypes.c_uint32), +] + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._fields_ = [ + ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION), + ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION), + ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION), + ('SRC_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION), + ('SRC_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION), + ('SRC_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION), + ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION), + ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION), + ('DST_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION), + ('DST_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION), + ('DST_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION), + ('RECT_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION), + ('RECT_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION), +] + +SDMA_PKT_COPY_LINEAR_RECT = struct_SDMA_PKT_COPY_LINEAR_RECT_TAG +class struct_SDMA_PKT_CONSTANT_FILL_TAG(Structure): + pass + +class union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION(Union): + pass + +class struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0(Structure): + pass + +struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._pack_ = 1 # source:False +struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._fields_ = [ + ('op', ctypes.c_uint32, 8), + ('sub_op', ctypes.c_uint32, 8), + ('sw', ctypes.c_uint32, 2), + ('reserved_0', ctypes.c_uint32, 12), + ('fillsize', ctypes.c_uint32, 2), +] + +union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._pack_ = 1 # source:False +union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0), + ('DW_0_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION(Union): + pass + +class struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0(Structure): + pass + +struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._pack_ = 1 # source:False +struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._fields_ = [ + ('dst_addr_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0), + ('DW_1_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION(Union): + pass + +class struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0(Structure): + pass + +struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._pack_ = 1 # source:False +struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._fields_ = [ + ('dst_addr_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0), + ('DW_2_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION(Union): + pass + +class struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0(Structure): + pass + +struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._pack_ = 1 # source:False +struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._fields_ = [ + ('src_data_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._pack_ = 1 # source:False +union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0), + ('DW_3_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION(Union): + pass + +class struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0(Structure): + pass + +struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._pack_ = 1 # source:False +struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._fields_ = [ + ('count', ctypes.c_uint32, 22), + ('reserved_0', ctypes.c_uint32, 10), +] + +union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._pack_ = 1 # source:False +union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0), + ('DW_4_DATA', ctypes.c_uint32), +] + +struct_SDMA_PKT_CONSTANT_FILL_TAG._pack_ = 1 # source:False +struct_SDMA_PKT_CONSTANT_FILL_TAG._fields_ = [ + ('HEADER_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION), + ('DST_ADDR_LO_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION), + ('DST_ADDR_HI_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION), + ('DATA_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION), + ('COUNT_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION), +] + +SDMA_PKT_CONSTANT_FILL = struct_SDMA_PKT_CONSTANT_FILL_TAG +class struct_SDMA_PKT_FENCE_TAG(Structure): + pass + +class union_SDMA_PKT_FENCE_TAG_HEADER_UNION(Union): + pass + +class struct_SDMA_PKT_FENCE_TAG_0_0(Structure): + pass + +struct_SDMA_PKT_FENCE_TAG_0_0._pack_ = 1 # source:False +struct_SDMA_PKT_FENCE_TAG_0_0._fields_ = [ + ('op', ctypes.c_uint32, 8), + ('sub_op', ctypes.c_uint32, 8), + ('mtype', ctypes.c_uint32, 3), + ('gcc', ctypes.c_uint32, 1), + ('sys', ctypes.c_uint32, 1), + ('pad1', ctypes.c_uint32, 1), + ('snp', ctypes.c_uint32, 1), + ('gpa', ctypes.c_uint32, 1), + ('l2_policy', ctypes.c_uint32, 2), + ('reserved_0', ctypes.c_uint32, 6), +] + +union_SDMA_PKT_FENCE_TAG_HEADER_UNION._pack_ = 1 # source:False +union_SDMA_PKT_FENCE_TAG_HEADER_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_FENCE_TAG_HEADER_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_FENCE_TAG_0_0), + ('DW_0_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION(Union): + pass + +class struct_SDMA_PKT_FENCE_TAG_1_0(Structure): + pass + +struct_SDMA_PKT_FENCE_TAG_1_0._pack_ = 1 # source:False +struct_SDMA_PKT_FENCE_TAG_1_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_FENCE_TAG_1_0), + ('DW_1_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION(Union): + pass + +class struct_SDMA_PKT_FENCE_TAG_2_0(Structure): + pass + +struct_SDMA_PKT_FENCE_TAG_2_0._pack_ = 1 # source:False +struct_SDMA_PKT_FENCE_TAG_2_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_FENCE_TAG_2_0), + ('DW_2_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_FENCE_TAG_DATA_UNION(Union): + pass + +class struct_SDMA_PKT_FENCE_TAG_3_0(Structure): + pass + +struct_SDMA_PKT_FENCE_TAG_3_0._pack_ = 1 # source:False +struct_SDMA_PKT_FENCE_TAG_3_0._fields_ = [ + ('data', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_FENCE_TAG_DATA_UNION._pack_ = 1 # source:False +union_SDMA_PKT_FENCE_TAG_DATA_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_FENCE_TAG_DATA_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_FENCE_TAG_3_0), + ('DW_3_DATA', ctypes.c_uint32), +] + +struct_SDMA_PKT_FENCE_TAG._pack_ = 1 # source:False +struct_SDMA_PKT_FENCE_TAG._fields_ = [ + ('HEADER_UNION', union_SDMA_PKT_FENCE_TAG_HEADER_UNION), + ('ADDR_LO_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION), + ('DATA_UNION', union_SDMA_PKT_FENCE_TAG_DATA_UNION), +] + +SDMA_PKT_FENCE = struct_SDMA_PKT_FENCE_TAG +class struct_SDMA_PKT_POLL_REGMEM_TAG(Structure): + pass + +class union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION(Union): + pass + +class struct_SDMA_PKT_POLL_REGMEM_TAG_0_0(Structure): + pass + +struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._pack_ = 1 # source:False +struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._fields_ = [ + ('op', ctypes.c_uint32, 8), + ('sub_op', ctypes.c_uint32, 8), + ('reserved_0', ctypes.c_uint32, 10), + ('hdp_flush', ctypes.c_uint32, 1), + ('reserved_1', ctypes.c_uint32, 1), + ('func', ctypes.c_uint32, 3), + ('mem_poll', ctypes.c_uint32, 1), +] + +union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._pack_ = 1 # source:False +union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_0_0), + ('DW_0_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION(Union): + pass + +class struct_SDMA_PKT_POLL_REGMEM_TAG_1_0(Structure): + pass + +struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._pack_ = 1 # source:False +struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_1_0), + ('DW_1_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION(Union): + pass + +class struct_SDMA_PKT_POLL_REGMEM_TAG_2_0(Structure): + pass + +struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._pack_ = 1 # source:False +struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_2_0), + ('DW_2_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION(Union): + pass + +class struct_SDMA_PKT_POLL_REGMEM_TAG_3_0(Structure): + pass + +struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._pack_ = 1 # source:False +struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._fields_ = [ + ('value', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._pack_ = 1 # source:False +union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_3_0), + ('DW_3_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION(Union): + pass + +class struct_SDMA_PKT_POLL_REGMEM_TAG_4_0(Structure): + pass + +struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._pack_ = 1 # source:False +struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._fields_ = [ + ('mask', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._pack_ = 1 # source:False +union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_4_0), + ('DW_4_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION(Union): + pass + +class struct_SDMA_PKT_POLL_REGMEM_TAG_5_0(Structure): + pass + +struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._pack_ = 1 # source:False +struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._fields_ = [ + ('interval', ctypes.c_uint32, 16), + ('retry_count', ctypes.c_uint32, 12), + ('reserved_0', ctypes.c_uint32, 4), +] + +union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._pack_ = 1 # source:False +union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_5_0), + ('DW_5_DATA', ctypes.c_uint32), +] + +struct_SDMA_PKT_POLL_REGMEM_TAG._pack_ = 1 # source:False +struct_SDMA_PKT_POLL_REGMEM_TAG._fields_ = [ + ('HEADER_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION), + ('ADDR_LO_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION), + ('VALUE_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION), + ('MASK_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION), + ('DW5_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION), +] + +SDMA_PKT_POLL_REGMEM = struct_SDMA_PKT_POLL_REGMEM_TAG +class struct_SDMA_PKT_ATOMIC_TAG(Structure): + pass + +class union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION(Union): + pass + +class struct_SDMA_PKT_ATOMIC_TAG_0_0(Structure): + pass + +struct_SDMA_PKT_ATOMIC_TAG_0_0._pack_ = 1 # source:False +struct_SDMA_PKT_ATOMIC_TAG_0_0._fields_ = [ + ('op', ctypes.c_uint32, 8), + ('sub_op', ctypes.c_uint32, 8), + ('l', ctypes.c_uint32, 1), + ('reserved_0', ctypes.c_uint32, 8), + ('operation', ctypes.c_uint32, 7), +] + +union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._pack_ = 1 # source:False +union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_ATOMIC_TAG_0_0), + ('DW_0_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION(Union): + pass + +class struct_SDMA_PKT_ATOMIC_TAG_1_0(Structure): + pass + +struct_SDMA_PKT_ATOMIC_TAG_1_0._pack_ = 1 # source:False +struct_SDMA_PKT_ATOMIC_TAG_1_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_ATOMIC_TAG_1_0), + ('DW_1_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION(Union): + pass + +class struct_SDMA_PKT_ATOMIC_TAG_2_0(Structure): + pass + +struct_SDMA_PKT_ATOMIC_TAG_2_0._pack_ = 1 # source:False +struct_SDMA_PKT_ATOMIC_TAG_2_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_ATOMIC_TAG_2_0), + ('DW_2_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION(Union): + pass + +class struct_SDMA_PKT_ATOMIC_TAG_3_0(Structure): + pass + +struct_SDMA_PKT_ATOMIC_TAG_3_0._pack_ = 1 # source:False +struct_SDMA_PKT_ATOMIC_TAG_3_0._fields_ = [ + ('src_data_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_ATOMIC_TAG_3_0), + ('DW_3_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION(Union): + pass + +class struct_SDMA_PKT_ATOMIC_TAG_4_0(Structure): + pass + +struct_SDMA_PKT_ATOMIC_TAG_4_0._pack_ = 1 # source:False +struct_SDMA_PKT_ATOMIC_TAG_4_0._fields_ = [ + ('src_data_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_ATOMIC_TAG_4_0), + ('DW_4_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION(Union): + pass + +class struct_SDMA_PKT_ATOMIC_TAG_5_0(Structure): + pass + +struct_SDMA_PKT_ATOMIC_TAG_5_0._pack_ = 1 # source:False +struct_SDMA_PKT_ATOMIC_TAG_5_0._fields_ = [ + ('cmp_data_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_ATOMIC_TAG_5_0), + ('DW_5_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION(Union): + pass + +class struct_SDMA_PKT_ATOMIC_TAG_6_0(Structure): + pass + +struct_SDMA_PKT_ATOMIC_TAG_6_0._pack_ = 1 # source:False +struct_SDMA_PKT_ATOMIC_TAG_6_0._fields_ = [ + ('cmp_data_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_ATOMIC_TAG_6_0), + ('DW_6_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION(Union): + pass + +class struct_SDMA_PKT_ATOMIC_TAG_7_0(Structure): + pass + +struct_SDMA_PKT_ATOMIC_TAG_7_0._pack_ = 1 # source:False +struct_SDMA_PKT_ATOMIC_TAG_7_0._fields_ = [ + ('loop_interval', ctypes.c_uint32, 13), + ('reserved_0', ctypes.c_uint32, 19), +] + +union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._pack_ = 1 # source:False +union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_ATOMIC_TAG_7_0), + ('DW_7_DATA', ctypes.c_uint32), +] + +struct_SDMA_PKT_ATOMIC_TAG._pack_ = 1 # source:False +struct_SDMA_PKT_ATOMIC_TAG._fields_ = [ + ('HEADER_UNION', union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION), + ('ADDR_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION), + ('SRC_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION), + ('SRC_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION), + ('CMP_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION), + ('CMP_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION), + ('LOOP_UNION', union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION), +] + +SDMA_PKT_ATOMIC = struct_SDMA_PKT_ATOMIC_TAG +class struct_SDMA_PKT_TIMESTAMP_TAG(Structure): + pass + +class union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION(Union): + pass + +class struct_SDMA_PKT_TIMESTAMP_TAG_0_0(Structure): + pass + +struct_SDMA_PKT_TIMESTAMP_TAG_0_0._pack_ = 1 # source:False +struct_SDMA_PKT_TIMESTAMP_TAG_0_0._fields_ = [ + ('op', ctypes.c_uint32, 8), + ('sub_op', ctypes.c_uint32, 8), + ('reserved_0', ctypes.c_uint32, 16), +] + +union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._pack_ = 1 # source:False +union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_0_0), + ('DW_0_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION(Union): + pass + +class struct_SDMA_PKT_TIMESTAMP_TAG_1_0(Structure): + pass + +struct_SDMA_PKT_TIMESTAMP_TAG_1_0._pack_ = 1 # source:False +struct_SDMA_PKT_TIMESTAMP_TAG_1_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_1_0), + ('DW_1_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION(Union): + pass + +class struct_SDMA_PKT_TIMESTAMP_TAG_2_0(Structure): + pass + +struct_SDMA_PKT_TIMESTAMP_TAG_2_0._pack_ = 1 # source:False +struct_SDMA_PKT_TIMESTAMP_TAG_2_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_2_0), + ('DW_2_DATA', ctypes.c_uint32), +] + +struct_SDMA_PKT_TIMESTAMP_TAG._pack_ = 1 # source:False +struct_SDMA_PKT_TIMESTAMP_TAG._fields_ = [ + ('HEADER_UNION', union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION), + ('ADDR_LO_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION), +] + +SDMA_PKT_TIMESTAMP = struct_SDMA_PKT_TIMESTAMP_TAG +class struct_SDMA_PKT_TRAP_TAG(Structure): + pass + +class union_SDMA_PKT_TRAP_TAG_HEADER_UNION(Union): + pass + +class struct_SDMA_PKT_TRAP_TAG_0_0(Structure): + pass + +struct_SDMA_PKT_TRAP_TAG_0_0._pack_ = 1 # source:False +struct_SDMA_PKT_TRAP_TAG_0_0._fields_ = [ + ('op', ctypes.c_uint32, 8), + ('sub_op', ctypes.c_uint32, 8), + ('reserved_0', ctypes.c_uint32, 16), +] + +union_SDMA_PKT_TRAP_TAG_HEADER_UNION._pack_ = 1 # source:False +union_SDMA_PKT_TRAP_TAG_HEADER_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_TRAP_TAG_HEADER_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_TRAP_TAG_0_0), + ('DW_0_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION(Union): + pass + +class struct_SDMA_PKT_TRAP_TAG_1_0(Structure): + pass + +struct_SDMA_PKT_TRAP_TAG_1_0._pack_ = 1 # source:False +struct_SDMA_PKT_TRAP_TAG_1_0._fields_ = [ + ('int_ctx', ctypes.c_uint32, 28), + ('reserved_1', ctypes.c_uint32, 4), +] + +union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._pack_ = 1 # source:False +union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_TRAP_TAG_1_0), + ('DW_1_DATA', ctypes.c_uint32), +] + +struct_SDMA_PKT_TRAP_TAG._pack_ = 1 # source:False +struct_SDMA_PKT_TRAP_TAG._fields_ = [ + ('HEADER_UNION', union_SDMA_PKT_TRAP_TAG_HEADER_UNION), + ('INT_CONTEXT_UNION', union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION), +] + +SDMA_PKT_TRAP = struct_SDMA_PKT_TRAP_TAG +class struct_SDMA_PKT_HDP_FLUSH_TAG(Structure): + pass + +struct_SDMA_PKT_HDP_FLUSH_TAG._pack_ = 1 # source:False +struct_SDMA_PKT_HDP_FLUSH_TAG._fields_ = [ + ('DW_0_DATA', ctypes.c_uint32), + ('DW_1_DATA', ctypes.c_uint32), + ('DW_2_DATA', ctypes.c_uint32), + ('DW_3_DATA', ctypes.c_uint32), + ('DW_4_DATA', ctypes.c_uint32), + ('DW_5_DATA', ctypes.c_uint32), +] + +SDMA_PKT_HDP_FLUSH = struct_SDMA_PKT_HDP_FLUSH_TAG +hdp_flush_cmd = struct_SDMA_PKT_HDP_FLUSH_TAG # Variable struct_SDMA_PKT_HDP_FLUSH_TAG +class struct_SDMA_PKT_GCR_TAG(Structure): + pass + +class union_SDMA_PKT_GCR_TAG_HEADER_UNION(Union): + pass + +class struct_SDMA_PKT_GCR_TAG_0_0(Structure): + pass + +struct_SDMA_PKT_GCR_TAG_0_0._pack_ = 1 # source:False +struct_SDMA_PKT_GCR_TAG_0_0._fields_ = [ + ('op', ctypes.c_uint32, 8), + ('sub_op', ctypes.c_uint32, 8), + ('_2', ctypes.c_uint32, 16), +] + +union_SDMA_PKT_GCR_TAG_HEADER_UNION._pack_ = 1 # source:False +union_SDMA_PKT_GCR_TAG_HEADER_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_GCR_TAG_HEADER_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_GCR_TAG_0_0), + ('DW_0_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_GCR_TAG_WORD1_UNION(Union): + pass + +class struct_SDMA_PKT_GCR_TAG_1_0(Structure): + pass + +struct_SDMA_PKT_GCR_TAG_1_0._pack_ = 1 # source:False +struct_SDMA_PKT_GCR_TAG_1_0._fields_ = [ + ('_0', ctypes.c_uint32, 7), + ('BaseVA_LO', ctypes.c_uint32, 25), +] + +union_SDMA_PKT_GCR_TAG_WORD1_UNION._pack_ = 1 # source:False +union_SDMA_PKT_GCR_TAG_WORD1_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_GCR_TAG_WORD1_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_GCR_TAG_1_0), + ('DW_1_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_GCR_TAG_WORD2_UNION(Union): + pass + +class struct_SDMA_PKT_GCR_TAG_2_0(Structure): + pass + +struct_SDMA_PKT_GCR_TAG_2_0._pack_ = 1 # source:False +struct_SDMA_PKT_GCR_TAG_2_0._fields_ = [ + ('BaseVA_HI', ctypes.c_uint32, 16), + ('GCR_CONTROL_GLI_INV', ctypes.c_uint32, 2), + ('GCR_CONTROL_GL1_RANGE', ctypes.c_uint32, 2), + ('GCR_CONTROL_GLM_WB', ctypes.c_uint32, 1), + ('GCR_CONTROL_GLM_INV', ctypes.c_uint32, 1), + ('GCR_CONTROL_GLK_WB', ctypes.c_uint32, 1), + ('GCR_CONTROL_GLK_INV', ctypes.c_uint32, 1), + ('GCR_CONTROL_GLV_INV', ctypes.c_uint32, 1), + ('GCR_CONTROL_GL1_INV', ctypes.c_uint32, 1), + ('GCR_CONTROL_GL2_US', ctypes.c_uint32, 1), + ('GCR_CONTROL_GL2_RANGE', ctypes.c_uint32, 2), + ('GCR_CONTROL_GL2_DISCARD', ctypes.c_uint32, 1), + ('GCR_CONTROL_GL2_INV', ctypes.c_uint32, 1), + ('GCR_CONTROL_GL2_WB', ctypes.c_uint32, 1), +] + +union_SDMA_PKT_GCR_TAG_WORD2_UNION._pack_ = 1 # source:False +union_SDMA_PKT_GCR_TAG_WORD2_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_GCR_TAG_WORD2_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_GCR_TAG_2_0), + ('DW_2_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_GCR_TAG_WORD3_UNION(Union): + pass + +class struct_SDMA_PKT_GCR_TAG_3_0(Structure): + pass + +struct_SDMA_PKT_GCR_TAG_3_0._pack_ = 1 # source:False +struct_SDMA_PKT_GCR_TAG_3_0._fields_ = [ + ('GCR_CONTROL_RANGE_IS_PA', ctypes.c_uint32, 1), + ('GCR_CONTROL_SEQ', ctypes.c_uint32, 2), + ('_2', ctypes.c_uint32, 4), + ('LimitVA_LO', ctypes.c_uint32, 25), +] + +union_SDMA_PKT_GCR_TAG_WORD3_UNION._pack_ = 1 # source:False +union_SDMA_PKT_GCR_TAG_WORD3_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_GCR_TAG_WORD3_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_GCR_TAG_3_0), + ('DW_3_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_GCR_TAG_WORD4_UNION(Union): + pass + +class struct_SDMA_PKT_GCR_TAG_4_0(Structure): + pass + +struct_SDMA_PKT_GCR_TAG_4_0._pack_ = 1 # source:False +struct_SDMA_PKT_GCR_TAG_4_0._fields_ = [ + ('LimitVA_HI', ctypes.c_uint32, 16), + ('_1', ctypes.c_uint32, 8), + ('VMID', ctypes.c_uint32, 4), + ('_3', ctypes.c_uint32, 4), +] + +union_SDMA_PKT_GCR_TAG_WORD4_UNION._pack_ = 1 # source:False +union_SDMA_PKT_GCR_TAG_WORD4_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_GCR_TAG_WORD4_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_GCR_TAG_4_0), + ('DW_4_DATA', ctypes.c_uint32), +] + +struct_SDMA_PKT_GCR_TAG._pack_ = 1 # source:False +struct_SDMA_PKT_GCR_TAG._fields_ = [ + ('HEADER_UNION', union_SDMA_PKT_GCR_TAG_HEADER_UNION), + ('WORD1_UNION', union_SDMA_PKT_GCR_TAG_WORD1_UNION), + ('WORD2_UNION', union_SDMA_PKT_GCR_TAG_WORD2_UNION), + ('WORD3_UNION', union_SDMA_PKT_GCR_TAG_WORD3_UNION), + ('WORD4_UNION', union_SDMA_PKT_GCR_TAG_WORD4_UNION), +] + +SDMA_PKT_GCR = struct_SDMA_PKT_GCR_TAG +__VEGA10_SDMA_PKT_OPEN_H_ = True # macro +SDMA_OP_NOP = 0 # macro +SDMA_OP_WRITE = 2 # macro +SDMA_OP_INDIRECT = 4 # macro +SDMA_OP_SEM = 7 # macro +SDMA_OP_COND_EXE = 9 # macro +SDMA_OP_PTEPDE = 12 # macro +SDMA_OP_SRBM_WRITE = 14 # macro +SDMA_OP_PRE_EXE = 15 # macro +SDMA_OP_DUMMY_TRAP = 16 # macro +SDMA_SUBOP_TIMESTAMP_SET = 0 # macro +SDMA_SUBOP_TIMESTAMP_GET = 1 # macro +SDMA_SUBOP_COPY_LINEAR_SUB_WIND = 4 # macro +SDMA_SUBOP_COPY_TILED = 1 # macro +SDMA_SUBOP_COPY_TILED_SUB_WIND = 5 # macro +SDMA_SUBOP_COPY_T2T_SUB_WIND = 6 # macro +SDMA_SUBOP_COPY_SOA = 3 # macro +SDMA_SUBOP_COPY_DIRTY_PAGE = 7 # macro +SDMA_SUBOP_COPY_LINEAR_PHY = 8 # macro +SDMA_SUBOP_WRITE_LINEAR = 0 # macro +SDMA_SUBOP_WRITE_TILED = 1 # macro +SDMA_SUBOP_PTEPDE_GEN = 0 # macro +SDMA_SUBOP_PTEPDE_COPY = 1 # macro +SDMA_SUBOP_PTEPDE_RMW = 2 # macro +SDMA_SUBOP_PTEPDE_COPY_BACKWARDS = 3 # macro +SDMA_SUBOP_DATA_FILL_MULTI = 1 # macro +SDMA_SUBOP_POLL_REG_WRITE_MEM = 1 # macro +SDMA_SUBOP_POLL_DBIT_WRITE_MEM = 2 # macro +SDMA_SUBOP_POLL_MEM_VERIFY = 3 # macro +HEADER_AGENT_DISPATCH = 4 # macro +HEADER_BARRIER = 5 # macro +SDMA_OP_AQL_COPY = 0 # macro +SDMA_OP_AQL_BARRIER_OR = 0 # macro +SDMA_PKT_HEADER_op_offset = 0 # macro +SDMA_PKT_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_HEADER_op_shift = 0 # macro +def SDMA_PKT_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_LINEAR_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro +SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro +SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift = 27 # macro +def SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x): # macro + return (((x)&0x00000001)<<27) +SDMA_PKT_COPY_LINEAR_COUNT_count_offset = 1 # macro +SDMA_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF # macro +SDMA_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro + return (((x)&0x003FFFFF)<<0) +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 2 # macro +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 2 # macro +SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro +SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro +SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro +SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro +SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset = 0 # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift = 31 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset = 1 # macro +SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask = 0x003FFFFF # macro +SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x): # macro + return (((x)&0x003FFFFF)<<0) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift = 16 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift = 19 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift = 20 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x): # macro + return (((x)&0x00000001)<<20) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift = 22 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x): # macro + return (((x)&0x00000001)<<22) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift = 23 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x): # macro + return (((x)&0x00000001)<<23) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift = 28 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift = 30 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x): # macro + return (((x)&0x00000001)<<30) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift = 31 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset = 1 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask = 0x003FFFFF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x): # macro + return (((x)&0x003FFFFF)<<0) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift = 16 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift = 19 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift = 20 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x): # macro + return (((x)&0x00000001)<<20) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift = 21 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x): # macro + return (((x)&0x00000001)<<21) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift = 22 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x): # macro + return (((x)&0x00000001)<<22) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift = 23 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x): # macro + return (((x)&0x00000001)<<23) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift = 27 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x): # macro + return (((x)&0x00000001)<<27) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift = 28 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift = 30 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x): # macro + return (((x)&0x00000001)<<30) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift = 31 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset = 0 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift = 16 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset = 0 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift = 27 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x): # macro + return (((x)&0x00000001)<<27) +SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset = 1 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask = 0x003FFFFF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x): # macro + return (((x)&0x003FFFFF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset = 2 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift = 8 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x): # macro + return (((x)&0x00000003)<<8) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset = 2 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift = 16 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset = 2 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset = 5 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset = 6 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset = 7 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset = 8 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask = 0x00000007 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift = 29 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x): # macro + return (((x)&0x00000007)<<29) +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset = 3 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset = 3 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset = 4 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset = 4 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask = 0x0007FFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift = 13 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x): # macro + return (((x)&0x0007FFFF)<<13) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset = 5 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask = 0x0FFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x): # macro + return (((x)&0x0FFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset = 6 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset = 7 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset = 8 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset = 8 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset = 9 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset = 9 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask = 0x0007FFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift = 13 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x): # macro + return (((x)&0x0007FFFF)<<13) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset = 10 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x): # macro + return (((x)&0x0FFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset = 11 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset = 11 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset = 12 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset = 12 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset = 12 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_TILED_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_TILED_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_TILED_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_TILED_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_TILED_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_TILED_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_TILED_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_TILED_HEADER_encrypt_offset = 0 # macro +SDMA_PKT_COPY_TILED_HEADER_encrypt_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_HEADER_encrypt_shift = 16 # macro +def SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_COPY_TILED_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_TILED_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_TILED_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_TILED_HEADER_mip_max_offset = 0 # macro +SDMA_PKT_COPY_TILED_HEADER_mip_max_mask = 0x0000000F # macro +SDMA_PKT_COPY_TILED_HEADER_mip_max_shift = 20 # macro +def SDMA_PKT_COPY_TILED_HEADER_MIP_MAX(x): # macro + return (((x)&0x0000000F)<<20) +SDMA_PKT_COPY_TILED_HEADER_detile_offset = 0 # macro +SDMA_PKT_COPY_TILED_HEADER_detile_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_HEADER_detile_shift = 31 # macro +def SDMA_PKT_COPY_TILED_HEADER_DETILE(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro +SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro +SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_DW_3_width_offset = 3 # macro +SDMA_PKT_COPY_TILED_DW_3_width_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_DW_3_width_shift = 0 # macro +def SDMA_PKT_COPY_TILED_DW_3_WIDTH(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_DW_4_height_offset = 4 # macro +SDMA_PKT_COPY_TILED_DW_4_height_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_DW_4_height_shift = 0 # macro +def SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_DW_4_depth_offset = 4 # macro +SDMA_PKT_COPY_TILED_DW_4_depth_mask = 0x000007FF # macro +SDMA_PKT_COPY_TILED_DW_4_depth_shift = 16 # macro +def SDMA_PKT_COPY_TILED_DW_4_DEPTH(x): # macro + return (((x)&0x000007FF)<<16) +SDMA_PKT_COPY_TILED_DW_5_element_size_offset = 5 # macro +SDMA_PKT_COPY_TILED_DW_5_element_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_TILED_DW_5_element_size_shift = 0 # macro +def SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset = 5 # macro +SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro +SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift = 3 # macro +def SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x): # macro + return (((x)&0x0000001F)<<3) +SDMA_PKT_COPY_TILED_DW_5_dimension_offset = 5 # macro +SDMA_PKT_COPY_TILED_DW_5_dimension_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_DW_5_dimension_shift = 9 # macro +def SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x): # macro + return (((x)&0x00000003)<<9) +SDMA_PKT_COPY_TILED_DW_5_epitch_offset = 5 # macro +SDMA_PKT_COPY_TILED_DW_5_epitch_mask = 0x0000FFFF # macro +SDMA_PKT_COPY_TILED_DW_5_epitch_shift = 16 # macro +def SDMA_PKT_COPY_TILED_DW_5_EPITCH(x): # macro + return (((x)&0x0000FFFF)<<16) +SDMA_PKT_COPY_TILED_DW_6_x_offset = 6 # macro +SDMA_PKT_COPY_TILED_DW_6_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_DW_6_x_shift = 0 # macro +def SDMA_PKT_COPY_TILED_DW_6_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_DW_6_y_offset = 6 # macro +SDMA_PKT_COPY_TILED_DW_6_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_DW_6_y_shift = 16 # macro +def SDMA_PKT_COPY_TILED_DW_6_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_DW_7_z_offset = 7 # macro +SDMA_PKT_COPY_TILED_DW_7_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_TILED_DW_7_z_shift = 0 # macro +def SDMA_PKT_COPY_TILED_DW_7_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset = 7 # macro +SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift = 16 # macro +def SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset = 7 # macro +SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift = 24 # macro +def SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 # macro +SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 # macro +SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset = 10 # macro +SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro +SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift = 0 # macro +def SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x): # macro + return (((x)&0x0007FFFF)<<0) +SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 # macro +SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro +def SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_COUNT_count_offset = 12 # macro +SDMA_PKT_COPY_TILED_COUNT_count_mask = 0x000FFFFF # macro +SDMA_PKT_COPY_TILED_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_TILED_COUNT_COUNT(x): # macro + return (((x)&0x000FFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset = 0 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask = 0x00000001 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift = 16 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_offset = 0 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask = 0x0000000F # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift = 20 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_MIP_MAX(x): # macro + return (((x)&0x0000000F)<<20) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset = 0 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask = 0x00000001 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift = 26 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x): # macro + return (((x)&0x00000001)<<26) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset = 0 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask = 0x00000001 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift = 27 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x): # macro + return (((x)&0x00000001)<<27) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset = 1 # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset = 2 # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset = 3 # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset = 4 # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset = 5 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask = 0x00003FFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset = 6 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask = 0x00003FFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset = 6 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask = 0x000007FF # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift = 16 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x): # macro + return (((x)&0x000007FF)<<16) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset = 7 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset = 7 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask = 0x0000001F # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift = 3 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x): # macro + return (((x)&0x0000001F)<<3) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset = 7 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask = 0x00000003 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift = 9 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x): # macro + return (((x)&0x00000003)<<9) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_offset = 7 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask = 0x0000FFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift = 16 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_EPITCH(x): # macro + return (((x)&0x0000FFFF)<<16) +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset = 8 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset = 8 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift = 16 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset = 9 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset = 10 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift = 8 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x): # macro + return (((x)&0x00000003)<<8) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset = 10 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift = 16 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset = 10 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift = 24 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset = 11 # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset = 12 # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset = 13 # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x): # macro + return (((x)&0x0007FFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 14 # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset = 15 # macro +SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask = 0x000FFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x): # macro + return (((x)&0x000FFFFF)<<0) +SDMA_PKT_COPY_T2T_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_T2T_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_T2T_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_T2T_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_T2T_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_T2T_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_T2T_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_T2T_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_T2T_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_T2T_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_T2T_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_T2T_HEADER_mip_max_offset = 0 # macro +SDMA_PKT_COPY_T2T_HEADER_mip_max_mask = 0x0000000F # macro +SDMA_PKT_COPY_T2T_HEADER_mip_max_shift = 20 # macro +def SDMA_PKT_COPY_T2T_HEADER_MIP_MAX(x): # macro + return (((x)&0x0000000F)<<20) +SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro +SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro +SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_T2T_DW_3_src_x_offset = 3 # macro +SDMA_PKT_COPY_T2T_DW_3_src_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_3_src_x_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_3_SRC_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_T2T_DW_3_src_y_offset = 3 # macro +SDMA_PKT_COPY_T2T_DW_3_src_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_3_src_y_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_T2T_DW_4_src_z_offset = 4 # macro +SDMA_PKT_COPY_T2T_DW_4_src_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_T2T_DW_4_src_z_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_T2T_DW_4_src_width_offset = 4 # macro +SDMA_PKT_COPY_T2T_DW_4_src_width_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_4_src_width_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_T2T_DW_5_src_height_offset = 5 # macro +SDMA_PKT_COPY_T2T_DW_5_src_height_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_5_src_height_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_T2T_DW_5_src_depth_offset = 5 # macro +SDMA_PKT_COPY_T2T_DW_5_src_depth_mask = 0x000007FF # macro +SDMA_PKT_COPY_T2T_DW_5_src_depth_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x): # macro + return (((x)&0x000007FF)<<16) +SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset = 6 # macro +SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset = 6 # macro +SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask = 0x0000001F # macro +SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift = 3 # macro +def SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x): # macro + return (((x)&0x0000001F)<<3) +SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset = 6 # macro +SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift = 9 # macro +def SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x): # macro + return (((x)&0x00000003)<<9) +SDMA_PKT_COPY_T2T_DW_6_src_epitch_offset = 6 # macro +SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask = 0x0000FFFF # macro +SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_6_SRC_EPITCH(x): # macro + return (((x)&0x0000FFFF)<<16) +SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset = 7 # macro +SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset = 8 # macro +SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_T2T_DW_9_dst_x_offset = 9 # macro +SDMA_PKT_COPY_T2T_DW_9_dst_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_9_dst_x_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_9_DST_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_T2T_DW_9_dst_y_offset = 9 # macro +SDMA_PKT_COPY_T2T_DW_9_dst_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_9_dst_y_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_9_DST_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_T2T_DW_10_dst_z_offset = 10 # macro +SDMA_PKT_COPY_T2T_DW_10_dst_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_T2T_DW_10_dst_z_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_10_DST_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_T2T_DW_10_dst_width_offset = 10 # macro +SDMA_PKT_COPY_T2T_DW_10_dst_width_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_10_dst_width_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_T2T_DW_11_dst_height_offset = 11 # macro +SDMA_PKT_COPY_T2T_DW_11_dst_height_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_11_dst_height_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset = 11 # macro +SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask = 0x000007FF # macro +SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x): # macro + return (((x)&0x000007FF)<<16) +SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset = 12 # macro +SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset = 12 # macro +SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask = 0x0000001F # macro +SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift = 3 # macro +def SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x): # macro + return (((x)&0x0000001F)<<3) +SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset = 12 # macro +SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift = 9 # macro +def SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x): # macro + return (((x)&0x00000003)<<9) +SDMA_PKT_COPY_T2T_DW_12_dst_epitch_offset = 12 # macro +SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask = 0x0000FFFF # macro +SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_12_DST_EPITCH(x): # macro + return (((x)&0x0000FFFF)<<16) +SDMA_PKT_COPY_T2T_DW_13_rect_x_offset = 13 # macro +SDMA_PKT_COPY_T2T_DW_13_rect_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_13_rect_x_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_13_RECT_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_T2T_DW_13_rect_y_offset = 13 # macro +SDMA_PKT_COPY_T2T_DW_13_rect_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_13_rect_y_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_T2T_DW_14_rect_z_offset = 14 # macro +SDMA_PKT_COPY_T2T_DW_14_rect_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_T2T_DW_14_rect_z_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset = 14 # macro +SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_14_DST_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_T2T_DW_14_src_sw_offset = 14 # macro +SDMA_PKT_COPY_T2T_DW_14_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_DW_14_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_offset = 0 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask = 0x0000000F # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift = 20 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_MAX(x): # macro + return (((x)&0x0000000F)<<20) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_offset = 0 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask = 0x0000000F # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift = 24 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_ID(x): # macro + return (((x)&0x0000000F)<<24) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset = 0 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift = 31 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset = 3 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset = 3 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset = 4 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset = 4 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset = 5 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset = 5 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask = 0x000007FF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x): # macro + return (((x)&0x000007FF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask = 0x0000001F # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift = 3 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x): # macro + return (((x)&0x0000001F)<<3) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift = 9 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x): # macro + return (((x)&0x00000003)<<9) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask = 0x0000FFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_EPITCH(x): # macro + return (((x)&0x0000FFFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 # macro +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 # macro +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset = 9 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset = 9 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset = 10 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset = 10 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset = 11 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x): # macro + return (((x)&0x0FFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset = 12 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset = 12 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset = 13 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset = 13 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset = 13 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift = 24 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_STRUCT_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_STRUCT_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_STRUCT_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_STRUCT_HEADER_detile_offset = 0 # macro +SDMA_PKT_COPY_STRUCT_HEADER_detile_mask = 0x00000001 # macro +SDMA_PKT_COPY_STRUCT_HEADER_detile_shift = 31 # macro +def SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset = 1 # macro +SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset = 2 # macro +SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset = 3 # macro +SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_STRUCT_COUNT_count_offset = 4 # macro +SDMA_PKT_COPY_STRUCT_COUNT_count_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_STRUCT_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_STRUCT_DW_5_stride_offset = 5 # macro +SDMA_PKT_COPY_STRUCT_DW_5_stride_mask = 0x000007FF # macro +SDMA_PKT_COPY_STRUCT_DW_5_stride_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset = 5 # macro +SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift = 16 # macro +def SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset = 5 # macro +SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift = 24 # macro +def SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset = 6 # macro +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset = 7 # macro +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_UNTILED_HEADER_op_offset = 0 # macro +SDMA_PKT_WRITE_UNTILED_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_WRITE_UNTILED_HEADER_op_shift = 0 # macro +def SDMA_PKT_WRITE_UNTILED_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset = 0 # macro +SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask = 0x00000001 # macro +SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift = 16 # macro +def SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset = 0 # macro +SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro +SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro +SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_UNTILED_DW_3_count_offset = 3 # macro +SDMA_PKT_WRITE_UNTILED_DW_3_count_mask = 0x000FFFFF # macro +SDMA_PKT_WRITE_UNTILED_DW_3_count_shift = 0 # macro +def SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x): # macro + return (((x)&0x000FFFFF)<<0) +SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset = 3 # macro +SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask = 0x00000003 # macro +SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift = 24 # macro +def SDMA_PKT_WRITE_UNTILED_DW_3_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset = 4 # macro +SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift = 0 # macro +def SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_TILED_HEADER_op_offset = 0 # macro +SDMA_PKT_WRITE_TILED_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_WRITE_TILED_HEADER_op_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset = 0 # macro +SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask = 0x00000001 # macro +SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift = 16 # macro +def SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_WRITE_TILED_HEADER_tmz_offset = 0 # macro +SDMA_PKT_WRITE_TILED_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_WRITE_TILED_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_WRITE_TILED_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_WRITE_TILED_HEADER_mip_max_offset = 0 # macro +SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask = 0x0000000F # macro +SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift = 20 # macro +def SDMA_PKT_WRITE_TILED_HEADER_MIP_MAX(x): # macro + return (((x)&0x0000000F)<<20) +SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro +SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro +SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_TILED_DW_3_width_offset = 3 # macro +SDMA_PKT_WRITE_TILED_DW_3_width_mask = 0x00003FFF # macro +SDMA_PKT_WRITE_TILED_DW_3_width_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_WRITE_TILED_DW_4_height_offset = 4 # macro +SDMA_PKT_WRITE_TILED_DW_4_height_mask = 0x00003FFF # macro +SDMA_PKT_WRITE_TILED_DW_4_height_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_WRITE_TILED_DW_4_depth_offset = 4 # macro +SDMA_PKT_WRITE_TILED_DW_4_depth_mask = 0x000007FF # macro +SDMA_PKT_WRITE_TILED_DW_4_depth_shift = 16 # macro +def SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x): # macro + return (((x)&0x000007FF)<<16) +SDMA_PKT_WRITE_TILED_DW_5_element_size_offset = 5 # macro +SDMA_PKT_WRITE_TILED_DW_5_element_size_mask = 0x00000007 # macro +SDMA_PKT_WRITE_TILED_DW_5_element_size_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset = 5 # macro +SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro +SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift = 3 # macro +def SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x): # macro + return (((x)&0x0000001F)<<3) +SDMA_PKT_WRITE_TILED_DW_5_dimension_offset = 5 # macro +SDMA_PKT_WRITE_TILED_DW_5_dimension_mask = 0x00000003 # macro +SDMA_PKT_WRITE_TILED_DW_5_dimension_shift = 9 # macro +def SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x): # macro + return (((x)&0x00000003)<<9) +SDMA_PKT_WRITE_TILED_DW_5_epitch_offset = 5 # macro +SDMA_PKT_WRITE_TILED_DW_5_epitch_mask = 0x0000FFFF # macro +SDMA_PKT_WRITE_TILED_DW_5_epitch_shift = 16 # macro +def SDMA_PKT_WRITE_TILED_DW_5_EPITCH(x): # macro + return (((x)&0x0000FFFF)<<16) +SDMA_PKT_WRITE_TILED_DW_6_x_offset = 6 # macro +SDMA_PKT_WRITE_TILED_DW_6_x_mask = 0x00003FFF # macro +SDMA_PKT_WRITE_TILED_DW_6_x_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DW_6_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_WRITE_TILED_DW_6_y_offset = 6 # macro +SDMA_PKT_WRITE_TILED_DW_6_y_mask = 0x00003FFF # macro +SDMA_PKT_WRITE_TILED_DW_6_y_shift = 16 # macro +def SDMA_PKT_WRITE_TILED_DW_6_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_WRITE_TILED_DW_7_z_offset = 7 # macro +SDMA_PKT_WRITE_TILED_DW_7_z_mask = 0x000007FF # macro +SDMA_PKT_WRITE_TILED_DW_7_z_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DW_7_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_WRITE_TILED_DW_7_sw_offset = 7 # macro +SDMA_PKT_WRITE_TILED_DW_7_sw_mask = 0x00000003 # macro +SDMA_PKT_WRITE_TILED_DW_7_sw_shift = 24 # macro +def SDMA_PKT_WRITE_TILED_DW_7_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_WRITE_TILED_COUNT_count_offset = 8 # macro +SDMA_PKT_WRITE_TILED_COUNT_count_mask = 0x000FFFFF # macro +SDMA_PKT_WRITE_TILED_COUNT_count_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_COUNT_COUNT(x): # macro + return (((x)&0x000FFFFF)<<0) +SDMA_PKT_WRITE_TILED_DATA0_data0_offset = 9 # macro +SDMA_PKT_WRITE_TILED_DATA0_data0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_TILED_DATA0_data0_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DATA0_DATA0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_HEADER_op_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_COPY_HEADER_op_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift = 31 # macro +def SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro +SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro +SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset = 5 # macro +SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset = 6 # macro +SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_COUNT_count_offset = 7 # macro +SDMA_PKT_PTEPDE_COPY_COUNT_count_mask = 0x0007FFFF # macro +SDMA_PKT_PTEPDE_COPY_COUNT_count_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x): # macro + return (((x)&0x0007FFFF)<<0) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask = 0x00000003 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift = 28 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x): # macro + return (((x)&0x00000003)<<28) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift = 30 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x): # macro + return (((x)&0x00000001)<<30) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift = 31 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset = 5 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset = 5 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift = 8 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset = 6 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask = 0x0001FFFF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x): # macro + return (((x)&0x0001FFFF)<<0) +SDMA_PKT_PTEPDE_RMW_HEADER_op_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_RMW_HEADER_op_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift = 19 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift = 20 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x): # macro + return (((x)&0x00000001)<<20) +SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift = 22 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x): # macro + return (((x)&0x00000001)<<22) +SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift = 23 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x): # macro + return (((x)&0x00000001)<<23) +SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset = 3 # macro +SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset = 4 # macro +SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset = 5 # macro +SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset = 6 # macro +SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_HEADER_op_offset = 0 # macro +SDMA_PKT_WRITE_INCR_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_WRITE_INCR_HEADER_op_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro +SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro +SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset = 3 # macro +SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset = 4 # macro +SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset = 5 # macro +SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset = 6 # macro +SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset = 7 # macro +SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset = 8 # macro +SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_COUNT_count_offset = 9 # macro +SDMA_PKT_WRITE_INCR_COUNT_count_mask = 0x0007FFFF # macro +SDMA_PKT_WRITE_INCR_COUNT_count_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_COUNT_COUNT(x): # macro + return (((x)&0x0007FFFF)<<0) +SDMA_PKT_INDIRECT_HEADER_op_offset = 0 # macro +SDMA_PKT_INDIRECT_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_INDIRECT_HEADER_op_shift = 0 # macro +def SDMA_PKT_INDIRECT_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_INDIRECT_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_INDIRECT_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_INDIRECT_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_INDIRECT_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_INDIRECT_HEADER_vmid_offset = 0 # macro +SDMA_PKT_INDIRECT_HEADER_vmid_mask = 0x0000000F # macro +SDMA_PKT_INDIRECT_HEADER_vmid_shift = 16 # macro +def SDMA_PKT_INDIRECT_HEADER_VMID(x): # macro + return (((x)&0x0000000F)<<16) +SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset = 1 # macro +SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift = 0 # macro +def SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset = 2 # macro +SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift = 0 # macro +def SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset = 3 # macro +SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask = 0x000FFFFF # macro +SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift = 0 # macro +def SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x): # macro + return (((x)&0x000FFFFF)<<0) +SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset = 4 # macro +SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift = 0 # macro +def SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset = 5 # macro +SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift = 0 # macro +def SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_SEMAPHORE_HEADER_op_offset = 0 # macro +SDMA_PKT_SEMAPHORE_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_SEMAPHORE_HEADER_op_shift = 0 # macro +def SDMA_PKT_SEMAPHORE_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_SEMAPHORE_HEADER_write_one_offset = 0 # macro +SDMA_PKT_SEMAPHORE_HEADER_write_one_mask = 0x00000001 # macro +SDMA_PKT_SEMAPHORE_HEADER_write_one_shift = 29 # macro +def SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x): # macro + return (((x)&0x00000001)<<29) +SDMA_PKT_SEMAPHORE_HEADER_signal_offset = 0 # macro +SDMA_PKT_SEMAPHORE_HEADER_signal_mask = 0x00000001 # macro +SDMA_PKT_SEMAPHORE_HEADER_signal_shift = 30 # macro +def SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x): # macro + return (((x)&0x00000001)<<30) +SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset = 0 # macro +SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask = 0x00000001 # macro +SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift = 31 # macro +def SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_FENCE_HEADER_op_offset = 0 # macro +SDMA_PKT_FENCE_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_FENCE_HEADER_op_shift = 0 # macro +def SDMA_PKT_FENCE_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_FENCE_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_FENCE_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_FENCE_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_FENCE_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_FENCE_DATA_data_offset = 3 # macro +SDMA_PKT_FENCE_DATA_data_mask = 0xFFFFFFFF # macro +SDMA_PKT_FENCE_DATA_data_shift = 0 # macro +def SDMA_PKT_FENCE_DATA_DATA(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_SRBM_WRITE_HEADER_op_offset = 0 # macro +SDMA_PKT_SRBM_WRITE_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_SRBM_WRITE_HEADER_op_shift = 0 # macro +def SDMA_PKT_SRBM_WRITE_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset = 0 # macro +SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask = 0x0000000F # macro +SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift = 28 # macro +def SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x): # macro + return (((x)&0x0000000F)<<28) +SDMA_PKT_SRBM_WRITE_ADDR_addr_offset = 1 # macro +SDMA_PKT_SRBM_WRITE_ADDR_addr_mask = 0x0003FFFF # macro +SDMA_PKT_SRBM_WRITE_ADDR_addr_shift = 0 # macro +def SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x): # macro + return (((x)&0x0003FFFF)<<0) +SDMA_PKT_SRBM_WRITE_DATA_data_offset = 2 # macro +SDMA_PKT_SRBM_WRITE_DATA_data_mask = 0xFFFFFFFF # macro +SDMA_PKT_SRBM_WRITE_DATA_data_shift = 0 # macro +def SDMA_PKT_SRBM_WRITE_DATA_DATA(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PRE_EXE_HEADER_op_offset = 0 # macro +SDMA_PKT_PRE_EXE_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_PRE_EXE_HEADER_op_shift = 0 # macro +def SDMA_PKT_PRE_EXE_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_PRE_EXE_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_PRE_EXE_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_PRE_EXE_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset = 0 # macro +SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask = 0x000000FF # macro +SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift = 16 # macro +def SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x): # macro + return (((x)&0x000000FF)<<16) +SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset = 1 # macro +SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro +SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift = 0 # macro +def SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COND_EXE_HEADER_op_offset = 0 # macro +SDMA_PKT_COND_EXE_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COND_EXE_HEADER_op_shift = 0 # macro +def SDMA_PKT_COND_EXE_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COND_EXE_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COND_EXE_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COND_EXE_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COND_EXE_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COND_EXE_REFERENCE_reference_offset = 3 # macro +SDMA_PKT_COND_EXE_REFERENCE_reference_mask = 0xFFFFFFFF # macro +SDMA_PKT_COND_EXE_REFERENCE_reference_shift = 0 # macro +def SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset = 4 # macro +SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro +SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift = 0 # macro +def SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_CONSTANT_FILL_HEADER_op_offset = 0 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_CONSTANT_FILL_HEADER_op_shift = 0 # macro +def SDMA_PKT_CONSTANT_FILL_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset = 0 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask = 0x00000003 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift = 16 # macro +def SDMA_PKT_CONSTANT_FILL_HEADER_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset = 0 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask = 0x00000003 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift = 30 # macro +def SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x): # macro + return (((x)&0x00000003)<<30) +SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro +SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro +SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset = 3 # macro +SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift = 0 # macro +def SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_CONSTANT_FILL_COUNT_count_offset = 4 # macro +SDMA_PKT_CONSTANT_FILL_COUNT_count_mask = 0x003FFFFF # macro +SDMA_PKT_CONSTANT_FILL_COUNT_count_shift = 0 # macro +def SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x): # macro + return (((x)&0x003FFFFF)<<0) +SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset = 0 # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift = 0 # macro +def SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset = 0 # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask = 0x00000001 # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift = 31 # macro +def SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset = 1 # macro +SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask = 0xFFFFFFFF # macro +SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift = 0 # macro +def SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset = 2 # macro +SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask = 0xFFFFFFFF # macro +SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift = 0 # macro +def SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset = 5 # macro +SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask = 0x03FFFFFF # macro +SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift = 0 # macro +def SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x): # macro + return (((x)&0x03FFFFFF)<<0) +SDMA_PKT_POLL_REGMEM_HEADER_op_offset = 0 # macro +SDMA_PKT_POLL_REGMEM_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_REGMEM_HEADER_op_shift = 0 # macro +def SDMA_PKT_POLL_REGMEM_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset = 0 # macro +SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask = 0x00000001 # macro +SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift = 26 # macro +def SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x): # macro + return (((x)&0x00000001)<<26) +SDMA_PKT_POLL_REGMEM_HEADER_func_offset = 0 # macro +SDMA_PKT_POLL_REGMEM_HEADER_func_mask = 0x00000007 # macro +SDMA_PKT_POLL_REGMEM_HEADER_func_shift = 28 # macro +def SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x): # macro + return (((x)&0x00000007)<<28) +SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset = 0 # macro +SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask = 0x00000001 # macro +SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift = 31 # macro +def SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_REGMEM_VALUE_value_offset = 3 # macro +SDMA_PKT_POLL_REGMEM_VALUE_value_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_REGMEM_VALUE_value_shift = 0 # macro +def SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_REGMEM_MASK_mask_offset = 4 # macro +SDMA_PKT_POLL_REGMEM_MASK_mask_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_REGMEM_MASK_mask_shift = 0 # macro +def SDMA_PKT_POLL_REGMEM_MASK_MASK(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_REGMEM_DW5_interval_offset = 5 # macro +SDMA_PKT_POLL_REGMEM_DW5_interval_mask = 0x0000FFFF # macro +SDMA_PKT_POLL_REGMEM_DW5_interval_shift = 0 # macro +def SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x): # macro + return (((x)&0x0000FFFF)<<0) +SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset = 5 # macro +SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask = 0x00000FFF # macro +SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift = 16 # macro +def SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x): # macro + return (((x)&0x00000FFF)<<16) +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset = 0 # macro +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift = 0 # macro +def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset = 1 # macro +SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask = 0x3FFFFFFF # macro +SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift = 2 # macro +def SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x): # macro + return (((x)&0x3FFFFFFF)<<2) +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 2 # macro +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 3 # macro +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset = 0 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift = 0 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset = 0 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask = 0x00000003 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift = 16 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset = 3 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask = 0x0FFFFFFF # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift = 4 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x): # macro + return (((x)&0x0FFFFFFF)<<4) +SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset = 4 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift = 0 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset = 0 # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset = 0 # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask = 0x00000001 # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift = 31 # macro +def SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset = 1 # macro +SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset = 2 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset = 3 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset = 4 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset = 5 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset = 6 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset = 7 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset = 8 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset = 9 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset = 10 # macro +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset = 11 # macro +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset = 12 # macro +SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_ATOMIC_HEADER_op_offset = 0 # macro +SDMA_PKT_ATOMIC_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_ATOMIC_HEADER_op_shift = 0 # macro +def SDMA_PKT_ATOMIC_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_ATOMIC_HEADER_loop_offset = 0 # macro +SDMA_PKT_ATOMIC_HEADER_loop_mask = 0x00000001 # macro +SDMA_PKT_ATOMIC_HEADER_loop_shift = 16 # macro +def SDMA_PKT_ATOMIC_HEADER_LOOP(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_ATOMIC_HEADER_tmz_offset = 0 # macro +SDMA_PKT_ATOMIC_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_ATOMIC_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_ATOMIC_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_ATOMIC_HEADER_atomic_op_offset = 0 # macro +SDMA_PKT_ATOMIC_HEADER_atomic_op_mask = 0x0000007F # macro +SDMA_PKT_ATOMIC_HEADER_atomic_op_shift = 25 # macro +def SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x): # macro + return (((x)&0x0000007F)<<25) +SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset = 3 # macro +SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift = 0 # macro +def SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset = 4 # macro +SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift = 0 # macro +def SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset = 5 # macro +SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift = 0 # macro +def SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset = 6 # macro +SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift = 0 # macro +def SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset = 7 # macro +SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask = 0x00001FFF # macro +SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift = 0 # macro +def SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x): # macro + return (((x)&0x00001FFF)<<0) +SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset = 0 # macro +SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift = 0 # macro +def SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset = 1 # macro +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift = 0 # macro +def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset = 2 # macro +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift = 0 # macro +def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset = 0 # macro +SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift = 0 # macro +def SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro +def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro + return (((x)&0x1FFFFFFF)<<3) +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro +def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset = 0 # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift = 0 # macro +def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro +def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro + return (((x)&0x1FFFFFFF)<<3) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro +def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_TRAP_HEADER_op_offset = 0 # macro +SDMA_PKT_TRAP_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_TRAP_HEADER_op_shift = 0 # macro +def SDMA_PKT_TRAP_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_TRAP_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_TRAP_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_TRAP_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_TRAP_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset = 1 # macro +SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro +SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift = 0 # macro +def SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro + return (((x)&0x0FFFFFFF)<<0) +SDMA_PKT_DUMMY_TRAP_HEADER_op_offset = 0 # macro +SDMA_PKT_DUMMY_TRAP_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_DUMMY_TRAP_HEADER_op_shift = 0 # macro +def SDMA_PKT_DUMMY_TRAP_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset = 1 # macro +SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro +SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift = 0 # macro +def SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro + return (((x)&0x0FFFFFFF)<<0) +SDMA_PKT_NOP_HEADER_op_offset = 0 # macro +SDMA_PKT_NOP_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_NOP_HEADER_op_shift = 0 # macro +def SDMA_PKT_NOP_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_NOP_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_NOP_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_NOP_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_NOP_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_NOP_HEADER_count_offset = 0 # macro +SDMA_PKT_NOP_HEADER_count_mask = 0x00003FFF # macro +SDMA_PKT_NOP_HEADER_count_shift = 16 # macro +def SDMA_PKT_NOP_HEADER_COUNT(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_NOP_DATA0_data0_offset = 1 # macro +SDMA_PKT_NOP_DATA0_data0_mask = 0xFFFFFFFF # macro +SDMA_PKT_NOP_DATA0_data0_shift = 0 # macro +def SDMA_PKT_NOP_DATA0_DATA0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_HEADER_HEADER_format_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_format_mask = 0x000000FF # macro +SDMA_AQL_PKT_HEADER_HEADER_format_shift = 0 # macro +def SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_AQL_PKT_HEADER_HEADER_barrier_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_barrier_mask = 0x00000001 # macro +SDMA_AQL_PKT_HEADER_HEADER_barrier_shift = 8 # macro +def SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x): # macro + return (((x)&0x00000001)<<8) +SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask = 0x00000003 # macro +SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift = 9 # macro +def SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro + return (((x)&0x00000003)<<9) +SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask = 0x00000003 # macro +SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift = 11 # macro +def SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x): # macro + return (((x)&0x00000003)<<11) +SDMA_AQL_PKT_HEADER_HEADER_reserved_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_reserved_mask = 0x00000007 # macro +SDMA_AQL_PKT_HEADER_HEADER_reserved_shift = 13 # macro +def SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x): # macro + return (((x)&0x00000007)<<13) +SDMA_AQL_PKT_HEADER_HEADER_op_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_op_mask = 0x0000000F # macro +SDMA_AQL_PKT_HEADER_HEADER_op_shift = 16 # macro +def SDMA_AQL_PKT_HEADER_HEADER_OP(x): # macro + return (((x)&0x0000000F)<<16) +SDMA_AQL_PKT_HEADER_HEADER_subop_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_subop_mask = 0x00000007 # macro +SDMA_AQL_PKT_HEADER_HEADER_subop_shift = 20 # macro +def SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x): # macro + return (((x)&0x00000007)<<20) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask = 0x000000FF # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask = 0x00000001 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift = 8 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x): # macro + return (((x)&0x00000001)<<8) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift = 9 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro + return (((x)&0x00000003)<<9) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask = 0x00000003 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift = 11 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x): # macro + return (((x)&0x00000003)<<11) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask = 0x00000007 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift = 13 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x): # macro + return (((x)&0x00000007)<<13) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask = 0x0000000F # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift = 16 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x): # macro + return (((x)&0x0000000F)<<16) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask = 0x00000007 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift = 20 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x): # macro + return (((x)&0x00000007)<<20) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset = 1 # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset = 2 # macro +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset = 3 # macro +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset = 4 # macro +SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro + return (((x)&0x003FFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 5 # macro +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro +def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 5 # macro +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro +def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 6 # macro +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 7 # macro +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 8 # macro +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 9 # macro +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset = 10 # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset = 11 # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset = 12 # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset = 13 # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask = 0x000000FF # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask = 0x00000001 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift = 8 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x): # macro + return (((x)&0x00000001)<<8) +SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift = 9 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro + return (((x)&0x00000003)<<9) +SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask = 0x00000003 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift = 11 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x): # macro + return (((x)&0x00000003)<<11) +SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask = 0x00000007 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift = 13 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x): # macro + return (((x)&0x00000007)<<13) +SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask = 0x0000000F # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift = 16 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x): # macro + return (((x)&0x0000000F)<<16) +SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask = 0x00000007 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift = 20 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x): # macro + return (((x)&0x00000007)<<20) +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset = 1 # macro +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset = 2 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset = 3 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset = 4 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset = 5 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset = 6 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset = 7 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset = 8 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset = 9 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset = 10 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset = 11 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset = 12 # macro +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset = 13 # macro +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +__all__ = \ + ['HEADER_AGENT_DISPATCH', 'HEADER_BARRIER', + 'HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_', + 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', + 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', + 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', + 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', + 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', + 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_barrier_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_barrier_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_barrier_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_format_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_format_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_format_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_op_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_op_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_op_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_reserved_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_reserved_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_reserved_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_subop_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_subop_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_subop_shift', 'SDMA_ATOMIC_ADD64', + 'SDMA_OP_AQL_BARRIER_OR', 'SDMA_OP_AQL_COPY', 'SDMA_OP_ATOMIC', + 'SDMA_OP_COND_EXE', 'SDMA_OP_CONST_FILL', 'SDMA_OP_COPY', + 'SDMA_OP_DUMMY_TRAP', 'SDMA_OP_FENCE', 'SDMA_OP_GCR', + 'SDMA_OP_INDIRECT', 'SDMA_OP_NOP', 'SDMA_OP_POLL_REGMEM', + 'SDMA_OP_PRE_EXE', 'SDMA_OP_PTEPDE', 'SDMA_OP_SEM', + 'SDMA_OP_SRBM_WRITE', 'SDMA_OP_TIMESTAMP', 'SDMA_OP_TRAP', + 'SDMA_OP_WRITE', 'SDMA_PKT_ATOMIC', + 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask', + 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset', + 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift', + 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask', + 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset', + 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift', + 'SDMA_PKT_ATOMIC_HEADER_atomic_op_mask', + 'SDMA_PKT_ATOMIC_HEADER_atomic_op_offset', + 'SDMA_PKT_ATOMIC_HEADER_atomic_op_shift', + 'SDMA_PKT_ATOMIC_HEADER_loop_mask', + 'SDMA_PKT_ATOMIC_HEADER_loop_offset', + 'SDMA_PKT_ATOMIC_HEADER_loop_shift', + 'SDMA_PKT_ATOMIC_HEADER_op_mask', + 'SDMA_PKT_ATOMIC_HEADER_op_offset', + 'SDMA_PKT_ATOMIC_HEADER_op_shift', + 'SDMA_PKT_ATOMIC_HEADER_tmz_mask', + 'SDMA_PKT_ATOMIC_HEADER_tmz_offset', + 'SDMA_PKT_ATOMIC_HEADER_tmz_shift', + 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask', + 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset', + 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift', + 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask', + 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset', + 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift', + 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask', + 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset', + 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift', + 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask', + 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset', + 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift', + 'SDMA_PKT_COND_EXE_HEADER_op_mask', + 'SDMA_PKT_COND_EXE_HEADER_op_offset', + 'SDMA_PKT_COND_EXE_HEADER_op_shift', + 'SDMA_PKT_COND_EXE_HEADER_sub_op_mask', + 'SDMA_PKT_COND_EXE_HEADER_sub_op_offset', + 'SDMA_PKT_COND_EXE_HEADER_sub_op_shift', + 'SDMA_PKT_COND_EXE_REFERENCE_reference_mask', + 'SDMA_PKT_COND_EXE_REFERENCE_reference_offset', + 'SDMA_PKT_COND_EXE_REFERENCE_reference_shift', + 'SDMA_PKT_CONSTANT_FILL', + 'SDMA_PKT_CONSTANT_FILL_COUNT_count_mask', + 'SDMA_PKT_CONSTANT_FILL_COUNT_count_offset', + 'SDMA_PKT_CONSTANT_FILL_COUNT_count_shift', + 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask', + 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset', + 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift', + 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask', + 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset', + 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift', + 'SDMA_PKT_CONSTANT_FILL_HEADER_op_mask', + 'SDMA_PKT_CONSTANT_FILL_HEADER_op_offset', + 'SDMA_PKT_CONSTANT_FILL_HEADER_op_shift', + 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask', + 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset', + 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift', + 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask', + 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset', + 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift', + 'SDMA_PKT_COPY_LINEAR', 'SDMA_PKT_COPY_LINEAR_COUNT_count_mask', + 'SDMA_PKT_COPY_LINEAR_COUNT_count_offset', + 'SDMA_PKT_COPY_LINEAR_COUNT_count_shift', + 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask', + 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset', + 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift', + 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask', + 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset', + 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift', + 'SDMA_PKT_COPY_LINEAR_HEADER_op_mask', + 'SDMA_PKT_COPY_LINEAR_HEADER_op_offset', + 'SDMA_PKT_COPY_LINEAR_HEADER_op_shift', + 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask', + 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset', + 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', + 'SDMA_PKT_COPY_LINEAR_RECT', + 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_STRUCT_COUNT_count_mask', + 'SDMA_PKT_COPY_STRUCT_COUNT_count_offset', + 'SDMA_PKT_COPY_STRUCT_COUNT_count_shift', + 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask', + 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset', + 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift', + 'SDMA_PKT_COPY_STRUCT_DW_5_stride_mask', + 'SDMA_PKT_COPY_STRUCT_DW_5_stride_offset', + 'SDMA_PKT_COPY_STRUCT_DW_5_stride_shift', + 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask', + 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset', + 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift', + 'SDMA_PKT_COPY_STRUCT_HEADER_detile_mask', + 'SDMA_PKT_COPY_STRUCT_HEADER_detile_offset', + 'SDMA_PKT_COPY_STRUCT_HEADER_detile_shift', + 'SDMA_PKT_COPY_STRUCT_HEADER_op_mask', + 'SDMA_PKT_COPY_STRUCT_HEADER_op_offset', + 'SDMA_PKT_COPY_STRUCT_HEADER_op_shift', + 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask', + 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset', + 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift', + 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask', + 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset', + 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift', + 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask', + 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset', + 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift', + 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask', + 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset', + 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift', + 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask', + 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset', + 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift', + 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask', + 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset', + 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift', + 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_COPY_T2T_DW_10_dst_width_mask', + 'SDMA_PKT_COPY_T2T_DW_10_dst_width_offset', + 'SDMA_PKT_COPY_T2T_DW_10_dst_width_shift', + 'SDMA_PKT_COPY_T2T_DW_10_dst_z_mask', + 'SDMA_PKT_COPY_T2T_DW_10_dst_z_offset', + 'SDMA_PKT_COPY_T2T_DW_10_dst_z_shift', + 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask', + 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset', + 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift', + 'SDMA_PKT_COPY_T2T_DW_11_dst_height_mask', + 'SDMA_PKT_COPY_T2T_DW_11_dst_height_offset', + 'SDMA_PKT_COPY_T2T_DW_11_dst_height_shift', + 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask', + 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset', + 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift', + 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask', + 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset', + 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift', + 'SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask', + 'SDMA_PKT_COPY_T2T_DW_12_dst_epitch_offset', + 'SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift', + 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask', + 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset', + 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift', + 'SDMA_PKT_COPY_T2T_DW_13_rect_x_mask', + 'SDMA_PKT_COPY_T2T_DW_13_rect_x_offset', + 'SDMA_PKT_COPY_T2T_DW_13_rect_x_shift', + 'SDMA_PKT_COPY_T2T_DW_13_rect_y_mask', + 'SDMA_PKT_COPY_T2T_DW_13_rect_y_offset', + 'SDMA_PKT_COPY_T2T_DW_13_rect_y_shift', + 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask', + 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset', + 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift', + 'SDMA_PKT_COPY_T2T_DW_14_rect_z_mask', + 'SDMA_PKT_COPY_T2T_DW_14_rect_z_offset', + 'SDMA_PKT_COPY_T2T_DW_14_rect_z_shift', + 'SDMA_PKT_COPY_T2T_DW_14_src_sw_mask', + 'SDMA_PKT_COPY_T2T_DW_14_src_sw_offset', + 'SDMA_PKT_COPY_T2T_DW_14_src_sw_shift', + 'SDMA_PKT_COPY_T2T_DW_3_src_x_mask', + 'SDMA_PKT_COPY_T2T_DW_3_src_x_offset', + 'SDMA_PKT_COPY_T2T_DW_3_src_x_shift', + 'SDMA_PKT_COPY_T2T_DW_3_src_y_mask', + 'SDMA_PKT_COPY_T2T_DW_3_src_y_offset', + 'SDMA_PKT_COPY_T2T_DW_3_src_y_shift', + 'SDMA_PKT_COPY_T2T_DW_4_src_width_mask', + 'SDMA_PKT_COPY_T2T_DW_4_src_width_offset', + 'SDMA_PKT_COPY_T2T_DW_4_src_width_shift', + 'SDMA_PKT_COPY_T2T_DW_4_src_z_mask', + 'SDMA_PKT_COPY_T2T_DW_4_src_z_offset', + 'SDMA_PKT_COPY_T2T_DW_4_src_z_shift', + 'SDMA_PKT_COPY_T2T_DW_5_src_depth_mask', + 'SDMA_PKT_COPY_T2T_DW_5_src_depth_offset', + 'SDMA_PKT_COPY_T2T_DW_5_src_depth_shift', + 'SDMA_PKT_COPY_T2T_DW_5_src_height_mask', + 'SDMA_PKT_COPY_T2T_DW_5_src_height_offset', + 'SDMA_PKT_COPY_T2T_DW_5_src_height_shift', + 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask', + 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset', + 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift', + 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask', + 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset', + 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift', + 'SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask', + 'SDMA_PKT_COPY_T2T_DW_6_src_epitch_offset', + 'SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift', + 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask', + 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset', + 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift', + 'SDMA_PKT_COPY_T2T_DW_9_dst_x_mask', + 'SDMA_PKT_COPY_T2T_DW_9_dst_x_offset', + 'SDMA_PKT_COPY_T2T_DW_9_dst_x_shift', + 'SDMA_PKT_COPY_T2T_DW_9_dst_y_mask', + 'SDMA_PKT_COPY_T2T_DW_9_dst_y_offset', + 'SDMA_PKT_COPY_T2T_DW_9_dst_y_shift', + 'SDMA_PKT_COPY_T2T_HEADER_mip_max_mask', + 'SDMA_PKT_COPY_T2T_HEADER_mip_max_offset', + 'SDMA_PKT_COPY_T2T_HEADER_mip_max_shift', + 'SDMA_PKT_COPY_T2T_HEADER_op_mask', + 'SDMA_PKT_COPY_T2T_HEADER_op_offset', + 'SDMA_PKT_COPY_T2T_HEADER_op_shift', + 'SDMA_PKT_COPY_T2T_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_T2T_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_T2T_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_T2T_HEADER_tmz_mask', + 'SDMA_PKT_COPY_T2T_HEADER_tmz_offset', + 'SDMA_PKT_COPY_T2T_HEADER_tmz_shift', + 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_TILED_COUNT_count_mask', + 'SDMA_PKT_COPY_TILED_COUNT_count_offset', + 'SDMA_PKT_COPY_TILED_COUNT_count_shift', + 'SDMA_PKT_COPY_TILED_DW_3_width_mask', + 'SDMA_PKT_COPY_TILED_DW_3_width_offset', + 'SDMA_PKT_COPY_TILED_DW_3_width_shift', + 'SDMA_PKT_COPY_TILED_DW_4_depth_mask', + 'SDMA_PKT_COPY_TILED_DW_4_depth_offset', + 'SDMA_PKT_COPY_TILED_DW_4_depth_shift', + 'SDMA_PKT_COPY_TILED_DW_4_height_mask', + 'SDMA_PKT_COPY_TILED_DW_4_height_offset', + 'SDMA_PKT_COPY_TILED_DW_4_height_shift', + 'SDMA_PKT_COPY_TILED_DW_5_dimension_mask', + 'SDMA_PKT_COPY_TILED_DW_5_dimension_offset', + 'SDMA_PKT_COPY_TILED_DW_5_dimension_shift', + 'SDMA_PKT_COPY_TILED_DW_5_element_size_mask', + 'SDMA_PKT_COPY_TILED_DW_5_element_size_offset', + 'SDMA_PKT_COPY_TILED_DW_5_element_size_shift', + 'SDMA_PKT_COPY_TILED_DW_5_epitch_mask', + 'SDMA_PKT_COPY_TILED_DW_5_epitch_offset', + 'SDMA_PKT_COPY_TILED_DW_5_epitch_shift', + 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask', + 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset', + 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift', + 'SDMA_PKT_COPY_TILED_DW_6_x_mask', + 'SDMA_PKT_COPY_TILED_DW_6_x_offset', + 'SDMA_PKT_COPY_TILED_DW_6_x_shift', + 'SDMA_PKT_COPY_TILED_DW_6_y_mask', + 'SDMA_PKT_COPY_TILED_DW_6_y_offset', + 'SDMA_PKT_COPY_TILED_DW_6_y_shift', + 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask', + 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset', + 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift', + 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask', + 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset', + 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift', + 'SDMA_PKT_COPY_TILED_DW_7_z_mask', + 'SDMA_PKT_COPY_TILED_DW_7_z_offset', + 'SDMA_PKT_COPY_TILED_DW_7_z_shift', + 'SDMA_PKT_COPY_TILED_HEADER_detile_mask', + 'SDMA_PKT_COPY_TILED_HEADER_detile_offset', + 'SDMA_PKT_COPY_TILED_HEADER_detile_shift', + 'SDMA_PKT_COPY_TILED_HEADER_encrypt_mask', + 'SDMA_PKT_COPY_TILED_HEADER_encrypt_offset', + 'SDMA_PKT_COPY_TILED_HEADER_encrypt_shift', + 'SDMA_PKT_COPY_TILED_HEADER_mip_max_mask', + 'SDMA_PKT_COPY_TILED_HEADER_mip_max_offset', + 'SDMA_PKT_COPY_TILED_HEADER_mip_max_shift', + 'SDMA_PKT_COPY_TILED_HEADER_op_mask', + 'SDMA_PKT_COPY_TILED_HEADER_op_offset', + 'SDMA_PKT_COPY_TILED_HEADER_op_shift', + 'SDMA_PKT_COPY_TILED_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_TILED_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_TILED_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_TILED_HEADER_tmz_mask', + 'SDMA_PKT_COPY_TILED_HEADER_tmz_offset', + 'SDMA_PKT_COPY_TILED_HEADER_tmz_shift', + 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask', + 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset', + 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift', + 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask', + 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset', + 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift', + 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask', + 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset', + 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift', + 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', + 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', + 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift', + 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask', + 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset', + 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift', + 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask', + 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset', + 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift', + 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask', + 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset', + 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift', + 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask', + 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset', + 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift', + 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask', + 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset', + 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift', + 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift', + 'SDMA_PKT_DUMMY_TRAP_HEADER_op_mask', + 'SDMA_PKT_DUMMY_TRAP_HEADER_op_offset', + 'SDMA_PKT_DUMMY_TRAP_HEADER_op_shift', + 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask', + 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset', + 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift', + 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask', + 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset', + 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift', + 'SDMA_PKT_FENCE', 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_FENCE_DATA_data_mask', + 'SDMA_PKT_FENCE_DATA_data_offset', + 'SDMA_PKT_FENCE_DATA_data_shift', 'SDMA_PKT_FENCE_HEADER_op_mask', + 'SDMA_PKT_FENCE_HEADER_op_offset', + 'SDMA_PKT_FENCE_HEADER_op_shift', + 'SDMA_PKT_FENCE_HEADER_sub_op_mask', + 'SDMA_PKT_FENCE_HEADER_sub_op_offset', + 'SDMA_PKT_FENCE_HEADER_sub_op_shift', 'SDMA_PKT_GCR', + 'SDMA_PKT_HDP_FLUSH', 'SDMA_PKT_HEADER_op_mask', + 'SDMA_PKT_HEADER_op_offset', 'SDMA_PKT_HEADER_op_shift', + 'SDMA_PKT_HEADER_sub_op_mask', 'SDMA_PKT_HEADER_sub_op_offset', + 'SDMA_PKT_HEADER_sub_op_shift', + 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask', + 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset', + 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift', + 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask', + 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset', + 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift', + 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask', + 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset', + 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift', + 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask', + 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset', + 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift', + 'SDMA_PKT_INDIRECT_HEADER_op_mask', + 'SDMA_PKT_INDIRECT_HEADER_op_offset', + 'SDMA_PKT_INDIRECT_HEADER_op_shift', + 'SDMA_PKT_INDIRECT_HEADER_sub_op_mask', + 'SDMA_PKT_INDIRECT_HEADER_sub_op_offset', + 'SDMA_PKT_INDIRECT_HEADER_sub_op_shift', + 'SDMA_PKT_INDIRECT_HEADER_vmid_mask', + 'SDMA_PKT_INDIRECT_HEADER_vmid_offset', + 'SDMA_PKT_INDIRECT_HEADER_vmid_shift', + 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask', + 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset', + 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift', + 'SDMA_PKT_NOP_DATA0_data0_mask', + 'SDMA_PKT_NOP_DATA0_data0_offset', + 'SDMA_PKT_NOP_DATA0_data0_shift', + 'SDMA_PKT_NOP_HEADER_count_mask', + 'SDMA_PKT_NOP_HEADER_count_offset', + 'SDMA_PKT_NOP_HEADER_count_shift', 'SDMA_PKT_NOP_HEADER_op_mask', + 'SDMA_PKT_NOP_HEADER_op_offset', 'SDMA_PKT_NOP_HEADER_op_shift', + 'SDMA_PKT_NOP_HEADER_sub_op_mask', + 'SDMA_PKT_NOP_HEADER_sub_op_offset', + 'SDMA_PKT_NOP_HEADER_sub_op_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift', + 'SDMA_PKT_POLL_REGMEM', + 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_POLL_REGMEM_DW5_interval_mask', + 'SDMA_PKT_POLL_REGMEM_DW5_interval_offset', + 'SDMA_PKT_POLL_REGMEM_DW5_interval_shift', + 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask', + 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset', + 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift', + 'SDMA_PKT_POLL_REGMEM_HEADER_func_mask', + 'SDMA_PKT_POLL_REGMEM_HEADER_func_offset', + 'SDMA_PKT_POLL_REGMEM_HEADER_func_shift', + 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask', + 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset', + 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift', + 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask', + 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset', + 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift', + 'SDMA_PKT_POLL_REGMEM_HEADER_op_mask', + 'SDMA_PKT_POLL_REGMEM_HEADER_op_offset', + 'SDMA_PKT_POLL_REGMEM_HEADER_op_shift', + 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask', + 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset', + 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift', + 'SDMA_PKT_POLL_REGMEM_MASK_mask_mask', + 'SDMA_PKT_POLL_REGMEM_MASK_mask_offset', + 'SDMA_PKT_POLL_REGMEM_MASK_mask_shift', + 'SDMA_PKT_POLL_REGMEM_VALUE_value_mask', + 'SDMA_PKT_POLL_REGMEM_VALUE_value_offset', + 'SDMA_PKT_POLL_REGMEM_VALUE_value_shift', + 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift', + 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask', + 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset', + 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift', + 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask', + 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset', + 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift', + 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask', + 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset', + 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift', + 'SDMA_PKT_PRE_EXE_HEADER_op_mask', + 'SDMA_PKT_PRE_EXE_HEADER_op_offset', + 'SDMA_PKT_PRE_EXE_HEADER_op_shift', + 'SDMA_PKT_PRE_EXE_HEADER_sub_op_mask', + 'SDMA_PKT_PRE_EXE_HEADER_sub_op_offset', + 'SDMA_PKT_PRE_EXE_HEADER_sub_op_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_PTEPDE_COPY_COUNT_count_mask', + 'SDMA_PKT_PTEPDE_COPY_COUNT_count_offset', + 'SDMA_PKT_PTEPDE_COPY_COUNT_count_shift', + 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_PTEPDE_COPY_HEADER_op_mask', + 'SDMA_PKT_PTEPDE_COPY_HEADER_op_offset', + 'SDMA_PKT_PTEPDE_COPY_HEADER_op_shift', + 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask', + 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset', + 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift', + 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask', + 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset', + 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift', + 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask', + 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset', + 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift', + 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask', + 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset', + 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift', + 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_op_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_op_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_op_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift', + 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask', + 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset', + 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift', + 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask', + 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset', + 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift', + 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask', + 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset', + 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift', + 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask', + 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset', + 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift', + 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask', + 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset', + 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift', + 'SDMA_PKT_SEMAPHORE_HEADER_op_mask', + 'SDMA_PKT_SEMAPHORE_HEADER_op_offset', + 'SDMA_PKT_SEMAPHORE_HEADER_op_shift', + 'SDMA_PKT_SEMAPHORE_HEADER_signal_mask', + 'SDMA_PKT_SEMAPHORE_HEADER_signal_offset', + 'SDMA_PKT_SEMAPHORE_HEADER_signal_shift', + 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask', + 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset', + 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift', + 'SDMA_PKT_SEMAPHORE_HEADER_write_one_mask', + 'SDMA_PKT_SEMAPHORE_HEADER_write_one_offset', + 'SDMA_PKT_SEMAPHORE_HEADER_write_one_shift', + 'SDMA_PKT_SRBM_WRITE_ADDR_addr_mask', + 'SDMA_PKT_SRBM_WRITE_ADDR_addr_offset', + 'SDMA_PKT_SRBM_WRITE_ADDR_addr_shift', + 'SDMA_PKT_SRBM_WRITE_DATA_data_mask', + 'SDMA_PKT_SRBM_WRITE_DATA_data_offset', + 'SDMA_PKT_SRBM_WRITE_DATA_data_shift', + 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask', + 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset', + 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift', + 'SDMA_PKT_SRBM_WRITE_HEADER_op_mask', + 'SDMA_PKT_SRBM_WRITE_HEADER_op_offset', + 'SDMA_PKT_SRBM_WRITE_HEADER_op_shift', + 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask', + 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset', + 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift', 'SDMA_PKT_TIMESTAMP', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift', + 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask', + 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset', + 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift', + 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask', + 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset', + 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift', + 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask', + 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset', + 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift', + 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask', + 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset', + 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift', + 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask', + 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset', + 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift', + 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask', + 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset', + 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift', + 'SDMA_PKT_TRAP', 'SDMA_PKT_TRAP_HEADER_op_mask', + 'SDMA_PKT_TRAP_HEADER_op_offset', 'SDMA_PKT_TRAP_HEADER_op_shift', + 'SDMA_PKT_TRAP_HEADER_sub_op_mask', + 'SDMA_PKT_TRAP_HEADER_sub_op_offset', + 'SDMA_PKT_TRAP_HEADER_sub_op_shift', + 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask', + 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset', + 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift', + 'SDMA_PKT_WRITE_INCR_COUNT_count_mask', + 'SDMA_PKT_WRITE_INCR_COUNT_count_offset', + 'SDMA_PKT_WRITE_INCR_COUNT_count_shift', + 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_WRITE_INCR_HEADER_op_mask', + 'SDMA_PKT_WRITE_INCR_HEADER_op_offset', + 'SDMA_PKT_WRITE_INCR_HEADER_op_shift', + 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask', + 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset', + 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift', + 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask', + 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset', + 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift', + 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask', + 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset', + 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift', + 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask', + 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset', + 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift', + 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask', + 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset', + 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift', + 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask', + 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset', + 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift', + 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask', + 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset', + 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift', + 'SDMA_PKT_WRITE_TILED_COUNT_count_mask', + 'SDMA_PKT_WRITE_TILED_COUNT_count_offset', + 'SDMA_PKT_WRITE_TILED_COUNT_count_shift', + 'SDMA_PKT_WRITE_TILED_DATA0_data0_mask', + 'SDMA_PKT_WRITE_TILED_DATA0_data0_offset', + 'SDMA_PKT_WRITE_TILED_DATA0_data0_shift', + 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_WRITE_TILED_DW_3_width_mask', + 'SDMA_PKT_WRITE_TILED_DW_3_width_offset', + 'SDMA_PKT_WRITE_TILED_DW_3_width_shift', + 'SDMA_PKT_WRITE_TILED_DW_4_depth_mask', + 'SDMA_PKT_WRITE_TILED_DW_4_depth_offset', + 'SDMA_PKT_WRITE_TILED_DW_4_depth_shift', + 'SDMA_PKT_WRITE_TILED_DW_4_height_mask', + 'SDMA_PKT_WRITE_TILED_DW_4_height_offset', + 'SDMA_PKT_WRITE_TILED_DW_4_height_shift', + 'SDMA_PKT_WRITE_TILED_DW_5_dimension_mask', + 'SDMA_PKT_WRITE_TILED_DW_5_dimension_offset', + 'SDMA_PKT_WRITE_TILED_DW_5_dimension_shift', + 'SDMA_PKT_WRITE_TILED_DW_5_element_size_mask', + 'SDMA_PKT_WRITE_TILED_DW_5_element_size_offset', + 'SDMA_PKT_WRITE_TILED_DW_5_element_size_shift', + 'SDMA_PKT_WRITE_TILED_DW_5_epitch_mask', + 'SDMA_PKT_WRITE_TILED_DW_5_epitch_offset', + 'SDMA_PKT_WRITE_TILED_DW_5_epitch_shift', + 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask', + 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset', + 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift', + 'SDMA_PKT_WRITE_TILED_DW_6_x_mask', + 'SDMA_PKT_WRITE_TILED_DW_6_x_offset', + 'SDMA_PKT_WRITE_TILED_DW_6_x_shift', + 'SDMA_PKT_WRITE_TILED_DW_6_y_mask', + 'SDMA_PKT_WRITE_TILED_DW_6_y_offset', + 'SDMA_PKT_WRITE_TILED_DW_6_y_shift', + 'SDMA_PKT_WRITE_TILED_DW_7_sw_mask', + 'SDMA_PKT_WRITE_TILED_DW_7_sw_offset', + 'SDMA_PKT_WRITE_TILED_DW_7_sw_shift', + 'SDMA_PKT_WRITE_TILED_DW_7_z_mask', + 'SDMA_PKT_WRITE_TILED_DW_7_z_offset', + 'SDMA_PKT_WRITE_TILED_DW_7_z_shift', + 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask', + 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset', + 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift', + 'SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask', + 'SDMA_PKT_WRITE_TILED_HEADER_mip_max_offset', + 'SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift', + 'SDMA_PKT_WRITE_TILED_HEADER_op_mask', + 'SDMA_PKT_WRITE_TILED_HEADER_op_offset', + 'SDMA_PKT_WRITE_TILED_HEADER_op_shift', + 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask', + 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset', + 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift', + 'SDMA_PKT_WRITE_TILED_HEADER_tmz_mask', + 'SDMA_PKT_WRITE_TILED_HEADER_tmz_offset', + 'SDMA_PKT_WRITE_TILED_HEADER_tmz_shift', + 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask', + 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset', + 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift', + 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_WRITE_UNTILED_DW_3_count_mask', + 'SDMA_PKT_WRITE_UNTILED_DW_3_count_offset', + 'SDMA_PKT_WRITE_UNTILED_DW_3_count_shift', + 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask', + 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset', + 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift', + 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask', + 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset', + 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift', + 'SDMA_PKT_WRITE_UNTILED_HEADER_op_mask', + 'SDMA_PKT_WRITE_UNTILED_HEADER_op_offset', + 'SDMA_PKT_WRITE_UNTILED_HEADER_op_shift', + 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask', + 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset', + 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift', + 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask', + 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset', + 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift', + 'SDMA_SUBOP_COPY_DIRTY_PAGE', 'SDMA_SUBOP_COPY_LINEAR', + 'SDMA_SUBOP_COPY_LINEAR_PHY', 'SDMA_SUBOP_COPY_LINEAR_RECT', + 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND', 'SDMA_SUBOP_COPY_SOA', + 'SDMA_SUBOP_COPY_T2T_SUB_WIND', 'SDMA_SUBOP_COPY_TILED', + 'SDMA_SUBOP_COPY_TILED_SUB_WIND', 'SDMA_SUBOP_DATA_FILL_MULTI', + 'SDMA_SUBOP_POLL_DBIT_WRITE_MEM', 'SDMA_SUBOP_POLL_MEM_VERIFY', + 'SDMA_SUBOP_POLL_REG_WRITE_MEM', 'SDMA_SUBOP_PTEPDE_COPY', + 'SDMA_SUBOP_PTEPDE_COPY_BACKWARDS', 'SDMA_SUBOP_PTEPDE_GEN', + 'SDMA_SUBOP_PTEPDE_RMW', 'SDMA_SUBOP_TIMESTAMP_GET', + 'SDMA_SUBOP_TIMESTAMP_GET_GLOBAL', 'SDMA_SUBOP_TIMESTAMP_SET', + 'SDMA_SUBOP_USER_GCR', 'SDMA_SUBOP_WRITE_LINEAR', + 'SDMA_SUBOP_WRITE_TILED', '__VEGA10_SDMA_PKT_OPEN_H_', + 'hdp_flush_cmd', 'struct_SDMA_PKT_ATOMIC_TAG', + 'struct_SDMA_PKT_ATOMIC_TAG_0_0', + 'struct_SDMA_PKT_ATOMIC_TAG_1_0', + 'struct_SDMA_PKT_ATOMIC_TAG_2_0', + 'struct_SDMA_PKT_ATOMIC_TAG_3_0', + 'struct_SDMA_PKT_ATOMIC_TAG_4_0', + 'struct_SDMA_PKT_ATOMIC_TAG_5_0', + 'struct_SDMA_PKT_ATOMIC_TAG_6_0', + 'struct_SDMA_PKT_ATOMIC_TAG_7_0', + 'struct_SDMA_PKT_CONSTANT_FILL_TAG', + 'struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0', + 'struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0', + 'struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0', + 'struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0', + 'struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0', + 'struct_SDMA_PKT_COPY_LINEAR_TAG', + 'struct_SDMA_PKT_COPY_LINEAR_TAG_0_0', + 'struct_SDMA_PKT_COPY_LINEAR_TAG_1_0', + 'struct_SDMA_PKT_COPY_LINEAR_TAG_2_0', + 'struct_SDMA_PKT_COPY_LINEAR_TAG_3_0', + 'struct_SDMA_PKT_COPY_LINEAR_TAG_4_0', + 'struct_SDMA_PKT_COPY_LINEAR_TAG_5_0', + 'struct_SDMA_PKT_COPY_LINEAR_TAG_6_0', + 'struct_SDMA_PKT_FENCE_TAG', 'struct_SDMA_PKT_FENCE_TAG_0_0', + 'struct_SDMA_PKT_FENCE_TAG_1_0', 'struct_SDMA_PKT_FENCE_TAG_2_0', + 'struct_SDMA_PKT_FENCE_TAG_3_0', 'struct_SDMA_PKT_GCR_TAG', + 'struct_SDMA_PKT_GCR_TAG_0_0', 'struct_SDMA_PKT_GCR_TAG_1_0', + 'struct_SDMA_PKT_GCR_TAG_2_0', 'struct_SDMA_PKT_GCR_TAG_3_0', + 'struct_SDMA_PKT_GCR_TAG_4_0', 'struct_SDMA_PKT_HDP_FLUSH_TAG', + 'struct_SDMA_PKT_POLL_REGMEM_TAG', + 'struct_SDMA_PKT_POLL_REGMEM_TAG_0_0', + 'struct_SDMA_PKT_POLL_REGMEM_TAG_1_0', + 'struct_SDMA_PKT_POLL_REGMEM_TAG_2_0', + 'struct_SDMA_PKT_POLL_REGMEM_TAG_3_0', + 'struct_SDMA_PKT_POLL_REGMEM_TAG_4_0', + 'struct_SDMA_PKT_POLL_REGMEM_TAG_5_0', + 'struct_SDMA_PKT_TIMESTAMP_TAG', + 'struct_SDMA_PKT_TIMESTAMP_TAG_0_0', + 'struct_SDMA_PKT_TIMESTAMP_TAG_1_0', + 'struct_SDMA_PKT_TIMESTAMP_TAG_2_0', 'struct_SDMA_PKT_TRAP_TAG', + 'struct_SDMA_PKT_TRAP_TAG_0_0', 'struct_SDMA_PKT_TRAP_TAG_1_0', + 'union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION', + 'union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION', + 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION', + 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION', + 'union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION', + 'union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION', + 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION', + 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION', + 'union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION', + 'union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION', + 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION', + 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION', + 'union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION', + 'union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION', + 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION', + 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION', + 'union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION', + 'union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION', + 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION', + 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION', + 'union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION', + 'union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION', + 'union_SDMA_PKT_FENCE_TAG_DATA_UNION', + 'union_SDMA_PKT_FENCE_TAG_HEADER_UNION', + 'union_SDMA_PKT_GCR_TAG_HEADER_UNION', + 'union_SDMA_PKT_GCR_TAG_WORD1_UNION', + 'union_SDMA_PKT_GCR_TAG_WORD2_UNION', + 'union_SDMA_PKT_GCR_TAG_WORD3_UNION', + 'union_SDMA_PKT_GCR_TAG_WORD4_UNION', + 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION', + 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION', + 'union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION', + 'union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION', + 'union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION', + 'union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION', + 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION', + 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION', + 'union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION', + 'union_SDMA_PKT_TRAP_TAG_HEADER_UNION', + 'union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION'] diff --git a/tinygrad/runtime/autogen/am/sdma_4_4_2.py b/tinygrad/runtime/autogen/am/sdma_4_4_2.py new file mode 100644 index 0000000000..a48adeed78 --- /dev/null +++ b/tinygrad/runtime/autogen/am/sdma_4_4_2.py @@ -0,0 +1,5209 @@ +# mypy: ignore-errors +# -*- coding: utf-8 -*- +# +# TARGET arch is: ['-I/opt/rocm/include', '-x', 'c++'] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes + + +class AsDictMixin: + @classmethod + def as_dict(cls, self): + result = {} + if not isinstance(self, AsDictMixin): + # not a structure, assume it's already a python object + return self + if not hasattr(cls, "_fields_"): + return result + # sys.version_info >= (3, 5) + # for (field, *_) in cls._fields_: # noqa + for field_tuple in cls._fields_: # noqa + field = field_tuple[0] + if field.startswith('PADDING_'): + continue + value = getattr(self, field) + type_ = type(value) + if hasattr(value, "_length_") and hasattr(value, "_type_"): + # array + if not hasattr(type_, "as_dict"): + value = [v for v in value] + else: + type_ = type_._type_ + value = [type_.as_dict(v) for v in value] + elif hasattr(value, "contents") and hasattr(value, "_type_"): + # pointer + try: + if not hasattr(type_, "as_dict"): + value = value.contents + else: + type_ = type_._type_ + value = type_.as_dict(value.contents) + except ValueError: + # nullptr + value = None + elif isinstance(value, AsDictMixin): + # other structure + value = type_.as_dict(value) + result[field] = value + return result + + +class Structure(ctypes.Structure, AsDictMixin): + + def __init__(self, *args, **kwds): + # We don't want to use positional arguments fill PADDING_* fields + + args = dict(zip(self.__class__._field_names_(), args)) + args.update(kwds) + super(Structure, self).__init__(**args) + + @classmethod + def _field_names_(cls): + if hasattr(cls, '_fields_'): + return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) + else: + return () + + @classmethod + def get_type(cls, field): + for f in cls._fields_: + if f[0] == field: + return f[1] + return None + + @classmethod + def bind(cls, bound_fields): + fields = {} + for name, type_ in cls._fields_: + if hasattr(type_, "restype"): + if name in bound_fields: + if bound_fields[name] is None: + fields[name] = type_() + else: + # use a closure to capture the callback from the loop scope + fields[name] = ( + type_((lambda callback: lambda *args: callback(*args))( + bound_fields[name])) + ) + del bound_fields[name] + else: + # default callback implementation (does nothing) + try: + default_ = type_(0).restype().value + except TypeError: + default_ = None + fields[name] = type_(( + lambda default_: lambda *args: default_)(default_)) + else: + # not a callback function, use default initialization + if name in bound_fields: + fields[name] = bound_fields[name] + del bound_fields[name] + else: + fields[name] = type_() + if len(bound_fields) != 0: + raise ValueError( + "Cannot bind the following unknown callback(s) {}.{}".format( + cls.__name__, bound_fields.keys() + )) + return cls(**fields) + + +class Union(ctypes.Union, AsDictMixin): + pass + + + + + +HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_ = True # macro +SDMA_OP_COPY = 1 # macro +SDMA_OP_FENCE = 5 # macro +SDMA_OP_TRAP = 6 # macro +SDMA_OP_POLL_REGMEM = 8 # macro +SDMA_OP_ATOMIC = 10 # macro +SDMA_OP_CONST_FILL = 11 # macro +SDMA_OP_TIMESTAMP = 13 # macro +SDMA_OP_GCR = 17 # Variable ctypes.c_uint32 +SDMA_SUBOP_COPY_LINEAR = 0 # macro +SDMA_SUBOP_COPY_LINEAR_RECT = 4 # Variable ctypes.c_uint32 +SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 # macro +SDMA_SUBOP_USER_GCR = 1 # Variable ctypes.c_uint32 +SDMA_ATOMIC_ADD64 = 47 # Variable ctypes.c_uint32 +class struct_SDMA_PKT_COPY_LINEAR_TAG(Structure): + pass + +class union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_TAG_0_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._fields_ = [ + ('op', ctypes.c_uint32, 8), + ('sub_op', ctypes.c_uint32, 8), + ('extra_info', ctypes.c_uint32, 16), +] + +union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_0_0), + ('DW_0_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_TAG_1_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._fields_ = [ + ('count', ctypes.c_uint32, 22), + ('reserved_0', ctypes.c_uint32, 10), +] + +union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_1_0), + ('DW_1_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_TAG_2_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._fields_ = [ + ('reserved_0', ctypes.c_uint32, 16), + ('dst_swap', ctypes.c_uint32, 2), + ('reserved_1', ctypes.c_uint32, 6), + ('src_swap', ctypes.c_uint32, 2), + ('reserved_2', ctypes.c_uint32, 6), +] + +union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_2_0), + ('DW_2_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_TAG_3_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._fields_ = [ + ('src_addr_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_3_0), + ('DW_3_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_TAG_4_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._fields_ = [ + ('src_addr_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_4_0), + ('DW_4_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_TAG_5_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._fields_ = [ + ('dst_addr_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_5_0), + ('DW_5_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_TAG_6_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._fields_ = [ + ('dst_addr_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_6_0), + ('DW_6_DATA', ctypes.c_uint32), +] + +struct_SDMA_PKT_COPY_LINEAR_TAG._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_TAG._fields_ = [ + ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION), + ('COUNT_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION), + ('PARAMETER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION), + ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION), + ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION), + ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION), + ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION), +] + +SDMA_PKT_COPY_LINEAR = struct_SDMA_PKT_COPY_LINEAR_TAG +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG(Structure): + pass + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._fields_ = [ + ('op', ctypes.c_uint32, 8), + ('sub_op', ctypes.c_uint32, 8), + ('reserved', ctypes.c_uint32, 13), + ('element', ctypes.c_uint32, 3), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0), + ('DW_0_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._fields_ = [ + ('src_addr_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0), + ('DW_1_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._fields_ = [ + ('src_addr_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0), + ('DW_2_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._fields_ = [ + ('src_offset_x', ctypes.c_uint32, 14), + ('reserved_1', ctypes.c_uint32, 2), + ('src_offset_y', ctypes.c_uint32, 14), + ('reserved_2', ctypes.c_uint32, 2), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0), + ('DW_3_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._fields_ = [ + ('src_offset_z', ctypes.c_uint32, 11), + ('reserved_1', ctypes.c_uint32, 2), + ('src_pitch', ctypes.c_uint32, 19), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0), + ('DW_4_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._fields_ = [ + ('src_slice_pitch', ctypes.c_uint32, 28), + ('reserved_1', ctypes.c_uint32, 4), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0), + ('DW_5_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._fields_ = [ + ('dst_addr_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0), + ('DW_6_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._fields_ = [ + ('dst_addr_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0), + ('DW_7_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._fields_ = [ + ('dst_offset_x', ctypes.c_uint32, 14), + ('reserved_1', ctypes.c_uint32, 2), + ('dst_offset_y', ctypes.c_uint32, 14), + ('reserved_2', ctypes.c_uint32, 2), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0), + ('DW_8_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._fields_ = [ + ('dst_offset_z', ctypes.c_uint32, 11), + ('reserved_1', ctypes.c_uint32, 2), + ('dst_pitch', ctypes.c_uint32, 19), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0), + ('DW_9_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._fields_ = [ + ('dst_slice_pitch', ctypes.c_uint32, 28), + ('reserved_1', ctypes.c_uint32, 4), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0), + ('DW_10_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._fields_ = [ + ('rect_x', ctypes.c_uint32, 14), + ('reserved_1', ctypes.c_uint32, 2), + ('rect_y', ctypes.c_uint32, 14), + ('reserved_2', ctypes.c_uint32, 2), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0), + ('DW_11_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION(Union): + pass + +class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0(Structure): + pass + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._fields_ = [ + ('rect_z', ctypes.c_uint32, 11), + ('reserved_1', ctypes.c_uint32, 5), + ('dst_swap', ctypes.c_uint32, 2), + ('reserved_2', ctypes.c_uint32, 6), + ('src_swap', ctypes.c_uint32, 2), + ('reserved_3', ctypes.c_uint32, 6), +] + +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._pack_ = 1 # source:False +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0), + ('DW_12_DATA', ctypes.c_uint32), +] + +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._pack_ = 1 # source:False +struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._fields_ = [ + ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION), + ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION), + ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION), + ('SRC_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION), + ('SRC_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION), + ('SRC_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION), + ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION), + ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION), + ('DST_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION), + ('DST_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION), + ('DST_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION), + ('RECT_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION), + ('RECT_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION), +] + +SDMA_PKT_COPY_LINEAR_RECT = struct_SDMA_PKT_COPY_LINEAR_RECT_TAG +class struct_SDMA_PKT_CONSTANT_FILL_TAG(Structure): + pass + +class union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION(Union): + pass + +class struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0(Structure): + pass + +struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._pack_ = 1 # source:False +struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._fields_ = [ + ('op', ctypes.c_uint32, 8), + ('sub_op', ctypes.c_uint32, 8), + ('sw', ctypes.c_uint32, 2), + ('reserved_0', ctypes.c_uint32, 12), + ('fillsize', ctypes.c_uint32, 2), +] + +union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._pack_ = 1 # source:False +union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0), + ('DW_0_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION(Union): + pass + +class struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0(Structure): + pass + +struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._pack_ = 1 # source:False +struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._fields_ = [ + ('dst_addr_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0), + ('DW_1_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION(Union): + pass + +class struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0(Structure): + pass + +struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._pack_ = 1 # source:False +struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._fields_ = [ + ('dst_addr_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0), + ('DW_2_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION(Union): + pass + +class struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0(Structure): + pass + +struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._pack_ = 1 # source:False +struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._fields_ = [ + ('src_data_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._pack_ = 1 # source:False +union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0), + ('DW_3_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION(Union): + pass + +class struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0(Structure): + pass + +struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._pack_ = 1 # source:False +struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._fields_ = [ + ('count', ctypes.c_uint32, 22), + ('reserved_0', ctypes.c_uint32, 10), +] + +union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._pack_ = 1 # source:False +union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0), + ('DW_4_DATA', ctypes.c_uint32), +] + +struct_SDMA_PKT_CONSTANT_FILL_TAG._pack_ = 1 # source:False +struct_SDMA_PKT_CONSTANT_FILL_TAG._fields_ = [ + ('HEADER_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION), + ('DST_ADDR_LO_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION), + ('DST_ADDR_HI_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION), + ('DATA_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION), + ('COUNT_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION), +] + +SDMA_PKT_CONSTANT_FILL = struct_SDMA_PKT_CONSTANT_FILL_TAG +class struct_SDMA_PKT_FENCE_TAG(Structure): + pass + +class union_SDMA_PKT_FENCE_TAG_HEADER_UNION(Union): + pass + +class struct_SDMA_PKT_FENCE_TAG_0_0(Structure): + pass + +struct_SDMA_PKT_FENCE_TAG_0_0._pack_ = 1 # source:False +struct_SDMA_PKT_FENCE_TAG_0_0._fields_ = [ + ('op', ctypes.c_uint32, 8), + ('sub_op', ctypes.c_uint32, 8), + ('mtype', ctypes.c_uint32, 3), + ('gcc', ctypes.c_uint32, 1), + ('sys', ctypes.c_uint32, 1), + ('pad1', ctypes.c_uint32, 1), + ('snp', ctypes.c_uint32, 1), + ('gpa', ctypes.c_uint32, 1), + ('l2_policy', ctypes.c_uint32, 2), + ('reserved_0', ctypes.c_uint32, 6), +] + +union_SDMA_PKT_FENCE_TAG_HEADER_UNION._pack_ = 1 # source:False +union_SDMA_PKT_FENCE_TAG_HEADER_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_FENCE_TAG_HEADER_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_FENCE_TAG_0_0), + ('DW_0_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION(Union): + pass + +class struct_SDMA_PKT_FENCE_TAG_1_0(Structure): + pass + +struct_SDMA_PKT_FENCE_TAG_1_0._pack_ = 1 # source:False +struct_SDMA_PKT_FENCE_TAG_1_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_FENCE_TAG_1_0), + ('DW_1_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION(Union): + pass + +class struct_SDMA_PKT_FENCE_TAG_2_0(Structure): + pass + +struct_SDMA_PKT_FENCE_TAG_2_0._pack_ = 1 # source:False +struct_SDMA_PKT_FENCE_TAG_2_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_FENCE_TAG_2_0), + ('DW_2_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_FENCE_TAG_DATA_UNION(Union): + pass + +class struct_SDMA_PKT_FENCE_TAG_3_0(Structure): + pass + +struct_SDMA_PKT_FENCE_TAG_3_0._pack_ = 1 # source:False +struct_SDMA_PKT_FENCE_TAG_3_0._fields_ = [ + ('data', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_FENCE_TAG_DATA_UNION._pack_ = 1 # source:False +union_SDMA_PKT_FENCE_TAG_DATA_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_FENCE_TAG_DATA_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_FENCE_TAG_3_0), + ('DW_3_DATA', ctypes.c_uint32), +] + +struct_SDMA_PKT_FENCE_TAG._pack_ = 1 # source:False +struct_SDMA_PKT_FENCE_TAG._fields_ = [ + ('HEADER_UNION', union_SDMA_PKT_FENCE_TAG_HEADER_UNION), + ('ADDR_LO_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION), + ('DATA_UNION', union_SDMA_PKT_FENCE_TAG_DATA_UNION), +] + +SDMA_PKT_FENCE = struct_SDMA_PKT_FENCE_TAG +class struct_SDMA_PKT_POLL_REGMEM_TAG(Structure): + pass + +class union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION(Union): + pass + +class struct_SDMA_PKT_POLL_REGMEM_TAG_0_0(Structure): + pass + +struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._pack_ = 1 # source:False +struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._fields_ = [ + ('op', ctypes.c_uint32, 8), + ('sub_op', ctypes.c_uint32, 8), + ('reserved_0', ctypes.c_uint32, 10), + ('hdp_flush', ctypes.c_uint32, 1), + ('reserved_1', ctypes.c_uint32, 1), + ('func', ctypes.c_uint32, 3), + ('mem_poll', ctypes.c_uint32, 1), +] + +union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._pack_ = 1 # source:False +union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_0_0), + ('DW_0_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION(Union): + pass + +class struct_SDMA_PKT_POLL_REGMEM_TAG_1_0(Structure): + pass + +struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._pack_ = 1 # source:False +struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_1_0), + ('DW_1_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION(Union): + pass + +class struct_SDMA_PKT_POLL_REGMEM_TAG_2_0(Structure): + pass + +struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._pack_ = 1 # source:False +struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_2_0), + ('DW_2_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION(Union): + pass + +class struct_SDMA_PKT_POLL_REGMEM_TAG_3_0(Structure): + pass + +struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._pack_ = 1 # source:False +struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._fields_ = [ + ('value', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._pack_ = 1 # source:False +union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_3_0), + ('DW_3_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION(Union): + pass + +class struct_SDMA_PKT_POLL_REGMEM_TAG_4_0(Structure): + pass + +struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._pack_ = 1 # source:False +struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._fields_ = [ + ('mask', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._pack_ = 1 # source:False +union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_4_0), + ('DW_4_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION(Union): + pass + +class struct_SDMA_PKT_POLL_REGMEM_TAG_5_0(Structure): + pass + +struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._pack_ = 1 # source:False +struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._fields_ = [ + ('interval', ctypes.c_uint32, 16), + ('retry_count', ctypes.c_uint32, 12), + ('reserved_0', ctypes.c_uint32, 4), +] + +union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._pack_ = 1 # source:False +union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_5_0), + ('DW_5_DATA', ctypes.c_uint32), +] + +struct_SDMA_PKT_POLL_REGMEM_TAG._pack_ = 1 # source:False +struct_SDMA_PKT_POLL_REGMEM_TAG._fields_ = [ + ('HEADER_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION), + ('ADDR_LO_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION), + ('VALUE_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION), + ('MASK_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION), + ('DW5_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION), +] + +SDMA_PKT_POLL_REGMEM = struct_SDMA_PKT_POLL_REGMEM_TAG +class struct_SDMA_PKT_ATOMIC_TAG(Structure): + pass + +class union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION(Union): + pass + +class struct_SDMA_PKT_ATOMIC_TAG_0_0(Structure): + pass + +struct_SDMA_PKT_ATOMIC_TAG_0_0._pack_ = 1 # source:False +struct_SDMA_PKT_ATOMIC_TAG_0_0._fields_ = [ + ('op', ctypes.c_uint32, 8), + ('sub_op', ctypes.c_uint32, 8), + ('l', ctypes.c_uint32, 1), + ('reserved_0', ctypes.c_uint32, 8), + ('operation', ctypes.c_uint32, 7), +] + +union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._pack_ = 1 # source:False +union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_ATOMIC_TAG_0_0), + ('DW_0_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION(Union): + pass + +class struct_SDMA_PKT_ATOMIC_TAG_1_0(Structure): + pass + +struct_SDMA_PKT_ATOMIC_TAG_1_0._pack_ = 1 # source:False +struct_SDMA_PKT_ATOMIC_TAG_1_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_ATOMIC_TAG_1_0), + ('DW_1_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION(Union): + pass + +class struct_SDMA_PKT_ATOMIC_TAG_2_0(Structure): + pass + +struct_SDMA_PKT_ATOMIC_TAG_2_0._pack_ = 1 # source:False +struct_SDMA_PKT_ATOMIC_TAG_2_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_ATOMIC_TAG_2_0), + ('DW_2_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION(Union): + pass + +class struct_SDMA_PKT_ATOMIC_TAG_3_0(Structure): + pass + +struct_SDMA_PKT_ATOMIC_TAG_3_0._pack_ = 1 # source:False +struct_SDMA_PKT_ATOMIC_TAG_3_0._fields_ = [ + ('src_data_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_ATOMIC_TAG_3_0), + ('DW_3_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION(Union): + pass + +class struct_SDMA_PKT_ATOMIC_TAG_4_0(Structure): + pass + +struct_SDMA_PKT_ATOMIC_TAG_4_0._pack_ = 1 # source:False +struct_SDMA_PKT_ATOMIC_TAG_4_0._fields_ = [ + ('src_data_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_ATOMIC_TAG_4_0), + ('DW_4_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION(Union): + pass + +class struct_SDMA_PKT_ATOMIC_TAG_5_0(Structure): + pass + +struct_SDMA_PKT_ATOMIC_TAG_5_0._pack_ = 1 # source:False +struct_SDMA_PKT_ATOMIC_TAG_5_0._fields_ = [ + ('cmp_data_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_ATOMIC_TAG_5_0), + ('DW_5_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION(Union): + pass + +class struct_SDMA_PKT_ATOMIC_TAG_6_0(Structure): + pass + +struct_SDMA_PKT_ATOMIC_TAG_6_0._pack_ = 1 # source:False +struct_SDMA_PKT_ATOMIC_TAG_6_0._fields_ = [ + ('cmp_data_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_ATOMIC_TAG_6_0), + ('DW_6_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION(Union): + pass + +class struct_SDMA_PKT_ATOMIC_TAG_7_0(Structure): + pass + +struct_SDMA_PKT_ATOMIC_TAG_7_0._pack_ = 1 # source:False +struct_SDMA_PKT_ATOMIC_TAG_7_0._fields_ = [ + ('loop_interval', ctypes.c_uint32, 13), + ('reserved_0', ctypes.c_uint32, 19), +] + +union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._pack_ = 1 # source:False +union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_ATOMIC_TAG_7_0), + ('DW_7_DATA', ctypes.c_uint32), +] + +struct_SDMA_PKT_ATOMIC_TAG._pack_ = 1 # source:False +struct_SDMA_PKT_ATOMIC_TAG._fields_ = [ + ('HEADER_UNION', union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION), + ('ADDR_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION), + ('SRC_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION), + ('SRC_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION), + ('CMP_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION), + ('CMP_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION), + ('LOOP_UNION', union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION), +] + +SDMA_PKT_ATOMIC = struct_SDMA_PKT_ATOMIC_TAG +class struct_SDMA_PKT_TIMESTAMP_TAG(Structure): + pass + +class union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION(Union): + pass + +class struct_SDMA_PKT_TIMESTAMP_TAG_0_0(Structure): + pass + +struct_SDMA_PKT_TIMESTAMP_TAG_0_0._pack_ = 1 # source:False +struct_SDMA_PKT_TIMESTAMP_TAG_0_0._fields_ = [ + ('op', ctypes.c_uint32, 8), + ('sub_op', ctypes.c_uint32, 8), + ('reserved_0', ctypes.c_uint32, 16), +] + +union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._pack_ = 1 # source:False +union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_0_0), + ('DW_0_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION(Union): + pass + +class struct_SDMA_PKT_TIMESTAMP_TAG_1_0(Structure): + pass + +struct_SDMA_PKT_TIMESTAMP_TAG_1_0._pack_ = 1 # source:False +struct_SDMA_PKT_TIMESTAMP_TAG_1_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._pack_ = 1 # source:False +union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_1_0), + ('DW_1_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION(Union): + pass + +class struct_SDMA_PKT_TIMESTAMP_TAG_2_0(Structure): + pass + +struct_SDMA_PKT_TIMESTAMP_TAG_2_0._pack_ = 1 # source:False +struct_SDMA_PKT_TIMESTAMP_TAG_2_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32, 32), +] + +union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._pack_ = 1 # source:False +union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_2_0), + ('DW_2_DATA', ctypes.c_uint32), +] + +struct_SDMA_PKT_TIMESTAMP_TAG._pack_ = 1 # source:False +struct_SDMA_PKT_TIMESTAMP_TAG._fields_ = [ + ('HEADER_UNION', union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION), + ('ADDR_LO_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION), +] + +SDMA_PKT_TIMESTAMP = struct_SDMA_PKT_TIMESTAMP_TAG +class struct_SDMA_PKT_TRAP_TAG(Structure): + pass + +class union_SDMA_PKT_TRAP_TAG_HEADER_UNION(Union): + pass + +class struct_SDMA_PKT_TRAP_TAG_0_0(Structure): + pass + +struct_SDMA_PKT_TRAP_TAG_0_0._pack_ = 1 # source:False +struct_SDMA_PKT_TRAP_TAG_0_0._fields_ = [ + ('op', ctypes.c_uint32, 8), + ('sub_op', ctypes.c_uint32, 8), + ('reserved_0', ctypes.c_uint32, 16), +] + +union_SDMA_PKT_TRAP_TAG_HEADER_UNION._pack_ = 1 # source:False +union_SDMA_PKT_TRAP_TAG_HEADER_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_TRAP_TAG_HEADER_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_TRAP_TAG_0_0), + ('DW_0_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION(Union): + pass + +class struct_SDMA_PKT_TRAP_TAG_1_0(Structure): + pass + +struct_SDMA_PKT_TRAP_TAG_1_0._pack_ = 1 # source:False +struct_SDMA_PKT_TRAP_TAG_1_0._fields_ = [ + ('int_ctx', ctypes.c_uint32, 28), + ('reserved_1', ctypes.c_uint32, 4), +] + +union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._pack_ = 1 # source:False +union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_TRAP_TAG_1_0), + ('DW_1_DATA', ctypes.c_uint32), +] + +struct_SDMA_PKT_TRAP_TAG._pack_ = 1 # source:False +struct_SDMA_PKT_TRAP_TAG._fields_ = [ + ('HEADER_UNION', union_SDMA_PKT_TRAP_TAG_HEADER_UNION), + ('INT_CONTEXT_UNION', union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION), +] + +SDMA_PKT_TRAP = struct_SDMA_PKT_TRAP_TAG +class struct_SDMA_PKT_HDP_FLUSH_TAG(Structure): + pass + +struct_SDMA_PKT_HDP_FLUSH_TAG._pack_ = 1 # source:False +struct_SDMA_PKT_HDP_FLUSH_TAG._fields_ = [ + ('DW_0_DATA', ctypes.c_uint32), + ('DW_1_DATA', ctypes.c_uint32), + ('DW_2_DATA', ctypes.c_uint32), + ('DW_3_DATA', ctypes.c_uint32), + ('DW_4_DATA', ctypes.c_uint32), + ('DW_5_DATA', ctypes.c_uint32), +] + +SDMA_PKT_HDP_FLUSH = struct_SDMA_PKT_HDP_FLUSH_TAG +hdp_flush_cmd = struct_SDMA_PKT_HDP_FLUSH_TAG # Variable struct_SDMA_PKT_HDP_FLUSH_TAG +class struct_SDMA_PKT_GCR_TAG(Structure): + pass + +class union_SDMA_PKT_GCR_TAG_HEADER_UNION(Union): + pass + +class struct_SDMA_PKT_GCR_TAG_0_0(Structure): + pass + +struct_SDMA_PKT_GCR_TAG_0_0._pack_ = 1 # source:False +struct_SDMA_PKT_GCR_TAG_0_0._fields_ = [ + ('op', ctypes.c_uint32, 8), + ('sub_op', ctypes.c_uint32, 8), + ('_2', ctypes.c_uint32, 16), +] + +union_SDMA_PKT_GCR_TAG_HEADER_UNION._pack_ = 1 # source:False +union_SDMA_PKT_GCR_TAG_HEADER_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_GCR_TAG_HEADER_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_GCR_TAG_0_0), + ('DW_0_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_GCR_TAG_WORD1_UNION(Union): + pass + +class struct_SDMA_PKT_GCR_TAG_1_0(Structure): + pass + +struct_SDMA_PKT_GCR_TAG_1_0._pack_ = 1 # source:False +struct_SDMA_PKT_GCR_TAG_1_0._fields_ = [ + ('_0', ctypes.c_uint32, 7), + ('BaseVA_LO', ctypes.c_uint32, 25), +] + +union_SDMA_PKT_GCR_TAG_WORD1_UNION._pack_ = 1 # source:False +union_SDMA_PKT_GCR_TAG_WORD1_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_GCR_TAG_WORD1_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_GCR_TAG_1_0), + ('DW_1_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_GCR_TAG_WORD2_UNION(Union): + pass + +class struct_SDMA_PKT_GCR_TAG_2_0(Structure): + pass + +struct_SDMA_PKT_GCR_TAG_2_0._pack_ = 1 # source:False +struct_SDMA_PKT_GCR_TAG_2_0._fields_ = [ + ('BaseVA_HI', ctypes.c_uint32, 16), + ('GCR_CONTROL_GLI_INV', ctypes.c_uint32, 2), + ('GCR_CONTROL_GL1_RANGE', ctypes.c_uint32, 2), + ('GCR_CONTROL_GLM_WB', ctypes.c_uint32, 1), + ('GCR_CONTROL_GLM_INV', ctypes.c_uint32, 1), + ('GCR_CONTROL_GLK_WB', ctypes.c_uint32, 1), + ('GCR_CONTROL_GLK_INV', ctypes.c_uint32, 1), + ('GCR_CONTROL_GLV_INV', ctypes.c_uint32, 1), + ('GCR_CONTROL_GL1_INV', ctypes.c_uint32, 1), + ('GCR_CONTROL_GL2_US', ctypes.c_uint32, 1), + ('GCR_CONTROL_GL2_RANGE', ctypes.c_uint32, 2), + ('GCR_CONTROL_GL2_DISCARD', ctypes.c_uint32, 1), + ('GCR_CONTROL_GL2_INV', ctypes.c_uint32, 1), + ('GCR_CONTROL_GL2_WB', ctypes.c_uint32, 1), +] + +union_SDMA_PKT_GCR_TAG_WORD2_UNION._pack_ = 1 # source:False +union_SDMA_PKT_GCR_TAG_WORD2_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_GCR_TAG_WORD2_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_GCR_TAG_2_0), + ('DW_2_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_GCR_TAG_WORD3_UNION(Union): + pass + +class struct_SDMA_PKT_GCR_TAG_3_0(Structure): + pass + +struct_SDMA_PKT_GCR_TAG_3_0._pack_ = 1 # source:False +struct_SDMA_PKT_GCR_TAG_3_0._fields_ = [ + ('GCR_CONTROL_RANGE_IS_PA', ctypes.c_uint32, 1), + ('GCR_CONTROL_SEQ', ctypes.c_uint32, 2), + ('_2', ctypes.c_uint32, 4), + ('LimitVA_LO', ctypes.c_uint32, 25), +] + +union_SDMA_PKT_GCR_TAG_WORD3_UNION._pack_ = 1 # source:False +union_SDMA_PKT_GCR_TAG_WORD3_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_GCR_TAG_WORD3_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_GCR_TAG_3_0), + ('DW_3_DATA', ctypes.c_uint32), +] + +class union_SDMA_PKT_GCR_TAG_WORD4_UNION(Union): + pass + +class struct_SDMA_PKT_GCR_TAG_4_0(Structure): + pass + +struct_SDMA_PKT_GCR_TAG_4_0._pack_ = 1 # source:False +struct_SDMA_PKT_GCR_TAG_4_0._fields_ = [ + ('LimitVA_HI', ctypes.c_uint32, 16), + ('_1', ctypes.c_uint32, 8), + ('VMID', ctypes.c_uint32, 4), + ('_3', ctypes.c_uint32, 4), +] + +union_SDMA_PKT_GCR_TAG_WORD4_UNION._pack_ = 1 # source:False +union_SDMA_PKT_GCR_TAG_WORD4_UNION._anonymous_ = ('_0',) +union_SDMA_PKT_GCR_TAG_WORD4_UNION._fields_ = [ + ('_0', struct_SDMA_PKT_GCR_TAG_4_0), + ('DW_4_DATA', ctypes.c_uint32), +] + +struct_SDMA_PKT_GCR_TAG._pack_ = 1 # source:False +struct_SDMA_PKT_GCR_TAG._fields_ = [ + ('HEADER_UNION', union_SDMA_PKT_GCR_TAG_HEADER_UNION), + ('WORD1_UNION', union_SDMA_PKT_GCR_TAG_WORD1_UNION), + ('WORD2_UNION', union_SDMA_PKT_GCR_TAG_WORD2_UNION), + ('WORD3_UNION', union_SDMA_PKT_GCR_TAG_WORD3_UNION), + ('WORD4_UNION', union_SDMA_PKT_GCR_TAG_WORD4_UNION), +] + +SDMA_PKT_GCR = struct_SDMA_PKT_GCR_TAG +__VEGA10_SDMA_PKT_OPEN_H_ = True # macro +SDMA_OP_NOP = 0 # macro +SDMA_OP_WRITE = 2 # macro +SDMA_OP_INDIRECT = 4 # macro +SDMA_OP_SEM = 7 # macro +SDMA_OP_COND_EXE = 9 # macro +SDMA_OP_PTEPDE = 12 # macro +SDMA_OP_SRBM_WRITE = 14 # macro +SDMA_OP_PRE_EXE = 15 # macro +SDMA_OP_DUMMY_TRAP = 16 # macro +SDMA_SUBOP_TIMESTAMP_SET = 0 # macro +SDMA_SUBOP_TIMESTAMP_GET = 1 # macro +SDMA_SUBOP_COPY_LINEAR_SUB_WIND = 4 # macro +SDMA_SUBOP_COPY_TILED = 1 # macro +SDMA_SUBOP_COPY_TILED_SUB_WIND = 5 # macro +SDMA_SUBOP_COPY_T2T_SUB_WIND = 6 # macro +SDMA_SUBOP_COPY_SOA = 3 # macro +SDMA_SUBOP_COPY_DIRTY_PAGE = 7 # macro +SDMA_SUBOP_COPY_LINEAR_PHY = 8 # macro +SDMA_SUBOP_WRITE_LINEAR = 0 # macro +SDMA_SUBOP_WRITE_TILED = 1 # macro +SDMA_SUBOP_PTEPDE_GEN = 0 # macro +SDMA_SUBOP_PTEPDE_COPY = 1 # macro +SDMA_SUBOP_PTEPDE_RMW = 2 # macro +SDMA_SUBOP_PTEPDE_COPY_BACKWARDS = 3 # macro +SDMA_SUBOP_DATA_FILL_MULTI = 1 # macro +SDMA_SUBOP_POLL_REG_WRITE_MEM = 1 # macro +SDMA_SUBOP_POLL_DBIT_WRITE_MEM = 2 # macro +SDMA_SUBOP_POLL_MEM_VERIFY = 3 # macro +HEADER_AGENT_DISPATCH = 4 # macro +HEADER_BARRIER = 5 # macro +SDMA_OP_AQL_COPY = 0 # macro +SDMA_OP_AQL_BARRIER_OR = 0 # macro +SDMA_PKT_HEADER_op_offset = 0 # macro +SDMA_PKT_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_HEADER_op_shift = 0 # macro +def SDMA_PKT_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_LINEAR_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro +SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro +SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift = 27 # macro +def SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x): # macro + return (((x)&0x00000001)<<27) +SDMA_PKT_COPY_LINEAR_COUNT_count_offset = 1 # macro +SDMA_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF # macro +SDMA_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro + return (((x)&0x003FFFFF)<<0) +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 2 # macro +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 2 # macro +SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro +SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro +SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro +SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro +SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset = 0 # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift = 31 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset = 1 # macro +SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask = 0x003FFFFF # macro +SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x): # macro + return (((x)&0x003FFFFF)<<0) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift = 16 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift = 19 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift = 20 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x): # macro + return (((x)&0x00000001)<<20) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift = 22 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x): # macro + return (((x)&0x00000001)<<22) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift = 23 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x): # macro + return (((x)&0x00000001)<<23) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift = 28 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift = 30 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x): # macro + return (((x)&0x00000001)<<30) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift = 31 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset = 1 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask = 0x003FFFFF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x): # macro + return (((x)&0x003FFFFF)<<0) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift = 16 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift = 19 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift = 20 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x): # macro + return (((x)&0x00000001)<<20) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift = 21 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x): # macro + return (((x)&0x00000001)<<21) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift = 22 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x): # macro + return (((x)&0x00000001)<<22) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift = 23 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x): # macro + return (((x)&0x00000001)<<23) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift = 27 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x): # macro + return (((x)&0x00000001)<<27) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift = 28 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift = 30 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x): # macro + return (((x)&0x00000001)<<30) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift = 31 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset = 0 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift = 16 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset = 0 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift = 27 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x): # macro + return (((x)&0x00000001)<<27) +SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset = 1 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask = 0x003FFFFF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x): # macro + return (((x)&0x003FFFFF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset = 2 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift = 8 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x): # macro + return (((x)&0x00000003)<<8) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset = 2 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift = 16 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset = 2 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset = 5 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset = 6 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset = 7 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset = 8 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask = 0x00000007 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift = 29 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x): # macro + return (((x)&0x00000007)<<29) +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset = 3 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset = 3 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset = 4 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset = 4 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask = 0x0007FFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift = 13 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x): # macro + return (((x)&0x0007FFFF)<<13) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset = 5 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask = 0x0FFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x): # macro + return (((x)&0x0FFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset = 6 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset = 7 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset = 8 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset = 8 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset = 9 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset = 9 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask = 0x0007FFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift = 13 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x): # macro + return (((x)&0x0007FFFF)<<13) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset = 10 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x): # macro + return (((x)&0x0FFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset = 11 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset = 11 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset = 12 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset = 12 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset = 12 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_TILED_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_TILED_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_TILED_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_TILED_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_TILED_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_TILED_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_TILED_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_TILED_HEADER_encrypt_offset = 0 # macro +SDMA_PKT_COPY_TILED_HEADER_encrypt_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_HEADER_encrypt_shift = 16 # macro +def SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_COPY_TILED_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_TILED_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_TILED_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_TILED_HEADER_mip_max_offset = 0 # macro +SDMA_PKT_COPY_TILED_HEADER_mip_max_mask = 0x0000000F # macro +SDMA_PKT_COPY_TILED_HEADER_mip_max_shift = 20 # macro +def SDMA_PKT_COPY_TILED_HEADER_MIP_MAX(x): # macro + return (((x)&0x0000000F)<<20) +SDMA_PKT_COPY_TILED_HEADER_detile_offset = 0 # macro +SDMA_PKT_COPY_TILED_HEADER_detile_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_HEADER_detile_shift = 31 # macro +def SDMA_PKT_COPY_TILED_HEADER_DETILE(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro +SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro +SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_DW_3_width_offset = 3 # macro +SDMA_PKT_COPY_TILED_DW_3_width_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_DW_3_width_shift = 0 # macro +def SDMA_PKT_COPY_TILED_DW_3_WIDTH(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_DW_4_height_offset = 4 # macro +SDMA_PKT_COPY_TILED_DW_4_height_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_DW_4_height_shift = 0 # macro +def SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_DW_4_depth_offset = 4 # macro +SDMA_PKT_COPY_TILED_DW_4_depth_mask = 0x000007FF # macro +SDMA_PKT_COPY_TILED_DW_4_depth_shift = 16 # macro +def SDMA_PKT_COPY_TILED_DW_4_DEPTH(x): # macro + return (((x)&0x000007FF)<<16) +SDMA_PKT_COPY_TILED_DW_5_element_size_offset = 5 # macro +SDMA_PKT_COPY_TILED_DW_5_element_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_TILED_DW_5_element_size_shift = 0 # macro +def SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset = 5 # macro +SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro +SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift = 3 # macro +def SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x): # macro + return (((x)&0x0000001F)<<3) +SDMA_PKT_COPY_TILED_DW_5_dimension_offset = 5 # macro +SDMA_PKT_COPY_TILED_DW_5_dimension_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_DW_5_dimension_shift = 9 # macro +def SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x): # macro + return (((x)&0x00000003)<<9) +SDMA_PKT_COPY_TILED_DW_5_epitch_offset = 5 # macro +SDMA_PKT_COPY_TILED_DW_5_epitch_mask = 0x0000FFFF # macro +SDMA_PKT_COPY_TILED_DW_5_epitch_shift = 16 # macro +def SDMA_PKT_COPY_TILED_DW_5_EPITCH(x): # macro + return (((x)&0x0000FFFF)<<16) +SDMA_PKT_COPY_TILED_DW_6_x_offset = 6 # macro +SDMA_PKT_COPY_TILED_DW_6_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_DW_6_x_shift = 0 # macro +def SDMA_PKT_COPY_TILED_DW_6_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_DW_6_y_offset = 6 # macro +SDMA_PKT_COPY_TILED_DW_6_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_DW_6_y_shift = 16 # macro +def SDMA_PKT_COPY_TILED_DW_6_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_DW_7_z_offset = 7 # macro +SDMA_PKT_COPY_TILED_DW_7_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_TILED_DW_7_z_shift = 0 # macro +def SDMA_PKT_COPY_TILED_DW_7_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset = 7 # macro +SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift = 16 # macro +def SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset = 7 # macro +SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift = 24 # macro +def SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 # macro +SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 # macro +SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset = 10 # macro +SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro +SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift = 0 # macro +def SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x): # macro + return (((x)&0x0007FFFF)<<0) +SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 # macro +SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro +def SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_COUNT_count_offset = 12 # macro +SDMA_PKT_COPY_TILED_COUNT_count_mask = 0x000FFFFF # macro +SDMA_PKT_COPY_TILED_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_TILED_COUNT_COUNT(x): # macro + return (((x)&0x000FFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset = 0 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask = 0x00000001 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift = 16 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_offset = 0 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask = 0x0000000F # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift = 20 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_MIP_MAX(x): # macro + return (((x)&0x0000000F)<<20) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset = 0 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask = 0x00000001 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift = 26 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x): # macro + return (((x)&0x00000001)<<26) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset = 0 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask = 0x00000001 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift = 27 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x): # macro + return (((x)&0x00000001)<<27) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset = 1 # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset = 2 # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset = 3 # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset = 4 # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset = 5 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask = 0x00003FFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset = 6 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask = 0x00003FFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset = 6 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask = 0x000007FF # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift = 16 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x): # macro + return (((x)&0x000007FF)<<16) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset = 7 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset = 7 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask = 0x0000001F # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift = 3 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x): # macro + return (((x)&0x0000001F)<<3) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset = 7 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask = 0x00000003 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift = 9 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x): # macro + return (((x)&0x00000003)<<9) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_offset = 7 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask = 0x0000FFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift = 16 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_EPITCH(x): # macro + return (((x)&0x0000FFFF)<<16) +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset = 8 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset = 8 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift = 16 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset = 9 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset = 10 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift = 8 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x): # macro + return (((x)&0x00000003)<<8) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset = 10 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift = 16 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset = 10 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift = 24 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset = 11 # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset = 12 # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset = 13 # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x): # macro + return (((x)&0x0007FFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 14 # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset = 15 # macro +SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask = 0x000FFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x): # macro + return (((x)&0x000FFFFF)<<0) +SDMA_PKT_COPY_T2T_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_T2T_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_T2T_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_T2T_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_T2T_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_T2T_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_T2T_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_T2T_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_T2T_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_T2T_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_T2T_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_T2T_HEADER_mip_max_offset = 0 # macro +SDMA_PKT_COPY_T2T_HEADER_mip_max_mask = 0x0000000F # macro +SDMA_PKT_COPY_T2T_HEADER_mip_max_shift = 20 # macro +def SDMA_PKT_COPY_T2T_HEADER_MIP_MAX(x): # macro + return (((x)&0x0000000F)<<20) +SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro +SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro +SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_T2T_DW_3_src_x_offset = 3 # macro +SDMA_PKT_COPY_T2T_DW_3_src_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_3_src_x_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_3_SRC_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_T2T_DW_3_src_y_offset = 3 # macro +SDMA_PKT_COPY_T2T_DW_3_src_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_3_src_y_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_T2T_DW_4_src_z_offset = 4 # macro +SDMA_PKT_COPY_T2T_DW_4_src_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_T2T_DW_4_src_z_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_T2T_DW_4_src_width_offset = 4 # macro +SDMA_PKT_COPY_T2T_DW_4_src_width_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_4_src_width_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_T2T_DW_5_src_height_offset = 5 # macro +SDMA_PKT_COPY_T2T_DW_5_src_height_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_5_src_height_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_T2T_DW_5_src_depth_offset = 5 # macro +SDMA_PKT_COPY_T2T_DW_5_src_depth_mask = 0x000007FF # macro +SDMA_PKT_COPY_T2T_DW_5_src_depth_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x): # macro + return (((x)&0x000007FF)<<16) +SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset = 6 # macro +SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset = 6 # macro +SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask = 0x0000001F # macro +SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift = 3 # macro +def SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x): # macro + return (((x)&0x0000001F)<<3) +SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset = 6 # macro +SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift = 9 # macro +def SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x): # macro + return (((x)&0x00000003)<<9) +SDMA_PKT_COPY_T2T_DW_6_src_epitch_offset = 6 # macro +SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask = 0x0000FFFF # macro +SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_6_SRC_EPITCH(x): # macro + return (((x)&0x0000FFFF)<<16) +SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset = 7 # macro +SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset = 8 # macro +SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_T2T_DW_9_dst_x_offset = 9 # macro +SDMA_PKT_COPY_T2T_DW_9_dst_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_9_dst_x_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_9_DST_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_T2T_DW_9_dst_y_offset = 9 # macro +SDMA_PKT_COPY_T2T_DW_9_dst_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_9_dst_y_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_9_DST_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_T2T_DW_10_dst_z_offset = 10 # macro +SDMA_PKT_COPY_T2T_DW_10_dst_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_T2T_DW_10_dst_z_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_10_DST_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_T2T_DW_10_dst_width_offset = 10 # macro +SDMA_PKT_COPY_T2T_DW_10_dst_width_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_10_dst_width_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_T2T_DW_11_dst_height_offset = 11 # macro +SDMA_PKT_COPY_T2T_DW_11_dst_height_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_11_dst_height_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset = 11 # macro +SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask = 0x000007FF # macro +SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x): # macro + return (((x)&0x000007FF)<<16) +SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset = 12 # macro +SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset = 12 # macro +SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask = 0x0000001F # macro +SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift = 3 # macro +def SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x): # macro + return (((x)&0x0000001F)<<3) +SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset = 12 # macro +SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift = 9 # macro +def SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x): # macro + return (((x)&0x00000003)<<9) +SDMA_PKT_COPY_T2T_DW_12_dst_epitch_offset = 12 # macro +SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask = 0x0000FFFF # macro +SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_12_DST_EPITCH(x): # macro + return (((x)&0x0000FFFF)<<16) +SDMA_PKT_COPY_T2T_DW_13_rect_x_offset = 13 # macro +SDMA_PKT_COPY_T2T_DW_13_rect_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_13_rect_x_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_13_RECT_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_T2T_DW_13_rect_y_offset = 13 # macro +SDMA_PKT_COPY_T2T_DW_13_rect_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_13_rect_y_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_T2T_DW_14_rect_z_offset = 14 # macro +SDMA_PKT_COPY_T2T_DW_14_rect_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_T2T_DW_14_rect_z_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset = 14 # macro +SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_14_DST_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_T2T_DW_14_src_sw_offset = 14 # macro +SDMA_PKT_COPY_T2T_DW_14_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_DW_14_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_offset = 0 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask = 0x0000000F # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift = 20 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_MAX(x): # macro + return (((x)&0x0000000F)<<20) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_offset = 0 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask = 0x0000000F # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift = 24 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_ID(x): # macro + return (((x)&0x0000000F)<<24) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset = 0 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift = 31 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset = 3 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset = 3 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset = 4 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset = 4 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset = 5 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset = 5 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask = 0x000007FF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x): # macro + return (((x)&0x000007FF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask = 0x0000001F # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift = 3 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x): # macro + return (((x)&0x0000001F)<<3) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift = 9 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x): # macro + return (((x)&0x00000003)<<9) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask = 0x0000FFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_EPITCH(x): # macro + return (((x)&0x0000FFFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 # macro +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 # macro +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset = 9 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset = 9 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset = 10 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset = 10 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset = 11 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x): # macro + return (((x)&0x0FFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset = 12 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset = 12 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset = 13 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset = 13 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset = 13 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift = 24 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_STRUCT_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_STRUCT_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_STRUCT_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_STRUCT_HEADER_detile_offset = 0 # macro +SDMA_PKT_COPY_STRUCT_HEADER_detile_mask = 0x00000001 # macro +SDMA_PKT_COPY_STRUCT_HEADER_detile_shift = 31 # macro +def SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset = 1 # macro +SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset = 2 # macro +SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset = 3 # macro +SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_STRUCT_COUNT_count_offset = 4 # macro +SDMA_PKT_COPY_STRUCT_COUNT_count_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_STRUCT_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_STRUCT_DW_5_stride_offset = 5 # macro +SDMA_PKT_COPY_STRUCT_DW_5_stride_mask = 0x000007FF # macro +SDMA_PKT_COPY_STRUCT_DW_5_stride_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset = 5 # macro +SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift = 16 # macro +def SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset = 5 # macro +SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift = 24 # macro +def SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset = 6 # macro +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset = 7 # macro +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_UNTILED_HEADER_op_offset = 0 # macro +SDMA_PKT_WRITE_UNTILED_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_WRITE_UNTILED_HEADER_op_shift = 0 # macro +def SDMA_PKT_WRITE_UNTILED_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset = 0 # macro +SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask = 0x00000001 # macro +SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift = 16 # macro +def SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset = 0 # macro +SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro +SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro +SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_UNTILED_DW_3_count_offset = 3 # macro +SDMA_PKT_WRITE_UNTILED_DW_3_count_mask = 0x000FFFFF # macro +SDMA_PKT_WRITE_UNTILED_DW_3_count_shift = 0 # macro +def SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x): # macro + return (((x)&0x000FFFFF)<<0) +SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset = 3 # macro +SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask = 0x00000003 # macro +SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift = 24 # macro +def SDMA_PKT_WRITE_UNTILED_DW_3_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset = 4 # macro +SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift = 0 # macro +def SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_TILED_HEADER_op_offset = 0 # macro +SDMA_PKT_WRITE_TILED_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_WRITE_TILED_HEADER_op_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset = 0 # macro +SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask = 0x00000001 # macro +SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift = 16 # macro +def SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_WRITE_TILED_HEADER_tmz_offset = 0 # macro +SDMA_PKT_WRITE_TILED_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_WRITE_TILED_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_WRITE_TILED_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_WRITE_TILED_HEADER_mip_max_offset = 0 # macro +SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask = 0x0000000F # macro +SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift = 20 # macro +def SDMA_PKT_WRITE_TILED_HEADER_MIP_MAX(x): # macro + return (((x)&0x0000000F)<<20) +SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro +SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro +SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_TILED_DW_3_width_offset = 3 # macro +SDMA_PKT_WRITE_TILED_DW_3_width_mask = 0x00003FFF # macro +SDMA_PKT_WRITE_TILED_DW_3_width_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_WRITE_TILED_DW_4_height_offset = 4 # macro +SDMA_PKT_WRITE_TILED_DW_4_height_mask = 0x00003FFF # macro +SDMA_PKT_WRITE_TILED_DW_4_height_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_WRITE_TILED_DW_4_depth_offset = 4 # macro +SDMA_PKT_WRITE_TILED_DW_4_depth_mask = 0x000007FF # macro +SDMA_PKT_WRITE_TILED_DW_4_depth_shift = 16 # macro +def SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x): # macro + return (((x)&0x000007FF)<<16) +SDMA_PKT_WRITE_TILED_DW_5_element_size_offset = 5 # macro +SDMA_PKT_WRITE_TILED_DW_5_element_size_mask = 0x00000007 # macro +SDMA_PKT_WRITE_TILED_DW_5_element_size_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset = 5 # macro +SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro +SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift = 3 # macro +def SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x): # macro + return (((x)&0x0000001F)<<3) +SDMA_PKT_WRITE_TILED_DW_5_dimension_offset = 5 # macro +SDMA_PKT_WRITE_TILED_DW_5_dimension_mask = 0x00000003 # macro +SDMA_PKT_WRITE_TILED_DW_5_dimension_shift = 9 # macro +def SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x): # macro + return (((x)&0x00000003)<<9) +SDMA_PKT_WRITE_TILED_DW_5_epitch_offset = 5 # macro +SDMA_PKT_WRITE_TILED_DW_5_epitch_mask = 0x0000FFFF # macro +SDMA_PKT_WRITE_TILED_DW_5_epitch_shift = 16 # macro +def SDMA_PKT_WRITE_TILED_DW_5_EPITCH(x): # macro + return (((x)&0x0000FFFF)<<16) +SDMA_PKT_WRITE_TILED_DW_6_x_offset = 6 # macro +SDMA_PKT_WRITE_TILED_DW_6_x_mask = 0x00003FFF # macro +SDMA_PKT_WRITE_TILED_DW_6_x_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DW_6_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_WRITE_TILED_DW_6_y_offset = 6 # macro +SDMA_PKT_WRITE_TILED_DW_6_y_mask = 0x00003FFF # macro +SDMA_PKT_WRITE_TILED_DW_6_y_shift = 16 # macro +def SDMA_PKT_WRITE_TILED_DW_6_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_WRITE_TILED_DW_7_z_offset = 7 # macro +SDMA_PKT_WRITE_TILED_DW_7_z_mask = 0x000007FF # macro +SDMA_PKT_WRITE_TILED_DW_7_z_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DW_7_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_WRITE_TILED_DW_7_sw_offset = 7 # macro +SDMA_PKT_WRITE_TILED_DW_7_sw_mask = 0x00000003 # macro +SDMA_PKT_WRITE_TILED_DW_7_sw_shift = 24 # macro +def SDMA_PKT_WRITE_TILED_DW_7_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_WRITE_TILED_COUNT_count_offset = 8 # macro +SDMA_PKT_WRITE_TILED_COUNT_count_mask = 0x000FFFFF # macro +SDMA_PKT_WRITE_TILED_COUNT_count_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_COUNT_COUNT(x): # macro + return (((x)&0x000FFFFF)<<0) +SDMA_PKT_WRITE_TILED_DATA0_data0_offset = 9 # macro +SDMA_PKT_WRITE_TILED_DATA0_data0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_TILED_DATA0_data0_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DATA0_DATA0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_HEADER_op_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_COPY_HEADER_op_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift = 31 # macro +def SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro +SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro +SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset = 5 # macro +SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset = 6 # macro +SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_COUNT_count_offset = 7 # macro +SDMA_PKT_PTEPDE_COPY_COUNT_count_mask = 0x0007FFFF # macro +SDMA_PKT_PTEPDE_COPY_COUNT_count_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x): # macro + return (((x)&0x0007FFFF)<<0) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask = 0x00000003 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift = 28 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x): # macro + return (((x)&0x00000003)<<28) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift = 30 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x): # macro + return (((x)&0x00000001)<<30) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift = 31 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset = 5 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset = 5 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift = 8 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset = 6 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask = 0x0001FFFF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x): # macro + return (((x)&0x0001FFFF)<<0) +SDMA_PKT_PTEPDE_RMW_HEADER_op_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_RMW_HEADER_op_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift = 19 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift = 20 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x): # macro + return (((x)&0x00000001)<<20) +SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift = 22 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x): # macro + return (((x)&0x00000001)<<22) +SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift = 23 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x): # macro + return (((x)&0x00000001)<<23) +SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset = 3 # macro +SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset = 4 # macro +SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset = 5 # macro +SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset = 6 # macro +SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_HEADER_op_offset = 0 # macro +SDMA_PKT_WRITE_INCR_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_WRITE_INCR_HEADER_op_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro +SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro +SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset = 3 # macro +SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset = 4 # macro +SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset = 5 # macro +SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset = 6 # macro +SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset = 7 # macro +SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset = 8 # macro +SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_COUNT_count_offset = 9 # macro +SDMA_PKT_WRITE_INCR_COUNT_count_mask = 0x0007FFFF # macro +SDMA_PKT_WRITE_INCR_COUNT_count_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_COUNT_COUNT(x): # macro + return (((x)&0x0007FFFF)<<0) +SDMA_PKT_INDIRECT_HEADER_op_offset = 0 # macro +SDMA_PKT_INDIRECT_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_INDIRECT_HEADER_op_shift = 0 # macro +def SDMA_PKT_INDIRECT_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_INDIRECT_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_INDIRECT_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_INDIRECT_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_INDIRECT_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_INDIRECT_HEADER_vmid_offset = 0 # macro +SDMA_PKT_INDIRECT_HEADER_vmid_mask = 0x0000000F # macro +SDMA_PKT_INDIRECT_HEADER_vmid_shift = 16 # macro +def SDMA_PKT_INDIRECT_HEADER_VMID(x): # macro + return (((x)&0x0000000F)<<16) +SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset = 1 # macro +SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift = 0 # macro +def SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset = 2 # macro +SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift = 0 # macro +def SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset = 3 # macro +SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask = 0x000FFFFF # macro +SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift = 0 # macro +def SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x): # macro + return (((x)&0x000FFFFF)<<0) +SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset = 4 # macro +SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift = 0 # macro +def SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset = 5 # macro +SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift = 0 # macro +def SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_SEMAPHORE_HEADER_op_offset = 0 # macro +SDMA_PKT_SEMAPHORE_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_SEMAPHORE_HEADER_op_shift = 0 # macro +def SDMA_PKT_SEMAPHORE_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_SEMAPHORE_HEADER_write_one_offset = 0 # macro +SDMA_PKT_SEMAPHORE_HEADER_write_one_mask = 0x00000001 # macro +SDMA_PKT_SEMAPHORE_HEADER_write_one_shift = 29 # macro +def SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x): # macro + return (((x)&0x00000001)<<29) +SDMA_PKT_SEMAPHORE_HEADER_signal_offset = 0 # macro +SDMA_PKT_SEMAPHORE_HEADER_signal_mask = 0x00000001 # macro +SDMA_PKT_SEMAPHORE_HEADER_signal_shift = 30 # macro +def SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x): # macro + return (((x)&0x00000001)<<30) +SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset = 0 # macro +SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask = 0x00000001 # macro +SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift = 31 # macro +def SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_FENCE_HEADER_op_offset = 0 # macro +SDMA_PKT_FENCE_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_FENCE_HEADER_op_shift = 0 # macro +def SDMA_PKT_FENCE_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_FENCE_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_FENCE_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_FENCE_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_FENCE_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_FENCE_DATA_data_offset = 3 # macro +SDMA_PKT_FENCE_DATA_data_mask = 0xFFFFFFFF # macro +SDMA_PKT_FENCE_DATA_data_shift = 0 # macro +def SDMA_PKT_FENCE_DATA_DATA(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_SRBM_WRITE_HEADER_op_offset = 0 # macro +SDMA_PKT_SRBM_WRITE_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_SRBM_WRITE_HEADER_op_shift = 0 # macro +def SDMA_PKT_SRBM_WRITE_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset = 0 # macro +SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask = 0x0000000F # macro +SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift = 28 # macro +def SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x): # macro + return (((x)&0x0000000F)<<28) +SDMA_PKT_SRBM_WRITE_ADDR_addr_offset = 1 # macro +SDMA_PKT_SRBM_WRITE_ADDR_addr_mask = 0x0003FFFF # macro +SDMA_PKT_SRBM_WRITE_ADDR_addr_shift = 0 # macro +def SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x): # macro + return (((x)&0x0003FFFF)<<0) +SDMA_PKT_SRBM_WRITE_DATA_data_offset = 2 # macro +SDMA_PKT_SRBM_WRITE_DATA_data_mask = 0xFFFFFFFF # macro +SDMA_PKT_SRBM_WRITE_DATA_data_shift = 0 # macro +def SDMA_PKT_SRBM_WRITE_DATA_DATA(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PRE_EXE_HEADER_op_offset = 0 # macro +SDMA_PKT_PRE_EXE_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_PRE_EXE_HEADER_op_shift = 0 # macro +def SDMA_PKT_PRE_EXE_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_PRE_EXE_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_PRE_EXE_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_PRE_EXE_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset = 0 # macro +SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask = 0x000000FF # macro +SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift = 16 # macro +def SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x): # macro + return (((x)&0x000000FF)<<16) +SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset = 1 # macro +SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro +SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift = 0 # macro +def SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COND_EXE_HEADER_op_offset = 0 # macro +SDMA_PKT_COND_EXE_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COND_EXE_HEADER_op_shift = 0 # macro +def SDMA_PKT_COND_EXE_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COND_EXE_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COND_EXE_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COND_EXE_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COND_EXE_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COND_EXE_REFERENCE_reference_offset = 3 # macro +SDMA_PKT_COND_EXE_REFERENCE_reference_mask = 0xFFFFFFFF # macro +SDMA_PKT_COND_EXE_REFERENCE_reference_shift = 0 # macro +def SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset = 4 # macro +SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro +SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift = 0 # macro +def SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_CONSTANT_FILL_HEADER_op_offset = 0 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_CONSTANT_FILL_HEADER_op_shift = 0 # macro +def SDMA_PKT_CONSTANT_FILL_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset = 0 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask = 0x00000003 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift = 16 # macro +def SDMA_PKT_CONSTANT_FILL_HEADER_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset = 0 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask = 0x00000003 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift = 30 # macro +def SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x): # macro + return (((x)&0x00000003)<<30) +SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro +SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro +SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset = 3 # macro +SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift = 0 # macro +def SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_CONSTANT_FILL_COUNT_count_offset = 4 # macro +SDMA_PKT_CONSTANT_FILL_COUNT_count_mask = 0x003FFFFF # macro +SDMA_PKT_CONSTANT_FILL_COUNT_count_shift = 0 # macro +def SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x): # macro + return (((x)&0x003FFFFF)<<0) +SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset = 0 # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift = 0 # macro +def SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset = 0 # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask = 0x00000001 # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift = 31 # macro +def SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset = 1 # macro +SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask = 0xFFFFFFFF # macro +SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift = 0 # macro +def SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset = 2 # macro +SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask = 0xFFFFFFFF # macro +SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift = 0 # macro +def SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset = 5 # macro +SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask = 0x03FFFFFF # macro +SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift = 0 # macro +def SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x): # macro + return (((x)&0x03FFFFFF)<<0) +SDMA_PKT_POLL_REGMEM_HEADER_op_offset = 0 # macro +SDMA_PKT_POLL_REGMEM_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_REGMEM_HEADER_op_shift = 0 # macro +def SDMA_PKT_POLL_REGMEM_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset = 0 # macro +SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask = 0x00000001 # macro +SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift = 26 # macro +def SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x): # macro + return (((x)&0x00000001)<<26) +SDMA_PKT_POLL_REGMEM_HEADER_func_offset = 0 # macro +SDMA_PKT_POLL_REGMEM_HEADER_func_mask = 0x00000007 # macro +SDMA_PKT_POLL_REGMEM_HEADER_func_shift = 28 # macro +def SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x): # macro + return (((x)&0x00000007)<<28) +SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset = 0 # macro +SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask = 0x00000001 # macro +SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift = 31 # macro +def SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_REGMEM_VALUE_value_offset = 3 # macro +SDMA_PKT_POLL_REGMEM_VALUE_value_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_REGMEM_VALUE_value_shift = 0 # macro +def SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_REGMEM_MASK_mask_offset = 4 # macro +SDMA_PKT_POLL_REGMEM_MASK_mask_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_REGMEM_MASK_mask_shift = 0 # macro +def SDMA_PKT_POLL_REGMEM_MASK_MASK(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_REGMEM_DW5_interval_offset = 5 # macro +SDMA_PKT_POLL_REGMEM_DW5_interval_mask = 0x0000FFFF # macro +SDMA_PKT_POLL_REGMEM_DW5_interval_shift = 0 # macro +def SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x): # macro + return (((x)&0x0000FFFF)<<0) +SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset = 5 # macro +SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask = 0x00000FFF # macro +SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift = 16 # macro +def SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x): # macro + return (((x)&0x00000FFF)<<16) +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset = 0 # macro +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift = 0 # macro +def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset = 1 # macro +SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask = 0x3FFFFFFF # macro +SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift = 2 # macro +def SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x): # macro + return (((x)&0x3FFFFFFF)<<2) +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 2 # macro +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 3 # macro +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset = 0 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift = 0 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset = 0 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask = 0x00000003 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift = 16 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset = 3 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask = 0x0FFFFFFF # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift = 4 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x): # macro + return (((x)&0x0FFFFFFF)<<4) +SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset = 4 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift = 0 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset = 0 # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset = 0 # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask = 0x00000001 # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift = 31 # macro +def SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset = 1 # macro +SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset = 2 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset = 3 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset = 4 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset = 5 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset = 6 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset = 7 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset = 8 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset = 9 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset = 10 # macro +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset = 11 # macro +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset = 12 # macro +SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_ATOMIC_HEADER_op_offset = 0 # macro +SDMA_PKT_ATOMIC_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_ATOMIC_HEADER_op_shift = 0 # macro +def SDMA_PKT_ATOMIC_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_ATOMIC_HEADER_loop_offset = 0 # macro +SDMA_PKT_ATOMIC_HEADER_loop_mask = 0x00000001 # macro +SDMA_PKT_ATOMIC_HEADER_loop_shift = 16 # macro +def SDMA_PKT_ATOMIC_HEADER_LOOP(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_ATOMIC_HEADER_tmz_offset = 0 # macro +SDMA_PKT_ATOMIC_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_ATOMIC_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_ATOMIC_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_ATOMIC_HEADER_atomic_op_offset = 0 # macro +SDMA_PKT_ATOMIC_HEADER_atomic_op_mask = 0x0000007F # macro +SDMA_PKT_ATOMIC_HEADER_atomic_op_shift = 25 # macro +def SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x): # macro + return (((x)&0x0000007F)<<25) +SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset = 3 # macro +SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift = 0 # macro +def SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset = 4 # macro +SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift = 0 # macro +def SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset = 5 # macro +SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift = 0 # macro +def SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset = 6 # macro +SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift = 0 # macro +def SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset = 7 # macro +SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask = 0x00001FFF # macro +SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift = 0 # macro +def SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x): # macro + return (((x)&0x00001FFF)<<0) +SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset = 0 # macro +SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift = 0 # macro +def SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset = 1 # macro +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift = 0 # macro +def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset = 2 # macro +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift = 0 # macro +def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset = 0 # macro +SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift = 0 # macro +def SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro +def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro + return (((x)&0x1FFFFFFF)<<3) +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro +def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset = 0 # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift = 0 # macro +def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro +def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro + return (((x)&0x1FFFFFFF)<<3) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro +def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_TRAP_HEADER_op_offset = 0 # macro +SDMA_PKT_TRAP_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_TRAP_HEADER_op_shift = 0 # macro +def SDMA_PKT_TRAP_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_TRAP_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_TRAP_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_TRAP_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_TRAP_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset = 1 # macro +SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro +SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift = 0 # macro +def SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro + return (((x)&0x0FFFFFFF)<<0) +SDMA_PKT_DUMMY_TRAP_HEADER_op_offset = 0 # macro +SDMA_PKT_DUMMY_TRAP_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_DUMMY_TRAP_HEADER_op_shift = 0 # macro +def SDMA_PKT_DUMMY_TRAP_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset = 1 # macro +SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro +SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift = 0 # macro +def SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro + return (((x)&0x0FFFFFFF)<<0) +SDMA_PKT_NOP_HEADER_op_offset = 0 # macro +SDMA_PKT_NOP_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_NOP_HEADER_op_shift = 0 # macro +def SDMA_PKT_NOP_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_NOP_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_NOP_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_NOP_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_NOP_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_NOP_HEADER_count_offset = 0 # macro +SDMA_PKT_NOP_HEADER_count_mask = 0x00003FFF # macro +SDMA_PKT_NOP_HEADER_count_shift = 16 # macro +def SDMA_PKT_NOP_HEADER_COUNT(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_NOP_DATA0_data0_offset = 1 # macro +SDMA_PKT_NOP_DATA0_data0_mask = 0xFFFFFFFF # macro +SDMA_PKT_NOP_DATA0_data0_shift = 0 # macro +def SDMA_PKT_NOP_DATA0_DATA0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_HEADER_HEADER_format_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_format_mask = 0x000000FF # macro +SDMA_AQL_PKT_HEADER_HEADER_format_shift = 0 # macro +def SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_AQL_PKT_HEADER_HEADER_barrier_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_barrier_mask = 0x00000001 # macro +SDMA_AQL_PKT_HEADER_HEADER_barrier_shift = 8 # macro +def SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x): # macro + return (((x)&0x00000001)<<8) +SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask = 0x00000003 # macro +SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift = 9 # macro +def SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro + return (((x)&0x00000003)<<9) +SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask = 0x00000003 # macro +SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift = 11 # macro +def SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x): # macro + return (((x)&0x00000003)<<11) +SDMA_AQL_PKT_HEADER_HEADER_reserved_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_reserved_mask = 0x00000007 # macro +SDMA_AQL_PKT_HEADER_HEADER_reserved_shift = 13 # macro +def SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x): # macro + return (((x)&0x00000007)<<13) +SDMA_AQL_PKT_HEADER_HEADER_op_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_op_mask = 0x0000000F # macro +SDMA_AQL_PKT_HEADER_HEADER_op_shift = 16 # macro +def SDMA_AQL_PKT_HEADER_HEADER_OP(x): # macro + return (((x)&0x0000000F)<<16) +SDMA_AQL_PKT_HEADER_HEADER_subop_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_subop_mask = 0x00000007 # macro +SDMA_AQL_PKT_HEADER_HEADER_subop_shift = 20 # macro +def SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x): # macro + return (((x)&0x00000007)<<20) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask = 0x000000FF # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask = 0x00000001 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift = 8 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x): # macro + return (((x)&0x00000001)<<8) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift = 9 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro + return (((x)&0x00000003)<<9) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask = 0x00000003 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift = 11 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x): # macro + return (((x)&0x00000003)<<11) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask = 0x00000007 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift = 13 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x): # macro + return (((x)&0x00000007)<<13) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask = 0x0000000F # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift = 16 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x): # macro + return (((x)&0x0000000F)<<16) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask = 0x00000007 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift = 20 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x): # macro + return (((x)&0x00000007)<<20) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset = 1 # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset = 2 # macro +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset = 3 # macro +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset = 4 # macro +SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro + return (((x)&0x003FFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 5 # macro +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro +def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 5 # macro +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro +def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 6 # macro +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 7 # macro +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 8 # macro +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 9 # macro +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset = 10 # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset = 11 # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset = 12 # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset = 13 # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask = 0x000000FF # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask = 0x00000001 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift = 8 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x): # macro + return (((x)&0x00000001)<<8) +SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift = 9 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro + return (((x)&0x00000003)<<9) +SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask = 0x00000003 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift = 11 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x): # macro + return (((x)&0x00000003)<<11) +SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask = 0x00000007 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift = 13 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x): # macro + return (((x)&0x00000007)<<13) +SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask = 0x0000000F # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift = 16 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x): # macro + return (((x)&0x0000000F)<<16) +SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask = 0x00000007 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift = 20 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x): # macro + return (((x)&0x00000007)<<20) +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset = 1 # macro +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset = 2 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset = 3 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset = 4 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset = 5 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset = 6 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset = 7 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset = 8 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset = 9 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset = 10 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset = 11 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset = 12 # macro +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset = 13 # macro +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +__all__ = \ + ['HEADER_AGENT_DISPATCH', 'HEADER_BARRIER', + 'HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_', + 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', + 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', + 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', + 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', + 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', + 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_barrier_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_barrier_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_barrier_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_format_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_format_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_format_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_op_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_op_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_op_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_reserved_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_reserved_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_reserved_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_subop_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_subop_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_subop_shift', 'SDMA_ATOMIC_ADD64', + 'SDMA_OP_AQL_BARRIER_OR', 'SDMA_OP_AQL_COPY', 'SDMA_OP_ATOMIC', + 'SDMA_OP_COND_EXE', 'SDMA_OP_CONST_FILL', 'SDMA_OP_COPY', + 'SDMA_OP_DUMMY_TRAP', 'SDMA_OP_FENCE', 'SDMA_OP_GCR', + 'SDMA_OP_INDIRECT', 'SDMA_OP_NOP', 'SDMA_OP_POLL_REGMEM', + 'SDMA_OP_PRE_EXE', 'SDMA_OP_PTEPDE', 'SDMA_OP_SEM', + 'SDMA_OP_SRBM_WRITE', 'SDMA_OP_TIMESTAMP', 'SDMA_OP_TRAP', + 'SDMA_OP_WRITE', 'SDMA_PKT_ATOMIC', + 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask', + 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset', + 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift', + 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask', + 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset', + 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift', + 'SDMA_PKT_ATOMIC_HEADER_atomic_op_mask', + 'SDMA_PKT_ATOMIC_HEADER_atomic_op_offset', + 'SDMA_PKT_ATOMIC_HEADER_atomic_op_shift', + 'SDMA_PKT_ATOMIC_HEADER_loop_mask', + 'SDMA_PKT_ATOMIC_HEADER_loop_offset', + 'SDMA_PKT_ATOMIC_HEADER_loop_shift', + 'SDMA_PKT_ATOMIC_HEADER_op_mask', + 'SDMA_PKT_ATOMIC_HEADER_op_offset', + 'SDMA_PKT_ATOMIC_HEADER_op_shift', + 'SDMA_PKT_ATOMIC_HEADER_tmz_mask', + 'SDMA_PKT_ATOMIC_HEADER_tmz_offset', + 'SDMA_PKT_ATOMIC_HEADER_tmz_shift', + 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask', + 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset', + 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift', + 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask', + 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset', + 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift', + 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask', + 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset', + 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift', + 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask', + 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset', + 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift', + 'SDMA_PKT_COND_EXE_HEADER_op_mask', + 'SDMA_PKT_COND_EXE_HEADER_op_offset', + 'SDMA_PKT_COND_EXE_HEADER_op_shift', + 'SDMA_PKT_COND_EXE_HEADER_sub_op_mask', + 'SDMA_PKT_COND_EXE_HEADER_sub_op_offset', + 'SDMA_PKT_COND_EXE_HEADER_sub_op_shift', + 'SDMA_PKT_COND_EXE_REFERENCE_reference_mask', + 'SDMA_PKT_COND_EXE_REFERENCE_reference_offset', + 'SDMA_PKT_COND_EXE_REFERENCE_reference_shift', + 'SDMA_PKT_CONSTANT_FILL', + 'SDMA_PKT_CONSTANT_FILL_COUNT_count_mask', + 'SDMA_PKT_CONSTANT_FILL_COUNT_count_offset', + 'SDMA_PKT_CONSTANT_FILL_COUNT_count_shift', + 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask', + 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset', + 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift', + 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask', + 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset', + 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift', + 'SDMA_PKT_CONSTANT_FILL_HEADER_op_mask', + 'SDMA_PKT_CONSTANT_FILL_HEADER_op_offset', + 'SDMA_PKT_CONSTANT_FILL_HEADER_op_shift', + 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask', + 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset', + 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift', + 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask', + 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset', + 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift', + 'SDMA_PKT_COPY_LINEAR', 'SDMA_PKT_COPY_LINEAR_COUNT_count_mask', + 'SDMA_PKT_COPY_LINEAR_COUNT_count_offset', + 'SDMA_PKT_COPY_LINEAR_COUNT_count_shift', + 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask', + 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset', + 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift', + 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask', + 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset', + 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift', + 'SDMA_PKT_COPY_LINEAR_HEADER_op_mask', + 'SDMA_PKT_COPY_LINEAR_HEADER_op_offset', + 'SDMA_PKT_COPY_LINEAR_HEADER_op_shift', + 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask', + 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset', + 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', + 'SDMA_PKT_COPY_LINEAR_RECT', + 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_STRUCT_COUNT_count_mask', + 'SDMA_PKT_COPY_STRUCT_COUNT_count_offset', + 'SDMA_PKT_COPY_STRUCT_COUNT_count_shift', + 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask', + 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset', + 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift', + 'SDMA_PKT_COPY_STRUCT_DW_5_stride_mask', + 'SDMA_PKT_COPY_STRUCT_DW_5_stride_offset', + 'SDMA_PKT_COPY_STRUCT_DW_5_stride_shift', + 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask', + 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset', + 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift', + 'SDMA_PKT_COPY_STRUCT_HEADER_detile_mask', + 'SDMA_PKT_COPY_STRUCT_HEADER_detile_offset', + 'SDMA_PKT_COPY_STRUCT_HEADER_detile_shift', + 'SDMA_PKT_COPY_STRUCT_HEADER_op_mask', + 'SDMA_PKT_COPY_STRUCT_HEADER_op_offset', + 'SDMA_PKT_COPY_STRUCT_HEADER_op_shift', + 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask', + 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset', + 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift', + 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask', + 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset', + 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift', + 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask', + 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset', + 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift', + 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask', + 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset', + 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift', + 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask', + 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset', + 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift', + 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask', + 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset', + 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift', + 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_COPY_T2T_DW_10_dst_width_mask', + 'SDMA_PKT_COPY_T2T_DW_10_dst_width_offset', + 'SDMA_PKT_COPY_T2T_DW_10_dst_width_shift', + 'SDMA_PKT_COPY_T2T_DW_10_dst_z_mask', + 'SDMA_PKT_COPY_T2T_DW_10_dst_z_offset', + 'SDMA_PKT_COPY_T2T_DW_10_dst_z_shift', + 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask', + 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset', + 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift', + 'SDMA_PKT_COPY_T2T_DW_11_dst_height_mask', + 'SDMA_PKT_COPY_T2T_DW_11_dst_height_offset', + 'SDMA_PKT_COPY_T2T_DW_11_dst_height_shift', + 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask', + 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset', + 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift', + 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask', + 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset', + 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift', + 'SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask', + 'SDMA_PKT_COPY_T2T_DW_12_dst_epitch_offset', + 'SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift', + 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask', + 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset', + 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift', + 'SDMA_PKT_COPY_T2T_DW_13_rect_x_mask', + 'SDMA_PKT_COPY_T2T_DW_13_rect_x_offset', + 'SDMA_PKT_COPY_T2T_DW_13_rect_x_shift', + 'SDMA_PKT_COPY_T2T_DW_13_rect_y_mask', + 'SDMA_PKT_COPY_T2T_DW_13_rect_y_offset', + 'SDMA_PKT_COPY_T2T_DW_13_rect_y_shift', + 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask', + 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset', + 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift', + 'SDMA_PKT_COPY_T2T_DW_14_rect_z_mask', + 'SDMA_PKT_COPY_T2T_DW_14_rect_z_offset', + 'SDMA_PKT_COPY_T2T_DW_14_rect_z_shift', + 'SDMA_PKT_COPY_T2T_DW_14_src_sw_mask', + 'SDMA_PKT_COPY_T2T_DW_14_src_sw_offset', + 'SDMA_PKT_COPY_T2T_DW_14_src_sw_shift', + 'SDMA_PKT_COPY_T2T_DW_3_src_x_mask', + 'SDMA_PKT_COPY_T2T_DW_3_src_x_offset', + 'SDMA_PKT_COPY_T2T_DW_3_src_x_shift', + 'SDMA_PKT_COPY_T2T_DW_3_src_y_mask', + 'SDMA_PKT_COPY_T2T_DW_3_src_y_offset', + 'SDMA_PKT_COPY_T2T_DW_3_src_y_shift', + 'SDMA_PKT_COPY_T2T_DW_4_src_width_mask', + 'SDMA_PKT_COPY_T2T_DW_4_src_width_offset', + 'SDMA_PKT_COPY_T2T_DW_4_src_width_shift', + 'SDMA_PKT_COPY_T2T_DW_4_src_z_mask', + 'SDMA_PKT_COPY_T2T_DW_4_src_z_offset', + 'SDMA_PKT_COPY_T2T_DW_4_src_z_shift', + 'SDMA_PKT_COPY_T2T_DW_5_src_depth_mask', + 'SDMA_PKT_COPY_T2T_DW_5_src_depth_offset', + 'SDMA_PKT_COPY_T2T_DW_5_src_depth_shift', + 'SDMA_PKT_COPY_T2T_DW_5_src_height_mask', + 'SDMA_PKT_COPY_T2T_DW_5_src_height_offset', + 'SDMA_PKT_COPY_T2T_DW_5_src_height_shift', + 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask', + 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset', + 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift', + 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask', + 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset', + 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift', + 'SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask', + 'SDMA_PKT_COPY_T2T_DW_6_src_epitch_offset', + 'SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift', + 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask', + 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset', + 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift', + 'SDMA_PKT_COPY_T2T_DW_9_dst_x_mask', + 'SDMA_PKT_COPY_T2T_DW_9_dst_x_offset', + 'SDMA_PKT_COPY_T2T_DW_9_dst_x_shift', + 'SDMA_PKT_COPY_T2T_DW_9_dst_y_mask', + 'SDMA_PKT_COPY_T2T_DW_9_dst_y_offset', + 'SDMA_PKT_COPY_T2T_DW_9_dst_y_shift', + 'SDMA_PKT_COPY_T2T_HEADER_mip_max_mask', + 'SDMA_PKT_COPY_T2T_HEADER_mip_max_offset', + 'SDMA_PKT_COPY_T2T_HEADER_mip_max_shift', + 'SDMA_PKT_COPY_T2T_HEADER_op_mask', + 'SDMA_PKT_COPY_T2T_HEADER_op_offset', + 'SDMA_PKT_COPY_T2T_HEADER_op_shift', + 'SDMA_PKT_COPY_T2T_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_T2T_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_T2T_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_T2T_HEADER_tmz_mask', + 'SDMA_PKT_COPY_T2T_HEADER_tmz_offset', + 'SDMA_PKT_COPY_T2T_HEADER_tmz_shift', + 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_TILED_COUNT_count_mask', + 'SDMA_PKT_COPY_TILED_COUNT_count_offset', + 'SDMA_PKT_COPY_TILED_COUNT_count_shift', + 'SDMA_PKT_COPY_TILED_DW_3_width_mask', + 'SDMA_PKT_COPY_TILED_DW_3_width_offset', + 'SDMA_PKT_COPY_TILED_DW_3_width_shift', + 'SDMA_PKT_COPY_TILED_DW_4_depth_mask', + 'SDMA_PKT_COPY_TILED_DW_4_depth_offset', + 'SDMA_PKT_COPY_TILED_DW_4_depth_shift', + 'SDMA_PKT_COPY_TILED_DW_4_height_mask', + 'SDMA_PKT_COPY_TILED_DW_4_height_offset', + 'SDMA_PKT_COPY_TILED_DW_4_height_shift', + 'SDMA_PKT_COPY_TILED_DW_5_dimension_mask', + 'SDMA_PKT_COPY_TILED_DW_5_dimension_offset', + 'SDMA_PKT_COPY_TILED_DW_5_dimension_shift', + 'SDMA_PKT_COPY_TILED_DW_5_element_size_mask', + 'SDMA_PKT_COPY_TILED_DW_5_element_size_offset', + 'SDMA_PKT_COPY_TILED_DW_5_element_size_shift', + 'SDMA_PKT_COPY_TILED_DW_5_epitch_mask', + 'SDMA_PKT_COPY_TILED_DW_5_epitch_offset', + 'SDMA_PKT_COPY_TILED_DW_5_epitch_shift', + 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask', + 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset', + 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift', + 'SDMA_PKT_COPY_TILED_DW_6_x_mask', + 'SDMA_PKT_COPY_TILED_DW_6_x_offset', + 'SDMA_PKT_COPY_TILED_DW_6_x_shift', + 'SDMA_PKT_COPY_TILED_DW_6_y_mask', + 'SDMA_PKT_COPY_TILED_DW_6_y_offset', + 'SDMA_PKT_COPY_TILED_DW_6_y_shift', + 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask', + 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset', + 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift', + 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask', + 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset', + 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift', + 'SDMA_PKT_COPY_TILED_DW_7_z_mask', + 'SDMA_PKT_COPY_TILED_DW_7_z_offset', + 'SDMA_PKT_COPY_TILED_DW_7_z_shift', + 'SDMA_PKT_COPY_TILED_HEADER_detile_mask', + 'SDMA_PKT_COPY_TILED_HEADER_detile_offset', + 'SDMA_PKT_COPY_TILED_HEADER_detile_shift', + 'SDMA_PKT_COPY_TILED_HEADER_encrypt_mask', + 'SDMA_PKT_COPY_TILED_HEADER_encrypt_offset', + 'SDMA_PKT_COPY_TILED_HEADER_encrypt_shift', + 'SDMA_PKT_COPY_TILED_HEADER_mip_max_mask', + 'SDMA_PKT_COPY_TILED_HEADER_mip_max_offset', + 'SDMA_PKT_COPY_TILED_HEADER_mip_max_shift', + 'SDMA_PKT_COPY_TILED_HEADER_op_mask', + 'SDMA_PKT_COPY_TILED_HEADER_op_offset', + 'SDMA_PKT_COPY_TILED_HEADER_op_shift', + 'SDMA_PKT_COPY_TILED_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_TILED_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_TILED_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_TILED_HEADER_tmz_mask', + 'SDMA_PKT_COPY_TILED_HEADER_tmz_offset', + 'SDMA_PKT_COPY_TILED_HEADER_tmz_shift', + 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask', + 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset', + 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift', + 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask', + 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset', + 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift', + 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask', + 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset', + 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift', + 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', + 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', + 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift', + 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask', + 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset', + 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift', + 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask', + 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset', + 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift', + 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask', + 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset', + 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift', + 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask', + 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset', + 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift', + 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask', + 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset', + 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift', + 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift', + 'SDMA_PKT_DUMMY_TRAP_HEADER_op_mask', + 'SDMA_PKT_DUMMY_TRAP_HEADER_op_offset', + 'SDMA_PKT_DUMMY_TRAP_HEADER_op_shift', + 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask', + 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset', + 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift', + 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask', + 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset', + 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift', + 'SDMA_PKT_FENCE', 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_FENCE_DATA_data_mask', + 'SDMA_PKT_FENCE_DATA_data_offset', + 'SDMA_PKT_FENCE_DATA_data_shift', 'SDMA_PKT_FENCE_HEADER_op_mask', + 'SDMA_PKT_FENCE_HEADER_op_offset', + 'SDMA_PKT_FENCE_HEADER_op_shift', + 'SDMA_PKT_FENCE_HEADER_sub_op_mask', + 'SDMA_PKT_FENCE_HEADER_sub_op_offset', + 'SDMA_PKT_FENCE_HEADER_sub_op_shift', 'SDMA_PKT_GCR', + 'SDMA_PKT_HDP_FLUSH', 'SDMA_PKT_HEADER_op_mask', + 'SDMA_PKT_HEADER_op_offset', 'SDMA_PKT_HEADER_op_shift', + 'SDMA_PKT_HEADER_sub_op_mask', 'SDMA_PKT_HEADER_sub_op_offset', + 'SDMA_PKT_HEADER_sub_op_shift', + 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask', + 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset', + 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift', + 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask', + 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset', + 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift', + 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask', + 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset', + 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift', + 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask', + 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset', + 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift', + 'SDMA_PKT_INDIRECT_HEADER_op_mask', + 'SDMA_PKT_INDIRECT_HEADER_op_offset', + 'SDMA_PKT_INDIRECT_HEADER_op_shift', + 'SDMA_PKT_INDIRECT_HEADER_sub_op_mask', + 'SDMA_PKT_INDIRECT_HEADER_sub_op_offset', + 'SDMA_PKT_INDIRECT_HEADER_sub_op_shift', + 'SDMA_PKT_INDIRECT_HEADER_vmid_mask', + 'SDMA_PKT_INDIRECT_HEADER_vmid_offset', + 'SDMA_PKT_INDIRECT_HEADER_vmid_shift', + 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask', + 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset', + 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift', + 'SDMA_PKT_NOP_DATA0_data0_mask', + 'SDMA_PKT_NOP_DATA0_data0_offset', + 'SDMA_PKT_NOP_DATA0_data0_shift', + 'SDMA_PKT_NOP_HEADER_count_mask', + 'SDMA_PKT_NOP_HEADER_count_offset', + 'SDMA_PKT_NOP_HEADER_count_shift', 'SDMA_PKT_NOP_HEADER_op_mask', + 'SDMA_PKT_NOP_HEADER_op_offset', 'SDMA_PKT_NOP_HEADER_op_shift', + 'SDMA_PKT_NOP_HEADER_sub_op_mask', + 'SDMA_PKT_NOP_HEADER_sub_op_offset', + 'SDMA_PKT_NOP_HEADER_sub_op_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift', + 'SDMA_PKT_POLL_REGMEM', + 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_POLL_REGMEM_DW5_interval_mask', + 'SDMA_PKT_POLL_REGMEM_DW5_interval_offset', + 'SDMA_PKT_POLL_REGMEM_DW5_interval_shift', + 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask', + 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset', + 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift', + 'SDMA_PKT_POLL_REGMEM_HEADER_func_mask', + 'SDMA_PKT_POLL_REGMEM_HEADER_func_offset', + 'SDMA_PKT_POLL_REGMEM_HEADER_func_shift', + 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask', + 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset', + 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift', + 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask', + 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset', + 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift', + 'SDMA_PKT_POLL_REGMEM_HEADER_op_mask', + 'SDMA_PKT_POLL_REGMEM_HEADER_op_offset', + 'SDMA_PKT_POLL_REGMEM_HEADER_op_shift', + 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask', + 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset', + 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift', + 'SDMA_PKT_POLL_REGMEM_MASK_mask_mask', + 'SDMA_PKT_POLL_REGMEM_MASK_mask_offset', + 'SDMA_PKT_POLL_REGMEM_MASK_mask_shift', + 'SDMA_PKT_POLL_REGMEM_VALUE_value_mask', + 'SDMA_PKT_POLL_REGMEM_VALUE_value_offset', + 'SDMA_PKT_POLL_REGMEM_VALUE_value_shift', + 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift', + 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask', + 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset', + 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift', + 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask', + 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset', + 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift', + 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask', + 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset', + 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift', + 'SDMA_PKT_PRE_EXE_HEADER_op_mask', + 'SDMA_PKT_PRE_EXE_HEADER_op_offset', + 'SDMA_PKT_PRE_EXE_HEADER_op_shift', + 'SDMA_PKT_PRE_EXE_HEADER_sub_op_mask', + 'SDMA_PKT_PRE_EXE_HEADER_sub_op_offset', + 'SDMA_PKT_PRE_EXE_HEADER_sub_op_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_PTEPDE_COPY_COUNT_count_mask', + 'SDMA_PKT_PTEPDE_COPY_COUNT_count_offset', + 'SDMA_PKT_PTEPDE_COPY_COUNT_count_shift', + 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_PTEPDE_COPY_HEADER_op_mask', + 'SDMA_PKT_PTEPDE_COPY_HEADER_op_offset', + 'SDMA_PKT_PTEPDE_COPY_HEADER_op_shift', + 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask', + 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset', + 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift', + 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask', + 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset', + 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift', + 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask', + 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset', + 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift', + 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask', + 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset', + 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift', + 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_op_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_op_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_op_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift', + 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask', + 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset', + 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift', + 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask', + 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset', + 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift', + 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask', + 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset', + 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift', + 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask', + 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset', + 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift', + 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask', + 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset', + 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift', + 'SDMA_PKT_SEMAPHORE_HEADER_op_mask', + 'SDMA_PKT_SEMAPHORE_HEADER_op_offset', + 'SDMA_PKT_SEMAPHORE_HEADER_op_shift', + 'SDMA_PKT_SEMAPHORE_HEADER_signal_mask', + 'SDMA_PKT_SEMAPHORE_HEADER_signal_offset', + 'SDMA_PKT_SEMAPHORE_HEADER_signal_shift', + 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask', + 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset', + 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift', + 'SDMA_PKT_SEMAPHORE_HEADER_write_one_mask', + 'SDMA_PKT_SEMAPHORE_HEADER_write_one_offset', + 'SDMA_PKT_SEMAPHORE_HEADER_write_one_shift', + 'SDMA_PKT_SRBM_WRITE_ADDR_addr_mask', + 'SDMA_PKT_SRBM_WRITE_ADDR_addr_offset', + 'SDMA_PKT_SRBM_WRITE_ADDR_addr_shift', + 'SDMA_PKT_SRBM_WRITE_DATA_data_mask', + 'SDMA_PKT_SRBM_WRITE_DATA_data_offset', + 'SDMA_PKT_SRBM_WRITE_DATA_data_shift', + 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask', + 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset', + 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift', + 'SDMA_PKT_SRBM_WRITE_HEADER_op_mask', + 'SDMA_PKT_SRBM_WRITE_HEADER_op_offset', + 'SDMA_PKT_SRBM_WRITE_HEADER_op_shift', + 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask', + 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset', + 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift', 'SDMA_PKT_TIMESTAMP', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift', + 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask', + 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset', + 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift', + 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask', + 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset', + 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift', + 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask', + 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset', + 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift', + 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask', + 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset', + 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift', + 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask', + 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset', + 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift', + 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask', + 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset', + 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift', + 'SDMA_PKT_TRAP', 'SDMA_PKT_TRAP_HEADER_op_mask', + 'SDMA_PKT_TRAP_HEADER_op_offset', 'SDMA_PKT_TRAP_HEADER_op_shift', + 'SDMA_PKT_TRAP_HEADER_sub_op_mask', + 'SDMA_PKT_TRAP_HEADER_sub_op_offset', + 'SDMA_PKT_TRAP_HEADER_sub_op_shift', + 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask', + 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset', + 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift', + 'SDMA_PKT_WRITE_INCR_COUNT_count_mask', + 'SDMA_PKT_WRITE_INCR_COUNT_count_offset', + 'SDMA_PKT_WRITE_INCR_COUNT_count_shift', + 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_WRITE_INCR_HEADER_op_mask', + 'SDMA_PKT_WRITE_INCR_HEADER_op_offset', + 'SDMA_PKT_WRITE_INCR_HEADER_op_shift', + 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask', + 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset', + 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift', + 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask', + 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset', + 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift', + 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask', + 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset', + 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift', + 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask', + 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset', + 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift', + 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask', + 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset', + 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift', + 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask', + 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset', + 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift', + 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask', + 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset', + 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift', + 'SDMA_PKT_WRITE_TILED_COUNT_count_mask', + 'SDMA_PKT_WRITE_TILED_COUNT_count_offset', + 'SDMA_PKT_WRITE_TILED_COUNT_count_shift', + 'SDMA_PKT_WRITE_TILED_DATA0_data0_mask', + 'SDMA_PKT_WRITE_TILED_DATA0_data0_offset', + 'SDMA_PKT_WRITE_TILED_DATA0_data0_shift', + 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_WRITE_TILED_DW_3_width_mask', + 'SDMA_PKT_WRITE_TILED_DW_3_width_offset', + 'SDMA_PKT_WRITE_TILED_DW_3_width_shift', + 'SDMA_PKT_WRITE_TILED_DW_4_depth_mask', + 'SDMA_PKT_WRITE_TILED_DW_4_depth_offset', + 'SDMA_PKT_WRITE_TILED_DW_4_depth_shift', + 'SDMA_PKT_WRITE_TILED_DW_4_height_mask', + 'SDMA_PKT_WRITE_TILED_DW_4_height_offset', + 'SDMA_PKT_WRITE_TILED_DW_4_height_shift', + 'SDMA_PKT_WRITE_TILED_DW_5_dimension_mask', + 'SDMA_PKT_WRITE_TILED_DW_5_dimension_offset', + 'SDMA_PKT_WRITE_TILED_DW_5_dimension_shift', + 'SDMA_PKT_WRITE_TILED_DW_5_element_size_mask', + 'SDMA_PKT_WRITE_TILED_DW_5_element_size_offset', + 'SDMA_PKT_WRITE_TILED_DW_5_element_size_shift', + 'SDMA_PKT_WRITE_TILED_DW_5_epitch_mask', + 'SDMA_PKT_WRITE_TILED_DW_5_epitch_offset', + 'SDMA_PKT_WRITE_TILED_DW_5_epitch_shift', + 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask', + 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset', + 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift', + 'SDMA_PKT_WRITE_TILED_DW_6_x_mask', + 'SDMA_PKT_WRITE_TILED_DW_6_x_offset', + 'SDMA_PKT_WRITE_TILED_DW_6_x_shift', + 'SDMA_PKT_WRITE_TILED_DW_6_y_mask', + 'SDMA_PKT_WRITE_TILED_DW_6_y_offset', + 'SDMA_PKT_WRITE_TILED_DW_6_y_shift', + 'SDMA_PKT_WRITE_TILED_DW_7_sw_mask', + 'SDMA_PKT_WRITE_TILED_DW_7_sw_offset', + 'SDMA_PKT_WRITE_TILED_DW_7_sw_shift', + 'SDMA_PKT_WRITE_TILED_DW_7_z_mask', + 'SDMA_PKT_WRITE_TILED_DW_7_z_offset', + 'SDMA_PKT_WRITE_TILED_DW_7_z_shift', + 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask', + 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset', + 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift', + 'SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask', + 'SDMA_PKT_WRITE_TILED_HEADER_mip_max_offset', + 'SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift', + 'SDMA_PKT_WRITE_TILED_HEADER_op_mask', + 'SDMA_PKT_WRITE_TILED_HEADER_op_offset', + 'SDMA_PKT_WRITE_TILED_HEADER_op_shift', + 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask', + 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset', + 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift', + 'SDMA_PKT_WRITE_TILED_HEADER_tmz_mask', + 'SDMA_PKT_WRITE_TILED_HEADER_tmz_offset', + 'SDMA_PKT_WRITE_TILED_HEADER_tmz_shift', + 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask', + 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset', + 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift', + 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_WRITE_UNTILED_DW_3_count_mask', + 'SDMA_PKT_WRITE_UNTILED_DW_3_count_offset', + 'SDMA_PKT_WRITE_UNTILED_DW_3_count_shift', + 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask', + 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset', + 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift', + 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask', + 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset', + 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift', + 'SDMA_PKT_WRITE_UNTILED_HEADER_op_mask', + 'SDMA_PKT_WRITE_UNTILED_HEADER_op_offset', + 'SDMA_PKT_WRITE_UNTILED_HEADER_op_shift', + 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask', + 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset', + 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift', + 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask', + 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset', + 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift', + 'SDMA_SUBOP_COPY_DIRTY_PAGE', 'SDMA_SUBOP_COPY_LINEAR', + 'SDMA_SUBOP_COPY_LINEAR_PHY', 'SDMA_SUBOP_COPY_LINEAR_RECT', + 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND', 'SDMA_SUBOP_COPY_SOA', + 'SDMA_SUBOP_COPY_T2T_SUB_WIND', 'SDMA_SUBOP_COPY_TILED', + 'SDMA_SUBOP_COPY_TILED_SUB_WIND', 'SDMA_SUBOP_DATA_FILL_MULTI', + 'SDMA_SUBOP_POLL_DBIT_WRITE_MEM', 'SDMA_SUBOP_POLL_MEM_VERIFY', + 'SDMA_SUBOP_POLL_REG_WRITE_MEM', 'SDMA_SUBOP_PTEPDE_COPY', + 'SDMA_SUBOP_PTEPDE_COPY_BACKWARDS', 'SDMA_SUBOP_PTEPDE_GEN', + 'SDMA_SUBOP_PTEPDE_RMW', 'SDMA_SUBOP_TIMESTAMP_GET', + 'SDMA_SUBOP_TIMESTAMP_GET_GLOBAL', 'SDMA_SUBOP_TIMESTAMP_SET', + 'SDMA_SUBOP_USER_GCR', 'SDMA_SUBOP_WRITE_LINEAR', + 'SDMA_SUBOP_WRITE_TILED', '__VEGA10_SDMA_PKT_OPEN_H_', + 'hdp_flush_cmd', 'struct_SDMA_PKT_ATOMIC_TAG', + 'struct_SDMA_PKT_ATOMIC_TAG_0_0', + 'struct_SDMA_PKT_ATOMIC_TAG_1_0', + 'struct_SDMA_PKT_ATOMIC_TAG_2_0', + 'struct_SDMA_PKT_ATOMIC_TAG_3_0', + 'struct_SDMA_PKT_ATOMIC_TAG_4_0', + 'struct_SDMA_PKT_ATOMIC_TAG_5_0', + 'struct_SDMA_PKT_ATOMIC_TAG_6_0', + 'struct_SDMA_PKT_ATOMIC_TAG_7_0', + 'struct_SDMA_PKT_CONSTANT_FILL_TAG', + 'struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0', + 'struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0', + 'struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0', + 'struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0', + 'struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0', + 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0', + 'struct_SDMA_PKT_COPY_LINEAR_TAG', + 'struct_SDMA_PKT_COPY_LINEAR_TAG_0_0', + 'struct_SDMA_PKT_COPY_LINEAR_TAG_1_0', + 'struct_SDMA_PKT_COPY_LINEAR_TAG_2_0', + 'struct_SDMA_PKT_COPY_LINEAR_TAG_3_0', + 'struct_SDMA_PKT_COPY_LINEAR_TAG_4_0', + 'struct_SDMA_PKT_COPY_LINEAR_TAG_5_0', + 'struct_SDMA_PKT_COPY_LINEAR_TAG_6_0', + 'struct_SDMA_PKT_FENCE_TAG', 'struct_SDMA_PKT_FENCE_TAG_0_0', + 'struct_SDMA_PKT_FENCE_TAG_1_0', 'struct_SDMA_PKT_FENCE_TAG_2_0', + 'struct_SDMA_PKT_FENCE_TAG_3_0', 'struct_SDMA_PKT_GCR_TAG', + 'struct_SDMA_PKT_GCR_TAG_0_0', 'struct_SDMA_PKT_GCR_TAG_1_0', + 'struct_SDMA_PKT_GCR_TAG_2_0', 'struct_SDMA_PKT_GCR_TAG_3_0', + 'struct_SDMA_PKT_GCR_TAG_4_0', 'struct_SDMA_PKT_HDP_FLUSH_TAG', + 'struct_SDMA_PKT_POLL_REGMEM_TAG', + 'struct_SDMA_PKT_POLL_REGMEM_TAG_0_0', + 'struct_SDMA_PKT_POLL_REGMEM_TAG_1_0', + 'struct_SDMA_PKT_POLL_REGMEM_TAG_2_0', + 'struct_SDMA_PKT_POLL_REGMEM_TAG_3_0', + 'struct_SDMA_PKT_POLL_REGMEM_TAG_4_0', + 'struct_SDMA_PKT_POLL_REGMEM_TAG_5_0', + 'struct_SDMA_PKT_TIMESTAMP_TAG', + 'struct_SDMA_PKT_TIMESTAMP_TAG_0_0', + 'struct_SDMA_PKT_TIMESTAMP_TAG_1_0', + 'struct_SDMA_PKT_TIMESTAMP_TAG_2_0', 'struct_SDMA_PKT_TRAP_TAG', + 'struct_SDMA_PKT_TRAP_TAG_0_0', 'struct_SDMA_PKT_TRAP_TAG_1_0', + 'union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION', + 'union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION', + 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION', + 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION', + 'union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION', + 'union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION', + 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION', + 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION', + 'union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION', + 'union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION', + 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION', + 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION', + 'union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION', + 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION', + 'union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION', + 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION', + 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION', + 'union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION', + 'union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION', + 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION', + 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION', + 'union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION', + 'union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION', + 'union_SDMA_PKT_FENCE_TAG_DATA_UNION', + 'union_SDMA_PKT_FENCE_TAG_HEADER_UNION', + 'union_SDMA_PKT_GCR_TAG_HEADER_UNION', + 'union_SDMA_PKT_GCR_TAG_WORD1_UNION', + 'union_SDMA_PKT_GCR_TAG_WORD2_UNION', + 'union_SDMA_PKT_GCR_TAG_WORD3_UNION', + 'union_SDMA_PKT_GCR_TAG_WORD4_UNION', + 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION', + 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION', + 'union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION', + 'union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION', + 'union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION', + 'union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION', + 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION', + 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION', + 'union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION', + 'union_SDMA_PKT_TRAP_TAG_HEADER_UNION', + 'union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION'] diff --git a/tinygrad/runtime/autogen/am/vega10.py b/tinygrad/runtime/autogen/am/vega10.py new file mode 100644 index 0000000000..510fbe6a03 --- /dev/null +++ b/tinygrad/runtime/autogen/am/vega10.py @@ -0,0 +1,36196 @@ +# mypy: ignore-errors +# -*- coding: utf-8 -*- +# +# TARGET arch is: [] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes + + + + +_vega10_ENUM_HEADER = True # macro +ENUMS_GDS_PERFCOUNT_SELECT_H = True # macro +SQ_WAVE_TYPE_PS0 = 0x00000000 # macro +SQIND_GLOBAL_REGS_OFFSET = 0x00000000 # macro +SQIND_GLOBAL_REGS_SIZE = 0x00000008 # macro +SQIND_LOCAL_REGS_OFFSET = 0x00000008 # macro +SQIND_LOCAL_REGS_SIZE = 0x00000008 # macro +SQIND_WAVE_HWREGS_OFFSET = 0x00000010 # macro +SQIND_WAVE_HWREGS_SIZE = 0x000001f0 # macro +SQIND_WAVE_SGPRS_OFFSET = 0x00000200 # macro +SQIND_WAVE_SGPRS_SIZE = 0x00000200 # macro +SQIND_WAVE_VGPRS_OFFSET = 0x00000400 # macro +SQIND_WAVE_VGPRS_SIZE = 0x00000100 # macro +SQ_GFXDEC_BEGIN = 0x0000a000 # macro +SQ_GFXDEC_END = 0x0000c000 # macro +SQ_GFXDEC_STATE_ID_SHIFT = 0x0000000a # macro +SQDEC_BEGIN = 0x00002300 # macro +SQDEC_END = 0x000023ff # macro +SQPERFSDEC_BEGIN = 0x0000d9c0 # macro +SQPERFSDEC_END = 0x0000da40 # macro +SQPERFDDEC_BEGIN = 0x0000d1c0 # macro +SQPERFDDEC_END = 0x0000d240 # macro +SQGFXUDEC_BEGIN = 0x0000c330 # macro +SQGFXUDEC_END = 0x0000c380 # macro +SQPWRDEC_BEGIN = 0x0000f08c # macro +SQPWRDEC_END = 0x0000f094 # macro +SQ_DISPATCHER_GFX_MIN = 0x00000010 # macro +SQ_DISPATCHER_GFX_CNT_PER_RING = 0x00000008 # macro +SQ_MAX_PGM_SGPRS = 0x00000068 # macro +SQ_MAX_PGM_VGPRS = 0x00000100 # macro +SQ_THREAD_TRACE_TIME_UNIT = 0x00000004 # macro +SQ_EX_MODE_EXCP_VALU_BASE = 0x00000000 # macro +SQ_EX_MODE_EXCP_VALU_SIZE = 0x00000007 # macro +SQ_EX_MODE_EXCP_INVALID = 0x00000000 # macro +SQ_EX_MODE_EXCP_INPUT_DENORM = 0x00000001 # macro +SQ_EX_MODE_EXCP_DIV0 = 0x00000002 # macro +SQ_EX_MODE_EXCP_OVERFLOW = 0x00000003 # macro +SQ_EX_MODE_EXCP_UNDERFLOW = 0x00000004 # macro +SQ_EX_MODE_EXCP_INEXACT = 0x00000005 # macro +SQ_EX_MODE_EXCP_INT_DIV0 = 0x00000006 # macro +SQ_EX_MODE_EXCP_ADDR_WATCH0 = 0x00000007 # macro +SQ_EX_MODE_EXCP_MEM_VIOL = 0x00000008 # macro +SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 = 0x00000000 # macro +SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 = 0x00000001 # macro +SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 = 0x00000002 # macro +INST_ID_PRIV_START = 0x80000000 # macro +INST_ID_ECC_INTERRUPT_MSG = 0xfffffff0 # macro +INST_ID_TTRACE_NEW_PC_MSG = 0xfffffff1 # macro +INST_ID_HW_TRAP = 0xfffffff2 # macro +INST_ID_KILL_SEQ = 0xfffffff3 # macro +INST_ID_SPI_WREXEC = 0xfffffff4 # macro +INST_ID_HOST_REG_TRAP_MSG = 0xfffffffe # macro +SIMM16_WAITCNT_VM_CNT_START = 0x00000000 # macro +SIMM16_WAITCNT_VM_CNT_SIZE = 0x00000004 # macro +SIMM16_WAITCNT_EXP_CNT_START = 0x00000004 # macro +SIMM16_WAITCNT_EXP_CNT_SIZE = 0x00000003 # macro +SIMM16_WAITCNT_LGKM_CNT_START = 0x00000008 # macro +SIMM16_WAITCNT_LGKM_CNT_SIZE = 0x00000004 # macro +SIMM16_WAITCNT_VM_CNT_HI_START = 0x0000000e # macro +SIMM16_WAITCNT_VM_CNT_HI_SIZE = 0x00000002 # macro +SQ_EDC_FUE_CNTL_SQ = 0x00000000 # macro +SQ_EDC_FUE_CNTL_LDS = 0x00000001 # macro +SQ_EDC_FUE_CNTL_SIMD0 = 0x00000002 # macro +SQ_EDC_FUE_CNTL_SIMD1 = 0x00000003 # macro +SQ_EDC_FUE_CNTL_SIMD2 = 0x00000004 # macro +SQ_EDC_FUE_CNTL_SIMD3 = 0x00000005 # macro +SQ_EDC_FUE_CNTL_TA = 0x00000006 # macro +SQ_EDC_FUE_CNTL_TD = 0x00000007 # macro +SQ_EDC_FUE_CNTL_TCP = 0x00000008 # macro +CSDATA_TYPE_WIDTH = 0x00000002 # macro +CSDATA_ADDR_WIDTH = 0x00000007 # macro +CSDATA_DATA_WIDTH = 0x00000020 # macro +GSTHREADID_SIZE = 0x00000002 # macro +GB_TILING_CONFIG_TABLE_SIZE = 0x00000020 # macro +GB_TILING_CONFIG_MACROTABLE_SIZE = 0x00000010 # macro +SEM_ECC_ERROR = 0x00000000 # macro +SEM_TRANS_ERROR = 0x00000001 # macro +SEM_FAILED = 0x00000002 # macro +SEM_PASSED = 0x00000003 # macro +IQ_QUEUE_SLEEP = 0x00000000 # macro +IQ_OFFLOAD_RETRY = 0x00000001 # macro +IQ_SCH_WAVE_MSG = 0x00000002 # macro +IQ_SEM_REARM = 0x00000003 # macro +IQ_DEQUEUE_RETRY = 0x00000004 # macro +IQ_INTR_TYPE_PQ = 0x00000000 # macro +IQ_INTR_TYPE_IB = 0x00000001 # macro +IQ_INTR_TYPE_MQD = 0x00000002 # macro +VMID_SZ = 0x00000004 # macro +CONFIG_SPACE_START = 0x00002000 # macro +CONFIG_SPACE_END = 0x00009fff # macro +CONFIG_SPACE1_START = 0x00002000 # macro +CONFIG_SPACE1_END = 0x00002bff # macro +CONFIG_SPACE2_START = 0x00003000 # macro +CONFIG_SPACE2_END = 0x00009fff # macro +UCONFIG_SPACE_START = 0x0000c000 # macro +UCONFIG_SPACE_END = 0x0000ffff # macro +PERSISTENT_SPACE_START = 0x00002c00 # macro +PERSISTENT_SPACE_END = 0x00002fff # macro +CONTEXT_SPACE_START = 0x0000a000 # macro +CONTEXT_SPACE_END = 0x0000bfff # macro +SQ_ENC_SOP1_BITS = 0xbe800000 # macro +SQ_ENC_SOP1_MASK = 0xff800000 # macro +SQ_ENC_SOP1_FIELD = 0x0000017d # macro +SQ_ENC_SOPC_BITS = 0xbf000000 # macro +SQ_ENC_SOPC_MASK = 0xff800000 # macro +SQ_ENC_SOPC_FIELD = 0x0000017e # macro +SQ_ENC_SOPP_BITS = 0xbf800000 # macro +SQ_ENC_SOPP_MASK = 0xff800000 # macro +SQ_ENC_SOPP_FIELD = 0x0000017f # macro +SQ_ENC_SOPK_BITS = 0xb0000000 # macro +SQ_ENC_SOPK_MASK = 0xf0000000 # macro +SQ_ENC_SOPK_FIELD = 0x0000000b # macro +SQ_ENC_SOP2_BITS = 0x80000000 # macro +SQ_ENC_SOP2_MASK = 0xc0000000 # macro +SQ_ENC_SOP2_FIELD = 0x00000002 # macro +SQ_ENC_SMEM_BITS = 0xc0000000 # macro +SQ_ENC_SMEM_MASK = 0xfc000000 # macro +SQ_ENC_SMEM_FIELD = 0x00000030 # macro +SQ_ENC_VOP1_BITS = 0x7e000000 # macro +SQ_ENC_VOP1_MASK = 0xfe000000 # macro +SQ_ENC_VOP1_FIELD = 0x0000003f # macro +SQ_ENC_VOPC_BITS = 0x7c000000 # macro +SQ_ENC_VOPC_MASK = 0xfe000000 # macro +SQ_ENC_VOPC_FIELD = 0x0000003e # macro +SQ_ENC_VOP2_BITS = 0x00000000 # macro +SQ_ENC_VOP2_MASK = 0x80000000 # macro +SQ_ENC_VOP2_FIELD = 0x00000000 # macro +SQ_ENC_VINTRP_BITS = 0xd4000000 # macro +SQ_ENC_VINTRP_MASK = 0xfc000000 # macro +SQ_ENC_VINTRP_FIELD = 0x00000035 # macro +SQ_ENC_VOP3P_BITS = 0xd3800000 # macro +SQ_ENC_VOP3P_MASK = 0xff800000 # macro +SQ_ENC_VOP3P_FIELD = 0x000001a7 # macro +SQ_ENC_VOP3_BITS = 0xd0000000 # macro +SQ_ENC_VOP3_MASK = 0xfc000000 # macro +SQ_ENC_VOP3_FIELD = 0x00000034 # macro +SQ_ENC_DS_BITS = 0xd8000000 # macro +SQ_ENC_DS_MASK = 0xfc000000 # macro +SQ_ENC_DS_FIELD = 0x00000036 # macro +SQ_ENC_MUBUF_BITS = 0xe0000000 # macro +SQ_ENC_MUBUF_MASK = 0xfc000000 # macro +SQ_ENC_MUBUF_FIELD = 0x00000038 # macro +SQ_ENC_MTBUF_BITS = 0xe8000000 # macro +SQ_ENC_MTBUF_MASK = 0xfc000000 # macro +SQ_ENC_MTBUF_FIELD = 0x0000003a # macro +SQ_ENC_MIMG_BITS = 0xf0000000 # macro +SQ_ENC_MIMG_MASK = 0xfc000000 # macro +SQ_ENC_MIMG_FIELD = 0x0000003c # macro +SQ_ENC_EXP_BITS = 0xc4000000 # macro +SQ_ENC_EXP_MASK = 0xfc000000 # macro +SQ_ENC_EXP_FIELD = 0x00000031 # macro +SQ_ENC_FLAT_BITS = 0xdc000000 # macro +SQ_ENC_FLAT_MASK = 0xfc000000 # macro +SQ_ENC_FLAT_FIELD = 0x00000037 # macro +SQ_V_OP3_INTRP_COUNT = 0x0000000c # macro +SQ_SENDMSG_SYSTEM_SIZE = 0x00000003 # macro +SQ_HWREG_ID_SIZE = 0x00000006 # macro +SQ_V_OPC_COUNT = 0x00000100 # macro +SQ_NUM_VGPR = 0x00000100 # macro +SQ_WAITCNT_LGKM_SHIFT = 0x00000008 # macro +SQ_HWREG_ID_SHIFT = 0x00000000 # macro +SQ_EXP_NUM_POS = 0x00000004 # macro +SQ_XLATE_VOP3_TO_VOPC_OFFSET = 0x00000000 # macro +SQ_V_OP3_2IN_OFFSET = 0x00000280 # macro +SQ_XLATE_VOP3_TO_VOP2_OFFSET = 0x00000100 # macro +SQ_EXP_NUM_MRT = 0x00000008 # macro +SQ_NUM_TTMP = 0x00000010 # macro +SQ_SENDMSG_STREAMID_SHIFT = 0x00000008 # macro +SQ_V_OP1_COUNT = 0x00000080 # macro +SQ_WAITCNT_LGKM_SIZE = 0x00000004 # macro +SQ_XLATE_VOP3_TO_VOPC_COUNT = 0x00000100 # macro +SQ_SENDMSG_MSG_SHIFT = 0x00000000 # macro +SQ_V_OP3_3IN_OFFSET = 0x000001c0 # macro +SQ_HWREG_OFFSET_SHIFT = 0x00000006 # macro +SQ_HWREG_SIZE_SHIFT = 0x0000000b # macro +SQ_HWREG_OFFSET_SIZE = 0x00000005 # macro +SQ_V_OP3_3IN_COUNT = 0x000000b0 # macro +SQ_SENDMSG_MSG_SIZE = 0x00000004 # macro +SQ_XLATE_VOP3_TO_VOP1_COUNT = 0x00000080 # macro +SQ_EXP_NUM_GDS = 0x00000005 # macro +SQ_V_OP2_COUNT = 0x00000040 # macro +SQ_SENDMSG_GSOP_SIZE = 0x00000002 # macro +SQ_WAITCNT_VM_SHIFT = 0x00000000 # macro +SQ_XLATE_VOP3_TO_VOP3P_COUNT = 0x00000080 # macro +SQ_V_OP3_2IN_COUNT = 0x00000080 # macro +SQ_SENDMSG_SYSTEM_SHIFT = 0x00000004 # macro +SQ_WAITCNT_VM_SIZE = 0x00000004 # macro +SQ_XLATE_VOP3_TO_VOP3P_OFFSET = 0x00000380 # macro +SQ_WAITCNT_EXP_SHIFT = 0x00000004 # macro +SQ_XLATE_VOP3_TO_VOP2_COUNT = 0x00000040 # macro +SQ_EXP_NUM_PARAM = 0x00000020 # macro +SQ_HWREG_SIZE_SIZE = 0x00000005 # macro +SQ_WAITCNT_EXP_SIZE = 0x00000003 # macro +SQ_V_OP3_INTRP_OFFSET = 0x00000274 # macro +SQ_SENDMSG_GSOP_SHIFT = 0x00000004 # macro +SQ_XLATE_VOP3_TO_VINTRP_OFFSET = 0x00000270 # macro +SQ_NUM_ATTR = 0x00000021 # macro +SQ_NUM_SGPR = 0x00000066 # macro +SQ_SRC_VGPR_BIT = 0x00000100 # macro +SQ_V_INTRP_COUNT = 0x00000004 # macro +SQ_SENDMSG_STREAMID_SIZE = 0x00000002 # macro +SQ_V_OP3P_COUNT = 0x00000080 # macro +SQ_XLATE_VOP3_TO_VOP1_OFFSET = 0x00000140 # macro +SQ_XLATE_VOP3_TO_VINTRP_COUNT = 0x00000004 # macro +SQ_SRC_DPP = 0x000000fa # macro +SQ_TBUFFER_LOAD_FORMAT_X = 0x00000000 # macro +SQ_TBUFFER_LOAD_FORMAT_XY = 0x00000001 # macro +SQ_TBUFFER_LOAD_FORMAT_XYZ = 0x00000002 # macro +SQ_TBUFFER_LOAD_FORMAT_XYZW = 0x00000003 # macro +SQ_TBUFFER_STORE_FORMAT_X = 0x00000004 # macro +SQ_TBUFFER_STORE_FORMAT_XY = 0x00000005 # macro +SQ_TBUFFER_STORE_FORMAT_XYZ = 0x00000006 # macro +SQ_TBUFFER_STORE_FORMAT_XYZW = 0x00000007 # macro +SQ_TBUFFER_LOAD_FORMAT_D16_X = 0x00000008 # macro +SQ_TBUFFER_LOAD_FORMAT_D16_XY = 0x00000009 # macro +SQ_TBUFFER_LOAD_FORMAT_D16_XYZ = 0x0000000a # macro +SQ_TBUFFER_LOAD_FORMAT_D16_XYZW = 0x0000000b # macro +SQ_TBUFFER_STORE_FORMAT_D16_X = 0x0000000c # macro +SQ_TBUFFER_STORE_FORMAT_D16_XY = 0x0000000d # macro +SQ_TBUFFER_STORE_FORMAT_D16_XYZ = 0x0000000e # macro +SQ_TBUFFER_STORE_FORMAT_D16_XYZW = 0x0000000f # macro +SQ_GLOBAL_LOAD_UBYTE = 0x00000010 # macro +SQ_GLOBAL_LOAD_SBYTE = 0x00000011 # macro +SQ_GLOBAL_LOAD_USHORT = 0x00000012 # macro +SQ_GLOBAL_LOAD_SSHORT = 0x00000013 # macro +SQ_GLOBAL_LOAD_DWORD = 0x00000014 # macro +SQ_GLOBAL_LOAD_DWORDX2 = 0x00000015 # macro +SQ_GLOBAL_LOAD_DWORDX3 = 0x00000016 # macro +SQ_GLOBAL_LOAD_DWORDX4 = 0x00000017 # macro +SQ_GLOBAL_STORE_BYTE = 0x00000018 # macro +SQ_GLOBAL_STORE_SHORT = 0x0000001a # macro +SQ_GLOBAL_STORE_DWORD = 0x0000001c # macro +SQ_GLOBAL_STORE_DWORDX2 = 0x0000001d # macro +SQ_GLOBAL_STORE_DWORDX3 = 0x0000001e # macro +SQ_GLOBAL_STORE_DWORDX4 = 0x0000001f # macro +SQ_GLOBAL_ATOMIC_SWAP = 0x00000040 # macro +SQ_GLOBAL_ATOMIC_CMPSWAP = 0x00000041 # macro +SQ_GLOBAL_ATOMIC_ADD = 0x00000042 # macro +SQ_GLOBAL_ATOMIC_SUB = 0x00000043 # macro +SQ_GLOBAL_ATOMIC_SMIN = 0x00000044 # macro +SQ_GLOBAL_ATOMIC_UMIN = 0x00000045 # macro +SQ_GLOBAL_ATOMIC_SMAX = 0x00000046 # macro +SQ_GLOBAL_ATOMIC_UMAX = 0x00000047 # macro +SQ_GLOBAL_ATOMIC_AND = 0x00000048 # macro +SQ_GLOBAL_ATOMIC_OR = 0x00000049 # macro +SQ_GLOBAL_ATOMIC_XOR = 0x0000004a # macro +SQ_GLOBAL_ATOMIC_INC = 0x0000004b # macro +SQ_GLOBAL_ATOMIC_DEC = 0x0000004c # macro +SQ_GLOBAL_ATOMIC_SWAP_X2 = 0x00000060 # macro +SQ_GLOBAL_ATOMIC_CMPSWAP_X2 = 0x00000061 # macro +SQ_GLOBAL_ATOMIC_ADD_X2 = 0x00000062 # macro +SQ_GLOBAL_ATOMIC_SUB_X2 = 0x00000063 # macro +SQ_GLOBAL_ATOMIC_SMIN_X2 = 0x00000064 # macro +SQ_GLOBAL_ATOMIC_UMIN_X2 = 0x00000065 # macro +SQ_GLOBAL_ATOMIC_SMAX_X2 = 0x00000066 # macro +SQ_GLOBAL_ATOMIC_UMAX_X2 = 0x00000067 # macro +SQ_GLOBAL_ATOMIC_AND_X2 = 0x00000068 # macro +SQ_GLOBAL_ATOMIC_OR_X2 = 0x00000069 # macro +SQ_GLOBAL_ATOMIC_XOR_X2 = 0x0000006a # macro +SQ_GLOBAL_ATOMIC_INC_X2 = 0x0000006b # macro +SQ_GLOBAL_ATOMIC_DEC_X2 = 0x0000006c # macro +SQ_VGPR0 = 0x00000000 # macro +SQ_SCRATCH_LOAD_UBYTE = 0x00000010 # macro +SQ_SCRATCH_LOAD_SBYTE = 0x00000011 # macro +SQ_SCRATCH_LOAD_USHORT = 0x00000012 # macro +SQ_SCRATCH_LOAD_SSHORT = 0x00000013 # macro +SQ_SCRATCH_LOAD_DWORD = 0x00000014 # macro +SQ_SCRATCH_LOAD_DWORDX2 = 0x00000015 # macro +SQ_SCRATCH_LOAD_DWORDX3 = 0x00000016 # macro +SQ_SCRATCH_LOAD_DWORDX4 = 0x00000017 # macro +SQ_SCRATCH_STORE_BYTE = 0x00000018 # macro +SQ_SCRATCH_STORE_SHORT = 0x0000001a # macro +SQ_SCRATCH_STORE_DWORD = 0x0000001c # macro +SQ_SCRATCH_STORE_DWORDX2 = 0x0000001d # macro +SQ_SCRATCH_STORE_DWORDX3 = 0x0000001e # macro +SQ_SCRATCH_STORE_DWORDX4 = 0x0000001f # macro +SQ_VCC_ALL = 0x00000000 # macro +SQ_SRC_0 = 0x00000080 # macro +SQ_SRC_1_INT = 0x00000081 # macro +SQ_SRC_2_INT = 0x00000082 # macro +SQ_SRC_3_INT = 0x00000083 # macro +SQ_SRC_4_INT = 0x00000084 # macro +SQ_SRC_5_INT = 0x00000085 # macro +SQ_SRC_6_INT = 0x00000086 # macro +SQ_SRC_7_INT = 0x00000087 # macro +SQ_SRC_8_INT = 0x00000088 # macro +SQ_SRC_9_INT = 0x00000089 # macro +SQ_SRC_10_INT = 0x0000008a # macro +SQ_SRC_11_INT = 0x0000008b # macro +SQ_SRC_12_INT = 0x0000008c # macro +SQ_SRC_13_INT = 0x0000008d # macro +SQ_SRC_14_INT = 0x0000008e # macro +SQ_SRC_15_INT = 0x0000008f # macro +SQ_SRC_16_INT = 0x00000090 # macro +SQ_SRC_17_INT = 0x00000091 # macro +SQ_SRC_18_INT = 0x00000092 # macro +SQ_SRC_19_INT = 0x00000093 # macro +SQ_SRC_20_INT = 0x00000094 # macro +SQ_SRC_21_INT = 0x00000095 # macro +SQ_SRC_22_INT = 0x00000096 # macro +SQ_SRC_23_INT = 0x00000097 # macro +SQ_SRC_24_INT = 0x00000098 # macro +SQ_SRC_25_INT = 0x00000099 # macro +SQ_SRC_26_INT = 0x0000009a # macro +SQ_SRC_27_INT = 0x0000009b # macro +SQ_SRC_28_INT = 0x0000009c # macro +SQ_SRC_29_INT = 0x0000009d # macro +SQ_SRC_30_INT = 0x0000009e # macro +SQ_SRC_31_INT = 0x0000009f # macro +SQ_SRC_32_INT = 0x000000a0 # macro +SQ_SRC_33_INT = 0x000000a1 # macro +SQ_SRC_34_INT = 0x000000a2 # macro +SQ_SRC_35_INT = 0x000000a3 # macro +SQ_SRC_36_INT = 0x000000a4 # macro +SQ_SRC_37_INT = 0x000000a5 # macro +SQ_SRC_38_INT = 0x000000a6 # macro +SQ_SRC_39_INT = 0x000000a7 # macro +SQ_SRC_40_INT = 0x000000a8 # macro +SQ_SRC_41_INT = 0x000000a9 # macro +SQ_SRC_42_INT = 0x000000aa # macro +SQ_SRC_43_INT = 0x000000ab # macro +SQ_SRC_44_INT = 0x000000ac # macro +SQ_SRC_45_INT = 0x000000ad # macro +SQ_SRC_46_INT = 0x000000ae # macro +SQ_SRC_47_INT = 0x000000af # macro +SQ_SRC_48_INT = 0x000000b0 # macro +SQ_SRC_49_INT = 0x000000b1 # macro +SQ_SRC_50_INT = 0x000000b2 # macro +SQ_SRC_51_INT = 0x000000b3 # macro +SQ_SRC_52_INT = 0x000000b4 # macro +SQ_SRC_53_INT = 0x000000b5 # macro +SQ_SRC_54_INT = 0x000000b6 # macro +SQ_SRC_55_INT = 0x000000b7 # macro +SQ_SRC_56_INT = 0x000000b8 # macro +SQ_SRC_57_INT = 0x000000b9 # macro +SQ_SRC_58_INT = 0x000000ba # macro +SQ_SRC_59_INT = 0x000000bb # macro +SQ_SRC_60_INT = 0x000000bc # macro +SQ_SRC_61_INT = 0x000000bd # macro +SQ_SRC_62_INT = 0x000000be # macro +SQ_SRC_63_INT = 0x000000bf # macro +SQ_IMAGE_LOAD = 0x00000000 # macro +SQ_IMAGE_LOAD_MIP = 0x00000001 # macro +SQ_IMAGE_LOAD_PCK = 0x00000002 # macro +SQ_IMAGE_LOAD_PCK_SGN = 0x00000003 # macro +SQ_IMAGE_LOAD_MIP_PCK = 0x00000004 # macro +SQ_IMAGE_LOAD_MIP_PCK_SGN = 0x00000005 # macro +SQ_IMAGE_STORE = 0x00000008 # macro +SQ_IMAGE_STORE_MIP = 0x00000009 # macro +SQ_IMAGE_STORE_PCK = 0x0000000a # macro +SQ_IMAGE_STORE_MIP_PCK = 0x0000000b # macro +SQ_IMAGE_GET_RESINFO = 0x0000000e # macro +SQ_IMAGE_ATOMIC_SWAP = 0x00000010 # macro +SQ_IMAGE_ATOMIC_CMPSWAP = 0x00000011 # macro +SQ_IMAGE_ATOMIC_ADD = 0x00000012 # macro +SQ_IMAGE_ATOMIC_SUB = 0x00000013 # macro +SQ_IMAGE_ATOMIC_SMIN = 0x00000014 # macro +SQ_IMAGE_ATOMIC_UMIN = 0x00000015 # macro +SQ_IMAGE_ATOMIC_SMAX = 0x00000016 # macro +SQ_IMAGE_ATOMIC_UMAX = 0x00000017 # macro +SQ_IMAGE_ATOMIC_AND = 0x00000018 # macro +SQ_IMAGE_ATOMIC_OR = 0x00000019 # macro +SQ_IMAGE_ATOMIC_XOR = 0x0000001a # macro +SQ_IMAGE_ATOMIC_INC = 0x0000001b # macro +SQ_IMAGE_ATOMIC_DEC = 0x0000001c # macro +SQ_IMAGE_SAMPLE = 0x00000020 # macro +SQ_IMAGE_SAMPLE_CL = 0x00000021 # macro +SQ_IMAGE_SAMPLE_D = 0x00000022 # macro +SQ_IMAGE_SAMPLE_D_CL = 0x00000023 # macro +SQ_IMAGE_SAMPLE_L = 0x00000024 # macro +SQ_IMAGE_SAMPLE_B = 0x00000025 # macro +SQ_IMAGE_SAMPLE_B_CL = 0x00000026 # macro +SQ_IMAGE_SAMPLE_LZ = 0x00000027 # macro +SQ_IMAGE_SAMPLE_C = 0x00000028 # macro +SQ_IMAGE_SAMPLE_C_CL = 0x00000029 # macro +SQ_IMAGE_SAMPLE_C_D = 0x0000002a # macro +SQ_IMAGE_SAMPLE_C_D_CL = 0x0000002b # macro +SQ_IMAGE_SAMPLE_C_L = 0x0000002c # macro +SQ_IMAGE_SAMPLE_C_B = 0x0000002d # macro +SQ_IMAGE_SAMPLE_C_B_CL = 0x0000002e # macro +SQ_IMAGE_SAMPLE_C_LZ = 0x0000002f # macro +SQ_IMAGE_SAMPLE_O = 0x00000030 # macro +SQ_IMAGE_SAMPLE_CL_O = 0x00000031 # macro +SQ_IMAGE_SAMPLE_D_O = 0x00000032 # macro +SQ_IMAGE_SAMPLE_D_CL_O = 0x00000033 # macro +SQ_IMAGE_SAMPLE_L_O = 0x00000034 # macro +SQ_IMAGE_SAMPLE_B_O = 0x00000035 # macro +SQ_IMAGE_SAMPLE_B_CL_O = 0x00000036 # macro +SQ_IMAGE_SAMPLE_LZ_O = 0x00000037 # macro +SQ_IMAGE_SAMPLE_C_O = 0x00000038 # macro +SQ_IMAGE_SAMPLE_C_CL_O = 0x00000039 # macro +SQ_IMAGE_SAMPLE_C_D_O = 0x0000003a # macro +SQ_IMAGE_SAMPLE_C_D_CL_O = 0x0000003b # macro +SQ_IMAGE_SAMPLE_C_L_O = 0x0000003c # macro +SQ_IMAGE_SAMPLE_C_B_O = 0x0000003d # macro +SQ_IMAGE_SAMPLE_C_B_CL_O = 0x0000003e # macro +SQ_IMAGE_SAMPLE_C_LZ_O = 0x0000003f # macro +SQ_IMAGE_GATHER4 = 0x00000040 # macro +SQ_IMAGE_GATHER4_CL = 0x00000041 # macro +SQ_IMAGE_GATHER4H = 0x00000042 # macro +SQ_IMAGE_GATHER4_L = 0x00000044 # macro +SQ_IMAGE_GATHER4_B = 0x00000045 # macro +SQ_IMAGE_GATHER4_B_CL = 0x00000046 # macro +SQ_IMAGE_GATHER4_LZ = 0x00000047 # macro +SQ_IMAGE_GATHER4_C = 0x00000048 # macro +SQ_IMAGE_GATHER4_C_CL = 0x00000049 # macro +SQ_IMAGE_GATHER4H_PCK = 0x0000004a # macro +SQ_IMAGE_GATHER8H_PCK = 0x0000004b # macro +SQ_IMAGE_GATHER4_C_L = 0x0000004c # macro +SQ_IMAGE_GATHER4_C_B = 0x0000004d # macro +SQ_IMAGE_GATHER4_C_B_CL = 0x0000004e # macro +SQ_IMAGE_GATHER4_C_LZ = 0x0000004f # macro +SQ_IMAGE_GATHER4_O = 0x00000050 # macro +SQ_IMAGE_GATHER4_CL_O = 0x00000051 # macro +SQ_IMAGE_GATHER4_L_O = 0x00000054 # macro +SQ_IMAGE_GATHER4_B_O = 0x00000055 # macro +SQ_IMAGE_GATHER4_B_CL_O = 0x00000056 # macro +SQ_IMAGE_GATHER4_LZ_O = 0x00000057 # macro +SQ_IMAGE_GATHER4_C_O = 0x00000058 # macro +SQ_IMAGE_GATHER4_C_CL_O = 0x00000059 # macro +SQ_IMAGE_GATHER4_C_L_O = 0x0000005c # macro +SQ_IMAGE_GATHER4_C_B_O = 0x0000005d # macro +SQ_IMAGE_GATHER4_C_B_CL_O = 0x0000005e # macro +SQ_IMAGE_GATHER4_C_LZ_O = 0x0000005f # macro +SQ_IMAGE_GET_LOD = 0x00000060 # macro +SQ_IMAGE_SAMPLE_CD = 0x00000068 # macro +SQ_IMAGE_SAMPLE_CD_CL = 0x00000069 # macro +SQ_IMAGE_SAMPLE_C_CD = 0x0000006a # macro +SQ_IMAGE_SAMPLE_C_CD_CL = 0x0000006b # macro +SQ_IMAGE_SAMPLE_CD_O = 0x0000006c # macro +SQ_IMAGE_SAMPLE_CD_CL_O = 0x0000006d # macro +SQ_IMAGE_SAMPLE_C_CD_O = 0x0000006e # macro +SQ_IMAGE_SAMPLE_C_CD_CL_O = 0x0000006f # macro +SQ_IMAGE_RSRC256 = 0x0000007e # macro +SQ_IMAGE_SAMPLER = 0x0000007f # macro +SQ_HW_REG_MODE = 0x00000001 # macro +SQ_HW_REG_STATUS = 0x00000002 # macro +SQ_HW_REG_TRAPSTS = 0x00000003 # macro +SQ_HW_REG_HW_ID = 0x00000004 # macro +SQ_HW_REG_GPR_ALLOC = 0x00000005 # macro +SQ_HW_REG_LDS_ALLOC = 0x00000006 # macro +SQ_HW_REG_IB_STS = 0x00000007 # macro +SQ_HW_REG_PC_LO = 0x00000008 # macro +SQ_HW_REG_PC_HI = 0x00000009 # macro +SQ_HW_REG_INST_DW0 = 0x0000000a # macro +SQ_HW_REG_INST_DW1 = 0x0000000b # macro +SQ_HW_REG_IB_DBG0 = 0x0000000c # macro +SQ_HW_REG_IB_DBG1 = 0x0000000d # macro +SQ_HW_REG_FLUSH_IB = 0x0000000e # macro +SQ_HW_REG_SH_MEM_BASES = 0x0000000f # macro +SQ_HW_REG_SQ_SHADER_TBA_LO = 0x00000010 # macro +SQ_HW_REG_SQ_SHADER_TBA_HI = 0x00000011 # macro +SQ_HW_REG_SQ_SHADER_TMA_LO = 0x00000012 # macro +SQ_HW_REG_SQ_SHADER_TMA_HI = 0x00000013 # macro +SQ_S_MOV_B32 = 0x00000000 # macro +SQ_S_MOV_B64 = 0x00000001 # macro +SQ_S_CMOV_B32 = 0x00000002 # macro +SQ_S_CMOV_B64 = 0x00000003 # macro +SQ_S_NOT_B32 = 0x00000004 # macro +SQ_S_NOT_B64 = 0x00000005 # macro +SQ_S_WQM_B32 = 0x00000006 # macro +SQ_S_WQM_B64 = 0x00000007 # macro +SQ_S_BREV_B32 = 0x00000008 # macro +SQ_S_BREV_B64 = 0x00000009 # macro +SQ_S_BCNT0_I32_B32 = 0x0000000a # macro +SQ_S_BCNT0_I32_B64 = 0x0000000b # macro +SQ_S_BCNT1_I32_B32 = 0x0000000c # macro +SQ_S_BCNT1_I32_B64 = 0x0000000d # macro +SQ_S_FF0_I32_B32 = 0x0000000e # macro +SQ_S_FF0_I32_B64 = 0x0000000f # macro +SQ_S_FF1_I32_B32 = 0x00000010 # macro +SQ_S_FF1_I32_B64 = 0x00000011 # macro +SQ_S_FLBIT_I32_B32 = 0x00000012 # macro +SQ_S_FLBIT_I32_B64 = 0x00000013 # macro +SQ_S_FLBIT_I32 = 0x00000014 # macro +SQ_S_FLBIT_I32_I64 = 0x00000015 # macro +SQ_S_SEXT_I32_I8 = 0x00000016 # macro +SQ_S_SEXT_I32_I16 = 0x00000017 # macro +SQ_S_BITSET0_B32 = 0x00000018 # macro +SQ_S_BITSET0_B64 = 0x00000019 # macro +SQ_S_BITSET1_B32 = 0x0000001a # macro +SQ_S_BITSET1_B64 = 0x0000001b # macro +SQ_S_GETPC_B64 = 0x0000001c # macro +SQ_S_SETPC_B64 = 0x0000001d # macro +SQ_S_SWAPPC_B64 = 0x0000001e # macro +SQ_S_RFE_B64 = 0x0000001f # macro +SQ_S_AND_SAVEEXEC_B64 = 0x00000020 # macro +SQ_S_OR_SAVEEXEC_B64 = 0x00000021 # macro +SQ_S_XOR_SAVEEXEC_B64 = 0x00000022 # macro +SQ_S_ANDN2_SAVEEXEC_B64 = 0x00000023 # macro +SQ_S_ORN2_SAVEEXEC_B64 = 0x00000024 # macro +SQ_S_NAND_SAVEEXEC_B64 = 0x00000025 # macro +SQ_S_NOR_SAVEEXEC_B64 = 0x00000026 # macro +SQ_S_XNOR_SAVEEXEC_B64 = 0x00000027 # macro +SQ_S_QUADMASK_B32 = 0x00000028 # macro +SQ_S_QUADMASK_B64 = 0x00000029 # macro +SQ_S_MOVRELS_B32 = 0x0000002a # macro +SQ_S_MOVRELS_B64 = 0x0000002b # macro +SQ_S_MOVRELD_B32 = 0x0000002c # macro +SQ_S_MOVRELD_B64 = 0x0000002d # macro +SQ_S_CBRANCH_JOIN = 0x0000002e # macro +SQ_S_MOV_REGRD_B32 = 0x0000002f # macro +SQ_S_ABS_I32 = 0x00000030 # macro +SQ_S_MOV_FED_B32 = 0x00000031 # macro +SQ_S_SET_GPR_IDX_IDX = 0x00000032 # macro +SQ_S_ANDN1_SAVEEXEC_B64 = 0x00000033 # macro +SQ_S_ORN1_SAVEEXEC_B64 = 0x00000034 # macro +SQ_S_ANDN1_WREXEC_B64 = 0x00000035 # macro +SQ_S_ANDN2_WREXEC_B64 = 0x00000036 # macro +SQ_S_BITREPLICATE_B64_B32 = 0x00000037 # macro +SQ_CNT1 = 0x00000000 # macro +SQ_CNT2 = 0x00000001 # macro +SQ_CNT3 = 0x00000002 # macro +SQ_CNT4 = 0x00000003 # macro +SQ_V_MAD_LEGACY_F32 = 0x000001c0 # macro +SQ_V_MAD_F32 = 0x000001c1 # macro +SQ_V_MAD_I32_I24 = 0x000001c2 # macro +SQ_V_MAD_U32_U24 = 0x000001c3 # macro +SQ_V_CUBEID_F32 = 0x000001c4 # macro +SQ_V_CUBESC_F32 = 0x000001c5 # macro +SQ_V_CUBETC_F32 = 0x000001c6 # macro +SQ_V_CUBEMA_F32 = 0x000001c7 # macro +SQ_V_BFE_U32 = 0x000001c8 # macro +SQ_V_BFE_I32 = 0x000001c9 # macro +SQ_V_BFI_B32 = 0x000001ca # macro +SQ_V_FMA_F32 = 0x000001cb # macro +SQ_V_FMA_F64 = 0x000001cc # macro +SQ_V_LERP_U8 = 0x000001cd # macro +SQ_V_ALIGNBIT_B32 = 0x000001ce # macro +SQ_V_ALIGNBYTE_B32 = 0x000001cf # macro +SQ_V_MIN3_F32 = 0x000001d0 # macro +SQ_V_MIN3_I32 = 0x000001d1 # macro +SQ_V_MIN3_U32 = 0x000001d2 # macro +SQ_V_MAX3_F32 = 0x000001d3 # macro +SQ_V_MAX3_I32 = 0x000001d4 # macro +SQ_V_MAX3_U32 = 0x000001d5 # macro +SQ_V_MED3_F32 = 0x000001d6 # macro +SQ_V_MED3_I32 = 0x000001d7 # macro +SQ_V_MED3_U32 = 0x000001d8 # macro +SQ_V_SAD_U8 = 0x000001d9 # macro +SQ_V_SAD_HI_U8 = 0x000001da # macro +SQ_V_SAD_U16 = 0x000001db # macro +SQ_V_SAD_U32 = 0x000001dc # macro +SQ_V_CVT_PK_U8_F32 = 0x000001dd # macro +SQ_V_DIV_FIXUP_F32 = 0x000001de # macro +SQ_V_DIV_FIXUP_F64 = 0x000001df # macro +SQ_V_DIV_SCALE_F32 = 0x000001e0 # macro +SQ_V_DIV_SCALE_F64 = 0x000001e1 # macro +SQ_V_DIV_FMAS_F32 = 0x000001e2 # macro +SQ_V_DIV_FMAS_F64 = 0x000001e3 # macro +SQ_V_MSAD_U8 = 0x000001e4 # macro +SQ_V_QSAD_PK_U16_U8 = 0x000001e5 # macro +SQ_V_MQSAD_PK_U16_U8 = 0x000001e6 # macro +SQ_V_MQSAD_U32_U8 = 0x000001e7 # macro +SQ_V_MAD_U64_U32 = 0x000001e8 # macro +SQ_V_MAD_I64_I32 = 0x000001e9 # macro +SQ_V_MAD_LEGACY_F16 = 0x000001ea # macro +SQ_V_MAD_LEGACY_U16 = 0x000001eb # macro +SQ_V_MAD_LEGACY_I16 = 0x000001ec # macro +SQ_V_PERM_B32 = 0x000001ed # macro +SQ_V_FMA_LEGACY_F16 = 0x000001ee # macro +SQ_V_DIV_FIXUP_LEGACY_F16 = 0x000001ef # macro +SQ_V_CVT_PKACCUM_U8_F32 = 0x000001f0 # macro +SQ_V_MAD_U32_U16 = 0x000001f1 # macro +SQ_V_MAD_I32_I16 = 0x000001f2 # macro +SQ_V_XAD_U32 = 0x000001f3 # macro +SQ_V_MIN3_F16 = 0x000001f4 # macro +SQ_V_MIN3_I16 = 0x000001f5 # macro +SQ_V_MIN3_U16 = 0x000001f6 # macro +SQ_V_MAX3_F16 = 0x000001f7 # macro +SQ_V_MAX3_I16 = 0x000001f8 # macro +SQ_V_MAX3_U16 = 0x000001f9 # macro +SQ_V_MED3_F16 = 0x000001fa # macro +SQ_V_MED3_I16 = 0x000001fb # macro +SQ_V_MED3_U16 = 0x000001fc # macro +SQ_V_LSHL_ADD_U32 = 0x000001fd # macro +SQ_V_ADD_LSHL_U32 = 0x000001fe # macro +SQ_V_ADD3_U32 = 0x000001ff # macro +SQ_V_LSHL_OR_B32 = 0x00000200 # macro +SQ_V_AND_OR_B32 = 0x00000201 # macro +SQ_V_OR3_B32 = 0x00000202 # macro +SQ_V_MAD_F16 = 0x00000203 # macro +SQ_V_MAD_U16 = 0x00000204 # macro +SQ_V_MAD_I16 = 0x00000205 # macro +SQ_V_FMA_F16 = 0x00000206 # macro +SQ_V_DIV_FIXUP_F16 = 0x00000207 # macro +SQ_V_INTERP_P1LL_F16 = 0x00000274 # macro +SQ_V_INTERP_P1LV_F16 = 0x00000275 # macro +SQ_V_INTERP_P2_LEGACY_F16 = 0x00000276 # macro +SQ_V_INTERP_P2_F16 = 0x00000277 # macro +SQ_V_ADD_F64 = 0x00000280 # macro +SQ_V_MUL_F64 = 0x00000281 # macro +SQ_V_MIN_F64 = 0x00000282 # macro +SQ_V_MAX_F64 = 0x00000283 # macro +SQ_V_LDEXP_F64 = 0x00000284 # macro +SQ_V_MUL_LO_U32 = 0x00000285 # macro +SQ_V_MUL_HI_U32 = 0x00000286 # macro +SQ_V_MUL_HI_I32 = 0x00000287 # macro +SQ_V_LDEXP_F32 = 0x00000288 # macro +SQ_V_READLANE_B32 = 0x00000289 # macro +SQ_V_WRITELANE_B32 = 0x0000028a # macro +SQ_V_BCNT_U32_B32 = 0x0000028b # macro +SQ_V_MBCNT_LO_U32_B32 = 0x0000028c # macro +SQ_V_MBCNT_HI_U32_B32 = 0x0000028d # macro +SQ_V_MAC_LEGACY_F32 = 0x0000028e # macro +SQ_V_LSHLREV_B64 = 0x0000028f # macro +SQ_V_LSHRREV_B64 = 0x00000290 # macro +SQ_V_ASHRREV_I64 = 0x00000291 # macro +SQ_V_TRIG_PREOP_F64 = 0x00000292 # macro +SQ_V_BFM_B32 = 0x00000293 # macro +SQ_V_CVT_PKNORM_I16_F32 = 0x00000294 # macro +SQ_V_CVT_PKNORM_U16_F32 = 0x00000295 # macro +SQ_V_CVT_PKRTZ_F16_F32 = 0x00000296 # macro +SQ_V_CVT_PK_U16_U32 = 0x00000297 # macro +SQ_V_CVT_PK_I16_I32 = 0x00000298 # macro +SQ_V_CVT_PKNORM_I16_F16 = 0x00000299 # macro +SQ_V_CVT_PKNORM_U16_F16 = 0x0000029a # macro +SQ_V_READLANE_REGRD_B32 = 0x0000029b # macro +SQ_V_ADD_I32 = 0x0000029c # macro +SQ_V_SUB_I32 = 0x0000029d # macro +SQ_V_ADD_I16 = 0x0000029e # macro +SQ_V_SUB_I16 = 0x0000029f # macro +SQ_V_PACK_B32_F16 = 0x000002a0 # macro +SQ_SRC_LITERAL = 0x000000ff # macro +SQ_DPP_QUAD_PERM = 0x00000000 # macro +SQ_DPP_ROW_SL1 = 0x00000101 # macro +SQ_DPP_ROW_SL2 = 0x00000102 # macro +SQ_DPP_ROW_SL3 = 0x00000103 # macro +SQ_DPP_ROW_SL4 = 0x00000104 # macro +SQ_DPP_ROW_SL5 = 0x00000105 # macro +SQ_DPP_ROW_SL6 = 0x00000106 # macro +SQ_DPP_ROW_SL7 = 0x00000107 # macro +SQ_DPP_ROW_SL8 = 0x00000108 # macro +SQ_DPP_ROW_SL9 = 0x00000109 # macro +SQ_DPP_ROW_SL10 = 0x0000010a # macro +SQ_DPP_ROW_SL11 = 0x0000010b # macro +SQ_DPP_ROW_SL12 = 0x0000010c # macro +SQ_DPP_ROW_SL13 = 0x0000010d # macro +SQ_DPP_ROW_SL14 = 0x0000010e # macro +SQ_DPP_ROW_SL15 = 0x0000010f # macro +SQ_DPP_ROW_SR1 = 0x00000111 # macro +SQ_DPP_ROW_SR2 = 0x00000112 # macro +SQ_DPP_ROW_SR3 = 0x00000113 # macro +SQ_DPP_ROW_SR4 = 0x00000114 # macro +SQ_DPP_ROW_SR5 = 0x00000115 # macro +SQ_DPP_ROW_SR6 = 0x00000116 # macro +SQ_DPP_ROW_SR7 = 0x00000117 # macro +SQ_DPP_ROW_SR8 = 0x00000118 # macro +SQ_DPP_ROW_SR9 = 0x00000119 # macro +SQ_DPP_ROW_SR10 = 0x0000011a # macro +SQ_DPP_ROW_SR11 = 0x0000011b # macro +SQ_DPP_ROW_SR12 = 0x0000011c # macro +SQ_DPP_ROW_SR13 = 0x0000011d # macro +SQ_DPP_ROW_SR14 = 0x0000011e # macro +SQ_DPP_ROW_SR15 = 0x0000011f # macro +SQ_DPP_ROW_RR1 = 0x00000121 # macro +SQ_DPP_ROW_RR2 = 0x00000122 # macro +SQ_DPP_ROW_RR3 = 0x00000123 # macro +SQ_DPP_ROW_RR4 = 0x00000124 # macro +SQ_DPP_ROW_RR5 = 0x00000125 # macro +SQ_DPP_ROW_RR6 = 0x00000126 # macro +SQ_DPP_ROW_RR7 = 0x00000127 # macro +SQ_DPP_ROW_RR8 = 0x00000128 # macro +SQ_DPP_ROW_RR9 = 0x00000129 # macro +SQ_DPP_ROW_RR10 = 0x0000012a # macro +SQ_DPP_ROW_RR11 = 0x0000012b # macro +SQ_DPP_ROW_RR12 = 0x0000012c # macro +SQ_DPP_ROW_RR13 = 0x0000012d # macro +SQ_DPP_ROW_RR14 = 0x0000012e # macro +SQ_DPP_ROW_RR15 = 0x0000012f # macro +SQ_DPP_WF_SL1 = 0x00000130 # macro +SQ_DPP_WF_RL1 = 0x00000134 # macro +SQ_DPP_WF_SR1 = 0x00000138 # macro +SQ_DPP_WF_RR1 = 0x0000013c # macro +SQ_DPP_ROW_MIRROR = 0x00000140 # macro +SQ_DPP_ROW_HALF_MIRROR = 0x00000141 # macro +SQ_DPP_ROW_BCAST15 = 0x00000142 # macro +SQ_DPP_ROW_BCAST31 = 0x00000143 # macro +SQ_FLAT_SCRATCH_LO = 0x00000066 # macro +SQ_FLAT_SCRATCH_HI = 0x00000067 # macro +SQ_V_NOP = 0x00000000 # macro +SQ_V_MOV_B32 = 0x00000001 # macro +SQ_V_READFIRSTLANE_B32 = 0x00000002 # macro +SQ_V_CVT_I32_F64 = 0x00000003 # macro +SQ_V_CVT_F64_I32 = 0x00000004 # macro +SQ_V_CVT_F32_I32 = 0x00000005 # macro +SQ_V_CVT_F32_U32 = 0x00000006 # macro +SQ_V_CVT_U32_F32 = 0x00000007 # macro +SQ_V_CVT_I32_F32 = 0x00000008 # macro +SQ_V_MOV_FED_B32 = 0x00000009 # macro +SQ_V_CVT_F16_F32 = 0x0000000a # macro +SQ_V_CVT_F32_F16 = 0x0000000b # macro +SQ_V_CVT_RPI_I32_F32 = 0x0000000c # macro +SQ_V_CVT_FLR_I32_F32 = 0x0000000d # macro +SQ_V_CVT_OFF_F32_I4 = 0x0000000e # macro +SQ_V_CVT_F32_F64 = 0x0000000f # macro +SQ_V_CVT_F64_F32 = 0x00000010 # macro +SQ_V_CVT_F32_UBYTE0 = 0x00000011 # macro +SQ_V_CVT_F32_UBYTE1 = 0x00000012 # macro +SQ_V_CVT_F32_UBYTE2 = 0x00000013 # macro +SQ_V_CVT_F32_UBYTE3 = 0x00000014 # macro +SQ_V_CVT_U32_F64 = 0x00000015 # macro +SQ_V_CVT_F64_U32 = 0x00000016 # macro +SQ_V_TRUNC_F64 = 0x00000017 # macro +SQ_V_CEIL_F64 = 0x00000018 # macro +SQ_V_RNDNE_F64 = 0x00000019 # macro +SQ_V_FLOOR_F64 = 0x0000001a # macro +SQ_V_FRACT_F32 = 0x0000001b # macro +SQ_V_TRUNC_F32 = 0x0000001c # macro +SQ_V_CEIL_F32 = 0x0000001d # macro +SQ_V_RNDNE_F32 = 0x0000001e # macro +SQ_V_FLOOR_F32 = 0x0000001f # macro +SQ_V_EXP_F32 = 0x00000020 # macro +SQ_V_LOG_F32 = 0x00000021 # macro +SQ_V_RCP_F32 = 0x00000022 # macro +SQ_V_RCP_IFLAG_F32 = 0x00000023 # macro +SQ_V_RSQ_F32 = 0x00000024 # macro +SQ_V_RCP_F64 = 0x00000025 # macro +SQ_V_RSQ_F64 = 0x00000026 # macro +SQ_V_SQRT_F32 = 0x00000027 # macro +SQ_V_SQRT_F64 = 0x00000028 # macro +SQ_V_SIN_F32 = 0x00000029 # macro +SQ_V_COS_F32 = 0x0000002a # macro +SQ_V_NOT_B32 = 0x0000002b # macro +SQ_V_BFREV_B32 = 0x0000002c # macro +SQ_V_FFBH_U32 = 0x0000002d # macro +SQ_V_FFBL_B32 = 0x0000002e # macro +SQ_V_FFBH_I32 = 0x0000002f # macro +SQ_V_FREXP_EXP_I32_F64 = 0x00000030 # macro +SQ_V_FREXP_MANT_F64 = 0x00000031 # macro +SQ_V_FRACT_F64 = 0x00000032 # macro +SQ_V_FREXP_EXP_I32_F32 = 0x00000033 # macro +SQ_V_FREXP_MANT_F32 = 0x00000034 # macro +SQ_V_CLREXCP = 0x00000035 # macro +SQ_V_MOV_PRSV_B32 = 0x00000036 # macro +SQ_V_CVT_F16_U16 = 0x00000039 # macro +SQ_V_CVT_F16_I16 = 0x0000003a # macro +SQ_V_CVT_U16_F16 = 0x0000003b # macro +SQ_V_CVT_I16_F16 = 0x0000003c # macro +SQ_V_RCP_F16 = 0x0000003d # macro +SQ_V_SQRT_F16 = 0x0000003e # macro +SQ_V_RSQ_F16 = 0x0000003f # macro +SQ_V_LOG_F16 = 0x00000040 # macro +SQ_V_EXP_F16 = 0x00000041 # macro +SQ_V_FREXP_MANT_F16 = 0x00000042 # macro +SQ_V_FREXP_EXP_I16_F16 = 0x00000043 # macro +SQ_V_FLOOR_F16 = 0x00000044 # macro +SQ_V_CEIL_F16 = 0x00000045 # macro +SQ_V_TRUNC_F16 = 0x00000046 # macro +SQ_V_RNDNE_F16 = 0x00000047 # macro +SQ_V_FRACT_F16 = 0x00000048 # macro +SQ_V_SIN_F16 = 0x00000049 # macro +SQ_V_COS_F16 = 0x0000004a # macro +SQ_V_EXP_LEGACY_F32 = 0x0000004b # macro +SQ_V_LOG_LEGACY_F32 = 0x0000004c # macro +SQ_V_CVT_NORM_I16_F16 = 0x0000004d # macro +SQ_V_CVT_NORM_U16_F16 = 0x0000004e # macro +SQ_V_SAT_PK_U8_I16 = 0x0000004f # macro +SQ_V_WRITELANE_IMM32 = 0x00000050 # macro +SQ_V_SWAP_B32 = 0x00000051 # macro +SQ_FLAT_LOAD_UBYTE = 0x00000010 # macro +SQ_FLAT_LOAD_SBYTE = 0x00000011 # macro +SQ_FLAT_LOAD_USHORT = 0x00000012 # macro +SQ_FLAT_LOAD_SSHORT = 0x00000013 # macro +SQ_FLAT_LOAD_DWORD = 0x00000014 # macro +SQ_FLAT_LOAD_DWORDX2 = 0x00000015 # macro +SQ_FLAT_LOAD_DWORDX3 = 0x00000016 # macro +SQ_FLAT_LOAD_DWORDX4 = 0x00000017 # macro +SQ_FLAT_STORE_BYTE = 0x00000018 # macro +SQ_FLAT_STORE_SHORT = 0x0000001a # macro +SQ_FLAT_STORE_DWORD = 0x0000001c # macro +SQ_FLAT_STORE_DWORDX2 = 0x0000001d # macro +SQ_FLAT_STORE_DWORDX3 = 0x0000001e # macro +SQ_FLAT_STORE_DWORDX4 = 0x0000001f # macro +SQ_FLAT_ATOMIC_SWAP = 0x00000040 # macro +SQ_FLAT_ATOMIC_CMPSWAP = 0x00000041 # macro +SQ_FLAT_ATOMIC_ADD = 0x00000042 # macro +SQ_FLAT_ATOMIC_SUB = 0x00000043 # macro +SQ_FLAT_ATOMIC_SMIN = 0x00000044 # macro +SQ_FLAT_ATOMIC_UMIN = 0x00000045 # macro +SQ_FLAT_ATOMIC_SMAX = 0x00000046 # macro +SQ_FLAT_ATOMIC_UMAX = 0x00000047 # macro +SQ_FLAT_ATOMIC_AND = 0x00000048 # macro +SQ_FLAT_ATOMIC_OR = 0x00000049 # macro +SQ_FLAT_ATOMIC_XOR = 0x0000004a # macro +SQ_FLAT_ATOMIC_INC = 0x0000004b # macro +SQ_FLAT_ATOMIC_DEC = 0x0000004c # macro +SQ_FLAT_ATOMIC_SWAP_X2 = 0x00000060 # macro +SQ_FLAT_ATOMIC_CMPSWAP_X2 = 0x00000061 # macro +SQ_FLAT_ATOMIC_ADD_X2 = 0x00000062 # macro +SQ_FLAT_ATOMIC_SUB_X2 = 0x00000063 # macro +SQ_FLAT_ATOMIC_SMIN_X2 = 0x00000064 # macro +SQ_FLAT_ATOMIC_UMIN_X2 = 0x00000065 # macro +SQ_FLAT_ATOMIC_SMAX_X2 = 0x00000066 # macro +SQ_FLAT_ATOMIC_UMAX_X2 = 0x00000067 # macro +SQ_FLAT_ATOMIC_AND_X2 = 0x00000068 # macro +SQ_FLAT_ATOMIC_OR_X2 = 0x00000069 # macro +SQ_FLAT_ATOMIC_XOR_X2 = 0x0000006a # macro +SQ_FLAT_ATOMIC_INC_X2 = 0x0000006b # macro +SQ_FLAT_ATOMIC_DEC_X2 = 0x0000006c # macro +SQ_DS_ADD_U32 = 0x00000000 # macro +SQ_DS_SUB_U32 = 0x00000001 # macro +SQ_DS_RSUB_U32 = 0x00000002 # macro +SQ_DS_INC_U32 = 0x00000003 # macro +SQ_DS_DEC_U32 = 0x00000004 # macro +SQ_DS_MIN_I32 = 0x00000005 # macro +SQ_DS_MAX_I32 = 0x00000006 # macro +SQ_DS_MIN_U32 = 0x00000007 # macro +SQ_DS_MAX_U32 = 0x00000008 # macro +SQ_DS_AND_B32 = 0x00000009 # macro +SQ_DS_OR_B32 = 0x0000000a # macro +SQ_DS_XOR_B32 = 0x0000000b # macro +SQ_DS_MSKOR_B32 = 0x0000000c # macro +SQ_DS_WRITE_B32 = 0x0000000d # macro +SQ_DS_WRITE2_B32 = 0x0000000e # macro +SQ_DS_WRITE2ST64_B32 = 0x0000000f # macro +SQ_DS_CMPST_B32 = 0x00000010 # macro +SQ_DS_CMPST_F32 = 0x00000011 # macro +SQ_DS_MIN_F32 = 0x00000012 # macro +SQ_DS_MAX_F32 = 0x00000013 # macro +SQ_DS_NOP = 0x00000014 # macro +SQ_DS_ADD_F32 = 0x00000015 # macro +SQ_DS_WRITE_ADDTID_B32 = 0x0000001d # macro +SQ_DS_WRITE_B8 = 0x0000001e # macro +SQ_DS_WRITE_B16 = 0x0000001f # macro +SQ_DS_ADD_RTN_U32 = 0x00000020 # macro +SQ_DS_SUB_RTN_U32 = 0x00000021 # macro +SQ_DS_RSUB_RTN_U32 = 0x00000022 # macro +SQ_DS_INC_RTN_U32 = 0x00000023 # macro +SQ_DS_DEC_RTN_U32 = 0x00000024 # macro +SQ_DS_MIN_RTN_I32 = 0x00000025 # macro +SQ_DS_MAX_RTN_I32 = 0x00000026 # macro +SQ_DS_MIN_RTN_U32 = 0x00000027 # macro +SQ_DS_MAX_RTN_U32 = 0x00000028 # macro +SQ_DS_AND_RTN_B32 = 0x00000029 # macro +SQ_DS_OR_RTN_B32 = 0x0000002a # macro +SQ_DS_XOR_RTN_B32 = 0x0000002b # macro +SQ_DS_MSKOR_RTN_B32 = 0x0000002c # macro +SQ_DS_WRXCHG_RTN_B32 = 0x0000002d # macro +SQ_DS_WRXCHG2_RTN_B32 = 0x0000002e # macro +SQ_DS_WRXCHG2ST64_RTN_B32 = 0x0000002f # macro +SQ_DS_CMPST_RTN_B32 = 0x00000030 # macro +SQ_DS_CMPST_RTN_F32 = 0x00000031 # macro +SQ_DS_MIN_RTN_F32 = 0x00000032 # macro +SQ_DS_MAX_RTN_F32 = 0x00000033 # macro +SQ_DS_WRAP_RTN_B32 = 0x00000034 # macro +SQ_DS_ADD_RTN_F32 = 0x00000035 # macro +SQ_DS_READ_B32 = 0x00000036 # macro +SQ_DS_READ2_B32 = 0x00000037 # macro +SQ_DS_READ2ST64_B32 = 0x00000038 # macro +SQ_DS_READ_I8 = 0x00000039 # macro +SQ_DS_READ_U8 = 0x0000003a # macro +SQ_DS_READ_I16 = 0x0000003b # macro +SQ_DS_READ_U16 = 0x0000003c # macro +SQ_DS_SWIZZLE_B32 = 0x0000003d # macro +SQ_DS_PERMUTE_B32 = 0x0000003e # macro +SQ_DS_BPERMUTE_B32 = 0x0000003f # macro +SQ_DS_ADD_U64 = 0x00000040 # macro +SQ_DS_SUB_U64 = 0x00000041 # macro +SQ_DS_RSUB_U64 = 0x00000042 # macro +SQ_DS_INC_U64 = 0x00000043 # macro +SQ_DS_DEC_U64 = 0x00000044 # macro +SQ_DS_MIN_I64 = 0x00000045 # macro +SQ_DS_MAX_I64 = 0x00000046 # macro +SQ_DS_MIN_U64 = 0x00000047 # macro +SQ_DS_MAX_U64 = 0x00000048 # macro +SQ_DS_AND_B64 = 0x00000049 # macro +SQ_DS_OR_B64 = 0x0000004a # macro +SQ_DS_XOR_B64 = 0x0000004b # macro +SQ_DS_MSKOR_B64 = 0x0000004c # macro +SQ_DS_WRITE_B64 = 0x0000004d # macro +SQ_DS_WRITE2_B64 = 0x0000004e # macro +SQ_DS_WRITE2ST64_B64 = 0x0000004f # macro +SQ_DS_CMPST_B64 = 0x00000050 # macro +SQ_DS_CMPST_F64 = 0x00000051 # macro +SQ_DS_MIN_F64 = 0x00000052 # macro +SQ_DS_MAX_F64 = 0x00000053 # macro +SQ_DS_ADD_RTN_U64 = 0x00000060 # macro +SQ_DS_SUB_RTN_U64 = 0x00000061 # macro +SQ_DS_RSUB_RTN_U64 = 0x00000062 # macro +SQ_DS_INC_RTN_U64 = 0x00000063 # macro +SQ_DS_DEC_RTN_U64 = 0x00000064 # macro +SQ_DS_MIN_RTN_I64 = 0x00000065 # macro +SQ_DS_MAX_RTN_I64 = 0x00000066 # macro +SQ_DS_MIN_RTN_U64 = 0x00000067 # macro +SQ_DS_MAX_RTN_U64 = 0x00000068 # macro +SQ_DS_AND_RTN_B64 = 0x00000069 # macro +SQ_DS_OR_RTN_B64 = 0x0000006a # macro +SQ_DS_XOR_RTN_B64 = 0x0000006b # macro +SQ_DS_MSKOR_RTN_B64 = 0x0000006c # macro +SQ_DS_WRXCHG_RTN_B64 = 0x0000006d # macro +SQ_DS_WRXCHG2_RTN_B64 = 0x0000006e # macro +SQ_DS_WRXCHG2ST64_RTN_B64 = 0x0000006f # macro +SQ_DS_CMPST_RTN_B64 = 0x00000070 # macro +SQ_DS_CMPST_RTN_F64 = 0x00000071 # macro +SQ_DS_MIN_RTN_F64 = 0x00000072 # macro +SQ_DS_MAX_RTN_F64 = 0x00000073 # macro +SQ_DS_READ_B64 = 0x00000076 # macro +SQ_DS_READ2_B64 = 0x00000077 # macro +SQ_DS_READ2ST64_B64 = 0x00000078 # macro +SQ_DS_CONDXCHG32_RTN_B64 = 0x0000007e # macro +SQ_DS_ADD_SRC2_U32 = 0x00000080 # macro +SQ_DS_SUB_SRC2_U32 = 0x00000081 # macro +SQ_DS_RSUB_SRC2_U32 = 0x00000082 # macro +SQ_DS_INC_SRC2_U32 = 0x00000083 # macro +SQ_DS_DEC_SRC2_U32 = 0x00000084 # macro +SQ_DS_MIN_SRC2_I32 = 0x00000085 # macro +SQ_DS_MAX_SRC2_I32 = 0x00000086 # macro +SQ_DS_MIN_SRC2_U32 = 0x00000087 # macro +SQ_DS_MAX_SRC2_U32 = 0x00000088 # macro +SQ_DS_AND_SRC2_B32 = 0x00000089 # macro +SQ_DS_OR_SRC2_B32 = 0x0000008a # macro +SQ_DS_XOR_SRC2_B32 = 0x0000008b # macro +SQ_DS_WRITE_SRC2_B32 = 0x0000008d # macro +SQ_DS_MIN_SRC2_F32 = 0x00000092 # macro +SQ_DS_MAX_SRC2_F32 = 0x00000093 # macro +SQ_DS_ADD_SRC2_F32 = 0x00000095 # macro +SQ_DS_GWS_SEMA_RELEASE_ALL = 0x00000098 # macro +SQ_DS_GWS_INIT = 0x00000099 # macro +SQ_DS_GWS_SEMA_V = 0x0000009a # macro +SQ_DS_GWS_SEMA_BR = 0x0000009b # macro +SQ_DS_GWS_SEMA_P = 0x0000009c # macro +SQ_DS_GWS_BARRIER = 0x0000009d # macro +SQ_DS_READ_ADDTID_B32 = 0x000000b6 # macro +SQ_DS_CONSUME = 0x000000bd # macro +SQ_DS_APPEND = 0x000000be # macro +SQ_DS_ORDERED_COUNT = 0x000000bf # macro +SQ_DS_ADD_SRC2_U64 = 0x000000c0 # macro +SQ_DS_SUB_SRC2_U64 = 0x000000c1 # macro +SQ_DS_RSUB_SRC2_U64 = 0x000000c2 # macro +SQ_DS_INC_SRC2_U64 = 0x000000c3 # macro +SQ_DS_DEC_SRC2_U64 = 0x000000c4 # macro +SQ_DS_MIN_SRC2_I64 = 0x000000c5 # macro +SQ_DS_MAX_SRC2_I64 = 0x000000c6 # macro +SQ_DS_MIN_SRC2_U64 = 0x000000c7 # macro +SQ_DS_MAX_SRC2_U64 = 0x000000c8 # macro +SQ_DS_AND_SRC2_B64 = 0x000000c9 # macro +SQ_DS_OR_SRC2_B64 = 0x000000ca # macro +SQ_DS_XOR_SRC2_B64 = 0x000000cb # macro +SQ_DS_WRITE_SRC2_B64 = 0x000000cd # macro +SQ_DS_MIN_SRC2_F64 = 0x000000d2 # macro +SQ_DS_MAX_SRC2_F64 = 0x000000d3 # macro +SQ_DS_WRITE_B96 = 0x000000de # macro +SQ_DS_WRITE_B128 = 0x000000df # macro +SQ_DS_CONDXCHG32_RTN_B128 = 0x000000fd # macro +SQ_DS_READ_B96 = 0x000000fe # macro +SQ_DS_READ_B128 = 0x000000ff # macro +SQ_S_LOAD_DWORD = 0x00000000 # macro +SQ_S_LOAD_DWORDX2 = 0x00000001 # macro +SQ_S_LOAD_DWORDX4 = 0x00000002 # macro +SQ_S_LOAD_DWORDX8 = 0x00000003 # macro +SQ_S_LOAD_DWORDX16 = 0x00000004 # macro +SQ_S_SCRATCH_LOAD_DWORD = 0x00000005 # macro +SQ_S_SCRATCH_LOAD_DWORDX2 = 0x00000006 # macro +SQ_S_SCRATCH_LOAD_DWORDX4 = 0x00000007 # macro +SQ_S_BUFFER_LOAD_DWORD = 0x00000008 # macro +SQ_S_BUFFER_LOAD_DWORDX2 = 0x00000009 # macro +SQ_S_BUFFER_LOAD_DWORDX4 = 0x0000000a # macro +SQ_S_BUFFER_LOAD_DWORDX8 = 0x0000000b # macro +SQ_S_BUFFER_LOAD_DWORDX16 = 0x0000000c # macro +SQ_S_STORE_DWORD = 0x00000010 # macro +SQ_S_STORE_DWORDX2 = 0x00000011 # macro +SQ_S_STORE_DWORDX4 = 0x00000012 # macro +SQ_S_SCRATCH_STORE_DWORD = 0x00000015 # macro +SQ_S_SCRATCH_STORE_DWORDX2 = 0x00000016 # macro +SQ_S_SCRATCH_STORE_DWORDX4 = 0x00000017 # macro +SQ_S_BUFFER_STORE_DWORD = 0x00000018 # macro +SQ_S_BUFFER_STORE_DWORDX2 = 0x00000019 # macro +SQ_S_BUFFER_STORE_DWORDX4 = 0x0000001a # macro +SQ_S_DCACHE_INV = 0x00000020 # macro +SQ_S_DCACHE_WB = 0x00000021 # macro +SQ_S_DCACHE_INV_VOL = 0x00000022 # macro +SQ_S_DCACHE_WB_VOL = 0x00000023 # macro +SQ_S_MEMTIME = 0x00000024 # macro +SQ_S_MEMREALTIME = 0x00000025 # macro +SQ_S_ATC_PROBE = 0x00000026 # macro +SQ_S_ATC_PROBE_BUFFER = 0x00000027 # macro +SQ_S_BUFFER_ATOMIC_SWAP = 0x00000040 # macro +SQ_S_BUFFER_ATOMIC_CMPSWAP = 0x00000041 # macro +SQ_S_BUFFER_ATOMIC_ADD = 0x00000042 # macro +SQ_S_BUFFER_ATOMIC_SUB = 0x00000043 # macro +SQ_S_BUFFER_ATOMIC_SMIN = 0x00000044 # macro +SQ_S_BUFFER_ATOMIC_UMIN = 0x00000045 # macro +SQ_S_BUFFER_ATOMIC_SMAX = 0x00000046 # macro +SQ_S_BUFFER_ATOMIC_UMAX = 0x00000047 # macro +SQ_S_BUFFER_ATOMIC_AND = 0x00000048 # macro +SQ_S_BUFFER_ATOMIC_OR = 0x00000049 # macro +SQ_S_BUFFER_ATOMIC_XOR = 0x0000004a # macro +SQ_S_BUFFER_ATOMIC_INC = 0x0000004b # macro +SQ_S_BUFFER_ATOMIC_DEC = 0x0000004c # macro +SQ_S_BUFFER_ATOMIC_SWAP_X2 = 0x00000060 # macro +SQ_S_BUFFER_ATOMIC_CMPSWAP_X2 = 0x00000061 # macro +SQ_S_BUFFER_ATOMIC_ADD_X2 = 0x00000062 # macro +SQ_S_BUFFER_ATOMIC_SUB_X2 = 0x00000063 # macro +SQ_S_BUFFER_ATOMIC_SMIN_X2 = 0x00000064 # macro +SQ_S_BUFFER_ATOMIC_UMIN_X2 = 0x00000065 # macro +SQ_S_BUFFER_ATOMIC_SMAX_X2 = 0x00000066 # macro +SQ_S_BUFFER_ATOMIC_UMAX_X2 = 0x00000067 # macro +SQ_S_BUFFER_ATOMIC_AND_X2 = 0x00000068 # macro +SQ_S_BUFFER_ATOMIC_OR_X2 = 0x00000069 # macro +SQ_S_BUFFER_ATOMIC_XOR_X2 = 0x0000006a # macro +SQ_S_BUFFER_ATOMIC_INC_X2 = 0x0000006b # macro +SQ_S_BUFFER_ATOMIC_DEC_X2 = 0x0000006c # macro +SQ_S_ATOMIC_SWAP = 0x00000080 # macro +SQ_S_ATOMIC_CMPSWAP = 0x00000081 # macro +SQ_S_ATOMIC_ADD = 0x00000082 # macro +SQ_S_ATOMIC_SUB = 0x00000083 # macro +SQ_S_ATOMIC_SMIN = 0x00000084 # macro +SQ_S_ATOMIC_UMIN = 0x00000085 # macro +SQ_S_ATOMIC_SMAX = 0x00000086 # macro +SQ_S_ATOMIC_UMAX = 0x00000087 # macro +SQ_S_ATOMIC_AND = 0x00000088 # macro +SQ_S_ATOMIC_OR = 0x00000089 # macro +SQ_S_ATOMIC_XOR = 0x0000008a # macro +SQ_S_ATOMIC_INC = 0x0000008b # macro +SQ_S_ATOMIC_DEC = 0x0000008c # macro +SQ_S_ATOMIC_SWAP_X2 = 0x000000a0 # macro +SQ_S_ATOMIC_CMPSWAP_X2 = 0x000000a1 # macro +SQ_S_ATOMIC_ADD_X2 = 0x000000a2 # macro +SQ_S_ATOMIC_SUB_X2 = 0x000000a3 # macro +SQ_S_ATOMIC_SMIN_X2 = 0x000000a4 # macro +SQ_S_ATOMIC_UMIN_X2 = 0x000000a5 # macro +SQ_S_ATOMIC_SMAX_X2 = 0x000000a6 # macro +SQ_S_ATOMIC_UMAX_X2 = 0x000000a7 # macro +SQ_S_ATOMIC_AND_X2 = 0x000000a8 # macro +SQ_S_ATOMIC_OR_X2 = 0x000000a9 # macro +SQ_S_ATOMIC_XOR_X2 = 0x000000aa # macro +SQ_S_ATOMIC_INC_X2 = 0x000000ab # macro +SQ_S_ATOMIC_DEC_X2 = 0x000000ac # macro +SQ_V_CNDMASK_B32 = 0x00000000 # macro +SQ_V_ADD_F32 = 0x00000001 # macro +SQ_V_SUB_F32 = 0x00000002 # macro +SQ_V_SUBREV_F32 = 0x00000003 # macro +SQ_V_MUL_LEGACY_F32 = 0x00000004 # macro +SQ_V_MUL_F32 = 0x00000005 # macro +SQ_V_MUL_I32_I24 = 0x00000006 # macro +SQ_V_MUL_HI_I32_I24 = 0x00000007 # macro +SQ_V_MUL_U32_U24 = 0x00000008 # macro +SQ_V_MUL_HI_U32_U24 = 0x00000009 # macro +SQ_V_MIN_F32 = 0x0000000a # macro +SQ_V_MAX_F32 = 0x0000000b # macro +SQ_V_MIN_I32 = 0x0000000c # macro +SQ_V_MAX_I32 = 0x0000000d # macro +SQ_V_MIN_U32 = 0x0000000e # macro +SQ_V_MAX_U32 = 0x0000000f # macro +SQ_V_LSHRREV_B32 = 0x00000010 # macro +SQ_V_ASHRREV_I32 = 0x00000011 # macro +SQ_V_LSHLREV_B32 = 0x00000012 # macro +SQ_V_AND_B32 = 0x00000013 # macro +SQ_V_OR_B32 = 0x00000014 # macro +SQ_V_XOR_B32 = 0x00000015 # macro +SQ_V_MAC_F32 = 0x00000016 # macro +SQ_V_MADMK_F32 = 0x00000017 # macro +SQ_V_MADAK_F32 = 0x00000018 # macro +SQ_V_ADD_CO_U32 = 0x00000019 # macro +SQ_V_SUB_CO_U32 = 0x0000001a # macro +SQ_V_SUBREV_CO_U32 = 0x0000001b # macro +SQ_V_ADDC_CO_U32 = 0x0000001c # macro +SQ_V_SUBB_CO_U32 = 0x0000001d # macro +SQ_V_SUBBREV_CO_U32 = 0x0000001e # macro +SQ_V_ADD_F16 = 0x0000001f # macro +SQ_V_SUB_F16 = 0x00000020 # macro +SQ_V_SUBREV_F16 = 0x00000021 # macro +SQ_V_MUL_F16 = 0x00000022 # macro +SQ_V_MAC_F16 = 0x00000023 # macro +SQ_V_MADMK_F16 = 0x00000024 # macro +SQ_V_MADAK_F16 = 0x00000025 # macro +SQ_V_ADD_U16 = 0x00000026 # macro +SQ_V_SUB_U16 = 0x00000027 # macro +SQ_V_SUBREV_U16 = 0x00000028 # macro +SQ_V_MUL_LO_U16 = 0x00000029 # macro +SQ_V_LSHLREV_B16 = 0x0000002a # macro +SQ_V_LSHRREV_B16 = 0x0000002b # macro +SQ_V_ASHRREV_I16 = 0x0000002c # macro +SQ_V_MAX_F16 = 0x0000002d # macro +SQ_V_MIN_F16 = 0x0000002e # macro +SQ_V_MAX_U16 = 0x0000002f # macro +SQ_V_MAX_I16 = 0x00000030 # macro +SQ_V_MIN_U16 = 0x00000031 # macro +SQ_V_MIN_I16 = 0x00000032 # macro +SQ_V_LDEXP_F16 = 0x00000033 # macro +SQ_V_ADD_U32 = 0x00000034 # macro +SQ_V_SUB_U32 = 0x00000035 # macro +SQ_V_SUBREV_U32 = 0x00000036 # macro +SQ_SYSMSG_OP_ECC_ERR_INTERRUPT = 0x00000001 # macro +SQ_SYSMSG_OP_REG_RD = 0x00000002 # macro +SQ_SYSMSG_OP_HOST_TRAP_ACK = 0x00000003 # macro +SQ_SYSMSG_OP_TTRACE_PC = 0x00000004 # macro +SQ_SYSMSG_OP_ILLEGAL_INST_INTERRUPT = 0x00000005 # macro +SQ_SYSMSG_OP_MEMVIOL_INTERRUPT = 0x00000006 # macro +SQ_SRC_VCCZ = 0x000000fb # macro +SQ_CHAN_X = 0x00000000 # macro +SQ_CHAN_Y = 0x00000001 # macro +SQ_CHAN_Z = 0x00000002 # macro +SQ_CHAN_W = 0x00000003 # macro +SQ_S_MOVK_I32 = 0x00000000 # macro +SQ_S_CMOVK_I32 = 0x00000001 # macro +SQ_S_CMPK_EQ_I32 = 0x00000002 # macro +SQ_S_CMPK_LG_I32 = 0x00000003 # macro +SQ_S_CMPK_GT_I32 = 0x00000004 # macro +SQ_S_CMPK_GE_I32 = 0x00000005 # macro +SQ_S_CMPK_LT_I32 = 0x00000006 # macro +SQ_S_CMPK_LE_I32 = 0x00000007 # macro +SQ_S_CMPK_EQ_U32 = 0x00000008 # macro +SQ_S_CMPK_LG_U32 = 0x00000009 # macro +SQ_S_CMPK_GT_U32 = 0x0000000a # macro +SQ_S_CMPK_GE_U32 = 0x0000000b # macro +SQ_S_CMPK_LT_U32 = 0x0000000c # macro +SQ_S_CMPK_LE_U32 = 0x0000000d # macro +SQ_S_ADDK_I32 = 0x0000000e # macro +SQ_S_MULK_I32 = 0x0000000f # macro +SQ_S_CBRANCH_I_FORK = 0x00000010 # macro +SQ_S_GETREG_B32 = 0x00000011 # macro +SQ_S_SETREG_B32 = 0x00000012 # macro +SQ_S_GETREG_REGRD_B32 = 0x00000013 # macro +SQ_S_SETREG_IMM32_B32 = 0x00000014 # macro +SQ_S_CALL_B64 = 0x00000015 # macro +SQ_L1 = 0x00000001 # macro +SQ_L2 = 0x00000002 # macro +SQ_L3 = 0x00000003 # macro +SQ_L4 = 0x00000004 # macro +SQ_L5 = 0x00000005 # macro +SQ_L6 = 0x00000006 # macro +SQ_L7 = 0x00000007 # macro +SQ_L8 = 0x00000008 # macro +SQ_L9 = 0x00000009 # macro +SQ_L10 = 0x0000000a # macro +SQ_L11 = 0x0000000b # macro +SQ_L12 = 0x0000000c # macro +SQ_L13 = 0x0000000d # macro +SQ_L14 = 0x0000000e # macro +SQ_L15 = 0x0000000f # macro +SQ_SGPR0 = 0x00000000 # macro +SQ_V_PK_MAD_I16 = 0x00000000 # macro +SQ_V_PK_MUL_LO_U16 = 0x00000001 # macro +SQ_V_PK_ADD_I16 = 0x00000002 # macro +SQ_V_PK_SUB_I16 = 0x00000003 # macro +SQ_V_PK_LSHLREV_B16 = 0x00000004 # macro +SQ_V_PK_LSHRREV_B16 = 0x00000005 # macro +SQ_V_PK_ASHRREV_I16 = 0x00000006 # macro +SQ_V_PK_MAX_I16 = 0x00000007 # macro +SQ_V_PK_MIN_I16 = 0x00000008 # macro +SQ_V_PK_MAD_U16 = 0x00000009 # macro +SQ_V_PK_ADD_U16 = 0x0000000a # macro +SQ_V_PK_SUB_U16 = 0x0000000b # macro +SQ_V_PK_MAX_U16 = 0x0000000c # macro +SQ_V_PK_MIN_U16 = 0x0000000d # macro +SQ_V_PK_MAD_F16 = 0x0000000e # macro +SQ_V_PK_ADD_F16 = 0x0000000f # macro +SQ_V_PK_MUL_F16 = 0x00000010 # macro +SQ_V_PK_MIN_F16 = 0x00000011 # macro +SQ_V_PK_MAX_F16 = 0x00000012 # macro +SQ_V_MAD_MIX_F32 = 0x00000020 # macro +SQ_V_MAD_MIXLO_F16 = 0x00000021 # macro +SQ_V_MAD_MIXHI_F16 = 0x00000022 # macro +SQ_V_INTERP_P1_F32 = 0x00000000 # macro +SQ_V_INTERP_P2_F32 = 0x00000001 # macro +SQ_V_INTERP_MOV_F32 = 0x00000002 # macro +SQ_R1 = 0x00000001 # macro +SQ_R2 = 0x00000002 # macro +SQ_R3 = 0x00000003 # macro +SQ_R4 = 0x00000004 # macro +SQ_R5 = 0x00000005 # macro +SQ_R6 = 0x00000006 # macro +SQ_R7 = 0x00000007 # macro +SQ_R8 = 0x00000008 # macro +SQ_R9 = 0x00000009 # macro +SQ_R10 = 0x0000000a # macro +SQ_R11 = 0x0000000b # macro +SQ_R12 = 0x0000000c # macro +SQ_R13 = 0x0000000d # macro +SQ_R14 = 0x0000000e # macro +SQ_R15 = 0x0000000f # macro +SQ_S_ADD_U32 = 0x00000000 # macro +SQ_S_SUB_U32 = 0x00000001 # macro +SQ_S_ADD_I32 = 0x00000002 # macro +SQ_S_SUB_I32 = 0x00000003 # macro +SQ_S_ADDC_U32 = 0x00000004 # macro +SQ_S_SUBB_U32 = 0x00000005 # macro +SQ_S_MIN_I32 = 0x00000006 # macro +SQ_S_MIN_U32 = 0x00000007 # macro +SQ_S_MAX_I32 = 0x00000008 # macro +SQ_S_MAX_U32 = 0x00000009 # macro +SQ_S_CSELECT_B32 = 0x0000000a # macro +SQ_S_CSELECT_B64 = 0x0000000b # macro +SQ_S_AND_B32 = 0x0000000c # macro +SQ_S_AND_B64 = 0x0000000d # macro +SQ_S_OR_B32 = 0x0000000e # macro +SQ_S_OR_B64 = 0x0000000f # macro +SQ_S_XOR_B32 = 0x00000010 # macro +SQ_S_XOR_B64 = 0x00000011 # macro +SQ_S_ANDN2_B32 = 0x00000012 # macro +SQ_S_ANDN2_B64 = 0x00000013 # macro +SQ_S_ORN2_B32 = 0x00000014 # macro +SQ_S_ORN2_B64 = 0x00000015 # macro +SQ_S_NAND_B32 = 0x00000016 # macro +SQ_S_NAND_B64 = 0x00000017 # macro +SQ_S_NOR_B32 = 0x00000018 # macro +SQ_S_NOR_B64 = 0x00000019 # macro +SQ_S_XNOR_B32 = 0x0000001a # macro +SQ_S_XNOR_B64 = 0x0000001b # macro +SQ_S_LSHL_B32 = 0x0000001c # macro +SQ_S_LSHL_B64 = 0x0000001d # macro +SQ_S_LSHR_B32 = 0x0000001e # macro +SQ_S_LSHR_B64 = 0x0000001f # macro +SQ_S_ASHR_I32 = 0x00000020 # macro +SQ_S_ASHR_I64 = 0x00000021 # macro +SQ_S_BFM_B32 = 0x00000022 # macro +SQ_S_BFM_B64 = 0x00000023 # macro +SQ_S_MUL_I32 = 0x00000024 # macro +SQ_S_BFE_U32 = 0x00000025 # macro +SQ_S_BFE_I32 = 0x00000026 # macro +SQ_S_BFE_U64 = 0x00000027 # macro +SQ_S_BFE_I64 = 0x00000028 # macro +SQ_S_CBRANCH_G_FORK = 0x00000029 # macro +SQ_S_ABSDIFF_I32 = 0x0000002a # macro +SQ_S_RFE_RESTORE_B64 = 0x0000002b # macro +SQ_S_MUL_HI_U32 = 0x0000002c # macro +SQ_S_MUL_HI_I32 = 0x0000002d # macro +SQ_S_LSHL1_ADD_U32 = 0x0000002e # macro +SQ_S_LSHL2_ADD_U32 = 0x0000002f # macro +SQ_S_LSHL3_ADD_U32 = 0x00000030 # macro +SQ_S_LSHL4_ADD_U32 = 0x00000031 # macro +SQ_S_PACK_LL_B32_B16 = 0x00000032 # macro +SQ_S_PACK_LH_B32_B16 = 0x00000033 # macro +SQ_S_PACK_HH_B32_B16 = 0x00000034 # macro +SQ_FLAT = 0x00000000 # macro +SQ_SCRATCH = 0x00000001 # macro +SQ_GLOBAL = 0x00000002 # macro +SQ_EXEC_LO = 0x0000007e # macro +SQ_EXEC_HI = 0x0000007f # macro +SQ_SRC_64_INT = 0x000000c0 # macro +SQ_SRC_M_1_INT = 0x000000c1 # macro +SQ_SRC_M_2_INT = 0x000000c2 # macro +SQ_SRC_M_3_INT = 0x000000c3 # macro +SQ_SRC_M_4_INT = 0x000000c4 # macro +SQ_SRC_M_5_INT = 0x000000c5 # macro +SQ_SRC_M_6_INT = 0x000000c6 # macro +SQ_SRC_M_7_INT = 0x000000c7 # macro +SQ_SRC_M_8_INT = 0x000000c8 # macro +SQ_SRC_M_9_INT = 0x000000c9 # macro +SQ_SRC_M_10_INT = 0x000000ca # macro +SQ_SRC_M_11_INT = 0x000000cb # macro +SQ_SRC_M_12_INT = 0x000000cc # macro +SQ_SRC_M_13_INT = 0x000000cd # macro +SQ_SRC_M_14_INT = 0x000000ce # macro +SQ_SRC_M_15_INT = 0x000000cf # macro +SQ_SRC_M_16_INT = 0x000000d0 # macro +SQ_SRC_0_5 = 0x000000f0 # macro +SQ_SRC_M_0_5 = 0x000000f1 # macro +SQ_SRC_1 = 0x000000f2 # macro +SQ_SRC_M_1 = 0x000000f3 # macro +SQ_SRC_2 = 0x000000f4 # macro +SQ_SRC_M_2 = 0x000000f5 # macro +SQ_SRC_4 = 0x000000f6 # macro +SQ_SRC_M_4 = 0x000000f7 # macro +SQ_SRC_INV_2PI = 0x000000f8 # macro +SQ_VCC_LO = 0x0000006a # macro +SQ_VCC_HI = 0x0000006b # macro +SQ_EXP_MRT0 = 0x00000000 # macro +SQ_EXP_MRTZ = 0x00000008 # macro +SQ_EXP_NULL = 0x00000009 # macro +SQ_EXP_POS0 = 0x0000000c # macro +SQ_EXP_PARAM0 = 0x00000020 # macro +SQ_S_NOP = 0x00000000 # macro +SQ_S_ENDPGM = 0x00000001 # macro +SQ_S_BRANCH = 0x00000002 # macro +SQ_S_WAKEUP = 0x00000003 # macro +SQ_S_CBRANCH_SCC0 = 0x00000004 # macro +SQ_S_CBRANCH_SCC1 = 0x00000005 # macro +SQ_S_CBRANCH_VCCZ = 0x00000006 # macro +SQ_S_CBRANCH_VCCNZ = 0x00000007 # macro +SQ_S_CBRANCH_EXECZ = 0x00000008 # macro +SQ_S_CBRANCH_EXECNZ = 0x00000009 # macro +SQ_S_BARRIER = 0x0000000a # macro +SQ_S_SETKILL = 0x0000000b # macro +SQ_S_WAITCNT = 0x0000000c # macro +SQ_S_SETHALT = 0x0000000d # macro +SQ_S_SLEEP = 0x0000000e # macro +SQ_S_SETPRIO = 0x0000000f # macro +SQ_S_SENDMSG = 0x00000010 # macro +SQ_S_SENDMSGHALT = 0x00000011 # macro +SQ_S_TRAP = 0x00000012 # macro +SQ_S_ICACHE_INV = 0x00000013 # macro +SQ_S_INCPERFLEVEL = 0x00000014 # macro +SQ_S_DECPERFLEVEL = 0x00000015 # macro +SQ_S_TTRACEDATA = 0x00000016 # macro +SQ_S_CBRANCH_CDBGSYS = 0x00000017 # macro +SQ_S_CBRANCH_CDBGUSER = 0x00000018 # macro +SQ_S_CBRANCH_CDBGSYS_OR_USER = 0x00000019 # macro +SQ_S_CBRANCH_CDBGSYS_AND_USER = 0x0000001a # macro +SQ_S_ENDPGM_SAVED = 0x0000001b # macro +SQ_S_SET_GPR_IDX_OFF = 0x0000001c # macro +SQ_S_SET_GPR_IDX_MODE = 0x0000001d # macro +SQ_S_ENDPGM_ORDERED_PS_DONE = 0x0000001e # macro +SQ_EXP = 0x00000000 # macro +SQ_SRC_POPS_EXITING_WAVE_ID = 0x000000ef # macro +SQ_XNACK_MASK_LO = 0x00000068 # macro +SQ_XNACK_MASK_HI = 0x00000069 # macro +SQ_OMOD_OFF = 0x00000000 # macro +SQ_OMOD_M2 = 0x00000001 # macro +SQ_OMOD_M4 = 0x00000002 # macro +SQ_OMOD_D2 = 0x00000003 # macro +SQ_SRC_EXECZ = 0x000000fc # macro +SQ_F = 0x00000000 # macro +SQ_LT = 0x00000001 # macro +SQ_EQ = 0x00000002 # macro +SQ_LE = 0x00000003 # macro +SQ_GT = 0x00000004 # macro +SQ_NE = 0x00000005 # macro +SQ_GE = 0x00000006 # macro +SQ_T = 0x00000007 # macro +SQ_DPP_BOUND_OFF = 0x00000000 # macro +SQ_DPP_BOUND_ZERO = 0x00000001 # macro +SQ_M0 = 0x0000007c # macro +SQ_MSG_INTERRUPT = 0x00000001 # macro +SQ_MSG_GS = 0x00000002 # macro +SQ_MSG_GS_DONE = 0x00000003 # macro +SQ_MSG_SAVEWAVE = 0x00000004 # macro +SQ_MSG_STALL_WAVE_GEN = 0x00000005 # macro +SQ_MSG_HALT_WAVES = 0x00000006 # macro +SQ_MSG_ORDERED_PS_DONE = 0x00000007 # macro +SQ_MSG_EARLY_PRIM_DEALLOC = 0x00000008 # macro +SQ_MSG_GS_ALLOC_REQ = 0x00000009 # macro +SQ_MSG_SYSMSG = 0x0000000f # macro +SQ_PARAM_P10 = 0x00000000 # macro +SQ_PARAM_P20 = 0x00000001 # macro +SQ_PARAM_P0 = 0x00000002 # macro +SQ_V_OPC_OFFSET = 0x00000000 # macro +SQ_V_OP2_OFFSET = 0x00000100 # macro +SQ_V_OP1_OFFSET = 0x00000140 # macro +SQ_V_INTRP_OFFSET = 0x00000270 # macro +SQ_V_OP3P_OFFSET = 0x00000380 # macro +SQ_SRC_SDWA = 0x000000f9 # macro +SQ_SRC_SHARED_BASE = 0x000000eb # macro +SQ_SRC_SHARED_LIMIT = 0x000000ec # macro +SQ_SRC_PRIVATE_BASE = 0x000000ed # macro +SQ_SRC_PRIVATE_LIMIT = 0x000000ee # macro +SQ_LG = 0x00000005 # macro +SQ_O = 0x00000007 # macro +SQ_U = 0x00000008 # macro +SQ_NGE = 0x00000009 # macro +SQ_NLG = 0x0000000a # macro +SQ_NGT = 0x0000000b # macro +SQ_NLE = 0x0000000c # macro +SQ_NEQ = 0x0000000d # macro +SQ_NLT = 0x0000000e # macro +SQ_TRU = 0x0000000f # macro +SQ_SDWA_UNUSED_PAD = 0x00000000 # macro +SQ_SDWA_UNUSED_SEXT = 0x00000001 # macro +SQ_SDWA_UNUSED_PRESERVE = 0x00000002 # macro +SQ_SRC_SCC = 0x000000fd # macro +SQ_V_CMP_CLASS_F32 = 0x00000010 # macro +SQ_V_CMPX_CLASS_F32 = 0x00000011 # macro +SQ_V_CMP_CLASS_F64 = 0x00000012 # macro +SQ_V_CMPX_CLASS_F64 = 0x00000013 # macro +SQ_V_CMP_CLASS_F16 = 0x00000014 # macro +SQ_V_CMPX_CLASS_F16 = 0x00000015 # macro +SQ_V_CMP_F_F16 = 0x00000020 # macro +SQ_V_CMP_LT_F16 = 0x00000021 # macro +SQ_V_CMP_EQ_F16 = 0x00000022 # macro +SQ_V_CMP_LE_F16 = 0x00000023 # macro +SQ_V_CMP_GT_F16 = 0x00000024 # macro +SQ_V_CMP_LG_F16 = 0x00000025 # macro +SQ_V_CMP_GE_F16 = 0x00000026 # macro +SQ_V_CMP_O_F16 = 0x00000027 # macro +SQ_V_CMP_U_F16 = 0x00000028 # macro +SQ_V_CMP_NGE_F16 = 0x00000029 # macro +SQ_V_CMP_NLG_F16 = 0x0000002a # macro +SQ_V_CMP_NGT_F16 = 0x0000002b # macro +SQ_V_CMP_NLE_F16 = 0x0000002c # macro +SQ_V_CMP_NEQ_F16 = 0x0000002d # macro +SQ_V_CMP_NLT_F16 = 0x0000002e # macro +SQ_V_CMP_TRU_F16 = 0x0000002f # macro +SQ_V_CMPX_F_F16 = 0x00000030 # macro +SQ_V_CMPX_LT_F16 = 0x00000031 # macro +SQ_V_CMPX_EQ_F16 = 0x00000032 # macro +SQ_V_CMPX_LE_F16 = 0x00000033 # macro +SQ_V_CMPX_GT_F16 = 0x00000034 # macro +SQ_V_CMPX_LG_F16 = 0x00000035 # macro +SQ_V_CMPX_GE_F16 = 0x00000036 # macro +SQ_V_CMPX_O_F16 = 0x00000037 # macro +SQ_V_CMPX_U_F16 = 0x00000038 # macro +SQ_V_CMPX_NGE_F16 = 0x00000039 # macro +SQ_V_CMPX_NLG_F16 = 0x0000003a # macro +SQ_V_CMPX_NGT_F16 = 0x0000003b # macro +SQ_V_CMPX_NLE_F16 = 0x0000003c # macro +SQ_V_CMPX_NEQ_F16 = 0x0000003d # macro +SQ_V_CMPX_NLT_F16 = 0x0000003e # macro +SQ_V_CMPX_TRU_F16 = 0x0000003f # macro +SQ_V_CMP_F_F32 = 0x00000040 # macro +SQ_V_CMP_LT_F32 = 0x00000041 # macro +SQ_V_CMP_EQ_F32 = 0x00000042 # macro +SQ_V_CMP_LE_F32 = 0x00000043 # macro +SQ_V_CMP_GT_F32 = 0x00000044 # macro +SQ_V_CMP_LG_F32 = 0x00000045 # macro +SQ_V_CMP_GE_F32 = 0x00000046 # macro +SQ_V_CMP_O_F32 = 0x00000047 # macro +SQ_V_CMP_U_F32 = 0x00000048 # macro +SQ_V_CMP_NGE_F32 = 0x00000049 # macro +SQ_V_CMP_NLG_F32 = 0x0000004a # macro +SQ_V_CMP_NGT_F32 = 0x0000004b # macro +SQ_V_CMP_NLE_F32 = 0x0000004c # macro +SQ_V_CMP_NEQ_F32 = 0x0000004d # macro +SQ_V_CMP_NLT_F32 = 0x0000004e # macro +SQ_V_CMP_TRU_F32 = 0x0000004f # macro +SQ_V_CMPX_F_F32 = 0x00000050 # macro +SQ_V_CMPX_LT_F32 = 0x00000051 # macro +SQ_V_CMPX_EQ_F32 = 0x00000052 # macro +SQ_V_CMPX_LE_F32 = 0x00000053 # macro +SQ_V_CMPX_GT_F32 = 0x00000054 # macro +SQ_V_CMPX_LG_F32 = 0x00000055 # macro +SQ_V_CMPX_GE_F32 = 0x00000056 # macro +SQ_V_CMPX_O_F32 = 0x00000057 # macro +SQ_V_CMPX_U_F32 = 0x00000058 # macro +SQ_V_CMPX_NGE_F32 = 0x00000059 # macro +SQ_V_CMPX_NLG_F32 = 0x0000005a # macro +SQ_V_CMPX_NGT_F32 = 0x0000005b # macro +SQ_V_CMPX_NLE_F32 = 0x0000005c # macro +SQ_V_CMPX_NEQ_F32 = 0x0000005d # macro +SQ_V_CMPX_NLT_F32 = 0x0000005e # macro +SQ_V_CMPX_TRU_F32 = 0x0000005f # macro +SQ_V_CMP_F_F64 = 0x00000060 # macro +SQ_V_CMP_LT_F64 = 0x00000061 # macro +SQ_V_CMP_EQ_F64 = 0x00000062 # macro +SQ_V_CMP_LE_F64 = 0x00000063 # macro +SQ_V_CMP_GT_F64 = 0x00000064 # macro +SQ_V_CMP_LG_F64 = 0x00000065 # macro +SQ_V_CMP_GE_F64 = 0x00000066 # macro +SQ_V_CMP_O_F64 = 0x00000067 # macro +SQ_V_CMP_U_F64 = 0x00000068 # macro +SQ_V_CMP_NGE_F64 = 0x00000069 # macro +SQ_V_CMP_NLG_F64 = 0x0000006a # macro +SQ_V_CMP_NGT_F64 = 0x0000006b # macro +SQ_V_CMP_NLE_F64 = 0x0000006c # macro +SQ_V_CMP_NEQ_F64 = 0x0000006d # macro +SQ_V_CMP_NLT_F64 = 0x0000006e # macro +SQ_V_CMP_TRU_F64 = 0x0000006f # macro +SQ_V_CMPX_F_F64 = 0x00000070 # macro +SQ_V_CMPX_LT_F64 = 0x00000071 # macro +SQ_V_CMPX_EQ_F64 = 0x00000072 # macro +SQ_V_CMPX_LE_F64 = 0x00000073 # macro +SQ_V_CMPX_GT_F64 = 0x00000074 # macro +SQ_V_CMPX_LG_F64 = 0x00000075 # macro +SQ_V_CMPX_GE_F64 = 0x00000076 # macro +SQ_V_CMPX_O_F64 = 0x00000077 # macro +SQ_V_CMPX_U_F64 = 0x00000078 # macro +SQ_V_CMPX_NGE_F64 = 0x00000079 # macro +SQ_V_CMPX_NLG_F64 = 0x0000007a # macro +SQ_V_CMPX_NGT_F64 = 0x0000007b # macro +SQ_V_CMPX_NLE_F64 = 0x0000007c # macro +SQ_V_CMPX_NEQ_F64 = 0x0000007d # macro +SQ_V_CMPX_NLT_F64 = 0x0000007e # macro +SQ_V_CMPX_TRU_F64 = 0x0000007f # macro +SQ_V_CMP_F_I16 = 0x000000a0 # macro +SQ_V_CMP_LT_I16 = 0x000000a1 # macro +SQ_V_CMP_EQ_I16 = 0x000000a2 # macro +SQ_V_CMP_LE_I16 = 0x000000a3 # macro +SQ_V_CMP_GT_I16 = 0x000000a4 # macro +SQ_V_CMP_NE_I16 = 0x000000a5 # macro +SQ_V_CMP_GE_I16 = 0x000000a6 # macro +SQ_V_CMP_T_I16 = 0x000000a7 # macro +SQ_V_CMP_F_U16 = 0x000000a8 # macro +SQ_V_CMP_LT_U16 = 0x000000a9 # macro +SQ_V_CMP_EQ_U16 = 0x000000aa # macro +SQ_V_CMP_LE_U16 = 0x000000ab # macro +SQ_V_CMP_GT_U16 = 0x000000ac # macro +SQ_V_CMP_NE_U16 = 0x000000ad # macro +SQ_V_CMP_GE_U16 = 0x000000ae # macro +SQ_V_CMP_T_U16 = 0x000000af # macro +SQ_V_CMPX_F_I16 = 0x000000b0 # macro +SQ_V_CMPX_LT_I16 = 0x000000b1 # macro +SQ_V_CMPX_EQ_I16 = 0x000000b2 # macro +SQ_V_CMPX_LE_I16 = 0x000000b3 # macro +SQ_V_CMPX_GT_I16 = 0x000000b4 # macro +SQ_V_CMPX_NE_I16 = 0x000000b5 # macro +SQ_V_CMPX_GE_I16 = 0x000000b6 # macro +SQ_V_CMPX_T_I16 = 0x000000b7 # macro +SQ_V_CMPX_F_U16 = 0x000000b8 # macro +SQ_V_CMPX_LT_U16 = 0x000000b9 # macro +SQ_V_CMPX_EQ_U16 = 0x000000ba # macro +SQ_V_CMPX_LE_U16 = 0x000000bb # macro +SQ_V_CMPX_GT_U16 = 0x000000bc # macro +SQ_V_CMPX_NE_U16 = 0x000000bd # macro +SQ_V_CMPX_GE_U16 = 0x000000be # macro +SQ_V_CMPX_T_U16 = 0x000000bf # macro +SQ_V_CMP_F_I32 = 0x000000c0 # macro +SQ_V_CMP_LT_I32 = 0x000000c1 # macro +SQ_V_CMP_EQ_I32 = 0x000000c2 # macro +SQ_V_CMP_LE_I32 = 0x000000c3 # macro +SQ_V_CMP_GT_I32 = 0x000000c4 # macro +SQ_V_CMP_NE_I32 = 0x000000c5 # macro +SQ_V_CMP_GE_I32 = 0x000000c6 # macro +SQ_V_CMP_T_I32 = 0x000000c7 # macro +SQ_V_CMP_F_U32 = 0x000000c8 # macro +SQ_V_CMP_LT_U32 = 0x000000c9 # macro +SQ_V_CMP_EQ_U32 = 0x000000ca # macro +SQ_V_CMP_LE_U32 = 0x000000cb # macro +SQ_V_CMP_GT_U32 = 0x000000cc # macro +SQ_V_CMP_NE_U32 = 0x000000cd # macro +SQ_V_CMP_GE_U32 = 0x000000ce # macro +SQ_V_CMP_T_U32 = 0x000000cf # macro +SQ_V_CMPX_F_I32 = 0x000000d0 # macro +SQ_V_CMPX_LT_I32 = 0x000000d1 # macro +SQ_V_CMPX_EQ_I32 = 0x000000d2 # macro +SQ_V_CMPX_LE_I32 = 0x000000d3 # macro +SQ_V_CMPX_GT_I32 = 0x000000d4 # macro +SQ_V_CMPX_NE_I32 = 0x000000d5 # macro +SQ_V_CMPX_GE_I32 = 0x000000d6 # macro +SQ_V_CMPX_T_I32 = 0x000000d7 # macro +SQ_V_CMPX_F_U32 = 0x000000d8 # macro +SQ_V_CMPX_LT_U32 = 0x000000d9 # macro +SQ_V_CMPX_EQ_U32 = 0x000000da # macro +SQ_V_CMPX_LE_U32 = 0x000000db # macro +SQ_V_CMPX_GT_U32 = 0x000000dc # macro +SQ_V_CMPX_NE_U32 = 0x000000dd # macro +SQ_V_CMPX_GE_U32 = 0x000000de # macro +SQ_V_CMPX_T_U32 = 0x000000df # macro +SQ_V_CMP_F_I64 = 0x000000e0 # macro +SQ_V_CMP_LT_I64 = 0x000000e1 # macro +SQ_V_CMP_EQ_I64 = 0x000000e2 # macro +SQ_V_CMP_LE_I64 = 0x000000e3 # macro +SQ_V_CMP_GT_I64 = 0x000000e4 # macro +SQ_V_CMP_NE_I64 = 0x000000e5 # macro +SQ_V_CMP_GE_I64 = 0x000000e6 # macro +SQ_V_CMP_T_I64 = 0x000000e7 # macro +SQ_V_CMP_F_U64 = 0x000000e8 # macro +SQ_V_CMP_LT_U64 = 0x000000e9 # macro +SQ_V_CMP_EQ_U64 = 0x000000ea # macro +SQ_V_CMP_LE_U64 = 0x000000eb # macro +SQ_V_CMP_GT_U64 = 0x000000ec # macro +SQ_V_CMP_NE_U64 = 0x000000ed # macro +SQ_V_CMP_GE_U64 = 0x000000ee # macro +SQ_V_CMP_T_U64 = 0x000000ef # macro +SQ_V_CMPX_F_I64 = 0x000000f0 # macro +SQ_V_CMPX_LT_I64 = 0x000000f1 # macro +SQ_V_CMPX_EQ_I64 = 0x000000f2 # macro +SQ_V_CMPX_LE_I64 = 0x000000f3 # macro +SQ_V_CMPX_GT_I64 = 0x000000f4 # macro +SQ_V_CMPX_NE_I64 = 0x000000f5 # macro +SQ_V_CMPX_GE_I64 = 0x000000f6 # macro +SQ_V_CMPX_T_I64 = 0x000000f7 # macro +SQ_V_CMPX_F_U64 = 0x000000f8 # macro +SQ_V_CMPX_LT_U64 = 0x000000f9 # macro +SQ_V_CMPX_EQ_U64 = 0x000000fa # macro +SQ_V_CMPX_LE_U64 = 0x000000fb # macro +SQ_V_CMPX_GT_U64 = 0x000000fc # macro +SQ_V_CMPX_NE_U64 = 0x000000fd # macro +SQ_V_CMPX_GE_U64 = 0x000000fe # macro +SQ_V_CMPX_T_U64 = 0x000000ff # macro +SQ_GS_OP_NOP = 0x00000000 # macro +SQ_GS_OP_CUT = 0x00000001 # macro +SQ_GS_OP_EMIT = 0x00000002 # macro +SQ_GS_OP_EMIT_CUT = 0x00000003 # macro +SQ_SRC_LDS_DIRECT = 0x000000fe # macro +SQ_ATTR0 = 0x00000000 # macro +SQ_EXP_GDS0 = 0x00000018 # macro +SQ_S_CMP_EQ_I32 = 0x00000000 # macro +SQ_S_CMP_LG_I32 = 0x00000001 # macro +SQ_S_CMP_GT_I32 = 0x00000002 # macro +SQ_S_CMP_GE_I32 = 0x00000003 # macro +SQ_S_CMP_LT_I32 = 0x00000004 # macro +SQ_S_CMP_LE_I32 = 0x00000005 # macro +SQ_S_CMP_EQ_U32 = 0x00000006 # macro +SQ_S_CMP_LG_U32 = 0x00000007 # macro +SQ_S_CMP_GT_U32 = 0x00000008 # macro +SQ_S_CMP_GE_U32 = 0x00000009 # macro +SQ_S_CMP_LT_U32 = 0x0000000a # macro +SQ_S_CMP_LE_U32 = 0x0000000b # macro +SQ_S_BITCMP0_B32 = 0x0000000c # macro +SQ_S_BITCMP1_B32 = 0x0000000d # macro +SQ_S_BITCMP0_B64 = 0x0000000e # macro +SQ_S_BITCMP1_B64 = 0x0000000f # macro +SQ_S_SETVSKIP = 0x00000010 # macro +SQ_S_SET_GPR_IDX_ON = 0x00000011 # macro +SQ_S_CMP_EQ_U64 = 0x00000012 # macro +SQ_S_CMP_LG_U64 = 0x00000013 # macro +SQ_TTMP0 = 0x0000006c # macro +SQ_TTMP1 = 0x0000006d # macro +SQ_TTMP2 = 0x0000006e # macro +SQ_TTMP3 = 0x0000006f # macro +SQ_TTMP4 = 0x00000070 # macro +SQ_TTMP5 = 0x00000071 # macro +SQ_TTMP6 = 0x00000072 # macro +SQ_TTMP7 = 0x00000073 # macro +SQ_TTMP8 = 0x00000074 # macro +SQ_TTMP9 = 0x00000075 # macro +SQ_TTMP10 = 0x00000076 # macro +SQ_TTMP11 = 0x00000077 # macro +SQ_TTMP12 = 0x00000078 # macro +SQ_TTMP13 = 0x00000079 # macro +SQ_TTMP14 = 0x0000007a # macro +SQ_TTMP15 = 0x0000007b # macro +SQ_SRC_VGPR0 = 0x00000100 # macro +SQ_BUFFER_LOAD_FORMAT_X = 0x00000000 # macro +SQ_BUFFER_LOAD_FORMAT_XY = 0x00000001 # macro +SQ_BUFFER_LOAD_FORMAT_XYZ = 0x00000002 # macro +SQ_BUFFER_LOAD_FORMAT_XYZW = 0x00000003 # macro +SQ_BUFFER_STORE_FORMAT_X = 0x00000004 # macro +SQ_BUFFER_STORE_FORMAT_XY = 0x00000005 # macro +SQ_BUFFER_STORE_FORMAT_XYZ = 0x00000006 # macro +SQ_BUFFER_STORE_FORMAT_XYZW = 0x00000007 # macro +SQ_BUFFER_LOAD_FORMAT_D16_X = 0x00000008 # macro +SQ_BUFFER_LOAD_FORMAT_D16_XY = 0x00000009 # macro +SQ_BUFFER_LOAD_FORMAT_D16_XYZ = 0x0000000a # macro +SQ_BUFFER_LOAD_FORMAT_D16_XYZW = 0x0000000b # macro +SQ_BUFFER_STORE_FORMAT_D16_X = 0x0000000c # macro +SQ_BUFFER_STORE_FORMAT_D16_XY = 0x0000000d # macro +SQ_BUFFER_STORE_FORMAT_D16_XYZ = 0x0000000e # macro +SQ_BUFFER_STORE_FORMAT_D16_XYZW = 0x0000000f # macro +SQ_BUFFER_LOAD_UBYTE = 0x00000010 # macro +SQ_BUFFER_LOAD_SBYTE = 0x00000011 # macro +SQ_BUFFER_LOAD_USHORT = 0x00000012 # macro +SQ_BUFFER_LOAD_SSHORT = 0x00000013 # macro +SQ_BUFFER_LOAD_DWORD = 0x00000014 # macro +SQ_BUFFER_LOAD_DWORDX2 = 0x00000015 # macro +SQ_BUFFER_LOAD_DWORDX3 = 0x00000016 # macro +SQ_BUFFER_LOAD_DWORDX4 = 0x00000017 # macro +SQ_BUFFER_STORE_BYTE = 0x00000018 # macro +SQ_BUFFER_STORE_SHORT = 0x0000001a # macro +SQ_BUFFER_STORE_DWORD = 0x0000001c # macro +SQ_BUFFER_STORE_DWORDX2 = 0x0000001d # macro +SQ_BUFFER_STORE_DWORDX3 = 0x0000001e # macro +SQ_BUFFER_STORE_DWORDX4 = 0x0000001f # macro +SQ_BUFFER_STORE_LDS_DWORD = 0x0000003d # macro +SQ_BUFFER_WBINVL1 = 0x0000003e # macro +SQ_BUFFER_WBINVL1_VOL = 0x0000003f # macro +SQ_BUFFER_ATOMIC_SWAP = 0x00000040 # macro +SQ_BUFFER_ATOMIC_CMPSWAP = 0x00000041 # macro +SQ_BUFFER_ATOMIC_ADD = 0x00000042 # macro +SQ_BUFFER_ATOMIC_SUB = 0x00000043 # macro +SQ_BUFFER_ATOMIC_SMIN = 0x00000044 # macro +SQ_BUFFER_ATOMIC_UMIN = 0x00000045 # macro +SQ_BUFFER_ATOMIC_SMAX = 0x00000046 # macro +SQ_BUFFER_ATOMIC_UMAX = 0x00000047 # macro +SQ_BUFFER_ATOMIC_AND = 0x00000048 # macro +SQ_BUFFER_ATOMIC_OR = 0x00000049 # macro +SQ_BUFFER_ATOMIC_XOR = 0x0000004a # macro +SQ_BUFFER_ATOMIC_INC = 0x0000004b # macro +SQ_BUFFER_ATOMIC_DEC = 0x0000004c # macro +SQ_BUFFER_ATOMIC_SWAP_X2 = 0x00000060 # macro +SQ_BUFFER_ATOMIC_CMPSWAP_X2 = 0x00000061 # macro +SQ_BUFFER_ATOMIC_ADD_X2 = 0x00000062 # macro +SQ_BUFFER_ATOMIC_SUB_X2 = 0x00000063 # macro +SQ_BUFFER_ATOMIC_SMIN_X2 = 0x00000064 # macro +SQ_BUFFER_ATOMIC_UMIN_X2 = 0x00000065 # macro +SQ_BUFFER_ATOMIC_SMAX_X2 = 0x00000066 # macro +SQ_BUFFER_ATOMIC_UMAX_X2 = 0x00000067 # macro +SQ_BUFFER_ATOMIC_AND_X2 = 0x00000068 # macro +SQ_BUFFER_ATOMIC_OR_X2 = 0x00000069 # macro +SQ_BUFFER_ATOMIC_XOR_X2 = 0x0000006a # macro +SQ_BUFFER_ATOMIC_INC_X2 = 0x0000006b # macro +SQ_BUFFER_ATOMIC_DEC_X2 = 0x0000006c # macro +SQ_SDWA_BYTE_0 = 0x00000000 # macro +SQ_SDWA_BYTE_1 = 0x00000001 # macro +SQ_SDWA_BYTE_2 = 0x00000002 # macro +SQ_SDWA_BYTE_3 = 0x00000003 # macro +SQ_SDWA_WORD_0 = 0x00000004 # macro +SQ_SDWA_WORD_1 = 0x00000005 # macro +SQ_SDWA_DWORD = 0x00000006 # macro +ROM_SIGNATURE = 0x0000aa55 # macro + +# values for enumeration 'GDS_PERFCOUNT_SELECT' +GDS_PERFCOUNT_SELECT__enumvalues = { + 0: 'GDS_PERF_SEL_DS_ADDR_CONFL', + 1: 'GDS_PERF_SEL_DS_BANK_CONFL', + 2: 'GDS_PERF_SEL_WBUF_FLUSH', + 3: 'GDS_PERF_SEL_WR_COMP', + 4: 'GDS_PERF_SEL_WBUF_WR', + 5: 'GDS_PERF_SEL_RBUF_HIT', + 6: 'GDS_PERF_SEL_RBUF_MISS', + 7: 'GDS_PERF_SEL_SE0_SH0_NORET', + 8: 'GDS_PERF_SEL_SE0_SH0_RET', + 9: 'GDS_PERF_SEL_SE0_SH0_ORD_CNT', + 10: 'GDS_PERF_SEL_SE0_SH0_2COMP_REQ', + 11: 'GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID', + 12: 'GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID', + 13: 'GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD', + 14: 'GDS_PERF_SEL_SE0_SH0_GDS_WR_OP', + 15: 'GDS_PERF_SEL_SE0_SH0_GDS_RD_OP', + 16: 'GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP', + 17: 'GDS_PERF_SEL_SE0_SH0_GDS_REL_OP', + 18: 'GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP', + 19: 'GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP', + 20: 'GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP', + 21: 'GDS_PERF_SEL_SE0_SH1_NORET', + 22: 'GDS_PERF_SEL_SE0_SH1_RET', + 23: 'GDS_PERF_SEL_SE0_SH1_ORD_CNT', + 24: 'GDS_PERF_SEL_SE0_SH1_2COMP_REQ', + 25: 'GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID', + 26: 'GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID', + 27: 'GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD', + 28: 'GDS_PERF_SEL_SE0_SH1_GDS_WR_OP', + 29: 'GDS_PERF_SEL_SE0_SH1_GDS_RD_OP', + 30: 'GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP', + 31: 'GDS_PERF_SEL_SE0_SH1_GDS_REL_OP', + 32: 'GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP', + 33: 'GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP', + 34: 'GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP', + 35: 'GDS_PERF_SEL_SE1_SH0_NORET', + 36: 'GDS_PERF_SEL_SE1_SH0_RET', + 37: 'GDS_PERF_SEL_SE1_SH0_ORD_CNT', + 38: 'GDS_PERF_SEL_SE1_SH0_2COMP_REQ', + 39: 'GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID', + 40: 'GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID', + 41: 'GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD', + 42: 'GDS_PERF_SEL_SE1_SH0_GDS_WR_OP', + 43: 'GDS_PERF_SEL_SE1_SH0_GDS_RD_OP', + 44: 'GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP', + 45: 'GDS_PERF_SEL_SE1_SH0_GDS_REL_OP', + 46: 'GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP', + 47: 'GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP', + 48: 'GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP', + 49: 'GDS_PERF_SEL_SE1_SH1_NORET', + 50: 'GDS_PERF_SEL_SE1_SH1_RET', + 51: 'GDS_PERF_SEL_SE1_SH1_ORD_CNT', + 52: 'GDS_PERF_SEL_SE1_SH1_2COMP_REQ', + 53: 'GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID', + 54: 'GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID', + 55: 'GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD', + 56: 'GDS_PERF_SEL_SE1_SH1_GDS_WR_OP', + 57: 'GDS_PERF_SEL_SE1_SH1_GDS_RD_OP', + 58: 'GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP', + 59: 'GDS_PERF_SEL_SE1_SH1_GDS_REL_OP', + 60: 'GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP', + 61: 'GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP', + 62: 'GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP', + 63: 'GDS_PERF_SEL_SE2_SH0_NORET', + 64: 'GDS_PERF_SEL_SE2_SH0_RET', + 65: 'GDS_PERF_SEL_SE2_SH0_ORD_CNT', + 66: 'GDS_PERF_SEL_SE2_SH0_2COMP_REQ', + 67: 'GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID', + 68: 'GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID', + 69: 'GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD', + 70: 'GDS_PERF_SEL_SE2_SH0_GDS_WR_OP', + 71: 'GDS_PERF_SEL_SE2_SH0_GDS_RD_OP', + 72: 'GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP', + 73: 'GDS_PERF_SEL_SE2_SH0_GDS_REL_OP', + 74: 'GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP', + 75: 'GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP', + 76: 'GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP', + 77: 'GDS_PERF_SEL_SE2_SH1_NORET', + 78: 'GDS_PERF_SEL_SE2_SH1_RET', + 79: 'GDS_PERF_SEL_SE2_SH1_ORD_CNT', + 80: 'GDS_PERF_SEL_SE2_SH1_2COMP_REQ', + 81: 'GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID', + 82: 'GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID', + 83: 'GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD', + 84: 'GDS_PERF_SEL_SE2_SH1_GDS_WR_OP', + 85: 'GDS_PERF_SEL_SE2_SH1_GDS_RD_OP', + 86: 'GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP', + 87: 'GDS_PERF_SEL_SE2_SH1_GDS_REL_OP', + 88: 'GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP', + 89: 'GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP', + 90: 'GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP', + 91: 'GDS_PERF_SEL_SE3_SH0_NORET', + 92: 'GDS_PERF_SEL_SE3_SH0_RET', + 93: 'GDS_PERF_SEL_SE3_SH0_ORD_CNT', + 94: 'GDS_PERF_SEL_SE3_SH0_2COMP_REQ', + 95: 'GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID', + 96: 'GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID', + 97: 'GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD', + 98: 'GDS_PERF_SEL_SE3_SH0_GDS_WR_OP', + 99: 'GDS_PERF_SEL_SE3_SH0_GDS_RD_OP', + 100: 'GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP', + 101: 'GDS_PERF_SEL_SE3_SH0_GDS_REL_OP', + 102: 'GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP', + 103: 'GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP', + 104: 'GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP', + 105: 'GDS_PERF_SEL_SE3_SH1_NORET', + 106: 'GDS_PERF_SEL_SE3_SH1_RET', + 107: 'GDS_PERF_SEL_SE3_SH1_ORD_CNT', + 108: 'GDS_PERF_SEL_SE3_SH1_2COMP_REQ', + 109: 'GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID', + 110: 'GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID', + 111: 'GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD', + 112: 'GDS_PERF_SEL_SE3_SH1_GDS_WR_OP', + 113: 'GDS_PERF_SEL_SE3_SH1_GDS_RD_OP', + 114: 'GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP', + 115: 'GDS_PERF_SEL_SE3_SH1_GDS_REL_OP', + 116: 'GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP', + 117: 'GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP', + 118: 'GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP', + 119: 'GDS_PERF_SEL_GWS_RELEASED', + 120: 'GDS_PERF_SEL_GWS_BYPASS', +} +GDS_PERF_SEL_DS_ADDR_CONFL = 0 +GDS_PERF_SEL_DS_BANK_CONFL = 1 +GDS_PERF_SEL_WBUF_FLUSH = 2 +GDS_PERF_SEL_WR_COMP = 3 +GDS_PERF_SEL_WBUF_WR = 4 +GDS_PERF_SEL_RBUF_HIT = 5 +GDS_PERF_SEL_RBUF_MISS = 6 +GDS_PERF_SEL_SE0_SH0_NORET = 7 +GDS_PERF_SEL_SE0_SH0_RET = 8 +GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9 +GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10 +GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11 +GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12 +GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13 +GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14 +GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15 +GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16 +GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17 +GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18 +GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19 +GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20 +GDS_PERF_SEL_SE0_SH1_NORET = 21 +GDS_PERF_SEL_SE0_SH1_RET = 22 +GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23 +GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24 +GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25 +GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26 +GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27 +GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28 +GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29 +GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30 +GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31 +GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32 +GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33 +GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34 +GDS_PERF_SEL_SE1_SH0_NORET = 35 +GDS_PERF_SEL_SE1_SH0_RET = 36 +GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37 +GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38 +GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39 +GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40 +GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41 +GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42 +GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43 +GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44 +GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45 +GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46 +GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47 +GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48 +GDS_PERF_SEL_SE1_SH1_NORET = 49 +GDS_PERF_SEL_SE1_SH1_RET = 50 +GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51 +GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52 +GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53 +GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54 +GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55 +GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56 +GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57 +GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58 +GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59 +GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60 +GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61 +GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62 +GDS_PERF_SEL_SE2_SH0_NORET = 63 +GDS_PERF_SEL_SE2_SH0_RET = 64 +GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65 +GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66 +GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67 +GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68 +GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69 +GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70 +GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71 +GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72 +GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73 +GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74 +GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75 +GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76 +GDS_PERF_SEL_SE2_SH1_NORET = 77 +GDS_PERF_SEL_SE2_SH1_RET = 78 +GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79 +GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80 +GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81 +GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82 +GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83 +GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84 +GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85 +GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86 +GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87 +GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88 +GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89 +GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90 +GDS_PERF_SEL_SE3_SH0_NORET = 91 +GDS_PERF_SEL_SE3_SH0_RET = 92 +GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93 +GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94 +GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95 +GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96 +GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97 +GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98 +GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99 +GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100 +GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101 +GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102 +GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103 +GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104 +GDS_PERF_SEL_SE3_SH1_NORET = 105 +GDS_PERF_SEL_SE3_SH1_RET = 106 +GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107 +GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108 +GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109 +GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110 +GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111 +GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112 +GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113 +GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114 +GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115 +GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116 +GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117 +GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118 +GDS_PERF_SEL_GWS_RELEASED = 119 +GDS_PERF_SEL_GWS_BYPASS = 120 +GDS_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_FORCE_CTRL' +MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'NO_FORCE_REQUEST', + 1: 'FORCE_LIGHT_SLEEP_REQUEST', + 2: 'FORCE_DEEP_SLEEP_REQUEST', + 3: 'FORCE_SHUT_DOWN_REQUEST', +} +NO_FORCE_REQUEST = 0 +FORCE_LIGHT_SLEEP_REQUEST = 1 +FORCE_DEEP_SLEEP_REQUEST = 2 +FORCE_SHUT_DOWN_REQUEST = 3 +MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_FORCE_CTRL2' +MEM_PWR_FORCE_CTRL2__enumvalues = { + 0: 'NO_FORCE_REQ', + 1: 'FORCE_LIGHT_SLEEP_REQ', +} +NO_FORCE_REQ = 0 +FORCE_LIGHT_SLEEP_REQ = 1 +MEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_DIS_CTRL' +MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'ENABLE_MEM_PWR_CTRL', + 1: 'DISABLE_MEM_PWR_CTRL', +} +ENABLE_MEM_PWR_CTRL = 0 +DISABLE_MEM_PWR_CTRL = 1 +MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_SEL_CTRL' +MEM_PWR_SEL_CTRL__enumvalues = { + 0: 'DYNAMIC_SHUT_DOWN_ENABLE', + 1: 'DYNAMIC_DEEP_SLEEP_ENABLE', + 2: 'DYNAMIC_LIGHT_SLEEP_ENABLE', +} +DYNAMIC_SHUT_DOWN_ENABLE = 0 +DYNAMIC_DEEP_SLEEP_ENABLE = 1 +DYNAMIC_LIGHT_SLEEP_ENABLE = 2 +MEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_SEL_CTRL2' +MEM_PWR_SEL_CTRL2__enumvalues = { + 0: 'DYNAMIC_DEEP_SLEEP_EN', + 1: 'DYNAMIC_LIGHT_SLEEP_EN', +} +DYNAMIC_DEEP_SLEEP_EN = 0 +DYNAMIC_LIGHT_SLEEP_EN = 1 +MEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'RowSize' +RowSize__enumvalues = { + 0: 'ADDR_CONFIG_1KB_ROW', + 1: 'ADDR_CONFIG_2KB_ROW', + 2: 'ADDR_CONFIG_4KB_ROW', +} +ADDR_CONFIG_1KB_ROW = 0 +ADDR_CONFIG_2KB_ROW = 1 +ADDR_CONFIG_4KB_ROW = 2 +RowSize = ctypes.c_uint32 # enum + +# values for enumeration 'SurfaceEndian' +SurfaceEndian__enumvalues = { + 0: 'ENDIAN_NONE', + 1: 'ENDIAN_8IN16', + 2: 'ENDIAN_8IN32', + 3: 'ENDIAN_8IN64', +} +ENDIAN_NONE = 0 +ENDIAN_8IN16 = 1 +ENDIAN_8IN32 = 2 +ENDIAN_8IN64 = 3 +SurfaceEndian = ctypes.c_uint32 # enum + +# values for enumeration 'ArrayMode' +ArrayMode__enumvalues = { + 0: 'ARRAY_LINEAR_GENERAL', + 1: 'ARRAY_LINEAR_ALIGNED', + 2: 'ARRAY_1D_TILED_THIN1', + 3: 'ARRAY_1D_TILED_THICK', + 4: 'ARRAY_2D_TILED_THIN1', + 5: 'ARRAY_PRT_TILED_THIN1', + 6: 'ARRAY_PRT_2D_TILED_THIN1', + 7: 'ARRAY_2D_TILED_THICK', + 8: 'ARRAY_2D_TILED_XTHICK', + 9: 'ARRAY_PRT_TILED_THICK', + 10: 'ARRAY_PRT_2D_TILED_THICK', + 11: 'ARRAY_PRT_3D_TILED_THIN1', + 12: 'ARRAY_3D_TILED_THIN1', + 13: 'ARRAY_3D_TILED_THICK', + 14: 'ARRAY_3D_TILED_XTHICK', + 15: 'ARRAY_PRT_3D_TILED_THICK', +} +ARRAY_LINEAR_GENERAL = 0 +ARRAY_LINEAR_ALIGNED = 1 +ARRAY_1D_TILED_THIN1 = 2 +ARRAY_1D_TILED_THICK = 3 +ARRAY_2D_TILED_THIN1 = 4 +ARRAY_PRT_TILED_THIN1 = 5 +ARRAY_PRT_2D_TILED_THIN1 = 6 +ARRAY_2D_TILED_THICK = 7 +ARRAY_2D_TILED_XTHICK = 8 +ARRAY_PRT_TILED_THICK = 9 +ARRAY_PRT_2D_TILED_THICK = 10 +ARRAY_PRT_3D_TILED_THIN1 = 11 +ARRAY_3D_TILED_THIN1 = 12 +ARRAY_3D_TILED_THICK = 13 +ARRAY_3D_TILED_XTHICK = 14 +ARRAY_PRT_3D_TILED_THICK = 15 +ArrayMode = ctypes.c_uint32 # enum + +# values for enumeration 'NumPipes' +NumPipes__enumvalues = { + 0: 'ADDR_CONFIG_1_PIPE', + 1: 'ADDR_CONFIG_2_PIPE', + 2: 'ADDR_CONFIG_4_PIPE', + 3: 'ADDR_CONFIG_8_PIPE', + 4: 'ADDR_CONFIG_16_PIPE', + 5: 'ADDR_CONFIG_32_PIPE', +} +ADDR_CONFIG_1_PIPE = 0 +ADDR_CONFIG_2_PIPE = 1 +ADDR_CONFIG_4_PIPE = 2 +ADDR_CONFIG_8_PIPE = 3 +ADDR_CONFIG_16_PIPE = 4 +ADDR_CONFIG_32_PIPE = 5 +NumPipes = ctypes.c_uint32 # enum + +# values for enumeration 'NumBanksConfig' +NumBanksConfig__enumvalues = { + 0: 'ADDR_CONFIG_1_BANK', + 1: 'ADDR_CONFIG_2_BANK', + 2: 'ADDR_CONFIG_4_BANK', + 3: 'ADDR_CONFIG_8_BANK', + 4: 'ADDR_CONFIG_16_BANK', +} +ADDR_CONFIG_1_BANK = 0 +ADDR_CONFIG_2_BANK = 1 +ADDR_CONFIG_4_BANK = 2 +ADDR_CONFIG_8_BANK = 3 +ADDR_CONFIG_16_BANK = 4 +NumBanksConfig = ctypes.c_uint32 # enum + +# values for enumeration 'PipeInterleaveSize' +PipeInterleaveSize__enumvalues = { + 0: 'ADDR_CONFIG_PIPE_INTERLEAVE_256B', + 1: 'ADDR_CONFIG_PIPE_INTERLEAVE_512B', + 2: 'ADDR_CONFIG_PIPE_INTERLEAVE_1KB', + 3: 'ADDR_CONFIG_PIPE_INTERLEAVE_2KB', +} +ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0 +ADDR_CONFIG_PIPE_INTERLEAVE_512B = 1 +ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 2 +ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 3 +PipeInterleaveSize = ctypes.c_uint32 # enum + +# values for enumeration 'BankInterleaveSize' +BankInterleaveSize__enumvalues = { + 0: 'ADDR_CONFIG_BANK_INTERLEAVE_1', + 1: 'ADDR_CONFIG_BANK_INTERLEAVE_2', + 2: 'ADDR_CONFIG_BANK_INTERLEAVE_4', + 3: 'ADDR_CONFIG_BANK_INTERLEAVE_8', +} +ADDR_CONFIG_BANK_INTERLEAVE_1 = 0 +ADDR_CONFIG_BANK_INTERLEAVE_2 = 1 +ADDR_CONFIG_BANK_INTERLEAVE_4 = 2 +ADDR_CONFIG_BANK_INTERLEAVE_8 = 3 +BankInterleaveSize = ctypes.c_uint32 # enum + +# values for enumeration 'NumShaderEngines' +NumShaderEngines__enumvalues = { + 0: 'ADDR_CONFIG_1_SHADER_ENGINE', + 1: 'ADDR_CONFIG_2_SHADER_ENGINE', + 2: 'ADDR_CONFIG_4_SHADER_ENGINE', + 3: 'ADDR_CONFIG_8_SHADER_ENGINE', +} +ADDR_CONFIG_1_SHADER_ENGINE = 0 +ADDR_CONFIG_2_SHADER_ENGINE = 1 +ADDR_CONFIG_4_SHADER_ENGINE = 2 +ADDR_CONFIG_8_SHADER_ENGINE = 3 +NumShaderEngines = ctypes.c_uint32 # enum + +# values for enumeration 'NumRbPerShaderEngine' +NumRbPerShaderEngine__enumvalues = { + 0: 'ADDR_CONFIG_1_RB_PER_SHADER_ENGINE', + 1: 'ADDR_CONFIG_2_RB_PER_SHADER_ENGINE', + 2: 'ADDR_CONFIG_4_RB_PER_SHADER_ENGINE', +} +ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0 +ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 1 +ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 2 +NumRbPerShaderEngine = ctypes.c_uint32 # enum + +# values for enumeration 'NumGPUs' +NumGPUs__enumvalues = { + 0: 'ADDR_CONFIG_1_GPU', + 1: 'ADDR_CONFIG_2_GPU', + 2: 'ADDR_CONFIG_4_GPU', + 3: 'ADDR_CONFIG_8_GPU', +} +ADDR_CONFIG_1_GPU = 0 +ADDR_CONFIG_2_GPU = 1 +ADDR_CONFIG_4_GPU = 2 +ADDR_CONFIG_8_GPU = 3 +NumGPUs = ctypes.c_uint32 # enum + +# values for enumeration 'NumMaxCompressedFragments' +NumMaxCompressedFragments__enumvalues = { + 0: 'ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS', + 1: 'ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS', + 2: 'ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS', + 3: 'ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS', +} +ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0 +ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 1 +ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 2 +ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 3 +NumMaxCompressedFragments = ctypes.c_uint32 # enum + +# values for enumeration 'ShaderEngineTileSize' +ShaderEngineTileSize__enumvalues = { + 0: 'ADDR_CONFIG_SE_TILE_16', + 1: 'ADDR_CONFIG_SE_TILE_32', +} +ADDR_CONFIG_SE_TILE_16 = 0 +ADDR_CONFIG_SE_TILE_32 = 1 +ShaderEngineTileSize = ctypes.c_uint32 # enum + +# values for enumeration 'MultiGPUTileSize' +MultiGPUTileSize__enumvalues = { + 0: 'ADDR_CONFIG_GPU_TILE_16', + 1: 'ADDR_CONFIG_GPU_TILE_32', + 2: 'ADDR_CONFIG_GPU_TILE_64', + 3: 'ADDR_CONFIG_GPU_TILE_128', +} +ADDR_CONFIG_GPU_TILE_16 = 0 +ADDR_CONFIG_GPU_TILE_32 = 1 +ADDR_CONFIG_GPU_TILE_64 = 2 +ADDR_CONFIG_GPU_TILE_128 = 3 +MultiGPUTileSize = ctypes.c_uint32 # enum + +# values for enumeration 'NumLowerPipes' +NumLowerPipes__enumvalues = { + 0: 'ADDR_CONFIG_1_LOWER_PIPES', + 1: 'ADDR_CONFIG_2_LOWER_PIPES', +} +ADDR_CONFIG_1_LOWER_PIPES = 0 +ADDR_CONFIG_2_LOWER_PIPES = 1 +NumLowerPipes = ctypes.c_uint32 # enum + +# values for enumeration 'ColorTransform' +ColorTransform__enumvalues = { + 0: 'DCC_CT_AUTO', + 1: 'DCC_CT_NONE', + 2: 'ABGR_TO_A_BG_G_RB', + 3: 'BGRA_TO_BG_G_RB_A', +} +DCC_CT_AUTO = 0 +DCC_CT_NONE = 1 +ABGR_TO_A_BG_G_RB = 2 +BGRA_TO_BG_G_RB_A = 3 +ColorTransform = ctypes.c_uint32 # enum + +# values for enumeration 'CompareRef' +CompareRef__enumvalues = { + 0: 'REF_NEVER', + 1: 'REF_LESS', + 2: 'REF_EQUAL', + 3: 'REF_LEQUAL', + 4: 'REF_GREATER', + 5: 'REF_NOTEQUAL', + 6: 'REF_GEQUAL', + 7: 'REF_ALWAYS', +} +REF_NEVER = 0 +REF_LESS = 1 +REF_EQUAL = 2 +REF_LEQUAL = 3 +REF_GREATER = 4 +REF_NOTEQUAL = 5 +REF_GEQUAL = 6 +REF_ALWAYS = 7 +CompareRef = ctypes.c_uint32 # enum + +# values for enumeration 'ReadSize' +ReadSize__enumvalues = { + 0: 'READ_256_BITS', + 1: 'READ_512_BITS', +} +READ_256_BITS = 0 +READ_512_BITS = 1 +ReadSize = ctypes.c_uint32 # enum + +# values for enumeration 'DepthFormat' +DepthFormat__enumvalues = { + 0: 'DEPTH_INVALID', + 1: 'DEPTH_16', + 2: 'DEPTH_X8_24', + 3: 'DEPTH_8_24', + 4: 'DEPTH_X8_24_FLOAT', + 5: 'DEPTH_8_24_FLOAT', + 6: 'DEPTH_32_FLOAT', + 7: 'DEPTH_X24_8_32_FLOAT', +} +DEPTH_INVALID = 0 +DEPTH_16 = 1 +DEPTH_X8_24 = 2 +DEPTH_8_24 = 3 +DEPTH_X8_24_FLOAT = 4 +DEPTH_8_24_FLOAT = 5 +DEPTH_32_FLOAT = 6 +DEPTH_X24_8_32_FLOAT = 7 +DepthFormat = ctypes.c_uint32 # enum + +# values for enumeration 'ZFormat' +ZFormat__enumvalues = { + 0: 'Z_INVALID', + 1: 'Z_16', + 2: 'Z_24', + 3: 'Z_32_FLOAT', +} +Z_INVALID = 0 +Z_16 = 1 +Z_24 = 2 +Z_32_FLOAT = 3 +ZFormat = ctypes.c_uint32 # enum + +# values for enumeration 'StencilFormat' +StencilFormat__enumvalues = { + 0: 'STENCIL_INVALID', + 1: 'STENCIL_8', +} +STENCIL_INVALID = 0 +STENCIL_8 = 1 +StencilFormat = ctypes.c_uint32 # enum + +# values for enumeration 'CmaskMode' +CmaskMode__enumvalues = { + 0: 'CMASK_CLEAR_NONE', + 1: 'CMASK_CLEAR_ONE', + 2: 'CMASK_CLEAR_ALL', + 3: 'CMASK_ANY_EXPANDED', + 4: 'CMASK_ALPHA0_FRAG1', + 5: 'CMASK_ALPHA0_FRAG2', + 6: 'CMASK_ALPHA0_FRAG4', + 7: 'CMASK_ALPHA0_FRAGS', + 8: 'CMASK_ALPHA1_FRAG1', + 9: 'CMASK_ALPHA1_FRAG2', + 10: 'CMASK_ALPHA1_FRAG4', + 11: 'CMASK_ALPHA1_FRAGS', + 12: 'CMASK_ALPHAX_FRAG1', + 13: 'CMASK_ALPHAX_FRAG2', + 14: 'CMASK_ALPHAX_FRAG4', + 15: 'CMASK_ALPHAX_FRAGS', +} +CMASK_CLEAR_NONE = 0 +CMASK_CLEAR_ONE = 1 +CMASK_CLEAR_ALL = 2 +CMASK_ANY_EXPANDED = 3 +CMASK_ALPHA0_FRAG1 = 4 +CMASK_ALPHA0_FRAG2 = 5 +CMASK_ALPHA0_FRAG4 = 6 +CMASK_ALPHA0_FRAGS = 7 +CMASK_ALPHA1_FRAG1 = 8 +CMASK_ALPHA1_FRAG2 = 9 +CMASK_ALPHA1_FRAG4 = 10 +CMASK_ALPHA1_FRAGS = 11 +CMASK_ALPHAX_FRAG1 = 12 +CMASK_ALPHAX_FRAG2 = 13 +CMASK_ALPHAX_FRAG4 = 14 +CMASK_ALPHAX_FRAGS = 15 +CmaskMode = ctypes.c_uint32 # enum + +# values for enumeration 'QuadExportFormat' +QuadExportFormat__enumvalues = { + 0: 'EXPORT_UNUSED', + 1: 'EXPORT_32_R', + 2: 'EXPORT_32_GR', + 3: 'EXPORT_32_AR', + 4: 'EXPORT_FP16_ABGR', + 5: 'EXPORT_UNSIGNED16_ABGR', + 6: 'EXPORT_SIGNED16_ABGR', + 7: 'EXPORT_32_ABGR', + 8: 'EXPORT_32BPP_8PIX', + 9: 'EXPORT_16_16_UNSIGNED_8PIX', + 10: 'EXPORT_16_16_SIGNED_8PIX', + 11: 'EXPORT_16_16_FLOAT_8PIX', +} +EXPORT_UNUSED = 0 +EXPORT_32_R = 1 +EXPORT_32_GR = 2 +EXPORT_32_AR = 3 +EXPORT_FP16_ABGR = 4 +EXPORT_UNSIGNED16_ABGR = 5 +EXPORT_SIGNED16_ABGR = 6 +EXPORT_32_ABGR = 7 +EXPORT_32BPP_8PIX = 8 +EXPORT_16_16_UNSIGNED_8PIX = 9 +EXPORT_16_16_SIGNED_8PIX = 10 +EXPORT_16_16_FLOAT_8PIX = 11 +QuadExportFormat = ctypes.c_uint32 # enum + +# values for enumeration 'QuadExportFormatOld' +QuadExportFormatOld__enumvalues = { + 0: 'EXPORT_4P_32BPC_ABGR', + 1: 'EXPORT_4P_16BPC_ABGR', + 2: 'EXPORT_4P_32BPC_GR', + 3: 'EXPORT_4P_32BPC_AR', + 4: 'EXPORT_2P_32BPC_ABGR', + 5: 'EXPORT_8P_32BPC_R', +} +EXPORT_4P_32BPC_ABGR = 0 +EXPORT_4P_16BPC_ABGR = 1 +EXPORT_4P_32BPC_GR = 2 +EXPORT_4P_32BPC_AR = 3 +EXPORT_2P_32BPC_ABGR = 4 +EXPORT_8P_32BPC_R = 5 +QuadExportFormatOld = ctypes.c_uint32 # enum + +# values for enumeration 'ColorFormat' +ColorFormat__enumvalues = { + 0: 'COLOR_INVALID', + 1: 'COLOR_8', + 2: 'COLOR_16', + 3: 'COLOR_8_8', + 4: 'COLOR_32', + 5: 'COLOR_16_16', + 6: 'COLOR_10_11_11', + 7: 'COLOR_11_11_10', + 8: 'COLOR_10_10_10_2', + 9: 'COLOR_2_10_10_10', + 10: 'COLOR_8_8_8_8', + 11: 'COLOR_32_32', + 12: 'COLOR_16_16_16_16', + 13: 'COLOR_RESERVED_13', + 14: 'COLOR_32_32_32_32', + 15: 'COLOR_RESERVED_15', + 16: 'COLOR_5_6_5', + 17: 'COLOR_1_5_5_5', + 18: 'COLOR_5_5_5_1', + 19: 'COLOR_4_4_4_4', + 20: 'COLOR_8_24', + 21: 'COLOR_24_8', + 22: 'COLOR_X24_8_32_FLOAT', + 23: 'COLOR_RESERVED_23', + 24: 'COLOR_RESERVED_24', + 25: 'COLOR_RESERVED_25', + 26: 'COLOR_RESERVED_26', + 27: 'COLOR_RESERVED_27', + 28: 'COLOR_RESERVED_28', + 29: 'COLOR_RESERVED_29', + 30: 'COLOR_RESERVED_30', + 31: 'COLOR_2_10_10_10_6E4', +} +COLOR_INVALID = 0 +COLOR_8 = 1 +COLOR_16 = 2 +COLOR_8_8 = 3 +COLOR_32 = 4 +COLOR_16_16 = 5 +COLOR_10_11_11 = 6 +COLOR_11_11_10 = 7 +COLOR_10_10_10_2 = 8 +COLOR_2_10_10_10 = 9 +COLOR_8_8_8_8 = 10 +COLOR_32_32 = 11 +COLOR_16_16_16_16 = 12 +COLOR_RESERVED_13 = 13 +COLOR_32_32_32_32 = 14 +COLOR_RESERVED_15 = 15 +COLOR_5_6_5 = 16 +COLOR_1_5_5_5 = 17 +COLOR_5_5_5_1 = 18 +COLOR_4_4_4_4 = 19 +COLOR_8_24 = 20 +COLOR_24_8 = 21 +COLOR_X24_8_32_FLOAT = 22 +COLOR_RESERVED_23 = 23 +COLOR_RESERVED_24 = 24 +COLOR_RESERVED_25 = 25 +COLOR_RESERVED_26 = 26 +COLOR_RESERVED_27 = 27 +COLOR_RESERVED_28 = 28 +COLOR_RESERVED_29 = 29 +COLOR_RESERVED_30 = 30 +COLOR_2_10_10_10_6E4 = 31 +ColorFormat = ctypes.c_uint32 # enum + +# values for enumeration 'SurfaceFormat' +SurfaceFormat__enumvalues = { + 0: 'FMT_INVALID', + 1: 'FMT_8', + 2: 'FMT_16', + 3: 'FMT_8_8', + 4: 'FMT_32', + 5: 'FMT_16_16', + 6: 'FMT_10_11_11', + 7: 'FMT_11_11_10', + 8: 'FMT_10_10_10_2', + 9: 'FMT_2_10_10_10', + 10: 'FMT_8_8_8_8', + 11: 'FMT_32_32', + 12: 'FMT_16_16_16_16', + 13: 'FMT_32_32_32', + 14: 'FMT_32_32_32_32', + 15: 'FMT_RESERVED_4', + 16: 'FMT_5_6_5', + 17: 'FMT_1_5_5_5', + 18: 'FMT_5_5_5_1', + 19: 'FMT_4_4_4_4', + 20: 'FMT_8_24', + 21: 'FMT_24_8', + 22: 'FMT_X24_8_32_FLOAT', + 23: 'FMT_RESERVED_33', + 24: 'FMT_11_11_10_FLOAT', + 25: 'FMT_16_FLOAT', + 26: 'FMT_32_FLOAT', + 27: 'FMT_16_16_FLOAT', + 28: 'FMT_8_24_FLOAT', + 29: 'FMT_24_8_FLOAT', + 30: 'FMT_32_32_FLOAT', + 31: 'FMT_10_11_11_FLOAT', + 32: 'FMT_16_16_16_16_FLOAT', + 33: 'FMT_3_3_2', + 34: 'FMT_6_5_5', + 35: 'FMT_32_32_32_32_FLOAT', + 36: 'FMT_RESERVED_36', + 37: 'FMT_1', + 38: 'FMT_1_REVERSED', + 39: 'FMT_GB_GR', + 40: 'FMT_BG_RG', + 41: 'FMT_32_AS_8', + 42: 'FMT_32_AS_8_8', + 43: 'FMT_5_9_9_9_SHAREDEXP', + 44: 'FMT_8_8_8', + 45: 'FMT_16_16_16', + 46: 'FMT_16_16_16_FLOAT', + 47: 'FMT_4_4', + 48: 'FMT_32_32_32_FLOAT', + 49: 'FMT_BC1', + 50: 'FMT_BC2', + 51: 'FMT_BC3', + 52: 'FMT_BC4', + 53: 'FMT_BC5', + 54: 'FMT_BC6', + 55: 'FMT_BC7', + 56: 'FMT_32_AS_32_32_32_32', + 57: 'FMT_APC3', + 58: 'FMT_APC4', + 59: 'FMT_APC5', + 60: 'FMT_APC6', + 61: 'FMT_APC7', + 62: 'FMT_CTX1', + 63: 'FMT_RESERVED_63', +} +FMT_INVALID = 0 +FMT_8 = 1 +FMT_16 = 2 +FMT_8_8 = 3 +FMT_32 = 4 +FMT_16_16 = 5 +FMT_10_11_11 = 6 +FMT_11_11_10 = 7 +FMT_10_10_10_2 = 8 +FMT_2_10_10_10 = 9 +FMT_8_8_8_8 = 10 +FMT_32_32 = 11 +FMT_16_16_16_16 = 12 +FMT_32_32_32 = 13 +FMT_32_32_32_32 = 14 +FMT_RESERVED_4 = 15 +FMT_5_6_5 = 16 +FMT_1_5_5_5 = 17 +FMT_5_5_5_1 = 18 +FMT_4_4_4_4 = 19 +FMT_8_24 = 20 +FMT_24_8 = 21 +FMT_X24_8_32_FLOAT = 22 +FMT_RESERVED_33 = 23 +FMT_11_11_10_FLOAT = 24 +FMT_16_FLOAT = 25 +FMT_32_FLOAT = 26 +FMT_16_16_FLOAT = 27 +FMT_8_24_FLOAT = 28 +FMT_24_8_FLOAT = 29 +FMT_32_32_FLOAT = 30 +FMT_10_11_11_FLOAT = 31 +FMT_16_16_16_16_FLOAT = 32 +FMT_3_3_2 = 33 +FMT_6_5_5 = 34 +FMT_32_32_32_32_FLOAT = 35 +FMT_RESERVED_36 = 36 +FMT_1 = 37 +FMT_1_REVERSED = 38 +FMT_GB_GR = 39 +FMT_BG_RG = 40 +FMT_32_AS_8 = 41 +FMT_32_AS_8_8 = 42 +FMT_5_9_9_9_SHAREDEXP = 43 +FMT_8_8_8 = 44 +FMT_16_16_16 = 45 +FMT_16_16_16_FLOAT = 46 +FMT_4_4 = 47 +FMT_32_32_32_FLOAT = 48 +FMT_BC1 = 49 +FMT_BC2 = 50 +FMT_BC3 = 51 +FMT_BC4 = 52 +FMT_BC5 = 53 +FMT_BC6 = 54 +FMT_BC7 = 55 +FMT_32_AS_32_32_32_32 = 56 +FMT_APC3 = 57 +FMT_APC4 = 58 +FMT_APC5 = 59 +FMT_APC6 = 60 +FMT_APC7 = 61 +FMT_CTX1 = 62 +FMT_RESERVED_63 = 63 +SurfaceFormat = ctypes.c_uint32 # enum + +# values for enumeration 'BUF_DATA_FORMAT' +BUF_DATA_FORMAT__enumvalues = { + 0: 'BUF_DATA_FORMAT_INVALID', + 1: 'BUF_DATA_FORMAT_8', + 2: 'BUF_DATA_FORMAT_16', + 3: 'BUF_DATA_FORMAT_8_8', + 4: 'BUF_DATA_FORMAT_32', + 5: 'BUF_DATA_FORMAT_16_16', + 6: 'BUF_DATA_FORMAT_10_11_11', + 7: 'BUF_DATA_FORMAT_11_11_10', + 8: 'BUF_DATA_FORMAT_10_10_10_2', + 9: 'BUF_DATA_FORMAT_2_10_10_10', + 10: 'BUF_DATA_FORMAT_8_8_8_8', + 11: 'BUF_DATA_FORMAT_32_32', + 12: 'BUF_DATA_FORMAT_16_16_16_16', + 13: 'BUF_DATA_FORMAT_32_32_32', + 14: 'BUF_DATA_FORMAT_32_32_32_32', + 15: 'BUF_DATA_FORMAT_RESERVED_15', +} +BUF_DATA_FORMAT_INVALID = 0 +BUF_DATA_FORMAT_8 = 1 +BUF_DATA_FORMAT_16 = 2 +BUF_DATA_FORMAT_8_8 = 3 +BUF_DATA_FORMAT_32 = 4 +BUF_DATA_FORMAT_16_16 = 5 +BUF_DATA_FORMAT_10_11_11 = 6 +BUF_DATA_FORMAT_11_11_10 = 7 +BUF_DATA_FORMAT_10_10_10_2 = 8 +BUF_DATA_FORMAT_2_10_10_10 = 9 +BUF_DATA_FORMAT_8_8_8_8 = 10 +BUF_DATA_FORMAT_32_32 = 11 +BUF_DATA_FORMAT_16_16_16_16 = 12 +BUF_DATA_FORMAT_32_32_32 = 13 +BUF_DATA_FORMAT_32_32_32_32 = 14 +BUF_DATA_FORMAT_RESERVED_15 = 15 +BUF_DATA_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'IMG_DATA_FORMAT' +IMG_DATA_FORMAT__enumvalues = { + 0: 'IMG_DATA_FORMAT_INVALID', + 1: 'IMG_DATA_FORMAT_8', + 2: 'IMG_DATA_FORMAT_16', + 3: 'IMG_DATA_FORMAT_8_8', + 4: 'IMG_DATA_FORMAT_32', + 5: 'IMG_DATA_FORMAT_16_16', + 6: 'IMG_DATA_FORMAT_10_11_11', + 7: 'IMG_DATA_FORMAT_11_11_10', + 8: 'IMG_DATA_FORMAT_10_10_10_2', + 9: 'IMG_DATA_FORMAT_2_10_10_10', + 10: 'IMG_DATA_FORMAT_8_8_8_8', + 11: 'IMG_DATA_FORMAT_32_32', + 12: 'IMG_DATA_FORMAT_16_16_16_16', + 13: 'IMG_DATA_FORMAT_32_32_32', + 14: 'IMG_DATA_FORMAT_32_32_32_32', + 15: 'IMG_DATA_FORMAT_RESERVED_15', + 16: 'IMG_DATA_FORMAT_5_6_5', + 17: 'IMG_DATA_FORMAT_1_5_5_5', + 18: 'IMG_DATA_FORMAT_5_5_5_1', + 19: 'IMG_DATA_FORMAT_4_4_4_4', + 20: 'IMG_DATA_FORMAT_8_24', + 21: 'IMG_DATA_FORMAT_24_8', + 22: 'IMG_DATA_FORMAT_X24_8_32', + 23: 'IMG_DATA_FORMAT_8_AS_8_8_8_8', + 24: 'IMG_DATA_FORMAT_ETC2_RGB', + 25: 'IMG_DATA_FORMAT_ETC2_RGBA', + 26: 'IMG_DATA_FORMAT_ETC2_R', + 27: 'IMG_DATA_FORMAT_ETC2_RG', + 28: 'IMG_DATA_FORMAT_ETC2_RGBA1', + 29: 'IMG_DATA_FORMAT_RESERVED_29', + 30: 'IMG_DATA_FORMAT_RESERVED_30', + 31: 'IMG_DATA_FORMAT_6E4', + 32: 'IMG_DATA_FORMAT_GB_GR', + 33: 'IMG_DATA_FORMAT_BG_RG', + 34: 'IMG_DATA_FORMAT_5_9_9_9', + 35: 'IMG_DATA_FORMAT_BC1', + 36: 'IMG_DATA_FORMAT_BC2', + 37: 'IMG_DATA_FORMAT_BC3', + 38: 'IMG_DATA_FORMAT_BC4', + 39: 'IMG_DATA_FORMAT_BC5', + 40: 'IMG_DATA_FORMAT_BC6', + 41: 'IMG_DATA_FORMAT_BC7', + 42: 'IMG_DATA_FORMAT_16_AS_32_32', + 43: 'IMG_DATA_FORMAT_16_AS_16_16_16_16', + 44: 'IMG_DATA_FORMAT_16_AS_32_32_32_32', + 45: 'IMG_DATA_FORMAT_FMASK', + 46: 'IMG_DATA_FORMAT_ASTC_2D_LDR', + 47: 'IMG_DATA_FORMAT_ASTC_2D_HDR', + 48: 'IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB', + 49: 'IMG_DATA_FORMAT_ASTC_3D_LDR', + 50: 'IMG_DATA_FORMAT_ASTC_3D_HDR', + 51: 'IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB', + 52: 'IMG_DATA_FORMAT_N_IN_16', + 53: 'IMG_DATA_FORMAT_N_IN_16_16', + 54: 'IMG_DATA_FORMAT_N_IN_16_16_16_16', + 55: 'IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16', + 56: 'IMG_DATA_FORMAT_RESERVED_56', + 57: 'IMG_DATA_FORMAT_4_4', + 58: 'IMG_DATA_FORMAT_6_5_5', + 59: 'IMG_DATA_FORMAT_RESERVED_59', + 60: 'IMG_DATA_FORMAT_RESERVED_60', + 61: 'IMG_DATA_FORMAT_8_AS_32', + 62: 'IMG_DATA_FORMAT_8_AS_32_32', + 63: 'IMG_DATA_FORMAT_32_AS_32_32_32_32', +} +IMG_DATA_FORMAT_INVALID = 0 +IMG_DATA_FORMAT_8 = 1 +IMG_DATA_FORMAT_16 = 2 +IMG_DATA_FORMAT_8_8 = 3 +IMG_DATA_FORMAT_32 = 4 +IMG_DATA_FORMAT_16_16 = 5 +IMG_DATA_FORMAT_10_11_11 = 6 +IMG_DATA_FORMAT_11_11_10 = 7 +IMG_DATA_FORMAT_10_10_10_2 = 8 +IMG_DATA_FORMAT_2_10_10_10 = 9 +IMG_DATA_FORMAT_8_8_8_8 = 10 +IMG_DATA_FORMAT_32_32 = 11 +IMG_DATA_FORMAT_16_16_16_16 = 12 +IMG_DATA_FORMAT_32_32_32 = 13 +IMG_DATA_FORMAT_32_32_32_32 = 14 +IMG_DATA_FORMAT_RESERVED_15 = 15 +IMG_DATA_FORMAT_5_6_5 = 16 +IMG_DATA_FORMAT_1_5_5_5 = 17 +IMG_DATA_FORMAT_5_5_5_1 = 18 +IMG_DATA_FORMAT_4_4_4_4 = 19 +IMG_DATA_FORMAT_8_24 = 20 +IMG_DATA_FORMAT_24_8 = 21 +IMG_DATA_FORMAT_X24_8_32 = 22 +IMG_DATA_FORMAT_8_AS_8_8_8_8 = 23 +IMG_DATA_FORMAT_ETC2_RGB = 24 +IMG_DATA_FORMAT_ETC2_RGBA = 25 +IMG_DATA_FORMAT_ETC2_R = 26 +IMG_DATA_FORMAT_ETC2_RG = 27 +IMG_DATA_FORMAT_ETC2_RGBA1 = 28 +IMG_DATA_FORMAT_RESERVED_29 = 29 +IMG_DATA_FORMAT_RESERVED_30 = 30 +IMG_DATA_FORMAT_6E4 = 31 +IMG_DATA_FORMAT_GB_GR = 32 +IMG_DATA_FORMAT_BG_RG = 33 +IMG_DATA_FORMAT_5_9_9_9 = 34 +IMG_DATA_FORMAT_BC1 = 35 +IMG_DATA_FORMAT_BC2 = 36 +IMG_DATA_FORMAT_BC3 = 37 +IMG_DATA_FORMAT_BC4 = 38 +IMG_DATA_FORMAT_BC5 = 39 +IMG_DATA_FORMAT_BC6 = 40 +IMG_DATA_FORMAT_BC7 = 41 +IMG_DATA_FORMAT_16_AS_32_32 = 42 +IMG_DATA_FORMAT_16_AS_16_16_16_16 = 43 +IMG_DATA_FORMAT_16_AS_32_32_32_32 = 44 +IMG_DATA_FORMAT_FMASK = 45 +IMG_DATA_FORMAT_ASTC_2D_LDR = 46 +IMG_DATA_FORMAT_ASTC_2D_HDR = 47 +IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB = 48 +IMG_DATA_FORMAT_ASTC_3D_LDR = 49 +IMG_DATA_FORMAT_ASTC_3D_HDR = 50 +IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB = 51 +IMG_DATA_FORMAT_N_IN_16 = 52 +IMG_DATA_FORMAT_N_IN_16_16 = 53 +IMG_DATA_FORMAT_N_IN_16_16_16_16 = 54 +IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16 = 55 +IMG_DATA_FORMAT_RESERVED_56 = 56 +IMG_DATA_FORMAT_4_4 = 57 +IMG_DATA_FORMAT_6_5_5 = 58 +IMG_DATA_FORMAT_RESERVED_59 = 59 +IMG_DATA_FORMAT_RESERVED_60 = 60 +IMG_DATA_FORMAT_8_AS_32 = 61 +IMG_DATA_FORMAT_8_AS_32_32 = 62 +IMG_DATA_FORMAT_32_AS_32_32_32_32 = 63 +IMG_DATA_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'BUF_NUM_FORMAT' +BUF_NUM_FORMAT__enumvalues = { + 0: 'BUF_NUM_FORMAT_UNORM', + 1: 'BUF_NUM_FORMAT_SNORM', + 2: 'BUF_NUM_FORMAT_USCALED', + 3: 'BUF_NUM_FORMAT_SSCALED', + 4: 'BUF_NUM_FORMAT_UINT', + 5: 'BUF_NUM_FORMAT_SINT', + 6: 'BUF_NUM_FORMAT_UNORM_UINT', + 7: 'BUF_NUM_FORMAT_FLOAT', +} +BUF_NUM_FORMAT_UNORM = 0 +BUF_NUM_FORMAT_SNORM = 1 +BUF_NUM_FORMAT_USCALED = 2 +BUF_NUM_FORMAT_SSCALED = 3 +BUF_NUM_FORMAT_UINT = 4 +BUF_NUM_FORMAT_SINT = 5 +BUF_NUM_FORMAT_UNORM_UINT = 6 +BUF_NUM_FORMAT_FLOAT = 7 +BUF_NUM_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'IMG_NUM_FORMAT' +IMG_NUM_FORMAT__enumvalues = { + 0: 'IMG_NUM_FORMAT_UNORM', + 1: 'IMG_NUM_FORMAT_SNORM', + 2: 'IMG_NUM_FORMAT_USCALED', + 3: 'IMG_NUM_FORMAT_SSCALED', + 4: 'IMG_NUM_FORMAT_UINT', + 5: 'IMG_NUM_FORMAT_SINT', + 6: 'IMG_NUM_FORMAT_UNORM_UINT', + 7: 'IMG_NUM_FORMAT_FLOAT', + 8: 'IMG_NUM_FORMAT_RESERVED_8', + 9: 'IMG_NUM_FORMAT_SRGB', + 10: 'IMG_NUM_FORMAT_RESERVED_10', + 11: 'IMG_NUM_FORMAT_RESERVED_11', + 12: 'IMG_NUM_FORMAT_RESERVED_12', + 13: 'IMG_NUM_FORMAT_RESERVED_13', + 14: 'IMG_NUM_FORMAT_RESERVED_14', + 15: 'IMG_NUM_FORMAT_RESERVED_15', +} +IMG_NUM_FORMAT_UNORM = 0 +IMG_NUM_FORMAT_SNORM = 1 +IMG_NUM_FORMAT_USCALED = 2 +IMG_NUM_FORMAT_SSCALED = 3 +IMG_NUM_FORMAT_UINT = 4 +IMG_NUM_FORMAT_SINT = 5 +IMG_NUM_FORMAT_UNORM_UINT = 6 +IMG_NUM_FORMAT_FLOAT = 7 +IMG_NUM_FORMAT_RESERVED_8 = 8 +IMG_NUM_FORMAT_SRGB = 9 +IMG_NUM_FORMAT_RESERVED_10 = 10 +IMG_NUM_FORMAT_RESERVED_11 = 11 +IMG_NUM_FORMAT_RESERVED_12 = 12 +IMG_NUM_FORMAT_RESERVED_13 = 13 +IMG_NUM_FORMAT_RESERVED_14 = 14 +IMG_NUM_FORMAT_RESERVED_15 = 15 +IMG_NUM_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'IMG_NUM_FORMAT_FMASK' +IMG_NUM_FORMAT_FMASK__enumvalues = { + 0: 'IMG_NUM_FORMAT_FMASK_8_2_1', + 1: 'IMG_NUM_FORMAT_FMASK_8_4_1', + 2: 'IMG_NUM_FORMAT_FMASK_8_8_1', + 3: 'IMG_NUM_FORMAT_FMASK_8_2_2', + 4: 'IMG_NUM_FORMAT_FMASK_8_4_2', + 5: 'IMG_NUM_FORMAT_FMASK_8_4_4', + 6: 'IMG_NUM_FORMAT_FMASK_16_16_1', + 7: 'IMG_NUM_FORMAT_FMASK_16_8_2', + 8: 'IMG_NUM_FORMAT_FMASK_32_16_2', + 9: 'IMG_NUM_FORMAT_FMASK_32_8_4', + 10: 'IMG_NUM_FORMAT_FMASK_32_8_8', + 11: 'IMG_NUM_FORMAT_FMASK_64_16_4', + 12: 'IMG_NUM_FORMAT_FMASK_64_16_8', + 13: 'IMG_NUM_FORMAT_FMASK_RESERVED_13', + 14: 'IMG_NUM_FORMAT_FMASK_RESERVED_14', + 15: 'IMG_NUM_FORMAT_FMASK_RESERVED_15', +} +IMG_NUM_FORMAT_FMASK_8_2_1 = 0 +IMG_NUM_FORMAT_FMASK_8_4_1 = 1 +IMG_NUM_FORMAT_FMASK_8_8_1 = 2 +IMG_NUM_FORMAT_FMASK_8_2_2 = 3 +IMG_NUM_FORMAT_FMASK_8_4_2 = 4 +IMG_NUM_FORMAT_FMASK_8_4_4 = 5 +IMG_NUM_FORMAT_FMASK_16_16_1 = 6 +IMG_NUM_FORMAT_FMASK_16_8_2 = 7 +IMG_NUM_FORMAT_FMASK_32_16_2 = 8 +IMG_NUM_FORMAT_FMASK_32_8_4 = 9 +IMG_NUM_FORMAT_FMASK_32_8_8 = 10 +IMG_NUM_FORMAT_FMASK_64_16_4 = 11 +IMG_NUM_FORMAT_FMASK_64_16_8 = 12 +IMG_NUM_FORMAT_FMASK_RESERVED_13 = 13 +IMG_NUM_FORMAT_FMASK_RESERVED_14 = 14 +IMG_NUM_FORMAT_FMASK_RESERVED_15 = 15 +IMG_NUM_FORMAT_FMASK = ctypes.c_uint32 # enum + +# values for enumeration 'IMG_NUM_FORMAT_N_IN_16' +IMG_NUM_FORMAT_N_IN_16__enumvalues = { + 0: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_0', + 1: 'IMG_NUM_FORMAT_N_IN_16_UNORM_10', + 2: 'IMG_NUM_FORMAT_N_IN_16_UNORM_9', + 3: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_3', + 4: 'IMG_NUM_FORMAT_N_IN_16_UINT_10', + 5: 'IMG_NUM_FORMAT_N_IN_16_UINT_9', + 6: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_6', + 7: 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10', + 8: 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9', + 9: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_9', + 10: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_10', + 11: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_11', + 12: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_12', + 13: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_13', + 14: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_14', + 15: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_15', +} +IMG_NUM_FORMAT_N_IN_16_RESERVED_0 = 0 +IMG_NUM_FORMAT_N_IN_16_UNORM_10 = 1 +IMG_NUM_FORMAT_N_IN_16_UNORM_9 = 2 +IMG_NUM_FORMAT_N_IN_16_RESERVED_3 = 3 +IMG_NUM_FORMAT_N_IN_16_UINT_10 = 4 +IMG_NUM_FORMAT_N_IN_16_UINT_9 = 5 +IMG_NUM_FORMAT_N_IN_16_RESERVED_6 = 6 +IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10 = 7 +IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9 = 8 +IMG_NUM_FORMAT_N_IN_16_RESERVED_9 = 9 +IMG_NUM_FORMAT_N_IN_16_RESERVED_10 = 10 +IMG_NUM_FORMAT_N_IN_16_RESERVED_11 = 11 +IMG_NUM_FORMAT_N_IN_16_RESERVED_12 = 12 +IMG_NUM_FORMAT_N_IN_16_RESERVED_13 = 13 +IMG_NUM_FORMAT_N_IN_16_RESERVED_14 = 14 +IMG_NUM_FORMAT_N_IN_16_RESERVED_15 = 15 +IMG_NUM_FORMAT_N_IN_16 = ctypes.c_uint32 # enum + +# values for enumeration 'IMG_NUM_FORMAT_ASTC_2D' +IMG_NUM_FORMAT_ASTC_2D__enumvalues = { + 0: 'IMG_NUM_FORMAT_ASTC_2D_4x4', + 1: 'IMG_NUM_FORMAT_ASTC_2D_5x4', + 2: 'IMG_NUM_FORMAT_ASTC_2D_5x5', + 3: 'IMG_NUM_FORMAT_ASTC_2D_6x5', + 4: 'IMG_NUM_FORMAT_ASTC_2D_6x6', + 5: 'IMG_NUM_FORMAT_ASTC_2D_8x5', + 6: 'IMG_NUM_FORMAT_ASTC_2D_8x6', + 7: 'IMG_NUM_FORMAT_ASTC_2D_8x8', + 8: 'IMG_NUM_FORMAT_ASTC_2D_10x5', + 9: 'IMG_NUM_FORMAT_ASTC_2D_10x6', + 10: 'IMG_NUM_FORMAT_ASTC_2D_10x8', + 11: 'IMG_NUM_FORMAT_ASTC_2D_10x10', + 12: 'IMG_NUM_FORMAT_ASTC_2D_12x10', + 13: 'IMG_NUM_FORMAT_ASTC_2D_12x12', + 14: 'IMG_NUM_FORMAT_ASTC_2D_RESERVED_14', + 15: 'IMG_NUM_FORMAT_ASTC_2D_RESERVED_15', +} +IMG_NUM_FORMAT_ASTC_2D_4x4 = 0 +IMG_NUM_FORMAT_ASTC_2D_5x4 = 1 +IMG_NUM_FORMAT_ASTC_2D_5x5 = 2 +IMG_NUM_FORMAT_ASTC_2D_6x5 = 3 +IMG_NUM_FORMAT_ASTC_2D_6x6 = 4 +IMG_NUM_FORMAT_ASTC_2D_8x5 = 5 +IMG_NUM_FORMAT_ASTC_2D_8x6 = 6 +IMG_NUM_FORMAT_ASTC_2D_8x8 = 7 +IMG_NUM_FORMAT_ASTC_2D_10x5 = 8 +IMG_NUM_FORMAT_ASTC_2D_10x6 = 9 +IMG_NUM_FORMAT_ASTC_2D_10x8 = 10 +IMG_NUM_FORMAT_ASTC_2D_10x10 = 11 +IMG_NUM_FORMAT_ASTC_2D_12x10 = 12 +IMG_NUM_FORMAT_ASTC_2D_12x12 = 13 +IMG_NUM_FORMAT_ASTC_2D_RESERVED_14 = 14 +IMG_NUM_FORMAT_ASTC_2D_RESERVED_15 = 15 +IMG_NUM_FORMAT_ASTC_2D = ctypes.c_uint32 # enum + +# values for enumeration 'IMG_NUM_FORMAT_ASTC_3D' +IMG_NUM_FORMAT_ASTC_3D__enumvalues = { + 0: 'IMG_NUM_FORMAT_ASTC_3D_3x3x3', + 1: 'IMG_NUM_FORMAT_ASTC_3D_4x3x3', + 2: 'IMG_NUM_FORMAT_ASTC_3D_4x4x3', + 3: 'IMG_NUM_FORMAT_ASTC_3D_4x4x4', + 4: 'IMG_NUM_FORMAT_ASTC_3D_5x4x4', + 5: 'IMG_NUM_FORMAT_ASTC_3D_5x5x4', + 6: 'IMG_NUM_FORMAT_ASTC_3D_5x5x5', + 7: 'IMG_NUM_FORMAT_ASTC_3D_6x5x5', + 8: 'IMG_NUM_FORMAT_ASTC_3D_6x6x5', + 9: 'IMG_NUM_FORMAT_ASTC_3D_6x6x6', + 10: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_10', + 11: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_11', + 12: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_12', + 13: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_13', + 14: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_14', + 15: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_15', +} +IMG_NUM_FORMAT_ASTC_3D_3x3x3 = 0 +IMG_NUM_FORMAT_ASTC_3D_4x3x3 = 1 +IMG_NUM_FORMAT_ASTC_3D_4x4x3 = 2 +IMG_NUM_FORMAT_ASTC_3D_4x4x4 = 3 +IMG_NUM_FORMAT_ASTC_3D_5x4x4 = 4 +IMG_NUM_FORMAT_ASTC_3D_5x5x4 = 5 +IMG_NUM_FORMAT_ASTC_3D_5x5x5 = 6 +IMG_NUM_FORMAT_ASTC_3D_6x5x5 = 7 +IMG_NUM_FORMAT_ASTC_3D_6x6x5 = 8 +IMG_NUM_FORMAT_ASTC_3D_6x6x6 = 9 +IMG_NUM_FORMAT_ASTC_3D_RESERVED_10 = 10 +IMG_NUM_FORMAT_ASTC_3D_RESERVED_11 = 11 +IMG_NUM_FORMAT_ASTC_3D_RESERVED_12 = 12 +IMG_NUM_FORMAT_ASTC_3D_RESERVED_13 = 13 +IMG_NUM_FORMAT_ASTC_3D_RESERVED_14 = 14 +IMG_NUM_FORMAT_ASTC_3D_RESERVED_15 = 15 +IMG_NUM_FORMAT_ASTC_3D = ctypes.c_uint32 # enum + +# values for enumeration 'TileType' +TileType__enumvalues = { + 0: 'ARRAY_COLOR_TILE', + 1: 'ARRAY_DEPTH_TILE', +} +ARRAY_COLOR_TILE = 0 +ARRAY_DEPTH_TILE = 1 +TileType = ctypes.c_uint32 # enum + +# values for enumeration 'NonDispTilingOrder' +NonDispTilingOrder__enumvalues = { + 0: 'ADDR_SURF_MICRO_TILING_DISPLAY', + 1: 'ADDR_SURF_MICRO_TILING_NON_DISPLAY', +} +ADDR_SURF_MICRO_TILING_DISPLAY = 0 +ADDR_SURF_MICRO_TILING_NON_DISPLAY = 1 +NonDispTilingOrder = ctypes.c_uint32 # enum + +# values for enumeration 'MicroTileMode' +MicroTileMode__enumvalues = { + 0: 'ADDR_SURF_DISPLAY_MICRO_TILING', + 1: 'ADDR_SURF_THIN_MICRO_TILING', + 2: 'ADDR_SURF_DEPTH_MICRO_TILING', + 3: 'ADDR_SURF_ROTATED_MICRO_TILING', + 4: 'ADDR_SURF_THICK_MICRO_TILING', +} +ADDR_SURF_DISPLAY_MICRO_TILING = 0 +ADDR_SURF_THIN_MICRO_TILING = 1 +ADDR_SURF_DEPTH_MICRO_TILING = 2 +ADDR_SURF_ROTATED_MICRO_TILING = 3 +ADDR_SURF_THICK_MICRO_TILING = 4 +MicroTileMode = ctypes.c_uint32 # enum + +# values for enumeration 'TileSplit' +TileSplit__enumvalues = { + 0: 'ADDR_SURF_TILE_SPLIT_64B', + 1: 'ADDR_SURF_TILE_SPLIT_128B', + 2: 'ADDR_SURF_TILE_SPLIT_256B', + 3: 'ADDR_SURF_TILE_SPLIT_512B', + 4: 'ADDR_SURF_TILE_SPLIT_1KB', + 5: 'ADDR_SURF_TILE_SPLIT_2KB', + 6: 'ADDR_SURF_TILE_SPLIT_4KB', +} +ADDR_SURF_TILE_SPLIT_64B = 0 +ADDR_SURF_TILE_SPLIT_128B = 1 +ADDR_SURF_TILE_SPLIT_256B = 2 +ADDR_SURF_TILE_SPLIT_512B = 3 +ADDR_SURF_TILE_SPLIT_1KB = 4 +ADDR_SURF_TILE_SPLIT_2KB = 5 +ADDR_SURF_TILE_SPLIT_4KB = 6 +TileSplit = ctypes.c_uint32 # enum + +# values for enumeration 'SampleSplit' +SampleSplit__enumvalues = { + 0: 'ADDR_SURF_SAMPLE_SPLIT_1', + 1: 'ADDR_SURF_SAMPLE_SPLIT_2', + 2: 'ADDR_SURF_SAMPLE_SPLIT_4', + 3: 'ADDR_SURF_SAMPLE_SPLIT_8', +} +ADDR_SURF_SAMPLE_SPLIT_1 = 0 +ADDR_SURF_SAMPLE_SPLIT_2 = 1 +ADDR_SURF_SAMPLE_SPLIT_4 = 2 +ADDR_SURF_SAMPLE_SPLIT_8 = 3 +SampleSplit = ctypes.c_uint32 # enum + +# values for enumeration 'PipeConfig' +PipeConfig__enumvalues = { + 0: 'ADDR_SURF_P2', + 1: 'ADDR_SURF_P2_RESERVED0', + 2: 'ADDR_SURF_P2_RESERVED1', + 3: 'ADDR_SURF_P2_RESERVED2', + 4: 'ADDR_SURF_P4_8x16', + 5: 'ADDR_SURF_P4_16x16', + 6: 'ADDR_SURF_P4_16x32', + 7: 'ADDR_SURF_P4_32x32', + 8: 'ADDR_SURF_P8_16x16_8x16', + 9: 'ADDR_SURF_P8_16x32_8x16', + 10: 'ADDR_SURF_P8_32x32_8x16', + 11: 'ADDR_SURF_P8_16x32_16x16', + 12: 'ADDR_SURF_P8_32x32_16x16', + 13: 'ADDR_SURF_P8_32x32_16x32', + 14: 'ADDR_SURF_P8_32x64_32x32', + 15: 'ADDR_SURF_P8_RESERVED0', + 16: 'ADDR_SURF_P16_32x32_8x16', + 17: 'ADDR_SURF_P16_32x32_16x16', +} +ADDR_SURF_P2 = 0 +ADDR_SURF_P2_RESERVED0 = 1 +ADDR_SURF_P2_RESERVED1 = 2 +ADDR_SURF_P2_RESERVED2 = 3 +ADDR_SURF_P4_8x16 = 4 +ADDR_SURF_P4_16x16 = 5 +ADDR_SURF_P4_16x32 = 6 +ADDR_SURF_P4_32x32 = 7 +ADDR_SURF_P8_16x16_8x16 = 8 +ADDR_SURF_P8_16x32_8x16 = 9 +ADDR_SURF_P8_32x32_8x16 = 10 +ADDR_SURF_P8_16x32_16x16 = 11 +ADDR_SURF_P8_32x32_16x16 = 12 +ADDR_SURF_P8_32x32_16x32 = 13 +ADDR_SURF_P8_32x64_32x32 = 14 +ADDR_SURF_P8_RESERVED0 = 15 +ADDR_SURF_P16_32x32_8x16 = 16 +ADDR_SURF_P16_32x32_16x16 = 17 +PipeConfig = ctypes.c_uint32 # enum + +# values for enumeration 'SeEnable' +SeEnable__enumvalues = { + 0: 'ADDR_CONFIG_DISABLE_SE', + 1: 'ADDR_CONFIG_ENABLE_SE', +} +ADDR_CONFIG_DISABLE_SE = 0 +ADDR_CONFIG_ENABLE_SE = 1 +SeEnable = ctypes.c_uint32 # enum + +# values for enumeration 'NumBanks' +NumBanks__enumvalues = { + 0: 'ADDR_SURF_2_BANK', + 1: 'ADDR_SURF_4_BANK', + 2: 'ADDR_SURF_8_BANK', + 3: 'ADDR_SURF_16_BANK', +} +ADDR_SURF_2_BANK = 0 +ADDR_SURF_4_BANK = 1 +ADDR_SURF_8_BANK = 2 +ADDR_SURF_16_BANK = 3 +NumBanks = ctypes.c_uint32 # enum + +# values for enumeration 'BankWidth' +BankWidth__enumvalues = { + 0: 'ADDR_SURF_BANK_WIDTH_1', + 1: 'ADDR_SURF_BANK_WIDTH_2', + 2: 'ADDR_SURF_BANK_WIDTH_4', + 3: 'ADDR_SURF_BANK_WIDTH_8', +} +ADDR_SURF_BANK_WIDTH_1 = 0 +ADDR_SURF_BANK_WIDTH_2 = 1 +ADDR_SURF_BANK_WIDTH_4 = 2 +ADDR_SURF_BANK_WIDTH_8 = 3 +BankWidth = ctypes.c_uint32 # enum + +# values for enumeration 'BankHeight' +BankHeight__enumvalues = { + 0: 'ADDR_SURF_BANK_HEIGHT_1', + 1: 'ADDR_SURF_BANK_HEIGHT_2', + 2: 'ADDR_SURF_BANK_HEIGHT_4', + 3: 'ADDR_SURF_BANK_HEIGHT_8', +} +ADDR_SURF_BANK_HEIGHT_1 = 0 +ADDR_SURF_BANK_HEIGHT_2 = 1 +ADDR_SURF_BANK_HEIGHT_4 = 2 +ADDR_SURF_BANK_HEIGHT_8 = 3 +BankHeight = ctypes.c_uint32 # enum + +# values for enumeration 'BankWidthHeight' +BankWidthHeight__enumvalues = { + 0: 'ADDR_SURF_BANK_WH_1', + 1: 'ADDR_SURF_BANK_WH_2', + 2: 'ADDR_SURF_BANK_WH_4', + 3: 'ADDR_SURF_BANK_WH_8', +} +ADDR_SURF_BANK_WH_1 = 0 +ADDR_SURF_BANK_WH_2 = 1 +ADDR_SURF_BANK_WH_4 = 2 +ADDR_SURF_BANK_WH_8 = 3 +BankWidthHeight = ctypes.c_uint32 # enum + +# values for enumeration 'MacroTileAspect' +MacroTileAspect__enumvalues = { + 0: 'ADDR_SURF_MACRO_ASPECT_1', + 1: 'ADDR_SURF_MACRO_ASPECT_2', + 2: 'ADDR_SURF_MACRO_ASPECT_4', + 3: 'ADDR_SURF_MACRO_ASPECT_8', +} +ADDR_SURF_MACRO_ASPECT_1 = 0 +ADDR_SURF_MACRO_ASPECT_2 = 1 +ADDR_SURF_MACRO_ASPECT_4 = 2 +ADDR_SURF_MACRO_ASPECT_8 = 3 +MacroTileAspect = ctypes.c_uint32 # enum + +# values for enumeration 'GATCL1RequestType' +GATCL1RequestType__enumvalues = { + 0: 'GATCL1_TYPE_NORMAL', + 1: 'GATCL1_TYPE_SHOOTDOWN', + 2: 'GATCL1_TYPE_BYPASS', +} +GATCL1_TYPE_NORMAL = 0 +GATCL1_TYPE_SHOOTDOWN = 1 +GATCL1_TYPE_BYPASS = 2 +GATCL1RequestType = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL1RequestType' +UTCL1RequestType__enumvalues = { + 0: 'UTCL1_TYPE_NORMAL', + 1: 'UTCL1_TYPE_SHOOTDOWN', + 2: 'UTCL1_TYPE_BYPASS', +} +UTCL1_TYPE_NORMAL = 0 +UTCL1_TYPE_SHOOTDOWN = 1 +UTCL1_TYPE_BYPASS = 2 +UTCL1RequestType = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL1FaultType' +UTCL1FaultType__enumvalues = { + 0: 'UTCL1_XNACK_SUCCESS', + 1: 'UTCL1_XNACK_RETRY', + 2: 'UTCL1_XNACK_PRT', + 3: 'UTCL1_XNACK_NO_RETRY', +} +UTCL1_XNACK_SUCCESS = 0 +UTCL1_XNACK_RETRY = 1 +UTCL1_XNACK_PRT = 2 +UTCL1_XNACK_NO_RETRY = 3 +UTCL1FaultType = ctypes.c_uint32 # enum + +# values for enumeration 'TCC_CACHE_POLICIES' +TCC_CACHE_POLICIES__enumvalues = { + 0: 'TCC_CACHE_POLICY_LRU', + 1: 'TCC_CACHE_POLICY_STREAM', +} +TCC_CACHE_POLICY_LRU = 0 +TCC_CACHE_POLICY_STREAM = 1 +TCC_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'MTYPE' +MTYPE__enumvalues = { + 0: 'MTYPE_NC', + 1: 'MTYPE_WC', + 1: 'MTYPE_RW', + 2: 'MTYPE_CC', + 3: 'MTYPE_UC', +} +MTYPE_NC = 0 +MTYPE_WC = 1 +MTYPE_RW = 1 +MTYPE_CC = 2 +MTYPE_UC = 3 +MTYPE = ctypes.c_uint32 # enum + +# values for enumeration 'RMI_CID' +RMI_CID__enumvalues = { + 0: 'RMI_CID_CC', + 1: 'RMI_CID_FC', + 2: 'RMI_CID_CM', + 3: 'RMI_CID_DC', + 4: 'RMI_CID_Z', + 5: 'RMI_CID_S', + 6: 'RMI_CID_TILE', + 7: 'RMI_CID_ZPCPSD', +} +RMI_CID_CC = 0 +RMI_CID_FC = 1 +RMI_CID_CM = 2 +RMI_CID_DC = 3 +RMI_CID_Z = 4 +RMI_CID_S = 5 +RMI_CID_TILE = 6 +RMI_CID_ZPCPSD = 7 +RMI_CID = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_COUNTER_MODE' +PERFMON_COUNTER_MODE__enumvalues = { + 0: 'PERFMON_COUNTER_MODE_ACCUM', + 1: 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', + 2: 'PERFMON_COUNTER_MODE_MAX', + 3: 'PERFMON_COUNTER_MODE_DIRTY', + 4: 'PERFMON_COUNTER_MODE_SAMPLE', + 5: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', + 6: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', + 7: 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', + 8: 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', + 9: 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', + 15: 'PERFMON_COUNTER_MODE_RESERVED', +} +PERFMON_COUNTER_MODE_ACCUM = 0 +PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 1 +PERFMON_COUNTER_MODE_MAX = 2 +PERFMON_COUNTER_MODE_DIRTY = 3 +PERFMON_COUNTER_MODE_SAMPLE = 4 +PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 5 +PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 6 +PERFMON_COUNTER_MODE_CYCLES_GE_HI = 7 +PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 8 +PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 9 +PERFMON_COUNTER_MODE_RESERVED = 15 +PERFMON_COUNTER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_SPM_MODE' +PERFMON_SPM_MODE__enumvalues = { + 0: 'PERFMON_SPM_MODE_OFF', + 1: 'PERFMON_SPM_MODE_16BIT_CLAMP', + 2: 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', + 3: 'PERFMON_SPM_MODE_32BIT_CLAMP', + 4: 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', + 5: 'PERFMON_SPM_MODE_RESERVED_5', + 6: 'PERFMON_SPM_MODE_RESERVED_6', + 7: 'PERFMON_SPM_MODE_RESERVED_7', + 8: 'PERFMON_SPM_MODE_TEST_MODE_0', + 9: 'PERFMON_SPM_MODE_TEST_MODE_1', + 10: 'PERFMON_SPM_MODE_TEST_MODE_2', +} +PERFMON_SPM_MODE_OFF = 0 +PERFMON_SPM_MODE_16BIT_CLAMP = 1 +PERFMON_SPM_MODE_16BIT_NO_CLAMP = 2 +PERFMON_SPM_MODE_32BIT_CLAMP = 3 +PERFMON_SPM_MODE_32BIT_NO_CLAMP = 4 +PERFMON_SPM_MODE_RESERVED_5 = 5 +PERFMON_SPM_MODE_RESERVED_6 = 6 +PERFMON_SPM_MODE_RESERVED_7 = 7 +PERFMON_SPM_MODE_TEST_MODE_0 = 8 +PERFMON_SPM_MODE_TEST_MODE_1 = 9 +PERFMON_SPM_MODE_TEST_MODE_2 = 10 +PERFMON_SPM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SurfaceTiling' +SurfaceTiling__enumvalues = { + 0: 'ARRAY_LINEAR', + 1: 'ARRAY_TILED', +} +ARRAY_LINEAR = 0 +ARRAY_TILED = 1 +SurfaceTiling = ctypes.c_uint32 # enum + +# values for enumeration 'SurfaceArray' +SurfaceArray__enumvalues = { + 0: 'ARRAY_1D', + 1: 'ARRAY_2D', + 2: 'ARRAY_3D', + 3: 'ARRAY_3D_SLICE', +} +ARRAY_1D = 0 +ARRAY_2D = 1 +ARRAY_3D = 2 +ARRAY_3D_SLICE = 3 +SurfaceArray = ctypes.c_uint32 # enum + +# values for enumeration 'ColorArray' +ColorArray__enumvalues = { + 0: 'ARRAY_2D_ALT_COLOR', + 1: 'ARRAY_2D_COLOR', + 3: 'ARRAY_3D_SLICE_COLOR', +} +ARRAY_2D_ALT_COLOR = 0 +ARRAY_2D_COLOR = 1 +ARRAY_3D_SLICE_COLOR = 3 +ColorArray = ctypes.c_uint32 # enum + +# values for enumeration 'DepthArray' +DepthArray__enumvalues = { + 0: 'ARRAY_2D_ALT_DEPTH', + 1: 'ARRAY_2D_DEPTH', +} +ARRAY_2D_ALT_DEPTH = 0 +ARRAY_2D_DEPTH = 1 +DepthArray = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_NUM_SIMD_PER_CU' +ENUM_NUM_SIMD_PER_CU__enumvalues = { + 4: 'NUM_SIMD_PER_CU', +} +NUM_SIMD_PER_CU = 4 +ENUM_NUM_SIMD_PER_CU = ctypes.c_uint32 # enum + +# values for enumeration 'DSM_ENABLE_ERROR_INJECT' +DSM_ENABLE_ERROR_INJECT__enumvalues = { + 0: 'DSM_ENABLE_ERROR_INJECT_FED_IN', + 1: 'DSM_ENABLE_ERROR_INJECT_SINGLE', + 2: 'DSM_ENABLE_ERROR_INJECT_DOUBLE', + 3: 'DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED', +} +DSM_ENABLE_ERROR_INJECT_FED_IN = 0 +DSM_ENABLE_ERROR_INJECT_SINGLE = 1 +DSM_ENABLE_ERROR_INJECT_DOUBLE = 2 +DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED = 3 +DSM_ENABLE_ERROR_INJECT = ctypes.c_uint32 # enum + +# values for enumeration 'DSM_SELECT_INJECT_DELAY' +DSM_SELECT_INJECT_DELAY__enumvalues = { + 0: 'DSM_SELECT_INJECT_DELAY_NO_DELAY', + 1: 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', +} +DSM_SELECT_INJECT_DELAY_NO_DELAY = 0 +DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 1 +DSM_SELECT_INJECT_DELAY = ctypes.c_uint32 # enum + +# values for enumeration 'SWIZZLE_TYPE_ENUM' +SWIZZLE_TYPE_ENUM__enumvalues = { + 0: 'SW_Z', + 1: 'SW_S', + 2: 'SW_D', + 3: 'SW_R', + 4: 'SW_L', +} +SW_Z = 0 +SW_S = 1 +SW_D = 2 +SW_R = 3 +SW_L = 4 +SWIZZLE_TYPE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'TC_MICRO_TILE_MODE' +TC_MICRO_TILE_MODE__enumvalues = { + 0: 'MICRO_TILE_MODE_LINEAR', + 1: 'MICRO_TILE_MODE_ROTATED', + 2: 'MICRO_TILE_MODE_STD_2D', + 3: 'MICRO_TILE_MODE_STD_3D', + 4: 'MICRO_TILE_MODE_DISPLAY_2D', + 5: 'MICRO_TILE_MODE_DISPLAY_3D', + 6: 'MICRO_TILE_MODE_Z_2D', + 7: 'MICRO_TILE_MODE_Z_3D', +} +MICRO_TILE_MODE_LINEAR = 0 +MICRO_TILE_MODE_ROTATED = 1 +MICRO_TILE_MODE_STD_2D = 2 +MICRO_TILE_MODE_STD_3D = 3 +MICRO_TILE_MODE_DISPLAY_2D = 4 +MICRO_TILE_MODE_DISPLAY_3D = 5 +MICRO_TILE_MODE_Z_2D = 6 +MICRO_TILE_MODE_Z_3D = 7 +TC_MICRO_TILE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SWIZZLE_MODE_ENUM' +SWIZZLE_MODE_ENUM__enumvalues = { + 0: 'SW_LINEAR', + 1: 'SW_256B_S', + 2: 'SW_256B_D', + 3: 'SW_256B_R', + 4: 'SW_4KB_Z', + 5: 'SW_4KB_S', + 6: 'SW_4KB_D', + 7: 'SW_4KB_R', + 8: 'SW_64KB_Z', + 9: 'SW_64KB_S', + 10: 'SW_64KB_D', + 11: 'SW_64KB_R', + 12: 'SW_VAR_Z', + 13: 'SW_VAR_S', + 14: 'SW_VAR_D', + 15: 'SW_VAR_R', + 16: 'SW_RESERVED_16', + 17: 'SW_RESERVED_17', + 18: 'SW_RESERVED_18', + 19: 'SW_RESERVED_19', + 20: 'SW_4KB_Z_X', + 21: 'SW_4KB_S_X', + 22: 'SW_4KB_D_X', + 23: 'SW_4KB_R_X', + 24: 'SW_64KB_Z_X', + 25: 'SW_64KB_S_X', + 26: 'SW_64KB_D_X', + 27: 'SW_64KB_R_X', + 28: 'SW_VAR_Z_X', + 29: 'SW_VAR_S_X', + 30: 'SW_VAR_D_X', + 31: 'SW_VAR_R_X', + 32: 'SW_RESERVED_12', + 33: 'SW_RESERVED_13', + 34: 'SW_RESERVED_14', + 35: 'SW_RESERVED_15', +} +SW_LINEAR = 0 +SW_256B_S = 1 +SW_256B_D = 2 +SW_256B_R = 3 +SW_4KB_Z = 4 +SW_4KB_S = 5 +SW_4KB_D = 6 +SW_4KB_R = 7 +SW_64KB_Z = 8 +SW_64KB_S = 9 +SW_64KB_D = 10 +SW_64KB_R = 11 +SW_VAR_Z = 12 +SW_VAR_S = 13 +SW_VAR_D = 14 +SW_VAR_R = 15 +SW_RESERVED_16 = 16 +SW_RESERVED_17 = 17 +SW_RESERVED_18 = 18 +SW_RESERVED_19 = 19 +SW_4KB_Z_X = 20 +SW_4KB_S_X = 21 +SW_4KB_D_X = 22 +SW_4KB_R_X = 23 +SW_64KB_Z_X = 24 +SW_64KB_S_X = 25 +SW_64KB_D_X = 26 +SW_64KB_R_X = 27 +SW_VAR_Z_X = 28 +SW_VAR_S_X = 29 +SW_VAR_D_X = 30 +SW_VAR_R_X = 31 +SW_RESERVED_12 = 32 +SW_RESERVED_13 = 33 +SW_RESERVED_14 = 34 +SW_RESERVED_15 = 35 +SWIZZLE_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'PipeTiling' +PipeTiling__enumvalues = { + 0: 'CONFIG_1_PIPE', + 1: 'CONFIG_2_PIPE', + 2: 'CONFIG_4_PIPE', + 3: 'CONFIG_8_PIPE', +} +CONFIG_1_PIPE = 0 +CONFIG_2_PIPE = 1 +CONFIG_4_PIPE = 2 +CONFIG_8_PIPE = 3 +PipeTiling = ctypes.c_uint32 # enum + +# values for enumeration 'BankTiling' +BankTiling__enumvalues = { + 0: 'CONFIG_4_BANK', + 1: 'CONFIG_8_BANK', +} +CONFIG_4_BANK = 0 +CONFIG_8_BANK = 1 +BankTiling = ctypes.c_uint32 # enum + +# values for enumeration 'GroupInterleave' +GroupInterleave__enumvalues = { + 0: 'CONFIG_256B_GROUP', + 1: 'CONFIG_512B_GROUP', +} +CONFIG_256B_GROUP = 0 +CONFIG_512B_GROUP = 1 +GroupInterleave = ctypes.c_uint32 # enum + +# values for enumeration 'RowTiling' +RowTiling__enumvalues = { + 0: 'CONFIG_1KB_ROW', + 1: 'CONFIG_2KB_ROW', + 2: 'CONFIG_4KB_ROW', + 3: 'CONFIG_8KB_ROW', + 4: 'CONFIG_1KB_ROW_OPT', + 5: 'CONFIG_2KB_ROW_OPT', + 6: 'CONFIG_4KB_ROW_OPT', + 7: 'CONFIG_8KB_ROW_OPT', +} +CONFIG_1KB_ROW = 0 +CONFIG_2KB_ROW = 1 +CONFIG_4KB_ROW = 2 +CONFIG_8KB_ROW = 3 +CONFIG_1KB_ROW_OPT = 4 +CONFIG_2KB_ROW_OPT = 5 +CONFIG_4KB_ROW_OPT = 6 +CONFIG_8KB_ROW_OPT = 7 +RowTiling = ctypes.c_uint32 # enum + +# values for enumeration 'BankSwapBytes' +BankSwapBytes__enumvalues = { + 0: 'CONFIG_128B_SWAPS', + 1: 'CONFIG_256B_SWAPS', + 2: 'CONFIG_512B_SWAPS', + 3: 'CONFIG_1KB_SWAPS', +} +CONFIG_128B_SWAPS = 0 +CONFIG_256B_SWAPS = 1 +CONFIG_512B_SWAPS = 2 +CONFIG_1KB_SWAPS = 3 +BankSwapBytes = ctypes.c_uint32 # enum + +# values for enumeration 'SampleSplitBytes' +SampleSplitBytes__enumvalues = { + 0: 'CONFIG_1KB_SPLIT', + 1: 'CONFIG_2KB_SPLIT', + 2: 'CONFIG_4KB_SPLIT', + 3: 'CONFIG_8KB_SPLIT', +} +CONFIG_1KB_SPLIT = 0 +CONFIG_2KB_SPLIT = 1 +CONFIG_4KB_SPLIT = 2 +CONFIG_8KB_SPLIT = 3 +SampleSplitBytes = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', + 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', + 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', + 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', + 8: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', + 9: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', + 10: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', + 11: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', + 12: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', + 13: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', + 14: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', + 15: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 5 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 6 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 7 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 8 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 9 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 10 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 11 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 12 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 13 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 14 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 15 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_CONTROL_BLND_MODE' +BLNDV_CONTROL_BLND_MODE__enumvalues = { + 0: 'BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY', + 1: 'BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY', + 2: 'BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE', + 3: 'BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE', +} +BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0 +BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 1 +BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 2 +BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 3 +BLNDV_CONTROL_BLND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_CONTROL_BLND_STEREO_TYPE' +BLNDV_CONTROL_BLND_STEREO_TYPE__enumvalues = { + 0: 'BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO', + 1: 'BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO', + 2: 'BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO', + 3: 'BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED', +} +BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0 +BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 1 +BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 2 +BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED = 3 +BLNDV_CONTROL_BLND_STEREO_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_CONTROL_BLND_STEREO_POLARITY' +BLNDV_CONTROL_BLND_STEREO_POLARITY__enumvalues = { + 0: 'BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW', + 1: 'BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH', +} +BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW = 0 +BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH = 1 +BLNDV_CONTROL_BLND_STEREO_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN' +BLNDV_CONTROL_BLND_FEEDTHROUGH_EN__enumvalues = { + 0: 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE', + 1: 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE', +} +BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0 +BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 1 +BLNDV_CONTROL_BLND_FEEDTHROUGH_EN = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_CONTROL_BLND_ALPHA_MODE' +BLNDV_CONTROL_BLND_ALPHA_MODE__enumvalues = { + 0: 'BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA', + 1: 'BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', + 2: 'BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY', + 3: 'BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED', +} +BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0 +BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 1 +BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 2 +BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED = 3 +BLNDV_CONTROL_BLND_ALPHA_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY' +BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY__enumvalues = { + 0: 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE', + 1: 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE', +} +BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE = 0 +BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE = 1 +BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE' +BLNDV_CONTROL_BLND_MULTIPLIED_MODE__enumvalues = { + 0: 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE', + 1: 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE', +} +BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0 +BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 1 +BLNDV_CONTROL_BLND_MULTIPLIED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_SM_CONTROL2_SM_MODE' +BLNDV_SM_CONTROL2_SM_MODE__enumvalues = { + 0: 'BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE', + 2: 'BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING', + 4: 'BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING', + 6: 'BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING', +} +BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0 +BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 2 +BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 4 +BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 6 +BLNDV_SM_CONTROL2_SM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE' +BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE__enumvalues = { + 0: 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE', + 1: 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE', +} +BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0 +BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 1 +BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE' +BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE__enumvalues = { + 0: 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE', + 1: 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE', +} +BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0 +BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 1 +BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL' +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL__enumvalues = { + 0: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', + 1: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED', + 2: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', + 3: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', +} +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0 +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 1 +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 2 +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 3 +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL' +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL__enumvalues = { + 0: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE', + 1: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED', + 2: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', + 3: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', +} +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0 +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 1 +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 2 +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 3 +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_CONTROL2_PTI_ENABLE' +BLNDV_CONTROL2_PTI_ENABLE__enumvalues = { + 0: 'BLNDV_CONTROL2_PTI_ENABLE_FALSE', + 1: 'BLNDV_CONTROL2_PTI_ENABLE_TRUE', +} +BLNDV_CONTROL2_PTI_ENABLE_FALSE = 0 +BLNDV_CONTROL2_PTI_ENABLE_TRUE = 1 +BLNDV_CONTROL2_PTI_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN' +BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN__enumvalues = { + 0: 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE', + 1: 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE', +} +BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0 +BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 1 +BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN' +BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN__enumvalues = { + 0: 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE', + 1: 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE', +} +BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0 +BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 1 +BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK' +BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK__enumvalues = { + 0: 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE', + 1: 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE', +} +BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0 +BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 1 +BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK' +BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK__enumvalues = { + 0: 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE', + 1: 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE', +} +BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0 +BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 1 +BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK' +BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK__enumvalues = { + 0: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE', + 1: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE', +} +BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0 +BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 1 +BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK' +BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__enumvalues = { + 0: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE', + 1: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE', +} +BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0 +BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 1 +BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK' +BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK__enumvalues = { + 0: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE', + 1: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE', +} +BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0 +BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 1 +BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK' +BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK__enumvalues = { + 0: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE', + 1: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE', +} +BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0 +BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 1 +BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK' +BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK__enumvalues = { + 0: 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE', + 1: 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE', +} +BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0 +BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 1 +BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK' +BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK__enumvalues = { + 0: 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE', + 1: 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE', +} +BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0 +BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 1 +BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE' +BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE__enumvalues = { + 0: 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE', + 1: 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE', +} +BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0 +BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 1 +BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT' +BLNDV_DEBUG_BLND_CNV_MUX_SELECT__enumvalues = { + 0: 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW', + 1: 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH', +} +BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0 +BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 1 +BLNDV_DEBUG_BLND_CNV_MUX_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN' +BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE', + 1: 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE', +} +BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0 +BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 1 +BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LBV_PIXEL_DEPTH' +LBV_PIXEL_DEPTH__enumvalues = { + 0: 'PIXEL_DEPTH_30BPP', + 1: 'PIXEL_DEPTH_24BPP', + 2: 'PIXEL_DEPTH_18BPP', + 3: 'PIXEL_DEPTH_38BPP', +} +PIXEL_DEPTH_30BPP = 0 +PIXEL_DEPTH_24BPP = 1 +PIXEL_DEPTH_18BPP = 2 +PIXEL_DEPTH_38BPP = 3 +LBV_PIXEL_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'LBV_PIXEL_EXPAN_MODE' +LBV_PIXEL_EXPAN_MODE__enumvalues = { + 0: 'PIXEL_EXPAN_MODE_ZERO_EXP', + 1: 'PIXEL_EXPAN_MODE_DYN_EXP', +} +PIXEL_EXPAN_MODE_ZERO_EXP = 0 +PIXEL_EXPAN_MODE_DYN_EXP = 1 +LBV_PIXEL_EXPAN_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'LBV_INTERLEAVE_EN' +LBV_INTERLEAVE_EN__enumvalues = { + 0: 'INTERLEAVE_DIS', + 1: 'INTERLEAVE_EN', +} +INTERLEAVE_DIS = 0 +INTERLEAVE_EN = 1 +LBV_INTERLEAVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LBV_PIXEL_REDUCE_MODE' +LBV_PIXEL_REDUCE_MODE__enumvalues = { + 0: 'PIXEL_REDUCE_MODE_TRUNCATION', + 1: 'PIXEL_REDUCE_MODE_ROUNDING', +} +PIXEL_REDUCE_MODE_TRUNCATION = 0 +PIXEL_REDUCE_MODE_ROUNDING = 1 +LBV_PIXEL_REDUCE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'LBV_DYNAMIC_PIXEL_DEPTH' +LBV_DYNAMIC_PIXEL_DEPTH__enumvalues = { + 0: 'DYNAMIC_PIXEL_DEPTH_36BPP', + 1: 'DYNAMIC_PIXEL_DEPTH_30BPP', +} +DYNAMIC_PIXEL_DEPTH_36BPP = 0 +DYNAMIC_PIXEL_DEPTH_30BPP = 1 +LBV_DYNAMIC_PIXEL_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'LBV_DITHER_EN' +LBV_DITHER_EN__enumvalues = { + 0: 'DITHER_DIS', + 1: 'DITHER_EN', +} +DITHER_DIS = 0 +DITHER_EN = 1 +LBV_DITHER_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LBV_DOWNSCALE_PREFETCH_EN' +LBV_DOWNSCALE_PREFETCH_EN__enumvalues = { + 0: 'DOWNSCALE_PREFETCH_DIS', + 1: 'DOWNSCALE_PREFETCH_EN', +} +DOWNSCALE_PREFETCH_DIS = 0 +DOWNSCALE_PREFETCH_EN = 1 +LBV_DOWNSCALE_PREFETCH_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LBV_MEMORY_CONFIG' +LBV_MEMORY_CONFIG__enumvalues = { + 0: 'MEMORY_CONFIG_0', + 1: 'MEMORY_CONFIG_1', + 2: 'MEMORY_CONFIG_2', + 3: 'MEMORY_CONFIG_3', +} +MEMORY_CONFIG_0 = 0 +MEMORY_CONFIG_1 = 1 +MEMORY_CONFIG_2 = 2 +MEMORY_CONFIG_3 = 3 +LBV_MEMORY_CONFIG = ctypes.c_uint32 # enum + +# values for enumeration 'LBV_SYNC_RESET_SEL2' +LBV_SYNC_RESET_SEL2__enumvalues = { + 0: 'SYNC_RESET_SEL2_VBLANK', + 1: 'SYNC_RESET_SEL2_VSYNC', +} +SYNC_RESET_SEL2_VBLANK = 0 +SYNC_RESET_SEL2_VSYNC = 1 +LBV_SYNC_RESET_SEL2 = ctypes.c_uint32 # enum + +# values for enumeration 'LBV_SYNC_DURATION' +LBV_SYNC_DURATION__enumvalues = { + 0: 'SYNC_DURATION_16', + 1: 'SYNC_DURATION_32', + 2: 'SYNC_DURATION_64', + 3: 'SYNC_DURATION_128', +} +SYNC_DURATION_16 = 0 +SYNC_DURATION_32 = 1 +SYNC_DURATION_64 = 2 +SYNC_DURATION_128 = 3 +LBV_SYNC_DURATION = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CONTROL_CRTC_START_POINT_CNTL' +CRTC_CONTROL_CRTC_START_POINT_CNTL__enumvalues = { + 0: 'CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL', + 1: 'CRTC_CONTROL_CRTC_START_POINT_CNTL_DP', +} +CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0 +CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 1 +CRTC_CONTROL_CRTC_START_POINT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL' +CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL__enumvalues = { + 0: 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL', + 1: 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP', +} +CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0 +CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 1 +CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL' +CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL__enumvalues = { + 0: 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE', + 1: 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT', + 2: 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED', + 3: 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST', +} +CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0 +CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT = 1 +CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 2 +CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST = 3 +CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY' +CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY__enumvalues = { + 0: 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE', + 1: 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE', +} +CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0 +CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 1 +CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE' +CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE__enumvalues = { + 0: 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE', + 1: 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE', +} +CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE = 0 +CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 1 +CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CONTROL_CRTC_SOF_PULL_EN' +CRTC_CONTROL_CRTC_SOF_PULL_EN__enumvalues = { + 0: 'CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE', + 1: 'CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE', +} +CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE = 0 +CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE = 1 +CRTC_CONTROL_CRTC_SOF_PULL_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL' +CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL__enumvalues = { + 0: 'CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE', + 1: 'CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE', +} +CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE = 0 +CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE = 1 +CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL' +CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL__enumvalues = { + 0: 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE', + 1: 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE', +} +CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE = 0 +CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE = 1 +CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL' +CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL__enumvalues = { + 0: 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE', + 1: 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE', +} +CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE = 0 +CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE = 1 +CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN' +CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN__enumvalues = { + 0: 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE', + 1: 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE', +} +CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE = 0 +CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE = 1 +CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC' +CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC__enumvalues = { + 0: 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', + 1: 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', +} +CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0 +CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 1 +CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT' +CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT__enumvalues = { + 0: 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE', + 1: 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE', +} +CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE = 0 +CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE = 1 +CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK' +CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__enumvalues = { + 0: 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE', + 1: 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE', +} +CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0 +CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE = 1 +CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR' +CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR__enumvalues = { + 0: 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE', + 1: 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE', +} +CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE = 0 +CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE = 1 +CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL' +CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL__enumvalues = { + 0: 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE', + 1: 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE', +} +CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE = 0 +CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE = 1 +CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN' +CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN__enumvalues = { + 0: 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE', + 1: 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE', +} +CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE = 0 +CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE = 1 +CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT' +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT__enumvalues = { + 1: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER', + 2: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER', + 5: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF', + 6: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE', + 7: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA', + 8: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA', + 9: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB', + 10: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB', + 11: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1', + 12: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2', + 13: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD', + 14: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC', + 16: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0', + 17: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1', + 18: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2', + 19: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON', + 20: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA', + 21: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB', + 22: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW', + 23: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW', +} +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER = 1 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER = 2 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF = 5 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE = 6 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA = 7 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA = 8 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB = 9 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB = 10 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1 = 11 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2 = 12 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD = 13 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC = 14 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0 = 16 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1 = 17 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2 = 18 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON = 19 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA = 20 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB = 21 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW = 22 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW = 23 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT' +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT__enumvalues = { + 1: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE', + 2: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA', + 3: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB', + 4: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA', + 5: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB', + 6: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO', + 7: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC', +} +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE = 1 +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA = 2 +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB = 3 +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA = 4 +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB = 5 +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 6 +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC = 7 +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN' +CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN__enumvalues = { + 0: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE', + 1: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE', +} +CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE = 0 +CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 1 +CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR' +CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR__enumvalues = { + 0: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE', + 1: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE', +} +CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE = 0 +CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE = 1 +CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT' +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT__enumvalues = { + 1: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER', + 2: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER', + 5: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF', + 6: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE', + 7: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA', + 8: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA', + 9: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB', + 10: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB', + 11: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1', + 12: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2', + 13: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD', + 14: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC', + 16: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0', + 17: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1', + 18: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2', + 19: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON', + 20: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA', + 21: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB', + 22: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW', + 23: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW', +} +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER = 1 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER = 2 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF = 5 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE = 6 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA = 7 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA = 8 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB = 9 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB = 10 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1 = 11 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2 = 12 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD = 13 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC = 14 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0 = 16 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1 = 17 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2 = 18 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON = 19 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA = 20 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB = 21 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW = 22 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW = 23 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT' +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT__enumvalues = { + 1: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE', + 2: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA', + 3: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB', + 4: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA', + 5: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB', + 6: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO', + 7: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC', +} +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE = 1 +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA = 2 +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB = 3 +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA = 4 +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB = 5 +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 6 +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC = 7 +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN' +CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN__enumvalues = { + 0: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE', + 1: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE', +} +CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE = 0 +CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 1 +CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR' +CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR__enumvalues = { + 0: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE', + 1: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE', +} +CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE = 0 +CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE = 1 +CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE' +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE__enumvalues = { + 0: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE', + 1: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT', + 2: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', + 3: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED', +} +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE = 0 +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT = 1 +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 2 +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED = 3 +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK' +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK__enumvalues = { + 0: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE', + 1: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE', +} +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE = 0 +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE = 1 +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL' +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL__enumvalues = { + 0: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE', + 1: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE', +} +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0 +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 1 +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR' +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR__enumvalues = { + 0: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE', + 1: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE', +} +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE = 0 +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE = 1 +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT' +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT__enumvalues = { + 0: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', + 1: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF', + 2: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE', + 3: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1', + 4: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2', + 5: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', + 6: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', + 7: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', + 8: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', + 9: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK', + 10: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL', + 11: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', + 12: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB', + 13: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA', + 14: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD', + 15: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC', +} +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 1 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 2 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 3 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 4 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 5 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 6 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 7 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 8 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK = 9 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL = 10 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 11 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 12 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 13 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 14 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 15 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY' +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY__enumvalues = { + 0: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE', + 1: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE', +} +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE = 0 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE = 1 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY' +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY__enumvalues = { + 0: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE', + 1: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE', +} +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE = 0 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE = 1 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE' +CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE__enumvalues = { + 0: 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO', + 1: 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT', + 2: 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT', + 3: 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED', +} +CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO = 0 +CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT = 1 +CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT = 2 +CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED = 3 +CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CONTROL_CRTC_MASTER_EN' +CRTC_CONTROL_CRTC_MASTER_EN__enumvalues = { + 0: 'CRTC_CONTROL_CRTC_MASTER_EN_FALSE', + 1: 'CRTC_CONTROL_CRTC_MASTER_EN_TRUE', +} +CRTC_CONTROL_CRTC_MASTER_EN_FALSE = 0 +CRTC_CONTROL_CRTC_MASTER_EN_TRUE = 1 +CRTC_CONTROL_CRTC_MASTER_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN' +CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN__enumvalues = { + 0: 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE', + 1: 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE', +} +CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE = 0 +CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE = 1 +CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE' +CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE__enumvalues = { + 0: 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE', + 1: 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE', +} +CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE = 0 +CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE = 1 +CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE' +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE__enumvalues = { + 0: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE', + 1: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE', +} +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE = 0 +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE = 1 +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD' +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD__enumvalues = { + 0: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT', + 1: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD', + 2: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN', + 3: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2', +} +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT = 0 +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD = 1 +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN = 2 +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 3 +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY' +CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY__enumvalues = { + 0: 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE', + 1: 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE', +} +CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE = 0 +CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE = 1 +CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT' +CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT__enumvalues = { + 0: 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE', + 1: 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE', +} +CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE = 0 +CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE = 1 +CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN' +CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN__enumvalues = { + 0: 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE', + 1: 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE', +} +CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE = 0 +CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE = 1 +CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE' +CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__enumvalues = { + 0: 'CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', + 1: 'CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', +} +CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0 +CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 1 +CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR' +CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__enumvalues = { + 0: 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', + 1: 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', +} +CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0 +CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 1 +CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE' +CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE__enumvalues = { + 0: 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE', + 1: 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA', + 2: 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB', + 3: 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED', +} +CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE = 0 +CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 1 +CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 2 +CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED = 3 +CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY' +CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY__enumvalues = { + 0: 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE', + 1: 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE', +} +CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0 +CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 1 +CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY' +CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY__enumvalues = { + 0: 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE', + 1: 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE', +} +CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE = 0 +CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE = 1 +CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY' +CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY__enumvalues = { + 0: 'CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE', + 1: 'CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE', +} +CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE = 0 +CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE = 1 +CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_STEREO_CONTROL_CRTC_STEREO_EN' +CRTC_STEREO_CONTROL_CRTC_STEREO_EN__enumvalues = { + 0: 'CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE', + 1: 'CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE', +} +CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE = 0 +CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE = 1 +CRTC_STEREO_CONTROL_CRTC_STEREO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR' +CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR__enumvalues = { + 0: 'CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE', + 1: 'CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE', +} +CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0 +CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE = 1 +CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL' +CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL__enumvalues = { + 0: 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', + 1: 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', + 2: 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', + 3: 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', +} +CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0 +CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 1 +CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 2 +CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 3 +CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY' +CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY__enumvalues = { + 0: 'CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE', + 1: 'CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE', +} +CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE = 0 +CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE = 1 +CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY' +CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY__enumvalues = { + 0: 'CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE', + 1: 'CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE', +} +CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE = 0 +CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE = 1 +CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN' +CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN__enumvalues = { + 0: 'CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE', + 1: 'CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE', +} +CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE = 0 +CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE = 1 +CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN' +CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN__enumvalues = { + 0: 'CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE', + 1: 'CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE', +} +CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE = 0 +CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE = 1 +CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK' +CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE' +CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK' +CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE' +CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK' +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE' +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK' +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE' +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK' +CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE' +CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK' +CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE' +CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK' +CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE' +CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK' +CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE' +CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK' +CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK__enumvalues = { + 0: 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE', + 1: 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE', +} +CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE = 0 +CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE = 1 +CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY' +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY__enumvalues = { + 0: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE', + 1: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE', +} +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE = 0 +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE = 1 +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN' +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__enumvalues = { + 0: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE', + 1: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE', +} +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE = 0 +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE = 1 +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE' +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__enumvalues = { + 0: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0', + 1: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1', +} +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0 = 0 +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1 = 1 +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE' +CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE__enumvalues = { + 0: 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE', + 1: 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE', +} +CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE = 0 +CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE = 1 +CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN' +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN__enumvalues = { + 0: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE', + 1: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE', +} +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE = 0 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE = 1 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE' +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE__enumvalues = { + 0: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB', + 1: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601', + 2: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709', + 3: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS', + 4: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS', + 5: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB', + 6: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB', + 7: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS', +} +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB = 0 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601 = 1 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709 = 2 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS = 3 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS = 4 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB = 5 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB = 6 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS = 7 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE' +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE__enumvalues = { + 0: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE', + 1: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE', +} +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE = 0 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE = 1 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT' +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT__enumvalues = { + 0: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC', + 1: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC', + 2: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC', + 3: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED', +} +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC = 0 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC = 1 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC = 2 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED = 3 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK' +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', + 1: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', +} +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0 +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 1 +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK' +MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE', + 1: 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE', +} +MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE = 0 +MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE = 1 +MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK' +MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE', + 1: 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE', +} +MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0 +MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 1 +MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE' +MASTER_UPDATE_MODE_MASTER_UPDATE_MODE__enumvalues = { + 0: 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN', + 1: 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA', + 2: 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA', + 3: 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE', +} +MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN = 0 +MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA = 1 +MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA = 2 +MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE = 3 +MASTER_UPDATE_MODE_MASTER_UPDATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE' +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE__enumvalues = { + 0: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', + 1: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN', + 2: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD', + 3: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', +} +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN = 1 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD = 2 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 3 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE' +CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE__enumvalues = { + 0: 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE', + 1: 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG', + 2: 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL', +} +CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE = 0 +CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG = 1 +CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL = 2 +CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR' +CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR__enumvalues = { + 0: 'CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE', + 1: 'CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE', +} +CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0 +CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE = 1 +CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR' +CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__enumvalues = { + 0: 'CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE', + 1: 'CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE', +} +CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0 +CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE = 1 +CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR' +CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR__enumvalues = { + 0: 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE', + 1: 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE', +} +CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE = 0 +CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE = 1 +CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY' +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__enumvalues = { + 0: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', + 1: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', +} +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0 +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 1 +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE' +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__enumvalues = { + 0: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', + 1: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', +} +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0 +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 1 +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR' +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR__enumvalues = { + 0: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE', + 1: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE', +} +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0 +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE = 1 +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE' +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE__enumvalues = { + 0: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', + 1: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', +} +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0 +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 1 +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR' +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR__enumvalues = { + 0: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', + 1: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE', +} +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0 +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE = 1 +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE' +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__enumvalues = { + 0: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', + 1: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', +} +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0 +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 1 +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE' +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE__enumvalues = { + 0: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', + 1: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', +} +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0 +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 1 +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR' +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR__enumvalues = { + 0: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', + 1: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE', +} +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0 +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE = 1 +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE' +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__enumvalues = { + 0: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', + 1: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', +} +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0 +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 1 +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE' +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE__enumvalues = { + 0: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', + 1: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', +} +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0 +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 1 +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CRC_CNTL_CRTC_CRC_EN' +CRTC_CRC_CNTL_CRTC_CRC_EN__enumvalues = { + 0: 'CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE', + 1: 'CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE', +} +CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE = 0 +CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE = 1 +CRTC_CRC_CNTL_CRTC_CRC_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN' +CRTC_CRC_CNTL_CRTC_CRC_CONT_EN__enumvalues = { + 0: 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE', + 1: 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE', +} +CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE = 0 +CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE = 1 +CRTC_CRC_CNTL_CRTC_CRC_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE' +CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE__enumvalues = { + 0: 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT', + 1: 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT', + 2: 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES', + 3: 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS', +} +CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT = 0 +CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT = 1 +CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES = 2 +CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS = 3 +CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE' +CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE__enumvalues = { + 0: 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP', + 1: 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM', + 2: 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM', + 3: 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD', +} +CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP = 0 +CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM = 1 +CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM = 2 +CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 3 +CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS' +CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__enumvalues = { + 0: 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', + 1: 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', +} +CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0 +CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 1 +CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT' +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT__enumvalues = { + 0: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB', + 1: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B', + 2: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB', + 3: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B', + 4: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB', + 5: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B', + 6: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB', + 7: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B', +} +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB = 0 +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B = 1 +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB = 2 +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B = 3 +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB = 4 +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B = 5 +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB = 6 +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B = 7 +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT' +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT__enumvalues = { + 0: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB', + 1: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B', + 2: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB', + 3: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B', + 4: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB', + 5: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B', + 6: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB', + 7: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B', +} +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB = 0 +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B = 1 +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB = 2 +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B = 3 +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB = 4 +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B = 5 +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB = 6 +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B = 7 +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE' +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE', + 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT', + 2: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS', + 3: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED', +} +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE = 0 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT = 1 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS = 2 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED = 3 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE' +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE', +} +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE' +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE', +} +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW' +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel', + 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel', + 2: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel', + 3: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel', +} +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel = 0 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel = 1 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel = 2 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel = 3 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE' +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE', +} +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE' +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE', +} +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY' +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE', +} +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE = 0 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE = 1 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY' +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE', +} +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE = 0 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE = 1 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE' +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE', +} +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE' +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE', +} +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR' +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE', +} +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE = 1 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE' +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE', +} +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT' +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME', + 1: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME', + 2: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME', + 3: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME', + 4: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME', + 5: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME', + 6: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME', + 7: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME', +} +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME = 0 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME = 1 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME = 2 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME = 3 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME = 4 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME = 5 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME = 6 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME = 7 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE' +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE', +} +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR' +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE', +} +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE = 0 +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE = 1 +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE' +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE', +} +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE' +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE', +} +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR' +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE', +} +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0 +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE = 1 +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE' +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE', +} +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE' +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE__enumvalues = { + 0: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE', + 1: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE', +} +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE = 0 +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE = 1 +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR' +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR__enumvalues = { + 0: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE', + 1: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE', +} +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE = 0 +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE = 1 +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE' +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE__enumvalues = { + 0: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE', + 1: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE', +} +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE = 0 +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE = 1 +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE' +CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE__enumvalues = { + 0: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE', + 1: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE', +} +CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE = 0 +CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE = 1 +CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE' +CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE__enumvalues = { + 0: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF', + 1: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON', +} +CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0 +CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON = 1 +CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN' +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN__enumvalues = { + 0: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE', + 1: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE', +} +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE = 0 +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE = 1 +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB' +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB__enumvalues = { + 0: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE', + 1: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE', +} +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE = 0 +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE = 1 +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE' +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE__enumvalues = { + 0: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', + 1: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', + 2: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', + 3: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', +} +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0 +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 1 +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 2 +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 3 +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR' +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR__enumvalues = { + 0: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', + 1: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', +} +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0 +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 1 +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_V_SYNC_A_POL' +CRTC_V_SYNC_A_POL__enumvalues = { + 0: 'CRTC_V_SYNC_A_POL_HIGH', + 1: 'CRTC_V_SYNC_A_POL_LOW', +} +CRTC_V_SYNC_A_POL_HIGH = 0 +CRTC_V_SYNC_A_POL_LOW = 1 +CRTC_V_SYNC_A_POL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_H_SYNC_A_POL' +CRTC_H_SYNC_A_POL__enumvalues = { + 0: 'CRTC_H_SYNC_A_POL_HIGH', + 1: 'CRTC_H_SYNC_A_POL_LOW', +} +CRTC_H_SYNC_A_POL_HIGH = 0 +CRTC_H_SYNC_A_POL_LOW = 1 +CRTC_H_SYNC_A_POL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_HORZ_REPETITION_COUNT' +CRTC_HORZ_REPETITION_COUNT__enumvalues = { + 0: 'CRTC_HORZ_REPETITION_COUNT_0', + 1: 'CRTC_HORZ_REPETITION_COUNT_1', + 2: 'CRTC_HORZ_REPETITION_COUNT_2', + 3: 'CRTC_HORZ_REPETITION_COUNT_3', + 4: 'CRTC_HORZ_REPETITION_COUNT_4', + 5: 'CRTC_HORZ_REPETITION_COUNT_5', + 6: 'CRTC_HORZ_REPETITION_COUNT_6', + 7: 'CRTC_HORZ_REPETITION_COUNT_7', + 8: 'CRTC_HORZ_REPETITION_COUNT_8', + 9: 'CRTC_HORZ_REPETITION_COUNT_9', + 10: 'CRTC_HORZ_REPETITION_COUNT_10', + 11: 'CRTC_HORZ_REPETITION_COUNT_11', + 12: 'CRTC_HORZ_REPETITION_COUNT_12', + 13: 'CRTC_HORZ_REPETITION_COUNT_13', + 14: 'CRTC_HORZ_REPETITION_COUNT_14', + 15: 'CRTC_HORZ_REPETITION_COUNT_15', +} +CRTC_HORZ_REPETITION_COUNT_0 = 0 +CRTC_HORZ_REPETITION_COUNT_1 = 1 +CRTC_HORZ_REPETITION_COUNT_2 = 2 +CRTC_HORZ_REPETITION_COUNT_3 = 3 +CRTC_HORZ_REPETITION_COUNT_4 = 4 +CRTC_HORZ_REPETITION_COUNT_5 = 5 +CRTC_HORZ_REPETITION_COUNT_6 = 6 +CRTC_HORZ_REPETITION_COUNT_7 = 7 +CRTC_HORZ_REPETITION_COUNT_8 = 8 +CRTC_HORZ_REPETITION_COUNT_9 = 9 +CRTC_HORZ_REPETITION_COUNT_10 = 10 +CRTC_HORZ_REPETITION_COUNT_11 = 11 +CRTC_HORZ_REPETITION_COUNT_12 = 12 +CRTC_HORZ_REPETITION_COUNT_13 = 13 +CRTC_HORZ_REPETITION_COUNT_14 = 14 +CRTC_HORZ_REPETITION_COUNT_15 = 15 +CRTC_HORZ_REPETITION_COUNT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_DRR_MODE_DBUF_UPDATE_MODE' +CRTC_DRR_MODE_DBUF_UPDATE_MODE__enumvalues = { + 0: 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE', + 1: 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL', + 2: 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF', + 3: 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF', +} +CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE = 0 +CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL = 1 +CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF = 2 +CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF = 3 +CRTC_DRR_MODE_DBUF_UPDATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_PIXEL_ENCODING' +FMT_CONTROL_PIXEL_ENCODING__enumvalues = { + 0: 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', + 1: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', + 2: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', + 3: 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', +} +FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0 +FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 1 +FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 2 +FMT_CONTROL_PIXEL_ENCODING_RESERVED = 3 +FMT_CONTROL_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_SUBSAMPLING_MODE' +FMT_CONTROL_SUBSAMPLING_MODE__enumvalues = { + 0: 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', + 1: 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', + 2: 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', + 3: 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', +} +FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0 +FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 1 +FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 2 +FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 3 +FMT_CONTROL_SUBSAMPLING_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_SUBSAMPLING_ORDER' +FMT_CONTROL_SUBSAMPLING_ORDER__enumvalues = { + 0: 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', + 1: 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', +} +FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0 +FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 1 +FMT_CONTROL_SUBSAMPLING_ORDER = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS' +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS__enumvalues = { + 0: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', + 1: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', +} +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0 +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 1 +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE' +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', + 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', +} +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 1 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH' +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', + 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', + 2: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', +} +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 1 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 2 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH' +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', + 1: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', + 2: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', +} +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0 +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 1 +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 2 +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH' +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', + 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', + 2: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', +} +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 1 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 2 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL' +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', + 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', +} +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 1 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL' +FMT_BIT_DEPTH_CONTROL_25FRC_SEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', + 1: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', + 2: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', + 3: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', +} +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 1 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 2 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 3 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL' +FMT_BIT_DEPTH_CONTROL_50FRC_SEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', + 1: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', + 2: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', + 3: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', +} +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 1 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 2 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 3 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL' +FMT_BIT_DEPTH_CONTROL_75FRC_SEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', + 1: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', + 2: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', + 3: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', +} +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 1 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 2 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 3 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT' +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT__enumvalues = { + 0: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN', + 1: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN', +} +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN = 0 +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN = 1 +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0' +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0__enumvalues = { + 0: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', + 1: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', +} +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0 +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 1 +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CLAMP_CNTL_COLOR_FORMAT' +FMT_CLAMP_CNTL_COLOR_FORMAT__enumvalues = { + 0: 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', + 1: 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', + 2: 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', + 3: 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', + 4: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', + 5: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', + 6: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', + 7: 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', +} +FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0 +FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 1 +FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 2 +FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 3 +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 4 +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 5 +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 6 +FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 7 +FMT_CLAMP_CNTL_COLOR_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CRC_CNTL_CONT_EN' +FMT_CRC_CNTL_CONT_EN__enumvalues = { + 0: 'FMT_CRC_CNTL_CONT_EN_ONE_SHOT', + 1: 'FMT_CRC_CNTL_CONT_EN_CONT', +} +FMT_CRC_CNTL_CONT_EN_ONE_SHOT = 0 +FMT_CRC_CNTL_CONT_EN_CONT = 1 +FMT_CRC_CNTL_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CRC_CNTL_INCLUDE_OVERSCAN' +FMT_CRC_CNTL_INCLUDE_OVERSCAN__enumvalues = { + 0: 'FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE', + 1: 'FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE', +} +FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE = 0 +FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE = 1 +FMT_CRC_CNTL_INCLUDE_OVERSCAN = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CRC_CNTL_ONLY_BLANKB' +FMT_CRC_CNTL_ONLY_BLANKB__enumvalues = { + 0: 'FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD', + 1: 'FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK', +} +FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD = 0 +FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK = 1 +FMT_CRC_CNTL_ONLY_BLANKB = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CRC_CNTL_PSR_MODE_ENABLE' +FMT_CRC_CNTL_PSR_MODE_ENABLE__enumvalues = { + 0: 'FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL', + 1: 'FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC', +} +FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL = 0 +FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC = 1 +FMT_CRC_CNTL_PSR_MODE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CRC_CNTL_INTERLACE_MODE' +FMT_CRC_CNTL_INTERLACE_MODE__enumvalues = { + 0: 'FMT_CRC_CNTL_INTERLACE_MODE_TOP', + 1: 'FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM', + 2: 'FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM', + 3: 'FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH', +} +FMT_CRC_CNTL_INTERLACE_MODE_TOP = 0 +FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM = 1 +FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM = 2 +FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH = 3 +FMT_CRC_CNTL_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE' +FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE__enumvalues = { + 0: 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL', + 1: 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN', +} +FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL = 0 +FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN = 1 +FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT' +FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT__enumvalues = { + 0: 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN', + 1: 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD', +} +FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN = 0 +FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD = 1 +FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_DEBUG_CNTL_COLOR_SELECT' +FMT_DEBUG_CNTL_COLOR_SELECT__enumvalues = { + 0: 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', + 1: 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', + 2: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', + 3: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', +} +FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0 +FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 1 +FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 2 +FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 3 +FMT_DEBUG_CNTL_COLOR_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_SPATIAL_DITHER_MODE' +FMT_SPATIAL_DITHER_MODE__enumvalues = { + 0: 'FMT_SPATIAL_DITHER_MODE_0', + 1: 'FMT_SPATIAL_DITHER_MODE_1', + 2: 'FMT_SPATIAL_DITHER_MODE_2', + 3: 'FMT_SPATIAL_DITHER_MODE_3', +} +FMT_SPATIAL_DITHER_MODE_0 = 0 +FMT_SPATIAL_DITHER_MODE_1 = 1 +FMT_SPATIAL_DITHER_MODE_2 = 2 +FMT_SPATIAL_DITHER_MODE_3 = 3 +FMT_SPATIAL_DITHER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_STEREOSYNC_OVR_POL' +FMT_STEREOSYNC_OVR_POL__enumvalues = { + 0: 'FMT_STEREOSYNC_OVR_POL_INVERTED', + 1: 'FMT_STEREOSYNC_OVR_POL_NOT_INVERTED', +} +FMT_STEREOSYNC_OVR_POL_INVERTED = 0 +FMT_STEREOSYNC_OVR_POL_NOT_INVERTED = 1 +FMT_STEREOSYNC_OVR_POL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_DYNAMIC_EXP_MODE' +FMT_DYNAMIC_EXP_MODE__enumvalues = { + 0: 'FMT_DYNAMIC_EXP_MODE_10to12', + 1: 'FMT_DYNAMIC_EXP_MODE_8to12', +} +FMT_DYNAMIC_EXP_MODE_10to12 = 0 +FMT_DYNAMIC_EXP_MODE_8to12 = 1 +FMT_DYNAMIC_EXP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HPD_INT_CONTROL_ACK' +HPD_INT_CONTROL_ACK__enumvalues = { + 0: 'HPD_INT_CONTROL_ACK_0', + 1: 'HPD_INT_CONTROL_ACK_1', +} +HPD_INT_CONTROL_ACK_0 = 0 +HPD_INT_CONTROL_ACK_1 = 1 +HPD_INT_CONTROL_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'HPD_INT_CONTROL_POLARITY' +HPD_INT_CONTROL_POLARITY__enumvalues = { + 0: 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', + 1: 'HPD_INT_CONTROL_GEN_INT_ON_CON', +} +HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0 +HPD_INT_CONTROL_GEN_INT_ON_CON = 1 +HPD_INT_CONTROL_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'HPD_INT_CONTROL_RX_INT_ACK' +HPD_INT_CONTROL_RX_INT_ACK__enumvalues = { + 0: 'HPD_INT_CONTROL_RX_INT_ACK_0', + 1: 'HPD_INT_CONTROL_RX_INT_ACK_1', +} +HPD_INT_CONTROL_RX_INT_ACK_0 = 0 +HPD_INT_CONTROL_RX_INT_ACK_1 = 1 +HPD_INT_CONTROL_RX_INT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DATA_FORMAT_PIXEL_DEPTH' +LB_DATA_FORMAT_PIXEL_DEPTH__enumvalues = { + 0: 'LB_DATA_FORMAT_PIXEL_DEPTH_30BPP', + 1: 'LB_DATA_FORMAT_PIXEL_DEPTH_24BPP', + 2: 'LB_DATA_FORMAT_PIXEL_DEPTH_18BPP', + 3: 'LB_DATA_FORMAT_PIXEL_DEPTH_36BPP', +} +LB_DATA_FORMAT_PIXEL_DEPTH_30BPP = 0 +LB_DATA_FORMAT_PIXEL_DEPTH_24BPP = 1 +LB_DATA_FORMAT_PIXEL_DEPTH_18BPP = 2 +LB_DATA_FORMAT_PIXEL_DEPTH_36BPP = 3 +LB_DATA_FORMAT_PIXEL_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE' +LB_DATA_FORMAT_PIXEL_EXPAN_MODE__enumvalues = { + 0: 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION', + 1: 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION', +} +LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION = 0 +LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION = 1 +LB_DATA_FORMAT_PIXEL_EXPAN_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE' +LB_DATA_FORMAT_PIXEL_REDUCE_MODE__enumvalues = { + 0: 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION', + 1: 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING', +} +LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION = 0 +LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING = 1 +LB_DATA_FORMAT_PIXEL_REDUCE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH' +LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH__enumvalues = { + 0: 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP', + 1: 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP', +} +LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP = 0 +LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP = 1 +LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DATA_FORMAT_INTERLEAVE_EN' +LB_DATA_FORMAT_INTERLEAVE_EN__enumvalues = { + 0: 'LB_DATA_FORMAT_INTERLEAVE_DISABLE', + 1: 'LB_DATA_FORMAT_INTERLEAVE_ENABLE', +} +LB_DATA_FORMAT_INTERLEAVE_DISABLE = 0 +LB_DATA_FORMAT_INTERLEAVE_ENABLE = 1 +LB_DATA_FORMAT_INTERLEAVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DATA_FORMAT_REQUEST_MODE' +LB_DATA_FORMAT_REQUEST_MODE__enumvalues = { + 0: 'LB_DATA_FORMAT_REQUEST_MODE_NORMAL', + 1: 'LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE', +} +LB_DATA_FORMAT_REQUEST_MODE_NORMAL = 0 +LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE = 1 +LB_DATA_FORMAT_REQUEST_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DATA_FORMAT_ALPHA_EN' +LB_DATA_FORMAT_ALPHA_EN__enumvalues = { + 0: 'LB_DATA_FORMAT_ALPHA_DISABLE', + 1: 'LB_DATA_FORMAT_ALPHA_ENABLE', +} +LB_DATA_FORMAT_ALPHA_DISABLE = 0 +LB_DATA_FORMAT_ALPHA_ENABLE = 1 +LB_DATA_FORMAT_ALPHA_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LB_VLINE_START_END_VLINE_INV' +LB_VLINE_START_END_VLINE_INV__enumvalues = { + 0: 'LB_VLINE_START_END_VLINE_NORMAL', + 1: 'LB_VLINE_START_END_VLINE_INVERSE', +} +LB_VLINE_START_END_VLINE_NORMAL = 0 +LB_VLINE_START_END_VLINE_INVERSE = 1 +LB_VLINE_START_END_VLINE_INV = ctypes.c_uint32 # enum + +# values for enumeration 'LB_VLINE2_START_END_VLINE2_INV' +LB_VLINE2_START_END_VLINE2_INV__enumvalues = { + 0: 'LB_VLINE2_START_END_VLINE2_NORMAL', + 1: 'LB_VLINE2_START_END_VLINE2_INVERSE', +} +LB_VLINE2_START_END_VLINE2_NORMAL = 0 +LB_VLINE2_START_END_VLINE2_INVERSE = 1 +LB_VLINE2_START_END_VLINE2_INV = ctypes.c_uint32 # enum + +# values for enumeration 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK' +LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK__enumvalues = { + 0: 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE', + 1: 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE', +} +LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE = 0 +LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE = 1 +LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK' +LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK__enumvalues = { + 0: 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE', + 1: 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE', +} +LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE = 0 +LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE = 1 +LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK' +LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK__enumvalues = { + 0: 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE', + 1: 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE', +} +LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE = 0 +LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE = 1 +LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'LB_VLINE_STATUS_VLINE_ACK' +LB_VLINE_STATUS_VLINE_ACK__enumvalues = { + 0: 'LB_VLINE_STATUS_VLINE_NORMAL', + 1: 'LB_VLINE_STATUS_VLINE_CLEAR', +} +LB_VLINE_STATUS_VLINE_NORMAL = 0 +LB_VLINE_STATUS_VLINE_CLEAR = 1 +LB_VLINE_STATUS_VLINE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE' +LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE__enumvalues = { + 0: 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED', + 1: 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED', +} +LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED = 0 +LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED = 1 +LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_VLINE2_STATUS_VLINE2_ACK' +LB_VLINE2_STATUS_VLINE2_ACK__enumvalues = { + 0: 'LB_VLINE2_STATUS_VLINE2_NORMAL', + 1: 'LB_VLINE2_STATUS_VLINE2_CLEAR', +} +LB_VLINE2_STATUS_VLINE2_NORMAL = 0 +LB_VLINE2_STATUS_VLINE2_CLEAR = 1 +LB_VLINE2_STATUS_VLINE2_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE' +LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE__enumvalues = { + 0: 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED', + 1: 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED', +} +LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED = 0 +LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED = 1 +LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_VBLANK_STATUS_VBLANK_ACK' +LB_VBLANK_STATUS_VBLANK_ACK__enumvalues = { + 0: 'LB_VBLANK_STATUS_VBLANK_NORMAL', + 1: 'LB_VBLANK_STATUS_VBLANK_CLEAR', +} +LB_VBLANK_STATUS_VBLANK_NORMAL = 0 +LB_VBLANK_STATUS_VBLANK_CLEAR = 1 +LB_VBLANK_STATUS_VBLANK_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE' +LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE__enumvalues = { + 0: 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED', + 1: 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED', +} +LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED = 0 +LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED = 1 +LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL' +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL__enumvalues = { + 0: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE', + 1: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK', + 2: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET', + 3: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET', +} +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE = 0 +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK = 1 +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET = 2 +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET = 3 +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2' +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2__enumvalues = { + 0: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK', + 1: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC', +} +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK = 0 +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC = 1 +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 = ctypes.c_uint32 # enum + +# values for enumeration 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION' +LB_SYNC_RESET_SEL_LB_SYNC_DURATION__enumvalues = { + 0: 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS', + 1: 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS', + 2: 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS', + 3: 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS', +} +LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS = 0 +LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS = 1 +LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 2 +LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS = 3 +LB_SYNC_RESET_SEL_LB_SYNC_DURATION = ctypes.c_uint32 # enum + +# values for enumeration 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN' +LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN__enumvalues = { + 0: 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE', + 1: 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE', +} +LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE = 0 +LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE = 1 +LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN' +LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN__enumvalues = { + 0: 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE', + 1: 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE', +} +LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE = 0 +LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE = 1 +LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK' +LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK__enumvalues = { + 0: 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL', + 1: 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET', +} +LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL = 0 +LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET = 1 +LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK' +LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK__enumvalues = { + 0: 'LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL', + 1: 'LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET', +} +LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL = 0 +LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET = 1 +LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE' +LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE__enumvalues = { + 2: 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP', + 3: 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP', +} +LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 2 +LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP = 3 +LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET' +LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET__enumvalues = { + 0: 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL', + 1: 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE', +} +LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL = 0 +LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE = 1 +LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK' +LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK__enumvalues = { + 0: 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0', + 1: 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1', +} +LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0 = 0 +LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1 = 1 +LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE' +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE__enumvalues = { + 0: 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT', + 1: 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG', + 2: 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE', +} +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT = 0 +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG = 1 +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE = 2 +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE' +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE__enumvalues = { + 0: 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE', + 1: 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN', +} +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE = 0 +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN = 1 +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE' +LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE__enumvalues = { + 1: 'ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER', + 2: 'ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE', +} +ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER = 1 +ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE = 2 +LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL' +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL__enumvalues = { + 0: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0', + 1: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1', +} +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0 = 0 +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1 = 1 +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE' +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__enumvalues = { + 0: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE', + 1: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE', +} +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE = 0 +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE = 1 +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO' +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__enumvalues = { + 0: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO', + 1: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO', +} +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO = 0 +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO = 1 +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO = ctypes.c_uint32 # enum + +# values for enumeration 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN' +LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0', + 1: 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1', +} +LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0 = 0 +LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1 = 1 +LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_KEEPOUT_MODE' +HDMI_KEEPOUT_MODE__enumvalues = { + 0: 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', + 1: 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', +} +HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0 +HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 1 +HDMI_KEEPOUT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_DATA_SCRAMBLE_EN' +HDMI_DATA_SCRAMBLE_EN__enumvalues = { + 0: 'HDMI_DATA_SCRAMBLE_DISABLE', + 1: 'HDMI_DATA_SCRAMBLE_ENABLE', +} +HDMI_DATA_SCRAMBLE_DISABLE = 0 +HDMI_DATA_SCRAMBLE_ENABLE = 1 +HDMI_DATA_SCRAMBLE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_CLOCK_CHANNEL_RATE' +HDMI_CLOCK_CHANNEL_RATE__enumvalues = { + 0: 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', + 1: 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', +} +HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0 +HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 1 +HDMI_CLOCK_CHANNEL_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_NO_EXTRA_NULL_PACKET_FILLED' +HDMI_NO_EXTRA_NULL_PACKET_FILLED__enumvalues = { + 0: 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', + 1: 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', +} +HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0 +HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 1 +HDMI_NO_EXTRA_NULL_PACKET_FILLED = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_PACKET_GEN_VERSION' +HDMI_PACKET_GEN_VERSION__enumvalues = { + 0: 'HDMI_PACKET_GEN_VERSION_OLD', + 1: 'HDMI_PACKET_GEN_VERSION_NEW', +} +HDMI_PACKET_GEN_VERSION_OLD = 0 +HDMI_PACKET_GEN_VERSION_NEW = 1 +HDMI_PACKET_GEN_VERSION = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ERROR_ACK' +HDMI_ERROR_ACK__enumvalues = { + 0: 'HDMI_ERROR_ACK_INT', + 1: 'HDMI_ERROR_NOT_ACK', +} +HDMI_ERROR_ACK_INT = 0 +HDMI_ERROR_NOT_ACK = 1 +HDMI_ERROR_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ERROR_MASK' +HDMI_ERROR_MASK__enumvalues = { + 0: 'HDMI_ERROR_MASK_INT', + 1: 'HDMI_ERROR_NOT_MASK', +} +HDMI_ERROR_MASK_INT = 0 +HDMI_ERROR_NOT_MASK = 1 +HDMI_ERROR_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_DEEP_COLOR_DEPTH' +HDMI_DEEP_COLOR_DEPTH__enumvalues = { + 0: 'HDMI_DEEP_COLOR_DEPTH_24BPP', + 1: 'HDMI_DEEP_COLOR_DEPTH_30BPP', + 2: 'HDMI_DEEP_COLOR_DEPTH_36BPP', + 3: 'HDMI_DEEP_COLOR_DEPTH_RESERVED', +} +HDMI_DEEP_COLOR_DEPTH_24BPP = 0 +HDMI_DEEP_COLOR_DEPTH_30BPP = 1 +HDMI_DEEP_COLOR_DEPTH_36BPP = 2 +HDMI_DEEP_COLOR_DEPTH_RESERVED = 3 +HDMI_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_DELAY_EN' +HDMI_AUDIO_DELAY_EN__enumvalues = { + 0: 'HDMI_AUDIO_DELAY_DISABLE', + 1: 'HDMI_AUDIO_DELAY_58CLK', + 2: 'HDMI_AUDIO_DELAY_56CLK', + 3: 'HDMI_AUDIO_DELAY_RESERVED', +} +HDMI_AUDIO_DELAY_DISABLE = 0 +HDMI_AUDIO_DELAY_58CLK = 1 +HDMI_AUDIO_DELAY_56CLK = 2 +HDMI_AUDIO_DELAY_RESERVED = 3 +HDMI_AUDIO_DELAY_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_SEND_MAX_PACKETS' +HDMI_AUDIO_SEND_MAX_PACKETS__enumvalues = { + 0: 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', + 1: 'HDMI_SEND_MAX_AUDIO_PACKETS', +} +HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0 +HDMI_SEND_MAX_AUDIO_PACKETS = 1 +HDMI_AUDIO_SEND_MAX_PACKETS = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_SEND' +HDMI_ACR_SEND__enumvalues = { + 0: 'HDMI_ACR_NOT_SEND', + 1: 'HDMI_ACR_PKT_SEND', +} +HDMI_ACR_NOT_SEND = 0 +HDMI_ACR_PKT_SEND = 1 +HDMI_ACR_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_CONT' +HDMI_ACR_CONT__enumvalues = { + 0: 'HDMI_ACR_CONT_DISABLE', + 1: 'HDMI_ACR_CONT_ENABLE', +} +HDMI_ACR_CONT_DISABLE = 0 +HDMI_ACR_CONT_ENABLE = 1 +HDMI_ACR_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_SELECT' +HDMI_ACR_SELECT__enumvalues = { + 0: 'HDMI_ACR_SELECT_HW', + 1: 'HDMI_ACR_SELECT_32K', + 2: 'HDMI_ACR_SELECT_44K', + 3: 'HDMI_ACR_SELECT_48K', +} +HDMI_ACR_SELECT_HW = 0 +HDMI_ACR_SELECT_32K = 1 +HDMI_ACR_SELECT_44K = 2 +HDMI_ACR_SELECT_48K = 3 +HDMI_ACR_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_SOURCE' +HDMI_ACR_SOURCE__enumvalues = { + 0: 'HDMI_ACR_SOURCE_HW', + 1: 'HDMI_ACR_SOURCE_SW', +} +HDMI_ACR_SOURCE_HW = 0 +HDMI_ACR_SOURCE_SW = 1 +HDMI_ACR_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_N_MULTIPLE' +HDMI_ACR_N_MULTIPLE__enumvalues = { + 0: 'HDMI_ACR_0_MULTIPLE_RESERVED', + 1: 'HDMI_ACR_1_MULTIPLE', + 2: 'HDMI_ACR_2_MULTIPLE', + 3: 'HDMI_ACR_3_MULTIPLE_RESERVED', + 4: 'HDMI_ACR_4_MULTIPLE', + 5: 'HDMI_ACR_5_MULTIPLE_RESERVED', + 6: 'HDMI_ACR_6_MULTIPLE_RESERVED', + 7: 'HDMI_ACR_7_MULTIPLE_RESERVED', +} +HDMI_ACR_0_MULTIPLE_RESERVED = 0 +HDMI_ACR_1_MULTIPLE = 1 +HDMI_ACR_2_MULTIPLE = 2 +HDMI_ACR_3_MULTIPLE_RESERVED = 3 +HDMI_ACR_4_MULTIPLE = 4 +HDMI_ACR_5_MULTIPLE_RESERVED = 5 +HDMI_ACR_6_MULTIPLE_RESERVED = 6 +HDMI_ACR_7_MULTIPLE_RESERVED = 7 +HDMI_ACR_N_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_AUDIO_PRIORITY' +HDMI_ACR_AUDIO_PRIORITY__enumvalues = { + 0: 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', + 1: 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', +} +HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0 +HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1 +HDMI_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_NULL_SEND' +HDMI_NULL_SEND__enumvalues = { + 0: 'HDMI_NULL_NOT_SEND', + 1: 'HDMI_NULL_PKT_SEND', +} +HDMI_NULL_NOT_SEND = 0 +HDMI_NULL_PKT_SEND = 1 +HDMI_NULL_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_SEND' +HDMI_GC_SEND__enumvalues = { + 0: 'HDMI_GC_NOT_SEND', + 1: 'HDMI_GC_PKT_SEND', +} +HDMI_GC_NOT_SEND = 0 +HDMI_GC_PKT_SEND = 1 +HDMI_GC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_CONT' +HDMI_GC_CONT__enumvalues = { + 0: 'HDMI_GC_CONT_DISABLE', + 1: 'HDMI_GC_CONT_ENABLE', +} +HDMI_GC_CONT_DISABLE = 0 +HDMI_GC_CONT_ENABLE = 1 +HDMI_GC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ISRC_SEND' +HDMI_ISRC_SEND__enumvalues = { + 0: 'HDMI_ISRC_NOT_SEND', + 1: 'HDMI_ISRC_PKT_SEND', +} +HDMI_ISRC_NOT_SEND = 0 +HDMI_ISRC_PKT_SEND = 1 +HDMI_ISRC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ISRC_CONT' +HDMI_ISRC_CONT__enumvalues = { + 0: 'HDMI_ISRC_CONT_DISABLE', + 1: 'HDMI_ISRC_CONT_ENABLE', +} +HDMI_ISRC_CONT_DISABLE = 0 +HDMI_ISRC_CONT_ENABLE = 1 +HDMI_ISRC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AVI_INFO_SEND' +HDMI_AVI_INFO_SEND__enumvalues = { + 0: 'HDMI_AVI_INFO_NOT_SEND', + 1: 'HDMI_AVI_INFO_PKT_SEND', +} +HDMI_AVI_INFO_NOT_SEND = 0 +HDMI_AVI_INFO_PKT_SEND = 1 +HDMI_AVI_INFO_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AVI_INFO_CONT' +HDMI_AVI_INFO_CONT__enumvalues = { + 0: 'HDMI_AVI_INFO_CONT_DISABLE', + 1: 'HDMI_AVI_INFO_CONT_ENABLE', +} +HDMI_AVI_INFO_CONT_DISABLE = 0 +HDMI_AVI_INFO_CONT_ENABLE = 1 +HDMI_AVI_INFO_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_INFO_SEND' +HDMI_AUDIO_INFO_SEND__enumvalues = { + 0: 'HDMI_AUDIO_INFO_NOT_SEND', + 1: 'HDMI_AUDIO_INFO_PKT_SEND', +} +HDMI_AUDIO_INFO_NOT_SEND = 0 +HDMI_AUDIO_INFO_PKT_SEND = 1 +HDMI_AUDIO_INFO_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_INFO_CONT' +HDMI_AUDIO_INFO_CONT__enumvalues = { + 0: 'HDMI_AUDIO_INFO_CONT_DISABLE', + 1: 'HDMI_AUDIO_INFO_CONT_ENABLE', +} +HDMI_AUDIO_INFO_CONT_DISABLE = 0 +HDMI_AUDIO_INFO_CONT_ENABLE = 1 +HDMI_AUDIO_INFO_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_MPEG_INFO_SEND' +HDMI_MPEG_INFO_SEND__enumvalues = { + 0: 'HDMI_MPEG_INFO_NOT_SEND', + 1: 'HDMI_MPEG_INFO_PKT_SEND', +} +HDMI_MPEG_INFO_NOT_SEND = 0 +HDMI_MPEG_INFO_PKT_SEND = 1 +HDMI_MPEG_INFO_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_MPEG_INFO_CONT' +HDMI_MPEG_INFO_CONT__enumvalues = { + 0: 'HDMI_MPEG_INFO_CONT_DISABLE', + 1: 'HDMI_MPEG_INFO_CONT_ENABLE', +} +HDMI_MPEG_INFO_CONT_DISABLE = 0 +HDMI_MPEG_INFO_CONT_ENABLE = 1 +HDMI_MPEG_INFO_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC0_SEND' +HDMI_GENERIC0_SEND__enumvalues = { + 0: 'HDMI_GENERIC0_NOT_SEND', + 1: 'HDMI_GENERIC0_PKT_SEND', +} +HDMI_GENERIC0_NOT_SEND = 0 +HDMI_GENERIC0_PKT_SEND = 1 +HDMI_GENERIC0_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC0_CONT' +HDMI_GENERIC0_CONT__enumvalues = { + 0: 'HDMI_GENERIC0_CONT_DISABLE', + 1: 'HDMI_GENERIC0_CONT_ENABLE', +} +HDMI_GENERIC0_CONT_DISABLE = 0 +HDMI_GENERIC0_CONT_ENABLE = 1 +HDMI_GENERIC0_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC1_SEND' +HDMI_GENERIC1_SEND__enumvalues = { + 0: 'HDMI_GENERIC1_NOT_SEND', + 1: 'HDMI_GENERIC1_PKT_SEND', +} +HDMI_GENERIC1_NOT_SEND = 0 +HDMI_GENERIC1_PKT_SEND = 1 +HDMI_GENERIC1_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC1_CONT' +HDMI_GENERIC1_CONT__enumvalues = { + 0: 'HDMI_GENERIC1_CONT_DISABLE', + 1: 'HDMI_GENERIC1_CONT_ENABLE', +} +HDMI_GENERIC1_CONT_DISABLE = 0 +HDMI_GENERIC1_CONT_ENABLE = 1 +HDMI_GENERIC1_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_AVMUTE_CONT' +HDMI_GC_AVMUTE_CONT__enumvalues = { + 0: 'HDMI_GC_AVMUTE_CONT_DISABLE', + 1: 'HDMI_GC_AVMUTE_CONT_ENABLE', +} +HDMI_GC_AVMUTE_CONT_DISABLE = 0 +HDMI_GC_AVMUTE_CONT_ENABLE = 1 +HDMI_GC_AVMUTE_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_PACKING_PHASE_OVERRIDE' +HDMI_PACKING_PHASE_OVERRIDE__enumvalues = { + 0: 'HDMI_PACKING_PHASE_SET_BY_HW', + 1: 'HDMI_PACKING_PHASE_SET_BY_SW', +} +HDMI_PACKING_PHASE_SET_BY_HW = 0 +HDMI_PACKING_PHASE_SET_BY_SW = 1 +HDMI_PACKING_PHASE_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC2_SEND' +HDMI_GENERIC2_SEND__enumvalues = { + 0: 'HDMI_GENERIC2_NOT_SEND', + 1: 'HDMI_GENERIC2_PKT_SEND', +} +HDMI_GENERIC2_NOT_SEND = 0 +HDMI_GENERIC2_PKT_SEND = 1 +HDMI_GENERIC2_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC2_CONT' +HDMI_GENERIC2_CONT__enumvalues = { + 0: 'HDMI_GENERIC2_CONT_DISABLE', + 1: 'HDMI_GENERIC2_CONT_ENABLE', +} +HDMI_GENERIC2_CONT_DISABLE = 0 +HDMI_GENERIC2_CONT_ENABLE = 1 +HDMI_GENERIC2_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC3_SEND' +HDMI_GENERIC3_SEND__enumvalues = { + 0: 'HDMI_GENERIC3_NOT_SEND', + 1: 'HDMI_GENERIC3_PKT_SEND', +} +HDMI_GENERIC3_NOT_SEND = 0 +HDMI_GENERIC3_PKT_SEND = 1 +HDMI_GENERIC3_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC3_CONT' +HDMI_GENERIC3_CONT__enumvalues = { + 0: 'HDMI_GENERIC3_CONT_DISABLE', + 1: 'HDMI_GENERIC3_CONT_ENABLE', +} +HDMI_GENERIC3_CONT_DISABLE = 0 +HDMI_GENERIC3_CONT_ENABLE = 1 +HDMI_GENERIC3_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_PIXEL_ENCODING' +TMDS_PIXEL_ENCODING__enumvalues = { + 0: 'TMDS_PIXEL_ENCODING_444_OR_420', + 1: 'TMDS_PIXEL_ENCODING_422', +} +TMDS_PIXEL_ENCODING_444_OR_420 = 0 +TMDS_PIXEL_ENCODING_422 = 1 +TMDS_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_COLOR_FORMAT' +TMDS_COLOR_FORMAT__enumvalues = { + 0: 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', + 1: 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', + 2: 'TMDS_COLOR_FORMAT_DUAL30BPP', + 3: 'TMDS_COLOR_FORMAT_RESERVED', +} +TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0 +TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 1 +TMDS_COLOR_FORMAT_DUAL30BPP = 2 +TMDS_COLOR_FORMAT_RESERVED = 3 +TMDS_COLOR_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_STEREOSYNC_CTL_SEL_REG' +TMDS_STEREOSYNC_CTL_SEL_REG__enumvalues = { + 0: 'TMDS_STEREOSYNC_CTL0', + 1: 'TMDS_STEREOSYNC_CTL1', + 2: 'TMDS_STEREOSYNC_CTL2', + 3: 'TMDS_STEREOSYNC_CTL3', +} +TMDS_STEREOSYNC_CTL0 = 0 +TMDS_STEREOSYNC_CTL1 = 1 +TMDS_STEREOSYNC_CTL2 = 2 +TMDS_STEREOSYNC_CTL3 = 3 +TMDS_STEREOSYNC_CTL_SEL_REG = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_DATA_SEL' +TMDS_CTL0_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL0_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL0_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL0_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL0_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', + 7: 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', +} +TMDS_CTL0_DATA_SEL0_RESERVED = 0 +TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL0_DATA_SEL2_VSYNC = 2 +TMDS_CTL0_DATA_SEL3_RESERVED = 3 +TMDS_CTL0_DATA_SEL4_HSYNC = 4 +TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 6 +TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 7 +TMDS_CTL0_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_DATA_INVERT' +TMDS_CTL0_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL0_DATA_NORMAL', + 1: 'TMDS_CTL0_DATA_INVERT_EN', +} +TMDS_CTL0_DATA_NORMAL = 0 +TMDS_CTL0_DATA_INVERT_EN = 1 +TMDS_CTL0_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_DATA_MODULATION' +TMDS_CTL0_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL0_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL0_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL0_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL0_DATA_MODULATION_BIT2', +} +TMDS_CTL0_DATA_MODULATION_DISABLE = 0 +TMDS_CTL0_DATA_MODULATION_BIT0 = 1 +TMDS_CTL0_DATA_MODULATION_BIT1 = 2 +TMDS_CTL0_DATA_MODULATION_BIT2 = 3 +TMDS_CTL0_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_PATTERN_OUT_EN' +TMDS_CTL0_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL0_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL0_PATTERN_OUT_ENABLE', +} +TMDS_CTL0_PATTERN_OUT_DISABLE = 0 +TMDS_CTL0_PATTERN_OUT_ENABLE = 1 +TMDS_CTL0_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_DATA_SEL' +TMDS_CTL1_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL1_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL1_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL1_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL1_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', + 7: 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', +} +TMDS_CTL1_DATA_SEL0_RESERVED = 0 +TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL1_DATA_SEL2_VSYNC = 2 +TMDS_CTL1_DATA_SEL3_RESERVED = 3 +TMDS_CTL1_DATA_SEL4_HSYNC = 4 +TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL1_DATA_SEL8_BLANK_TIME = 6 +TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 7 +TMDS_CTL1_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_DATA_INVERT' +TMDS_CTL1_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL1_DATA_NORMAL', + 1: 'TMDS_CTL1_DATA_INVERT_EN', +} +TMDS_CTL1_DATA_NORMAL = 0 +TMDS_CTL1_DATA_INVERT_EN = 1 +TMDS_CTL1_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_DATA_MODULATION' +TMDS_CTL1_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL1_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL1_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL1_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL1_DATA_MODULATION_BIT2', +} +TMDS_CTL1_DATA_MODULATION_DISABLE = 0 +TMDS_CTL1_DATA_MODULATION_BIT0 = 1 +TMDS_CTL1_DATA_MODULATION_BIT1 = 2 +TMDS_CTL1_DATA_MODULATION_BIT2 = 3 +TMDS_CTL1_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_PATTERN_OUT_EN' +TMDS_CTL1_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL1_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL1_PATTERN_OUT_ENABLE', +} +TMDS_CTL1_PATTERN_OUT_DISABLE = 0 +TMDS_CTL1_PATTERN_OUT_ENABLE = 1 +TMDS_CTL1_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_DATA_SEL' +TMDS_CTL2_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL2_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL2_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL2_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL2_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', + 7: 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', +} +TMDS_CTL2_DATA_SEL0_RESERVED = 0 +TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL2_DATA_SEL2_VSYNC = 2 +TMDS_CTL2_DATA_SEL3_RESERVED = 3 +TMDS_CTL2_DATA_SEL4_HSYNC = 4 +TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL2_DATA_SEL8_BLANK_TIME = 6 +TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 7 +TMDS_CTL2_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_DATA_INVERT' +TMDS_CTL2_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL2_DATA_NORMAL', + 1: 'TMDS_CTL2_DATA_INVERT_EN', +} +TMDS_CTL2_DATA_NORMAL = 0 +TMDS_CTL2_DATA_INVERT_EN = 1 +TMDS_CTL2_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_DATA_MODULATION' +TMDS_CTL2_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL2_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL2_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL2_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL2_DATA_MODULATION_BIT2', +} +TMDS_CTL2_DATA_MODULATION_DISABLE = 0 +TMDS_CTL2_DATA_MODULATION_BIT0 = 1 +TMDS_CTL2_DATA_MODULATION_BIT1 = 2 +TMDS_CTL2_DATA_MODULATION_BIT2 = 3 +TMDS_CTL2_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_PATTERN_OUT_EN' +TMDS_CTL2_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL2_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL2_PATTERN_OUT_ENABLE', +} +TMDS_CTL2_PATTERN_OUT_DISABLE = 0 +TMDS_CTL2_PATTERN_OUT_ENABLE = 1 +TMDS_CTL2_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_DATA_INVERT' +TMDS_CTL3_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL3_DATA_NORMAL', + 1: 'TMDS_CTL3_DATA_INVERT_EN', +} +TMDS_CTL3_DATA_NORMAL = 0 +TMDS_CTL3_DATA_INVERT_EN = 1 +TMDS_CTL3_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_DATA_MODULATION' +TMDS_CTL3_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL3_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL3_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL3_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL3_DATA_MODULATION_BIT2', +} +TMDS_CTL3_DATA_MODULATION_DISABLE = 0 +TMDS_CTL3_DATA_MODULATION_BIT0 = 1 +TMDS_CTL3_DATA_MODULATION_BIT1 = 2 +TMDS_CTL3_DATA_MODULATION_BIT2 = 3 +TMDS_CTL3_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_PATTERN_OUT_EN' +TMDS_CTL3_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL3_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL3_PATTERN_OUT_ENABLE', +} +TMDS_CTL3_PATTERN_OUT_DISABLE = 0 +TMDS_CTL3_PATTERN_OUT_ENABLE = 1 +TMDS_CTL3_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_DATA_SEL' +TMDS_CTL3_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL3_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL3_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL3_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL3_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', + 7: 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', +} +TMDS_CTL3_DATA_SEL0_RESERVED = 0 +TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL3_DATA_SEL2_VSYNC = 2 +TMDS_CTL3_DATA_SEL3_RESERVED = 3 +TMDS_CTL3_DATA_SEL4_HSYNC = 4 +TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL3_DATA_SEL8_BLANK_TIME = 6 +TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 7 +TMDS_CTL3_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FE_CNTL_SOURCE_SELECT' +DIG_FE_CNTL_SOURCE_SELECT__enumvalues = { + 0: 'DIG_FE_SOURCE_FROM_FMT0', + 1: 'DIG_FE_SOURCE_FROM_FMT1', + 2: 'DIG_FE_SOURCE_FROM_FMT2', + 3: 'DIG_FE_SOURCE_FROM_FMT3', + 4: 'DIG_FE_SOURCE_FROM_FMT4', + 5: 'DIG_FE_SOURCE_FROM_FMT5', +} +DIG_FE_SOURCE_FROM_FMT0 = 0 +DIG_FE_SOURCE_FROM_FMT1 = 1 +DIG_FE_SOURCE_FROM_FMT2 = 2 +DIG_FE_SOURCE_FROM_FMT3 = 3 +DIG_FE_SOURCE_FROM_FMT4 = 4 +DIG_FE_SOURCE_FROM_FMT5 = 5 +DIG_FE_CNTL_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FE_CNTL_STEREOSYNC_SELECT' +DIG_FE_CNTL_STEREOSYNC_SELECT__enumvalues = { + 0: 'DIG_FE_STEREOSYNC_FROM_FMT0', + 1: 'DIG_FE_STEREOSYNC_FROM_FMT1', + 2: 'DIG_FE_STEREOSYNC_FROM_FMT2', + 3: 'DIG_FE_STEREOSYNC_FROM_FMT3', + 4: 'DIG_FE_STEREOSYNC_FROM_FMT4', + 5: 'DIG_FE_STEREOSYNC_FROM_FMT5', +} +DIG_FE_STEREOSYNC_FROM_FMT0 = 0 +DIG_FE_STEREOSYNC_FROM_FMT1 = 1 +DIG_FE_STEREOSYNC_FROM_FMT2 = 2 +DIG_FE_STEREOSYNC_FROM_FMT3 = 3 +DIG_FE_STEREOSYNC_FROM_FMT4 = 4 +DIG_FE_STEREOSYNC_FROM_FMT5 = 5 +DIG_FE_CNTL_STEREOSYNC_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_READ_CLOCK_SRC' +DIG_FIFO_READ_CLOCK_SRC__enumvalues = { + 0: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', + 1: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', +} +DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0 +DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 1 +DIG_FIFO_READ_CLOCK_SRC = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_OUTPUT_CRC_CNTL_LINK_SEL' +DIG_OUTPUT_CRC_CNTL_LINK_SEL__enumvalues = { + 0: 'DIG_OUTPUT_CRC_ON_LINK0', + 1: 'DIG_OUTPUT_CRC_ON_LINK1', +} +DIG_OUTPUT_CRC_ON_LINK0 = 0 +DIG_OUTPUT_CRC_ON_LINK1 = 1 +DIG_OUTPUT_CRC_CNTL_LINK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_OUTPUT_CRC_DATA_SEL' +DIG_OUTPUT_CRC_DATA_SEL__enumvalues = { + 0: 'DIG_OUTPUT_CRC_FOR_FULLFRAME', + 1: 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', + 2: 'DIG_OUTPUT_CRC_FOR_VBI', + 3: 'DIG_OUTPUT_CRC_FOR_AUDIO', +} +DIG_OUTPUT_CRC_FOR_FULLFRAME = 0 +DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 1 +DIG_OUTPUT_CRC_FOR_VBI = 2 +DIG_OUTPUT_CRC_FOR_AUDIO = 3 +DIG_OUTPUT_CRC_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN' +DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN__enumvalues = { + 0: 'DIG_IN_NORMAL_OPERATION', + 1: 'DIG_IN_DEBUG_MODE', +} +DIG_IN_NORMAL_OPERATION = 0 +DIG_IN_DEBUG_MODE = 1 +DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL' +DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL__enumvalues = { + 0: 'DIG_10BIT_TEST_PATTERN', + 1: 'DIG_ALTERNATING_TEST_PATTERN', +} +DIG_10BIT_TEST_PATTERN = 0 +DIG_ALTERNATING_TEST_PATTERN = 1 +DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN' +DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN__enumvalues = { + 0: 'DIG_TEST_PATTERN_NORMAL', + 1: 'DIG_TEST_PATTERN_RANDOM', +} +DIG_TEST_PATTERN_NORMAL = 0 +DIG_TEST_PATTERN_RANDOM = 1 +DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET' +DIG_TEST_PATTERN_RANDOM_PATTERN_RESET__enumvalues = { + 0: 'DIG_RANDOM_PATTERN_ENABLED', + 1: 'DIG_RANDOM_PATTERN_RESETED', +} +DIG_RANDOM_PATTERN_ENABLED = 0 +DIG_RANDOM_PATTERN_RESETED = 1 +DIG_TEST_PATTERN_RANDOM_PATTERN_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN' +DIG_TEST_PATTERN_EXTERNAL_RESET_EN__enumvalues = { + 0: 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', + 1: 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', +} +DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0 +DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 1 +DIG_TEST_PATTERN_EXTERNAL_RESET_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_RANDOM_PATTERN_SEED_RAN_PAT' +DIG_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { + 0: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', + 1: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', +} +DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0 +DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 1 +DIG_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL' +DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL__enumvalues = { + 0: 'DIG_FIFO_USE_OVERWRITE_LEVEL', + 1: 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', +} +DIG_FIFO_USE_OVERWRITE_LEVEL = 0 +DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 1 +DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_ERROR_ACK' +DIG_FIFO_ERROR_ACK__enumvalues = { + 0: 'DIG_FIFO_ERROR_ACK_INT', + 1: 'DIG_FIFO_ERROR_NOT_ACK', +} +DIG_FIFO_ERROR_ACK_INT = 0 +DIG_FIFO_ERROR_NOT_ACK = 1 +DIG_FIFO_ERROR_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE' +DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE__enumvalues = { + 0: 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', + 1: 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', +} +DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0 +DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 1 +DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX' +DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX__enumvalues = { + 0: 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', + 1: 'DIG_FIFO_FORCE_RECOMP_MINMAX', +} +DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0 +DIG_FIFO_FORCE_RECOMP_MINMAX = 1 +DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_INTERRUPT_STATUS_CHG_MASK' +AFMT_INTERRUPT_STATUS_CHG_MASK__enumvalues = { + 0: 'AFMT_INTERRUPT_DISABLE', + 1: 'AFMT_INTERRUPT_ENABLE', +} +AFMT_INTERRUPT_DISABLE = 0 +AFMT_INTERRUPT_ENABLE = 1 +AFMT_INTERRUPT_STATUS_CHG_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_AVMUTE' +HDMI_GC_AVMUTE__enumvalues = { + 0: 'HDMI_GC_AVMUTE_SET', + 1: 'HDMI_GC_AVMUTE_UNSET', +} +HDMI_GC_AVMUTE_SET = 0 +HDMI_GC_AVMUTE_UNSET = 1 +HDMI_GC_AVMUTE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_DEFAULT_PAHSE' +HDMI_DEFAULT_PAHSE__enumvalues = { + 0: 'HDMI_DEFAULT_PHASE_IS_0', + 1: 'HDMI_DEFAULT_PHASE_IS_1', +} +HDMI_DEFAULT_PHASE_IS_0 = 0 +HDMI_DEFAULT_PHASE_IS_1 = 1 +HDMI_DEFAULT_PAHSE = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD' +AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD__enumvalues = { + 0: 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', + 1: 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', +} +AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0 +AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 1 +AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD = ctypes.c_uint32 # enum + +# values for enumeration 'AUDIO_LAYOUT_SELECT' +AUDIO_LAYOUT_SELECT__enumvalues = { + 0: 'AUDIO_LAYOUT_0', + 1: 'AUDIO_LAYOUT_1', +} +AUDIO_LAYOUT_0 = 0 +AUDIO_LAYOUT_1 = 1 +AUDIO_LAYOUT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CONT' +AFMT_AUDIO_CRC_CONTROL_CONT__enumvalues = { + 0: 'AFMT_AUDIO_CRC_ONESHOT', + 1: 'AFMT_AUDIO_CRC_AUTO_RESTART', +} +AFMT_AUDIO_CRC_ONESHOT = 0 +AFMT_AUDIO_CRC_AUTO_RESTART = 1 +AFMT_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_SOURCE' +AFMT_AUDIO_CRC_CONTROL_SOURCE__enumvalues = { + 0: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', + 1: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', +} +AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0 +AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 1 +AFMT_AUDIO_CRC_CONTROL_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CH_SEL' +AFMT_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = { + 0: 'AFMT_AUDIO_CRC_CH0_SIG', + 1: 'AFMT_AUDIO_CRC_CH1_SIG', + 2: 'AFMT_AUDIO_CRC_CH2_SIG', + 3: 'AFMT_AUDIO_CRC_CH3_SIG', + 4: 'AFMT_AUDIO_CRC_CH4_SIG', + 5: 'AFMT_AUDIO_CRC_CH5_SIG', + 6: 'AFMT_AUDIO_CRC_CH6_SIG', + 7: 'AFMT_AUDIO_CRC_CH7_SIG', + 8: 'AFMT_AUDIO_CRC_RESERVED_8', + 9: 'AFMT_AUDIO_CRC_RESERVED_9', + 10: 'AFMT_AUDIO_CRC_RESERVED_10', + 11: 'AFMT_AUDIO_CRC_RESERVED_11', + 12: 'AFMT_AUDIO_CRC_RESERVED_12', + 13: 'AFMT_AUDIO_CRC_RESERVED_13', + 14: 'AFMT_AUDIO_CRC_RESERVED_14', + 15: 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', +} +AFMT_AUDIO_CRC_CH0_SIG = 0 +AFMT_AUDIO_CRC_CH1_SIG = 1 +AFMT_AUDIO_CRC_CH2_SIG = 2 +AFMT_AUDIO_CRC_CH3_SIG = 3 +AFMT_AUDIO_CRC_CH4_SIG = 4 +AFMT_AUDIO_CRC_CH5_SIG = 5 +AFMT_AUDIO_CRC_CH6_SIG = 6 +AFMT_AUDIO_CRC_CH7_SIG = 7 +AFMT_AUDIO_CRC_RESERVED_8 = 8 +AFMT_AUDIO_CRC_RESERVED_9 = 9 +AFMT_AUDIO_CRC_RESERVED_10 = 10 +AFMT_AUDIO_CRC_RESERVED_11 = 11 +AFMT_AUDIO_CRC_RESERVED_12 = 12 +AFMT_AUDIO_CRC_RESERVED_13 = 13 +AFMT_AUDIO_CRC_RESERVED_14 = 14 +AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 15 +AFMT_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_RAMP_CONTROL0_SIGN' +AFMT_RAMP_CONTROL0_SIGN__enumvalues = { + 0: 'AFMT_RAMP_SIGNED', + 1: 'AFMT_RAMP_UNSIGNED', +} +AFMT_RAMP_SIGNED = 0 +AFMT_RAMP_UNSIGNED = 1 +AFMT_RAMP_CONTROL0_SIGN = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND' +AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND__enumvalues = { + 0: 'AFMT_AUDIO_PACKET_SENT_DISABLED', + 1: 'AFMT_AUDIO_PACKET_SENT_ENABLED', +} +AFMT_AUDIO_PACKET_SENT_DISABLED = 0 +AFMT_AUDIO_PACKET_SENT_ENABLED = 1 +AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS' +AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS__enumvalues = { + 0: 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', + 1: 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', +} +AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0 +AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 1 +AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE' +AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE__enumvalues = { + 0: 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', + 1: 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', +} +AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0 +AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 1 +AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_SRC_CONTROL_SELECT' +AFMT_AUDIO_SRC_CONTROL_SELECT__enumvalues = { + 0: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', + 1: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', + 2: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', + 3: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', + 4: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', + 5: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', + 6: 'AFMT_AUDIO_SRC_RESERVED', +} +AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0 +AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 1 +AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 2 +AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 3 +AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 4 +AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 5 +AFMT_AUDIO_SRC_RESERVED = 6 +AFMT_AUDIO_SRC_CONTROL_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_BE_CNTL_MODE' +DIG_BE_CNTL_MODE__enumvalues = { + 0: 'DIG_BE_DP_SST_MODE', + 1: 'DIG_BE_RESERVED1', + 2: 'DIG_BE_TMDS_DVI_MODE', + 3: 'DIG_BE_TMDS_HDMI_MODE', + 4: 'DIG_BE_SDVO_RESERVED', + 5: 'DIG_BE_DP_MST_MODE', + 6: 'DIG_BE_RESERVED2', + 7: 'DIG_BE_RESERVED3', +} +DIG_BE_DP_SST_MODE = 0 +DIG_BE_RESERVED1 = 1 +DIG_BE_TMDS_DVI_MODE = 2 +DIG_BE_TMDS_HDMI_MODE = 3 +DIG_BE_SDVO_RESERVED = 4 +DIG_BE_DP_MST_MODE = 5 +DIG_BE_RESERVED2 = 6 +DIG_BE_RESERVED3 = 7 +DIG_BE_CNTL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_BE_CNTL_HPD_SELECT' +DIG_BE_CNTL_HPD_SELECT__enumvalues = { + 0: 'DIG_BE_CNTL_HPD1', + 1: 'DIG_BE_CNTL_HPD2', + 2: 'DIG_BE_CNTL_HPD3', + 3: 'DIG_BE_CNTL_HPD4', + 4: 'DIG_BE_CNTL_HPD5', + 5: 'DIG_BE_CNTL_HPD6', +} +DIG_BE_CNTL_HPD1 = 0 +DIG_BE_CNTL_HPD2 = 1 +DIG_BE_CNTL_HPD3 = 2 +DIG_BE_CNTL_HPD4 = 3 +DIG_BE_CNTL_HPD5 = 4 +DIG_BE_CNTL_HPD6 = 5 +DIG_BE_CNTL_HPD_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT' +LVTMA_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { + 0: 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', + 1: 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', +} +LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0 +LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 1 +LVTMA_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_SYNC_PHASE' +TMDS_SYNC_PHASE__enumvalues = { + 0: 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', + 1: 'TMDS_SYNC_PHASE_ON_FRAME_START', +} +TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0 +TMDS_SYNC_PHASE_ON_FRAME_START = 1 +TMDS_SYNC_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL' +TMDS_DATA_SYNCHRONIZATION_DSINTSEL__enumvalues = { + 0: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', + 1: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', +} +TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0 +TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 1 +TMDS_DATA_SYNCHRONIZATION_DSINTSEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_ENABLE_HPD_MASK' +TMDS_TRANSMITTER_ENABLE_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', + 1: 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', +} +TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0 +TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 1 +TMDS_TRANSMITTER_ENABLE_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK' +TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', + 1: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', +} +TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0 +TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 1 +TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK' +TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', + 1: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', +} +TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0 +TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 1 +TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK' +TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', + 1: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', + 2: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', + 3: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', +} +TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0 +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 1 +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 2 +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 3 +TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA' +TMDS_TRANSMITTER_CONTROL_IDSCKSELA__enumvalues = { + 0: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', + 1: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', +} +TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0 +TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 1 +TMDS_TRANSMITTER_CONTROL_IDSCKSELA = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB' +TMDS_TRANSMITTER_CONTROL_IDSCKSELB__enumvalues = { + 0: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', + 1: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', +} +TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0 +TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 1 +TMDS_TRANSMITTER_CONTROL_IDSCKSELB = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN' +TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN__enumvalues = { + 0: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', + 1: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', +} +TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0 +TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 1 +TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK' +TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', + 1: 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', +} +TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0 +TMDS_TRANSMITTER_PLL_RST_ON_HPD = 1 +TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS' +TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS__enumvalues = { + 0: 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', + 1: 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', +} +TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0 +TMDS_TRANSMITTER_TMCLK_FROM_PADS = 1 +TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS' +TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS__enumvalues = { + 0: 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', + 1: 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', +} +TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0 +TMDS_TRANSMITTER_TDCLK_FROM_PADS = 1 +TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN' +TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN__enumvalues = { + 0: 'TMDS_TRANSMITTER_PLLSEL_BY_HW', + 1: 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', +} +TMDS_TRANSMITTER_PLLSEL_BY_HW = 0 +TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 1 +TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA' +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA__enumvalues = { + 0: 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', + 1: 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', +} +TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0 +TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 1 +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB' +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB__enumvalues = { + 0: 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', + 1: 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', +} +TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0 +TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 1 +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_REG_TEST_OUTPUTA_CNTLA' +TMDS_REG_TEST_OUTPUTA_CNTLA__enumvalues = { + 0: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', + 1: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', + 2: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', + 3: 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', +} +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0 +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 1 +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 2 +TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 3 +TMDS_REG_TEST_OUTPUTA_CNTLA = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_REG_TEST_OUTPUTB_CNTLB' +TMDS_REG_TEST_OUTPUTB_CNTLB__enumvalues = { + 0: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', + 1: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', + 2: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', + 3: 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', +} +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0 +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 1 +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 2 +TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 3 +TMDS_REG_TEST_OUTPUTB_CNTLB = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_ENABLE' +DCP_GRPH_ENABLE__enumvalues = { + 0: 'DCP_GRPH_ENABLE_FALSE', + 1: 'DCP_GRPH_ENABLE_TRUE', +} +DCP_GRPH_ENABLE_FALSE = 0 +DCP_GRPH_ENABLE_TRUE = 1 +DCP_GRPH_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_KEYER_ALPHA_SEL' +DCP_GRPH_KEYER_ALPHA_SEL__enumvalues = { + 0: 'DCP_GRPH_KEYER_ALPHA_SEL_FALSE', + 1: 'DCP_GRPH_KEYER_ALPHA_SEL_TRUE', +} +DCP_GRPH_KEYER_ALPHA_SEL_FALSE = 0 +DCP_GRPH_KEYER_ALPHA_SEL_TRUE = 1 +DCP_GRPH_KEYER_ALPHA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_DEPTH' +DCP_GRPH_DEPTH__enumvalues = { + 0: 'DCP_GRPH_DEPTH_8BPP', + 1: 'DCP_GRPH_DEPTH_16BPP', + 2: 'DCP_GRPH_DEPTH_32BPP', + 3: 'DCP_GRPH_DEPTH_64BPP', +} +DCP_GRPH_DEPTH_8BPP = 0 +DCP_GRPH_DEPTH_16BPP = 1 +DCP_GRPH_DEPTH_32BPP = 2 +DCP_GRPH_DEPTH_64BPP = 3 +DCP_GRPH_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_NUM_BANKS' +DCP_GRPH_NUM_BANKS__enumvalues = { + 0: 'DCP_GRPH_NUM_BANKS_1BANK', + 1: 'DCP_GRPH_NUM_BANKS_2BANK', + 2: 'DCP_GRPH_NUM_BANKS_4BANK', + 3: 'DCP_GRPH_NUM_BANKS_8BANK', + 4: 'DCP_GRPH_NUM_BANKS_16BANK', +} +DCP_GRPH_NUM_BANKS_1BANK = 0 +DCP_GRPH_NUM_BANKS_2BANK = 1 +DCP_GRPH_NUM_BANKS_4BANK = 2 +DCP_GRPH_NUM_BANKS_8BANK = 3 +DCP_GRPH_NUM_BANKS_16BANK = 4 +DCP_GRPH_NUM_BANKS = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_NUM_PIPES' +DCP_GRPH_NUM_PIPES__enumvalues = { + 0: 'DCP_GRPH_NUM_PIPES_1PIPE', + 1: 'DCP_GRPH_NUM_PIPES_2PIPE', + 2: 'DCP_GRPH_NUM_PIPES_4PIPE', + 3: 'DCP_GRPH_NUM_PIPES_8PIPE', +} +DCP_GRPH_NUM_PIPES_1PIPE = 0 +DCP_GRPH_NUM_PIPES_2PIPE = 1 +DCP_GRPH_NUM_PIPES_4PIPE = 2 +DCP_GRPH_NUM_PIPES_8PIPE = 3 +DCP_GRPH_NUM_PIPES = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_FORMAT' +DCP_GRPH_FORMAT__enumvalues = { + 0: 'DCP_GRPH_FORMAT_8BPP', + 1: 'DCP_GRPH_FORMAT_16BPP', + 2: 'DCP_GRPH_FORMAT_32BPP', + 3: 'DCP_GRPH_FORMAT_64BPP', +} +DCP_GRPH_FORMAT_8BPP = 0 +DCP_GRPH_FORMAT_16BPP = 1 +DCP_GRPH_FORMAT_32BPP = 2 +DCP_GRPH_FORMAT_64BPP = 3 +DCP_GRPH_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE' +DCP_GRPH_ADDRESS_TRANSLATION_ENABLE__enumvalues = { + 0: 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE', + 1: 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE', +} +DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE = 0 +DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE = 1 +DCP_GRPH_ADDRESS_TRANSLATION_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SW_MODE' +DCP_GRPH_SW_MODE__enumvalues = { + 0: 'DCP_GRPH_SW_MODE_0', + 2: 'DCP_GRPH_SW_MODE_2', + 3: 'DCP_GRPH_SW_MODE_3', + 22: 'DCP_GRPH_SW_MODE_22', + 23: 'DCP_GRPH_SW_MODE_23', + 26: 'DCP_GRPH_SW_MODE_26', + 27: 'DCP_GRPH_SW_MODE_27', + 30: 'DCP_GRPH_SW_MODE_30', + 31: 'DCP_GRPH_SW_MODE_31', +} +DCP_GRPH_SW_MODE_0 = 0 +DCP_GRPH_SW_MODE_2 = 2 +DCP_GRPH_SW_MODE_3 = 3 +DCP_GRPH_SW_MODE_22 = 22 +DCP_GRPH_SW_MODE_23 = 23 +DCP_GRPH_SW_MODE_26 = 26 +DCP_GRPH_SW_MODE_27 = 27 +DCP_GRPH_SW_MODE_30 = 30 +DCP_GRPH_SW_MODE_31 = 31 +DCP_GRPH_SW_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_COLOR_EXPANSION_MODE' +DCP_GRPH_COLOR_EXPANSION_MODE__enumvalues = { + 0: 'DCP_GRPH_COLOR_EXPANSION_MODE_DEXP', + 1: 'DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP', +} +DCP_GRPH_COLOR_EXPANSION_MODE_DEXP = 0 +DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP = 1 +DCP_GRPH_COLOR_EXPANSION_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_LUT_10BIT_BYPASS_EN' +DCP_GRPH_LUT_10BIT_BYPASS_EN__enumvalues = { + 0: 'DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE', + 1: 'DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE', +} +DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE = 0 +DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE = 1 +DCP_GRPH_LUT_10BIT_BYPASS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN' +DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__enumvalues = { + 0: 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE', + 1: 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE', +} +DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE = 0 +DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE = 1 +DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_ENDIAN_SWAP' +DCP_GRPH_ENDIAN_SWAP__enumvalues = { + 0: 'DCP_GRPH_ENDIAN_SWAP_NONE', + 1: 'DCP_GRPH_ENDIAN_SWAP_8IN16', + 2: 'DCP_GRPH_ENDIAN_SWAP_8IN32', + 3: 'DCP_GRPH_ENDIAN_SWAP_8IN64', +} +DCP_GRPH_ENDIAN_SWAP_NONE = 0 +DCP_GRPH_ENDIAN_SWAP_8IN16 = 1 +DCP_GRPH_ENDIAN_SWAP_8IN32 = 2 +DCP_GRPH_ENDIAN_SWAP_8IN64 = 3 +DCP_GRPH_ENDIAN_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_RED_CROSSBAR' +DCP_GRPH_RED_CROSSBAR__enumvalues = { + 0: 'DCP_GRPH_RED_CROSSBAR_FROM_R', + 1: 'DCP_GRPH_RED_CROSSBAR_FROM_G', + 2: 'DCP_GRPH_RED_CROSSBAR_FROM_B', + 3: 'DCP_GRPH_RED_CROSSBAR_FROM_A', +} +DCP_GRPH_RED_CROSSBAR_FROM_R = 0 +DCP_GRPH_RED_CROSSBAR_FROM_G = 1 +DCP_GRPH_RED_CROSSBAR_FROM_B = 2 +DCP_GRPH_RED_CROSSBAR_FROM_A = 3 +DCP_GRPH_RED_CROSSBAR = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_GREEN_CROSSBAR' +DCP_GRPH_GREEN_CROSSBAR__enumvalues = { + 0: 'DCP_GRPH_GREEN_CROSSBAR_FROM_G', + 1: 'DCP_GRPH_GREEN_CROSSBAR_FROM_B', + 2: 'DCP_GRPH_GREEN_CROSSBAR_FROM_A', + 3: 'DCP_GRPH_GREEN_CROSSBAR_FROM_R', +} +DCP_GRPH_GREEN_CROSSBAR_FROM_G = 0 +DCP_GRPH_GREEN_CROSSBAR_FROM_B = 1 +DCP_GRPH_GREEN_CROSSBAR_FROM_A = 2 +DCP_GRPH_GREEN_CROSSBAR_FROM_R = 3 +DCP_GRPH_GREEN_CROSSBAR = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_BLUE_CROSSBAR' +DCP_GRPH_BLUE_CROSSBAR__enumvalues = { + 0: 'DCP_GRPH_BLUE_CROSSBAR_FROM_B', + 1: 'DCP_GRPH_BLUE_CROSSBAR_FROM_A', + 2: 'DCP_GRPH_BLUE_CROSSBAR_FROM_R', + 3: 'DCP_GRPH_BLUE_CROSSBAR_FROM_G', +} +DCP_GRPH_BLUE_CROSSBAR_FROM_B = 0 +DCP_GRPH_BLUE_CROSSBAR_FROM_A = 1 +DCP_GRPH_BLUE_CROSSBAR_FROM_R = 2 +DCP_GRPH_BLUE_CROSSBAR_FROM_G = 3 +DCP_GRPH_BLUE_CROSSBAR = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_ALPHA_CROSSBAR' +DCP_GRPH_ALPHA_CROSSBAR__enumvalues = { + 0: 'DCP_GRPH_ALPHA_CROSSBAR_FROM_A', + 1: 'DCP_GRPH_ALPHA_CROSSBAR_FROM_R', + 2: 'DCP_GRPH_ALPHA_CROSSBAR_FROM_G', + 3: 'DCP_GRPH_ALPHA_CROSSBAR_FROM_B', +} +DCP_GRPH_ALPHA_CROSSBAR_FROM_A = 0 +DCP_GRPH_ALPHA_CROSSBAR_FROM_R = 1 +DCP_GRPH_ALPHA_CROSSBAR_FROM_G = 2 +DCP_GRPH_ALPHA_CROSSBAR_FROM_B = 3 +DCP_GRPH_ALPHA_CROSSBAR = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_PRIMARY_DFQ_ENABLE' +DCP_GRPH_PRIMARY_DFQ_ENABLE__enumvalues = { + 0: 'DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE', + 1: 'DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE', +} +DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE = 0 +DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE = 1 +DCP_GRPH_PRIMARY_DFQ_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SECONDARY_DFQ_ENABLE' +DCP_GRPH_SECONDARY_DFQ_ENABLE__enumvalues = { + 0: 'DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE', + 1: 'DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE', +} +DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE = 0 +DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE = 1 +DCP_GRPH_SECONDARY_DFQ_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_INPUT_GAMMA_MODE' +DCP_GRPH_INPUT_GAMMA_MODE__enumvalues = { + 0: 'DCP_GRPH_INPUT_GAMMA_MODE_LUT', + 1: 'DCP_GRPH_INPUT_GAMMA_MODE_BYPASS', +} +DCP_GRPH_INPUT_GAMMA_MODE_LUT = 0 +DCP_GRPH_INPUT_GAMMA_MODE_BYPASS = 1 +DCP_GRPH_INPUT_GAMMA_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_MODE_UPDATE_PENDING' +DCP_GRPH_MODE_UPDATE_PENDING__enumvalues = { + 0: 'DCP_GRPH_MODE_UPDATE_PENDING_FALSE', + 1: 'DCP_GRPH_MODE_UPDATE_PENDING_TRUE', +} +DCP_GRPH_MODE_UPDATE_PENDING_FALSE = 0 +DCP_GRPH_MODE_UPDATE_PENDING_TRUE = 1 +DCP_GRPH_MODE_UPDATE_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_MODE_UPDATE_TAKEN' +DCP_GRPH_MODE_UPDATE_TAKEN__enumvalues = { + 0: 'DCP_GRPH_MODE_UPDATE_TAKEN_FALSE', + 1: 'DCP_GRPH_MODE_UPDATE_TAKEN_TRUE', +} +DCP_GRPH_MODE_UPDATE_TAKEN_FALSE = 0 +DCP_GRPH_MODE_UPDATE_TAKEN_TRUE = 1 +DCP_GRPH_MODE_UPDATE_TAKEN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SURFACE_UPDATE_PENDING' +DCP_GRPH_SURFACE_UPDATE_PENDING__enumvalues = { + 0: 'DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE', + 1: 'DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE', +} +DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE = 0 +DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE = 1 +DCP_GRPH_SURFACE_UPDATE_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SURFACE_UPDATE_TAKEN' +DCP_GRPH_SURFACE_UPDATE_TAKEN__enumvalues = { + 0: 'DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE', + 1: 'DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE', +} +DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE = 0 +DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE = 1 +DCP_GRPH_SURFACE_UPDATE_TAKEN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE' +DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE__enumvalues = { + 0: 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE', + 1: 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE', +} +DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE = 0 +DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE = 1 +DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_UPDATE_LOCK' +DCP_GRPH_UPDATE_LOCK__enumvalues = { + 0: 'DCP_GRPH_UPDATE_LOCK_FALSE', + 1: 'DCP_GRPH_UPDATE_LOCK_TRUE', +} +DCP_GRPH_UPDATE_LOCK_FALSE = 0 +DCP_GRPH_UPDATE_LOCK_TRUE = 1 +DCP_GRPH_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK' +DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK__enumvalues = { + 0: 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE', + 1: 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE', +} +DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE = 0 +DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE = 1 +DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE' +DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE__enumvalues = { + 0: 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE', + 1: 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE', +} +DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE = 0 +DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE = 1 +DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE' +DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__enumvalues = { + 0: 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE', + 1: 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE', +} +DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE = 0 +DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE = 1 +DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN' +DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN__enumvalues = { + 0: 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE', + 1: 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE', +} +DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE = 0 +DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE = 1 +DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_SUPER_AA_EN' +DCP_GRPH_XDMA_SUPER_AA_EN__enumvalues = { + 0: 'DCP_GRPH_XDMA_SUPER_AA_EN_FALSE', + 1: 'DCP_GRPH_XDMA_SUPER_AA_EN_TRUE', +} +DCP_GRPH_XDMA_SUPER_AA_EN_FALSE = 0 +DCP_GRPH_XDMA_SUPER_AA_EN_TRUE = 1 +DCP_GRPH_XDMA_SUPER_AA_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_DFQ_RESET' +DCP_GRPH_DFQ_RESET__enumvalues = { + 0: 'DCP_GRPH_DFQ_RESET_FALSE', + 1: 'DCP_GRPH_DFQ_RESET_TRUE', +} +DCP_GRPH_DFQ_RESET_FALSE = 0 +DCP_GRPH_DFQ_RESET_TRUE = 1 +DCP_GRPH_DFQ_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_DFQ_SIZE' +DCP_GRPH_DFQ_SIZE__enumvalues = { + 0: 'DCP_GRPH_DFQ_SIZE_DEEP1', + 1: 'DCP_GRPH_DFQ_SIZE_DEEP2', + 2: 'DCP_GRPH_DFQ_SIZE_DEEP3', + 3: 'DCP_GRPH_DFQ_SIZE_DEEP4', + 4: 'DCP_GRPH_DFQ_SIZE_DEEP5', + 5: 'DCP_GRPH_DFQ_SIZE_DEEP6', + 6: 'DCP_GRPH_DFQ_SIZE_DEEP7', + 7: 'DCP_GRPH_DFQ_SIZE_DEEP8', +} +DCP_GRPH_DFQ_SIZE_DEEP1 = 0 +DCP_GRPH_DFQ_SIZE_DEEP2 = 1 +DCP_GRPH_DFQ_SIZE_DEEP3 = 2 +DCP_GRPH_DFQ_SIZE_DEEP4 = 3 +DCP_GRPH_DFQ_SIZE_DEEP5 = 4 +DCP_GRPH_DFQ_SIZE_DEEP6 = 5 +DCP_GRPH_DFQ_SIZE_DEEP7 = 6 +DCP_GRPH_DFQ_SIZE_DEEP8 = 7 +DCP_GRPH_DFQ_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES' +DCP_GRPH_DFQ_MIN_FREE_ENTRIES__enumvalues = { + 0: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1', + 1: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2', + 2: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3', + 3: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4', + 4: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5', + 5: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6', + 6: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7', + 7: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8', +} +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1 = 0 +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2 = 1 +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3 = 2 +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4 = 3 +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5 = 4 +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6 = 5 +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7 = 6 +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8 = 7 +DCP_GRPH_DFQ_MIN_FREE_ENTRIES = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_DFQ_RESET_ACK' +DCP_GRPH_DFQ_RESET_ACK__enumvalues = { + 0: 'DCP_GRPH_DFQ_RESET_ACK_FALSE', + 1: 'DCP_GRPH_DFQ_RESET_ACK_TRUE', +} +DCP_GRPH_DFQ_RESET_ACK_FALSE = 0 +DCP_GRPH_DFQ_RESET_ACK_TRUE = 1 +DCP_GRPH_DFQ_RESET_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_PFLIP_INT_CLEAR' +DCP_GRPH_PFLIP_INT_CLEAR__enumvalues = { + 0: 'DCP_GRPH_PFLIP_INT_CLEAR_FALSE', + 1: 'DCP_GRPH_PFLIP_INT_CLEAR_TRUE', +} +DCP_GRPH_PFLIP_INT_CLEAR_FALSE = 0 +DCP_GRPH_PFLIP_INT_CLEAR_TRUE = 1 +DCP_GRPH_PFLIP_INT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_PFLIP_INT_MASK' +DCP_GRPH_PFLIP_INT_MASK__enumvalues = { + 0: 'DCP_GRPH_PFLIP_INT_MASK_FALSE', + 1: 'DCP_GRPH_PFLIP_INT_MASK_TRUE', +} +DCP_GRPH_PFLIP_INT_MASK_FALSE = 0 +DCP_GRPH_PFLIP_INT_MASK_TRUE = 1 +DCP_GRPH_PFLIP_INT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_PFLIP_INT_TYPE' +DCP_GRPH_PFLIP_INT_TYPE__enumvalues = { + 0: 'DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL', + 1: 'DCP_GRPH_PFLIP_INT_TYPE_PULSE', +} +DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL = 0 +DCP_GRPH_PFLIP_INT_TYPE_PULSE = 1 +DCP_GRPH_PFLIP_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_PRESCALE_SELECT' +DCP_GRPH_PRESCALE_SELECT__enumvalues = { + 0: 'DCP_GRPH_PRESCALE_SELECT_FIXED', + 1: 'DCP_GRPH_PRESCALE_SELECT_FLOATING', +} +DCP_GRPH_PRESCALE_SELECT_FIXED = 0 +DCP_GRPH_PRESCALE_SELECT_FLOATING = 1 +DCP_GRPH_PRESCALE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_PRESCALE_R_SIGN' +DCP_GRPH_PRESCALE_R_SIGN__enumvalues = { + 0: 'DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED', + 1: 'DCP_GRPH_PRESCALE_R_SIGN_SIGNED', +} +DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED = 0 +DCP_GRPH_PRESCALE_R_SIGN_SIGNED = 1 +DCP_GRPH_PRESCALE_R_SIGN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_PRESCALE_G_SIGN' +DCP_GRPH_PRESCALE_G_SIGN__enumvalues = { + 0: 'DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED', + 1: 'DCP_GRPH_PRESCALE_G_SIGN_SIGNED', +} +DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED = 0 +DCP_GRPH_PRESCALE_G_SIGN_SIGNED = 1 +DCP_GRPH_PRESCALE_G_SIGN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_PRESCALE_B_SIGN' +DCP_GRPH_PRESCALE_B_SIGN__enumvalues = { + 0: 'DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED', + 1: 'DCP_GRPH_PRESCALE_B_SIGN_SIGNED', +} +DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED = 0 +DCP_GRPH_PRESCALE_B_SIGN_SIGNED = 1 +DCP_GRPH_PRESCALE_B_SIGN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_PRESCALE_BYPASS' +DCP_GRPH_PRESCALE_BYPASS__enumvalues = { + 0: 'DCP_GRPH_PRESCALE_BYPASS_FALSE', + 1: 'DCP_GRPH_PRESCALE_BYPASS_TRUE', +} +DCP_GRPH_PRESCALE_BYPASS_FALSE = 0 +DCP_GRPH_PRESCALE_BYPASS_TRUE = 1 +DCP_GRPH_PRESCALE_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_INPUT_CSC_GRPH_MODE' +DCP_INPUT_CSC_GRPH_MODE__enumvalues = { + 0: 'DCP_INPUT_CSC_GRPH_MODE_BYPASS', + 1: 'DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF', + 2: 'DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF', + 3: 'DCP_INPUT_CSC_GRPH_MODE_RESERVED', +} +DCP_INPUT_CSC_GRPH_MODE_BYPASS = 0 +DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF = 1 +DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF = 2 +DCP_INPUT_CSC_GRPH_MODE_RESERVED = 3 +DCP_INPUT_CSC_GRPH_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_OUTPUT_CSC_GRPH_MODE' +DCP_OUTPUT_CSC_GRPH_MODE__enumvalues = { + 0: 'DCP_OUTPUT_CSC_GRPH_MODE_BYPASS', + 1: 'DCP_OUTPUT_CSC_GRPH_MODE_RGB', + 2: 'DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601', + 3: 'DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709', + 4: 'DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF', + 5: 'DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF', + 6: 'DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0', + 7: 'DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1', +} +DCP_OUTPUT_CSC_GRPH_MODE_BYPASS = 0 +DCP_OUTPUT_CSC_GRPH_MODE_RGB = 1 +DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601 = 2 +DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709 = 3 +DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF = 4 +DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF = 5 +DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0 = 6 +DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1 = 7 +DCP_OUTPUT_CSC_GRPH_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DENORM_MODE' +DCP_DENORM_MODE__enumvalues = { + 0: 'DCP_DENORM_MODE_UNITY', + 1: 'DCP_DENORM_MODE_6BIT', + 2: 'DCP_DENORM_MODE_8BIT', + 3: 'DCP_DENORM_MODE_10BIT', + 4: 'DCP_DENORM_MODE_11BIT', + 5: 'DCP_DENORM_MODE_12BIT', + 6: 'DCP_DENORM_MODE_RESERVED0', + 7: 'DCP_DENORM_MODE_RESERVED1', +} +DCP_DENORM_MODE_UNITY = 0 +DCP_DENORM_MODE_6BIT = 1 +DCP_DENORM_MODE_8BIT = 2 +DCP_DENORM_MODE_10BIT = 3 +DCP_DENORM_MODE_11BIT = 4 +DCP_DENORM_MODE_12BIT = 5 +DCP_DENORM_MODE_RESERVED0 = 6 +DCP_DENORM_MODE_RESERVED1 = 7 +DCP_DENORM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DENORM_14BIT_OUT' +DCP_DENORM_14BIT_OUT__enumvalues = { + 0: 'DCP_DENORM_14BIT_OUT_FALSE', + 1: 'DCP_DENORM_14BIT_OUT_TRUE', +} +DCP_DENORM_14BIT_OUT_FALSE = 0 +DCP_DENORM_14BIT_OUT_TRUE = 1 +DCP_DENORM_14BIT_OUT = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_OUT_ROUND_TRUNC_MODE' +DCP_OUT_ROUND_TRUNC_MODE__enumvalues = { + 0: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12', + 1: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11', + 2: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10', + 3: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9', + 4: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8', + 5: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED', + 6: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14', + 7: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13', + 8: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_12', + 9: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_11', + 10: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_10', + 11: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_9', + 12: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_8', + 13: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED', + 14: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_14', + 15: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_13', +} +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12 = 0 +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11 = 1 +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10 = 2 +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9 = 3 +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8 = 4 +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED = 5 +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14 = 6 +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13 = 7 +DCP_OUT_ROUND_TRUNC_MODE_ROUND_12 = 8 +DCP_OUT_ROUND_TRUNC_MODE_ROUND_11 = 9 +DCP_OUT_ROUND_TRUNC_MODE_ROUND_10 = 10 +DCP_OUT_ROUND_TRUNC_MODE_ROUND_9 = 11 +DCP_OUT_ROUND_TRUNC_MODE_ROUND_8 = 12 +DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED = 13 +DCP_OUT_ROUND_TRUNC_MODE_ROUND_14 = 14 +DCP_OUT_ROUND_TRUNC_MODE_ROUND_13 = 15 +DCP_OUT_ROUND_TRUNC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_KEY_MODE' +DCP_KEY_MODE__enumvalues = { + 0: 'DCP_KEY_MODE_ALPHA0', + 1: 'DCP_KEY_MODE_ALPHA1', + 2: 'DCP_KEY_MODE_IN_RANGE_ALPHA1', + 3: 'DCP_KEY_MODE_IN_RANGE_ALPHA0', +} +DCP_KEY_MODE_ALPHA0 = 0 +DCP_KEY_MODE_ALPHA1 = 1 +DCP_KEY_MODE_IN_RANGE_ALPHA1 = 2 +DCP_KEY_MODE_IN_RANGE_ALPHA0 = 3 +DCP_KEY_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_DEGAMMA_MODE' +DCP_GRPH_DEGAMMA_MODE__enumvalues = { + 0: 'DCP_GRPH_DEGAMMA_MODE_BYPASS', + 1: 'DCP_GRPH_DEGAMMA_MODE_ROMA', + 2: 'DCP_GRPH_DEGAMMA_MODE_ROMB', + 3: 'DCP_GRPH_DEGAMMA_MODE_RESERVED', +} +DCP_GRPH_DEGAMMA_MODE_BYPASS = 0 +DCP_GRPH_DEGAMMA_MODE_ROMA = 1 +DCP_GRPH_DEGAMMA_MODE_ROMB = 2 +DCP_GRPH_DEGAMMA_MODE_RESERVED = 3 +DCP_GRPH_DEGAMMA_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_DEGAMMA_MODE' +DCP_CURSOR_DEGAMMA_MODE__enumvalues = { + 0: 'DCP_CURSOR_DEGAMMA_MODE_BYPASS', + 1: 'DCP_CURSOR_DEGAMMA_MODE_ROMA', + 2: 'DCP_CURSOR_DEGAMMA_MODE_ROMB', + 3: 'DCP_CURSOR_DEGAMMA_MODE_RESERVED', +} +DCP_CURSOR_DEGAMMA_MODE_BYPASS = 0 +DCP_CURSOR_DEGAMMA_MODE_ROMA = 1 +DCP_CURSOR_DEGAMMA_MODE_ROMB = 2 +DCP_CURSOR_DEGAMMA_MODE_RESERVED = 3 +DCP_CURSOR_DEGAMMA_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_GAMUT_REMAP_MODE' +DCP_GRPH_GAMUT_REMAP_MODE__enumvalues = { + 0: 'DCP_GRPH_GAMUT_REMAP_MODE_BYPASS', + 1: 'DCP_GRPH_GAMUT_REMAP_MODE_ROMA', + 2: 'DCP_GRPH_GAMUT_REMAP_MODE_ROMB', + 3: 'DCP_GRPH_GAMUT_REMAP_MODE_RESERVED', +} +DCP_GRPH_GAMUT_REMAP_MODE_BYPASS = 0 +DCP_GRPH_GAMUT_REMAP_MODE_ROMA = 1 +DCP_GRPH_GAMUT_REMAP_MODE_ROMB = 2 +DCP_GRPH_GAMUT_REMAP_MODE_RESERVED = 3 +DCP_GRPH_GAMUT_REMAP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_SPATIAL_DITHER_EN' +DCP_SPATIAL_DITHER_EN__enumvalues = { + 0: 'DCP_SPATIAL_DITHER_EN_FALSE', + 1: 'DCP_SPATIAL_DITHER_EN_TRUE', +} +DCP_SPATIAL_DITHER_EN_FALSE = 0 +DCP_SPATIAL_DITHER_EN_TRUE = 1 +DCP_SPATIAL_DITHER_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_SPATIAL_DITHER_MODE' +DCP_SPATIAL_DITHER_MODE__enumvalues = { + 0: 'DCP_SPATIAL_DITHER_MODE_BYPASS', + 1: 'DCP_SPATIAL_DITHER_MODE_ROMA', + 2: 'DCP_SPATIAL_DITHER_MODE_ROMB', + 3: 'DCP_SPATIAL_DITHER_MODE_RESERVED', +} +DCP_SPATIAL_DITHER_MODE_BYPASS = 0 +DCP_SPATIAL_DITHER_MODE_ROMA = 1 +DCP_SPATIAL_DITHER_MODE_ROMB = 2 +DCP_SPATIAL_DITHER_MODE_RESERVED = 3 +DCP_SPATIAL_DITHER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_SPATIAL_DITHER_DEPTH' +DCP_SPATIAL_DITHER_DEPTH__enumvalues = { + 0: 'DCP_SPATIAL_DITHER_DEPTH_30BPP', + 1: 'DCP_SPATIAL_DITHER_DEPTH_24BPP', + 2: 'DCP_SPATIAL_DITHER_DEPTH_36BPP', + 3: 'DCP_SPATIAL_DITHER_DEPTH_UNDEFINED', +} +DCP_SPATIAL_DITHER_DEPTH_30BPP = 0 +DCP_SPATIAL_DITHER_DEPTH_24BPP = 1 +DCP_SPATIAL_DITHER_DEPTH_36BPP = 2 +DCP_SPATIAL_DITHER_DEPTH_UNDEFINED = 3 +DCP_SPATIAL_DITHER_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_FRAME_RANDOM_ENABLE' +DCP_FRAME_RANDOM_ENABLE__enumvalues = { + 0: 'DCP_FRAME_RANDOM_ENABLE_FALSE', + 1: 'DCP_FRAME_RANDOM_ENABLE_TRUE', +} +DCP_FRAME_RANDOM_ENABLE_FALSE = 0 +DCP_FRAME_RANDOM_ENABLE_TRUE = 1 +DCP_FRAME_RANDOM_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_RGB_RANDOM_ENABLE' +DCP_RGB_RANDOM_ENABLE__enumvalues = { + 0: 'DCP_RGB_RANDOM_ENABLE_FALSE', + 1: 'DCP_RGB_RANDOM_ENABLE_TRUE', +} +DCP_RGB_RANDOM_ENABLE_FALSE = 0 +DCP_RGB_RANDOM_ENABLE_TRUE = 1 +DCP_RGB_RANDOM_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_HIGHPASS_RANDOM_ENABLE' +DCP_HIGHPASS_RANDOM_ENABLE__enumvalues = { + 0: 'DCP_HIGHPASS_RANDOM_ENABLE_FALSE', + 1: 'DCP_HIGHPASS_RANDOM_ENABLE_TRUE', +} +DCP_HIGHPASS_RANDOM_ENABLE_FALSE = 0 +DCP_HIGHPASS_RANDOM_ENABLE_TRUE = 1 +DCP_HIGHPASS_RANDOM_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_EN' +DCP_CURSOR_EN__enumvalues = { + 0: 'DCP_CURSOR_EN_FALSE', + 1: 'DCP_CURSOR_EN_TRUE', +} +DCP_CURSOR_EN_FALSE = 0 +DCP_CURSOR_EN_TRUE = 1 +DCP_CURSOR_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CUR_INV_TRANS_CLAMP' +DCP_CUR_INV_TRANS_CLAMP__enumvalues = { + 0: 'DCP_CUR_INV_TRANS_CLAMP_FALSE', + 1: 'DCP_CUR_INV_TRANS_CLAMP_TRUE', +} +DCP_CUR_INV_TRANS_CLAMP_FALSE = 0 +DCP_CUR_INV_TRANS_CLAMP_TRUE = 1 +DCP_CUR_INV_TRANS_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_MODE' +DCP_CURSOR_MODE__enumvalues = { + 0: 'DCP_CURSOR_MODE_MONO_2BPP', + 1: 'DCP_CURSOR_MODE_24BPP_1BIT', + 2: 'DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI', + 3: 'DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI', +} +DCP_CURSOR_MODE_MONO_2BPP = 0 +DCP_CURSOR_MODE_24BPP_1BIT = 1 +DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI = 2 +DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI = 3 +DCP_CURSOR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM' +DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM__enumvalues = { + 0: 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE', + 1: 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO', +} +DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE = 0 +DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO = 1 +DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_2X_MAGNIFY' +DCP_CURSOR_2X_MAGNIFY__enumvalues = { + 0: 'DCP_CURSOR_2X_MAGNIFY_FALSE', + 1: 'DCP_CURSOR_2X_MAGNIFY_TRUE', +} +DCP_CURSOR_2X_MAGNIFY_FALSE = 0 +DCP_CURSOR_2X_MAGNIFY_TRUE = 1 +DCP_CURSOR_2X_MAGNIFY = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_FORCE_MC_ON' +DCP_CURSOR_FORCE_MC_ON__enumvalues = { + 0: 'DCP_CURSOR_FORCE_MC_ON_FALSE', + 1: 'DCP_CURSOR_FORCE_MC_ON_TRUE', +} +DCP_CURSOR_FORCE_MC_ON_FALSE = 0 +DCP_CURSOR_FORCE_MC_ON_TRUE = 1 +DCP_CURSOR_FORCE_MC_ON = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_URGENT_CONTROL' +DCP_CURSOR_URGENT_CONTROL__enumvalues = { + 0: 'DCP_CURSOR_URGENT_CONTROL_MODE_0', + 1: 'DCP_CURSOR_URGENT_CONTROL_MODE_1', + 2: 'DCP_CURSOR_URGENT_CONTROL_MODE_2', + 3: 'DCP_CURSOR_URGENT_CONTROL_MODE_3', + 4: 'DCP_CURSOR_URGENT_CONTROL_MODE_4', +} +DCP_CURSOR_URGENT_CONTROL_MODE_0 = 0 +DCP_CURSOR_URGENT_CONTROL_MODE_1 = 1 +DCP_CURSOR_URGENT_CONTROL_MODE_2 = 2 +DCP_CURSOR_URGENT_CONTROL_MODE_3 = 3 +DCP_CURSOR_URGENT_CONTROL_MODE_4 = 4 +DCP_CURSOR_URGENT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_UPDATE_PENDING' +DCP_CURSOR_UPDATE_PENDING__enumvalues = { + 0: 'DCP_CURSOR_UPDATE_PENDING_FALSE', + 1: 'DCP_CURSOR_UPDATE_PENDING_TRUE', +} +DCP_CURSOR_UPDATE_PENDING_FALSE = 0 +DCP_CURSOR_UPDATE_PENDING_TRUE = 1 +DCP_CURSOR_UPDATE_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_UPDATE_TAKEN' +DCP_CURSOR_UPDATE_TAKEN__enumvalues = { + 0: 'DCP_CURSOR_UPDATE_TAKEN_FALSE', + 1: 'DCP_CURSOR_UPDATE_TAKEN_TRUE', +} +DCP_CURSOR_UPDATE_TAKEN_FALSE = 0 +DCP_CURSOR_UPDATE_TAKEN_TRUE = 1 +DCP_CURSOR_UPDATE_TAKEN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_UPDATE_LOCK' +DCP_CURSOR_UPDATE_LOCK__enumvalues = { + 0: 'DCP_CURSOR_UPDATE_LOCK_FALSE', + 1: 'DCP_CURSOR_UPDATE_LOCK_TRUE', +} +DCP_CURSOR_UPDATE_LOCK_FALSE = 0 +DCP_CURSOR_UPDATE_LOCK_TRUE = 1 +DCP_CURSOR_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE' +DCP_CURSOR_DISABLE_MULTIPLE_UPDATE__enumvalues = { + 0: 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE', + 1: 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE', +} +DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE = 0 +DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE = 1 +DCP_CURSOR_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_UPDATE_STEREO_MODE' +DCP_CURSOR_UPDATE_STEREO_MODE__enumvalues = { + 0: 'DCP_CURSOR_UPDATE_STEREO_MODE_BOTH', + 1: 'DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY', + 2: 'DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED', + 3: 'DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY', +} +DCP_CURSOR_UPDATE_STEREO_MODE_BOTH = 0 +DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY = 1 +DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED = 2 +DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY = 3 +DCP_CURSOR_UPDATE_STEREO_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CUR2_INV_TRANS_CLAMP' +DCP_CUR2_INV_TRANS_CLAMP__enumvalues = { + 0: 'DCP_CUR2_INV_TRANS_CLAMP_FALSE', + 1: 'DCP_CUR2_INV_TRANS_CLAMP_TRUE', +} +DCP_CUR2_INV_TRANS_CLAMP_FALSE = 0 +DCP_CUR2_INV_TRANS_CLAMP_TRUE = 1 +DCP_CUR2_INV_TRANS_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CUR_REQUEST_FILTER_DIS' +DCP_CUR_REQUEST_FILTER_DIS__enumvalues = { + 0: 'DCP_CUR_REQUEST_FILTER_DIS_FALSE', + 1: 'DCP_CUR_REQUEST_FILTER_DIS_TRUE', +} +DCP_CUR_REQUEST_FILTER_DIS_FALSE = 0 +DCP_CUR_REQUEST_FILTER_DIS_TRUE = 1 +DCP_CUR_REQUEST_FILTER_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_STEREO_EN' +DCP_CURSOR_STEREO_EN__enumvalues = { + 0: 'DCP_CURSOR_STEREO_EN_FALSE', + 1: 'DCP_CURSOR_STEREO_EN_TRUE', +} +DCP_CURSOR_STEREO_EN_FALSE = 0 +DCP_CURSOR_STEREO_EN_TRUE = 1 +DCP_CURSOR_STEREO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_STEREO_OFFSET_YNX' +DCP_CURSOR_STEREO_OFFSET_YNX__enumvalues = { + 0: 'DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION', + 1: 'DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION', +} +DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION = 0 +DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION = 1 +DCP_CURSOR_STEREO_OFFSET_YNX = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_RW_MODE' +DCP_DC_LUT_RW_MODE__enumvalues = { + 0: 'DCP_DC_LUT_RW_MODE_256_ENTRY', + 1: 'DCP_DC_LUT_RW_MODE_PWL', +} +DCP_DC_LUT_RW_MODE_256_ENTRY = 0 +DCP_DC_LUT_RW_MODE_PWL = 1 +DCP_DC_LUT_RW_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_VGA_ACCESS_ENABLE' +DCP_DC_LUT_VGA_ACCESS_ENABLE__enumvalues = { + 0: 'DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE', + 1: 'DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE', +} +DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE = 0 +DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE = 1 +DCP_DC_LUT_VGA_ACCESS_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_AUTOFILL' +DCP_DC_LUT_AUTOFILL__enumvalues = { + 0: 'DCP_DC_LUT_AUTOFILL_FALSE', + 1: 'DCP_DC_LUT_AUTOFILL_TRUE', +} +DCP_DC_LUT_AUTOFILL_FALSE = 0 +DCP_DC_LUT_AUTOFILL_TRUE = 1 +DCP_DC_LUT_AUTOFILL = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_AUTOFILL_DONE' +DCP_DC_LUT_AUTOFILL_DONE__enumvalues = { + 0: 'DCP_DC_LUT_AUTOFILL_DONE_FALSE', + 1: 'DCP_DC_LUT_AUTOFILL_DONE_TRUE', +} +DCP_DC_LUT_AUTOFILL_DONE_FALSE = 0 +DCP_DC_LUT_AUTOFILL_DONE_TRUE = 1 +DCP_DC_LUT_AUTOFILL_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_INC_B' +DCP_DC_LUT_INC_B__enumvalues = { + 0: 'DCP_DC_LUT_INC_B_NA', + 1: 'DCP_DC_LUT_INC_B_2', + 2: 'DCP_DC_LUT_INC_B_4', + 3: 'DCP_DC_LUT_INC_B_8', + 4: 'DCP_DC_LUT_INC_B_16', + 5: 'DCP_DC_LUT_INC_B_32', + 6: 'DCP_DC_LUT_INC_B_64', + 7: 'DCP_DC_LUT_INC_B_128', + 8: 'DCP_DC_LUT_INC_B_256', + 9: 'DCP_DC_LUT_INC_B_512', +} +DCP_DC_LUT_INC_B_NA = 0 +DCP_DC_LUT_INC_B_2 = 1 +DCP_DC_LUT_INC_B_4 = 2 +DCP_DC_LUT_INC_B_8 = 3 +DCP_DC_LUT_INC_B_16 = 4 +DCP_DC_LUT_INC_B_32 = 5 +DCP_DC_LUT_INC_B_64 = 6 +DCP_DC_LUT_INC_B_128 = 7 +DCP_DC_LUT_INC_B_256 = 8 +DCP_DC_LUT_INC_B_512 = 9 +DCP_DC_LUT_INC_B = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_DATA_B_SIGNED_EN' +DCP_DC_LUT_DATA_B_SIGNED_EN__enumvalues = { + 0: 'DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE', + 1: 'DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE', +} +DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE = 0 +DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE = 1 +DCP_DC_LUT_DATA_B_SIGNED_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN' +DCP_DC_LUT_DATA_B_FLOAT_POINT_EN__enumvalues = { + 0: 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE', + 1: 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE', +} +DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE = 0 +DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE = 1 +DCP_DC_LUT_DATA_B_FLOAT_POINT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_DATA_B_FORMAT' +DCP_DC_LUT_DATA_B_FORMAT__enumvalues = { + 0: 'DCP_DC_LUT_DATA_B_FORMAT_U0P10', + 1: 'DCP_DC_LUT_DATA_B_FORMAT_S1P10', + 2: 'DCP_DC_LUT_DATA_B_FORMAT_U1P11', + 3: 'DCP_DC_LUT_DATA_B_FORMAT_U0P12', +} +DCP_DC_LUT_DATA_B_FORMAT_U0P10 = 0 +DCP_DC_LUT_DATA_B_FORMAT_S1P10 = 1 +DCP_DC_LUT_DATA_B_FORMAT_U1P11 = 2 +DCP_DC_LUT_DATA_B_FORMAT_U0P12 = 3 +DCP_DC_LUT_DATA_B_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_INC_G' +DCP_DC_LUT_INC_G__enumvalues = { + 0: 'DCP_DC_LUT_INC_G_NA', + 1: 'DCP_DC_LUT_INC_G_2', + 2: 'DCP_DC_LUT_INC_G_4', + 3: 'DCP_DC_LUT_INC_G_8', + 4: 'DCP_DC_LUT_INC_G_16', + 5: 'DCP_DC_LUT_INC_G_32', + 6: 'DCP_DC_LUT_INC_G_64', + 7: 'DCP_DC_LUT_INC_G_128', + 8: 'DCP_DC_LUT_INC_G_256', + 9: 'DCP_DC_LUT_INC_G_512', +} +DCP_DC_LUT_INC_G_NA = 0 +DCP_DC_LUT_INC_G_2 = 1 +DCP_DC_LUT_INC_G_4 = 2 +DCP_DC_LUT_INC_G_8 = 3 +DCP_DC_LUT_INC_G_16 = 4 +DCP_DC_LUT_INC_G_32 = 5 +DCP_DC_LUT_INC_G_64 = 6 +DCP_DC_LUT_INC_G_128 = 7 +DCP_DC_LUT_INC_G_256 = 8 +DCP_DC_LUT_INC_G_512 = 9 +DCP_DC_LUT_INC_G = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_DATA_G_SIGNED_EN' +DCP_DC_LUT_DATA_G_SIGNED_EN__enumvalues = { + 0: 'DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE', + 1: 'DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE', +} +DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE = 0 +DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE = 1 +DCP_DC_LUT_DATA_G_SIGNED_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN' +DCP_DC_LUT_DATA_G_FLOAT_POINT_EN__enumvalues = { + 0: 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE', + 1: 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE', +} +DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE = 0 +DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE = 1 +DCP_DC_LUT_DATA_G_FLOAT_POINT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_DATA_G_FORMAT' +DCP_DC_LUT_DATA_G_FORMAT__enumvalues = { + 0: 'DCP_DC_LUT_DATA_G_FORMAT_U0P10', + 1: 'DCP_DC_LUT_DATA_G_FORMAT_S1P10', + 2: 'DCP_DC_LUT_DATA_G_FORMAT_U1P11', + 3: 'DCP_DC_LUT_DATA_G_FORMAT_U0P12', +} +DCP_DC_LUT_DATA_G_FORMAT_U0P10 = 0 +DCP_DC_LUT_DATA_G_FORMAT_S1P10 = 1 +DCP_DC_LUT_DATA_G_FORMAT_U1P11 = 2 +DCP_DC_LUT_DATA_G_FORMAT_U0P12 = 3 +DCP_DC_LUT_DATA_G_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_INC_R' +DCP_DC_LUT_INC_R__enumvalues = { + 0: 'DCP_DC_LUT_INC_R_NA', + 1: 'DCP_DC_LUT_INC_R_2', + 2: 'DCP_DC_LUT_INC_R_4', + 3: 'DCP_DC_LUT_INC_R_8', + 4: 'DCP_DC_LUT_INC_R_16', + 5: 'DCP_DC_LUT_INC_R_32', + 6: 'DCP_DC_LUT_INC_R_64', + 7: 'DCP_DC_LUT_INC_R_128', + 8: 'DCP_DC_LUT_INC_R_256', + 9: 'DCP_DC_LUT_INC_R_512', +} +DCP_DC_LUT_INC_R_NA = 0 +DCP_DC_LUT_INC_R_2 = 1 +DCP_DC_LUT_INC_R_4 = 2 +DCP_DC_LUT_INC_R_8 = 3 +DCP_DC_LUT_INC_R_16 = 4 +DCP_DC_LUT_INC_R_32 = 5 +DCP_DC_LUT_INC_R_64 = 6 +DCP_DC_LUT_INC_R_128 = 7 +DCP_DC_LUT_INC_R_256 = 8 +DCP_DC_LUT_INC_R_512 = 9 +DCP_DC_LUT_INC_R = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_DATA_R_SIGNED_EN' +DCP_DC_LUT_DATA_R_SIGNED_EN__enumvalues = { + 0: 'DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE', + 1: 'DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE', +} +DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE = 0 +DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE = 1 +DCP_DC_LUT_DATA_R_SIGNED_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN' +DCP_DC_LUT_DATA_R_FLOAT_POINT_EN__enumvalues = { + 0: 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE', + 1: 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE', +} +DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE = 0 +DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE = 1 +DCP_DC_LUT_DATA_R_FLOAT_POINT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_DATA_R_FORMAT' +DCP_DC_LUT_DATA_R_FORMAT__enumvalues = { + 0: 'DCP_DC_LUT_DATA_R_FORMAT_U0P10', + 1: 'DCP_DC_LUT_DATA_R_FORMAT_S1P10', + 2: 'DCP_DC_LUT_DATA_R_FORMAT_U1P11', + 3: 'DCP_DC_LUT_DATA_R_FORMAT_U0P12', +} +DCP_DC_LUT_DATA_R_FORMAT_U0P10 = 0 +DCP_DC_LUT_DATA_R_FORMAT_S1P10 = 1 +DCP_DC_LUT_DATA_R_FORMAT_U1P11 = 2 +DCP_DC_LUT_DATA_R_FORMAT_U0P12 = 3 +DCP_DC_LUT_DATA_R_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CRC_ENABLE' +DCP_CRC_ENABLE__enumvalues = { + 0: 'DCP_CRC_ENABLE_FALSE', + 1: 'DCP_CRC_ENABLE_TRUE', +} +DCP_CRC_ENABLE_FALSE = 0 +DCP_CRC_ENABLE_TRUE = 1 +DCP_CRC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CRC_SOURCE_SEL' +DCP_CRC_SOURCE_SEL__enumvalues = { + 0: 'DCP_CRC_SOURCE_SEL_OUTPUT_PIX', + 1: 'DCP_CRC_SOURCE_SEL_INPUT_L32', + 2: 'DCP_CRC_SOURCE_SEL_INPUT_H32', + 4: 'DCP_CRC_SOURCE_SEL_OUTPUT_CNTL', +} +DCP_CRC_SOURCE_SEL_OUTPUT_PIX = 0 +DCP_CRC_SOURCE_SEL_INPUT_L32 = 1 +DCP_CRC_SOURCE_SEL_INPUT_H32 = 2 +DCP_CRC_SOURCE_SEL_OUTPUT_CNTL = 4 +DCP_CRC_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CRC_LINE_SEL' +DCP_CRC_LINE_SEL__enumvalues = { + 0: 'DCP_CRC_LINE_SEL_RESERVED', + 1: 'DCP_CRC_LINE_SEL_EVEN', + 2: 'DCP_CRC_LINE_SEL_ODD', + 3: 'DCP_CRC_LINE_SEL_BOTH', +} +DCP_CRC_LINE_SEL_RESERVED = 0 +DCP_CRC_LINE_SEL_EVEN = 1 +DCP_CRC_LINE_SEL_ODD = 2 +DCP_CRC_LINE_SEL_BOTH = 3 +DCP_CRC_LINE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_FLIP_RATE' +DCP_GRPH_FLIP_RATE__enumvalues = { + 0: 'DCP_GRPH_FLIP_RATE_1FRAME', + 1: 'DCP_GRPH_FLIP_RATE_2FRAME', + 2: 'DCP_GRPH_FLIP_RATE_3FRAME', + 3: 'DCP_GRPH_FLIP_RATE_4FRAME', + 4: 'DCP_GRPH_FLIP_RATE_5FRAME', + 5: 'DCP_GRPH_FLIP_RATE_6FRAME', + 6: 'DCP_GRPH_FLIP_RATE_7FRAME', + 7: 'DCP_GRPH_FLIP_RATE_8FRAME', +} +DCP_GRPH_FLIP_RATE_1FRAME = 0 +DCP_GRPH_FLIP_RATE_2FRAME = 1 +DCP_GRPH_FLIP_RATE_3FRAME = 2 +DCP_GRPH_FLIP_RATE_4FRAME = 3 +DCP_GRPH_FLIP_RATE_5FRAME = 4 +DCP_GRPH_FLIP_RATE_6FRAME = 5 +DCP_GRPH_FLIP_RATE_7FRAME = 6 +DCP_GRPH_FLIP_RATE_8FRAME = 7 +DCP_GRPH_FLIP_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_FLIP_RATE_ENABLE' +DCP_GRPH_FLIP_RATE_ENABLE__enumvalues = { + 0: 'DCP_GRPH_FLIP_RATE_ENABLE_FALSE', + 1: 'DCP_GRPH_FLIP_RATE_ENABLE_TRUE', +} +DCP_GRPH_FLIP_RATE_ENABLE_FALSE = 0 +DCP_GRPH_FLIP_RATE_ENABLE_TRUE = 1 +DCP_GRPH_FLIP_RATE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GSL0_EN' +DCP_GSL0_EN__enumvalues = { + 0: 'DCP_GSL0_EN_FALSE', + 1: 'DCP_GSL0_EN_TRUE', +} +DCP_GSL0_EN_FALSE = 0 +DCP_GSL0_EN_TRUE = 1 +DCP_GSL0_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GSL1_EN' +DCP_GSL1_EN__enumvalues = { + 0: 'DCP_GSL1_EN_FALSE', + 1: 'DCP_GSL1_EN_TRUE', +} +DCP_GSL1_EN_FALSE = 0 +DCP_GSL1_EN_TRUE = 1 +DCP_GSL1_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GSL2_EN' +DCP_GSL2_EN__enumvalues = { + 0: 'DCP_GSL2_EN_FALSE', + 1: 'DCP_GSL2_EN_TRUE', +} +DCP_GSL2_EN_FALSE = 0 +DCP_GSL2_EN_TRUE = 1 +DCP_GSL2_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GSL_MASTER_EN' +DCP_GSL_MASTER_EN__enumvalues = { + 0: 'DCP_GSL_MASTER_EN_FALSE', + 1: 'DCP_GSL_MASTER_EN_TRUE', +} +DCP_GSL_MASTER_EN_FALSE = 0 +DCP_GSL_MASTER_EN_TRUE = 1 +DCP_GSL_MASTER_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GSL_XDMA_GROUP' +DCP_GSL_XDMA_GROUP__enumvalues = { + 0: 'DCP_GSL_XDMA_GROUP_VSYNC', + 1: 'DCP_GSL_XDMA_GROUP_HSYNC0', + 2: 'DCP_GSL_XDMA_GROUP_HSYNC1', + 3: 'DCP_GSL_XDMA_GROUP_HSYNC2', +} +DCP_GSL_XDMA_GROUP_VSYNC = 0 +DCP_GSL_XDMA_GROUP_HSYNC0 = 1 +DCP_GSL_XDMA_GROUP_HSYNC1 = 2 +DCP_GSL_XDMA_GROUP_HSYNC2 = 3 +DCP_GSL_XDMA_GROUP = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN' +DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__enumvalues = { + 0: 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE', + 1: 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE', +} +DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE = 0 +DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE = 1 +DCP_GSL_XDMA_GROUP_UNDERFLOW_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GSL_SYNC_SOURCE' +DCP_GSL_SYNC_SOURCE__enumvalues = { + 0: 'DCP_GSL_SYNC_SOURCE_FLIP', + 1: 'DCP_GSL_SYNC_SOURCE_PHASE0', + 2: 'DCP_GSL_SYNC_SOURCE_RESET', + 3: 'DCP_GSL_SYNC_SOURCE_PHASE1', +} +DCP_GSL_SYNC_SOURCE_FLIP = 0 +DCP_GSL_SYNC_SOURCE_PHASE0 = 1 +DCP_GSL_SYNC_SOURCE_RESET = 2 +DCP_GSL_SYNC_SOURCE_PHASE1 = 3 +DCP_GSL_SYNC_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC' +DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__enumvalues = { + 0: 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_DIS', + 1: 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_EN', +} +DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_DIS = 0 +DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_EN = 1 +DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING' +DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__enumvalues = { + 0: 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE', + 1: 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE', +} +DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE = 0 +DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE = 1 +DCP_GSL_DELAY_SURFACE_UPDATE_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_TEST_DEBUG_WRITE_EN' +DCP_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'DCP_TEST_DEBUG_WRITE_EN_FALSE', + 1: 'DCP_TEST_DEBUG_WRITE_EN_TRUE', +} +DCP_TEST_DEBUG_WRITE_EN_FALSE = 0 +DCP_TEST_DEBUG_WRITE_EN_TRUE = 1 +DCP_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_STEREOSYNC_FLIP_EN' +DCP_GRPH_STEREOSYNC_FLIP_EN__enumvalues = { + 0: 'DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE', + 1: 'DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE', +} +DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE = 0 +DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE = 1 +DCP_GRPH_STEREOSYNC_FLIP_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_STEREOSYNC_FLIP_MODE' +DCP_GRPH_STEREOSYNC_FLIP_MODE__enumvalues = { + 0: 'DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP', + 1: 'DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0', + 2: 'DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET', + 3: 'DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1', +} +DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP = 0 +DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0 = 1 +DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET = 2 +DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1 = 3 +DCP_GRPH_STEREOSYNC_FLIP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE' +DCP_GRPH_STEREOSYNC_SELECT_DISABLE__enumvalues = { + 0: 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE', + 1: 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE', +} +DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE = 0 +DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE = 1 +DCP_GRPH_STEREOSYNC_SELECT_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_ROTATION_ANGLE' +DCP_GRPH_ROTATION_ANGLE__enumvalues = { + 0: 'DCP_GRPH_ROTATION_ANGLE_0', + 1: 'DCP_GRPH_ROTATION_ANGLE_90', + 2: 'DCP_GRPH_ROTATION_ANGLE_180', + 3: 'DCP_GRPH_ROTATION_ANGLE_270', +} +DCP_GRPH_ROTATION_ANGLE_0 = 0 +DCP_GRPH_ROTATION_ANGLE_90 = 1 +DCP_GRPH_ROTATION_ANGLE_180 = 2 +DCP_GRPH_ROTATION_ANGLE_270 = 3 +DCP_GRPH_ROTATION_ANGLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN' +DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__enumvalues = { + 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE', + 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE', +} +DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE = 0 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE = 1 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE' +DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__enumvalues = { + 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM', + 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE', +} +DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM = 0 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE = 1 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_REGAMMA_MODE' +DCP_GRPH_REGAMMA_MODE__enumvalues = { + 0: 'DCP_GRPH_REGAMMA_MODE_BYPASS', + 1: 'DCP_GRPH_REGAMMA_MODE_SRGB', + 2: 'DCP_GRPH_REGAMMA_MODE_XVYCC', + 3: 'DCP_GRPH_REGAMMA_MODE_PROGA', + 4: 'DCP_GRPH_REGAMMA_MODE_PROGB', +} +DCP_GRPH_REGAMMA_MODE_BYPASS = 0 +DCP_GRPH_REGAMMA_MODE_SRGB = 1 +DCP_GRPH_REGAMMA_MODE_XVYCC = 2 +DCP_GRPH_REGAMMA_MODE_PROGA = 3 +DCP_GRPH_REGAMMA_MODE_PROGB = 4 +DCP_GRPH_REGAMMA_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_ALPHA_ROUND_TRUNC_MODE' +DCP_ALPHA_ROUND_TRUNC_MODE__enumvalues = { + 0: 'DCP_ALPHA_ROUND_TRUNC_MODE_ROUND', + 1: 'DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC', +} +DCP_ALPHA_ROUND_TRUNC_MODE_ROUND = 0 +DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC = 1 +DCP_ALPHA_ROUND_TRUNC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_ALPHA_BLND_ENA' +DCP_CURSOR_ALPHA_BLND_ENA__enumvalues = { + 0: 'DCP_CURSOR_ALPHA_BLND_ENA_FALSE', + 1: 'DCP_CURSOR_ALPHA_BLND_ENA_TRUE', +} +DCP_CURSOR_ALPHA_BLND_ENA_FALSE = 0 +DCP_CURSOR_ALPHA_BLND_ENA_TRUE = 1 +DCP_CURSOR_ALPHA_BLND_ENA = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK' +DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__enumvalues = { + 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE', + 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE', +} +DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE = 0 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE = 1 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK' +DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__enumvalues = { + 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE', + 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE', +} +DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE = 0 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE = 1 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK' +DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__enumvalues = { + 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE', + 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE', +} +DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE = 0 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE = 1 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK' +DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__enumvalues = { + 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE', + 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE', +} +DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE = 0 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE = 1 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SURFACE_COUNTER_EN' +DCP_GRPH_SURFACE_COUNTER_EN__enumvalues = { + 0: 'DCP_GRPH_SURFACE_COUNTER_EN_DISABLE', + 1: 'DCP_GRPH_SURFACE_COUNTER_EN_ENABLE', +} +DCP_GRPH_SURFACE_COUNTER_EN_DISABLE = 0 +DCP_GRPH_SURFACE_COUNTER_EN_ENABLE = 1 +DCP_GRPH_SURFACE_COUNTER_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT' +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT__enumvalues = { + 0: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0', + 1: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1', + 2: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2', + 3: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3', + 4: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4', + 5: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5', + 6: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6', + 7: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7', + 8: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8', + 9: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9', + 10: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10', + 11: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11', +} +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0 = 0 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1 = 1 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2 = 2 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3 = 3 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4 = 4 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5 = 5 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6 = 6 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7 = 7 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8 = 8 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9 = 9 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10 = 10 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11 = 11 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED' +DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__enumvalues = { + 0: 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO', + 1: 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES', +} +DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO = 0 +DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES = 1 +DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR' +DCP_GRPH_XDMA_FLIP_TYPE_CLEAR__enumvalues = { + 0: 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_DISABLE', + 1: 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_ENABLE', +} +DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_DISABLE = 0 +DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_ENABLE = 1 +DCP_GRPH_XDMA_FLIP_TYPE_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_DRR_MODE_ENABLE' +DCP_GRPH_XDMA_DRR_MODE_ENABLE__enumvalues = { + 0: 'DCP_GRPH_XDMA_DRR_MODE_ENABLE_DISABLE', + 1: 'DCP_GRPH_XDMA_DRR_MODE_ENABLE_ENABLE', +} +DCP_GRPH_XDMA_DRR_MODE_ENABLE_DISABLE = 0 +DCP_GRPH_XDMA_DRR_MODE_ENABLE_ENABLE = 1 +DCP_GRPH_XDMA_DRR_MODE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE' +DCP_GRPH_XDMA_MULTIFLIP_ENABLE__enumvalues = { + 0: 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE_DISABLE', + 1: 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE_ENABLE', +} +DCP_GRPH_XDMA_MULTIFLIP_ENABLE_DISABLE = 0 +DCP_GRPH_XDMA_MULTIFLIP_ENABLE_ENABLE = 1 +DCP_GRPH_XDMA_MULTIFLIP_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK' +DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK__enumvalues = { + 0: 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_FALSE', + 1: 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_TRUE', +} +DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_FALSE = 0 +DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_TRUE = 1 +DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK' +DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK__enumvalues = { + 0: 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_FALSE', + 1: 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_TRUE', +} +DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_FALSE = 0 +DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_TRUE = 1 +DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CVALUE_SEL' +PERFCOUNTER_CVALUE_SEL__enumvalues = { + 0: 'PERFCOUNTER_CVALUE_SEL_47_0', + 1: 'PERFCOUNTER_CVALUE_SEL_15_0', + 2: 'PERFCOUNTER_CVALUE_SEL_31_16', + 3: 'PERFCOUNTER_CVALUE_SEL_47_32', + 4: 'PERFCOUNTER_CVALUE_SEL_11_0', + 5: 'PERFCOUNTER_CVALUE_SEL_23_12', + 6: 'PERFCOUNTER_CVALUE_SEL_35_24', + 7: 'PERFCOUNTER_CVALUE_SEL_47_36', +} +PERFCOUNTER_CVALUE_SEL_47_0 = 0 +PERFCOUNTER_CVALUE_SEL_15_0 = 1 +PERFCOUNTER_CVALUE_SEL_31_16 = 2 +PERFCOUNTER_CVALUE_SEL_47_32 = 3 +PERFCOUNTER_CVALUE_SEL_11_0 = 4 +PERFCOUNTER_CVALUE_SEL_23_12 = 5 +PERFCOUNTER_CVALUE_SEL_35_24 = 6 +PERFCOUNTER_CVALUE_SEL_47_36 = 7 +PERFCOUNTER_CVALUE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_INC_MODE' +PERFCOUNTER_INC_MODE__enumvalues = { + 0: 'PERFCOUNTER_INC_MODE_MULTI_BIT', + 1: 'PERFCOUNTER_INC_MODE_BOTH_EDGE', + 2: 'PERFCOUNTER_INC_MODE_LSB', + 3: 'PERFCOUNTER_INC_MODE_POS_EDGE', + 4: 'PERFCOUNTER_INC_MODE_NEG_EDGE', +} +PERFCOUNTER_INC_MODE_MULTI_BIT = 0 +PERFCOUNTER_INC_MODE_BOTH_EDGE = 1 +PERFCOUNTER_INC_MODE_LSB = 2 +PERFCOUNTER_INC_MODE_POS_EDGE = 3 +PERFCOUNTER_INC_MODE_NEG_EDGE = 4 +PERFCOUNTER_INC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_HW_CNTL_SEL' +PERFCOUNTER_HW_CNTL_SEL__enumvalues = { + 0: 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', + 1: 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', +} +PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0 +PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 1 +PERFCOUNTER_HW_CNTL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_RUNEN_MODE' +PERFCOUNTER_RUNEN_MODE__enumvalues = { + 0: 'PERFCOUNTER_RUNEN_MODE_LEVEL', + 1: 'PERFCOUNTER_RUNEN_MODE_EDGE', +} +PERFCOUNTER_RUNEN_MODE_LEVEL = 0 +PERFCOUNTER_RUNEN_MODE_EDGE = 1 +PERFCOUNTER_RUNEN_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNTOFF_START_DIS' +PERFCOUNTER_CNTOFF_START_DIS__enumvalues = { + 0: 'PERFCOUNTER_CNTOFF_START_ENABLE', + 1: 'PERFCOUNTER_CNTOFF_START_DISABLE', +} +PERFCOUNTER_CNTOFF_START_ENABLE = 0 +PERFCOUNTER_CNTOFF_START_DISABLE = 1 +PERFCOUNTER_CNTOFF_START_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_RESTART_EN' +PERFCOUNTER_RESTART_EN__enumvalues = { + 0: 'PERFCOUNTER_RESTART_DISABLE', + 1: 'PERFCOUNTER_RESTART_ENABLE', +} +PERFCOUNTER_RESTART_DISABLE = 0 +PERFCOUNTER_RESTART_ENABLE = 1 +PERFCOUNTER_RESTART_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_INT_EN' +PERFCOUNTER_INT_EN__enumvalues = { + 0: 'PERFCOUNTER_INT_DISABLE', + 1: 'PERFCOUNTER_INT_ENABLE', +} +PERFCOUNTER_INT_DISABLE = 0 +PERFCOUNTER_INT_ENABLE = 1 +PERFCOUNTER_INT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_OFF_MASK' +PERFCOUNTER_OFF_MASK__enumvalues = { + 0: 'PERFCOUNTER_OFF_MASK_DISABLE', + 1: 'PERFCOUNTER_OFF_MASK_ENABLE', +} +PERFCOUNTER_OFF_MASK_DISABLE = 0 +PERFCOUNTER_OFF_MASK_ENABLE = 1 +PERFCOUNTER_OFF_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_ACTIVE' +PERFCOUNTER_ACTIVE__enumvalues = { + 0: 'PERFCOUNTER_IS_IDLE', + 1: 'PERFCOUNTER_IS_ACTIVE', +} +PERFCOUNTER_IS_IDLE = 0 +PERFCOUNTER_IS_ACTIVE = 1 +PERFCOUNTER_ACTIVE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_INT_TYPE' +PERFCOUNTER_INT_TYPE__enumvalues = { + 0: 'PERFCOUNTER_INT_TYPE_LEVEL', + 1: 'PERFCOUNTER_INT_TYPE_PULSE', +} +PERFCOUNTER_INT_TYPE_LEVEL = 0 +PERFCOUNTER_INT_TYPE_PULSE = 1 +PERFCOUNTER_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_COUNTED_VALUE_TYPE' +PERFCOUNTER_COUNTED_VALUE_TYPE__enumvalues = { + 0: 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', + 1: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', + 2: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', +} +PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0 +PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 1 +PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 2 +PERFCOUNTER_COUNTED_VALUE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNTL_SEL' +PERFCOUNTER_CNTL_SEL__enumvalues = { + 0: 'PERFCOUNTER_CNTL_SEL_0', + 1: 'PERFCOUNTER_CNTL_SEL_1', + 2: 'PERFCOUNTER_CNTL_SEL_2', + 3: 'PERFCOUNTER_CNTL_SEL_3', + 4: 'PERFCOUNTER_CNTL_SEL_4', + 5: 'PERFCOUNTER_CNTL_SEL_5', + 6: 'PERFCOUNTER_CNTL_SEL_6', + 7: 'PERFCOUNTER_CNTL_SEL_7', +} +PERFCOUNTER_CNTL_SEL_0 = 0 +PERFCOUNTER_CNTL_SEL_1 = 1 +PERFCOUNTER_CNTL_SEL_2 = 2 +PERFCOUNTER_CNTL_SEL_3 = 3 +PERFCOUNTER_CNTL_SEL_4 = 4 +PERFCOUNTER_CNTL_SEL_5 = 5 +PERFCOUNTER_CNTL_SEL_6 = 6 +PERFCOUNTER_CNTL_SEL_7 = 7 +PERFCOUNTER_CNTL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT0_STATE' +PERFCOUNTER_CNT0_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT0_STATE_RESET', + 1: 'PERFCOUNTER_CNT0_STATE_START', + 2: 'PERFCOUNTER_CNT0_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT0_STATE_HW', +} +PERFCOUNTER_CNT0_STATE_RESET = 0 +PERFCOUNTER_CNT0_STATE_START = 1 +PERFCOUNTER_CNT0_STATE_FREEZE = 2 +PERFCOUNTER_CNT0_STATE_HW = 3 +PERFCOUNTER_CNT0_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL0' +PERFCOUNTER_STATE_SEL0__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL0_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL0_LOCAL', +} +PERFCOUNTER_STATE_SEL0_GLOBAL = 0 +PERFCOUNTER_STATE_SEL0_LOCAL = 1 +PERFCOUNTER_STATE_SEL0 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT1_STATE' +PERFCOUNTER_CNT1_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT1_STATE_RESET', + 1: 'PERFCOUNTER_CNT1_STATE_START', + 2: 'PERFCOUNTER_CNT1_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT1_STATE_HW', +} +PERFCOUNTER_CNT1_STATE_RESET = 0 +PERFCOUNTER_CNT1_STATE_START = 1 +PERFCOUNTER_CNT1_STATE_FREEZE = 2 +PERFCOUNTER_CNT1_STATE_HW = 3 +PERFCOUNTER_CNT1_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL1' +PERFCOUNTER_STATE_SEL1__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL1_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL1_LOCAL', +} +PERFCOUNTER_STATE_SEL1_GLOBAL = 0 +PERFCOUNTER_STATE_SEL1_LOCAL = 1 +PERFCOUNTER_STATE_SEL1 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT2_STATE' +PERFCOUNTER_CNT2_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT2_STATE_RESET', + 1: 'PERFCOUNTER_CNT2_STATE_START', + 2: 'PERFCOUNTER_CNT2_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT2_STATE_HW', +} +PERFCOUNTER_CNT2_STATE_RESET = 0 +PERFCOUNTER_CNT2_STATE_START = 1 +PERFCOUNTER_CNT2_STATE_FREEZE = 2 +PERFCOUNTER_CNT2_STATE_HW = 3 +PERFCOUNTER_CNT2_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL2' +PERFCOUNTER_STATE_SEL2__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL2_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL2_LOCAL', +} +PERFCOUNTER_STATE_SEL2_GLOBAL = 0 +PERFCOUNTER_STATE_SEL2_LOCAL = 1 +PERFCOUNTER_STATE_SEL2 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT3_STATE' +PERFCOUNTER_CNT3_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT3_STATE_RESET', + 1: 'PERFCOUNTER_CNT3_STATE_START', + 2: 'PERFCOUNTER_CNT3_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT3_STATE_HW', +} +PERFCOUNTER_CNT3_STATE_RESET = 0 +PERFCOUNTER_CNT3_STATE_START = 1 +PERFCOUNTER_CNT3_STATE_FREEZE = 2 +PERFCOUNTER_CNT3_STATE_HW = 3 +PERFCOUNTER_CNT3_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL3' +PERFCOUNTER_STATE_SEL3__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL3_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL3_LOCAL', +} +PERFCOUNTER_STATE_SEL3_GLOBAL = 0 +PERFCOUNTER_STATE_SEL3_LOCAL = 1 +PERFCOUNTER_STATE_SEL3 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT4_STATE' +PERFCOUNTER_CNT4_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT4_STATE_RESET', + 1: 'PERFCOUNTER_CNT4_STATE_START', + 2: 'PERFCOUNTER_CNT4_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT4_STATE_HW', +} +PERFCOUNTER_CNT4_STATE_RESET = 0 +PERFCOUNTER_CNT4_STATE_START = 1 +PERFCOUNTER_CNT4_STATE_FREEZE = 2 +PERFCOUNTER_CNT4_STATE_HW = 3 +PERFCOUNTER_CNT4_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL4' +PERFCOUNTER_STATE_SEL4__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL4_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL4_LOCAL', +} +PERFCOUNTER_STATE_SEL4_GLOBAL = 0 +PERFCOUNTER_STATE_SEL4_LOCAL = 1 +PERFCOUNTER_STATE_SEL4 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT5_STATE' +PERFCOUNTER_CNT5_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT5_STATE_RESET', + 1: 'PERFCOUNTER_CNT5_STATE_START', + 2: 'PERFCOUNTER_CNT5_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT5_STATE_HW', +} +PERFCOUNTER_CNT5_STATE_RESET = 0 +PERFCOUNTER_CNT5_STATE_START = 1 +PERFCOUNTER_CNT5_STATE_FREEZE = 2 +PERFCOUNTER_CNT5_STATE_HW = 3 +PERFCOUNTER_CNT5_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL5' +PERFCOUNTER_STATE_SEL5__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL5_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL5_LOCAL', +} +PERFCOUNTER_STATE_SEL5_GLOBAL = 0 +PERFCOUNTER_STATE_SEL5_LOCAL = 1 +PERFCOUNTER_STATE_SEL5 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT6_STATE' +PERFCOUNTER_CNT6_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT6_STATE_RESET', + 1: 'PERFCOUNTER_CNT6_STATE_START', + 2: 'PERFCOUNTER_CNT6_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT6_STATE_HW', +} +PERFCOUNTER_CNT6_STATE_RESET = 0 +PERFCOUNTER_CNT6_STATE_START = 1 +PERFCOUNTER_CNT6_STATE_FREEZE = 2 +PERFCOUNTER_CNT6_STATE_HW = 3 +PERFCOUNTER_CNT6_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL6' +PERFCOUNTER_STATE_SEL6__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL6_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL6_LOCAL', +} +PERFCOUNTER_STATE_SEL6_GLOBAL = 0 +PERFCOUNTER_STATE_SEL6_LOCAL = 1 +PERFCOUNTER_STATE_SEL6 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT7_STATE' +PERFCOUNTER_CNT7_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT7_STATE_RESET', + 1: 'PERFCOUNTER_CNT7_STATE_START', + 2: 'PERFCOUNTER_CNT7_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT7_STATE_HW', +} +PERFCOUNTER_CNT7_STATE_RESET = 0 +PERFCOUNTER_CNT7_STATE_START = 1 +PERFCOUNTER_CNT7_STATE_FREEZE = 2 +PERFCOUNTER_CNT7_STATE_HW = 3 +PERFCOUNTER_CNT7_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL7' +PERFCOUNTER_STATE_SEL7__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL7_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL7_LOCAL', +} +PERFCOUNTER_STATE_SEL7_GLOBAL = 0 +PERFCOUNTER_STATE_SEL7_LOCAL = 1 +PERFCOUNTER_STATE_SEL7 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_STATE' +PERFMON_STATE__enumvalues = { + 0: 'PERFMON_STATE_RESET', + 1: 'PERFMON_STATE_START', + 2: 'PERFMON_STATE_FREEZE', + 3: 'PERFMON_STATE_HW', +} +PERFMON_STATE_RESET = 0 +PERFMON_STATE_START = 1 +PERFMON_STATE_FREEZE = 2 +PERFMON_STATE_HW = 3 +PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_CNTOFF_AND_OR' +PERFMON_CNTOFF_AND_OR__enumvalues = { + 0: 'PERFMON_CNTOFF_OR', + 1: 'PERFMON_CNTOFF_AND', +} +PERFMON_CNTOFF_OR = 0 +PERFMON_CNTOFF_AND = 1 +PERFMON_CNTOFF_AND_OR = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_CNTOFF_INT_EN' +PERFMON_CNTOFF_INT_EN__enumvalues = { + 0: 'PERFMON_CNTOFF_INT_DISABLE', + 1: 'PERFMON_CNTOFF_INT_ENABLE', +} +PERFMON_CNTOFF_INT_DISABLE = 0 +PERFMON_CNTOFF_INT_ENABLE = 1 +PERFMON_CNTOFF_INT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_CNTOFF_INT_TYPE' +PERFMON_CNTOFF_INT_TYPE__enumvalues = { + 0: 'PERFMON_CNTOFF_INT_TYPE_LEVEL', + 1: 'PERFMON_CNTOFF_INT_TYPE_PULSE', +} +PERFMON_CNTOFF_INT_TYPE_LEVEL = 0 +PERFMON_CNTOFF_INT_TYPE_PULSE = 1 +PERFMON_CNTOFF_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_C_RAM_TAP_PAIR_IDX' +SCL_C_RAM_TAP_PAIR_IDX__enumvalues = { + 0: 'SCL_C_RAM_TAP_PAIR_ID0', + 1: 'SCL_C_RAM_TAP_PAIR_ID1', + 2: 'SCL_C_RAM_TAP_PAIR_ID2', + 3: 'SCL_C_RAM_TAP_PAIR_ID3', + 4: 'SCL_C_RAM_TAP_PAIR_ID4', +} +SCL_C_RAM_TAP_PAIR_ID0 = 0 +SCL_C_RAM_TAP_PAIR_ID1 = 1 +SCL_C_RAM_TAP_PAIR_ID2 = 2 +SCL_C_RAM_TAP_PAIR_ID3 = 3 +SCL_C_RAM_TAP_PAIR_ID4 = 4 +SCL_C_RAM_TAP_PAIR_IDX = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_C_RAM_PHASE' +SCL_C_RAM_PHASE__enumvalues = { + 0: 'SCL_C_RAM_PHASE_0', + 1: 'SCL_C_RAM_PHASE_1', + 2: 'SCL_C_RAM_PHASE_2', + 3: 'SCL_C_RAM_PHASE_3', + 4: 'SCL_C_RAM_PHASE_4', + 5: 'SCL_C_RAM_PHASE_5', + 6: 'SCL_C_RAM_PHASE_6', + 7: 'SCL_C_RAM_PHASE_7', + 8: 'SCL_C_RAM_PHASE_8', +} +SCL_C_RAM_PHASE_0 = 0 +SCL_C_RAM_PHASE_1 = 1 +SCL_C_RAM_PHASE_2 = 2 +SCL_C_RAM_PHASE_3 = 3 +SCL_C_RAM_PHASE_4 = 4 +SCL_C_RAM_PHASE_5 = 5 +SCL_C_RAM_PHASE_6 = 6 +SCL_C_RAM_PHASE_7 = 7 +SCL_C_RAM_PHASE_8 = 8 +SCL_C_RAM_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_C_RAM_FILTER_TYPE' +SCL_C_RAM_FILTER_TYPE__enumvalues = { + 0: 'SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT', + 1: 'SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT', + 2: 'SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT', + 3: 'SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT', +} +SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT = 0 +SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT = 1 +SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT = 2 +SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT = 3 +SCL_C_RAM_FILTER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_MODE_SEL' +SCL_MODE_SEL__enumvalues = { + 0: 'SCL_MODE_RGB_BYPASS', + 1: 'SCL_MODE_RGB_SCALING', + 2: 'SCL_MODE_YCBCR_SCALING', + 3: 'SCL_MODE_YCBCR_BYPASS', +} +SCL_MODE_RGB_BYPASS = 0 +SCL_MODE_RGB_SCALING = 1 +SCL_MODE_YCBCR_SCALING = 2 +SCL_MODE_YCBCR_BYPASS = 3 +SCL_MODE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_PSCL_EN' +SCL_PSCL_EN__enumvalues = { + 0: 'SCL_PSCL_DISABLE', + 1: 'SCL_PSCL_ENANBLE', +} +SCL_PSCL_DISABLE = 0 +SCL_PSCL_ENANBLE = 1 +SCL_PSCL_EN = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_V_NUM_OF_TAPS' +SCL_V_NUM_OF_TAPS__enumvalues = { + 0: 'SCL_V_NUM_OF_TAPS_1', + 1: 'SCL_V_NUM_OF_TAPS_2', + 2: 'SCL_V_NUM_OF_TAPS_3', + 3: 'SCL_V_NUM_OF_TAPS_4', + 4: 'SCL_V_NUM_OF_TAPS_5', + 5: 'SCL_V_NUM_OF_TAPS_6', +} +SCL_V_NUM_OF_TAPS_1 = 0 +SCL_V_NUM_OF_TAPS_2 = 1 +SCL_V_NUM_OF_TAPS_3 = 2 +SCL_V_NUM_OF_TAPS_4 = 3 +SCL_V_NUM_OF_TAPS_5 = 4 +SCL_V_NUM_OF_TAPS_6 = 5 +SCL_V_NUM_OF_TAPS = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_H_NUM_OF_TAPS' +SCL_H_NUM_OF_TAPS__enumvalues = { + 0: 'SCL_H_NUM_OF_TAPS_1', + 1: 'SCL_H_NUM_OF_TAPS_2', + 3: 'SCL_H_NUM_OF_TAPS_4', + 5: 'SCL_H_NUM_OF_TAPS_6', + 7: 'SCL_H_NUM_OF_TAPS_8', + 9: 'SCL_H_NUM_OF_TAPS_10', +} +SCL_H_NUM_OF_TAPS_1 = 0 +SCL_H_NUM_OF_TAPS_2 = 1 +SCL_H_NUM_OF_TAPS_4 = 3 +SCL_H_NUM_OF_TAPS_6 = 5 +SCL_H_NUM_OF_TAPS_8 = 7 +SCL_H_NUM_OF_TAPS_10 = 9 +SCL_H_NUM_OF_TAPS = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_BOUNDARY_MODE' +SCL_BOUNDARY_MODE__enumvalues = { + 0: 'SCL_BOUNDARY_MODE_BLACK', + 1: 'SCL_BOUNDARY_MODE_EDGE', +} +SCL_BOUNDARY_MODE_BLACK = 0 +SCL_BOUNDARY_MODE_EDGE = 1 +SCL_BOUNDARY_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_EARLY_EOL_MOD' +SCL_EARLY_EOL_MOD__enumvalues = { + 0: 'SCL_EARLY_EOL_MODE_CRTC', + 1: 'SCL_EARLY_EOL_MODE_INTERNAL', +} +SCL_EARLY_EOL_MODE_CRTC = 0 +SCL_EARLY_EOL_MODE_INTERNAL = 1 +SCL_EARLY_EOL_MOD = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_BYPASS_MODE' +SCL_BYPASS_MODE__enumvalues = { + 0: 'SCL_BYPASS_MODE_MC_MR', + 1: 'SCL_BYPASS_MODE_AC_NR', + 2: 'SCL_BYPASS_MODE_AC_AR', + 3: 'SCL_BYPASS_MODE_RESERVED', +} +SCL_BYPASS_MODE_MC_MR = 0 +SCL_BYPASS_MODE_AC_NR = 1 +SCL_BYPASS_MODE_AC_AR = 2 +SCL_BYPASS_MODE_RESERVED = 3 +SCL_BYPASS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_V_MANUAL_REPLICATE_FACTOR' +SCL_V_MANUAL_REPLICATE_FACTOR__enumvalues = { + 0: 'SCL_V_MANUAL_REPLICATE_FACTOR_1', + 1: 'SCL_V_MANUAL_REPLICATE_FACTOR_2', + 2: 'SCL_V_MANUAL_REPLICATE_FACTOR_3', + 3: 'SCL_V_MANUAL_REPLICATE_FACTOR_4', + 4: 'SCL_V_MANUAL_REPLICATE_FACTOR_5', + 5: 'SCL_V_MANUAL_REPLICATE_FACTOR_6', + 6: 'SCL_V_MANUAL_REPLICATE_FACTOR_7', + 7: 'SCL_V_MANUAL_REPLICATE_FACTOR_8', + 8: 'SCL_V_MANUAL_REPLICATE_FACTOR_9', + 9: 'SCL_V_MANUAL_REPLICATE_FACTOR_10', + 10: 'SCL_V_MANUAL_REPLICATE_FACTOR_11', + 11: 'SCL_V_MANUAL_REPLICATE_FACTOR_12', + 12: 'SCL_V_MANUAL_REPLICATE_FACTOR_13', + 13: 'SCL_V_MANUAL_REPLICATE_FACTOR_14', + 14: 'SCL_V_MANUAL_REPLICATE_FACTOR_15', + 15: 'SCL_V_MANUAL_REPLICATE_FACTOR_16', +} +SCL_V_MANUAL_REPLICATE_FACTOR_1 = 0 +SCL_V_MANUAL_REPLICATE_FACTOR_2 = 1 +SCL_V_MANUAL_REPLICATE_FACTOR_3 = 2 +SCL_V_MANUAL_REPLICATE_FACTOR_4 = 3 +SCL_V_MANUAL_REPLICATE_FACTOR_5 = 4 +SCL_V_MANUAL_REPLICATE_FACTOR_6 = 5 +SCL_V_MANUAL_REPLICATE_FACTOR_7 = 6 +SCL_V_MANUAL_REPLICATE_FACTOR_8 = 7 +SCL_V_MANUAL_REPLICATE_FACTOR_9 = 8 +SCL_V_MANUAL_REPLICATE_FACTOR_10 = 9 +SCL_V_MANUAL_REPLICATE_FACTOR_11 = 10 +SCL_V_MANUAL_REPLICATE_FACTOR_12 = 11 +SCL_V_MANUAL_REPLICATE_FACTOR_13 = 12 +SCL_V_MANUAL_REPLICATE_FACTOR_14 = 13 +SCL_V_MANUAL_REPLICATE_FACTOR_15 = 14 +SCL_V_MANUAL_REPLICATE_FACTOR_16 = 15 +SCL_V_MANUAL_REPLICATE_FACTOR = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_H_MANUAL_REPLICATE_FACTOR' +SCL_H_MANUAL_REPLICATE_FACTOR__enumvalues = { + 0: 'SCL_H_MANUAL_REPLICATE_FACTOR_1', + 1: 'SCL_H_MANUAL_REPLICATE_FACTOR_2', + 2: 'SCL_H_MANUAL_REPLICATE_FACTOR_3', + 3: 'SCL_H_MANUAL_REPLICATE_FACTOR_4', + 4: 'SCL_H_MANUAL_REPLICATE_FACTOR_5', + 5: 'SCL_H_MANUAL_REPLICATE_FACTOR_6', + 6: 'SCL_H_MANUAL_REPLICATE_FACTOR_7', + 7: 'SCL_H_MANUAL_REPLICATE_FACTOR_8', + 8: 'SCL_H_MANUAL_REPLICATE_FACTOR_9', + 9: 'SCL_H_MANUAL_REPLICATE_FACTOR_10', + 10: 'SCL_H_MANUAL_REPLICATE_FACTOR_11', + 11: 'SCL_H_MANUAL_REPLICATE_FACTOR_12', + 12: 'SCL_H_MANUAL_REPLICATE_FACTOR_13', + 13: 'SCL_H_MANUAL_REPLICATE_FACTOR_14', + 14: 'SCL_H_MANUAL_REPLICATE_FACTOR_15', + 15: 'SCL_H_MANUAL_REPLICATE_FACTOR_16', +} +SCL_H_MANUAL_REPLICATE_FACTOR_1 = 0 +SCL_H_MANUAL_REPLICATE_FACTOR_2 = 1 +SCL_H_MANUAL_REPLICATE_FACTOR_3 = 2 +SCL_H_MANUAL_REPLICATE_FACTOR_4 = 3 +SCL_H_MANUAL_REPLICATE_FACTOR_5 = 4 +SCL_H_MANUAL_REPLICATE_FACTOR_6 = 5 +SCL_H_MANUAL_REPLICATE_FACTOR_7 = 6 +SCL_H_MANUAL_REPLICATE_FACTOR_8 = 7 +SCL_H_MANUAL_REPLICATE_FACTOR_9 = 8 +SCL_H_MANUAL_REPLICATE_FACTOR_10 = 9 +SCL_H_MANUAL_REPLICATE_FACTOR_11 = 10 +SCL_H_MANUAL_REPLICATE_FACTOR_12 = 11 +SCL_H_MANUAL_REPLICATE_FACTOR_13 = 12 +SCL_H_MANUAL_REPLICATE_FACTOR_14 = 13 +SCL_H_MANUAL_REPLICATE_FACTOR_15 = 14 +SCL_H_MANUAL_REPLICATE_FACTOR_16 = 15 +SCL_H_MANUAL_REPLICATE_FACTOR = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_V_CALC_AUTO_RATIO_EN' +SCL_V_CALC_AUTO_RATIO_EN__enumvalues = { + 0: 'SCL_V_CALC_AUTO_RATIO_DISABLE', + 1: 'SCL_V_CALC_AUTO_RATIO_ENABLE', +} +SCL_V_CALC_AUTO_RATIO_DISABLE = 0 +SCL_V_CALC_AUTO_RATIO_ENABLE = 1 +SCL_V_CALC_AUTO_RATIO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_H_CALC_AUTO_RATIO_EN' +SCL_H_CALC_AUTO_RATIO_EN__enumvalues = { + 0: 'SCL_H_CALC_AUTO_RATIO_DISABLE', + 1: 'SCL_H_CALC_AUTO_RATIO_ENABLE', +} +SCL_H_CALC_AUTO_RATIO_DISABLE = 0 +SCL_H_CALC_AUTO_RATIO_ENABLE = 1 +SCL_H_CALC_AUTO_RATIO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_H_FILTER_PICK_NEAREST' +SCL_H_FILTER_PICK_NEAREST__enumvalues = { + 0: 'SCL_H_FILTER_PICK_NEAREST_DISABLE', + 1: 'SCL_H_FILTER_PICK_NEAREST_ENABLE', +} +SCL_H_FILTER_PICK_NEAREST_DISABLE = 0 +SCL_H_FILTER_PICK_NEAREST_ENABLE = 1 +SCL_H_FILTER_PICK_NEAREST = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_H_2TAP_HARDCODE_COEF_EN' +SCL_H_2TAP_HARDCODE_COEF_EN__enumvalues = { + 0: 'SCL_H_2TAP_HARDCODE_COEF_DISABLE', + 1: 'SCL_H_2TAP_HARDCODE_COEF_ENABLE', +} +SCL_H_2TAP_HARDCODE_COEF_DISABLE = 0 +SCL_H_2TAP_HARDCODE_COEF_ENABLE = 1 +SCL_H_2TAP_HARDCODE_COEF_EN = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_V_FILTER_PICK_NEAREST' +SCL_V_FILTER_PICK_NEAREST__enumvalues = { + 0: 'SCL_V_FILTER_PICK_NEAREST_DISABLE', + 1: 'SCL_V_FILTER_PICK_NEAREST_ENABLE', +} +SCL_V_FILTER_PICK_NEAREST_DISABLE = 0 +SCL_V_FILTER_PICK_NEAREST_ENABLE = 1 +SCL_V_FILTER_PICK_NEAREST = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_V_2TAP_HARDCODE_COEF_EN' +SCL_V_2TAP_HARDCODE_COEF_EN__enumvalues = { + 0: 'SCL_V_2TAP_HARDCODE_COEF_DISABLE', + 1: 'SCL_V_2TAP_HARDCODE_COEF_ENABLE', +} +SCL_V_2TAP_HARDCODE_COEF_DISABLE = 0 +SCL_V_2TAP_HARDCODE_COEF_ENABLE = 1 +SCL_V_2TAP_HARDCODE_COEF_EN = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_UPDATE_TAKEN' +SCL_UPDATE_TAKEN__enumvalues = { + 0: 'SCL_UPDATE_TAKEN_NO', + 1: 'SCL_UPDATE_TAKEN_YES', +} +SCL_UPDATE_TAKEN_NO = 0 +SCL_UPDATE_TAKEN_YES = 1 +SCL_UPDATE_TAKEN = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_UPDATE_LOCK' +SCL_UPDATE_LOCK__enumvalues = { + 0: 'SCL_UPDATE_UNLOCKED', + 1: 'SCL_UPDATE_LOCKED', +} +SCL_UPDATE_UNLOCKED = 0 +SCL_UPDATE_LOCKED = 1 +SCL_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_COEF_UPDATE_COMPLETE' +SCL_COEF_UPDATE_COMPLETE__enumvalues = { + 0: 'SCL_COEF_UPDATE_NOT_COMPLETED', + 1: 'SCL_COEF_UPDATE_COMPLETED', +} +SCL_COEF_UPDATE_NOT_COMPLETED = 0 +SCL_COEF_UPDATE_COMPLETED = 1 +SCL_COEF_UPDATE_COMPLETE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_HF_SHARP_SCALE_FACTOR' +SCL_HF_SHARP_SCALE_FACTOR__enumvalues = { + 0: 'SCL_HF_SHARP_SCALE_FACTOR_0', + 1: 'SCL_HF_SHARP_SCALE_FACTOR_1', + 2: 'SCL_HF_SHARP_SCALE_FACTOR_2', + 3: 'SCL_HF_SHARP_SCALE_FACTOR_3', + 4: 'SCL_HF_SHARP_SCALE_FACTOR_4', + 5: 'SCL_HF_SHARP_SCALE_FACTOR_5', + 6: 'SCL_HF_SHARP_SCALE_FACTOR_6', + 7: 'SCL_HF_SHARP_SCALE_FACTOR_7', +} +SCL_HF_SHARP_SCALE_FACTOR_0 = 0 +SCL_HF_SHARP_SCALE_FACTOR_1 = 1 +SCL_HF_SHARP_SCALE_FACTOR_2 = 2 +SCL_HF_SHARP_SCALE_FACTOR_3 = 3 +SCL_HF_SHARP_SCALE_FACTOR_4 = 4 +SCL_HF_SHARP_SCALE_FACTOR_5 = 5 +SCL_HF_SHARP_SCALE_FACTOR_6 = 6 +SCL_HF_SHARP_SCALE_FACTOR_7 = 7 +SCL_HF_SHARP_SCALE_FACTOR = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_HF_SHARP_EN' +SCL_HF_SHARP_EN__enumvalues = { + 0: 'SCL_HF_SHARP_DISABLE', + 1: 'SCL_HF_SHARP_ENABLE', +} +SCL_HF_SHARP_DISABLE = 0 +SCL_HF_SHARP_ENABLE = 1 +SCL_HF_SHARP_EN = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_VF_SHARP_SCALE_FACTOR' +SCL_VF_SHARP_SCALE_FACTOR__enumvalues = { + 0: 'SCL_VF_SHARP_SCALE_FACTOR_0', + 1: 'SCL_VF_SHARP_SCALE_FACTOR_1', + 2: 'SCL_VF_SHARP_SCALE_FACTOR_2', + 3: 'SCL_VF_SHARP_SCALE_FACTOR_3', + 4: 'SCL_VF_SHARP_SCALE_FACTOR_4', + 5: 'SCL_VF_SHARP_SCALE_FACTOR_5', + 6: 'SCL_VF_SHARP_SCALE_FACTOR_6', + 7: 'SCL_VF_SHARP_SCALE_FACTOR_7', +} +SCL_VF_SHARP_SCALE_FACTOR_0 = 0 +SCL_VF_SHARP_SCALE_FACTOR_1 = 1 +SCL_VF_SHARP_SCALE_FACTOR_2 = 2 +SCL_VF_SHARP_SCALE_FACTOR_3 = 3 +SCL_VF_SHARP_SCALE_FACTOR_4 = 4 +SCL_VF_SHARP_SCALE_FACTOR_5 = 5 +SCL_VF_SHARP_SCALE_FACTOR_6 = 6 +SCL_VF_SHARP_SCALE_FACTOR_7 = 7 +SCL_VF_SHARP_SCALE_FACTOR = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_VF_SHARP_EN' +SCL_VF_SHARP_EN__enumvalues = { + 0: 'SCL_VF_SHARP_DISABLE', + 1: 'SCL_VF_SHARP_ENABLE', +} +SCL_VF_SHARP_DISABLE = 0 +SCL_VF_SHARP_ENABLE = 1 +SCL_VF_SHARP_EN = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_ALU_DISABLE' +SCL_ALU_DISABLE__enumvalues = { + 0: 'SCL_ALU_ENABLED', + 1: 'SCL_ALU_DISABLED', +} +SCL_ALU_ENABLED = 0 +SCL_ALU_DISABLED = 1 +SCL_ALU_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_HOST_CONFLICT_MASK' +SCL_HOST_CONFLICT_MASK__enumvalues = { + 0: 'SCL_HOST_CONFLICT_DISABLE_INTERRUPT', + 1: 'SCL_HOST_CONFLICT_ENABLE_INTERRUPT', +} +SCL_HOST_CONFLICT_DISABLE_INTERRUPT = 0 +SCL_HOST_CONFLICT_ENABLE_INTERRUPT = 1 +SCL_HOST_CONFLICT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_SCL_MODE_CHANGE_MASK' +SCL_SCL_MODE_CHANGE_MASK__enumvalues = { + 0: 'SCL_MODE_CHANGE_DISABLE_INTERRUPT', + 1: 'SCL_MODE_CHANGE_ENABLE_INTERRUPT', +} +SCL_MODE_CHANGE_DISABLE_INTERRUPT = 0 +SCL_MODE_CHANGE_ENABLE_INTERRUPT = 1 +SCL_SCL_MODE_CHANGE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'SCLV_MODE_SEL' +SCLV_MODE_SEL__enumvalues = { + 0: 'SCLV_MODE_RGB_BYPASS', + 1: 'SCLV_MODE_RGB_SCALING', + 2: 'SCLV_MODE_YCBCR_SCALING', + 3: 'SCLV_MODE_YCBCR_BYPASS', +} +SCLV_MODE_RGB_BYPASS = 0 +SCLV_MODE_RGB_SCALING = 1 +SCLV_MODE_YCBCR_SCALING = 2 +SCLV_MODE_YCBCR_BYPASS = 3 +SCLV_MODE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SCLV_INTERLACE_SOURCE' +SCLV_INTERLACE_SOURCE__enumvalues = { + 0: 'INTERLACE_SOURCE_PROGRESSIVE', + 1: 'INTERLACE_SOURCE_INTERLEAVE', + 2: 'INTERLACE_SOURCE_STACK', +} +INTERLACE_SOURCE_PROGRESSIVE = 0 +INTERLACE_SOURCE_INTERLEAVE = 1 +INTERLACE_SOURCE_STACK = 2 +SCLV_INTERLACE_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'SCLV_UPDATE_LOCK' +SCLV_UPDATE_LOCK__enumvalues = { + 0: 'UPDATE_UNLOCKED', + 1: 'UPDATE_LOCKED', +} +UPDATE_UNLOCKED = 0 +UPDATE_LOCKED = 1 +SCLV_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'SCLV_COEF_UPDATE_COMPLETE' +SCLV_COEF_UPDATE_COMPLETE__enumvalues = { + 0: 'COEF_UPDATE_NOT_COMPLETE', + 1: 'COEF_UPDATE_COMPLETE', +} +COEF_UPDATE_NOT_COMPLETE = 0 +COEF_UPDATE_COMPLETE = 1 +SCLV_COEF_UPDATE_COMPLETE = ctypes.c_uint32 # enum + +# values for enumeration 'DPRX_SD_PIXEL_ENCODING' +DPRX_SD_PIXEL_ENCODING__enumvalues = { + 0: 'PIXEL_FORMAT_RGB_444', + 1: 'PIXEL_FORMAT_YCBCR_444', + 2: 'PIXEL_FORMAT_YCBCR_422', + 3: 'PIXEL_FORMAT_Y_ONLY', +} +PIXEL_FORMAT_RGB_444 = 0 +PIXEL_FORMAT_YCBCR_444 = 1 +PIXEL_FORMAT_YCBCR_422 = 2 +PIXEL_FORMAT_Y_ONLY = 3 +DPRX_SD_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'DPRX_SD_COMPONENT_DEPTH' +DPRX_SD_COMPONENT_DEPTH__enumvalues = { + 0: 'COMPONENT_DEPTH_6BPC', + 1: 'COMPONENT_DEPTH_8BPC', + 2: 'COMPONENT_DEPTH_10BPC', + 3: 'COMPONENT_DEPTH_12BPC', + 4: 'COMPONENT_DEPTH_16BPC', +} +COMPONENT_DEPTH_6BPC = 0 +COMPONENT_DEPTH_8BPC = 1 +COMPONENT_DEPTH_10BPC = 2 +COMPONENT_DEPTH_12BPC = 3 +COMPONENT_DEPTH_16BPC = 4 +DPRX_SD_COMPONENT_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_LATENCY_COUNTER_CONTROL' +AZ_LATENCY_COUNTER_CONTROL__enumvalues = { + 0: 'AZ_LATENCY_COUNTER_NO_RESET', + 1: 'AZ_LATENCY_COUNTER_RESET_DONE', +} +AZ_LATENCY_COUNTER_NO_RESET = 0 +AZ_LATENCY_COUNTER_RESET_DONE = 1 +AZ_LATENCY_COUNTER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_CONTROL_BLND_MODE' +BLND_CONTROL_BLND_MODE__enumvalues = { + 0: 'BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY', + 1: 'BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY', + 2: 'BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE', + 3: 'BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE', +} +BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0 +BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 1 +BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 2 +BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 3 +BLND_CONTROL_BLND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_CONTROL_BLND_STEREO_TYPE' +BLND_CONTROL_BLND_STEREO_TYPE__enumvalues = { + 0: 'BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO', + 1: 'BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO', + 2: 'BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO', + 3: 'BLND_CONTROL_BLND_STEREO_TYPE_UNUSED', +} +BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0 +BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 1 +BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 2 +BLND_CONTROL_BLND_STEREO_TYPE_UNUSED = 3 +BLND_CONTROL_BLND_STEREO_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_CONTROL_BLND_STEREO_POLARITY' +BLND_CONTROL_BLND_STEREO_POLARITY__enumvalues = { + 0: 'BLND_CONTROL_BLND_STEREO_POLARITY_LOW', + 1: 'BLND_CONTROL_BLND_STEREO_POLARITY_HIGH', +} +BLND_CONTROL_BLND_STEREO_POLARITY_LOW = 0 +BLND_CONTROL_BLND_STEREO_POLARITY_HIGH = 1 +BLND_CONTROL_BLND_STEREO_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_CONTROL_BLND_FEEDTHROUGH_EN' +BLND_CONTROL_BLND_FEEDTHROUGH_EN__enumvalues = { + 0: 'BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE', + 1: 'BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE', +} +BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0 +BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 1 +BLND_CONTROL_BLND_FEEDTHROUGH_EN = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_CONTROL_BLND_ALPHA_MODE' +BLND_CONTROL_BLND_ALPHA_MODE__enumvalues = { + 0: 'BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA', + 1: 'BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', + 2: 'BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY', + 3: 'BLND_CONTROL_BLND_ALPHA_MODE_UNUSED', +} +BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0 +BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 1 +BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 2 +BLND_CONTROL_BLND_ALPHA_MODE_UNUSED = 3 +BLND_CONTROL_BLND_ALPHA_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY' +BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY__enumvalues = { + 0: 'BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE', + 1: 'BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE', +} +BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE = 0 +BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE = 1 +BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_CONTROL_BLND_MULTIPLIED_MODE' +BLND_CONTROL_BLND_MULTIPLIED_MODE__enumvalues = { + 0: 'BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE', + 1: 'BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE', +} +BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0 +BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 1 +BLND_CONTROL_BLND_MULTIPLIED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_SM_CONTROL2_SM_MODE' +BLND_SM_CONTROL2_SM_MODE__enumvalues = { + 0: 'BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE', + 2: 'BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING', + 4: 'BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING', + 6: 'BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING', +} +BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0 +BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 2 +BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 4 +BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 6 +BLND_SM_CONTROL2_SM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE' +BLND_SM_CONTROL2_SM_FRAME_ALTERNATE__enumvalues = { + 0: 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE', + 1: 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE', +} +BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0 +BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 1 +BLND_SM_CONTROL2_SM_FRAME_ALTERNATE = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE' +BLND_SM_CONTROL2_SM_FIELD_ALTERNATE__enumvalues = { + 0: 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE', + 1: 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE', +} +BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0 +BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 1 +BLND_SM_CONTROL2_SM_FIELD_ALTERNATE = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL' +BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL__enumvalues = { + 0: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', + 1: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED', + 2: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', + 3: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', +} +BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0 +BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 1 +BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 2 +BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 3 +BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL' +BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL__enumvalues = { + 0: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE', + 1: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED', + 2: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', + 3: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', +} +BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0 +BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 1 +BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 2 +BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 3 +BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_CONTROL2_PTI_ENABLE' +BLND_CONTROL2_PTI_ENABLE__enumvalues = { + 0: 'BLND_CONTROL2_PTI_ENABLE_FALSE', + 1: 'BLND_CONTROL2_PTI_ENABLE_TRUE', +} +BLND_CONTROL2_PTI_ENABLE_FALSE = 0 +BLND_CONTROL2_PTI_ENABLE_TRUE = 1 +BLND_CONTROL2_PTI_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN' +BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN__enumvalues = { + 0: 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE', + 1: 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE', +} +BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0 +BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 1 +BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN' +BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN__enumvalues = { + 0: 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE', + 1: 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE', +} +BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0 +BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 1 +BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK' +BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK__enumvalues = { + 0: 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE', + 1: 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE', +} +BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0 +BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 1 +BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK' +BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK__enumvalues = { + 0: 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE', + 1: 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE', +} +BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0 +BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 1 +BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK' +BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK__enumvalues = { + 0: 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE', + 1: 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE', +} +BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0 +BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 1 +BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK' +BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__enumvalues = { + 0: 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE', + 1: 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE', +} +BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0 +BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 1 +BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK' +BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK__enumvalues = { + 0: 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE', + 1: 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE', +} +BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0 +BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 1 +BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK' +BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK__enumvalues = { + 0: 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE', + 1: 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE', +} +BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0 +BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 1 +BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK' +BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK__enumvalues = { + 0: 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE', + 1: 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE', +} +BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0 +BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 1 +BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK' +BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK__enumvalues = { + 0: 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE', + 1: 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE', +} +BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0 +BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 1 +BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE' +BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE__enumvalues = { + 0: 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE', + 1: 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE', +} +BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0 +BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 1 +BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_DEBUG_BLND_CNV_MUX_SELECT' +BLND_DEBUG_BLND_CNV_MUX_SELECT__enumvalues = { + 0: 'BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW', + 1: 'BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH', +} +BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0 +BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 1 +BLND_DEBUG_BLND_CNV_MUX_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN' +BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE', + 1: 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE', +} +BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0 +BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 1 +BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 9: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 9: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 1: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', +} +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', + 1: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', +} +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0 +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 1 +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 9: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 9: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_EN' +UNP_GRPH_EN__enumvalues = { + 0: 'UNP_GRPH_DISABLED', + 1: 'UNP_GRPH_ENABLED', +} +UNP_GRPH_DISABLED = 0 +UNP_GRPH_ENABLED = 1 +UNP_GRPH_EN = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_DEPTH' +UNP_GRPH_DEPTH__enumvalues = { + 0: 'UNP_GRPH_8BPP', + 1: 'UNP_GRPH_16BPP', + 2: 'UNP_GRPH_32BPP', +} +UNP_GRPH_8BPP = 0 +UNP_GRPH_16BPP = 1 +UNP_GRPH_32BPP = 2 +UNP_GRPH_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_NUM_BANKS' +UNP_GRPH_NUM_BANKS__enumvalues = { + 0: 'UNP_GRPH_ADDR_SURF_2_BANK', + 1: 'UNP_GRPH_ADDR_SURF_4_BANK', + 2: 'UNP_GRPH_ADDR_SURF_8_BANK', + 3: 'UNP_GRPH_ADDR_SURF_16_BANK', +} +UNP_GRPH_ADDR_SURF_2_BANK = 0 +UNP_GRPH_ADDR_SURF_4_BANK = 1 +UNP_GRPH_ADDR_SURF_8_BANK = 2 +UNP_GRPH_ADDR_SURF_16_BANK = 3 +UNP_GRPH_NUM_BANKS = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_BANK_WIDTH' +UNP_GRPH_BANK_WIDTH__enumvalues = { + 0: 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_1', + 1: 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_2', + 2: 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_4', + 3: 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_8', +} +UNP_GRPH_ADDR_SURF_BANK_WIDTH_1 = 0 +UNP_GRPH_ADDR_SURF_BANK_WIDTH_2 = 1 +UNP_GRPH_ADDR_SURF_BANK_WIDTH_4 = 2 +UNP_GRPH_ADDR_SURF_BANK_WIDTH_8 = 3 +UNP_GRPH_BANK_WIDTH = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_BANK_HEIGHT' +UNP_GRPH_BANK_HEIGHT__enumvalues = { + 0: 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1', + 1: 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2', + 2: 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4', + 3: 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8', +} +UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1 = 0 +UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2 = 1 +UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4 = 2 +UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8 = 3 +UNP_GRPH_BANK_HEIGHT = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_TILE_SPLIT' +UNP_GRPH_TILE_SPLIT__enumvalues = { + 0: 'UNP_ADDR_SURF_TILE_SPLIT_64B', + 1: 'UNP_ADDR_SURF_TILE_SPLIT_128B', + 2: 'UNP_ADDR_SURF_TILE_SPLIT_256B', + 3: 'UNP_ADDR_SURF_TILE_SPLIT_512B', + 4: 'UNP_ADDR_SURF_TILE_SPLIT_1KB', + 5: 'UNP_ADDR_SURF_TILE_SPLIT_2KB', + 6: 'UNP_ADDR_SURF_TILE_SPLIT_4KB', +} +UNP_ADDR_SURF_TILE_SPLIT_64B = 0 +UNP_ADDR_SURF_TILE_SPLIT_128B = 1 +UNP_ADDR_SURF_TILE_SPLIT_256B = 2 +UNP_ADDR_SURF_TILE_SPLIT_512B = 3 +UNP_ADDR_SURF_TILE_SPLIT_1KB = 4 +UNP_ADDR_SURF_TILE_SPLIT_2KB = 5 +UNP_ADDR_SURF_TILE_SPLIT_4KB = 6 +UNP_GRPH_TILE_SPLIT = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE' +UNP_GRPH_ADDRESS_TRANSLATION_ENABLE__enumvalues = { + 0: 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0', + 1: 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1', +} +UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0 = 0 +UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1 = 1 +UNP_GRPH_ADDRESS_TRANSLATION_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_MACRO_TILE_ASPECT' +UNP_GRPH_MACRO_TILE_ASPECT__enumvalues = { + 0: 'UNP_ADDR_SURF_MACRO_ASPECT_1', + 1: 'UNP_ADDR_SURF_MACRO_ASPECT_2', + 2: 'UNP_ADDR_SURF_MACRO_ASPECT_4', + 3: 'UNP_ADDR_SURF_MACRO_ASPECT_8', +} +UNP_ADDR_SURF_MACRO_ASPECT_1 = 0 +UNP_ADDR_SURF_MACRO_ASPECT_2 = 1 +UNP_ADDR_SURF_MACRO_ASPECT_4 = 2 +UNP_ADDR_SURF_MACRO_ASPECT_8 = 3 +UNP_GRPH_MACRO_TILE_ASPECT = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_COLOR_EXPANSION_MODE' +UNP_GRPH_COLOR_EXPANSION_MODE__enumvalues = { + 0: 'UNP_GRPH_DYNAMIC_EXPANSION', + 1: 'UNP_GRPH_ZERO_EXPANSION', +} +UNP_GRPH_DYNAMIC_EXPANSION = 0 +UNP_GRPH_ZERO_EXPANSION = 1 +UNP_GRPH_COLOR_EXPANSION_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_VIDEO_FORMAT' +UNP_VIDEO_FORMAT__enumvalues = { + 0: 'UNP_VIDEO_FORMAT0', + 1: 'UNP_VIDEO_FORMAT1', + 2: 'UNP_VIDEO_FORMAT_YUV420_YCbCr', + 3: 'UNP_VIDEO_FORMAT_YUV420_YCrCb', + 4: 'UNP_VIDEO_FORMAT_YUV422_YCb', + 5: 'UNP_VIDEO_FORMAT_YUV422_YCr', + 6: 'UNP_VIDEO_FORMAT_YUV422_CbY', + 7: 'UNP_VIDEO_FORMAT_YUV422_CrY', +} +UNP_VIDEO_FORMAT0 = 0 +UNP_VIDEO_FORMAT1 = 1 +UNP_VIDEO_FORMAT_YUV420_YCbCr = 2 +UNP_VIDEO_FORMAT_YUV420_YCrCb = 3 +UNP_VIDEO_FORMAT_YUV422_YCb = 4 +UNP_VIDEO_FORMAT_YUV422_YCr = 5 +UNP_VIDEO_FORMAT_YUV422_CbY = 6 +UNP_VIDEO_FORMAT_YUV422_CrY = 7 +UNP_VIDEO_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_ENDIAN_SWAP' +UNP_GRPH_ENDIAN_SWAP__enumvalues = { + 0: 'UNP_GRPH_ENDIAN_SWAP_NONE', + 1: 'UNP_GRPH_ENDIAN_SWAP_8IN16', + 2: 'UNP_GRPH_ENDIAN_SWAP_8IN32', + 3: 'UNP_GRPH_ENDIAN_SWAP_8IN43', +} +UNP_GRPH_ENDIAN_SWAP_NONE = 0 +UNP_GRPH_ENDIAN_SWAP_8IN16 = 1 +UNP_GRPH_ENDIAN_SWAP_8IN32 = 2 +UNP_GRPH_ENDIAN_SWAP_8IN43 = 3 +UNP_GRPH_ENDIAN_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_RED_CROSSBAR' +UNP_GRPH_RED_CROSSBAR__enumvalues = { + 0: 'UNP_GRPH_RED_CROSSBAR_R_Cr', + 1: 'UNP_GRPH_RED_CROSSBAR_G_Y', + 2: 'UNP_GRPH_RED_CROSSBAR_B_Cb', + 3: 'UNP_GRPH_RED_CROSSBAR_A', +} +UNP_GRPH_RED_CROSSBAR_R_Cr = 0 +UNP_GRPH_RED_CROSSBAR_G_Y = 1 +UNP_GRPH_RED_CROSSBAR_B_Cb = 2 +UNP_GRPH_RED_CROSSBAR_A = 3 +UNP_GRPH_RED_CROSSBAR = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_GREEN_CROSSBAR' +UNP_GRPH_GREEN_CROSSBAR__enumvalues = { + 0: 'UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y', + 1: 'UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C', + 2: 'UNP_UNP_GRPH_GREEN_CROSSBAR_A', + 3: 'UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr', +} +UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y = 0 +UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C = 1 +UNP_UNP_GRPH_GREEN_CROSSBAR_A = 2 +UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr = 3 +UNP_GRPH_GREEN_CROSSBAR = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_BLUE_CROSSBAR' +UNP_GRPH_BLUE_CROSSBAR__enumvalues = { + 0: 'UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C', + 1: 'UNP_GRPH_BLUE_CROSSBAR_A', + 2: 'UNP_GRPH_BLUE_CROSSBAR_R_Cr', + 3: 'UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y', +} +UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C = 0 +UNP_GRPH_BLUE_CROSSBAR_A = 1 +UNP_GRPH_BLUE_CROSSBAR_R_Cr = 2 +UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y = 3 +UNP_GRPH_BLUE_CROSSBAR = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_MODE_UPDATE_LOCKG' +UNP_GRPH_MODE_UPDATE_LOCKG__enumvalues = { + 0: 'UNP_GRPH_UPDATE_LOCK_0', + 1: 'UNP_GRPH_UPDATE_LOCK_1', +} +UNP_GRPH_UPDATE_LOCK_0 = 0 +UNP_GRPH_UPDATE_LOCK_1 = 1 +UNP_GRPH_MODE_UPDATE_LOCKG = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK' +UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK__enumvalues = { + 0: 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0', + 1: 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1', +} +UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0 = 0 +UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1 = 1 +UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE' +UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE__enumvalues = { + 0: 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0', + 1: 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1', +} +UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0 = 0 +UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1 = 1 +UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE' +UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__enumvalues = { + 0: 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0', + 1: 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1', +} +UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0 = 0 +UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1 = 1 +UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_STEREOSYNC_FLIP_EN' +UNP_GRPH_STEREOSYNC_FLIP_EN__enumvalues = { + 0: 'UNP_GRPH_STEREOSYNC_FLIP_DISABLE', + 1: 'UNP_GRPH_STEREOSYNC_FLIP_ENABLE', +} +UNP_GRPH_STEREOSYNC_FLIP_DISABLE = 0 +UNP_GRPH_STEREOSYNC_FLIP_ENABLE = 1 +UNP_GRPH_STEREOSYNC_FLIP_EN = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_STEREOSYNC_FLIP_MODE' +UNP_GRPH_STEREOSYNC_FLIP_MODE__enumvalues = { + 0: 'UNP_GRPH_STEREOSYNC_FLIP_MODE_0', + 1: 'UNP_GRPH_STEREOSYNC_FLIP_MODE_1', + 2: 'UNP_GRPH_STEREOSYNC_FLIP_MODE_2', + 3: 'UNP_GRPH_STEREOSYNC_FLIP_MODE_3', +} +UNP_GRPH_STEREOSYNC_FLIP_MODE_0 = 0 +UNP_GRPH_STEREOSYNC_FLIP_MODE_1 = 1 +UNP_GRPH_STEREOSYNC_FLIP_MODE_2 = 2 +UNP_GRPH_STEREOSYNC_FLIP_MODE_3 = 3 +UNP_GRPH_STEREOSYNC_FLIP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_STACK_INTERLACE_FLIP_EN' +UNP_GRPH_STACK_INTERLACE_FLIP_EN__enumvalues = { + 0: 'UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE', + 1: 'UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE', +} +UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE = 0 +UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE = 1 +UNP_GRPH_STACK_INTERLACE_FLIP_EN = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE' +UNP_GRPH_STACK_INTERLACE_FLIP_MODE__enumvalues = { + 0: 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0', + 1: 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1', + 2: 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2', + 3: 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3', +} +UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0 = 0 +UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1 = 1 +UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2 = 2 +UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3 = 3 +UNP_GRPH_STACK_INTERLACE_FLIP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_STEREOSYNC_SELECT_DISABLE' +UNP_GRPH_STEREOSYNC_SELECT_DISABLE__enumvalues = { + 0: 'UNP_GRPH_STEREOSYNC_SELECT_EN', + 1: 'UNP_GRPH_STEREOSYNC_SELECT_DIS', +} +UNP_GRPH_STEREOSYNC_SELECT_EN = 0 +UNP_GRPH_STEREOSYNC_SELECT_DIS = 1 +UNP_GRPH_STEREOSYNC_SELECT_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_CRC_SOURCE_SEL' +UNP_CRC_SOURCE_SEL__enumvalues = { + 0: 'UNP_CRC_SOURCE_SEL_NP_TO_LBV', + 1: 'UNP_CRC_SOURCE_SEL_LOWER32', + 2: 'UNP_CRC_SOURCE_SEL_RESERVED', + 3: 'UNP_CRC_SOURCE_SEL_LOWER16', + 4: 'UNP_CRC_SOURCE_SEL_UNP_TO_LBV', +} +UNP_CRC_SOURCE_SEL_NP_TO_LBV = 0 +UNP_CRC_SOURCE_SEL_LOWER32 = 1 +UNP_CRC_SOURCE_SEL_RESERVED = 2 +UNP_CRC_SOURCE_SEL_LOWER16 = 3 +UNP_CRC_SOURCE_SEL_UNP_TO_LBV = 4 +UNP_CRC_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_CRC_LINE_SEL' +UNP_CRC_LINE_SEL__enumvalues = { + 0: 'UNP_CRC_LINE_SEL_RESERVED', + 1: 'UNP_CRC_LINE_SEL_EVEN_ONLY', + 2: 'UNP_CRC_LINE_SEL_ODD_ONLY', + 3: 'UNP_CRC_LINE_SEL_ODD_EVEN', +} +UNP_CRC_LINE_SEL_RESERVED = 0 +UNP_CRC_LINE_SEL_EVEN_ONLY = 1 +UNP_CRC_LINE_SEL_ODD_ONLY = 2 +UNP_CRC_LINE_SEL_ODD_EVEN = 3 +UNP_CRC_LINE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_ROTATION_ANGLE' +UNP_ROTATION_ANGLE__enumvalues = { + 0: 'UNP_ROTATION_ANGLE_0', + 1: 'UNP_ROTATION_ANGLE_90', + 2: 'UNP_ROTATION_ANGLE_180', + 3: 'UNP_ROTATION_ANGLE_270', + 4: 'UNP_ROTATION_ANGLE_0m', + 5: 'UNP_ROTATION_ANGLE_90m', + 6: 'UNP_ROTATION_ANGLE_180m', + 7: 'UNP_ROTATION_ANGLE_270m', +} +UNP_ROTATION_ANGLE_0 = 0 +UNP_ROTATION_ANGLE_90 = 1 +UNP_ROTATION_ANGLE_180 = 2 +UNP_ROTATION_ANGLE_270 = 3 +UNP_ROTATION_ANGLE_0m = 4 +UNP_ROTATION_ANGLE_90m = 5 +UNP_ROTATION_ANGLE_180m = 6 +UNP_ROTATION_ANGLE_270m = 7 +UNP_ROTATION_ANGLE = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_PIXEL_DROP' +UNP_PIXEL_DROP__enumvalues = { + 0: 'UNP_PIXEL_NO_DROP', + 1: 'UNP_PIXEL_DROPPING', +} +UNP_PIXEL_NO_DROP = 0 +UNP_PIXEL_DROPPING = 1 +UNP_PIXEL_DROP = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_BUFFER_MODE' +UNP_BUFFER_MODE__enumvalues = { + 0: 'UNP_BUFFER_MODE_LUMA', + 1: 'UNP_BUFFER_MODE_LUMA_CHROMA', +} +UNP_BUFFER_MODE_LUMA = 0 +UNP_BUFFER_MODE_LUMA_CHROMA = 1 +UNP_BUFFER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_LINK_TRAINING_COMPLETE' +DP_LINK_TRAINING_COMPLETE__enumvalues = { + 0: 'DP_LINK_TRAINING_NOT_COMPLETE', + 1: 'DP_LINK_TRAINING_ALREADY_COMPLETE', +} +DP_LINK_TRAINING_NOT_COMPLETE = 0 +DP_LINK_TRAINING_ALREADY_COMPLETE = 1 +DP_LINK_TRAINING_COMPLETE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_EMBEDDED_PANEL_MODE' +DP_EMBEDDED_PANEL_MODE__enumvalues = { + 0: 'DP_EXTERNAL_PANEL', + 1: 'DP_EMBEDDED_PANEL', +} +DP_EXTERNAL_PANEL = 0 +DP_EMBEDDED_PANEL = 1 +DP_EMBEDDED_PANEL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_PIXEL_ENCODING' +DP_PIXEL_ENCODING__enumvalues = { + 0: 'DP_PIXEL_ENCODING_RGB444', + 1: 'DP_PIXEL_ENCODING_YCBCR422', + 2: 'DP_PIXEL_ENCODING_YCBCR444', + 3: 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', + 4: 'DP_PIXEL_ENCODING_Y_ONLY', + 5: 'DP_PIXEL_ENCODING_YCBCR420', + 6: 'DP_PIXEL_ENCODING_RESERVED', +} +DP_PIXEL_ENCODING_RGB444 = 0 +DP_PIXEL_ENCODING_YCBCR422 = 1 +DP_PIXEL_ENCODING_YCBCR444 = 2 +DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 3 +DP_PIXEL_ENCODING_Y_ONLY = 4 +DP_PIXEL_ENCODING_YCBCR420 = 5 +DP_PIXEL_ENCODING_RESERVED = 6 +DP_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DYN_RANGE' +DP_DYN_RANGE__enumvalues = { + 0: 'DP_DYN_VESA_RANGE', + 1: 'DP_DYN_CEA_RANGE', +} +DP_DYN_VESA_RANGE = 0 +DP_DYN_CEA_RANGE = 1 +DP_DYN_RANGE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_YCBCR_RANGE' +DP_YCBCR_RANGE__enumvalues = { + 0: 'DP_YCBCR_RANGE_BT601_5', + 1: 'DP_YCBCR_RANGE_BT709_5', +} +DP_YCBCR_RANGE_BT601_5 = 0 +DP_YCBCR_RANGE_BT709_5 = 1 +DP_YCBCR_RANGE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_COMPONENT_DEPTH' +DP_COMPONENT_DEPTH__enumvalues = { + 0: 'DP_COMPONENT_DEPTH_6BPC', + 1: 'DP_COMPONENT_DEPTH_8BPC', + 2: 'DP_COMPONENT_DEPTH_10BPC', + 3: 'DP_COMPONENT_DEPTH_12BPC', + 4: 'DP_COMPONENT_DEPTH_16BPC_RESERVED', + 5: 'DP_COMPONENT_DEPTH_RESERVED', +} +DP_COMPONENT_DEPTH_6BPC = 0 +DP_COMPONENT_DEPTH_8BPC = 1 +DP_COMPONENT_DEPTH_10BPC = 2 +DP_COMPONENT_DEPTH_12BPC = 3 +DP_COMPONENT_DEPTH_16BPC_RESERVED = 4 +DP_COMPONENT_DEPTH_RESERVED = 5 +DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSA_MISC0_OVERRIDE_ENABLE' +DP_MSA_MISC0_OVERRIDE_ENABLE__enumvalues = { + 0: 'MSA_MISC0_OVERRIDE_DISABLE', + 1: 'MSA_MISC0_OVERRIDE_ENABLE', +} +MSA_MISC0_OVERRIDE_DISABLE = 0 +MSA_MISC0_OVERRIDE_ENABLE = 1 +DP_MSA_MISC0_OVERRIDE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE' +DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__enumvalues = { + 0: 'MSA_MISC1_BIT7_OVERRIDE_DISABLE', + 1: 'MSA_MISC1_BIT7_OVERRIDE_ENABLE', +} +MSA_MISC1_BIT7_OVERRIDE_DISABLE = 0 +MSA_MISC1_BIT7_OVERRIDE_ENABLE = 1 +DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_UDI_LANES' +DP_UDI_LANES__enumvalues = { + 0: 'DP_UDI_1_LANE', + 1: 'DP_UDI_2_LANES', + 2: 'DP_UDI_LANES_RESERVED', + 3: 'DP_UDI_4_LANES', +} +DP_UDI_1_LANE = 0 +DP_UDI_2_LANES = 1 +DP_UDI_LANES_RESERVED = 2 +DP_UDI_4_LANES = 3 +DP_UDI_LANES = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_STREAM_DIS_DEFER' +DP_VID_STREAM_DIS_DEFER__enumvalues = { + 0: 'DP_VID_STREAM_DIS_NO_DEFER', + 1: 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', + 2: 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', +} +DP_VID_STREAM_DIS_NO_DEFER = 0 +DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 1 +DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 2 +DP_VID_STREAM_DIS_DEFER = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STEER_OVERFLOW_ACK' +DP_STEER_OVERFLOW_ACK__enumvalues = { + 0: 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', + 1: 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', +} +DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0 +DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 1 +DP_STEER_OVERFLOW_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STEER_OVERFLOW_MASK' +DP_STEER_OVERFLOW_MASK__enumvalues = { + 0: 'DP_STEER_OVERFLOW_MASKED', + 1: 'DP_STEER_OVERFLOW_UNMASK', +} +DP_STEER_OVERFLOW_MASKED = 0 +DP_STEER_OVERFLOW_UNMASK = 1 +DP_STEER_OVERFLOW_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_TU_OVERFLOW_ACK' +DP_TU_OVERFLOW_ACK__enumvalues = { + 0: 'DP_TU_OVERFLOW_ACK_NO_EFFECT', + 1: 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', +} +DP_TU_OVERFLOW_ACK_NO_EFFECT = 0 +DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 1 +DP_TU_OVERFLOW_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ALT_SCRAMBLER_RESET_EN' +DPHY_ALT_SCRAMBLER_RESET_EN__enumvalues = { + 0: 'DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE', + 1: 'DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION', +} +DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE = 0 +DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION = 1 +DPHY_ALT_SCRAMBLER_RESET_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ALT_SCRAMBLER_RESET_SEL' +DPHY_ALT_SCRAMBLER_RESET_SEL__enumvalues = { + 0: 'DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE', + 1: 'DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE', +} +DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE = 0 +DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE = 1 +DPHY_ALT_SCRAMBLER_RESET_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_TIMING_MODE' +DP_VID_TIMING_MODE__enumvalues = { + 0: 'DP_VID_TIMING_MODE_ASYNC', + 1: 'DP_VID_TIMING_MODE_SYNC', +} +DP_VID_TIMING_MODE_ASYNC = 0 +DP_VID_TIMING_MODE_SYNC = 1 +DP_VID_TIMING_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_M_N_DOUBLE_BUFFER_MODE' +DP_VID_M_N_DOUBLE_BUFFER_MODE__enumvalues = { + 0: 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', + 1: 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', +} +DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0 +DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 1 +DP_VID_M_N_DOUBLE_BUFFER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_M_N_GEN_EN' +DP_VID_M_N_GEN_EN__enumvalues = { + 0: 'DP_VID_M_N_PROGRAMMED_VIA_REG', + 1: 'DP_VID_M_N_CALC_AUTO', +} +DP_VID_M_N_PROGRAMMED_VIA_REG = 0 +DP_VID_M_N_CALC_AUTO = 1 +DP_VID_M_N_GEN_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_M_DOUBLE_VALUE_EN' +DP_VID_M_DOUBLE_VALUE_EN__enumvalues = { + 0: 'DP_VID_M_INPUT_PIXEL_RATE', + 1: 'DP_VID_M_DOUBLE_INPUT_PIXEL_RATE', +} +DP_VID_M_INPUT_PIXEL_RATE = 0 +DP_VID_M_DOUBLE_INPUT_PIXEL_RATE = 1 +DP_VID_M_DOUBLE_VALUE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_ENHANCED_FRAME_MODE' +DP_VID_ENHANCED_FRAME_MODE__enumvalues = { + 0: 'VID_NORMAL_FRAME_MODE', + 1: 'VID_ENHANCED_MODE', +} +VID_NORMAL_FRAME_MODE = 0 +VID_ENHANCED_MODE = 1 +DP_VID_ENHANCED_FRAME_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_MSA_TOP_FIELD_MODE' +DP_VID_MSA_TOP_FIELD_MODE__enumvalues = { + 0: 'DP_TOP_FIELD_ONLY', + 1: 'DP_TOP_PLUS_BOTTOM_FIELD', +} +DP_TOP_FIELD_ONLY = 0 +DP_TOP_PLUS_BOTTOM_FIELD = 1 +DP_VID_MSA_TOP_FIELD_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_VBID_FIELD_POL' +DP_VID_VBID_FIELD_POL__enumvalues = { + 0: 'DP_VID_VBID_FIELD_POL_NORMAL', + 1: 'DP_VID_VBID_FIELD_POL_INV', +} +DP_VID_VBID_FIELD_POL_NORMAL = 0 +DP_VID_VBID_FIELD_POL_INV = 1 +DP_VID_VBID_FIELD_POL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_STREAM_DISABLE_ACK' +DP_VID_STREAM_DISABLE_ACK__enumvalues = { + 0: 'ID_STREAM_DISABLE_NO_ACK', + 1: 'ID_STREAM_DISABLE_ACKED', +} +ID_STREAM_DISABLE_NO_ACK = 0 +ID_STREAM_DISABLE_ACKED = 1 +DP_VID_STREAM_DISABLE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_STREAM_DISABLE_MASK' +DP_VID_STREAM_DISABLE_MASK__enumvalues = { + 0: 'VID_STREAM_DISABLE_MASKED', + 1: 'VID_STREAM_DISABLE_UNMASK', +} +VID_STREAM_DISABLE_MASKED = 0 +VID_STREAM_DISABLE_UNMASK = 1 +DP_VID_STREAM_DISABLE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE0' +DPHY_ATEST_SEL_LANE0__enumvalues = { + 0: 'DPHY_ATEST_LANE0_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE0_REG_PATTERN', +} +DPHY_ATEST_LANE0_PRBS_PATTERN = 0 +DPHY_ATEST_LANE0_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE0 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE1' +DPHY_ATEST_SEL_LANE1__enumvalues = { + 0: 'DPHY_ATEST_LANE1_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE1_REG_PATTERN', +} +DPHY_ATEST_LANE1_PRBS_PATTERN = 0 +DPHY_ATEST_LANE1_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE1 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE2' +DPHY_ATEST_SEL_LANE2__enumvalues = { + 0: 'DPHY_ATEST_LANE2_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE2_REG_PATTERN', +} +DPHY_ATEST_LANE2_PRBS_PATTERN = 0 +DPHY_ATEST_LANE2_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE2 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE3' +DPHY_ATEST_SEL_LANE3__enumvalues = { + 0: 'DPHY_ATEST_LANE3_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE3_REG_PATTERN', +} +DPHY_ATEST_LANE3_PRBS_PATTERN = 0 +DPHY_ATEST_LANE3_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE3 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SCRAMBLER_SEL' +DPHY_SCRAMBLER_SEL__enumvalues = { + 0: 'DPHY_SCRAMBLER_SEL_LANE_DATA', + 1: 'DPHY_SCRAMBLER_SEL_DBG_DATA', +} +DPHY_SCRAMBLER_SEL_LANE_DATA = 0 +DPHY_SCRAMBLER_SEL_DBG_DATA = 1 +DPHY_SCRAMBLER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_BYPASS' +DPHY_BYPASS__enumvalues = { + 0: 'DPHY_8B10B_OUTPUT', + 1: 'DPHY_DBG_OUTPUT', +} +DPHY_8B10B_OUTPUT = 0 +DPHY_DBG_OUTPUT = 1 +DPHY_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SKEW_BYPASS' +DPHY_SKEW_BYPASS__enumvalues = { + 0: 'DPHY_WITH_SKEW', + 1: 'DPHY_NO_SKEW', +} +DPHY_WITH_SKEW = 0 +DPHY_NO_SKEW = 1 +DPHY_SKEW_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_TRAINING_PATTERN_SEL' +DPHY_TRAINING_PATTERN_SEL__enumvalues = { + 0: 'DPHY_TRAINING_PATTERN_1', + 1: 'DPHY_TRAINING_PATTERN_2', + 2: 'DPHY_TRAINING_PATTERN_3', + 3: 'DPHY_TRAINING_PATTERN_4', +} +DPHY_TRAINING_PATTERN_1 = 0 +DPHY_TRAINING_PATTERN_2 = 1 +DPHY_TRAINING_PATTERN_3 = 2 +DPHY_TRAINING_PATTERN_4 = 3 +DPHY_TRAINING_PATTERN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_8B10B_RESET' +DPHY_8B10B_RESET__enumvalues = { + 0: 'DPHY_8B10B_NOT_RESET', + 1: 'DPHY_8B10B_RESETET', +} +DPHY_8B10B_NOT_RESET = 0 +DPHY_8B10B_RESETET = 1 +DPHY_8B10B_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_8B10B_EXT_DISP' +DP_DPHY_8B10B_EXT_DISP__enumvalues = { + 0: 'DP_DPHY_8B10B_EXT_DISP_ZERO', + 1: 'DP_DPHY_8B10B_EXT_DISP_ONE', +} +DP_DPHY_8B10B_EXT_DISP_ZERO = 0 +DP_DPHY_8B10B_EXT_DISP_ONE = 1 +DP_DPHY_8B10B_EXT_DISP = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_8B10B_CUR_DISP' +DPHY_8B10B_CUR_DISP__enumvalues = { + 0: 'DPHY_8B10B_CUR_DISP_ZERO', + 1: 'DPHY_8B10B_CUR_DISP_ONE', +} +DPHY_8B10B_CUR_DISP_ZERO = 0 +DPHY_8B10B_CUR_DISP_ONE = 1 +DPHY_8B10B_CUR_DISP = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_PRBS_EN' +DPHY_PRBS_EN__enumvalues = { + 0: 'DPHY_PRBS_DISABLE', + 1: 'DPHY_PRBS_ENABLE', +} +DPHY_PRBS_DISABLE = 0 +DPHY_PRBS_ENABLE = 1 +DPHY_PRBS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_PRBS_SEL' +DPHY_PRBS_SEL__enumvalues = { + 0: 'DPHY_PRBS7_SELECTED', + 1: 'DPHY_PRBS23_SELECTED', + 2: 'DPHY_PRBS11_SELECTED', +} +DPHY_PRBS7_SELECTED = 0 +DPHY_PRBS23_SELECTED = 1 +DPHY_PRBS11_SELECTED = 2 +DPHY_PRBS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SCRAMBLER_DIS' +DPHY_SCRAMBLER_DIS__enumvalues = { + 0: 'DPHY_SCR_ENABLED', + 1: 'DPHY_SCR_DISABLED', +} +DPHY_SCR_ENABLED = 0 +DPHY_SCR_DISABLED = 1 +DPHY_SCRAMBLER_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SCRAMBLER_ADVANCE' +DPHY_SCRAMBLER_ADVANCE__enumvalues = { + 0: 'DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY', + 1: 'DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL', +} +DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY = 0 +DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL = 1 +DPHY_SCRAMBLER_ADVANCE = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SCRAMBLER_KCODE' +DPHY_SCRAMBLER_KCODE__enumvalues = { + 0: 'DPHY_SCRAMBLER_KCODE_DISABLED', + 1: 'DPHY_SCRAMBLER_KCODE_ENABLED', +} +DPHY_SCRAMBLER_KCODE_DISABLED = 0 +DPHY_SCRAMBLER_KCODE_ENABLED = 1 +DPHY_SCRAMBLER_KCODE = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_LOAD_BS_COUNT_START' +DPHY_LOAD_BS_COUNT_START__enumvalues = { + 0: 'DPHY_LOAD_BS_COUNT_STARTED', + 1: 'DPHY_LOAD_BS_COUNT_NOT_STARTED', +} +DPHY_LOAD_BS_COUNT_STARTED = 0 +DPHY_LOAD_BS_COUNT_NOT_STARTED = 1 +DPHY_LOAD_BS_COUNT_START = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_EN' +DPHY_CRC_EN__enumvalues = { + 0: 'DPHY_CRC_DISABLED', + 1: 'DPHY_CRC_ENABLED', +} +DPHY_CRC_DISABLED = 0 +DPHY_CRC_ENABLED = 1 +DPHY_CRC_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_CONT_EN' +DPHY_CRC_CONT_EN__enumvalues = { + 0: 'DPHY_CRC_ONE_SHOT', + 1: 'DPHY_CRC_CONTINUOUS', +} +DPHY_CRC_ONE_SHOT = 0 +DPHY_CRC_CONTINUOUS = 1 +DPHY_CRC_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_FIELD' +DPHY_CRC_FIELD__enumvalues = { + 0: 'DPHY_CRC_START_FROM_TOP_FIELD', + 1: 'DPHY_CRC_START_FROM_BOTTOM_FIELD', +} +DPHY_CRC_START_FROM_TOP_FIELD = 0 +DPHY_CRC_START_FROM_BOTTOM_FIELD = 1 +DPHY_CRC_FIELD = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_SEL' +DPHY_CRC_SEL__enumvalues = { + 0: 'DPHY_CRC_LANE0_SELECTED', + 1: 'DPHY_CRC_LANE1_SELECTED', + 2: 'DPHY_CRC_LANE2_SELECTED', + 3: 'DPHY_CRC_LANE3_SELECTED', +} +DPHY_CRC_LANE0_SELECTED = 0 +DPHY_CRC_LANE1_SELECTED = 1 +DPHY_CRC_LANE2_SELECTED = 2 +DPHY_CRC_LANE3_SELECTED = 3 +DPHY_CRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_RX_FAST_TRAINING_CAPABLE' +DPHY_RX_FAST_TRAINING_CAPABLE__enumvalues = { + 0: 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', + 1: 'DPHY_FAST_TRAINING_CAPABLE', +} +DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0 +DPHY_FAST_TRAINING_CAPABLE = 1 +DPHY_RX_FAST_TRAINING_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_COLLISION_ACK' +DP_SEC_COLLISION_ACK__enumvalues = { + 0: 'DP_SEC_COLLISION_ACK_NO_EFFECT', + 1: 'DP_SEC_COLLISION_ACK_CLR_FLAG', +} +DP_SEC_COLLISION_ACK_NO_EFFECT = 0 +DP_SEC_COLLISION_ACK_CLR_FLAG = 1 +DP_SEC_COLLISION_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_AUDIO_MUTE' +DP_SEC_AUDIO_MUTE__enumvalues = { + 0: 'DP_SEC_AUDIO_MUTE_HW_CTRL', + 1: 'DP_SEC_AUDIO_MUTE_SW_CTRL', +} +DP_SEC_AUDIO_MUTE_HW_CTRL = 0 +DP_SEC_AUDIO_MUTE_SW_CTRL = 1 +DP_SEC_AUDIO_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_TIMESTAMP_MODE' +DP_SEC_TIMESTAMP_MODE__enumvalues = { + 0: 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', + 1: 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', +} +DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0 +DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 1 +DP_SEC_TIMESTAMP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_ASP_PRIORITY' +DP_SEC_ASP_PRIORITY__enumvalues = { + 0: 'DP_SEC_ASP_LOW_PRIORITY', + 1: 'DP_SEC_ASP_HIGH_PRIORITY', +} +DP_SEC_ASP_LOW_PRIORITY = 0 +DP_SEC_ASP_HIGH_PRIORITY = 1 +DP_SEC_ASP_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE' +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = { + 0: 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', + 1: 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', +} +DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0 +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1 +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_UPDATE_ACT' +DP_MSE_SAT_UPDATE_ACT__enumvalues = { + 0: 'DP_MSE_SAT_UPDATE_NO_ACTION', + 1: 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', + 2: 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', +} +DP_MSE_SAT_UPDATE_NO_ACTION = 0 +DP_MSE_SAT_UPDATE_WITH_TRIGGER = 1 +DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 2 +DP_MSE_SAT_UPDATE_ACT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_LINK_LINE' +DP_MSE_LINK_LINE__enumvalues = { + 0: 'DP_MSE_LINK_LINE_32_MTP_LONG', + 1: 'DP_MSE_LINK_LINE_64_MTP_LONG', + 2: 'DP_MSE_LINK_LINE_128_MTP_LONG', + 3: 'DP_MSE_LINK_LINE_256_MTP_LONG', +} +DP_MSE_LINK_LINE_32_MTP_LONG = 0 +DP_MSE_LINK_LINE_64_MTP_LONG = 1 +DP_MSE_LINK_LINE_128_MTP_LONG = 2 +DP_MSE_LINK_LINE_256_MTP_LONG = 3 +DP_MSE_LINK_LINE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_BLANK_CODE' +DP_MSE_BLANK_CODE__enumvalues = { + 0: 'DP_MSE_BLANK_CODE_SF_FILLED', + 1: 'DP_MSE_BLANK_CODE_ZERO_FILLED', +} +DP_MSE_BLANK_CODE_SF_FILLED = 0 +DP_MSE_BLANK_CODE_ZERO_FILLED = 1 +DP_MSE_BLANK_CODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_TIMESTAMP_MODE' +DP_MSE_TIMESTAMP_MODE__enumvalues = { + 0: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', + 1: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', +} +DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0 +DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 1 +DP_MSE_TIMESTAMP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_ZERO_ENCODER' +DP_MSE_ZERO_ENCODER__enumvalues = { + 0: 'DP_MSE_NOT_ZERO_FE_ENCODER', + 1: 'DP_MSE_ZERO_FE_ENCODER', +} +DP_MSE_NOT_ZERO_FE_ENCODER = 0 +DP_MSE_ZERO_FE_ENCODER = 1 +DP_MSE_ZERO_ENCODER = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_OUTPUT_DPDBG_DATA' +DP_MSE_OUTPUT_DPDBG_DATA__enumvalues = { + 0: 'DP_MSE_OUTPUT_DPDBG_DATA_DIS', + 1: 'DP_MSE_OUTPUT_DPDBG_DATA_EN', +} +DP_MSE_OUTPUT_DPDBG_DATA_DIS = 0 +DP_MSE_OUTPUT_DPDBG_DATA_EN = 1 +DP_MSE_OUTPUT_DPDBG_DATA = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE' +DP_DPHY_HBR2_PATTERN_CONTROL_MODE__enumvalues = { + 0: 'DP_DPHY_HBR2_PASS_THROUGH', + 1: 'DP_DPHY_HBR2_PATTERN_1', + 2: 'DP_DPHY_HBR2_PATTERN_2_NEG', + 3: 'DP_DPHY_HBR2_PATTERN_3', + 6: 'DP_DPHY_HBR2_PATTERN_2_POS', +} +DP_DPHY_HBR2_PASS_THROUGH = 0 +DP_DPHY_HBR2_PATTERN_1 = 1 +DP_DPHY_HBR2_PATTERN_2_NEG = 2 +DP_DPHY_HBR2_PATTERN_3 = 3 +DP_DPHY_HBR2_PATTERN_2_POS = 6 +DP_DPHY_HBR2_PATTERN_CONTROL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_MST_PHASE_ERROR_ACK' +DPHY_CRC_MST_PHASE_ERROR_ACK__enumvalues = { + 0: 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', + 1: 'DPHY_CRC_MST_PHASE_ERROR_ACKED', +} +DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0 +DPHY_CRC_MST_PHASE_ERROR_ACKED = 1 +DPHY_CRC_MST_PHASE_ERROR_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SW_FAST_TRAINING_START' +DPHY_SW_FAST_TRAINING_START__enumvalues = { + 0: 'DPHY_SW_FAST_TRAINING_NOT_STARTED', + 1: 'DPHY_SW_FAST_TRAINING_STARTED', +} +DPHY_SW_FAST_TRAINING_NOT_STARTED = 0 +DPHY_SW_FAST_TRAINING_STARTED = 1 +DPHY_SW_FAST_TRAINING_START = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN' +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__enumvalues = { + 0: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', + 1: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', +} +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0 +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 1 +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK' +DP_DPHY_FAST_TRAINING_COMPLETE_MASK__enumvalues = { + 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', + 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', +} +DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0 +DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 1 +DP_DPHY_FAST_TRAINING_COMPLETE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK' +DP_DPHY_FAST_TRAINING_COMPLETE_ACK__enumvalues = { + 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', + 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', +} +DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0 +DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 1 +DP_DPHY_FAST_TRAINING_COMPLETE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSA_V_TIMING_OVERRIDE_EN' +DP_MSA_V_TIMING_OVERRIDE_EN__enumvalues = { + 0: 'MSA_V_TIMING_OVERRIDE_DISABLED', + 1: 'MSA_V_TIMING_OVERRIDE_ENABLED', +} +MSA_V_TIMING_OVERRIDE_DISABLED = 0 +MSA_V_TIMING_OVERRIDE_ENABLED = 1 +DP_MSA_V_TIMING_OVERRIDE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP0_PRIORITY' +DP_SEC_GSP0_PRIORITY__enumvalues = { + 0: 'SEC_GSP0_PRIORITY_LOW', + 1: 'SEC_GSP0_PRIORITY_HIGH', +} +SEC_GSP0_PRIORITY_LOW = 0 +SEC_GSP0_PRIORITY_HIGH = 1 +DP_SEC_GSP0_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP0_SEND' +DP_SEC_GSP0_SEND__enumvalues = { + 0: 'NOT_SENT', + 1: 'FORCE_SENT', +} +NOT_SENT = 0 +FORCE_SENT = 1 +DP_SEC_GSP0_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_UPDATE_LOCK' +COL_MAN_UPDATE_LOCK__enumvalues = { + 0: 'COL_MAN_UPDATE_UNLOCKED', + 1: 'COL_MAN_UPDATE_LOCKED', +} +COL_MAN_UPDATE_UNLOCKED = 0 +COL_MAN_UPDATE_LOCKED = 1 +COL_MAN_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_DISABLE_MULTIPLE_UPDATE' +COL_MAN_DISABLE_MULTIPLE_UPDATE__enumvalues = { + 0: 'COL_MAN_MULTIPLE_UPDATE', + 1: 'COL_MAN_MULTIPLE_UPDAT_EDISABLE', +} +COL_MAN_MULTIPLE_UPDATE = 0 +COL_MAN_MULTIPLE_UPDAT_EDISABLE = 1 +COL_MAN_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_INPUTCSC_MODE' +COL_MAN_INPUTCSC_MODE__enumvalues = { + 0: 'INPUTCSC_MODE_BYPASS', + 1: 'INPUTCSC_MODE_A', + 2: 'INPUTCSC_MODE_B', + 3: 'INPUTCSC_MODE_UNITY', +} +INPUTCSC_MODE_BYPASS = 0 +INPUTCSC_MODE_A = 1 +INPUTCSC_MODE_B = 2 +INPUTCSC_MODE_UNITY = 3 +COL_MAN_INPUTCSC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_INPUTCSC_TYPE' +COL_MAN_INPUTCSC_TYPE__enumvalues = { + 0: 'INPUTCSC_TYPE_12_0', + 1: 'INPUTCSC_TYPE_10_2', + 2: 'INPUTCSC_TYPE_8_4', +} +INPUTCSC_TYPE_12_0 = 0 +INPUTCSC_TYPE_10_2 = 1 +INPUTCSC_TYPE_8_4 = 2 +COL_MAN_INPUTCSC_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_INPUTCSC_CONVERT' +COL_MAN_INPUTCSC_CONVERT__enumvalues = { + 0: 'INPUTCSC_ROUND', + 1: 'INPUTCSC_TRUNCATE', +} +INPUTCSC_ROUND = 0 +INPUTCSC_TRUNCATE = 1 +COL_MAN_INPUTCSC_CONVERT = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_PRESCALE_MODE' +COL_MAN_PRESCALE_MODE__enumvalues = { + 0: 'PRESCALE_MODE_BYPASS', + 1: 'PRESCALE_MODE_PROGRAM', + 2: 'PRESCALE_MODE_UNITY', +} +PRESCALE_MODE_BYPASS = 0 +PRESCALE_MODE_PROGRAM = 1 +PRESCALE_MODE_UNITY = 2 +COL_MAN_PRESCALE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_INPUT_GAMMA_MODE' +COL_MAN_INPUT_GAMMA_MODE__enumvalues = { + 0: 'INGAMMA_MODE_BYPASS', + 1: 'INGAMMA_MODE_FIX', + 2: 'INGAMMA_MODE_FLOAT', +} +INGAMMA_MODE_BYPASS = 0 +INGAMMA_MODE_FIX = 1 +INGAMMA_MODE_FLOAT = 2 +COL_MAN_INPUT_GAMMA_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_OUTPUT_CSC_MODE' +COL_MAN_OUTPUT_CSC_MODE__enumvalues = { + 0: 'COL_MAN_OUTPUT_CSC_BYPASS', + 1: 'COL_MAN_OUTPUT_CSC_RGB', + 2: 'COL_MAN_OUTPUT_CSC_YCrCb601', + 3: 'COL_MAN_OUTPUT_CSC_YCrCb709', + 4: 'COL_MAN_OUTPUT_CSC_A', + 5: 'COL_MAN_OUTPUT_CSC_B', + 6: 'COL_MAN_OUTPUT_CSC_UNITY', +} +COL_MAN_OUTPUT_CSC_BYPASS = 0 +COL_MAN_OUTPUT_CSC_RGB = 1 +COL_MAN_OUTPUT_CSC_YCrCb601 = 2 +COL_MAN_OUTPUT_CSC_YCrCb709 = 3 +COL_MAN_OUTPUT_CSC_A = 4 +COL_MAN_OUTPUT_CSC_B = 5 +COL_MAN_OUTPUT_CSC_UNITY = 6 +COL_MAN_OUTPUT_CSC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_DENORM_CLAMP_CONTROL' +COL_MAN_DENORM_CLAMP_CONTROL__enumvalues = { + 0: 'DENORM_CLAMP_MODE_UNITY', + 1: 'DENORM_CLAMP_MODE_8', + 2: 'DENORM_CLAMP_MODE_10', + 3: 'DENORM_CLAMP_MODE_12', +} +DENORM_CLAMP_MODE_UNITY = 0 +DENORM_CLAMP_MODE_8 = 1 +DENORM_CLAMP_MODE_10 = 2 +DENORM_CLAMP_MODE_12 = 3 +COL_MAN_DENORM_CLAMP_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_REGAMMA_MODE_CONTROL' +COL_MAN_REGAMMA_MODE_CONTROL__enumvalues = { + 0: 'COL_MAN_REGAMMA_MODE_BYPASS', + 1: 'COL_MAN_REGAMMA_MODE_ROM_A', + 2: 'COL_MAN_REGAMMA_MODE_ROM_B', + 3: 'COL_MAN_REGAMMA_MODE_A', + 4: 'COL_MAN_REGAMMA_MODE_B', +} +COL_MAN_REGAMMA_MODE_BYPASS = 0 +COL_MAN_REGAMMA_MODE_ROM_A = 1 +COL_MAN_REGAMMA_MODE_ROM_B = 2 +COL_MAN_REGAMMA_MODE_A = 3 +COL_MAN_REGAMMA_MODE_B = 4 +COL_MAN_REGAMMA_MODE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_GLOBAL_PASSTHROUGH_ENABLE' +COL_MAN_GLOBAL_PASSTHROUGH_ENABLE__enumvalues = { + 0: 'CM_GLOBAL_PASSTHROUGH_DISBALE', + 1: 'CM_GLOBAL_PASSTHROUGH_ENABLE', +} +CM_GLOBAL_PASSTHROUGH_DISBALE = 0 +CM_GLOBAL_PASSTHROUGH_ENABLE = 1 +COL_MAN_GLOBAL_PASSTHROUGH_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_DEGAMMA_MODE' +COL_MAN_DEGAMMA_MODE__enumvalues = { + 0: 'DEGAMMA_MODE_BYPASS', + 1: 'DEGAMMA_MODE_A', + 2: 'DEGAMMA_MODE_B', +} +DEGAMMA_MODE_BYPASS = 0 +DEGAMMA_MODE_A = 1 +DEGAMMA_MODE_B = 2 +COL_MAN_DEGAMMA_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_GAMUT_REMAP_MODE' +COL_MAN_GAMUT_REMAP_MODE__enumvalues = { + 0: 'GAMUT_REMAP_MODE_BYPASS', + 1: 'GAMUT_REMAP_MODE_1', + 2: 'GAMUT_REMAP_MODE_2', + 3: 'GAMUT_REMAP_MODE_3', +} +GAMUT_REMAP_MODE_BYPASS = 0 +GAMUT_REMAP_MODE_1 = 1 +GAMUT_REMAP_MODE_2 = 2 +GAMUT_REMAP_MODE_3 = 3 +COL_MAN_GAMUT_REMAP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_CONTROL_HPD_SEL' +DP_AUX_CONTROL_HPD_SEL__enumvalues = { + 0: 'DP_AUX_CONTROL_HPD1_SELECTED', + 1: 'DP_AUX_CONTROL_HPD2_SELECTED', + 2: 'DP_AUX_CONTROL_HPD3_SELECTED', + 3: 'DP_AUX_CONTROL_HPD4_SELECTED', + 4: 'DP_AUX_CONTROL_HPD5_SELECTED', + 5: 'DP_AUX_CONTROL_HPD6_SELECTED', +} +DP_AUX_CONTROL_HPD1_SELECTED = 0 +DP_AUX_CONTROL_HPD2_SELECTED = 1 +DP_AUX_CONTROL_HPD3_SELECTED = 2 +DP_AUX_CONTROL_HPD4_SELECTED = 3 +DP_AUX_CONTROL_HPD5_SELECTED = 4 +DP_AUX_CONTROL_HPD6_SELECTED = 5 +DP_AUX_CONTROL_HPD_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_CONTROL_TEST_MODE' +DP_AUX_CONTROL_TEST_MODE__enumvalues = { + 0: 'DP_AUX_CONTROL_TEST_MODE_DISABLE', + 1: 'DP_AUX_CONTROL_TEST_MODE_ENABLE', +} +DP_AUX_CONTROL_TEST_MODE_DISABLE = 0 +DP_AUX_CONTROL_TEST_MODE_ENABLE = 1 +DP_AUX_CONTROL_TEST_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_SW_CONTROL_SW_GO' +DP_AUX_SW_CONTROL_SW_GO__enumvalues = { + 0: 'DP_AUX_SW_CONTROL_SW__NOT_GO', + 1: 'DP_AUX_SW_CONTROL_SW__GO', +} +DP_AUX_SW_CONTROL_SW__NOT_GO = 0 +DP_AUX_SW_CONTROL_SW__GO = 1 +DP_AUX_SW_CONTROL_SW_GO = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_SW_CONTROL_LS_READ_TRIG' +DP_AUX_SW_CONTROL_LS_READ_TRIG__enumvalues = { + 0: 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', + 1: 'DP_AUX_SW_CONTROL_LS_READ__TRIG', +} +DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0 +DP_AUX_SW_CONTROL_LS_READ__TRIG = 1 +DP_AUX_SW_CONTROL_LS_READ_TRIG = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_CONTROL_ARB_PRIORITY' +DP_AUX_ARB_CONTROL_ARB_PRIORITY__enumvalues = { + 0: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', + 1: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', + 2: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', + 3: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', +} +DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0 +DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 1 +DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 2 +DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 3 +DP_AUX_ARB_CONTROL_ARB_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ' +DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ__enumvalues = { + 0: 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', + 1: 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', +} +DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0 +DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 1 +DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG' +DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG__enumvalues = { + 0: 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', + 1: 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', +} +DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0 +DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 1 +DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_INT_ACK' +DP_AUX_INT_ACK__enumvalues = { + 0: 'DP_AUX_INT__NOT_ACK', + 1: 'DP_AUX_INT__ACK', +} +DP_AUX_INT__NOT_ACK = 0 +DP_AUX_INT__ACK = 1 +DP_AUX_INT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_LS_UPDATE_ACK' +DP_AUX_LS_UPDATE_ACK__enumvalues = { + 0: 'DP_AUX_INT_LS_UPDATE_NOT_ACK', + 1: 'DP_AUX_INT_LS_UPDATE_ACK', +} +DP_AUX_INT_LS_UPDATE_NOT_ACK = 0 +DP_AUX_INT_LS_UPDATE_ACK = 1 +DP_AUX_LS_UPDATE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL' +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__enumvalues = { + 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', + 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', +} +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0 +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 1 +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE' +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__enumvalues = { + 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', + 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', + 2: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', + 3: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', +} +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 1 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 2 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 3 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN' +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__enumvalues = { + 0: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US', + 1: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US', + 2: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US', + 3: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US', + 4: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US', + 5: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US', + 6: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US', + 7: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US', +} +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US = 0 +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US = 1 +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US = 2 +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US = 3 +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US = 4 +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US = 5 +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US = 6 +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US = 7 +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY' +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__enumvalues = { + 0: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', + 1: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', + 2: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', + 3: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', + 4: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', + 5: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', +} +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 1 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 2 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 3 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 4 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 5 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW' +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', + 1: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', + 2: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', + 3: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', + 4: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', + 5: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', + 6: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', + 7: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', +} +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 1 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 2 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 3 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 4 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 5 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 6 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 7 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW' +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', + 1: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', + 2: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', + 3: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', + 4: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', + 5: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', + 6: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', + 7: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', +} +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 1 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 2 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 3 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 4 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 5 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 6 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 7 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN' +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', + 1: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', + 2: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', + 3: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', +} +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 1 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 2 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 3 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT' +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', +} +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0 +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 1 +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START' +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', + 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', +} +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0 +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 1 +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP' +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', + 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', +} +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0 +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 1 +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN' +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', + 1: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', + 2: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', + 3: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', +} +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 1 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 2 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 3 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN' +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US', + 1: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US', + 2: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US', + 3: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US', + 4: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US', + 5: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US', + 6: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US', + 7: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US', +} +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US = 0 +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US = 1 +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US = 2 +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US = 3 +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US = 4 +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US = 5 +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US = 6 +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US = 7 +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD' +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__enumvalues = { + 0: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', + 1: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', + 2: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', + 3: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', + 4: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', + 5: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', + 6: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', + 7: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', +} +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 1 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 2 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 3 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 4 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 5 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 6 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 7 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ' +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', + 1: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', +} +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0 +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 1 +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW' +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', + 1: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', + 2: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', + 3: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', +} +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 1 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 2 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 3 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT' +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', + 1: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', + 2: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', + 3: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', +} +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 1 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 2 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 3 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN' +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', + 1: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', + 2: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', + 3: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', +} +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 1 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 2 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 3 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ERR_OCCURRED_ACK' +DP_AUX_ERR_OCCURRED_ACK__enumvalues = { + 0: 'DP_AUX_ERR_OCCURRED__NOT_ACK', + 1: 'DP_AUX_ERR_OCCURRED__ACK', +} +DP_AUX_ERR_OCCURRED__NOT_ACK = 0 +DP_AUX_ERR_OCCURRED__ACK = 1 +DP_AUX_ERR_OCCURRED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_POTENTIAL_ERR_REACHED_ACK' +DP_AUX_POTENTIAL_ERR_REACHED_ACK__enumvalues = { + 0: 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', + 1: 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', +} +DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0 +DP_AUX_POTENTIAL_ERR_REACHED__ACK = 1 +DP_AUX_POTENTIAL_ERR_REACHED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DEFINITE_ERR_REACHED_ACK' +DP_AUX_DEFINITE_ERR_REACHED_ACK__enumvalues = { + 0: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', + 1: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', +} +ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0 +ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 1 +DP_AUX_DEFINITE_ERR_REACHED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_RESET' +DP_AUX_RESET__enumvalues = { + 0: 'DP_AUX_RESET_DEASSERTED', + 1: 'DP_AUX_RESET_ASSERTED', +} +DP_AUX_RESET_DEASSERTED = 0 +DP_AUX_RESET_ASSERTED = 1 +DP_AUX_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_RESET_DONE' +DP_AUX_RESET_DONE__enumvalues = { + 0: 'DP_AUX_RESET_SEQUENCE_NOT_DONE', + 1: 'DP_AUX_RESET_SEQUENCE_DONE', +} +DP_AUX_RESET_SEQUENCE_NOT_DONE = 0 +DP_AUX_RESET_SEQUENCE_DONE = 1 +DP_AUX_RESET_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_COMMAND_MODE_SRC_FORMAT' +DSI_COMMAND_MODE_SRC_FORMAT__enumvalues = { + 2: 'DSI_COMMAND_SRC_FORMAT_RGB8BIT', + 3: 'DSI_COMMAND_SRC_FORMAT_RGB332', + 4: 'DSI_COMMAND_SRC_FORMAT_RGB444', + 5: 'DSI_COMMAND_SRC_FORMAT_RGB555', + 6: 'DSI_COMMAND_SRC_FORMAT_RGB565', + 8: 'DSI_COMMAND_SRC_FORMAT_RGB888', +} +DSI_COMMAND_SRC_FORMAT_RGB8BIT = 2 +DSI_COMMAND_SRC_FORMAT_RGB332 = 3 +DSI_COMMAND_SRC_FORMAT_RGB444 = 4 +DSI_COMMAND_SRC_FORMAT_RGB555 = 5 +DSI_COMMAND_SRC_FORMAT_RGB565 = 6 +DSI_COMMAND_SRC_FORMAT_RGB888 = 8 +DSI_COMMAND_MODE_SRC_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_COMMAND_MODE_DST_FORMAT' +DSI_COMMAND_MODE_DST_FORMAT__enumvalues = { + 0: 'DSI_COMMAND_DST_FORMAT_RGB111', + 3: 'DSI_COMMAND_DST_FORMAT_RGB332', + 4: 'DSI_COMMAND_DST_FORMAT_RGB444', + 6: 'DSI_COMMAND_DST_FORMAT_RGB565', + 7: 'DSI_COMMAND_DST_FORMAT_RGB666', + 8: 'DSI_COMMAND_DST_FORMAT_RGB888', +} +DSI_COMMAND_DST_FORMAT_RGB111 = 0 +DSI_COMMAND_DST_FORMAT_RGB332 = 3 +DSI_COMMAND_DST_FORMAT_RGB444 = 4 +DSI_COMMAND_DST_FORMAT_RGB565 = 6 +DSI_COMMAND_DST_FORMAT_RGB666 = 7 +DSI_COMMAND_DST_FORMAT_RGB888 = 8 +DSI_COMMAND_MODE_DST_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_FLAG_CLR' +DSI_FLAG_CLR__enumvalues = { + 0: 'DSI_FLAG_NO_CLEAR', + 1: 'DSI_FLAG_CLEAR', +} +DSI_FLAG_NO_CLEAR = 0 +DSI_FLAG_CLEAR = 1 +DSI_FLAG_CLR = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_BIT_SWAP' +DSI_BIT_SWAP__enumvalues = { + 0: 'DSI_BIT_SWAP_DISABLE', + 1: 'DSI_BIT_SWAP_ENABLE', +} +DSI_BIT_SWAP_DISABLE = 0 +DSI_BIT_SWAP_ENABLE = 1 +DSI_BIT_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CLK_GATING' +DSI_CLK_GATING__enumvalues = { + 0: 'DSI_CLK_GATING_ENABLE', + 1: 'DSI_CLK_GATING_DISABLE', +} +DSI_CLK_GATING_ENABLE = 0 +DSI_CLK_GATING_DISABLE = 1 +DSI_CLK_GATING = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_LANE_ULPS_REQUEST' +DSI_LANE_ULPS_REQUEST__enumvalues = { + 0: 'DSI_LANE_ULPS_REQUEST_DEASSERT', + 1: 'DSI_LANE_ULPS_REQUEST_ASSERT', +} +DSI_LANE_ULPS_REQUEST_DEASSERT = 0 +DSI_LANE_ULPS_REQUEST_ASSERT = 1 +DSI_LANE_ULPS_REQUEST = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_LANE_ULPS_EXIT' +DSI_LANE_ULPS_EXIT__enumvalues = { + 0: 'DSI_LANE_ULPS_EXIT_DEASSERT', + 1: 'DSI_LANE_ULPS_EXIT_ASSERT', +} +DSI_LANE_ULPS_EXIT_DEASSERT = 0 +DSI_LANE_ULPS_EXIT_ASSERT = 1 +DSI_LANE_ULPS_EXIT = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_LANE_FORCE_TX_STOP' +DSI_LANE_FORCE_TX_STOP__enumvalues = { + 0: 'DSI_LANE_FORCE_TX_STOP_DEASSERT', + 1: 'DSI_LANE_FORCE_TX_STOP_ASSERT', +} +DSI_LANE_FORCE_TX_STOP_DEASSERT = 0 +DSI_LANE_FORCE_TX_STOP_ASSERT = 1 +DSI_LANE_FORCE_TX_STOP = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CLOCK_LANE_HS_FORCE_REQUEST' +DSI_CLOCK_LANE_HS_FORCE_REQUEST__enumvalues = { + 0: 'DSI_CLOCK_LANE_HS_FORCE_REQUEST_DEASSERT', + 1: 'DSI_CLOCK_LANE_HS_FORCE_REQUEST_ASSERT', +} +DSI_CLOCK_LANE_HS_FORCE_REQUEST_DEASSERT = 0 +DSI_CLOCK_LANE_HS_FORCE_REQUEST_ASSERT = 1 +DSI_CLOCK_LANE_HS_FORCE_REQUEST = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CONTROLLER_EN' +DSI_CONTROLLER_EN__enumvalues = { + 0: 'DSI_CONTROLLER_DISABLE', + 1: 'DSI_CONTROLLER_ENABLE', +} +DSI_CONTROLLER_DISABLE = 0 +DSI_CONTROLLER_ENABLE = 1 +DSI_CONTROLLER_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_VIDEO_MODE_EN' +DSI_VIDEO_MODE_EN__enumvalues = { + 0: 'DSI_VIDEO_MODE_DISABLE', + 1: 'DSI_VIDEO_MODE_ENABLE', +} +DSI_VIDEO_MODE_DISABLE = 0 +DSI_VIDEO_MODE_ENABLE = 1 +DSI_VIDEO_MODE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CMD_MODE_EN' +DSI_CMD_MODE_EN__enumvalues = { + 0: 'DSI_CMD_MODE_DISABLE', + 1: 'DSI_CMD_MODE_ENABLE', +} +DSI_CMD_MODE_DISABLE = 0 +DSI_CMD_MODE_ENABLE = 1 +DSI_CMD_MODE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DATA_LANE0_EN' +DSI_DATA_LANE0_EN__enumvalues = { + 0: 'DSI_DATA_LANE0_DISABLE', + 1: 'DSI_DATA_LANE0_ENABLE', +} +DSI_DATA_LANE0_DISABLE = 0 +DSI_DATA_LANE0_ENABLE = 1 +DSI_DATA_LANE0_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DATA_LANE1_EN' +DSI_DATA_LANE1_EN__enumvalues = { + 0: 'DSI_DATA_LANE1_DISABLE', + 1: 'DSI_DATA_LANE1_ENABLE', +} +DSI_DATA_LANE1_DISABLE = 0 +DSI_DATA_LANE1_ENABLE = 1 +DSI_DATA_LANE1_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DATA_LANE2_EN' +DSI_DATA_LANE2_EN__enumvalues = { + 0: 'DSI_DATA_LANE2_DISABLE', + 1: 'DSI_DATA_LANE2_ENABLE', +} +DSI_DATA_LANE2_DISABLE = 0 +DSI_DATA_LANE2_ENABLE = 1 +DSI_DATA_LANE2_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DATA_LANE3_EN' +DSI_DATA_LANE3_EN__enumvalues = { + 0: 'DSI_DATA_LANE3_DISABLE', + 1: 'DSI_DATA_LANE3_ENABLE', +} +DSI_DATA_LANE3_DISABLE = 0 +DSI_DATA_LANE3_ENABLE = 1 +DSI_DATA_LANE3_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CLOCK_LANE_EN' +DSI_CLOCK_LANE_EN__enumvalues = { + 0: 'DSI_CLOCK_LANE_DISABLE', + 1: 'DSI_CLOCK_LANE_ENABLE', +} +DSI_CLOCK_LANE_DISABLE = 0 +DSI_CLOCK_LANE_ENABLE = 1 +DSI_CLOCK_LANE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_PHY_DATA_LANE0_EN' +DSI_PHY_DATA_LANE0_EN__enumvalues = { + 0: 'DSI_PHY_DATA_LANE0_DISABLE', + 1: 'DSI_PHY_DATA_LANE0_ENABLE', +} +DSI_PHY_DATA_LANE0_DISABLE = 0 +DSI_PHY_DATA_LANE0_ENABLE = 1 +DSI_PHY_DATA_LANE0_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_PHY_DATA_LANE1_EN' +DSI_PHY_DATA_LANE1_EN__enumvalues = { + 0: 'DSI_PHY_DATA_LANE1_DISABLE', + 1: 'DSI_PHY_DATA_LANE1_ENABLE', +} +DSI_PHY_DATA_LANE1_DISABLE = 0 +DSI_PHY_DATA_LANE1_ENABLE = 1 +DSI_PHY_DATA_LANE1_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_PHY_DATA_LANE2_EN' +DSI_PHY_DATA_LANE2_EN__enumvalues = { + 0: 'DSI_PHY_DATA_LANE2_DISABLE', + 1: 'DSI_PHY_DATA_LANE2_ENABLE', +} +DSI_PHY_DATA_LANE2_DISABLE = 0 +DSI_PHY_DATA_LANE2_ENABLE = 1 +DSI_PHY_DATA_LANE2_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_PHY_DATA_LANE3_EN' +DSI_PHY_DATA_LANE3_EN__enumvalues = { + 0: 'DSI_PHY_DATA_LANE3_DISABLE', + 1: 'DSI_PHY_DATA_LANE3_ENABLE', +} +DSI_PHY_DATA_LANE3_DISABLE = 0 +DSI_PHY_DATA_LANE3_ENABLE = 1 +DSI_PHY_DATA_LANE3_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_RESET_DISPCLK' +DSI_RESET_DISPCLK__enumvalues = { + 0: 'DSI_NO_RESET_ON_DISPCLK_DOMAIN_LOGIC', + 1: 'DSI_RESET_ON_DISPCLK_DOMAIN_LOGIC', +} +DSI_NO_RESET_ON_DISPCLK_DOMAIN_LOGIC = 0 +DSI_RESET_ON_DISPCLK_DOMAIN_LOGIC = 1 +DSI_RESET_DISPCLK = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_RESET_DSICLK' +DSI_RESET_DSICLK__enumvalues = { + 0: 'DSI_NO_RESET_ON_DSICLK_DOMAIN_LOGIC', + 1: 'DSI_RESET_ON_DSICLK_DOMAIN_LOGIC', +} +DSI_NO_RESET_ON_DSICLK_DOMAIN_LOGIC = 0 +DSI_RESET_ON_DSICLK_DOMAIN_LOGIC = 1 +DSI_RESET_DSICLK = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_RESET_BYTECLK' +DSI_RESET_BYTECLK__enumvalues = { + 0: 'DSI_NO_RESET_ON_BYTECLK_DOMAIN_LOGIC', + 1: 'DSI_RESET_ON_BYTECLK_DOMAIN_LOGIC', +} +DSI_NO_RESET_ON_BYTECLK_DOMAIN_LOGIC = 0 +DSI_RESET_ON_BYTECLK_DOMAIN_LOGIC = 1 +DSI_RESET_BYTECLK = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_RESET_ESCCLK' +DSI_RESET_ESCCLK__enumvalues = { + 0: 'DSI_NO_RESET_ON_ESCCLK_DOMAIN_LOGIC', + 1: 'DSI_RESET_ON_ESCCLK_DOMAIN_LOGIC', +} +DSI_NO_RESET_ON_ESCCLK_DOMAIN_LOGIC = 0 +DSI_RESET_ON_ESCCLK_DOMAIN_LOGIC = 1 +DSI_RESET_ESCCLK = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CRTC_SEL' +DSI_CRTC_SEL__enumvalues = { + 0: 'DSI_GET_PIXEL_STREAM_FROM_FMT0', + 1: 'DSI_GET_PIXEL_STREAM_FROM_FMT1', + 2: 'DSI_GET_PIXEL_STREAM_FROM_FMT2', + 3: 'DSI_GET_PIXEL_STREAM_FROM_FMT3', + 4: 'DSI_GET_PIXEL_STREAM_FROM_FMT4', + 5: 'DSI_GET_PIXEL_STREAM_FROM_FMT5', +} +DSI_GET_PIXEL_STREAM_FROM_FMT0 = 0 +DSI_GET_PIXEL_STREAM_FROM_FMT1 = 1 +DSI_GET_PIXEL_STREAM_FROM_FMT2 = 2 +DSI_GET_PIXEL_STREAM_FROM_FMT3 = 3 +DSI_GET_PIXEL_STREAM_FROM_FMT4 = 4 +DSI_GET_PIXEL_STREAM_FROM_FMT5 = 5 +DSI_CRTC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_PACKET_BYTE_MSB_LSB_FLIP' +DSI_PACKET_BYTE_MSB_LSB_FLIP__enumvalues = { + 0: 'DSI_PACKET_BYTE_MSB_LSB_FLIP_NO_SWAP', + 1: 'DSI_PACKET_BYTE_MSB_LSB_FLIP_SWAP', +} +DSI_PACKET_BYTE_MSB_LSB_FLIP_NO_SWAP = 0 +DSI_PACKET_BYTE_MSB_LSB_FLIP_SWAP = 1 +DSI_PACKET_BYTE_MSB_LSB_FLIP = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_VIDEO_MODE_DST_FORMAT' +DSI_VIDEO_MODE_DST_FORMAT__enumvalues = { + 0: 'DSI_VIDEO_DST_FORMAT_RGB565', + 1: 'DSI_VIDEO_DST_FORMAT_RGB666_PACKED', + 2: 'DSI_VIDEO_DST_FORMAT_RGB666_LOOSELY_PACKED', + 3: 'DSI_VIDEO_DST_FORMAT_RGB888', +} +DSI_VIDEO_DST_FORMAT_RGB565 = 0 +DSI_VIDEO_DST_FORMAT_RGB666_PACKED = 1 +DSI_VIDEO_DST_FORMAT_RGB666_LOOSELY_PACKED = 2 +DSI_VIDEO_DST_FORMAT_RGB888 = 3 +DSI_VIDEO_MODE_DST_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_VIDEO_TRAFFIC_MODE' +DSI_VIDEO_TRAFFIC_MODE__enumvalues = { + 0: 'DSI_TRAFFIC_MODE_SYNC_PULSES', + 1: 'DSI_TRAFFIC_MODE_SYNC_EVENTS', + 2: 'DSI_TRAFFIC_MODE_BURST', + 3: 'DSI_TRAFFIC_MODE_RESERVED', +} +DSI_TRAFFIC_MODE_SYNC_PULSES = 0 +DSI_TRAFFIC_MODE_SYNC_EVENTS = 1 +DSI_TRAFFIC_MODE_BURST = 2 +DSI_TRAFFIC_MODE_RESERVED = 3 +DSI_VIDEO_TRAFFIC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_VIDEO_BLLP_PWR_MODE' +DSI_VIDEO_BLLP_PWR_MODE__enumvalues = { + 0: 'DSI_VIDEO_BLLP_PWR_MODE_HS', + 1: 'DSI_VIDEO_BLLP_PWR_MODE_LP', +} +DSI_VIDEO_BLLP_PWR_MODE_HS = 0 +DSI_VIDEO_BLLP_PWR_MODE_LP = 1 +DSI_VIDEO_BLLP_PWR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_VIDEO_EOF_BLLP_PWR_MODE' +DSI_VIDEO_EOF_BLLP_PWR_MODE__enumvalues = { + 0: 'DSI_VIDEO_EOF_BLLP_PWR_MODE_HS', + 1: 'DSI_VIDEO_EOF_BLLP_PWR_MODE_LP', +} +DSI_VIDEO_EOF_BLLP_PWR_MODE_HS = 0 +DSI_VIDEO_EOF_BLLP_PWR_MODE_LP = 1 +DSI_VIDEO_EOF_BLLP_PWR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_VIDEO_PWR_MODE' +DSI_VIDEO_PWR_MODE__enumvalues = { + 0: 'DSI_VIDEO_PWR_MODE_HS', + 1: 'DSI_VIDEO_PWR_MODE_LP', +} +DSI_VIDEO_PWR_MODE_HS = 0 +DSI_VIDEO_PWR_MODE_LP = 1 +DSI_VIDEO_PWR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_VIDEO_PULSE_MODE_OPT' +DSI_VIDEO_PULSE_MODE_OPT__enumvalues = { + 0: 'PULSE_MODE_OPT_NO_HSA', + 1: 'PULSE_MODE_OPT_SEND', +} +PULSE_MODE_OPT_NO_HSA = 0 +PULSE_MODE_OPT_SEND = 1 +DSI_VIDEO_PULSE_MODE_OPT = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_RGB_SWAP' +DSI_RGB_SWAP__enumvalues = { + 0: 'DSI_SWAP_RGB', + 1: 'DSI_SWAP_RBG', + 2: 'DSI_SWAP_BGR', + 3: 'DSI_SWAP_BRG', + 4: 'DSI_SWAP_GRB', + 5: 'DSI_SWAP_GBR', +} +DSI_SWAP_RGB = 0 +DSI_SWAP_RBG = 1 +DSI_SWAP_BGR = 2 +DSI_SWAP_BRG = 3 +DSI_SWAP_GRB = 4 +DSI_SWAP_GBR = 5 +DSI_RGB_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CMD_PACKET_TYPE' +DSI_CMD_PACKET_TYPE__enumvalues = { + 0: 'DSI_CMD_PACKET_TYPE_SHORT', + 1: 'DSI_CMD_PACKET_TYPE_LONG', +} +DSI_CMD_PACKET_TYPE_SHORT = 0 +DSI_CMD_PACKET_TYPE_LONG = 1 +DSI_CMD_PACKET_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CMD_PWR_MODE' +DSI_CMD_PWR_MODE__enumvalues = { + 0: 'DSI_CMD_PWR_MODE_HS', + 1: 'DSI_CMD_PWR_MODE_LP', +} +DSI_CMD_PWR_MODE_HS = 0 +DSI_CMD_PWR_MODE_LP = 1 +DSI_CMD_PWR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CMD_EMBEDDED_MODE' +DSI_CMD_EMBEDDED_MODE__enumvalues = { + 0: 'CMD_EMBEDDED_MODE_DISABLE', + 1: 'CMD_EMBEDDED_MODE_ENABLE', +} +CMD_EMBEDDED_MODE_DISABLE = 0 +CMD_EMBEDDED_MODE_ENABLE = 1 +DSI_CMD_EMBEDDED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CMD_ORDER' +DSI_CMD_ORDER__enumvalues = { + 0: 'DSI_CMD_ORDER_COMMAND_FIRST', + 1: 'DSI_CMD_ORDER_DATA_FIRST', +} +DSI_CMD_ORDER_COMMAND_FIRST = 0 +DSI_CMD_ORDER_DATA_FIRST = 1 +DSI_CMD_ORDER = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DATA_BUFFER_ID' +DSI_DATA_BUFFER_ID__enumvalues = { + 0: 'DSI_DATA_BUFFER_OFFSET0', + 1: 'DSI_DATA_BUFFER_OFFSET1', +} +DSI_DATA_BUFFER_OFFSET0 = 0 +DSI_DATA_BUFFER_OFFSET1 = 1 +DSI_DATA_BUFFER_ID = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DWORD_BYTE_SWAP' +DSI_DWORD_BYTE_SWAP__enumvalues = { + 0: 'DWORD_BYTE_SWAP_NO_SWAP', + 1: 'DWORD_BYTE_SWAP_BYTE_SWAP', + 2: 'DWORD_BYTE_SWAP_WORD_SWAP', + 3: 'DWORD_BYTE_SWAP_BOTH_SWAP', +} +DWORD_BYTE_SWAP_NO_SWAP = 0 +DWORD_BYTE_SWAP_BYTE_SWAP = 1 +DWORD_BYTE_SWAP_WORD_SWAP = 2 +DWORD_BYTE_SWAP_BOTH_SWAP = 3 +DSI_DWORD_BYTE_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_INSERT_DCS_COMMAND' +DSI_INSERT_DCS_COMMAND__enumvalues = { + 0: 'DSI_INSERT_DCS_COMMAND_DISABLE', + 1: 'DSI_INSERT_DCS_COMMAND_ENABLE', +} +DSI_INSERT_DCS_COMMAND_DISABLE = 0 +DSI_INSERT_DCS_COMMAND_ENABLE = 1 +DSI_INSERT_DCS_COMMAND = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DMAFIFO_WRITE_WATERMARK' +DSI_DMAFIFO_WRITE_WATERMARK__enumvalues = { + 0: 'DSI_DMAFIFO_WRITE_WATERMARK_HALF', + 1: 'DSI_DMAFIFO_WRITE_WATERMARK_FOURTH', + 2: 'DSI_DMAFIFO_WRITE_WATERMARK_EIGHTH', + 3: 'DSI_DMAFIFO_WRITE_WATERMARK_SIXTEENTH', +} +DSI_DMAFIFO_WRITE_WATERMARK_HALF = 0 +DSI_DMAFIFO_WRITE_WATERMARK_FOURTH = 1 +DSI_DMAFIFO_WRITE_WATERMARK_EIGHTH = 2 +DSI_DMAFIFO_WRITE_WATERMARK_SIXTEENTH = 3 +DSI_DMAFIFO_WRITE_WATERMARK = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DMAFIFO_READ_WATERMARK' +DSI_DMAFIFO_READ_WATERMARK__enumvalues = { + 0: 'DSI_DMAFIFO_READ_WATERMARK_HALF', + 1: 'DSI_DMAFIFO_READ_WATERMARK_FOURTH', + 2: 'DSI_DMAFIFO_READ_WATERMARK_EIGHTH', + 3: 'DSI_DMAFIFO_READ_WATERMARK_SIXTEENTH', +} +DSI_DMAFIFO_READ_WATERMARK_HALF = 0 +DSI_DMAFIFO_READ_WATERMARK_FOURTH = 1 +DSI_DMAFIFO_READ_WATERMARK_EIGHTH = 2 +DSI_DMAFIFO_READ_WATERMARK_SIXTEENTH = 3 +DSI_DMAFIFO_READ_WATERMARK = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_USE_DENG_LENGTH' +DSI_USE_DENG_LENGTH__enumvalues = { + 0: 'DSI_USE_DENG_LENGTH_DISABLE', + 1: 'DSI_USE_DENG_LENGTH_ENABLE', +} +DSI_USE_DENG_LENGTH_DISABLE = 0 +DSI_USE_DENG_LENGTH_ENABLE = 1 +DSI_USE_DENG_LENGTH = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_COMMAND_TRIGGER_MODE' +DSI_COMMAND_TRIGGER_MODE__enumvalues = { + 0: 'DSI_COMMAND_TRIGGER_MODE_AUTO', + 1: 'DSI_COMMAND_TRIGGER_MODE_MANUAL', +} +DSI_COMMAND_TRIGGER_MODE_AUTO = 0 +DSI_COMMAND_TRIGGER_MODE_MANUAL = 1 +DSI_COMMAND_TRIGGER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_COMMAND_TRIGGER_SEL' +DSI_COMMAND_TRIGGER_SEL__enumvalues = { + 0: 'DSI_COMMAND_TRIGGER_SEL_NONE', + 1: 'DSI_COMMAND_TRIGGER_SEL_CRTC', + 2: 'DSI_COMMAND_TRIGGER_SEL_TE', + 3: 'DSI_COMMAND_TRIGGER_SEL_HW', +} +DSI_COMMAND_TRIGGER_SEL_NONE = 0 +DSI_COMMAND_TRIGGER_SEL_CRTC = 1 +DSI_COMMAND_TRIGGER_SEL_TE = 2 +DSI_COMMAND_TRIGGER_SEL_HW = 3 +DSI_COMMAND_TRIGGER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_HW_SOURCE_SEL' +DSI_HW_SOURCE_SEL__enumvalues = { + 0: 'HW_SOURCE_SEL_NONE', + 1: 'HW_SOURCE_SEL_DSC_VUP', + 2: 'HW_SOURCE_SEL_DSC_VLP', + 3: 'HW_SOURCE_SEL_DSC_JPEG', +} +HW_SOURCE_SEL_NONE = 0 +HW_SOURCE_SEL_DSC_VUP = 1 +HW_SOURCE_SEL_DSC_VLP = 2 +HW_SOURCE_SEL_DSC_JPEG = 3 +DSI_HW_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_COMMAND_TRIGGER_ORDER' +DSI_COMMAND_TRIGGER_ORDER__enumvalues = { + 0: 'DSI_COMMAND_TRIGGER_ORDER_DMA', + 1: 'DSI_COMMAND_TRIGGER_ORDER_DENG', +} +DSI_COMMAND_TRIGGER_ORDER_DMA = 0 +DSI_COMMAND_TRIGGER_ORDER_DENG = 1 +DSI_COMMAND_TRIGGER_ORDER = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_TE_SRC_SEL' +DSI_TE_SRC_SEL__enumvalues = { + 0: 'DSI_TE_SEL_LINK', + 1: 'DSI_TE_SEL_PIN', +} +DSI_TE_SEL_LINK = 0 +DSI_TE_SEL_PIN = 1 +DSI_TE_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_EXT_TE_MUX' +DSI_EXT_TE_MUX__enumvalues = { + 0: 'DSI_XT_TE_MUX_LCDD17', + 1: 'DSI_XT_TE_MUX_DCLK', + 2: 'DSI_XT_TE_MUX_SS', + 3: 'DSI_XT_TE_MUX_GCLK', + 4: 'DSI_XT_TE_MUX_GOE', + 5: 'DSI_XT_TE_MUX_DINV', + 6: 'DSI_XT_TE_MUX_FRAME', + 7: 'DSI_XT_TE_MUX_GPIO4', + 8: 'DSI_XT_TE_MUX_GPIO5', +} +DSI_XT_TE_MUX_LCDD17 = 0 +DSI_XT_TE_MUX_DCLK = 1 +DSI_XT_TE_MUX_SS = 2 +DSI_XT_TE_MUX_GCLK = 3 +DSI_XT_TE_MUX_GOE = 4 +DSI_XT_TE_MUX_DINV = 5 +DSI_XT_TE_MUX_FRAME = 6 +DSI_XT_TE_MUX_GPIO4 = 7 +DSI_XT_TE_MUX_GPIO5 = 8 +DSI_EXT_TE_MUX = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_EXT_TE_MODE' +DSI_EXT_TE_MODE__enumvalues = { + 0: 'DSI_EXT_TE_MODE_VSYNC_EDGE', + 1: 'DSI_EXT_TE_MODE_VSYNC_WIDTH', + 2: 'DSI_EXT_TE_MODE_HVSYNC_EDGE', + 3: 'DSI_EXT_TE_MODE_HVSYNC_WIDTH', +} +DSI_EXT_TE_MODE_VSYNC_EDGE = 0 +DSI_EXT_TE_MODE_VSYNC_WIDTH = 1 +DSI_EXT_TE_MODE_HVSYNC_EDGE = 2 +DSI_EXT_TE_MODE_HVSYNC_WIDTH = 3 +DSI_EXT_TE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_EXT_RESET_POL' +DSI_EXT_RESET_POL__enumvalues = { + 0: 'DSI_EXT_RESET_POL_HIGH', + 1: 'DSI_EXT_RESET_POL_LOW', +} +DSI_EXT_RESET_POL_HIGH = 0 +DSI_EXT_RESET_POL_LOW = 1 +DSI_EXT_RESET_POL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_EXT_TE_POL' +DSI_EXT_TE_POL__enumvalues = { + 0: 'DSI_EXT_TE_POL_RISING', + 1: 'DSI_EXT_TE_POL_FALLING', +} +DSI_EXT_TE_POL_RISING = 0 +DSI_EXT_TE_POL_FALLING = 1 +DSI_EXT_TE_POL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_RESET_PANEL' +DSI_RESET_PANEL__enumvalues = { + 0: 'DSI_RESET_PANEL_DEASSERT', + 1: 'DSI_RESET_PANEL_ASSERT', +} +DSI_RESET_PANEL_DEASSERT = 0 +DSI_RESET_PANEL_ASSERT = 1 +DSI_RESET_PANEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CRC_ENABLE' +DSI_CRC_ENABLE__enumvalues = { + 0: 'DSI_CRC_CAL_DISABLE', + 1: 'DSI_CRC_CAL_ENABLE', +} +DSI_CRC_CAL_DISABLE = 0 +DSI_CRC_CAL_ENABLE = 1 +DSI_CRC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_TX_EOT_APPEND' +DSI_TX_EOT_APPEND__enumvalues = { + 0: 'DSI_TX_EOT_APPEND_DISABLE', + 1: 'DSI_TX_EOT_APPEND_ENABLE', +} +DSI_TX_EOT_APPEND_DISABLE = 0 +DSI_TX_EOT_APPEND_ENABLE = 1 +DSI_TX_EOT_APPEND = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_RX_EOT_IGNORE' +DSI_RX_EOT_IGNORE__enumvalues = { + 0: 'DSI_RX_EOT_IGNORE_DISABLE', + 1: 'DSI_RX_EOT_IGNORE_ENABLE', +} +DSI_RX_EOT_IGNORE_DISABLE = 0 +DSI_RX_EOT_IGNORE_ENABLE = 1 +DSI_RX_EOT_IGNORE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_MIPI_BIST_RESET' +DSI_MIPI_BIST_RESET__enumvalues = { + 0: 'DSI_MIPI_BIST_RESET_DEASSERT', + 1: 'DSI_MIPI_BIST_RESET_ASSERT', +} +DSI_MIPI_BIST_RESET_DEASSERT = 0 +DSI_MIPI_BIST_RESET_ASSERT = 1 +DSI_MIPI_BIST_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_MIPI_BIST_VIDEO_FRMT' +DSI_MIPI_BIST_VIDEO_FRMT__enumvalues = { + 0: 'DSI_MIPI_BIST_VIDEO_FRMT_YUV422', + 1: 'DSI_MIPI_BIST_VIDEO_FRMT_RAW8', +} +DSI_MIPI_BIST_VIDEO_FRMT_YUV422 = 0 +DSI_MIPI_BIST_VIDEO_FRMT_RAW8 = 1 +DSI_MIPI_BIST_VIDEO_FRMT = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_MIPI_BIST_START' +DSI_MIPI_BIST_START__enumvalues = { + 0: 'DSI_MIPI_BIST_START_DEASSERT', + 1: 'DSI_MIPI_BIST_START_ASSERT', +} +DSI_MIPI_BIST_START_DEASSERT = 0 +DSI_MIPI_BIST_START_ASSERT = 1 +DSI_MIPI_BIST_START = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DBG_CLK_SEL' +DSI_DBG_CLK_SEL__enumvalues = { + 0: 'DSI_TEST_CLK_SEL_DISPCLK_P', + 1: 'DSI_TEST_CLK_SEL_DISPCLK_G', + 2: 'DSI_TEST_CLK_SEL_DISPCLK_R', + 3: 'DSI_TEST_CLK_SEL_ESCCLK_G', + 4: 'DSI_TEST_CLK_SEL_BYTECLK_G', + 5: 'DSI_TEST_CLK_SEL_DSICLK_P', + 6: 'DSI_TEST_CLK_SEL_DSICLK_R', + 7: 'DSI_TEST_CLK_SEL_DSICLK_G', + 8: 'DSI_TEST_CLK_SEL_DSICLK_TRN', +} +DSI_TEST_CLK_SEL_DISPCLK_P = 0 +DSI_TEST_CLK_SEL_DISPCLK_G = 1 +DSI_TEST_CLK_SEL_DISPCLK_R = 2 +DSI_TEST_CLK_SEL_ESCCLK_G = 3 +DSI_TEST_CLK_SEL_BYTECLK_G = 4 +DSI_TEST_CLK_SEL_DSICLK_P = 5 +DSI_TEST_CLK_SEL_DSICLK_R = 6 +DSI_TEST_CLK_SEL_DSICLK_G = 7 +DSI_TEST_CLK_SEL_DSICLK_TRN = 8 +DSI_DBG_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DENG_FIFO_USE_OVERWRITE_LEVEL' +DSI_DENG_FIFO_USE_OVERWRITE_LEVEL__enumvalues = { + 0: 'DSI_DENG_FIFO_LEVEL_OVERWRITE', + 1: 'DSI_DENG_FIFO_LEVEL_CAL_AVERAGE', +} +DSI_DENG_FIFO_LEVEL_OVERWRITE = 0 +DSI_DENG_FIFO_LEVEL_CAL_AVERAGE = 1 +DSI_DENG_FIFO_USE_OVERWRITE_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE' +DSI_DENG_FIFO_FORCE_RECAL_AVERAGE__enumvalues = { + 0: 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_DEASSERT', + 1: 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_ASSERT', +} +DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_DEASSERT = 0 +DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_ASSERT = 1 +DSI_DENG_FIFO_FORCE_RECAL_AVERAGE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX' +DSI_DENG_FIFO_FORCE_RECOMP_MINMAX__enumvalues = { + 0: 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_DEASSERT', + 1: 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_ASSERT', +} +DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_DEASSERT = 0 +DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_ASSERT = 1 +DSI_DENG_FIFO_FORCE_RECOMP_MINMAX = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DENG_FIFO_START' +DSI_DENG_FIFO_START__enumvalues = { + 0: 'DSI_DENG_FIFO_START_DEASSERT', + 1: 'DSI_DENG_FIFO_START_ASSERT', +} +DSI_DENG_FIFO_START_DEASSERT = 0 +DSI_DENG_FIFO_START_ASSERT = 1 +DSI_DENG_FIFO_START = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_USE_CMDFIFO' +DSI_USE_CMDFIFO__enumvalues = { + 0: 'DSI_CMD_USE_DMAFIFO', + 1: 'DSI_CMD_USE_CMDFIFO', +} +DSI_CMD_USE_DMAFIFO = 0 +DSI_CMD_USE_CMDFIFO = 1 +DSI_USE_CMDFIFO = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CRTC_FREEZE_TRIG' +DSI_CRTC_FREEZE_TRIG__enumvalues = { + 0: 'DSI_CRTC_FREEZE_TRIG_DEASSERT', + 1: 'DSI_CRTC_FREEZE_TRIG_ASSERT', +} +DSI_CRTC_FREEZE_TRIG_DEASSERT = 0 +DSI_CRTC_FREEZE_TRIG_ASSERT = 1 +DSI_CRTC_FREEZE_TRIG = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_PERF_LATENCY_SEL' +DSI_PERF_LATENCY_SEL__enumvalues = { + 0: 'DSI_PERF_LATENCY_SEL_DATA_LANE0', + 1: 'DSI_PERF_LATENCY_SEL_DATA_LANE1', + 2: 'DSI_PERF_LATENCY_SEL_DATA_LANE2', + 3: 'DSI_PERF_LATENCY_SEL_DATA_LANE3', +} +DSI_PERF_LATENCY_SEL_DATA_LANE0 = 0 +DSI_PERF_LATENCY_SEL_DATA_LANE1 = 1 +DSI_PERF_LATENCY_SEL_DATA_LANE2 = 2 +DSI_PERF_LATENCY_SEL_DATA_LANE3 = 3 +DSI_PERF_LATENCY_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DEBUG_DSICLK_SEL' +DSI_DEBUG_DSICLK_SEL__enumvalues = { + 0: 'DSI_DEBUG_DSICLK_SEL_VIDEO_ENGINE', + 1: 'DSI_DEBUG_DSICLK_SEL_CMD_ENGINE', + 2: 'DSI_DEBUG_DSICLK_SEL_RESYNC_FIFO', + 3: 'DSI_DEBUG_DSICLK_SEL_CMDFIFO', + 4: 'DSI_DEBUG_DSICLK_SEL_CMDBUFFER', + 5: 'DSI_DEBUG_DSICLK_SEL_AFIFO', + 6: 'DSI_DEBUG_DSICLK_SEL_LANECTRL', +} +DSI_DEBUG_DSICLK_SEL_VIDEO_ENGINE = 0 +DSI_DEBUG_DSICLK_SEL_CMD_ENGINE = 1 +DSI_DEBUG_DSICLK_SEL_RESYNC_FIFO = 2 +DSI_DEBUG_DSICLK_SEL_CMDFIFO = 3 +DSI_DEBUG_DSICLK_SEL_CMDBUFFER = 4 +DSI_DEBUG_DSICLK_SEL_AFIFO = 5 +DSI_DEBUG_DSICLK_SEL_LANECTRL = 6 +DSI_DEBUG_DSICLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DEBUG_BYTECLK_SEL' +DSI_DEBUG_BYTECLK_SEL__enumvalues = { + 0: 'DSI_DEBUG_BYTECLK_SEL_AFIFO', + 1: 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO0', + 2: 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO1', + 3: 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO2', + 4: 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO3', + 5: 'DSI_DEBUG_BYTECLK_SEL_LANEBUF0', + 6: 'DSI_DEBUG_BYTECLK_SEL_LANEBUF1', + 7: 'DSI_DEBUG_BYTECLK_SEL_LANEBUF2', + 8: 'DSI_DEBUG_BYTECLK_SEL_LANEBUF3', + 9: 'DSI_DEBUG_BYTECLK_SEL_PINGPONG0', + 10: 'DSI_DEBUG_BYTECLK_SEL_PINGPONG1', + 11: 'DSI_DEBUG_BYTECLK_SEL_PINGPING2', + 12: 'DSI_DEBUG_BYTECLK_SEL_PINGPING3', + 13: 'DSI_DEBUG_BYTECLK_SEL_EOT', + 14: 'DSI_DEBUG_BYTECLK_SEL_LANECTRL', +} +DSI_DEBUG_BYTECLK_SEL_AFIFO = 0 +DSI_DEBUG_BYTECLK_SEL_LANEFIFO0 = 1 +DSI_DEBUG_BYTECLK_SEL_LANEFIFO1 = 2 +DSI_DEBUG_BYTECLK_SEL_LANEFIFO2 = 3 +DSI_DEBUG_BYTECLK_SEL_LANEFIFO3 = 4 +DSI_DEBUG_BYTECLK_SEL_LANEBUF0 = 5 +DSI_DEBUG_BYTECLK_SEL_LANEBUF1 = 6 +DSI_DEBUG_BYTECLK_SEL_LANEBUF2 = 7 +DSI_DEBUG_BYTECLK_SEL_LANEBUF3 = 8 +DSI_DEBUG_BYTECLK_SEL_PINGPONG0 = 9 +DSI_DEBUG_BYTECLK_SEL_PINGPONG1 = 10 +DSI_DEBUG_BYTECLK_SEL_PINGPING2 = 11 +DSI_DEBUG_BYTECLK_SEL_PINGPING3 = 12 +DSI_DEBUG_BYTECLK_SEL_EOT = 13 +DSI_DEBUG_BYTECLK_SEL_LANECTRL = 14 +DSI_DEBUG_BYTECLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_HPD_SEL' +DCIOCHIP_HPD_SEL__enumvalues = { + 0: 'DCIOCHIP_HPD_SEL_ASYNC', + 1: 'DCIOCHIP_HPD_SEL_CLOCKED', +} +DCIOCHIP_HPD_SEL_ASYNC = 0 +DCIOCHIP_HPD_SEL_CLOCKED = 1 +DCIOCHIP_HPD_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_PAD_MODE' +DCIOCHIP_PAD_MODE__enumvalues = { + 0: 'DCIOCHIP_PAD_MODE_DDC', + 1: 'DCIOCHIP_PAD_MODE_DP', +} +DCIOCHIP_PAD_MODE_DDC = 0 +DCIOCHIP_PAD_MODE_DP = 1 +DCIOCHIP_PAD_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUXSLAVE_PAD_MODE' +DCIOCHIP_AUXSLAVE_PAD_MODE__enumvalues = { + 0: 'DCIOCHIP_AUXSLAVE_PAD_MODE_I2C', + 1: 'DCIOCHIP_AUXSLAVE_PAD_MODE_AUX', +} +DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0 +DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 1 +DCIOCHIP_AUXSLAVE_PAD_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_INVERT' +DCIOCHIP_INVERT__enumvalues = { + 0: 'DCIOCHIP_POL_NON_INVERT', + 1: 'DCIOCHIP_POL_INVERT', +} +DCIOCHIP_POL_NON_INVERT = 0 +DCIOCHIP_POL_INVERT = 1 +DCIOCHIP_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_PD_EN' +DCIOCHIP_PD_EN__enumvalues = { + 0: 'DCIOCHIP_PD_EN_NOTALLOW', + 1: 'DCIOCHIP_PD_EN_ALLOW', +} +DCIOCHIP_PD_EN_NOTALLOW = 0 +DCIOCHIP_PD_EN_ALLOW = 1 +DCIOCHIP_PD_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_GPIO_MASK_EN' +DCIOCHIP_GPIO_MASK_EN__enumvalues = { + 0: 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', + 1: 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', +} +DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0 +DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 1 +DCIOCHIP_GPIO_MASK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_MASK' +DCIOCHIP_MASK__enumvalues = { + 0: 'DCIOCHIP_MASK_DISABLE', + 1: 'DCIOCHIP_MASK_ENABLE', +} +DCIOCHIP_MASK_DISABLE = 0 +DCIOCHIP_MASK_ENABLE = 1 +DCIOCHIP_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_GPIO_I2C_MASK' +DCIOCHIP_GPIO_I2C_MASK__enumvalues = { + 0: 'DCIOCHIP_GPIO_I2C_MASK_DISABLE', + 1: 'DCIOCHIP_GPIO_I2C_MASK_ENABLE', +} +DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0 +DCIOCHIP_GPIO_I2C_MASK_ENABLE = 1 +DCIOCHIP_GPIO_I2C_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_GPIO_I2C_DRIVE' +DCIOCHIP_GPIO_I2C_DRIVE__enumvalues = { + 0: 'DCIOCHIP_GPIO_I2C_DRIVE_LOW', + 1: 'DCIOCHIP_GPIO_I2C_DRIVE_HIGH', +} +DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0 +DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 1 +DCIOCHIP_GPIO_I2C_DRIVE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_GPIO_I2C_EN' +DCIOCHIP_GPIO_I2C_EN__enumvalues = { + 0: 'DCIOCHIP_GPIO_I2C_DISABLE', + 1: 'DCIOCHIP_GPIO_I2C_ENABLE', +} +DCIOCHIP_GPIO_I2C_DISABLE = 0 +DCIOCHIP_GPIO_I2C_ENABLE = 1 +DCIOCHIP_GPIO_I2C_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_MASK_4BIT' +DCIOCHIP_MASK_4BIT__enumvalues = { + 0: 'DCIOCHIP_MASK_4BIT_DISABLE', + 15: 'DCIOCHIP_MASK_4BIT_ENABLE', +} +DCIOCHIP_MASK_4BIT_DISABLE = 0 +DCIOCHIP_MASK_4BIT_ENABLE = 15 +DCIOCHIP_MASK_4BIT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_ENABLE_4BIT' +DCIOCHIP_ENABLE_4BIT__enumvalues = { + 0: 'DCIOCHIP_4BIT_DISABLE', + 15: 'DCIOCHIP_4BIT_ENABLE', +} +DCIOCHIP_4BIT_DISABLE = 0 +DCIOCHIP_4BIT_ENABLE = 15 +DCIOCHIP_ENABLE_4BIT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_MASK_5BIT' +DCIOCHIP_MASK_5BIT__enumvalues = { + 0: 'DCIOCHIP_MASIK_5BIT_DISABLE', + 31: 'DCIOCHIP_MASIK_5BIT_ENABLE', +} +DCIOCHIP_MASIK_5BIT_DISABLE = 0 +DCIOCHIP_MASIK_5BIT_ENABLE = 31 +DCIOCHIP_MASK_5BIT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_ENABLE_5BIT' +DCIOCHIP_ENABLE_5BIT__enumvalues = { + 0: 'DCIOCHIP_5BIT_DISABLE', + 31: 'DCIOCHIP_5BIT_ENABLE', +} +DCIOCHIP_5BIT_DISABLE = 0 +DCIOCHIP_5BIT_ENABLE = 31 +DCIOCHIP_ENABLE_5BIT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_MASK_2BIT' +DCIOCHIP_MASK_2BIT__enumvalues = { + 0: 'DCIOCHIP_MASK_2BIT_DISABLE', + 3: 'DCIOCHIP_MASK_2BIT_ENABLE', +} +DCIOCHIP_MASK_2BIT_DISABLE = 0 +DCIOCHIP_MASK_2BIT_ENABLE = 3 +DCIOCHIP_MASK_2BIT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_ENABLE_2BIT' +DCIOCHIP_ENABLE_2BIT__enumvalues = { + 0: 'DCIOCHIP_2BIT_DISABLE', + 3: 'DCIOCHIP_2BIT_ENABLE', +} +DCIOCHIP_2BIT_DISABLE = 0 +DCIOCHIP_2BIT_ENABLE = 3 +DCIOCHIP_ENABLE_2BIT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_REF_27_SRC_SEL' +DCIOCHIP_REF_27_SRC_SEL__enumvalues = { + 0: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', + 1: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', + 2: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', + 3: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', +} +DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0 +DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 1 +DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 2 +DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 3 +DCIOCHIP_REF_27_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_DVO_VREFPON' +DCIOCHIP_DVO_VREFPON__enumvalues = { + 0: 'DCIOCHIP_DVO_VREFPON_DISABLE', + 1: 'DCIOCHIP_DVO_VREFPON_ENABLE', +} +DCIOCHIP_DVO_VREFPON_DISABLE = 0 +DCIOCHIP_DVO_VREFPON_ENABLE = 1 +DCIOCHIP_DVO_VREFPON = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_DVO_VREFSEL' +DCIOCHIP_DVO_VREFSEL__enumvalues = { + 0: 'DCIOCHIP_DVO_VREFSEL_ONCHIP', + 1: 'DCIOCHIP_DVO_VREFSEL_EXTERNAL', +} +DCIOCHIP_DVO_VREFSEL_ONCHIP = 0 +DCIOCHIP_DVO_VREFSEL_EXTERNAL = 1 +DCIOCHIP_DVO_VREFSEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_SPDIF1_IMODE' +DCIOCHIP_SPDIF1_IMODE__enumvalues = { + 0: 'DCIOCHIP_SPDIF1_IMODE_OE_A', + 1: 'DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO', +} +DCIOCHIP_SPDIF1_IMODE_OE_A = 0 +DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO = 1 +DCIOCHIP_SPDIF1_IMODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_FALLSLEWSEL' +DCIOCHIP_AUX_FALLSLEWSEL__enumvalues = { + 0: 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', + 1: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', + 2: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', + 3: 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', +} +DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0 +DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 1 +DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 2 +DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 3 +DCIOCHIP_AUX_FALLSLEWSEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_SPIKESEL' +DCIOCHIP_AUX_SPIKESEL__enumvalues = { + 0: 'DCIOCHIP_AUX_SPIKESEL_50NS', + 1: 'DCIOCHIP_AUX_SPIKESEL_10NS', +} +DCIOCHIP_AUX_SPIKESEL_50NS = 0 +DCIOCHIP_AUX_SPIKESEL_10NS = 1 +DCIOCHIP_AUX_SPIKESEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_CSEL0P9' +DCIOCHIP_AUX_CSEL0P9__enumvalues = { + 0: 'DCIOCHIP_AUX_CSEL_DEC1P0', + 1: 'DCIOCHIP_AUX_CSEL_DEC0P9', +} +DCIOCHIP_AUX_CSEL_DEC1P0 = 0 +DCIOCHIP_AUX_CSEL_DEC0P9 = 1 +DCIOCHIP_AUX_CSEL0P9 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_CSEL1P1' +DCIOCHIP_AUX_CSEL1P1__enumvalues = { + 0: 'DCIOCHIP_AUX_CSEL_INC1P0', + 1: 'DCIOCHIP_AUX_CSEL_INC1P1', +} +DCIOCHIP_AUX_CSEL_INC1P0 = 0 +DCIOCHIP_AUX_CSEL_INC1P1 = 1 +DCIOCHIP_AUX_CSEL1P1 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_RSEL0P9' +DCIOCHIP_AUX_RSEL0P9__enumvalues = { + 0: 'DCIOCHIP_AUX_RSEL_DEC1P0', + 1: 'DCIOCHIP_AUX_RSEL_DEC0P9', +} +DCIOCHIP_AUX_RSEL_DEC1P0 = 0 +DCIOCHIP_AUX_RSEL_DEC0P9 = 1 +DCIOCHIP_AUX_RSEL0P9 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_RSEL1P1' +DCIOCHIP_AUX_RSEL1P1__enumvalues = { + 0: 'DCIOCHIP_AUX_RSEL_INC1P0', + 1: 'DCIOCHIP_AUX_RSEL_INC1P1', +} +DCIOCHIP_AUX_RSEL_INC1P0 = 0 +DCIOCHIP_AUX_RSEL_INC1P1 = 1 +DCIOCHIP_AUX_RSEL1P1 = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL' +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', +} +GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 1 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED' +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', +} +GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 1 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS' +GENERIC_AZ_CONTROLLER_REGISTER_STATUS__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', +} +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 1 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED' +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', +} +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 1 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_GLOBAL_CAPABILITIES' +AZ_GLOBAL_CAPABILITIES__enumvalues = { + 0: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', + 1: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', +} +AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0 +AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 1 +AZ_GLOBAL_CAPABILITIES = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE' +GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE__enumvalues = { + 0: 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', + 1: 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE', +} +ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0 +ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 1 +GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_CONTROL_FLUSH_CONTROL' +GLOBAL_CONTROL_FLUSH_CONTROL__enumvalues = { + 0: 'FLUSH_CONTROL_FLUSH_NOT_STARTED', + 1: 'FLUSH_CONTROL_FLUSH_STARTED', +} +FLUSH_CONTROL_FLUSH_NOT_STARTED = 0 +FLUSH_CONTROL_FLUSH_STARTED = 1 +GLOBAL_CONTROL_FLUSH_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_CONTROL_CONTROLLER_RESET' +GLOBAL_CONTROL_CONTROLLER_RESET__enumvalues = { + 0: 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', + 1: 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', +} +CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0 +CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 1 +GLOBAL_CONTROL_CONTROLLER_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_STATE_CHANGE_STATUS' +AZ_STATE_CHANGE_STATUS__enumvalues = { + 0: 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', + 1: 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', +} +AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0 +AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 1 +AZ_STATE_CHANGE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_STATUS_FLUSH_STATUS' +GLOBAL_STATUS_FLUSH_STATUS__enumvalues = { + 0: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', + 1: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', +} +GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0 +GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 1 +GLOBAL_STATUS_FLUSH_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_0_SYNCHRONIZATION' +STREAM_0_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_0_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_1_SYNCHRONIZATION' +STREAM_1_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_1_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_2_SYNCHRONIZATION' +STREAM_2_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_2_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_3_SYNCHRONIZATION' +STREAM_3_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_3_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_4_SYNCHRONIZATION' +STREAM_4_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_4_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_4_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_5_SYNCHRONIZATION' +STREAM_5_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_5_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_5_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_6_SYNCHRONIZATION' +STREAM_6_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_6_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_7_SYNCHRONIZATION' +STREAM_7_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_7_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_8_SYNCHRONIZATION' +STREAM_8_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_8_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_9_SYNCHRONIZATION' +STREAM_9_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_9_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_10_SYNCHRONIZATION' +STREAM_10_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_10_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_11_SYNCHRONIZATION' +STREAM_11_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_11_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_12_SYNCHRONIZATION' +STREAM_12_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_12_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_13_SYNCHRONIZATION' +STREAM_13_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_13_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_14_SYNCHRONIZATION' +STREAM_14_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_14_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_15_SYNCHRONIZATION' +STREAM_15_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_15_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'CORB_READ_POINTER_RESET' +CORB_READ_POINTER_RESET__enumvalues = { + 0: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', + 1: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', +} +CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0 +CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 1 +CORB_READ_POINTER_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_CORB_SIZE' +AZ_CORB_SIZE__enumvalues = { + 0: 'AZ_CORB_SIZE_2ENTRIES_RESERVED', + 1: 'AZ_CORB_SIZE_16ENTRIES_RESERVED', + 2: 'AZ_CORB_SIZE_256ENTRIES', + 3: 'AZ_CORB_SIZE_RESERVED', +} +AZ_CORB_SIZE_2ENTRIES_RESERVED = 0 +AZ_CORB_SIZE_16ENTRIES_RESERVED = 1 +AZ_CORB_SIZE_256ENTRIES = 2 +AZ_CORB_SIZE_RESERVED = 3 +AZ_CORB_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_RIRB_WRITE_POINTER_RESET' +AZ_RIRB_WRITE_POINTER_RESET__enumvalues = { + 0: 'AZ_RIRB_WRITE_POINTER_NOT_RESET', + 1: 'AZ_RIRB_WRITE_POINTER_DO_RESET', +} +AZ_RIRB_WRITE_POINTER_NOT_RESET = 0 +AZ_RIRB_WRITE_POINTER_DO_RESET = 1 +AZ_RIRB_WRITE_POINTER_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL' +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL__enumvalues = { + 0: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 1: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', +} +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL' +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL__enumvalues = { + 0: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 1: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', +} +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_RIRB_SIZE' +AZ_RIRB_SIZE__enumvalues = { + 0: 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', + 1: 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', + 2: 'AZ_RIRB_SIZE_256ENTRIES', + 3: 'AZ_RIRB_SIZE_UNDEFINED', +} +AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0 +AZ_RIRB_SIZE_16ENTRIES_RESERVED = 1 +AZ_RIRB_SIZE_256ENTRIES = 2 +AZ_RIRB_SIZE_UNDEFINED = 3 +AZ_RIRB_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID' +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID__enumvalues = { + 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', + 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', +} +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 1 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID = ctypes.c_uint32 # enum + +# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY' +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY__enumvalues = { + 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', + 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', +} +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 1 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY = ctypes.c_uint32 # enum + +# values for enumeration 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE' +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE__enumvalues = { + 0: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', + 1: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', +} +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0 +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 1 +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 8: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE' +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', +} +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0 +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 1 +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', +} +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT' +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', +} +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 1 +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET' +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET__enumvalues = { + 0: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', + 1: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', +} +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0 +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 1 +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY' +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY__enumvalues = { + 0: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', + 1: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', + 2: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', + 3: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', + 4: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', + 5: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', + 6: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', + 7: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', +} +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 1 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 2 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 3 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 4 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 5 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 6 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 7 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY = ctypes.c_uint32 # enum + +# values for enumeration 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY' +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY__enumvalues = { + 0: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', + 1: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', + 2: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', + 3: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', + 4: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', + 5: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', + 6: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', + 7: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', +} +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 1 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 2 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 3 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 4 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 5 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 6 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 7 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 8: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET' +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET__enumvalues = { + 0: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', + 1: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', +} +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0 +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 1 +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'ENABLE' +ENABLE__enumvalues = { + 0: 'DISABLE_THE_FEATURE', + 1: 'ENABLE_THE_FEATURE', +} +DISABLE_THE_FEATURE = 0 +ENABLE_THE_FEATURE = 1 +ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'ENABLE_CLOCK' +ENABLE_CLOCK__enumvalues = { + 0: 'DISABLE_THE_CLOCK', + 1: 'ENABLE_THE_CLOCK', +} +DISABLE_THE_CLOCK = 0 +ENABLE_THE_CLOCK = 1 +ENABLE_CLOCK = ctypes.c_uint32 # enum + +# values for enumeration 'FORCE_VBI' +FORCE_VBI__enumvalues = { + 0: 'FORCE_VBI_LOW', + 1: 'FORCE_VBI_HIGH', +} +FORCE_VBI_LOW = 0 +FORCE_VBI_HIGH = 1 +FORCE_VBI = ctypes.c_uint32 # enum + +# values for enumeration 'OVERRIDE_CGTT_SCLK' +OVERRIDE_CGTT_SCLK__enumvalues = { + 0: 'OVERRIDE_CGTT_SCLK_NOOP', + 1: 'SET_OVERRIDE_CGTT_SCLK', +} +OVERRIDE_CGTT_SCLK_NOOP = 0 +SET_OVERRIDE_CGTT_SCLK = 1 +OVERRIDE_CGTT_SCLK = ctypes.c_uint32 # enum + +# values for enumeration 'CLEAR_SMU_INTR' +CLEAR_SMU_INTR__enumvalues = { + 0: 'SMU_INTR_STATUS_NOOP', + 1: 'SMU_INTR_STATUS_CLEAR', +} +SMU_INTR_STATUS_NOOP = 0 +SMU_INTR_STATUS_CLEAR = 1 +CLEAR_SMU_INTR = ctypes.c_uint32 # enum + +# values for enumeration 'STATIC_SCREEN_SMU_INTR' +STATIC_SCREEN_SMU_INTR__enumvalues = { + 0: 'STATIC_SCREEN_SMU_INTR_NOOP', + 1: 'SET_STATIC_SCREEN_SMU_INTR', +} +STATIC_SCREEN_SMU_INTR_NOOP = 0 +SET_STATIC_SCREEN_SMU_INTR = 1 +STATIC_SCREEN_SMU_INTR = ctypes.c_uint32 # enum + +# values for enumeration 'JITTER_REMOVE_DISABLE' +JITTER_REMOVE_DISABLE__enumvalues = { + 0: 'ENABLE_JITTER_REMOVAL', + 1: 'DISABLE_JITTER_REMOVAL', +} +ENABLE_JITTER_REMOVAL = 0 +DISABLE_JITTER_REMOVAL = 1 +JITTER_REMOVE_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DS_REF_SRC' +DS_REF_SRC__enumvalues = { + 0: 'DS_REF_IS_XTALIN', + 1: 'DS_REF_IS_EXT_GENLOCK', + 2: 'DS_REF_IS_PCIE', +} +DS_REF_IS_XTALIN = 0 +DS_REF_IS_EXT_GENLOCK = 1 +DS_REF_IS_PCIE = 2 +DS_REF_SRC = ctypes.c_uint32 # enum + +# values for enumeration 'DISABLE_CLOCK_GATING' +DISABLE_CLOCK_GATING__enumvalues = { + 0: 'CLOCK_GATING_ENABLED', + 1: 'CLOCK_GATING_DISABLED', +} +CLOCK_GATING_ENABLED = 0 +CLOCK_GATING_DISABLED = 1 +DISABLE_CLOCK_GATING = ctypes.c_uint32 # enum + +# values for enumeration 'DISABLE_CLOCK_GATING_IN_DCO' +DISABLE_CLOCK_GATING_IN_DCO__enumvalues = { + 0: 'CLOCK_GATING_ENABLED_IN_DCO', + 1: 'CLOCK_GATING_DISABLED_IN_DCO', +} +CLOCK_GATING_ENABLED_IN_DCO = 0 +CLOCK_GATING_DISABLED_IN_DCO = 1 +DISABLE_CLOCK_GATING_IN_DCO = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_DEEP_COLOR_CNTL' +DCCG_DEEP_COLOR_CNTL__enumvalues = { + 0: 'DCCG_DEEP_COLOR_DTO_DISABLE', + 1: 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', + 2: 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', + 3: 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', +} +DCCG_DEEP_COLOR_DTO_DISABLE = 0 +DCCG_DEEP_COLOR_DTO_5_4_RATIO = 1 +DCCG_DEEP_COLOR_DTO_3_2_RATIO = 2 +DCCG_DEEP_COLOR_DTO_2_1_RATIO = 3 +DCCG_DEEP_COLOR_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'REFCLK_CLOCK_EN' +REFCLK_CLOCK_EN__enumvalues = { + 0: 'REFCLK_CLOCK_EN_XTALIN_CLK', + 1: 'REFCLK_CLOCK_EN_ALLOW_SRC_SEL', +} +REFCLK_CLOCK_EN_XTALIN_CLK = 0 +REFCLK_CLOCK_EN_ALLOW_SRC_SEL = 1 +REFCLK_CLOCK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'REFCLK_SRC_SEL' +REFCLK_SRC_SEL__enumvalues = { + 0: 'REFCLK_SRC_SEL_PCIE_REFCLK', + 1: 'REFCLK_SRC_SEL_CPL_REFCLK', +} +REFCLK_SRC_SEL_PCIE_REFCLK = 0 +REFCLK_SRC_SEL_CPL_REFCLK = 1 +REFCLK_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPREFCLK_SRC_SEL' +DPREFCLK_SRC_SEL__enumvalues = { + 0: 'DPREFCLK_SRC_SEL_CK', + 1: 'DPREFCLK_SRC_SEL_P0PLL', + 2: 'DPREFCLK_SRC_SEL_P1PLL', + 3: 'DPREFCLK_SRC_SEL_P2PLL', + 4: 'DPREFCLK_SRC_SEL_P3PLL', +} +DPREFCLK_SRC_SEL_CK = 0 +DPREFCLK_SRC_SEL_P0PLL = 1 +DPREFCLK_SRC_SEL_P1PLL = 2 +DPREFCLK_SRC_SEL_P2PLL = 3 +DPREFCLK_SRC_SEL_P3PLL = 4 +DPREFCLK_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'XTAL_REF_SEL' +XTAL_REF_SEL__enumvalues = { + 0: 'XTAL_REF_SEL_1X', + 1: 'XTAL_REF_SEL_2X', +} +XTAL_REF_SEL_1X = 0 +XTAL_REF_SEL_2X = 1 +XTAL_REF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'XTAL_REF_CLOCK_SOURCE_SEL' +XTAL_REF_CLOCK_SOURCE_SEL__enumvalues = { + 0: 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', + 1: 'XTAL_REF_CLOCK_SOURCE_SEL_PPLL', +} +XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0 +XTAL_REF_CLOCK_SOURCE_SEL_PPLL = 1 +XTAL_REF_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL' +MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { + 0: 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', + 1: 'MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK', +} +MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 +MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 1 +MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'ALLOW_SR_ON_TRANS_REQ' +ALLOW_SR_ON_TRANS_REQ__enumvalues = { + 0: 'ALLOW_SR_ON_TRANS_REQ_ENABLE', + 1: 'ALLOW_SR_ON_TRANS_REQ_DISABLE', +} +ALLOW_SR_ON_TRANS_REQ_ENABLE = 0 +ALLOW_SR_ON_TRANS_REQ_DISABLE = 1 +ALLOW_SR_ON_TRANS_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL' +MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { + 0: 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', + 1: 'MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK', +} +MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 +MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 1 +MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_PIXEL_RATE_SOURCE' +PIPE_PIXEL_RATE_SOURCE__enumvalues = { + 0: 'PIPE_PIXEL_RATE_SOURCE_P0PLL', + 1: 'PIPE_PIXEL_RATE_SOURCE_P1PLL', + 2: 'PIPE_PIXEL_RATE_SOURCE_P2PLL', +} +PIPE_PIXEL_RATE_SOURCE_P0PLL = 0 +PIPE_PIXEL_RATE_SOURCE_P1PLL = 1 +PIPE_PIXEL_RATE_SOURCE_P2PLL = 2 +PIPE_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_PHYPLL_PIXEL_RATE_SOURCE' +PIPE_PHYPLL_PIXEL_RATE_SOURCE__enumvalues = { + 0: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', + 1: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', + 2: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', + 3: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', + 4: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE', + 5: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF', + 6: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG', +} +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 1 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 2 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 3 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE = 4 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF = 5 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG = 6 +PIPE_PHYPLL_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_PIXEL_RATE_PLL_SOURCE' +PIPE_PIXEL_RATE_PLL_SOURCE__enumvalues = { + 0: 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', + 1: 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', +} +PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0 +PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 1 +PIPE_PIXEL_RATE_PLL_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DTO_DS_DISABLE' +DP_DTO_DS_DISABLE__enumvalues = { + 0: 'DP_DTO_DESPREAD_DISABLE', + 1: 'DP_DTO_DESPREAD_ENABLE', +} +DP_DTO_DESPREAD_DISABLE = 0 +DP_DTO_DESPREAD_ENABLE = 1 +DP_DTO_DS_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_ADD_PIXEL' +CRTC_ADD_PIXEL__enumvalues = { + 0: 'CRTC_ADD_PIXEL_NOOP', + 1: 'CRTC_ADD_PIXEL_FORCE', +} +CRTC_ADD_PIXEL_NOOP = 0 +CRTC_ADD_PIXEL_FORCE = 1 +CRTC_ADD_PIXEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_DROP_PIXEL' +CRTC_DROP_PIXEL__enumvalues = { + 0: 'CRTC_DROP_PIXEL_NOOP', + 1: 'CRTC_DROP_PIXEL_FORCE', +} +CRTC_DROP_PIXEL_NOOP = 0 +CRTC_DROP_PIXEL_FORCE = 1 +CRTC_DROP_PIXEL = ctypes.c_uint32 # enum + +# values for enumeration 'SYMCLK_FE_FORCE_EN' +SYMCLK_FE_FORCE_EN__enumvalues = { + 0: 'SYMCLK_FE_FORCE_EN_DISABLE', + 1: 'SYMCLK_FE_FORCE_EN_ENABLE', +} +SYMCLK_FE_FORCE_EN_DISABLE = 0 +SYMCLK_FE_FORCE_EN_ENABLE = 1 +SYMCLK_FE_FORCE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'SYMCLK_FE_FORCE_SRC' +SYMCLK_FE_FORCE_SRC__enumvalues = { + 0: 'SYMCLK_FE_FORCE_SRC_UNIPHYA', + 1: 'SYMCLK_FE_FORCE_SRC_UNIPHYB', + 2: 'SYMCLK_FE_FORCE_SRC_UNIPHYC', + 3: 'SYMCLK_FE_FORCE_SRC_UNIPHYD', + 4: 'SYMCLK_FE_FORCE_SRC_UNIPHYE', + 5: 'SYMCLK_FE_FORCE_SRC_UNIPHYF', + 6: 'SYMCLK_FE_FORCE_SRC_UNIPHYG', +} +SYMCLK_FE_FORCE_SRC_UNIPHYA = 0 +SYMCLK_FE_FORCE_SRC_UNIPHYB = 1 +SYMCLK_FE_FORCE_SRC_UNIPHYC = 2 +SYMCLK_FE_FORCE_SRC_UNIPHYD = 3 +SYMCLK_FE_FORCE_SRC_UNIPHYE = 4 +SYMCLK_FE_FORCE_SRC_UNIPHYF = 5 +SYMCLK_FE_FORCE_SRC_UNIPHYG = 6 +SYMCLK_FE_FORCE_SRC = ctypes.c_uint32 # enum + +# values for enumeration 'DPDBG_CLK_FORCE_EN' +DPDBG_CLK_FORCE_EN__enumvalues = { + 0: 'DPDBG_CLK_FORCE_EN_DISABLE', + 1: 'DPDBG_CLK_FORCE_EN_ENABLE', +} +DPDBG_CLK_FORCE_EN_DISABLE = 0 +DPDBG_CLK_FORCE_EN_ENABLE = 1 +DPDBG_CLK_FORCE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLK_COARSE_SKEW_CNTL' +DVOACLK_COARSE_SKEW_CNTL__enumvalues = { + 0: 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', + 1: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', + 2: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', + 3: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', + 4: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', + 5: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', + 6: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', + 7: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', + 8: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', + 9: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', + 10: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', + 11: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', + 12: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', + 13: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', + 14: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', + 15: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', + 16: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', + 17: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', + 18: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', + 19: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', + 20: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', + 21: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', + 22: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', + 23: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', + 24: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', + 25: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', + 26: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', + 27: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', + 28: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', + 29: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', + 30: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', +} +DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0 +DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 1 +DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 2 +DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 3 +DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 4 +DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 5 +DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 6 +DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 7 +DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 8 +DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 9 +DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 10 +DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 11 +DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 12 +DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 13 +DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 14 +DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 15 +DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 16 +DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 17 +DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 18 +DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 19 +DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 20 +DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 21 +DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 22 +DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 23 +DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 24 +DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 25 +DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 26 +DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 27 +DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 28 +DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 29 +DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 30 +DVOACLK_COARSE_SKEW_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLK_FINE_SKEW_CNTL' +DVOACLK_FINE_SKEW_CNTL__enumvalues = { + 0: 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', + 1: 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', + 2: 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', + 3: 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', + 4: 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', + 5: 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', + 6: 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', + 7: 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', +} +DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0 +DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 1 +DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 2 +DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 3 +DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 4 +DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 5 +DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 6 +DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 7 +DVOACLK_FINE_SKEW_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKD_IN_PHASE' +DVOACLKD_IN_PHASE__enumvalues = { + 0: 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 1: 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', +} +DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 +DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 1 +DVOACLKD_IN_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKC_IN_PHASE' +DVOACLKC_IN_PHASE__enumvalues = { + 0: 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 1: 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', +} +DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 +DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 1 +DVOACLKC_IN_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKC_MVP_IN_PHASE' +DVOACLKC_MVP_IN_PHASE__enumvalues = { + 0: 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 1: 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', +} +DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 +DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 1 +DVOACLKC_MVP_IN_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE' +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__enumvalues = { + 0: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', + 1: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', +} +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0 +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 1 +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'MVP_CLK_SRC_SEL' +MVP_CLK_SRC_SEL__enumvalues = { + 0: 'MVP_CLK_SRC_SEL_RSRV', + 1: 'MVP_CLK_SRC_SEL_IO_1', + 2: 'MVP_CLK_SRC_SEL_IO_2', + 3: 'MVP_CLK_SRC_SEL_REFCLK', +} +MVP_CLK_SRC_SEL_RSRV = 0 +MVP_CLK_SRC_SEL_IO_1 = 1 +MVP_CLK_SRC_SEL_IO_2 = 2 +MVP_CLK_SRC_SEL_REFCLK = 3 +MVP_CLK_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO0_SOURCE_SEL' +DCCG_AUDIO_DTO0_SOURCE_SEL__enumvalues = { + 0: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0', + 1: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1', + 2: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2', + 3: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3', + 4: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4', + 5: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5', + 6: 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', +} +DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0 = 0 +DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1 = 1 +DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2 = 2 +DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3 = 3 +DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4 = 4 +DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5 = 5 +DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 6 +DCCG_AUDIO_DTO0_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO_SEL' +DCCG_AUDIO_DTO_SEL__enumvalues = { + 0: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', + 1: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', + 2: 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', +} +DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0 +DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 1 +DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 2 +DCCG_AUDIO_DTO_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO2_SOURCE_SEL' +DCCG_AUDIO_DTO2_SOURCE_SEL__enumvalues = { + 0: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', + 1: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1', +} +DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0 +DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1 = 1 +DCCG_AUDIO_DTO2_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO_USE_512FBR_DTO' +DCCG_AUDIO_DTO_USE_512FBR_DTO__enumvalues = { + 0: 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', + 1: 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', +} +DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0 +DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 1 +DCCG_AUDIO_DTO_USE_512FBR_DTO = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_DBG_EN' +DCCG_DBG_EN__enumvalues = { + 0: 'DCCG_DBG_EN_DISABLE', + 1: 'DCCG_DBG_EN_ENABLE', +} +DCCG_DBG_EN_DISABLE = 0 +DCCG_DBG_EN_ENABLE = 1 +DCCG_DBG_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_DBG_BLOCK_SEL' +DCCG_DBG_BLOCK_SEL__enumvalues = { + 0: 'DCCG_DBG_BLOCK_SEL_DCCG', + 1: 'DCCG_DBG_BLOCK_SEL_PMON', + 2: 'DCCG_DBG_BLOCK_SEL_PMON2', +} +DCCG_DBG_BLOCK_SEL_DCCG = 0 +DCCG_DBG_BLOCK_SEL_PMON = 1 +DCCG_DBG_BLOCK_SEL_PMON2 = 2 +DCCG_DBG_BLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DISPCLK_FREQ_RAMP_DONE' +DISPCLK_FREQ_RAMP_DONE__enumvalues = { + 0: 'DISPCLK_FREQ_RAMP_IN_PROGRESS', + 1: 'DISPCLK_FREQ_RAMP_COMPLETED', +} +DISPCLK_FREQ_RAMP_IN_PROGRESS = 0 +DISPCLK_FREQ_RAMP_COMPLETED = 1 +DISPCLK_FREQ_RAMP_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_FIFO_ERRDET_RESET' +DCCG_FIFO_ERRDET_RESET__enumvalues = { + 0: 'DCCG_FIFO_ERRDET_RESET_NOOP', + 1: 'DCCG_FIFO_ERRDET_RESET_FORCE', +} +DCCG_FIFO_ERRDET_RESET_NOOP = 0 +DCCG_FIFO_ERRDET_RESET_FORCE = 1 +DCCG_FIFO_ERRDET_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_FIFO_ERRDET_STATE' +DCCG_FIFO_ERRDET_STATE__enumvalues = { + 0: 'DCCG_FIFO_ERRDET_STATE_DETECTION', + 1: 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', +} +DCCG_FIFO_ERRDET_STATE_DETECTION = 0 +DCCG_FIFO_ERRDET_STATE_CALIBRATION = 1 +DCCG_FIFO_ERRDET_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_FIFO_ERRDET_OVR_EN' +DCCG_FIFO_ERRDET_OVR_EN__enumvalues = { + 0: 'DCCG_FIFO_ERRDET_OVR_DISABLE', + 1: 'DCCG_FIFO_ERRDET_OVR_ENABLE', +} +DCCG_FIFO_ERRDET_OVR_DISABLE = 0 +DCCG_FIFO_ERRDET_OVR_ENABLE = 1 +DCCG_FIFO_ERRDET_OVR_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DISPCLK_CHG_FWD_CORR_DISABLE' +DISPCLK_CHG_FWD_CORR_DISABLE__enumvalues = { + 0: 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', + 1: 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', +} +DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0 +DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 1 +DISPCLK_CHG_FWD_CORR_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DC_MEM_GLOBAL_PWR_REQ_DIS' +DC_MEM_GLOBAL_PWR_REQ_DIS__enumvalues = { + 0: 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', + 1: 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', +} +DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0 +DC_MEM_GLOBAL_PWR_REQ_DISABLE = 1 +DC_MEM_GLOBAL_PWR_REQ_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_RUN' +DCCG_PERF_RUN__enumvalues = { + 0: 'DCCG_PERF_RUN_NOOP', + 1: 'DCCG_PERF_RUN_START', +} +DCCG_PERF_RUN_NOOP = 0 +DCCG_PERF_RUN_START = 1 +DCCG_PERF_RUN = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_MODE_VSYNC' +DCCG_PERF_MODE_VSYNC__enumvalues = { + 0: 'DCCG_PERF_MODE_VSYNC_NOOP', + 1: 'DCCG_PERF_MODE_VSYNC_START', +} +DCCG_PERF_MODE_VSYNC_NOOP = 0 +DCCG_PERF_MODE_VSYNC_START = 1 +DCCG_PERF_MODE_VSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_MODE_HSYNC' +DCCG_PERF_MODE_HSYNC__enumvalues = { + 0: 'DCCG_PERF_MODE_HSYNC_NOOP', + 1: 'DCCG_PERF_MODE_HSYNC_START', +} +DCCG_PERF_MODE_HSYNC_NOOP = 0 +DCCG_PERF_MODE_HSYNC_START = 1 +DCCG_PERF_MODE_HSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_CRTC_SELECT' +DCCG_PERF_CRTC_SELECT__enumvalues = { + 0: 'DCCG_PERF_SEL_CRTC0', + 1: 'DCCG_PERF_SEL_CRTC1', + 2: 'DCCG_PERF_SEL_CRTC2', + 3: 'DCCG_PERF_SEL_CRTC3', + 4: 'DCCG_PERF_SEL_CRTC4', + 5: 'DCCG_PERF_SEL_CRTC5', +} +DCCG_PERF_SEL_CRTC0 = 0 +DCCG_PERF_SEL_CRTC1 = 1 +DCCG_PERF_SEL_CRTC2 = 2 +DCCG_PERF_SEL_CRTC3 = 3 +DCCG_PERF_SEL_CRTC4 = 4 +DCCG_PERF_SEL_CRTC5 = 5 +DCCG_PERF_CRTC_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'CLOCK_BRANCH_SOFT_RESET' +CLOCK_BRANCH_SOFT_RESET__enumvalues = { + 0: 'CLOCK_BRANCH_SOFT_RESET_NOOP', + 1: 'CLOCK_BRANCH_SOFT_RESET_FORCE', +} +CLOCK_BRANCH_SOFT_RESET_NOOP = 0 +CLOCK_BRANCH_SOFT_RESET_FORCE = 1 +CLOCK_BRANCH_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'PLL_CFG_IF_SOFT_RESET' +PLL_CFG_IF_SOFT_RESET__enumvalues = { + 0: 'PLL_CFG_IF_SOFT_RESET_NOOP', + 1: 'PLL_CFG_IF_SOFT_RESET_FORCE', +} +PLL_CFG_IF_SOFT_RESET_NOOP = 0 +PLL_CFG_IF_SOFT_RESET_FORCE = 1 +PLL_CFG_IF_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DVO_ENABLE_RST' +DVO_ENABLE_RST__enumvalues = { + 0: 'DVO_ENABLE_RST_DISABLE', + 1: 'DVO_ENABLE_RST_ENABLE', +} +DVO_ENABLE_RST_DISABLE = 0 +DVO_ENABLE_RST_ENABLE = 1 +DVO_ENABLE_RST = ctypes.c_uint32 # enum + +# values for enumeration 'LptNumPipes' +LptNumPipes__enumvalues = { + 0: 'LPT_NUM_PIPES_1CH', + 1: 'LPT_NUM_PIPES_2CH', + 2: 'LPT_NUM_PIPES_4CH', + 3: 'LPT_NUM_PIPES_8CH', +} +LPT_NUM_PIPES_1CH = 0 +LPT_NUM_PIPES_2CH = 1 +LPT_NUM_PIPES_4CH = 2 +LPT_NUM_PIPES_8CH = 3 +LptNumPipes = ctypes.c_uint32 # enum + +# values for enumeration 'LptNumBanks' +LptNumBanks__enumvalues = { + 0: 'LPT_NUM_BANKS_2BANK', + 1: 'LPT_NUM_BANKS_4BANK', + 2: 'LPT_NUM_BANKS_8BANK', + 3: 'LPT_NUM_BANKS_16BANK', + 4: 'LPT_NUM_BANKS_32BANK', +} +LPT_NUM_BANKS_2BANK = 0 +LPT_NUM_BANKS_4BANK = 1 +LPT_NUM_BANKS_8BANK = 2 +LPT_NUM_BANKS_16BANK = 3 +LPT_NUM_BANKS_32BANK = 4 +LptNumBanks = ctypes.c_uint32 # enum + +# values for enumeration 'OVERRIDE_CGTT_DCEFCLK' +OVERRIDE_CGTT_DCEFCLK__enumvalues = { + 0: 'OVERRIDE_CGTT_DCEFCLK_NOOP', + 1: 'SET_OVERRIDE_CGTT_DCEFCLK', +} +OVERRIDE_CGTT_DCEFCLK_NOOP = 0 +SET_OVERRIDE_CGTT_DCEFCLK = 1 +OVERRIDE_CGTT_DCEFCLK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERICA_SEL' +DCIO_DC_GENERICA_SEL__enumvalues = { + 0: 'DCIO_GENERICA_SEL_DACA_STEREOSYNC', + 1: 'DCIO_GENERICA_SEL_STEREOSYNC', + 2: 'DCIO_GENERICA_SEL_DACA_PIXCLK', + 3: 'DCIO_GENERICA_SEL_DACB_PIXCLK', + 4: 'DCIO_GENERICA_SEL_DVOA_CTL3', + 5: 'DCIO_GENERICA_SEL_P1_PLLCLK', + 6: 'DCIO_GENERICA_SEL_P2_PLLCLK', + 7: 'DCIO_GENERICA_SEL_DVOA_STEREOSYNC', + 8: 'DCIO_GENERICA_SEL_DACA_FIELD_NUMBER', + 9: 'DCIO_GENERICA_SEL_DACB_FIELD_NUMBER', + 10: 'DCIO_GENERICA_SEL_GENERICA_DCCG', + 11: 'DCIO_GENERICA_SEL_SYNCEN', + 12: 'DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK', + 13: 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK', + 14: 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK', + 15: 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2', + 16: 'DCIO_GENERICA_SEL_GENERICA_DPRX', + 17: 'DCIO_GENERICA_SEL_GENERICB_DPRX', +} +DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0 +DCIO_GENERICA_SEL_STEREOSYNC = 1 +DCIO_GENERICA_SEL_DACA_PIXCLK = 2 +DCIO_GENERICA_SEL_DACB_PIXCLK = 3 +DCIO_GENERICA_SEL_DVOA_CTL3 = 4 +DCIO_GENERICA_SEL_P1_PLLCLK = 5 +DCIO_GENERICA_SEL_P2_PLLCLK = 6 +DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 7 +DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 8 +DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 9 +DCIO_GENERICA_SEL_GENERICA_DCCG = 10 +DCIO_GENERICA_SEL_SYNCEN = 11 +DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK = 12 +DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK = 13 +DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK = 14 +DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2 = 15 +DCIO_GENERICA_SEL_GENERICA_DPRX = 16 +DCIO_GENERICA_SEL_GENERICB_DPRX = 17 +DCIO_DC_GENERICA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL' +DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_TEST_REFDIV_CLK', + 1: 'DCIO_UNIPHYB_TEST_REFDIV_CLK', + 2: 'DCIO_UNIPHYC_TEST_REFDIV_CLK', + 3: 'DCIO_UNIPHYD_TEST_REFDIV_CLK', + 4: 'DCIO_UNIPHYE_TEST_REFDIV_CLK', + 5: 'DCIO_UNIPHYF_TEST_REFDIV_CLK', + 6: 'DCIO_UNIPHYG_TEST_REFDIV_CLK', + 7: 'DCIO_UNIPHYLPA_TEST_REFDIV_CLK', + 8: 'DCIO_UNIPHYLPB_TEST_REFDIV_CLK', +} +DCIO_UNIPHYA_TEST_REFDIV_CLK = 0 +DCIO_UNIPHYB_TEST_REFDIV_CLK = 1 +DCIO_UNIPHYC_TEST_REFDIV_CLK = 2 +DCIO_UNIPHYD_TEST_REFDIV_CLK = 3 +DCIO_UNIPHYE_TEST_REFDIV_CLK = 4 +DCIO_UNIPHYF_TEST_REFDIV_CLK = 5 +DCIO_UNIPHYG_TEST_REFDIV_CLK = 6 +DCIO_UNIPHYLPA_TEST_REFDIV_CLK = 7 +DCIO_UNIPHYLPB_TEST_REFDIV_CLK = 8 +DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL' +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_FBDIV_CLK', + 1: 'DCIO_UNIPHYB_FBDIV_CLK', + 2: 'DCIO_UNIPHYC_FBDIV_CLK', + 3: 'DCIO_UNIPHYD_FBDIV_CLK', + 4: 'DCIO_UNIPHYE_FBDIV_CLK', + 5: 'DCIO_UNIPHYF_FBDIV_CLK', + 6: 'DCIO_UNIPHYG_FBDIV_CLK', + 7: 'DCIO_UNIPHYLPA_FBDIV_CLK', + 8: 'DCIO_UNIPHYLPB_FBDIV_CLK', +} +DCIO_UNIPHYA_FBDIV_CLK = 0 +DCIO_UNIPHYB_FBDIV_CLK = 1 +DCIO_UNIPHYC_FBDIV_CLK = 2 +DCIO_UNIPHYD_FBDIV_CLK = 3 +DCIO_UNIPHYE_FBDIV_CLK = 4 +DCIO_UNIPHYF_FBDIV_CLK = 5 +DCIO_UNIPHYG_FBDIV_CLK = 6 +DCIO_UNIPHYLPA_FBDIV_CLK = 7 +DCIO_UNIPHYLPB_FBDIV_CLK = 8 +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL' +DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_FBDIV_SSC_CLK', + 1: 'DCIO_UNIPHYB_FBDIV_SSC_CLK', + 2: 'DCIO_UNIPHYC_FBDIV_SSC_CLK', + 3: 'DCIO_UNIPHYD_FBDIV_SSC_CLK', + 4: 'DCIO_UNIPHYE_FBDIV_SSC_CLK', + 5: 'DCIO_UNIPHYF_FBDIV_SSC_CLK', + 6: 'DCIO_UNIPHYG_FBDIV_SSC_CLK', + 7: 'DCIO_UNIPHYLPA_FBDIV_SSC_CLK', + 8: 'DCIO_UNIPHYLPB_FBDIV_SSC_CLK', +} +DCIO_UNIPHYA_FBDIV_SSC_CLK = 0 +DCIO_UNIPHYB_FBDIV_SSC_CLK = 1 +DCIO_UNIPHYC_FBDIV_SSC_CLK = 2 +DCIO_UNIPHYD_FBDIV_SSC_CLK = 3 +DCIO_UNIPHYE_FBDIV_SSC_CLK = 4 +DCIO_UNIPHYF_FBDIV_SSC_CLK = 5 +DCIO_UNIPHYG_FBDIV_SSC_CLK = 6 +DCIO_UNIPHYLPA_FBDIV_SSC_CLK = 7 +DCIO_UNIPHYLPB_FBDIV_SSC_CLK = 8 +DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL' +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', + 1: 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', + 2: 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', + 3: 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', + 4: 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', + 5: 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', + 6: 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', + 7: 'DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2', + 8: 'DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2', +} +DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0 +DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 1 +DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 2 +DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 3 +DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 4 +DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 5 +DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 6 +DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2 = 7 +DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2 = 8 +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERICB_SEL' +DCIO_DC_GENERICB_SEL__enumvalues = { + 0: 'DCIO_GENERICB_SEL_DACA_STEREOSYNC', + 1: 'DCIO_GENERICB_SEL_STEREOSYNC', + 2: 'DCIO_GENERICB_SEL_DACA_PIXCLK', + 3: 'DCIO_GENERICB_SEL_DACB_PIXCLK', + 4: 'DCIO_GENERICB_SEL_DVOA_CTL3', + 5: 'DCIO_GENERICB_SEL_P1_PLLCLK', + 6: 'DCIO_GENERICB_SEL_P2_PLLCLK', + 7: 'DCIO_GENERICB_SEL_DVOA_STEREOSYNC', + 8: 'DCIO_GENERICB_SEL_DACA_FIELD_NUMBER', + 9: 'DCIO_GENERICB_SEL_DACB_FIELD_NUMBER', + 10: 'DCIO_GENERICB_SEL_GENERICB_DCCG', + 11: 'DCIO_GENERICB_SEL_SYNCEN', + 12: 'DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK', + 13: 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK', + 14: 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK', + 15: 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2', +} +DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0 +DCIO_GENERICB_SEL_STEREOSYNC = 1 +DCIO_GENERICB_SEL_DACA_PIXCLK = 2 +DCIO_GENERICB_SEL_DACB_PIXCLK = 3 +DCIO_GENERICB_SEL_DVOA_CTL3 = 4 +DCIO_GENERICB_SEL_P1_PLLCLK = 5 +DCIO_GENERICB_SEL_P2_PLLCLK = 6 +DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 7 +DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 8 +DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 9 +DCIO_GENERICB_SEL_GENERICB_DCCG = 10 +DCIO_GENERICB_SEL_SYNCEN = 11 +DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK = 12 +DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK = 13 +DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK = 14 +DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2 = 15 +DCIO_DC_GENERICB_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_PAD_EXTERN_SIG_SEL' +DCIO_DC_PAD_EXTERN_SIG_SEL__enumvalues = { + 0: 'DCIO_DC_PAD_EXTERN_SIG_SEL_MVP', + 1: 'DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA', + 2: 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK', + 3: 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC', + 4: 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA', + 5: 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB', + 6: 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC', + 7: 'DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1', + 8: 'DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2', + 9: 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK', + 10: 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA', + 11: 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK', + 12: 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA', + 13: 'DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1', + 14: 'DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0', + 15: 'DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL', +} +DCIO_DC_PAD_EXTERN_SIG_SEL_MVP = 0 +DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 1 +DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 2 +DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 3 +DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA = 4 +DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB = 5 +DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC = 6 +DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1 = 7 +DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2 = 8 +DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK = 9 +DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 10 +DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK = 11 +DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA = 12 +DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1 = 13 +DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0 = 14 +DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL = 15 +DCIO_DC_PAD_EXTERN_SIG_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS' +DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS__enumvalues = { + 0: 'DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA', + 1: 'DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE', + 2: 'DCIO_MVP_PIXEL_SRC_STATUS_CRTC', + 3: 'DCIO_MVP_PIXEL_SRC_STATUS_LB', +} +DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA = 0 +DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 1 +DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 2 +DCIO_MVP_PIXEL_SRC_STATUS_LB = 3 +DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL' +DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL__enumvalues = { + 0: 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', + 1: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', + 2: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', + 3: 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', +} +DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0 +DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 1 +DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 2 +DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 3 +DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL' +DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL__enumvalues = { + 0: 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', + 1: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', + 2: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', + 3: 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', +} +DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0 +DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 1 +DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 2 +DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 3 +DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPIO_VIP_DEBUG' +DCIO_DC_GPIO_VIP_DEBUG__enumvalues = { + 0: 'DCIO_DC_GPIO_VIP_DEBUG_NORMAL', + 1: 'DCIO_DC_GPIO_VIP_DEBUG_CG_BIG', +} +DCIO_DC_GPIO_VIP_DEBUG_NORMAL = 0 +DCIO_DC_GPIO_VIP_DEBUG_CG_BIG = 1 +DCIO_DC_GPIO_VIP_DEBUG = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPIO_MACRO_DEBUG' +DCIO_DC_GPIO_MACRO_DEBUG__enumvalues = { + 0: 'DCIO_DC_GPIO_MACRO_DEBUG_NORMAL', + 1: 'DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF', + 2: 'DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2', + 3: 'DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3', +} +DCIO_DC_GPIO_MACRO_DEBUG_NORMAL = 0 +DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF = 1 +DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 2 +DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 3 +DCIO_DC_GPIO_MACRO_DEBUG = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL' +DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__enumvalues = { + 0: 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL', + 1: 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP', +} +DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0 +DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 1 +DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN' +DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN__enumvalues = { + 0: 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS', + 1: 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE', +} +DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS = 0 +DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE = 1 +DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE' +DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE__enumvalues = { + 0: 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', + 1: 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', +} +DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0 +DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 1 +DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION' +DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION__enumvalues = { + 0: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS', + 1: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS', + 2: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS', + 3: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS', + 4: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS', + 5: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS', + 6: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS', + 7: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS', +} +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0 +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 1 +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS = 2 +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS = 3 +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS = 4 +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS = 5 +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS = 6 +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS = 7 +DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT' +DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT__enumvalues = { + 0: 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', + 1: 'DCIO_UNIPHY_CHANNEL_INVERTED', +} +DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0 +DCIO_UNIPHY_CHANNEL_INVERTED = 1 +DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK' +DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK__enumvalues = { + 0: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', + 1: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', + 2: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', + 3: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', +} +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0 +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 1 +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 2 +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 3 +DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE' +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE__enumvalues = { + 0: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', + 1: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', + 2: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', + 3: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', +} +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 1 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 2 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 3 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN' +DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN__enumvalues = { + 0: 'DCIO_VIP_MUX_EN_DVO', + 1: 'DCIO_VIP_MUX_EN_VIP', +} +DCIO_VIP_MUX_EN_DVO = 0 +DCIO_VIP_MUX_EN_VIP = 1 +DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN' +DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN__enumvalues = { + 0: 'DCIO_VIP_ALTER_MAPPING_EN_DEFAULT', + 1: 'DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE', +} +DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0 +DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 1 +DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN' +DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN__enumvalues = { + 0: 'DCIO_DVO_ALTER_MAPPING_EN_DEFAULT', + 1: 'DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE', +} +DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0 +DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 1 +DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN' +DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN__enumvalues = { + 0: 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE', + 1: 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE', +} +DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE = 0 +DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE = 1 +DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE' +DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE__enumvalues = { + 0: 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF', + 1: 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON', +} +DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0 +DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 1 +DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL' +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL__enumvalues = { + 0: 'DCIO_LVTMA_SYNCEN_POL_NON_INVERT', + 1: 'DCIO_LVTMA_SYNCEN_POL_INVERT', +} +DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0 +DCIO_LVTMA_SYNCEN_POL_INVERT = 1 +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON' +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON__enumvalues = { + 0: 'DCIO_LVTMA_DIGON_OFF', + 1: 'DCIO_LVTMA_DIGON_ON', +} +DCIO_LVTMA_DIGON_OFF = 0 +DCIO_LVTMA_DIGON_ON = 1 +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL' +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL__enumvalues = { + 0: 'DCIO_LVTMA_DIGON_POL_NON_INVERT', + 1: 'DCIO_LVTMA_DIGON_POL_INVERT', +} +DCIO_LVTMA_DIGON_POL_NON_INVERT = 0 +DCIO_LVTMA_DIGON_POL_INVERT = 1 +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON' +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON__enumvalues = { + 0: 'DCIO_LVTMA_BLON_OFF', + 1: 'DCIO_LVTMA_BLON_ON', +} +DCIO_LVTMA_BLON_OFF = 0 +DCIO_LVTMA_BLON_ON = 1 +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL' +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL__enumvalues = { + 0: 'DCIO_LVTMA_BLON_POL_NON_INVERT', + 1: 'DCIO_LVTMA_BLON_POL_INVERT', +} +DCIO_LVTMA_BLON_POL_NON_INVERT = 0 +DCIO_LVTMA_BLON_POL_INVERT = 1 +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN' +DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN__enumvalues = { + 0: 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON', + 1: 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE', +} +DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0 +DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 1 +DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN' +DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN__enumvalues = { + 0: 'DCIO_BL_PWM_FRACTIONAL_DISABLE', + 1: 'DCIO_BL_PWM_FRACTIONAL_ENABLE', +} +DCIO_BL_PWM_FRACTIONAL_DISABLE = 0 +DCIO_BL_PWM_FRACTIONAL_ENABLE = 1 +DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_CNTL_BL_PWM_EN' +DCIO_BL_PWM_CNTL_BL_PWM_EN__enumvalues = { + 0: 'DCIO_BL_PWM_DISABLE', + 1: 'DCIO_BL_PWM_ENABLE', +} +DCIO_BL_PWM_DISABLE = 0 +DCIO_BL_PWM_ENABLE = 1 +DCIO_BL_PWM_CNTL_BL_PWM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT' +DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT__enumvalues = { + 0: 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', + 1: 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', + 2: 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', + 3: 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', +} +DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0 +DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 1 +DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 2 +DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 3 +DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE' +DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE__enumvalues = { + 0: 'DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE', + 1: 'DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE', +} +DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0 +DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 1 +DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN' +DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__enumvalues = { + 0: 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL', + 1: 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM', +} +DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0 +DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 1 +DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_GRP1_REG_LOCK' +DCIO_BL_PWM_GRP1_REG_LOCK__enumvalues = { + 0: 'DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE', + 1: 'DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE', +} +DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0 +DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 1 +DCIO_BL_PWM_GRP1_REG_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START' +DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START__enumvalues = { + 0: 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', + 1: 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', +} +DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0 +DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 1 +DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL' +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL__enumvalues = { + 0: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', + 1: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', + 2: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', + 3: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', + 4: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', + 5: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', +} +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 1 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 2 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 3 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 4 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 5 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN' +DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__enumvalues = { + 0: 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', + 1: 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', +} +DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0 +DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 1 +DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN' +DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__enumvalues = { + 0: 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', + 1: 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', +} +DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0 +DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 1 +DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GSL_SEL' +DCIO_GSL_SEL__enumvalues = { + 0: 'DCIO_GSL_SEL_GROUP_0', + 1: 'DCIO_GSL_SEL_GROUP_1', + 2: 'DCIO_GSL_SEL_GROUP_2', +} +DCIO_GSL_SEL_GROUP_0 = 0 +DCIO_GSL_SEL_GROUP_1 = 1 +DCIO_GSL_SEL_GROUP_2 = 2 +DCIO_GSL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GENLK_CLK_GSL_MASK' +DCIO_GENLK_CLK_GSL_MASK__enumvalues = { + 0: 'DCIO_GENLK_CLK_GSL_MASK_NO', + 1: 'DCIO_GENLK_CLK_GSL_MASK_TIMING', + 2: 'DCIO_GENLK_CLK_GSL_MASK_STEREO', +} +DCIO_GENLK_CLK_GSL_MASK_NO = 0 +DCIO_GENLK_CLK_GSL_MASK_TIMING = 1 +DCIO_GENLK_CLK_GSL_MASK_STEREO = 2 +DCIO_GENLK_CLK_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GENLK_VSYNC_GSL_MASK' +DCIO_GENLK_VSYNC_GSL_MASK__enumvalues = { + 0: 'DCIO_GENLK_VSYNC_GSL_MASK_NO', + 1: 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', + 2: 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', +} +DCIO_GENLK_VSYNC_GSL_MASK_NO = 0 +DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 1 +DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 2 +DCIO_GENLK_VSYNC_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_SWAPLOCK_A_GSL_MASK' +DCIO_SWAPLOCK_A_GSL_MASK__enumvalues = { + 0: 'DCIO_SWAPLOCK_A_GSL_MASK_NO', + 1: 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', + 2: 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', +} +DCIO_SWAPLOCK_A_GSL_MASK_NO = 0 +DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 1 +DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 2 +DCIO_SWAPLOCK_A_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_SWAPLOCK_B_GSL_MASK' +DCIO_SWAPLOCK_B_GSL_MASK__enumvalues = { + 0: 'DCIO_SWAPLOCK_B_GSL_MASK_NO', + 1: 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', + 2: 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', +} +DCIO_SWAPLOCK_B_GSL_MASK_NO = 0 +DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 1 +DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 2 +DCIO_SWAPLOCK_B_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GSL_VSYNC_SEL' +DCIO_GSL_VSYNC_SEL__enumvalues = { + 0: 'DCIO_GSL_VSYNC_SEL_PIPE0', + 1: 'DCIO_GSL_VSYNC_SEL_PIPE1', + 2: 'DCIO_GSL_VSYNC_SEL_PIPE2', + 3: 'DCIO_GSL_VSYNC_SEL_PIPE3', + 4: 'DCIO_GSL_VSYNC_SEL_PIPE4', + 5: 'DCIO_GSL_VSYNC_SEL_PIPE5', +} +DCIO_GSL_VSYNC_SEL_PIPE0 = 0 +DCIO_GSL_VSYNC_SEL_PIPE1 = 1 +DCIO_GSL_VSYNC_SEL_PIPE2 = 2 +DCIO_GSL_VSYNC_SEL_PIPE3 = 3 +DCIO_GSL_VSYNC_SEL_PIPE4 = 4 +DCIO_GSL_VSYNC_SEL_PIPE5 = 5 +DCIO_GSL_VSYNC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GSL0_TIMING_SYNC_SEL' +DCIO_GSL0_TIMING_SYNC_SEL__enumvalues = { + 0: 'DCIO_GSL0_TIMING_SYNC_SEL_PIPE', + 1: 'DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC', + 2: 'DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK', + 3: 'DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A', + 4: 'DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B', +} +DCIO_GSL0_TIMING_SYNC_SEL_PIPE = 0 +DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC = 1 +DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 2 +DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A = 3 +DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B = 4 +DCIO_GSL0_TIMING_SYNC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GSL0_GLOBAL_UNLOCK_SEL' +DCIO_GSL0_GLOBAL_UNLOCK_SEL__enumvalues = { + 0: 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION', + 1: 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', + 2: 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK', + 3: 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', + 4: 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', +} +DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION = 0 +DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 1 +DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 2 +DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 3 +DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 4 +DCIO_GSL0_GLOBAL_UNLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GSL1_TIMING_SYNC_SEL' +DCIO_GSL1_TIMING_SYNC_SEL__enumvalues = { + 0: 'DCIO_GSL1_TIMING_SYNC_SEL_PIPE', + 1: 'DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC', + 2: 'DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK', + 3: 'DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A', + 4: 'DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B', +} +DCIO_GSL1_TIMING_SYNC_SEL_PIPE = 0 +DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC = 1 +DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 2 +DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A = 3 +DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B = 4 +DCIO_GSL1_TIMING_SYNC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GSL1_GLOBAL_UNLOCK_SEL' +DCIO_GSL1_GLOBAL_UNLOCK_SEL__enumvalues = { + 0: 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION', + 1: 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', + 2: 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK', + 3: 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', + 4: 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', +} +DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION = 0 +DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 1 +DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 2 +DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 3 +DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 4 +DCIO_GSL1_GLOBAL_UNLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GSL2_TIMING_SYNC_SEL' +DCIO_GSL2_TIMING_SYNC_SEL__enumvalues = { + 0: 'DCIO_GSL2_TIMING_SYNC_SEL_PIPE', + 1: 'DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC', + 2: 'DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK', + 3: 'DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A', + 4: 'DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B', +} +DCIO_GSL2_TIMING_SYNC_SEL_PIPE = 0 +DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 1 +DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 2 +DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A = 3 +DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B = 4 +DCIO_GSL2_TIMING_SYNC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GSL2_GLOBAL_UNLOCK_SEL' +DCIO_GSL2_GLOBAL_UNLOCK_SEL__enumvalues = { + 0: 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION', + 1: 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', + 2: 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK', + 3: 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', + 4: 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', +} +DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION = 0 +DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 1 +DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 2 +DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 3 +DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 4 +DCIO_GSL2_GLOBAL_UNLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPU_TIMER_START_POSITION' +DCIO_DC_GPU_TIMER_START_POSITION__enumvalues = { + 0: 'DCIO_GPU_TIMER_START_0_END_27', + 1: 'DCIO_GPU_TIMER_START_1_END_28', + 2: 'DCIO_GPU_TIMER_START_2_END_29', + 3: 'DCIO_GPU_TIMER_START_3_END_30', + 4: 'DCIO_GPU_TIMER_START_4_END_31', + 5: 'DCIO_GPU_TIMER_START_6_END_33', + 6: 'DCIO_GPU_TIMER_START_8_END_35', + 7: 'DCIO_GPU_TIMER_START_10_END_37', +} +DCIO_GPU_TIMER_START_0_END_27 = 0 +DCIO_GPU_TIMER_START_1_END_28 = 1 +DCIO_GPU_TIMER_START_2_END_29 = 2 +DCIO_GPU_TIMER_START_3_END_30 = 3 +DCIO_GPU_TIMER_START_4_END_31 = 4 +DCIO_GPU_TIMER_START_6_END_33 = 5 +DCIO_GPU_TIMER_START_8_END_35 = 6 +DCIO_GPU_TIMER_START_10_END_37 = 7 +DCIO_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL' +DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL__enumvalues = { + 0: 'DCIO_TEST_CLK_SEL_DISPCLK', + 1: 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', + 2: 'DCIO_TEST_CLK_SEL_SCLK', +} +DCIO_TEST_CLK_SEL_DISPCLK = 0 +DCIO_TEST_CLK_SEL_GATED_DISPCLK = 1 +DCIO_TEST_CLK_SEL_SCLK = 2 +DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS' +DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS__enumvalues = { + 0: 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', + 1: 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', +} +DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0 +DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 1 +DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DCO_DCFE_EXT_VSYNC_MUX' +DCIO_DCO_DCFE_EXT_VSYNC_MUX__enumvalues = { + 0: 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', + 1: 'DCIO_EXT_VSYNC_MUX_CRTC0', + 2: 'DCIO_EXT_VSYNC_MUX_CRTC1', + 3: 'DCIO_EXT_VSYNC_MUX_CRTC2', + 4: 'DCIO_EXT_VSYNC_MUX_CRTC3', + 5: 'DCIO_EXT_VSYNC_MUX_CRTC4', + 6: 'DCIO_EXT_VSYNC_MUX_CRTC5', + 7: 'DCIO_EXT_VSYNC_MUX_GENERICB', +} +DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0 +DCIO_EXT_VSYNC_MUX_CRTC0 = 1 +DCIO_EXT_VSYNC_MUX_CRTC1 = 2 +DCIO_EXT_VSYNC_MUX_CRTC2 = 3 +DCIO_EXT_VSYNC_MUX_CRTC3 = 4 +DCIO_EXT_VSYNC_MUX_CRTC4 = 5 +DCIO_EXT_VSYNC_MUX_CRTC5 = 6 +DCIO_EXT_VSYNC_MUX_GENERICB = 7 +DCIO_DCO_DCFE_EXT_VSYNC_MUX = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DCO_EXT_VSYNC_MASK' +DCIO_DCO_EXT_VSYNC_MASK__enumvalues = { + 0: 'DCIO_EXT_VSYNC_MASK_NONE', + 1: 'DCIO_EXT_VSYNC_MASK_PIPE0', + 2: 'DCIO_EXT_VSYNC_MASK_PIPE1', + 3: 'DCIO_EXT_VSYNC_MASK_PIPE2', + 4: 'DCIO_EXT_VSYNC_MASK_PIPE3', + 5: 'DCIO_EXT_VSYNC_MASK_PIPE4', + 6: 'DCIO_EXT_VSYNC_MASK_PIPE5', + 7: 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', +} +DCIO_EXT_VSYNC_MASK_NONE = 0 +DCIO_EXT_VSYNC_MASK_PIPE0 = 1 +DCIO_EXT_VSYNC_MASK_PIPE1 = 2 +DCIO_EXT_VSYNC_MASK_PIPE2 = 3 +DCIO_EXT_VSYNC_MASK_PIPE3 = 4 +DCIO_EXT_VSYNC_MASK_PIPE4 = 5 +DCIO_EXT_VSYNC_MASK_PIPE5 = 6 +DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 7 +DCIO_DCO_EXT_VSYNC_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DSYNC_SOFT_RESET' +DCIO_DSYNC_SOFT_RESET__enumvalues = { + 0: 'DCIO_DSYNC_SOFT_RESET_DEASSERT', + 1: 'DCIO_DSYNC_SOFT_RESET_ASSERT', +} +DCIO_DSYNC_SOFT_RESET_DEASSERT = 0 +DCIO_DSYNC_SOFT_RESET_ASSERT = 1 +DCIO_DSYNC_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DACA_SOFT_RESET' +DCIO_DACA_SOFT_RESET__enumvalues = { + 0: 'DCIO_DACA_SOFT_RESET_DEASSERT', + 1: 'DCIO_DACA_SOFT_RESET_ASSERT', +} +DCIO_DACA_SOFT_RESET_DEASSERT = 0 +DCIO_DACA_SOFT_RESET_ASSERT = 1 +DCIO_DACA_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DCRXPHY_SOFT_RESET' +DCIO_DCRXPHY_SOFT_RESET__enumvalues = { + 0: 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', + 1: 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', +} +DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0 +DCIO_DCRXPHY_SOFT_RESET_ASSERT = 1 +DCIO_DCRXPHY_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DPHY_LANE_SEL' +DCIO_DPHY_LANE_SEL__enumvalues = { + 0: 'DCIO_DPHY_LANE_SEL_LANE0', + 1: 'DCIO_DPHY_LANE_SEL_LANE1', + 2: 'DCIO_DPHY_LANE_SEL_LANE2', + 3: 'DCIO_DPHY_LANE_SEL_LANE3', +} +DCIO_DPHY_LANE_SEL_LANE0 = 0 +DCIO_DPHY_LANE_SEL_LANE1 = 1 +DCIO_DPHY_LANE_SEL_LANE2 = 2 +DCIO_DPHY_LANE_SEL_LANE3 = 3 +DCIO_DPHY_LANE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DPCS_INTERRUPT_TYPE' +DCIO_DPCS_INTERRUPT_TYPE__enumvalues = { + 0: 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', + 1: 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', +} +DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0 +DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 1 +DCIO_DPCS_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DPCS_INTERRUPT_MASK' +DCIO_DPCS_INTERRUPT_MASK__enumvalues = { + 0: 'DCIO_DPCS_INTERRUPT_DISABLE', + 1: 'DCIO_DPCS_INTERRUPT_ENABLE', +} +DCIO_DPCS_INTERRUPT_DISABLE = 0 +DCIO_DPCS_INTERRUPT_ENABLE = 1 +DCIO_DPCS_INTERRUPT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPU_TIMER_READ_SELECT' +DCIO_DC_GPU_TIMER_READ_SELECT__enumvalues = { + 0: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', + 1: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', + 2: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE', + 3: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE', + 4: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE', + 5: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE', + 6: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE', + 7: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE', + 8: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE', + 9: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE', + 10: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE', + 11: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE', + 12: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', + 13: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', + 14: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP', + 15: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP', + 16: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP', + 17: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP', + 18: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP', + 19: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP', + 20: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP', + 21: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP', + 22: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP', + 23: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP', + 24: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', + 25: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', + 26: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM', + 27: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM', + 28: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM', + 29: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM', + 30: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM', + 31: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM', + 32: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM', + 33: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM', + 34: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM', + 35: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM', +} +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 1 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 2 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 3 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 4 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 5 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE = 6 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE = 7 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE = 8 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE = 9 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE = 10 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE = 11 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 12 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 13 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 14 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 15 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 16 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 17 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP = 18 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP = 19 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP = 20 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP = 21 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP = 22 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP = 23 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 24 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 25 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 26 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 27 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 28 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 29 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM = 30 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM = 31 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM = 32 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM = 33 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM = 34 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM = 35 +DCIO_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_IMPCAL_STEP_DELAY' +DCIO_IMPCAL_STEP_DELAY__enumvalues = { + 0: 'DCIO_IMPCAL_STEP_DELAY_1us', + 1: 'DCIO_IMPCAL_STEP_DELAY_2us', + 2: 'DCIO_IMPCAL_STEP_DELAY_3us', + 3: 'DCIO_IMPCAL_STEP_DELAY_4us', + 4: 'DCIO_IMPCAL_STEP_DELAY_5us', + 5: 'DCIO_IMPCAL_STEP_DELAY_6us', + 6: 'DCIO_IMPCAL_STEP_DELAY_7us', + 7: 'DCIO_IMPCAL_STEP_DELAY_8us', + 8: 'DCIO_IMPCAL_STEP_DELAY_9us', + 9: 'DCIO_IMPCAL_STEP_DELAY_10us', + 10: 'DCIO_IMPCAL_STEP_DELAY_11us', + 11: 'DCIO_IMPCAL_STEP_DELAY_12us', + 12: 'DCIO_IMPCAL_STEP_DELAY_13us', + 13: 'DCIO_IMPCAL_STEP_DELAY_14us', + 14: 'DCIO_IMPCAL_STEP_DELAY_15us', + 15: 'DCIO_IMPCAL_STEP_DELAY_16us', +} +DCIO_IMPCAL_STEP_DELAY_1us = 0 +DCIO_IMPCAL_STEP_DELAY_2us = 1 +DCIO_IMPCAL_STEP_DELAY_3us = 2 +DCIO_IMPCAL_STEP_DELAY_4us = 3 +DCIO_IMPCAL_STEP_DELAY_5us = 4 +DCIO_IMPCAL_STEP_DELAY_6us = 5 +DCIO_IMPCAL_STEP_DELAY_7us = 6 +DCIO_IMPCAL_STEP_DELAY_8us = 7 +DCIO_IMPCAL_STEP_DELAY_9us = 8 +DCIO_IMPCAL_STEP_DELAY_10us = 9 +DCIO_IMPCAL_STEP_DELAY_11us = 10 +DCIO_IMPCAL_STEP_DELAY_12us = 11 +DCIO_IMPCAL_STEP_DELAY_13us = 12 +DCIO_IMPCAL_STEP_DELAY_14us = 13 +DCIO_IMPCAL_STEP_DELAY_15us = 14 +DCIO_IMPCAL_STEP_DELAY_16us = 15 +DCIO_IMPCAL_STEP_DELAY = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_IMPCAL_SEL' +DCIO_UNIPHY_IMPCAL_SEL__enumvalues = { + 0: 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', + 1: 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', +} +DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0 +DCIO_UNIPHY_IMPCAL_SEL_BINARY = 1 +DCIO_UNIPHY_IMPCAL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DBG_ASYNC_BLOCK_SEL' +DCIO_DBG_ASYNC_BLOCK_SEL__enumvalues = { + 0: 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', + 1: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', + 2: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', + 3: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCO', +} +DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0 +DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 1 +DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 2 +DCIO_DBG_ASYNC_BLOCK_SEL_DCO = 3 +DCIO_DBG_ASYNC_BLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DBG_ASYNC_4BIT_SEL' +DCIO_DBG_ASYNC_4BIT_SEL__enumvalues = { + 0: 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', + 1: 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', + 2: 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', + 3: 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', + 4: 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', + 5: 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', + 6: 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', + 7: 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', +} +DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0 +DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 1 +DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 2 +DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 3 +DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 4 +DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 5 +DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 6 +DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 7 +DCIO_DBG_ASYNC_4BIT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'AOUT_EN' +AOUT_EN__enumvalues = { + 0: 'AOUT_DISABLE', + 1: 'AOUT_ENABLE', +} +AOUT_DISABLE = 0 +AOUT_ENABLE = 1 +AOUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'AOUT_FIFO_START_ADDR' +AOUT_FIFO_START_ADDR__enumvalues = { + 0: 'AOUT_FIFO_START_ADDR_2', + 1: 'AOUT_FIFO_START_ADDR_3', +} +AOUT_FIFO_START_ADDR_2 = 0 +AOUT_FIFO_START_ADDR_3 = 1 +AOUT_FIFO_START_ADDR = ctypes.c_uint32 # enum + +# values for enumeration 'AOUT_CRC_TEST_EN' +AOUT_CRC_TEST_EN__enumvalues = { + 0: 'AOUT_CRC_DISABLE', + 1: 'AOUT_CRC_ENABLE', +} +AOUT_CRC_DISABLE = 0 +AOUT_CRC_ENABLE = 1 +AOUT_CRC_TEST_EN = ctypes.c_uint32 # enum + +# values for enumeration 'AOUT_CRC_SOFT_RESET' +AOUT_CRC_SOFT_RESET__enumvalues = { + 0: 'AOUT_CRC_NO_RESET', + 1: 'AOUT_CRC_RESET', +} +AOUT_CRC_NO_RESET = 0 +AOUT_CRC_RESET = 1 +AOUT_CRC_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'AOUT_CRC_CONT_EN' +AOUT_CRC_CONT_EN__enumvalues = { + 0: 'AOUT_CRC_ONE_SHOT', + 1: 'AOUT_CRC_CONT', +} +AOUT_CRC_ONE_SHOT = 0 +AOUT_CRC_CONT = 1 +AOUT_CRC_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'I2S_WORD_SIZE' +I2S_WORD_SIZE__enumvalues = { + 0: 'I2S_WORD_SIZE_32', + 1: 'I2S_WORD_SIZE_16', +} +I2S_WORD_SIZE_32 = 0 +I2S_WORD_SIZE_16 = 1 +I2S_WORD_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'I2S_SAMPLE_ALIGNMENT' +I2S_SAMPLE_ALIGNMENT__enumvalues = { + 0: 'I2S_SAMPLE_LEFT_ALIGNED', + 1: 'I2S_SAMPLE_RIGHT_ALIGNED', +} +I2S_SAMPLE_LEFT_ALIGNED = 0 +I2S_SAMPLE_RIGHT_ALIGNED = 1 +I2S_SAMPLE_ALIGNMENT = ctypes.c_uint32 # enum + +# values for enumeration 'I2S_SAMPLE_BIT_ORDER' +I2S_SAMPLE_BIT_ORDER__enumvalues = { + 0: 'I2S_SAMPLE_BIT_ORDER_MSB', + 1: 'I2S_SAMPLE_BIT_ORDER_LSB', +} +I2S_SAMPLE_BIT_ORDER_MSB = 0 +I2S_SAMPLE_BIT_ORDER_LSB = 1 +I2S_SAMPLE_BIT_ORDER = ctypes.c_uint32 # enum + +# values for enumeration 'I2S_LRCLK_POLARITY' +I2S_LRCLK_POLARITY__enumvalues = { + 0: 'I2S_LRCLK_LOW_LEFT', + 1: 'I2S_LRCLK_HIGH_LEFT', +} +I2S_LRCLK_LOW_LEFT = 0 +I2S_LRCLK_HIGH_LEFT = 1 +I2S_LRCLK_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'I2S_WORD_ALIGNMENT' +I2S_WORD_ALIGNMENT__enumvalues = { + 0: 'I2S_WORD_ALTERNATE_ALIGNMENT', + 1: 'I2S_WORD_I2S_ALIGNMENT', +} +I2S_WORD_ALTERNATE_ALIGNMENT = 0 +I2S_WORD_I2S_ALIGNMENT = 1 +I2S_WORD_ALIGNMENT = ctypes.c_uint32 # enum + +# values for enumeration 'SPDIF_INVERT_EN' +SPDIF_INVERT_EN__enumvalues = { + 0: 'SPDIF_INVERT_DISABLE', + 1: 'SPDIF_INVERT_ENABLE', +} +SPDIF_INVERT_DISABLE = 0 +SPDIF_INVERT_ENABLE = 1 +SPDIF_INVERT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPDBG_EN' +DPDBG_EN__enumvalues = { + 0: 'DPDBG_DISABLE', + 1: 'DPDBG_ENABLE', +} +DPDBG_DISABLE = 0 +DPDBG_ENABLE = 1 +DPDBG_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPDBG_INPUT_EN' +DPDBG_INPUT_EN__enumvalues = { + 0: 'DPDBG_INPUT_DISABLE', + 1: 'DPDBG_INPUT_ENABLE', +} +DPDBG_INPUT_DISABLE = 0 +DPDBG_INPUT_ENABLE = 1 +DPDBG_INPUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPDBG_ERROR_DETECTION_MODE' +DPDBG_ERROR_DETECTION_MODE__enumvalues = { + 0: 'DPDBG_ERROR_DETECTION_MODE_CSC', + 1: 'DPDBG_ERROR_DETECTION_MODE_RS_ENCODING', +} +DPDBG_ERROR_DETECTION_MODE_CSC = 0 +DPDBG_ERROR_DETECTION_MODE_RS_ENCODING = 1 +DPDBG_ERROR_DETECTION_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK' +DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK__enumvalues = { + 0: 'DPDBG_FIFO_OVERFLOW_INT_DISABLE', + 1: 'DPDBG_FIFO_OVERFLOW_INT_ENABLE', +} +DPDBG_FIFO_OVERFLOW_INT_DISABLE = 0 +DPDBG_FIFO_OVERFLOW_INT_ENABLE = 1 +DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE' +DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE__enumvalues = { + 0: 'DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED', + 1: 'DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED', +} +DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED = 0 +DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED = 1 +DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK' +DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK__enumvalues = { + 0: 'DPDBG_FIFO_OVERFLOW_INT_NO_ACK', + 1: 'DPDBG_FIFO_OVERFLOW_INT_CLEAR', +} +DPDBG_FIFO_OVERFLOW_INT_NO_ACK = 0 +DPDBG_FIFO_OVERFLOW_INT_CLEAR = 1 +DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'PM_ASSERT_RESET' +PM_ASSERT_RESET__enumvalues = { + 0: 'PM_ASSERT_RESET_0', + 1: 'PM_ASSERT_RESET_1', +} +PM_ASSERT_RESET_0 = 0 +PM_ASSERT_RESET_1 = 1 +PM_ASSERT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DAC_MUX_SELECT' +DAC_MUX_SELECT__enumvalues = { + 0: 'DAC_MUX_SELECT_DACA', + 1: 'DAC_MUX_SELECT_DACB', +} +DAC_MUX_SELECT_DACA = 0 +DAC_MUX_SELECT_DACB = 1 +DAC_MUX_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_DVO_MUX_SELECT' +TMDS_DVO_MUX_SELECT__enumvalues = { + 0: 'TMDS_DVO_MUX_SELECT_B', + 1: 'TMDS_DVO_MUX_SELECT_G', + 2: 'TMDS_DVO_MUX_SELECT_R', + 3: 'TMDS_DVO_MUX_SELECT_RESERVED', +} +TMDS_DVO_MUX_SELECT_B = 0 +TMDS_DVO_MUX_SELECT_G = 1 +TMDS_DVO_MUX_SELECT_R = 2 +TMDS_DVO_MUX_SELECT_RESERVED = 3 +TMDS_DVO_MUX_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DACA_SOFT_RESET' +DACA_SOFT_RESET__enumvalues = { + 0: 'DACA_SOFT_RESET_0', + 1: 'DACA_SOFT_RESET_1', +} +DACA_SOFT_RESET_0 = 0 +DACA_SOFT_RESET_1 = 1 +DACA_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'I2S0_SPDIF0_SOFT_RESET' +I2S0_SPDIF0_SOFT_RESET__enumvalues = { + 0: 'I2S0_SPDIF0_SOFT_RESET_0', + 1: 'I2S0_SPDIF0_SOFT_RESET_1', +} +I2S0_SPDIF0_SOFT_RESET_0 = 0 +I2S0_SPDIF0_SOFT_RESET_1 = 1 +I2S0_SPDIF0_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'I2S1_SOFT_RESET' +I2S1_SOFT_RESET__enumvalues = { + 0: 'I2S1_SOFT_RESET_0', + 1: 'I2S1_SOFT_RESET_1', +} +I2S1_SOFT_RESET_0 = 0 +I2S1_SOFT_RESET_1 = 1 +I2S1_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'SPDIF1_SOFT_RESET' +SPDIF1_SOFT_RESET__enumvalues = { + 0: 'SPDIF1_SOFT_RESET_0', + 1: 'SPDIF1_SOFT_RESET_1', +} +SPDIF1_SOFT_RESET_0 = 0 +SPDIF1_SOFT_RESET_1 = 1 +SPDIF1_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DB_CLK_SOFT_RESET' +DB_CLK_SOFT_RESET__enumvalues = { + 0: 'DB_CLK_SOFT_RESET_0', + 1: 'DB_CLK_SOFT_RESET_1', +} +DB_CLK_SOFT_RESET_0 = 0 +DB_CLK_SOFT_RESET_1 = 1 +DB_CLK_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'FMT0_SOFT_RESET' +FMT0_SOFT_RESET__enumvalues = { + 0: 'FMT0_SOFT_RESET_0', + 1: 'FMT0_SOFT_RESET_1', +} +FMT0_SOFT_RESET_0 = 0 +FMT0_SOFT_RESET_1 = 1 +FMT0_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'FMT1_SOFT_RESET' +FMT1_SOFT_RESET__enumvalues = { + 0: 'FMT1_SOFT_RESET_0', + 1: 'FMT1_SOFT_RESET_1', +} +FMT1_SOFT_RESET_0 = 0 +FMT1_SOFT_RESET_1 = 1 +FMT1_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'FMT2_SOFT_RESET' +FMT2_SOFT_RESET__enumvalues = { + 0: 'FMT2_SOFT_RESET_0', + 1: 'FMT2_SOFT_RESET_1', +} +FMT2_SOFT_RESET_0 = 0 +FMT2_SOFT_RESET_1 = 1 +FMT2_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'FMT3_SOFT_RESET' +FMT3_SOFT_RESET__enumvalues = { + 0: 'FMT3_SOFT_RESET_0', + 1: 'FMT3_SOFT_RESET_1', +} +FMT3_SOFT_RESET_0 = 0 +FMT3_SOFT_RESET_1 = 1 +FMT3_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'FMT4_SOFT_RESET' +FMT4_SOFT_RESET__enumvalues = { + 0: 'FMT4_SOFT_RESET_0', + 1: 'FMT4_SOFT_RESET_1', +} +FMT4_SOFT_RESET_0 = 0 +FMT4_SOFT_RESET_1 = 1 +FMT4_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'FMT5_SOFT_RESET' +FMT5_SOFT_RESET__enumvalues = { + 0: 'FMT5_SOFT_RESET_0', + 1: 'FMT5_SOFT_RESET_1', +} +FMT5_SOFT_RESET_0 = 0 +FMT5_SOFT_RESET_1 = 1 +FMT5_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'MVP_SOFT_RESET' +MVP_SOFT_RESET__enumvalues = { + 0: 'MVP_SOFT_RESET_0', + 1: 'MVP_SOFT_RESET_1', +} +MVP_SOFT_RESET_0 = 0 +MVP_SOFT_RESET_1 = 1 +MVP_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'ABM_SOFT_RESET' +ABM_SOFT_RESET__enumvalues = { + 0: 'ABM_SOFT_RESET_0', + 1: 'ABM_SOFT_RESET_1', +} +ABM_SOFT_RESET_0 = 0 +ABM_SOFT_RESET_1 = 1 +ABM_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DVO_SOFT_RESET' +DVO_SOFT_RESET__enumvalues = { + 0: 'DVO_SOFT_RESET_0', + 1: 'DVO_SOFT_RESET_1', +} +DVO_SOFT_RESET_0 = 0 +DVO_SOFT_RESET_1 = 1 +DVO_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGA_FE_SOFT_RESET' +DIGA_FE_SOFT_RESET__enumvalues = { + 0: 'DIGA_FE_SOFT_RESET_0', + 1: 'DIGA_FE_SOFT_RESET_1', +} +DIGA_FE_SOFT_RESET_0 = 0 +DIGA_FE_SOFT_RESET_1 = 1 +DIGA_FE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGA_BE_SOFT_RESET' +DIGA_BE_SOFT_RESET__enumvalues = { + 0: 'DIGA_BE_SOFT_RESET_0', + 1: 'DIGA_BE_SOFT_RESET_1', +} +DIGA_BE_SOFT_RESET_0 = 0 +DIGA_BE_SOFT_RESET_1 = 1 +DIGA_BE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGB_FE_SOFT_RESET' +DIGB_FE_SOFT_RESET__enumvalues = { + 0: 'DIGB_FE_SOFT_RESET_0', + 1: 'DIGB_FE_SOFT_RESET_1', +} +DIGB_FE_SOFT_RESET_0 = 0 +DIGB_FE_SOFT_RESET_1 = 1 +DIGB_FE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGB_BE_SOFT_RESET' +DIGB_BE_SOFT_RESET__enumvalues = { + 0: 'DIGB_BE_SOFT_RESET_0', + 1: 'DIGB_BE_SOFT_RESET_1', +} +DIGB_BE_SOFT_RESET_0 = 0 +DIGB_BE_SOFT_RESET_1 = 1 +DIGB_BE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGC_FE_SOFT_RESET' +DIGC_FE_SOFT_RESET__enumvalues = { + 0: 'DIGC_FE_SOFT_RESET_0', + 1: 'DIGC_FE_SOFT_RESET_1', +} +DIGC_FE_SOFT_RESET_0 = 0 +DIGC_FE_SOFT_RESET_1 = 1 +DIGC_FE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGC_BE_SOFT_RESET' +DIGC_BE_SOFT_RESET__enumvalues = { + 0: 'DIGC_BE_SOFT_RESET_0', + 1: 'DIGC_BE_SOFT_RESET_1', +} +DIGC_BE_SOFT_RESET_0 = 0 +DIGC_BE_SOFT_RESET_1 = 1 +DIGC_BE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGD_FE_SOFT_RESET' +DIGD_FE_SOFT_RESET__enumvalues = { + 0: 'DIGD_FE_SOFT_RESET_0', + 1: 'DIGD_FE_SOFT_RESET_1', +} +DIGD_FE_SOFT_RESET_0 = 0 +DIGD_FE_SOFT_RESET_1 = 1 +DIGD_FE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGD_BE_SOFT_RESET' +DIGD_BE_SOFT_RESET__enumvalues = { + 0: 'DIGD_BE_SOFT_RESET_0', + 1: 'DIGD_BE_SOFT_RESET_1', +} +DIGD_BE_SOFT_RESET_0 = 0 +DIGD_BE_SOFT_RESET_1 = 1 +DIGD_BE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGE_FE_SOFT_RESET' +DIGE_FE_SOFT_RESET__enumvalues = { + 0: 'DIGE_FE_SOFT_RESET_0', + 1: 'DIGE_FE_SOFT_RESET_1', +} +DIGE_FE_SOFT_RESET_0 = 0 +DIGE_FE_SOFT_RESET_1 = 1 +DIGE_FE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGE_BE_SOFT_RESET' +DIGE_BE_SOFT_RESET__enumvalues = { + 0: 'DIGE_BE_SOFT_RESET_0', + 1: 'DIGE_BE_SOFT_RESET_1', +} +DIGE_BE_SOFT_RESET_0 = 0 +DIGE_BE_SOFT_RESET_1 = 1 +DIGE_BE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGF_FE_SOFT_RESET' +DIGF_FE_SOFT_RESET__enumvalues = { + 0: 'DIGF_FE_SOFT_RESET_0', + 1: 'DIGF_FE_SOFT_RESET_1', +} +DIGF_FE_SOFT_RESET_0 = 0 +DIGF_FE_SOFT_RESET_1 = 1 +DIGF_FE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGF_BE_SOFT_RESET' +DIGF_BE_SOFT_RESET__enumvalues = { + 0: 'DIGF_BE_SOFT_RESET_0', + 1: 'DIGF_BE_SOFT_RESET_1', +} +DIGF_BE_SOFT_RESET_0 = 0 +DIGF_BE_SOFT_RESET_1 = 1 +DIGF_BE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGG_FE_SOFT_RESET' +DIGG_FE_SOFT_RESET__enumvalues = { + 0: 'DIGG_FE_SOFT_RESET_0', + 1: 'DIGG_FE_SOFT_RESET_1', +} +DIGG_FE_SOFT_RESET_0 = 0 +DIGG_FE_SOFT_RESET_1 = 1 +DIGG_FE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGG_BE_SOFT_RESET' +DIGG_BE_SOFT_RESET__enumvalues = { + 0: 'DIGG_BE_SOFT_RESET_0', + 1: 'DIGG_BE_SOFT_RESET_1', +} +DIGG_BE_SOFT_RESET_0 = 0 +DIGG_BE_SOFT_RESET_1 = 1 +DIGG_BE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DPDBG_SOFT_RESET' +DPDBG_SOFT_RESET__enumvalues = { + 0: 'DPDBG_SOFT_RESET_0', + 1: 'DPDBG_SOFT_RESET_1', +} +DPDBG_SOFT_RESET_0 = 0 +DPDBG_SOFT_RESET_1 = 1 +DPDBG_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGLPA_FE_SOFT_RESET' +DIGLPA_FE_SOFT_RESET__enumvalues = { + 0: 'DIGLPA_FE_SOFT_RESET_0', + 1: 'DIGLPA_FE_SOFT_RESET_1', +} +DIGLPA_FE_SOFT_RESET_0 = 0 +DIGLPA_FE_SOFT_RESET_1 = 1 +DIGLPA_FE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGLPA_BE_SOFT_RESET' +DIGLPA_BE_SOFT_RESET__enumvalues = { + 0: 'DIGLPA_BE_SOFT_RESET_0', + 1: 'DIGLPA_BE_SOFT_RESET_1', +} +DIGLPA_BE_SOFT_RESET_0 = 0 +DIGLPA_BE_SOFT_RESET_1 = 1 +DIGLPA_BE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGLPB_FE_SOFT_RESET' +DIGLPB_FE_SOFT_RESET__enumvalues = { + 0: 'DIGLPB_FE_SOFT_RESET_0', + 1: 'DIGLPB_FE_SOFT_RESET_1', +} +DIGLPB_FE_SOFT_RESET_0 = 0 +DIGLPB_FE_SOFT_RESET_1 = 1 +DIGLPB_FE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGLPB_BE_SOFT_RESET' +DIGLPB_BE_SOFT_RESET__enumvalues = { + 0: 'DIGLPB_BE_SOFT_RESET_0', + 1: 'DIGLPB_BE_SOFT_RESET_1', +} +DIGLPB_BE_SOFT_RESET_0 = 0 +DIGLPB_BE_SOFT_RESET_1 = 1 +DIGLPB_BE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'GENERICA_STEREOSYNC_SEL' +GENERICA_STEREOSYNC_SEL__enumvalues = { + 0: 'GENERICA_STEREOSYNC_SEL_D1', + 1: 'GENERICA_STEREOSYNC_SEL_D2', + 2: 'GENERICA_STEREOSYNC_SEL_D3', + 3: 'GENERICA_STEREOSYNC_SEL_D4', + 4: 'GENERICA_STEREOSYNC_SEL_D5', + 5: 'GENERICA_STEREOSYNC_SEL_D6', + 6: 'GENERICA_STEREOSYNC_SEL_RESERVED', +} +GENERICA_STEREOSYNC_SEL_D1 = 0 +GENERICA_STEREOSYNC_SEL_D2 = 1 +GENERICA_STEREOSYNC_SEL_D3 = 2 +GENERICA_STEREOSYNC_SEL_D4 = 3 +GENERICA_STEREOSYNC_SEL_D5 = 4 +GENERICA_STEREOSYNC_SEL_D6 = 5 +GENERICA_STEREOSYNC_SEL_RESERVED = 6 +GENERICA_STEREOSYNC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GENERICB_STEREOSYNC_SEL' +GENERICB_STEREOSYNC_SEL__enumvalues = { + 0: 'GENERICB_STEREOSYNC_SEL_D1', + 1: 'GENERICB_STEREOSYNC_SEL_D2', + 2: 'GENERICB_STEREOSYNC_SEL_D3', + 3: 'GENERICB_STEREOSYNC_SEL_D4', + 4: 'GENERICB_STEREOSYNC_SEL_D5', + 5: 'GENERICB_STEREOSYNC_SEL_D6', + 6: 'GENERICB_STEREOSYNC_SEL_RESERVED', +} +GENERICB_STEREOSYNC_SEL_D1 = 0 +GENERICB_STEREOSYNC_SEL_D2 = 1 +GENERICB_STEREOSYNC_SEL_D3 = 2 +GENERICB_STEREOSYNC_SEL_D4 = 3 +GENERICB_STEREOSYNC_SEL_D5 = 4 +GENERICB_STEREOSYNC_SEL_D6 = 5 +GENERICB_STEREOSYNC_SEL_RESERVED = 6 +GENERICB_STEREOSYNC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCO_DBG_BLOCK_SEL' +DCO_DBG_BLOCK_SEL__enumvalues = { + 0: 'DCO_DBG_BLOCK_SEL_DCO', + 1: 'DCO_DBG_BLOCK_SEL_ABM', + 2: 'DCO_DBG_BLOCK_SEL_DVO', + 3: 'DCO_DBG_BLOCK_SEL_DAC', + 4: 'DCO_DBG_BLOCK_SEL_MVP', + 5: 'DCO_DBG_BLOCK_SEL_FMT0', + 6: 'DCO_DBG_BLOCK_SEL_FMT1', + 7: 'DCO_DBG_BLOCK_SEL_FMT2', + 8: 'DCO_DBG_BLOCK_SEL_FMT3', + 9: 'DCO_DBG_BLOCK_SEL_FMT4', + 10: 'DCO_DBG_BLOCK_SEL_FMT5', + 11: 'DCO_DBG_BLOCK_SEL_DIGFE_A', + 12: 'DCO_DBG_BLOCK_SEL_DIGFE_B', + 13: 'DCO_DBG_BLOCK_SEL_DIGFE_C', + 14: 'DCO_DBG_BLOCK_SEL_DIGFE_D', + 15: 'DCO_DBG_BLOCK_SEL_DIGFE_E', + 16: 'DCO_DBG_BLOCK_SEL_DIGFE_F', + 17: 'DCO_DBG_BLOCK_SEL_DIGFE_G', + 18: 'DCO_DBG_BLOCK_SEL_DIGA', + 19: 'DCO_DBG_BLOCK_SEL_DIGB', + 20: 'DCO_DBG_BLOCK_SEL_DIGC', + 21: 'DCO_DBG_BLOCK_SEL_DIGD', + 22: 'DCO_DBG_BLOCK_SEL_DIGE', + 23: 'DCO_DBG_BLOCK_SEL_DIGF', + 24: 'DCO_DBG_BLOCK_SEL_DIGG', + 25: 'DCO_DBG_BLOCK_SEL_DPFE_A', + 26: 'DCO_DBG_BLOCK_SEL_DPFE_B', + 27: 'DCO_DBG_BLOCK_SEL_DPFE_C', + 28: 'DCO_DBG_BLOCK_SEL_DPFE_D', + 29: 'DCO_DBG_BLOCK_SEL_DPFE_E', + 30: 'DCO_DBG_BLOCK_SEL_DPFE_F', + 31: 'DCO_DBG_BLOCK_SEL_DPFE_G', + 32: 'DCO_DBG_BLOCK_SEL_DPA', + 33: 'DCO_DBG_BLOCK_SEL_DPB', + 34: 'DCO_DBG_BLOCK_SEL_DPC', + 35: 'DCO_DBG_BLOCK_SEL_DPD', + 36: 'DCO_DBG_BLOCK_SEL_DPE', + 37: 'DCO_DBG_BLOCK_SEL_DPF', + 38: 'DCO_DBG_BLOCK_SEL_DPG', + 39: 'DCO_DBG_BLOCK_SEL_AUX0', + 40: 'DCO_DBG_BLOCK_SEL_AUX1', + 41: 'DCO_DBG_BLOCK_SEL_AUX2', + 42: 'DCO_DBG_BLOCK_SEL_AUX3', + 43: 'DCO_DBG_BLOCK_SEL_AUX4', + 44: 'DCO_DBG_BLOCK_SEL_AUX5', + 45: 'DCO_DBG_BLOCK_SEL_PERFMON_DCO', + 46: 'DCO_DBG_BLOCK_SEL_AUDIO_OUT', + 47: 'DCO_DBG_BLOCK_SEL_DIGLPFEA', + 48: 'DCO_DBG_BLOCK_SEL_DIGLPFEB', + 49: 'DCO_DBG_BLOCK_SEL_DIGLPA', + 50: 'DCO_DBG_BLOCK_SEL_DIGLPB', + 51: 'DCO_DBG_BLOCK_SEL_DPLPFEA', + 52: 'DCO_DBG_BLOCK_SEL_DPLPFEB', + 53: 'DCO_DBG_BLOCK_SEL_DPLPA', + 54: 'DCO_DBG_BLOCK_SEL_DPLPB', +} +DCO_DBG_BLOCK_SEL_DCO = 0 +DCO_DBG_BLOCK_SEL_ABM = 1 +DCO_DBG_BLOCK_SEL_DVO = 2 +DCO_DBG_BLOCK_SEL_DAC = 3 +DCO_DBG_BLOCK_SEL_MVP = 4 +DCO_DBG_BLOCK_SEL_FMT0 = 5 +DCO_DBG_BLOCK_SEL_FMT1 = 6 +DCO_DBG_BLOCK_SEL_FMT2 = 7 +DCO_DBG_BLOCK_SEL_FMT3 = 8 +DCO_DBG_BLOCK_SEL_FMT4 = 9 +DCO_DBG_BLOCK_SEL_FMT5 = 10 +DCO_DBG_BLOCK_SEL_DIGFE_A = 11 +DCO_DBG_BLOCK_SEL_DIGFE_B = 12 +DCO_DBG_BLOCK_SEL_DIGFE_C = 13 +DCO_DBG_BLOCK_SEL_DIGFE_D = 14 +DCO_DBG_BLOCK_SEL_DIGFE_E = 15 +DCO_DBG_BLOCK_SEL_DIGFE_F = 16 +DCO_DBG_BLOCK_SEL_DIGFE_G = 17 +DCO_DBG_BLOCK_SEL_DIGA = 18 +DCO_DBG_BLOCK_SEL_DIGB = 19 +DCO_DBG_BLOCK_SEL_DIGC = 20 +DCO_DBG_BLOCK_SEL_DIGD = 21 +DCO_DBG_BLOCK_SEL_DIGE = 22 +DCO_DBG_BLOCK_SEL_DIGF = 23 +DCO_DBG_BLOCK_SEL_DIGG = 24 +DCO_DBG_BLOCK_SEL_DPFE_A = 25 +DCO_DBG_BLOCK_SEL_DPFE_B = 26 +DCO_DBG_BLOCK_SEL_DPFE_C = 27 +DCO_DBG_BLOCK_SEL_DPFE_D = 28 +DCO_DBG_BLOCK_SEL_DPFE_E = 29 +DCO_DBG_BLOCK_SEL_DPFE_F = 30 +DCO_DBG_BLOCK_SEL_DPFE_G = 31 +DCO_DBG_BLOCK_SEL_DPA = 32 +DCO_DBG_BLOCK_SEL_DPB = 33 +DCO_DBG_BLOCK_SEL_DPC = 34 +DCO_DBG_BLOCK_SEL_DPD = 35 +DCO_DBG_BLOCK_SEL_DPE = 36 +DCO_DBG_BLOCK_SEL_DPF = 37 +DCO_DBG_BLOCK_SEL_DPG = 38 +DCO_DBG_BLOCK_SEL_AUX0 = 39 +DCO_DBG_BLOCK_SEL_AUX1 = 40 +DCO_DBG_BLOCK_SEL_AUX2 = 41 +DCO_DBG_BLOCK_SEL_AUX3 = 42 +DCO_DBG_BLOCK_SEL_AUX4 = 43 +DCO_DBG_BLOCK_SEL_AUX5 = 44 +DCO_DBG_BLOCK_SEL_PERFMON_DCO = 45 +DCO_DBG_BLOCK_SEL_AUDIO_OUT = 46 +DCO_DBG_BLOCK_SEL_DIGLPFEA = 47 +DCO_DBG_BLOCK_SEL_DIGLPFEB = 48 +DCO_DBG_BLOCK_SEL_DIGLPA = 49 +DCO_DBG_BLOCK_SEL_DIGLPB = 50 +DCO_DBG_BLOCK_SEL_DPLPFEA = 51 +DCO_DBG_BLOCK_SEL_DPLPFEB = 52 +DCO_DBG_BLOCK_SEL_DPLPA = 53 +DCO_DBG_BLOCK_SEL_DPLPB = 54 +DCO_DBG_BLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE' +DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE__enumvalues = { + 0: 'DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', + 1: 'DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', +} +DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0 +DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 1 +DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT420_MEMORY_SOURCE_SEL' +FMT420_MEMORY_SOURCE_SEL__enumvalues = { + 0: 'FMT420_MEMORY_SOURCE_SEL_FMT0', + 1: 'FMT420_MEMORY_SOURCE_SEL_FMT1', + 2: 'FMT420_MEMORY_SOURCE_SEL_FMT2', + 3: 'FMT420_MEMORY_SOURCE_SEL_FMT3', + 4: 'FMT420_MEMORY_SOURCE_SEL_FMT4', + 5: 'FMT420_MEMORY_SOURCE_SEL_FMT5', + 6: 'FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED', +} +FMT420_MEMORY_SOURCE_SEL_FMT0 = 0 +FMT420_MEMORY_SOURCE_SEL_FMT1 = 1 +FMT420_MEMORY_SOURCE_SEL_FMT2 = 2 +FMT420_MEMORY_SOURCE_SEL_FMT3 = 3 +FMT420_MEMORY_SOURCE_SEL_FMT4 = 4 +FMT420_MEMORY_SOURCE_SEL_FMT5 = 5 +FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED = 6 +FMT420_MEMORY_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_GO' +DOUT_I2C_CONTROL_GO__enumvalues = { + 0: 'DOUT_I2C_CONTROL_STOP_TRANSFER', + 1: 'DOUT_I2C_CONTROL_START_TRANSFER', +} +DOUT_I2C_CONTROL_STOP_TRANSFER = 0 +DOUT_I2C_CONTROL_START_TRANSFER = 1 +DOUT_I2C_CONTROL_GO = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SOFT_RESET' +DOUT_I2C_CONTROL_SOFT_RESET__enumvalues = { + 0: 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', + 1: 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', +} +DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0 +DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 1 +DOUT_I2C_CONTROL_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET' +DOUT_I2C_CONTROL_SEND_RESET__enumvalues = { + 0: 'DOUT_I2C_CONTROL__NOT_SEND_RESET', + 1: 'DOUT_I2C_CONTROL__SEND_RESET', +} +DOUT_I2C_CONTROL__NOT_SEND_RESET = 0 +DOUT_I2C_CONTROL__SEND_RESET = 1 +DOUT_I2C_CONTROL_SEND_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SW_STATUS_RESET' +DOUT_I2C_CONTROL_SW_STATUS_RESET__enumvalues = { + 0: 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', + 1: 'DOUT_I2C_CONTROL_RESET_SW_STATUS', +} +DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0 +DOUT_I2C_CONTROL_RESET_SW_STATUS = 1 +DOUT_I2C_CONTROL_SW_STATUS_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_DDC_SELECT' +DOUT_I2C_CONTROL_DDC_SELECT__enumvalues = { + 0: 'DOUT_I2C_CONTROL_SELECT_DDC1', + 1: 'DOUT_I2C_CONTROL_SELECT_DDC2', + 2: 'DOUT_I2C_CONTROL_SELECT_DDC3', + 3: 'DOUT_I2C_CONTROL_SELECT_DDC4', + 4: 'DOUT_I2C_CONTROL_SELECT_DDC5', + 5: 'DOUT_I2C_CONTROL_SELECT_DDC6', + 6: 'DOUT_I2C_CONTROL_SELECT_DDCVGA', +} +DOUT_I2C_CONTROL_SELECT_DDC1 = 0 +DOUT_I2C_CONTROL_SELECT_DDC2 = 1 +DOUT_I2C_CONTROL_SELECT_DDC3 = 2 +DOUT_I2C_CONTROL_SELECT_DDC4 = 3 +DOUT_I2C_CONTROL_SELECT_DDC5 = 4 +DOUT_I2C_CONTROL_SELECT_DDC6 = 5 +DOUT_I2C_CONTROL_SELECT_DDCVGA = 6 +DOUT_I2C_CONTROL_DDC_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_TRANSACTION_COUNT' +DOUT_I2C_CONTROL_TRANSACTION_COUNT__enumvalues = { + 0: 'DOUT_I2C_CONTROL_TRANS0', + 1: 'DOUT_I2C_CONTROL_TRANS0_TRANS1', + 2: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', + 3: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', +} +DOUT_I2C_CONTROL_TRANS0 = 0 +DOUT_I2C_CONTROL_TRANS0_TRANS1 = 1 +DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 2 +DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 3 +DOUT_I2C_CONTROL_TRANSACTION_COUNT = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_DBG_REF_SEL' +DOUT_I2C_CONTROL_DBG_REF_SEL__enumvalues = { + 0: 'DOUT_I2C_CONTROL_NORMAL_DEBUG', + 1: 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', +} +DOUT_I2C_CONTROL_NORMAL_DEBUG = 0 +DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 1 +DOUT_I2C_CONTROL_DBG_REF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_SW_PRIORITY' +DOUT_I2C_ARBITRATION_SW_PRIORITY__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', + 1: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', + 2: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', + 3: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', +} +DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0 +DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 1 +DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 2 +DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 3 +DOUT_I2C_ARBITRATION_SW_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO' +DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', + 1: 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', +} +DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0 +DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 1 +DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_ABORT_XFER' +DOUT_I2C_ARBITRATION_ABORT_XFER__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', + 1: 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', +} +DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0 +DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 1 +DOUT_I2C_ARBITRATION_ABORT_XFER = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ' +DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', + 1: 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', +} +DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0 +DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 1 +DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG' +DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', + 1: 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', +} +DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0 +DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 1 +DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ACK' +DOUT_I2C_ACK__enumvalues = { + 0: 'DOUT_I2C_NO_ACK', + 1: 'DOUT_I2C_ACK_TO_CLEAN', +} +DOUT_I2C_NO_ACK = 0 +DOUT_I2C_ACK_TO_CLEAN = 1 +DOUT_I2C_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SPEED_THRESHOLD' +DOUT_I2C_DDC_SPEED_THRESHOLD__enumvalues = { + 0: 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', + 1: 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', + 2: 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', + 3: 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', +} +DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0 +DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 1 +DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 2 +DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 3 +DOUT_I2C_DDC_SPEED_THRESHOLD = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN' +DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', + 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', +} +DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0 +DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 1 +DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL' +DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', + 1: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', +} +DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0 +DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 1 +DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE' +DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', + 1: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', +} +DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0 +DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 1 +DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN' +DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', + 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', +} +DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0 +DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 1 +DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_TRANSACTION_STOP_ON_NACK' +DOUT_I2C_TRANSACTION_STOP_ON_NACK__enumvalues = { + 0: 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', + 1: 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', +} +DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0 +DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 1 +DOUT_I2C_TRANSACTION_STOP_ON_NACK = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DATA_INDEX_WRITE' +DOUT_I2C_DATA_INDEX_WRITE__enumvalues = { + 0: 'DOUT_I2C_DATA__NOT_INDEX_WRITE', + 1: 'DOUT_I2C_DATA__INDEX_WRITE', +} +DOUT_I2C_DATA__NOT_INDEX_WRITE = 0 +DOUT_I2C_DATA__INDEX_WRITE = 1 +DOUT_I2C_DATA_INDEX_WRITE = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET' +DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET__enumvalues = { + 0: 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', + 1: 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', +} +DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0 +DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 1 +DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE' +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__enumvalues = { + 0: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', + 1: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', +} +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0 +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 1 +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'FBC_IDLE_MASK_MASK_BITS' +FBC_IDLE_MASK_MASK_BITS__enumvalues = { + 0: 'FBC_IDLE_MASK_DISP_REG_UPDATE', + 1: 'FBC_IDLE_MASK_RESERVED1', + 2: 'FBC_IDLE_MASK_FBC_GRPH_COMP_EN', + 3: 'FBC_IDLE_MASK_FBC_MIN_COMPRESSION', + 4: 'FBC_IDLE_MASK_FBC_ALPHA_COMP_EN', + 5: 'FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN', + 6: 'FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF', + 7: 'FBC_IDLE_MASK_RESERVED7', + 8: 'FBC_IDLE_MASK_RESERVED8', + 9: 'FBC_IDLE_MASK_RESERVED9', + 10: 'FBC_IDLE_MASK_RESERVED10', + 11: 'FBC_IDLE_MASK_RESERVED11', + 12: 'FBC_IDLE_MASK_RESERVED12', + 13: 'FBC_IDLE_MASK_RESERVED13', + 14: 'FBC_IDLE_MASK_RESERVED14', + 15: 'FBC_IDLE_MASK_RESERVED15', + 16: 'FBC_IDLE_MASK_RESERVED16', + 17: 'FBC_IDLE_MASK_RESERVED17', + 18: 'FBC_IDLE_MASK_RESERVED18', + 19: 'FBC_IDLE_MASK_RESERVED19', + 20: 'FBC_IDLE_MASK_RESERVED20', + 21: 'FBC_IDLE_MASK_RESERVED21', + 22: 'FBC_IDLE_MASK_RESERVED22', + 23: 'FBC_IDLE_MASK_RESERVED23', + 24: 'FBC_IDLE_MASK_MC_HIT_REGION_0', + 25: 'FBC_IDLE_MASK_MC_HIT_REGION_1', + 26: 'FBC_IDLE_MASK_MC_HIT_REGION_2', + 27: 'FBC_IDLE_MASK_MC_HIT_REGION_3', + 28: 'FBC_IDLE_MASK_MC_WRITE', + 29: 'FBC_IDLE_MASK_RESERVED29', + 30: 'FBC_IDLE_MASK_RESERVED30', + 31: 'FBC_IDLE_MASK_RESERVED31', +} +FBC_IDLE_MASK_DISP_REG_UPDATE = 0 +FBC_IDLE_MASK_RESERVED1 = 1 +FBC_IDLE_MASK_FBC_GRPH_COMP_EN = 2 +FBC_IDLE_MASK_FBC_MIN_COMPRESSION = 3 +FBC_IDLE_MASK_FBC_ALPHA_COMP_EN = 4 +FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN = 5 +FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF = 6 +FBC_IDLE_MASK_RESERVED7 = 7 +FBC_IDLE_MASK_RESERVED8 = 8 +FBC_IDLE_MASK_RESERVED9 = 9 +FBC_IDLE_MASK_RESERVED10 = 10 +FBC_IDLE_MASK_RESERVED11 = 11 +FBC_IDLE_MASK_RESERVED12 = 12 +FBC_IDLE_MASK_RESERVED13 = 13 +FBC_IDLE_MASK_RESERVED14 = 14 +FBC_IDLE_MASK_RESERVED15 = 15 +FBC_IDLE_MASK_RESERVED16 = 16 +FBC_IDLE_MASK_RESERVED17 = 17 +FBC_IDLE_MASK_RESERVED18 = 18 +FBC_IDLE_MASK_RESERVED19 = 19 +FBC_IDLE_MASK_RESERVED20 = 20 +FBC_IDLE_MASK_RESERVED21 = 21 +FBC_IDLE_MASK_RESERVED22 = 22 +FBC_IDLE_MASK_RESERVED23 = 23 +FBC_IDLE_MASK_MC_HIT_REGION_0 = 24 +FBC_IDLE_MASK_MC_HIT_REGION_1 = 25 +FBC_IDLE_MASK_MC_HIT_REGION_2 = 26 +FBC_IDLE_MASK_MC_HIT_REGION_3 = 27 +FBC_IDLE_MASK_MC_WRITE = 28 +FBC_IDLE_MASK_RESERVED29 = 29 +FBC_IDLE_MASK_RESERVED30 = 30 +FBC_IDLE_MASK_RESERVED31 = 31 +FBC_IDLE_MASK_MASK_BITS = ctypes.c_uint32 # enum + +# values for enumeration 'DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL' +DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL__enumvalues = { + 0: 'DPCSRX_BPHY_PCS_RX0_CLK', + 1: 'DPCSRX_BPHY_PCS_RX1_CLK', + 2: 'DPCSRX_BPHY_PCS_RX2_CLK', + 3: 'DPCSRX_BPHY_PCS_RX3_CLK', +} +DPCSRX_BPHY_PCS_RX0_CLK = 0 +DPCSRX_BPHY_PCS_RX1_CLK = 1 +DPCSRX_BPHY_PCS_RX2_CLK = 2 +DPCSRX_BPHY_PCS_RX3_CLK = 3 +DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPCSRX_DBG_CFGCLK_SEL' +DPCSRX_DBG_CFGCLK_SEL__enumvalues = { + 0: 'DPCSRX_DBG_CFGCLK_SEL_DC_DPCS_INF', + 1: 'DPCSRX_DBG_CFGCLK_SEL_DPCS_BPHY_INF', + 2: 'DPCSRX_DBG_CFGCLK_SEL_CBUS_SLAVE', + 3: 'DPCSRX_DBG_CFGCLK_SEL_CBUS_MASTER', +} +DPCSRX_DBG_CFGCLK_SEL_DC_DPCS_INF = 0 +DPCSRX_DBG_CFGCLK_SEL_DPCS_BPHY_INF = 1 +DPCSRX_DBG_CFGCLK_SEL_CBUS_SLAVE = 2 +DPCSRX_DBG_CFGCLK_SEL_CBUS_MASTER = 3 +DPCSRX_DBG_CFGCLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPCSRX_RX_SYMCLK_SEL' +DPCSRX_RX_SYMCLK_SEL__enumvalues = { + 0: 'DPCSRX_DBG_RX_SYMCLK_SEL_OUT0', + 1: 'DPCSRX_DBG_RX_SYMCLK_SEL_OUT1', + 2: 'DPCSRX_DBG_RX_SYMCLK_SEL_INT', +} +DPCSRX_DBG_RX_SYMCLK_SEL_OUT0 = 0 +DPCSRX_DBG_RX_SYMCLK_SEL_OUT1 = 1 +DPCSRX_DBG_RX_SYMCLK_SEL_INT = 2 +DPCSRX_RX_SYMCLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPCSTX_DBG_CFGCLK_SEL' +DPCSTX_DBG_CFGCLK_SEL__enumvalues = { + 0: 'DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF', + 1: 'DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF', + 2: 'DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE', + 3: 'DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER', +} +DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF = 0 +DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF = 1 +DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE = 2 +DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER = 3 +DPCSTX_DBG_CFGCLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPCSTX_TX_SYMCLK_SEL' +DPCSTX_TX_SYMCLK_SEL__enumvalues = { + 0: 'DPCSTX_DBG_TX_SYMCLK_SEL_IN0', + 1: 'DPCSTX_DBG_TX_SYMCLK_SEL_IN1', + 2: 'DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR', +} +DPCSTX_DBG_TX_SYMCLK_SEL_IN0 = 0 +DPCSTX_DBG_TX_SYMCLK_SEL_IN1 = 1 +DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR = 2 +DPCSTX_TX_SYMCLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPCSTX_TX_SYMCLK_DIV2_SEL' +DPCSTX_TX_SYMCLK_DIV2_SEL__enumvalues = { + 0: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0', + 1: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1', + 2: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2', + 3: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3', + 4: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD', + 5: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT', +} +DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0 = 0 +DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1 = 1 +DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2 = 2 +DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3 = 3 +DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD = 4 +DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT = 5 +DPCSTX_TX_SYMCLK_DIV2_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SurfaceNumber' +SurfaceNumber__enumvalues = { + 0: 'NUMBER_UNORM', + 1: 'NUMBER_SNORM', + 2: 'NUMBER_USCALED', + 3: 'NUMBER_SSCALED', + 4: 'NUMBER_UINT', + 5: 'NUMBER_SINT', + 6: 'NUMBER_SRGB', + 7: 'NUMBER_FLOAT', +} +NUMBER_UNORM = 0 +NUMBER_SNORM = 1 +NUMBER_USCALED = 2 +NUMBER_SSCALED = 3 +NUMBER_UINT = 4 +NUMBER_SINT = 5 +NUMBER_SRGB = 6 +NUMBER_FLOAT = 7 +SurfaceNumber = ctypes.c_uint32 # enum + +# values for enumeration 'SurfaceSwap' +SurfaceSwap__enumvalues = { + 0: 'SWAP_STD', + 1: 'SWAP_ALT', + 2: 'SWAP_STD_REV', + 3: 'SWAP_ALT_REV', +} +SWAP_STD = 0 +SWAP_ALT = 1 +SWAP_STD_REV = 2 +SWAP_ALT_REV = 3 +SurfaceSwap = ctypes.c_uint32 # enum + +# values for enumeration 'CBMode' +CBMode__enumvalues = { + 0: 'CB_DISABLE', + 1: 'CB_NORMAL', + 2: 'CB_ELIMINATE_FAST_CLEAR', + 3: 'CB_RESOLVE', + 4: 'CB_DECOMPRESS', + 5: 'CB_FMASK_DECOMPRESS', + 6: 'CB_DCC_DECOMPRESS', +} +CB_DISABLE = 0 +CB_NORMAL = 1 +CB_ELIMINATE_FAST_CLEAR = 2 +CB_RESOLVE = 3 +CB_DECOMPRESS = 4 +CB_FMASK_DECOMPRESS = 5 +CB_DCC_DECOMPRESS = 6 +CBMode = ctypes.c_uint32 # enum + +# values for enumeration 'RoundMode' +RoundMode__enumvalues = { + 0: 'ROUND_BY_HALF', + 1: 'ROUND_TRUNCATE', +} +ROUND_BY_HALF = 0 +ROUND_TRUNCATE = 1 +RoundMode = ctypes.c_uint32 # enum + +# values for enumeration 'SourceFormat' +SourceFormat__enumvalues = { + 0: 'EXPORT_4C_32BPC', + 1: 'EXPORT_4C_16BPC', + 2: 'EXPORT_2C_32BPC_GR', + 3: 'EXPORT_2C_32BPC_AR', +} +EXPORT_4C_32BPC = 0 +EXPORT_4C_16BPC = 1 +EXPORT_2C_32BPC_GR = 2 +EXPORT_2C_32BPC_AR = 3 +SourceFormat = ctypes.c_uint32 # enum + +# values for enumeration 'BlendOp' +BlendOp__enumvalues = { + 0: 'BLEND_ZERO', + 1: 'BLEND_ONE', + 2: 'BLEND_SRC_COLOR', + 3: 'BLEND_ONE_MINUS_SRC_COLOR', + 4: 'BLEND_SRC_ALPHA', + 5: 'BLEND_ONE_MINUS_SRC_ALPHA', + 6: 'BLEND_DST_ALPHA', + 7: 'BLEND_ONE_MINUS_DST_ALPHA', + 8: 'BLEND_DST_COLOR', + 9: 'BLEND_ONE_MINUS_DST_COLOR', + 10: 'BLEND_SRC_ALPHA_SATURATE', + 11: 'BLEND_BOTH_SRC_ALPHA', + 12: 'BLEND_BOTH_INV_SRC_ALPHA', + 13: 'BLEND_CONSTANT_COLOR', + 14: 'BLEND_ONE_MINUS_CONSTANT_COLOR', + 15: 'BLEND_SRC1_COLOR', + 16: 'BLEND_INV_SRC1_COLOR', + 17: 'BLEND_SRC1_ALPHA', + 18: 'BLEND_INV_SRC1_ALPHA', + 19: 'BLEND_CONSTANT_ALPHA', + 20: 'BLEND_ONE_MINUS_CONSTANT_ALPHA', +} +BLEND_ZERO = 0 +BLEND_ONE = 1 +BLEND_SRC_COLOR = 2 +BLEND_ONE_MINUS_SRC_COLOR = 3 +BLEND_SRC_ALPHA = 4 +BLEND_ONE_MINUS_SRC_ALPHA = 5 +BLEND_DST_ALPHA = 6 +BLEND_ONE_MINUS_DST_ALPHA = 7 +BLEND_DST_COLOR = 8 +BLEND_ONE_MINUS_DST_COLOR = 9 +BLEND_SRC_ALPHA_SATURATE = 10 +BLEND_BOTH_SRC_ALPHA = 11 +BLEND_BOTH_INV_SRC_ALPHA = 12 +BLEND_CONSTANT_COLOR = 13 +BLEND_ONE_MINUS_CONSTANT_COLOR = 14 +BLEND_SRC1_COLOR = 15 +BLEND_INV_SRC1_COLOR = 16 +BLEND_SRC1_ALPHA = 17 +BLEND_INV_SRC1_ALPHA = 18 +BLEND_CONSTANT_ALPHA = 19 +BLEND_ONE_MINUS_CONSTANT_ALPHA = 20 +BlendOp = ctypes.c_uint32 # enum +GL__ZERO = BLEND_ZERO # macro +GL__ONE = BLEND_ONE # macro +GL__SRC_COLOR = BLEND_SRC_COLOR # macro +GL__ONE_MINUS_SRC_COLOR = BLEND_ONE_MINUS_SRC_COLOR # macro +GL__DST_COLOR = BLEND_DST_COLOR # macro +GL__ONE_MINUS_DST_COLOR = BLEND_ONE_MINUS_DST_COLOR # macro +GL__SRC_ALPHA = BLEND_SRC_ALPHA # macro +GL__ONE_MINUS_SRC_ALPHA = BLEND_ONE_MINUS_SRC_ALPHA # macro +GL__DST_ALPHA = BLEND_DST_ALPHA # macro +GL__ONE_MINUS_DST_ALPHA = BLEND_ONE_MINUS_DST_ALPHA # macro +GL__SRC_ALPHA_SATURATE = BLEND_SRC_ALPHA_SATURATE # macro +GL__CONSTANT_COLOR = BLEND_CONSTANT_COLOR # macro +GL__ONE_MINUS_CONSTANT_COLOR = BLEND_ONE_MINUS_CONSTANT_COLOR # macro +GL__CONSTANT_ALPHA = BLEND_CONSTANT_ALPHA # macro +GL__ONE_MINUS_CONSTANT_ALPHA = BLEND_ONE_MINUS_CONSTANT_ALPHA # macro + +# values for enumeration 'CombFunc' +CombFunc__enumvalues = { + 0: 'COMB_DST_PLUS_SRC', + 1: 'COMB_SRC_MINUS_DST', + 2: 'COMB_MIN_DST_SRC', + 3: 'COMB_MAX_DST_SRC', + 4: 'COMB_DST_MINUS_SRC', +} +COMB_DST_PLUS_SRC = 0 +COMB_SRC_MINUS_DST = 1 +COMB_MIN_DST_SRC = 2 +COMB_MAX_DST_SRC = 3 +COMB_DST_MINUS_SRC = 4 +CombFunc = ctypes.c_uint32 # enum + +# values for enumeration 'BlendOpt' +BlendOpt__enumvalues = { + 0: 'FORCE_OPT_AUTO', + 1: 'FORCE_OPT_DISABLE', + 2: 'FORCE_OPT_ENABLE_IF_SRC_A_0', + 3: 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', + 4: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', + 5: 'FORCE_OPT_ENABLE_IF_SRC_A_1', + 6: 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', + 7: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', +} +FORCE_OPT_AUTO = 0 +FORCE_OPT_DISABLE = 1 +FORCE_OPT_ENABLE_IF_SRC_A_0 = 2 +FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 3 +FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 4 +FORCE_OPT_ENABLE_IF_SRC_A_1 = 5 +FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 6 +FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 7 +BlendOpt = ctypes.c_uint32 # enum + +# values for enumeration 'CmaskCode' +CmaskCode__enumvalues = { + 0: 'CMASK_CLR00_F0', + 1: 'CMASK_CLR00_F1', + 2: 'CMASK_CLR00_F2', + 3: 'CMASK_CLR00_FX', + 4: 'CMASK_CLR01_F0', + 5: 'CMASK_CLR01_F1', + 6: 'CMASK_CLR01_F2', + 7: 'CMASK_CLR01_FX', + 8: 'CMASK_CLR10_F0', + 9: 'CMASK_CLR10_F1', + 10: 'CMASK_CLR10_F2', + 11: 'CMASK_CLR10_FX', + 12: 'CMASK_CLR11_F0', + 13: 'CMASK_CLR11_F1', + 14: 'CMASK_CLR11_F2', + 15: 'CMASK_CLR11_FX', +} +CMASK_CLR00_F0 = 0 +CMASK_CLR00_F1 = 1 +CMASK_CLR00_F2 = 2 +CMASK_CLR00_FX = 3 +CMASK_CLR01_F0 = 4 +CMASK_CLR01_F1 = 5 +CMASK_CLR01_F2 = 6 +CMASK_CLR01_FX = 7 +CMASK_CLR10_F0 = 8 +CMASK_CLR10_F1 = 9 +CMASK_CLR10_F2 = 10 +CMASK_CLR10_FX = 11 +CMASK_CLR11_F0 = 12 +CMASK_CLR11_F1 = 13 +CMASK_CLR11_F2 = 14 +CMASK_CLR11_FX = 15 +CmaskCode = ctypes.c_uint32 # enum + +# values for enumeration 'CmaskAddr' +CmaskAddr__enumvalues = { + 0: 'CMASK_ADDR_TILED', + 1: 'CMASK_ADDR_LINEAR', + 2: 'CMASK_ADDR_COMPATIBLE', +} +CMASK_ADDR_TILED = 0 +CMASK_ADDR_LINEAR = 1 +CMASK_ADDR_COMPATIBLE = 2 +CmaskAddr = ctypes.c_uint32 # enum + +# values for enumeration 'MemArbMode' +MemArbMode__enumvalues = { + 0: 'MEM_ARB_MODE_FIXED', + 1: 'MEM_ARB_MODE_AGE', + 2: 'MEM_ARB_MODE_WEIGHT', + 3: 'MEM_ARB_MODE_BOTH', +} +MEM_ARB_MODE_FIXED = 0 +MEM_ARB_MODE_AGE = 1 +MEM_ARB_MODE_WEIGHT = 2 +MEM_ARB_MODE_BOTH = 3 +MemArbMode = ctypes.c_uint32 # enum + +# values for enumeration 'CBPerfSel' +CBPerfSel__enumvalues = { + 0: 'CB_PERF_SEL_NONE', + 1: 'CB_PERF_SEL_BUSY', + 2: 'CB_PERF_SEL_CORE_SCLK_VLD', + 3: 'CB_PERF_SEL_REG_SCLK0_VLD', + 4: 'CB_PERF_SEL_REG_SCLK1_VLD', + 5: 'CB_PERF_SEL_DRAWN_QUAD', + 6: 'CB_PERF_SEL_DRAWN_PIXEL', + 7: 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', + 8: 'CB_PERF_SEL_DRAWN_TILE', + 9: 'CB_PERF_SEL_DB_CB_TILE_VALID_READY', + 10: 'CB_PERF_SEL_DB_CB_TILE_VALID_READYB', + 11: 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READY', + 12: 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB', + 13: 'CB_PERF_SEL_CM_FC_TILE_VALID_READY', + 14: 'CB_PERF_SEL_CM_FC_TILE_VALID_READYB', + 15: 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READY', + 16: 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB', + 17: 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY', + 18: 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB', + 19: 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READY', + 20: 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB', + 21: 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY', + 22: 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB', + 23: 'CB_PERF_SEL_LQUAD_NO_TILE', + 24: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R', + 25: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR', + 26: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR', + 27: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR', + 28: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR', + 29: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR', + 30: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR', + 31: 'CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT', + 32: 'CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID', + 33: 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK', + 34: 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK', + 35: 'CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL', + 36: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY', + 37: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB', + 38: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY', + 39: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB', + 40: 'CB_PERF_SEL_FOP_IN_VALID_READY', + 41: 'CB_PERF_SEL_FOP_IN_VALID_READYB', + 42: 'CB_PERF_SEL_FOP_IN_VALIDB_READY', + 43: 'CB_PERF_SEL_FOP_IN_VALIDB_READYB', + 44: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY', + 45: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB', + 46: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY', + 47: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB', + 48: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY', + 49: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB', + 50: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY', + 51: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB', + 52: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY', + 53: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB', + 54: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY', + 55: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB', + 56: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY', + 57: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB', + 58: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY', + 59: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB', + 60: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY', + 61: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB', + 62: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY', + 63: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB', + 64: 'CB_PERF_SEL_CC_BC_CS_FRAG_VALID', + 65: 'CB_PERF_SEL_CM_CACHE_HIT', + 66: 'CB_PERF_SEL_CM_CACHE_TAG_MISS', + 67: 'CB_PERF_SEL_CM_CACHE_SECTOR_MISS', + 68: 'CB_PERF_SEL_CM_CACHE_REEVICTION_STALL', + 69: 'CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 70: 'CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL', + 71: 'CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 72: 'CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL', + 73: 'CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL', + 74: 'CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL', + 75: 'CB_PERF_SEL_CM_CACHE_STALL', + 76: 'CB_PERF_SEL_CM_CACHE_FLUSH', + 77: 'CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED', + 78: 'CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED', + 79: 'CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED', + 80: 'CB_PERF_SEL_FC_CACHE_HIT', + 81: 'CB_PERF_SEL_FC_CACHE_TAG_MISS', + 82: 'CB_PERF_SEL_FC_CACHE_SECTOR_MISS', + 83: 'CB_PERF_SEL_FC_CACHE_REEVICTION_STALL', + 84: 'CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 85: 'CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL', + 86: 'CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 87: 'CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL', + 88: 'CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL', + 89: 'CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL', + 90: 'CB_PERF_SEL_FC_CACHE_STALL', + 91: 'CB_PERF_SEL_FC_CACHE_FLUSH', + 92: 'CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED', + 93: 'CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED', + 94: 'CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED', + 95: 'CB_PERF_SEL_CC_CACHE_HIT', + 96: 'CB_PERF_SEL_CC_CACHE_TAG_MISS', + 97: 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', + 98: 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', + 99: 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 100: 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', + 101: 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 102: 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', + 103: 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', + 104: 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', + 105: 'CB_PERF_SEL_CC_CACHE_STALL', + 106: 'CB_PERF_SEL_CC_CACHE_FLUSH', + 107: 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', + 108: 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', + 109: 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', + 110: 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', + 111: 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', + 112: 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY', + 113: 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB', + 114: 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY', + 115: 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB', + 116: 'CB_PERF_SEL_CM_MC_WRITE_REQUEST', + 117: 'CB_PERF_SEL_FC_MC_WRITE_REQUEST', + 118: 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', + 119: 'CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT', + 120: 'CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT', + 121: 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', + 122: 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY', + 123: 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB', + 124: 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY', + 125: 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB', + 126: 'CB_PERF_SEL_CM_MC_READ_REQUEST', + 127: 'CB_PERF_SEL_FC_MC_READ_REQUEST', + 128: 'CB_PERF_SEL_CC_MC_READ_REQUEST', + 129: 'CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT', + 130: 'CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT', + 131: 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', + 132: 'CB_PERF_SEL_CM_TQ_FULL', + 133: 'CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL', + 134: 'CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL', + 135: 'CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL', + 136: 'CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL', + 137: 'CB_PERF_SEL_FOP_FMASK_RAW_STALL', + 138: 'CB_PERF_SEL_FOP_FMASK_BYPASS_STALL', + 139: 'CB_PERF_SEL_CC_SF_FULL', + 140: 'CB_PERF_SEL_CC_RB_FULL', + 141: 'CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL', + 142: 'CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL', + 143: 'CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL', + 144: 'CB_PERF_SEL_EVENT', + 145: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', + 146: 'CB_PERF_SEL_EVENT_CONTEXT_DONE', + 147: 'CB_PERF_SEL_EVENT_CACHE_FLUSH', + 148: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', + 149: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', + 150: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', + 151: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', + 152: 'CB_PERF_SEL_CC_SURFACE_SYNC', + 153: 'CB_PERF_SEL_CMASK_READ_DATA_0xC', + 154: 'CB_PERF_SEL_CMASK_READ_DATA_0xD', + 155: 'CB_PERF_SEL_CMASK_READ_DATA_0xE', + 156: 'CB_PERF_SEL_CMASK_READ_DATA_0xF', + 157: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xC', + 158: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xD', + 159: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xE', + 160: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xF', + 161: 'CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT', + 162: 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', + 163: 'CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT', + 164: 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE', + 165: 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE', + 166: 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE', + 167: 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE', + 168: 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE', + 169: 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE', + 170: 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE', + 171: 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE', + 172: 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE', + 173: 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE', + 174: 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE', + 175: 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE', + 176: 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE', + 177: 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE', + 178: 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE', + 179: 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE', + 180: 'CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT', + 181: 'CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS', + 182: 'CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS', + 183: 'CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS', + 184: 'CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS', + 185: 'CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS', + 186: 'CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS', + 187: 'CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT', + 188: 'CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS', + 189: 'CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS', + 190: 'CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS', + 191: 'CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS', + 192: 'CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS', + 193: 'CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS', + 194: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_0', + 195: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_1', + 196: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_2', + 197: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_3', + 198: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_4', + 199: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_5', + 200: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_6', + 201: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_7', + 202: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0', + 203: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1', + 204: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2', + 205: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3', + 206: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4', + 207: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5', + 208: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6', + 209: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7', + 210: 'CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST', + 211: 'CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS', + 212: 'CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS', + 213: 'CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', + 214: 'CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', + 215: 'CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED', + 216: 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', + 217: 'CB_PERF_SEL_DRAWN_BUSY', + 218: 'CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY', + 219: 'CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY', + 220: 'CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY', + 221: 'CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY', + 222: 'CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED', + 223: 'CB_PERF_SEL_FC_SEQUENCER_CLEAR', + 224: 'CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR', + 225: 'CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS', + 226: 'CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE', + 227: 'CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL', + 228: 'CB_PERF_SEL_FC_DOC_IS_STALLED', + 229: 'CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED', + 230: 'CB_PERF_SEL_FC_DOC_MRTS_COMBINED', + 231: 'CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS', + 232: 'CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT', + 233: 'CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS', + 234: 'CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT', + 235: 'CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL', + 236: 'CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR', + 237: 'CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS', + 238: 'CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS', + 239: 'CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS', + 240: 'CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS', + 241: 'CB_PERF_SEL_FC_DCC_CACHE_HIT', + 242: 'CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS', + 243: 'CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS', + 244: 'CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL', + 245: 'CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 246: 'CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', + 247: 'CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 248: 'CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL', + 249: 'CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL', + 250: 'CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL', + 251: 'CB_PERF_SEL_FC_DCC_CACHE_STALL', + 252: 'CB_PERF_SEL_FC_DCC_CACHE_FLUSH', + 253: 'CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED', + 254: 'CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED', + 255: 'CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED', + 256: 'CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT', + 257: 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST', + 258: 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT', + 259: 'CB_PERF_SEL_FC_MC_DCC_READ_REQUEST', + 260: 'CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT', + 261: 'CB_PERF_SEL_CC_DCC_RDREQ_STALL', + 262: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN', + 263: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT', + 264: 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN', + 265: 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT', + 266: 'CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR', + 267: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1', + 268: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2', + 269: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', + 270: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1', + 271: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1', + 272: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2', + 273: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1', + 274: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', + 275: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', + 276: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1', + 277: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2', + 278: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2', + 279: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2', + 280: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', + 281: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1', + 282: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1', + 283: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2', + 284: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3', + 285: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4', + 286: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1', + 287: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2', + 288: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3', + 289: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4', + 290: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1', + 291: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2', + 292: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3', + 293: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4', + 294: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1', + 295: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2', + 296: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3', + 297: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1', + 298: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2', + 299: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3', + 300: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4', + 301: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1', + 302: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2', + 303: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3', + 304: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4', + 305: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1', + 306: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2', + 307: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3', + 308: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4', + 309: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1', + 310: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2', + 311: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3', + 312: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1', + 313: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1', + 314: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1', + 315: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1', + 316: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1', + 317: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1', + 318: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1', + 319: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1', + 320: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2', + 321: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2', + 322: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2', + 323: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2', + 324: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2', + 325: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2', + 326: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2', + 327: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1', + 328: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1', + 329: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1', + 330: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1', + 331: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2', + 332: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2', + 333: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2', + 334: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2', + 335: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2', + 336: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2', + 337: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2', + 338: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1', + 339: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1', + 340: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1', + 341: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1', + 342: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1', + 343: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2', + 344: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3', + 345: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4', + 346: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5', + 347: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6', + 348: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0', + 349: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1', + 350: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1', + 351: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2', + 352: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3', + 353: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4', + 354: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5', + 355: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0', + 356: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1', + 357: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1', + 358: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1', + 359: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1', + 360: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1', + 361: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1', + 362: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1', + 363: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1', + 364: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1', + 365: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2', + 366: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2', + 367: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2', + 368: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2', + 369: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2', + 370: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2', + 371: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2', + 372: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1', + 373: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2', + 374: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3', + 375: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4', + 376: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5', + 377: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6', + 378: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7', + 379: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED', + 380: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1', + 381: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1', + 382: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2', + 383: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3', + 384: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1', + 385: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2', + 386: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3', + 387: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4', + 388: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5', + 389: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1', + 390: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2', + 391: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3', + 392: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4', + 393: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5', + 394: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6', + 395: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7', + 396: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH', + 397: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT', + 398: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT', + 399: 'CB_PERF_SEL_RBP_SPLIT_MICROTILE', + 400: 'CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK', + 401: 'CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK', + 402: 'CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING', + 403: 'CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS', + 404: 'CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD', +} +CB_PERF_SEL_NONE = 0 +CB_PERF_SEL_BUSY = 1 +CB_PERF_SEL_CORE_SCLK_VLD = 2 +CB_PERF_SEL_REG_SCLK0_VLD = 3 +CB_PERF_SEL_REG_SCLK1_VLD = 4 +CB_PERF_SEL_DRAWN_QUAD = 5 +CB_PERF_SEL_DRAWN_PIXEL = 6 +CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 7 +CB_PERF_SEL_DRAWN_TILE = 8 +CB_PERF_SEL_DB_CB_TILE_VALID_READY = 9 +CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 10 +CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 11 +CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 12 +CB_PERF_SEL_CM_FC_TILE_VALID_READY = 13 +CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 14 +CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 15 +CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 16 +CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 17 +CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 18 +CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 19 +CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 20 +CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 21 +CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 22 +CB_PERF_SEL_LQUAD_NO_TILE = 23 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 24 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 25 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 26 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 27 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 28 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 29 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR = 30 +CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 31 +CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 32 +CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK = 33 +CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 34 +CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 35 +CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 36 +CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 37 +CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 38 +CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 39 +CB_PERF_SEL_FOP_IN_VALID_READY = 40 +CB_PERF_SEL_FOP_IN_VALID_READYB = 41 +CB_PERF_SEL_FOP_IN_VALIDB_READY = 42 +CB_PERF_SEL_FOP_IN_VALIDB_READYB = 43 +CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 44 +CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 45 +CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 46 +CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 47 +CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 48 +CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 49 +CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 50 +CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 51 +CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 52 +CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 53 +CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 54 +CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 55 +CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 56 +CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 57 +CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 58 +CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 59 +CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 60 +CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 61 +CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 62 +CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 63 +CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 64 +CB_PERF_SEL_CM_CACHE_HIT = 65 +CB_PERF_SEL_CM_CACHE_TAG_MISS = 66 +CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 67 +CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 68 +CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 69 +CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 70 +CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 71 +CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 72 +CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 73 +CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 74 +CB_PERF_SEL_CM_CACHE_STALL = 75 +CB_PERF_SEL_CM_CACHE_FLUSH = 76 +CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 77 +CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 78 +CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 79 +CB_PERF_SEL_FC_CACHE_HIT = 80 +CB_PERF_SEL_FC_CACHE_TAG_MISS = 81 +CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 82 +CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 83 +CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 84 +CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 85 +CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 86 +CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 87 +CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 88 +CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 89 +CB_PERF_SEL_FC_CACHE_STALL = 90 +CB_PERF_SEL_FC_CACHE_FLUSH = 91 +CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 92 +CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 93 +CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 94 +CB_PERF_SEL_CC_CACHE_HIT = 95 +CB_PERF_SEL_CC_CACHE_TAG_MISS = 96 +CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 97 +CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 98 +CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 99 +CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 100 +CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 101 +CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 102 +CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 103 +CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 104 +CB_PERF_SEL_CC_CACHE_STALL = 105 +CB_PERF_SEL_CC_CACHE_FLUSH = 106 +CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 107 +CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 108 +CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 109 +CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 110 +CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 111 +CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 112 +CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 113 +CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 114 +CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 115 +CB_PERF_SEL_CM_MC_WRITE_REQUEST = 116 +CB_PERF_SEL_FC_MC_WRITE_REQUEST = 117 +CB_PERF_SEL_CC_MC_WRITE_REQUEST = 118 +CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 119 +CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 120 +CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 121 +CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 122 +CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 123 +CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 124 +CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 125 +CB_PERF_SEL_CM_MC_READ_REQUEST = 126 +CB_PERF_SEL_FC_MC_READ_REQUEST = 127 +CB_PERF_SEL_CC_MC_READ_REQUEST = 128 +CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 129 +CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 130 +CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 131 +CB_PERF_SEL_CM_TQ_FULL = 132 +CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 133 +CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 134 +CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 135 +CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 136 +CB_PERF_SEL_FOP_FMASK_RAW_STALL = 137 +CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 138 +CB_PERF_SEL_CC_SF_FULL = 139 +CB_PERF_SEL_CC_RB_FULL = 140 +CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 141 +CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 142 +CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 143 +CB_PERF_SEL_EVENT = 144 +CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 145 +CB_PERF_SEL_EVENT_CONTEXT_DONE = 146 +CB_PERF_SEL_EVENT_CACHE_FLUSH = 147 +CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 148 +CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 149 +CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 150 +CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 151 +CB_PERF_SEL_CC_SURFACE_SYNC = 152 +CB_PERF_SEL_CMASK_READ_DATA_0xC = 153 +CB_PERF_SEL_CMASK_READ_DATA_0xD = 154 +CB_PERF_SEL_CMASK_READ_DATA_0xE = 155 +CB_PERF_SEL_CMASK_READ_DATA_0xF = 156 +CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 157 +CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 158 +CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 159 +CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 160 +CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 161 +CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 162 +CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 163 +CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 164 +CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 165 +CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 166 +CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 167 +CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 168 +CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 169 +CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 170 +CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 171 +CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 172 +CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 173 +CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 174 +CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 175 +CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 176 +CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 177 +CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 178 +CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 179 +CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 180 +CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 181 +CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 182 +CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 183 +CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 184 +CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 185 +CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 186 +CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 187 +CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 188 +CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 189 +CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 190 +CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 191 +CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 192 +CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 193 +CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 194 +CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 195 +CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 196 +CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 197 +CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 198 +CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 199 +CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 200 +CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 201 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 202 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 203 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 204 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 205 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 206 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 207 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 208 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 209 +CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 210 +CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 211 +CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 212 +CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 213 +CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 214 +CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 215 +CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 216 +CB_PERF_SEL_DRAWN_BUSY = 217 +CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 218 +CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 219 +CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 220 +CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 221 +CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED = 222 +CB_PERF_SEL_FC_SEQUENCER_CLEAR = 223 +CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 224 +CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 225 +CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE = 226 +CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL = 227 +CB_PERF_SEL_FC_DOC_IS_STALLED = 228 +CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED = 229 +CB_PERF_SEL_FC_DOC_MRTS_COMBINED = 230 +CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS = 231 +CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT = 232 +CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS = 233 +CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT = 234 +CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL = 235 +CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR = 236 +CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS = 237 +CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS = 238 +CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS = 239 +CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS = 240 +CB_PERF_SEL_FC_DCC_CACHE_HIT = 241 +CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS = 242 +CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS = 243 +CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL = 244 +CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 245 +CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 246 +CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 247 +CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL = 248 +CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL = 249 +CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL = 250 +CB_PERF_SEL_FC_DCC_CACHE_STALL = 251 +CB_PERF_SEL_FC_DCC_CACHE_FLUSH = 252 +CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED = 253 +CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED = 254 +CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 255 +CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT = 256 +CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST = 257 +CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT = 258 +CB_PERF_SEL_FC_MC_DCC_READ_REQUEST = 259 +CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT = 260 +CB_PERF_SEL_CC_DCC_RDREQ_STALL = 261 +CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN = 262 +CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT = 263 +CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN = 264 +CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT = 265 +CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR = 266 +CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1 = 267 +CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2 = 268 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 269 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1 = 270 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1 = 271 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2 = 272 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1 = 273 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 274 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 275 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1 = 276 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2 = 277 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2 = 278 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2 = 279 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 280 +CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1 = 281 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1 = 282 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2 = 283 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3 = 284 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4 = 285 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1 = 286 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2 = 287 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3 = 288 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4 = 289 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1 = 290 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2 = 291 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3 = 292 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4 = 293 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1 = 294 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2 = 295 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3 = 296 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1 = 297 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2 = 298 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3 = 299 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4 = 300 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1 = 301 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2 = 302 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3 = 303 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4 = 304 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1 = 305 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2 = 306 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3 = 307 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4 = 308 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1 = 309 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2 = 310 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3 = 311 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1 = 312 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1 = 313 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1 = 314 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1 = 315 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1 = 316 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1 = 317 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1 = 318 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1 = 319 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2 = 320 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2 = 321 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2 = 322 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2 = 323 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2 = 324 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2 = 325 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2 = 326 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1 = 327 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1 = 328 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1 = 329 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1 = 330 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2 = 331 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2 = 332 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2 = 333 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2 = 334 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 335 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2 = 336 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2 = 337 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 338 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1 = 339 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1 = 340 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1 = 341 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1 = 342 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2 = 343 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3 = 344 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4 = 345 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5 = 346 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6 = 347 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0 = 348 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1 = 349 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1 = 350 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2 = 351 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3 = 352 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4 = 353 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5 = 354 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0 = 355 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1 = 356 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1 = 357 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1 = 358 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1 = 359 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1 = 360 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1 = 361 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1 = 362 +CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1 = 363 +CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1 = 364 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2 = 365 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2 = 366 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2 = 367 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2 = 368 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2 = 369 +CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2 = 370 +CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2 = 371 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1 = 372 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2 = 373 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3 = 374 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4 = 375 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5 = 376 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6 = 377 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7 = 378 +CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED = 379 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1 = 380 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1 = 381 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2 = 382 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3 = 383 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1 = 384 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2 = 385 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3 = 386 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4 = 387 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5 = 388 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1 = 389 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2 = 390 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3 = 391 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4 = 392 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5 = 393 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6 = 394 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7 = 395 +CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 396 +CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 397 +CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 398 +CB_PERF_SEL_RBP_SPLIT_MICROTILE = 399 +CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK = 400 +CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK = 401 +CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING = 402 +CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS = 403 +CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD = 404 +CBPerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'CBPerfOpFilterSel' +CBPerfOpFilterSel__enumvalues = { + 0: 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', + 1: 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', + 2: 'CB_PERF_OP_FILTER_SEL_RESOLVE', + 3: 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', + 4: 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', + 5: 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', +} +CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0 +CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 1 +CB_PERF_OP_FILTER_SEL_RESOLVE = 2 +CB_PERF_OP_FILTER_SEL_DECOMPRESS = 3 +CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 4 +CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 5 +CBPerfOpFilterSel = ctypes.c_uint32 # enum + +# values for enumeration 'CBPerfClearFilterSel' +CBPerfClearFilterSel__enumvalues = { + 0: 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', + 1: 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', +} +CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0 +CB_PERF_CLEAR_FILTER_SEL_CLEAR = 1 +CBPerfClearFilterSel = ctypes.c_uint32 # enum + +# values for enumeration 'TC_OP_MASKS' +TC_OP_MASKS__enumvalues = { + 8: 'TC_OP_MASK_FLUSH_DENROM', + 32: 'TC_OP_MASK_64', + 64: 'TC_OP_MASK_NO_RTN', +} +TC_OP_MASK_FLUSH_DENROM = 8 +TC_OP_MASK_64 = 32 +TC_OP_MASK_NO_RTN = 64 +TC_OP_MASKS = ctypes.c_uint32 # enum + +# values for enumeration 'TC_OP' +TC_OP__enumvalues = { + 0: 'TC_OP_READ', + 1: 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', + 2: 'TC_OP_ATOMIC_FMIN_RTN_32', + 3: 'TC_OP_ATOMIC_FMAX_RTN_32', + 4: 'TC_OP_RESERVED_FOP_RTN_32_0', + 5: 'TC_OP_RESERVED_FOP_RTN_32_1', + 6: 'TC_OP_RESERVED_FOP_RTN_32_2', + 7: 'TC_OP_ATOMIC_SWAP_RTN_32', + 8: 'TC_OP_ATOMIC_CMPSWAP_RTN_32', + 9: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 10: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 11: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 12: 'TC_OP_PROBE_FILTER', + 13: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1', + 14: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 15: 'TC_OP_ATOMIC_ADD_RTN_32', + 16: 'TC_OP_ATOMIC_SUB_RTN_32', + 17: 'TC_OP_ATOMIC_SMIN_RTN_32', + 18: 'TC_OP_ATOMIC_UMIN_RTN_32', + 19: 'TC_OP_ATOMIC_SMAX_RTN_32', + 20: 'TC_OP_ATOMIC_UMAX_RTN_32', + 21: 'TC_OP_ATOMIC_AND_RTN_32', + 22: 'TC_OP_ATOMIC_OR_RTN_32', + 23: 'TC_OP_ATOMIC_XOR_RTN_32', + 24: 'TC_OP_ATOMIC_INC_RTN_32', + 25: 'TC_OP_ATOMIC_DEC_RTN_32', + 26: 'TC_OP_WBINVL1_VOL', + 27: 'TC_OP_WBINVL1_SD', + 28: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', + 29: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', + 30: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', + 31: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', + 32: 'TC_OP_WRITE', + 33: 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', + 34: 'TC_OP_ATOMIC_FMIN_RTN_64', + 35: 'TC_OP_ATOMIC_FMAX_RTN_64', + 36: 'TC_OP_RESERVED_FOP_RTN_64_0', + 37: 'TC_OP_RESERVED_FOP_RTN_64_1', + 38: 'TC_OP_RESERVED_FOP_RTN_64_2', + 39: 'TC_OP_ATOMIC_SWAP_RTN_64', + 40: 'TC_OP_ATOMIC_CMPSWAP_RTN_64', + 41: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 42: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 43: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 44: 'TC_OP_WBINVL2_SD', + 45: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', + 46: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', + 47: 'TC_OP_ATOMIC_ADD_RTN_64', + 48: 'TC_OP_ATOMIC_SUB_RTN_64', + 49: 'TC_OP_ATOMIC_SMIN_RTN_64', + 50: 'TC_OP_ATOMIC_UMIN_RTN_64', + 51: 'TC_OP_ATOMIC_SMAX_RTN_64', + 52: 'TC_OP_ATOMIC_UMAX_RTN_64', + 53: 'TC_OP_ATOMIC_AND_RTN_64', + 54: 'TC_OP_ATOMIC_OR_RTN_64', + 55: 'TC_OP_ATOMIC_XOR_RTN_64', + 56: 'TC_OP_ATOMIC_INC_RTN_64', + 57: 'TC_OP_ATOMIC_DEC_RTN_64', + 58: 'TC_OP_WBL2_NC', + 59: 'TC_OP_WBL2_WC', + 60: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', + 61: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', + 62: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', + 63: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', + 64: 'TC_OP_WBINVL1', + 65: 'TC_OP_ATOMIC_FCMPSWAP_32', + 66: 'TC_OP_ATOMIC_FMIN_32', + 67: 'TC_OP_ATOMIC_FMAX_32', + 68: 'TC_OP_RESERVED_FOP_32_0', + 69: 'TC_OP_RESERVED_FOP_32_1', + 70: 'TC_OP_RESERVED_FOP_32_2', + 71: 'TC_OP_ATOMIC_SWAP_32', + 72: 'TC_OP_ATOMIC_CMPSWAP_32', + 73: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 74: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 75: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 76: 'TC_OP_INV_METADATA', + 77: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1', + 78: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', + 79: 'TC_OP_ATOMIC_ADD_32', + 80: 'TC_OP_ATOMIC_SUB_32', + 81: 'TC_OP_ATOMIC_SMIN_32', + 82: 'TC_OP_ATOMIC_UMIN_32', + 83: 'TC_OP_ATOMIC_SMAX_32', + 84: 'TC_OP_ATOMIC_UMAX_32', + 85: 'TC_OP_ATOMIC_AND_32', + 86: 'TC_OP_ATOMIC_OR_32', + 87: 'TC_OP_ATOMIC_XOR_32', + 88: 'TC_OP_ATOMIC_INC_32', + 89: 'TC_OP_ATOMIC_DEC_32', + 90: 'TC_OP_INVL2_NC', + 91: 'TC_OP_NOP_RTN0', + 92: 'TC_OP_RESERVED_NON_FLOAT_32_1', + 93: 'TC_OP_RESERVED_NON_FLOAT_32_2', + 94: 'TC_OP_RESERVED_NON_FLOAT_32_3', + 95: 'TC_OP_RESERVED_NON_FLOAT_32_4', + 96: 'TC_OP_WBINVL2', + 97: 'TC_OP_ATOMIC_FCMPSWAP_64', + 98: 'TC_OP_ATOMIC_FMIN_64', + 99: 'TC_OP_ATOMIC_FMAX_64', + 100: 'TC_OP_RESERVED_FOP_64_0', + 101: 'TC_OP_RESERVED_FOP_64_1', + 102: 'TC_OP_RESERVED_FOP_64_2', + 103: 'TC_OP_ATOMIC_SWAP_64', + 104: 'TC_OP_ATOMIC_CMPSWAP_64', + 105: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 106: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 107: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 108: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', + 109: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', + 110: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', + 111: 'TC_OP_ATOMIC_ADD_64', + 112: 'TC_OP_ATOMIC_SUB_64', + 113: 'TC_OP_ATOMIC_SMIN_64', + 114: 'TC_OP_ATOMIC_UMIN_64', + 115: 'TC_OP_ATOMIC_SMAX_64', + 116: 'TC_OP_ATOMIC_UMAX_64', + 117: 'TC_OP_ATOMIC_AND_64', + 118: 'TC_OP_ATOMIC_OR_64', + 119: 'TC_OP_ATOMIC_XOR_64', + 120: 'TC_OP_ATOMIC_INC_64', + 121: 'TC_OP_ATOMIC_DEC_64', + 122: 'TC_OP_WBINVL2_NC', + 123: 'TC_OP_NOP_ACK', + 124: 'TC_OP_RESERVED_NON_FLOAT_64_1', + 125: 'TC_OP_RESERVED_NON_FLOAT_64_2', + 126: 'TC_OP_RESERVED_NON_FLOAT_64_3', + 127: 'TC_OP_RESERVED_NON_FLOAT_64_4', +} +TC_OP_READ = 0 +TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 +TC_OP_ATOMIC_FMIN_RTN_32 = 2 +TC_OP_ATOMIC_FMAX_RTN_32 = 3 +TC_OP_RESERVED_FOP_RTN_32_0 = 4 +TC_OP_RESERVED_FOP_RTN_32_1 = 5 +TC_OP_RESERVED_FOP_RTN_32_2 = 6 +TC_OP_ATOMIC_SWAP_RTN_32 = 7 +TC_OP_ATOMIC_CMPSWAP_RTN_32 = 8 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 +TC_OP_PROBE_FILTER = 12 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 13 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 +TC_OP_ATOMIC_ADD_RTN_32 = 15 +TC_OP_ATOMIC_SUB_RTN_32 = 16 +TC_OP_ATOMIC_SMIN_RTN_32 = 17 +TC_OP_ATOMIC_UMIN_RTN_32 = 18 +TC_OP_ATOMIC_SMAX_RTN_32 = 19 +TC_OP_ATOMIC_UMAX_RTN_32 = 20 +TC_OP_ATOMIC_AND_RTN_32 = 21 +TC_OP_ATOMIC_OR_RTN_32 = 22 +TC_OP_ATOMIC_XOR_RTN_32 = 23 +TC_OP_ATOMIC_INC_RTN_32 = 24 +TC_OP_ATOMIC_DEC_RTN_32 = 25 +TC_OP_WBINVL1_VOL = 26 +TC_OP_WBINVL1_SD = 27 +TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 28 +TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 29 +TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 30 +TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 31 +TC_OP_WRITE = 32 +TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 +TC_OP_ATOMIC_FMIN_RTN_64 = 34 +TC_OP_ATOMIC_FMAX_RTN_64 = 35 +TC_OP_RESERVED_FOP_RTN_64_0 = 36 +TC_OP_RESERVED_FOP_RTN_64_1 = 37 +TC_OP_RESERVED_FOP_RTN_64_2 = 38 +TC_OP_ATOMIC_SWAP_RTN_64 = 39 +TC_OP_ATOMIC_CMPSWAP_RTN_64 = 40 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 +TC_OP_WBINVL2_SD = 44 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 45 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 46 +TC_OP_ATOMIC_ADD_RTN_64 = 47 +TC_OP_ATOMIC_SUB_RTN_64 = 48 +TC_OP_ATOMIC_SMIN_RTN_64 = 49 +TC_OP_ATOMIC_UMIN_RTN_64 = 50 +TC_OP_ATOMIC_SMAX_RTN_64 = 51 +TC_OP_ATOMIC_UMAX_RTN_64 = 52 +TC_OP_ATOMIC_AND_RTN_64 = 53 +TC_OP_ATOMIC_OR_RTN_64 = 54 +TC_OP_ATOMIC_XOR_RTN_64 = 55 +TC_OP_ATOMIC_INC_RTN_64 = 56 +TC_OP_ATOMIC_DEC_RTN_64 = 57 +TC_OP_WBL2_NC = 58 +TC_OP_WBL2_WC = 59 +TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 60 +TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 61 +TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 62 +TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 63 +TC_OP_WBINVL1 = 64 +TC_OP_ATOMIC_FCMPSWAP_32 = 65 +TC_OP_ATOMIC_FMIN_32 = 66 +TC_OP_ATOMIC_FMAX_32 = 67 +TC_OP_RESERVED_FOP_32_0 = 68 +TC_OP_RESERVED_FOP_32_1 = 69 +TC_OP_RESERVED_FOP_32_2 = 70 +TC_OP_ATOMIC_SWAP_32 = 71 +TC_OP_ATOMIC_CMPSWAP_32 = 72 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 +TC_OP_INV_METADATA = 76 +TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 77 +TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 78 +TC_OP_ATOMIC_ADD_32 = 79 +TC_OP_ATOMIC_SUB_32 = 80 +TC_OP_ATOMIC_SMIN_32 = 81 +TC_OP_ATOMIC_UMIN_32 = 82 +TC_OP_ATOMIC_SMAX_32 = 83 +TC_OP_ATOMIC_UMAX_32 = 84 +TC_OP_ATOMIC_AND_32 = 85 +TC_OP_ATOMIC_OR_32 = 86 +TC_OP_ATOMIC_XOR_32 = 87 +TC_OP_ATOMIC_INC_32 = 88 +TC_OP_ATOMIC_DEC_32 = 89 +TC_OP_INVL2_NC = 90 +TC_OP_NOP_RTN0 = 91 +TC_OP_RESERVED_NON_FLOAT_32_1 = 92 +TC_OP_RESERVED_NON_FLOAT_32_2 = 93 +TC_OP_RESERVED_NON_FLOAT_32_3 = 94 +TC_OP_RESERVED_NON_FLOAT_32_4 = 95 +TC_OP_WBINVL2 = 96 +TC_OP_ATOMIC_FCMPSWAP_64 = 97 +TC_OP_ATOMIC_FMIN_64 = 98 +TC_OP_ATOMIC_FMAX_64 = 99 +TC_OP_RESERVED_FOP_64_0 = 100 +TC_OP_RESERVED_FOP_64_1 = 101 +TC_OP_RESERVED_FOP_64_2 = 102 +TC_OP_ATOMIC_SWAP_64 = 103 +TC_OP_ATOMIC_CMPSWAP_64 = 104 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 108 +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 109 +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 110 +TC_OP_ATOMIC_ADD_64 = 111 +TC_OP_ATOMIC_SUB_64 = 112 +TC_OP_ATOMIC_SMIN_64 = 113 +TC_OP_ATOMIC_UMIN_64 = 114 +TC_OP_ATOMIC_SMAX_64 = 115 +TC_OP_ATOMIC_UMAX_64 = 116 +TC_OP_ATOMIC_AND_64 = 117 +TC_OP_ATOMIC_OR_64 = 118 +TC_OP_ATOMIC_XOR_64 = 119 +TC_OP_ATOMIC_INC_64 = 120 +TC_OP_ATOMIC_DEC_64 = 121 +TC_OP_WBINVL2_NC = 122 +TC_OP_NOP_ACK = 123 +TC_OP_RESERVED_NON_FLOAT_64_1 = 124 +TC_OP_RESERVED_NON_FLOAT_64_2 = 125 +TC_OP_RESERVED_NON_FLOAT_64_3 = 126 +TC_OP_RESERVED_NON_FLOAT_64_4 = 127 +TC_OP = ctypes.c_uint32 # enum + +# values for enumeration 'TC_CHUB_REQ_CREDITS_ENUM' +TC_CHUB_REQ_CREDITS_ENUM__enumvalues = { + 16: 'TC_CHUB_REQ_CREDITS', +} +TC_CHUB_REQ_CREDITS = 16 +TC_CHUB_REQ_CREDITS_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CHUB_TC_RET_CREDITS_ENUM' +CHUB_TC_RET_CREDITS_ENUM__enumvalues = { + 32: 'CHUB_TC_RET_CREDITS', +} +CHUB_TC_RET_CREDITS = 32 +CHUB_TC_RET_CREDITS_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'TC_NACKS' +TC_NACKS__enumvalues = { + 0: 'TC_NACK_NO_FAULT', + 1: 'TC_NACK_PAGE_FAULT', + 2: 'TC_NACK_PROTECTION_FAULT', + 3: 'TC_NACK_DATA_ERROR', +} +TC_NACK_NO_FAULT = 0 +TC_NACK_PAGE_FAULT = 1 +TC_NACK_PROTECTION_FAULT = 2 +TC_NACK_DATA_ERROR = 3 +TC_NACKS = ctypes.c_uint32 # enum + +# values for enumeration 'TC_EA_CID' +TC_EA_CID__enumvalues = { + 0: 'TC_EA_CID_RT', + 1: 'TC_EA_CID_FMASK', + 2: 'TC_EA_CID_DCC', + 3: 'TC_EA_CID_TCPMETA', + 4: 'TC_EA_CID_Z', + 5: 'TC_EA_CID_STENCIL', + 6: 'TC_EA_CID_HTILE', + 7: 'TC_EA_CID_MISC', + 8: 'TC_EA_CID_TCP', + 9: 'TC_EA_CID_SQC', + 10: 'TC_EA_CID_CPF', + 11: 'TC_EA_CID_CPG', + 12: 'TC_EA_CID_IA', + 13: 'TC_EA_CID_WD', + 14: 'TC_EA_CID_PA', + 15: 'TC_EA_CID_UTCL2_TPI', +} +TC_EA_CID_RT = 0 +TC_EA_CID_FMASK = 1 +TC_EA_CID_DCC = 2 +TC_EA_CID_TCPMETA = 3 +TC_EA_CID_Z = 4 +TC_EA_CID_STENCIL = 5 +TC_EA_CID_HTILE = 6 +TC_EA_CID_MISC = 7 +TC_EA_CID_TCP = 8 +TC_EA_CID_SQC = 9 +TC_EA_CID_CPF = 10 +TC_EA_CID_CPG = 11 +TC_EA_CID_IA = 12 +TC_EA_CID_WD = 13 +TC_EA_CID_PA = 14 +TC_EA_CID_UTCL2_TPI = 15 +TC_EA_CID = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_SAMPLE_CNTL' +SPI_SAMPLE_CNTL__enumvalues = { + 0: 'CENTROIDS_ONLY', + 1: 'CENTERS_ONLY', + 2: 'CENTROIDS_AND_CENTERS', + 3: 'UNDEF', +} +CENTROIDS_ONLY = 0 +CENTERS_ONLY = 1 +CENTROIDS_AND_CENTERS = 2 +UNDEF = 3 +SPI_SAMPLE_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_FOG_MODE' +SPI_FOG_MODE__enumvalues = { + 0: 'SPI_FOG_NONE', + 1: 'SPI_FOG_EXP', + 2: 'SPI_FOG_EXP2', + 3: 'SPI_FOG_LINEAR', +} +SPI_FOG_NONE = 0 +SPI_FOG_EXP = 1 +SPI_FOG_EXP2 = 2 +SPI_FOG_LINEAR = 3 +SPI_FOG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_PNT_SPRITE_OVERRIDE' +SPI_PNT_SPRITE_OVERRIDE__enumvalues = { + 0: 'SPI_PNT_SPRITE_SEL_0', + 1: 'SPI_PNT_SPRITE_SEL_1', + 2: 'SPI_PNT_SPRITE_SEL_S', + 3: 'SPI_PNT_SPRITE_SEL_T', + 4: 'SPI_PNT_SPRITE_SEL_NONE', +} +SPI_PNT_SPRITE_SEL_0 = 0 +SPI_PNT_SPRITE_SEL_1 = 1 +SPI_PNT_SPRITE_SEL_S = 2 +SPI_PNT_SPRITE_SEL_T = 3 +SPI_PNT_SPRITE_SEL_NONE = 4 +SPI_PNT_SPRITE_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_PERFCNT_SEL' +SPI_PERFCNT_SEL__enumvalues = { + 0: 'SPI_PERF_VS_WINDOW_VALID', + 1: 'SPI_PERF_VS_BUSY', + 2: 'SPI_PERF_VS_FIRST_WAVE', + 3: 'SPI_PERF_VS_LAST_WAVE', + 4: 'SPI_PERF_VS_LSHS_DEALLOC', + 5: 'SPI_PERF_VS_PC_STALL', + 6: 'SPI_PERF_VS_POS0_STALL', + 7: 'SPI_PERF_VS_POS1_STALL', + 8: 'SPI_PERF_VS_CRAWLER_STALL', + 9: 'SPI_PERF_VS_EVENT_WAVE', + 10: 'SPI_PERF_VS_WAVE', + 11: 'SPI_PERF_VS_PERS_UPD_FULL0', + 12: 'SPI_PERF_VS_PERS_UPD_FULL1', + 13: 'SPI_PERF_VS_LATE_ALLOC_FULL', + 14: 'SPI_PERF_VS_FIRST_SUBGRP', + 15: 'SPI_PERF_VS_LAST_SUBGRP', + 16: 'SPI_PERF_GS_WINDOW_VALID', + 17: 'SPI_PERF_GS_BUSY', + 18: 'SPI_PERF_GS_CRAWLER_STALL', + 19: 'SPI_PERF_GS_EVENT_WAVE', + 20: 'SPI_PERF_GS_WAVE', + 21: 'SPI_PERF_GS_PERS_UPD_FULL0', + 22: 'SPI_PERF_GS_PERS_UPD_FULL1', + 23: 'SPI_PERF_GS_FIRST_SUBGRP', + 24: 'SPI_PERF_GS_LAST_SUBGRP', + 25: 'SPI_PERF_ES_WINDOW_VALID', + 26: 'SPI_PERF_ES_BUSY', + 27: 'SPI_PERF_ES_CRAWLER_STALL', + 28: 'SPI_PERF_ES_FIRST_WAVE', + 29: 'SPI_PERF_ES_LAST_WAVE', + 30: 'SPI_PERF_ES_LSHS_DEALLOC', + 31: 'SPI_PERF_ES_EVENT_WAVE', + 32: 'SPI_PERF_ES_WAVE', + 33: 'SPI_PERF_ES_PERS_UPD_FULL0', + 34: 'SPI_PERF_ES_PERS_UPD_FULL1', + 35: 'SPI_PERF_ES_FIRST_SUBGRP', + 36: 'SPI_PERF_ES_LAST_SUBGRP', + 37: 'SPI_PERF_HS_WINDOW_VALID', + 38: 'SPI_PERF_HS_BUSY', + 39: 'SPI_PERF_HS_CRAWLER_STALL', + 40: 'SPI_PERF_HS_FIRST_WAVE', + 41: 'SPI_PERF_HS_LAST_WAVE', + 42: 'SPI_PERF_HS_LSHS_DEALLOC', + 43: 'SPI_PERF_HS_EVENT_WAVE', + 44: 'SPI_PERF_HS_WAVE', + 45: 'SPI_PERF_HS_PERS_UPD_FULL0', + 46: 'SPI_PERF_HS_PERS_UPD_FULL1', + 47: 'SPI_PERF_LS_WINDOW_VALID', + 48: 'SPI_PERF_LS_BUSY', + 49: 'SPI_PERF_LS_CRAWLER_STALL', + 50: 'SPI_PERF_LS_FIRST_WAVE', + 51: 'SPI_PERF_LS_LAST_WAVE', + 52: 'SPI_PERF_OFFCHIP_LDS_STALL_LS', + 53: 'SPI_PERF_LS_EVENT_WAVE', + 54: 'SPI_PERF_LS_WAVE', + 55: 'SPI_PERF_LS_PERS_UPD_FULL0', + 56: 'SPI_PERF_LS_PERS_UPD_FULL1', + 57: 'SPI_PERF_CSG_WINDOW_VALID', + 58: 'SPI_PERF_CSG_BUSY', + 59: 'SPI_PERF_CSG_NUM_THREADGROUPS', + 60: 'SPI_PERF_CSG_CRAWLER_STALL', + 61: 'SPI_PERF_CSG_EVENT_WAVE', + 62: 'SPI_PERF_CSG_WAVE', + 63: 'SPI_PERF_CSN_WINDOW_VALID', + 64: 'SPI_PERF_CSN_BUSY', + 65: 'SPI_PERF_CSN_NUM_THREADGROUPS', + 66: 'SPI_PERF_CSN_CRAWLER_STALL', + 67: 'SPI_PERF_CSN_EVENT_WAVE', + 68: 'SPI_PERF_CSN_WAVE', + 69: 'SPI_PERF_PS_CTL_WINDOW_VALID', + 70: 'SPI_PERF_PS_CTL_BUSY', + 71: 'SPI_PERF_PS_CTL_ACTIVE', + 72: 'SPI_PERF_PS_CTL_DEALLOC_BIN0', + 73: 'SPI_PERF_PS_CTL_FPOS_BIN1_STALL', + 74: 'SPI_PERF_PS_CTL_EVENT_WAVE', + 75: 'SPI_PERF_PS_CTL_WAVE', + 76: 'SPI_PERF_PS_CTL_OPT_WAVE', + 77: 'SPI_PERF_PS_CTL_PASS_BIN0', + 78: 'SPI_PERF_PS_CTL_PASS_BIN1', + 79: 'SPI_PERF_PS_CTL_FPOS_BIN2', + 80: 'SPI_PERF_PS_CTL_PRIM_BIN0', + 81: 'SPI_PERF_PS_CTL_PRIM_BIN1', + 82: 'SPI_PERF_PS_CTL_CNF_BIN2', + 83: 'SPI_PERF_PS_CTL_CNF_BIN3', + 84: 'SPI_PERF_PS_CTL_CRAWLER_STALL', + 85: 'SPI_PERF_PS_CTL_LDS_RES_FULL', + 86: 'SPI_PERF_PS_PERS_UPD_FULL0', + 87: 'SPI_PERF_PS_PERS_UPD_FULL1', + 88: 'SPI_PERF_PIX_ALLOC_PEND_CNT', + 89: 'SPI_PERF_PIX_ALLOC_SCB_STALL', + 90: 'SPI_PERF_PIX_ALLOC_DB0_STALL', + 91: 'SPI_PERF_PIX_ALLOC_DB1_STALL', + 92: 'SPI_PERF_PIX_ALLOC_DB2_STALL', + 93: 'SPI_PERF_PIX_ALLOC_DB3_STALL', + 94: 'SPI_PERF_LDS0_PC_VALID', + 95: 'SPI_PERF_LDS1_PC_VALID', + 96: 'SPI_PERF_RA_PIPE_REQ_BIN2', + 97: 'SPI_PERF_RA_TASK_REQ_BIN3', + 98: 'SPI_PERF_RA_WR_CTL_FULL', + 99: 'SPI_PERF_RA_REQ_NO_ALLOC', + 100: 'SPI_PERF_RA_REQ_NO_ALLOC_PS', + 101: 'SPI_PERF_RA_REQ_NO_ALLOC_VS', + 102: 'SPI_PERF_RA_REQ_NO_ALLOC_GS', + 103: 'SPI_PERF_RA_REQ_NO_ALLOC_ES', + 104: 'SPI_PERF_RA_REQ_NO_ALLOC_HS', + 105: 'SPI_PERF_RA_REQ_NO_ALLOC_LS', + 106: 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', + 107: 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', + 108: 'SPI_PERF_RA_RES_STALL_PS', + 109: 'SPI_PERF_RA_RES_STALL_VS', + 110: 'SPI_PERF_RA_RES_STALL_GS', + 111: 'SPI_PERF_RA_RES_STALL_ES', + 112: 'SPI_PERF_RA_RES_STALL_HS', + 113: 'SPI_PERF_RA_RES_STALL_LS', + 114: 'SPI_PERF_RA_RES_STALL_CSG', + 115: 'SPI_PERF_RA_RES_STALL_CSN', + 116: 'SPI_PERF_RA_TMP_STALL_PS', + 117: 'SPI_PERF_RA_TMP_STALL_VS', + 118: 'SPI_PERF_RA_TMP_STALL_GS', + 119: 'SPI_PERF_RA_TMP_STALL_ES', + 120: 'SPI_PERF_RA_TMP_STALL_HS', + 121: 'SPI_PERF_RA_TMP_STALL_LS', + 122: 'SPI_PERF_RA_TMP_STALL_CSG', + 123: 'SPI_PERF_RA_TMP_STALL_CSN', + 124: 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', + 125: 'SPI_PERF_RA_WAVE_SIMD_FULL_VS', + 126: 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', + 127: 'SPI_PERF_RA_WAVE_SIMD_FULL_ES', + 128: 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', + 129: 'SPI_PERF_RA_WAVE_SIMD_FULL_LS', + 130: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', + 131: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', + 132: 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', + 133: 'SPI_PERF_RA_VGPR_SIMD_FULL_VS', + 134: 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', + 135: 'SPI_PERF_RA_VGPR_SIMD_FULL_ES', + 136: 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', + 137: 'SPI_PERF_RA_VGPR_SIMD_FULL_LS', + 138: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', + 139: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', + 140: 'SPI_PERF_RA_SGPR_SIMD_FULL_PS', + 141: 'SPI_PERF_RA_SGPR_SIMD_FULL_VS', + 142: 'SPI_PERF_RA_SGPR_SIMD_FULL_GS', + 143: 'SPI_PERF_RA_SGPR_SIMD_FULL_ES', + 144: 'SPI_PERF_RA_SGPR_SIMD_FULL_HS', + 145: 'SPI_PERF_RA_SGPR_SIMD_FULL_LS', + 146: 'SPI_PERF_RA_SGPR_SIMD_FULL_CSG', + 147: 'SPI_PERF_RA_SGPR_SIMD_FULL_CSN', + 148: 'SPI_PERF_RA_LDS_CU_FULL_PS', + 149: 'SPI_PERF_RA_LDS_CU_FULL_LS', + 150: 'SPI_PERF_RA_LDS_CU_FULL_ES', + 151: 'SPI_PERF_RA_LDS_CU_FULL_CSG', + 152: 'SPI_PERF_RA_LDS_CU_FULL_CSN', + 153: 'SPI_PERF_RA_BAR_CU_FULL_HS', + 154: 'SPI_PERF_RA_BAR_CU_FULL_CSG', + 155: 'SPI_PERF_RA_BAR_CU_FULL_CSN', + 156: 'SPI_PERF_RA_BULKY_CU_FULL_CSG', + 157: 'SPI_PERF_RA_BULKY_CU_FULL_CSN', + 158: 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', + 159: 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', + 160: 'SPI_PERF_RA_WVLIM_STALL_PS', + 161: 'SPI_PERF_RA_WVLIM_STALL_VS', + 162: 'SPI_PERF_RA_WVLIM_STALL_GS', + 163: 'SPI_PERF_RA_WVLIM_STALL_ES', + 164: 'SPI_PERF_RA_WVLIM_STALL_HS', + 165: 'SPI_PERF_RA_WVLIM_STALL_LS', + 166: 'SPI_PERF_RA_WVLIM_STALL_CSG', + 167: 'SPI_PERF_RA_WVLIM_STALL_CSN', + 168: 'SPI_PERF_RA_PS_LOCK_NA', + 169: 'SPI_PERF_RA_VS_LOCK', + 170: 'SPI_PERF_RA_GS_LOCK', + 171: 'SPI_PERF_RA_ES_LOCK', + 172: 'SPI_PERF_RA_HS_LOCK', + 173: 'SPI_PERF_RA_LS_LOCK', + 174: 'SPI_PERF_RA_CSG_LOCK', + 175: 'SPI_PERF_RA_CSN_LOCK', + 176: 'SPI_PERF_RA_RSV_UPD', + 177: 'SPI_PERF_EXP_ARB_COL_CNT', + 178: 'SPI_PERF_EXP_ARB_PAR_CNT', + 179: 'SPI_PERF_EXP_ARB_POS_CNT', + 180: 'SPI_PERF_EXP_ARB_GDS_CNT', + 181: 'SPI_PERF_CLKGATE_BUSY_STALL', + 182: 'SPI_PERF_CLKGATE_ACTIVE_STALL', + 183: 'SPI_PERF_CLKGATE_ALL_CLOCKS_ON', + 184: 'SPI_PERF_CLKGATE_CGTT_DYN_ON', + 185: 'SPI_PERF_CLKGATE_CGTT_REG_ON', + 186: 'SPI_PERF_NUM_VS_POS_EXPORTS', + 187: 'SPI_PERF_NUM_VS_PARAM_EXPORTS', + 188: 'SPI_PERF_NUM_PS_COL_EXPORTS', + 189: 'SPI_PERF_ES_GRP_FIFO_FULL', + 190: 'SPI_PERF_GS_GRP_FIFO_FULL', + 191: 'SPI_PERF_HS_GRP_FIFO_FULL', + 192: 'SPI_PERF_LS_GRP_FIFO_FULL', + 193: 'SPI_PERF_VS_ALLOC_CNT', + 194: 'SPI_PERF_VS_LATE_ALLOC_ACCUM', + 195: 'SPI_PERF_PC_ALLOC_CNT', + 196: 'SPI_PERF_PC_ALLOC_ACCUM', +} +SPI_PERF_VS_WINDOW_VALID = 0 +SPI_PERF_VS_BUSY = 1 +SPI_PERF_VS_FIRST_WAVE = 2 +SPI_PERF_VS_LAST_WAVE = 3 +SPI_PERF_VS_LSHS_DEALLOC = 4 +SPI_PERF_VS_PC_STALL = 5 +SPI_PERF_VS_POS0_STALL = 6 +SPI_PERF_VS_POS1_STALL = 7 +SPI_PERF_VS_CRAWLER_STALL = 8 +SPI_PERF_VS_EVENT_WAVE = 9 +SPI_PERF_VS_WAVE = 10 +SPI_PERF_VS_PERS_UPD_FULL0 = 11 +SPI_PERF_VS_PERS_UPD_FULL1 = 12 +SPI_PERF_VS_LATE_ALLOC_FULL = 13 +SPI_PERF_VS_FIRST_SUBGRP = 14 +SPI_PERF_VS_LAST_SUBGRP = 15 +SPI_PERF_GS_WINDOW_VALID = 16 +SPI_PERF_GS_BUSY = 17 +SPI_PERF_GS_CRAWLER_STALL = 18 +SPI_PERF_GS_EVENT_WAVE = 19 +SPI_PERF_GS_WAVE = 20 +SPI_PERF_GS_PERS_UPD_FULL0 = 21 +SPI_PERF_GS_PERS_UPD_FULL1 = 22 +SPI_PERF_GS_FIRST_SUBGRP = 23 +SPI_PERF_GS_LAST_SUBGRP = 24 +SPI_PERF_ES_WINDOW_VALID = 25 +SPI_PERF_ES_BUSY = 26 +SPI_PERF_ES_CRAWLER_STALL = 27 +SPI_PERF_ES_FIRST_WAVE = 28 +SPI_PERF_ES_LAST_WAVE = 29 +SPI_PERF_ES_LSHS_DEALLOC = 30 +SPI_PERF_ES_EVENT_WAVE = 31 +SPI_PERF_ES_WAVE = 32 +SPI_PERF_ES_PERS_UPD_FULL0 = 33 +SPI_PERF_ES_PERS_UPD_FULL1 = 34 +SPI_PERF_ES_FIRST_SUBGRP = 35 +SPI_PERF_ES_LAST_SUBGRP = 36 +SPI_PERF_HS_WINDOW_VALID = 37 +SPI_PERF_HS_BUSY = 38 +SPI_PERF_HS_CRAWLER_STALL = 39 +SPI_PERF_HS_FIRST_WAVE = 40 +SPI_PERF_HS_LAST_WAVE = 41 +SPI_PERF_HS_LSHS_DEALLOC = 42 +SPI_PERF_HS_EVENT_WAVE = 43 +SPI_PERF_HS_WAVE = 44 +SPI_PERF_HS_PERS_UPD_FULL0 = 45 +SPI_PERF_HS_PERS_UPD_FULL1 = 46 +SPI_PERF_LS_WINDOW_VALID = 47 +SPI_PERF_LS_BUSY = 48 +SPI_PERF_LS_CRAWLER_STALL = 49 +SPI_PERF_LS_FIRST_WAVE = 50 +SPI_PERF_LS_LAST_WAVE = 51 +SPI_PERF_OFFCHIP_LDS_STALL_LS = 52 +SPI_PERF_LS_EVENT_WAVE = 53 +SPI_PERF_LS_WAVE = 54 +SPI_PERF_LS_PERS_UPD_FULL0 = 55 +SPI_PERF_LS_PERS_UPD_FULL1 = 56 +SPI_PERF_CSG_WINDOW_VALID = 57 +SPI_PERF_CSG_BUSY = 58 +SPI_PERF_CSG_NUM_THREADGROUPS = 59 +SPI_PERF_CSG_CRAWLER_STALL = 60 +SPI_PERF_CSG_EVENT_WAVE = 61 +SPI_PERF_CSG_WAVE = 62 +SPI_PERF_CSN_WINDOW_VALID = 63 +SPI_PERF_CSN_BUSY = 64 +SPI_PERF_CSN_NUM_THREADGROUPS = 65 +SPI_PERF_CSN_CRAWLER_STALL = 66 +SPI_PERF_CSN_EVENT_WAVE = 67 +SPI_PERF_CSN_WAVE = 68 +SPI_PERF_PS_CTL_WINDOW_VALID = 69 +SPI_PERF_PS_CTL_BUSY = 70 +SPI_PERF_PS_CTL_ACTIVE = 71 +SPI_PERF_PS_CTL_DEALLOC_BIN0 = 72 +SPI_PERF_PS_CTL_FPOS_BIN1_STALL = 73 +SPI_PERF_PS_CTL_EVENT_WAVE = 74 +SPI_PERF_PS_CTL_WAVE = 75 +SPI_PERF_PS_CTL_OPT_WAVE = 76 +SPI_PERF_PS_CTL_PASS_BIN0 = 77 +SPI_PERF_PS_CTL_PASS_BIN1 = 78 +SPI_PERF_PS_CTL_FPOS_BIN2 = 79 +SPI_PERF_PS_CTL_PRIM_BIN0 = 80 +SPI_PERF_PS_CTL_PRIM_BIN1 = 81 +SPI_PERF_PS_CTL_CNF_BIN2 = 82 +SPI_PERF_PS_CTL_CNF_BIN3 = 83 +SPI_PERF_PS_CTL_CRAWLER_STALL = 84 +SPI_PERF_PS_CTL_LDS_RES_FULL = 85 +SPI_PERF_PS_PERS_UPD_FULL0 = 86 +SPI_PERF_PS_PERS_UPD_FULL1 = 87 +SPI_PERF_PIX_ALLOC_PEND_CNT = 88 +SPI_PERF_PIX_ALLOC_SCB_STALL = 89 +SPI_PERF_PIX_ALLOC_DB0_STALL = 90 +SPI_PERF_PIX_ALLOC_DB1_STALL = 91 +SPI_PERF_PIX_ALLOC_DB2_STALL = 92 +SPI_PERF_PIX_ALLOC_DB3_STALL = 93 +SPI_PERF_LDS0_PC_VALID = 94 +SPI_PERF_LDS1_PC_VALID = 95 +SPI_PERF_RA_PIPE_REQ_BIN2 = 96 +SPI_PERF_RA_TASK_REQ_BIN3 = 97 +SPI_PERF_RA_WR_CTL_FULL = 98 +SPI_PERF_RA_REQ_NO_ALLOC = 99 +SPI_PERF_RA_REQ_NO_ALLOC_PS = 100 +SPI_PERF_RA_REQ_NO_ALLOC_VS = 101 +SPI_PERF_RA_REQ_NO_ALLOC_GS = 102 +SPI_PERF_RA_REQ_NO_ALLOC_ES = 103 +SPI_PERF_RA_REQ_NO_ALLOC_HS = 104 +SPI_PERF_RA_REQ_NO_ALLOC_LS = 105 +SPI_PERF_RA_REQ_NO_ALLOC_CSG = 106 +SPI_PERF_RA_REQ_NO_ALLOC_CSN = 107 +SPI_PERF_RA_RES_STALL_PS = 108 +SPI_PERF_RA_RES_STALL_VS = 109 +SPI_PERF_RA_RES_STALL_GS = 110 +SPI_PERF_RA_RES_STALL_ES = 111 +SPI_PERF_RA_RES_STALL_HS = 112 +SPI_PERF_RA_RES_STALL_LS = 113 +SPI_PERF_RA_RES_STALL_CSG = 114 +SPI_PERF_RA_RES_STALL_CSN = 115 +SPI_PERF_RA_TMP_STALL_PS = 116 +SPI_PERF_RA_TMP_STALL_VS = 117 +SPI_PERF_RA_TMP_STALL_GS = 118 +SPI_PERF_RA_TMP_STALL_ES = 119 +SPI_PERF_RA_TMP_STALL_HS = 120 +SPI_PERF_RA_TMP_STALL_LS = 121 +SPI_PERF_RA_TMP_STALL_CSG = 122 +SPI_PERF_RA_TMP_STALL_CSN = 123 +SPI_PERF_RA_WAVE_SIMD_FULL_PS = 124 +SPI_PERF_RA_WAVE_SIMD_FULL_VS = 125 +SPI_PERF_RA_WAVE_SIMD_FULL_GS = 126 +SPI_PERF_RA_WAVE_SIMD_FULL_ES = 127 +SPI_PERF_RA_WAVE_SIMD_FULL_HS = 128 +SPI_PERF_RA_WAVE_SIMD_FULL_LS = 129 +SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 130 +SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 131 +SPI_PERF_RA_VGPR_SIMD_FULL_PS = 132 +SPI_PERF_RA_VGPR_SIMD_FULL_VS = 133 +SPI_PERF_RA_VGPR_SIMD_FULL_GS = 134 +SPI_PERF_RA_VGPR_SIMD_FULL_ES = 135 +SPI_PERF_RA_VGPR_SIMD_FULL_HS = 136 +SPI_PERF_RA_VGPR_SIMD_FULL_LS = 137 +SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 138 +SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 139 +SPI_PERF_RA_SGPR_SIMD_FULL_PS = 140 +SPI_PERF_RA_SGPR_SIMD_FULL_VS = 141 +SPI_PERF_RA_SGPR_SIMD_FULL_GS = 142 +SPI_PERF_RA_SGPR_SIMD_FULL_ES = 143 +SPI_PERF_RA_SGPR_SIMD_FULL_HS = 144 +SPI_PERF_RA_SGPR_SIMD_FULL_LS = 145 +SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 146 +SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 147 +SPI_PERF_RA_LDS_CU_FULL_PS = 148 +SPI_PERF_RA_LDS_CU_FULL_LS = 149 +SPI_PERF_RA_LDS_CU_FULL_ES = 150 +SPI_PERF_RA_LDS_CU_FULL_CSG = 151 +SPI_PERF_RA_LDS_CU_FULL_CSN = 152 +SPI_PERF_RA_BAR_CU_FULL_HS = 153 +SPI_PERF_RA_BAR_CU_FULL_CSG = 154 +SPI_PERF_RA_BAR_CU_FULL_CSN = 155 +SPI_PERF_RA_BULKY_CU_FULL_CSG = 156 +SPI_PERF_RA_BULKY_CU_FULL_CSN = 157 +SPI_PERF_RA_TGLIM_CU_FULL_CSG = 158 +SPI_PERF_RA_TGLIM_CU_FULL_CSN = 159 +SPI_PERF_RA_WVLIM_STALL_PS = 160 +SPI_PERF_RA_WVLIM_STALL_VS = 161 +SPI_PERF_RA_WVLIM_STALL_GS = 162 +SPI_PERF_RA_WVLIM_STALL_ES = 163 +SPI_PERF_RA_WVLIM_STALL_HS = 164 +SPI_PERF_RA_WVLIM_STALL_LS = 165 +SPI_PERF_RA_WVLIM_STALL_CSG = 166 +SPI_PERF_RA_WVLIM_STALL_CSN = 167 +SPI_PERF_RA_PS_LOCK_NA = 168 +SPI_PERF_RA_VS_LOCK = 169 +SPI_PERF_RA_GS_LOCK = 170 +SPI_PERF_RA_ES_LOCK = 171 +SPI_PERF_RA_HS_LOCK = 172 +SPI_PERF_RA_LS_LOCK = 173 +SPI_PERF_RA_CSG_LOCK = 174 +SPI_PERF_RA_CSN_LOCK = 175 +SPI_PERF_RA_RSV_UPD = 176 +SPI_PERF_EXP_ARB_COL_CNT = 177 +SPI_PERF_EXP_ARB_PAR_CNT = 178 +SPI_PERF_EXP_ARB_POS_CNT = 179 +SPI_PERF_EXP_ARB_GDS_CNT = 180 +SPI_PERF_CLKGATE_BUSY_STALL = 181 +SPI_PERF_CLKGATE_ACTIVE_STALL = 182 +SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 183 +SPI_PERF_CLKGATE_CGTT_DYN_ON = 184 +SPI_PERF_CLKGATE_CGTT_REG_ON = 185 +SPI_PERF_NUM_VS_POS_EXPORTS = 186 +SPI_PERF_NUM_VS_PARAM_EXPORTS = 187 +SPI_PERF_NUM_PS_COL_EXPORTS = 188 +SPI_PERF_ES_GRP_FIFO_FULL = 189 +SPI_PERF_GS_GRP_FIFO_FULL = 190 +SPI_PERF_HS_GRP_FIFO_FULL = 191 +SPI_PERF_LS_GRP_FIFO_FULL = 192 +SPI_PERF_VS_ALLOC_CNT = 193 +SPI_PERF_VS_LATE_ALLOC_ACCUM = 194 +SPI_PERF_PC_ALLOC_CNT = 195 +SPI_PERF_PC_ALLOC_ACCUM = 196 +SPI_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_SHADER_FORMAT' +SPI_SHADER_FORMAT__enumvalues = { + 0: 'SPI_SHADER_NONE', + 1: 'SPI_SHADER_1COMP', + 2: 'SPI_SHADER_2COMP', + 3: 'SPI_SHADER_4COMPRESS', + 4: 'SPI_SHADER_4COMP', +} +SPI_SHADER_NONE = 0 +SPI_SHADER_1COMP = 1 +SPI_SHADER_2COMP = 2 +SPI_SHADER_4COMPRESS = 3 +SPI_SHADER_4COMP = 4 +SPI_SHADER_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_SHADER_EX_FORMAT' +SPI_SHADER_EX_FORMAT__enumvalues = { + 0: 'SPI_SHADER_ZERO', + 1: 'SPI_SHADER_32_R', + 2: 'SPI_SHADER_32_GR', + 3: 'SPI_SHADER_32_AR', + 4: 'SPI_SHADER_FP16_ABGR', + 5: 'SPI_SHADER_UNORM16_ABGR', + 6: 'SPI_SHADER_SNORM16_ABGR', + 7: 'SPI_SHADER_UINT16_ABGR', + 8: 'SPI_SHADER_SINT16_ABGR', + 9: 'SPI_SHADER_32_ABGR', +} +SPI_SHADER_ZERO = 0 +SPI_SHADER_32_R = 1 +SPI_SHADER_32_GR = 2 +SPI_SHADER_32_AR = 3 +SPI_SHADER_FP16_ABGR = 4 +SPI_SHADER_UNORM16_ABGR = 5 +SPI_SHADER_SNORM16_ABGR = 6 +SPI_SHADER_UINT16_ABGR = 7 +SPI_SHADER_SINT16_ABGR = 8 +SPI_SHADER_32_ABGR = 9 +SPI_SHADER_EX_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'CLKGATE_SM_MODE' +CLKGATE_SM_MODE__enumvalues = { + 0: 'ON_SEQ', + 1: 'OFF_SEQ', + 2: 'PROG_SEQ', + 3: 'READ_SEQ', + 4: 'SM_MODE_RESERVED', +} +ON_SEQ = 0 +OFF_SEQ = 1 +PROG_SEQ = 2 +READ_SEQ = 3 +SM_MODE_RESERVED = 4 +CLKGATE_SM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CLKGATE_BASE_MODE' +CLKGATE_BASE_MODE__enumvalues = { + 0: 'MULT_8', + 1: 'MULT_16', +} +MULT_8 = 0 +MULT_16 = 1 +CLKGATE_BASE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_CLAMP' +SQ_TEX_CLAMP__enumvalues = { + 0: 'SQ_TEX_WRAP', + 1: 'SQ_TEX_MIRROR', + 2: 'SQ_TEX_CLAMP_LAST_TEXEL', + 3: 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', + 4: 'SQ_TEX_CLAMP_HALF_BORDER', + 5: 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', + 6: 'SQ_TEX_CLAMP_BORDER', + 7: 'SQ_TEX_MIRROR_ONCE_BORDER', +} +SQ_TEX_WRAP = 0 +SQ_TEX_MIRROR = 1 +SQ_TEX_CLAMP_LAST_TEXEL = 2 +SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3 +SQ_TEX_CLAMP_HALF_BORDER = 4 +SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5 +SQ_TEX_CLAMP_BORDER = 6 +SQ_TEX_MIRROR_ONCE_BORDER = 7 +SQ_TEX_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_XY_FILTER' +SQ_TEX_XY_FILTER__enumvalues = { + 0: 'SQ_TEX_XY_FILTER_POINT', + 1: 'SQ_TEX_XY_FILTER_BILINEAR', + 2: 'SQ_TEX_XY_FILTER_ANISO_POINT', + 3: 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', +} +SQ_TEX_XY_FILTER_POINT = 0 +SQ_TEX_XY_FILTER_BILINEAR = 1 +SQ_TEX_XY_FILTER_ANISO_POINT = 2 +SQ_TEX_XY_FILTER_ANISO_BILINEAR = 3 +SQ_TEX_XY_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_Z_FILTER' +SQ_TEX_Z_FILTER__enumvalues = { + 0: 'SQ_TEX_Z_FILTER_NONE', + 1: 'SQ_TEX_Z_FILTER_POINT', + 2: 'SQ_TEX_Z_FILTER_LINEAR', +} +SQ_TEX_Z_FILTER_NONE = 0 +SQ_TEX_Z_FILTER_POINT = 1 +SQ_TEX_Z_FILTER_LINEAR = 2 +SQ_TEX_Z_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_MIP_FILTER' +SQ_TEX_MIP_FILTER__enumvalues = { + 0: 'SQ_TEX_MIP_FILTER_NONE', + 1: 'SQ_TEX_MIP_FILTER_POINT', + 2: 'SQ_TEX_MIP_FILTER_LINEAR', + 3: 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', +} +SQ_TEX_MIP_FILTER_NONE = 0 +SQ_TEX_MIP_FILTER_POINT = 1 +SQ_TEX_MIP_FILTER_LINEAR = 2 +SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 3 +SQ_TEX_MIP_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_ANISO_RATIO' +SQ_TEX_ANISO_RATIO__enumvalues = { + 0: 'SQ_TEX_ANISO_RATIO_1', + 1: 'SQ_TEX_ANISO_RATIO_2', + 2: 'SQ_TEX_ANISO_RATIO_4', + 3: 'SQ_TEX_ANISO_RATIO_8', + 4: 'SQ_TEX_ANISO_RATIO_16', +} +SQ_TEX_ANISO_RATIO_1 = 0 +SQ_TEX_ANISO_RATIO_2 = 1 +SQ_TEX_ANISO_RATIO_4 = 2 +SQ_TEX_ANISO_RATIO_8 = 3 +SQ_TEX_ANISO_RATIO_16 = 4 +SQ_TEX_ANISO_RATIO = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_DEPTH_COMPARE' +SQ_TEX_DEPTH_COMPARE__enumvalues = { + 0: 'SQ_TEX_DEPTH_COMPARE_NEVER', + 1: 'SQ_TEX_DEPTH_COMPARE_LESS', + 2: 'SQ_TEX_DEPTH_COMPARE_EQUAL', + 3: 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', + 4: 'SQ_TEX_DEPTH_COMPARE_GREATER', + 5: 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', + 6: 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', + 7: 'SQ_TEX_DEPTH_COMPARE_ALWAYS', +} +SQ_TEX_DEPTH_COMPARE_NEVER = 0 +SQ_TEX_DEPTH_COMPARE_LESS = 1 +SQ_TEX_DEPTH_COMPARE_EQUAL = 2 +SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 3 +SQ_TEX_DEPTH_COMPARE_GREATER = 4 +SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 5 +SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 6 +SQ_TEX_DEPTH_COMPARE_ALWAYS = 7 +SQ_TEX_DEPTH_COMPARE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_BORDER_COLOR' +SQ_TEX_BORDER_COLOR__enumvalues = { + 0: 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', + 1: 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', + 2: 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', + 3: 'SQ_TEX_BORDER_COLOR_REGISTER', +} +SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0 +SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 1 +SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 2 +SQ_TEX_BORDER_COLOR_REGISTER = 3 +SQ_TEX_BORDER_COLOR = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_RSRC_BUF_TYPE' +SQ_RSRC_BUF_TYPE__enumvalues = { + 0: 'SQ_RSRC_BUF', + 1: 'SQ_RSRC_BUF_RSVD_1', + 2: 'SQ_RSRC_BUF_RSVD_2', + 3: 'SQ_RSRC_BUF_RSVD_3', +} +SQ_RSRC_BUF = 0 +SQ_RSRC_BUF_RSVD_1 = 1 +SQ_RSRC_BUF_RSVD_2 = 2 +SQ_RSRC_BUF_RSVD_3 = 3 +SQ_RSRC_BUF_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_RSRC_IMG_TYPE' +SQ_RSRC_IMG_TYPE__enumvalues = { + 0: 'SQ_RSRC_IMG_RSVD_0', + 1: 'SQ_RSRC_IMG_RSVD_1', + 2: 'SQ_RSRC_IMG_RSVD_2', + 3: 'SQ_RSRC_IMG_RSVD_3', + 4: 'SQ_RSRC_IMG_RSVD_4', + 5: 'SQ_RSRC_IMG_RSVD_5', + 6: 'SQ_RSRC_IMG_RSVD_6', + 7: 'SQ_RSRC_IMG_RSVD_7', + 8: 'SQ_RSRC_IMG_1D', + 9: 'SQ_RSRC_IMG_2D', + 10: 'SQ_RSRC_IMG_3D', + 11: 'SQ_RSRC_IMG_CUBE', + 12: 'SQ_RSRC_IMG_1D_ARRAY', + 13: 'SQ_RSRC_IMG_2D_ARRAY', + 14: 'SQ_RSRC_IMG_2D_MSAA', + 15: 'SQ_RSRC_IMG_2D_MSAA_ARRAY', +} +SQ_RSRC_IMG_RSVD_0 = 0 +SQ_RSRC_IMG_RSVD_1 = 1 +SQ_RSRC_IMG_RSVD_2 = 2 +SQ_RSRC_IMG_RSVD_3 = 3 +SQ_RSRC_IMG_RSVD_4 = 4 +SQ_RSRC_IMG_RSVD_5 = 5 +SQ_RSRC_IMG_RSVD_6 = 6 +SQ_RSRC_IMG_RSVD_7 = 7 +SQ_RSRC_IMG_1D = 8 +SQ_RSRC_IMG_2D = 9 +SQ_RSRC_IMG_3D = 10 +SQ_RSRC_IMG_CUBE = 11 +SQ_RSRC_IMG_1D_ARRAY = 12 +SQ_RSRC_IMG_2D_ARRAY = 13 +SQ_RSRC_IMG_2D_MSAA = 14 +SQ_RSRC_IMG_2D_MSAA_ARRAY = 15 +SQ_RSRC_IMG_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_RSRC_FLAT_TYPE' +SQ_RSRC_FLAT_TYPE__enumvalues = { + 0: 'SQ_RSRC_FLAT_RSVD_0', + 1: 'SQ_RSRC_FLAT', + 2: 'SQ_RSRC_FLAT_RSVD_2', + 3: 'SQ_RSRC_FLAT_RSVD_3', +} +SQ_RSRC_FLAT_RSVD_0 = 0 +SQ_RSRC_FLAT = 1 +SQ_RSRC_FLAT_RSVD_2 = 2 +SQ_RSRC_FLAT_RSVD_3 = 3 +SQ_RSRC_FLAT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IMG_FILTER_TYPE' +SQ_IMG_FILTER_TYPE__enumvalues = { + 0: 'SQ_IMG_FILTER_MODE_BLEND', + 1: 'SQ_IMG_FILTER_MODE_MIN', + 2: 'SQ_IMG_FILTER_MODE_MAX', +} +SQ_IMG_FILTER_MODE_BLEND = 0 +SQ_IMG_FILTER_MODE_MIN = 1 +SQ_IMG_FILTER_MODE_MAX = 2 +SQ_IMG_FILTER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_SEL_XYZW01' +SQ_SEL_XYZW01__enumvalues = { + 0: 'SQ_SEL_0', + 1: 'SQ_SEL_1', + 2: 'SQ_SEL_RESERVED_0', + 3: 'SQ_SEL_RESERVED_1', + 4: 'SQ_SEL_X', + 5: 'SQ_SEL_Y', + 6: 'SQ_SEL_Z', + 7: 'SQ_SEL_W', +} +SQ_SEL_0 = 0 +SQ_SEL_1 = 1 +SQ_SEL_RESERVED_0 = 2 +SQ_SEL_RESERVED_1 = 3 +SQ_SEL_X = 4 +SQ_SEL_Y = 5 +SQ_SEL_Z = 6 +SQ_SEL_W = 7 +SQ_SEL_XYZW01 = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_TYPE' +SQ_WAVE_TYPE__enumvalues = { + 0: 'SQ_WAVE_TYPE_PS', + 1: 'SQ_WAVE_TYPE_VS', + 2: 'SQ_WAVE_TYPE_GS', + 3: 'SQ_WAVE_TYPE_ES', + 4: 'SQ_WAVE_TYPE_HS', + 5: 'SQ_WAVE_TYPE_LS', + 6: 'SQ_WAVE_TYPE_CS', + 7: 'SQ_WAVE_TYPE_PS1', +} +SQ_WAVE_TYPE_PS = 0 +SQ_WAVE_TYPE_VS = 1 +SQ_WAVE_TYPE_GS = 2 +SQ_WAVE_TYPE_ES = 3 +SQ_WAVE_TYPE_HS = 4 +SQ_WAVE_TYPE_LS = 5 +SQ_WAVE_TYPE_CS = 6 +SQ_WAVE_TYPE_PS1 = 7 +SQ_WAVE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_TOKEN_TYPE' +SQ_THREAD_TRACE_TOKEN_TYPE__enumvalues = { + 0: 'SQ_THREAD_TRACE_TOKEN_MISC', + 1: 'SQ_THREAD_TRACE_TOKEN_TIMESTAMP', + 2: 'SQ_THREAD_TRACE_TOKEN_REG', + 3: 'SQ_THREAD_TRACE_TOKEN_WAVE_START', + 4: 'SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC', + 5: 'SQ_THREAD_TRACE_TOKEN_REG_CSPRIV', + 6: 'SQ_THREAD_TRACE_TOKEN_WAVE_END', + 7: 'SQ_THREAD_TRACE_TOKEN_EVENT', + 8: 'SQ_THREAD_TRACE_TOKEN_EVENT_CS', + 9: 'SQ_THREAD_TRACE_TOKEN_EVENT_GFX1', + 10: 'SQ_THREAD_TRACE_TOKEN_INST', + 11: 'SQ_THREAD_TRACE_TOKEN_INST_PC', + 12: 'SQ_THREAD_TRACE_TOKEN_INST_USERDATA', + 13: 'SQ_THREAD_TRACE_TOKEN_ISSUE', + 14: 'SQ_THREAD_TRACE_TOKEN_PERF', + 15: 'SQ_THREAD_TRACE_TOKEN_REG_CS', +} +SQ_THREAD_TRACE_TOKEN_MISC = 0 +SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 1 +SQ_THREAD_TRACE_TOKEN_REG = 2 +SQ_THREAD_TRACE_TOKEN_WAVE_START = 3 +SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC = 4 +SQ_THREAD_TRACE_TOKEN_REG_CSPRIV = 5 +SQ_THREAD_TRACE_TOKEN_WAVE_END = 6 +SQ_THREAD_TRACE_TOKEN_EVENT = 7 +SQ_THREAD_TRACE_TOKEN_EVENT_CS = 8 +SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 9 +SQ_THREAD_TRACE_TOKEN_INST = 10 +SQ_THREAD_TRACE_TOKEN_INST_PC = 11 +SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 12 +SQ_THREAD_TRACE_TOKEN_ISSUE = 13 +SQ_THREAD_TRACE_TOKEN_PERF = 14 +SQ_THREAD_TRACE_TOKEN_REG_CS = 15 +SQ_THREAD_TRACE_TOKEN_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_MISC_TOKEN_TYPE' +SQ_THREAD_TRACE_MISC_TOKEN_TYPE__enumvalues = { + 0: 'SQ_THREAD_TRACE_MISC_TOKEN_TIME', + 1: 'SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET', + 2: 'SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST', + 3: 'SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC', + 4: 'SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN', + 5: 'SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END', + 6: 'SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX', + 7: 'SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN', +} +SQ_THREAD_TRACE_MISC_TOKEN_TIME = 0 +SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET = 1 +SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 2 +SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC = 3 +SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN = 4 +SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END = 5 +SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX = 6 +SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN = 7 +SQ_THREAD_TRACE_MISC_TOKEN_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_INST_TYPE' +SQ_THREAD_TRACE_INST_TYPE__enumvalues = { + 0: 'SQ_THREAD_TRACE_INST_TYPE_SMEM_RD', + 1: 'SQ_THREAD_TRACE_INST_TYPE_SALU_32', + 2: 'SQ_THREAD_TRACE_INST_TYPE_VMEM_RD', + 3: 'SQ_THREAD_TRACE_INST_TYPE_VMEM_WR', + 4: 'SQ_THREAD_TRACE_INST_TYPE_FLAT_WR', + 5: 'SQ_THREAD_TRACE_INST_TYPE_VALU_32', + 6: 'SQ_THREAD_TRACE_INST_TYPE_LDS', + 7: 'SQ_THREAD_TRACE_INST_TYPE_PC', + 8: 'SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS', + 9: 'SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX', + 10: 'SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL', + 11: 'SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS', + 12: 'SQ_THREAD_TRACE_INST_TYPE_JUMP', + 13: 'SQ_THREAD_TRACE_INST_TYPE_NEXT', + 14: 'SQ_THREAD_TRACE_INST_TYPE_FLAT_RD', + 15: 'SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG', + 16: 'SQ_THREAD_TRACE_INST_TYPE_SMEM_WR', + 17: 'SQ_THREAD_TRACE_INST_TYPE_SALU_64', + 18: 'SQ_THREAD_TRACE_INST_TYPE_VALU_64', + 19: 'SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY', + 20: 'SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY', + 21: 'SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY', + 22: 'SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY', + 23: 'SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY', + 24: 'SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY', + 25: 'SQ_THREAD_TRACE_INST_TYPE_FATAL_HALT', +} +SQ_THREAD_TRACE_INST_TYPE_SMEM_RD = 0 +SQ_THREAD_TRACE_INST_TYPE_SALU_32 = 1 +SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 2 +SQ_THREAD_TRACE_INST_TYPE_VMEM_WR = 3 +SQ_THREAD_TRACE_INST_TYPE_FLAT_WR = 4 +SQ_THREAD_TRACE_INST_TYPE_VALU_32 = 5 +SQ_THREAD_TRACE_INST_TYPE_LDS = 6 +SQ_THREAD_TRACE_INST_TYPE_PC = 7 +SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 8 +SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 9 +SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 10 +SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 11 +SQ_THREAD_TRACE_INST_TYPE_JUMP = 12 +SQ_THREAD_TRACE_INST_TYPE_NEXT = 13 +SQ_THREAD_TRACE_INST_TYPE_FLAT_RD = 14 +SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 15 +SQ_THREAD_TRACE_INST_TYPE_SMEM_WR = 16 +SQ_THREAD_TRACE_INST_TYPE_SALU_64 = 17 +SQ_THREAD_TRACE_INST_TYPE_VALU_64 = 18 +SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY = 19 +SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY = 20 +SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY = 21 +SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY = 22 +SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY = 23 +SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY = 24 +SQ_THREAD_TRACE_INST_TYPE_FATAL_HALT = 25 +SQ_THREAD_TRACE_INST_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_REG_TYPE' +SQ_THREAD_TRACE_REG_TYPE__enumvalues = { + 0: 'SQ_THREAD_TRACE_REG_TYPE_EVENT', + 1: 'SQ_THREAD_TRACE_REG_TYPE_DRAW', + 2: 'SQ_THREAD_TRACE_REG_TYPE_DISPATCH', + 3: 'SQ_THREAD_TRACE_REG_TYPE_USERDATA', + 4: 'SQ_THREAD_TRACE_REG_TYPE_MARKER', + 5: 'SQ_THREAD_TRACE_REG_TYPE_GFXDEC', + 6: 'SQ_THREAD_TRACE_REG_TYPE_SHDEC', + 7: 'SQ_THREAD_TRACE_REG_TYPE_OTHER', +} +SQ_THREAD_TRACE_REG_TYPE_EVENT = 0 +SQ_THREAD_TRACE_REG_TYPE_DRAW = 1 +SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 2 +SQ_THREAD_TRACE_REG_TYPE_USERDATA = 3 +SQ_THREAD_TRACE_REG_TYPE_MARKER = 4 +SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 5 +SQ_THREAD_TRACE_REG_TYPE_SHDEC = 6 +SQ_THREAD_TRACE_REG_TYPE_OTHER = 7 +SQ_THREAD_TRACE_REG_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_REG_OP' +SQ_THREAD_TRACE_REG_OP__enumvalues = { + 0: 'SQ_THREAD_TRACE_REG_OP_READ', + 1: 'SQ_THREAD_TRACE_REG_OP_WRITE', +} +SQ_THREAD_TRACE_REG_OP_READ = 0 +SQ_THREAD_TRACE_REG_OP_WRITE = 1 +SQ_THREAD_TRACE_REG_OP = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_MODE_SEL' +SQ_THREAD_TRACE_MODE_SEL__enumvalues = { + 0: 'SQ_THREAD_TRACE_MODE_OFF', + 1: 'SQ_THREAD_TRACE_MODE_ON', +} +SQ_THREAD_TRACE_MODE_OFF = 0 +SQ_THREAD_TRACE_MODE_ON = 1 +SQ_THREAD_TRACE_MODE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_CAPTURE_MODE' +SQ_THREAD_TRACE_CAPTURE_MODE__enumvalues = { + 0: 'SQ_THREAD_TRACE_CAPTURE_MODE_ALL', + 1: 'SQ_THREAD_TRACE_CAPTURE_MODE_SELECT', + 2: 'SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL', +} +SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0 +SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 1 +SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 2 +SQ_THREAD_TRACE_CAPTURE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_VM_ID_MASK' +SQ_THREAD_TRACE_VM_ID_MASK__enumvalues = { + 0: 'SQ_THREAD_TRACE_VM_ID_MASK_SINGLE', + 1: 'SQ_THREAD_TRACE_VM_ID_MASK_ALL', + 2: 'SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL', +} +SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0 +SQ_THREAD_TRACE_VM_ID_MASK_ALL = 1 +SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 2 +SQ_THREAD_TRACE_VM_ID_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_WAVE_MASK' +SQ_THREAD_TRACE_WAVE_MASK__enumvalues = { + 0: 'SQ_THREAD_TRACE_WAVE_MASK_NONE', + 1: 'SQ_THREAD_TRACE_WAVE_MASK_ALL', +} +SQ_THREAD_TRACE_WAVE_MASK_NONE = 0 +SQ_THREAD_TRACE_WAVE_MASK_ALL = 1 +SQ_THREAD_TRACE_WAVE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_ISSUE' +SQ_THREAD_TRACE_ISSUE__enumvalues = { + 0: 'SQ_THREAD_TRACE_ISSUE_NULL', + 1: 'SQ_THREAD_TRACE_ISSUE_STALL', + 2: 'SQ_THREAD_TRACE_ISSUE_INST', + 3: 'SQ_THREAD_TRACE_ISSUE_IMMED', +} +SQ_THREAD_TRACE_ISSUE_NULL = 0 +SQ_THREAD_TRACE_ISSUE_STALL = 1 +SQ_THREAD_TRACE_ISSUE_INST = 2 +SQ_THREAD_TRACE_ISSUE_IMMED = 3 +SQ_THREAD_TRACE_ISSUE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_ISSUE_MASK' +SQ_THREAD_TRACE_ISSUE_MASK__enumvalues = { + 0: 'SQ_THREAD_TRACE_ISSUE_MASK_ALL', + 1: 'SQ_THREAD_TRACE_ISSUE_MASK_STALLED', + 2: 'SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED', + 3: 'SQ_THREAD_TRACE_ISSUE_MASK_IMMED', +} +SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0 +SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 1 +SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 2 +SQ_THREAD_TRACE_ISSUE_MASK_IMMED = 3 +SQ_THREAD_TRACE_ISSUE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_PERF_SEL' +SQ_PERF_SEL__enumvalues = { + 0: 'SQ_PERF_SEL_NONE', + 1: 'SQ_PERF_SEL_ACCUM_PREV', + 2: 'SQ_PERF_SEL_CYCLES', + 3: 'SQ_PERF_SEL_BUSY_CYCLES', + 4: 'SQ_PERF_SEL_WAVES', + 5: 'SQ_PERF_SEL_LEVEL_WAVES', + 6: 'SQ_PERF_SEL_WAVES_EQ_64', + 7: 'SQ_PERF_SEL_WAVES_LT_64', + 8: 'SQ_PERF_SEL_WAVES_LT_48', + 9: 'SQ_PERF_SEL_WAVES_LT_32', + 10: 'SQ_PERF_SEL_WAVES_LT_16', + 11: 'SQ_PERF_SEL_WAVES_CU', + 12: 'SQ_PERF_SEL_LEVEL_WAVES_CU', + 13: 'SQ_PERF_SEL_BUSY_CU_CYCLES', + 14: 'SQ_PERF_SEL_ITEMS', + 15: 'SQ_PERF_SEL_QUADS', + 16: 'SQ_PERF_SEL_EVENTS', + 17: 'SQ_PERF_SEL_SURF_SYNCS', + 18: 'SQ_PERF_SEL_TTRACE_REQS', + 19: 'SQ_PERF_SEL_TTRACE_INFLIGHT_REQS', + 20: 'SQ_PERF_SEL_TTRACE_STALL', + 21: 'SQ_PERF_SEL_MSG_CNTR', + 22: 'SQ_PERF_SEL_MSG_PERF', + 23: 'SQ_PERF_SEL_MSG_GSCNT', + 24: 'SQ_PERF_SEL_MSG_INTERRUPT', + 25: 'SQ_PERF_SEL_INSTS', + 26: 'SQ_PERF_SEL_INSTS_VALU', + 27: 'SQ_PERF_SEL_INSTS_VMEM_WR', + 28: 'SQ_PERF_SEL_INSTS_VMEM_RD', + 29: 'SQ_PERF_SEL_INSTS_VMEM', + 30: 'SQ_PERF_SEL_INSTS_SALU', + 31: 'SQ_PERF_SEL_INSTS_SMEM', + 32: 'SQ_PERF_SEL_INSTS_FLAT', + 33: 'SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY', + 34: 'SQ_PERF_SEL_INSTS_LDS', + 35: 'SQ_PERF_SEL_INSTS_GDS', + 36: 'SQ_PERF_SEL_INSTS_EXP', + 37: 'SQ_PERF_SEL_INSTS_EXP_GDS', + 38: 'SQ_PERF_SEL_INSTS_BRANCH', + 39: 'SQ_PERF_SEL_INSTS_SENDMSG', + 40: 'SQ_PERF_SEL_INSTS_VSKIPPED', + 41: 'SQ_PERF_SEL_INST_LEVEL_VMEM', + 42: 'SQ_PERF_SEL_INST_LEVEL_SMEM', + 43: 'SQ_PERF_SEL_INST_LEVEL_LDS', + 44: 'SQ_PERF_SEL_INST_LEVEL_GDS', + 45: 'SQ_PERF_SEL_INST_LEVEL_EXP', + 46: 'SQ_PERF_SEL_WAVE_CYCLES', + 47: 'SQ_PERF_SEL_WAVE_READY', + 48: 'SQ_PERF_SEL_WAIT_CNT_VM', + 49: 'SQ_PERF_SEL_WAIT_CNT_LGKM', + 50: 'SQ_PERF_SEL_WAIT_CNT_EXP', + 51: 'SQ_PERF_SEL_WAIT_CNT_ANY', + 52: 'SQ_PERF_SEL_WAIT_BARRIER', + 53: 'SQ_PERF_SEL_WAIT_EXP_ALLOC', + 54: 'SQ_PERF_SEL_WAIT_SLEEP', + 55: 'SQ_PERF_SEL_WAIT_SLEEP_XNACK', + 56: 'SQ_PERF_SEL_WAIT_OTHER', + 57: 'SQ_PERF_SEL_WAIT_ANY', + 58: 'SQ_PERF_SEL_WAIT_TTRACE', + 59: 'SQ_PERF_SEL_WAIT_IFETCH', + 60: 'SQ_PERF_SEL_WAIT_INST_ANY', + 61: 'SQ_PERF_SEL_WAIT_INST_VMEM', + 62: 'SQ_PERF_SEL_WAIT_INST_SCA', + 63: 'SQ_PERF_SEL_WAIT_INST_LDS', + 64: 'SQ_PERF_SEL_WAIT_INST_VALU', + 65: 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', + 66: 'SQ_PERF_SEL_WAIT_INST_MISC', + 67: 'SQ_PERF_SEL_WAIT_INST_FLAT', + 68: 'SQ_PERF_SEL_ACTIVE_INST_ANY', + 69: 'SQ_PERF_SEL_ACTIVE_INST_VMEM', + 70: 'SQ_PERF_SEL_ACTIVE_INST_LDS', + 71: 'SQ_PERF_SEL_ACTIVE_INST_VALU', + 72: 'SQ_PERF_SEL_ACTIVE_INST_SCA', + 73: 'SQ_PERF_SEL_ACTIVE_INST_EXP_GDS', + 74: 'SQ_PERF_SEL_ACTIVE_INST_MISC', + 75: 'SQ_PERF_SEL_ACTIVE_INST_FLAT', + 76: 'SQ_PERF_SEL_INST_CYCLES_VMEM_WR', + 77: 'SQ_PERF_SEL_INST_CYCLES_VMEM_RD', + 78: 'SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR', + 79: 'SQ_PERF_SEL_INST_CYCLES_VMEM_DATA', + 80: 'SQ_PERF_SEL_INST_CYCLES_VMEM_CMD', + 81: 'SQ_PERF_SEL_INST_CYCLES_EXP', + 82: 'SQ_PERF_SEL_INST_CYCLES_GDS', + 83: 'SQ_PERF_SEL_INST_CYCLES_SMEM', + 84: 'SQ_PERF_SEL_INST_CYCLES_SALU', + 85: 'SQ_PERF_SEL_THREAD_CYCLES_VALU', + 86: 'SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX', + 87: 'SQ_PERF_SEL_IFETCH', + 88: 'SQ_PERF_SEL_IFETCH_LEVEL', + 89: 'SQ_PERF_SEL_CBRANCH_FORK', + 90: 'SQ_PERF_SEL_CBRANCH_FORK_SPLIT', + 91: 'SQ_PERF_SEL_VALU_LDS_DIRECT_RD', + 92: 'SQ_PERF_SEL_VALU_LDS_INTERP_OP', + 93: 'SQ_PERF_SEL_LDS_BANK_CONFLICT', + 94: 'SQ_PERF_SEL_LDS_ADDR_CONFLICT', + 95: 'SQ_PERF_SEL_LDS_UNALIGNED_STALL', + 96: 'SQ_PERF_SEL_LDS_MEM_VIOLATIONS', + 97: 'SQ_PERF_SEL_LDS_ATOMIC_RETURN', + 98: 'SQ_PERF_SEL_LDS_IDX_ACTIVE', + 99: 'SQ_PERF_SEL_VALU_DEP_STALL', + 100: 'SQ_PERF_SEL_VALU_STARVE', + 101: 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', + 102: 'SQ_PERF_SEL_LDS_DATA_FIFO_FULL', + 103: 'SQ_PERF_SEL_LDS_CMD_FIFO_FULL', + 104: 'SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL', + 105: 'SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL', + 106: 'SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY', + 107: 'SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL', + 108: 'SQ_PERF_SEL_VALU_SRC_C_CONFLICT', + 109: 'SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT', + 110: 'SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT', + 111: 'SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT', + 112: 'SQ_PERF_SEL_LDS_SRC_CD_CONFLICT', + 113: 'SQ_PERF_SEL_SRC_CD_BUSY', + 114: 'SQ_PERF_SEL_PT_POWER_STALL', + 115: 'SQ_PERF_SEL_USER0', + 116: 'SQ_PERF_SEL_USER1', + 117: 'SQ_PERF_SEL_USER2', + 118: 'SQ_PERF_SEL_USER3', + 119: 'SQ_PERF_SEL_USER4', + 120: 'SQ_PERF_SEL_USER5', + 121: 'SQ_PERF_SEL_USER6', + 122: 'SQ_PERF_SEL_USER7', + 123: 'SQ_PERF_SEL_USER8', + 124: 'SQ_PERF_SEL_USER9', + 125: 'SQ_PERF_SEL_USER10', + 126: 'SQ_PERF_SEL_USER11', + 127: 'SQ_PERF_SEL_USER12', + 128: 'SQ_PERF_SEL_USER13', + 129: 'SQ_PERF_SEL_USER14', + 130: 'SQ_PERF_SEL_USER15', + 131: 'SQ_PERF_SEL_USER_LEVEL0', + 132: 'SQ_PERF_SEL_USER_LEVEL1', + 133: 'SQ_PERF_SEL_USER_LEVEL2', + 134: 'SQ_PERF_SEL_USER_LEVEL3', + 135: 'SQ_PERF_SEL_USER_LEVEL4', + 136: 'SQ_PERF_SEL_USER_LEVEL5', + 137: 'SQ_PERF_SEL_USER_LEVEL6', + 138: 'SQ_PERF_SEL_USER_LEVEL7', + 139: 'SQ_PERF_SEL_USER_LEVEL8', + 140: 'SQ_PERF_SEL_USER_LEVEL9', + 141: 'SQ_PERF_SEL_USER_LEVEL10', + 142: 'SQ_PERF_SEL_USER_LEVEL11', + 143: 'SQ_PERF_SEL_USER_LEVEL12', + 144: 'SQ_PERF_SEL_USER_LEVEL13', + 145: 'SQ_PERF_SEL_USER_LEVEL14', + 146: 'SQ_PERF_SEL_USER_LEVEL15', + 147: 'SQ_PERF_SEL_POWER_VALU', + 148: 'SQ_PERF_SEL_POWER_VALU0', + 149: 'SQ_PERF_SEL_POWER_VALU1', + 150: 'SQ_PERF_SEL_POWER_VALU2', + 151: 'SQ_PERF_SEL_POWER_GPR_RD', + 152: 'SQ_PERF_SEL_POWER_GPR_WR', + 153: 'SQ_PERF_SEL_POWER_LDS_BUSY', + 154: 'SQ_PERF_SEL_POWER_ALU_BUSY', + 155: 'SQ_PERF_SEL_POWER_TEX_BUSY', + 156: 'SQ_PERF_SEL_ACCUM_PREV_HIRES', + 157: 'SQ_PERF_SEL_WAVES_RESTORED', + 158: 'SQ_PERF_SEL_WAVES_SAVED', + 159: 'SQ_PERF_SEL_INSTS_SMEM_NORM', + 160: 'SQ_PERF_SEL_ATC_INSTS_VMEM', + 161: 'SQ_PERF_SEL_ATC_INST_LEVEL_VMEM', + 162: 'SQ_PERF_SEL_ATC_XNACK_FIRST', + 163: 'SQ_PERF_SEL_ATC_XNACK_ALL', + 164: 'SQ_PERF_SEL_ATC_XNACK_FIFO_FULL', + 165: 'SQ_PERF_SEL_ATC_INSTS_SMEM', + 166: 'SQ_PERF_SEL_ATC_INST_LEVEL_SMEM', + 167: 'SQ_PERF_SEL_IFETCH_XNACK', + 168: 'SQ_PERF_SEL_TLB_SHOOTDOWN', + 169: 'SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES', + 170: 'SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY', + 171: 'SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY', + 172: 'SQ_PERF_SEL_INSTS_VMEM_REPLAY', + 173: 'SQ_PERF_SEL_INSTS_SMEM_REPLAY', + 174: 'SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY', + 175: 'SQ_PERF_SEL_INSTS_FLAT_REPLAY', + 176: 'SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY', + 177: 'SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY', + 178: 'SQ_PERF_SEL_UTCL1_TRANSLATION_MISS', + 179: 'SQ_PERF_SEL_UTCL1_PERMISSION_MISS', + 180: 'SQ_PERF_SEL_UTCL1_REQUEST', + 181: 'SQ_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', + 182: 'SQ_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', + 183: 'SQ_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', + 184: 'SQ_PERF_SEL_UTCL1_LFIFO_FULL', + 185: 'SQ_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', + 186: 'SQ_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', + 187: 'SQ_PERF_SEL_DUMMY_END', + 255: 'SQ_PERF_SEL_DUMMY_LAST', + 256: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READY', + 257: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', + 258: 'SQC_PERF_SEL_ICACHE_INPUT_VALIDB', + 259: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READY', + 260: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', + 261: 'SQC_PERF_SEL_DCACHE_INPUT_VALIDB', + 262: 'SQC_PERF_SEL_TC_REQ', + 263: 'SQC_PERF_SEL_TC_INST_REQ', + 264: 'SQC_PERF_SEL_TC_DATA_READ_REQ', + 265: 'SQC_PERF_SEL_TC_DATA_WRITE_REQ', + 266: 'SQC_PERF_SEL_TC_DATA_ATOMIC_REQ', + 267: 'SQC_PERF_SEL_TC_STALL', + 268: 'SQC_PERF_SEL_TC_STARVE', + 269: 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', + 270: 'SQC_PERF_SEL_ICACHE_REQ', + 271: 'SQC_PERF_SEL_ICACHE_HITS', + 272: 'SQC_PERF_SEL_ICACHE_MISSES', + 273: 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', + 274: 'SQC_PERF_SEL_ICACHE_INVAL_INST', + 275: 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', + 276: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', + 277: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', + 278: 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', + 279: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO', + 280: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', + 281: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT', + 282: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO', + 283: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO', + 284: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF', + 285: 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 286: 'SQC_PERF_SEL_ICACHE_PREFETCH_1', + 287: 'SQC_PERF_SEL_ICACHE_PREFETCH_2', + 288: 'SQC_PERF_SEL_ICACHE_PREFETCH_FILTERED', + 289: 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', + 290: 'SQC_PERF_SEL_DCACHE_REQ', + 291: 'SQC_PERF_SEL_DCACHE_HITS', + 292: 'SQC_PERF_SEL_DCACHE_MISSES', + 293: 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', + 294: 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', + 295: 'SQC_PERF_SEL_DCACHE_MISS_EVICT_READ', + 296: 'SQC_PERF_SEL_DCACHE_WC_LRU_WRITE', + 297: 'SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE', + 298: 'SQC_PERF_SEL_DCACHE_ATOMIC', + 299: 'SQC_PERF_SEL_DCACHE_VOLATILE', + 300: 'SQC_PERF_SEL_DCACHE_INVAL_INST', + 301: 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', + 302: 'SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST', + 303: 'SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC', + 304: 'SQC_PERF_SEL_DCACHE_WB_INST', + 305: 'SQC_PERF_SEL_DCACHE_WB_ASYNC', + 306: 'SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST', + 307: 'SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC', + 308: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', + 309: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', + 310: 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', + 311: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', + 312: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', + 313: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT', + 314: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED', + 315: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE', + 316: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT', + 317: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH', + 318: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE', + 319: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO', + 320: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO', + 321: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF', + 322: 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 323: 'SQC_PERF_SEL_DCACHE_REQ_READ_1', + 324: 'SQC_PERF_SEL_DCACHE_REQ_READ_2', + 325: 'SQC_PERF_SEL_DCACHE_REQ_READ_4', + 326: 'SQC_PERF_SEL_DCACHE_REQ_READ_8', + 327: 'SQC_PERF_SEL_DCACHE_REQ_READ_16', + 328: 'SQC_PERF_SEL_DCACHE_REQ_TIME', + 329: 'SQC_PERF_SEL_DCACHE_REQ_WRITE_1', + 330: 'SQC_PERF_SEL_DCACHE_REQ_WRITE_2', + 331: 'SQC_PERF_SEL_DCACHE_REQ_WRITE_4', + 332: 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', + 333: 'SQC_PERF_SEL_SQ_DCACHE_REQS', + 334: 'SQC_PERF_SEL_DCACHE_FLAT_REQ', + 335: 'SQC_PERF_SEL_DCACHE_NONFLAT_REQ', + 336: 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', + 337: 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', + 338: 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', + 339: 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', + 340: 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', + 341: 'SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS', + 342: 'SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS', + 343: 'SQC_PERF_SEL_ICACHE_GATCL1_REQUEST', + 344: 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX', + 345: 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT', + 346: 'SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL', + 347: 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES', + 348: 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS', + 349: 'SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT', + 350: 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL', + 351: 'SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS', + 352: 'SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS', + 353: 'SQC_PERF_SEL_DCACHE_GATCL1_REQUEST', + 354: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX', + 355: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT', + 356: 'SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL', + 357: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES', + 358: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS', + 359: 'SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT', + 360: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL', + 361: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS', + 362: 'SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL', + 363: 'SQC_PERF_SEL_DUMMY_LAST', +} +SQ_PERF_SEL_NONE = 0 +SQ_PERF_SEL_ACCUM_PREV = 1 +SQ_PERF_SEL_CYCLES = 2 +SQ_PERF_SEL_BUSY_CYCLES = 3 +SQ_PERF_SEL_WAVES = 4 +SQ_PERF_SEL_LEVEL_WAVES = 5 +SQ_PERF_SEL_WAVES_EQ_64 = 6 +SQ_PERF_SEL_WAVES_LT_64 = 7 +SQ_PERF_SEL_WAVES_LT_48 = 8 +SQ_PERF_SEL_WAVES_LT_32 = 9 +SQ_PERF_SEL_WAVES_LT_16 = 10 +SQ_PERF_SEL_WAVES_CU = 11 +SQ_PERF_SEL_LEVEL_WAVES_CU = 12 +SQ_PERF_SEL_BUSY_CU_CYCLES = 13 +SQ_PERF_SEL_ITEMS = 14 +SQ_PERF_SEL_QUADS = 15 +SQ_PERF_SEL_EVENTS = 16 +SQ_PERF_SEL_SURF_SYNCS = 17 +SQ_PERF_SEL_TTRACE_REQS = 18 +SQ_PERF_SEL_TTRACE_INFLIGHT_REQS = 19 +SQ_PERF_SEL_TTRACE_STALL = 20 +SQ_PERF_SEL_MSG_CNTR = 21 +SQ_PERF_SEL_MSG_PERF = 22 +SQ_PERF_SEL_MSG_GSCNT = 23 +SQ_PERF_SEL_MSG_INTERRUPT = 24 +SQ_PERF_SEL_INSTS = 25 +SQ_PERF_SEL_INSTS_VALU = 26 +SQ_PERF_SEL_INSTS_VMEM_WR = 27 +SQ_PERF_SEL_INSTS_VMEM_RD = 28 +SQ_PERF_SEL_INSTS_VMEM = 29 +SQ_PERF_SEL_INSTS_SALU = 30 +SQ_PERF_SEL_INSTS_SMEM = 31 +SQ_PERF_SEL_INSTS_FLAT = 32 +SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY = 33 +SQ_PERF_SEL_INSTS_LDS = 34 +SQ_PERF_SEL_INSTS_GDS = 35 +SQ_PERF_SEL_INSTS_EXP = 36 +SQ_PERF_SEL_INSTS_EXP_GDS = 37 +SQ_PERF_SEL_INSTS_BRANCH = 38 +SQ_PERF_SEL_INSTS_SENDMSG = 39 +SQ_PERF_SEL_INSTS_VSKIPPED = 40 +SQ_PERF_SEL_INST_LEVEL_VMEM = 41 +SQ_PERF_SEL_INST_LEVEL_SMEM = 42 +SQ_PERF_SEL_INST_LEVEL_LDS = 43 +SQ_PERF_SEL_INST_LEVEL_GDS = 44 +SQ_PERF_SEL_INST_LEVEL_EXP = 45 +SQ_PERF_SEL_WAVE_CYCLES = 46 +SQ_PERF_SEL_WAVE_READY = 47 +SQ_PERF_SEL_WAIT_CNT_VM = 48 +SQ_PERF_SEL_WAIT_CNT_LGKM = 49 +SQ_PERF_SEL_WAIT_CNT_EXP = 50 +SQ_PERF_SEL_WAIT_CNT_ANY = 51 +SQ_PERF_SEL_WAIT_BARRIER = 52 +SQ_PERF_SEL_WAIT_EXP_ALLOC = 53 +SQ_PERF_SEL_WAIT_SLEEP = 54 +SQ_PERF_SEL_WAIT_SLEEP_XNACK = 55 +SQ_PERF_SEL_WAIT_OTHER = 56 +SQ_PERF_SEL_WAIT_ANY = 57 +SQ_PERF_SEL_WAIT_TTRACE = 58 +SQ_PERF_SEL_WAIT_IFETCH = 59 +SQ_PERF_SEL_WAIT_INST_ANY = 60 +SQ_PERF_SEL_WAIT_INST_VMEM = 61 +SQ_PERF_SEL_WAIT_INST_SCA = 62 +SQ_PERF_SEL_WAIT_INST_LDS = 63 +SQ_PERF_SEL_WAIT_INST_VALU = 64 +SQ_PERF_SEL_WAIT_INST_EXP_GDS = 65 +SQ_PERF_SEL_WAIT_INST_MISC = 66 +SQ_PERF_SEL_WAIT_INST_FLAT = 67 +SQ_PERF_SEL_ACTIVE_INST_ANY = 68 +SQ_PERF_SEL_ACTIVE_INST_VMEM = 69 +SQ_PERF_SEL_ACTIVE_INST_LDS = 70 +SQ_PERF_SEL_ACTIVE_INST_VALU = 71 +SQ_PERF_SEL_ACTIVE_INST_SCA = 72 +SQ_PERF_SEL_ACTIVE_INST_EXP_GDS = 73 +SQ_PERF_SEL_ACTIVE_INST_MISC = 74 +SQ_PERF_SEL_ACTIVE_INST_FLAT = 75 +SQ_PERF_SEL_INST_CYCLES_VMEM_WR = 76 +SQ_PERF_SEL_INST_CYCLES_VMEM_RD = 77 +SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR = 78 +SQ_PERF_SEL_INST_CYCLES_VMEM_DATA = 79 +SQ_PERF_SEL_INST_CYCLES_VMEM_CMD = 80 +SQ_PERF_SEL_INST_CYCLES_EXP = 81 +SQ_PERF_SEL_INST_CYCLES_GDS = 82 +SQ_PERF_SEL_INST_CYCLES_SMEM = 83 +SQ_PERF_SEL_INST_CYCLES_SALU = 84 +SQ_PERF_SEL_THREAD_CYCLES_VALU = 85 +SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX = 86 +SQ_PERF_SEL_IFETCH = 87 +SQ_PERF_SEL_IFETCH_LEVEL = 88 +SQ_PERF_SEL_CBRANCH_FORK = 89 +SQ_PERF_SEL_CBRANCH_FORK_SPLIT = 90 +SQ_PERF_SEL_VALU_LDS_DIRECT_RD = 91 +SQ_PERF_SEL_VALU_LDS_INTERP_OP = 92 +SQ_PERF_SEL_LDS_BANK_CONFLICT = 93 +SQ_PERF_SEL_LDS_ADDR_CONFLICT = 94 +SQ_PERF_SEL_LDS_UNALIGNED_STALL = 95 +SQ_PERF_SEL_LDS_MEM_VIOLATIONS = 96 +SQ_PERF_SEL_LDS_ATOMIC_RETURN = 97 +SQ_PERF_SEL_LDS_IDX_ACTIVE = 98 +SQ_PERF_SEL_VALU_DEP_STALL = 99 +SQ_PERF_SEL_VALU_STARVE = 100 +SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 101 +SQ_PERF_SEL_LDS_DATA_FIFO_FULL = 102 +SQ_PERF_SEL_LDS_CMD_FIFO_FULL = 103 +SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL = 104 +SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL = 105 +SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY = 106 +SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL = 107 +SQ_PERF_SEL_VALU_SRC_C_CONFLICT = 108 +SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT = 109 +SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT = 110 +SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT = 111 +SQ_PERF_SEL_LDS_SRC_CD_CONFLICT = 112 +SQ_PERF_SEL_SRC_CD_BUSY = 113 +SQ_PERF_SEL_PT_POWER_STALL = 114 +SQ_PERF_SEL_USER0 = 115 +SQ_PERF_SEL_USER1 = 116 +SQ_PERF_SEL_USER2 = 117 +SQ_PERF_SEL_USER3 = 118 +SQ_PERF_SEL_USER4 = 119 +SQ_PERF_SEL_USER5 = 120 +SQ_PERF_SEL_USER6 = 121 +SQ_PERF_SEL_USER7 = 122 +SQ_PERF_SEL_USER8 = 123 +SQ_PERF_SEL_USER9 = 124 +SQ_PERF_SEL_USER10 = 125 +SQ_PERF_SEL_USER11 = 126 +SQ_PERF_SEL_USER12 = 127 +SQ_PERF_SEL_USER13 = 128 +SQ_PERF_SEL_USER14 = 129 +SQ_PERF_SEL_USER15 = 130 +SQ_PERF_SEL_USER_LEVEL0 = 131 +SQ_PERF_SEL_USER_LEVEL1 = 132 +SQ_PERF_SEL_USER_LEVEL2 = 133 +SQ_PERF_SEL_USER_LEVEL3 = 134 +SQ_PERF_SEL_USER_LEVEL4 = 135 +SQ_PERF_SEL_USER_LEVEL5 = 136 +SQ_PERF_SEL_USER_LEVEL6 = 137 +SQ_PERF_SEL_USER_LEVEL7 = 138 +SQ_PERF_SEL_USER_LEVEL8 = 139 +SQ_PERF_SEL_USER_LEVEL9 = 140 +SQ_PERF_SEL_USER_LEVEL10 = 141 +SQ_PERF_SEL_USER_LEVEL11 = 142 +SQ_PERF_SEL_USER_LEVEL12 = 143 +SQ_PERF_SEL_USER_LEVEL13 = 144 +SQ_PERF_SEL_USER_LEVEL14 = 145 +SQ_PERF_SEL_USER_LEVEL15 = 146 +SQ_PERF_SEL_POWER_VALU = 147 +SQ_PERF_SEL_POWER_VALU0 = 148 +SQ_PERF_SEL_POWER_VALU1 = 149 +SQ_PERF_SEL_POWER_VALU2 = 150 +SQ_PERF_SEL_POWER_GPR_RD = 151 +SQ_PERF_SEL_POWER_GPR_WR = 152 +SQ_PERF_SEL_POWER_LDS_BUSY = 153 +SQ_PERF_SEL_POWER_ALU_BUSY = 154 +SQ_PERF_SEL_POWER_TEX_BUSY = 155 +SQ_PERF_SEL_ACCUM_PREV_HIRES = 156 +SQ_PERF_SEL_WAVES_RESTORED = 157 +SQ_PERF_SEL_WAVES_SAVED = 158 +SQ_PERF_SEL_INSTS_SMEM_NORM = 159 +SQ_PERF_SEL_ATC_INSTS_VMEM = 160 +SQ_PERF_SEL_ATC_INST_LEVEL_VMEM = 161 +SQ_PERF_SEL_ATC_XNACK_FIRST = 162 +SQ_PERF_SEL_ATC_XNACK_ALL = 163 +SQ_PERF_SEL_ATC_XNACK_FIFO_FULL = 164 +SQ_PERF_SEL_ATC_INSTS_SMEM = 165 +SQ_PERF_SEL_ATC_INST_LEVEL_SMEM = 166 +SQ_PERF_SEL_IFETCH_XNACK = 167 +SQ_PERF_SEL_TLB_SHOOTDOWN = 168 +SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES = 169 +SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY = 170 +SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY = 171 +SQ_PERF_SEL_INSTS_VMEM_REPLAY = 172 +SQ_PERF_SEL_INSTS_SMEM_REPLAY = 173 +SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY = 174 +SQ_PERF_SEL_INSTS_FLAT_REPLAY = 175 +SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY = 176 +SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY = 177 +SQ_PERF_SEL_UTCL1_TRANSLATION_MISS = 178 +SQ_PERF_SEL_UTCL1_PERMISSION_MISS = 179 +SQ_PERF_SEL_UTCL1_REQUEST = 180 +SQ_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 181 +SQ_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 182 +SQ_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 183 +SQ_PERF_SEL_UTCL1_LFIFO_FULL = 184 +SQ_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 185 +SQ_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 186 +SQ_PERF_SEL_DUMMY_END = 187 +SQ_PERF_SEL_DUMMY_LAST = 255 +SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 256 +SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 257 +SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 258 +SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 259 +SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 260 +SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 261 +SQC_PERF_SEL_TC_REQ = 262 +SQC_PERF_SEL_TC_INST_REQ = 263 +SQC_PERF_SEL_TC_DATA_READ_REQ = 264 +SQC_PERF_SEL_TC_DATA_WRITE_REQ = 265 +SQC_PERF_SEL_TC_DATA_ATOMIC_REQ = 266 +SQC_PERF_SEL_TC_STALL = 267 +SQC_PERF_SEL_TC_STARVE = 268 +SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 269 +SQC_PERF_SEL_ICACHE_REQ = 270 +SQC_PERF_SEL_ICACHE_HITS = 271 +SQC_PERF_SEL_ICACHE_MISSES = 272 +SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 273 +SQC_PERF_SEL_ICACHE_INVAL_INST = 274 +SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 275 +SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 276 +SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 277 +SQC_PERF_SEL_ICACHE_CACHE_STALLED = 278 +SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 279 +SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 280 +SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 281 +SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 282 +SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 283 +SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 284 +SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 285 +SQC_PERF_SEL_ICACHE_PREFETCH_1 = 286 +SQC_PERF_SEL_ICACHE_PREFETCH_2 = 287 +SQC_PERF_SEL_ICACHE_PREFETCH_FILTERED = 288 +SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 289 +SQC_PERF_SEL_DCACHE_REQ = 290 +SQC_PERF_SEL_DCACHE_HITS = 291 +SQC_PERF_SEL_DCACHE_MISSES = 292 +SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 293 +SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 294 +SQC_PERF_SEL_DCACHE_MISS_EVICT_READ = 295 +SQC_PERF_SEL_DCACHE_WC_LRU_WRITE = 296 +SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE = 297 +SQC_PERF_SEL_DCACHE_ATOMIC = 298 +SQC_PERF_SEL_DCACHE_VOLATILE = 299 +SQC_PERF_SEL_DCACHE_INVAL_INST = 300 +SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 301 +SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST = 302 +SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC = 303 +SQC_PERF_SEL_DCACHE_WB_INST = 304 +SQC_PERF_SEL_DCACHE_WB_ASYNC = 305 +SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST = 306 +SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC = 307 +SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 308 +SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 309 +SQC_PERF_SEL_DCACHE_CACHE_STALLED = 310 +SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 311 +SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 312 +SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT = 313 +SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED = 314 +SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE = 315 +SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT = 316 +SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH = 317 +SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE = 318 +SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 319 +SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 320 +SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 321 +SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 322 +SQC_PERF_SEL_DCACHE_REQ_READ_1 = 323 +SQC_PERF_SEL_DCACHE_REQ_READ_2 = 324 +SQC_PERF_SEL_DCACHE_REQ_READ_4 = 325 +SQC_PERF_SEL_DCACHE_REQ_READ_8 = 326 +SQC_PERF_SEL_DCACHE_REQ_READ_16 = 327 +SQC_PERF_SEL_DCACHE_REQ_TIME = 328 +SQC_PERF_SEL_DCACHE_REQ_WRITE_1 = 329 +SQC_PERF_SEL_DCACHE_REQ_WRITE_2 = 330 +SQC_PERF_SEL_DCACHE_REQ_WRITE_4 = 331 +SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 332 +SQC_PERF_SEL_SQ_DCACHE_REQS = 333 +SQC_PERF_SEL_DCACHE_FLAT_REQ = 334 +SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 335 +SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 336 +SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 337 +SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 338 +SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 339 +SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 340 +SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS = 341 +SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS = 342 +SQC_PERF_SEL_ICACHE_GATCL1_REQUEST = 343 +SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX = 344 +SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT = 345 +SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL = 346 +SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES = 347 +SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS = 348 +SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT = 349 +SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL = 350 +SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS = 351 +SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS = 352 +SQC_PERF_SEL_DCACHE_GATCL1_REQUEST = 353 +SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX = 354 +SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT = 355 +SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL = 356 +SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES = 357 +SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS = 358 +SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT = 359 +SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL = 360 +SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS = 361 +SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL = 362 +SQC_PERF_SEL_DUMMY_LAST = 363 +SQ_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_CAC_POWER_SEL' +SQ_CAC_POWER_SEL__enumvalues = { + 0: 'SQ_CAC_POWER_VALU', + 1: 'SQ_CAC_POWER_VALU0', + 2: 'SQ_CAC_POWER_VALU1', + 3: 'SQ_CAC_POWER_VALU2', + 4: 'SQ_CAC_POWER_GPR_RD', + 5: 'SQ_CAC_POWER_GPR_WR', + 6: 'SQ_CAC_POWER_LDS_BUSY', + 7: 'SQ_CAC_POWER_ALU_BUSY', + 8: 'SQ_CAC_POWER_TEX_BUSY', +} +SQ_CAC_POWER_VALU = 0 +SQ_CAC_POWER_VALU0 = 1 +SQ_CAC_POWER_VALU1 = 2 +SQ_CAC_POWER_VALU2 = 3 +SQ_CAC_POWER_GPR_RD = 4 +SQ_CAC_POWER_GPR_WR = 5 +SQ_CAC_POWER_LDS_BUSY = 6 +SQ_CAC_POWER_ALU_BUSY = 7 +SQ_CAC_POWER_TEX_BUSY = 8 +SQ_CAC_POWER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IND_CMD_CMD' +SQ_IND_CMD_CMD__enumvalues = { + 0: 'SQ_IND_CMD_CMD_NULL', + 1: 'SQ_IND_CMD_CMD_SETHALT', + 2: 'SQ_IND_CMD_CMD_SAVECTX', + 3: 'SQ_IND_CMD_CMD_KILL', + 4: 'SQ_IND_CMD_CMD_DEBUG', + 5: 'SQ_IND_CMD_CMD_TRAP', + 6: 'SQ_IND_CMD_CMD_SET_SPI_PRIO', + 7: 'SQ_IND_CMD_CMD_SETFATALHALT', +} +SQ_IND_CMD_CMD_NULL = 0 +SQ_IND_CMD_CMD_SETHALT = 1 +SQ_IND_CMD_CMD_SAVECTX = 2 +SQ_IND_CMD_CMD_KILL = 3 +SQ_IND_CMD_CMD_DEBUG = 4 +SQ_IND_CMD_CMD_TRAP = 5 +SQ_IND_CMD_CMD_SET_SPI_PRIO = 6 +SQ_IND_CMD_CMD_SETFATALHALT = 7 +SQ_IND_CMD_CMD = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IND_CMD_MODE' +SQ_IND_CMD_MODE__enumvalues = { + 0: 'SQ_IND_CMD_MODE_SINGLE', + 1: 'SQ_IND_CMD_MODE_BROADCAST', + 2: 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', + 3: 'SQ_IND_CMD_MODE_BROADCAST_PIPE', + 4: 'SQ_IND_CMD_MODE_BROADCAST_ME', +} +SQ_IND_CMD_MODE_SINGLE = 0 +SQ_IND_CMD_MODE_BROADCAST = 1 +SQ_IND_CMD_MODE_BROADCAST_QUEUE = 2 +SQ_IND_CMD_MODE_BROADCAST_PIPE = 3 +SQ_IND_CMD_MODE_BROADCAST_ME = 4 +SQ_IND_CMD_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_EDC_INFO_SOURCE' +SQ_EDC_INFO_SOURCE__enumvalues = { + 0: 'SQ_EDC_INFO_SOURCE_INVALID', + 1: 'SQ_EDC_INFO_SOURCE_INST', + 2: 'SQ_EDC_INFO_SOURCE_SGPR', + 3: 'SQ_EDC_INFO_SOURCE_VGPR', + 4: 'SQ_EDC_INFO_SOURCE_LDS', + 5: 'SQ_EDC_INFO_SOURCE_GDS', + 6: 'SQ_EDC_INFO_SOURCE_TA', +} +SQ_EDC_INFO_SOURCE_INVALID = 0 +SQ_EDC_INFO_SOURCE_INST = 1 +SQ_EDC_INFO_SOURCE_SGPR = 2 +SQ_EDC_INFO_SOURCE_VGPR = 3 +SQ_EDC_INFO_SOURCE_LDS = 4 +SQ_EDC_INFO_SOURCE_GDS = 5 +SQ_EDC_INFO_SOURCE_TA = 6 +SQ_EDC_INFO_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_ROUND_MODE' +SQ_ROUND_MODE__enumvalues = { + 0: 'SQ_ROUND_NEAREST_EVEN', + 1: 'SQ_ROUND_PLUS_INFINITY', + 2: 'SQ_ROUND_MINUS_INFINITY', + 3: 'SQ_ROUND_TO_ZERO', +} +SQ_ROUND_NEAREST_EVEN = 0 +SQ_ROUND_PLUS_INFINITY = 1 +SQ_ROUND_MINUS_INFINITY = 2 +SQ_ROUND_TO_ZERO = 3 +SQ_ROUND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_INTERRUPT_WORD_ENCODING' +SQ_INTERRUPT_WORD_ENCODING__enumvalues = { + 0: 'SQ_INTERRUPT_WORD_ENCODING_AUTO', + 1: 'SQ_INTERRUPT_WORD_ENCODING_INST', + 2: 'SQ_INTERRUPT_WORD_ENCODING_ERROR', +} +SQ_INTERRUPT_WORD_ENCODING_AUTO = 0 +SQ_INTERRUPT_WORD_ENCODING_INST = 1 +SQ_INTERRUPT_WORD_ENCODING_ERROR = 2 +SQ_INTERRUPT_WORD_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_SQ_EXPORT_RAT_INST' +ENUM_SQ_EXPORT_RAT_INST__enumvalues = { + 0: 'SQ_EXPORT_RAT_INST_NOP', + 1: 'SQ_EXPORT_RAT_INST_STORE_TYPED', + 2: 'SQ_EXPORT_RAT_INST_STORE_RAW', + 3: 'SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM', + 4: 'SQ_EXPORT_RAT_INST_CMPXCHG_INT', + 5: 'SQ_EXPORT_RAT_INST_CMPXCHG_FLT', + 6: 'SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM', + 7: 'SQ_EXPORT_RAT_INST_ADD', + 8: 'SQ_EXPORT_RAT_INST_SUB', + 9: 'SQ_EXPORT_RAT_INST_RSUB', + 10: 'SQ_EXPORT_RAT_INST_MIN_INT', + 11: 'SQ_EXPORT_RAT_INST_MIN_UINT', + 12: 'SQ_EXPORT_RAT_INST_MAX_INT', + 13: 'SQ_EXPORT_RAT_INST_MAX_UINT', + 14: 'SQ_EXPORT_RAT_INST_AND', + 15: 'SQ_EXPORT_RAT_INST_OR', + 16: 'SQ_EXPORT_RAT_INST_XOR', + 17: 'SQ_EXPORT_RAT_INST_MSKOR', + 18: 'SQ_EXPORT_RAT_INST_INC_UINT', + 19: 'SQ_EXPORT_RAT_INST_DEC_UINT', + 20: 'SQ_EXPORT_RAT_INST_STORE_DWORD', + 21: 'SQ_EXPORT_RAT_INST_STORE_SHORT', + 22: 'SQ_EXPORT_RAT_INST_STORE_BYTE', + 32: 'SQ_EXPORT_RAT_INST_NOP_RTN', + 34: 'SQ_EXPORT_RAT_INST_XCHG_RTN', + 35: 'SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN', + 36: 'SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN', + 37: 'SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN', + 38: 'SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN', + 39: 'SQ_EXPORT_RAT_INST_ADD_RTN', + 40: 'SQ_EXPORT_RAT_INST_SUB_RTN', + 41: 'SQ_EXPORT_RAT_INST_RSUB_RTN', + 42: 'SQ_EXPORT_RAT_INST_MIN_INT_RTN', + 43: 'SQ_EXPORT_RAT_INST_MIN_UINT_RTN', + 44: 'SQ_EXPORT_RAT_INST_MAX_INT_RTN', + 45: 'SQ_EXPORT_RAT_INST_MAX_UINT_RTN', + 46: 'SQ_EXPORT_RAT_INST_AND_RTN', + 47: 'SQ_EXPORT_RAT_INST_OR_RTN', + 48: 'SQ_EXPORT_RAT_INST_XOR_RTN', + 49: 'SQ_EXPORT_RAT_INST_MSKOR_RTN', + 50: 'SQ_EXPORT_RAT_INST_INC_UINT_RTN', + 51: 'SQ_EXPORT_RAT_INST_DEC_UINT_RTN', +} +SQ_EXPORT_RAT_INST_NOP = 0 +SQ_EXPORT_RAT_INST_STORE_TYPED = 1 +SQ_EXPORT_RAT_INST_STORE_RAW = 2 +SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 3 +SQ_EXPORT_RAT_INST_CMPXCHG_INT = 4 +SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 5 +SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 6 +SQ_EXPORT_RAT_INST_ADD = 7 +SQ_EXPORT_RAT_INST_SUB = 8 +SQ_EXPORT_RAT_INST_RSUB = 9 +SQ_EXPORT_RAT_INST_MIN_INT = 10 +SQ_EXPORT_RAT_INST_MIN_UINT = 11 +SQ_EXPORT_RAT_INST_MAX_INT = 12 +SQ_EXPORT_RAT_INST_MAX_UINT = 13 +SQ_EXPORT_RAT_INST_AND = 14 +SQ_EXPORT_RAT_INST_OR = 15 +SQ_EXPORT_RAT_INST_XOR = 16 +SQ_EXPORT_RAT_INST_MSKOR = 17 +SQ_EXPORT_RAT_INST_INC_UINT = 18 +SQ_EXPORT_RAT_INST_DEC_UINT = 19 +SQ_EXPORT_RAT_INST_STORE_DWORD = 20 +SQ_EXPORT_RAT_INST_STORE_SHORT = 21 +SQ_EXPORT_RAT_INST_STORE_BYTE = 22 +SQ_EXPORT_RAT_INST_NOP_RTN = 32 +SQ_EXPORT_RAT_INST_XCHG_RTN = 34 +SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 35 +SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 36 +SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 37 +SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 38 +SQ_EXPORT_RAT_INST_ADD_RTN = 39 +SQ_EXPORT_RAT_INST_SUB_RTN = 40 +SQ_EXPORT_RAT_INST_RSUB_RTN = 41 +SQ_EXPORT_RAT_INST_MIN_INT_RTN = 42 +SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 43 +SQ_EXPORT_RAT_INST_MAX_INT_RTN = 44 +SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 45 +SQ_EXPORT_RAT_INST_AND_RTN = 46 +SQ_EXPORT_RAT_INST_OR_RTN = 47 +SQ_EXPORT_RAT_INST_XOR_RTN = 48 +SQ_EXPORT_RAT_INST_MSKOR_RTN = 49 +SQ_EXPORT_RAT_INST_INC_UINT_RTN = 50 +SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 51 +ENUM_SQ_EXPORT_RAT_INST = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IBUF_ST' +SQ_IBUF_ST__enumvalues = { + 0: 'SQ_IBUF_IB_IDLE', + 1: 'SQ_IBUF_IB_INI_WAIT_GNT', + 2: 'SQ_IBUF_IB_INI_WAIT_DRET', + 3: 'SQ_IBUF_IB_LE_4DW', + 4: 'SQ_IBUF_IB_WAIT_DRET', + 5: 'SQ_IBUF_IB_EMPTY_WAIT_DRET', + 6: 'SQ_IBUF_IB_DRET', + 7: 'SQ_IBUF_IB_EMPTY_WAIT_GNT', +} +SQ_IBUF_IB_IDLE = 0 +SQ_IBUF_IB_INI_WAIT_GNT = 1 +SQ_IBUF_IB_INI_WAIT_DRET = 2 +SQ_IBUF_IB_LE_4DW = 3 +SQ_IBUF_IB_WAIT_DRET = 4 +SQ_IBUF_IB_EMPTY_WAIT_DRET = 5 +SQ_IBUF_IB_DRET = 6 +SQ_IBUF_IB_EMPTY_WAIT_GNT = 7 +SQ_IBUF_ST = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_INST_STR_ST' +SQ_INST_STR_ST__enumvalues = { + 0: 'SQ_INST_STR_IB_WAVE_NORML', + 1: 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', + 2: 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', + 3: 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', + 4: 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST0', + 5: 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST1', + 6: 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', + 7: 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', +} +SQ_INST_STR_IB_WAVE_NORML = 0 +SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 1 +SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 2 +SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 3 +SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 4 +SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 5 +SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 6 +SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 7 +SQ_INST_STR_ST = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_IB_ECC_ST' +SQ_WAVE_IB_ECC_ST__enumvalues = { + 0: 'SQ_WAVE_IB_ECC_CLEAN', + 1: 'SQ_WAVE_IB_ECC_ERR_CONTINUE', + 2: 'SQ_WAVE_IB_ECC_ERR_HALT', + 3: 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', +} +SQ_WAVE_IB_ECC_CLEAN = 0 +SQ_WAVE_IB_ECC_ERR_CONTINUE = 1 +SQ_WAVE_IB_ECC_ERR_HALT = 2 +SQ_WAVE_IB_ECC_WITH_ERR_MSG = 3 +SQ_WAVE_IB_ECC_ST = ctypes.c_uint32 # enum + +# values for enumeration 'SH_MEM_ADDRESS_MODE' +SH_MEM_ADDRESS_MODE__enumvalues = { + 0: 'SH_MEM_ADDRESS_MODE_64', + 1: 'SH_MEM_ADDRESS_MODE_32', +} +SH_MEM_ADDRESS_MODE_64 = 0 +SH_MEM_ADDRESS_MODE_32 = 1 +SH_MEM_ADDRESS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SH_MEM_ALIGNMENT_MODE' +SH_MEM_ALIGNMENT_MODE__enumvalues = { + 0: 'SH_MEM_ALIGNMENT_MODE_DWORD', + 1: 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', + 2: 'SH_MEM_ALIGNMENT_MODE_STRICT', + 3: 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', +} +SH_MEM_ALIGNMENT_MODE_DWORD = 0 +SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 1 +SH_MEM_ALIGNMENT_MODE_STRICT = 2 +SH_MEM_ALIGNMENT_MODE_UNALIGNED = 3 +SH_MEM_ALIGNMENT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX' +SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX__enumvalues = { + 24: 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC', + 25: 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE', +} +SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC = 24 +SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE = 25 +SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_LB_CTR_SEL_VALUES' +SQ_LB_CTR_SEL_VALUES__enumvalues = { + 0: 'SQ_LB_CTR_SEL_ALU_CYCLES', + 1: 'SQ_LB_CTR_SEL_ALU_STALLS', + 2: 'SQ_LB_CTR_SEL_TEX_CYCLES', + 3: 'SQ_LB_CTR_SEL_TEX_STALLS', + 4: 'SQ_LB_CTR_SEL_SALU_CYCLES', + 5: 'SQ_LB_CTR_SEL_SCALAR_STALLS', + 6: 'SQ_LB_CTR_SEL_SMEM_CYCLES', + 7: 'SQ_LB_CTR_SEL_ICACHE_STALLS', + 8: 'SQ_LB_CTR_SEL_DCACHE_STALLS', + 9: 'SQ_LB_CTR_SEL_RESERVED0', + 10: 'SQ_LB_CTR_SEL_RESERVED1', + 11: 'SQ_LB_CTR_SEL_RESERVED2', + 12: 'SQ_LB_CTR_SEL_RESERVED3', + 13: 'SQ_LB_CTR_SEL_RESERVED4', + 14: 'SQ_LB_CTR_SEL_RESERVED5', + 15: 'SQ_LB_CTR_SEL_RESERVED6', +} +SQ_LB_CTR_SEL_ALU_CYCLES = 0 +SQ_LB_CTR_SEL_ALU_STALLS = 1 +SQ_LB_CTR_SEL_TEX_CYCLES = 2 +SQ_LB_CTR_SEL_TEX_STALLS = 3 +SQ_LB_CTR_SEL_SALU_CYCLES = 4 +SQ_LB_CTR_SEL_SCALAR_STALLS = 5 +SQ_LB_CTR_SEL_SMEM_CYCLES = 6 +SQ_LB_CTR_SEL_ICACHE_STALLS = 7 +SQ_LB_CTR_SEL_DCACHE_STALLS = 8 +SQ_LB_CTR_SEL_RESERVED0 = 9 +SQ_LB_CTR_SEL_RESERVED1 = 10 +SQ_LB_CTR_SEL_RESERVED2 = 11 +SQ_LB_CTR_SEL_RESERVED3 = 12 +SQ_LB_CTR_SEL_RESERVED4 = 13 +SQ_LB_CTR_SEL_RESERVED5 = 14 +SQ_LB_CTR_SEL_RESERVED6 = 15 +SQ_LB_CTR_SEL_VALUES = ctypes.c_uint32 # enum + +# values for enumeration 'CSDATA_TYPE' +CSDATA_TYPE__enumvalues = { + 0: 'CSDATA_TYPE_TG', + 1: 'CSDATA_TYPE_STATE', + 2: 'CSDATA_TYPE_EVENT', + 3: 'CSDATA_TYPE_PRIVATE', +} +CSDATA_TYPE_TG = 0 +CSDATA_TYPE_STATE = 1 +CSDATA_TYPE_EVENT = 2 +CSDATA_TYPE_PRIVATE = 3 +CSDATA_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_OUT_PRIM_TYPE' +VGT_OUT_PRIM_TYPE__enumvalues = { + 0: 'VGT_OUT_POINT', + 1: 'VGT_OUT_LINE', + 2: 'VGT_OUT_TRI', + 3: 'VGT_OUT_RECT_V0', + 4: 'VGT_OUT_RECT_V1', + 5: 'VGT_OUT_RECT_V2', + 6: 'VGT_OUT_RECT_V3', + 7: 'VGT_OUT_2D_RECT', + 8: 'VGT_TE_QUAD', + 9: 'VGT_TE_PRIM_INDEX_LINE', + 10: 'VGT_TE_PRIM_INDEX_TRI', + 11: 'VGT_TE_PRIM_INDEX_QUAD', + 12: 'VGT_OUT_LINE_ADJ', + 13: 'VGT_OUT_TRI_ADJ', + 14: 'VGT_OUT_PATCH', +} +VGT_OUT_POINT = 0 +VGT_OUT_LINE = 1 +VGT_OUT_TRI = 2 +VGT_OUT_RECT_V0 = 3 +VGT_OUT_RECT_V1 = 4 +VGT_OUT_RECT_V2 = 5 +VGT_OUT_RECT_V3 = 6 +VGT_OUT_2D_RECT = 7 +VGT_TE_QUAD = 8 +VGT_TE_PRIM_INDEX_LINE = 9 +VGT_TE_PRIM_INDEX_TRI = 10 +VGT_TE_PRIM_INDEX_QUAD = 11 +VGT_OUT_LINE_ADJ = 12 +VGT_OUT_TRI_ADJ = 13 +VGT_OUT_PATCH = 14 +VGT_OUT_PRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_PRIM_TYPE' +VGT_DI_PRIM_TYPE__enumvalues = { + 0: 'DI_PT_NONE', + 1: 'DI_PT_POINTLIST', + 2: 'DI_PT_LINELIST', + 3: 'DI_PT_LINESTRIP', + 4: 'DI_PT_TRILIST', + 5: 'DI_PT_TRIFAN', + 6: 'DI_PT_TRISTRIP', + 7: 'DI_PT_2D_RECTANGLE', + 8: 'DI_PT_UNUSED_1', + 9: 'DI_PT_PATCH', + 10: 'DI_PT_LINELIST_ADJ', + 11: 'DI_PT_LINESTRIP_ADJ', + 12: 'DI_PT_TRILIST_ADJ', + 13: 'DI_PT_TRISTRIP_ADJ', + 14: 'DI_PT_UNUSED_3', + 15: 'DI_PT_UNUSED_4', + 16: 'DI_PT_TRI_WITH_WFLAGS', + 17: 'DI_PT_RECTLIST', + 18: 'DI_PT_LINELOOP', + 19: 'DI_PT_QUADLIST', + 20: 'DI_PT_QUADSTRIP', + 21: 'DI_PT_POLYGON', +} +DI_PT_NONE = 0 +DI_PT_POINTLIST = 1 +DI_PT_LINELIST = 2 +DI_PT_LINESTRIP = 3 +DI_PT_TRILIST = 4 +DI_PT_TRIFAN = 5 +DI_PT_TRISTRIP = 6 +DI_PT_2D_RECTANGLE = 7 +DI_PT_UNUSED_1 = 8 +DI_PT_PATCH = 9 +DI_PT_LINELIST_ADJ = 10 +DI_PT_LINESTRIP_ADJ = 11 +DI_PT_TRILIST_ADJ = 12 +DI_PT_TRISTRIP_ADJ = 13 +DI_PT_UNUSED_3 = 14 +DI_PT_UNUSED_4 = 15 +DI_PT_TRI_WITH_WFLAGS = 16 +DI_PT_RECTLIST = 17 +DI_PT_LINELOOP = 18 +DI_PT_QUADLIST = 19 +DI_PT_QUADSTRIP = 20 +DI_PT_POLYGON = 21 +VGT_DI_PRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_SOURCE_SELECT' +VGT_DI_SOURCE_SELECT__enumvalues = { + 0: 'DI_SRC_SEL_DMA', + 1: 'DI_SRC_SEL_IMMEDIATE', + 2: 'DI_SRC_SEL_AUTO_INDEX', + 3: 'DI_SRC_SEL_RESERVED', +} +DI_SRC_SEL_DMA = 0 +DI_SRC_SEL_IMMEDIATE = 1 +DI_SRC_SEL_AUTO_INDEX = 2 +DI_SRC_SEL_RESERVED = 3 +VGT_DI_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_MAJOR_MODE_SELECT' +VGT_DI_MAJOR_MODE_SELECT__enumvalues = { + 0: 'DI_MAJOR_MODE_0', + 1: 'DI_MAJOR_MODE_1', +} +DI_MAJOR_MODE_0 = 0 +DI_MAJOR_MODE_1 = 1 +VGT_DI_MAJOR_MODE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_INDEX_SIZE' +VGT_DI_INDEX_SIZE__enumvalues = { + 0: 'DI_INDEX_SIZE_16_BIT', + 1: 'DI_INDEX_SIZE_32_BIT', + 2: 'DI_INDEX_SIZE_8_BIT', +} +DI_INDEX_SIZE_16_BIT = 0 +DI_INDEX_SIZE_32_BIT = 1 +DI_INDEX_SIZE_8_BIT = 2 +VGT_DI_INDEX_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_EVENT_TYPE' +VGT_EVENT_TYPE__enumvalues = { + 0: 'Reserved_0x00', + 1: 'SAMPLE_STREAMOUTSTATS1', + 2: 'SAMPLE_STREAMOUTSTATS2', + 3: 'SAMPLE_STREAMOUTSTATS3', + 4: 'CACHE_FLUSH_TS', + 5: 'CONTEXT_DONE', + 6: 'CACHE_FLUSH', + 7: 'CS_PARTIAL_FLUSH', + 8: 'VGT_STREAMOUT_SYNC', + 9: 'Reserved_0x09', + 10: 'VGT_STREAMOUT_RESET', + 11: 'END_OF_PIPE_INCR_DE', + 12: 'END_OF_PIPE_IB_END', + 13: 'RST_PIX_CNT', + 14: 'BREAK_BATCH', + 15: 'VS_PARTIAL_FLUSH', + 16: 'PS_PARTIAL_FLUSH', + 17: 'FLUSH_HS_OUTPUT', + 18: 'FLUSH_DFSM', + 19: 'RESET_TO_LOWEST_VGT', + 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', + 21: 'ZPASS_DONE', + 22: 'CACHE_FLUSH_AND_INV_EVENT', + 23: 'PERFCOUNTER_START', + 24: 'PERFCOUNTER_STOP', + 25: 'PIPELINESTAT_START', + 26: 'PIPELINESTAT_STOP', + 27: 'PERFCOUNTER_SAMPLE', + 28: 'Available_0x1c', + 29: 'Available_0x1d', + 30: 'SAMPLE_PIPELINESTAT', + 31: 'SO_VGTSTREAMOUT_FLUSH', + 32: 'SAMPLE_STREAMOUTSTATS', + 33: 'RESET_VTX_CNT', + 34: 'BLOCK_CONTEXT_DONE', + 35: 'CS_CONTEXT_DONE', + 36: 'VGT_FLUSH', + 37: 'TGID_ROLLOVER', + 38: 'SQ_NON_EVENT', + 39: 'SC_SEND_DB_VPZ', + 40: 'BOTTOM_OF_PIPE_TS', + 41: 'FLUSH_SX_TS', + 42: 'DB_CACHE_FLUSH_AND_INV', + 43: 'FLUSH_AND_INV_DB_DATA_TS', + 44: 'FLUSH_AND_INV_DB_META', + 45: 'FLUSH_AND_INV_CB_DATA_TS', + 46: 'FLUSH_AND_INV_CB_META', + 47: 'CS_DONE', + 48: 'PS_DONE', + 49: 'FLUSH_AND_INV_CB_PIXEL_DATA', + 50: 'SX_CB_RAT_ACK_REQUEST', + 51: 'THREAD_TRACE_START', + 52: 'THREAD_TRACE_STOP', + 53: 'THREAD_TRACE_MARKER', + 54: 'THREAD_TRACE_FLUSH', + 55: 'THREAD_TRACE_FINISH', + 56: 'PIXEL_PIPE_STAT_CONTROL', + 57: 'PIXEL_PIPE_STAT_DUMP', + 58: 'PIXEL_PIPE_STAT_RESET', + 59: 'CONTEXT_SUSPEND', + 60: 'OFFCHIP_HS_DEALLOC', + 61: 'ENABLE_NGG_PIPELINE', + 62: 'ENABLE_LEGACY_PIPELINE', + 63: 'Reserved_0x3f', +} +Reserved_0x00 = 0 +SAMPLE_STREAMOUTSTATS1 = 1 +SAMPLE_STREAMOUTSTATS2 = 2 +SAMPLE_STREAMOUTSTATS3 = 3 +CACHE_FLUSH_TS = 4 +CONTEXT_DONE = 5 +CACHE_FLUSH = 6 +CS_PARTIAL_FLUSH = 7 +VGT_STREAMOUT_SYNC = 8 +Reserved_0x09 = 9 +VGT_STREAMOUT_RESET = 10 +END_OF_PIPE_INCR_DE = 11 +END_OF_PIPE_IB_END = 12 +RST_PIX_CNT = 13 +BREAK_BATCH = 14 +VS_PARTIAL_FLUSH = 15 +PS_PARTIAL_FLUSH = 16 +FLUSH_HS_OUTPUT = 17 +FLUSH_DFSM = 18 +RESET_TO_LOWEST_VGT = 19 +CACHE_FLUSH_AND_INV_TS_EVENT = 20 +ZPASS_DONE = 21 +CACHE_FLUSH_AND_INV_EVENT = 22 +PERFCOUNTER_START = 23 +PERFCOUNTER_STOP = 24 +PIPELINESTAT_START = 25 +PIPELINESTAT_STOP = 26 +PERFCOUNTER_SAMPLE = 27 +Available_0x1c = 28 +Available_0x1d = 29 +SAMPLE_PIPELINESTAT = 30 +SO_VGTSTREAMOUT_FLUSH = 31 +SAMPLE_STREAMOUTSTATS = 32 +RESET_VTX_CNT = 33 +BLOCK_CONTEXT_DONE = 34 +CS_CONTEXT_DONE = 35 +VGT_FLUSH = 36 +TGID_ROLLOVER = 37 +SQ_NON_EVENT = 38 +SC_SEND_DB_VPZ = 39 +BOTTOM_OF_PIPE_TS = 40 +FLUSH_SX_TS = 41 +DB_CACHE_FLUSH_AND_INV = 42 +FLUSH_AND_INV_DB_DATA_TS = 43 +FLUSH_AND_INV_DB_META = 44 +FLUSH_AND_INV_CB_DATA_TS = 45 +FLUSH_AND_INV_CB_META = 46 +CS_DONE = 47 +PS_DONE = 48 +FLUSH_AND_INV_CB_PIXEL_DATA = 49 +SX_CB_RAT_ACK_REQUEST = 50 +THREAD_TRACE_START = 51 +THREAD_TRACE_STOP = 52 +THREAD_TRACE_MARKER = 53 +THREAD_TRACE_FLUSH = 54 +THREAD_TRACE_FINISH = 55 +PIXEL_PIPE_STAT_CONTROL = 56 +PIXEL_PIPE_STAT_DUMP = 57 +PIXEL_PIPE_STAT_RESET = 58 +CONTEXT_SUSPEND = 59 +OFFCHIP_HS_DEALLOC = 60 +ENABLE_NGG_PIPELINE = 61 +ENABLE_LEGACY_PIPELINE = 62 +Reserved_0x3f = 63 +VGT_EVENT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DMA_SWAP_MODE' +VGT_DMA_SWAP_MODE__enumvalues = { + 0: 'VGT_DMA_SWAP_NONE', + 1: 'VGT_DMA_SWAP_16_BIT', + 2: 'VGT_DMA_SWAP_32_BIT', + 3: 'VGT_DMA_SWAP_WORD', +} +VGT_DMA_SWAP_NONE = 0 +VGT_DMA_SWAP_16_BIT = 1 +VGT_DMA_SWAP_32_BIT = 2 +VGT_DMA_SWAP_WORD = 3 +VGT_DMA_SWAP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_INDEX_TYPE_MODE' +VGT_INDEX_TYPE_MODE__enumvalues = { + 0: 'VGT_INDEX_16', + 1: 'VGT_INDEX_32', + 2: 'VGT_INDEX_8', +} +VGT_INDEX_16 = 0 +VGT_INDEX_32 = 1 +VGT_INDEX_8 = 2 +VGT_INDEX_TYPE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DMA_BUF_TYPE' +VGT_DMA_BUF_TYPE__enumvalues = { + 0: 'VGT_DMA_BUF_MEM', + 1: 'VGT_DMA_BUF_RING', + 2: 'VGT_DMA_BUF_SETUP', + 3: 'VGT_DMA_PTR_UPDATE', +} +VGT_DMA_BUF_MEM = 0 +VGT_DMA_BUF_RING = 1 +VGT_DMA_BUF_SETUP = 2 +VGT_DMA_PTR_UPDATE = 3 +VGT_DMA_BUF_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_OUTPATH_SELECT' +VGT_OUTPATH_SELECT__enumvalues = { + 0: 'VGT_OUTPATH_VTX_REUSE', + 1: 'VGT_OUTPATH_TESS_EN', + 2: 'VGT_OUTPATH_PASSTHRU', + 3: 'VGT_OUTPATH_GS_BLOCK', + 4: 'VGT_OUTPATH_HS_BLOCK', + 5: 'VGT_OUTPATH_PRIM_GEN', +} +VGT_OUTPATH_VTX_REUSE = 0 +VGT_OUTPATH_TESS_EN = 1 +VGT_OUTPATH_PASSTHRU = 2 +VGT_OUTPATH_GS_BLOCK = 3 +VGT_OUTPATH_HS_BLOCK = 4 +VGT_OUTPATH_PRIM_GEN = 5 +VGT_OUTPATH_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GRP_PRIM_TYPE' +VGT_GRP_PRIM_TYPE__enumvalues = { + 0: 'VGT_GRP_3D_POINT', + 1: 'VGT_GRP_3D_LINE', + 2: 'VGT_GRP_3D_TRI', + 3: 'VGT_GRP_3D_RECT', + 4: 'VGT_GRP_3D_QUAD', + 5: 'VGT_GRP_2D_COPY_RECT_V0', + 6: 'VGT_GRP_2D_COPY_RECT_V1', + 7: 'VGT_GRP_2D_COPY_RECT_V2', + 8: 'VGT_GRP_2D_COPY_RECT_V3', + 9: 'VGT_GRP_2D_FILL_RECT', + 10: 'VGT_GRP_2D_LINE', + 11: 'VGT_GRP_2D_TRI', + 12: 'VGT_GRP_PRIM_INDEX_LINE', + 13: 'VGT_GRP_PRIM_INDEX_TRI', + 14: 'VGT_GRP_PRIM_INDEX_QUAD', + 15: 'VGT_GRP_3D_LINE_ADJ', + 16: 'VGT_GRP_3D_TRI_ADJ', + 17: 'VGT_GRP_3D_PATCH', + 18: 'VGT_GRP_2D_RECT', +} +VGT_GRP_3D_POINT = 0 +VGT_GRP_3D_LINE = 1 +VGT_GRP_3D_TRI = 2 +VGT_GRP_3D_RECT = 3 +VGT_GRP_3D_QUAD = 4 +VGT_GRP_2D_COPY_RECT_V0 = 5 +VGT_GRP_2D_COPY_RECT_V1 = 6 +VGT_GRP_2D_COPY_RECT_V2 = 7 +VGT_GRP_2D_COPY_RECT_V3 = 8 +VGT_GRP_2D_FILL_RECT = 9 +VGT_GRP_2D_LINE = 10 +VGT_GRP_2D_TRI = 11 +VGT_GRP_PRIM_INDEX_LINE = 12 +VGT_GRP_PRIM_INDEX_TRI = 13 +VGT_GRP_PRIM_INDEX_QUAD = 14 +VGT_GRP_3D_LINE_ADJ = 15 +VGT_GRP_3D_TRI_ADJ = 16 +VGT_GRP_3D_PATCH = 17 +VGT_GRP_2D_RECT = 18 +VGT_GRP_PRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GRP_PRIM_ORDER' +VGT_GRP_PRIM_ORDER__enumvalues = { + 0: 'VGT_GRP_LIST', + 1: 'VGT_GRP_STRIP', + 2: 'VGT_GRP_FAN', + 3: 'VGT_GRP_LOOP', + 4: 'VGT_GRP_POLYGON', +} +VGT_GRP_LIST = 0 +VGT_GRP_STRIP = 1 +VGT_GRP_FAN = 2 +VGT_GRP_LOOP = 3 +VGT_GRP_POLYGON = 4 +VGT_GRP_PRIM_ORDER = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GROUP_CONV_SEL' +VGT_GROUP_CONV_SEL__enumvalues = { + 0: 'VGT_GRP_INDEX_16', + 1: 'VGT_GRP_INDEX_32', + 2: 'VGT_GRP_UINT_16', + 3: 'VGT_GRP_UINT_32', + 4: 'VGT_GRP_SINT_16', + 5: 'VGT_GRP_SINT_32', + 6: 'VGT_GRP_FLOAT_32', + 7: 'VGT_GRP_AUTO_PRIM', + 8: 'VGT_GRP_FIX_1_23_TO_FLOAT', +} +VGT_GRP_INDEX_16 = 0 +VGT_GRP_INDEX_32 = 1 +VGT_GRP_UINT_16 = 2 +VGT_GRP_UINT_32 = 3 +VGT_GRP_SINT_16 = 4 +VGT_GRP_SINT_32 = 5 +VGT_GRP_FLOAT_32 = 6 +VGT_GRP_AUTO_PRIM = 7 +VGT_GRP_FIX_1_23_TO_FLOAT = 8 +VGT_GROUP_CONV_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GS_MODE_TYPE' +VGT_GS_MODE_TYPE__enumvalues = { + 0: 'GS_OFF', + 1: 'GS_SCENARIO_A', + 2: 'GS_SCENARIO_B', + 3: 'GS_SCENARIO_G', + 4: 'GS_SCENARIO_C', + 5: 'SPRITE_EN', +} +GS_OFF = 0 +GS_SCENARIO_A = 1 +GS_SCENARIO_B = 2 +GS_SCENARIO_G = 3 +GS_SCENARIO_C = 4 +SPRITE_EN = 5 +VGT_GS_MODE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GS_CUT_MODE' +VGT_GS_CUT_MODE__enumvalues = { + 0: 'GS_CUT_1024', + 1: 'GS_CUT_512', + 2: 'GS_CUT_256', + 3: 'GS_CUT_128', +} +GS_CUT_1024 = 0 +GS_CUT_512 = 1 +GS_CUT_256 = 2 +GS_CUT_128 = 3 +VGT_GS_CUT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GS_OUTPRIM_TYPE' +VGT_GS_OUTPRIM_TYPE__enumvalues = { + 0: 'POINTLIST', + 1: 'LINESTRIP', + 2: 'TRISTRIP', + 3: 'RECTLIST', +} +POINTLIST = 0 +LINESTRIP = 1 +TRISTRIP = 2 +RECTLIST = 3 +VGT_GS_OUTPRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_CACHE_INVALID_MODE' +VGT_CACHE_INVALID_MODE__enumvalues = { + 0: 'VC_ONLY', + 1: 'TC_ONLY', + 2: 'VC_AND_TC', +} +VC_ONLY = 0 +TC_ONLY = 1 +VC_AND_TC = 2 +VGT_CACHE_INVALID_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TESS_TYPE' +VGT_TESS_TYPE__enumvalues = { + 0: 'TESS_ISOLINE', + 1: 'TESS_TRIANGLE', + 2: 'TESS_QUAD', +} +TESS_ISOLINE = 0 +TESS_TRIANGLE = 1 +TESS_QUAD = 2 +VGT_TESS_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TESS_PARTITION' +VGT_TESS_PARTITION__enumvalues = { + 0: 'PART_INTEGER', + 1: 'PART_POW2', + 2: 'PART_FRAC_ODD', + 3: 'PART_FRAC_EVEN', +} +PART_INTEGER = 0 +PART_POW2 = 1 +PART_FRAC_ODD = 2 +PART_FRAC_EVEN = 3 +VGT_TESS_PARTITION = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TESS_TOPOLOGY' +VGT_TESS_TOPOLOGY__enumvalues = { + 0: 'OUTPUT_POINT', + 1: 'OUTPUT_LINE', + 2: 'OUTPUT_TRIANGLE_CW', + 3: 'OUTPUT_TRIANGLE_CCW', +} +OUTPUT_POINT = 0 +OUTPUT_LINE = 1 +OUTPUT_TRIANGLE_CW = 2 +OUTPUT_TRIANGLE_CCW = 3 +VGT_TESS_TOPOLOGY = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_RDREQ_POLICY' +VGT_RDREQ_POLICY__enumvalues = { + 0: 'VGT_POLICY_LRU', + 1: 'VGT_POLICY_STREAM', +} +VGT_POLICY_LRU = 0 +VGT_POLICY_STREAM = 1 +VGT_RDREQ_POLICY = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DIST_MODE' +VGT_DIST_MODE__enumvalues = { + 0: 'NO_DIST', + 1: 'PATCHES', + 2: 'DONUTS', + 3: 'TRAPEZOIDS', +} +NO_DIST = 0 +PATCHES = 1 +DONUTS = 2 +TRAPEZOIDS = 3 +VGT_DIST_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_LS_EN' +VGT_STAGES_LS_EN__enumvalues = { + 0: 'LS_STAGE_OFF', + 1: 'LS_STAGE_ON', + 2: 'CS_STAGE_ON', + 3: 'RESERVED_LS', +} +LS_STAGE_OFF = 0 +LS_STAGE_ON = 1 +CS_STAGE_ON = 2 +RESERVED_LS = 3 +VGT_STAGES_LS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_HS_EN' +VGT_STAGES_HS_EN__enumvalues = { + 0: 'HS_STAGE_OFF', + 1: 'HS_STAGE_ON', +} +HS_STAGE_OFF = 0 +HS_STAGE_ON = 1 +VGT_STAGES_HS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_ES_EN' +VGT_STAGES_ES_EN__enumvalues = { + 0: 'ES_STAGE_OFF', + 1: 'ES_STAGE_DS', + 2: 'ES_STAGE_REAL', + 3: 'RESERVED_ES', +} +ES_STAGE_OFF = 0 +ES_STAGE_DS = 1 +ES_STAGE_REAL = 2 +RESERVED_ES = 3 +VGT_STAGES_ES_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_GS_EN' +VGT_STAGES_GS_EN__enumvalues = { + 0: 'GS_STAGE_OFF', + 1: 'GS_STAGE_ON', +} +GS_STAGE_OFF = 0 +GS_STAGE_ON = 1 +VGT_STAGES_GS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_VS_EN' +VGT_STAGES_VS_EN__enumvalues = { + 0: 'VS_STAGE_REAL', + 1: 'VS_STAGE_DS', + 2: 'VS_STAGE_COPY_SHADER', + 3: 'RESERVED_VS', +} +VS_STAGE_REAL = 0 +VS_STAGE_DS = 1 +VS_STAGE_COPY_SHADER = 2 +RESERVED_VS = 3 +VGT_STAGES_VS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_PERFCOUNT_SELECT' +VGT_PERFCOUNT_SELECT__enumvalues = { + 0: 'vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE', + 1: 'vgt_perf_VGT_SPI_ESVERT_VALID', + 2: 'vgt_perf_VGT_SPI_ESVERT_EOV', + 3: 'vgt_perf_VGT_SPI_ESVERT_STALLED', + 4: 'vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY', + 5: 'vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE', + 6: 'vgt_perf_VGT_SPI_ESVERT_STATIC', + 7: 'vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT', + 8: 'vgt_perf_VGT_SPI_ESTHREAD_SEND', + 9: 'vgt_perf_VGT_SPI_GSPRIM_VALID', + 10: 'vgt_perf_VGT_SPI_GSPRIM_EOV', + 11: 'vgt_perf_VGT_SPI_GSPRIM_CONT', + 12: 'vgt_perf_VGT_SPI_GSPRIM_STALLED', + 13: 'vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY', + 14: 'vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE', + 15: 'vgt_perf_VGT_SPI_GSPRIM_STATIC', + 16: 'vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE', + 17: 'vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT', + 18: 'vgt_perf_VGT_SPI_GSTHREAD_SEND', + 19: 'vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE', + 20: 'vgt_perf_VGT_SPI_VSVERT_SEND', + 21: 'vgt_perf_VGT_SPI_VSVERT_EOV', + 22: 'vgt_perf_VGT_SPI_VSVERT_STALLED', + 23: 'vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY', + 24: 'vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE', + 25: 'vgt_perf_VGT_SPI_VSVERT_STATIC', + 26: 'vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT', + 27: 'vgt_perf_VGT_SPI_VSTHREAD_SEND', + 28: 'vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE', + 29: 'vgt_perf_VGT_PA_CLIPV_SEND', + 30: 'vgt_perf_VGT_PA_CLIPV_FIRSTVERT', + 31: 'vgt_perf_VGT_PA_CLIPV_STALLED', + 32: 'vgt_perf_VGT_PA_CLIPV_STARVED_BUSY', + 33: 'vgt_perf_VGT_PA_CLIPV_STARVED_IDLE', + 34: 'vgt_perf_VGT_PA_CLIPV_STATIC', + 35: 'vgt_perf_VGT_PA_CLIPP_SEND', + 36: 'vgt_perf_VGT_PA_CLIPP_EOP', + 37: 'vgt_perf_VGT_PA_CLIPP_IS_EVENT', + 38: 'vgt_perf_VGT_PA_CLIPP_NULL_PRIM', + 39: 'vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT', + 40: 'vgt_perf_VGT_PA_CLIPP_STALLED', + 41: 'vgt_perf_VGT_PA_CLIPP_STARVED_BUSY', + 42: 'vgt_perf_VGT_PA_CLIPP_STARVED_IDLE', + 43: 'vgt_perf_VGT_PA_CLIPP_STATIC', + 44: 'vgt_perf_VGT_PA_CLIPS_SEND', + 45: 'vgt_perf_VGT_PA_CLIPS_STALLED', + 46: 'vgt_perf_VGT_PA_CLIPS_STARVED_BUSY', + 47: 'vgt_perf_VGT_PA_CLIPS_STARVED_IDLE', + 48: 'vgt_perf_VGT_PA_CLIPS_STATIC', + 49: 'vgt_perf_vsvert_ds_send', + 50: 'vgt_perf_vsvert_api_send', + 51: 'vgt_perf_hs_tif_stall', + 52: 'vgt_perf_hs_input_stall', + 53: 'vgt_perf_hs_interface_stall', + 54: 'vgt_perf_hs_tfm_stall', + 55: 'vgt_perf_te11_starved', + 56: 'vgt_perf_gs_event_stall', + 57: 'vgt_perf_vgt_pa_clipp_send_not_event', + 58: 'vgt_perf_vgt_pa_clipp_valid_prim', + 59: 'vgt_perf_reused_es_indices', + 60: 'vgt_perf_vs_cache_hits', + 61: 'vgt_perf_gs_cache_hits', + 62: 'vgt_perf_ds_cache_hits', + 63: 'vgt_perf_total_cache_hits', + 64: 'vgt_perf_vgt_busy', + 65: 'vgt_perf_vgt_gs_busy', + 66: 'vgt_perf_esvert_stalled_es_tbl', + 67: 'vgt_perf_esvert_stalled_gs_tbl', + 68: 'vgt_perf_esvert_stalled_gs_event', + 69: 'vgt_perf_esvert_stalled_gsprim', + 70: 'vgt_perf_gsprim_stalled_es_tbl', + 71: 'vgt_perf_gsprim_stalled_gs_tbl', + 72: 'vgt_perf_gsprim_stalled_gs_event', + 73: 'vgt_perf_gsprim_stalled_esvert', + 74: 'vgt_perf_esthread_stalled_es_rb_full', + 75: 'vgt_perf_esthread_stalled_spi_bp', + 76: 'vgt_perf_counters_avail_stalled', + 77: 'vgt_perf_gs_rb_space_avail_stalled', + 78: 'vgt_perf_gs_issue_rtr_stalled', + 79: 'vgt_perf_gsthread_stalled', + 80: 'vgt_perf_strmout_stalled', + 81: 'vgt_perf_wait_for_es_done_stalled', + 82: 'vgt_perf_cm_stalled_by_gog', + 83: 'vgt_perf_cm_reading_stalled', + 84: 'vgt_perf_cm_stalled_by_gsfetch_done', + 85: 'vgt_perf_gog_vs_tbl_stalled', + 86: 'vgt_perf_gog_out_indx_stalled', + 87: 'vgt_perf_gog_out_prim_stalled', + 88: 'vgt_perf_waveid_stalled', + 89: 'vgt_perf_gog_busy', + 90: 'vgt_perf_reused_vs_indices', + 91: 'vgt_perf_sclk_reg_vld_event', + 92: 'vgt_perf_vs_conflicting_indices', + 93: 'vgt_perf_sclk_core_vld_event', + 94: 'vgt_perf_hswave_stalled', + 95: 'vgt_perf_sclk_gs_vld_event', + 96: 'vgt_perf_VGT_SPI_LSVERT_VALID', + 97: 'vgt_perf_VGT_SPI_LSVERT_EOV', + 98: 'vgt_perf_VGT_SPI_LSVERT_STALLED', + 99: 'vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY', + 100: 'vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE', + 101: 'vgt_perf_VGT_SPI_LSVERT_STATIC', + 102: 'vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE', + 103: 'vgt_perf_VGT_SPI_LSWAVE_IS_EVENT', + 104: 'vgt_perf_VGT_SPI_LSWAVE_SEND', + 105: 'vgt_perf_VGT_SPI_HSVERT_VALID', + 106: 'vgt_perf_VGT_SPI_HSVERT_EOV', + 107: 'vgt_perf_VGT_SPI_HSVERT_STALLED', + 108: 'vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY', + 109: 'vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE', + 110: 'vgt_perf_VGT_SPI_HSVERT_STATIC', + 111: 'vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE', + 112: 'vgt_perf_VGT_SPI_HSWAVE_IS_EVENT', + 113: 'vgt_perf_VGT_SPI_HSWAVE_SEND', + 114: 'vgt_perf_ds_prims', + 115: 'vgt_perf_ds_RESERVED', + 116: 'vgt_perf_ls_thread_groups', + 117: 'vgt_perf_hs_thread_groups', + 118: 'vgt_perf_es_thread_groups', + 119: 'vgt_perf_vs_thread_groups', + 120: 'vgt_perf_ls_done_latency', + 121: 'vgt_perf_hs_done_latency', + 122: 'vgt_perf_es_done_latency', + 123: 'vgt_perf_gs_done_latency', + 124: 'vgt_perf_vgt_hs_busy', + 125: 'vgt_perf_vgt_te11_busy', + 126: 'vgt_perf_ls_flush', + 127: 'vgt_perf_hs_flush', + 128: 'vgt_perf_es_flush', + 129: 'vgt_perf_vgt_pa_clipp_eopg', + 130: 'vgt_perf_ls_done', + 131: 'vgt_perf_hs_done', + 132: 'vgt_perf_es_done', + 133: 'vgt_perf_gs_done', + 134: 'vgt_perf_vsfetch_done', + 135: 'vgt_perf_gs_done_received', + 136: 'vgt_perf_es_ring_high_water_mark', + 137: 'vgt_perf_gs_ring_high_water_mark', + 138: 'vgt_perf_vs_table_high_water_mark', + 139: 'vgt_perf_hs_tgs_active_high_water_mark', + 140: 'vgt_perf_pa_clipp_dealloc', + 141: 'vgt_perf_cut_mem_flush_stalled', + 142: 'vgt_perf_vsvert_work_received', + 143: 'vgt_perf_vgt_pa_clipp_starved_after_work', + 144: 'vgt_perf_te11_con_starved_after_work', + 145: 'vgt_perf_hs_waiting_on_ls_done_stall', + 146: 'vgt_spi_vsvert_valid', +} +vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0 +vgt_perf_VGT_SPI_ESVERT_VALID = 1 +vgt_perf_VGT_SPI_ESVERT_EOV = 2 +vgt_perf_VGT_SPI_ESVERT_STALLED = 3 +vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 4 +vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 5 +vgt_perf_VGT_SPI_ESVERT_STATIC = 6 +vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT = 7 +vgt_perf_VGT_SPI_ESTHREAD_SEND = 8 +vgt_perf_VGT_SPI_GSPRIM_VALID = 9 +vgt_perf_VGT_SPI_GSPRIM_EOV = 10 +vgt_perf_VGT_SPI_GSPRIM_CONT = 11 +vgt_perf_VGT_SPI_GSPRIM_STALLED = 12 +vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 13 +vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 14 +vgt_perf_VGT_SPI_GSPRIM_STATIC = 15 +vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 16 +vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT = 17 +vgt_perf_VGT_SPI_GSTHREAD_SEND = 18 +vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 19 +vgt_perf_VGT_SPI_VSVERT_SEND = 20 +vgt_perf_VGT_SPI_VSVERT_EOV = 21 +vgt_perf_VGT_SPI_VSVERT_STALLED = 22 +vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 23 +vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 24 +vgt_perf_VGT_SPI_VSVERT_STATIC = 25 +vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT = 26 +vgt_perf_VGT_SPI_VSTHREAD_SEND = 27 +vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 28 +vgt_perf_VGT_PA_CLIPV_SEND = 29 +vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 30 +vgt_perf_VGT_PA_CLIPV_STALLED = 31 +vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 32 +vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 33 +vgt_perf_VGT_PA_CLIPV_STATIC = 34 +vgt_perf_VGT_PA_CLIPP_SEND = 35 +vgt_perf_VGT_PA_CLIPP_EOP = 36 +vgt_perf_VGT_PA_CLIPP_IS_EVENT = 37 +vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 38 +vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 39 +vgt_perf_VGT_PA_CLIPP_STALLED = 40 +vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 41 +vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 42 +vgt_perf_VGT_PA_CLIPP_STATIC = 43 +vgt_perf_VGT_PA_CLIPS_SEND = 44 +vgt_perf_VGT_PA_CLIPS_STALLED = 45 +vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 46 +vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 47 +vgt_perf_VGT_PA_CLIPS_STATIC = 48 +vgt_perf_vsvert_ds_send = 49 +vgt_perf_vsvert_api_send = 50 +vgt_perf_hs_tif_stall = 51 +vgt_perf_hs_input_stall = 52 +vgt_perf_hs_interface_stall = 53 +vgt_perf_hs_tfm_stall = 54 +vgt_perf_te11_starved = 55 +vgt_perf_gs_event_stall = 56 +vgt_perf_vgt_pa_clipp_send_not_event = 57 +vgt_perf_vgt_pa_clipp_valid_prim = 58 +vgt_perf_reused_es_indices = 59 +vgt_perf_vs_cache_hits = 60 +vgt_perf_gs_cache_hits = 61 +vgt_perf_ds_cache_hits = 62 +vgt_perf_total_cache_hits = 63 +vgt_perf_vgt_busy = 64 +vgt_perf_vgt_gs_busy = 65 +vgt_perf_esvert_stalled_es_tbl = 66 +vgt_perf_esvert_stalled_gs_tbl = 67 +vgt_perf_esvert_stalled_gs_event = 68 +vgt_perf_esvert_stalled_gsprim = 69 +vgt_perf_gsprim_stalled_es_tbl = 70 +vgt_perf_gsprim_stalled_gs_tbl = 71 +vgt_perf_gsprim_stalled_gs_event = 72 +vgt_perf_gsprim_stalled_esvert = 73 +vgt_perf_esthread_stalled_es_rb_full = 74 +vgt_perf_esthread_stalled_spi_bp = 75 +vgt_perf_counters_avail_stalled = 76 +vgt_perf_gs_rb_space_avail_stalled = 77 +vgt_perf_gs_issue_rtr_stalled = 78 +vgt_perf_gsthread_stalled = 79 +vgt_perf_strmout_stalled = 80 +vgt_perf_wait_for_es_done_stalled = 81 +vgt_perf_cm_stalled_by_gog = 82 +vgt_perf_cm_reading_stalled = 83 +vgt_perf_cm_stalled_by_gsfetch_done = 84 +vgt_perf_gog_vs_tbl_stalled = 85 +vgt_perf_gog_out_indx_stalled = 86 +vgt_perf_gog_out_prim_stalled = 87 +vgt_perf_waveid_stalled = 88 +vgt_perf_gog_busy = 89 +vgt_perf_reused_vs_indices = 90 +vgt_perf_sclk_reg_vld_event = 91 +vgt_perf_vs_conflicting_indices = 92 +vgt_perf_sclk_core_vld_event = 93 +vgt_perf_hswave_stalled = 94 +vgt_perf_sclk_gs_vld_event = 95 +vgt_perf_VGT_SPI_LSVERT_VALID = 96 +vgt_perf_VGT_SPI_LSVERT_EOV = 97 +vgt_perf_VGT_SPI_LSVERT_STALLED = 98 +vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY = 99 +vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE = 100 +vgt_perf_VGT_SPI_LSVERT_STATIC = 101 +vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 102 +vgt_perf_VGT_SPI_LSWAVE_IS_EVENT = 103 +vgt_perf_VGT_SPI_LSWAVE_SEND = 104 +vgt_perf_VGT_SPI_HSVERT_VALID = 105 +vgt_perf_VGT_SPI_HSVERT_EOV = 106 +vgt_perf_VGT_SPI_HSVERT_STALLED = 107 +vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY = 108 +vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE = 109 +vgt_perf_VGT_SPI_HSVERT_STATIC = 110 +vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 111 +vgt_perf_VGT_SPI_HSWAVE_IS_EVENT = 112 +vgt_perf_VGT_SPI_HSWAVE_SEND = 113 +vgt_perf_ds_prims = 114 +vgt_perf_ds_RESERVED = 115 +vgt_perf_ls_thread_groups = 116 +vgt_perf_hs_thread_groups = 117 +vgt_perf_es_thread_groups = 118 +vgt_perf_vs_thread_groups = 119 +vgt_perf_ls_done_latency = 120 +vgt_perf_hs_done_latency = 121 +vgt_perf_es_done_latency = 122 +vgt_perf_gs_done_latency = 123 +vgt_perf_vgt_hs_busy = 124 +vgt_perf_vgt_te11_busy = 125 +vgt_perf_ls_flush = 126 +vgt_perf_hs_flush = 127 +vgt_perf_es_flush = 128 +vgt_perf_vgt_pa_clipp_eopg = 129 +vgt_perf_ls_done = 130 +vgt_perf_hs_done = 131 +vgt_perf_es_done = 132 +vgt_perf_gs_done = 133 +vgt_perf_vsfetch_done = 134 +vgt_perf_gs_done_received = 135 +vgt_perf_es_ring_high_water_mark = 136 +vgt_perf_gs_ring_high_water_mark = 137 +vgt_perf_vs_table_high_water_mark = 138 +vgt_perf_hs_tgs_active_high_water_mark = 139 +vgt_perf_pa_clipp_dealloc = 140 +vgt_perf_cut_mem_flush_stalled = 141 +vgt_perf_vsvert_work_received = 142 +vgt_perf_vgt_pa_clipp_starved_after_work = 143 +vgt_perf_te11_con_starved_after_work = 144 +vgt_perf_hs_waiting_on_ls_done_stall = 145 +vgt_spi_vsvert_valid = 146 +VGT_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'IA_PERFCOUNT_SELECT' +IA_PERFCOUNT_SELECT__enumvalues = { + 0: 'ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE', + 1: 'ia_perf_dma_data_fifo_full', + 2: 'ia_perf_RESERVED1', + 3: 'ia_perf_RESERVED2', + 4: 'ia_perf_RESERVED3', + 5: 'ia_perf_RESERVED4', + 6: 'ia_perf_RESERVED5', + 7: 'ia_perf_MC_LAT_BIN_0', + 8: 'ia_perf_MC_LAT_BIN_1', + 9: 'ia_perf_MC_LAT_BIN_2', + 10: 'ia_perf_MC_LAT_BIN_3', + 11: 'ia_perf_MC_LAT_BIN_4', + 12: 'ia_perf_MC_LAT_BIN_5', + 13: 'ia_perf_MC_LAT_BIN_6', + 14: 'ia_perf_MC_LAT_BIN_7', + 15: 'ia_perf_ia_busy', + 16: 'ia_perf_ia_sclk_reg_vld_event', + 17: 'ia_perf_RESERVED6', + 18: 'ia_perf_ia_sclk_core_vld_event', + 19: 'ia_perf_RESERVED7', + 20: 'ia_perf_ia_dma_return', + 21: 'ia_perf_ia_stalled', + 22: 'ia_perf_shift_starved_pipe0_event', + 23: 'ia_perf_shift_starved_pipe1_event', +} +ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE = 0 +ia_perf_dma_data_fifo_full = 1 +ia_perf_RESERVED1 = 2 +ia_perf_RESERVED2 = 3 +ia_perf_RESERVED3 = 4 +ia_perf_RESERVED4 = 5 +ia_perf_RESERVED5 = 6 +ia_perf_MC_LAT_BIN_0 = 7 +ia_perf_MC_LAT_BIN_1 = 8 +ia_perf_MC_LAT_BIN_2 = 9 +ia_perf_MC_LAT_BIN_3 = 10 +ia_perf_MC_LAT_BIN_4 = 11 +ia_perf_MC_LAT_BIN_5 = 12 +ia_perf_MC_LAT_BIN_6 = 13 +ia_perf_MC_LAT_BIN_7 = 14 +ia_perf_ia_busy = 15 +ia_perf_ia_sclk_reg_vld_event = 16 +ia_perf_RESERVED6 = 17 +ia_perf_ia_sclk_core_vld_event = 18 +ia_perf_RESERVED7 = 19 +ia_perf_ia_dma_return = 20 +ia_perf_ia_stalled = 21 +ia_perf_shift_starved_pipe0_event = 22 +ia_perf_shift_starved_pipe1_event = 23 +IA_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'WD_PERFCOUNT_SELECT' +WD_PERFCOUNT_SELECT__enumvalues = { + 0: 'wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE', + 1: 'wd_perf_RBIU_DR_FIFO_STARVED', + 2: 'wd_perf_RBIU_DR_FIFO_STALLED', + 3: 'wd_perf_RBIU_DI_FIFO_STARVED', + 4: 'wd_perf_RBIU_DI_FIFO_STALLED', + 5: 'wd_perf_wd_busy', + 6: 'wd_perf_wd_sclk_reg_vld_event', + 7: 'wd_perf_wd_sclk_input_vld_event', + 8: 'wd_perf_wd_sclk_core_vld_event', + 9: 'wd_perf_wd_stalled', + 10: 'wd_perf_inside_tf_bin_0', + 11: 'wd_perf_inside_tf_bin_1', + 12: 'wd_perf_inside_tf_bin_2', + 13: 'wd_perf_inside_tf_bin_3', + 14: 'wd_perf_inside_tf_bin_4', + 15: 'wd_perf_inside_tf_bin_5', + 16: 'wd_perf_inside_tf_bin_6', + 17: 'wd_perf_inside_tf_bin_7', + 18: 'wd_perf_inside_tf_bin_8', + 19: 'wd_perf_tfreq_lat_bin_0', + 20: 'wd_perf_tfreq_lat_bin_1', + 21: 'wd_perf_tfreq_lat_bin_2', + 22: 'wd_perf_tfreq_lat_bin_3', + 23: 'wd_perf_tfreq_lat_bin_4', + 24: 'wd_perf_tfreq_lat_bin_5', + 25: 'wd_perf_tfreq_lat_bin_6', + 26: 'wd_perf_tfreq_lat_bin_7', + 27: 'wd_starved_on_hs_done', + 28: 'wd_perf_se0_hs_done_latency', + 29: 'wd_perf_se1_hs_done_latency', + 30: 'wd_perf_se2_hs_done_latency', + 31: 'wd_perf_se3_hs_done_latency', + 32: 'wd_perf_hs_done_se0', + 33: 'wd_perf_hs_done_se1', + 34: 'wd_perf_hs_done_se2', + 35: 'wd_perf_hs_done_se3', + 36: 'wd_perf_null_patches', +} +wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0 +wd_perf_RBIU_DR_FIFO_STARVED = 1 +wd_perf_RBIU_DR_FIFO_STALLED = 2 +wd_perf_RBIU_DI_FIFO_STARVED = 3 +wd_perf_RBIU_DI_FIFO_STALLED = 4 +wd_perf_wd_busy = 5 +wd_perf_wd_sclk_reg_vld_event = 6 +wd_perf_wd_sclk_input_vld_event = 7 +wd_perf_wd_sclk_core_vld_event = 8 +wd_perf_wd_stalled = 9 +wd_perf_inside_tf_bin_0 = 10 +wd_perf_inside_tf_bin_1 = 11 +wd_perf_inside_tf_bin_2 = 12 +wd_perf_inside_tf_bin_3 = 13 +wd_perf_inside_tf_bin_4 = 14 +wd_perf_inside_tf_bin_5 = 15 +wd_perf_inside_tf_bin_6 = 16 +wd_perf_inside_tf_bin_7 = 17 +wd_perf_inside_tf_bin_8 = 18 +wd_perf_tfreq_lat_bin_0 = 19 +wd_perf_tfreq_lat_bin_1 = 20 +wd_perf_tfreq_lat_bin_2 = 21 +wd_perf_tfreq_lat_bin_3 = 22 +wd_perf_tfreq_lat_bin_4 = 23 +wd_perf_tfreq_lat_bin_5 = 24 +wd_perf_tfreq_lat_bin_6 = 25 +wd_perf_tfreq_lat_bin_7 = 26 +wd_starved_on_hs_done = 27 +wd_perf_se0_hs_done_latency = 28 +wd_perf_se1_hs_done_latency = 29 +wd_perf_se2_hs_done_latency = 30 +wd_perf_se3_hs_done_latency = 31 +wd_perf_hs_done_se0 = 32 +wd_perf_hs_done_se1 = 33 +wd_perf_hs_done_se2 = 34 +wd_perf_hs_done_se3 = 35 +wd_perf_null_patches = 36 +WD_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'WD_IA_DRAW_TYPE' +WD_IA_DRAW_TYPE__enumvalues = { + 0: 'WD_IA_DRAW_TYPE_DI_MM0', + 1: 'WD_IA_DRAW_TYPE_REG_XFER', + 2: 'WD_IA_DRAW_TYPE_EVENT_INIT', + 3: 'WD_IA_DRAW_TYPE_EVENT_ADDR', + 4: 'WD_IA_DRAW_TYPE_MIN_INDX', + 5: 'WD_IA_DRAW_TYPE_MAX_INDX', + 6: 'WD_IA_DRAW_TYPE_INDX_OFF', + 7: 'WD_IA_DRAW_TYPE_IMM_DATA', +} +WD_IA_DRAW_TYPE_DI_MM0 = 0 +WD_IA_DRAW_TYPE_REG_XFER = 1 +WD_IA_DRAW_TYPE_EVENT_INIT = 2 +WD_IA_DRAW_TYPE_EVENT_ADDR = 3 +WD_IA_DRAW_TYPE_MIN_INDX = 4 +WD_IA_DRAW_TYPE_MAX_INDX = 5 +WD_IA_DRAW_TYPE_INDX_OFF = 6 +WD_IA_DRAW_TYPE_IMM_DATA = 7 +WD_IA_DRAW_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'WD_IA_DRAW_REG_XFER' +WD_IA_DRAW_REG_XFER__enumvalues = { + 0: 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', + 1: 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', +} +WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0 +WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 1 +WD_IA_DRAW_REG_XFER = ctypes.c_uint32 # enum + +# values for enumeration 'WD_IA_DRAW_SOURCE' +WD_IA_DRAW_SOURCE__enumvalues = { + 0: 'WD_IA_DRAW_SOURCE_DMA', + 1: 'WD_IA_DRAW_SOURCE_IMMD', + 2: 'WD_IA_DRAW_SOURCE_AUTO', + 3: 'WD_IA_DRAW_SOURCE_OPAQ', +} +WD_IA_DRAW_SOURCE_DMA = 0 +WD_IA_DRAW_SOURCE_IMMD = 1 +WD_IA_DRAW_SOURCE_AUTO = 2 +WD_IA_DRAW_SOURCE_OPAQ = 3 +WD_IA_DRAW_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'GB_EDC_DED_MODE' +GB_EDC_DED_MODE__enumvalues = { + 0: 'GB_EDC_DED_MODE_LOG', + 1: 'GB_EDC_DED_MODE_HALT', + 2: 'GB_EDC_DED_MODE_INT_HALT', +} +GB_EDC_DED_MODE_LOG = 0 +GB_EDC_DED_MODE_HALT = 1 +GB_EDC_DED_MODE_INT_HALT = 2 +GB_EDC_DED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'TA_TC_ADDR_MODES' +TA_TC_ADDR_MODES__enumvalues = { + 0: 'TA_TC_ADDR_MODE_DEFAULT', + 1: 'TA_TC_ADDR_MODE_COMP0', + 2: 'TA_TC_ADDR_MODE_COMP1', + 3: 'TA_TC_ADDR_MODE_COMP2', + 4: 'TA_TC_ADDR_MODE_COMP3', + 5: 'TA_TC_ADDR_MODE_UNALIGNED', + 6: 'TA_TC_ADDR_MODE_BORDER_COLOR', +} +TA_TC_ADDR_MODE_DEFAULT = 0 +TA_TC_ADDR_MODE_COMP0 = 1 +TA_TC_ADDR_MODE_COMP1 = 2 +TA_TC_ADDR_MODE_COMP2 = 3 +TA_TC_ADDR_MODE_COMP3 = 4 +TA_TC_ADDR_MODE_UNALIGNED = 5 +TA_TC_ADDR_MODE_BORDER_COLOR = 6 +TA_TC_ADDR_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'TA_PERFCOUNT_SEL' +TA_PERFCOUNT_SEL__enumvalues = { + 0: 'TA_PERF_SEL_NULL', + 1: 'TA_PERF_SEL_sh_fifo_busy', + 2: 'TA_PERF_SEL_sh_fifo_cmd_busy', + 3: 'TA_PERF_SEL_sh_fifo_addr_busy', + 4: 'TA_PERF_SEL_sh_fifo_data_busy', + 5: 'TA_PERF_SEL_sh_fifo_data_sfifo_busy', + 6: 'TA_PERF_SEL_sh_fifo_data_tfifo_busy', + 7: 'TA_PERF_SEL_gradient_busy', + 8: 'TA_PERF_SEL_gradient_fifo_busy', + 9: 'TA_PERF_SEL_lod_busy', + 10: 'TA_PERF_SEL_lod_fifo_busy', + 11: 'TA_PERF_SEL_addresser_busy', + 12: 'TA_PERF_SEL_addresser_fifo_busy', + 13: 'TA_PERF_SEL_aligner_busy', + 14: 'TA_PERF_SEL_write_path_busy', + 15: 'TA_PERF_SEL_ta_busy', + 16: 'TA_PERF_SEL_sq_ta_cmd_cycles', + 17: 'TA_PERF_SEL_sp_ta_addr_cycles', + 18: 'TA_PERF_SEL_sp_ta_data_cycles', + 19: 'TA_PERF_SEL_ta_fa_data_state_cycles', + 20: 'TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles', + 21: 'TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles', + 22: 'TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles', + 23: 'TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles', + 24: 'TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles', + 25: 'TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles', + 26: 'TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles', + 27: 'TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles', + 28: 'TA_PERF_SEL_RESERVED_28', + 29: 'TA_PERF_SEL_RESERVED_29', + 30: 'TA_PERF_SEL_sh_fifo_addr_cycles', + 31: 'TA_PERF_SEL_sh_fifo_data_cycles', + 32: 'TA_PERF_SEL_total_wavefronts', + 33: 'TA_PERF_SEL_gradient_cycles', + 34: 'TA_PERF_SEL_walker_cycles', + 35: 'TA_PERF_SEL_aligner_cycles', + 36: 'TA_PERF_SEL_image_wavefronts', + 37: 'TA_PERF_SEL_image_read_wavefronts', + 38: 'TA_PERF_SEL_image_write_wavefronts', + 39: 'TA_PERF_SEL_image_atomic_wavefronts', + 40: 'TA_PERF_SEL_image_total_cycles', + 41: 'TA_PERF_SEL_RESERVED_41', + 42: 'TA_PERF_SEL_RESERVED_42', + 43: 'TA_PERF_SEL_RESERVED_43', + 44: 'TA_PERF_SEL_buffer_wavefronts', + 45: 'TA_PERF_SEL_buffer_read_wavefronts', + 46: 'TA_PERF_SEL_buffer_write_wavefronts', + 47: 'TA_PERF_SEL_buffer_atomic_wavefronts', + 48: 'TA_PERF_SEL_buffer_coalescable_wavefronts', + 49: 'TA_PERF_SEL_buffer_total_cycles', + 50: 'TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles', + 51: 'TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles', + 52: 'TA_PERF_SEL_buffer_coalesced_read_cycles', + 53: 'TA_PERF_SEL_buffer_coalesced_write_cycles', + 54: 'TA_PERF_SEL_addr_stalled_by_tc_cycles', + 55: 'TA_PERF_SEL_addr_stalled_by_td_cycles', + 56: 'TA_PERF_SEL_data_stalled_by_tc_cycles', + 57: 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', + 58: 'TA_PERF_SEL_addresser_stalled_cycles', + 59: 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', + 60: 'TA_PERF_SEL_aniso_stalled_cycles', + 61: 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', + 62: 'TA_PERF_SEL_deriv_stalled_cycles', + 63: 'TA_PERF_SEL_aniso_gt1_cycle_quads', + 64: 'TA_PERF_SEL_color_1_cycle_pixels', + 65: 'TA_PERF_SEL_color_2_cycle_pixels', + 66: 'TA_PERF_SEL_color_3_cycle_pixels', + 67: 'TA_PERF_SEL_color_4_cycle_pixels', + 68: 'TA_PERF_SEL_mip_1_cycle_pixels', + 69: 'TA_PERF_SEL_mip_2_cycle_pixels', + 70: 'TA_PERF_SEL_vol_1_cycle_pixels', + 71: 'TA_PERF_SEL_vol_2_cycle_pixels', + 72: 'TA_PERF_SEL_bilin_point_1_cycle_pixels', + 73: 'TA_PERF_SEL_mipmap_lod_0_samples', + 74: 'TA_PERF_SEL_mipmap_lod_1_samples', + 75: 'TA_PERF_SEL_mipmap_lod_2_samples', + 76: 'TA_PERF_SEL_mipmap_lod_3_samples', + 77: 'TA_PERF_SEL_mipmap_lod_4_samples', + 78: 'TA_PERF_SEL_mipmap_lod_5_samples', + 79: 'TA_PERF_SEL_mipmap_lod_6_samples', + 80: 'TA_PERF_SEL_mipmap_lod_7_samples', + 81: 'TA_PERF_SEL_mipmap_lod_8_samples', + 82: 'TA_PERF_SEL_mipmap_lod_9_samples', + 83: 'TA_PERF_SEL_mipmap_lod_10_samples', + 84: 'TA_PERF_SEL_mipmap_lod_11_samples', + 85: 'TA_PERF_SEL_mipmap_lod_12_samples', + 86: 'TA_PERF_SEL_mipmap_lod_13_samples', + 87: 'TA_PERF_SEL_mipmap_lod_14_samples', + 88: 'TA_PERF_SEL_mipmap_invalid_samples', + 89: 'TA_PERF_SEL_aniso_1_cycle_quads', + 90: 'TA_PERF_SEL_aniso_2_cycle_quads', + 91: 'TA_PERF_SEL_aniso_4_cycle_quads', + 92: 'TA_PERF_SEL_aniso_6_cycle_quads', + 93: 'TA_PERF_SEL_aniso_8_cycle_quads', + 94: 'TA_PERF_SEL_aniso_10_cycle_quads', + 95: 'TA_PERF_SEL_aniso_12_cycle_quads', + 96: 'TA_PERF_SEL_aniso_14_cycle_quads', + 97: 'TA_PERF_SEL_aniso_16_cycle_quads', + 98: 'TA_PERF_SEL_write_path_input_cycles', + 99: 'TA_PERF_SEL_write_path_output_cycles', + 100: 'TA_PERF_SEL_flat_wavefronts', + 101: 'TA_PERF_SEL_flat_read_wavefronts', + 102: 'TA_PERF_SEL_flat_write_wavefronts', + 103: 'TA_PERF_SEL_flat_atomic_wavefronts', + 104: 'TA_PERF_SEL_flat_coalesceable_wavefronts', + 105: 'TA_PERF_SEL_reg_sclk_vld', + 106: 'TA_PERF_SEL_local_cg_dyn_sclk_grp0_en', + 107: 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_en', + 108: 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en', + 109: 'TA_PERF_SEL_local_cg_dyn_sclk_grp4_en', + 110: 'TA_PERF_SEL_local_cg_dyn_sclk_grp5_en', + 111: 'TA_PERF_SEL_xnack_on_phase0', + 112: 'TA_PERF_SEL_xnack_on_phase1', + 113: 'TA_PERF_SEL_xnack_on_phase2', + 114: 'TA_PERF_SEL_xnack_on_phase3', + 115: 'TA_PERF_SEL_first_xnack_on_phase0', + 116: 'TA_PERF_SEL_first_xnack_on_phase1', + 117: 'TA_PERF_SEL_first_xnack_on_phase2', + 118: 'TA_PERF_SEL_first_xnack_on_phase3', +} +TA_PERF_SEL_NULL = 0 +TA_PERF_SEL_sh_fifo_busy = 1 +TA_PERF_SEL_sh_fifo_cmd_busy = 2 +TA_PERF_SEL_sh_fifo_addr_busy = 3 +TA_PERF_SEL_sh_fifo_data_busy = 4 +TA_PERF_SEL_sh_fifo_data_sfifo_busy = 5 +TA_PERF_SEL_sh_fifo_data_tfifo_busy = 6 +TA_PERF_SEL_gradient_busy = 7 +TA_PERF_SEL_gradient_fifo_busy = 8 +TA_PERF_SEL_lod_busy = 9 +TA_PERF_SEL_lod_fifo_busy = 10 +TA_PERF_SEL_addresser_busy = 11 +TA_PERF_SEL_addresser_fifo_busy = 12 +TA_PERF_SEL_aligner_busy = 13 +TA_PERF_SEL_write_path_busy = 14 +TA_PERF_SEL_ta_busy = 15 +TA_PERF_SEL_sq_ta_cmd_cycles = 16 +TA_PERF_SEL_sp_ta_addr_cycles = 17 +TA_PERF_SEL_sp_ta_data_cycles = 18 +TA_PERF_SEL_ta_fa_data_state_cycles = 19 +TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 20 +TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 21 +TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles = 22 +TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles = 23 +TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles = 24 +TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles = 25 +TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles = 26 +TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles = 27 +TA_PERF_SEL_RESERVED_28 = 28 +TA_PERF_SEL_RESERVED_29 = 29 +TA_PERF_SEL_sh_fifo_addr_cycles = 30 +TA_PERF_SEL_sh_fifo_data_cycles = 31 +TA_PERF_SEL_total_wavefronts = 32 +TA_PERF_SEL_gradient_cycles = 33 +TA_PERF_SEL_walker_cycles = 34 +TA_PERF_SEL_aligner_cycles = 35 +TA_PERF_SEL_image_wavefronts = 36 +TA_PERF_SEL_image_read_wavefronts = 37 +TA_PERF_SEL_image_write_wavefronts = 38 +TA_PERF_SEL_image_atomic_wavefronts = 39 +TA_PERF_SEL_image_total_cycles = 40 +TA_PERF_SEL_RESERVED_41 = 41 +TA_PERF_SEL_RESERVED_42 = 42 +TA_PERF_SEL_RESERVED_43 = 43 +TA_PERF_SEL_buffer_wavefronts = 44 +TA_PERF_SEL_buffer_read_wavefronts = 45 +TA_PERF_SEL_buffer_write_wavefronts = 46 +TA_PERF_SEL_buffer_atomic_wavefronts = 47 +TA_PERF_SEL_buffer_coalescable_wavefronts = 48 +TA_PERF_SEL_buffer_total_cycles = 49 +TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles = 50 +TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles = 51 +TA_PERF_SEL_buffer_coalesced_read_cycles = 52 +TA_PERF_SEL_buffer_coalesced_write_cycles = 53 +TA_PERF_SEL_addr_stalled_by_tc_cycles = 54 +TA_PERF_SEL_addr_stalled_by_td_cycles = 55 +TA_PERF_SEL_data_stalled_by_tc_cycles = 56 +TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 57 +TA_PERF_SEL_addresser_stalled_cycles = 58 +TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 59 +TA_PERF_SEL_aniso_stalled_cycles = 60 +TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 61 +TA_PERF_SEL_deriv_stalled_cycles = 62 +TA_PERF_SEL_aniso_gt1_cycle_quads = 63 +TA_PERF_SEL_color_1_cycle_pixels = 64 +TA_PERF_SEL_color_2_cycle_pixels = 65 +TA_PERF_SEL_color_3_cycle_pixels = 66 +TA_PERF_SEL_color_4_cycle_pixels = 67 +TA_PERF_SEL_mip_1_cycle_pixels = 68 +TA_PERF_SEL_mip_2_cycle_pixels = 69 +TA_PERF_SEL_vol_1_cycle_pixels = 70 +TA_PERF_SEL_vol_2_cycle_pixels = 71 +TA_PERF_SEL_bilin_point_1_cycle_pixels = 72 +TA_PERF_SEL_mipmap_lod_0_samples = 73 +TA_PERF_SEL_mipmap_lod_1_samples = 74 +TA_PERF_SEL_mipmap_lod_2_samples = 75 +TA_PERF_SEL_mipmap_lod_3_samples = 76 +TA_PERF_SEL_mipmap_lod_4_samples = 77 +TA_PERF_SEL_mipmap_lod_5_samples = 78 +TA_PERF_SEL_mipmap_lod_6_samples = 79 +TA_PERF_SEL_mipmap_lod_7_samples = 80 +TA_PERF_SEL_mipmap_lod_8_samples = 81 +TA_PERF_SEL_mipmap_lod_9_samples = 82 +TA_PERF_SEL_mipmap_lod_10_samples = 83 +TA_PERF_SEL_mipmap_lod_11_samples = 84 +TA_PERF_SEL_mipmap_lod_12_samples = 85 +TA_PERF_SEL_mipmap_lod_13_samples = 86 +TA_PERF_SEL_mipmap_lod_14_samples = 87 +TA_PERF_SEL_mipmap_invalid_samples = 88 +TA_PERF_SEL_aniso_1_cycle_quads = 89 +TA_PERF_SEL_aniso_2_cycle_quads = 90 +TA_PERF_SEL_aniso_4_cycle_quads = 91 +TA_PERF_SEL_aniso_6_cycle_quads = 92 +TA_PERF_SEL_aniso_8_cycle_quads = 93 +TA_PERF_SEL_aniso_10_cycle_quads = 94 +TA_PERF_SEL_aniso_12_cycle_quads = 95 +TA_PERF_SEL_aniso_14_cycle_quads = 96 +TA_PERF_SEL_aniso_16_cycle_quads = 97 +TA_PERF_SEL_write_path_input_cycles = 98 +TA_PERF_SEL_write_path_output_cycles = 99 +TA_PERF_SEL_flat_wavefronts = 100 +TA_PERF_SEL_flat_read_wavefronts = 101 +TA_PERF_SEL_flat_write_wavefronts = 102 +TA_PERF_SEL_flat_atomic_wavefronts = 103 +TA_PERF_SEL_flat_coalesceable_wavefronts = 104 +TA_PERF_SEL_reg_sclk_vld = 105 +TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 106 +TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 107 +TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 108 +TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 109 +TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 110 +TA_PERF_SEL_xnack_on_phase0 = 111 +TA_PERF_SEL_xnack_on_phase1 = 112 +TA_PERF_SEL_xnack_on_phase2 = 113 +TA_PERF_SEL_xnack_on_phase3 = 114 +TA_PERF_SEL_first_xnack_on_phase0 = 115 +TA_PERF_SEL_first_xnack_on_phase1 = 116 +TA_PERF_SEL_first_xnack_on_phase2 = 117 +TA_PERF_SEL_first_xnack_on_phase3 = 118 +TA_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TD_PERFCOUNT_SEL' +TD_PERFCOUNT_SEL__enumvalues = { + 0: 'TD_PERF_SEL_none', + 1: 'TD_PERF_SEL_td_busy', + 2: 'TD_PERF_SEL_input_busy', + 3: 'TD_PERF_SEL_output_busy', + 4: 'TD_PERF_SEL_lerp_busy', + 5: 'TD_PERF_SEL_reg_sclk_vld', + 6: 'TD_PERF_SEL_local_cg_dyn_sclk_grp0_en', + 7: 'TD_PERF_SEL_local_cg_dyn_sclk_grp1_en', + 8: 'TD_PERF_SEL_local_cg_dyn_sclk_grp4_en', + 9: 'TD_PERF_SEL_local_cg_dyn_sclk_grp5_en', + 10: 'TD_PERF_SEL_tc_td_fifo_full', + 11: 'TD_PERF_SEL_constant_state_full', + 12: 'TD_PERF_SEL_sample_state_full', + 13: 'TD_PERF_SEL_output_fifo_full', + 14: 'TD_PERF_SEL_RESERVED_14', + 15: 'TD_PERF_SEL_tc_stall', + 16: 'TD_PERF_SEL_pc_stall', + 17: 'TD_PERF_SEL_gds_stall', + 18: 'TD_PERF_SEL_RESERVED_18', + 19: 'TD_PERF_SEL_RESERVED_19', + 20: 'TD_PERF_SEL_gather4_wavefront', + 21: 'TD_PERF_SEL_gather4h_wavefront', + 22: 'TD_PERF_SEL_gather4h_packed_wavefront', + 23: 'TD_PERF_SEL_gather8h_packed_wavefront', + 24: 'TD_PERF_SEL_sample_c_wavefront', + 25: 'TD_PERF_SEL_load_wavefront', + 26: 'TD_PERF_SEL_atomic_wavefront', + 27: 'TD_PERF_SEL_store_wavefront', + 28: 'TD_PERF_SEL_ldfptr_wavefront', + 29: 'TD_PERF_SEL_d16_en_wavefront', + 30: 'TD_PERF_SEL_bypass_filter_wavefront', + 31: 'TD_PERF_SEL_min_max_filter_wavefront', + 32: 'TD_PERF_SEL_coalescable_wavefront', + 33: 'TD_PERF_SEL_coalesced_phase', + 34: 'TD_PERF_SEL_four_phase_wavefront', + 35: 'TD_PERF_SEL_eight_phase_wavefront', + 36: 'TD_PERF_SEL_sixteen_phase_wavefront', + 37: 'TD_PERF_SEL_four_phase_forward_wavefront', + 38: 'TD_PERF_SEL_write_ack_wavefront', + 39: 'TD_PERF_SEL_RESERVED_39', + 40: 'TD_PERF_SEL_user_defined_border', + 41: 'TD_PERF_SEL_white_border', + 42: 'TD_PERF_SEL_opaque_black_border', + 43: 'TD_PERF_SEL_RESERVED_43', + 44: 'TD_PERF_SEL_RESERVED_44', + 45: 'TD_PERF_SEL_nack', + 46: 'TD_PERF_SEL_td_sp_traffic', + 47: 'TD_PERF_SEL_consume_gds_traffic', + 48: 'TD_PERF_SEL_addresscmd_poison', + 49: 'TD_PERF_SEL_data_poison', + 50: 'TD_PERF_SEL_start_cycle_0', + 51: 'TD_PERF_SEL_start_cycle_1', + 52: 'TD_PERF_SEL_start_cycle_2', + 53: 'TD_PERF_SEL_start_cycle_3', + 54: 'TD_PERF_SEL_null_cycle_output', + 55: 'TD_PERF_SEL_d16_data_packed', + 56: 'TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt', +} +TD_PERF_SEL_none = 0 +TD_PERF_SEL_td_busy = 1 +TD_PERF_SEL_input_busy = 2 +TD_PERF_SEL_output_busy = 3 +TD_PERF_SEL_lerp_busy = 4 +TD_PERF_SEL_reg_sclk_vld = 5 +TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 6 +TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 7 +TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 8 +TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 9 +TD_PERF_SEL_tc_td_fifo_full = 10 +TD_PERF_SEL_constant_state_full = 11 +TD_PERF_SEL_sample_state_full = 12 +TD_PERF_SEL_output_fifo_full = 13 +TD_PERF_SEL_RESERVED_14 = 14 +TD_PERF_SEL_tc_stall = 15 +TD_PERF_SEL_pc_stall = 16 +TD_PERF_SEL_gds_stall = 17 +TD_PERF_SEL_RESERVED_18 = 18 +TD_PERF_SEL_RESERVED_19 = 19 +TD_PERF_SEL_gather4_wavefront = 20 +TD_PERF_SEL_gather4h_wavefront = 21 +TD_PERF_SEL_gather4h_packed_wavefront = 22 +TD_PERF_SEL_gather8h_packed_wavefront = 23 +TD_PERF_SEL_sample_c_wavefront = 24 +TD_PERF_SEL_load_wavefront = 25 +TD_PERF_SEL_atomic_wavefront = 26 +TD_PERF_SEL_store_wavefront = 27 +TD_PERF_SEL_ldfptr_wavefront = 28 +TD_PERF_SEL_d16_en_wavefront = 29 +TD_PERF_SEL_bypass_filter_wavefront = 30 +TD_PERF_SEL_min_max_filter_wavefront = 31 +TD_PERF_SEL_coalescable_wavefront = 32 +TD_PERF_SEL_coalesced_phase = 33 +TD_PERF_SEL_four_phase_wavefront = 34 +TD_PERF_SEL_eight_phase_wavefront = 35 +TD_PERF_SEL_sixteen_phase_wavefront = 36 +TD_PERF_SEL_four_phase_forward_wavefront = 37 +TD_PERF_SEL_write_ack_wavefront = 38 +TD_PERF_SEL_RESERVED_39 = 39 +TD_PERF_SEL_user_defined_border = 40 +TD_PERF_SEL_white_border = 41 +TD_PERF_SEL_opaque_black_border = 42 +TD_PERF_SEL_RESERVED_43 = 43 +TD_PERF_SEL_RESERVED_44 = 44 +TD_PERF_SEL_nack = 45 +TD_PERF_SEL_td_sp_traffic = 46 +TD_PERF_SEL_consume_gds_traffic = 47 +TD_PERF_SEL_addresscmd_poison = 48 +TD_PERF_SEL_data_poison = 49 +TD_PERF_SEL_start_cycle_0 = 50 +TD_PERF_SEL_start_cycle_1 = 51 +TD_PERF_SEL_start_cycle_2 = 52 +TD_PERF_SEL_start_cycle_3 = 53 +TD_PERF_SEL_null_cycle_output = 54 +TD_PERF_SEL_d16_data_packed = 55 +TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt = 56 +TD_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_PERFCOUNT_SELECT' +TCP_PERFCOUNT_SELECT__enumvalues = { + 0: 'TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES', + 1: 'TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES', + 2: 'TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES', + 3: 'TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES', + 4: 'TCP_PERF_SEL_TD_TCP_STALL_CYCLES', + 5: 'TCP_PERF_SEL_TCR_TCP_STALL_CYCLES', + 6: 'TCP_PERF_SEL_LOD_STALL_CYCLES', + 7: 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES', + 8: 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES', + 9: 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES', + 10: 'TCP_PERF_SEL_ALLOC_STALL_CYCLES', + 11: 'TCP_PERF_SEL_LFIFO_STALL_CYCLES', + 12: 'TCP_PERF_SEL_RFIFO_STALL_CYCLES', + 13: 'TCP_PERF_SEL_TCR_RDRET_STALL', + 14: 'TCP_PERF_SEL_WRITE_CONFLICT_STALL', + 15: 'TCP_PERF_SEL_HOLE_READ_STALL', + 16: 'TCP_PERF_SEL_READCONFLICT_STALL_CYCLES', + 17: 'TCP_PERF_SEL_PENDING_STALL_CYCLES', + 18: 'TCP_PERF_SEL_READFIFO_STALL_CYCLES', + 19: 'TCP_PERF_SEL_TCP_LATENCY', + 20: 'TCP_PERF_SEL_TCC_READ_REQ_LATENCY', + 21: 'TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY', + 22: 'TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY', + 23: 'TCP_PERF_SEL_TCC_READ_REQ', + 24: 'TCP_PERF_SEL_TCC_WRITE_REQ', + 25: 'TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ', + 26: 'TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ', + 27: 'TCP_PERF_SEL_TOTAL_LOCAL_READ', + 28: 'TCP_PERF_SEL_TOTAL_GLOBAL_READ', + 29: 'TCP_PERF_SEL_TOTAL_LOCAL_WRITE', + 30: 'TCP_PERF_SEL_TOTAL_GLOBAL_WRITE', + 31: 'TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET', + 32: 'TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET', + 33: 'TCP_PERF_SEL_TOTAL_WBINVL1', + 34: 'TCP_PERF_SEL_IMG_READ_FMT_1', + 35: 'TCP_PERF_SEL_IMG_READ_FMT_8', + 36: 'TCP_PERF_SEL_IMG_READ_FMT_16', + 37: 'TCP_PERF_SEL_IMG_READ_FMT_32', + 38: 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_8', + 39: 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_16', + 40: 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_128', + 41: 'TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE', + 42: 'TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE', + 43: 'TCP_PERF_SEL_IMG_READ_FMT_96', + 44: 'TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE', + 45: 'TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE', + 46: 'TCP_PERF_SEL_IMG_READ_FMT_BC1', + 47: 'TCP_PERF_SEL_IMG_READ_FMT_BC2', + 48: 'TCP_PERF_SEL_IMG_READ_FMT_BC3', + 49: 'TCP_PERF_SEL_IMG_READ_FMT_BC4', + 50: 'TCP_PERF_SEL_IMG_READ_FMT_BC5', + 51: 'TCP_PERF_SEL_IMG_READ_FMT_BC6', + 52: 'TCP_PERF_SEL_IMG_READ_FMT_BC7', + 53: 'TCP_PERF_SEL_IMG_READ_FMT_I8', + 54: 'TCP_PERF_SEL_IMG_READ_FMT_I16', + 55: 'TCP_PERF_SEL_IMG_READ_FMT_I32', + 56: 'TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8', + 57: 'TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16', + 58: 'TCP_PERF_SEL_IMG_READ_FMT_D8', + 59: 'TCP_PERF_SEL_IMG_READ_FMT_D16', + 60: 'TCP_PERF_SEL_IMG_READ_FMT_D32', + 61: 'TCP_PERF_SEL_IMG_WRITE_FMT_8', + 62: 'TCP_PERF_SEL_IMG_WRITE_FMT_16', + 63: 'TCP_PERF_SEL_IMG_WRITE_FMT_32', + 64: 'TCP_PERF_SEL_IMG_WRITE_FMT_64', + 65: 'TCP_PERF_SEL_IMG_WRITE_FMT_128', + 66: 'TCP_PERF_SEL_IMG_WRITE_FMT_D8', + 67: 'TCP_PERF_SEL_IMG_WRITE_FMT_D16', + 68: 'TCP_PERF_SEL_IMG_WRITE_FMT_D32', + 69: 'TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32', + 70: 'TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32', + 71: 'TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64', + 72: 'TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64', + 73: 'TCP_PERF_SEL_BUF_READ_FMT_8', + 74: 'TCP_PERF_SEL_BUF_READ_FMT_16', + 75: 'TCP_PERF_SEL_BUF_READ_FMT_32', + 76: 'TCP_PERF_SEL_BUF_WRITE_FMT_8', + 77: 'TCP_PERF_SEL_BUF_WRITE_FMT_16', + 78: 'TCP_PERF_SEL_BUF_WRITE_FMT_32', + 79: 'TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32', + 80: 'TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32', + 81: 'TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64', + 82: 'TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64', + 83: 'TCP_PERF_SEL_ARR_LINEAR_GENERAL', + 84: 'TCP_PERF_SEL_ARR_LINEAR_ALIGNED', + 85: 'TCP_PERF_SEL_ARR_1D_THIN1', + 86: 'TCP_PERF_SEL_ARR_1D_THICK', + 87: 'TCP_PERF_SEL_ARR_2D_THIN1', + 88: 'TCP_PERF_SEL_ARR_2D_THICK', + 89: 'TCP_PERF_SEL_ARR_2D_XTHICK', + 90: 'TCP_PERF_SEL_ARR_3D_THIN1', + 91: 'TCP_PERF_SEL_ARR_3D_THICK', + 92: 'TCP_PERF_SEL_ARR_3D_XTHICK', + 93: 'TCP_PERF_SEL_DIM_1D', + 94: 'TCP_PERF_SEL_DIM_2D', + 95: 'TCP_PERF_SEL_DIM_3D', + 96: 'TCP_PERF_SEL_DIM_1D_ARRAY', + 97: 'TCP_PERF_SEL_DIM_2D_ARRAY', + 98: 'TCP_PERF_SEL_DIM_2D_MSAA', + 99: 'TCP_PERF_SEL_DIM_2D_ARRAY_MSAA', + 100: 'TCP_PERF_SEL_DIM_CUBE_ARRAY', + 101: 'TCP_PERF_SEL_CP_TCP_INVALIDATE', + 102: 'TCP_PERF_SEL_TA_TCP_STATE_READ', + 103: 'TCP_PERF_SEL_TAGRAM0_REQ', + 104: 'TCP_PERF_SEL_TAGRAM1_REQ', + 105: 'TCP_PERF_SEL_TAGRAM2_REQ', + 106: 'TCP_PERF_SEL_TAGRAM3_REQ', + 107: 'TCP_PERF_SEL_GATE_EN1', + 108: 'TCP_PERF_SEL_GATE_EN2', + 109: 'TCP_PERF_SEL_CORE_REG_SCLK_VLD', + 110: 'TCP_PERF_SEL_TCC_REQ', + 111: 'TCP_PERF_SEL_TCC_NON_READ_REQ', + 112: 'TCP_PERF_SEL_TCC_BYPASS_READ_REQ', + 113: 'TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ', + 114: 'TCP_PERF_SEL_TCC_VOLATILE_READ_REQ', + 115: 'TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ', + 116: 'TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ', + 117: 'TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ', + 118: 'TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ', + 119: 'TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ', + 120: 'TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ', + 121: 'TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ', + 122: 'TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ', + 123: 'TCP_PERF_SEL_TCC_ATOMIC_REQ', + 124: 'TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ', + 125: 'TCP_PERF_SEL_TCC_DATA_BUS_BUSY', + 126: 'TCP_PERF_SEL_TOTAL_ACCESSES', + 127: 'TCP_PERF_SEL_TOTAL_READ', + 128: 'TCP_PERF_SEL_TOTAL_HIT_LRU_READ', + 129: 'TCP_PERF_SEL_TOTAL_HIT_EVICT_READ', + 130: 'TCP_PERF_SEL_TOTAL_MISS_LRU_READ', + 131: 'TCP_PERF_SEL_TOTAL_MISS_EVICT_READ', + 132: 'TCP_PERF_SEL_TOTAL_NON_READ', + 133: 'TCP_PERF_SEL_TOTAL_WRITE', + 134: 'TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE', + 135: 'TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE', + 136: 'TCP_PERF_SEL_TOTAL_WBINVL1_VOL', + 137: 'TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES', + 138: 'TCP_PERF_SEL_DISPLAY_MICROTILING', + 139: 'TCP_PERF_SEL_THIN_MICROTILING', + 140: 'TCP_PERF_SEL_DEPTH_MICROTILING', + 141: 'TCP_PERF_SEL_ARR_PRT_THIN1', + 142: 'TCP_PERF_SEL_ARR_PRT_2D_THIN1', + 143: 'TCP_PERF_SEL_ARR_PRT_3D_THIN1', + 144: 'TCP_PERF_SEL_ARR_PRT_THICK', + 145: 'TCP_PERF_SEL_ARR_PRT_2D_THICK', + 146: 'TCP_PERF_SEL_ARR_PRT_3D_THICK', + 147: 'TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL', + 148: 'TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL', + 149: 'TCP_PERF_SEL_UNALIGNED', + 150: 'TCP_PERF_SEL_ROTATED_MICROTILING', + 151: 'TCP_PERF_SEL_THICK_MICROTILING', + 152: 'TCP_PERF_SEL_ATC', + 153: 'TCP_PERF_SEL_POWER_STALL', + 154: 'TCP_PERF_SEL_RESERVED_154', + 155: 'TCP_PERF_SEL_TCC_LRU_REQ', + 156: 'TCP_PERF_SEL_TCC_STREAM_REQ', + 157: 'TCP_PERF_SEL_TCC_NC_READ_REQ', + 158: 'TCP_PERF_SEL_TCC_NC_WRITE_REQ', + 159: 'TCP_PERF_SEL_TCC_NC_ATOMIC_REQ', + 160: 'TCP_PERF_SEL_TCC_UC_READ_REQ', + 161: 'TCP_PERF_SEL_TCC_UC_WRITE_REQ', + 162: 'TCP_PERF_SEL_TCC_UC_ATOMIC_REQ', + 163: 'TCP_PERF_SEL_TCC_CC_READ_REQ', + 164: 'TCP_PERF_SEL_TCC_CC_WRITE_REQ', + 165: 'TCP_PERF_SEL_TCC_CC_ATOMIC_REQ', + 166: 'TCP_PERF_SEL_TCC_DCC_REQ', + 167: 'TCP_PERF_SEL_TCC_PHYSICAL_REQ', + 168: 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', + 169: 'TCP_PERF_SEL_VOLATILE', + 170: 'TCP_PERF_SEL_TC_TA_XNACK_STALL', + 171: 'TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL', + 172: 'TCP_PERF_SEL_SHOOTDOWN', + 173: 'TCP_PERF_SEL_UTCL1_TRANSLATION_MISS', + 174: 'TCP_PERF_SEL_UTCL1_PERMISSION_MISS', + 175: 'TCP_PERF_SEL_UTCL1_REQUEST', + 176: 'TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', + 177: 'TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', + 178: 'TCP_PERF_SEL_UTCL1_LFIFO_FULL', + 179: 'TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', + 180: 'TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', + 181: 'TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT', + 182: 'TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', + 183: 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB', + 184: 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA', + 185: 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1', + 186: 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_R', + 187: 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG', + 188: 'TCP_PERF_SEL_IMG_READ_FMT_8_AS_32', + 189: 'TCP_PERF_SEL_IMG_READ_FMT_8_AS_64', + 190: 'TCP_PERF_SEL_IMG_READ_FMT_16_AS_64', + 191: 'TCP_PERF_SEL_IMG_READ_FMT_16_AS_128', + 192: 'TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32', + 193: 'TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64', + 194: 'TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64', + 195: 'TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128', +} +TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0 +TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 1 +TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 2 +TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 3 +TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 4 +TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 5 +TCP_PERF_SEL_LOD_STALL_CYCLES = 6 +TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 7 +TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 8 +TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 9 +TCP_PERF_SEL_ALLOC_STALL_CYCLES = 10 +TCP_PERF_SEL_LFIFO_STALL_CYCLES = 11 +TCP_PERF_SEL_RFIFO_STALL_CYCLES = 12 +TCP_PERF_SEL_TCR_RDRET_STALL = 13 +TCP_PERF_SEL_WRITE_CONFLICT_STALL = 14 +TCP_PERF_SEL_HOLE_READ_STALL = 15 +TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 16 +TCP_PERF_SEL_PENDING_STALL_CYCLES = 17 +TCP_PERF_SEL_READFIFO_STALL_CYCLES = 18 +TCP_PERF_SEL_TCP_LATENCY = 19 +TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 20 +TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 21 +TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 22 +TCP_PERF_SEL_TCC_READ_REQ = 23 +TCP_PERF_SEL_TCC_WRITE_REQ = 24 +TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 25 +TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 26 +TCP_PERF_SEL_TOTAL_LOCAL_READ = 27 +TCP_PERF_SEL_TOTAL_GLOBAL_READ = 28 +TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 29 +TCP_PERF_SEL_TOTAL_GLOBAL_WRITE = 30 +TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 31 +TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 32 +TCP_PERF_SEL_TOTAL_WBINVL1 = 33 +TCP_PERF_SEL_IMG_READ_FMT_1 = 34 +TCP_PERF_SEL_IMG_READ_FMT_8 = 35 +TCP_PERF_SEL_IMG_READ_FMT_16 = 36 +TCP_PERF_SEL_IMG_READ_FMT_32 = 37 +TCP_PERF_SEL_IMG_READ_FMT_32_AS_8 = 38 +TCP_PERF_SEL_IMG_READ_FMT_32_AS_16 = 39 +TCP_PERF_SEL_IMG_READ_FMT_32_AS_128 = 40 +TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE = 41 +TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE = 42 +TCP_PERF_SEL_IMG_READ_FMT_96 = 43 +TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE = 44 +TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE = 45 +TCP_PERF_SEL_IMG_READ_FMT_BC1 = 46 +TCP_PERF_SEL_IMG_READ_FMT_BC2 = 47 +TCP_PERF_SEL_IMG_READ_FMT_BC3 = 48 +TCP_PERF_SEL_IMG_READ_FMT_BC4 = 49 +TCP_PERF_SEL_IMG_READ_FMT_BC5 = 50 +TCP_PERF_SEL_IMG_READ_FMT_BC6 = 51 +TCP_PERF_SEL_IMG_READ_FMT_BC7 = 52 +TCP_PERF_SEL_IMG_READ_FMT_I8 = 53 +TCP_PERF_SEL_IMG_READ_FMT_I16 = 54 +TCP_PERF_SEL_IMG_READ_FMT_I32 = 55 +TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8 = 56 +TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16 = 57 +TCP_PERF_SEL_IMG_READ_FMT_D8 = 58 +TCP_PERF_SEL_IMG_READ_FMT_D16 = 59 +TCP_PERF_SEL_IMG_READ_FMT_D32 = 60 +TCP_PERF_SEL_IMG_WRITE_FMT_8 = 61 +TCP_PERF_SEL_IMG_WRITE_FMT_16 = 62 +TCP_PERF_SEL_IMG_WRITE_FMT_32 = 63 +TCP_PERF_SEL_IMG_WRITE_FMT_64 = 64 +TCP_PERF_SEL_IMG_WRITE_FMT_128 = 65 +TCP_PERF_SEL_IMG_WRITE_FMT_D8 = 66 +TCP_PERF_SEL_IMG_WRITE_FMT_D16 = 67 +TCP_PERF_SEL_IMG_WRITE_FMT_D32 = 68 +TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32 = 69 +TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32 = 70 +TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64 = 71 +TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64 = 72 +TCP_PERF_SEL_BUF_READ_FMT_8 = 73 +TCP_PERF_SEL_BUF_READ_FMT_16 = 74 +TCP_PERF_SEL_BUF_READ_FMT_32 = 75 +TCP_PERF_SEL_BUF_WRITE_FMT_8 = 76 +TCP_PERF_SEL_BUF_WRITE_FMT_16 = 77 +TCP_PERF_SEL_BUF_WRITE_FMT_32 = 78 +TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32 = 79 +TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32 = 80 +TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64 = 81 +TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64 = 82 +TCP_PERF_SEL_ARR_LINEAR_GENERAL = 83 +TCP_PERF_SEL_ARR_LINEAR_ALIGNED = 84 +TCP_PERF_SEL_ARR_1D_THIN1 = 85 +TCP_PERF_SEL_ARR_1D_THICK = 86 +TCP_PERF_SEL_ARR_2D_THIN1 = 87 +TCP_PERF_SEL_ARR_2D_THICK = 88 +TCP_PERF_SEL_ARR_2D_XTHICK = 89 +TCP_PERF_SEL_ARR_3D_THIN1 = 90 +TCP_PERF_SEL_ARR_3D_THICK = 91 +TCP_PERF_SEL_ARR_3D_XTHICK = 92 +TCP_PERF_SEL_DIM_1D = 93 +TCP_PERF_SEL_DIM_2D = 94 +TCP_PERF_SEL_DIM_3D = 95 +TCP_PERF_SEL_DIM_1D_ARRAY = 96 +TCP_PERF_SEL_DIM_2D_ARRAY = 97 +TCP_PERF_SEL_DIM_2D_MSAA = 98 +TCP_PERF_SEL_DIM_2D_ARRAY_MSAA = 99 +TCP_PERF_SEL_DIM_CUBE_ARRAY = 100 +TCP_PERF_SEL_CP_TCP_INVALIDATE = 101 +TCP_PERF_SEL_TA_TCP_STATE_READ = 102 +TCP_PERF_SEL_TAGRAM0_REQ = 103 +TCP_PERF_SEL_TAGRAM1_REQ = 104 +TCP_PERF_SEL_TAGRAM2_REQ = 105 +TCP_PERF_SEL_TAGRAM3_REQ = 106 +TCP_PERF_SEL_GATE_EN1 = 107 +TCP_PERF_SEL_GATE_EN2 = 108 +TCP_PERF_SEL_CORE_REG_SCLK_VLD = 109 +TCP_PERF_SEL_TCC_REQ = 110 +TCP_PERF_SEL_TCC_NON_READ_REQ = 111 +TCP_PERF_SEL_TCC_BYPASS_READ_REQ = 112 +TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ = 113 +TCP_PERF_SEL_TCC_VOLATILE_READ_REQ = 114 +TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ = 115 +TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ = 116 +TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ = 117 +TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ = 118 +TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ = 119 +TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ = 120 +TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ = 121 +TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ = 122 +TCP_PERF_SEL_TCC_ATOMIC_REQ = 123 +TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ = 124 +TCP_PERF_SEL_TCC_DATA_BUS_BUSY = 125 +TCP_PERF_SEL_TOTAL_ACCESSES = 126 +TCP_PERF_SEL_TOTAL_READ = 127 +TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 128 +TCP_PERF_SEL_TOTAL_HIT_EVICT_READ = 129 +TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 130 +TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 131 +TCP_PERF_SEL_TOTAL_NON_READ = 132 +TCP_PERF_SEL_TOTAL_WRITE = 133 +TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 134 +TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 135 +TCP_PERF_SEL_TOTAL_WBINVL1_VOL = 136 +TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 137 +TCP_PERF_SEL_DISPLAY_MICROTILING = 138 +TCP_PERF_SEL_THIN_MICROTILING = 139 +TCP_PERF_SEL_DEPTH_MICROTILING = 140 +TCP_PERF_SEL_ARR_PRT_THIN1 = 141 +TCP_PERF_SEL_ARR_PRT_2D_THIN1 = 142 +TCP_PERF_SEL_ARR_PRT_3D_THIN1 = 143 +TCP_PERF_SEL_ARR_PRT_THICK = 144 +TCP_PERF_SEL_ARR_PRT_2D_THICK = 145 +TCP_PERF_SEL_ARR_PRT_3D_THICK = 146 +TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL = 147 +TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL = 148 +TCP_PERF_SEL_UNALIGNED = 149 +TCP_PERF_SEL_ROTATED_MICROTILING = 150 +TCP_PERF_SEL_THICK_MICROTILING = 151 +TCP_PERF_SEL_ATC = 152 +TCP_PERF_SEL_POWER_STALL = 153 +TCP_PERF_SEL_RESERVED_154 = 154 +TCP_PERF_SEL_TCC_LRU_REQ = 155 +TCP_PERF_SEL_TCC_STREAM_REQ = 156 +TCP_PERF_SEL_TCC_NC_READ_REQ = 157 +TCP_PERF_SEL_TCC_NC_WRITE_REQ = 158 +TCP_PERF_SEL_TCC_NC_ATOMIC_REQ = 159 +TCP_PERF_SEL_TCC_UC_READ_REQ = 160 +TCP_PERF_SEL_TCC_UC_WRITE_REQ = 161 +TCP_PERF_SEL_TCC_UC_ATOMIC_REQ = 162 +TCP_PERF_SEL_TCC_CC_READ_REQ = 163 +TCP_PERF_SEL_TCC_CC_WRITE_REQ = 164 +TCP_PERF_SEL_TCC_CC_ATOMIC_REQ = 165 +TCP_PERF_SEL_TCC_DCC_REQ = 166 +TCP_PERF_SEL_TCC_PHYSICAL_REQ = 167 +TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 168 +TCP_PERF_SEL_VOLATILE = 169 +TCP_PERF_SEL_TC_TA_XNACK_STALL = 170 +TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL = 171 +TCP_PERF_SEL_SHOOTDOWN = 172 +TCP_PERF_SEL_UTCL1_TRANSLATION_MISS = 173 +TCP_PERF_SEL_UTCL1_PERMISSION_MISS = 174 +TCP_PERF_SEL_UTCL1_REQUEST = 175 +TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 176 +TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 177 +TCP_PERF_SEL_UTCL1_LFIFO_FULL = 178 +TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 179 +TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 180 +TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT = 181 +TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 182 +TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB = 183 +TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA = 184 +TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1 = 185 +TCP_PERF_SEL_IMG_READ_FMT_ETC2_R = 186 +TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG = 187 +TCP_PERF_SEL_IMG_READ_FMT_8_AS_32 = 188 +TCP_PERF_SEL_IMG_READ_FMT_8_AS_64 = 189 +TCP_PERF_SEL_IMG_READ_FMT_16_AS_64 = 190 +TCP_PERF_SEL_IMG_READ_FMT_16_AS_128 = 191 +TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32 = 192 +TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64 = 193 +TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64 = 194 +TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128 = 195 +TCP_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_CACHE_POLICIES' +TCP_CACHE_POLICIES__enumvalues = { + 0: 'TCP_CACHE_POLICY_MISS_LRU', + 1: 'TCP_CACHE_POLICY_MISS_EVICT', + 2: 'TCP_CACHE_POLICY_HIT_LRU', + 3: 'TCP_CACHE_POLICY_HIT_EVICT', +} +TCP_CACHE_POLICY_MISS_LRU = 0 +TCP_CACHE_POLICY_MISS_EVICT = 1 +TCP_CACHE_POLICY_HIT_LRU = 2 +TCP_CACHE_POLICY_HIT_EVICT = 3 +TCP_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_CACHE_STORE_POLICIES' +TCP_CACHE_STORE_POLICIES__enumvalues = { + 0: 'TCP_CACHE_STORE_POLICY_WT_LRU', + 1: 'TCP_CACHE_STORE_POLICY_WT_EVICT', +} +TCP_CACHE_STORE_POLICY_WT_LRU = 0 +TCP_CACHE_STORE_POLICY_WT_EVICT = 1 +TCP_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_WATCH_MODES' +TCP_WATCH_MODES__enumvalues = { + 0: 'TCP_WATCH_MODE_READ', + 1: 'TCP_WATCH_MODE_NONREAD', + 2: 'TCP_WATCH_MODE_ATOMIC', + 3: 'TCP_WATCH_MODE_ALL', +} +TCP_WATCH_MODE_READ = 0 +TCP_WATCH_MODE_NONREAD = 1 +TCP_WATCH_MODE_ATOMIC = 2 +TCP_WATCH_MODE_ALL = 3 +TCP_WATCH_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_DSM_DATA_SEL' +TCP_DSM_DATA_SEL__enumvalues = { + 0: 'TCP_DSM_DISABLE', + 1: 'TCP_DSM_SEL0', + 2: 'TCP_DSM_SEL1', + 3: 'TCP_DSM_SEL_BOTH', +} +TCP_DSM_DISABLE = 0 +TCP_DSM_SEL0 = 1 +TCP_DSM_SEL1 = 2 +TCP_DSM_SEL_BOTH = 3 +TCP_DSM_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_DSM_SINGLE_WRITE' +TCP_DSM_SINGLE_WRITE__enumvalues = { + 0: 'TCP_DSM_SINGLE_WRITE_DIS', + 1: 'TCP_DSM_SINGLE_WRITE_EN', +} +TCP_DSM_SINGLE_WRITE_DIS = 0 +TCP_DSM_SINGLE_WRITE_EN = 1 +TCP_DSM_SINGLE_WRITE = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_DSM_INJECT_SEL' +TCP_DSM_INJECT_SEL__enumvalues = { + 0: 'TCP_DSM_INJECT_SEL0', + 1: 'TCP_DSM_INJECT_SEL1', + 2: 'TCP_DSM_INJECT_SEL2', + 3: 'TCP_DSM_INJECT_SEL3', +} +TCP_DSM_INJECT_SEL0 = 0 +TCP_DSM_INJECT_SEL1 = 1 +TCP_DSM_INJECT_SEL2 = 2 +TCP_DSM_INJECT_SEL3 = 3 +TCP_DSM_INJECT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TCC_PERF_SEL' +TCC_PERF_SEL__enumvalues = { + 0: 'TCC_PERF_SEL_NONE', + 1: 'TCC_PERF_SEL_CYCLE', + 2: 'TCC_PERF_SEL_BUSY', + 3: 'TCC_PERF_SEL_REQ', + 4: 'TCC_PERF_SEL_STREAMING_REQ', + 5: 'TCC_PERF_SEL_EXE_REQ', + 6: 'TCC_PERF_SEL_COMPRESSED_REQ', + 7: 'TCC_PERF_SEL_COMPRESSED_0_REQ', + 8: 'TCC_PERF_SEL_METADATA_REQ', + 9: 'TCC_PERF_SEL_NC_VIRTUAL_REQ', + 10: 'TCC_PERF_SEL_UC_VIRTUAL_REQ', + 11: 'TCC_PERF_SEL_CC_PHYSICAL_REQ', + 12: 'TCC_PERF_SEL_PROBE', + 13: 'TCC_PERF_SEL_PROBE_ALL', + 14: 'TCC_PERF_SEL_READ', + 15: 'TCC_PERF_SEL_WRITE', + 16: 'TCC_PERF_SEL_ATOMIC', + 17: 'TCC_PERF_SEL_HIT', + 18: 'TCC_PERF_SEL_SECTOR_HIT', + 19: 'TCC_PERF_SEL_MISS', + 20: 'TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT', + 21: 'TCC_PERF_SEL_FULLY_WRITTEN_HIT', + 22: 'TCC_PERF_SEL_WRITEBACK', + 23: 'TCC_PERF_SEL_LATENCY_FIFO_FULL', + 24: 'TCC_PERF_SEL_SRC_FIFO_FULL', + 25: 'TCC_PERF_SEL_HOLE_FIFO_FULL', + 26: 'TCC_PERF_SEL_EA_WRREQ', + 27: 'TCC_PERF_SEL_EA_WRREQ_64B', + 28: 'TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND', + 29: 'TCC_PERF_SEL_EA_WR_UNCACHED_32B', + 30: 'TCC_PERF_SEL_EA_WRREQ_STALL', + 31: 'TCC_PERF_SEL_EA_WRREQ_CREDIT_STALL', + 32: 'TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', + 33: 'TCC_PERF_SEL_EA_WRREQ_LEVEL', + 34: 'TCC_PERF_SEL_EA_ATOMIC', + 35: 'TCC_PERF_SEL_EA_ATOMIC_LEVEL', + 36: 'TCC_PERF_SEL_EA_RDREQ', + 37: 'TCC_PERF_SEL_EA_RDREQ_32B', + 38: 'TCC_PERF_SEL_EA_RD_UNCACHED_32B', + 39: 'TCC_PERF_SEL_EA_RD_MDC_32B', + 40: 'TCC_PERF_SEL_EA_RD_COMPRESSED_32B', + 41: 'TCC_PERF_SEL_EA_RDREQ_CREDIT_STALL', + 42: 'TCC_PERF_SEL_EA_RDREQ_LEVEL', + 43: 'TCC_PERF_SEL_TAG_STALL', + 44: 'TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', + 45: 'TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', + 46: 'TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', + 47: 'TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', + 48: 'TCC_PERF_SEL_TAG_PROBE_STALL', + 49: 'TCC_PERF_SEL_TAG_PROBE_FILTER_STALL', + 50: 'TCC_PERF_SEL_READ_RETURN_TIMEOUT', + 51: 'TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT', + 52: 'TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE', + 53: 'TCC_PERF_SEL_BUBBLE', + 54: 'TCC_PERF_SEL_RETURN_ACK', + 55: 'TCC_PERF_SEL_RETURN_DATA', + 56: 'TCC_PERF_SEL_RETURN_HOLE', + 57: 'TCC_PERF_SEL_RETURN_ACK_HOLE', + 58: 'TCC_PERF_SEL_IB_REQ', + 59: 'TCC_PERF_SEL_IB_STALL', + 60: 'TCC_PERF_SEL_IB_TAG_STALL', + 61: 'TCC_PERF_SEL_IB_MDC_STALL', + 62: 'TCC_PERF_SEL_TCA_LEVEL', + 63: 'TCC_PERF_SEL_HOLE_LEVEL', + 64: 'TCC_PERF_SEL_NORMAL_WRITEBACK', + 65: 'TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK', + 66: 'TCC_PERF_SEL_TC_OP_WBL2_WC_WRITEBACK', + 67: 'TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK', + 68: 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK', + 69: 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK', + 70: 'TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK', + 71: 'TCC_PERF_SEL_NORMAL_EVICT', + 72: 'TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT', + 73: 'TCC_PERF_SEL_TC_OP_WBL2_WC_EVICT', + 74: 'TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT', + 75: 'TCC_PERF_SEL_TC_OP_WBINVL2_EVICT', + 76: 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT', + 77: 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT', + 78: 'TCC_PERF_SEL_ALL_TC_OP_INV_EVICT', + 79: 'TCC_PERF_SEL_PROBE_EVICT', + 80: 'TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE', + 81: 'TCC_PERF_SEL_TC_OP_WBL2_WC_CYCLE', + 82: 'TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE', + 83: 'TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE', + 84: 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE', + 85: 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE', + 86: 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE', + 87: 'TCC_PERF_SEL_TC_OP_WBL2_NC_START', + 88: 'TCC_PERF_SEL_TC_OP_WBL2_WC_START', + 89: 'TCC_PERF_SEL_TC_OP_INVL2_NC_START', + 90: 'TCC_PERF_SEL_TC_OP_WBINVL2_START', + 91: 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_START', + 92: 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_START', + 93: 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', + 94: 'TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH', + 95: 'TCC_PERF_SEL_TC_OP_WBL2_WC_FINISH', + 96: 'TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH', + 97: 'TCC_PERF_SEL_TC_OP_WBINVL2_FINISH', + 98: 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH', + 99: 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH', + 100: 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH', + 101: 'TCC_PERF_SEL_MDC_REQ', + 102: 'TCC_PERF_SEL_MDC_LEVEL', + 103: 'TCC_PERF_SEL_MDC_TAG_HIT', + 104: 'TCC_PERF_SEL_MDC_SECTOR_HIT', + 105: 'TCC_PERF_SEL_MDC_SECTOR_MISS', + 106: 'TCC_PERF_SEL_MDC_TAG_STALL', + 107: 'TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', + 108: 'TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', + 109: 'TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', + 110: 'TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', + 111: 'TCC_PERF_SEL_PROBE_FILTER_DISABLED', + 128: 'TCC_PERF_SEL_CLIENT0_REQ', + 129: 'TCC_PERF_SEL_CLIENT1_REQ', + 130: 'TCC_PERF_SEL_CLIENT2_REQ', + 131: 'TCC_PERF_SEL_CLIENT3_REQ', + 132: 'TCC_PERF_SEL_CLIENT4_REQ', + 133: 'TCC_PERF_SEL_CLIENT5_REQ', + 134: 'TCC_PERF_SEL_CLIENT6_REQ', + 135: 'TCC_PERF_SEL_CLIENT7_REQ', + 136: 'TCC_PERF_SEL_CLIENT8_REQ', + 137: 'TCC_PERF_SEL_CLIENT9_REQ', + 138: 'TCC_PERF_SEL_CLIENT10_REQ', + 139: 'TCC_PERF_SEL_CLIENT11_REQ', + 140: 'TCC_PERF_SEL_CLIENT12_REQ', + 141: 'TCC_PERF_SEL_CLIENT13_REQ', + 142: 'TCC_PERF_SEL_CLIENT14_REQ', + 143: 'TCC_PERF_SEL_CLIENT15_REQ', + 144: 'TCC_PERF_SEL_CLIENT16_REQ', + 145: 'TCC_PERF_SEL_CLIENT17_REQ', + 146: 'TCC_PERF_SEL_CLIENT18_REQ', + 147: 'TCC_PERF_SEL_CLIENT19_REQ', + 148: 'TCC_PERF_SEL_CLIENT20_REQ', + 149: 'TCC_PERF_SEL_CLIENT21_REQ', + 150: 'TCC_PERF_SEL_CLIENT22_REQ', + 151: 'TCC_PERF_SEL_CLIENT23_REQ', + 152: 'TCC_PERF_SEL_CLIENT24_REQ', + 153: 'TCC_PERF_SEL_CLIENT25_REQ', + 154: 'TCC_PERF_SEL_CLIENT26_REQ', + 155: 'TCC_PERF_SEL_CLIENT27_REQ', + 156: 'TCC_PERF_SEL_CLIENT28_REQ', + 157: 'TCC_PERF_SEL_CLIENT29_REQ', + 158: 'TCC_PERF_SEL_CLIENT30_REQ', + 159: 'TCC_PERF_SEL_CLIENT31_REQ', + 160: 'TCC_PERF_SEL_CLIENT32_REQ', + 161: 'TCC_PERF_SEL_CLIENT33_REQ', + 162: 'TCC_PERF_SEL_CLIENT34_REQ', + 163: 'TCC_PERF_SEL_CLIENT35_REQ', + 164: 'TCC_PERF_SEL_CLIENT36_REQ', + 165: 'TCC_PERF_SEL_CLIENT37_REQ', + 166: 'TCC_PERF_SEL_CLIENT38_REQ', + 167: 'TCC_PERF_SEL_CLIENT39_REQ', + 168: 'TCC_PERF_SEL_CLIENT40_REQ', + 169: 'TCC_PERF_SEL_CLIENT41_REQ', + 170: 'TCC_PERF_SEL_CLIENT42_REQ', + 171: 'TCC_PERF_SEL_CLIENT43_REQ', + 172: 'TCC_PERF_SEL_CLIENT44_REQ', + 173: 'TCC_PERF_SEL_CLIENT45_REQ', + 174: 'TCC_PERF_SEL_CLIENT46_REQ', + 175: 'TCC_PERF_SEL_CLIENT47_REQ', + 176: 'TCC_PERF_SEL_CLIENT48_REQ', + 177: 'TCC_PERF_SEL_CLIENT49_REQ', + 178: 'TCC_PERF_SEL_CLIENT50_REQ', + 179: 'TCC_PERF_SEL_CLIENT51_REQ', + 180: 'TCC_PERF_SEL_CLIENT52_REQ', + 181: 'TCC_PERF_SEL_CLIENT53_REQ', + 182: 'TCC_PERF_SEL_CLIENT54_REQ', + 183: 'TCC_PERF_SEL_CLIENT55_REQ', + 184: 'TCC_PERF_SEL_CLIENT56_REQ', + 185: 'TCC_PERF_SEL_CLIENT57_REQ', + 186: 'TCC_PERF_SEL_CLIENT58_REQ', + 187: 'TCC_PERF_SEL_CLIENT59_REQ', + 188: 'TCC_PERF_SEL_CLIENT60_REQ', + 189: 'TCC_PERF_SEL_CLIENT61_REQ', + 190: 'TCC_PERF_SEL_CLIENT62_REQ', + 191: 'TCC_PERF_SEL_CLIENT63_REQ', + 192: 'TCC_PERF_SEL_CLIENT64_REQ', + 193: 'TCC_PERF_SEL_CLIENT65_REQ', + 194: 'TCC_PERF_SEL_CLIENT66_REQ', + 195: 'TCC_PERF_SEL_CLIENT67_REQ', + 196: 'TCC_PERF_SEL_CLIENT68_REQ', + 197: 'TCC_PERF_SEL_CLIENT69_REQ', + 198: 'TCC_PERF_SEL_CLIENT70_REQ', + 199: 'TCC_PERF_SEL_CLIENT71_REQ', + 200: 'TCC_PERF_SEL_CLIENT72_REQ', + 201: 'TCC_PERF_SEL_CLIENT73_REQ', + 202: 'TCC_PERF_SEL_CLIENT74_REQ', + 203: 'TCC_PERF_SEL_CLIENT75_REQ', + 204: 'TCC_PERF_SEL_CLIENT76_REQ', + 205: 'TCC_PERF_SEL_CLIENT77_REQ', + 206: 'TCC_PERF_SEL_CLIENT78_REQ', + 207: 'TCC_PERF_SEL_CLIENT79_REQ', + 208: 'TCC_PERF_SEL_CLIENT80_REQ', + 209: 'TCC_PERF_SEL_CLIENT81_REQ', + 210: 'TCC_PERF_SEL_CLIENT82_REQ', + 211: 'TCC_PERF_SEL_CLIENT83_REQ', + 212: 'TCC_PERF_SEL_CLIENT84_REQ', + 213: 'TCC_PERF_SEL_CLIENT85_REQ', + 214: 'TCC_PERF_SEL_CLIENT86_REQ', + 215: 'TCC_PERF_SEL_CLIENT87_REQ', + 216: 'TCC_PERF_SEL_CLIENT88_REQ', + 217: 'TCC_PERF_SEL_CLIENT89_REQ', + 218: 'TCC_PERF_SEL_CLIENT90_REQ', + 219: 'TCC_PERF_SEL_CLIENT91_REQ', + 220: 'TCC_PERF_SEL_CLIENT92_REQ', + 221: 'TCC_PERF_SEL_CLIENT93_REQ', + 222: 'TCC_PERF_SEL_CLIENT94_REQ', + 223: 'TCC_PERF_SEL_CLIENT95_REQ', + 224: 'TCC_PERF_SEL_CLIENT96_REQ', + 225: 'TCC_PERF_SEL_CLIENT97_REQ', + 226: 'TCC_PERF_SEL_CLIENT98_REQ', + 227: 'TCC_PERF_SEL_CLIENT99_REQ', + 228: 'TCC_PERF_SEL_CLIENT100_REQ', + 229: 'TCC_PERF_SEL_CLIENT101_REQ', + 230: 'TCC_PERF_SEL_CLIENT102_REQ', + 231: 'TCC_PERF_SEL_CLIENT103_REQ', + 232: 'TCC_PERF_SEL_CLIENT104_REQ', + 233: 'TCC_PERF_SEL_CLIENT105_REQ', + 234: 'TCC_PERF_SEL_CLIENT106_REQ', + 235: 'TCC_PERF_SEL_CLIENT107_REQ', + 236: 'TCC_PERF_SEL_CLIENT108_REQ', + 237: 'TCC_PERF_SEL_CLIENT109_REQ', + 238: 'TCC_PERF_SEL_CLIENT110_REQ', + 239: 'TCC_PERF_SEL_CLIENT111_REQ', + 240: 'TCC_PERF_SEL_CLIENT112_REQ', + 241: 'TCC_PERF_SEL_CLIENT113_REQ', + 242: 'TCC_PERF_SEL_CLIENT114_REQ', + 243: 'TCC_PERF_SEL_CLIENT115_REQ', + 244: 'TCC_PERF_SEL_CLIENT116_REQ', + 245: 'TCC_PERF_SEL_CLIENT117_REQ', + 246: 'TCC_PERF_SEL_CLIENT118_REQ', + 247: 'TCC_PERF_SEL_CLIENT119_REQ', + 248: 'TCC_PERF_SEL_CLIENT120_REQ', + 249: 'TCC_PERF_SEL_CLIENT121_REQ', + 250: 'TCC_PERF_SEL_CLIENT122_REQ', + 251: 'TCC_PERF_SEL_CLIENT123_REQ', + 252: 'TCC_PERF_SEL_CLIENT124_REQ', + 253: 'TCC_PERF_SEL_CLIENT125_REQ', + 254: 'TCC_PERF_SEL_CLIENT126_REQ', + 255: 'TCC_PERF_SEL_CLIENT127_REQ', +} +TCC_PERF_SEL_NONE = 0 +TCC_PERF_SEL_CYCLE = 1 +TCC_PERF_SEL_BUSY = 2 +TCC_PERF_SEL_REQ = 3 +TCC_PERF_SEL_STREAMING_REQ = 4 +TCC_PERF_SEL_EXE_REQ = 5 +TCC_PERF_SEL_COMPRESSED_REQ = 6 +TCC_PERF_SEL_COMPRESSED_0_REQ = 7 +TCC_PERF_SEL_METADATA_REQ = 8 +TCC_PERF_SEL_NC_VIRTUAL_REQ = 9 +TCC_PERF_SEL_UC_VIRTUAL_REQ = 10 +TCC_PERF_SEL_CC_PHYSICAL_REQ = 11 +TCC_PERF_SEL_PROBE = 12 +TCC_PERF_SEL_PROBE_ALL = 13 +TCC_PERF_SEL_READ = 14 +TCC_PERF_SEL_WRITE = 15 +TCC_PERF_SEL_ATOMIC = 16 +TCC_PERF_SEL_HIT = 17 +TCC_PERF_SEL_SECTOR_HIT = 18 +TCC_PERF_SEL_MISS = 19 +TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT = 20 +TCC_PERF_SEL_FULLY_WRITTEN_HIT = 21 +TCC_PERF_SEL_WRITEBACK = 22 +TCC_PERF_SEL_LATENCY_FIFO_FULL = 23 +TCC_PERF_SEL_SRC_FIFO_FULL = 24 +TCC_PERF_SEL_HOLE_FIFO_FULL = 25 +TCC_PERF_SEL_EA_WRREQ = 26 +TCC_PERF_SEL_EA_WRREQ_64B = 27 +TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 28 +TCC_PERF_SEL_EA_WR_UNCACHED_32B = 29 +TCC_PERF_SEL_EA_WRREQ_STALL = 30 +TCC_PERF_SEL_EA_WRREQ_CREDIT_STALL = 31 +TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 32 +TCC_PERF_SEL_EA_WRREQ_LEVEL = 33 +TCC_PERF_SEL_EA_ATOMIC = 34 +TCC_PERF_SEL_EA_ATOMIC_LEVEL = 35 +TCC_PERF_SEL_EA_RDREQ = 36 +TCC_PERF_SEL_EA_RDREQ_32B = 37 +TCC_PERF_SEL_EA_RD_UNCACHED_32B = 38 +TCC_PERF_SEL_EA_RD_MDC_32B = 39 +TCC_PERF_SEL_EA_RD_COMPRESSED_32B = 40 +TCC_PERF_SEL_EA_RDREQ_CREDIT_STALL = 41 +TCC_PERF_SEL_EA_RDREQ_LEVEL = 42 +TCC_PERF_SEL_TAG_STALL = 43 +TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 44 +TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 45 +TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 46 +TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 47 +TCC_PERF_SEL_TAG_PROBE_STALL = 48 +TCC_PERF_SEL_TAG_PROBE_FILTER_STALL = 49 +TCC_PERF_SEL_READ_RETURN_TIMEOUT = 50 +TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT = 51 +TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE = 52 +TCC_PERF_SEL_BUBBLE = 53 +TCC_PERF_SEL_RETURN_ACK = 54 +TCC_PERF_SEL_RETURN_DATA = 55 +TCC_PERF_SEL_RETURN_HOLE = 56 +TCC_PERF_SEL_RETURN_ACK_HOLE = 57 +TCC_PERF_SEL_IB_REQ = 58 +TCC_PERF_SEL_IB_STALL = 59 +TCC_PERF_SEL_IB_TAG_STALL = 60 +TCC_PERF_SEL_IB_MDC_STALL = 61 +TCC_PERF_SEL_TCA_LEVEL = 62 +TCC_PERF_SEL_HOLE_LEVEL = 63 +TCC_PERF_SEL_NORMAL_WRITEBACK = 64 +TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK = 65 +TCC_PERF_SEL_TC_OP_WBL2_WC_WRITEBACK = 66 +TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK = 67 +TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK = 68 +TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK = 69 +TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK = 70 +TCC_PERF_SEL_NORMAL_EVICT = 71 +TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT = 72 +TCC_PERF_SEL_TC_OP_WBL2_WC_EVICT = 73 +TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT = 74 +TCC_PERF_SEL_TC_OP_WBINVL2_EVICT = 75 +TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT = 76 +TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT = 77 +TCC_PERF_SEL_ALL_TC_OP_INV_EVICT = 78 +TCC_PERF_SEL_PROBE_EVICT = 79 +TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE = 80 +TCC_PERF_SEL_TC_OP_WBL2_WC_CYCLE = 81 +TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE = 82 +TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE = 83 +TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE = 84 +TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE = 85 +TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE = 86 +TCC_PERF_SEL_TC_OP_WBL2_NC_START = 87 +TCC_PERF_SEL_TC_OP_WBL2_WC_START = 88 +TCC_PERF_SEL_TC_OP_INVL2_NC_START = 89 +TCC_PERF_SEL_TC_OP_WBINVL2_START = 90 +TCC_PERF_SEL_TC_OP_WBINVL2_NC_START = 91 +TCC_PERF_SEL_TC_OP_WBINVL2_SD_START = 92 +TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 93 +TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH = 94 +TCC_PERF_SEL_TC_OP_WBL2_WC_FINISH = 95 +TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH = 96 +TCC_PERF_SEL_TC_OP_WBINVL2_FINISH = 97 +TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH = 98 +TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH = 99 +TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH = 100 +TCC_PERF_SEL_MDC_REQ = 101 +TCC_PERF_SEL_MDC_LEVEL = 102 +TCC_PERF_SEL_MDC_TAG_HIT = 103 +TCC_PERF_SEL_MDC_SECTOR_HIT = 104 +TCC_PERF_SEL_MDC_SECTOR_MISS = 105 +TCC_PERF_SEL_MDC_TAG_STALL = 106 +TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 107 +TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 108 +TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 109 +TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 110 +TCC_PERF_SEL_PROBE_FILTER_DISABLED = 111 +TCC_PERF_SEL_CLIENT0_REQ = 128 +TCC_PERF_SEL_CLIENT1_REQ = 129 +TCC_PERF_SEL_CLIENT2_REQ = 130 +TCC_PERF_SEL_CLIENT3_REQ = 131 +TCC_PERF_SEL_CLIENT4_REQ = 132 +TCC_PERF_SEL_CLIENT5_REQ = 133 +TCC_PERF_SEL_CLIENT6_REQ = 134 +TCC_PERF_SEL_CLIENT7_REQ = 135 +TCC_PERF_SEL_CLIENT8_REQ = 136 +TCC_PERF_SEL_CLIENT9_REQ = 137 +TCC_PERF_SEL_CLIENT10_REQ = 138 +TCC_PERF_SEL_CLIENT11_REQ = 139 +TCC_PERF_SEL_CLIENT12_REQ = 140 +TCC_PERF_SEL_CLIENT13_REQ = 141 +TCC_PERF_SEL_CLIENT14_REQ = 142 +TCC_PERF_SEL_CLIENT15_REQ = 143 +TCC_PERF_SEL_CLIENT16_REQ = 144 +TCC_PERF_SEL_CLIENT17_REQ = 145 +TCC_PERF_SEL_CLIENT18_REQ = 146 +TCC_PERF_SEL_CLIENT19_REQ = 147 +TCC_PERF_SEL_CLIENT20_REQ = 148 +TCC_PERF_SEL_CLIENT21_REQ = 149 +TCC_PERF_SEL_CLIENT22_REQ = 150 +TCC_PERF_SEL_CLIENT23_REQ = 151 +TCC_PERF_SEL_CLIENT24_REQ = 152 +TCC_PERF_SEL_CLIENT25_REQ = 153 +TCC_PERF_SEL_CLIENT26_REQ = 154 +TCC_PERF_SEL_CLIENT27_REQ = 155 +TCC_PERF_SEL_CLIENT28_REQ = 156 +TCC_PERF_SEL_CLIENT29_REQ = 157 +TCC_PERF_SEL_CLIENT30_REQ = 158 +TCC_PERF_SEL_CLIENT31_REQ = 159 +TCC_PERF_SEL_CLIENT32_REQ = 160 +TCC_PERF_SEL_CLIENT33_REQ = 161 +TCC_PERF_SEL_CLIENT34_REQ = 162 +TCC_PERF_SEL_CLIENT35_REQ = 163 +TCC_PERF_SEL_CLIENT36_REQ = 164 +TCC_PERF_SEL_CLIENT37_REQ = 165 +TCC_PERF_SEL_CLIENT38_REQ = 166 +TCC_PERF_SEL_CLIENT39_REQ = 167 +TCC_PERF_SEL_CLIENT40_REQ = 168 +TCC_PERF_SEL_CLIENT41_REQ = 169 +TCC_PERF_SEL_CLIENT42_REQ = 170 +TCC_PERF_SEL_CLIENT43_REQ = 171 +TCC_PERF_SEL_CLIENT44_REQ = 172 +TCC_PERF_SEL_CLIENT45_REQ = 173 +TCC_PERF_SEL_CLIENT46_REQ = 174 +TCC_PERF_SEL_CLIENT47_REQ = 175 +TCC_PERF_SEL_CLIENT48_REQ = 176 +TCC_PERF_SEL_CLIENT49_REQ = 177 +TCC_PERF_SEL_CLIENT50_REQ = 178 +TCC_PERF_SEL_CLIENT51_REQ = 179 +TCC_PERF_SEL_CLIENT52_REQ = 180 +TCC_PERF_SEL_CLIENT53_REQ = 181 +TCC_PERF_SEL_CLIENT54_REQ = 182 +TCC_PERF_SEL_CLIENT55_REQ = 183 +TCC_PERF_SEL_CLIENT56_REQ = 184 +TCC_PERF_SEL_CLIENT57_REQ = 185 +TCC_PERF_SEL_CLIENT58_REQ = 186 +TCC_PERF_SEL_CLIENT59_REQ = 187 +TCC_PERF_SEL_CLIENT60_REQ = 188 +TCC_PERF_SEL_CLIENT61_REQ = 189 +TCC_PERF_SEL_CLIENT62_REQ = 190 +TCC_PERF_SEL_CLIENT63_REQ = 191 +TCC_PERF_SEL_CLIENT64_REQ = 192 +TCC_PERF_SEL_CLIENT65_REQ = 193 +TCC_PERF_SEL_CLIENT66_REQ = 194 +TCC_PERF_SEL_CLIENT67_REQ = 195 +TCC_PERF_SEL_CLIENT68_REQ = 196 +TCC_PERF_SEL_CLIENT69_REQ = 197 +TCC_PERF_SEL_CLIENT70_REQ = 198 +TCC_PERF_SEL_CLIENT71_REQ = 199 +TCC_PERF_SEL_CLIENT72_REQ = 200 +TCC_PERF_SEL_CLIENT73_REQ = 201 +TCC_PERF_SEL_CLIENT74_REQ = 202 +TCC_PERF_SEL_CLIENT75_REQ = 203 +TCC_PERF_SEL_CLIENT76_REQ = 204 +TCC_PERF_SEL_CLIENT77_REQ = 205 +TCC_PERF_SEL_CLIENT78_REQ = 206 +TCC_PERF_SEL_CLIENT79_REQ = 207 +TCC_PERF_SEL_CLIENT80_REQ = 208 +TCC_PERF_SEL_CLIENT81_REQ = 209 +TCC_PERF_SEL_CLIENT82_REQ = 210 +TCC_PERF_SEL_CLIENT83_REQ = 211 +TCC_PERF_SEL_CLIENT84_REQ = 212 +TCC_PERF_SEL_CLIENT85_REQ = 213 +TCC_PERF_SEL_CLIENT86_REQ = 214 +TCC_PERF_SEL_CLIENT87_REQ = 215 +TCC_PERF_SEL_CLIENT88_REQ = 216 +TCC_PERF_SEL_CLIENT89_REQ = 217 +TCC_PERF_SEL_CLIENT90_REQ = 218 +TCC_PERF_SEL_CLIENT91_REQ = 219 +TCC_PERF_SEL_CLIENT92_REQ = 220 +TCC_PERF_SEL_CLIENT93_REQ = 221 +TCC_PERF_SEL_CLIENT94_REQ = 222 +TCC_PERF_SEL_CLIENT95_REQ = 223 +TCC_PERF_SEL_CLIENT96_REQ = 224 +TCC_PERF_SEL_CLIENT97_REQ = 225 +TCC_PERF_SEL_CLIENT98_REQ = 226 +TCC_PERF_SEL_CLIENT99_REQ = 227 +TCC_PERF_SEL_CLIENT100_REQ = 228 +TCC_PERF_SEL_CLIENT101_REQ = 229 +TCC_PERF_SEL_CLIENT102_REQ = 230 +TCC_PERF_SEL_CLIENT103_REQ = 231 +TCC_PERF_SEL_CLIENT104_REQ = 232 +TCC_PERF_SEL_CLIENT105_REQ = 233 +TCC_PERF_SEL_CLIENT106_REQ = 234 +TCC_PERF_SEL_CLIENT107_REQ = 235 +TCC_PERF_SEL_CLIENT108_REQ = 236 +TCC_PERF_SEL_CLIENT109_REQ = 237 +TCC_PERF_SEL_CLIENT110_REQ = 238 +TCC_PERF_SEL_CLIENT111_REQ = 239 +TCC_PERF_SEL_CLIENT112_REQ = 240 +TCC_PERF_SEL_CLIENT113_REQ = 241 +TCC_PERF_SEL_CLIENT114_REQ = 242 +TCC_PERF_SEL_CLIENT115_REQ = 243 +TCC_PERF_SEL_CLIENT116_REQ = 244 +TCC_PERF_SEL_CLIENT117_REQ = 245 +TCC_PERF_SEL_CLIENT118_REQ = 246 +TCC_PERF_SEL_CLIENT119_REQ = 247 +TCC_PERF_SEL_CLIENT120_REQ = 248 +TCC_PERF_SEL_CLIENT121_REQ = 249 +TCC_PERF_SEL_CLIENT122_REQ = 250 +TCC_PERF_SEL_CLIENT123_REQ = 251 +TCC_PERF_SEL_CLIENT124_REQ = 252 +TCC_PERF_SEL_CLIENT125_REQ = 253 +TCC_PERF_SEL_CLIENT126_REQ = 254 +TCC_PERF_SEL_CLIENT127_REQ = 255 +TCC_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TCA_PERF_SEL' +TCA_PERF_SEL__enumvalues = { + 0: 'TCA_PERF_SEL_NONE', + 1: 'TCA_PERF_SEL_CYCLE', + 2: 'TCA_PERF_SEL_BUSY', + 3: 'TCA_PERF_SEL_FORCED_HOLE_TCC0', + 4: 'TCA_PERF_SEL_FORCED_HOLE_TCC1', + 5: 'TCA_PERF_SEL_FORCED_HOLE_TCC2', + 6: 'TCA_PERF_SEL_FORCED_HOLE_TCC3', + 7: 'TCA_PERF_SEL_FORCED_HOLE_TCC4', + 8: 'TCA_PERF_SEL_FORCED_HOLE_TCC5', + 9: 'TCA_PERF_SEL_FORCED_HOLE_TCC6', + 10: 'TCA_PERF_SEL_FORCED_HOLE_TCC7', + 11: 'TCA_PERF_SEL_REQ_TCC0', + 12: 'TCA_PERF_SEL_REQ_TCC1', + 13: 'TCA_PERF_SEL_REQ_TCC2', + 14: 'TCA_PERF_SEL_REQ_TCC3', + 15: 'TCA_PERF_SEL_REQ_TCC4', + 16: 'TCA_PERF_SEL_REQ_TCC5', + 17: 'TCA_PERF_SEL_REQ_TCC6', + 18: 'TCA_PERF_SEL_REQ_TCC7', + 19: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0', + 20: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1', + 21: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2', + 22: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3', + 23: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4', + 24: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5', + 25: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6', + 26: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7', + 27: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC0', + 28: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC1', + 29: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC2', + 30: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC3', + 31: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC4', + 32: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC5', + 33: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC6', + 34: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC7', +} +TCA_PERF_SEL_NONE = 0 +TCA_PERF_SEL_CYCLE = 1 +TCA_PERF_SEL_BUSY = 2 +TCA_PERF_SEL_FORCED_HOLE_TCC0 = 3 +TCA_PERF_SEL_FORCED_HOLE_TCC1 = 4 +TCA_PERF_SEL_FORCED_HOLE_TCC2 = 5 +TCA_PERF_SEL_FORCED_HOLE_TCC3 = 6 +TCA_PERF_SEL_FORCED_HOLE_TCC4 = 7 +TCA_PERF_SEL_FORCED_HOLE_TCC5 = 8 +TCA_PERF_SEL_FORCED_HOLE_TCC6 = 9 +TCA_PERF_SEL_FORCED_HOLE_TCC7 = 10 +TCA_PERF_SEL_REQ_TCC0 = 11 +TCA_PERF_SEL_REQ_TCC1 = 12 +TCA_PERF_SEL_REQ_TCC2 = 13 +TCA_PERF_SEL_REQ_TCC3 = 14 +TCA_PERF_SEL_REQ_TCC4 = 15 +TCA_PERF_SEL_REQ_TCC5 = 16 +TCA_PERF_SEL_REQ_TCC6 = 17 +TCA_PERF_SEL_REQ_TCC7 = 18 +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 19 +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 20 +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 21 +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 22 +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 23 +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 24 +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 25 +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 26 +TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 27 +TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 28 +TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 29 +TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 30 +TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 31 +TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 32 +TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 33 +TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 34 +TCA_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_PERF_SEL' +GRBM_PERF_SEL__enumvalues = { + 0: 'GRBM_PERF_SEL_COUNT', + 1: 'GRBM_PERF_SEL_USER_DEFINED', + 2: 'GRBM_PERF_SEL_GUI_ACTIVE', + 3: 'GRBM_PERF_SEL_CP_BUSY', + 4: 'GRBM_PERF_SEL_CP_COHER_BUSY', + 5: 'GRBM_PERF_SEL_CP_DMA_BUSY', + 6: 'GRBM_PERF_SEL_CB_BUSY', + 7: 'GRBM_PERF_SEL_DB_BUSY', + 8: 'GRBM_PERF_SEL_PA_BUSY', + 9: 'GRBM_PERF_SEL_SC_BUSY', + 10: 'GRBM_PERF_SEL_RESERVED_6', + 11: 'GRBM_PERF_SEL_SPI_BUSY', + 12: 'GRBM_PERF_SEL_SX_BUSY', + 13: 'GRBM_PERF_SEL_TA_BUSY', + 14: 'GRBM_PERF_SEL_CB_CLEAN', + 15: 'GRBM_PERF_SEL_DB_CLEAN', + 16: 'GRBM_PERF_SEL_RESERVED_5', + 17: 'GRBM_PERF_SEL_VGT_BUSY', + 18: 'GRBM_PERF_SEL_RESERVED_4', + 19: 'GRBM_PERF_SEL_RESERVED_3', + 20: 'GRBM_PERF_SEL_RESERVED_2', + 21: 'GRBM_PERF_SEL_RESERVED_1', + 22: 'GRBM_PERF_SEL_RESERVED_0', + 23: 'GRBM_PERF_SEL_IA_BUSY', + 24: 'GRBM_PERF_SEL_IA_NO_DMA_BUSY', + 25: 'GRBM_PERF_SEL_GDS_BUSY', + 26: 'GRBM_PERF_SEL_BCI_BUSY', + 27: 'GRBM_PERF_SEL_RLC_BUSY', + 28: 'GRBM_PERF_SEL_TC_BUSY', + 29: 'GRBM_PERF_SEL_CPG_BUSY', + 30: 'GRBM_PERF_SEL_CPC_BUSY', + 31: 'GRBM_PERF_SEL_CPF_BUSY', + 32: 'GRBM_PERF_SEL_WD_BUSY', + 33: 'GRBM_PERF_SEL_WD_NO_DMA_BUSY', + 34: 'GRBM_PERF_SEL_UTCL2_BUSY', + 35: 'GRBM_PERF_SEL_EA_BUSY', + 36: 'GRBM_PERF_SEL_RMI_BUSY', + 37: 'GRBM_PERF_SEL_CPAXI_BUSY', +} +GRBM_PERF_SEL_COUNT = 0 +GRBM_PERF_SEL_USER_DEFINED = 1 +GRBM_PERF_SEL_GUI_ACTIVE = 2 +GRBM_PERF_SEL_CP_BUSY = 3 +GRBM_PERF_SEL_CP_COHER_BUSY = 4 +GRBM_PERF_SEL_CP_DMA_BUSY = 5 +GRBM_PERF_SEL_CB_BUSY = 6 +GRBM_PERF_SEL_DB_BUSY = 7 +GRBM_PERF_SEL_PA_BUSY = 8 +GRBM_PERF_SEL_SC_BUSY = 9 +GRBM_PERF_SEL_RESERVED_6 = 10 +GRBM_PERF_SEL_SPI_BUSY = 11 +GRBM_PERF_SEL_SX_BUSY = 12 +GRBM_PERF_SEL_TA_BUSY = 13 +GRBM_PERF_SEL_CB_CLEAN = 14 +GRBM_PERF_SEL_DB_CLEAN = 15 +GRBM_PERF_SEL_RESERVED_5 = 16 +GRBM_PERF_SEL_VGT_BUSY = 17 +GRBM_PERF_SEL_RESERVED_4 = 18 +GRBM_PERF_SEL_RESERVED_3 = 19 +GRBM_PERF_SEL_RESERVED_2 = 20 +GRBM_PERF_SEL_RESERVED_1 = 21 +GRBM_PERF_SEL_RESERVED_0 = 22 +GRBM_PERF_SEL_IA_BUSY = 23 +GRBM_PERF_SEL_IA_NO_DMA_BUSY = 24 +GRBM_PERF_SEL_GDS_BUSY = 25 +GRBM_PERF_SEL_BCI_BUSY = 26 +GRBM_PERF_SEL_RLC_BUSY = 27 +GRBM_PERF_SEL_TC_BUSY = 28 +GRBM_PERF_SEL_CPG_BUSY = 29 +GRBM_PERF_SEL_CPC_BUSY = 30 +GRBM_PERF_SEL_CPF_BUSY = 31 +GRBM_PERF_SEL_WD_BUSY = 32 +GRBM_PERF_SEL_WD_NO_DMA_BUSY = 33 +GRBM_PERF_SEL_UTCL2_BUSY = 34 +GRBM_PERF_SEL_EA_BUSY = 35 +GRBM_PERF_SEL_RMI_BUSY = 36 +GRBM_PERF_SEL_CPAXI_BUSY = 37 +GRBM_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE0_PERF_SEL' +GRBM_SE0_PERF_SEL__enumvalues = { + 0: 'GRBM_SE0_PERF_SEL_COUNT', + 1: 'GRBM_SE0_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE0_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE0_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE0_PERF_SEL_SC_BUSY', + 5: 'GRBM_SE0_PERF_SEL_RESERVED_1', + 6: 'GRBM_SE0_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE0_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE0_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE0_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE0_PERF_SEL_DB_CLEAN', + 11: 'GRBM_SE0_PERF_SEL_RESERVED_0', + 12: 'GRBM_SE0_PERF_SEL_PA_BUSY', + 13: 'GRBM_SE0_PERF_SEL_VGT_BUSY', + 14: 'GRBM_SE0_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE0_PERF_SEL_RMI_BUSY', +} +GRBM_SE0_PERF_SEL_COUNT = 0 +GRBM_SE0_PERF_SEL_USER_DEFINED = 1 +GRBM_SE0_PERF_SEL_CB_BUSY = 2 +GRBM_SE0_PERF_SEL_DB_BUSY = 3 +GRBM_SE0_PERF_SEL_SC_BUSY = 4 +GRBM_SE0_PERF_SEL_RESERVED_1 = 5 +GRBM_SE0_PERF_SEL_SPI_BUSY = 6 +GRBM_SE0_PERF_SEL_SX_BUSY = 7 +GRBM_SE0_PERF_SEL_TA_BUSY = 8 +GRBM_SE0_PERF_SEL_CB_CLEAN = 9 +GRBM_SE0_PERF_SEL_DB_CLEAN = 10 +GRBM_SE0_PERF_SEL_RESERVED_0 = 11 +GRBM_SE0_PERF_SEL_PA_BUSY = 12 +GRBM_SE0_PERF_SEL_VGT_BUSY = 13 +GRBM_SE0_PERF_SEL_BCI_BUSY = 14 +GRBM_SE0_PERF_SEL_RMI_BUSY = 15 +GRBM_SE0_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE1_PERF_SEL' +GRBM_SE1_PERF_SEL__enumvalues = { + 0: 'GRBM_SE1_PERF_SEL_COUNT', + 1: 'GRBM_SE1_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE1_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE1_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE1_PERF_SEL_SC_BUSY', + 5: 'GRBM_SE1_PERF_SEL_RESERVED_1', + 6: 'GRBM_SE1_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE1_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE1_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE1_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE1_PERF_SEL_DB_CLEAN', + 11: 'GRBM_SE1_PERF_SEL_RESERVED_0', + 12: 'GRBM_SE1_PERF_SEL_PA_BUSY', + 13: 'GRBM_SE1_PERF_SEL_VGT_BUSY', + 14: 'GRBM_SE1_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE1_PERF_SEL_RMI_BUSY', +} +GRBM_SE1_PERF_SEL_COUNT = 0 +GRBM_SE1_PERF_SEL_USER_DEFINED = 1 +GRBM_SE1_PERF_SEL_CB_BUSY = 2 +GRBM_SE1_PERF_SEL_DB_BUSY = 3 +GRBM_SE1_PERF_SEL_SC_BUSY = 4 +GRBM_SE1_PERF_SEL_RESERVED_1 = 5 +GRBM_SE1_PERF_SEL_SPI_BUSY = 6 +GRBM_SE1_PERF_SEL_SX_BUSY = 7 +GRBM_SE1_PERF_SEL_TA_BUSY = 8 +GRBM_SE1_PERF_SEL_CB_CLEAN = 9 +GRBM_SE1_PERF_SEL_DB_CLEAN = 10 +GRBM_SE1_PERF_SEL_RESERVED_0 = 11 +GRBM_SE1_PERF_SEL_PA_BUSY = 12 +GRBM_SE1_PERF_SEL_VGT_BUSY = 13 +GRBM_SE1_PERF_SEL_BCI_BUSY = 14 +GRBM_SE1_PERF_SEL_RMI_BUSY = 15 +GRBM_SE1_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE2_PERF_SEL' +GRBM_SE2_PERF_SEL__enumvalues = { + 0: 'GRBM_SE2_PERF_SEL_COUNT', + 1: 'GRBM_SE2_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE2_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE2_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE2_PERF_SEL_SC_BUSY', + 5: 'GRBM_SE2_PERF_SEL_RESERVED_1', + 6: 'GRBM_SE2_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE2_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE2_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE2_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE2_PERF_SEL_DB_CLEAN', + 11: 'GRBM_SE2_PERF_SEL_RESERVED_0', + 12: 'GRBM_SE2_PERF_SEL_PA_BUSY', + 13: 'GRBM_SE2_PERF_SEL_VGT_BUSY', + 14: 'GRBM_SE2_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE2_PERF_SEL_RMI_BUSY', +} +GRBM_SE2_PERF_SEL_COUNT = 0 +GRBM_SE2_PERF_SEL_USER_DEFINED = 1 +GRBM_SE2_PERF_SEL_CB_BUSY = 2 +GRBM_SE2_PERF_SEL_DB_BUSY = 3 +GRBM_SE2_PERF_SEL_SC_BUSY = 4 +GRBM_SE2_PERF_SEL_RESERVED_1 = 5 +GRBM_SE2_PERF_SEL_SPI_BUSY = 6 +GRBM_SE2_PERF_SEL_SX_BUSY = 7 +GRBM_SE2_PERF_SEL_TA_BUSY = 8 +GRBM_SE2_PERF_SEL_CB_CLEAN = 9 +GRBM_SE2_PERF_SEL_DB_CLEAN = 10 +GRBM_SE2_PERF_SEL_RESERVED_0 = 11 +GRBM_SE2_PERF_SEL_PA_BUSY = 12 +GRBM_SE2_PERF_SEL_VGT_BUSY = 13 +GRBM_SE2_PERF_SEL_BCI_BUSY = 14 +GRBM_SE2_PERF_SEL_RMI_BUSY = 15 +GRBM_SE2_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE3_PERF_SEL' +GRBM_SE3_PERF_SEL__enumvalues = { + 0: 'GRBM_SE3_PERF_SEL_COUNT', + 1: 'GRBM_SE3_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE3_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE3_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE3_PERF_SEL_SC_BUSY', + 5: 'GRBM_SE3_PERF_SEL_RESERVED_1', + 6: 'GRBM_SE3_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE3_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE3_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE3_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE3_PERF_SEL_DB_CLEAN', + 11: 'GRBM_SE3_PERF_SEL_RESERVED_0', + 12: 'GRBM_SE3_PERF_SEL_PA_BUSY', + 13: 'GRBM_SE3_PERF_SEL_VGT_BUSY', + 14: 'GRBM_SE3_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE3_PERF_SEL_RMI_BUSY', +} +GRBM_SE3_PERF_SEL_COUNT = 0 +GRBM_SE3_PERF_SEL_USER_DEFINED = 1 +GRBM_SE3_PERF_SEL_CB_BUSY = 2 +GRBM_SE3_PERF_SEL_DB_BUSY = 3 +GRBM_SE3_PERF_SEL_SC_BUSY = 4 +GRBM_SE3_PERF_SEL_RESERVED_1 = 5 +GRBM_SE3_PERF_SEL_SPI_BUSY = 6 +GRBM_SE3_PERF_SEL_SX_BUSY = 7 +GRBM_SE3_PERF_SEL_TA_BUSY = 8 +GRBM_SE3_PERF_SEL_CB_CLEAN = 9 +GRBM_SE3_PERF_SEL_DB_CLEAN = 10 +GRBM_SE3_PERF_SEL_RESERVED_0 = 11 +GRBM_SE3_PERF_SEL_PA_BUSY = 12 +GRBM_SE3_PERF_SEL_VGT_BUSY = 13 +GRBM_SE3_PERF_SEL_BCI_BUSY = 14 +GRBM_SE3_PERF_SEL_RMI_BUSY = 15 +GRBM_SE3_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CP_RING_ID' +CP_RING_ID__enumvalues = { + 0: 'RINGID0', + 1: 'RINGID1', + 2: 'RINGID2', + 3: 'RINGID3', +} +RINGID0 = 0 +RINGID1 = 1 +RINGID2 = 2 +RINGID3 = 3 +CP_RING_ID = ctypes.c_uint32 # enum + +# values for enumeration 'CP_PIPE_ID' +CP_PIPE_ID__enumvalues = { + 0: 'PIPE_ID0', + 1: 'PIPE_ID1', + 2: 'PIPE_ID2', + 3: 'PIPE_ID3', +} +PIPE_ID0 = 0 +PIPE_ID1 = 1 +PIPE_ID2 = 2 +PIPE_ID3 = 3 +CP_PIPE_ID = ctypes.c_uint32 # enum + +# values for enumeration 'CP_ME_ID' +CP_ME_ID__enumvalues = { + 0: 'ME_ID0', + 1: 'ME_ID1', + 2: 'ME_ID2', + 3: 'ME_ID3', +} +ME_ID0 = 0 +ME_ID1 = 1 +ME_ID2 = 2 +ME_ID3 = 3 +CP_ME_ID = ctypes.c_uint32 # enum + +# values for enumeration 'SPM_PERFMON_STATE' +SPM_PERFMON_STATE__enumvalues = { + 0: 'STRM_PERFMON_STATE_DISABLE_AND_RESET', + 1: 'STRM_PERFMON_STATE_START_COUNTING', + 2: 'STRM_PERFMON_STATE_STOP_COUNTING', + 3: 'STRM_PERFMON_STATE_RESERVED_3', + 4: 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 5: 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', +} +STRM_PERFMON_STATE_DISABLE_AND_RESET = 0 +STRM_PERFMON_STATE_START_COUNTING = 1 +STRM_PERFMON_STATE_STOP_COUNTING = 2 +STRM_PERFMON_STATE_RESERVED_3 = 3 +STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 +STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 +SPM_PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_PERFMON_STATE' +CP_PERFMON_STATE__enumvalues = { + 0: 'CP_PERFMON_STATE_DISABLE_AND_RESET', + 1: 'CP_PERFMON_STATE_START_COUNTING', + 2: 'CP_PERFMON_STATE_STOP_COUNTING', + 3: 'CP_PERFMON_STATE_RESERVED_3', + 4: 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 5: 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', +} +CP_PERFMON_STATE_DISABLE_AND_RESET = 0 +CP_PERFMON_STATE_START_COUNTING = 1 +CP_PERFMON_STATE_STOP_COUNTING = 2 +CP_PERFMON_STATE_RESERVED_3 = 3 +CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 +CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 +CP_PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_PERFMON_ENABLE_MODE' +CP_PERFMON_ENABLE_MODE__enumvalues = { + 0: 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', + 1: 'CP_PERFMON_ENABLE_MODE_RESERVED_1', + 2: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', + 3: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', +} +CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0 +CP_PERFMON_ENABLE_MODE_RESERVED_1 = 1 +CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 2 +CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 3 +CP_PERFMON_ENABLE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CPG_PERFCOUNT_SEL' +CPG_PERFCOUNT_SEL__enumvalues = { + 0: 'CPG_PERF_SEL_ALWAYS_COUNT', + 1: 'CPG_PERF_SEL_RBIU_FIFO_FULL', + 2: 'CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR', + 3: 'CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL', + 4: 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', + 5: 'CPG_PERF_SEL_ME_PARSER_BUSY', + 6: 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', + 7: 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', + 8: 'CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', + 9: 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', + 10: 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', + 11: 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', + 12: 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', + 13: 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', + 14: 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', + 15: 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', + 16: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', + 17: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', + 18: 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', + 19: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', + 20: 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', + 21: 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', + 22: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', + 23: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', + 24: 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', + 25: 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', + 26: 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', + 27: 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', + 28: 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', + 29: 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', + 30: 'CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS', + 31: 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', + 32: 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', + 33: 'CPG_PERF_SEL_REGISTER_CLK_VALID', + 34: 'CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT', + 35: 'CPG_PERF_SEL_MIU_READ_REQUEST_SENT', + 36: 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', + 37: 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', + 38: 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', + 39: 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', + 40: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU', + 41: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', + 42: 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', + 43: 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', + 44: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 45: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', + 46: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 47: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 48: 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', +} +CPG_PERF_SEL_ALWAYS_COUNT = 0 +CPG_PERF_SEL_RBIU_FIFO_FULL = 1 +CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 2 +CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 3 +CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 4 +CPG_PERF_SEL_ME_PARSER_BUSY = 5 +CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 6 +CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 7 +CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 8 +CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 9 +CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 10 +CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 11 +CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 12 +CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 13 +CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 14 +CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 15 +CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 16 +CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 17 +CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 18 +CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 19 +CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 20 +CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 21 +CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 22 +CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 23 +CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 24 +CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 25 +CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 26 +CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 27 +CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 28 +CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 29 +CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 30 +CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 31 +CPG_PERF_SEL_DYNAMIC_CLK_VALID = 32 +CPG_PERF_SEL_REGISTER_CLK_VALID = 33 +CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 34 +CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 35 +CPG_PERF_SEL_CE_STALL_RAM_DUMP = 36 +CPG_PERF_SEL_CE_STALL_RAM_WRITE = 37 +CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 38 +CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 39 +CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 40 +CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 41 +CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 42 +CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 43 +CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 44 +CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 45 +CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 46 +CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 47 +CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 48 +CPG_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPF_PERFCOUNT_SEL' +CPF_PERFCOUNT_SEL__enumvalues = { + 0: 'CPF_PERF_SEL_ALWAYS_COUNT', + 1: 'CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE', + 2: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', + 3: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', + 4: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', + 5: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', + 6: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', + 7: 'CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE', + 8: 'CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS', + 9: 'CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR', + 10: 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', + 11: 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', + 12: 'CPF_PERF_SEL_GRBM_DWORDS_SENT', + 13: 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', + 14: 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', + 15: 'CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND', + 16: 'CPF_PERF_SEL_MIU_READ_REQUEST_SEND', + 17: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 18: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 19: 'CPF_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 20: 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', +} +CPF_PERF_SEL_ALWAYS_COUNT = 0 +CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 1 +CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 2 +CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 3 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 4 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 5 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 6 +CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 7 +CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 8 +CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 9 +CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 10 +CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 11 +CPF_PERF_SEL_GRBM_DWORDS_SENT = 12 +CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 13 +CPF_PERF_SEL_REGISTER_CLOCK_VALID = 14 +CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 15 +CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 16 +CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 17 +CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 18 +CPF_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 19 +CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 20 +CPF_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPC_PERFCOUNT_SEL' +CPC_PERFCOUNT_SEL__enumvalues = { + 0: 'CPC_PERF_SEL_ALWAYS_COUNT', + 1: 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 2: 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', + 3: 'CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE', + 4: 'CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE', + 5: 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 6: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', + 7: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', + 8: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', + 9: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ', + 10: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE', + 11: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', + 12: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', + 13: 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', + 14: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', + 15: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', + 16: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', + 17: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ', + 18: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE', + 19: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', + 20: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', + 21: 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', + 22: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 23: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 24: 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', +} +CPC_PERF_SEL_ALWAYS_COUNT = 0 +CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 1 +CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 2 +CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 3 +CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 4 +CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 5 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 6 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 7 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 8 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 9 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 10 +CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 11 +CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 12 +CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 13 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 14 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 15 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 16 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 17 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 18 +CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 19 +CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 20 +CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 21 +CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 22 +CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 23 +CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 24 +CPC_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CP_ALPHA_TAG_RAM_SEL' +CP_ALPHA_TAG_RAM_SEL__enumvalues = { + 0: 'CPG_TAG_RAM', + 1: 'CPC_TAG_RAM', + 2: 'CPF_TAG_RAM', + 3: 'RSV_TAG_RAM', +} +CPG_TAG_RAM = 0 +CPC_TAG_RAM = 1 +CPF_TAG_RAM = 2 +RSV_TAG_RAM = 3 +CP_ALPHA_TAG_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SX_BLEND_OPT' +SX_BLEND_OPT__enumvalues = { + 0: 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', + 1: 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', + 2: 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', + 3: 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', + 4: 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', + 5: 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', + 6: 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', + 7: 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', +} +BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0 +BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 1 +BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 2 +BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 3 +BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 4 +BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 5 +BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 6 +BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 7 +SX_BLEND_OPT = ctypes.c_uint32 # enum + +# values for enumeration 'SX_OPT_COMB_FCN' +SX_OPT_COMB_FCN__enumvalues = { + 0: 'OPT_COMB_NONE', + 1: 'OPT_COMB_ADD', + 2: 'OPT_COMB_SUBTRACT', + 3: 'OPT_COMB_MIN', + 4: 'OPT_COMB_MAX', + 5: 'OPT_COMB_REVSUBTRACT', + 6: 'OPT_COMB_BLEND_DISABLED', + 7: 'OPT_COMB_SAFE_ADD', +} +OPT_COMB_NONE = 0 +OPT_COMB_ADD = 1 +OPT_COMB_SUBTRACT = 2 +OPT_COMB_MIN = 3 +OPT_COMB_MAX = 4 +OPT_COMB_REVSUBTRACT = 5 +OPT_COMB_BLEND_DISABLED = 6 +OPT_COMB_SAFE_ADD = 7 +SX_OPT_COMB_FCN = ctypes.c_uint32 # enum + +# values for enumeration 'SX_DOWNCONVERT_FORMAT' +SX_DOWNCONVERT_FORMAT__enumvalues = { + 0: 'SX_RT_EXPORT_NO_CONVERSION', + 1: 'SX_RT_EXPORT_32_R', + 2: 'SX_RT_EXPORT_32_A', + 3: 'SX_RT_EXPORT_10_11_11', + 4: 'SX_RT_EXPORT_2_10_10_10', + 5: 'SX_RT_EXPORT_8_8_8_8', + 6: 'SX_RT_EXPORT_5_6_5', + 7: 'SX_RT_EXPORT_1_5_5_5', + 8: 'SX_RT_EXPORT_4_4_4_4', + 9: 'SX_RT_EXPORT_16_16_GR', + 10: 'SX_RT_EXPORT_16_16_AR', +} +SX_RT_EXPORT_NO_CONVERSION = 0 +SX_RT_EXPORT_32_R = 1 +SX_RT_EXPORT_32_A = 2 +SX_RT_EXPORT_10_11_11 = 3 +SX_RT_EXPORT_2_10_10_10 = 4 +SX_RT_EXPORT_8_8_8_8 = 5 +SX_RT_EXPORT_5_6_5 = 6 +SX_RT_EXPORT_1_5_5_5 = 7 +SX_RT_EXPORT_4_4_4_4 = 8 +SX_RT_EXPORT_16_16_GR = 9 +SX_RT_EXPORT_16_16_AR = 10 +SX_DOWNCONVERT_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'SX_PERFCOUNTER_VALS' +SX_PERFCOUNTER_VALS__enumvalues = { + 0: 'SX_PERF_SEL_PA_IDLE_CYCLES', + 1: 'SX_PERF_SEL_PA_REQ', + 2: 'SX_PERF_SEL_PA_POS', + 3: 'SX_PERF_SEL_CLOCK', + 4: 'SX_PERF_SEL_GATE_EN1', + 5: 'SX_PERF_SEL_GATE_EN2', + 6: 'SX_PERF_SEL_GATE_EN3', + 7: 'SX_PERF_SEL_GATE_EN4', + 8: 'SX_PERF_SEL_SH_POS_STARVE', + 9: 'SX_PERF_SEL_SH_COLOR_STARVE', + 10: 'SX_PERF_SEL_SH_POS_STALL', + 11: 'SX_PERF_SEL_SH_COLOR_STALL', + 12: 'SX_PERF_SEL_DB0_PIXELS', + 13: 'SX_PERF_SEL_DB0_HALF_QUADS', + 14: 'SX_PERF_SEL_DB0_PIXEL_STALL', + 15: 'SX_PERF_SEL_DB0_PIXEL_IDLE', + 16: 'SX_PERF_SEL_DB0_PRED_PIXELS', + 17: 'SX_PERF_SEL_DB1_PIXELS', + 18: 'SX_PERF_SEL_DB1_HALF_QUADS', + 19: 'SX_PERF_SEL_DB1_PIXEL_STALL', + 20: 'SX_PERF_SEL_DB1_PIXEL_IDLE', + 21: 'SX_PERF_SEL_DB1_PRED_PIXELS', + 22: 'SX_PERF_SEL_DB2_PIXELS', + 23: 'SX_PERF_SEL_DB2_HALF_QUADS', + 24: 'SX_PERF_SEL_DB2_PIXEL_STALL', + 25: 'SX_PERF_SEL_DB2_PIXEL_IDLE', + 26: 'SX_PERF_SEL_DB2_PRED_PIXELS', + 27: 'SX_PERF_SEL_DB3_PIXELS', + 28: 'SX_PERF_SEL_DB3_HALF_QUADS', + 29: 'SX_PERF_SEL_DB3_PIXEL_STALL', + 30: 'SX_PERF_SEL_DB3_PIXEL_IDLE', + 31: 'SX_PERF_SEL_DB3_PRED_PIXELS', + 32: 'SX_PERF_SEL_COL_BUSY', + 33: 'SX_PERF_SEL_POS_BUSY', + 34: 'SX_PERF_SEL_DB0_A2M_DISCARD_QUADS', + 35: 'SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS', + 36: 'SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST', + 37: 'SX_PERF_SEL_DB0_MRT0_DISCARD_SRC', + 38: 'SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS', + 39: 'SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS', + 40: 'SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS', + 41: 'SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST', + 42: 'SX_PERF_SEL_DB0_MRT1_DISCARD_SRC', + 43: 'SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS', + 44: 'SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS', + 45: 'SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS', + 46: 'SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST', + 47: 'SX_PERF_SEL_DB0_MRT2_DISCARD_SRC', + 48: 'SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS', + 49: 'SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS', + 50: 'SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS', + 51: 'SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST', + 52: 'SX_PERF_SEL_DB0_MRT3_DISCARD_SRC', + 53: 'SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS', + 54: 'SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS', + 55: 'SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS', + 56: 'SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST', + 57: 'SX_PERF_SEL_DB0_MRT4_DISCARD_SRC', + 58: 'SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS', + 59: 'SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS', + 60: 'SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS', + 61: 'SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST', + 62: 'SX_PERF_SEL_DB0_MRT5_DISCARD_SRC', + 63: 'SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS', + 64: 'SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS', + 65: 'SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS', + 66: 'SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST', + 67: 'SX_PERF_SEL_DB0_MRT6_DISCARD_SRC', + 68: 'SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS', + 69: 'SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS', + 70: 'SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS', + 71: 'SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST', + 72: 'SX_PERF_SEL_DB0_MRT7_DISCARD_SRC', + 73: 'SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS', + 74: 'SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS', + 75: 'SX_PERF_SEL_DB1_A2M_DISCARD_QUADS', + 76: 'SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS', + 77: 'SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST', + 78: 'SX_PERF_SEL_DB1_MRT0_DISCARD_SRC', + 79: 'SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS', + 80: 'SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS', + 81: 'SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS', + 82: 'SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST', + 83: 'SX_PERF_SEL_DB1_MRT1_DISCARD_SRC', + 84: 'SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS', + 85: 'SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS', + 86: 'SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS', + 87: 'SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST', + 88: 'SX_PERF_SEL_DB1_MRT2_DISCARD_SRC', + 89: 'SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS', + 90: 'SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS', + 91: 'SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS', + 92: 'SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST', + 93: 'SX_PERF_SEL_DB1_MRT3_DISCARD_SRC', + 94: 'SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS', + 95: 'SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS', + 96: 'SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS', + 97: 'SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST', + 98: 'SX_PERF_SEL_DB1_MRT4_DISCARD_SRC', + 99: 'SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS', + 100: 'SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS', + 101: 'SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS', + 102: 'SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST', + 103: 'SX_PERF_SEL_DB1_MRT5_DISCARD_SRC', + 104: 'SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS', + 105: 'SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS', + 106: 'SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS', + 107: 'SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST', + 108: 'SX_PERF_SEL_DB1_MRT6_DISCARD_SRC', + 109: 'SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS', + 110: 'SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS', + 111: 'SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS', + 112: 'SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST', + 113: 'SX_PERF_SEL_DB1_MRT7_DISCARD_SRC', + 114: 'SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS', + 115: 'SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS', + 116: 'SX_PERF_SEL_DB2_A2M_DISCARD_QUADS', + 117: 'SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS', + 118: 'SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST', + 119: 'SX_PERF_SEL_DB2_MRT0_DISCARD_SRC', + 120: 'SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS', + 121: 'SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS', + 122: 'SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS', + 123: 'SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST', + 124: 'SX_PERF_SEL_DB2_MRT1_DISCARD_SRC', + 125: 'SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS', + 126: 'SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS', + 127: 'SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS', + 128: 'SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST', + 129: 'SX_PERF_SEL_DB2_MRT2_DISCARD_SRC', + 130: 'SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS', + 131: 'SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS', + 132: 'SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS', + 133: 'SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST', + 134: 'SX_PERF_SEL_DB2_MRT3_DISCARD_SRC', + 135: 'SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS', + 136: 'SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS', + 137: 'SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS', + 138: 'SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST', + 139: 'SX_PERF_SEL_DB2_MRT4_DISCARD_SRC', + 140: 'SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS', + 141: 'SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS', + 142: 'SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS', + 143: 'SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST', + 144: 'SX_PERF_SEL_DB2_MRT5_DISCARD_SRC', + 145: 'SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS', + 146: 'SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS', + 147: 'SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS', + 148: 'SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST', + 149: 'SX_PERF_SEL_DB2_MRT6_DISCARD_SRC', + 150: 'SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS', + 151: 'SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS', + 152: 'SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS', + 153: 'SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST', + 154: 'SX_PERF_SEL_DB2_MRT7_DISCARD_SRC', + 155: 'SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS', + 156: 'SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS', + 157: 'SX_PERF_SEL_DB3_A2M_DISCARD_QUADS', + 158: 'SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS', + 159: 'SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST', + 160: 'SX_PERF_SEL_DB3_MRT0_DISCARD_SRC', + 161: 'SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS', + 162: 'SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS', + 163: 'SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS', + 164: 'SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST', + 165: 'SX_PERF_SEL_DB3_MRT1_DISCARD_SRC', + 166: 'SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS', + 167: 'SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS', + 168: 'SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS', + 169: 'SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST', + 170: 'SX_PERF_SEL_DB3_MRT2_DISCARD_SRC', + 171: 'SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS', + 172: 'SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS', + 173: 'SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS', + 174: 'SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST', + 175: 'SX_PERF_SEL_DB3_MRT3_DISCARD_SRC', + 176: 'SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS', + 177: 'SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS', + 178: 'SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS', + 179: 'SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST', + 180: 'SX_PERF_SEL_DB3_MRT4_DISCARD_SRC', + 181: 'SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS', + 182: 'SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS', + 183: 'SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS', + 184: 'SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST', + 185: 'SX_PERF_SEL_DB3_MRT5_DISCARD_SRC', + 186: 'SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS', + 187: 'SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS', + 188: 'SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS', + 189: 'SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST', + 190: 'SX_PERF_SEL_DB3_MRT6_DISCARD_SRC', + 191: 'SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS', + 192: 'SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS', + 193: 'SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS', + 194: 'SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST', + 195: 'SX_PERF_SEL_DB3_MRT7_DISCARD_SRC', + 196: 'SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS', + 197: 'SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS', +} +SX_PERF_SEL_PA_IDLE_CYCLES = 0 +SX_PERF_SEL_PA_REQ = 1 +SX_PERF_SEL_PA_POS = 2 +SX_PERF_SEL_CLOCK = 3 +SX_PERF_SEL_GATE_EN1 = 4 +SX_PERF_SEL_GATE_EN2 = 5 +SX_PERF_SEL_GATE_EN3 = 6 +SX_PERF_SEL_GATE_EN4 = 7 +SX_PERF_SEL_SH_POS_STARVE = 8 +SX_PERF_SEL_SH_COLOR_STARVE = 9 +SX_PERF_SEL_SH_POS_STALL = 10 +SX_PERF_SEL_SH_COLOR_STALL = 11 +SX_PERF_SEL_DB0_PIXELS = 12 +SX_PERF_SEL_DB0_HALF_QUADS = 13 +SX_PERF_SEL_DB0_PIXEL_STALL = 14 +SX_PERF_SEL_DB0_PIXEL_IDLE = 15 +SX_PERF_SEL_DB0_PRED_PIXELS = 16 +SX_PERF_SEL_DB1_PIXELS = 17 +SX_PERF_SEL_DB1_HALF_QUADS = 18 +SX_PERF_SEL_DB1_PIXEL_STALL = 19 +SX_PERF_SEL_DB1_PIXEL_IDLE = 20 +SX_PERF_SEL_DB1_PRED_PIXELS = 21 +SX_PERF_SEL_DB2_PIXELS = 22 +SX_PERF_SEL_DB2_HALF_QUADS = 23 +SX_PERF_SEL_DB2_PIXEL_STALL = 24 +SX_PERF_SEL_DB2_PIXEL_IDLE = 25 +SX_PERF_SEL_DB2_PRED_PIXELS = 26 +SX_PERF_SEL_DB3_PIXELS = 27 +SX_PERF_SEL_DB3_HALF_QUADS = 28 +SX_PERF_SEL_DB3_PIXEL_STALL = 29 +SX_PERF_SEL_DB3_PIXEL_IDLE = 30 +SX_PERF_SEL_DB3_PRED_PIXELS = 31 +SX_PERF_SEL_COL_BUSY = 32 +SX_PERF_SEL_POS_BUSY = 33 +SX_PERF_SEL_DB0_A2M_DISCARD_QUADS = 34 +SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS = 35 +SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST = 36 +SX_PERF_SEL_DB0_MRT0_DISCARD_SRC = 37 +SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS = 38 +SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS = 39 +SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS = 40 +SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST = 41 +SX_PERF_SEL_DB0_MRT1_DISCARD_SRC = 42 +SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS = 43 +SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS = 44 +SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS = 45 +SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST = 46 +SX_PERF_SEL_DB0_MRT2_DISCARD_SRC = 47 +SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS = 48 +SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS = 49 +SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS = 50 +SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST = 51 +SX_PERF_SEL_DB0_MRT3_DISCARD_SRC = 52 +SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS = 53 +SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS = 54 +SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS = 55 +SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST = 56 +SX_PERF_SEL_DB0_MRT4_DISCARD_SRC = 57 +SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS = 58 +SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS = 59 +SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS = 60 +SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST = 61 +SX_PERF_SEL_DB0_MRT5_DISCARD_SRC = 62 +SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS = 63 +SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS = 64 +SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS = 65 +SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST = 66 +SX_PERF_SEL_DB0_MRT6_DISCARD_SRC = 67 +SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS = 68 +SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS = 69 +SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS = 70 +SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST = 71 +SX_PERF_SEL_DB0_MRT7_DISCARD_SRC = 72 +SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS = 73 +SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS = 74 +SX_PERF_SEL_DB1_A2M_DISCARD_QUADS = 75 +SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS = 76 +SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST = 77 +SX_PERF_SEL_DB1_MRT0_DISCARD_SRC = 78 +SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS = 79 +SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS = 80 +SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS = 81 +SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST = 82 +SX_PERF_SEL_DB1_MRT1_DISCARD_SRC = 83 +SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS = 84 +SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS = 85 +SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS = 86 +SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST = 87 +SX_PERF_SEL_DB1_MRT2_DISCARD_SRC = 88 +SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS = 89 +SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS = 90 +SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS = 91 +SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST = 92 +SX_PERF_SEL_DB1_MRT3_DISCARD_SRC = 93 +SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS = 94 +SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS = 95 +SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS = 96 +SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST = 97 +SX_PERF_SEL_DB1_MRT4_DISCARD_SRC = 98 +SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS = 99 +SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS = 100 +SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS = 101 +SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST = 102 +SX_PERF_SEL_DB1_MRT5_DISCARD_SRC = 103 +SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS = 104 +SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS = 105 +SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS = 106 +SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST = 107 +SX_PERF_SEL_DB1_MRT6_DISCARD_SRC = 108 +SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS = 109 +SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS = 110 +SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS = 111 +SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST = 112 +SX_PERF_SEL_DB1_MRT7_DISCARD_SRC = 113 +SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS = 114 +SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS = 115 +SX_PERF_SEL_DB2_A2M_DISCARD_QUADS = 116 +SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS = 117 +SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST = 118 +SX_PERF_SEL_DB2_MRT0_DISCARD_SRC = 119 +SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS = 120 +SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS = 121 +SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS = 122 +SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST = 123 +SX_PERF_SEL_DB2_MRT1_DISCARD_SRC = 124 +SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS = 125 +SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS = 126 +SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS = 127 +SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST = 128 +SX_PERF_SEL_DB2_MRT2_DISCARD_SRC = 129 +SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS = 130 +SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS = 131 +SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS = 132 +SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST = 133 +SX_PERF_SEL_DB2_MRT3_DISCARD_SRC = 134 +SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS = 135 +SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS = 136 +SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS = 137 +SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST = 138 +SX_PERF_SEL_DB2_MRT4_DISCARD_SRC = 139 +SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS = 140 +SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS = 141 +SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS = 142 +SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST = 143 +SX_PERF_SEL_DB2_MRT5_DISCARD_SRC = 144 +SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS = 145 +SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS = 146 +SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS = 147 +SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST = 148 +SX_PERF_SEL_DB2_MRT6_DISCARD_SRC = 149 +SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS = 150 +SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS = 151 +SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS = 152 +SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST = 153 +SX_PERF_SEL_DB2_MRT7_DISCARD_SRC = 154 +SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS = 155 +SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS = 156 +SX_PERF_SEL_DB3_A2M_DISCARD_QUADS = 157 +SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS = 158 +SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST = 159 +SX_PERF_SEL_DB3_MRT0_DISCARD_SRC = 160 +SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS = 161 +SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS = 162 +SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS = 163 +SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST = 164 +SX_PERF_SEL_DB3_MRT1_DISCARD_SRC = 165 +SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS = 166 +SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS = 167 +SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS = 168 +SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST = 169 +SX_PERF_SEL_DB3_MRT2_DISCARD_SRC = 170 +SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS = 171 +SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS = 172 +SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS = 173 +SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST = 174 +SX_PERF_SEL_DB3_MRT3_DISCARD_SRC = 175 +SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS = 176 +SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS = 177 +SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS = 178 +SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST = 179 +SX_PERF_SEL_DB3_MRT4_DISCARD_SRC = 180 +SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS = 181 +SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS = 182 +SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS = 183 +SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST = 184 +SX_PERF_SEL_DB3_MRT5_DISCARD_SRC = 185 +SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS = 186 +SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS = 187 +SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS = 188 +SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST = 189 +SX_PERF_SEL_DB3_MRT6_DISCARD_SRC = 190 +SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS = 191 +SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS = 192 +SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS = 193 +SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST = 194 +SX_PERF_SEL_DB3_MRT7_DISCARD_SRC = 195 +SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS = 196 +SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS = 197 +SX_PERFCOUNTER_VALS = ctypes.c_uint32 # enum + +# values for enumeration 'ForceControl' +ForceControl__enumvalues = { + 0: 'FORCE_OFF', + 1: 'FORCE_ENABLE', + 2: 'FORCE_DISABLE', + 3: 'FORCE_RESERVED', +} +FORCE_OFF = 0 +FORCE_ENABLE = 1 +FORCE_DISABLE = 2 +FORCE_RESERVED = 3 +ForceControl = ctypes.c_uint32 # enum + +# values for enumeration 'ZSamplePosition' +ZSamplePosition__enumvalues = { + 0: 'Z_SAMPLE_CENTER', + 1: 'Z_SAMPLE_CENTROID', +} +Z_SAMPLE_CENTER = 0 +Z_SAMPLE_CENTROID = 1 +ZSamplePosition = ctypes.c_uint32 # enum + +# values for enumeration 'ZOrder' +ZOrder__enumvalues = { + 0: 'LATE_Z', + 1: 'EARLY_Z_THEN_LATE_Z', + 2: 'RE_Z', + 3: 'EARLY_Z_THEN_RE_Z', +} +LATE_Z = 0 +EARLY_Z_THEN_LATE_Z = 1 +RE_Z = 2 +EARLY_Z_THEN_RE_Z = 3 +ZOrder = ctypes.c_uint32 # enum + +# values for enumeration 'ZpassControl' +ZpassControl__enumvalues = { + 0: 'ZPASS_DISABLE', + 1: 'ZPASS_SAMPLES', + 2: 'ZPASS_PIXELS', +} +ZPASS_DISABLE = 0 +ZPASS_SAMPLES = 1 +ZPASS_PIXELS = 2 +ZpassControl = ctypes.c_uint32 # enum + +# values for enumeration 'ZModeForce' +ZModeForce__enumvalues = { + 0: 'NO_FORCE', + 1: 'FORCE_EARLY_Z', + 2: 'FORCE_LATE_Z', + 3: 'FORCE_RE_Z', +} +NO_FORCE = 0 +FORCE_EARLY_Z = 1 +FORCE_LATE_Z = 2 +FORCE_RE_Z = 3 +ZModeForce = ctypes.c_uint32 # enum + +# values for enumeration 'ZLimitSumm' +ZLimitSumm__enumvalues = { + 0: 'FORCE_SUMM_OFF', + 1: 'FORCE_SUMM_MINZ', + 2: 'FORCE_SUMM_MAXZ', + 3: 'FORCE_SUMM_BOTH', +} +FORCE_SUMM_OFF = 0 +FORCE_SUMM_MINZ = 1 +FORCE_SUMM_MAXZ = 2 +FORCE_SUMM_BOTH = 3 +ZLimitSumm = ctypes.c_uint32 # enum + +# values for enumeration 'CompareFrag' +CompareFrag__enumvalues = { + 0: 'FRAG_NEVER', + 1: 'FRAG_LESS', + 2: 'FRAG_EQUAL', + 3: 'FRAG_LEQUAL', + 4: 'FRAG_GREATER', + 5: 'FRAG_NOTEQUAL', + 6: 'FRAG_GEQUAL', + 7: 'FRAG_ALWAYS', +} +FRAG_NEVER = 0 +FRAG_LESS = 1 +FRAG_EQUAL = 2 +FRAG_LEQUAL = 3 +FRAG_GREATER = 4 +FRAG_NOTEQUAL = 5 +FRAG_GEQUAL = 6 +FRAG_ALWAYS = 7 +CompareFrag = ctypes.c_uint32 # enum + +# values for enumeration 'StencilOp' +StencilOp__enumvalues = { + 0: 'STENCIL_KEEP', + 1: 'STENCIL_ZERO', + 2: 'STENCIL_ONES', + 3: 'STENCIL_REPLACE_TEST', + 4: 'STENCIL_REPLACE_OP', + 5: 'STENCIL_ADD_CLAMP', + 6: 'STENCIL_SUB_CLAMP', + 7: 'STENCIL_INVERT', + 8: 'STENCIL_ADD_WRAP', + 9: 'STENCIL_SUB_WRAP', + 10: 'STENCIL_AND', + 11: 'STENCIL_OR', + 12: 'STENCIL_XOR', + 13: 'STENCIL_NAND', + 14: 'STENCIL_NOR', + 15: 'STENCIL_XNOR', +} +STENCIL_KEEP = 0 +STENCIL_ZERO = 1 +STENCIL_ONES = 2 +STENCIL_REPLACE_TEST = 3 +STENCIL_REPLACE_OP = 4 +STENCIL_ADD_CLAMP = 5 +STENCIL_SUB_CLAMP = 6 +STENCIL_INVERT = 7 +STENCIL_ADD_WRAP = 8 +STENCIL_SUB_WRAP = 9 +STENCIL_AND = 10 +STENCIL_OR = 11 +STENCIL_XOR = 12 +STENCIL_NAND = 13 +STENCIL_NOR = 14 +STENCIL_XNOR = 15 +StencilOp = ctypes.c_uint32 # enum + +# values for enumeration 'ConservativeZExport' +ConservativeZExport__enumvalues = { + 0: 'EXPORT_ANY_Z', + 1: 'EXPORT_LESS_THAN_Z', + 2: 'EXPORT_GREATER_THAN_Z', + 3: 'EXPORT_RESERVED', +} +EXPORT_ANY_Z = 0 +EXPORT_LESS_THAN_Z = 1 +EXPORT_GREATER_THAN_Z = 2 +EXPORT_RESERVED = 3 +ConservativeZExport = ctypes.c_uint32 # enum + +# values for enumeration 'DbPSLControl' +DbPSLControl__enumvalues = { + 0: 'PSLC_AUTO', + 1: 'PSLC_ON_HANG_ONLY', + 2: 'PSLC_ASAP', + 3: 'PSLC_COUNTDOWN', +} +PSLC_AUTO = 0 +PSLC_ON_HANG_ONLY = 1 +PSLC_ASAP = 2 +PSLC_COUNTDOWN = 3 +DbPSLControl = ctypes.c_uint32 # enum + +# values for enumeration 'DbPRTFaultBehavior' +DbPRTFaultBehavior__enumvalues = { + 0: 'FAULT_ZERO', + 1: 'FAULT_ONE', + 2: 'FAULT_FAIL', + 3: 'FAULT_PASS', +} +FAULT_ZERO = 0 +FAULT_ONE = 1 +FAULT_FAIL = 2 +FAULT_PASS = 3 +DbPRTFaultBehavior = ctypes.c_uint32 # enum + +# values for enumeration 'PerfCounter_Vals' +PerfCounter_Vals__enumvalues = { + 0: 'DB_PERF_SEL_SC_DB_tile_sends', + 1: 'DB_PERF_SEL_SC_DB_tile_busy', + 2: 'DB_PERF_SEL_SC_DB_tile_stalls', + 3: 'DB_PERF_SEL_SC_DB_tile_events', + 4: 'DB_PERF_SEL_SC_DB_tile_tiles', + 5: 'DB_PERF_SEL_SC_DB_tile_covered', + 6: 'DB_PERF_SEL_hiz_tc_read_starved', + 7: 'DB_PERF_SEL_hiz_tc_write_stall', + 8: 'DB_PERF_SEL_hiz_qtiles_culled', + 9: 'DB_PERF_SEL_his_qtiles_culled', + 10: 'DB_PERF_SEL_DB_SC_tile_sends', + 11: 'DB_PERF_SEL_DB_SC_tile_busy', + 12: 'DB_PERF_SEL_DB_SC_tile_stalls', + 13: 'DB_PERF_SEL_DB_SC_tile_df_stalls', + 14: 'DB_PERF_SEL_DB_SC_tile_tiles', + 15: 'DB_PERF_SEL_DB_SC_tile_culled', + 16: 'DB_PERF_SEL_DB_SC_tile_hier_kill', + 17: 'DB_PERF_SEL_DB_SC_tile_fast_ops', + 18: 'DB_PERF_SEL_DB_SC_tile_no_ops', + 19: 'DB_PERF_SEL_DB_SC_tile_tile_rate', + 20: 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', + 21: 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', + 22: 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', + 23: 'DB_PERF_SEL_SC_DB_quad_sends', + 24: 'DB_PERF_SEL_SC_DB_quad_busy', + 25: 'DB_PERF_SEL_SC_DB_quad_squads', + 26: 'DB_PERF_SEL_SC_DB_quad_tiles', + 27: 'DB_PERF_SEL_SC_DB_quad_pixels', + 28: 'DB_PERF_SEL_SC_DB_quad_killed_tiles', + 29: 'DB_PERF_SEL_DB_SC_quad_sends', + 30: 'DB_PERF_SEL_DB_SC_quad_busy', + 31: 'DB_PERF_SEL_DB_SC_quad_stalls', + 32: 'DB_PERF_SEL_DB_SC_quad_tiles', + 33: 'DB_PERF_SEL_DB_SC_quad_lit_quad', + 34: 'DB_PERF_SEL_DB_CB_tile_sends', + 35: 'DB_PERF_SEL_DB_CB_tile_busy', + 36: 'DB_PERF_SEL_DB_CB_tile_stalls', + 37: 'DB_PERF_SEL_SX_DB_quad_sends', + 38: 'DB_PERF_SEL_SX_DB_quad_busy', + 39: 'DB_PERF_SEL_SX_DB_quad_stalls', + 40: 'DB_PERF_SEL_SX_DB_quad_quads', + 41: 'DB_PERF_SEL_SX_DB_quad_pixels', + 42: 'DB_PERF_SEL_SX_DB_quad_exports', + 43: 'DB_PERF_SEL_SH_quads_outstanding_sum', + 44: 'DB_PERF_SEL_DB_CB_lquad_sends', + 45: 'DB_PERF_SEL_DB_CB_lquad_busy', + 46: 'DB_PERF_SEL_DB_CB_lquad_stalls', + 47: 'DB_PERF_SEL_DB_CB_lquad_quads', + 48: 'DB_PERF_SEL_tile_rd_sends', + 49: 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', + 50: 'DB_PERF_SEL_quad_rd_sends', + 51: 'DB_PERF_SEL_quad_rd_busy', + 52: 'DB_PERF_SEL_quad_rd_mi_stall', + 53: 'DB_PERF_SEL_quad_rd_rw_collision', + 54: 'DB_PERF_SEL_quad_rd_tag_stall', + 55: 'DB_PERF_SEL_quad_rd_32byte_reqs', + 56: 'DB_PERF_SEL_quad_rd_panic', + 57: 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', + 58: 'DB_PERF_SEL_quad_rdret_sends', + 59: 'DB_PERF_SEL_quad_rdret_busy', + 60: 'DB_PERF_SEL_tile_wr_sends', + 61: 'DB_PERF_SEL_tile_wr_acks', + 62: 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', + 63: 'DB_PERF_SEL_quad_wr_sends', + 64: 'DB_PERF_SEL_quad_wr_busy', + 65: 'DB_PERF_SEL_quad_wr_mi_stall', + 66: 'DB_PERF_SEL_quad_wr_coherency_stall', + 67: 'DB_PERF_SEL_quad_wr_acks', + 68: 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', + 69: 'DB_PERF_SEL_Tile_Cache_misses', + 70: 'DB_PERF_SEL_Tile_Cache_hits', + 71: 'DB_PERF_SEL_Tile_Cache_flushes', + 72: 'DB_PERF_SEL_Tile_Cache_surface_stall', + 73: 'DB_PERF_SEL_Tile_Cache_starves', + 74: 'DB_PERF_SEL_Tile_Cache_mem_return_starve', + 75: 'DB_PERF_SEL_tcp_dispatcher_reads', + 76: 'DB_PERF_SEL_tcp_prefetcher_reads', + 77: 'DB_PERF_SEL_tcp_preloader_reads', + 78: 'DB_PERF_SEL_tcp_dispatcher_flushes', + 79: 'DB_PERF_SEL_tcp_prefetcher_flushes', + 80: 'DB_PERF_SEL_tcp_preloader_flushes', + 81: 'DB_PERF_SEL_Depth_Tile_Cache_sends', + 82: 'DB_PERF_SEL_Depth_Tile_Cache_busy', + 83: 'DB_PERF_SEL_Depth_Tile_Cache_starves', + 84: 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', + 85: 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', + 86: 'DB_PERF_SEL_Depth_Tile_Cache_misses', + 87: 'DB_PERF_SEL_Depth_Tile_Cache_hits', + 88: 'DB_PERF_SEL_Depth_Tile_Cache_flushes', + 89: 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', + 90: 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', + 91: 'DB_PERF_SEL_Depth_Tile_Cache_event', + 92: 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', + 93: 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', + 94: 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', + 95: 'DB_PERF_SEL_Stencil_Cache_misses', + 96: 'DB_PERF_SEL_Stencil_Cache_hits', + 97: 'DB_PERF_SEL_Stencil_Cache_flushes', + 98: 'DB_PERF_SEL_Stencil_Cache_starves', + 99: 'DB_PERF_SEL_Stencil_Cache_frees', + 100: 'DB_PERF_SEL_Z_Cache_separate_Z_misses', + 101: 'DB_PERF_SEL_Z_Cache_separate_Z_hits', + 102: 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', + 103: 'DB_PERF_SEL_Z_Cache_separate_Z_starves', + 104: 'DB_PERF_SEL_Z_Cache_pmask_misses', + 105: 'DB_PERF_SEL_Z_Cache_pmask_hits', + 106: 'DB_PERF_SEL_Z_Cache_pmask_flushes', + 107: 'DB_PERF_SEL_Z_Cache_pmask_starves', + 108: 'DB_PERF_SEL_Z_Cache_frees', + 109: 'DB_PERF_SEL_Plane_Cache_misses', + 110: 'DB_PERF_SEL_Plane_Cache_hits', + 111: 'DB_PERF_SEL_Plane_Cache_flushes', + 112: 'DB_PERF_SEL_Plane_Cache_starves', + 113: 'DB_PERF_SEL_Plane_Cache_frees', + 114: 'DB_PERF_SEL_flush_expanded_stencil', + 115: 'DB_PERF_SEL_flush_compressed_stencil', + 116: 'DB_PERF_SEL_flush_single_stencil', + 117: 'DB_PERF_SEL_planes_flushed', + 118: 'DB_PERF_SEL_flush_1plane', + 119: 'DB_PERF_SEL_flush_2plane', + 120: 'DB_PERF_SEL_flush_3plane', + 121: 'DB_PERF_SEL_flush_4plane', + 122: 'DB_PERF_SEL_flush_5plane', + 123: 'DB_PERF_SEL_flush_6plane', + 124: 'DB_PERF_SEL_flush_7plane', + 125: 'DB_PERF_SEL_flush_8plane', + 126: 'DB_PERF_SEL_flush_9plane', + 127: 'DB_PERF_SEL_flush_10plane', + 128: 'DB_PERF_SEL_flush_11plane', + 129: 'DB_PERF_SEL_flush_12plane', + 130: 'DB_PERF_SEL_flush_13plane', + 131: 'DB_PERF_SEL_flush_14plane', + 132: 'DB_PERF_SEL_flush_15plane', + 133: 'DB_PERF_SEL_flush_16plane', + 134: 'DB_PERF_SEL_flush_expanded_z', + 135: 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', + 136: 'DB_PERF_SEL_reZ_waiting_for_postZ_done', + 137: 'DB_PERF_SEL_dk_tile_sends', + 138: 'DB_PERF_SEL_dk_tile_busy', + 139: 'DB_PERF_SEL_dk_tile_quad_starves', + 140: 'DB_PERF_SEL_dk_tile_stalls', + 141: 'DB_PERF_SEL_dk_squad_sends', + 142: 'DB_PERF_SEL_dk_squad_busy', + 143: 'DB_PERF_SEL_dk_squad_stalls', + 144: 'DB_PERF_SEL_Op_Pipe_Busy', + 145: 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', + 146: 'DB_PERF_SEL_qc_busy', + 147: 'DB_PERF_SEL_qc_xfc', + 148: 'DB_PERF_SEL_qc_conflicts', + 149: 'DB_PERF_SEL_qc_full_stall', + 150: 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', + 151: 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', + 152: 'DB_PERF_SEL_tsc_insert_summarize_stall', + 153: 'DB_PERF_SEL_tl_busy', + 154: 'DB_PERF_SEL_tl_dtc_read_starved', + 155: 'DB_PERF_SEL_tl_z_fetch_stall', + 156: 'DB_PERF_SEL_tl_stencil_stall', + 157: 'DB_PERF_SEL_tl_z_decompress_stall', + 158: 'DB_PERF_SEL_tl_stencil_locked_stall', + 159: 'DB_PERF_SEL_tl_events', + 160: 'DB_PERF_SEL_tl_summarize_squads', + 161: 'DB_PERF_SEL_tl_flush_expand_squads', + 162: 'DB_PERF_SEL_tl_expand_squads', + 163: 'DB_PERF_SEL_tl_preZ_squads', + 164: 'DB_PERF_SEL_tl_postZ_squads', + 165: 'DB_PERF_SEL_tl_preZ_noop_squads', + 166: 'DB_PERF_SEL_tl_postZ_noop_squads', + 167: 'DB_PERF_SEL_tl_tile_ops', + 168: 'DB_PERF_SEL_tl_in_xfc', + 169: 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', + 170: 'DB_PERF_SEL_tl_in_fast_z_stall', + 171: 'DB_PERF_SEL_tl_out_xfc', + 172: 'DB_PERF_SEL_tl_out_squads', + 173: 'DB_PERF_SEL_zf_plane_multicycle', + 174: 'DB_PERF_SEL_PostZ_Samples_passing_Z', + 175: 'DB_PERF_SEL_PostZ_Samples_failing_Z', + 176: 'DB_PERF_SEL_PostZ_Samples_failing_S', + 177: 'DB_PERF_SEL_PreZ_Samples_passing_Z', + 178: 'DB_PERF_SEL_PreZ_Samples_failing_Z', + 179: 'DB_PERF_SEL_PreZ_Samples_failing_S', + 180: 'DB_PERF_SEL_ts_tc_update_stall', + 181: 'DB_PERF_SEL_sc_kick_start', + 182: 'DB_PERF_SEL_sc_kick_end', + 183: 'DB_PERF_SEL_clock_reg_active', + 184: 'DB_PERF_SEL_clock_main_active', + 185: 'DB_PERF_SEL_clock_mem_export_active', + 186: 'DB_PERF_SEL_esr_ps_out_busy', + 187: 'DB_PERF_SEL_esr_ps_lqf_busy', + 188: 'DB_PERF_SEL_esr_ps_lqf_stall', + 189: 'DB_PERF_SEL_etr_out_send', + 190: 'DB_PERF_SEL_etr_out_busy', + 191: 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', + 192: 'DB_PERF_SEL_etr_out_cb_tile_stall', + 193: 'DB_PERF_SEL_etr_out_esr_stall', + 194: 'DB_PERF_SEL_esr_ps_sqq_busy', + 195: 'DB_PERF_SEL_esr_ps_sqq_stall', + 196: 'DB_PERF_SEL_esr_eot_fwd_busy', + 197: 'DB_PERF_SEL_esr_eot_fwd_holding_squad', + 198: 'DB_PERF_SEL_esr_eot_fwd_forward', + 199: 'DB_PERF_SEL_esr_sqq_zi_busy', + 200: 'DB_PERF_SEL_esr_sqq_zi_stall', + 201: 'DB_PERF_SEL_postzl_sq_pt_busy', + 202: 'DB_PERF_SEL_postzl_sq_pt_stall', + 203: 'DB_PERF_SEL_postzl_se_busy', + 204: 'DB_PERF_SEL_postzl_se_stall', + 205: 'DB_PERF_SEL_postzl_partial_launch', + 206: 'DB_PERF_SEL_postzl_full_launch', + 207: 'DB_PERF_SEL_postzl_partial_waiting', + 208: 'DB_PERF_SEL_postzl_tile_mem_stall', + 209: 'DB_PERF_SEL_postzl_tile_init_stall', + 210: 'DB_PEFF_SEL_prezl_tile_mem_stall', + 211: 'DB_PERF_SEL_prezl_tile_init_stall', + 212: 'DB_PERF_SEL_dtt_sm_clash_stall', + 213: 'DB_PERF_SEL_dtt_sm_slot_stall', + 214: 'DB_PERF_SEL_dtt_sm_miss_stall', + 215: 'DB_PERF_SEL_mi_rdreq_busy', + 216: 'DB_PERF_SEL_mi_rdreq_stall', + 217: 'DB_PERF_SEL_mi_wrreq_busy', + 218: 'DB_PERF_SEL_mi_wrreq_stall', + 219: 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', + 220: 'DB_PERF_SEL_dkg_tile_rate_tile', + 221: 'DB_PERF_SEL_prezl_src_in_sends', + 222: 'DB_PERF_SEL_prezl_src_in_stall', + 223: 'DB_PERF_SEL_prezl_src_in_squads', + 224: 'DB_PERF_SEL_prezl_src_in_squads_unrolled', + 225: 'DB_PERF_SEL_prezl_src_in_tile_rate', + 226: 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', + 227: 'DB_PERF_SEL_prezl_src_out_stall', + 228: 'DB_PERF_SEL_postzl_src_in_sends', + 229: 'DB_PERF_SEL_postzl_src_in_stall', + 230: 'DB_PERF_SEL_postzl_src_in_squads', + 231: 'DB_PERF_SEL_postzl_src_in_squads_unrolled', + 232: 'DB_PERF_SEL_postzl_src_in_tile_rate', + 233: 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', + 234: 'DB_PERF_SEL_postzl_src_out_stall', + 235: 'DB_PERF_SEL_esr_ps_src_in_sends', + 236: 'DB_PERF_SEL_esr_ps_src_in_stall', + 237: 'DB_PERF_SEL_esr_ps_src_in_squads', + 238: 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', + 239: 'DB_PERF_SEL_esr_ps_src_in_tile_rate', + 240: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', + 241: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', + 242: 'DB_PERF_SEL_esr_ps_src_out_stall', + 243: 'DB_PERF_SEL_depth_bounds_qtiles_culled', + 244: 'DB_PERF_SEL_PreZ_Samples_failing_DB', + 245: 'DB_PERF_SEL_PostZ_Samples_failing_DB', + 246: 'DB_PERF_SEL_flush_compressed', + 247: 'DB_PERF_SEL_flush_plane_le4', + 248: 'DB_PERF_SEL_tiles_z_fully_summarized', + 249: 'DB_PERF_SEL_tiles_stencil_fully_summarized', + 250: 'DB_PERF_SEL_tiles_z_clear_on_expclear', + 251: 'DB_PERF_SEL_tiles_s_clear_on_expclear', + 252: 'DB_PERF_SEL_tiles_decomp_on_expclear', + 253: 'DB_PERF_SEL_tiles_compressed_to_decompressed', + 254: 'DB_PERF_SEL_Op_Pipe_Prez_Busy', + 255: 'DB_PERF_SEL_Op_Pipe_Postz_Busy', + 256: 'DB_PERF_SEL_di_dt_stall', + 257: 'DB_PERF_SEL_DB_SC_quad_double_quad', + 258: 'DB_PERF_SEL_SX_DB_quad_export_quads', + 259: 'DB_PERF_SEL_SX_DB_quad_double_format', + 260: 'DB_PERF_SEL_SX_DB_quad_fast_format', + 261: 'DB_PERF_SEL_SX_DB_quad_slow_format', + 262: 'DB_PERF_SEL_DB_CB_lquad_export_quads', + 263: 'DB_PERF_SEL_DB_CB_lquad_double_format', + 264: 'DB_PERF_SEL_DB_CB_lquad_fast_format', + 265: 'DB_PERF_SEL_DB_CB_lquad_slow_format', + 266: 'DB_PERF_SEL_CB_DB_rdreq_sends', + 267: 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', + 268: 'DB_PERF_SEL_CB_DB_wrreq_sends', + 269: 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', + 270: 'DB_PERF_SEL_DB_CB_rdret_ack', + 271: 'DB_PERF_SEL_DB_CB_rdret_nack', + 272: 'DB_PERF_SEL_DB_CB_wrret_ack', + 273: 'DB_PERF_SEL_DB_CB_wrret_nack', + 274: 'DB_PERF_SEL_DFSM_squads_in', + 275: 'DB_PERF_SEL_DFSM_full_cleared_squads_out', + 276: 'DB_PERF_SEL_DFSM_quads_in', + 277: 'DB_PERF_SEL_DFSM_fully_cleared_quads_out', + 278: 'DB_PERF_SEL_DFSM_lit_pixels_in', + 279: 'DB_PERF_SEL_DFSM_fully_cleared_pixels_out', + 280: 'DB_PERF_SEL_DFSM_lit_samples_in', + 281: 'DB_PERF_SEL_DFSM_lit_samples_out', + 282: 'DB_PERF_SEL_DFSM_cycles_above_watermark', + 283: 'DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream', + 284: 'DB_PERF_SEL_DFSM_stalled_by_downstream', + 285: 'DB_PERF_SEL_DFSM_evicted_squads_above_watermark', + 286: 'DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow', + 287: 'DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO', + 288: 'DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark', +} +DB_PERF_SEL_SC_DB_tile_sends = 0 +DB_PERF_SEL_SC_DB_tile_busy = 1 +DB_PERF_SEL_SC_DB_tile_stalls = 2 +DB_PERF_SEL_SC_DB_tile_events = 3 +DB_PERF_SEL_SC_DB_tile_tiles = 4 +DB_PERF_SEL_SC_DB_tile_covered = 5 +DB_PERF_SEL_hiz_tc_read_starved = 6 +DB_PERF_SEL_hiz_tc_write_stall = 7 +DB_PERF_SEL_hiz_qtiles_culled = 8 +DB_PERF_SEL_his_qtiles_culled = 9 +DB_PERF_SEL_DB_SC_tile_sends = 10 +DB_PERF_SEL_DB_SC_tile_busy = 11 +DB_PERF_SEL_DB_SC_tile_stalls = 12 +DB_PERF_SEL_DB_SC_tile_df_stalls = 13 +DB_PERF_SEL_DB_SC_tile_tiles = 14 +DB_PERF_SEL_DB_SC_tile_culled = 15 +DB_PERF_SEL_DB_SC_tile_hier_kill = 16 +DB_PERF_SEL_DB_SC_tile_fast_ops = 17 +DB_PERF_SEL_DB_SC_tile_no_ops = 18 +DB_PERF_SEL_DB_SC_tile_tile_rate = 19 +DB_PERF_SEL_DB_SC_tile_ssaa_kill = 20 +DB_PERF_SEL_DB_SC_tile_fast_z_ops = 21 +DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 22 +DB_PERF_SEL_SC_DB_quad_sends = 23 +DB_PERF_SEL_SC_DB_quad_busy = 24 +DB_PERF_SEL_SC_DB_quad_squads = 25 +DB_PERF_SEL_SC_DB_quad_tiles = 26 +DB_PERF_SEL_SC_DB_quad_pixels = 27 +DB_PERF_SEL_SC_DB_quad_killed_tiles = 28 +DB_PERF_SEL_DB_SC_quad_sends = 29 +DB_PERF_SEL_DB_SC_quad_busy = 30 +DB_PERF_SEL_DB_SC_quad_stalls = 31 +DB_PERF_SEL_DB_SC_quad_tiles = 32 +DB_PERF_SEL_DB_SC_quad_lit_quad = 33 +DB_PERF_SEL_DB_CB_tile_sends = 34 +DB_PERF_SEL_DB_CB_tile_busy = 35 +DB_PERF_SEL_DB_CB_tile_stalls = 36 +DB_PERF_SEL_SX_DB_quad_sends = 37 +DB_PERF_SEL_SX_DB_quad_busy = 38 +DB_PERF_SEL_SX_DB_quad_stalls = 39 +DB_PERF_SEL_SX_DB_quad_quads = 40 +DB_PERF_SEL_SX_DB_quad_pixels = 41 +DB_PERF_SEL_SX_DB_quad_exports = 42 +DB_PERF_SEL_SH_quads_outstanding_sum = 43 +DB_PERF_SEL_DB_CB_lquad_sends = 44 +DB_PERF_SEL_DB_CB_lquad_busy = 45 +DB_PERF_SEL_DB_CB_lquad_stalls = 46 +DB_PERF_SEL_DB_CB_lquad_quads = 47 +DB_PERF_SEL_tile_rd_sends = 48 +DB_PERF_SEL_mi_tile_rd_outstanding_sum = 49 +DB_PERF_SEL_quad_rd_sends = 50 +DB_PERF_SEL_quad_rd_busy = 51 +DB_PERF_SEL_quad_rd_mi_stall = 52 +DB_PERF_SEL_quad_rd_rw_collision = 53 +DB_PERF_SEL_quad_rd_tag_stall = 54 +DB_PERF_SEL_quad_rd_32byte_reqs = 55 +DB_PERF_SEL_quad_rd_panic = 56 +DB_PERF_SEL_mi_quad_rd_outstanding_sum = 57 +DB_PERF_SEL_quad_rdret_sends = 58 +DB_PERF_SEL_quad_rdret_busy = 59 +DB_PERF_SEL_tile_wr_sends = 60 +DB_PERF_SEL_tile_wr_acks = 61 +DB_PERF_SEL_mi_tile_wr_outstanding_sum = 62 +DB_PERF_SEL_quad_wr_sends = 63 +DB_PERF_SEL_quad_wr_busy = 64 +DB_PERF_SEL_quad_wr_mi_stall = 65 +DB_PERF_SEL_quad_wr_coherency_stall = 66 +DB_PERF_SEL_quad_wr_acks = 67 +DB_PERF_SEL_mi_quad_wr_outstanding_sum = 68 +DB_PERF_SEL_Tile_Cache_misses = 69 +DB_PERF_SEL_Tile_Cache_hits = 70 +DB_PERF_SEL_Tile_Cache_flushes = 71 +DB_PERF_SEL_Tile_Cache_surface_stall = 72 +DB_PERF_SEL_Tile_Cache_starves = 73 +DB_PERF_SEL_Tile_Cache_mem_return_starve = 74 +DB_PERF_SEL_tcp_dispatcher_reads = 75 +DB_PERF_SEL_tcp_prefetcher_reads = 76 +DB_PERF_SEL_tcp_preloader_reads = 77 +DB_PERF_SEL_tcp_dispatcher_flushes = 78 +DB_PERF_SEL_tcp_prefetcher_flushes = 79 +DB_PERF_SEL_tcp_preloader_flushes = 80 +DB_PERF_SEL_Depth_Tile_Cache_sends = 81 +DB_PERF_SEL_Depth_Tile_Cache_busy = 82 +DB_PERF_SEL_Depth_Tile_Cache_starves = 83 +DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 84 +DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 85 +DB_PERF_SEL_Depth_Tile_Cache_misses = 86 +DB_PERF_SEL_Depth_Tile_Cache_hits = 87 +DB_PERF_SEL_Depth_Tile_Cache_flushes = 88 +DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 89 +DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 90 +DB_PERF_SEL_Depth_Tile_Cache_event = 91 +DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 92 +DB_PERF_SEL_Depth_Tile_Cache_data_frees = 93 +DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 94 +DB_PERF_SEL_Stencil_Cache_misses = 95 +DB_PERF_SEL_Stencil_Cache_hits = 96 +DB_PERF_SEL_Stencil_Cache_flushes = 97 +DB_PERF_SEL_Stencil_Cache_starves = 98 +DB_PERF_SEL_Stencil_Cache_frees = 99 +DB_PERF_SEL_Z_Cache_separate_Z_misses = 100 +DB_PERF_SEL_Z_Cache_separate_Z_hits = 101 +DB_PERF_SEL_Z_Cache_separate_Z_flushes = 102 +DB_PERF_SEL_Z_Cache_separate_Z_starves = 103 +DB_PERF_SEL_Z_Cache_pmask_misses = 104 +DB_PERF_SEL_Z_Cache_pmask_hits = 105 +DB_PERF_SEL_Z_Cache_pmask_flushes = 106 +DB_PERF_SEL_Z_Cache_pmask_starves = 107 +DB_PERF_SEL_Z_Cache_frees = 108 +DB_PERF_SEL_Plane_Cache_misses = 109 +DB_PERF_SEL_Plane_Cache_hits = 110 +DB_PERF_SEL_Plane_Cache_flushes = 111 +DB_PERF_SEL_Plane_Cache_starves = 112 +DB_PERF_SEL_Plane_Cache_frees = 113 +DB_PERF_SEL_flush_expanded_stencil = 114 +DB_PERF_SEL_flush_compressed_stencil = 115 +DB_PERF_SEL_flush_single_stencil = 116 +DB_PERF_SEL_planes_flushed = 117 +DB_PERF_SEL_flush_1plane = 118 +DB_PERF_SEL_flush_2plane = 119 +DB_PERF_SEL_flush_3plane = 120 +DB_PERF_SEL_flush_4plane = 121 +DB_PERF_SEL_flush_5plane = 122 +DB_PERF_SEL_flush_6plane = 123 +DB_PERF_SEL_flush_7plane = 124 +DB_PERF_SEL_flush_8plane = 125 +DB_PERF_SEL_flush_9plane = 126 +DB_PERF_SEL_flush_10plane = 127 +DB_PERF_SEL_flush_11plane = 128 +DB_PERF_SEL_flush_12plane = 129 +DB_PERF_SEL_flush_13plane = 130 +DB_PERF_SEL_flush_14plane = 131 +DB_PERF_SEL_flush_15plane = 132 +DB_PERF_SEL_flush_16plane = 133 +DB_PERF_SEL_flush_expanded_z = 134 +DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 135 +DB_PERF_SEL_reZ_waiting_for_postZ_done = 136 +DB_PERF_SEL_dk_tile_sends = 137 +DB_PERF_SEL_dk_tile_busy = 138 +DB_PERF_SEL_dk_tile_quad_starves = 139 +DB_PERF_SEL_dk_tile_stalls = 140 +DB_PERF_SEL_dk_squad_sends = 141 +DB_PERF_SEL_dk_squad_busy = 142 +DB_PERF_SEL_dk_squad_stalls = 143 +DB_PERF_SEL_Op_Pipe_Busy = 144 +DB_PERF_SEL_Op_Pipe_MC_Read_stall = 145 +DB_PERF_SEL_qc_busy = 146 +DB_PERF_SEL_qc_xfc = 147 +DB_PERF_SEL_qc_conflicts = 148 +DB_PERF_SEL_qc_full_stall = 149 +DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 150 +DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 151 +DB_PERF_SEL_tsc_insert_summarize_stall = 152 +DB_PERF_SEL_tl_busy = 153 +DB_PERF_SEL_tl_dtc_read_starved = 154 +DB_PERF_SEL_tl_z_fetch_stall = 155 +DB_PERF_SEL_tl_stencil_stall = 156 +DB_PERF_SEL_tl_z_decompress_stall = 157 +DB_PERF_SEL_tl_stencil_locked_stall = 158 +DB_PERF_SEL_tl_events = 159 +DB_PERF_SEL_tl_summarize_squads = 160 +DB_PERF_SEL_tl_flush_expand_squads = 161 +DB_PERF_SEL_tl_expand_squads = 162 +DB_PERF_SEL_tl_preZ_squads = 163 +DB_PERF_SEL_tl_postZ_squads = 164 +DB_PERF_SEL_tl_preZ_noop_squads = 165 +DB_PERF_SEL_tl_postZ_noop_squads = 166 +DB_PERF_SEL_tl_tile_ops = 167 +DB_PERF_SEL_tl_in_xfc = 168 +DB_PERF_SEL_tl_in_single_stencil_expand_stall = 169 +DB_PERF_SEL_tl_in_fast_z_stall = 170 +DB_PERF_SEL_tl_out_xfc = 171 +DB_PERF_SEL_tl_out_squads = 172 +DB_PERF_SEL_zf_plane_multicycle = 173 +DB_PERF_SEL_PostZ_Samples_passing_Z = 174 +DB_PERF_SEL_PostZ_Samples_failing_Z = 175 +DB_PERF_SEL_PostZ_Samples_failing_S = 176 +DB_PERF_SEL_PreZ_Samples_passing_Z = 177 +DB_PERF_SEL_PreZ_Samples_failing_Z = 178 +DB_PERF_SEL_PreZ_Samples_failing_S = 179 +DB_PERF_SEL_ts_tc_update_stall = 180 +DB_PERF_SEL_sc_kick_start = 181 +DB_PERF_SEL_sc_kick_end = 182 +DB_PERF_SEL_clock_reg_active = 183 +DB_PERF_SEL_clock_main_active = 184 +DB_PERF_SEL_clock_mem_export_active = 185 +DB_PERF_SEL_esr_ps_out_busy = 186 +DB_PERF_SEL_esr_ps_lqf_busy = 187 +DB_PERF_SEL_esr_ps_lqf_stall = 188 +DB_PERF_SEL_etr_out_send = 189 +DB_PERF_SEL_etr_out_busy = 190 +DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 191 +DB_PERF_SEL_etr_out_cb_tile_stall = 192 +DB_PERF_SEL_etr_out_esr_stall = 193 +DB_PERF_SEL_esr_ps_sqq_busy = 194 +DB_PERF_SEL_esr_ps_sqq_stall = 195 +DB_PERF_SEL_esr_eot_fwd_busy = 196 +DB_PERF_SEL_esr_eot_fwd_holding_squad = 197 +DB_PERF_SEL_esr_eot_fwd_forward = 198 +DB_PERF_SEL_esr_sqq_zi_busy = 199 +DB_PERF_SEL_esr_sqq_zi_stall = 200 +DB_PERF_SEL_postzl_sq_pt_busy = 201 +DB_PERF_SEL_postzl_sq_pt_stall = 202 +DB_PERF_SEL_postzl_se_busy = 203 +DB_PERF_SEL_postzl_se_stall = 204 +DB_PERF_SEL_postzl_partial_launch = 205 +DB_PERF_SEL_postzl_full_launch = 206 +DB_PERF_SEL_postzl_partial_waiting = 207 +DB_PERF_SEL_postzl_tile_mem_stall = 208 +DB_PERF_SEL_postzl_tile_init_stall = 209 +DB_PEFF_SEL_prezl_tile_mem_stall = 210 +DB_PERF_SEL_prezl_tile_init_stall = 211 +DB_PERF_SEL_dtt_sm_clash_stall = 212 +DB_PERF_SEL_dtt_sm_slot_stall = 213 +DB_PERF_SEL_dtt_sm_miss_stall = 214 +DB_PERF_SEL_mi_rdreq_busy = 215 +DB_PERF_SEL_mi_rdreq_stall = 216 +DB_PERF_SEL_mi_wrreq_busy = 217 +DB_PERF_SEL_mi_wrreq_stall = 218 +DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 219 +DB_PERF_SEL_dkg_tile_rate_tile = 220 +DB_PERF_SEL_prezl_src_in_sends = 221 +DB_PERF_SEL_prezl_src_in_stall = 222 +DB_PERF_SEL_prezl_src_in_squads = 223 +DB_PERF_SEL_prezl_src_in_squads_unrolled = 224 +DB_PERF_SEL_prezl_src_in_tile_rate = 225 +DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 226 +DB_PERF_SEL_prezl_src_out_stall = 227 +DB_PERF_SEL_postzl_src_in_sends = 228 +DB_PERF_SEL_postzl_src_in_stall = 229 +DB_PERF_SEL_postzl_src_in_squads = 230 +DB_PERF_SEL_postzl_src_in_squads_unrolled = 231 +DB_PERF_SEL_postzl_src_in_tile_rate = 232 +DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 233 +DB_PERF_SEL_postzl_src_out_stall = 234 +DB_PERF_SEL_esr_ps_src_in_sends = 235 +DB_PERF_SEL_esr_ps_src_in_stall = 236 +DB_PERF_SEL_esr_ps_src_in_squads = 237 +DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 238 +DB_PERF_SEL_esr_ps_src_in_tile_rate = 239 +DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 240 +DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 241 +DB_PERF_SEL_esr_ps_src_out_stall = 242 +DB_PERF_SEL_depth_bounds_qtiles_culled = 243 +DB_PERF_SEL_PreZ_Samples_failing_DB = 244 +DB_PERF_SEL_PostZ_Samples_failing_DB = 245 +DB_PERF_SEL_flush_compressed = 246 +DB_PERF_SEL_flush_plane_le4 = 247 +DB_PERF_SEL_tiles_z_fully_summarized = 248 +DB_PERF_SEL_tiles_stencil_fully_summarized = 249 +DB_PERF_SEL_tiles_z_clear_on_expclear = 250 +DB_PERF_SEL_tiles_s_clear_on_expclear = 251 +DB_PERF_SEL_tiles_decomp_on_expclear = 252 +DB_PERF_SEL_tiles_compressed_to_decompressed = 253 +DB_PERF_SEL_Op_Pipe_Prez_Busy = 254 +DB_PERF_SEL_Op_Pipe_Postz_Busy = 255 +DB_PERF_SEL_di_dt_stall = 256 +DB_PERF_SEL_DB_SC_quad_double_quad = 257 +DB_PERF_SEL_SX_DB_quad_export_quads = 258 +DB_PERF_SEL_SX_DB_quad_double_format = 259 +DB_PERF_SEL_SX_DB_quad_fast_format = 260 +DB_PERF_SEL_SX_DB_quad_slow_format = 261 +DB_PERF_SEL_DB_CB_lquad_export_quads = 262 +DB_PERF_SEL_DB_CB_lquad_double_format = 263 +DB_PERF_SEL_DB_CB_lquad_fast_format = 264 +DB_PERF_SEL_DB_CB_lquad_slow_format = 265 +DB_PERF_SEL_CB_DB_rdreq_sends = 266 +DB_PERF_SEL_CB_DB_rdreq_prt_sends = 267 +DB_PERF_SEL_CB_DB_wrreq_sends = 268 +DB_PERF_SEL_CB_DB_wrreq_prt_sends = 269 +DB_PERF_SEL_DB_CB_rdret_ack = 270 +DB_PERF_SEL_DB_CB_rdret_nack = 271 +DB_PERF_SEL_DB_CB_wrret_ack = 272 +DB_PERF_SEL_DB_CB_wrret_nack = 273 +DB_PERF_SEL_DFSM_squads_in = 274 +DB_PERF_SEL_DFSM_full_cleared_squads_out = 275 +DB_PERF_SEL_DFSM_quads_in = 276 +DB_PERF_SEL_DFSM_fully_cleared_quads_out = 277 +DB_PERF_SEL_DFSM_lit_pixels_in = 278 +DB_PERF_SEL_DFSM_fully_cleared_pixels_out = 279 +DB_PERF_SEL_DFSM_lit_samples_in = 280 +DB_PERF_SEL_DFSM_lit_samples_out = 281 +DB_PERF_SEL_DFSM_cycles_above_watermark = 282 +DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream = 283 +DB_PERF_SEL_DFSM_stalled_by_downstream = 284 +DB_PERF_SEL_DFSM_evicted_squads_above_watermark = 285 +DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow = 286 +DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO = 287 +DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark = 288 +PerfCounter_Vals = ctypes.c_uint32 # enum + +# values for enumeration 'RingCounterControl' +RingCounterControl__enumvalues = { + 0: 'COUNTER_RING_SPLIT', + 1: 'COUNTER_RING_0', + 2: 'COUNTER_RING_1', +} +COUNTER_RING_SPLIT = 0 +COUNTER_RING_0 = 1 +COUNTER_RING_1 = 2 +RingCounterControl = ctypes.c_uint32 # enum + +# values for enumeration 'DbMemArbWatermarks' +DbMemArbWatermarks__enumvalues = { + 0: 'TRANSFERRED_64_BYTES', + 1: 'TRANSFERRED_128_BYTES', + 2: 'TRANSFERRED_256_BYTES', + 3: 'TRANSFERRED_512_BYTES', + 4: 'TRANSFERRED_1024_BYTES', + 5: 'TRANSFERRED_2048_BYTES', + 6: 'TRANSFERRED_4096_BYTES', + 7: 'TRANSFERRED_8192_BYTES', +} +TRANSFERRED_64_BYTES = 0 +TRANSFERRED_128_BYTES = 1 +TRANSFERRED_256_BYTES = 2 +TRANSFERRED_512_BYTES = 3 +TRANSFERRED_1024_BYTES = 4 +TRANSFERRED_2048_BYTES = 5 +TRANSFERRED_4096_BYTES = 6 +TRANSFERRED_8192_BYTES = 7 +DbMemArbWatermarks = ctypes.c_uint32 # enum + +# values for enumeration 'DFSMFlushEvents' +DFSMFlushEvents__enumvalues = { + 0: 'DB_FLUSH_AND_INV_DB_DATA_TS', + 1: 'DB_FLUSH_AND_INV_DB_META', + 2: 'DB_CACHE_FLUSH', + 3: 'DB_CACHE_FLUSH_TS', + 4: 'DB_CACHE_FLUSH_AND_INV_EVENT', + 5: 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', +} +DB_FLUSH_AND_INV_DB_DATA_TS = 0 +DB_FLUSH_AND_INV_DB_META = 1 +DB_CACHE_FLUSH = 2 +DB_CACHE_FLUSH_TS = 3 +DB_CACHE_FLUSH_AND_INV_EVENT = 4 +DB_CACHE_FLUSH_AND_INV_TS_EVENT = 5 +DFSMFlushEvents = ctypes.c_uint32 # enum + +# values for enumeration 'PixelPipeCounterId' +PixelPipeCounterId__enumvalues = { + 0: 'PIXEL_PIPE_OCCLUSION_COUNT_0', + 1: 'PIXEL_PIPE_OCCLUSION_COUNT_1', + 2: 'PIXEL_PIPE_OCCLUSION_COUNT_2', + 3: 'PIXEL_PIPE_OCCLUSION_COUNT_3', + 4: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', + 5: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', + 6: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', + 7: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', +} +PIXEL_PIPE_OCCLUSION_COUNT_0 = 0 +PIXEL_PIPE_OCCLUSION_COUNT_1 = 1 +PIXEL_PIPE_OCCLUSION_COUNT_2 = 2 +PIXEL_PIPE_OCCLUSION_COUNT_3 = 3 +PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 4 +PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 5 +PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 6 +PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 7 +PixelPipeCounterId = ctypes.c_uint32 # enum + +# values for enumeration 'PixelPipeStride' +PixelPipeStride__enumvalues = { + 0: 'PIXEL_PIPE_STRIDE_32_BITS', + 1: 'PIXEL_PIPE_STRIDE_64_BITS', + 2: 'PIXEL_PIPE_STRIDE_128_BITS', + 3: 'PIXEL_PIPE_STRIDE_256_BITS', +} +PIXEL_PIPE_STRIDE_32_BITS = 0 +PIXEL_PIPE_STRIDE_64_BITS = 1 +PIXEL_PIPE_STRIDE_128_BITS = 2 +PIXEL_PIPE_STRIDE_256_BITS = 3 +PixelPipeStride = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_BORDER_COLOR_TYPE' +TEX_BORDER_COLOR_TYPE__enumvalues = { + 0: 'TEX_BorderColor_TransparentBlack', + 1: 'TEX_BorderColor_OpaqueBlack', + 2: 'TEX_BorderColor_OpaqueWhite', + 3: 'TEX_BorderColor_Register', +} +TEX_BorderColor_TransparentBlack = 0 +TEX_BorderColor_OpaqueBlack = 1 +TEX_BorderColor_OpaqueWhite = 2 +TEX_BorderColor_Register = 3 +TEX_BORDER_COLOR_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_CHROMA_KEY' +TEX_CHROMA_KEY__enumvalues = { + 0: 'TEX_ChromaKey_Disabled', + 1: 'TEX_ChromaKey_Kill', + 2: 'TEX_ChromaKey_Blend', + 3: 'TEX_ChromaKey_RESERVED_3', +} +TEX_ChromaKey_Disabled = 0 +TEX_ChromaKey_Kill = 1 +TEX_ChromaKey_Blend = 2 +TEX_ChromaKey_RESERVED_3 = 3 +TEX_CHROMA_KEY = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_CLAMP' +TEX_CLAMP__enumvalues = { + 0: 'TEX_Clamp_Repeat', + 1: 'TEX_Clamp_Mirror', + 2: 'TEX_Clamp_ClampToLast', + 3: 'TEX_Clamp_MirrorOnceToLast', + 4: 'TEX_Clamp_ClampHalfToBorder', + 5: 'TEX_Clamp_MirrorOnceHalfToBorder', + 6: 'TEX_Clamp_ClampToBorder', + 7: 'TEX_Clamp_MirrorOnceToBorder', +} +TEX_Clamp_Repeat = 0 +TEX_Clamp_Mirror = 1 +TEX_Clamp_ClampToLast = 2 +TEX_Clamp_MirrorOnceToLast = 3 +TEX_Clamp_ClampHalfToBorder = 4 +TEX_Clamp_MirrorOnceHalfToBorder = 5 +TEX_Clamp_ClampToBorder = 6 +TEX_Clamp_MirrorOnceToBorder = 7 +TEX_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_COORD_TYPE' +TEX_COORD_TYPE__enumvalues = { + 0: 'TEX_CoordType_Unnormalized', + 1: 'TEX_CoordType_Normalized', +} +TEX_CoordType_Unnormalized = 0 +TEX_CoordType_Normalized = 1 +TEX_COORD_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_DEPTH_COMPARE_FUNCTION' +TEX_DEPTH_COMPARE_FUNCTION__enumvalues = { + 0: 'TEX_DepthCompareFunction_Never', + 1: 'TEX_DepthCompareFunction_Less', + 2: 'TEX_DepthCompareFunction_Equal', + 3: 'TEX_DepthCompareFunction_LessEqual', + 4: 'TEX_DepthCompareFunction_Greater', + 5: 'TEX_DepthCompareFunction_NotEqual', + 6: 'TEX_DepthCompareFunction_GreaterEqual', + 7: 'TEX_DepthCompareFunction_Always', +} +TEX_DepthCompareFunction_Never = 0 +TEX_DepthCompareFunction_Less = 1 +TEX_DepthCompareFunction_Equal = 2 +TEX_DepthCompareFunction_LessEqual = 3 +TEX_DepthCompareFunction_Greater = 4 +TEX_DepthCompareFunction_NotEqual = 5 +TEX_DepthCompareFunction_GreaterEqual = 6 +TEX_DepthCompareFunction_Always = 7 +TEX_DEPTH_COMPARE_FUNCTION = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_DIM' +TEX_DIM__enumvalues = { + 0: 'TEX_Dim_1D', + 1: 'TEX_Dim_2D', + 2: 'TEX_Dim_3D', + 3: 'TEX_Dim_CubeMap', + 4: 'TEX_Dim_1DArray', + 5: 'TEX_Dim_2DArray', + 6: 'TEX_Dim_2D_MSAA', + 7: 'TEX_Dim_2DArray_MSAA', +} +TEX_Dim_1D = 0 +TEX_Dim_2D = 1 +TEX_Dim_3D = 2 +TEX_Dim_CubeMap = 3 +TEX_Dim_1DArray = 4 +TEX_Dim_2DArray = 5 +TEX_Dim_2D_MSAA = 6 +TEX_Dim_2DArray_MSAA = 7 +TEX_DIM = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_FORMAT_COMP' +TEX_FORMAT_COMP__enumvalues = { + 0: 'TEX_FormatComp_Unsigned', + 1: 'TEX_FormatComp_Signed', + 2: 'TEX_FormatComp_UnsignedBiased', + 3: 'TEX_FormatComp_RESERVED_3', +} +TEX_FormatComp_Unsigned = 0 +TEX_FormatComp_Signed = 1 +TEX_FormatComp_UnsignedBiased = 2 +TEX_FormatComp_RESERVED_3 = 3 +TEX_FORMAT_COMP = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_MAX_ANISO_RATIO' +TEX_MAX_ANISO_RATIO__enumvalues = { + 0: 'TEX_MaxAnisoRatio_1to1', + 1: 'TEX_MaxAnisoRatio_2to1', + 2: 'TEX_MaxAnisoRatio_4to1', + 3: 'TEX_MaxAnisoRatio_8to1', + 4: 'TEX_MaxAnisoRatio_16to1', + 5: 'TEX_MaxAnisoRatio_RESERVED_5', + 6: 'TEX_MaxAnisoRatio_RESERVED_6', + 7: 'TEX_MaxAnisoRatio_RESERVED_7', +} +TEX_MaxAnisoRatio_1to1 = 0 +TEX_MaxAnisoRatio_2to1 = 1 +TEX_MaxAnisoRatio_4to1 = 2 +TEX_MaxAnisoRatio_8to1 = 3 +TEX_MaxAnisoRatio_16to1 = 4 +TEX_MaxAnisoRatio_RESERVED_5 = 5 +TEX_MaxAnisoRatio_RESERVED_6 = 6 +TEX_MaxAnisoRatio_RESERVED_7 = 7 +TEX_MAX_ANISO_RATIO = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_MIP_FILTER' +TEX_MIP_FILTER__enumvalues = { + 0: 'TEX_MipFilter_None', + 1: 'TEX_MipFilter_Point', + 2: 'TEX_MipFilter_Linear', + 3: 'TEX_MipFilter_Point_Aniso_Adj', +} +TEX_MipFilter_None = 0 +TEX_MipFilter_Point = 1 +TEX_MipFilter_Linear = 2 +TEX_MipFilter_Point_Aniso_Adj = 3 +TEX_MIP_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_REQUEST_SIZE' +TEX_REQUEST_SIZE__enumvalues = { + 0: 'TEX_RequestSize_32B', + 1: 'TEX_RequestSize_64B', + 2: 'TEX_RequestSize_128B', + 3: 'TEX_RequestSize_2X64B', +} +TEX_RequestSize_32B = 0 +TEX_RequestSize_64B = 1 +TEX_RequestSize_128B = 2 +TEX_RequestSize_2X64B = 3 +TEX_REQUEST_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_SAMPLER_TYPE' +TEX_SAMPLER_TYPE__enumvalues = { + 0: 'TEX_SamplerType_Invalid', + 1: 'TEX_SamplerType_Valid', +} +TEX_SamplerType_Invalid = 0 +TEX_SamplerType_Valid = 1 +TEX_SAMPLER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_XY_FILTER' +TEX_XY_FILTER__enumvalues = { + 0: 'TEX_XYFilter_Point', + 1: 'TEX_XYFilter_Linear', + 2: 'TEX_XYFilter_AnisoPoint', + 3: 'TEX_XYFilter_AnisoLinear', +} +TEX_XYFilter_Point = 0 +TEX_XYFilter_Linear = 1 +TEX_XYFilter_AnisoPoint = 2 +TEX_XYFilter_AnisoLinear = 3 +TEX_XY_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_Z_FILTER' +TEX_Z_FILTER__enumvalues = { + 0: 'TEX_ZFilter_None', + 1: 'TEX_ZFilter_Point', + 2: 'TEX_ZFilter_Linear', + 3: 'TEX_ZFilter_RESERVED_3', +} +TEX_ZFilter_None = 0 +TEX_ZFilter_Point = 1 +TEX_ZFilter_Linear = 2 +TEX_ZFilter_RESERVED_3 = 3 +TEX_Z_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'VTX_CLAMP' +VTX_CLAMP__enumvalues = { + 0: 'VTX_Clamp_ClampToZero', + 1: 'VTX_Clamp_ClampToNAN', +} +VTX_Clamp_ClampToZero = 0 +VTX_Clamp_ClampToNAN = 1 +VTX_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'VTX_FETCH_TYPE' +VTX_FETCH_TYPE__enumvalues = { + 0: 'VTX_FetchType_VertexData', + 1: 'VTX_FetchType_InstanceData', + 2: 'VTX_FetchType_NoIndexOffset', + 3: 'VTX_FetchType_RESERVED_3', +} +VTX_FetchType_VertexData = 0 +VTX_FetchType_InstanceData = 1 +VTX_FetchType_NoIndexOffset = 2 +VTX_FetchType_RESERVED_3 = 3 +VTX_FETCH_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VTX_FORMAT_COMP_ALL' +VTX_FORMAT_COMP_ALL__enumvalues = { + 0: 'VTX_FormatCompAll_Unsigned', + 1: 'VTX_FormatCompAll_Signed', +} +VTX_FormatCompAll_Unsigned = 0 +VTX_FormatCompAll_Signed = 1 +VTX_FORMAT_COMP_ALL = ctypes.c_uint32 # enum + +# values for enumeration 'VTX_MEM_REQUEST_SIZE' +VTX_MEM_REQUEST_SIZE__enumvalues = { + 0: 'VTX_MemRequestSize_32B', + 1: 'VTX_MemRequestSize_64B', +} +VTX_MemRequestSize_32B = 0 +VTX_MemRequestSize_64B = 1 +VTX_MEM_REQUEST_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_DATA_FORMAT' +TVX_DATA_FORMAT__enumvalues = { + 0: 'TVX_FMT_INVALID', + 1: 'TVX_FMT_8', + 2: 'TVX_FMT_4_4', + 3: 'TVX_FMT_3_3_2', + 4: 'TVX_FMT_RESERVED_4', + 5: 'TVX_FMT_16', + 6: 'TVX_FMT_16_FLOAT', + 7: 'TVX_FMT_8_8', + 8: 'TVX_FMT_5_6_5', + 9: 'TVX_FMT_6_5_5', + 10: 'TVX_FMT_1_5_5_5', + 11: 'TVX_FMT_4_4_4_4', + 12: 'TVX_FMT_5_5_5_1', + 13: 'TVX_FMT_32', + 14: 'TVX_FMT_32_FLOAT', + 15: 'TVX_FMT_16_16', + 16: 'TVX_FMT_16_16_FLOAT', + 17: 'TVX_FMT_8_24', + 18: 'TVX_FMT_8_24_FLOAT', + 19: 'TVX_FMT_24_8', + 20: 'TVX_FMT_24_8_FLOAT', + 21: 'TVX_FMT_10_11_11', + 22: 'TVX_FMT_10_11_11_FLOAT', + 23: 'TVX_FMT_11_11_10', + 24: 'TVX_FMT_11_11_10_FLOAT', + 25: 'TVX_FMT_2_10_10_10', + 26: 'TVX_FMT_8_8_8_8', + 27: 'TVX_FMT_10_10_10_2', + 28: 'TVX_FMT_X24_8_32_FLOAT', + 29: 'TVX_FMT_32_32', + 30: 'TVX_FMT_32_32_FLOAT', + 31: 'TVX_FMT_16_16_16_16', + 32: 'TVX_FMT_16_16_16_16_FLOAT', + 33: 'TVX_FMT_RESERVED_33', + 34: 'TVX_FMT_32_32_32_32', + 35: 'TVX_FMT_32_32_32_32_FLOAT', + 36: 'TVX_FMT_RESERVED_36', + 37: 'TVX_FMT_1', + 38: 'TVX_FMT_1_REVERSED', + 39: 'TVX_FMT_GB_GR', + 40: 'TVX_FMT_BG_RG', + 41: 'TVX_FMT_32_AS_8', + 42: 'TVX_FMT_32_AS_8_8', + 43: 'TVX_FMT_5_9_9_9_SHAREDEXP', + 44: 'TVX_FMT_8_8_8', + 45: 'TVX_FMT_16_16_16', + 46: 'TVX_FMT_16_16_16_FLOAT', + 47: 'TVX_FMT_32_32_32', + 48: 'TVX_FMT_32_32_32_FLOAT', + 49: 'TVX_FMT_BC1', + 50: 'TVX_FMT_BC2', + 51: 'TVX_FMT_BC3', + 52: 'TVX_FMT_BC4', + 53: 'TVX_FMT_BC5', + 54: 'TVX_FMT_APC0', + 55: 'TVX_FMT_APC1', + 56: 'TVX_FMT_APC2', + 57: 'TVX_FMT_APC3', + 58: 'TVX_FMT_APC4', + 59: 'TVX_FMT_APC5', + 60: 'TVX_FMT_APC6', + 61: 'TVX_FMT_APC7', + 62: 'TVX_FMT_CTX1', + 63: 'TVX_FMT_RESERVED_63', +} +TVX_FMT_INVALID = 0 +TVX_FMT_8 = 1 +TVX_FMT_4_4 = 2 +TVX_FMT_3_3_2 = 3 +TVX_FMT_RESERVED_4 = 4 +TVX_FMT_16 = 5 +TVX_FMT_16_FLOAT = 6 +TVX_FMT_8_8 = 7 +TVX_FMT_5_6_5 = 8 +TVX_FMT_6_5_5 = 9 +TVX_FMT_1_5_5_5 = 10 +TVX_FMT_4_4_4_4 = 11 +TVX_FMT_5_5_5_1 = 12 +TVX_FMT_32 = 13 +TVX_FMT_32_FLOAT = 14 +TVX_FMT_16_16 = 15 +TVX_FMT_16_16_FLOAT = 16 +TVX_FMT_8_24 = 17 +TVX_FMT_8_24_FLOAT = 18 +TVX_FMT_24_8 = 19 +TVX_FMT_24_8_FLOAT = 20 +TVX_FMT_10_11_11 = 21 +TVX_FMT_10_11_11_FLOAT = 22 +TVX_FMT_11_11_10 = 23 +TVX_FMT_11_11_10_FLOAT = 24 +TVX_FMT_2_10_10_10 = 25 +TVX_FMT_8_8_8_8 = 26 +TVX_FMT_10_10_10_2 = 27 +TVX_FMT_X24_8_32_FLOAT = 28 +TVX_FMT_32_32 = 29 +TVX_FMT_32_32_FLOAT = 30 +TVX_FMT_16_16_16_16 = 31 +TVX_FMT_16_16_16_16_FLOAT = 32 +TVX_FMT_RESERVED_33 = 33 +TVX_FMT_32_32_32_32 = 34 +TVX_FMT_32_32_32_32_FLOAT = 35 +TVX_FMT_RESERVED_36 = 36 +TVX_FMT_1 = 37 +TVX_FMT_1_REVERSED = 38 +TVX_FMT_GB_GR = 39 +TVX_FMT_BG_RG = 40 +TVX_FMT_32_AS_8 = 41 +TVX_FMT_32_AS_8_8 = 42 +TVX_FMT_5_9_9_9_SHAREDEXP = 43 +TVX_FMT_8_8_8 = 44 +TVX_FMT_16_16_16 = 45 +TVX_FMT_16_16_16_FLOAT = 46 +TVX_FMT_32_32_32 = 47 +TVX_FMT_32_32_32_FLOAT = 48 +TVX_FMT_BC1 = 49 +TVX_FMT_BC2 = 50 +TVX_FMT_BC3 = 51 +TVX_FMT_BC4 = 52 +TVX_FMT_BC5 = 53 +TVX_FMT_APC0 = 54 +TVX_FMT_APC1 = 55 +TVX_FMT_APC2 = 56 +TVX_FMT_APC3 = 57 +TVX_FMT_APC4 = 58 +TVX_FMT_APC5 = 59 +TVX_FMT_APC6 = 60 +TVX_FMT_APC7 = 61 +TVX_FMT_CTX1 = 62 +TVX_FMT_RESERVED_63 = 63 +TVX_DATA_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_DST_SEL' +TVX_DST_SEL__enumvalues = { + 0: 'TVX_DstSel_X', + 1: 'TVX_DstSel_Y', + 2: 'TVX_DstSel_Z', + 3: 'TVX_DstSel_W', + 4: 'TVX_DstSel_0f', + 5: 'TVX_DstSel_1f', + 6: 'TVX_DstSel_RESERVED_6', + 7: 'TVX_DstSel_Mask', +} +TVX_DstSel_X = 0 +TVX_DstSel_Y = 1 +TVX_DstSel_Z = 2 +TVX_DstSel_W = 3 +TVX_DstSel_0f = 4 +TVX_DstSel_1f = 5 +TVX_DstSel_RESERVED_6 = 6 +TVX_DstSel_Mask = 7 +TVX_DST_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_ENDIAN_SWAP' +TVX_ENDIAN_SWAP__enumvalues = { + 0: 'TVX_EndianSwap_None', + 1: 'TVX_EndianSwap_8in16', + 2: 'TVX_EndianSwap_8in32', + 3: 'TVX_EndianSwap_8in64', +} +TVX_EndianSwap_None = 0 +TVX_EndianSwap_8in16 = 1 +TVX_EndianSwap_8in32 = 2 +TVX_EndianSwap_8in64 = 3 +TVX_ENDIAN_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_INST' +TVX_INST__enumvalues = { + 0: 'TVX_Inst_NormalVertexFetch', + 1: 'TVX_Inst_SemanticVertexFetch', + 2: 'TVX_Inst_RESERVED_2', + 3: 'TVX_Inst_LD', + 4: 'TVX_Inst_GetTextureResInfo', + 5: 'TVX_Inst_GetNumberOfSamples', + 6: 'TVX_Inst_GetLOD', + 7: 'TVX_Inst_GetGradientsH', + 8: 'TVX_Inst_GetGradientsV', + 9: 'TVX_Inst_SetTextureOffsets', + 10: 'TVX_Inst_KeepGradients', + 11: 'TVX_Inst_SetGradientsH', + 12: 'TVX_Inst_SetGradientsV', + 13: 'TVX_Inst_Pass', + 14: 'TVX_Inst_GetBufferResInfo', + 15: 'TVX_Inst_RESERVED_15', + 16: 'TVX_Inst_Sample', + 17: 'TVX_Inst_Sample_L', + 18: 'TVX_Inst_Sample_LB', + 19: 'TVX_Inst_Sample_LZ', + 20: 'TVX_Inst_Sample_G', + 21: 'TVX_Inst_Gather4', + 22: 'TVX_Inst_Sample_G_LB', + 23: 'TVX_Inst_Gather4_O', + 24: 'TVX_Inst_Sample_C', + 25: 'TVX_Inst_Sample_C_L', + 26: 'TVX_Inst_Sample_C_LB', + 27: 'TVX_Inst_Sample_C_LZ', + 28: 'TVX_Inst_Sample_C_G', + 29: 'TVX_Inst_Gather4_C', + 30: 'TVX_Inst_Sample_C_G_LB', + 31: 'TVX_Inst_Gather4_C_O', +} +TVX_Inst_NormalVertexFetch = 0 +TVX_Inst_SemanticVertexFetch = 1 +TVX_Inst_RESERVED_2 = 2 +TVX_Inst_LD = 3 +TVX_Inst_GetTextureResInfo = 4 +TVX_Inst_GetNumberOfSamples = 5 +TVX_Inst_GetLOD = 6 +TVX_Inst_GetGradientsH = 7 +TVX_Inst_GetGradientsV = 8 +TVX_Inst_SetTextureOffsets = 9 +TVX_Inst_KeepGradients = 10 +TVX_Inst_SetGradientsH = 11 +TVX_Inst_SetGradientsV = 12 +TVX_Inst_Pass = 13 +TVX_Inst_GetBufferResInfo = 14 +TVX_Inst_RESERVED_15 = 15 +TVX_Inst_Sample = 16 +TVX_Inst_Sample_L = 17 +TVX_Inst_Sample_LB = 18 +TVX_Inst_Sample_LZ = 19 +TVX_Inst_Sample_G = 20 +TVX_Inst_Gather4 = 21 +TVX_Inst_Sample_G_LB = 22 +TVX_Inst_Gather4_O = 23 +TVX_Inst_Sample_C = 24 +TVX_Inst_Sample_C_L = 25 +TVX_Inst_Sample_C_LB = 26 +TVX_Inst_Sample_C_LZ = 27 +TVX_Inst_Sample_C_G = 28 +TVX_Inst_Gather4_C = 29 +TVX_Inst_Sample_C_G_LB = 30 +TVX_Inst_Gather4_C_O = 31 +TVX_INST = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_NUM_FORMAT_ALL' +TVX_NUM_FORMAT_ALL__enumvalues = { + 0: 'TVX_NumFormatAll_Norm', + 1: 'TVX_NumFormatAll_Int', + 2: 'TVX_NumFormatAll_Scaled', + 3: 'TVX_NumFormatAll_RESERVED_3', +} +TVX_NumFormatAll_Norm = 0 +TVX_NumFormatAll_Int = 1 +TVX_NumFormatAll_Scaled = 2 +TVX_NumFormatAll_RESERVED_3 = 3 +TVX_NUM_FORMAT_ALL = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_SRC_SEL' +TVX_SRC_SEL__enumvalues = { + 0: 'TVX_SrcSel_X', + 1: 'TVX_SrcSel_Y', + 2: 'TVX_SrcSel_Z', + 3: 'TVX_SrcSel_W', + 4: 'TVX_SrcSel_0f', + 5: 'TVX_SrcSel_1f', +} +TVX_SrcSel_X = 0 +TVX_SrcSel_Y = 1 +TVX_SrcSel_Z = 2 +TVX_SrcSel_W = 3 +TVX_SrcSel_0f = 4 +TVX_SrcSel_1f = 5 +TVX_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_SRF_MODE_ALL' +TVX_SRF_MODE_ALL__enumvalues = { + 0: 'TVX_SRFModeAll_ZCMO', + 1: 'TVX_SRFModeAll_NZ', +} +TVX_SRFModeAll_ZCMO = 0 +TVX_SRFModeAll_NZ = 1 +TVX_SRF_MODE_ALL = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_TYPE' +TVX_TYPE__enumvalues = { + 0: 'TVX_Type_InvalidTextureResource', + 1: 'TVX_Type_InvalidVertexBuffer', + 2: 'TVX_Type_ValidTextureResource', + 3: 'TVX_Type_ValidVertexBuffer', +} +TVX_Type_InvalidTextureResource = 0 +TVX_Type_InvalidVertexBuffer = 1 +TVX_Type_ValidTextureResource = 2 +TVX_Type_ValidVertexBuffer = 3 +TVX_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SU_PERFCNT_SEL' +SU_PERFCNT_SEL__enumvalues = { + 0: 'PERF_PAPC_PASX_REQ', + 1: 'PERF_PAPC_PASX_DISABLE_PIPE', + 2: 'PERF_PAPC_PASX_FIRST_VECTOR', + 3: 'PERF_PAPC_PASX_SECOND_VECTOR', + 4: 'PERF_PAPC_PASX_FIRST_DEAD', + 5: 'PERF_PAPC_PASX_SECOND_DEAD', + 6: 'PERF_PAPC_PASX_VTX_KILL_DISCARD', + 7: 'PERF_PAPC_PASX_VTX_NAN_DISCARD', + 8: 'PERF_PAPC_PA_INPUT_PRIM', + 9: 'PERF_PAPC_PA_INPUT_NULL_PRIM', + 10: 'PERF_PAPC_PA_INPUT_EVENT_FLAG', + 11: 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', + 12: 'PERF_PAPC_PA_INPUT_END_OF_PACKET', + 13: 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', + 14: 'PERF_PAPC_CLPR_CULL_PRIM', + 15: 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', + 16: 'PERF_PAPC_CLPR_VV_CULL_PRIM', + 17: 'PERF_PAPC_CLPR_UCP_CULL_PRIM', + 18: 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', + 19: 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', + 20: 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', + 21: 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', + 22: 'PERF_PAPC_CLPR_VV_CLIP_PRIM', + 23: 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', + 24: 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', + 25: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', + 26: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', + 27: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', + 28: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', + 29: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', + 30: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', + 31: 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', + 32: 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', + 33: 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', + 34: 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', + 35: 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', + 36: 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', + 37: 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', + 38: 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', + 39: 'PERF_PAPC_CLSM_NULL_PRIM', + 40: 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', + 41: 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', + 42: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', + 43: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', + 44: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', + 45: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', + 46: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', + 47: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', + 48: 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', + 49: 'PERF_PAPC_SU_INPUT_PRIM', + 50: 'PERF_PAPC_SU_INPUT_CLIP_PRIM', + 51: 'PERF_PAPC_SU_INPUT_NULL_PRIM', + 52: 'PERF_PAPC_SU_INPUT_PRIM_DUAL', + 53: 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', + 54: 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', + 55: 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', + 56: 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', + 57: 'PERF_PAPC_SU_POLYMODE_FACE_CULL', + 58: 'PERF_PAPC_SU_POLYMODE_BACK_CULL', + 59: 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', + 60: 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', + 61: 'PERF_PAPC_SU_OUTPUT_PRIM', + 62: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', + 63: 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', + 64: 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', + 65: 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', + 66: 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', + 67: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', + 68: 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', + 69: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', + 70: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', + 71: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', + 72: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', + 73: 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', + 74: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', + 75: 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', + 76: 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', + 77: 'PERF_PAPC_PASX_REQ_IDLE', + 78: 'PERF_PAPC_PASX_REQ_BUSY', + 79: 'PERF_PAPC_PASX_REQ_STALLED', + 80: 'PERF_PAPC_PASX_REC_IDLE', + 81: 'PERF_PAPC_PASX_REC_BUSY', + 82: 'PERF_PAPC_PASX_REC_STARVED_SX', + 83: 'PERF_PAPC_PASX_REC_STALLED', + 84: 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', + 85: 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', + 86: 'PERF_PAPC_CCGSM_IDLE', + 87: 'PERF_PAPC_CCGSM_BUSY', + 88: 'PERF_PAPC_CCGSM_STALLED', + 89: 'PERF_PAPC_CLPRIM_IDLE', + 90: 'PERF_PAPC_CLPRIM_BUSY', + 91: 'PERF_PAPC_CLPRIM_STALLED', + 92: 'PERF_PAPC_CLPRIM_STARVED_CCGSM', + 93: 'PERF_PAPC_CLIPSM_IDLE', + 94: 'PERF_PAPC_CLIPSM_BUSY', + 95: 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', + 96: 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', + 97: 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', + 98: 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', + 99: 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', + 100: 'PERF_PAPC_CLIPGA_IDLE', + 101: 'PERF_PAPC_CLIPGA_BUSY', + 102: 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', + 103: 'PERF_PAPC_CLIPGA_STALLED', + 104: 'PERF_PAPC_CLIP_IDLE', + 105: 'PERF_PAPC_CLIP_BUSY', + 106: 'PERF_PAPC_SU_IDLE', + 107: 'PERF_PAPC_SU_BUSY', + 108: 'PERF_PAPC_SU_STARVED_CLIP', + 109: 'PERF_PAPC_SU_STALLED_SC', + 110: 'PERF_PAPC_CL_DYN_SCLK_VLD', + 111: 'PERF_PAPC_SU_DYN_SCLK_VLD', + 112: 'PERF_PAPC_PA_REG_SCLK_VLD', + 113: 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', + 114: 'PERF_PAPC_PASX_SE0_REQ', + 115: 'PERF_PAPC_PASX_SE1_REQ', + 116: 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', + 117: 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', + 118: 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', + 119: 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', + 120: 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', + 121: 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', + 122: 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', + 123: 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', + 124: 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', + 125: 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', + 126: 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', + 127: 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', + 128: 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', + 129: 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', + 130: 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', + 131: 'PERF_PAPC_SU_SE0_STALLED_SC', + 132: 'PERF_PAPC_SU_SE1_STALLED_SC', + 133: 'PERF_PAPC_SU_SE01_STALLED_SC', + 134: 'PERF_PAPC_CLSM_CLIPPING_PRIM', + 135: 'PERF_PAPC_SU_CULLED_PRIM', + 136: 'PERF_PAPC_SU_OUTPUT_EOPG', + 137: 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', + 138: 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', + 139: 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', + 140: 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', + 141: 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', + 142: 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', + 143: 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', + 144: 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', + 145: 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', + 146: 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', + 147: 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', + 148: 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', + 149: 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', + 150: 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', + 151: 'PERF_PAPC_SU_SE2_STALLED_SC', + 152: 'PERF_PAPC_SU_SE3_STALLED_SC', +} +PERF_PAPC_PASX_REQ = 0 +PERF_PAPC_PASX_DISABLE_PIPE = 1 +PERF_PAPC_PASX_FIRST_VECTOR = 2 +PERF_PAPC_PASX_SECOND_VECTOR = 3 +PERF_PAPC_PASX_FIRST_DEAD = 4 +PERF_PAPC_PASX_SECOND_DEAD = 5 +PERF_PAPC_PASX_VTX_KILL_DISCARD = 6 +PERF_PAPC_PASX_VTX_NAN_DISCARD = 7 +PERF_PAPC_PA_INPUT_PRIM = 8 +PERF_PAPC_PA_INPUT_NULL_PRIM = 9 +PERF_PAPC_PA_INPUT_EVENT_FLAG = 10 +PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11 +PERF_PAPC_PA_INPUT_END_OF_PACKET = 12 +PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 13 +PERF_PAPC_CLPR_CULL_PRIM = 14 +PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 15 +PERF_PAPC_CLPR_VV_CULL_PRIM = 16 +PERF_PAPC_CLPR_UCP_CULL_PRIM = 17 +PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 18 +PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 19 +PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 20 +PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 21 +PERF_PAPC_CLPR_VV_CLIP_PRIM = 22 +PERF_PAPC_CLPR_UCP_CLIP_PRIM = 23 +PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 24 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 25 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 26 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 27 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 28 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 29 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 30 +PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 31 +PERF_PAPC_CLPR_CLIP_PLANE_FAR = 32 +PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 33 +PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 34 +PERF_PAPC_CLPR_CLIP_PLANE_TOP = 35 +PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 36 +PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 37 +PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 38 +PERF_PAPC_CLSM_NULL_PRIM = 39 +PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 40 +PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 41 +PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 42 +PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 43 +PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 44 +PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 45 +PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 46 +PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 47 +PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 48 +PERF_PAPC_SU_INPUT_PRIM = 49 +PERF_PAPC_SU_INPUT_CLIP_PRIM = 50 +PERF_PAPC_SU_INPUT_NULL_PRIM = 51 +PERF_PAPC_SU_INPUT_PRIM_DUAL = 52 +PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 53 +PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 54 +PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 55 +PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 56 +PERF_PAPC_SU_POLYMODE_FACE_CULL = 57 +PERF_PAPC_SU_POLYMODE_BACK_CULL = 58 +PERF_PAPC_SU_POLYMODE_FRONT_CULL = 59 +PERF_PAPC_SU_POLYMODE_INVALID_FILL = 60 +PERF_PAPC_SU_OUTPUT_PRIM = 61 +PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 62 +PERF_PAPC_SU_OUTPUT_NULL_PRIM = 63 +PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 64 +PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 65 +PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 66 +PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 67 +PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 68 +PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 69 +PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 70 +PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 71 +PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 72 +PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 73 +PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 74 +PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 75 +PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 76 +PERF_PAPC_PASX_REQ_IDLE = 77 +PERF_PAPC_PASX_REQ_BUSY = 78 +PERF_PAPC_PASX_REQ_STALLED = 79 +PERF_PAPC_PASX_REC_IDLE = 80 +PERF_PAPC_PASX_REC_BUSY = 81 +PERF_PAPC_PASX_REC_STARVED_SX = 82 +PERF_PAPC_PASX_REC_STALLED = 83 +PERF_PAPC_PASX_REC_STALLED_POS_MEM = 84 +PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 85 +PERF_PAPC_CCGSM_IDLE = 86 +PERF_PAPC_CCGSM_BUSY = 87 +PERF_PAPC_CCGSM_STALLED = 88 +PERF_PAPC_CLPRIM_IDLE = 89 +PERF_PAPC_CLPRIM_BUSY = 90 +PERF_PAPC_CLPRIM_STALLED = 91 +PERF_PAPC_CLPRIM_STARVED_CCGSM = 92 +PERF_PAPC_CLIPSM_IDLE = 93 +PERF_PAPC_CLIPSM_BUSY = 94 +PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 95 +PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 96 +PERF_PAPC_CLIPSM_WAIT_CLIPGA = 97 +PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 98 +PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 99 +PERF_PAPC_CLIPGA_IDLE = 100 +PERF_PAPC_CLIPGA_BUSY = 101 +PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 102 +PERF_PAPC_CLIPGA_STALLED = 103 +PERF_PAPC_CLIP_IDLE = 104 +PERF_PAPC_CLIP_BUSY = 105 +PERF_PAPC_SU_IDLE = 106 +PERF_PAPC_SU_BUSY = 107 +PERF_PAPC_SU_STARVED_CLIP = 108 +PERF_PAPC_SU_STALLED_SC = 109 +PERF_PAPC_CL_DYN_SCLK_VLD = 110 +PERF_PAPC_SU_DYN_SCLK_VLD = 111 +PERF_PAPC_PA_REG_SCLK_VLD = 112 +PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 113 +PERF_PAPC_PASX_SE0_REQ = 114 +PERF_PAPC_PASX_SE1_REQ = 115 +PERF_PAPC_PASX_SE0_FIRST_VECTOR = 116 +PERF_PAPC_PASX_SE0_SECOND_VECTOR = 117 +PERF_PAPC_PASX_SE1_FIRST_VECTOR = 118 +PERF_PAPC_PASX_SE1_SECOND_VECTOR = 119 +PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 120 +PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 121 +PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 122 +PERF_PAPC_SU_SE0_OUTPUT_PRIM = 123 +PERF_PAPC_SU_SE1_OUTPUT_PRIM = 124 +PERF_PAPC_SU_SE01_OUTPUT_PRIM = 125 +PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 126 +PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 127 +PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 128 +PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 129 +PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 130 +PERF_PAPC_SU_SE0_STALLED_SC = 131 +PERF_PAPC_SU_SE1_STALLED_SC = 132 +PERF_PAPC_SU_SE01_STALLED_SC = 133 +PERF_PAPC_CLSM_CLIPPING_PRIM = 134 +PERF_PAPC_SU_CULLED_PRIM = 135 +PERF_PAPC_SU_OUTPUT_EOPG = 136 +PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 137 +PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 138 +PERF_PAPC_SU_SE2_OUTPUT_PRIM = 139 +PERF_PAPC_SU_SE3_OUTPUT_PRIM = 140 +PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 141 +PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 142 +PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 143 +PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 144 +PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 145 +PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 146 +PERF_PAPC_SU_SE0_OUTPUT_EOPG = 147 +PERF_PAPC_SU_SE1_OUTPUT_EOPG = 148 +PERF_PAPC_SU_SE2_OUTPUT_EOPG = 149 +PERF_PAPC_SU_SE3_OUTPUT_EOPG = 150 +PERF_PAPC_SU_SE2_STALLED_SC = 151 +PERF_PAPC_SU_SE3_STALLED_SC = 152 +SU_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SC_PERFCNT_SEL' +SC_PERFCNT_SEL__enumvalues = { + 0: 'SC_SRPS_WINDOW_VALID', + 1: 'SC_PSSW_WINDOW_VALID', + 2: 'SC_TPQZ_WINDOW_VALID', + 3: 'SC_QZQP_WINDOW_VALID', + 4: 'SC_TRPK_WINDOW_VALID', + 5: 'SC_SRPS_WINDOW_VALID_BUSY', + 6: 'SC_PSSW_WINDOW_VALID_BUSY', + 7: 'SC_TPQZ_WINDOW_VALID_BUSY', + 8: 'SC_QZQP_WINDOW_VALID_BUSY', + 9: 'SC_TRPK_WINDOW_VALID_BUSY', + 10: 'SC_STARVED_BY_PA', + 11: 'SC_STALLED_BY_PRIMFIFO', + 12: 'SC_STALLED_BY_DB_TILE', + 13: 'SC_STARVED_BY_DB_TILE', + 14: 'SC_STALLED_BY_TILEORDERFIFO', + 15: 'SC_STALLED_BY_TILEFIFO', + 16: 'SC_STALLED_BY_DB_QUAD', + 17: 'SC_STARVED_BY_DB_QUAD', + 18: 'SC_STALLED_BY_QUADFIFO', + 19: 'SC_STALLED_BY_BCI', + 20: 'SC_STALLED_BY_SPI', + 21: 'SC_SCISSOR_DISCARD', + 22: 'SC_BB_DISCARD', + 23: 'SC_SUPERTILE_COUNT', + 24: 'SC_SUPERTILE_PER_PRIM_H0', + 25: 'SC_SUPERTILE_PER_PRIM_H1', + 26: 'SC_SUPERTILE_PER_PRIM_H2', + 27: 'SC_SUPERTILE_PER_PRIM_H3', + 28: 'SC_SUPERTILE_PER_PRIM_H4', + 29: 'SC_SUPERTILE_PER_PRIM_H5', + 30: 'SC_SUPERTILE_PER_PRIM_H6', + 31: 'SC_SUPERTILE_PER_PRIM_H7', + 32: 'SC_SUPERTILE_PER_PRIM_H8', + 33: 'SC_SUPERTILE_PER_PRIM_H9', + 34: 'SC_SUPERTILE_PER_PRIM_H10', + 35: 'SC_SUPERTILE_PER_PRIM_H11', + 36: 'SC_SUPERTILE_PER_PRIM_H12', + 37: 'SC_SUPERTILE_PER_PRIM_H13', + 38: 'SC_SUPERTILE_PER_PRIM_H14', + 39: 'SC_SUPERTILE_PER_PRIM_H15', + 40: 'SC_SUPERTILE_PER_PRIM_H16', + 41: 'SC_TILE_PER_PRIM_H0', + 42: 'SC_TILE_PER_PRIM_H1', + 43: 'SC_TILE_PER_PRIM_H2', + 44: 'SC_TILE_PER_PRIM_H3', + 45: 'SC_TILE_PER_PRIM_H4', + 46: 'SC_TILE_PER_PRIM_H5', + 47: 'SC_TILE_PER_PRIM_H6', + 48: 'SC_TILE_PER_PRIM_H7', + 49: 'SC_TILE_PER_PRIM_H8', + 50: 'SC_TILE_PER_PRIM_H9', + 51: 'SC_TILE_PER_PRIM_H10', + 52: 'SC_TILE_PER_PRIM_H11', + 53: 'SC_TILE_PER_PRIM_H12', + 54: 'SC_TILE_PER_PRIM_H13', + 55: 'SC_TILE_PER_PRIM_H14', + 56: 'SC_TILE_PER_PRIM_H15', + 57: 'SC_TILE_PER_PRIM_H16', + 58: 'SC_TILE_PER_SUPERTILE_H0', + 59: 'SC_TILE_PER_SUPERTILE_H1', + 60: 'SC_TILE_PER_SUPERTILE_H2', + 61: 'SC_TILE_PER_SUPERTILE_H3', + 62: 'SC_TILE_PER_SUPERTILE_H4', + 63: 'SC_TILE_PER_SUPERTILE_H5', + 64: 'SC_TILE_PER_SUPERTILE_H6', + 65: 'SC_TILE_PER_SUPERTILE_H7', + 66: 'SC_TILE_PER_SUPERTILE_H8', + 67: 'SC_TILE_PER_SUPERTILE_H9', + 68: 'SC_TILE_PER_SUPERTILE_H10', + 69: 'SC_TILE_PER_SUPERTILE_H11', + 70: 'SC_TILE_PER_SUPERTILE_H12', + 71: 'SC_TILE_PER_SUPERTILE_H13', + 72: 'SC_TILE_PER_SUPERTILE_H14', + 73: 'SC_TILE_PER_SUPERTILE_H15', + 74: 'SC_TILE_PER_SUPERTILE_H16', + 75: 'SC_TILE_PICKED_H1', + 76: 'SC_TILE_PICKED_H2', + 77: 'SC_TILE_PICKED_H3', + 78: 'SC_TILE_PICKED_H4', + 79: 'SC_QZ0_MULTI_GPU_TILE_DISCARD', + 80: 'SC_QZ1_MULTI_GPU_TILE_DISCARD', + 81: 'SC_QZ2_MULTI_GPU_TILE_DISCARD', + 82: 'SC_QZ3_MULTI_GPU_TILE_DISCARD', + 83: 'SC_QZ0_TILE_COUNT', + 84: 'SC_QZ1_TILE_COUNT', + 85: 'SC_QZ2_TILE_COUNT', + 86: 'SC_QZ3_TILE_COUNT', + 87: 'SC_QZ0_TILE_COVERED_COUNT', + 88: 'SC_QZ1_TILE_COVERED_COUNT', + 89: 'SC_QZ2_TILE_COVERED_COUNT', + 90: 'SC_QZ3_TILE_COVERED_COUNT', + 91: 'SC_QZ0_TILE_NOT_COVERED_COUNT', + 92: 'SC_QZ1_TILE_NOT_COVERED_COUNT', + 93: 'SC_QZ2_TILE_NOT_COVERED_COUNT', + 94: 'SC_QZ3_TILE_NOT_COVERED_COUNT', + 95: 'SC_QZ0_QUAD_PER_TILE_H0', + 96: 'SC_QZ0_QUAD_PER_TILE_H1', + 97: 'SC_QZ0_QUAD_PER_TILE_H2', + 98: 'SC_QZ0_QUAD_PER_TILE_H3', + 99: 'SC_QZ0_QUAD_PER_TILE_H4', + 100: 'SC_QZ0_QUAD_PER_TILE_H5', + 101: 'SC_QZ0_QUAD_PER_TILE_H6', + 102: 'SC_QZ0_QUAD_PER_TILE_H7', + 103: 'SC_QZ0_QUAD_PER_TILE_H8', + 104: 'SC_QZ0_QUAD_PER_TILE_H9', + 105: 'SC_QZ0_QUAD_PER_TILE_H10', + 106: 'SC_QZ0_QUAD_PER_TILE_H11', + 107: 'SC_QZ0_QUAD_PER_TILE_H12', + 108: 'SC_QZ0_QUAD_PER_TILE_H13', + 109: 'SC_QZ0_QUAD_PER_TILE_H14', + 110: 'SC_QZ0_QUAD_PER_TILE_H15', + 111: 'SC_QZ0_QUAD_PER_TILE_H16', + 112: 'SC_QZ1_QUAD_PER_TILE_H0', + 113: 'SC_QZ1_QUAD_PER_TILE_H1', + 114: 'SC_QZ1_QUAD_PER_TILE_H2', + 115: 'SC_QZ1_QUAD_PER_TILE_H3', + 116: 'SC_QZ1_QUAD_PER_TILE_H4', + 117: 'SC_QZ1_QUAD_PER_TILE_H5', + 118: 'SC_QZ1_QUAD_PER_TILE_H6', + 119: 'SC_QZ1_QUAD_PER_TILE_H7', + 120: 'SC_QZ1_QUAD_PER_TILE_H8', + 121: 'SC_QZ1_QUAD_PER_TILE_H9', + 122: 'SC_QZ1_QUAD_PER_TILE_H10', + 123: 'SC_QZ1_QUAD_PER_TILE_H11', + 124: 'SC_QZ1_QUAD_PER_TILE_H12', + 125: 'SC_QZ1_QUAD_PER_TILE_H13', + 126: 'SC_QZ1_QUAD_PER_TILE_H14', + 127: 'SC_QZ1_QUAD_PER_TILE_H15', + 128: 'SC_QZ1_QUAD_PER_TILE_H16', + 129: 'SC_QZ2_QUAD_PER_TILE_H0', + 130: 'SC_QZ2_QUAD_PER_TILE_H1', + 131: 'SC_QZ2_QUAD_PER_TILE_H2', + 132: 'SC_QZ2_QUAD_PER_TILE_H3', + 133: 'SC_QZ2_QUAD_PER_TILE_H4', + 134: 'SC_QZ2_QUAD_PER_TILE_H5', + 135: 'SC_QZ2_QUAD_PER_TILE_H6', + 136: 'SC_QZ2_QUAD_PER_TILE_H7', + 137: 'SC_QZ2_QUAD_PER_TILE_H8', + 138: 'SC_QZ2_QUAD_PER_TILE_H9', + 139: 'SC_QZ2_QUAD_PER_TILE_H10', + 140: 'SC_QZ2_QUAD_PER_TILE_H11', + 141: 'SC_QZ2_QUAD_PER_TILE_H12', + 142: 'SC_QZ2_QUAD_PER_TILE_H13', + 143: 'SC_QZ2_QUAD_PER_TILE_H14', + 144: 'SC_QZ2_QUAD_PER_TILE_H15', + 145: 'SC_QZ2_QUAD_PER_TILE_H16', + 146: 'SC_QZ3_QUAD_PER_TILE_H0', + 147: 'SC_QZ3_QUAD_PER_TILE_H1', + 148: 'SC_QZ3_QUAD_PER_TILE_H2', + 149: 'SC_QZ3_QUAD_PER_TILE_H3', + 150: 'SC_QZ3_QUAD_PER_TILE_H4', + 151: 'SC_QZ3_QUAD_PER_TILE_H5', + 152: 'SC_QZ3_QUAD_PER_TILE_H6', + 153: 'SC_QZ3_QUAD_PER_TILE_H7', + 154: 'SC_QZ3_QUAD_PER_TILE_H8', + 155: 'SC_QZ3_QUAD_PER_TILE_H9', + 156: 'SC_QZ3_QUAD_PER_TILE_H10', + 157: 'SC_QZ3_QUAD_PER_TILE_H11', + 158: 'SC_QZ3_QUAD_PER_TILE_H12', + 159: 'SC_QZ3_QUAD_PER_TILE_H13', + 160: 'SC_QZ3_QUAD_PER_TILE_H14', + 161: 'SC_QZ3_QUAD_PER_TILE_H15', + 162: 'SC_QZ3_QUAD_PER_TILE_H16', + 163: 'SC_QZ0_QUAD_COUNT', + 164: 'SC_QZ1_QUAD_COUNT', + 165: 'SC_QZ2_QUAD_COUNT', + 166: 'SC_QZ3_QUAD_COUNT', + 167: 'SC_P0_HIZ_TILE_COUNT', + 168: 'SC_P1_HIZ_TILE_COUNT', + 169: 'SC_P2_HIZ_TILE_COUNT', + 170: 'SC_P3_HIZ_TILE_COUNT', + 171: 'SC_P0_HIZ_QUAD_PER_TILE_H0', + 172: 'SC_P0_HIZ_QUAD_PER_TILE_H1', + 173: 'SC_P0_HIZ_QUAD_PER_TILE_H2', + 174: 'SC_P0_HIZ_QUAD_PER_TILE_H3', + 175: 'SC_P0_HIZ_QUAD_PER_TILE_H4', + 176: 'SC_P0_HIZ_QUAD_PER_TILE_H5', + 177: 'SC_P0_HIZ_QUAD_PER_TILE_H6', + 178: 'SC_P0_HIZ_QUAD_PER_TILE_H7', + 179: 'SC_P0_HIZ_QUAD_PER_TILE_H8', + 180: 'SC_P0_HIZ_QUAD_PER_TILE_H9', + 181: 'SC_P0_HIZ_QUAD_PER_TILE_H10', + 182: 'SC_P0_HIZ_QUAD_PER_TILE_H11', + 183: 'SC_P0_HIZ_QUAD_PER_TILE_H12', + 184: 'SC_P0_HIZ_QUAD_PER_TILE_H13', + 185: 'SC_P0_HIZ_QUAD_PER_TILE_H14', + 186: 'SC_P0_HIZ_QUAD_PER_TILE_H15', + 187: 'SC_P0_HIZ_QUAD_PER_TILE_H16', + 188: 'SC_P1_HIZ_QUAD_PER_TILE_H0', + 189: 'SC_P1_HIZ_QUAD_PER_TILE_H1', + 190: 'SC_P1_HIZ_QUAD_PER_TILE_H2', + 191: 'SC_P1_HIZ_QUAD_PER_TILE_H3', + 192: 'SC_P1_HIZ_QUAD_PER_TILE_H4', + 193: 'SC_P1_HIZ_QUAD_PER_TILE_H5', + 194: 'SC_P1_HIZ_QUAD_PER_TILE_H6', + 195: 'SC_P1_HIZ_QUAD_PER_TILE_H7', + 196: 'SC_P1_HIZ_QUAD_PER_TILE_H8', + 197: 'SC_P1_HIZ_QUAD_PER_TILE_H9', + 198: 'SC_P1_HIZ_QUAD_PER_TILE_H10', + 199: 'SC_P1_HIZ_QUAD_PER_TILE_H11', + 200: 'SC_P1_HIZ_QUAD_PER_TILE_H12', + 201: 'SC_P1_HIZ_QUAD_PER_TILE_H13', + 202: 'SC_P1_HIZ_QUAD_PER_TILE_H14', + 203: 'SC_P1_HIZ_QUAD_PER_TILE_H15', + 204: 'SC_P1_HIZ_QUAD_PER_TILE_H16', + 205: 'SC_P2_HIZ_QUAD_PER_TILE_H0', + 206: 'SC_P2_HIZ_QUAD_PER_TILE_H1', + 207: 'SC_P2_HIZ_QUAD_PER_TILE_H2', + 208: 'SC_P2_HIZ_QUAD_PER_TILE_H3', + 209: 'SC_P2_HIZ_QUAD_PER_TILE_H4', + 210: 'SC_P2_HIZ_QUAD_PER_TILE_H5', + 211: 'SC_P2_HIZ_QUAD_PER_TILE_H6', + 212: 'SC_P2_HIZ_QUAD_PER_TILE_H7', + 213: 'SC_P2_HIZ_QUAD_PER_TILE_H8', + 214: 'SC_P2_HIZ_QUAD_PER_TILE_H9', + 215: 'SC_P2_HIZ_QUAD_PER_TILE_H10', + 216: 'SC_P2_HIZ_QUAD_PER_TILE_H11', + 217: 'SC_P2_HIZ_QUAD_PER_TILE_H12', + 218: 'SC_P2_HIZ_QUAD_PER_TILE_H13', + 219: 'SC_P2_HIZ_QUAD_PER_TILE_H14', + 220: 'SC_P2_HIZ_QUAD_PER_TILE_H15', + 221: 'SC_P2_HIZ_QUAD_PER_TILE_H16', + 222: 'SC_P3_HIZ_QUAD_PER_TILE_H0', + 223: 'SC_P3_HIZ_QUAD_PER_TILE_H1', + 224: 'SC_P3_HIZ_QUAD_PER_TILE_H2', + 225: 'SC_P3_HIZ_QUAD_PER_TILE_H3', + 226: 'SC_P3_HIZ_QUAD_PER_TILE_H4', + 227: 'SC_P3_HIZ_QUAD_PER_TILE_H5', + 228: 'SC_P3_HIZ_QUAD_PER_TILE_H6', + 229: 'SC_P3_HIZ_QUAD_PER_TILE_H7', + 230: 'SC_P3_HIZ_QUAD_PER_TILE_H8', + 231: 'SC_P3_HIZ_QUAD_PER_TILE_H9', + 232: 'SC_P3_HIZ_QUAD_PER_TILE_H10', + 233: 'SC_P3_HIZ_QUAD_PER_TILE_H11', + 234: 'SC_P3_HIZ_QUAD_PER_TILE_H12', + 235: 'SC_P3_HIZ_QUAD_PER_TILE_H13', + 236: 'SC_P3_HIZ_QUAD_PER_TILE_H14', + 237: 'SC_P3_HIZ_QUAD_PER_TILE_H15', + 238: 'SC_P3_HIZ_QUAD_PER_TILE_H16', + 239: 'SC_P0_HIZ_QUAD_COUNT', + 240: 'SC_P1_HIZ_QUAD_COUNT', + 241: 'SC_P2_HIZ_QUAD_COUNT', + 242: 'SC_P3_HIZ_QUAD_COUNT', + 243: 'SC_P0_DETAIL_QUAD_COUNT', + 244: 'SC_P1_DETAIL_QUAD_COUNT', + 245: 'SC_P2_DETAIL_QUAD_COUNT', + 246: 'SC_P3_DETAIL_QUAD_COUNT', + 247: 'SC_P0_DETAIL_QUAD_WITH_1_PIX', + 248: 'SC_P0_DETAIL_QUAD_WITH_2_PIX', + 249: 'SC_P0_DETAIL_QUAD_WITH_3_PIX', + 250: 'SC_P0_DETAIL_QUAD_WITH_4_PIX', + 251: 'SC_P1_DETAIL_QUAD_WITH_1_PIX', + 252: 'SC_P1_DETAIL_QUAD_WITH_2_PIX', + 253: 'SC_P1_DETAIL_QUAD_WITH_3_PIX', + 254: 'SC_P1_DETAIL_QUAD_WITH_4_PIX', + 255: 'SC_P2_DETAIL_QUAD_WITH_1_PIX', + 256: 'SC_P2_DETAIL_QUAD_WITH_2_PIX', + 257: 'SC_P2_DETAIL_QUAD_WITH_3_PIX', + 258: 'SC_P2_DETAIL_QUAD_WITH_4_PIX', + 259: 'SC_P3_DETAIL_QUAD_WITH_1_PIX', + 260: 'SC_P3_DETAIL_QUAD_WITH_2_PIX', + 261: 'SC_P3_DETAIL_QUAD_WITH_3_PIX', + 262: 'SC_P3_DETAIL_QUAD_WITH_4_PIX', + 263: 'SC_EARLYZ_QUAD_COUNT', + 264: 'SC_EARLYZ_QUAD_WITH_1_PIX', + 265: 'SC_EARLYZ_QUAD_WITH_2_PIX', + 266: 'SC_EARLYZ_QUAD_WITH_3_PIX', + 267: 'SC_EARLYZ_QUAD_WITH_4_PIX', + 268: 'SC_PKR_QUAD_PER_ROW_H1', + 269: 'SC_PKR_QUAD_PER_ROW_H2', + 270: 'SC_PKR_4X2_QUAD_SPLIT', + 271: 'SC_PKR_4X2_FILL_QUAD', + 272: 'SC_PKR_END_OF_VECTOR', + 273: 'SC_PKR_CONTROL_XFER', + 274: 'SC_PKR_DBHANG_FORCE_EOV', + 275: 'SC_REG_SCLK_BUSY', + 276: 'SC_GRP0_DYN_SCLK_BUSY', + 277: 'SC_GRP1_DYN_SCLK_BUSY', + 278: 'SC_GRP2_DYN_SCLK_BUSY', + 279: 'SC_GRP3_DYN_SCLK_BUSY', + 280: 'SC_GRP4_DYN_SCLK_BUSY', + 281: 'SC_PA0_SC_DATA_FIFO_RD', + 282: 'SC_PA0_SC_DATA_FIFO_WE', + 283: 'SC_PA1_SC_DATA_FIFO_RD', + 284: 'SC_PA1_SC_DATA_FIFO_WE', + 285: 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 286: 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', + 287: 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 288: 'SC_PS_ARB_STALLED_FROM_BELOW', + 289: 'SC_PS_ARB_STARVED_FROM_ABOVE', + 290: 'SC_PS_ARB_SC_BUSY', + 291: 'SC_PS_ARB_PA_SC_BUSY', + 292: 'SC_PA2_SC_DATA_FIFO_RD', + 293: 'SC_PA2_SC_DATA_FIFO_WE', + 294: 'SC_PA3_SC_DATA_FIFO_RD', + 295: 'SC_PA3_SC_DATA_FIFO_WE', + 296: 'SC_PA_SC_DEALLOC_0_0_WE', + 297: 'SC_PA_SC_DEALLOC_0_1_WE', + 298: 'SC_PA_SC_DEALLOC_1_0_WE', + 299: 'SC_PA_SC_DEALLOC_1_1_WE', + 300: 'SC_PA_SC_DEALLOC_2_0_WE', + 301: 'SC_PA_SC_DEALLOC_2_1_WE', + 302: 'SC_PA_SC_DEALLOC_3_0_WE', + 303: 'SC_PA_SC_DEALLOC_3_1_WE', + 304: 'SC_PA0_SC_EOP_WE', + 305: 'SC_PA0_SC_EOPG_WE', + 306: 'SC_PA0_SC_EVENT_WE', + 307: 'SC_PA1_SC_EOP_WE', + 308: 'SC_PA1_SC_EOPG_WE', + 309: 'SC_PA1_SC_EVENT_WE', + 310: 'SC_PA2_SC_EOP_WE', + 311: 'SC_PA2_SC_EOPG_WE', + 312: 'SC_PA2_SC_EVENT_WE', + 313: 'SC_PA3_SC_EOP_WE', + 314: 'SC_PA3_SC_EOPG_WE', + 315: 'SC_PA3_SC_EVENT_WE', + 316: 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', + 317: 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', + 318: 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', + 319: 'SC_PS_ARB_EOP_POP_SYNC_POP', + 320: 'SC_PS_ARB_EVENT_SYNC_POP', + 321: 'SC_SC_PS_ENG_MULTICYCLE_BUBBLE', + 322: 'SC_PA0_SC_FPOV_WE', + 323: 'SC_PA1_SC_FPOV_WE', + 324: 'SC_PA2_SC_FPOV_WE', + 325: 'SC_PA3_SC_FPOV_WE', + 326: 'SC_PA0_SC_LPOV_WE', + 327: 'SC_PA1_SC_LPOV_WE', + 328: 'SC_PA2_SC_LPOV_WE', + 329: 'SC_PA3_SC_LPOV_WE', + 330: 'SC_SC_SPI_DEALLOC_0_0', + 331: 'SC_SC_SPI_DEALLOC_0_1', + 332: 'SC_SC_SPI_DEALLOC_0_2', + 333: 'SC_SC_SPI_DEALLOC_1_0', + 334: 'SC_SC_SPI_DEALLOC_1_1', + 335: 'SC_SC_SPI_DEALLOC_1_2', + 336: 'SC_SC_SPI_DEALLOC_2_0', + 337: 'SC_SC_SPI_DEALLOC_2_1', + 338: 'SC_SC_SPI_DEALLOC_2_2', + 339: 'SC_SC_SPI_DEALLOC_3_0', + 340: 'SC_SC_SPI_DEALLOC_3_1', + 341: 'SC_SC_SPI_DEALLOC_3_2', + 342: 'SC_SC_SPI_FPOV_0', + 343: 'SC_SC_SPI_FPOV_1', + 344: 'SC_SC_SPI_FPOV_2', + 345: 'SC_SC_SPI_FPOV_3', + 346: 'SC_SC_SPI_EVENT', + 347: 'SC_PS_TS_EVENT_FIFO_PUSH', + 348: 'SC_PS_TS_EVENT_FIFO_POP', + 349: 'SC_PS_CTX_DONE_FIFO_PUSH', + 350: 'SC_PS_CTX_DONE_FIFO_POP', + 351: 'SC_MULTICYCLE_BUBBLE_FREEZE', + 352: 'SC_EOP_SYNC_WINDOW', + 353: 'SC_PA0_SC_NULL_WE', + 354: 'SC_PA0_SC_NULL_DEALLOC_WE', + 355: 'SC_PA0_SC_DATA_FIFO_EOPG_RD', + 356: 'SC_PA0_SC_DATA_FIFO_EOP_RD', + 357: 'SC_PA0_SC_DEALLOC_0_RD', + 358: 'SC_PA0_SC_DEALLOC_1_RD', + 359: 'SC_PA1_SC_DATA_FIFO_EOPG_RD', + 360: 'SC_PA1_SC_DATA_FIFO_EOP_RD', + 361: 'SC_PA1_SC_DEALLOC_0_RD', + 362: 'SC_PA1_SC_DEALLOC_1_RD', + 363: 'SC_PA1_SC_NULL_WE', + 364: 'SC_PA1_SC_NULL_DEALLOC_WE', + 365: 'SC_PA2_SC_DATA_FIFO_EOPG_RD', + 366: 'SC_PA2_SC_DATA_FIFO_EOP_RD', + 367: 'SC_PA2_SC_DEALLOC_0_RD', + 368: 'SC_PA2_SC_DEALLOC_1_RD', + 369: 'SC_PA2_SC_NULL_WE', + 370: 'SC_PA2_SC_NULL_DEALLOC_WE', + 371: 'SC_PA3_SC_DATA_FIFO_EOPG_RD', + 372: 'SC_PA3_SC_DATA_FIFO_EOP_RD', + 373: 'SC_PA3_SC_DEALLOC_0_RD', + 374: 'SC_PA3_SC_DEALLOC_1_RD', + 375: 'SC_PA3_SC_NULL_WE', + 376: 'SC_PA3_SC_NULL_DEALLOC_WE', + 377: 'SC_PS_PA0_SC_FIFO_EMPTY', + 378: 'SC_PS_PA0_SC_FIFO_FULL', + 379: 'SC_PA0_PS_DATA_SEND', + 380: 'SC_PS_PA1_SC_FIFO_EMPTY', + 381: 'SC_PS_PA1_SC_FIFO_FULL', + 382: 'SC_PA1_PS_DATA_SEND', + 383: 'SC_PS_PA2_SC_FIFO_EMPTY', + 384: 'SC_PS_PA2_SC_FIFO_FULL', + 385: 'SC_PA2_PS_DATA_SEND', + 386: 'SC_PS_PA3_SC_FIFO_EMPTY', + 387: 'SC_PS_PA3_SC_FIFO_FULL', + 388: 'SC_PA3_PS_DATA_SEND', + 389: 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', + 390: 'SC_BUSY_CNT_NOT_ZERO', + 391: 'SC_BM_BUSY', + 392: 'SC_BACKEND_BUSY', + 393: 'SC_SCF_SCB_INTERFACE_BUSY', + 394: 'SC_SCB_BUSY', + 395: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', + 396: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', + 397: 'SC_PBB_BIN_HIST_NUM_PRIMS', + 398: 'SC_PBB_BATCH_HIST_NUM_PRIMS', + 399: 'SC_PBB_BIN_HIST_NUM_CONTEXTS', + 400: 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', + 401: 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', + 402: 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', + 403: 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', + 404: 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', + 405: 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', + 406: 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', + 407: 'SC_PBB_BUSY', + 408: 'SC_PBB_BUSY_AND_RTR', + 409: 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', + 410: 'SC_PBB_NUM_BINS', + 411: 'SC_PBB_END_OF_BIN', + 412: 'SC_PBB_END_OF_BATCH', + 413: 'SC_PBB_PRIMBIN_PROCESSED', + 414: 'SC_PBB_PRIM_ADDED_TO_BATCH', + 415: 'SC_PBB_NONBINNED_PRIM', + 416: 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', + 417: 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', + 418: 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', + 419: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', + 420: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', + 421: 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', + 422: 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', + 423: 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', + 424: 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', + 425: 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', + 426: 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', + 427: 'SC_POPS_INTRA_WAVE_OVERLAPS', + 428: 'SC_POPS_FORCE_EOV', + 429: 'SC_PKR_QUAD_OVERLAP_NOT_FOUND_IN_WAVE_TABLE', + 430: 'SC_PKR_QUAD_OVERLAP_FOUND_IN_WAVE_TABLE', +} +SC_SRPS_WINDOW_VALID = 0 +SC_PSSW_WINDOW_VALID = 1 +SC_TPQZ_WINDOW_VALID = 2 +SC_QZQP_WINDOW_VALID = 3 +SC_TRPK_WINDOW_VALID = 4 +SC_SRPS_WINDOW_VALID_BUSY = 5 +SC_PSSW_WINDOW_VALID_BUSY = 6 +SC_TPQZ_WINDOW_VALID_BUSY = 7 +SC_QZQP_WINDOW_VALID_BUSY = 8 +SC_TRPK_WINDOW_VALID_BUSY = 9 +SC_STARVED_BY_PA = 10 +SC_STALLED_BY_PRIMFIFO = 11 +SC_STALLED_BY_DB_TILE = 12 +SC_STARVED_BY_DB_TILE = 13 +SC_STALLED_BY_TILEORDERFIFO = 14 +SC_STALLED_BY_TILEFIFO = 15 +SC_STALLED_BY_DB_QUAD = 16 +SC_STARVED_BY_DB_QUAD = 17 +SC_STALLED_BY_QUADFIFO = 18 +SC_STALLED_BY_BCI = 19 +SC_STALLED_BY_SPI = 20 +SC_SCISSOR_DISCARD = 21 +SC_BB_DISCARD = 22 +SC_SUPERTILE_COUNT = 23 +SC_SUPERTILE_PER_PRIM_H0 = 24 +SC_SUPERTILE_PER_PRIM_H1 = 25 +SC_SUPERTILE_PER_PRIM_H2 = 26 +SC_SUPERTILE_PER_PRIM_H3 = 27 +SC_SUPERTILE_PER_PRIM_H4 = 28 +SC_SUPERTILE_PER_PRIM_H5 = 29 +SC_SUPERTILE_PER_PRIM_H6 = 30 +SC_SUPERTILE_PER_PRIM_H7 = 31 +SC_SUPERTILE_PER_PRIM_H8 = 32 +SC_SUPERTILE_PER_PRIM_H9 = 33 +SC_SUPERTILE_PER_PRIM_H10 = 34 +SC_SUPERTILE_PER_PRIM_H11 = 35 +SC_SUPERTILE_PER_PRIM_H12 = 36 +SC_SUPERTILE_PER_PRIM_H13 = 37 +SC_SUPERTILE_PER_PRIM_H14 = 38 +SC_SUPERTILE_PER_PRIM_H15 = 39 +SC_SUPERTILE_PER_PRIM_H16 = 40 +SC_TILE_PER_PRIM_H0 = 41 +SC_TILE_PER_PRIM_H1 = 42 +SC_TILE_PER_PRIM_H2 = 43 +SC_TILE_PER_PRIM_H3 = 44 +SC_TILE_PER_PRIM_H4 = 45 +SC_TILE_PER_PRIM_H5 = 46 +SC_TILE_PER_PRIM_H6 = 47 +SC_TILE_PER_PRIM_H7 = 48 +SC_TILE_PER_PRIM_H8 = 49 +SC_TILE_PER_PRIM_H9 = 50 +SC_TILE_PER_PRIM_H10 = 51 +SC_TILE_PER_PRIM_H11 = 52 +SC_TILE_PER_PRIM_H12 = 53 +SC_TILE_PER_PRIM_H13 = 54 +SC_TILE_PER_PRIM_H14 = 55 +SC_TILE_PER_PRIM_H15 = 56 +SC_TILE_PER_PRIM_H16 = 57 +SC_TILE_PER_SUPERTILE_H0 = 58 +SC_TILE_PER_SUPERTILE_H1 = 59 +SC_TILE_PER_SUPERTILE_H2 = 60 +SC_TILE_PER_SUPERTILE_H3 = 61 +SC_TILE_PER_SUPERTILE_H4 = 62 +SC_TILE_PER_SUPERTILE_H5 = 63 +SC_TILE_PER_SUPERTILE_H6 = 64 +SC_TILE_PER_SUPERTILE_H7 = 65 +SC_TILE_PER_SUPERTILE_H8 = 66 +SC_TILE_PER_SUPERTILE_H9 = 67 +SC_TILE_PER_SUPERTILE_H10 = 68 +SC_TILE_PER_SUPERTILE_H11 = 69 +SC_TILE_PER_SUPERTILE_H12 = 70 +SC_TILE_PER_SUPERTILE_H13 = 71 +SC_TILE_PER_SUPERTILE_H14 = 72 +SC_TILE_PER_SUPERTILE_H15 = 73 +SC_TILE_PER_SUPERTILE_H16 = 74 +SC_TILE_PICKED_H1 = 75 +SC_TILE_PICKED_H2 = 76 +SC_TILE_PICKED_H3 = 77 +SC_TILE_PICKED_H4 = 78 +SC_QZ0_MULTI_GPU_TILE_DISCARD = 79 +SC_QZ1_MULTI_GPU_TILE_DISCARD = 80 +SC_QZ2_MULTI_GPU_TILE_DISCARD = 81 +SC_QZ3_MULTI_GPU_TILE_DISCARD = 82 +SC_QZ0_TILE_COUNT = 83 +SC_QZ1_TILE_COUNT = 84 +SC_QZ2_TILE_COUNT = 85 +SC_QZ3_TILE_COUNT = 86 +SC_QZ0_TILE_COVERED_COUNT = 87 +SC_QZ1_TILE_COVERED_COUNT = 88 +SC_QZ2_TILE_COVERED_COUNT = 89 +SC_QZ3_TILE_COVERED_COUNT = 90 +SC_QZ0_TILE_NOT_COVERED_COUNT = 91 +SC_QZ1_TILE_NOT_COVERED_COUNT = 92 +SC_QZ2_TILE_NOT_COVERED_COUNT = 93 +SC_QZ3_TILE_NOT_COVERED_COUNT = 94 +SC_QZ0_QUAD_PER_TILE_H0 = 95 +SC_QZ0_QUAD_PER_TILE_H1 = 96 +SC_QZ0_QUAD_PER_TILE_H2 = 97 +SC_QZ0_QUAD_PER_TILE_H3 = 98 +SC_QZ0_QUAD_PER_TILE_H4 = 99 +SC_QZ0_QUAD_PER_TILE_H5 = 100 +SC_QZ0_QUAD_PER_TILE_H6 = 101 +SC_QZ0_QUAD_PER_TILE_H7 = 102 +SC_QZ0_QUAD_PER_TILE_H8 = 103 +SC_QZ0_QUAD_PER_TILE_H9 = 104 +SC_QZ0_QUAD_PER_TILE_H10 = 105 +SC_QZ0_QUAD_PER_TILE_H11 = 106 +SC_QZ0_QUAD_PER_TILE_H12 = 107 +SC_QZ0_QUAD_PER_TILE_H13 = 108 +SC_QZ0_QUAD_PER_TILE_H14 = 109 +SC_QZ0_QUAD_PER_TILE_H15 = 110 +SC_QZ0_QUAD_PER_TILE_H16 = 111 +SC_QZ1_QUAD_PER_TILE_H0 = 112 +SC_QZ1_QUAD_PER_TILE_H1 = 113 +SC_QZ1_QUAD_PER_TILE_H2 = 114 +SC_QZ1_QUAD_PER_TILE_H3 = 115 +SC_QZ1_QUAD_PER_TILE_H4 = 116 +SC_QZ1_QUAD_PER_TILE_H5 = 117 +SC_QZ1_QUAD_PER_TILE_H6 = 118 +SC_QZ1_QUAD_PER_TILE_H7 = 119 +SC_QZ1_QUAD_PER_TILE_H8 = 120 +SC_QZ1_QUAD_PER_TILE_H9 = 121 +SC_QZ1_QUAD_PER_TILE_H10 = 122 +SC_QZ1_QUAD_PER_TILE_H11 = 123 +SC_QZ1_QUAD_PER_TILE_H12 = 124 +SC_QZ1_QUAD_PER_TILE_H13 = 125 +SC_QZ1_QUAD_PER_TILE_H14 = 126 +SC_QZ1_QUAD_PER_TILE_H15 = 127 +SC_QZ1_QUAD_PER_TILE_H16 = 128 +SC_QZ2_QUAD_PER_TILE_H0 = 129 +SC_QZ2_QUAD_PER_TILE_H1 = 130 +SC_QZ2_QUAD_PER_TILE_H2 = 131 +SC_QZ2_QUAD_PER_TILE_H3 = 132 +SC_QZ2_QUAD_PER_TILE_H4 = 133 +SC_QZ2_QUAD_PER_TILE_H5 = 134 +SC_QZ2_QUAD_PER_TILE_H6 = 135 +SC_QZ2_QUAD_PER_TILE_H7 = 136 +SC_QZ2_QUAD_PER_TILE_H8 = 137 +SC_QZ2_QUAD_PER_TILE_H9 = 138 +SC_QZ2_QUAD_PER_TILE_H10 = 139 +SC_QZ2_QUAD_PER_TILE_H11 = 140 +SC_QZ2_QUAD_PER_TILE_H12 = 141 +SC_QZ2_QUAD_PER_TILE_H13 = 142 +SC_QZ2_QUAD_PER_TILE_H14 = 143 +SC_QZ2_QUAD_PER_TILE_H15 = 144 +SC_QZ2_QUAD_PER_TILE_H16 = 145 +SC_QZ3_QUAD_PER_TILE_H0 = 146 +SC_QZ3_QUAD_PER_TILE_H1 = 147 +SC_QZ3_QUAD_PER_TILE_H2 = 148 +SC_QZ3_QUAD_PER_TILE_H3 = 149 +SC_QZ3_QUAD_PER_TILE_H4 = 150 +SC_QZ3_QUAD_PER_TILE_H5 = 151 +SC_QZ3_QUAD_PER_TILE_H6 = 152 +SC_QZ3_QUAD_PER_TILE_H7 = 153 +SC_QZ3_QUAD_PER_TILE_H8 = 154 +SC_QZ3_QUAD_PER_TILE_H9 = 155 +SC_QZ3_QUAD_PER_TILE_H10 = 156 +SC_QZ3_QUAD_PER_TILE_H11 = 157 +SC_QZ3_QUAD_PER_TILE_H12 = 158 +SC_QZ3_QUAD_PER_TILE_H13 = 159 +SC_QZ3_QUAD_PER_TILE_H14 = 160 +SC_QZ3_QUAD_PER_TILE_H15 = 161 +SC_QZ3_QUAD_PER_TILE_H16 = 162 +SC_QZ0_QUAD_COUNT = 163 +SC_QZ1_QUAD_COUNT = 164 +SC_QZ2_QUAD_COUNT = 165 +SC_QZ3_QUAD_COUNT = 166 +SC_P0_HIZ_TILE_COUNT = 167 +SC_P1_HIZ_TILE_COUNT = 168 +SC_P2_HIZ_TILE_COUNT = 169 +SC_P3_HIZ_TILE_COUNT = 170 +SC_P0_HIZ_QUAD_PER_TILE_H0 = 171 +SC_P0_HIZ_QUAD_PER_TILE_H1 = 172 +SC_P0_HIZ_QUAD_PER_TILE_H2 = 173 +SC_P0_HIZ_QUAD_PER_TILE_H3 = 174 +SC_P0_HIZ_QUAD_PER_TILE_H4 = 175 +SC_P0_HIZ_QUAD_PER_TILE_H5 = 176 +SC_P0_HIZ_QUAD_PER_TILE_H6 = 177 +SC_P0_HIZ_QUAD_PER_TILE_H7 = 178 +SC_P0_HIZ_QUAD_PER_TILE_H8 = 179 +SC_P0_HIZ_QUAD_PER_TILE_H9 = 180 +SC_P0_HIZ_QUAD_PER_TILE_H10 = 181 +SC_P0_HIZ_QUAD_PER_TILE_H11 = 182 +SC_P0_HIZ_QUAD_PER_TILE_H12 = 183 +SC_P0_HIZ_QUAD_PER_TILE_H13 = 184 +SC_P0_HIZ_QUAD_PER_TILE_H14 = 185 +SC_P0_HIZ_QUAD_PER_TILE_H15 = 186 +SC_P0_HIZ_QUAD_PER_TILE_H16 = 187 +SC_P1_HIZ_QUAD_PER_TILE_H0 = 188 +SC_P1_HIZ_QUAD_PER_TILE_H1 = 189 +SC_P1_HIZ_QUAD_PER_TILE_H2 = 190 +SC_P1_HIZ_QUAD_PER_TILE_H3 = 191 +SC_P1_HIZ_QUAD_PER_TILE_H4 = 192 +SC_P1_HIZ_QUAD_PER_TILE_H5 = 193 +SC_P1_HIZ_QUAD_PER_TILE_H6 = 194 +SC_P1_HIZ_QUAD_PER_TILE_H7 = 195 +SC_P1_HIZ_QUAD_PER_TILE_H8 = 196 +SC_P1_HIZ_QUAD_PER_TILE_H9 = 197 +SC_P1_HIZ_QUAD_PER_TILE_H10 = 198 +SC_P1_HIZ_QUAD_PER_TILE_H11 = 199 +SC_P1_HIZ_QUAD_PER_TILE_H12 = 200 +SC_P1_HIZ_QUAD_PER_TILE_H13 = 201 +SC_P1_HIZ_QUAD_PER_TILE_H14 = 202 +SC_P1_HIZ_QUAD_PER_TILE_H15 = 203 +SC_P1_HIZ_QUAD_PER_TILE_H16 = 204 +SC_P2_HIZ_QUAD_PER_TILE_H0 = 205 +SC_P2_HIZ_QUAD_PER_TILE_H1 = 206 +SC_P2_HIZ_QUAD_PER_TILE_H2 = 207 +SC_P2_HIZ_QUAD_PER_TILE_H3 = 208 +SC_P2_HIZ_QUAD_PER_TILE_H4 = 209 +SC_P2_HIZ_QUAD_PER_TILE_H5 = 210 +SC_P2_HIZ_QUAD_PER_TILE_H6 = 211 +SC_P2_HIZ_QUAD_PER_TILE_H7 = 212 +SC_P2_HIZ_QUAD_PER_TILE_H8 = 213 +SC_P2_HIZ_QUAD_PER_TILE_H9 = 214 +SC_P2_HIZ_QUAD_PER_TILE_H10 = 215 +SC_P2_HIZ_QUAD_PER_TILE_H11 = 216 +SC_P2_HIZ_QUAD_PER_TILE_H12 = 217 +SC_P2_HIZ_QUAD_PER_TILE_H13 = 218 +SC_P2_HIZ_QUAD_PER_TILE_H14 = 219 +SC_P2_HIZ_QUAD_PER_TILE_H15 = 220 +SC_P2_HIZ_QUAD_PER_TILE_H16 = 221 +SC_P3_HIZ_QUAD_PER_TILE_H0 = 222 +SC_P3_HIZ_QUAD_PER_TILE_H1 = 223 +SC_P3_HIZ_QUAD_PER_TILE_H2 = 224 +SC_P3_HIZ_QUAD_PER_TILE_H3 = 225 +SC_P3_HIZ_QUAD_PER_TILE_H4 = 226 +SC_P3_HIZ_QUAD_PER_TILE_H5 = 227 +SC_P3_HIZ_QUAD_PER_TILE_H6 = 228 +SC_P3_HIZ_QUAD_PER_TILE_H7 = 229 +SC_P3_HIZ_QUAD_PER_TILE_H8 = 230 +SC_P3_HIZ_QUAD_PER_TILE_H9 = 231 +SC_P3_HIZ_QUAD_PER_TILE_H10 = 232 +SC_P3_HIZ_QUAD_PER_TILE_H11 = 233 +SC_P3_HIZ_QUAD_PER_TILE_H12 = 234 +SC_P3_HIZ_QUAD_PER_TILE_H13 = 235 +SC_P3_HIZ_QUAD_PER_TILE_H14 = 236 +SC_P3_HIZ_QUAD_PER_TILE_H15 = 237 +SC_P3_HIZ_QUAD_PER_TILE_H16 = 238 +SC_P0_HIZ_QUAD_COUNT = 239 +SC_P1_HIZ_QUAD_COUNT = 240 +SC_P2_HIZ_QUAD_COUNT = 241 +SC_P3_HIZ_QUAD_COUNT = 242 +SC_P0_DETAIL_QUAD_COUNT = 243 +SC_P1_DETAIL_QUAD_COUNT = 244 +SC_P2_DETAIL_QUAD_COUNT = 245 +SC_P3_DETAIL_QUAD_COUNT = 246 +SC_P0_DETAIL_QUAD_WITH_1_PIX = 247 +SC_P0_DETAIL_QUAD_WITH_2_PIX = 248 +SC_P0_DETAIL_QUAD_WITH_3_PIX = 249 +SC_P0_DETAIL_QUAD_WITH_4_PIX = 250 +SC_P1_DETAIL_QUAD_WITH_1_PIX = 251 +SC_P1_DETAIL_QUAD_WITH_2_PIX = 252 +SC_P1_DETAIL_QUAD_WITH_3_PIX = 253 +SC_P1_DETAIL_QUAD_WITH_4_PIX = 254 +SC_P2_DETAIL_QUAD_WITH_1_PIX = 255 +SC_P2_DETAIL_QUAD_WITH_2_PIX = 256 +SC_P2_DETAIL_QUAD_WITH_3_PIX = 257 +SC_P2_DETAIL_QUAD_WITH_4_PIX = 258 +SC_P3_DETAIL_QUAD_WITH_1_PIX = 259 +SC_P3_DETAIL_QUAD_WITH_2_PIX = 260 +SC_P3_DETAIL_QUAD_WITH_3_PIX = 261 +SC_P3_DETAIL_QUAD_WITH_4_PIX = 262 +SC_EARLYZ_QUAD_COUNT = 263 +SC_EARLYZ_QUAD_WITH_1_PIX = 264 +SC_EARLYZ_QUAD_WITH_2_PIX = 265 +SC_EARLYZ_QUAD_WITH_3_PIX = 266 +SC_EARLYZ_QUAD_WITH_4_PIX = 267 +SC_PKR_QUAD_PER_ROW_H1 = 268 +SC_PKR_QUAD_PER_ROW_H2 = 269 +SC_PKR_4X2_QUAD_SPLIT = 270 +SC_PKR_4X2_FILL_QUAD = 271 +SC_PKR_END_OF_VECTOR = 272 +SC_PKR_CONTROL_XFER = 273 +SC_PKR_DBHANG_FORCE_EOV = 274 +SC_REG_SCLK_BUSY = 275 +SC_GRP0_DYN_SCLK_BUSY = 276 +SC_GRP1_DYN_SCLK_BUSY = 277 +SC_GRP2_DYN_SCLK_BUSY = 278 +SC_GRP3_DYN_SCLK_BUSY = 279 +SC_GRP4_DYN_SCLK_BUSY = 280 +SC_PA0_SC_DATA_FIFO_RD = 281 +SC_PA0_SC_DATA_FIFO_WE = 282 +SC_PA1_SC_DATA_FIFO_RD = 283 +SC_PA1_SC_DATA_FIFO_WE = 284 +SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 285 +SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 286 +SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 287 +SC_PS_ARB_STALLED_FROM_BELOW = 288 +SC_PS_ARB_STARVED_FROM_ABOVE = 289 +SC_PS_ARB_SC_BUSY = 290 +SC_PS_ARB_PA_SC_BUSY = 291 +SC_PA2_SC_DATA_FIFO_RD = 292 +SC_PA2_SC_DATA_FIFO_WE = 293 +SC_PA3_SC_DATA_FIFO_RD = 294 +SC_PA3_SC_DATA_FIFO_WE = 295 +SC_PA_SC_DEALLOC_0_0_WE = 296 +SC_PA_SC_DEALLOC_0_1_WE = 297 +SC_PA_SC_DEALLOC_1_0_WE = 298 +SC_PA_SC_DEALLOC_1_1_WE = 299 +SC_PA_SC_DEALLOC_2_0_WE = 300 +SC_PA_SC_DEALLOC_2_1_WE = 301 +SC_PA_SC_DEALLOC_3_0_WE = 302 +SC_PA_SC_DEALLOC_3_1_WE = 303 +SC_PA0_SC_EOP_WE = 304 +SC_PA0_SC_EOPG_WE = 305 +SC_PA0_SC_EVENT_WE = 306 +SC_PA1_SC_EOP_WE = 307 +SC_PA1_SC_EOPG_WE = 308 +SC_PA1_SC_EVENT_WE = 309 +SC_PA2_SC_EOP_WE = 310 +SC_PA2_SC_EOPG_WE = 311 +SC_PA2_SC_EVENT_WE = 312 +SC_PA3_SC_EOP_WE = 313 +SC_PA3_SC_EOPG_WE = 314 +SC_PA3_SC_EVENT_WE = 315 +SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 316 +SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 317 +SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 318 +SC_PS_ARB_EOP_POP_SYNC_POP = 319 +SC_PS_ARB_EVENT_SYNC_POP = 320 +SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 321 +SC_PA0_SC_FPOV_WE = 322 +SC_PA1_SC_FPOV_WE = 323 +SC_PA2_SC_FPOV_WE = 324 +SC_PA3_SC_FPOV_WE = 325 +SC_PA0_SC_LPOV_WE = 326 +SC_PA1_SC_LPOV_WE = 327 +SC_PA2_SC_LPOV_WE = 328 +SC_PA3_SC_LPOV_WE = 329 +SC_SC_SPI_DEALLOC_0_0 = 330 +SC_SC_SPI_DEALLOC_0_1 = 331 +SC_SC_SPI_DEALLOC_0_2 = 332 +SC_SC_SPI_DEALLOC_1_0 = 333 +SC_SC_SPI_DEALLOC_1_1 = 334 +SC_SC_SPI_DEALLOC_1_2 = 335 +SC_SC_SPI_DEALLOC_2_0 = 336 +SC_SC_SPI_DEALLOC_2_1 = 337 +SC_SC_SPI_DEALLOC_2_2 = 338 +SC_SC_SPI_DEALLOC_3_0 = 339 +SC_SC_SPI_DEALLOC_3_1 = 340 +SC_SC_SPI_DEALLOC_3_2 = 341 +SC_SC_SPI_FPOV_0 = 342 +SC_SC_SPI_FPOV_1 = 343 +SC_SC_SPI_FPOV_2 = 344 +SC_SC_SPI_FPOV_3 = 345 +SC_SC_SPI_EVENT = 346 +SC_PS_TS_EVENT_FIFO_PUSH = 347 +SC_PS_TS_EVENT_FIFO_POP = 348 +SC_PS_CTX_DONE_FIFO_PUSH = 349 +SC_PS_CTX_DONE_FIFO_POP = 350 +SC_MULTICYCLE_BUBBLE_FREEZE = 351 +SC_EOP_SYNC_WINDOW = 352 +SC_PA0_SC_NULL_WE = 353 +SC_PA0_SC_NULL_DEALLOC_WE = 354 +SC_PA0_SC_DATA_FIFO_EOPG_RD = 355 +SC_PA0_SC_DATA_FIFO_EOP_RD = 356 +SC_PA0_SC_DEALLOC_0_RD = 357 +SC_PA0_SC_DEALLOC_1_RD = 358 +SC_PA1_SC_DATA_FIFO_EOPG_RD = 359 +SC_PA1_SC_DATA_FIFO_EOP_RD = 360 +SC_PA1_SC_DEALLOC_0_RD = 361 +SC_PA1_SC_DEALLOC_1_RD = 362 +SC_PA1_SC_NULL_WE = 363 +SC_PA1_SC_NULL_DEALLOC_WE = 364 +SC_PA2_SC_DATA_FIFO_EOPG_RD = 365 +SC_PA2_SC_DATA_FIFO_EOP_RD = 366 +SC_PA2_SC_DEALLOC_0_RD = 367 +SC_PA2_SC_DEALLOC_1_RD = 368 +SC_PA2_SC_NULL_WE = 369 +SC_PA2_SC_NULL_DEALLOC_WE = 370 +SC_PA3_SC_DATA_FIFO_EOPG_RD = 371 +SC_PA3_SC_DATA_FIFO_EOP_RD = 372 +SC_PA3_SC_DEALLOC_0_RD = 373 +SC_PA3_SC_DEALLOC_1_RD = 374 +SC_PA3_SC_NULL_WE = 375 +SC_PA3_SC_NULL_DEALLOC_WE = 376 +SC_PS_PA0_SC_FIFO_EMPTY = 377 +SC_PS_PA0_SC_FIFO_FULL = 378 +SC_PA0_PS_DATA_SEND = 379 +SC_PS_PA1_SC_FIFO_EMPTY = 380 +SC_PS_PA1_SC_FIFO_FULL = 381 +SC_PA1_PS_DATA_SEND = 382 +SC_PS_PA2_SC_FIFO_EMPTY = 383 +SC_PS_PA2_SC_FIFO_FULL = 384 +SC_PA2_PS_DATA_SEND = 385 +SC_PS_PA3_SC_FIFO_EMPTY = 386 +SC_PS_PA3_SC_FIFO_FULL = 387 +SC_PA3_PS_DATA_SEND = 388 +SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 389 +SC_BUSY_CNT_NOT_ZERO = 390 +SC_BM_BUSY = 391 +SC_BACKEND_BUSY = 392 +SC_SCF_SCB_INTERFACE_BUSY = 393 +SC_SCB_BUSY = 394 +SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 395 +SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 396 +SC_PBB_BIN_HIST_NUM_PRIMS = 397 +SC_PBB_BATCH_HIST_NUM_PRIMS = 398 +SC_PBB_BIN_HIST_NUM_CONTEXTS = 399 +SC_PBB_BATCH_HIST_NUM_CONTEXTS = 400 +SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 401 +SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 402 +SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 403 +SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 404 +SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 405 +SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 406 +SC_PBB_BUSY = 407 +SC_PBB_BUSY_AND_RTR = 408 +SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 409 +SC_PBB_NUM_BINS = 410 +SC_PBB_END_OF_BIN = 411 +SC_PBB_END_OF_BATCH = 412 +SC_PBB_PRIMBIN_PROCESSED = 413 +SC_PBB_PRIM_ADDED_TO_BATCH = 414 +SC_PBB_NONBINNED_PRIM = 415 +SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 416 +SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 417 +SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 418 +SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 419 +SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 420 +SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 421 +SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 422 +SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 423 +SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 424 +SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 425 +SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 426 +SC_POPS_INTRA_WAVE_OVERLAPS = 427 +SC_POPS_FORCE_EOV = 428 +SC_PKR_QUAD_OVERLAP_NOT_FOUND_IN_WAVE_TABLE = 429 +SC_PKR_QUAD_OVERLAP_FOUND_IN_WAVE_TABLE = 430 +SC_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SePairXsel' +SePairXsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', + 4: 'RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE', +} +RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 3 +RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE = 4 +SePairXsel = ctypes.c_uint32 # enum + +# values for enumeration 'SePairYsel' +SePairYsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', + 4: 'RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE', +} +RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 3 +RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE = 4 +SePairYsel = ctypes.c_uint32 # enum + +# values for enumeration 'SePairMap' +SePairMap__enumvalues = { + 0: 'RASTER_CONFIG_SE_PAIR_MAP_0', + 1: 'RASTER_CONFIG_SE_PAIR_MAP_1', + 2: 'RASTER_CONFIG_SE_PAIR_MAP_2', + 3: 'RASTER_CONFIG_SE_PAIR_MAP_3', +} +RASTER_CONFIG_SE_PAIR_MAP_0 = 0 +RASTER_CONFIG_SE_PAIR_MAP_1 = 1 +RASTER_CONFIG_SE_PAIR_MAP_2 = 2 +RASTER_CONFIG_SE_PAIR_MAP_3 = 3 +SePairMap = ctypes.c_uint32 # enum + +# values for enumeration 'SeXsel' +SeXsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', + 4: 'RASTER_CONFIG_SE_XSEL_128_WIDE_TILE', +} +RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 3 +RASTER_CONFIG_SE_XSEL_128_WIDE_TILE = 4 +SeXsel = ctypes.c_uint32 # enum + +# values for enumeration 'SeYsel' +SeYsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', + 4: 'RASTER_CONFIG_SE_YSEL_128_WIDE_TILE', +} +RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 3 +RASTER_CONFIG_SE_YSEL_128_WIDE_TILE = 4 +SeYsel = ctypes.c_uint32 # enum + +# values for enumeration 'SeMap' +SeMap__enumvalues = { + 0: 'RASTER_CONFIG_SE_MAP_0', + 1: 'RASTER_CONFIG_SE_MAP_1', + 2: 'RASTER_CONFIG_SE_MAP_2', + 3: 'RASTER_CONFIG_SE_MAP_3', +} +RASTER_CONFIG_SE_MAP_0 = 0 +RASTER_CONFIG_SE_MAP_1 = 1 +RASTER_CONFIG_SE_MAP_2 = 2 +RASTER_CONFIG_SE_MAP_3 = 3 +SeMap = ctypes.c_uint32 # enum + +# values for enumeration 'ScXsel' +ScXsel__enumvalues = { + 0: 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 3 +ScXsel = ctypes.c_uint32 # enum + +# values for enumeration 'ScYsel' +ScYsel__enumvalues = { + 0: 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 3 +ScYsel = ctypes.c_uint32 # enum + +# values for enumeration 'ScMap' +ScMap__enumvalues = { + 0: 'RASTER_CONFIG_SC_MAP_0', + 1: 'RASTER_CONFIG_SC_MAP_1', + 2: 'RASTER_CONFIG_SC_MAP_2', + 3: 'RASTER_CONFIG_SC_MAP_3', +} +RASTER_CONFIG_SC_MAP_0 = 0 +RASTER_CONFIG_SC_MAP_1 = 1 +RASTER_CONFIG_SC_MAP_2 = 2 +RASTER_CONFIG_SC_MAP_3 = 3 +ScMap = ctypes.c_uint32 # enum + +# values for enumeration 'PkrXsel2' +PkrXsel2__enumvalues = { + 0: 'RASTER_CONFIG_PKR_XSEL2_0', + 1: 'RASTER_CONFIG_PKR_XSEL2_1', + 2: 'RASTER_CONFIG_PKR_XSEL2_2', + 3: 'RASTER_CONFIG_PKR_XSEL2_3', +} +RASTER_CONFIG_PKR_XSEL2_0 = 0 +RASTER_CONFIG_PKR_XSEL2_1 = 1 +RASTER_CONFIG_PKR_XSEL2_2 = 2 +RASTER_CONFIG_PKR_XSEL2_3 = 3 +PkrXsel2 = ctypes.c_uint32 # enum + +# values for enumeration 'PkrXsel' +PkrXsel__enumvalues = { + 0: 'RASTER_CONFIG_PKR_XSEL_0', + 1: 'RASTER_CONFIG_PKR_XSEL_1', + 2: 'RASTER_CONFIG_PKR_XSEL_2', + 3: 'RASTER_CONFIG_PKR_XSEL_3', +} +RASTER_CONFIG_PKR_XSEL_0 = 0 +RASTER_CONFIG_PKR_XSEL_1 = 1 +RASTER_CONFIG_PKR_XSEL_2 = 2 +RASTER_CONFIG_PKR_XSEL_3 = 3 +PkrXsel = ctypes.c_uint32 # enum + +# values for enumeration 'PkrYsel' +PkrYsel__enumvalues = { + 0: 'RASTER_CONFIG_PKR_YSEL_0', + 1: 'RASTER_CONFIG_PKR_YSEL_1', + 2: 'RASTER_CONFIG_PKR_YSEL_2', + 3: 'RASTER_CONFIG_PKR_YSEL_3', +} +RASTER_CONFIG_PKR_YSEL_0 = 0 +RASTER_CONFIG_PKR_YSEL_1 = 1 +RASTER_CONFIG_PKR_YSEL_2 = 2 +RASTER_CONFIG_PKR_YSEL_3 = 3 +PkrYsel = ctypes.c_uint32 # enum + +# values for enumeration 'PkrMap' +PkrMap__enumvalues = { + 0: 'RASTER_CONFIG_PKR_MAP_0', + 1: 'RASTER_CONFIG_PKR_MAP_1', + 2: 'RASTER_CONFIG_PKR_MAP_2', + 3: 'RASTER_CONFIG_PKR_MAP_3', +} +RASTER_CONFIG_PKR_MAP_0 = 0 +RASTER_CONFIG_PKR_MAP_1 = 1 +RASTER_CONFIG_PKR_MAP_2 = 2 +RASTER_CONFIG_PKR_MAP_3 = 3 +PkrMap = ctypes.c_uint32 # enum + +# values for enumeration 'RbXsel' +RbXsel__enumvalues = { + 0: 'RASTER_CONFIG_RB_XSEL_0', + 1: 'RASTER_CONFIG_RB_XSEL_1', +} +RASTER_CONFIG_RB_XSEL_0 = 0 +RASTER_CONFIG_RB_XSEL_1 = 1 +RbXsel = ctypes.c_uint32 # enum + +# values for enumeration 'RbYsel' +RbYsel__enumvalues = { + 0: 'RASTER_CONFIG_RB_YSEL_0', + 1: 'RASTER_CONFIG_RB_YSEL_1', +} +RASTER_CONFIG_RB_YSEL_0 = 0 +RASTER_CONFIG_RB_YSEL_1 = 1 +RbYsel = ctypes.c_uint32 # enum + +# values for enumeration 'RbXsel2' +RbXsel2__enumvalues = { + 0: 'RASTER_CONFIG_RB_XSEL2_0', + 1: 'RASTER_CONFIG_RB_XSEL2_1', + 2: 'RASTER_CONFIG_RB_XSEL2_2', + 3: 'RASTER_CONFIG_RB_XSEL2_3', +} +RASTER_CONFIG_RB_XSEL2_0 = 0 +RASTER_CONFIG_RB_XSEL2_1 = 1 +RASTER_CONFIG_RB_XSEL2_2 = 2 +RASTER_CONFIG_RB_XSEL2_3 = 3 +RbXsel2 = ctypes.c_uint32 # enum + +# values for enumeration 'RbMap' +RbMap__enumvalues = { + 0: 'RASTER_CONFIG_RB_MAP_0', + 1: 'RASTER_CONFIG_RB_MAP_1', + 2: 'RASTER_CONFIG_RB_MAP_2', + 3: 'RASTER_CONFIG_RB_MAP_3', +} +RASTER_CONFIG_RB_MAP_0 = 0 +RASTER_CONFIG_RB_MAP_1 = 1 +RASTER_CONFIG_RB_MAP_2 = 2 +RASTER_CONFIG_RB_MAP_3 = 3 +RbMap = ctypes.c_uint32 # enum + +# values for enumeration 'BinningMode' +BinningMode__enumvalues = { + 0: 'BINNING_ALLOWED', + 1: 'FORCE_BINNING_ON', + 2: 'DISABLE_BINNING_USE_NEW_SC', + 3: 'DISABLE_BINNING_USE_LEGACY_SC', +} +BINNING_ALLOWED = 0 +FORCE_BINNING_ON = 1 +DISABLE_BINNING_USE_NEW_SC = 2 +DISABLE_BINNING_USE_LEGACY_SC = 3 +BinningMode = ctypes.c_uint32 # enum + +# values for enumeration 'BinEventCntl' +BinEventCntl__enumvalues = { + 0: 'BINNER_BREAK_BATCH', + 1: 'BINNER_PIPELINE', + 2: 'BINNER_DROP_ASSERT', +} +BINNER_BREAK_BATCH = 0 +BINNER_PIPELINE = 1 +BINNER_DROP_ASSERT = 2 +BinEventCntl = ctypes.c_uint32 # enum + +# values for enumeration 'CovToShaderSel' +CovToShaderSel__enumvalues = { + 0: 'INPUT_COVERAGE', + 1: 'INPUT_INNER_COVERAGE', + 2: 'INPUT_DEPTH_COVERAGE', + 3: 'RAW', +} +INPUT_COVERAGE = 0 +INPUT_INNER_COVERAGE = 1 +INPUT_DEPTH_COVERAGE = 2 +RAW = 3 +CovToShaderSel = ctypes.c_uint32 # enum + +# values for enumeration 'RMIPerfSel' +RMIPerfSel__enumvalues = { + 0: 'RMI_PERF_SEL_NONE', + 1: 'RMI_PERF_SEL_BUSY', + 2: 'RMI_PERF_SEL_REG_CLK_VLD', + 3: 'RMI_PERF_SEL_DYN_CLK_CMN_VLD', + 4: 'RMI_PERF_SEL_DYN_CLK_RB_VLD', + 5: 'RMI_PERF_SEL_DYN_CLK_PERF_VLD', + 6: 'RMI_PERF_SEL_PERF_WINDOW', + 7: 'RMI_PERF_SEL_EVENT_SEND', + 8: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0', + 9: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1', + 10: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2', + 11: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3', + 12: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4', + 13: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5', + 14: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6', + 15: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7', + 16: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8', + 17: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9', + 18: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10', + 19: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11', + 20: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12', + 21: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13', + 22: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14', + 23: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15', + 24: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL', + 25: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0', + 26: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1', + 27: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2', + 28: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3', + 29: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4', + 30: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5', + 31: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6', + 32: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7', + 33: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8', + 34: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9', + 35: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10', + 36: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11', + 37: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12', + 38: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13', + 39: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14', + 40: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15', + 41: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL', + 42: 'RMI_PERF_SEL_UTCL1_TRANSLATION_MISS', + 43: 'RMI_PERF_SEL_UTCL1_PERMISSION_MISS', + 44: 'RMI_PERF_SEL_UTCL1_REQUEST', + 45: 'RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', + 46: 'RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', + 47: 'RMI_PERF_SEL_UTCL1_LFIFO_FULL', + 48: 'RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', + 49: 'RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', + 50: 'RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', + 51: 'RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL', + 52: 'RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS', + 53: 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', + 54: 'RMI_PERF_SEL_RB_RMI_WRREQ_BUSY', + 55: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID0', + 56: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID1', + 57: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID2', + 58: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID3', + 59: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID4', + 60: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID5', + 61: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID6', + 62: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID7', + 63: 'RMI_PERF_SEL_RB_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID', + 64: 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID', + 65: 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID', + 66: 'RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY', + 67: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID', + 68: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0', + 69: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1', + 70: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2', + 71: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3', + 72: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4', + 73: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5', + 74: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6', + 75: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7', + 76: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0', + 77: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1', + 78: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2', + 79: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3', + 80: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID', + 81: 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', + 82: 'RMI_PERF_SEL_RB_RMI_RDREQ_BUSY', + 83: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0', + 84: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1', + 85: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2', + 86: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3', + 87: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4', + 88: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5', + 89: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6', + 90: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7', + 91: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID0', + 92: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID1', + 93: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID2', + 94: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID3', + 95: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID4', + 96: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID5', + 97: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID6', + 98: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID7', + 99: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID', + 100: 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID', + 101: 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID', + 102: 'RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY', + 103: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID', + 104: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0', + 105: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1', + 106: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2', + 107: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3', + 108: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4', + 109: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5', + 110: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6', + 111: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7', + 112: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0', + 113: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1', + 114: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2', + 115: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3', + 116: 'RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID', + 117: 'RMI_PERF_SEL_RMI_TC_REQ_BUSY', + 118: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID0', + 119: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID1', + 120: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID2', + 121: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID3', + 122: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID4', + 123: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID5', + 124: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID6', + 125: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID7', + 126: 'RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID', + 127: 'RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID', + 128: 'RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID', + 129: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID0', + 130: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID1', + 131: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID2', + 132: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID3', + 133: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID4', + 134: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID5', + 135: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID6', + 136: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID7', + 137: 'RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID', + 138: 'RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID', + 139: 'RMI_PERF_SEL_UTCL1_BUSY', + 140: 'RMI_PERF_SEL_RMI_UTC_REQ', + 141: 'RMI_PERF_SEL_RMI_UTC_BUSY', + 142: 'RMI_PERF_SEL_UTCL1_UTCL2_REQ', + 143: 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY', + 144: 'RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT', + 145: 'RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT', + 146: 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT', + 147: 'RMI_PERF_SEL_XNACK_FIFO_NUM_USED', + 148: 'RMI_PERF_SEL_LAT_FIFO_NUM_USED', + 149: 'RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ', + 150: 'RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ', + 151: 'RMI_PERF_SEL_XNACK_FIFO_FULL', + 152: 'RMI_PERF_SEL_XNACK_FIFO_BUSY', + 153: 'RMI_PERF_SEL_LAT_FIFO_FULL', + 154: 'RMI_PERF_SEL_SKID_FIFO_DEPTH', + 155: 'RMI_PERF_SEL_TCIW_INFLIGHT_COUNT', + 156: 'RMI_PERF_SEL_PRT_FIFO_NUM_USED', + 157: 'RMI_PERF_SEL_PRT_FIFO_REQ', + 158: 'RMI_PERF_SEL_PRT_FIFO_BUSY', + 159: 'RMI_PERF_SEL_TCIW_REQ', + 160: 'RMI_PERF_SEL_TCIW_BUSY', + 161: 'RMI_PERF_SEL_SKID_FIFO_REQ', + 162: 'RMI_PERF_SEL_SKID_FIFO_BUSY', + 163: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0', + 164: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1', + 165: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2', + 166: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3', + 167: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR', + 168: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR', + 169: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB', + 170: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB', + 171: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR', + 172: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR', + 173: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB', + 174: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB', + 175: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR', + 176: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR', + 177: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB', + 178: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB', + 179: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR', + 180: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR', + 181: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB', + 182: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB', + 183: 'RMI_PERF_SEL_POP_DEMUX_RTS_RTR', + 184: 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTR', + 185: 'RMI_PERF_SEL_POP_DEMUX_RTS_RTRB', + 186: 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB', + 187: 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR', + 188: 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR', + 189: 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB', + 190: 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB', + 191: 'RMI_PERF_SEL_UTC_POP_RTS_RTR', + 192: 'RMI_PERF_SEL_UTC_POP_RTSB_RTR', + 193: 'RMI_PERF_SEL_UTC_POP_RTS_RTRB', + 194: 'RMI_PERF_SEL_UTC_POP_RTSB_RTRB', + 195: 'RMI_PERF_SEL_POP_XNACK_RTS_RTR', + 196: 'RMI_PERF_SEL_POP_XNACK_RTSB_RTR', + 197: 'RMI_PERF_SEL_POP_XNACK_RTS_RTRB', + 198: 'RMI_PERF_SEL_POP_XNACK_RTSB_RTRB', + 199: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR', + 200: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR', + 201: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB', + 202: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB', + 203: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR', + 204: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR', + 205: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB', + 206: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB', + 207: 'RMI_PERF_SEL_SKID_FIFO_IN_RTS', + 208: 'RMI_PERF_SEL_SKID_FIFO_IN_RTSB', + 209: 'RMI_PERF_SEL_SKID_FIFO_OUT_RTS', + 210: 'RMI_PERF_SEL_SKID_FIFO_OUT_RTSB', + 211: 'RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR', + 212: 'RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR', + 213: 'RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR', + 214: 'RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR', + 215: 'RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR', + 216: 'RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR', + 217: 'RMI_PERF_SEL_REORDER_FIFO_REQ', + 218: 'RMI_PERF_SEL_REORDER_FIFO_BUSY', + 219: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID', + 220: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0', + 221: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1', + 222: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2', + 223: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3', + 224: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4', + 225: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5', + 226: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6', + 227: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7', + 228: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0', + 229: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1', + 230: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2', + 231: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3', +} +RMI_PERF_SEL_NONE = 0 +RMI_PERF_SEL_BUSY = 1 +RMI_PERF_SEL_REG_CLK_VLD = 2 +RMI_PERF_SEL_DYN_CLK_CMN_VLD = 3 +RMI_PERF_SEL_DYN_CLK_RB_VLD = 4 +RMI_PERF_SEL_DYN_CLK_PERF_VLD = 5 +RMI_PERF_SEL_PERF_WINDOW = 6 +RMI_PERF_SEL_EVENT_SEND = 7 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0 = 8 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1 = 9 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2 = 10 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3 = 11 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4 = 12 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5 = 13 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6 = 14 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7 = 15 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8 = 16 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9 = 17 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10 = 18 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11 = 19 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12 = 20 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13 = 21 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14 = 22 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15 = 23 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL = 24 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0 = 25 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1 = 26 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2 = 27 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3 = 28 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4 = 29 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5 = 30 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6 = 31 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7 = 32 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8 = 33 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9 = 34 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10 = 35 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11 = 36 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12 = 37 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13 = 38 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14 = 39 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15 = 40 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL = 41 +RMI_PERF_SEL_UTCL1_TRANSLATION_MISS = 42 +RMI_PERF_SEL_UTCL1_PERMISSION_MISS = 43 +RMI_PERF_SEL_UTCL1_REQUEST = 44 +RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 45 +RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 46 +RMI_PERF_SEL_UTCL1_LFIFO_FULL = 47 +RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 48 +RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 49 +RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 50 +RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL = 51 +RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS = 52 +RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 53 +RMI_PERF_SEL_RB_RMI_WRREQ_BUSY = 54 +RMI_PERF_SEL_RB_RMI_WRREQ_CID0 = 55 +RMI_PERF_SEL_RB_RMI_WRREQ_CID1 = 56 +RMI_PERF_SEL_RB_RMI_WRREQ_CID2 = 57 +RMI_PERF_SEL_RB_RMI_WRREQ_CID3 = 58 +RMI_PERF_SEL_RB_RMI_WRREQ_CID4 = 59 +RMI_PERF_SEL_RB_RMI_WRREQ_CID5 = 60 +RMI_PERF_SEL_RB_RMI_WRREQ_CID6 = 61 +RMI_PERF_SEL_RB_RMI_WRREQ_CID7 = 62 +RMI_PERF_SEL_RB_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID = 63 +RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 64 +RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 65 +RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY = 66 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID = 67 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0 = 68 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1 = 69 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2 = 70 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3 = 71 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4 = 72 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5 = 73 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6 = 74 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7 = 75 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0 = 76 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1 = 77 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2 = 78 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3 = 79 +RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID = 80 +RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 81 +RMI_PERF_SEL_RB_RMI_RDREQ_BUSY = 82 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0 = 83 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1 = 84 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2 = 85 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3 = 86 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4 = 87 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5 = 88 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6 = 89 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7 = 90 +RMI_PERF_SEL_RB_RMI_RDREQ_CID0 = 91 +RMI_PERF_SEL_RB_RMI_RDREQ_CID1 = 92 +RMI_PERF_SEL_RB_RMI_RDREQ_CID2 = 93 +RMI_PERF_SEL_RB_RMI_RDREQ_CID3 = 94 +RMI_PERF_SEL_RB_RMI_RDREQ_CID4 = 95 +RMI_PERF_SEL_RB_RMI_RDREQ_CID5 = 96 +RMI_PERF_SEL_RB_RMI_RDREQ_CID6 = 97 +RMI_PERF_SEL_RB_RMI_RDREQ_CID7 = 98 +RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 99 +RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 100 +RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 101 +RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY = 102 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 103 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0 = 104 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1 = 105 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2 = 106 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3 = 107 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4 = 108 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5 = 109 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6 = 110 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7 = 111 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 112 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 113 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 114 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 115 +RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID = 116 +RMI_PERF_SEL_RMI_TC_REQ_BUSY = 117 +RMI_PERF_SEL_RMI_TC_WRREQ_CID0 = 118 +RMI_PERF_SEL_RMI_TC_WRREQ_CID1 = 119 +RMI_PERF_SEL_RMI_TC_WRREQ_CID2 = 120 +RMI_PERF_SEL_RMI_TC_WRREQ_CID3 = 121 +RMI_PERF_SEL_RMI_TC_WRREQ_CID4 = 122 +RMI_PERF_SEL_RMI_TC_WRREQ_CID5 = 123 +RMI_PERF_SEL_RMI_TC_WRREQ_CID6 = 124 +RMI_PERF_SEL_RMI_TC_WRREQ_CID7 = 125 +RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 126 +RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID = 127 +RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID = 128 +RMI_PERF_SEL_RMI_TC_RDREQ_CID0 = 129 +RMI_PERF_SEL_RMI_TC_RDREQ_CID1 = 130 +RMI_PERF_SEL_RMI_TC_RDREQ_CID2 = 131 +RMI_PERF_SEL_RMI_TC_RDREQ_CID3 = 132 +RMI_PERF_SEL_RMI_TC_RDREQ_CID4 = 133 +RMI_PERF_SEL_RMI_TC_RDREQ_CID5 = 134 +RMI_PERF_SEL_RMI_TC_RDREQ_CID6 = 135 +RMI_PERF_SEL_RMI_TC_RDREQ_CID7 = 136 +RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 137 +RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID = 138 +RMI_PERF_SEL_UTCL1_BUSY = 139 +RMI_PERF_SEL_RMI_UTC_REQ = 140 +RMI_PERF_SEL_RMI_UTC_BUSY = 141 +RMI_PERF_SEL_UTCL1_UTCL2_REQ = 142 +RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY = 143 +RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT = 144 +RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT = 145 +RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT = 146 +RMI_PERF_SEL_XNACK_FIFO_NUM_USED = 147 +RMI_PERF_SEL_LAT_FIFO_NUM_USED = 148 +RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ = 149 +RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ = 150 +RMI_PERF_SEL_XNACK_FIFO_FULL = 151 +RMI_PERF_SEL_XNACK_FIFO_BUSY = 152 +RMI_PERF_SEL_LAT_FIFO_FULL = 153 +RMI_PERF_SEL_SKID_FIFO_DEPTH = 154 +RMI_PERF_SEL_TCIW_INFLIGHT_COUNT = 155 +RMI_PERF_SEL_PRT_FIFO_NUM_USED = 156 +RMI_PERF_SEL_PRT_FIFO_REQ = 157 +RMI_PERF_SEL_PRT_FIFO_BUSY = 158 +RMI_PERF_SEL_TCIW_REQ = 159 +RMI_PERF_SEL_TCIW_BUSY = 160 +RMI_PERF_SEL_SKID_FIFO_REQ = 161 +RMI_PERF_SEL_SKID_FIFO_BUSY = 162 +RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0 = 163 +RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1 = 164 +RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2 = 165 +RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3 = 166 +RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR = 167 +RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR = 168 +RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB = 169 +RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB = 170 +RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 171 +RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 172 +RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 173 +RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 174 +RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR = 175 +RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR = 176 +RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB = 177 +RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB = 178 +RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR = 179 +RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR = 180 +RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB = 181 +RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB = 182 +RMI_PERF_SEL_POP_DEMUX_RTS_RTR = 183 +RMI_PERF_SEL_POP_DEMUX_RTSB_RTR = 184 +RMI_PERF_SEL_POP_DEMUX_RTS_RTRB = 185 +RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB = 186 +RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR = 187 +RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR = 188 +RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB = 189 +RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB = 190 +RMI_PERF_SEL_UTC_POP_RTS_RTR = 191 +RMI_PERF_SEL_UTC_POP_RTSB_RTR = 192 +RMI_PERF_SEL_UTC_POP_RTS_RTRB = 193 +RMI_PERF_SEL_UTC_POP_RTSB_RTRB = 194 +RMI_PERF_SEL_POP_XNACK_RTS_RTR = 195 +RMI_PERF_SEL_POP_XNACK_RTSB_RTR = 196 +RMI_PERF_SEL_POP_XNACK_RTS_RTRB = 197 +RMI_PERF_SEL_POP_XNACK_RTSB_RTRB = 198 +RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR = 199 +RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR = 200 +RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB = 201 +RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB = 202 +RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR = 203 +RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR = 204 +RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB = 205 +RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB = 206 +RMI_PERF_SEL_SKID_FIFO_IN_RTS = 207 +RMI_PERF_SEL_SKID_FIFO_IN_RTSB = 208 +RMI_PERF_SEL_SKID_FIFO_OUT_RTS = 209 +RMI_PERF_SEL_SKID_FIFO_OUT_RTSB = 210 +RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR = 211 +RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR = 212 +RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR = 213 +RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR = 214 +RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR = 215 +RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR = 216 +RMI_PERF_SEL_REORDER_FIFO_REQ = 217 +RMI_PERF_SEL_REORDER_FIFO_BUSY = 218 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID = 219 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0 = 220 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1 = 221 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2 = 222 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3 = 223 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4 = 224 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5 = 225 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6 = 226 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7 = 227 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0 = 228 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1 = 229 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2 = 230 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3 = 231 +RMIPerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'IH_PERF_SEL' +IH_PERF_SEL__enumvalues = { + 0: 'IH_PERF_SEL_CYCLE', + 1: 'IH_PERF_SEL_IDLE', + 2: 'IH_PERF_SEL_INPUT_IDLE', + 3: 'IH_PERF_SEL_BUFFER_IDLE', + 4: 'IH_PERF_SEL_RB0_FULL', + 5: 'IH_PERF_SEL_RB0_OVERFLOW', + 6: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', + 7: 'IH_PERF_SEL_RB0_WPTR_WRAP', + 8: 'IH_PERF_SEL_RB0_RPTR_WRAP', + 9: 'IH_PERF_SEL_MC_WR_IDLE', + 10: 'IH_PERF_SEL_MC_WR_COUNT', + 11: 'IH_PERF_SEL_MC_WR_STALL', + 12: 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', + 13: 'IH_PERF_SEL_MC_WR_CLEAN_STALL', + 14: 'IH_PERF_SEL_BIF_LINE0_RISING', + 15: 'IH_PERF_SEL_BIF_LINE0_FALLING', + 16: 'IH_PERF_SEL_RB1_FULL', + 17: 'IH_PERF_SEL_RB1_OVERFLOW', + 18: 'Reserved18', + 19: 'IH_PERF_SEL_RB1_WPTR_WRAP', + 20: 'IH_PERF_SEL_RB1_RPTR_WRAP', + 21: 'IH_PERF_SEL_RB2_FULL', + 22: 'IH_PERF_SEL_RB2_OVERFLOW', + 23: 'Reserved23', + 24: 'IH_PERF_SEL_RB2_WPTR_WRAP', + 25: 'IH_PERF_SEL_RB2_RPTR_WRAP', + 26: 'Reserved26', + 27: 'Reserved27', + 28: 'Reserved28', + 29: 'Reserved29', + 30: 'IH_PERF_SEL_RB0_FULL_VF0', + 31: 'IH_PERF_SEL_RB0_FULL_VF1', + 32: 'IH_PERF_SEL_RB0_FULL_VF2', + 33: 'IH_PERF_SEL_RB0_FULL_VF3', + 34: 'IH_PERF_SEL_RB0_FULL_VF4', + 35: 'IH_PERF_SEL_RB0_FULL_VF5', + 36: 'IH_PERF_SEL_RB0_FULL_VF6', + 37: 'IH_PERF_SEL_RB0_FULL_VF7', + 38: 'IH_PERF_SEL_RB0_FULL_VF8', + 39: 'IH_PERF_SEL_RB0_FULL_VF9', + 40: 'IH_PERF_SEL_RB0_FULL_VF10', + 41: 'IH_PERF_SEL_RB0_FULL_VF11', + 42: 'IH_PERF_SEL_RB0_FULL_VF12', + 43: 'IH_PERF_SEL_RB0_FULL_VF13', + 44: 'IH_PERF_SEL_RB0_FULL_VF14', + 45: 'IH_PERF_SEL_RB0_FULL_VF15', + 46: 'IH_PERF_SEL_RB0_OVERFLOW_VF0', + 47: 'IH_PERF_SEL_RB0_OVERFLOW_VF1', + 48: 'IH_PERF_SEL_RB0_OVERFLOW_VF2', + 49: 'IH_PERF_SEL_RB0_OVERFLOW_VF3', + 50: 'IH_PERF_SEL_RB0_OVERFLOW_VF4', + 51: 'IH_PERF_SEL_RB0_OVERFLOW_VF5', + 52: 'IH_PERF_SEL_RB0_OVERFLOW_VF6', + 53: 'IH_PERF_SEL_RB0_OVERFLOW_VF7', + 54: 'IH_PERF_SEL_RB0_OVERFLOW_VF8', + 55: 'IH_PERF_SEL_RB0_OVERFLOW_VF9', + 56: 'IH_PERF_SEL_RB0_OVERFLOW_VF10', + 57: 'IH_PERF_SEL_RB0_OVERFLOW_VF11', + 58: 'IH_PERF_SEL_RB0_OVERFLOW_VF12', + 59: 'IH_PERF_SEL_RB0_OVERFLOW_VF13', + 60: 'IH_PERF_SEL_RB0_OVERFLOW_VF14', + 61: 'IH_PERF_SEL_RB0_OVERFLOW_VF15', + 62: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', + 63: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', + 64: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', + 65: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', + 66: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', + 67: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', + 68: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', + 69: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', + 70: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', + 71: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', + 72: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', + 73: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', + 74: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', + 75: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', + 76: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', + 77: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', + 78: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', + 79: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', + 80: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', + 81: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', + 82: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', + 83: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', + 84: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', + 85: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', + 86: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', + 87: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', + 88: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', + 89: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', + 90: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', + 91: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', + 92: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', + 93: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', + 94: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', + 95: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', + 96: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', + 97: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', + 98: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', + 99: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', + 100: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', + 101: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', + 102: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', + 103: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', + 104: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', + 105: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', + 106: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', + 107: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', + 108: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', + 109: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', + 110: 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', + 111: 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', + 112: 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', + 113: 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', + 114: 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', + 115: 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', + 116: 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', + 117: 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', + 118: 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', + 119: 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', + 120: 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', + 121: 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', + 122: 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', + 123: 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', + 124: 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', + 125: 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', + 126: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', + 127: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', + 128: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', + 129: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', + 130: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', + 131: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', + 132: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', + 133: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', + 134: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', + 135: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', + 136: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', + 137: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', + 138: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', + 139: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', + 140: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', + 141: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', + 142: 'Reserved142', + 143: 'Reserved143', + 144: 'Reserved144', + 145: 'Reserved145', + 146: 'Reserved146', + 147: 'Reserved147', + 148: 'Reserved148', + 149: 'Reserved149', + 150: 'IH_PERF_SEL_CLIENT0_INT', + 151: 'IH_PERF_SEL_CLIENT1_INT', + 152: 'IH_PERF_SEL_CLIENT2_INT', + 153: 'IH_PERF_SEL_CLIENT3_INT', + 154: 'IH_PERF_SEL_CLIENT4_INT', + 155: 'IH_PERF_SEL_CLIENT5_INT', + 156: 'IH_PERF_SEL_CLIENT6_INT', + 157: 'IH_PERF_SEL_CLIENT7_INT', + 158: 'IH_PERF_SEL_CLIENT8_INT', + 159: 'IH_PERF_SEL_CLIENT9_INT', + 160: 'IH_PERF_SEL_CLIENT10_INT', + 161: 'IH_PERF_SEL_CLIENT11_INT', + 162: 'IH_PERF_SEL_CLIENT12_INT', + 163: 'IH_PERF_SEL_CLIENT13_INT', + 164: 'IH_PERF_SEL_CLIENT14_INT', + 165: 'IH_PERF_SEL_CLIENT15_INT', + 166: 'IH_PERF_SEL_CLIENT16_INT', + 167: 'IH_PERF_SEL_CLIENT17_INT', + 168: 'IH_PERF_SEL_CLIENT18_INT', + 169: 'IH_PERF_SEL_CLIENT19_INT', + 170: 'IH_PERF_SEL_CLIENT20_INT', + 171: 'IH_PERF_SEL_CLIENT21_INT', + 172: 'IH_PERF_SEL_CLIENT22_INT', + 173: 'IH_PERF_SEL_CLIENT23_INT', + 174: 'IH_PERF_SEL_CLIENT24_INT', + 175: 'IH_PERF_SEL_CLIENT25_INT', + 176: 'IH_PERF_SEL_CLIENT26_INT', + 177: 'IH_PERF_SEL_CLIENT27_INT', + 178: 'IH_PERF_SEL_CLIENT28_INT', + 179: 'IH_PERF_SEL_CLIENT29_INT', + 180: 'IH_PERF_SEL_CLIENT30_INT', + 181: 'IH_PERF_SEL_CLIENT31_INT', + 182: 'Reserved182', + 183: 'Reserved183', + 184: 'Reserved184', + 185: 'Reserved185', + 186: 'Reserved186', + 187: 'Reserved187', + 188: 'Reserved188', + 189: 'Reserved189', + 190: 'Reserved190', + 191: 'Reserved191', + 192: 'Reserved192', + 193: 'Reserved193', + 194: 'Reserved194', + 195: 'Reserved195', + 196: 'Reserved196', + 197: 'Reserved197', + 198: 'Reserved198', + 199: 'Reserved199', + 200: 'Reserved200', + 201: 'Reserved201', + 202: 'Reserved202', + 203: 'Reserved203', + 204: 'Reserved204', + 205: 'Reserved205', + 206: 'Reserved206', + 207: 'Reserved207', + 208: 'Reserved208', + 209: 'Reserved209', + 210: 'Reserved210', + 211: 'Reserved211', + 212: 'Reserved212', + 213: 'Reserved213', + 214: 'Reserved214', + 215: 'Reserved215', + 216: 'Reserved216', + 217: 'Reserved217', + 218: 'Reserved218', + 219: 'Reserved219', + 220: 'IH_PERF_SEL_RB1_FULL_VF0', + 221: 'IH_PERF_SEL_RB1_FULL_VF1', + 222: 'IH_PERF_SEL_RB1_FULL_VF2', + 223: 'IH_PERF_SEL_RB1_FULL_VF3', + 224: 'IH_PERF_SEL_RB1_FULL_VF4', + 225: 'IH_PERF_SEL_RB1_FULL_VF5', + 226: 'IH_PERF_SEL_RB1_FULL_VF6', + 227: 'IH_PERF_SEL_RB1_FULL_VF7', + 228: 'IH_PERF_SEL_RB1_FULL_VF8', + 229: 'IH_PERF_SEL_RB1_FULL_VF9', + 230: 'IH_PERF_SEL_RB1_FULL_VF10', + 231: 'IH_PERF_SEL_RB1_FULL_VF11', + 232: 'IH_PERF_SEL_RB1_FULL_VF12', + 233: 'IH_PERF_SEL_RB1_FULL_VF13', + 234: 'IH_PERF_SEL_RB1_FULL_VF14', + 235: 'IH_PERF_SEL_RB1_FULL_VF15', + 236: 'IH_PERF_SEL_RB1_OVERFLOW_VF0', + 237: 'IH_PERF_SEL_RB1_OVERFLOW_VF1', + 238: 'IH_PERF_SEL_RB1_OVERFLOW_VF2', + 239: 'IH_PERF_SEL_RB1_OVERFLOW_VF3', + 240: 'IH_PERF_SEL_RB1_OVERFLOW_VF4', + 241: 'IH_PERF_SEL_RB1_OVERFLOW_VF5', + 242: 'IH_PERF_SEL_RB1_OVERFLOW_VF6', + 243: 'IH_PERF_SEL_RB1_OVERFLOW_VF7', + 244: 'IH_PERF_SEL_RB1_OVERFLOW_VF8', + 245: 'IH_PERF_SEL_RB1_OVERFLOW_VF9', + 246: 'IH_PERF_SEL_RB1_OVERFLOW_VF10', + 247: 'IH_PERF_SEL_RB1_OVERFLOW_VF11', + 248: 'IH_PERF_SEL_RB1_OVERFLOW_VF12', + 249: 'IH_PERF_SEL_RB1_OVERFLOW_VF13', + 250: 'IH_PERF_SEL_RB1_OVERFLOW_VF14', + 251: 'IH_PERF_SEL_RB1_OVERFLOW_VF15', + 252: 'Reserved252', + 253: 'Reserved253', + 254: 'Reserved254', + 255: 'Reserved255', + 256: 'Reserved256', + 257: 'Reserved257', + 258: 'Reserved258', + 259: 'Reserved259', + 260: 'Reserved260', + 261: 'Reserved261', + 262: 'Reserved262', + 263: 'Reserved263', + 264: 'Reserved264', + 265: 'Reserved265', + 266: 'Reserved266', + 267: 'Reserved267', + 268: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', + 269: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', + 270: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', + 271: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', + 272: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', + 273: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', + 274: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', + 275: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', + 276: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', + 277: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', + 278: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', + 279: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', + 280: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', + 281: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', + 282: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', + 283: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', + 284: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', + 285: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', + 286: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', + 287: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', + 288: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', + 289: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', + 290: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', + 291: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', + 292: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', + 293: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', + 294: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', + 295: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', + 296: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', + 297: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', + 298: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', + 299: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', + 300: 'Reserved300', + 301: 'Reserved301', + 302: 'Reserved302', + 303: 'Reserved303', + 304: 'Reserved304', + 305: 'Reserved305', + 306: 'Reserved306', + 307: 'Reserved307', + 308: 'Reserved308', + 309: 'Reserved309', + 310: 'Reserved310', + 311: 'Reserved311', + 312: 'Reserved312', + 313: 'Reserved313', + 314: 'Reserved314', + 315: 'Reserved315', + 316: 'Reserved316', + 317: 'Reserved317', + 318: 'Reserved318', + 319: 'Reserved319', + 320: 'Reserved320', + 321: 'Reserved321', + 322: 'Reserved322', + 323: 'Reserved323', + 324: 'Reserved324', + 325: 'Reserved325', + 326: 'Reserved326', + 327: 'Reserved327', + 328: 'Reserved328', + 329: 'Reserved329', + 330: 'Reserved330', + 331: 'Reserved331', + 332: 'IH_PERF_SEL_RB2_FULL_VF0', + 333: 'IH_PERF_SEL_RB2_FULL_VF1', + 334: 'IH_PERF_SEL_RB2_FULL_VF2', + 335: 'IH_PERF_SEL_RB2_FULL_VF3', + 336: 'IH_PERF_SEL_RB2_FULL_VF4', + 337: 'IH_PERF_SEL_RB2_FULL_VF5', + 338: 'IH_PERF_SEL_RB2_FULL_VF6', + 339: 'IH_PERF_SEL_RB2_FULL_VF7', + 340: 'IH_PERF_SEL_RB2_FULL_VF8', + 341: 'IH_PERF_SEL_RB2_FULL_VF9', + 342: 'IH_PERF_SEL_RB2_FULL_VF10', + 343: 'IH_PERF_SEL_RB2_FULL_VF11', + 344: 'IH_PERF_SEL_RB2_FULL_VF12', + 345: 'IH_PERF_SEL_RB2_FULL_VF13', + 346: 'IH_PERF_SEL_RB2_FULL_VF14', + 347: 'IH_PERF_SEL_RB2_FULL_VF15', + 348: 'IH_PERF_SEL_RB2_OVERFLOW_VF0', + 349: 'IH_PERF_SEL_RB2_OVERFLOW_VF1', + 350: 'IH_PERF_SEL_RB2_OVERFLOW_VF2', + 351: 'IH_PERF_SEL_RB2_OVERFLOW_VF3', + 352: 'IH_PERF_SEL_RB2_OVERFLOW_VF4', + 353: 'IH_PERF_SEL_RB2_OVERFLOW_VF5', + 354: 'IH_PERF_SEL_RB2_OVERFLOW_VF6', + 355: 'IH_PERF_SEL_RB2_OVERFLOW_VF7', + 356: 'IH_PERF_SEL_RB2_OVERFLOW_VF8', + 357: 'IH_PERF_SEL_RB2_OVERFLOW_VF9', + 358: 'IH_PERF_SEL_RB2_OVERFLOW_VF10', + 359: 'IH_PERF_SEL_RB2_OVERFLOW_VF11', + 360: 'IH_PERF_SEL_RB2_OVERFLOW_VF12', + 361: 'IH_PERF_SEL_RB2_OVERFLOW_VF13', + 362: 'IH_PERF_SEL_RB2_OVERFLOW_VF14', + 363: 'IH_PERF_SEL_RB2_OVERFLOW_VF15', + 364: 'Reserved364', + 365: 'Reserved365', + 366: 'Reserved366', + 367: 'Reserved367', + 368: 'Reserved368', + 369: 'Reserved369', + 370: 'Reserved370', + 371: 'Reserved371', + 372: 'Reserved372', + 373: 'Reserved373', + 374: 'Reserved374', + 375: 'Reserved375', + 376: 'Reserved376', + 377: 'Reserved377', + 378: 'Reserved378', + 379: 'Reserved379', + 380: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', + 381: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', + 382: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', + 383: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', + 384: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', + 385: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', + 386: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', + 387: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', + 388: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', + 389: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', + 390: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', + 391: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', + 392: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', + 393: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', + 394: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', + 395: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', + 396: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', + 397: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', + 398: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', + 399: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', + 400: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', + 401: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', + 402: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', + 403: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', + 404: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', + 405: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', + 406: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', + 407: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', + 408: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', + 409: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', + 410: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', + 411: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', + 412: 'Reserved412', + 413: 'Reserved413', + 414: 'Reserved414', + 415: 'Reserved415', + 416: 'Reserved416', + 417: 'Reserved417', + 418: 'Reserved418', + 419: 'Reserved419', + 420: 'Reserved420', + 421: 'Reserved421', + 422: 'Reserved422', + 423: 'Reserved423', + 424: 'Reserved424', + 425: 'Reserved425', + 426: 'Reserved426', + 427: 'Reserved427', + 428: 'Reserved428', + 429: 'Reserved429', + 430: 'Reserved430', + 431: 'Reserved431', + 432: 'Reserved432', + 433: 'Reserved433', + 434: 'Reserved434', + 435: 'Reserved435', + 436: 'Reserved436', + 437: 'Reserved437', + 438: 'Reserved438', + 439: 'Reserved439', + 440: 'Reserved440', + 441: 'Reserved441', + 442: 'Reserved442', + 443: 'Reserved443', + 444: 'Reserved444', + 445: 'Reserved445', + 446: 'Reserved446', + 447: 'Reserved447', + 448: 'Reserved448', + 449: 'Reserved449', + 450: 'Reserved450', + 451: 'Reserved451', + 452: 'Reserved452', + 453: 'Reserved453', + 454: 'Reserved454', + 455: 'Reserved455', + 456: 'Reserved456', + 457: 'Reserved457', + 458: 'Reserved458', + 459: 'Reserved459', + 460: 'Reserved460', + 461: 'Reserved461', + 462: 'Reserved462', + 463: 'Reserved463', + 464: 'Reserved464', + 465: 'Reserved465', + 466: 'Reserved466', + 467: 'Reserved467', + 468: 'Reserved468', + 469: 'Reserved469', + 470: 'Reserved470', + 471: 'Reserved471', + 472: 'Reserved472', + 473: 'Reserved473', + 474: 'Reserved474', + 475: 'Reserved475', + 476: 'Reserved476', + 477: 'Reserved477', + 478: 'Reserved478', + 479: 'Reserved479', + 480: 'Reserved480', + 481: 'Reserved481', + 482: 'Reserved482', + 483: 'Reserved483', + 484: 'Reserved484', + 485: 'Reserved485', + 486: 'Reserved486', + 487: 'Reserved487', + 488: 'Reserved488', + 489: 'Reserved489', + 490: 'Reserved490', + 491: 'Reserved491', + 492: 'Reserved492', + 493: 'Reserved493', + 494: 'Reserved494', + 495: 'Reserved495', + 496: 'Reserved496', + 497: 'Reserved497', + 498: 'Reserved498', + 499: 'Reserved499', + 500: 'Reserved500', + 501: 'Reserved501', + 502: 'Reserved502', + 503: 'Reserved503', + 504: 'Reserved504', + 505: 'Reserved505', + 506: 'Reserved506', + 507: 'Reserved507', + 508: 'Reserved508', + 509: 'Reserved509', + 510: 'Reserved510', + 511: 'Reserved511', +} +IH_PERF_SEL_CYCLE = 0 +IH_PERF_SEL_IDLE = 1 +IH_PERF_SEL_INPUT_IDLE = 2 +IH_PERF_SEL_BUFFER_IDLE = 3 +IH_PERF_SEL_RB0_FULL = 4 +IH_PERF_SEL_RB0_OVERFLOW = 5 +IH_PERF_SEL_RB0_WPTR_WRITEBACK = 6 +IH_PERF_SEL_RB0_WPTR_WRAP = 7 +IH_PERF_SEL_RB0_RPTR_WRAP = 8 +IH_PERF_SEL_MC_WR_IDLE = 9 +IH_PERF_SEL_MC_WR_COUNT = 10 +IH_PERF_SEL_MC_WR_STALL = 11 +IH_PERF_SEL_MC_WR_CLEAN_PENDING = 12 +IH_PERF_SEL_MC_WR_CLEAN_STALL = 13 +IH_PERF_SEL_BIF_LINE0_RISING = 14 +IH_PERF_SEL_BIF_LINE0_FALLING = 15 +IH_PERF_SEL_RB1_FULL = 16 +IH_PERF_SEL_RB1_OVERFLOW = 17 +Reserved18 = 18 +IH_PERF_SEL_RB1_WPTR_WRAP = 19 +IH_PERF_SEL_RB1_RPTR_WRAP = 20 +IH_PERF_SEL_RB2_FULL = 21 +IH_PERF_SEL_RB2_OVERFLOW = 22 +Reserved23 = 23 +IH_PERF_SEL_RB2_WPTR_WRAP = 24 +IH_PERF_SEL_RB2_RPTR_WRAP = 25 +Reserved26 = 26 +Reserved27 = 27 +Reserved28 = 28 +Reserved29 = 29 +IH_PERF_SEL_RB0_FULL_VF0 = 30 +IH_PERF_SEL_RB0_FULL_VF1 = 31 +IH_PERF_SEL_RB0_FULL_VF2 = 32 +IH_PERF_SEL_RB0_FULL_VF3 = 33 +IH_PERF_SEL_RB0_FULL_VF4 = 34 +IH_PERF_SEL_RB0_FULL_VF5 = 35 +IH_PERF_SEL_RB0_FULL_VF6 = 36 +IH_PERF_SEL_RB0_FULL_VF7 = 37 +IH_PERF_SEL_RB0_FULL_VF8 = 38 +IH_PERF_SEL_RB0_FULL_VF9 = 39 +IH_PERF_SEL_RB0_FULL_VF10 = 40 +IH_PERF_SEL_RB0_FULL_VF11 = 41 +IH_PERF_SEL_RB0_FULL_VF12 = 42 +IH_PERF_SEL_RB0_FULL_VF13 = 43 +IH_PERF_SEL_RB0_FULL_VF14 = 44 +IH_PERF_SEL_RB0_FULL_VF15 = 45 +IH_PERF_SEL_RB0_OVERFLOW_VF0 = 46 +IH_PERF_SEL_RB0_OVERFLOW_VF1 = 47 +IH_PERF_SEL_RB0_OVERFLOW_VF2 = 48 +IH_PERF_SEL_RB0_OVERFLOW_VF3 = 49 +IH_PERF_SEL_RB0_OVERFLOW_VF4 = 50 +IH_PERF_SEL_RB0_OVERFLOW_VF5 = 51 +IH_PERF_SEL_RB0_OVERFLOW_VF6 = 52 +IH_PERF_SEL_RB0_OVERFLOW_VF7 = 53 +IH_PERF_SEL_RB0_OVERFLOW_VF8 = 54 +IH_PERF_SEL_RB0_OVERFLOW_VF9 = 55 +IH_PERF_SEL_RB0_OVERFLOW_VF10 = 56 +IH_PERF_SEL_RB0_OVERFLOW_VF11 = 57 +IH_PERF_SEL_RB0_OVERFLOW_VF12 = 58 +IH_PERF_SEL_RB0_OVERFLOW_VF13 = 59 +IH_PERF_SEL_RB0_OVERFLOW_VF14 = 60 +IH_PERF_SEL_RB0_OVERFLOW_VF15 = 61 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 62 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 63 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 64 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 65 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 66 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 67 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 68 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 69 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 70 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 71 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 72 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 73 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 74 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 75 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 76 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 77 +IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 78 +IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 79 +IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 80 +IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 81 +IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 82 +IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 83 +IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 84 +IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 85 +IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 86 +IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 87 +IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 88 +IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 89 +IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 90 +IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 91 +IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 92 +IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 93 +IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 94 +IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 95 +IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 96 +IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 97 +IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 98 +IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 99 +IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 100 +IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 101 +IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 102 +IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 103 +IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 104 +IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 105 +IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 106 +IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 107 +IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 108 +IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 109 +IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 110 +IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 111 +IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 112 +IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 113 +IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 114 +IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 115 +IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 116 +IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 117 +IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 118 +IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 119 +IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 120 +IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 121 +IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 122 +IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 123 +IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 124 +IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 125 +IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 126 +IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 127 +IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 128 +IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 129 +IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 130 +IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 131 +IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 132 +IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 133 +IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 134 +IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 135 +IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 136 +IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 137 +IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 138 +IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 139 +IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 140 +IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 141 +Reserved142 = 142 +Reserved143 = 143 +Reserved144 = 144 +Reserved145 = 145 +Reserved146 = 146 +Reserved147 = 147 +Reserved148 = 148 +Reserved149 = 149 +IH_PERF_SEL_CLIENT0_INT = 150 +IH_PERF_SEL_CLIENT1_INT = 151 +IH_PERF_SEL_CLIENT2_INT = 152 +IH_PERF_SEL_CLIENT3_INT = 153 +IH_PERF_SEL_CLIENT4_INT = 154 +IH_PERF_SEL_CLIENT5_INT = 155 +IH_PERF_SEL_CLIENT6_INT = 156 +IH_PERF_SEL_CLIENT7_INT = 157 +IH_PERF_SEL_CLIENT8_INT = 158 +IH_PERF_SEL_CLIENT9_INT = 159 +IH_PERF_SEL_CLIENT10_INT = 160 +IH_PERF_SEL_CLIENT11_INT = 161 +IH_PERF_SEL_CLIENT12_INT = 162 +IH_PERF_SEL_CLIENT13_INT = 163 +IH_PERF_SEL_CLIENT14_INT = 164 +IH_PERF_SEL_CLIENT15_INT = 165 +IH_PERF_SEL_CLIENT16_INT = 166 +IH_PERF_SEL_CLIENT17_INT = 167 +IH_PERF_SEL_CLIENT18_INT = 168 +IH_PERF_SEL_CLIENT19_INT = 169 +IH_PERF_SEL_CLIENT20_INT = 170 +IH_PERF_SEL_CLIENT21_INT = 171 +IH_PERF_SEL_CLIENT22_INT = 172 +IH_PERF_SEL_CLIENT23_INT = 173 +IH_PERF_SEL_CLIENT24_INT = 174 +IH_PERF_SEL_CLIENT25_INT = 175 +IH_PERF_SEL_CLIENT26_INT = 176 +IH_PERF_SEL_CLIENT27_INT = 177 +IH_PERF_SEL_CLIENT28_INT = 178 +IH_PERF_SEL_CLIENT29_INT = 179 +IH_PERF_SEL_CLIENT30_INT = 180 +IH_PERF_SEL_CLIENT31_INT = 181 +Reserved182 = 182 +Reserved183 = 183 +Reserved184 = 184 +Reserved185 = 185 +Reserved186 = 186 +Reserved187 = 187 +Reserved188 = 188 +Reserved189 = 189 +Reserved190 = 190 +Reserved191 = 191 +Reserved192 = 192 +Reserved193 = 193 +Reserved194 = 194 +Reserved195 = 195 +Reserved196 = 196 +Reserved197 = 197 +Reserved198 = 198 +Reserved199 = 199 +Reserved200 = 200 +Reserved201 = 201 +Reserved202 = 202 +Reserved203 = 203 +Reserved204 = 204 +Reserved205 = 205 +Reserved206 = 206 +Reserved207 = 207 +Reserved208 = 208 +Reserved209 = 209 +Reserved210 = 210 +Reserved211 = 211 +Reserved212 = 212 +Reserved213 = 213 +Reserved214 = 214 +Reserved215 = 215 +Reserved216 = 216 +Reserved217 = 217 +Reserved218 = 218 +Reserved219 = 219 +IH_PERF_SEL_RB1_FULL_VF0 = 220 +IH_PERF_SEL_RB1_FULL_VF1 = 221 +IH_PERF_SEL_RB1_FULL_VF2 = 222 +IH_PERF_SEL_RB1_FULL_VF3 = 223 +IH_PERF_SEL_RB1_FULL_VF4 = 224 +IH_PERF_SEL_RB1_FULL_VF5 = 225 +IH_PERF_SEL_RB1_FULL_VF6 = 226 +IH_PERF_SEL_RB1_FULL_VF7 = 227 +IH_PERF_SEL_RB1_FULL_VF8 = 228 +IH_PERF_SEL_RB1_FULL_VF9 = 229 +IH_PERF_SEL_RB1_FULL_VF10 = 230 +IH_PERF_SEL_RB1_FULL_VF11 = 231 +IH_PERF_SEL_RB1_FULL_VF12 = 232 +IH_PERF_SEL_RB1_FULL_VF13 = 233 +IH_PERF_SEL_RB1_FULL_VF14 = 234 +IH_PERF_SEL_RB1_FULL_VF15 = 235 +IH_PERF_SEL_RB1_OVERFLOW_VF0 = 236 +IH_PERF_SEL_RB1_OVERFLOW_VF1 = 237 +IH_PERF_SEL_RB1_OVERFLOW_VF2 = 238 +IH_PERF_SEL_RB1_OVERFLOW_VF3 = 239 +IH_PERF_SEL_RB1_OVERFLOW_VF4 = 240 +IH_PERF_SEL_RB1_OVERFLOW_VF5 = 241 +IH_PERF_SEL_RB1_OVERFLOW_VF6 = 242 +IH_PERF_SEL_RB1_OVERFLOW_VF7 = 243 +IH_PERF_SEL_RB1_OVERFLOW_VF8 = 244 +IH_PERF_SEL_RB1_OVERFLOW_VF9 = 245 +IH_PERF_SEL_RB1_OVERFLOW_VF10 = 246 +IH_PERF_SEL_RB1_OVERFLOW_VF11 = 247 +IH_PERF_SEL_RB1_OVERFLOW_VF12 = 248 +IH_PERF_SEL_RB1_OVERFLOW_VF13 = 249 +IH_PERF_SEL_RB1_OVERFLOW_VF14 = 250 +IH_PERF_SEL_RB1_OVERFLOW_VF15 = 251 +Reserved252 = 252 +Reserved253 = 253 +Reserved254 = 254 +Reserved255 = 255 +Reserved256 = 256 +Reserved257 = 257 +Reserved258 = 258 +Reserved259 = 259 +Reserved260 = 260 +Reserved261 = 261 +Reserved262 = 262 +Reserved263 = 263 +Reserved264 = 264 +Reserved265 = 265 +Reserved266 = 266 +Reserved267 = 267 +IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 268 +IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 269 +IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 270 +IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 271 +IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 272 +IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 273 +IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 274 +IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 275 +IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 276 +IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 277 +IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 278 +IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 279 +IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 280 +IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 281 +IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 282 +IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 283 +IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 284 +IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 285 +IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 286 +IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 287 +IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 288 +IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 289 +IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 290 +IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 291 +IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 292 +IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 293 +IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 294 +IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 295 +IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 296 +IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 297 +IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 298 +IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 299 +Reserved300 = 300 +Reserved301 = 301 +Reserved302 = 302 +Reserved303 = 303 +Reserved304 = 304 +Reserved305 = 305 +Reserved306 = 306 +Reserved307 = 307 +Reserved308 = 308 +Reserved309 = 309 +Reserved310 = 310 +Reserved311 = 311 +Reserved312 = 312 +Reserved313 = 313 +Reserved314 = 314 +Reserved315 = 315 +Reserved316 = 316 +Reserved317 = 317 +Reserved318 = 318 +Reserved319 = 319 +Reserved320 = 320 +Reserved321 = 321 +Reserved322 = 322 +Reserved323 = 323 +Reserved324 = 324 +Reserved325 = 325 +Reserved326 = 326 +Reserved327 = 327 +Reserved328 = 328 +Reserved329 = 329 +Reserved330 = 330 +Reserved331 = 331 +IH_PERF_SEL_RB2_FULL_VF0 = 332 +IH_PERF_SEL_RB2_FULL_VF1 = 333 +IH_PERF_SEL_RB2_FULL_VF2 = 334 +IH_PERF_SEL_RB2_FULL_VF3 = 335 +IH_PERF_SEL_RB2_FULL_VF4 = 336 +IH_PERF_SEL_RB2_FULL_VF5 = 337 +IH_PERF_SEL_RB2_FULL_VF6 = 338 +IH_PERF_SEL_RB2_FULL_VF7 = 339 +IH_PERF_SEL_RB2_FULL_VF8 = 340 +IH_PERF_SEL_RB2_FULL_VF9 = 341 +IH_PERF_SEL_RB2_FULL_VF10 = 342 +IH_PERF_SEL_RB2_FULL_VF11 = 343 +IH_PERF_SEL_RB2_FULL_VF12 = 344 +IH_PERF_SEL_RB2_FULL_VF13 = 345 +IH_PERF_SEL_RB2_FULL_VF14 = 346 +IH_PERF_SEL_RB2_FULL_VF15 = 347 +IH_PERF_SEL_RB2_OVERFLOW_VF0 = 348 +IH_PERF_SEL_RB2_OVERFLOW_VF1 = 349 +IH_PERF_SEL_RB2_OVERFLOW_VF2 = 350 +IH_PERF_SEL_RB2_OVERFLOW_VF3 = 351 +IH_PERF_SEL_RB2_OVERFLOW_VF4 = 352 +IH_PERF_SEL_RB2_OVERFLOW_VF5 = 353 +IH_PERF_SEL_RB2_OVERFLOW_VF6 = 354 +IH_PERF_SEL_RB2_OVERFLOW_VF7 = 355 +IH_PERF_SEL_RB2_OVERFLOW_VF8 = 356 +IH_PERF_SEL_RB2_OVERFLOW_VF9 = 357 +IH_PERF_SEL_RB2_OVERFLOW_VF10 = 358 +IH_PERF_SEL_RB2_OVERFLOW_VF11 = 359 +IH_PERF_SEL_RB2_OVERFLOW_VF12 = 360 +IH_PERF_SEL_RB2_OVERFLOW_VF13 = 361 +IH_PERF_SEL_RB2_OVERFLOW_VF14 = 362 +IH_PERF_SEL_RB2_OVERFLOW_VF15 = 363 +Reserved364 = 364 +Reserved365 = 365 +Reserved366 = 366 +Reserved367 = 367 +Reserved368 = 368 +Reserved369 = 369 +Reserved370 = 370 +Reserved371 = 371 +Reserved372 = 372 +Reserved373 = 373 +Reserved374 = 374 +Reserved375 = 375 +Reserved376 = 376 +Reserved377 = 377 +Reserved378 = 378 +Reserved379 = 379 +IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 380 +IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 381 +IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 382 +IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 383 +IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 384 +IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 385 +IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 386 +IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 387 +IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 388 +IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 389 +IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 390 +IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 391 +IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 392 +IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 393 +IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 394 +IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 395 +IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 396 +IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 397 +IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 398 +IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 399 +IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 400 +IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 401 +IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 402 +IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 403 +IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 404 +IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 405 +IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 406 +IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 407 +IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 408 +IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 409 +IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 410 +IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 411 +Reserved412 = 412 +Reserved413 = 413 +Reserved414 = 414 +Reserved415 = 415 +Reserved416 = 416 +Reserved417 = 417 +Reserved418 = 418 +Reserved419 = 419 +Reserved420 = 420 +Reserved421 = 421 +Reserved422 = 422 +Reserved423 = 423 +Reserved424 = 424 +Reserved425 = 425 +Reserved426 = 426 +Reserved427 = 427 +Reserved428 = 428 +Reserved429 = 429 +Reserved430 = 430 +Reserved431 = 431 +Reserved432 = 432 +Reserved433 = 433 +Reserved434 = 434 +Reserved435 = 435 +Reserved436 = 436 +Reserved437 = 437 +Reserved438 = 438 +Reserved439 = 439 +Reserved440 = 440 +Reserved441 = 441 +Reserved442 = 442 +Reserved443 = 443 +Reserved444 = 444 +Reserved445 = 445 +Reserved446 = 446 +Reserved447 = 447 +Reserved448 = 448 +Reserved449 = 449 +Reserved450 = 450 +Reserved451 = 451 +Reserved452 = 452 +Reserved453 = 453 +Reserved454 = 454 +Reserved455 = 455 +Reserved456 = 456 +Reserved457 = 457 +Reserved458 = 458 +Reserved459 = 459 +Reserved460 = 460 +Reserved461 = 461 +Reserved462 = 462 +Reserved463 = 463 +Reserved464 = 464 +Reserved465 = 465 +Reserved466 = 466 +Reserved467 = 467 +Reserved468 = 468 +Reserved469 = 469 +Reserved470 = 470 +Reserved471 = 471 +Reserved472 = 472 +Reserved473 = 473 +Reserved474 = 474 +Reserved475 = 475 +Reserved476 = 476 +Reserved477 = 477 +Reserved478 = 478 +Reserved479 = 479 +Reserved480 = 480 +Reserved481 = 481 +Reserved482 = 482 +Reserved483 = 483 +Reserved484 = 484 +Reserved485 = 485 +Reserved486 = 486 +Reserved487 = 487 +Reserved488 = 488 +Reserved489 = 489 +Reserved490 = 490 +Reserved491 = 491 +Reserved492 = 492 +Reserved493 = 493 +Reserved494 = 494 +Reserved495 = 495 +Reserved496 = 496 +Reserved497 = 497 +Reserved498 = 498 +Reserved499 = 499 +Reserved500 = 500 +Reserved501 = 501 +Reserved502 = 502 +Reserved503 = 503 +Reserved504 = 504 +Reserved505 = 505 +Reserved506 = 506 +Reserved507 = 507 +Reserved508 = 508 +Reserved509 = 509 +Reserved510 = 510 +Reserved511 = 511 +IH_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SEM_PERF_SEL' +SEM_PERF_SEL__enumvalues = { + 0: 'SEM_PERF_SEL_CYCLE', + 1: 'SEM_PERF_SEL_IDLE', + 2: 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', + 3: 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', + 4: 'SEM_PERF_SEL_UVD_REQ_SIGNAL', + 5: 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', + 6: 'SEM_PERF_SEL_ACP_REQ_SIGNAL', + 7: 'SEM_PERF_SEL_ISP_REQ_SIGNAL', + 8: 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', + 9: 'SEM_PERF_SEL_VP8_REQ_SIGNAL', + 10: 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', + 11: 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', + 12: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', + 13: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', + 14: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', + 15: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', + 16: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', + 17: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', + 18: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', + 19: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', + 20: 'SEM_PERF_SEL_SDMA0_REQ_WAIT', + 21: 'SEM_PERF_SEL_SDMA1_REQ_WAIT', + 22: 'SEM_PERF_SEL_UVD_REQ_WAIT', + 23: 'SEM_PERF_SEL_VCE0_REQ_WAIT', + 24: 'SEM_PERF_SEL_ACP_REQ_WAIT', + 25: 'SEM_PERF_SEL_ISP_REQ_WAIT', + 26: 'SEM_PERF_SEL_VCE1_REQ_WAIT', + 27: 'SEM_PERF_SEL_VP8_REQ_WAIT', + 28: 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', + 29: 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', + 30: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', + 31: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', + 32: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', + 33: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', + 34: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', + 35: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', + 36: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', + 37: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', + 38: 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', + 39: 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', + 40: 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', + 41: 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', + 42: 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', + 43: 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', + 44: 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', + 45: 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', + 46: 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', + 47: 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', + 48: 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', + 49: 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', + 50: 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', + 51: 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', + 52: 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', + 53: 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', + 54: 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', + 55: 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', + 56: 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', + 57: 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', + 58: 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', + 59: 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', + 60: 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', + 61: 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', + 62: 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', + 63: 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', + 64: 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', + 65: 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', + 66: 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', + 67: 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', + 68: 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', + 69: 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', + 70: 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', + 71: 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', + 72: 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', + 73: 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', + 74: 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', + 75: 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', + 76: 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', + 77: 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', + 78: 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', + 79: 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', + 80: 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', + 81: 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', + 82: 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', + 83: 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', + 84: 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', + 85: 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', + 86: 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', + 87: 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', + 88: 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', + 89: 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', + 90: 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', + 91: 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', + 92: 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', + 93: 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', + 94: 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', + 95: 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', + 96: 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', + 97: 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', + 98: 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', + 99: 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', + 100: 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', + 101: 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', + 102: 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', + 103: 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', + 104: 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', + 105: 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', + 106: 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', + 107: 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', + 108: 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', + 109: 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', + 110: 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', + 111: 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', + 112: 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', + 113: 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', + 114: 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', + 115: 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', + 116: 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', + 117: 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', + 118: 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', + 119: 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', + 120: 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', + 121: 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', + 122: 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', + 123: 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', + 124: 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', + 125: 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', + 126: 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', + 127: 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', + 128: 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', + 129: 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', + 130: 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', + 131: 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', + 132: 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', + 133: 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', + 134: 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', + 135: 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', + 136: 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', + 137: 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', + 138: 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', + 139: 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', + 140: 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', + 141: 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', + 142: 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', + 143: 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', + 144: 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', + 145: 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', + 146: 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', + 147: 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', + 148: 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', + 149: 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', + 150: 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', + 151: 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', + 152: 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', + 153: 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', + 154: 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', + 155: 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', + 156: 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', + 157: 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', + 158: 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', + 159: 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', + 160: 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', + 161: 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', + 162: 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', + 163: 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', + 164: 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', + 165: 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', + 166: 'SEM_PERF_SEL_MC_RD_REQ', + 167: 'SEM_PERF_SEL_MC_RD_RET', + 168: 'SEM_PERF_SEL_MC_WR_REQ', + 169: 'SEM_PERF_SEL_MC_WR_RET', + 170: 'SEM_PERF_SEL_ATC_REQ', + 171: 'SEM_PERF_SEL_ATC_RET', + 172: 'SEM_PERF_SEL_ATC_XNACK', + 173: 'SEM_PERF_SEL_ATC_INVALIDATION', +} +SEM_PERF_SEL_CYCLE = 0 +SEM_PERF_SEL_IDLE = 1 +SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 2 +SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 3 +SEM_PERF_SEL_UVD_REQ_SIGNAL = 4 +SEM_PERF_SEL_VCE0_REQ_SIGNAL = 5 +SEM_PERF_SEL_ACP_REQ_SIGNAL = 6 +SEM_PERF_SEL_ISP_REQ_SIGNAL = 7 +SEM_PERF_SEL_VCE1_REQ_SIGNAL = 8 +SEM_PERF_SEL_VP8_REQ_SIGNAL = 9 +SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 10 +SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 11 +SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 12 +SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 13 +SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 14 +SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 15 +SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 16 +SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 17 +SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 18 +SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 19 +SEM_PERF_SEL_SDMA0_REQ_WAIT = 20 +SEM_PERF_SEL_SDMA1_REQ_WAIT = 21 +SEM_PERF_SEL_UVD_REQ_WAIT = 22 +SEM_PERF_SEL_VCE0_REQ_WAIT = 23 +SEM_PERF_SEL_ACP_REQ_WAIT = 24 +SEM_PERF_SEL_ISP_REQ_WAIT = 25 +SEM_PERF_SEL_VCE1_REQ_WAIT = 26 +SEM_PERF_SEL_VP8_REQ_WAIT = 27 +SEM_PERF_SEL_CPG_E0_REQ_WAIT = 28 +SEM_PERF_SEL_CPG_E1_REQ_WAIT = 29 +SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 30 +SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 31 +SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 32 +SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 33 +SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 34 +SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 35 +SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 36 +SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 37 +SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 38 +SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 39 +SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 40 +SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 41 +SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 42 +SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 43 +SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 44 +SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 45 +SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 46 +SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 47 +SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 48 +SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 49 +SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 50 +SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 51 +SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 52 +SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 53 +SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 54 +SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 55 +SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 56 +SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 57 +SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 58 +SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 59 +SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 60 +SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 61 +SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 62 +SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 63 +SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 64 +SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 65 +SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 66 +SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 67 +SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 68 +SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 69 +SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 70 +SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 71 +SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 72 +SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 73 +SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 74 +SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 75 +SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 76 +SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 77 +SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 78 +SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 79 +SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 80 +SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 81 +SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 82 +SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 83 +SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 84 +SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 85 +SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 86 +SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 87 +SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 88 +SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 89 +SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 90 +SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 91 +SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 92 +SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 93 +SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 94 +SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 95 +SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 96 +SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 97 +SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 98 +SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 99 +SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 100 +SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 101 +SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 102 +SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 103 +SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 104 +SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 105 +SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 106 +SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 107 +SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 108 +SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 109 +SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 110 +SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 111 +SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 112 +SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 113 +SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 114 +SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 115 +SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 116 +SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 117 +SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 118 +SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 119 +SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 120 +SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 121 +SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 122 +SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 123 +SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 124 +SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 125 +SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 126 +SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 127 +SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 128 +SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 129 +SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 130 +SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 131 +SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 132 +SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 133 +SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 134 +SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 135 +SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 136 +SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 137 +SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 138 +SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 139 +SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 140 +SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 141 +SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 142 +SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 143 +SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 144 +SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 145 +SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 146 +SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 147 +SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 148 +SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 149 +SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 150 +SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 151 +SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 152 +SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 153 +SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 154 +SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 155 +SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 156 +SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 157 +SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 158 +SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 159 +SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 160 +SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 161 +SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 162 +SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 163 +SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 164 +SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 165 +SEM_PERF_SEL_MC_RD_REQ = 166 +SEM_PERF_SEL_MC_RD_RET = 167 +SEM_PERF_SEL_MC_WR_REQ = 168 +SEM_PERF_SEL_MC_WR_RET = 169 +SEM_PERF_SEL_ATC_REQ = 170 +SEM_PERF_SEL_ATC_RET = 171 +SEM_PERF_SEL_ATC_XNACK = 172 +SEM_PERF_SEL_ATC_INVALIDATION = 173 +SEM_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SDMA_PERF_SEL' +SDMA_PERF_SEL__enumvalues = { + 0: 'SDMA_PERF_SEL_CYCLE', + 1: 'SDMA_PERF_SEL_IDLE', + 2: 'SDMA_PERF_SEL_REG_IDLE', + 3: 'SDMA_PERF_SEL_RB_EMPTY', + 4: 'SDMA_PERF_SEL_RB_FULL', + 5: 'SDMA_PERF_SEL_RB_WPTR_WRAP', + 6: 'SDMA_PERF_SEL_RB_RPTR_WRAP', + 7: 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', + 8: 'SDMA_PERF_SEL_RB_RPTR_WB', + 9: 'SDMA_PERF_SEL_RB_CMD_IDLE', + 10: 'SDMA_PERF_SEL_RB_CMD_FULL', + 11: 'SDMA_PERF_SEL_IB_CMD_IDLE', + 12: 'SDMA_PERF_SEL_IB_CMD_FULL', + 13: 'SDMA_PERF_SEL_EX_IDLE', + 14: 'SDMA_PERF_SEL_SRBM_REG_SEND', + 15: 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 16: 'SDMA_PERF_SEL_MC_WR_IDLE', + 17: 'SDMA_PERF_SEL_MC_WR_COUNT', + 18: 'SDMA_PERF_SEL_MC_RD_IDLE', + 19: 'SDMA_PERF_SEL_MC_RD_COUNT', + 20: 'SDMA_PERF_SEL_MC_RD_RET_STALL', + 21: 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 24: 'SDMA_PERF_SEL_SEM_IDLE', + 25: 'SDMA_PERF_SEL_SEM_REQ_STALL', + 26: 'SDMA_PERF_SEL_SEM_REQ_COUNT', + 27: 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 28: 'SDMA_PERF_SEL_SEM_RESP_FAIL', + 29: 'SDMA_PERF_SEL_SEM_RESP_PASS', + 30: 'SDMA_PERF_SEL_INT_IDLE', + 31: 'SDMA_PERF_SEL_INT_REQ_STALL', + 32: 'SDMA_PERF_SEL_INT_REQ_COUNT', + 33: 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', + 34: 'SDMA_PERF_SEL_INT_RESP_RETRY', + 35: 'SDMA_PERF_SEL_NUM_PACKET', + 37: 'SDMA_PERF_SEL_CE_WREQ_IDLE', + 38: 'SDMA_PERF_SEL_CE_WR_IDLE', + 39: 'SDMA_PERF_SEL_CE_SPLIT_IDLE', + 40: 'SDMA_PERF_SEL_CE_RREQ_IDLE', + 41: 'SDMA_PERF_SEL_CE_OUT_IDLE', + 42: 'SDMA_PERF_SEL_CE_IN_IDLE', + 43: 'SDMA_PERF_SEL_CE_DST_IDLE', + 46: 'SDMA_PERF_SEL_CE_AFIFO_FULL', + 49: 'SDMA_PERF_SEL_CE_INFO_FULL', + 50: 'SDMA_PERF_SEL_CE_INFO1_FULL', + 51: 'SDMA_PERF_SEL_CE_RD_STALL', + 52: 'SDMA_PERF_SEL_CE_WR_STALL', + 53: 'SDMA_PERF_SEL_GFX_SELECT', + 54: 'SDMA_PERF_SEL_RLC0_SELECT', + 55: 'SDMA_PERF_SEL_RLC1_SELECT', + 56: 'SDMA_PERF_SEL_PAGE_SELECT', + 57: 'SDMA_PERF_SEL_CTX_CHANGE', + 58: 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', + 59: 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 60: 'SDMA_PERF_SEL_DOORBELL', + 61: 'SDMA_PERF_SEL_RD_BA_RTR', + 62: 'SDMA_PERF_SEL_WR_BA_RTR', + 63: 'SDMA_PERF_SEL_F32_L1_WR_VLD', + 64: 'SDMA_PERF_SEL_CE_L1_WR_VLD', + 65: 'SDMA_PERF_SEL_CE_L1_STALL', + 66: 'SDMA_PERF_SEL_SDMA_INVACK_NFLUSH', + 67: 'SDMA_PERF_SEL_SDMA_INVACK_FLUSH', + 68: 'SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', + 69: 'SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', + 70: 'SDMA_PERF_SEL_ATCL2_RET_XNACK', + 71: 'SDMA_PERF_SEL_ATCL2_RET_ACK', + 72: 'SDMA_PERF_SEL_ATCL2_FREE', + 73: 'SDMA_PERF_SEL_SDMA_ATCL2_SEND', + 74: 'SDMA_PERF_SEL_DMA_L1_WR_SEND', + 75: 'SDMA_PERF_SEL_DMA_L1_RD_SEND', + 76: 'SDMA_PERF_SEL_DMA_MC_WR_SEND', + 77: 'SDMA_PERF_SEL_DMA_MC_RD_SEND', + 78: 'SDMA_PERF_SEL_L1_WR_FIFO_IDLE', + 79: 'SDMA_PERF_SEL_L1_RD_FIFO_IDLE', + 80: 'SDMA_PERF_SEL_L1_WRL2_IDLE', + 81: 'SDMA_PERF_SEL_L1_RDL2_IDLE', + 82: 'SDMA_PERF_SEL_L1_WRMC_IDLE', + 83: 'SDMA_PERF_SEL_L1_RDMC_IDLE', + 84: 'SDMA_PERF_SEL_L1_WR_INV_IDLE', + 85: 'SDMA_PERF_SEL_L1_RD_INV_IDLE', + 86: 'SDMA_PERF_SEL_L1_WR_INV_EN', + 87: 'SDMA_PERF_SEL_L1_RD_INV_EN', + 88: 'SDMA_PERF_SEL_L1_WR_WAIT_INVADR', + 89: 'SDMA_PERF_SEL_L1_RD_WAIT_INVADR', + 90: 'SDMA_PERF_SEL_IS_INVREQ_ADDR_WR', + 91: 'SDMA_PERF_SEL_IS_INVREQ_ADDR_RD', + 92: 'SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', + 93: 'SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', + 94: 'SDMA_PERF_SEL_L1_INV_MIDDLE', + 254: 'SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER', + 255: 'SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER', +} +SDMA_PERF_SEL_CYCLE = 0 +SDMA_PERF_SEL_IDLE = 1 +SDMA_PERF_SEL_REG_IDLE = 2 +SDMA_PERF_SEL_RB_EMPTY = 3 +SDMA_PERF_SEL_RB_FULL = 4 +SDMA_PERF_SEL_RB_WPTR_WRAP = 5 +SDMA_PERF_SEL_RB_RPTR_WRAP = 6 +SDMA_PERF_SEL_RB_WPTR_POLL_READ = 7 +SDMA_PERF_SEL_RB_RPTR_WB = 8 +SDMA_PERF_SEL_RB_CMD_IDLE = 9 +SDMA_PERF_SEL_RB_CMD_FULL = 10 +SDMA_PERF_SEL_IB_CMD_IDLE = 11 +SDMA_PERF_SEL_IB_CMD_FULL = 12 +SDMA_PERF_SEL_EX_IDLE = 13 +SDMA_PERF_SEL_SRBM_REG_SEND = 14 +SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 +SDMA_PERF_SEL_MC_WR_IDLE = 16 +SDMA_PERF_SEL_MC_WR_COUNT = 17 +SDMA_PERF_SEL_MC_RD_IDLE = 18 +SDMA_PERF_SEL_MC_RD_COUNT = 19 +SDMA_PERF_SEL_MC_RD_RET_STALL = 20 +SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21 +SDMA_PERF_SEL_SEM_IDLE = 24 +SDMA_PERF_SEL_SEM_REQ_STALL = 25 +SDMA_PERF_SEL_SEM_REQ_COUNT = 26 +SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27 +SDMA_PERF_SEL_SEM_RESP_FAIL = 28 +SDMA_PERF_SEL_SEM_RESP_PASS = 29 +SDMA_PERF_SEL_INT_IDLE = 30 +SDMA_PERF_SEL_INT_REQ_STALL = 31 +SDMA_PERF_SEL_INT_REQ_COUNT = 32 +SDMA_PERF_SEL_INT_RESP_ACCEPTED = 33 +SDMA_PERF_SEL_INT_RESP_RETRY = 34 +SDMA_PERF_SEL_NUM_PACKET = 35 +SDMA_PERF_SEL_CE_WREQ_IDLE = 37 +SDMA_PERF_SEL_CE_WR_IDLE = 38 +SDMA_PERF_SEL_CE_SPLIT_IDLE = 39 +SDMA_PERF_SEL_CE_RREQ_IDLE = 40 +SDMA_PERF_SEL_CE_OUT_IDLE = 41 +SDMA_PERF_SEL_CE_IN_IDLE = 42 +SDMA_PERF_SEL_CE_DST_IDLE = 43 +SDMA_PERF_SEL_CE_AFIFO_FULL = 46 +SDMA_PERF_SEL_CE_INFO_FULL = 49 +SDMA_PERF_SEL_CE_INFO1_FULL = 50 +SDMA_PERF_SEL_CE_RD_STALL = 51 +SDMA_PERF_SEL_CE_WR_STALL = 52 +SDMA_PERF_SEL_GFX_SELECT = 53 +SDMA_PERF_SEL_RLC0_SELECT = 54 +SDMA_PERF_SEL_RLC1_SELECT = 55 +SDMA_PERF_SEL_PAGE_SELECT = 56 +SDMA_PERF_SEL_CTX_CHANGE = 57 +SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58 +SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59 +SDMA_PERF_SEL_DOORBELL = 60 +SDMA_PERF_SEL_RD_BA_RTR = 61 +SDMA_PERF_SEL_WR_BA_RTR = 62 +SDMA_PERF_SEL_F32_L1_WR_VLD = 63 +SDMA_PERF_SEL_CE_L1_WR_VLD = 64 +SDMA_PERF_SEL_CE_L1_STALL = 65 +SDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 66 +SDMA_PERF_SEL_SDMA_INVACK_FLUSH = 67 +SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 68 +SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 69 +SDMA_PERF_SEL_ATCL2_RET_XNACK = 70 +SDMA_PERF_SEL_ATCL2_RET_ACK = 71 +SDMA_PERF_SEL_ATCL2_FREE = 72 +SDMA_PERF_SEL_SDMA_ATCL2_SEND = 73 +SDMA_PERF_SEL_DMA_L1_WR_SEND = 74 +SDMA_PERF_SEL_DMA_L1_RD_SEND = 75 +SDMA_PERF_SEL_DMA_MC_WR_SEND = 76 +SDMA_PERF_SEL_DMA_MC_RD_SEND = 77 +SDMA_PERF_SEL_L1_WR_FIFO_IDLE = 78 +SDMA_PERF_SEL_L1_RD_FIFO_IDLE = 79 +SDMA_PERF_SEL_L1_WRL2_IDLE = 80 +SDMA_PERF_SEL_L1_RDL2_IDLE = 81 +SDMA_PERF_SEL_L1_WRMC_IDLE = 82 +SDMA_PERF_SEL_L1_RDMC_IDLE = 83 +SDMA_PERF_SEL_L1_WR_INV_IDLE = 84 +SDMA_PERF_SEL_L1_RD_INV_IDLE = 85 +SDMA_PERF_SEL_L1_WR_INV_EN = 86 +SDMA_PERF_SEL_L1_RD_INV_EN = 87 +SDMA_PERF_SEL_L1_WR_WAIT_INVADR = 88 +SDMA_PERF_SEL_L1_RD_WAIT_INVADR = 89 +SDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 90 +SDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 91 +SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 92 +SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 93 +SDMA_PERF_SEL_L1_INV_MIDDLE = 94 +SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER = 254 +SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER = 255 +SDMA_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_XDMA_LOCAL_SW_MODE' +ENUM_XDMA_LOCAL_SW_MODE__enumvalues = { + 2: 'XDMA_LOCAL_SW_MODE_SW_256B_D', + 10: 'XDMA_LOCAL_SW_MODE_SW_64KB_D', + 26: 'XDMA_LOCAL_SW_MODE_SW_64KB_D_X', +} +XDMA_LOCAL_SW_MODE_SW_256B_D = 2 +XDMA_LOCAL_SW_MODE_SW_64KB_D = 10 +XDMA_LOCAL_SW_MODE_SW_64KB_D_X = 26 +ENUM_XDMA_LOCAL_SW_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_XDMA_SLV_ALPHA_POSITION' +ENUM_XDMA_SLV_ALPHA_POSITION__enumvalues = { + 0: 'XDMA_SLV_ALPHA_POSITION_7_0', + 1: 'XDMA_SLV_ALPHA_POSITION_15_8', + 2: 'XDMA_SLV_ALPHA_POSITION_23_16', + 3: 'XDMA_SLV_ALPHA_POSITION_31_24', +} +XDMA_SLV_ALPHA_POSITION_7_0 = 0 +XDMA_SLV_ALPHA_POSITION_15_8 = 1 +XDMA_SLV_ALPHA_POSITION_23_16 = 2 +XDMA_SLV_ALPHA_POSITION_31_24 = 3 +ENUM_XDMA_SLV_ALPHA_POSITION = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_XDMA_MSTR_ALPHA_POSITION' +ENUM_XDMA_MSTR_ALPHA_POSITION__enumvalues = { + 0: 'XDMA_MSTR_ALPHA_POSITION_7_0', + 1: 'XDMA_MSTR_ALPHA_POSITION_15_8', + 2: 'XDMA_MSTR_ALPHA_POSITION_23_16', + 3: 'XDMA_MSTR_ALPHA_POSITION_31_24', +} +XDMA_MSTR_ALPHA_POSITION_7_0 = 0 +XDMA_MSTR_ALPHA_POSITION_15_8 = 1 +XDMA_MSTR_ALPHA_POSITION_23_16 = 2 +XDMA_MSTR_ALPHA_POSITION_31_24 = 3 +ENUM_XDMA_MSTR_ALPHA_POSITION = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL' +ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL__enumvalues = { + 0: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE0', + 1: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE1', + 2: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE2', + 3: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE3', + 4: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE4', + 5: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE5', +} +XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE0 = 0 +XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE1 = 1 +XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE2 = 2 +XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE3 = 3 +XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE4 = 4 +XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE5 = 5 +ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL = ctypes.c_uint32 # enum +__all__ = \ + ['ABGR_TO_A_BG_G_RB', 'ABM_SOFT_RESET', 'ABM_SOFT_RESET_0', + 'ABM_SOFT_RESET_1', 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE', + 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', 'ADDR_CONFIG_16_BANK', + 'ADDR_CONFIG_16_PIPE', 'ADDR_CONFIG_1KB_ROW', + 'ADDR_CONFIG_1_BANK', 'ADDR_CONFIG_1_GPU', + 'ADDR_CONFIG_1_LOWER_PIPES', + 'ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_1_PIPE', + 'ADDR_CONFIG_1_RB_PER_SHADER_ENGINE', + 'ADDR_CONFIG_1_SHADER_ENGINE', 'ADDR_CONFIG_2KB_ROW', + 'ADDR_CONFIG_2_BANK', 'ADDR_CONFIG_2_GPU', + 'ADDR_CONFIG_2_LOWER_PIPES', + 'ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_2_PIPE', + 'ADDR_CONFIG_2_RB_PER_SHADER_ENGINE', + 'ADDR_CONFIG_2_SHADER_ENGINE', 'ADDR_CONFIG_32_PIPE', + 'ADDR_CONFIG_4KB_ROW', 'ADDR_CONFIG_4_BANK', 'ADDR_CONFIG_4_GPU', + 'ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_4_PIPE', + 'ADDR_CONFIG_4_RB_PER_SHADER_ENGINE', + 'ADDR_CONFIG_4_SHADER_ENGINE', 'ADDR_CONFIG_8_BANK', + 'ADDR_CONFIG_8_GPU', 'ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS', + 'ADDR_CONFIG_8_PIPE', 'ADDR_CONFIG_8_SHADER_ENGINE', + 'ADDR_CONFIG_BANK_INTERLEAVE_1', 'ADDR_CONFIG_BANK_INTERLEAVE_2', + 'ADDR_CONFIG_BANK_INTERLEAVE_4', 'ADDR_CONFIG_BANK_INTERLEAVE_8', + 'ADDR_CONFIG_DISABLE_SE', 'ADDR_CONFIG_ENABLE_SE', + 'ADDR_CONFIG_GPU_TILE_128', 'ADDR_CONFIG_GPU_TILE_16', + 'ADDR_CONFIG_GPU_TILE_32', 'ADDR_CONFIG_GPU_TILE_64', + 'ADDR_CONFIG_PIPE_INTERLEAVE_1KB', + 'ADDR_CONFIG_PIPE_INTERLEAVE_256B', + 'ADDR_CONFIG_PIPE_INTERLEAVE_2KB', + 'ADDR_CONFIG_PIPE_INTERLEAVE_512B', 'ADDR_CONFIG_SE_TILE_16', + 'ADDR_CONFIG_SE_TILE_32', 'ADDR_SURF_16_BANK', 'ADDR_SURF_2_BANK', + 'ADDR_SURF_4_BANK', 'ADDR_SURF_8_BANK', 'ADDR_SURF_BANK_HEIGHT_1', + 'ADDR_SURF_BANK_HEIGHT_2', 'ADDR_SURF_BANK_HEIGHT_4', + 'ADDR_SURF_BANK_HEIGHT_8', 'ADDR_SURF_BANK_WH_1', + 'ADDR_SURF_BANK_WH_2', 'ADDR_SURF_BANK_WH_4', + 'ADDR_SURF_BANK_WH_8', 'ADDR_SURF_BANK_WIDTH_1', + 'ADDR_SURF_BANK_WIDTH_2', 'ADDR_SURF_BANK_WIDTH_4', + 'ADDR_SURF_BANK_WIDTH_8', 'ADDR_SURF_DEPTH_MICRO_TILING', + 'ADDR_SURF_DISPLAY_MICRO_TILING', 'ADDR_SURF_MACRO_ASPECT_1', + 'ADDR_SURF_MACRO_ASPECT_2', 'ADDR_SURF_MACRO_ASPECT_4', + 'ADDR_SURF_MACRO_ASPECT_8', 'ADDR_SURF_MICRO_TILING_DISPLAY', + 'ADDR_SURF_MICRO_TILING_NON_DISPLAY', 'ADDR_SURF_P16_32x32_16x16', + 'ADDR_SURF_P16_32x32_8x16', 'ADDR_SURF_P2', + 'ADDR_SURF_P2_RESERVED0', 'ADDR_SURF_P2_RESERVED1', + 'ADDR_SURF_P2_RESERVED2', 'ADDR_SURF_P4_16x16', + 'ADDR_SURF_P4_16x32', 'ADDR_SURF_P4_32x32', 'ADDR_SURF_P4_8x16', + 'ADDR_SURF_P8_16x16_8x16', 'ADDR_SURF_P8_16x32_16x16', + 'ADDR_SURF_P8_16x32_8x16', 'ADDR_SURF_P8_32x32_16x16', + 'ADDR_SURF_P8_32x32_16x32', 'ADDR_SURF_P8_32x32_8x16', + 'ADDR_SURF_P8_32x64_32x32', 'ADDR_SURF_P8_RESERVED0', + 'ADDR_SURF_ROTATED_MICRO_TILING', 'ADDR_SURF_SAMPLE_SPLIT_1', + 'ADDR_SURF_SAMPLE_SPLIT_2', 'ADDR_SURF_SAMPLE_SPLIT_4', + 'ADDR_SURF_SAMPLE_SPLIT_8', 'ADDR_SURF_THICK_MICRO_TILING', + 'ADDR_SURF_THIN_MICRO_TILING', 'ADDR_SURF_TILE_SPLIT_128B', + 'ADDR_SURF_TILE_SPLIT_1KB', 'ADDR_SURF_TILE_SPLIT_256B', + 'ADDR_SURF_TILE_SPLIT_2KB', 'ADDR_SURF_TILE_SPLIT_4KB', + 'ADDR_SURF_TILE_SPLIT_512B', 'ADDR_SURF_TILE_SPLIT_64B', + 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', + 'AFMT_AUDIO_CRC_AUTO_RESTART', 'AFMT_AUDIO_CRC_CH0_SIG', + 'AFMT_AUDIO_CRC_CH1_SIG', 'AFMT_AUDIO_CRC_CH2_SIG', + 'AFMT_AUDIO_CRC_CH3_SIG', 'AFMT_AUDIO_CRC_CH4_SIG', + 'AFMT_AUDIO_CRC_CH5_SIG', 'AFMT_AUDIO_CRC_CH6_SIG', + 'AFMT_AUDIO_CRC_CH7_SIG', 'AFMT_AUDIO_CRC_CONTROL_CH_SEL', + 'AFMT_AUDIO_CRC_CONTROL_CONT', 'AFMT_AUDIO_CRC_CONTROL_SOURCE', + 'AFMT_AUDIO_CRC_ONESHOT', 'AFMT_AUDIO_CRC_RESERVED_10', + 'AFMT_AUDIO_CRC_RESERVED_11', 'AFMT_AUDIO_CRC_RESERVED_12', + 'AFMT_AUDIO_CRC_RESERVED_13', 'AFMT_AUDIO_CRC_RESERVED_14', + 'AFMT_AUDIO_CRC_RESERVED_8', 'AFMT_AUDIO_CRC_RESERVED_9', + 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', + 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', + 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', + 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', + 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD', + 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND', + 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS', + 'AFMT_AUDIO_PACKET_SENT_DISABLED', + 'AFMT_AUDIO_PACKET_SENT_ENABLED', 'AFMT_AUDIO_SRC_CONTROL_SELECT', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', 'AFMT_AUDIO_SRC_RESERVED', + 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE', + 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', + 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', + 'AFMT_INTERRUPT_DISABLE', 'AFMT_INTERRUPT_ENABLE', + 'AFMT_INTERRUPT_STATUS_CHG_MASK', + 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', + 'AFMT_RAMP_CONTROL0_SIGN', 'AFMT_RAMP_SIGNED', + 'AFMT_RAMP_UNSIGNED', 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', + 'ALLOW_SR_ON_TRANS_REQ', 'ALLOW_SR_ON_TRANS_REQ_DISABLE', + 'ALLOW_SR_ON_TRANS_REQ_ENABLE', + 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', + 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', + 'ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER', + 'ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE', + 'AOUT_CRC_CONT', 'AOUT_CRC_CONT_EN', 'AOUT_CRC_DISABLE', + 'AOUT_CRC_ENABLE', 'AOUT_CRC_NO_RESET', 'AOUT_CRC_ONE_SHOT', + 'AOUT_CRC_RESET', 'AOUT_CRC_SOFT_RESET', 'AOUT_CRC_TEST_EN', + 'AOUT_DISABLE', 'AOUT_EN', 'AOUT_ENABLE', 'AOUT_FIFO_START_ADDR', + 'AOUT_FIFO_START_ADDR_2', 'AOUT_FIFO_START_ADDR_3', 'ARRAY_1D', + 'ARRAY_1D_TILED_THICK', 'ARRAY_1D_TILED_THIN1', 'ARRAY_2D', + 'ARRAY_2D_ALT_COLOR', 'ARRAY_2D_ALT_DEPTH', 'ARRAY_2D_COLOR', + 'ARRAY_2D_DEPTH', 'ARRAY_2D_TILED_THICK', 'ARRAY_2D_TILED_THIN1', + 'ARRAY_2D_TILED_XTHICK', 'ARRAY_3D', 'ARRAY_3D_SLICE', + 'ARRAY_3D_SLICE_COLOR', 'ARRAY_3D_TILED_THICK', + 'ARRAY_3D_TILED_THIN1', 'ARRAY_3D_TILED_XTHICK', + 'ARRAY_COLOR_TILE', 'ARRAY_DEPTH_TILE', 'ARRAY_LINEAR', + 'ARRAY_LINEAR_ALIGNED', 'ARRAY_LINEAR_GENERAL', + 'ARRAY_PRT_2D_TILED_THICK', 'ARRAY_PRT_2D_TILED_THIN1', + 'ARRAY_PRT_3D_TILED_THICK', 'ARRAY_PRT_3D_TILED_THIN1', + 'ARRAY_PRT_TILED_THICK', 'ARRAY_PRT_TILED_THIN1', 'ARRAY_TILED', + 'AUDIO_LAYOUT_0', 'AUDIO_LAYOUT_1', 'AUDIO_LAYOUT_SELECT', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 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'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', + 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', + 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', + 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', 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'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 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'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', + 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'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', + 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', + 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', + 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', + 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', + 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT', + 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', + 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', + 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE', + 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', + 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', + 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET', + 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', + 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', + 'AZ_CORB_SIZE', 'AZ_CORB_SIZE_16ENTRIES_RESERVED', + 'AZ_CORB_SIZE_256ENTRIES', 'AZ_CORB_SIZE_2ENTRIES_RESERVED', + 'AZ_CORB_SIZE_RESERVED', 'AZ_GLOBAL_CAPABILITIES', + 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', + 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', + 'AZ_LATENCY_COUNTER_CONTROL', 'AZ_LATENCY_COUNTER_NO_RESET', + 'AZ_LATENCY_COUNTER_RESET_DONE', 'AZ_RIRB_SIZE', + 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', 'AZ_RIRB_SIZE_256ENTRIES', + 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', 'AZ_RIRB_SIZE_UNDEFINED', + 'AZ_RIRB_WRITE_POINTER_DO_RESET', + 'AZ_RIRB_WRITE_POINTER_NOT_RESET', 'AZ_RIRB_WRITE_POINTER_RESET', + 'AZ_STATE_CHANGE_STATUS', + 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', + 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', 'ArrayMode', + 'Available_0x1c', 'Available_0x1d', 'BGRA_TO_BG_G_RB_A', + 'BINNER_BREAK_BATCH', 'BINNER_DROP_ASSERT', 'BINNER_PIPELINE', + 'BINNING_ALLOWED', 'BLEND_BOTH_INV_SRC_ALPHA', + 'BLEND_BOTH_SRC_ALPHA', 'BLEND_CONSTANT_ALPHA', + 'BLEND_CONSTANT_COLOR', 'BLEND_DST_ALPHA', 'BLEND_DST_COLOR', + 'BLEND_INV_SRC1_ALPHA', 'BLEND_INV_SRC1_COLOR', 'BLEND_ONE', + 'BLEND_ONE_MINUS_CONSTANT_ALPHA', + 'BLEND_ONE_MINUS_CONSTANT_COLOR', 'BLEND_ONE_MINUS_DST_ALPHA', + 'BLEND_ONE_MINUS_DST_COLOR', 'BLEND_ONE_MINUS_SRC_ALPHA', + 'BLEND_ONE_MINUS_SRC_COLOR', 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', + 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', + 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', + 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', + 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', + 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', + 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', + 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', 'BLEND_SRC1_ALPHA', + 'BLEND_SRC1_COLOR', 'BLEND_SRC_ALPHA', 'BLEND_SRC_ALPHA_SATURATE', + 'BLEND_SRC_COLOR', 'BLEND_ZERO', + 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN', + 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE', + 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE', + 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN', + 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE', + 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE', + 'BLNDV_CONTROL2_PTI_ENABLE', 'BLNDV_CONTROL2_PTI_ENABLE_FALSE', + 'BLNDV_CONTROL2_PTI_ENABLE_TRUE', + 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY', + 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE', + 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE', + 'BLNDV_CONTROL_BLND_ALPHA_MODE', + 'BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA', + 'BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY', + 'BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', + 'BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED', + 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN', + 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE', + 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE', + 'BLNDV_CONTROL_BLND_MODE', + 'BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE', + 'BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY', + 'BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY', + 'BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE', + 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE', + 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE', + 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE', + 'BLNDV_CONTROL_BLND_STEREO_POLARITY', + 'BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH', + 'BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW', + 'BLNDV_CONTROL_BLND_STEREO_TYPE', + 'BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO', + 'BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO', + 'BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO', + 'BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED', + 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT', + 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH', + 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW', + 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE', + 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE', + 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE', + 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL', + 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', + 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', + 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', + 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED', + 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL', + 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', + 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', + 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE', + 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED', + 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE', + 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE', + 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE', + 'BLNDV_SM_CONTROL2_SM_MODE', + 'BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING', + 'BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING', + 'BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING', + 'BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE', + 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN', + 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE', + 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE', + 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK', + 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE', + 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE', + 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK', + 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE', + 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE', + 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK', + 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE', + 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE', + 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK', + 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE', + 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE', + 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE', + 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE', + 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE', + 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN', + 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE', + 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE', + 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN', + 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE', + 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE', + 'BLND_CONTROL2_PTI_ENABLE', 'BLND_CONTROL2_PTI_ENABLE_FALSE', + 'BLND_CONTROL2_PTI_ENABLE_TRUE', + 'BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY', + 'BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE', + 'BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE', + 'BLND_CONTROL_BLND_ALPHA_MODE', + 'BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA', + 'BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY', + 'BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', + 'BLND_CONTROL_BLND_ALPHA_MODE_UNUSED', + 'BLND_CONTROL_BLND_FEEDTHROUGH_EN', + 'BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE', + 'BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE', 'BLND_CONTROL_BLND_MODE', + 'BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE', + 'BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY', + 'BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY', + 'BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE', + 'BLND_CONTROL_BLND_MULTIPLIED_MODE', + 'BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE', + 'BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE', + 'BLND_CONTROL_BLND_STEREO_POLARITY', + 'BLND_CONTROL_BLND_STEREO_POLARITY_HIGH', + 'BLND_CONTROL_BLND_STEREO_POLARITY_LOW', + 'BLND_CONTROL_BLND_STEREO_TYPE', + 'BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO', + 'BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO', + 'BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO', + 'BLND_CONTROL_BLND_STEREO_TYPE_UNUSED', + 'BLND_DEBUG_BLND_CNV_MUX_SELECT', + 'BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH', + 'BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW', + 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE', + 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE', + 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE', + 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL', + 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', + 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', + 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', + 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED', + 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL', + 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', + 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', + 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE', + 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED', + 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE', + 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE', + 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE', + 'BLND_SM_CONTROL2_SM_MODE', + 'BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING', + 'BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING', + 'BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING', + 'BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE', + 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN', + 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE', + 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE', + 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK', + 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE', + 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE', + 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK', + 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE', + 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE', + 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK', + 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE', + 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE', + 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK', + 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE', + 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE', + 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK', + 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE', + 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE', + 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK', + 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE', + 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE', + 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK', + 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE', + 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE', + 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK', + 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE', + 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE', + 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE', + 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE', + 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE', + 'BLOCK_CONTEXT_DONE', 'BOTTOM_OF_PIPE_TS', 'BREAK_BATCH', + 'BUF_DATA_FORMAT', 'BUF_DATA_FORMAT_10_10_10_2', + 'BUF_DATA_FORMAT_10_11_11', 'BUF_DATA_FORMAT_11_11_10', + 'BUF_DATA_FORMAT_16', 'BUF_DATA_FORMAT_16_16', + 'BUF_DATA_FORMAT_16_16_16_16', 'BUF_DATA_FORMAT_2_10_10_10', + 'BUF_DATA_FORMAT_32', 'BUF_DATA_FORMAT_32_32', + 'BUF_DATA_FORMAT_32_32_32', 'BUF_DATA_FORMAT_32_32_32_32', + 'BUF_DATA_FORMAT_8', 'BUF_DATA_FORMAT_8_8', + 'BUF_DATA_FORMAT_8_8_8_8', 'BUF_DATA_FORMAT_INVALID', + 'BUF_DATA_FORMAT_RESERVED_15', 'BUF_NUM_FORMAT', + 'BUF_NUM_FORMAT_FLOAT', 'BUF_NUM_FORMAT_SINT', + 'BUF_NUM_FORMAT_SNORM', 'BUF_NUM_FORMAT_SSCALED', + 'BUF_NUM_FORMAT_UINT', 'BUF_NUM_FORMAT_UNORM', + 'BUF_NUM_FORMAT_UNORM_UINT', 'BUF_NUM_FORMAT_USCALED', + 'BankHeight', 'BankInterleaveSize', 'BankSwapBytes', 'BankTiling', + 'BankWidth', 'BankWidthHeight', 'BinEventCntl', 'BinningMode', + 'BlendOp', 'BlendOpt', 'CACHE_FLUSH', 'CACHE_FLUSH_AND_INV_EVENT', + 'CACHE_FLUSH_AND_INV_TS_EVENT', 'CACHE_FLUSH_TS', 'CBMode', + 'CBPerfClearFilterSel', 'CBPerfOpFilterSel', 'CBPerfSel', + 'CB_DCC_DECOMPRESS', 'CB_DECOMPRESS', 'CB_DISABLE', + 'CB_ELIMINATE_FAST_CLEAR', 'CB_FMASK_DECOMPRESS', 'CB_NORMAL', + 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', + 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', + 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', + 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', + 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', + 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', + 'CB_PERF_OP_FILTER_SEL_RESOLVE', + 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', + 'CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL', + 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', 'CB_PERF_SEL_BUSY', + 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY', + 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB', + 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY', + 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB', + 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY', + 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB', + 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY', + 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB', + 'CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY', + 'CB_PERF_SEL_CC_BC_CS_FRAG_VALID', + 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', + 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', + 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 'CB_PERF_SEL_CC_CACHE_FLUSH', 'CB_PERF_SEL_CC_CACHE_HIT', + 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', + 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', + 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', + 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', + 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', + 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CC_CACHE_STALL', + 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', + 'CB_PERF_SEL_CC_CACHE_TAG_MISS', + 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', + 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', + 'CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7', + 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN', + 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT', + 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN', + 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED', + 'CB_PERF_SEL_CC_DCC_RDREQ_STALL', + 'CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL', + 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY', + 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB', + 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY', + 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB', + 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY', + 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB', + 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY', + 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB', + 'CB_PERF_SEL_CC_MC_READ_REQUEST', + 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', + 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL', + 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY', + 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB', + 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY', + 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB', + 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY', + 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB', + 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY', + 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB', + 'CB_PERF_SEL_CC_RB_FULL', 'CB_PERF_SEL_CC_SF_FULL', + 'CB_PERF_SEL_CC_SURFACE_SYNC', 'CB_PERF_SEL_CMASK_READ_DATA_0xC', + 'CB_PERF_SEL_CMASK_READ_DATA_0xD', + 'CB_PERF_SEL_CMASK_READ_DATA_0xE', + 'CB_PERF_SEL_CMASK_READ_DATA_0xF', + 'CB_PERF_SEL_CMASK_WRITE_DATA_0xC', + 'CB_PERF_SEL_CMASK_WRITE_DATA_0xD', + 'CB_PERF_SEL_CMASK_WRITE_DATA_0xE', + 'CB_PERF_SEL_CMASK_WRITE_DATA_0xF', + 'CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY', + 'CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL', + 'CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED', + 'CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 'CB_PERF_SEL_CM_CACHE_FLUSH', 'CB_PERF_SEL_CM_CACHE_HIT', + 'CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 'CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL', + 'CB_PERF_SEL_CM_CACHE_REEVICTION_STALL', + 'CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL', + 'CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED', + 'CB_PERF_SEL_CM_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CM_CACHE_STALL', + 'CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED', + 'CB_PERF_SEL_CM_CACHE_TAG_MISS', + 'CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL', + 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READY', + 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB', + 'CB_PERF_SEL_CM_FC_TILE_VALID_READY', + 'CB_PERF_SEL_CM_FC_TILE_VALID_READYB', + 'CB_PERF_SEL_CM_MC_READ_REQUEST', + 'CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_CM_MC_WRITE_REQUEST', + 'CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL', + 'CB_PERF_SEL_CM_TQ_FULL', 'CB_PERF_SEL_CORE_SCLK_VLD', + 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY', + 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB', + 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READY', + 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB', + 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READY', + 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB', + 'CB_PERF_SEL_DB_CB_TILE_VALID_READY', + 'CB_PERF_SEL_DB_CB_TILE_VALID_READYB', 'CB_PERF_SEL_DRAWN_BUSY', + 'CB_PERF_SEL_DRAWN_PIXEL', 'CB_PERF_SEL_DRAWN_QUAD', + 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', 'CB_PERF_SEL_DRAWN_TILE', + 'CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT', + 'CB_PERF_SEL_EVENT', 'CB_PERF_SEL_EVENT_CACHE_FLUSH', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', + 'CB_PERF_SEL_EVENT_CONTEXT_DONE', + 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', + 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', + 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', + 'CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY', + 'CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL', + 'CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED', + 'CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 'CB_PERF_SEL_FC_CACHE_FLUSH', 'CB_PERF_SEL_FC_CACHE_HIT', + 'CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 'CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL', + 'CB_PERF_SEL_FC_CACHE_REEVICTION_STALL', + 'CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL', + 'CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED', + 'CB_PERF_SEL_FC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_FC_CACHE_STALL', + 'CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED', + 'CB_PERF_SEL_FC_CACHE_TAG_MISS', + 'CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL', + 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY', + 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB', + 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY', + 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB', + 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY', + 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB', + 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY', + 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB', + 'CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL', + 'CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED', + 'CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 'CB_PERF_SEL_FC_DCC_CACHE_FLUSH', 'CB_PERF_SEL_FC_DCC_CACHE_HIT', + 'CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 'CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL', + 'CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL', + 'CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', + 'CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED', + 'CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS', + 'CB_PERF_SEL_FC_DCC_CACHE_STALL', + 'CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED', + 'CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS', + 'CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL', + 'CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR', + 'CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT', + 'CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS', + 'CB_PERF_SEL_FC_DOC_IS_STALLED', + 'CB_PERF_SEL_FC_DOC_MRTS_COMBINED', + 'CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED', + 'CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR', + 'CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS', + 'CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS', + 'CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS', + 'CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT', + 'CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS', + 'CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL', + 'CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS', + 'CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL', + 'CB_PERF_SEL_FC_MC_DCC_READ_REQUEST', + 'CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST', + 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_FC_MC_READ_REQUEST', + 'CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_FC_MC_WRITE_REQUEST', + 'CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED', + 'CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL', + 'CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL', + 'CB_PERF_SEL_FC_SEQUENCER_CLEAR', + 'CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR', + 'CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE', + 'CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS', + 'CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL', + 'CB_PERF_SEL_FOP_FMASK_BYPASS_STALL', + 'CB_PERF_SEL_FOP_FMASK_RAW_STALL', + 'CB_PERF_SEL_FOP_IN_VALIDB_READY', + 'CB_PERF_SEL_FOP_IN_VALIDB_READYB', + 'CB_PERF_SEL_FOP_IN_VALID_READY', + 'CB_PERF_SEL_FOP_IN_VALID_READYB', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR', + 'CB_PERF_SEL_LQUAD_NO_TILE', + 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY', + 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB', 'CB_PERF_SEL_NONE', + 'CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT', + 'CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS', + 'CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS', + 'CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS', + 'CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS', + 'CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS', + 'CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS', + 'CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', + 'CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS', + 'CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS', + 'CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST', + 'CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED', + 'CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', + 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID', + 'CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL', + 'CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT', + 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK', + 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_0', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_1', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_2', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_3', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_4', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_5', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_6', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_7', + 'CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT', + 'CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS', + 'CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS', + 'CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS', + 'CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS', + 'CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS', + 'CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7', + 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH', + 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT', + 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT', + 'CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD', + 'CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS', + 'CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK', + 'CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING', + 'CB_PERF_SEL_RBP_SPLIT_MICROTILE', + 'CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK', + 'CB_PERF_SEL_REG_SCLK0_VLD', 'CB_PERF_SEL_REG_SCLK1_VLD', + 'CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY', + 'CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT', 'CB_RESOLVE', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', + 'CENTERS_ONLY', 'CENTROIDS_AND_CENTERS', 'CENTROIDS_ONLY', + 'CHUB_TC_RET_CREDITS', 'CHUB_TC_RET_CREDITS_ENUM', + 'CLEAR_SMU_INTR', 'CLKGATE_BASE_MODE', 'CLKGATE_SM_MODE', + 'CLOCK_BRANCH_SOFT_RESET', 'CLOCK_BRANCH_SOFT_RESET_FORCE', + 'CLOCK_BRANCH_SOFT_RESET_NOOP', 'CLOCK_GATING_DISABLED', + 'CLOCK_GATING_DISABLED_IN_DCO', 'CLOCK_GATING_ENABLED', + 'CLOCK_GATING_ENABLED_IN_DCO', 'CMASK_ADDR_COMPATIBLE', + 'CMASK_ADDR_LINEAR', 'CMASK_ADDR_TILED', 'CMASK_ALPHA0_FRAG1', + 'CMASK_ALPHA0_FRAG2', 'CMASK_ALPHA0_FRAG4', 'CMASK_ALPHA0_FRAGS', + 'CMASK_ALPHA1_FRAG1', 'CMASK_ALPHA1_FRAG2', 'CMASK_ALPHA1_FRAG4', + 'CMASK_ALPHA1_FRAGS', 'CMASK_ALPHAX_FRAG1', 'CMASK_ALPHAX_FRAG2', + 'CMASK_ALPHAX_FRAG4', 'CMASK_ALPHAX_FRAGS', 'CMASK_ANY_EXPANDED', + 'CMASK_CLEAR_ALL', 'CMASK_CLEAR_NONE', 'CMASK_CLEAR_ONE', + 'CMASK_CLR00_F0', 'CMASK_CLR00_F1', 'CMASK_CLR00_F2', + 'CMASK_CLR00_FX', 'CMASK_CLR01_F0', 'CMASK_CLR01_F1', + 'CMASK_CLR01_F2', 'CMASK_CLR01_FX', 'CMASK_CLR10_F0', + 'CMASK_CLR10_F1', 'CMASK_CLR10_F2', 'CMASK_CLR10_FX', + 'CMASK_CLR11_F0', 'CMASK_CLR11_F1', 'CMASK_CLR11_F2', + 'CMASK_CLR11_FX', 'CMD_EMBEDDED_MODE_DISABLE', + 'CMD_EMBEDDED_MODE_ENABLE', 'CM_GLOBAL_PASSTHROUGH_DISBALE', + 'CM_GLOBAL_PASSTHROUGH_ENABLE', 'COEF_UPDATE_COMPLETE', + 'COEF_UPDATE_NOT_COMPLETE', 'COLOR_10_10_10_2', 'COLOR_10_11_11', + 'COLOR_11_11_10', 'COLOR_16', 'COLOR_16_16', 'COLOR_16_16_16_16', + 'COLOR_1_5_5_5', 'COLOR_24_8', 'COLOR_2_10_10_10', + 'COLOR_2_10_10_10_6E4', 'COLOR_32', 'COLOR_32_32', + 'COLOR_32_32_32_32', 'COLOR_4_4_4_4', 'COLOR_5_5_5_1', + 'COLOR_5_6_5', 'COLOR_8', 'COLOR_8_24', 'COLOR_8_8', + 'COLOR_8_8_8_8', 'COLOR_INVALID', 'COLOR_RESERVED_13', + 'COLOR_RESERVED_15', 'COLOR_RESERVED_23', 'COLOR_RESERVED_24', + 'COLOR_RESERVED_25', 'COLOR_RESERVED_26', 'COLOR_RESERVED_27', + 'COLOR_RESERVED_28', 'COLOR_RESERVED_29', 'COLOR_RESERVED_30', + 'COLOR_X24_8_32_FLOAT', 'COL_MAN_DEGAMMA_MODE', + 'COL_MAN_DENORM_CLAMP_CONTROL', 'COL_MAN_DISABLE_MULTIPLE_UPDATE', + 'COL_MAN_GAMUT_REMAP_MODE', 'COL_MAN_GLOBAL_PASSTHROUGH_ENABLE', + 'COL_MAN_INPUTCSC_CONVERT', 'COL_MAN_INPUTCSC_MODE', + 'COL_MAN_INPUTCSC_TYPE', 'COL_MAN_INPUT_GAMMA_MODE', + 'COL_MAN_MULTIPLE_UPDATE', 'COL_MAN_MULTIPLE_UPDAT_EDISABLE', + 'COL_MAN_OUTPUT_CSC_A', 'COL_MAN_OUTPUT_CSC_B', + 'COL_MAN_OUTPUT_CSC_BYPASS', 'COL_MAN_OUTPUT_CSC_MODE', + 'COL_MAN_OUTPUT_CSC_RGB', 'COL_MAN_OUTPUT_CSC_UNITY', + 'COL_MAN_OUTPUT_CSC_YCrCb601', 'COL_MAN_OUTPUT_CSC_YCrCb709', + 'COL_MAN_PRESCALE_MODE', 'COL_MAN_REGAMMA_MODE_A', + 'COL_MAN_REGAMMA_MODE_B', 'COL_MAN_REGAMMA_MODE_BYPASS', + 'COL_MAN_REGAMMA_MODE_CONTROL', 'COL_MAN_REGAMMA_MODE_ROM_A', + 'COL_MAN_REGAMMA_MODE_ROM_B', 'COL_MAN_UPDATE_LOCK', + 'COL_MAN_UPDATE_LOCKED', 'COL_MAN_UPDATE_UNLOCKED', + 'COMB_DST_MINUS_SRC', 'COMB_DST_PLUS_SRC', 'COMB_MAX_DST_SRC', + 'COMB_MIN_DST_SRC', 'COMB_SRC_MINUS_DST', 'COMPONENT_DEPTH_10BPC', + 'COMPONENT_DEPTH_12BPC', 'COMPONENT_DEPTH_16BPC', + 'COMPONENT_DEPTH_6BPC', 'COMPONENT_DEPTH_8BPC', + 'CONFIG_128B_SWAPS', 'CONFIG_1KB_ROW', 'CONFIG_1KB_ROW_OPT', + 'CONFIG_1KB_SPLIT', 'CONFIG_1KB_SWAPS', 'CONFIG_1_PIPE', + 'CONFIG_256B_GROUP', 'CONFIG_256B_SWAPS', 'CONFIG_2KB_ROW', + 'CONFIG_2KB_ROW_OPT', 'CONFIG_2KB_SPLIT', 'CONFIG_2_PIPE', + 'CONFIG_4KB_ROW', 'CONFIG_4KB_ROW_OPT', 'CONFIG_4KB_SPLIT', + 'CONFIG_4_BANK', 'CONFIG_4_PIPE', 'CONFIG_512B_GROUP', + 'CONFIG_512B_SWAPS', 'CONFIG_8KB_ROW', 'CONFIG_8KB_ROW_OPT', + 'CONFIG_8KB_SPLIT', 'CONFIG_8_BANK', 'CONFIG_8_PIPE', + 'CONFIG_SPACE1_END', 'CONFIG_SPACE1_START', 'CONFIG_SPACE2_END', + 'CONFIG_SPACE2_START', 'CONFIG_SPACE_END', 'CONFIG_SPACE_START', + 'CONTEXT_DONE', 'CONTEXT_SPACE_END', 'CONTEXT_SPACE_START', + 'CONTEXT_SUSPEND', 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', + 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', + 'CORB_READ_POINTER_RESET', + 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', + 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', 'COUNTER_RING_0', + 'COUNTER_RING_1', 'COUNTER_RING_SPLIT', 'CPC_PERFCOUNT_SEL', + 'CPC_PERF_SEL_ALWAYS_COUNT', + 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', + 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', + 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', + 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', + 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', + 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', + 'CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE', + 'CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE', + 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', + 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPC_TAG_RAM', + 'CPF_PERFCOUNT_SEL', 'CPF_PERF_SEL_ALWAYS_COUNT', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', + 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', + 'CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR', + 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', + 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', + 'CPF_PERF_SEL_GRBM_DWORDS_SENT', + 'CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS', + 'CPF_PERF_SEL_MIU_READ_REQUEST_SEND', + 'CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE', + 'CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND', + 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', + 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', + 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', + 'CPF_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPF_TAG_RAM', + 'CPG_PERFCOUNT_SEL', 'CPG_PERF_SEL_ALWAYS_COUNT', + 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', + 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU', + 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', + 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', + 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', + 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', + 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', + 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', + 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', + 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', + 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', + 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', + 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', + 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', + 'CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', + 'CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR', + 'CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL', + 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', + 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', + 'CPG_PERF_SEL_ME_PARSER_BUSY', + 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', + 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', + 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', + 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', + 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', + 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', + 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', + 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', + 'CPG_PERF_SEL_MIU_READ_REQUEST_SENT', + 'CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT', + 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', + 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', + 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', + 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', + 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', + 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', + 'CPG_PERF_SEL_RBIU_FIFO_FULL', + 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', + 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', + 'CPG_PERF_SEL_REGISTER_CLK_VALID', + 'CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS', + 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', + 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', + 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', + 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPG_TAG_RAM', + 'CP_ALPHA_TAG_RAM_SEL', 'CP_ME_ID', 'CP_PERFMON_ENABLE_MODE', + 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', + 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', + 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', + 'CP_PERFMON_ENABLE_MODE_RESERVED_1', 'CP_PERFMON_STATE', + 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', + 'CP_PERFMON_STATE_DISABLE_AND_RESET', + 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 'CP_PERFMON_STATE_RESERVED_3', 'CP_PERFMON_STATE_START_COUNTING', + 'CP_PERFMON_STATE_STOP_COUNTING', 'CP_PIPE_ID', 'CP_RING_ID', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', + 'CRTC_ADD_PIXEL', 'CRTC_ADD_PIXEL_FORCE', 'CRTC_ADD_PIXEL_NOOP', + 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN', + 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE', + 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE', + 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE', + 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE', + 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE', + 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL', + 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE', + 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT', + 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST', + 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED', + 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE', + 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE', + 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE', + 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL', + 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP', + 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL', + 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY', + 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE', + 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE', + 'CRTC_CONTROL_CRTC_MASTER_EN', + 'CRTC_CONTROL_CRTC_MASTER_EN_FALSE', + 'CRTC_CONTROL_CRTC_MASTER_EN_TRUE', + 'CRTC_CONTROL_CRTC_SOF_PULL_EN', + 'CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE', + 'CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE', + 'CRTC_CONTROL_CRTC_START_POINT_CNTL', + 'CRTC_CONTROL_CRTC_START_POINT_CNTL_DP', + 'CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL', + 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN', + 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE', + 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE', + 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN', + 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE', + 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE', + 'CRTC_CRC_CNTL_CRTC_CRC_EN', 'CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE', + 'CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE', + 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE', + 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM', + 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD', + 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM', + 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP', + 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE', + 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES', + 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS', + 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT', + 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT', + 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS', + 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', + 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B', + 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN', + 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE', + 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE', + 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE', + 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0', + 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1', + 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY', + 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE', + 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE', + 'CRTC_DROP_PIXEL', 'CRTC_DROP_PIXEL_FORCE', + 'CRTC_DROP_PIXEL_NOOP', 'CRTC_DRR_MODE_DBUF_UPDATE_MODE', + 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE', + 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL', + 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF', + 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF', + 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN', + 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE', + 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE', + 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR', + 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE', + 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE', + 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE', + 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE', + 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE', + 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE', + 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE', + 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE', + 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR', + 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE', + 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE', + 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE', + 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE', + 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE', + 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE', + 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE', + 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE', + 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT', + 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE', + 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE', + 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY', + 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE', + 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE', + 'CRTC_HORZ_REPETITION_COUNT', 'CRTC_HORZ_REPETITION_COUNT_0', + 'CRTC_HORZ_REPETITION_COUNT_1', 'CRTC_HORZ_REPETITION_COUNT_10', + 'CRTC_HORZ_REPETITION_COUNT_11', 'CRTC_HORZ_REPETITION_COUNT_12', + 'CRTC_HORZ_REPETITION_COUNT_13', 'CRTC_HORZ_REPETITION_COUNT_14', + 'CRTC_HORZ_REPETITION_COUNT_15', 'CRTC_HORZ_REPETITION_COUNT_2', + 'CRTC_HORZ_REPETITION_COUNT_3', 'CRTC_HORZ_REPETITION_COUNT_4', + 'CRTC_HORZ_REPETITION_COUNT_5', 'CRTC_HORZ_REPETITION_COUNT_6', + 'CRTC_HORZ_REPETITION_COUNT_7', 'CRTC_HORZ_REPETITION_COUNT_8', + 'CRTC_HORZ_REPETITION_COUNT_9', 'CRTC_H_SYNC_A_POL', + 'CRTC_H_SYNC_A_POL_HIGH', 'CRTC_H_SYNC_A_POL_LOW', + 'CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL', + 'CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE', + 'CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE', + 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE', + 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE', + 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE', + 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD', + 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN', + 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT', + 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2', + 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK', + 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE', + 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK', + 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE', + 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK', + 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE', + 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK', + 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE', + 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE', + 'CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE', + 'CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', + 'CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', + 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE', + 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG', + 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE', + 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL', + 'CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR', + 'CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE', + 'CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE', + 'CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR', + 'CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE', + 'CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE', + 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL', + 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', + 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', + 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', + 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', + 'CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR', + 'CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE', + 'CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE', + 'CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY', + 'CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE', + 'CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE', + 'CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN', + 'CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE', + 'CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE', + 'CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN', + 'CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE', + 'CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE', + 'CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY', + 'CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE', + 'CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_EN', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE', + 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE', + 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT', + 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO', + 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED', + 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB', + 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK', + 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE', + 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', + 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR', + 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', + 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE', + 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE', + 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', + 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', + 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE', + 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', + 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', + 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR', + 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', + 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE', + 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE', + 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', + 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', + 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE', + 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', + 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', + 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE', + 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE', + 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED', + 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA', + 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB', + 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR', + 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', + 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', + 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE', + 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE', + 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE', + 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR', + 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE', + 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE', + 'CRTC_V_SYNC_A_POL', 'CRTC_V_SYNC_A_POL_HIGH', + 'CRTC_V_SYNC_A_POL_LOW', 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL', + 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE', + 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE', + 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT', + 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE', + 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE', + 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC', + 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', + 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', + 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN', + 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE', + 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE', + 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL', + 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE', + 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE', + 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL', + 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE', + 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE', + 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK', + 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE', + 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE', + 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR', + 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE', + 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE', + 'CSDATA_ADDR_WIDTH', 'CSDATA_DATA_WIDTH', 'CSDATA_TYPE', + 'CSDATA_TYPE_EVENT', 'CSDATA_TYPE_PRIVATE', 'CSDATA_TYPE_STATE', + 'CSDATA_TYPE_TG', 'CSDATA_TYPE_WIDTH', 'CS_CONTEXT_DONE', + 'CS_DONE', 'CS_PARTIAL_FLUSH', 'CS_STAGE_ON', 'CmaskAddr', + 'CmaskCode', 'CmaskMode', 'ColorArray', 'ColorFormat', + 'ColorTransform', 'CombFunc', 'CompareFrag', 'CompareRef', + 'ConservativeZExport', 'CovToShaderSel', 'DACA_SOFT_RESET', + 'DACA_SOFT_RESET_0', 'DACA_SOFT_RESET_1', 'DAC_MUX_SELECT', + 'DAC_MUX_SELECT_DACA', 'DAC_MUX_SELECT_DACB', 'DB_CACHE_FLUSH', + 'DB_CACHE_FLUSH_AND_INV', 'DB_CACHE_FLUSH_AND_INV_EVENT', + 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', 'DB_CACHE_FLUSH_TS', + 'DB_CLK_SOFT_RESET', 'DB_CLK_SOFT_RESET_0', 'DB_CLK_SOFT_RESET_1', + 'DB_FLUSH_AND_INV_DB_DATA_TS', 'DB_FLUSH_AND_INV_DB_META', + 'DB_PEFF_SEL_prezl_tile_mem_stall', + 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', + 'DB_PERF_SEL_CB_DB_rdreq_sends', + 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', + 'DB_PERF_SEL_CB_DB_wrreq_sends', 'DB_PERF_SEL_DB_CB_lquad_busy', + 'DB_PERF_SEL_DB_CB_lquad_double_format', + 'DB_PERF_SEL_DB_CB_lquad_export_quads', + 'DB_PERF_SEL_DB_CB_lquad_fast_format', + 'DB_PERF_SEL_DB_CB_lquad_quads', 'DB_PERF_SEL_DB_CB_lquad_sends', + 'DB_PERF_SEL_DB_CB_lquad_slow_format', + 'DB_PERF_SEL_DB_CB_lquad_stalls', 'DB_PERF_SEL_DB_CB_rdret_ack', + 'DB_PERF_SEL_DB_CB_rdret_nack', 'DB_PERF_SEL_DB_CB_tile_busy', + 'DB_PERF_SEL_DB_CB_tile_sends', 'DB_PERF_SEL_DB_CB_tile_stalls', + 'DB_PERF_SEL_DB_CB_wrret_ack', 'DB_PERF_SEL_DB_CB_wrret_nack', + 'DB_PERF_SEL_DB_SC_quad_busy', + 'DB_PERF_SEL_DB_SC_quad_double_quad', + 'DB_PERF_SEL_DB_SC_quad_lit_quad', 'DB_PERF_SEL_DB_SC_quad_sends', + 'DB_PERF_SEL_DB_SC_quad_stalls', 'DB_PERF_SEL_DB_SC_quad_tiles', + 'DB_PERF_SEL_DB_SC_tile_busy', 'DB_PERF_SEL_DB_SC_tile_culled', + 'DB_PERF_SEL_DB_SC_tile_df_stalls', + 'DB_PERF_SEL_DB_SC_tile_fast_ops', + 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', + 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', + 'DB_PERF_SEL_DB_SC_tile_hier_kill', + 'DB_PERF_SEL_DB_SC_tile_no_ops', 'DB_PERF_SEL_DB_SC_tile_sends', + 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', + 'DB_PERF_SEL_DB_SC_tile_stalls', + 'DB_PERF_SEL_DB_SC_tile_tile_rate', + 'DB_PERF_SEL_DB_SC_tile_tiles', + 'DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream', + 'DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO', + 'DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow', + 'DB_PERF_SEL_DFSM_cycles_above_watermark', + 'DB_PERF_SEL_DFSM_evicted_squads_above_watermark', + 'DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark', + 'DB_PERF_SEL_DFSM_full_cleared_squads_out', + 'DB_PERF_SEL_DFSM_fully_cleared_pixels_out', + 'DB_PERF_SEL_DFSM_fully_cleared_quads_out', + 'DB_PERF_SEL_DFSM_lit_pixels_in', + 'DB_PERF_SEL_DFSM_lit_samples_in', + 'DB_PERF_SEL_DFSM_lit_samples_out', 'DB_PERF_SEL_DFSM_quads_in', + 'DB_PERF_SEL_DFSM_squads_in', + 'DB_PERF_SEL_DFSM_stalled_by_downstream', + 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', + 'DB_PERF_SEL_Depth_Tile_Cache_busy', + 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', + 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', + 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', + 'DB_PERF_SEL_Depth_Tile_Cache_event', + 'DB_PERF_SEL_Depth_Tile_Cache_flushes', + 'DB_PERF_SEL_Depth_Tile_Cache_hits', + 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', + 'DB_PERF_SEL_Depth_Tile_Cache_misses', + 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', + 'DB_PERF_SEL_Depth_Tile_Cache_sends', + 'DB_PERF_SEL_Depth_Tile_Cache_starves', + 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', + 'DB_PERF_SEL_Op_Pipe_Busy', 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', + 'DB_PERF_SEL_Op_Pipe_Postz_Busy', 'DB_PERF_SEL_Op_Pipe_Prez_Busy', + 'DB_PERF_SEL_Plane_Cache_flushes', + 'DB_PERF_SEL_Plane_Cache_frees', 'DB_PERF_SEL_Plane_Cache_hits', + 'DB_PERF_SEL_Plane_Cache_misses', + 'DB_PERF_SEL_Plane_Cache_starves', + 'DB_PERF_SEL_PostZ_Samples_failing_DB', + 'DB_PERF_SEL_PostZ_Samples_failing_S', + 'DB_PERF_SEL_PostZ_Samples_failing_Z', + 'DB_PERF_SEL_PostZ_Samples_passing_Z', + 'DB_PERF_SEL_PreZ_Samples_failing_DB', + 'DB_PERF_SEL_PreZ_Samples_failing_S', + 'DB_PERF_SEL_PreZ_Samples_failing_Z', + 'DB_PERF_SEL_PreZ_Samples_passing_Z', + 'DB_PERF_SEL_SC_DB_quad_busy', + 'DB_PERF_SEL_SC_DB_quad_killed_tiles', + 'DB_PERF_SEL_SC_DB_quad_pixels', 'DB_PERF_SEL_SC_DB_quad_sends', + 'DB_PERF_SEL_SC_DB_quad_squads', 'DB_PERF_SEL_SC_DB_quad_tiles', + 'DB_PERF_SEL_SC_DB_tile_busy', 'DB_PERF_SEL_SC_DB_tile_covered', + 'DB_PERF_SEL_SC_DB_tile_events', 'DB_PERF_SEL_SC_DB_tile_sends', + 'DB_PERF_SEL_SC_DB_tile_stalls', 'DB_PERF_SEL_SC_DB_tile_tiles', + 'DB_PERF_SEL_SH_quads_outstanding_sum', + 'DB_PERF_SEL_SX_DB_quad_busy', + 'DB_PERF_SEL_SX_DB_quad_double_format', + 'DB_PERF_SEL_SX_DB_quad_export_quads', + 'DB_PERF_SEL_SX_DB_quad_exports', + 'DB_PERF_SEL_SX_DB_quad_fast_format', + 'DB_PERF_SEL_SX_DB_quad_pixels', 'DB_PERF_SEL_SX_DB_quad_quads', + 'DB_PERF_SEL_SX_DB_quad_sends', + 'DB_PERF_SEL_SX_DB_quad_slow_format', + 'DB_PERF_SEL_SX_DB_quad_stalls', + 'DB_PERF_SEL_Stencil_Cache_flushes', + 'DB_PERF_SEL_Stencil_Cache_frees', + 'DB_PERF_SEL_Stencil_Cache_hits', + 'DB_PERF_SEL_Stencil_Cache_misses', + 'DB_PERF_SEL_Stencil_Cache_starves', + 'DB_PERF_SEL_Tile_Cache_flushes', 'DB_PERF_SEL_Tile_Cache_hits', + 'DB_PERF_SEL_Tile_Cache_mem_return_starve', + 'DB_PERF_SEL_Tile_Cache_misses', 'DB_PERF_SEL_Tile_Cache_starves', + 'DB_PERF_SEL_Tile_Cache_surface_stall', + 'DB_PERF_SEL_Z_Cache_frees', 'DB_PERF_SEL_Z_Cache_pmask_flushes', + 'DB_PERF_SEL_Z_Cache_pmask_hits', + 'DB_PERF_SEL_Z_Cache_pmask_misses', + 'DB_PERF_SEL_Z_Cache_pmask_starves', + 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', + 'DB_PERF_SEL_Z_Cache_separate_Z_hits', + 'DB_PERF_SEL_Z_Cache_separate_Z_misses', + 'DB_PERF_SEL_Z_Cache_separate_Z_starves', + 'DB_PERF_SEL_clock_main_active', + 'DB_PERF_SEL_clock_mem_export_active', + 'DB_PERF_SEL_clock_reg_active', + 'DB_PERF_SEL_depth_bounds_qtiles_culled', + 'DB_PERF_SEL_di_dt_stall', 'DB_PERF_SEL_dk_squad_busy', + 'DB_PERF_SEL_dk_squad_sends', 'DB_PERF_SEL_dk_squad_stalls', + 'DB_PERF_SEL_dk_tile_busy', 'DB_PERF_SEL_dk_tile_quad_starves', + 'DB_PERF_SEL_dk_tile_sends', 'DB_PERF_SEL_dk_tile_stalls', + 'DB_PERF_SEL_dkg_tile_rate_tile', + 'DB_PERF_SEL_dtt_sm_clash_stall', 'DB_PERF_SEL_dtt_sm_miss_stall', + 'DB_PERF_SEL_dtt_sm_slot_stall', + 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', + 'DB_PERF_SEL_esr_eot_fwd_busy', 'DB_PERF_SEL_esr_eot_fwd_forward', + 'DB_PERF_SEL_esr_eot_fwd_holding_squad', + 'DB_PERF_SEL_esr_ps_lqf_busy', 'DB_PERF_SEL_esr_ps_lqf_stall', + 'DB_PERF_SEL_esr_ps_out_busy', 'DB_PERF_SEL_esr_ps_sqq_busy', + 'DB_PERF_SEL_esr_ps_sqq_stall', 'DB_PERF_SEL_esr_ps_src_in_sends', + 'DB_PERF_SEL_esr_ps_src_in_squads', + 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', + 'DB_PERF_SEL_esr_ps_src_in_stall', + 'DB_PERF_SEL_esr_ps_src_in_tile_rate', + 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', + 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', + 'DB_PERF_SEL_esr_ps_src_out_stall', 'DB_PERF_SEL_esr_sqq_zi_busy', + 'DB_PERF_SEL_esr_sqq_zi_stall', 'DB_PERF_SEL_etr_out_busy', + 'DB_PERF_SEL_etr_out_cb_tile_stall', + 'DB_PERF_SEL_etr_out_esr_stall', + 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', + 'DB_PERF_SEL_etr_out_send', 'DB_PERF_SEL_flush_10plane', + 'DB_PERF_SEL_flush_11plane', 'DB_PERF_SEL_flush_12plane', + 'DB_PERF_SEL_flush_13plane', 'DB_PERF_SEL_flush_14plane', + 'DB_PERF_SEL_flush_15plane', 'DB_PERF_SEL_flush_16plane', + 'DB_PERF_SEL_flush_1plane', 'DB_PERF_SEL_flush_2plane', + 'DB_PERF_SEL_flush_3plane', 'DB_PERF_SEL_flush_4plane', + 'DB_PERF_SEL_flush_5plane', 'DB_PERF_SEL_flush_6plane', + 'DB_PERF_SEL_flush_7plane', 'DB_PERF_SEL_flush_8plane', + 'DB_PERF_SEL_flush_9plane', 'DB_PERF_SEL_flush_compressed', + 'DB_PERF_SEL_flush_compressed_stencil', + 'DB_PERF_SEL_flush_expanded_stencil', + 'DB_PERF_SEL_flush_expanded_z', 'DB_PERF_SEL_flush_plane_le4', + 'DB_PERF_SEL_flush_single_stencil', + 'DB_PERF_SEL_his_qtiles_culled', 'DB_PERF_SEL_hiz_qtiles_culled', + 'DB_PERF_SEL_hiz_tc_read_starved', + 'DB_PERF_SEL_hiz_tc_write_stall', + 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', + 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', + 'DB_PERF_SEL_mi_rdreq_busy', 'DB_PERF_SEL_mi_rdreq_stall', + 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', + 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', + 'DB_PERF_SEL_mi_wrreq_busy', 'DB_PERF_SEL_mi_wrreq_stall', + 'DB_PERF_SEL_planes_flushed', 'DB_PERF_SEL_postzl_full_launch', + 'DB_PERF_SEL_postzl_partial_launch', + 'DB_PERF_SEL_postzl_partial_waiting', + 'DB_PERF_SEL_postzl_se_busy', 'DB_PERF_SEL_postzl_se_stall', + 'DB_PERF_SEL_postzl_sq_pt_busy', 'DB_PERF_SEL_postzl_sq_pt_stall', + 'DB_PERF_SEL_postzl_src_in_sends', + 'DB_PERF_SEL_postzl_src_in_squads', + 'DB_PERF_SEL_postzl_src_in_squads_unrolled', + 'DB_PERF_SEL_postzl_src_in_stall', + 'DB_PERF_SEL_postzl_src_in_tile_rate', + 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', + 'DB_PERF_SEL_postzl_src_out_stall', + 'DB_PERF_SEL_postzl_tile_init_stall', + 'DB_PERF_SEL_postzl_tile_mem_stall', + 'DB_PERF_SEL_prezl_src_in_sends', + 'DB_PERF_SEL_prezl_src_in_squads', + 'DB_PERF_SEL_prezl_src_in_squads_unrolled', + 'DB_PERF_SEL_prezl_src_in_stall', + 'DB_PERF_SEL_prezl_src_in_tile_rate', + 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', + 'DB_PERF_SEL_prezl_src_out_stall', + 'DB_PERF_SEL_prezl_tile_init_stall', 'DB_PERF_SEL_qc_busy', + 'DB_PERF_SEL_qc_conflicts', 'DB_PERF_SEL_qc_full_stall', + 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', + 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', 'DB_PERF_SEL_qc_xfc', + 'DB_PERF_SEL_quad_rd_32byte_reqs', 'DB_PERF_SEL_quad_rd_busy', + 'DB_PERF_SEL_quad_rd_mi_stall', 'DB_PERF_SEL_quad_rd_panic', + 'DB_PERF_SEL_quad_rd_rw_collision', 'DB_PERF_SEL_quad_rd_sends', + 'DB_PERF_SEL_quad_rd_tag_stall', 'DB_PERF_SEL_quad_rdret_busy', + 'DB_PERF_SEL_quad_rdret_sends', 'DB_PERF_SEL_quad_wr_acks', + 'DB_PERF_SEL_quad_wr_busy', 'DB_PERF_SEL_quad_wr_coherency_stall', + 'DB_PERF_SEL_quad_wr_mi_stall', 'DB_PERF_SEL_quad_wr_sends', + 'DB_PERF_SEL_reZ_waiting_for_postZ_done', + 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', + 'DB_PERF_SEL_sc_kick_end', 'DB_PERF_SEL_sc_kick_start', + 'DB_PERF_SEL_tcp_dispatcher_flushes', + 'DB_PERF_SEL_tcp_dispatcher_reads', + 'DB_PERF_SEL_tcp_prefetcher_flushes', + 'DB_PERF_SEL_tcp_prefetcher_reads', + 'DB_PERF_SEL_tcp_preloader_flushes', + 'DB_PERF_SEL_tcp_preloader_reads', 'DB_PERF_SEL_tile_rd_sends', + 'DB_PERF_SEL_tile_wr_acks', 'DB_PERF_SEL_tile_wr_sends', + 'DB_PERF_SEL_tiles_compressed_to_decompressed', + 'DB_PERF_SEL_tiles_decomp_on_expclear', + 'DB_PERF_SEL_tiles_s_clear_on_expclear', + 'DB_PERF_SEL_tiles_stencil_fully_summarized', + 'DB_PERF_SEL_tiles_z_clear_on_expclear', + 'DB_PERF_SEL_tiles_z_fully_summarized', 'DB_PERF_SEL_tl_busy', + 'DB_PERF_SEL_tl_dtc_read_starved', 'DB_PERF_SEL_tl_events', + 'DB_PERF_SEL_tl_expand_squads', + 'DB_PERF_SEL_tl_flush_expand_squads', + 'DB_PERF_SEL_tl_in_fast_z_stall', + 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', + 'DB_PERF_SEL_tl_in_xfc', 'DB_PERF_SEL_tl_out_squads', + 'DB_PERF_SEL_tl_out_xfc', 'DB_PERF_SEL_tl_postZ_noop_squads', + 'DB_PERF_SEL_tl_postZ_squads', 'DB_PERF_SEL_tl_preZ_noop_squads', + 'DB_PERF_SEL_tl_preZ_squads', + 'DB_PERF_SEL_tl_stencil_locked_stall', + 'DB_PERF_SEL_tl_stencil_stall', 'DB_PERF_SEL_tl_summarize_squads', + 'DB_PERF_SEL_tl_tile_ops', 'DB_PERF_SEL_tl_z_decompress_stall', + 'DB_PERF_SEL_tl_z_fetch_stall', 'DB_PERF_SEL_ts_tc_update_stall', + 'DB_PERF_SEL_tsc_insert_summarize_stall', + 'DB_PERF_SEL_zf_plane_multicycle', 'DCCG_AUDIO_DTO0_SOURCE_SEL', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', + 'DCCG_AUDIO_DTO2_SOURCE_SEL', 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', + 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1', 'DCCG_AUDIO_DTO_SEL', + 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', + 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', + 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', + 'DCCG_AUDIO_DTO_USE_512FBR_DTO', + 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', 'DCCG_DBG_BLOCK_SEL', + 'DCCG_DBG_BLOCK_SEL_DCCG', 'DCCG_DBG_BLOCK_SEL_PMON', + 'DCCG_DBG_BLOCK_SEL_PMON2', 'DCCG_DBG_EN', 'DCCG_DBG_EN_DISABLE', + 'DCCG_DBG_EN_ENABLE', 'DCCG_DEEP_COLOR_CNTL', + 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', + 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', 'DCCG_DEEP_COLOR_DTO_DISABLE', + 'DCCG_FIFO_ERRDET_OVR_DISABLE', 'DCCG_FIFO_ERRDET_OVR_EN', + 'DCCG_FIFO_ERRDET_OVR_ENABLE', 'DCCG_FIFO_ERRDET_RESET', + 'DCCG_FIFO_ERRDET_RESET_FORCE', 'DCCG_FIFO_ERRDET_RESET_NOOP', + 'DCCG_FIFO_ERRDET_STATE', 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', + 'DCCG_FIFO_ERRDET_STATE_DETECTION', 'DCCG_PERF_CRTC_SELECT', + 'DCCG_PERF_MODE_HSYNC', 'DCCG_PERF_MODE_HSYNC_NOOP', + 'DCCG_PERF_MODE_HSYNC_START', 'DCCG_PERF_MODE_VSYNC', + 'DCCG_PERF_MODE_VSYNC_NOOP', 'DCCG_PERF_MODE_VSYNC_START', + 'DCCG_PERF_RUN', 'DCCG_PERF_RUN_NOOP', 'DCCG_PERF_RUN_START', + 'DCCG_PERF_SEL_CRTC0', 'DCCG_PERF_SEL_CRTC1', + 'DCCG_PERF_SEL_CRTC2', 'DCCG_PERF_SEL_CRTC3', + 'DCCG_PERF_SEL_CRTC4', 'DCCG_PERF_SEL_CRTC5', 'DCC_CT_AUTO', + 'DCC_CT_NONE', 'DCIOCHIP_2BIT_DISABLE', 'DCIOCHIP_2BIT_ENABLE', + 'DCIOCHIP_4BIT_DISABLE', 'DCIOCHIP_4BIT_ENABLE', + 'DCIOCHIP_5BIT_DISABLE', 'DCIOCHIP_5BIT_ENABLE', + 'DCIOCHIP_AUXSLAVE_PAD_MODE', 'DCIOCHIP_AUXSLAVE_PAD_MODE_AUX', + 'DCIOCHIP_AUXSLAVE_PAD_MODE_I2C', 'DCIOCHIP_AUX_CSEL0P9', + 'DCIOCHIP_AUX_CSEL1P1', 'DCIOCHIP_AUX_CSEL_DEC0P9', + 'DCIOCHIP_AUX_CSEL_DEC1P0', 'DCIOCHIP_AUX_CSEL_INC1P0', + 'DCIOCHIP_AUX_CSEL_INC1P1', 'DCIOCHIP_AUX_FALLSLEWSEL', + 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', + 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', + 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', 'DCIOCHIP_AUX_RSEL0P9', + 'DCIOCHIP_AUX_RSEL1P1', 'DCIOCHIP_AUX_RSEL_DEC0P9', + 'DCIOCHIP_AUX_RSEL_DEC1P0', 'DCIOCHIP_AUX_RSEL_INC1P0', + 'DCIOCHIP_AUX_RSEL_INC1P1', 'DCIOCHIP_AUX_SPIKESEL', + 'DCIOCHIP_AUX_SPIKESEL_10NS', 'DCIOCHIP_AUX_SPIKESEL_50NS', + 'DCIOCHIP_DVO_VREFPON', 'DCIOCHIP_DVO_VREFPON_DISABLE', + 'DCIOCHIP_DVO_VREFPON_ENABLE', 'DCIOCHIP_DVO_VREFSEL', + 'DCIOCHIP_DVO_VREFSEL_EXTERNAL', 'DCIOCHIP_DVO_VREFSEL_ONCHIP', + 'DCIOCHIP_ENABLE_2BIT', 'DCIOCHIP_ENABLE_4BIT', + 'DCIOCHIP_ENABLE_5BIT', 'DCIOCHIP_GPIO_I2C_DISABLE', + 'DCIOCHIP_GPIO_I2C_DRIVE', 'DCIOCHIP_GPIO_I2C_DRIVE_HIGH', + 'DCIOCHIP_GPIO_I2C_DRIVE_LOW', 'DCIOCHIP_GPIO_I2C_EN', + 'DCIOCHIP_GPIO_I2C_ENABLE', 'DCIOCHIP_GPIO_I2C_MASK', + 'DCIOCHIP_GPIO_I2C_MASK_DISABLE', 'DCIOCHIP_GPIO_I2C_MASK_ENABLE', + 'DCIOCHIP_GPIO_MASK_EN', 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', + 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', 'DCIOCHIP_HPD_SEL', + 'DCIOCHIP_HPD_SEL_ASYNC', 'DCIOCHIP_HPD_SEL_CLOCKED', + 'DCIOCHIP_INVERT', 'DCIOCHIP_MASIK_5BIT_DISABLE', + 'DCIOCHIP_MASIK_5BIT_ENABLE', 'DCIOCHIP_MASK', + 'DCIOCHIP_MASK_2BIT', 'DCIOCHIP_MASK_2BIT_DISABLE', + 'DCIOCHIP_MASK_2BIT_ENABLE', 'DCIOCHIP_MASK_4BIT', + 'DCIOCHIP_MASK_4BIT_DISABLE', 'DCIOCHIP_MASK_4BIT_ENABLE', + 'DCIOCHIP_MASK_5BIT', 'DCIOCHIP_MASK_DISABLE', + 'DCIOCHIP_MASK_ENABLE', 'DCIOCHIP_PAD_MODE', + 'DCIOCHIP_PAD_MODE_DDC', 'DCIOCHIP_PAD_MODE_DP', 'DCIOCHIP_PD_EN', + 'DCIOCHIP_PD_EN_ALLOW', 'DCIOCHIP_PD_EN_NOTALLOW', + 'DCIOCHIP_POL_INVERT', 'DCIOCHIP_POL_NON_INVERT', + 'DCIOCHIP_REF_27_SRC_SEL', + 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', + 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', + 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', + 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', 'DCIOCHIP_SPDIF1_IMODE', + 'DCIOCHIP_SPDIF1_IMODE_OE_A', 'DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO', + 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE', + 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN', + 'DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT', + 'DCIO_BL_PWM_CNTL_BL_PWM_EN', + 'DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN', 'DCIO_BL_PWM_DISABLE', + 'DCIO_BL_PWM_ENABLE', 'DCIO_BL_PWM_FRACTIONAL_DISABLE', + 'DCIO_BL_PWM_FRACTIONAL_ENABLE', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', + 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', + 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN', + 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', + 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN', + 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', + 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', + 'DCIO_BL_PWM_GRP1_REG_LOCK', 'DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE', + 'DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE', + 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START', + 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', + 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', + 'DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE', + 'DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE', + 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL', + 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM', + 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL', + 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS', 'DCIO_DACA_SOFT_RESET', + 'DCIO_DACA_SOFT_RESET_ASSERT', 'DCIO_DACA_SOFT_RESET_DEASSERT', + 'DCIO_DBG_ASYNC_4BIT_SEL', 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', + 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', + 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', + 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', + 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', + 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', + 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', 'DCIO_DBG_ASYNC_BLOCK_SEL', + 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', + 'DCIO_DBG_ASYNC_BLOCK_SEL_DCO', + 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', + 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', + 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', + 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', + 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', + 'DCIO_DCO_DCFE_EXT_VSYNC_MUX', 'DCIO_DCO_EXT_VSYNC_MASK', + 'DCIO_DCRXPHY_SOFT_RESET', 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', + 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', + 'DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN', + 'DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN', + 'DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN', 'DCIO_DC_GENERICA_SEL', + 'DCIO_DC_GENERICB_SEL', + 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL', + 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL', + 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL', + 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL', + 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL', + 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL', + 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP', + 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN', + 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS', + 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE', + 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE', + 'DCIO_DC_GPIO_MACRO_DEBUG', 'DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF', + 'DCIO_DC_GPIO_MACRO_DEBUG_NORMAL', + 'DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2', + 'DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3', + 'DCIO_DC_GPIO_VIP_DEBUG', 'DCIO_DC_GPIO_VIP_DEBUG_CG_BIG', + 'DCIO_DC_GPIO_VIP_DEBUG_NORMAL', 'DCIO_DC_GPU_TIMER_READ_SELECT', + 'DCIO_DC_GPU_TIMER_START_POSITION', + 'DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS', + 'DCIO_DC_PAD_EXTERN_SIG_SEL', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_MVP', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA', + 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL', + 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL', + 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', + 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', 'DCIO_DPCS_INTERRUPT_DISABLE', + 'DCIO_DPCS_INTERRUPT_ENABLE', 'DCIO_DPCS_INTERRUPT_MASK', + 'DCIO_DPCS_INTERRUPT_TYPE', + 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', + 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', 'DCIO_DPHY_LANE_SEL', + 'DCIO_DPHY_LANE_SEL_LANE0', 'DCIO_DPHY_LANE_SEL_LANE1', + 'DCIO_DPHY_LANE_SEL_LANE2', 'DCIO_DPHY_LANE_SEL_LANE3', + 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', + 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', 'DCIO_DSYNC_SOFT_RESET', + 'DCIO_DSYNC_SOFT_RESET_ASSERT', 'DCIO_DSYNC_SOFT_RESET_DEASSERT', + 'DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE', + 'DCIO_DVO_ALTER_MAPPING_EN_DEFAULT', 'DCIO_EXT_VSYNC_MASK_NONE', + 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', 'DCIO_EXT_VSYNC_MASK_PIPE0', + 'DCIO_EXT_VSYNC_MASK_PIPE1', 'DCIO_EXT_VSYNC_MASK_PIPE2', + 'DCIO_EXT_VSYNC_MASK_PIPE3', 'DCIO_EXT_VSYNC_MASK_PIPE4', + 'DCIO_EXT_VSYNC_MASK_PIPE5', 'DCIO_EXT_VSYNC_MUX_CRTC0', + 'DCIO_EXT_VSYNC_MUX_CRTC1', 'DCIO_EXT_VSYNC_MUX_CRTC2', + 'DCIO_EXT_VSYNC_MUX_CRTC3', 'DCIO_EXT_VSYNC_MUX_CRTC4', + 'DCIO_EXT_VSYNC_MUX_CRTC5', 'DCIO_EXT_VSYNC_MUX_GENERICB', + 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', + 'DCIO_GENERICA_SEL_DACA_FIELD_NUMBER', + 'DCIO_GENERICA_SEL_DACA_PIXCLK', + 'DCIO_GENERICA_SEL_DACA_STEREOSYNC', + 'DCIO_GENERICA_SEL_DACB_FIELD_NUMBER', + 'DCIO_GENERICA_SEL_DACB_PIXCLK', 'DCIO_GENERICA_SEL_DVOA_CTL3', + 'DCIO_GENERICA_SEL_DVOA_STEREOSYNC', + 'DCIO_GENERICA_SEL_GENERICA_DCCG', + 'DCIO_GENERICA_SEL_GENERICA_DPRX', + 'DCIO_GENERICA_SEL_GENERICB_DPRX', 'DCIO_GENERICA_SEL_P1_PLLCLK', + 'DCIO_GENERICA_SEL_P2_PLLCLK', 'DCIO_GENERICA_SEL_STEREOSYNC', + 'DCIO_GENERICA_SEL_SYNCEN', 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK', + 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2', + 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK', + 'DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK', + 'DCIO_GENERICB_SEL_DACA_FIELD_NUMBER', + 'DCIO_GENERICB_SEL_DACA_PIXCLK', + 'DCIO_GENERICB_SEL_DACA_STEREOSYNC', + 'DCIO_GENERICB_SEL_DACB_FIELD_NUMBER', + 'DCIO_GENERICB_SEL_DACB_PIXCLK', 'DCIO_GENERICB_SEL_DVOA_CTL3', + 'DCIO_GENERICB_SEL_DVOA_STEREOSYNC', + 'DCIO_GENERICB_SEL_GENERICB_DCCG', 'DCIO_GENERICB_SEL_P1_PLLCLK', + 'DCIO_GENERICB_SEL_P2_PLLCLK', 'DCIO_GENERICB_SEL_STEREOSYNC', + 'DCIO_GENERICB_SEL_SYNCEN', 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK', + 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2', + 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK', + 'DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK', 'DCIO_GENLK_CLK_GSL_MASK', + 'DCIO_GENLK_CLK_GSL_MASK_NO', 'DCIO_GENLK_CLK_GSL_MASK_STEREO', + 'DCIO_GENLK_CLK_GSL_MASK_TIMING', + 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', + 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', + 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', + 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', + 'DCIO_GENLK_VSYNC_GSL_MASK', 'DCIO_GENLK_VSYNC_GSL_MASK_NO', + 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', + 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE', + 'DCIO_GPU_TIMER_START_0_END_27', 'DCIO_GPU_TIMER_START_10_END_37', + 'DCIO_GPU_TIMER_START_1_END_28', 'DCIO_GPU_TIMER_START_2_END_29', + 'DCIO_GPU_TIMER_START_3_END_30', 'DCIO_GPU_TIMER_START_4_END_31', + 'DCIO_GPU_TIMER_START_6_END_33', 'DCIO_GPU_TIMER_START_8_END_35', + 'DCIO_GSL0_GLOBAL_UNLOCK_SEL', + 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', + 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK', + 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION', + 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', + 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', + 'DCIO_GSL0_TIMING_SYNC_SEL', + 'DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK', + 'DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC', + 'DCIO_GSL0_TIMING_SYNC_SEL_PIPE', + 'DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A', + 'DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B', + 'DCIO_GSL1_GLOBAL_UNLOCK_SEL', + 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', + 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK', + 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION', + 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', + 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', + 'DCIO_GSL1_TIMING_SYNC_SEL', + 'DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK', + 'DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC', + 'DCIO_GSL1_TIMING_SYNC_SEL_PIPE', + 'DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A', + 'DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B', + 'DCIO_GSL2_GLOBAL_UNLOCK_SEL', + 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', + 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK', + 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION', + 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', + 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', + 'DCIO_GSL2_TIMING_SYNC_SEL', + 'DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK', + 'DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC', + 'DCIO_GSL2_TIMING_SYNC_SEL_PIPE', + 'DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A', + 'DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B', 'DCIO_GSL_SEL', + 'DCIO_GSL_SEL_GROUP_0', 'DCIO_GSL_SEL_GROUP_1', + 'DCIO_GSL_SEL_GROUP_2', 'DCIO_GSL_VSYNC_SEL', + 'DCIO_GSL_VSYNC_SEL_PIPE0', 'DCIO_GSL_VSYNC_SEL_PIPE1', + 'DCIO_GSL_VSYNC_SEL_PIPE2', 'DCIO_GSL_VSYNC_SEL_PIPE3', + 'DCIO_GSL_VSYNC_SEL_PIPE4', 'DCIO_GSL_VSYNC_SEL_PIPE5', + 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', + 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', + 'DCIO_IMPCAL_STEP_DELAY', 'DCIO_IMPCAL_STEP_DELAY_10us', + 'DCIO_IMPCAL_STEP_DELAY_11us', 'DCIO_IMPCAL_STEP_DELAY_12us', + 'DCIO_IMPCAL_STEP_DELAY_13us', 'DCIO_IMPCAL_STEP_DELAY_14us', + 'DCIO_IMPCAL_STEP_DELAY_15us', 'DCIO_IMPCAL_STEP_DELAY_16us', + 'DCIO_IMPCAL_STEP_DELAY_1us', 'DCIO_IMPCAL_STEP_DELAY_2us', + 'DCIO_IMPCAL_STEP_DELAY_3us', 'DCIO_IMPCAL_STEP_DELAY_4us', + 'DCIO_IMPCAL_STEP_DELAY_5us', 'DCIO_IMPCAL_STEP_DELAY_6us', + 'DCIO_IMPCAL_STEP_DELAY_7us', 'DCIO_IMPCAL_STEP_DELAY_8us', + 'DCIO_IMPCAL_STEP_DELAY_9us', 'DCIO_LVTMA_BLON_OFF', + 'DCIO_LVTMA_BLON_ON', 'DCIO_LVTMA_BLON_POL_INVERT', + 'DCIO_LVTMA_BLON_POL_NON_INVERT', 'DCIO_LVTMA_DIGON_OFF', + 'DCIO_LVTMA_DIGON_ON', 'DCIO_LVTMA_DIGON_POL_INVERT', + 'DCIO_LVTMA_DIGON_POL_NON_INVERT', + 'DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN', + 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON', + 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL', + 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON', + 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL', + 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL', + 'DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE', + 'DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN', + 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE', + 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE', + 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF', + 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON', + 'DCIO_LVTMA_SYNCEN_POL_INVERT', + 'DCIO_LVTMA_SYNCEN_POL_NON_INVERT', + 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON', + 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE', + 'DCIO_MVP_PIXEL_SRC_STATUS_CRTC', + 'DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA', + 'DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE', + 'DCIO_MVP_PIXEL_SRC_STATUS_LB', 'DCIO_SWAPLOCK_A_GSL_MASK', + 'DCIO_SWAPLOCK_A_GSL_MASK_NO', 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', + 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', 'DCIO_SWAPLOCK_B_GSL_MASK', + 'DCIO_SWAPLOCK_B_GSL_MASK_NO', 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', + 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', 'DCIO_TEST_CLK_SEL_DISPCLK', + 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', 'DCIO_TEST_CLK_SEL_SCLK', + 'DCIO_UNIPHYA_FBDIV_CLK', 'DCIO_UNIPHYA_FBDIV_SSC_CLK', + 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYA_TEST_REFDIV_CLK', 'DCIO_UNIPHYB_FBDIV_CLK', + 'DCIO_UNIPHYB_FBDIV_SSC_CLK', 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYB_TEST_REFDIV_CLK', 'DCIO_UNIPHYC_FBDIV_CLK', + 'DCIO_UNIPHYC_FBDIV_SSC_CLK', 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYC_TEST_REFDIV_CLK', 'DCIO_UNIPHYD_FBDIV_CLK', + 'DCIO_UNIPHYD_FBDIV_SSC_CLK', 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYD_TEST_REFDIV_CLK', 'DCIO_UNIPHYE_FBDIV_CLK', + 'DCIO_UNIPHYE_FBDIV_SSC_CLK', 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYE_TEST_REFDIV_CLK', 'DCIO_UNIPHYF_FBDIV_CLK', + 'DCIO_UNIPHYF_FBDIV_SSC_CLK', 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYF_TEST_REFDIV_CLK', 'DCIO_UNIPHYG_FBDIV_CLK', + 'DCIO_UNIPHYG_FBDIV_SSC_CLK', 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYG_TEST_REFDIV_CLK', 'DCIO_UNIPHYLPA_FBDIV_CLK', + 'DCIO_UNIPHYLPA_FBDIV_SSC_CLK', + 'DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYLPA_TEST_REFDIV_CLK', 'DCIO_UNIPHYLPB_FBDIV_CLK', + 'DCIO_UNIPHYLPB_FBDIV_SSC_CLK', + 'DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYLPB_TEST_REFDIV_CLK', 'DCIO_UNIPHY_CHANNEL_INVERTED', + 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', 'DCIO_UNIPHY_IMPCAL_SEL', + 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', + 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', + 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT', + 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK', + 'DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS', + 'DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE', + 'DCIO_VIP_ALTER_MAPPING_EN_DEFAULT', 'DCIO_VIP_MUX_EN_DVO', + 'DCIO_VIP_MUX_EN_VIP', 'DCO_DBG_BLOCK_SEL', + 'DCO_DBG_BLOCK_SEL_ABM', 'DCO_DBG_BLOCK_SEL_AUDIO_OUT', + 'DCO_DBG_BLOCK_SEL_AUX0', 'DCO_DBG_BLOCK_SEL_AUX1', + 'DCO_DBG_BLOCK_SEL_AUX2', 'DCO_DBG_BLOCK_SEL_AUX3', + 'DCO_DBG_BLOCK_SEL_AUX4', 'DCO_DBG_BLOCK_SEL_AUX5', + 'DCO_DBG_BLOCK_SEL_DAC', 'DCO_DBG_BLOCK_SEL_DCO', + 'DCO_DBG_BLOCK_SEL_DIGA', 'DCO_DBG_BLOCK_SEL_DIGB', + 'DCO_DBG_BLOCK_SEL_DIGC', 'DCO_DBG_BLOCK_SEL_DIGD', + 'DCO_DBG_BLOCK_SEL_DIGE', 'DCO_DBG_BLOCK_SEL_DIGF', + 'DCO_DBG_BLOCK_SEL_DIGFE_A', 'DCO_DBG_BLOCK_SEL_DIGFE_B', + 'DCO_DBG_BLOCK_SEL_DIGFE_C', 'DCO_DBG_BLOCK_SEL_DIGFE_D', + 'DCO_DBG_BLOCK_SEL_DIGFE_E', 'DCO_DBG_BLOCK_SEL_DIGFE_F', + 'DCO_DBG_BLOCK_SEL_DIGFE_G', 'DCO_DBG_BLOCK_SEL_DIGG', + 'DCO_DBG_BLOCK_SEL_DIGLPA', 'DCO_DBG_BLOCK_SEL_DIGLPB', + 'DCO_DBG_BLOCK_SEL_DIGLPFEA', 'DCO_DBG_BLOCK_SEL_DIGLPFEB', + 'DCO_DBG_BLOCK_SEL_DPA', 'DCO_DBG_BLOCK_SEL_DPB', + 'DCO_DBG_BLOCK_SEL_DPC', 'DCO_DBG_BLOCK_SEL_DPD', + 'DCO_DBG_BLOCK_SEL_DPE', 'DCO_DBG_BLOCK_SEL_DPF', + 'DCO_DBG_BLOCK_SEL_DPFE_A', 'DCO_DBG_BLOCK_SEL_DPFE_B', + 'DCO_DBG_BLOCK_SEL_DPFE_C', 'DCO_DBG_BLOCK_SEL_DPFE_D', + 'DCO_DBG_BLOCK_SEL_DPFE_E', 'DCO_DBG_BLOCK_SEL_DPFE_F', + 'DCO_DBG_BLOCK_SEL_DPFE_G', 'DCO_DBG_BLOCK_SEL_DPG', + 'DCO_DBG_BLOCK_SEL_DPLPA', 'DCO_DBG_BLOCK_SEL_DPLPB', + 'DCO_DBG_BLOCK_SEL_DPLPFEA', 'DCO_DBG_BLOCK_SEL_DPLPFEB', + 'DCO_DBG_BLOCK_SEL_DVO', 'DCO_DBG_BLOCK_SEL_FMT0', + 'DCO_DBG_BLOCK_SEL_FMT1', 'DCO_DBG_BLOCK_SEL_FMT2', + 'DCO_DBG_BLOCK_SEL_FMT3', 'DCO_DBG_BLOCK_SEL_FMT4', + 'DCO_DBG_BLOCK_SEL_FMT5', 'DCO_DBG_BLOCK_SEL_MVP', + 'DCO_DBG_BLOCK_SEL_PERFMON_DCO', + 'DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE', + 'DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', + 'DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', + 'DCP_ALPHA_ROUND_TRUNC_MODE', 'DCP_ALPHA_ROUND_TRUNC_MODE_ROUND', + 'DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC', 'DCP_CRC_ENABLE', + 'DCP_CRC_ENABLE_FALSE', 'DCP_CRC_ENABLE_TRUE', 'DCP_CRC_LINE_SEL', + 'DCP_CRC_LINE_SEL_BOTH', 'DCP_CRC_LINE_SEL_EVEN', + 'DCP_CRC_LINE_SEL_ODD', 'DCP_CRC_LINE_SEL_RESERVED', + 'DCP_CRC_SOURCE_SEL', 'DCP_CRC_SOURCE_SEL_INPUT_H32', + 'DCP_CRC_SOURCE_SEL_INPUT_L32', 'DCP_CRC_SOURCE_SEL_OUTPUT_CNTL', + 'DCP_CRC_SOURCE_SEL_OUTPUT_PIX', 'DCP_CUR2_INV_TRANS_CLAMP', + 'DCP_CUR2_INV_TRANS_CLAMP_FALSE', 'DCP_CUR2_INV_TRANS_CLAMP_TRUE', + 'DCP_CURSOR_2X_MAGNIFY', 'DCP_CURSOR_2X_MAGNIFY_FALSE', + 'DCP_CURSOR_2X_MAGNIFY_TRUE', 'DCP_CURSOR_ALPHA_BLND_ENA', + 'DCP_CURSOR_ALPHA_BLND_ENA_FALSE', + 'DCP_CURSOR_ALPHA_BLND_ENA_TRUE', 'DCP_CURSOR_DEGAMMA_MODE', + 'DCP_CURSOR_DEGAMMA_MODE_BYPASS', + 'DCP_CURSOR_DEGAMMA_MODE_RESERVED', + 'DCP_CURSOR_DEGAMMA_MODE_ROMA', 'DCP_CURSOR_DEGAMMA_MODE_ROMB', + 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE', + 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE', + 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE', 'DCP_CURSOR_EN', + 'DCP_CURSOR_EN_FALSE', 'DCP_CURSOR_EN_TRUE', + 'DCP_CURSOR_FORCE_MC_ON', 'DCP_CURSOR_FORCE_MC_ON_FALSE', + 'DCP_CURSOR_FORCE_MC_ON_TRUE', + 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM', + 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE', + 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO', 'DCP_CURSOR_MODE', + 'DCP_CURSOR_MODE_24BPP_1BIT', + 'DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI', + 'DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI', + 'DCP_CURSOR_MODE_MONO_2BPP', 'DCP_CURSOR_STEREO_EN', + 'DCP_CURSOR_STEREO_EN_FALSE', 'DCP_CURSOR_STEREO_EN_TRUE', + 'DCP_CURSOR_STEREO_OFFSET_YNX', + 'DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION', + 'DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION', + 'DCP_CURSOR_UPDATE_LOCK', 'DCP_CURSOR_UPDATE_LOCK_FALSE', + 'DCP_CURSOR_UPDATE_LOCK_TRUE', 'DCP_CURSOR_UPDATE_PENDING', + 'DCP_CURSOR_UPDATE_PENDING_FALSE', + 'DCP_CURSOR_UPDATE_PENDING_TRUE', 'DCP_CURSOR_UPDATE_STEREO_MODE', + 'DCP_CURSOR_UPDATE_STEREO_MODE_BOTH', + 'DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY', + 'DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY', + 'DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED', + 'DCP_CURSOR_UPDATE_TAKEN', 'DCP_CURSOR_UPDATE_TAKEN_FALSE', + 'DCP_CURSOR_UPDATE_TAKEN_TRUE', 'DCP_CURSOR_URGENT_CONTROL', + 'DCP_CURSOR_URGENT_CONTROL_MODE_0', + 'DCP_CURSOR_URGENT_CONTROL_MODE_1', + 'DCP_CURSOR_URGENT_CONTROL_MODE_2', + 'DCP_CURSOR_URGENT_CONTROL_MODE_3', + 'DCP_CURSOR_URGENT_CONTROL_MODE_4', 'DCP_CUR_INV_TRANS_CLAMP', + 'DCP_CUR_INV_TRANS_CLAMP_FALSE', 'DCP_CUR_INV_TRANS_CLAMP_TRUE', + 'DCP_CUR_REQUEST_FILTER_DIS', 'DCP_CUR_REQUEST_FILTER_DIS_FALSE', + 'DCP_CUR_REQUEST_FILTER_DIS_TRUE', 'DCP_DC_LUT_AUTOFILL', + 'DCP_DC_LUT_AUTOFILL_DONE', 'DCP_DC_LUT_AUTOFILL_DONE_FALSE', + 'DCP_DC_LUT_AUTOFILL_DONE_TRUE', 'DCP_DC_LUT_AUTOFILL_FALSE', + 'DCP_DC_LUT_AUTOFILL_TRUE', 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN', + 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE', + 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE', + 'DCP_DC_LUT_DATA_B_FORMAT', 'DCP_DC_LUT_DATA_B_FORMAT_S1P10', + 'DCP_DC_LUT_DATA_B_FORMAT_U0P10', + 'DCP_DC_LUT_DATA_B_FORMAT_U0P12', + 'DCP_DC_LUT_DATA_B_FORMAT_U1P11', 'DCP_DC_LUT_DATA_B_SIGNED_EN', + 'DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE', + 'DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE', + 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN', + 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE', + 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE', + 'DCP_DC_LUT_DATA_G_FORMAT', 'DCP_DC_LUT_DATA_G_FORMAT_S1P10', + 'DCP_DC_LUT_DATA_G_FORMAT_U0P10', + 'DCP_DC_LUT_DATA_G_FORMAT_U0P12', + 'DCP_DC_LUT_DATA_G_FORMAT_U1P11', 'DCP_DC_LUT_DATA_G_SIGNED_EN', + 'DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE', + 'DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE', + 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN', + 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE', + 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE', + 'DCP_DC_LUT_DATA_R_FORMAT', 'DCP_DC_LUT_DATA_R_FORMAT_S1P10', + 'DCP_DC_LUT_DATA_R_FORMAT_U0P10', + 'DCP_DC_LUT_DATA_R_FORMAT_U0P12', + 'DCP_DC_LUT_DATA_R_FORMAT_U1P11', 'DCP_DC_LUT_DATA_R_SIGNED_EN', + 'DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE', + 'DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE', 'DCP_DC_LUT_INC_B', + 'DCP_DC_LUT_INC_B_128', 'DCP_DC_LUT_INC_B_16', + 'DCP_DC_LUT_INC_B_2', 'DCP_DC_LUT_INC_B_256', + 'DCP_DC_LUT_INC_B_32', 'DCP_DC_LUT_INC_B_4', + 'DCP_DC_LUT_INC_B_512', 'DCP_DC_LUT_INC_B_64', + 'DCP_DC_LUT_INC_B_8', 'DCP_DC_LUT_INC_B_NA', 'DCP_DC_LUT_INC_G', + 'DCP_DC_LUT_INC_G_128', 'DCP_DC_LUT_INC_G_16', + 'DCP_DC_LUT_INC_G_2', 'DCP_DC_LUT_INC_G_256', + 'DCP_DC_LUT_INC_G_32', 'DCP_DC_LUT_INC_G_4', + 'DCP_DC_LUT_INC_G_512', 'DCP_DC_LUT_INC_G_64', + 'DCP_DC_LUT_INC_G_8', 'DCP_DC_LUT_INC_G_NA', 'DCP_DC_LUT_INC_R', + 'DCP_DC_LUT_INC_R_128', 'DCP_DC_LUT_INC_R_16', + 'DCP_DC_LUT_INC_R_2', 'DCP_DC_LUT_INC_R_256', + 'DCP_DC_LUT_INC_R_32', 'DCP_DC_LUT_INC_R_4', + 'DCP_DC_LUT_INC_R_512', 'DCP_DC_LUT_INC_R_64', + 'DCP_DC_LUT_INC_R_8', 'DCP_DC_LUT_INC_R_NA', 'DCP_DC_LUT_RW_MODE', + 'DCP_DC_LUT_RW_MODE_256_ENTRY', 'DCP_DC_LUT_RW_MODE_PWL', + 'DCP_DC_LUT_VGA_ACCESS_ENABLE', + 'DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE', + 'DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE', 'DCP_DENORM_14BIT_OUT', + 'DCP_DENORM_14BIT_OUT_FALSE', 'DCP_DENORM_14BIT_OUT_TRUE', + 'DCP_DENORM_MODE', 'DCP_DENORM_MODE_10BIT', + 'DCP_DENORM_MODE_11BIT', 'DCP_DENORM_MODE_12BIT', + 'DCP_DENORM_MODE_6BIT', 'DCP_DENORM_MODE_8BIT', + 'DCP_DENORM_MODE_RESERVED0', 'DCP_DENORM_MODE_RESERVED1', + 'DCP_DENORM_MODE_UNITY', 'DCP_FRAME_RANDOM_ENABLE', + 'DCP_FRAME_RANDOM_ENABLE_FALSE', 'DCP_FRAME_RANDOM_ENABLE_TRUE', + 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE', + 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE', + 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE', + 'DCP_GRPH_ALPHA_CROSSBAR', 'DCP_GRPH_ALPHA_CROSSBAR_FROM_A', + 'DCP_GRPH_ALPHA_CROSSBAR_FROM_B', + 'DCP_GRPH_ALPHA_CROSSBAR_FROM_G', + 'DCP_GRPH_ALPHA_CROSSBAR_FROM_R', 'DCP_GRPH_BLUE_CROSSBAR', + 'DCP_GRPH_BLUE_CROSSBAR_FROM_A', 'DCP_GRPH_BLUE_CROSSBAR_FROM_B', + 'DCP_GRPH_BLUE_CROSSBAR_FROM_G', 'DCP_GRPH_BLUE_CROSSBAR_FROM_R', + 'DCP_GRPH_COLOR_EXPANSION_MODE', + 'DCP_GRPH_COLOR_EXPANSION_MODE_DEXP', + 'DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP', 'DCP_GRPH_DEGAMMA_MODE', + 'DCP_GRPH_DEGAMMA_MODE_BYPASS', 'DCP_GRPH_DEGAMMA_MODE_RESERVED', + 'DCP_GRPH_DEGAMMA_MODE_ROMA', 'DCP_GRPH_DEGAMMA_MODE_ROMB', + 'DCP_GRPH_DEPTH', 'DCP_GRPH_DEPTH_16BPP', 'DCP_GRPH_DEPTH_32BPP', + 'DCP_GRPH_DEPTH_64BPP', 'DCP_GRPH_DEPTH_8BPP', + 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES', + 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1', + 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2', + 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3', + 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4', + 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5', + 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6', + 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7', + 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8', 'DCP_GRPH_DFQ_RESET', + 'DCP_GRPH_DFQ_RESET_ACK', 'DCP_GRPH_DFQ_RESET_ACK_FALSE', + 'DCP_GRPH_DFQ_RESET_ACK_TRUE', 'DCP_GRPH_DFQ_RESET_FALSE', + 'DCP_GRPH_DFQ_RESET_TRUE', 'DCP_GRPH_DFQ_SIZE', + 'DCP_GRPH_DFQ_SIZE_DEEP1', 'DCP_GRPH_DFQ_SIZE_DEEP2', + 'DCP_GRPH_DFQ_SIZE_DEEP3', 'DCP_GRPH_DFQ_SIZE_DEEP4', + 'DCP_GRPH_DFQ_SIZE_DEEP5', 'DCP_GRPH_DFQ_SIZE_DEEP6', + 'DCP_GRPH_DFQ_SIZE_DEEP7', 'DCP_GRPH_DFQ_SIZE_DEEP8', + 'DCP_GRPH_ENABLE', 'DCP_GRPH_ENABLE_FALSE', + 'DCP_GRPH_ENABLE_TRUE', 'DCP_GRPH_ENDIAN_SWAP', + 'DCP_GRPH_ENDIAN_SWAP_8IN16', 'DCP_GRPH_ENDIAN_SWAP_8IN32', + 'DCP_GRPH_ENDIAN_SWAP_8IN64', 'DCP_GRPH_ENDIAN_SWAP_NONE', + 'DCP_GRPH_FLIP_RATE', 'DCP_GRPH_FLIP_RATE_1FRAME', + 'DCP_GRPH_FLIP_RATE_2FRAME', 'DCP_GRPH_FLIP_RATE_3FRAME', + 'DCP_GRPH_FLIP_RATE_4FRAME', 'DCP_GRPH_FLIP_RATE_5FRAME', + 'DCP_GRPH_FLIP_RATE_6FRAME', 'DCP_GRPH_FLIP_RATE_7FRAME', + 'DCP_GRPH_FLIP_RATE_8FRAME', 'DCP_GRPH_FLIP_RATE_ENABLE', + 'DCP_GRPH_FLIP_RATE_ENABLE_FALSE', + 'DCP_GRPH_FLIP_RATE_ENABLE_TRUE', 'DCP_GRPH_FORMAT', + 'DCP_GRPH_FORMAT_16BPP', 'DCP_GRPH_FORMAT_32BPP', + 'DCP_GRPH_FORMAT_64BPP', 'DCP_GRPH_FORMAT_8BPP', + 'DCP_GRPH_GAMUT_REMAP_MODE', 'DCP_GRPH_GAMUT_REMAP_MODE_BYPASS', + 'DCP_GRPH_GAMUT_REMAP_MODE_RESERVED', + 'DCP_GRPH_GAMUT_REMAP_MODE_ROMA', + 'DCP_GRPH_GAMUT_REMAP_MODE_ROMB', 'DCP_GRPH_GREEN_CROSSBAR', + 'DCP_GRPH_GREEN_CROSSBAR_FROM_A', + 'DCP_GRPH_GREEN_CROSSBAR_FROM_B', + 'DCP_GRPH_GREEN_CROSSBAR_FROM_G', + 'DCP_GRPH_GREEN_CROSSBAR_FROM_R', 'DCP_GRPH_INPUT_GAMMA_MODE', + 'DCP_GRPH_INPUT_GAMMA_MODE_BYPASS', + 'DCP_GRPH_INPUT_GAMMA_MODE_LUT', 'DCP_GRPH_KEYER_ALPHA_SEL', + 'DCP_GRPH_KEYER_ALPHA_SEL_FALSE', 'DCP_GRPH_KEYER_ALPHA_SEL_TRUE', + 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN', + 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE', + 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE', + 'DCP_GRPH_LUT_10BIT_BYPASS_EN', + 'DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE', + 'DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE', + 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE', + 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE', + 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE', + 'DCP_GRPH_MODE_UPDATE_PENDING', + 'DCP_GRPH_MODE_UPDATE_PENDING_FALSE', + 'DCP_GRPH_MODE_UPDATE_PENDING_TRUE', 'DCP_GRPH_MODE_UPDATE_TAKEN', + 'DCP_GRPH_MODE_UPDATE_TAKEN_FALSE', + 'DCP_GRPH_MODE_UPDATE_TAKEN_TRUE', 'DCP_GRPH_NUM_BANKS', + 'DCP_GRPH_NUM_BANKS_16BANK', 'DCP_GRPH_NUM_BANKS_1BANK', + 'DCP_GRPH_NUM_BANKS_2BANK', 'DCP_GRPH_NUM_BANKS_4BANK', + 'DCP_GRPH_NUM_BANKS_8BANK', 'DCP_GRPH_NUM_PIPES', + 'DCP_GRPH_NUM_PIPES_1PIPE', 'DCP_GRPH_NUM_PIPES_2PIPE', + 'DCP_GRPH_NUM_PIPES_4PIPE', 'DCP_GRPH_NUM_PIPES_8PIPE', + 'DCP_GRPH_PFLIP_INT_CLEAR', 'DCP_GRPH_PFLIP_INT_CLEAR_FALSE', + 'DCP_GRPH_PFLIP_INT_CLEAR_TRUE', 'DCP_GRPH_PFLIP_INT_MASK', + 'DCP_GRPH_PFLIP_INT_MASK_FALSE', 'DCP_GRPH_PFLIP_INT_MASK_TRUE', + 'DCP_GRPH_PFLIP_INT_TYPE', 'DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL', + 'DCP_GRPH_PFLIP_INT_TYPE_PULSE', 'DCP_GRPH_PRESCALE_BYPASS', + 'DCP_GRPH_PRESCALE_BYPASS_FALSE', 'DCP_GRPH_PRESCALE_BYPASS_TRUE', + 'DCP_GRPH_PRESCALE_B_SIGN', 'DCP_GRPH_PRESCALE_B_SIGN_SIGNED', + 'DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED', 'DCP_GRPH_PRESCALE_G_SIGN', + 'DCP_GRPH_PRESCALE_G_SIGN_SIGNED', + 'DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED', 'DCP_GRPH_PRESCALE_R_SIGN', + 'DCP_GRPH_PRESCALE_R_SIGN_SIGNED', + 'DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED', 'DCP_GRPH_PRESCALE_SELECT', + 'DCP_GRPH_PRESCALE_SELECT_FIXED', + 'DCP_GRPH_PRESCALE_SELECT_FLOATING', + 'DCP_GRPH_PRIMARY_DFQ_ENABLE', + 'DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE', + 'DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE', 'DCP_GRPH_RED_CROSSBAR', + 'DCP_GRPH_RED_CROSSBAR_FROM_A', 'DCP_GRPH_RED_CROSSBAR_FROM_B', + 'DCP_GRPH_RED_CROSSBAR_FROM_G', 'DCP_GRPH_RED_CROSSBAR_FROM_R', + 'DCP_GRPH_REGAMMA_MODE', 'DCP_GRPH_REGAMMA_MODE_BYPASS', + 'DCP_GRPH_REGAMMA_MODE_PROGA', 'DCP_GRPH_REGAMMA_MODE_PROGB', + 'DCP_GRPH_REGAMMA_MODE_SRGB', 'DCP_GRPH_REGAMMA_MODE_XVYCC', + 'DCP_GRPH_ROTATION_ANGLE', 'DCP_GRPH_ROTATION_ANGLE_0', + 'DCP_GRPH_ROTATION_ANGLE_180', 'DCP_GRPH_ROTATION_ANGLE_270', + 'DCP_GRPH_ROTATION_ANGLE_90', 'DCP_GRPH_SECONDARY_DFQ_ENABLE', + 'DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE', + 'DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE', + 'DCP_GRPH_STEREOSYNC_FLIP_EN', + 'DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE', + 'DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE', + 'DCP_GRPH_STEREOSYNC_FLIP_MODE', + 'DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP', + 'DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0', + 'DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1', + 'DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET', + 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE', + 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE', + 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE', + 'DCP_GRPH_SURFACE_COUNTER_EN', + 'DCP_GRPH_SURFACE_COUNTER_EN_DISABLE', + 'DCP_GRPH_SURFACE_COUNTER_EN_ENABLE', + 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED', + 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO', + 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9', + 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE', + 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE', + 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE', + 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK', + 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE', + 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE', + 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN', + 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE', + 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE', + 'DCP_GRPH_SURFACE_UPDATE_PENDING', + 'DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE', + 'DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE', + 'DCP_GRPH_SURFACE_UPDATE_TAKEN', + 'DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE', + 'DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE', + 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE', + 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE', + 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE', 'DCP_GRPH_SW_MODE', + 'DCP_GRPH_SW_MODE_0', 'DCP_GRPH_SW_MODE_2', 'DCP_GRPH_SW_MODE_22', + 'DCP_GRPH_SW_MODE_23', 'DCP_GRPH_SW_MODE_26', + 'DCP_GRPH_SW_MODE_27', 'DCP_GRPH_SW_MODE_3', + 'DCP_GRPH_SW_MODE_30', 'DCP_GRPH_SW_MODE_31', + 'DCP_GRPH_UPDATE_LOCK', 'DCP_GRPH_UPDATE_LOCK_FALSE', + 'DCP_GRPH_UPDATE_LOCK_TRUE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE', + 'DCP_GRPH_XDMA_DRR_MODE_ENABLE', + 'DCP_GRPH_XDMA_DRR_MODE_ENABLE_DISABLE', + 'DCP_GRPH_XDMA_DRR_MODE_ENABLE_ENABLE', + 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK', + 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_FALSE', + 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_TRUE', + 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK', + 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_FALSE', + 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_TRUE', + 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR', + 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_DISABLE', + 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_ENABLE', + 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE', + 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE_DISABLE', + 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE_ENABLE', + 'DCP_GRPH_XDMA_SUPER_AA_EN', 'DCP_GRPH_XDMA_SUPER_AA_EN_FALSE', + 'DCP_GRPH_XDMA_SUPER_AA_EN_TRUE', 'DCP_GSL0_EN', + 'DCP_GSL0_EN_FALSE', 'DCP_GSL0_EN_TRUE', 'DCP_GSL1_EN', + 'DCP_GSL1_EN_FALSE', 'DCP_GSL1_EN_TRUE', 'DCP_GSL2_EN', + 'DCP_GSL2_EN_FALSE', 'DCP_GSL2_EN_TRUE', + 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING', + 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE', + 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE', 'DCP_GSL_MASTER_EN', + 'DCP_GSL_MASTER_EN_FALSE', 'DCP_GSL_MASTER_EN_TRUE', + 'DCP_GSL_SYNC_SOURCE', 'DCP_GSL_SYNC_SOURCE_FLIP', + 'DCP_GSL_SYNC_SOURCE_PHASE0', 'DCP_GSL_SYNC_SOURCE_PHASE1', + 'DCP_GSL_SYNC_SOURCE_RESET', + 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC', + 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_DIS', + 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_EN', 'DCP_GSL_XDMA_GROUP', + 'DCP_GSL_XDMA_GROUP_HSYNC0', 'DCP_GSL_XDMA_GROUP_HSYNC1', + 'DCP_GSL_XDMA_GROUP_HSYNC2', 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN', + 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE', + 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE', + 'DCP_GSL_XDMA_GROUP_VSYNC', 'DCP_HIGHPASS_RANDOM_ENABLE', + 'DCP_HIGHPASS_RANDOM_ENABLE_FALSE', + 'DCP_HIGHPASS_RANDOM_ENABLE_TRUE', 'DCP_INPUT_CSC_GRPH_MODE', + 'DCP_INPUT_CSC_GRPH_MODE_BYPASS', + 'DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF', + 'DCP_INPUT_CSC_GRPH_MODE_RESERVED', + 'DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF', 'DCP_KEY_MODE', + 'DCP_KEY_MODE_ALPHA0', 'DCP_KEY_MODE_ALPHA1', + 'DCP_KEY_MODE_IN_RANGE_ALPHA0', 'DCP_KEY_MODE_IN_RANGE_ALPHA1', + 'DCP_OUTPUT_CSC_GRPH_MODE', 'DCP_OUTPUT_CSC_GRPH_MODE_BYPASS', + 'DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF', + 'DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0', + 'DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1', + 'DCP_OUTPUT_CSC_GRPH_MODE_RGB', + 'DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF', + 'DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601', + 'DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709', 'DCP_OUT_ROUND_TRUNC_MODE', + 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_10', + 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_11', + 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_12', + 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_13', + 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_14', + 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_8', + 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_9', + 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED', + 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10', + 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11', + 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12', + 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13', + 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14', + 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8', + 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9', + 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED', + 'DCP_RGB_RANDOM_ENABLE', 'DCP_RGB_RANDOM_ENABLE_FALSE', + 'DCP_RGB_RANDOM_ENABLE_TRUE', 'DCP_SPATIAL_DITHER_DEPTH', + 'DCP_SPATIAL_DITHER_DEPTH_24BPP', + 'DCP_SPATIAL_DITHER_DEPTH_30BPP', + 'DCP_SPATIAL_DITHER_DEPTH_36BPP', + 'DCP_SPATIAL_DITHER_DEPTH_UNDEFINED', 'DCP_SPATIAL_DITHER_EN', + 'DCP_SPATIAL_DITHER_EN_FALSE', 'DCP_SPATIAL_DITHER_EN_TRUE', + 'DCP_SPATIAL_DITHER_MODE', 'DCP_SPATIAL_DITHER_MODE_BYPASS', + 'DCP_SPATIAL_DITHER_MODE_RESERVED', + 'DCP_SPATIAL_DITHER_MODE_ROMA', 'DCP_SPATIAL_DITHER_MODE_ROMB', + 'DCP_TEST_DEBUG_WRITE_EN', 'DCP_TEST_DEBUG_WRITE_EN_FALSE', + 'DCP_TEST_DEBUG_WRITE_EN_TRUE', 'DC_MEM_GLOBAL_PWR_REQ_DIS', + 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', + 'DEGAMMA_MODE_A', 'DEGAMMA_MODE_B', 'DEGAMMA_MODE_BYPASS', + 'DENORM_CLAMP_MODE_10', 'DENORM_CLAMP_MODE_12', + 'DENORM_CLAMP_MODE_8', 'DENORM_CLAMP_MODE_UNITY', 'DEPTH_16', + 'DEPTH_32_FLOAT', 'DEPTH_8_24', 'DEPTH_8_24_FLOAT', + 'DEPTH_INVALID', 'DEPTH_X24_8_32_FLOAT', 'DEPTH_X8_24', + 'DEPTH_X8_24_FLOAT', 'DFSMFlushEvents', 'DIGA_BE_SOFT_RESET', + 'DIGA_BE_SOFT_RESET_0', 'DIGA_BE_SOFT_RESET_1', + 'DIGA_FE_SOFT_RESET', 'DIGA_FE_SOFT_RESET_0', + 'DIGA_FE_SOFT_RESET_1', 'DIGB_BE_SOFT_RESET', + 'DIGB_BE_SOFT_RESET_0', 'DIGB_BE_SOFT_RESET_1', + 'DIGB_FE_SOFT_RESET', 'DIGB_FE_SOFT_RESET_0', + 'DIGB_FE_SOFT_RESET_1', 'DIGC_BE_SOFT_RESET', + 'DIGC_BE_SOFT_RESET_0', 'DIGC_BE_SOFT_RESET_1', + 'DIGC_FE_SOFT_RESET', 'DIGC_FE_SOFT_RESET_0', + 'DIGC_FE_SOFT_RESET_1', 'DIGD_BE_SOFT_RESET', + 'DIGD_BE_SOFT_RESET_0', 'DIGD_BE_SOFT_RESET_1', + 'DIGD_FE_SOFT_RESET', 'DIGD_FE_SOFT_RESET_0', + 'DIGD_FE_SOFT_RESET_1', 'DIGE_BE_SOFT_RESET', + 'DIGE_BE_SOFT_RESET_0', 'DIGE_BE_SOFT_RESET_1', + 'DIGE_FE_SOFT_RESET', 'DIGE_FE_SOFT_RESET_0', + 'DIGE_FE_SOFT_RESET_1', 'DIGF_BE_SOFT_RESET', + 'DIGF_BE_SOFT_RESET_0', 'DIGF_BE_SOFT_RESET_1', + 'DIGF_FE_SOFT_RESET', 'DIGF_FE_SOFT_RESET_0', + 'DIGF_FE_SOFT_RESET_1', 'DIGG_BE_SOFT_RESET', + 'DIGG_BE_SOFT_RESET_0', 'DIGG_BE_SOFT_RESET_1', + 'DIGG_FE_SOFT_RESET', 'DIGG_FE_SOFT_RESET_0', + 'DIGG_FE_SOFT_RESET_1', 'DIGLPA_BE_SOFT_RESET', + 'DIGLPA_BE_SOFT_RESET_0', 'DIGLPA_BE_SOFT_RESET_1', + 'DIGLPA_FE_SOFT_RESET', 'DIGLPA_FE_SOFT_RESET_0', + 'DIGLPA_FE_SOFT_RESET_1', 'DIGLPB_BE_SOFT_RESET', + 'DIGLPB_BE_SOFT_RESET_0', 'DIGLPB_BE_SOFT_RESET_1', + 'DIGLPB_FE_SOFT_RESET', 'DIGLPB_FE_SOFT_RESET_0', + 'DIGLPB_FE_SOFT_RESET_1', 'DIG_10BIT_TEST_PATTERN', + 'DIG_ALTERNATING_TEST_PATTERN', 'DIG_BE_CNTL_HPD1', + 'DIG_BE_CNTL_HPD2', 'DIG_BE_CNTL_HPD3', 'DIG_BE_CNTL_HPD4', + 'DIG_BE_CNTL_HPD5', 'DIG_BE_CNTL_HPD6', 'DIG_BE_CNTL_HPD_SELECT', + 'DIG_BE_CNTL_MODE', 'DIG_BE_DP_MST_MODE', 'DIG_BE_DP_SST_MODE', + 'DIG_BE_RESERVED1', 'DIG_BE_RESERVED2', 'DIG_BE_RESERVED3', + 'DIG_BE_SDVO_RESERVED', 'DIG_BE_TMDS_DVI_MODE', + 'DIG_BE_TMDS_HDMI_MODE', 'DIG_FE_CNTL_SOURCE_SELECT', + 'DIG_FE_CNTL_STEREOSYNC_SELECT', 'DIG_FE_SOURCE_FROM_FMT0', + 'DIG_FE_SOURCE_FROM_FMT1', 'DIG_FE_SOURCE_FROM_FMT2', + 'DIG_FE_SOURCE_FROM_FMT3', 'DIG_FE_SOURCE_FROM_FMT4', + 'DIG_FE_SOURCE_FROM_FMT5', 'DIG_FE_STEREOSYNC_FROM_FMT0', + 'DIG_FE_STEREOSYNC_FROM_FMT1', 'DIG_FE_STEREOSYNC_FROM_FMT2', + 'DIG_FE_STEREOSYNC_FROM_FMT3', 'DIG_FE_STEREOSYNC_FROM_FMT4', + 'DIG_FE_STEREOSYNC_FROM_FMT5', 'DIG_FIFO_ERROR_ACK', + 'DIG_FIFO_ERROR_ACK_INT', 'DIG_FIFO_ERROR_NOT_ACK', + 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', + 'DIG_FIFO_FORCE_RECOMP_MINMAX', + 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', + 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', 'DIG_FIFO_READ_CLOCK_SRC', + 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', + 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', + 'DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE', + 'DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX', + 'DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL', + 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', 'DIG_FIFO_USE_OVERWRITE_LEVEL', + 'DIG_IN_DEBUG_MODE', 'DIG_IN_NORMAL_OPERATION', + 'DIG_OUTPUT_CRC_CNTL_LINK_SEL', 'DIG_OUTPUT_CRC_DATA_SEL', + 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', 'DIG_OUTPUT_CRC_FOR_AUDIO', + 'DIG_OUTPUT_CRC_FOR_FULLFRAME', 'DIG_OUTPUT_CRC_FOR_VBI', + 'DIG_OUTPUT_CRC_ON_LINK0', 'DIG_OUTPUT_CRC_ON_LINK1', + 'DIG_RANDOM_PATTERN_ENABLED', 'DIG_RANDOM_PATTERN_RESETED', + 'DIG_RANDOM_PATTERN_SEED_RAN_PAT', + 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', + 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', + 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', + 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN', + 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', + 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL', + 'DIG_TEST_PATTERN_NORMAL', 'DIG_TEST_PATTERN_RANDOM', + 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN', + 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET', + 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN', + 'DISABLE_BINNING_USE_LEGACY_SC', 'DISABLE_BINNING_USE_NEW_SC', + 'DISABLE_CLOCK_GATING', 'DISABLE_CLOCK_GATING_IN_DCO', + 'DISABLE_JITTER_REMOVAL', 'DISABLE_MEM_PWR_CTRL', + 'DISABLE_THE_CLOCK', 'DISABLE_THE_FEATURE', + 'DISPCLK_CHG_FWD_CORR_DISABLE', + 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', + 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', + 'DISPCLK_FREQ_RAMP_COMPLETED', 'DISPCLK_FREQ_RAMP_DONE', + 'DISPCLK_FREQ_RAMP_IN_PROGRESS', 'DITHER_DIS', 'DITHER_EN', + 'DI_INDEX_SIZE_16_BIT', 'DI_INDEX_SIZE_32_BIT', + 'DI_INDEX_SIZE_8_BIT', 'DI_MAJOR_MODE_0', 'DI_MAJOR_MODE_1', + 'DI_PT_2D_RECTANGLE', 'DI_PT_LINELIST', 'DI_PT_LINELIST_ADJ', + 'DI_PT_LINELOOP', 'DI_PT_LINESTRIP', 'DI_PT_LINESTRIP_ADJ', + 'DI_PT_NONE', 'DI_PT_PATCH', 'DI_PT_POINTLIST', 'DI_PT_POLYGON', + 'DI_PT_QUADLIST', 'DI_PT_QUADSTRIP', 'DI_PT_RECTLIST', + 'DI_PT_TRIFAN', 'DI_PT_TRILIST', 'DI_PT_TRILIST_ADJ', + 'DI_PT_TRISTRIP', 'DI_PT_TRISTRIP_ADJ', 'DI_PT_TRI_WITH_WFLAGS', + 'DI_PT_UNUSED_1', 'DI_PT_UNUSED_3', 'DI_PT_UNUSED_4', + 'DI_SRC_SEL_AUTO_INDEX', 'DI_SRC_SEL_DMA', 'DI_SRC_SEL_IMMEDIATE', + 'DI_SRC_SEL_RESERVED', + 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE', + 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', + 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', + 'DONUTS', 'DOUT_I2C_ACK', 'DOUT_I2C_ACK_TO_CLEAN', + 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', + 'DOUT_I2C_ARBITRATION_ABORT_XFER', + 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG', + 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', + 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', + 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', + 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', + 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', + 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', + 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ', + 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', + 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', + 'DOUT_I2C_CONTROL_DBG_REF_SEL', 'DOUT_I2C_CONTROL_DDC_SELECT', + 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', 'DOUT_I2C_CONTROL_GO', + 'DOUT_I2C_CONTROL_NORMAL_DEBUG', + 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', + 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', + 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', + 'DOUT_I2C_CONTROL_RESET_SW_STATUS', + 'DOUT_I2C_CONTROL_SELECT_DDC1', 'DOUT_I2C_CONTROL_SELECT_DDC2', + 'DOUT_I2C_CONTROL_SELECT_DDC3', 'DOUT_I2C_CONTROL_SELECT_DDC4', + 'DOUT_I2C_CONTROL_SELECT_DDC5', 'DOUT_I2C_CONTROL_SELECT_DDC6', + 'DOUT_I2C_CONTROL_SELECT_DDCVGA', 'DOUT_I2C_CONTROL_SEND_RESET', + 'DOUT_I2C_CONTROL_SOFT_RESET', 'DOUT_I2C_CONTROL_START_TRANSFER', + 'DOUT_I2C_CONTROL_STOP_TRANSFER', + 'DOUT_I2C_CONTROL_SW_STATUS_RESET', 'DOUT_I2C_CONTROL_TRANS0', + 'DOUT_I2C_CONTROL_TRANS0_TRANS1', + 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', + 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', + 'DOUT_I2C_CONTROL_TRANSACTION_COUNT', + 'DOUT_I2C_CONTROL__NOT_SEND_RESET', + 'DOUT_I2C_CONTROL__SEND_RESET', 'DOUT_I2C_DATA_INDEX_WRITE', + 'DOUT_I2C_DATA__INDEX_WRITE', 'DOUT_I2C_DATA__NOT_INDEX_WRITE', + 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', + 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL', + 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', + 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', + 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE', + 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', + 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', + 'DOUT_I2C_DDC_SPEED_THRESHOLD', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', + 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET', + 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', + 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', + 'DOUT_I2C_NO_ACK', 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE', + 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', + 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', + 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', + 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', + 'DOUT_I2C_TRANSACTION_STOP_ON_NACK', 'DOWNSCALE_PREFETCH_DIS', + 'DOWNSCALE_PREFETCH_EN', 'DPCSRX_BPHY_PCS_RX0_CLK', + 'DPCSRX_BPHY_PCS_RX1_CLK', 'DPCSRX_BPHY_PCS_RX2_CLK', + 'DPCSRX_BPHY_PCS_RX3_CLK', 'DPCSRX_DBG_CFGCLK_SEL', + 'DPCSRX_DBG_CFGCLK_SEL_CBUS_MASTER', + 'DPCSRX_DBG_CFGCLK_SEL_CBUS_SLAVE', + 'DPCSRX_DBG_CFGCLK_SEL_DC_DPCS_INF', + 'DPCSRX_DBG_CFGCLK_SEL_DPCS_BPHY_INF', + 'DPCSRX_DBG_RX_SYMCLK_SEL_INT', 'DPCSRX_DBG_RX_SYMCLK_SEL_OUT0', + 'DPCSRX_DBG_RX_SYMCLK_SEL_OUT1', + 'DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL', 'DPCSRX_RX_SYMCLK_SEL', + 'DPCSTX_DBG_CFGCLK_SEL', 'DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER', + 'DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE', + 'DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF', + 'DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF', + 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD', + 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT', + 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0', + 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1', + 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2', + 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3', + 'DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR', + 'DPCSTX_DBG_TX_SYMCLK_SEL_IN0', 'DPCSTX_DBG_TX_SYMCLK_SEL_IN1', + 'DPCSTX_TX_SYMCLK_DIV2_SEL', 'DPCSTX_TX_SYMCLK_SEL', + 'DPDBG_CLK_FORCE_EN', 'DPDBG_CLK_FORCE_EN_DISABLE', + 'DPDBG_CLK_FORCE_EN_ENABLE', 'DPDBG_DISABLE', 'DPDBG_EN', + 'DPDBG_ENABLE', 'DPDBG_ERROR_DETECTION_MODE', + 'DPDBG_ERROR_DETECTION_MODE_CSC', + 'DPDBG_ERROR_DETECTION_MODE_RS_ENCODING', + 'DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK', + 'DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK', + 'DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE', + 'DPDBG_FIFO_OVERFLOW_INT_CLEAR', + 'DPDBG_FIFO_OVERFLOW_INT_DISABLE', + 'DPDBG_FIFO_OVERFLOW_INT_ENABLE', + 'DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED', + 'DPDBG_FIFO_OVERFLOW_INT_NO_ACK', + 'DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED', 'DPDBG_INPUT_DISABLE', + 'DPDBG_INPUT_EN', 'DPDBG_INPUT_ENABLE', 'DPDBG_SOFT_RESET', + 'DPDBG_SOFT_RESET_0', 'DPDBG_SOFT_RESET_1', 'DPHY_8B10B_CUR_DISP', + 'DPHY_8B10B_CUR_DISP_ONE', 'DPHY_8B10B_CUR_DISP_ZERO', + 'DPHY_8B10B_NOT_RESET', 'DPHY_8B10B_OUTPUT', 'DPHY_8B10B_RESET', + 'DPHY_8B10B_RESETET', + 'DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION', + 'DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE', + 'DPHY_ALT_SCRAMBLER_RESET_EN', 'DPHY_ALT_SCRAMBLER_RESET_SEL', + 'DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE', + 'DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE', + 'DPHY_ATEST_LANE0_PRBS_PATTERN', 'DPHY_ATEST_LANE0_REG_PATTERN', + 'DPHY_ATEST_LANE1_PRBS_PATTERN', 'DPHY_ATEST_LANE1_REG_PATTERN', + 'DPHY_ATEST_LANE2_PRBS_PATTERN', 'DPHY_ATEST_LANE2_REG_PATTERN', + 'DPHY_ATEST_LANE3_PRBS_PATTERN', 'DPHY_ATEST_LANE3_REG_PATTERN', + 'DPHY_ATEST_SEL_LANE0', 'DPHY_ATEST_SEL_LANE1', + 'DPHY_ATEST_SEL_LANE2', 'DPHY_ATEST_SEL_LANE3', 'DPHY_BYPASS', + 'DPHY_CRC_CONTINUOUS', 'DPHY_CRC_CONT_EN', 'DPHY_CRC_DISABLED', + 'DPHY_CRC_EN', 'DPHY_CRC_ENABLED', 'DPHY_CRC_FIELD', + 'DPHY_CRC_LANE0_SELECTED', 'DPHY_CRC_LANE1_SELECTED', + 'DPHY_CRC_LANE2_SELECTED', 'DPHY_CRC_LANE3_SELECTED', + 'DPHY_CRC_MST_PHASE_ERROR_ACK', 'DPHY_CRC_MST_PHASE_ERROR_ACKED', + 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', 'DPHY_CRC_ONE_SHOT', + 'DPHY_CRC_SEL', 'DPHY_CRC_START_FROM_BOTTOM_FIELD', + 'DPHY_CRC_START_FROM_TOP_FIELD', 'DPHY_DBG_OUTPUT', + 'DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY', + 'DPHY_FAST_TRAINING_CAPABLE', 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', + 'DPHY_LOAD_BS_COUNT_NOT_STARTED', 'DPHY_LOAD_BS_COUNT_START', + 'DPHY_LOAD_BS_COUNT_STARTED', 'DPHY_NO_SKEW', + 'DPHY_PRBS11_SELECTED', 'DPHY_PRBS23_SELECTED', + 'DPHY_PRBS7_SELECTED', 'DPHY_PRBS_DISABLE', 'DPHY_PRBS_EN', + 'DPHY_PRBS_ENABLE', 'DPHY_PRBS_SEL', + 'DPHY_RX_FAST_TRAINING_CAPABLE', 'DPHY_SCRAMBLER_ADVANCE', + 'DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL', + 'DPHY_SCRAMBLER_DIS', 'DPHY_SCRAMBLER_KCODE', + 'DPHY_SCRAMBLER_KCODE_DISABLED', 'DPHY_SCRAMBLER_KCODE_ENABLED', + 'DPHY_SCRAMBLER_SEL', 'DPHY_SCRAMBLER_SEL_DBG_DATA', + 'DPHY_SCRAMBLER_SEL_LANE_DATA', 'DPHY_SCR_DISABLED', + 'DPHY_SCR_ENABLED', 'DPHY_SKEW_BYPASS', + 'DPHY_SW_FAST_TRAINING_NOT_STARTED', + 'DPHY_SW_FAST_TRAINING_START', 'DPHY_SW_FAST_TRAINING_STARTED', + 'DPHY_TRAINING_PATTERN_1', 'DPHY_TRAINING_PATTERN_2', + 'DPHY_TRAINING_PATTERN_3', 'DPHY_TRAINING_PATTERN_4', + 'DPHY_TRAINING_PATTERN_SEL', 'DPHY_WITH_SKEW', 'DPREFCLK_SRC_SEL', + 'DPREFCLK_SRC_SEL_CK', 'DPREFCLK_SRC_SEL_P0PLL', + 'DPREFCLK_SRC_SEL_P1PLL', 'DPREFCLK_SRC_SEL_P2PLL', + 'DPREFCLK_SRC_SEL_P3PLL', 'DPRX_SD_COMPONENT_DEPTH', + 'DPRX_SD_PIXEL_ENCODING', 'DP_AUX_ARB_CONTROL_ARB_PRIORITY', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', + 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG', + 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ', + 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', + 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', + 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', + 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', + 'DP_AUX_CONTROL_HPD1_SELECTED', 'DP_AUX_CONTROL_HPD2_SELECTED', + 'DP_AUX_CONTROL_HPD3_SELECTED', 'DP_AUX_CONTROL_HPD4_SELECTED', + 'DP_AUX_CONTROL_HPD5_SELECTED', 'DP_AUX_CONTROL_HPD6_SELECTED', + 'DP_AUX_CONTROL_HPD_SEL', 'DP_AUX_CONTROL_TEST_MODE', + 'DP_AUX_CONTROL_TEST_MODE_DISABLE', + 'DP_AUX_CONTROL_TEST_MODE_ENABLE', + 'DP_AUX_DEFINITE_ERR_REACHED_ACK', + 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START', + 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN', + 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US', + 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US', + 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US', + 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US', + 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US', + 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US', + 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US', + 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US', + 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', + 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', + 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', + 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', + 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN', + 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US', + 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US', + 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US', + 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US', + 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US', + 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US', + 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US', + 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', + 'DP_AUX_ERR_OCCURRED_ACK', 'DP_AUX_ERR_OCCURRED__ACK', + 'DP_AUX_ERR_OCCURRED__NOT_ACK', + 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', + 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ', + 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', + 'DP_AUX_INT_ACK', 'DP_AUX_INT_LS_UPDATE_ACK', + 'DP_AUX_INT_LS_UPDATE_NOT_ACK', 'DP_AUX_INT__ACK', + 'DP_AUX_INT__NOT_ACK', 'DP_AUX_LS_UPDATE_ACK', + 'DP_AUX_POTENTIAL_ERR_REACHED_ACK', + 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', + 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', 'DP_AUX_RESET', + 'DP_AUX_RESET_ASSERTED', 'DP_AUX_RESET_DEASSERTED', + 'DP_AUX_RESET_DONE', 'DP_AUX_RESET_SEQUENCE_DONE', + 'DP_AUX_RESET_SEQUENCE_NOT_DONE', + 'DP_AUX_SW_CONTROL_LS_READ_TRIG', + 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', + 'DP_AUX_SW_CONTROL_LS_READ__TRIG', 'DP_AUX_SW_CONTROL_SW_GO', + 'DP_AUX_SW_CONTROL_SW__GO', 'DP_AUX_SW_CONTROL_SW__NOT_GO', + 'DP_COMPONENT_DEPTH', 'DP_COMPONENT_DEPTH_10BPC', + 'DP_COMPONENT_DEPTH_12BPC', 'DP_COMPONENT_DEPTH_16BPC_RESERVED', + 'DP_COMPONENT_DEPTH_6BPC', 'DP_COMPONENT_DEPTH_8BPC', + 'DP_COMPONENT_DEPTH_RESERVED', 'DP_DPHY_8B10B_EXT_DISP', + 'DP_DPHY_8B10B_EXT_DISP_ONE', 'DP_DPHY_8B10B_EXT_DISP_ZERO', + 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK', + 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', + 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK', + 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', + 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', + 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', + 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', + 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN', + 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', + 'DP_DPHY_HBR2_PASS_THROUGH', 'DP_DPHY_HBR2_PATTERN_1', + 'DP_DPHY_HBR2_PATTERN_2_NEG', 'DP_DPHY_HBR2_PATTERN_2_POS', + 'DP_DPHY_HBR2_PATTERN_3', 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE', + 'DP_DTO_DESPREAD_DISABLE', 'DP_DTO_DESPREAD_ENABLE', + 'DP_DTO_DS_DISABLE', 'DP_DYN_CEA_RANGE', 'DP_DYN_RANGE', + 'DP_DYN_VESA_RANGE', 'DP_EMBEDDED_PANEL', + 'DP_EMBEDDED_PANEL_MODE', 'DP_EXTERNAL_PANEL', + 'DP_LINK_TRAINING_ALREADY_COMPLETE', 'DP_LINK_TRAINING_COMPLETE', + 'DP_LINK_TRAINING_NOT_COMPLETE', 'DP_MSA_MISC0_OVERRIDE_ENABLE', + 'DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE', + 'DP_MSA_V_TIMING_OVERRIDE_EN', 'DP_MSE_BLANK_CODE', + 'DP_MSE_BLANK_CODE_SF_FILLED', 'DP_MSE_BLANK_CODE_ZERO_FILLED', + 'DP_MSE_LINK_LINE', 'DP_MSE_LINK_LINE_128_MTP_LONG', + 'DP_MSE_LINK_LINE_256_MTP_LONG', 'DP_MSE_LINK_LINE_32_MTP_LONG', + 'DP_MSE_LINK_LINE_64_MTP_LONG', 'DP_MSE_NOT_ZERO_FE_ENCODER', + 'DP_MSE_OUTPUT_DPDBG_DATA', 'DP_MSE_OUTPUT_DPDBG_DATA_DIS', + 'DP_MSE_OUTPUT_DPDBG_DATA_EN', 'DP_MSE_SAT_UPDATE_ACT', + 'DP_MSE_SAT_UPDATE_NO_ACTION', + 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', + 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', + 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', + 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', 'DP_MSE_TIMESTAMP_MODE', + 'DP_MSE_ZERO_ENCODER', 'DP_MSE_ZERO_FE_ENCODER', + 'DP_PIXEL_ENCODING', 'DP_PIXEL_ENCODING_RESERVED', + 'DP_PIXEL_ENCODING_RGB444', 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', + 'DP_PIXEL_ENCODING_YCBCR420', 'DP_PIXEL_ENCODING_YCBCR422', + 'DP_PIXEL_ENCODING_YCBCR444', 'DP_PIXEL_ENCODING_Y_ONLY', + 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', + 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE', + 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', + 'DP_SEC_ASP_HIGH_PRIORITY', 'DP_SEC_ASP_LOW_PRIORITY', + 'DP_SEC_ASP_PRIORITY', 'DP_SEC_AUDIO_MUTE', + 'DP_SEC_AUDIO_MUTE_HW_CTRL', 'DP_SEC_AUDIO_MUTE_SW_CTRL', + 'DP_SEC_COLLISION_ACK', 'DP_SEC_COLLISION_ACK_CLR_FLAG', + 'DP_SEC_COLLISION_ACK_NO_EFFECT', 'DP_SEC_GSP0_PRIORITY', + 'DP_SEC_GSP0_SEND', 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', + 'DP_SEC_TIMESTAMP_MODE', 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', + 'DP_STEER_OVERFLOW_ACK', 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', + 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', 'DP_STEER_OVERFLOW_MASK', + 'DP_STEER_OVERFLOW_MASKED', 'DP_STEER_OVERFLOW_UNMASK', + 'DP_TOP_FIELD_ONLY', 'DP_TOP_PLUS_BOTTOM_FIELD', + 'DP_TU_OVERFLOW_ACK', 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', + 'DP_TU_OVERFLOW_ACK_NO_EFFECT', 'DP_UDI_1_LANE', 'DP_UDI_2_LANES', + 'DP_UDI_4_LANES', 'DP_UDI_LANES', 'DP_UDI_LANES_RESERVED', + 'DP_VID_ENHANCED_FRAME_MODE', 'DP_VID_MSA_TOP_FIELD_MODE', + 'DP_VID_M_DOUBLE_INPUT_PIXEL_RATE', 'DP_VID_M_DOUBLE_VALUE_EN', + 'DP_VID_M_INPUT_PIXEL_RATE', 'DP_VID_M_N_CALC_AUTO', + 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', + 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', + 'DP_VID_M_N_DOUBLE_BUFFER_MODE', 'DP_VID_M_N_GEN_EN', + 'DP_VID_M_N_PROGRAMMED_VIA_REG', 'DP_VID_STREAM_DISABLE_ACK', + 'DP_VID_STREAM_DISABLE_MASK', 'DP_VID_STREAM_DIS_DEFER', + 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', + 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', 'DP_VID_STREAM_DIS_NO_DEFER', + 'DP_VID_TIMING_MODE', 'DP_VID_TIMING_MODE_ASYNC', + 'DP_VID_TIMING_MODE_SYNC', 'DP_VID_VBID_FIELD_POL', + 'DP_VID_VBID_FIELD_POL_INV', 'DP_VID_VBID_FIELD_POL_NORMAL', + 'DP_YCBCR_RANGE', 'DP_YCBCR_RANGE_BT601_5', + 'DP_YCBCR_RANGE_BT709_5', 'DSI_BIT_SWAP', 'DSI_BIT_SWAP_DISABLE', + 'DSI_BIT_SWAP_ENABLE', 'DSI_CLK_GATING', 'DSI_CLK_GATING_DISABLE', + 'DSI_CLK_GATING_ENABLE', 'DSI_CLOCK_LANE_DISABLE', + 'DSI_CLOCK_LANE_EN', 'DSI_CLOCK_LANE_ENABLE', + 'DSI_CLOCK_LANE_HS_FORCE_REQUEST', + 'DSI_CLOCK_LANE_HS_FORCE_REQUEST_ASSERT', + 'DSI_CLOCK_LANE_HS_FORCE_REQUEST_DEASSERT', + 'DSI_CMD_EMBEDDED_MODE', 'DSI_CMD_MODE_DISABLE', + 'DSI_CMD_MODE_EN', 'DSI_CMD_MODE_ENABLE', 'DSI_CMD_ORDER', + 'DSI_CMD_ORDER_COMMAND_FIRST', 'DSI_CMD_ORDER_DATA_FIRST', + 'DSI_CMD_PACKET_TYPE', 'DSI_CMD_PACKET_TYPE_LONG', + 'DSI_CMD_PACKET_TYPE_SHORT', 'DSI_CMD_PWR_MODE', + 'DSI_CMD_PWR_MODE_HS', 'DSI_CMD_PWR_MODE_LP', + 'DSI_CMD_USE_CMDFIFO', 'DSI_CMD_USE_DMAFIFO', + 'DSI_COMMAND_DST_FORMAT_RGB111', 'DSI_COMMAND_DST_FORMAT_RGB332', + 'DSI_COMMAND_DST_FORMAT_RGB444', 'DSI_COMMAND_DST_FORMAT_RGB565', + 'DSI_COMMAND_DST_FORMAT_RGB666', 'DSI_COMMAND_DST_FORMAT_RGB888', + 'DSI_COMMAND_MODE_DST_FORMAT', 'DSI_COMMAND_MODE_SRC_FORMAT', + 'DSI_COMMAND_SRC_FORMAT_RGB332', 'DSI_COMMAND_SRC_FORMAT_RGB444', + 'DSI_COMMAND_SRC_FORMAT_RGB555', 'DSI_COMMAND_SRC_FORMAT_RGB565', + 'DSI_COMMAND_SRC_FORMAT_RGB888', 'DSI_COMMAND_SRC_FORMAT_RGB8BIT', + 'DSI_COMMAND_TRIGGER_MODE', 'DSI_COMMAND_TRIGGER_MODE_AUTO', + 'DSI_COMMAND_TRIGGER_MODE_MANUAL', 'DSI_COMMAND_TRIGGER_ORDER', + 'DSI_COMMAND_TRIGGER_ORDER_DENG', 'DSI_COMMAND_TRIGGER_ORDER_DMA', + 'DSI_COMMAND_TRIGGER_SEL', 'DSI_COMMAND_TRIGGER_SEL_CRTC', + 'DSI_COMMAND_TRIGGER_SEL_HW', 'DSI_COMMAND_TRIGGER_SEL_NONE', + 'DSI_COMMAND_TRIGGER_SEL_TE', 'DSI_CONTROLLER_DISABLE', + 'DSI_CONTROLLER_EN', 'DSI_CONTROLLER_ENABLE', + 'DSI_CRC_CAL_DISABLE', 'DSI_CRC_CAL_ENABLE', 'DSI_CRC_ENABLE', + 'DSI_CRTC_FREEZE_TRIG', 'DSI_CRTC_FREEZE_TRIG_ASSERT', + 'DSI_CRTC_FREEZE_TRIG_DEASSERT', 'DSI_CRTC_SEL', + 'DSI_DATA_BUFFER_ID', 'DSI_DATA_BUFFER_OFFSET0', + 'DSI_DATA_BUFFER_OFFSET1', 'DSI_DATA_LANE0_DISABLE', + 'DSI_DATA_LANE0_EN', 'DSI_DATA_LANE0_ENABLE', + 'DSI_DATA_LANE1_DISABLE', 'DSI_DATA_LANE1_EN', + 'DSI_DATA_LANE1_ENABLE', 'DSI_DATA_LANE2_DISABLE', + 'DSI_DATA_LANE2_EN', 'DSI_DATA_LANE2_ENABLE', + 'DSI_DATA_LANE3_DISABLE', 'DSI_DATA_LANE3_EN', + 'DSI_DATA_LANE3_ENABLE', 'DSI_DBG_CLK_SEL', + 'DSI_DEBUG_BYTECLK_SEL', 'DSI_DEBUG_BYTECLK_SEL_AFIFO', + 'DSI_DEBUG_BYTECLK_SEL_EOT', 'DSI_DEBUG_BYTECLK_SEL_LANEBUF0', + 'DSI_DEBUG_BYTECLK_SEL_LANEBUF1', + 'DSI_DEBUG_BYTECLK_SEL_LANEBUF2', + 'DSI_DEBUG_BYTECLK_SEL_LANEBUF3', + 'DSI_DEBUG_BYTECLK_SEL_LANECTRL', + 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO0', + 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO1', + 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO2', + 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO3', + 'DSI_DEBUG_BYTECLK_SEL_PINGPING2', + 'DSI_DEBUG_BYTECLK_SEL_PINGPING3', + 'DSI_DEBUG_BYTECLK_SEL_PINGPONG0', + 'DSI_DEBUG_BYTECLK_SEL_PINGPONG1', 'DSI_DEBUG_DSICLK_SEL', + 'DSI_DEBUG_DSICLK_SEL_AFIFO', 'DSI_DEBUG_DSICLK_SEL_CMDBUFFER', + 'DSI_DEBUG_DSICLK_SEL_CMDFIFO', 'DSI_DEBUG_DSICLK_SEL_CMD_ENGINE', + 'DSI_DEBUG_DSICLK_SEL_LANECTRL', + 'DSI_DEBUG_DSICLK_SEL_RESYNC_FIFO', + 'DSI_DEBUG_DSICLK_SEL_VIDEO_ENGINE', + 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE', + 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_ASSERT', + 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_DEASSERT', + 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX', + 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_ASSERT', + 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_DEASSERT', + 'DSI_DENG_FIFO_LEVEL_CAL_AVERAGE', + 'DSI_DENG_FIFO_LEVEL_OVERWRITE', 'DSI_DENG_FIFO_START', + 'DSI_DENG_FIFO_START_ASSERT', 'DSI_DENG_FIFO_START_DEASSERT', + 'DSI_DENG_FIFO_USE_OVERWRITE_LEVEL', 'DSI_DMAFIFO_READ_WATERMARK', + 'DSI_DMAFIFO_READ_WATERMARK_EIGHTH', + 'DSI_DMAFIFO_READ_WATERMARK_FOURTH', + 'DSI_DMAFIFO_READ_WATERMARK_HALF', + 'DSI_DMAFIFO_READ_WATERMARK_SIXTEENTH', + 'DSI_DMAFIFO_WRITE_WATERMARK', + 'DSI_DMAFIFO_WRITE_WATERMARK_EIGHTH', + 'DSI_DMAFIFO_WRITE_WATERMARK_FOURTH', + 'DSI_DMAFIFO_WRITE_WATERMARK_HALF', + 'DSI_DMAFIFO_WRITE_WATERMARK_SIXTEENTH', 'DSI_DWORD_BYTE_SWAP', + 'DSI_EXT_RESET_POL', 'DSI_EXT_RESET_POL_HIGH', + 'DSI_EXT_RESET_POL_LOW', 'DSI_EXT_TE_MODE', + 'DSI_EXT_TE_MODE_HVSYNC_EDGE', 'DSI_EXT_TE_MODE_HVSYNC_WIDTH', + 'DSI_EXT_TE_MODE_VSYNC_EDGE', 'DSI_EXT_TE_MODE_VSYNC_WIDTH', + 'DSI_EXT_TE_MUX', 'DSI_EXT_TE_POL', 'DSI_EXT_TE_POL_FALLING', + 'DSI_EXT_TE_POL_RISING', 'DSI_FLAG_CLEAR', 'DSI_FLAG_CLR', + 'DSI_FLAG_NO_CLEAR', 'DSI_GET_PIXEL_STREAM_FROM_FMT0', + 'DSI_GET_PIXEL_STREAM_FROM_FMT1', + 'DSI_GET_PIXEL_STREAM_FROM_FMT2', + 'DSI_GET_PIXEL_STREAM_FROM_FMT3', + 'DSI_GET_PIXEL_STREAM_FROM_FMT4', + 'DSI_GET_PIXEL_STREAM_FROM_FMT5', 'DSI_HW_SOURCE_SEL', + 'DSI_INSERT_DCS_COMMAND', 'DSI_INSERT_DCS_COMMAND_DISABLE', + 'DSI_INSERT_DCS_COMMAND_ENABLE', 'DSI_LANE_FORCE_TX_STOP', + 'DSI_LANE_FORCE_TX_STOP_ASSERT', + 'DSI_LANE_FORCE_TX_STOP_DEASSERT', 'DSI_LANE_ULPS_EXIT', + 'DSI_LANE_ULPS_EXIT_ASSERT', 'DSI_LANE_ULPS_EXIT_DEASSERT', + 'DSI_LANE_ULPS_REQUEST', 'DSI_LANE_ULPS_REQUEST_ASSERT', + 'DSI_LANE_ULPS_REQUEST_DEASSERT', 'DSI_MIPI_BIST_RESET', + 'DSI_MIPI_BIST_RESET_ASSERT', 'DSI_MIPI_BIST_RESET_DEASSERT', + 'DSI_MIPI_BIST_START', 'DSI_MIPI_BIST_START_ASSERT', + 'DSI_MIPI_BIST_START_DEASSERT', 'DSI_MIPI_BIST_VIDEO_FRMT', + 'DSI_MIPI_BIST_VIDEO_FRMT_RAW8', + 'DSI_MIPI_BIST_VIDEO_FRMT_YUV422', + 'DSI_NO_RESET_ON_BYTECLK_DOMAIN_LOGIC', + 'DSI_NO_RESET_ON_DISPCLK_DOMAIN_LOGIC', + 'DSI_NO_RESET_ON_DSICLK_DOMAIN_LOGIC', + 'DSI_NO_RESET_ON_ESCCLK_DOMAIN_LOGIC', + 'DSI_PACKET_BYTE_MSB_LSB_FLIP', + 'DSI_PACKET_BYTE_MSB_LSB_FLIP_NO_SWAP', + 'DSI_PACKET_BYTE_MSB_LSB_FLIP_SWAP', 'DSI_PERF_LATENCY_SEL', + 'DSI_PERF_LATENCY_SEL_DATA_LANE0', + 'DSI_PERF_LATENCY_SEL_DATA_LANE1', + 'DSI_PERF_LATENCY_SEL_DATA_LANE2', + 'DSI_PERF_LATENCY_SEL_DATA_LANE3', 'DSI_PHY_DATA_LANE0_DISABLE', + 'DSI_PHY_DATA_LANE0_EN', 'DSI_PHY_DATA_LANE0_ENABLE', + 'DSI_PHY_DATA_LANE1_DISABLE', 'DSI_PHY_DATA_LANE1_EN', + 'DSI_PHY_DATA_LANE1_ENABLE', 'DSI_PHY_DATA_LANE2_DISABLE', + 'DSI_PHY_DATA_LANE2_EN', 'DSI_PHY_DATA_LANE2_ENABLE', + 'DSI_PHY_DATA_LANE3_DISABLE', 'DSI_PHY_DATA_LANE3_EN', + 'DSI_PHY_DATA_LANE3_ENABLE', 'DSI_RESET_BYTECLK', + 'DSI_RESET_DISPCLK', 'DSI_RESET_DSICLK', 'DSI_RESET_ESCCLK', + 'DSI_RESET_ON_BYTECLK_DOMAIN_LOGIC', + 'DSI_RESET_ON_DISPCLK_DOMAIN_LOGIC', + 'DSI_RESET_ON_DSICLK_DOMAIN_LOGIC', + 'DSI_RESET_ON_ESCCLK_DOMAIN_LOGIC', 'DSI_RESET_PANEL', + 'DSI_RESET_PANEL_ASSERT', 'DSI_RESET_PANEL_DEASSERT', + 'DSI_RGB_SWAP', 'DSI_RX_EOT_IGNORE', 'DSI_RX_EOT_IGNORE_DISABLE', + 'DSI_RX_EOT_IGNORE_ENABLE', 'DSI_SWAP_BGR', 'DSI_SWAP_BRG', + 'DSI_SWAP_GBR', 'DSI_SWAP_GRB', 'DSI_SWAP_RBG', 'DSI_SWAP_RGB', + 'DSI_TEST_CLK_SEL_BYTECLK_G', 'DSI_TEST_CLK_SEL_DISPCLK_G', + 'DSI_TEST_CLK_SEL_DISPCLK_P', 'DSI_TEST_CLK_SEL_DISPCLK_R', + 'DSI_TEST_CLK_SEL_DSICLK_G', 'DSI_TEST_CLK_SEL_DSICLK_P', + 'DSI_TEST_CLK_SEL_DSICLK_R', 'DSI_TEST_CLK_SEL_DSICLK_TRN', + 'DSI_TEST_CLK_SEL_ESCCLK_G', 'DSI_TE_SEL_LINK', 'DSI_TE_SEL_PIN', + 'DSI_TE_SRC_SEL', 'DSI_TRAFFIC_MODE_BURST', + 'DSI_TRAFFIC_MODE_RESERVED', 'DSI_TRAFFIC_MODE_SYNC_EVENTS', + 'DSI_TRAFFIC_MODE_SYNC_PULSES', 'DSI_TX_EOT_APPEND', + 'DSI_TX_EOT_APPEND_DISABLE', 'DSI_TX_EOT_APPEND_ENABLE', + 'DSI_USE_CMDFIFO', 'DSI_USE_DENG_LENGTH', + 'DSI_USE_DENG_LENGTH_DISABLE', 'DSI_USE_DENG_LENGTH_ENABLE', + 'DSI_VIDEO_BLLP_PWR_MODE', 'DSI_VIDEO_BLLP_PWR_MODE_HS', + 'DSI_VIDEO_BLLP_PWR_MODE_LP', 'DSI_VIDEO_DST_FORMAT_RGB565', + 'DSI_VIDEO_DST_FORMAT_RGB666_LOOSELY_PACKED', + 'DSI_VIDEO_DST_FORMAT_RGB666_PACKED', + 'DSI_VIDEO_DST_FORMAT_RGB888', 'DSI_VIDEO_EOF_BLLP_PWR_MODE', + 'DSI_VIDEO_EOF_BLLP_PWR_MODE_HS', + 'DSI_VIDEO_EOF_BLLP_PWR_MODE_LP', 'DSI_VIDEO_MODE_DISABLE', + 'DSI_VIDEO_MODE_DST_FORMAT', 'DSI_VIDEO_MODE_EN', + 'DSI_VIDEO_MODE_ENABLE', 'DSI_VIDEO_PULSE_MODE_OPT', + 'DSI_VIDEO_PWR_MODE', 'DSI_VIDEO_PWR_MODE_HS', + 'DSI_VIDEO_PWR_MODE_LP', 'DSI_VIDEO_TRAFFIC_MODE', + 'DSI_XT_TE_MUX_DCLK', 'DSI_XT_TE_MUX_DINV', 'DSI_XT_TE_MUX_FRAME', + 'DSI_XT_TE_MUX_GCLK', 'DSI_XT_TE_MUX_GOE', 'DSI_XT_TE_MUX_GPIO4', + 'DSI_XT_TE_MUX_GPIO5', 'DSI_XT_TE_MUX_LCDD17', 'DSI_XT_TE_MUX_SS', + 'DSM_ENABLE_ERROR_INJECT', 'DSM_ENABLE_ERROR_INJECT_DOUBLE', + 'DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED', + 'DSM_ENABLE_ERROR_INJECT_FED_IN', + 'DSM_ENABLE_ERROR_INJECT_SINGLE', 'DSM_SELECT_INJECT_DELAY', + 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', + 'DSM_SELECT_INJECT_DELAY_NO_DELAY', 'DS_REF_IS_EXT_GENLOCK', + 'DS_REF_IS_PCIE', 'DS_REF_IS_XTALIN', 'DS_REF_SRC', + 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKC_IN_PHASE', + 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', + 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 'DVOACLKC_MVP_IN_PHASE', 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', + 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE', + 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', + 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', + 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKD_IN_PHASE', + 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', 'DVOACLK_COARSE_SKEW_CNTL', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', + 'DVOACLK_FINE_SKEW_CNTL', 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', + 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', 'DVO_ENABLE_RST', + 'DVO_ENABLE_RST_DISABLE', 'DVO_ENABLE_RST_ENABLE', + 'DVO_SOFT_RESET', 'DVO_SOFT_RESET_0', 'DVO_SOFT_RESET_1', + 'DWORD_BYTE_SWAP_BOTH_SWAP', 'DWORD_BYTE_SWAP_BYTE_SWAP', + 'DWORD_BYTE_SWAP_NO_SWAP', 'DWORD_BYTE_SWAP_WORD_SWAP', + 'DYNAMIC_DEEP_SLEEP_EN', 'DYNAMIC_DEEP_SLEEP_ENABLE', + 'DYNAMIC_LIGHT_SLEEP_EN', 'DYNAMIC_LIGHT_SLEEP_ENABLE', + 'DYNAMIC_PIXEL_DEPTH_30BPP', 'DYNAMIC_PIXEL_DEPTH_36BPP', + 'DYNAMIC_SHUT_DOWN_ENABLE', 'DbMemArbWatermarks', + 'DbPRTFaultBehavior', 'DbPSLControl', 'DepthArray', 'DepthFormat', + 'EARLY_Z_THEN_LATE_Z', 'EARLY_Z_THEN_RE_Z', 'ENABLE', + 'ENABLE_CLOCK', 'ENABLE_JITTER_REMOVAL', 'ENABLE_LEGACY_PIPELINE', + 'ENABLE_MEM_PWR_CTRL', 'ENABLE_NGG_PIPELINE', 'ENABLE_THE_CLOCK', + 'ENABLE_THE_FEATURE', 'ENDIAN_8IN16', 'ENDIAN_8IN32', + 'ENDIAN_8IN64', 'ENDIAN_NONE', 'END_OF_PIPE_IB_END', + 'END_OF_PIPE_INCR_DE', 'ENUMS_GDS_PERFCOUNT_SELECT_H', + 'ENUM_NUM_SIMD_PER_CU', 'ENUM_SQ_EXPORT_RAT_INST', + 'ENUM_XDMA_LOCAL_SW_MODE', 'ENUM_XDMA_MSTR_ALPHA_POSITION', + 'ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL', + 'ENUM_XDMA_SLV_ALPHA_POSITION', 'ES_STAGE_DS', 'ES_STAGE_OFF', + 'ES_STAGE_REAL', 'EXPORT_16_16_FLOAT_8PIX', + 'EXPORT_16_16_SIGNED_8PIX', 'EXPORT_16_16_UNSIGNED_8PIX', + 'EXPORT_2C_32BPC_AR', 'EXPORT_2C_32BPC_GR', + 'EXPORT_2P_32BPC_ABGR', 'EXPORT_32BPP_8PIX', 'EXPORT_32_ABGR', + 'EXPORT_32_AR', 'EXPORT_32_GR', 'EXPORT_32_R', 'EXPORT_4C_16BPC', + 'EXPORT_4C_32BPC', 'EXPORT_4P_16BPC_ABGR', 'EXPORT_4P_32BPC_ABGR', + 'EXPORT_4P_32BPC_AR', 'EXPORT_4P_32BPC_GR', 'EXPORT_8P_32BPC_R', + 'EXPORT_ANY_Z', 'EXPORT_FP16_ABGR', 'EXPORT_GREATER_THAN_Z', + 'EXPORT_LESS_THAN_Z', 'EXPORT_RESERVED', 'EXPORT_SIGNED16_ABGR', + 'EXPORT_UNSIGNED16_ABGR', 'EXPORT_UNUSED', 'FAULT_FAIL', + 'FAULT_ONE', 'FAULT_PASS', 'FAULT_ZERO', + 'FBC_IDLE_MASK_DISP_REG_UPDATE', + 'FBC_IDLE_MASK_FBC_ALPHA_COMP_EN', + 'FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF', + 'FBC_IDLE_MASK_FBC_GRPH_COMP_EN', + 'FBC_IDLE_MASK_FBC_MIN_COMPRESSION', + 'FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN', + 'FBC_IDLE_MASK_MASK_BITS', 'FBC_IDLE_MASK_MC_HIT_REGION_0', + 'FBC_IDLE_MASK_MC_HIT_REGION_1', 'FBC_IDLE_MASK_MC_HIT_REGION_2', + 'FBC_IDLE_MASK_MC_HIT_REGION_3', 'FBC_IDLE_MASK_MC_WRITE', + 'FBC_IDLE_MASK_RESERVED1', 'FBC_IDLE_MASK_RESERVED10', + 'FBC_IDLE_MASK_RESERVED11', 'FBC_IDLE_MASK_RESERVED12', + 'FBC_IDLE_MASK_RESERVED13', 'FBC_IDLE_MASK_RESERVED14', + 'FBC_IDLE_MASK_RESERVED15', 'FBC_IDLE_MASK_RESERVED16', + 'FBC_IDLE_MASK_RESERVED17', 'FBC_IDLE_MASK_RESERVED18', + 'FBC_IDLE_MASK_RESERVED19', 'FBC_IDLE_MASK_RESERVED20', + 'FBC_IDLE_MASK_RESERVED21', 'FBC_IDLE_MASK_RESERVED22', + 'FBC_IDLE_MASK_RESERVED23', 'FBC_IDLE_MASK_RESERVED29', + 'FBC_IDLE_MASK_RESERVED30', 'FBC_IDLE_MASK_RESERVED31', + 'FBC_IDLE_MASK_RESERVED7', 'FBC_IDLE_MASK_RESERVED8', + 'FBC_IDLE_MASK_RESERVED9', 'FLUSH_AND_INV_CB_DATA_TS', + 'FLUSH_AND_INV_CB_META', 'FLUSH_AND_INV_CB_PIXEL_DATA', + 'FLUSH_AND_INV_DB_DATA_TS', 'FLUSH_AND_INV_DB_META', + 'FLUSH_CONTROL_FLUSH_NOT_STARTED', 'FLUSH_CONTROL_FLUSH_STARTED', + 'FLUSH_DFSM', 'FLUSH_HS_OUTPUT', 'FLUSH_SX_TS', 'FMT0_SOFT_RESET', + 'FMT0_SOFT_RESET_0', 'FMT0_SOFT_RESET_1', 'FMT1_SOFT_RESET', + 'FMT1_SOFT_RESET_0', 'FMT1_SOFT_RESET_1', 'FMT2_SOFT_RESET', + 'FMT2_SOFT_RESET_0', 'FMT2_SOFT_RESET_1', 'FMT3_SOFT_RESET', + 'FMT3_SOFT_RESET_0', 'FMT3_SOFT_RESET_1', + 'FMT420_MEMORY_SOURCE_SEL', 'FMT420_MEMORY_SOURCE_SEL_FMT0', + 'FMT420_MEMORY_SOURCE_SEL_FMT1', 'FMT420_MEMORY_SOURCE_SEL_FMT2', + 'FMT420_MEMORY_SOURCE_SEL_FMT3', 'FMT420_MEMORY_SOURCE_SEL_FMT4', + 'FMT420_MEMORY_SOURCE_SEL_FMT5', + 'FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED', 'FMT4_SOFT_RESET', + 'FMT4_SOFT_RESET_0', 'FMT4_SOFT_RESET_1', 'FMT5_SOFT_RESET', + 'FMT5_SOFT_RESET_0', 'FMT5_SOFT_RESET_1', 'FMT_1', + 'FMT_10_10_10_2', 'FMT_10_11_11', 'FMT_10_11_11_FLOAT', + 'FMT_11_11_10', 'FMT_11_11_10_FLOAT', 'FMT_16', 'FMT_16_16', + 'FMT_16_16_16', 'FMT_16_16_16_16', 'FMT_16_16_16_16_FLOAT', + 'FMT_16_16_16_FLOAT', 'FMT_16_16_FLOAT', 'FMT_16_FLOAT', + 'FMT_1_5_5_5', 'FMT_1_REVERSED', 'FMT_24_8', 'FMT_24_8_FLOAT', + 'FMT_2_10_10_10', 'FMT_32', 'FMT_32_32', 'FMT_32_32_32', + 'FMT_32_32_32_32', 'FMT_32_32_32_32_FLOAT', 'FMT_32_32_32_FLOAT', + 'FMT_32_32_FLOAT', 'FMT_32_AS_32_32_32_32', 'FMT_32_AS_8', + 'FMT_32_AS_8_8', 'FMT_32_FLOAT', 'FMT_3_3_2', 'FMT_4_4', + 'FMT_4_4_4_4', 'FMT_5_5_5_1', 'FMT_5_6_5', + 'FMT_5_9_9_9_SHAREDEXP', 'FMT_6_5_5', 'FMT_8', 'FMT_8_24', + 'FMT_8_24_FLOAT', 'FMT_8_8', 'FMT_8_8_8', 'FMT_8_8_8_8', + 'FMT_APC3', 'FMT_APC4', 'FMT_APC5', 'FMT_APC6', 'FMT_APC7', + 'FMT_BC1', 'FMT_BC2', 'FMT_BC3', 'FMT_BC4', 'FMT_BC5', 'FMT_BC6', + 'FMT_BC7', 'FMT_BG_RG', 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', + 'FMT_CLAMP_CNTL_COLOR_FORMAT', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', + 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS', + 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', + 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', + 'FMT_CONTROL_PIXEL_ENCODING', + 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', + 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', + 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', + 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', + 'FMT_CONTROL_SUBSAMPLING_MODE', + 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', + 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', + 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', + 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', + 'FMT_CONTROL_SUBSAMPLING_ORDER', + 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', + 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', + 'FMT_CRC_CNTL_CONT_EN', 'FMT_CRC_CNTL_CONT_EN_CONT', + 'FMT_CRC_CNTL_CONT_EN_ONE_SHOT', + 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE', + 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL', + 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN', + 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT', + 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN', + 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD', + 'FMT_CRC_CNTL_INCLUDE_OVERSCAN', + 'FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE', + 'FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE', + 'FMT_CRC_CNTL_INTERLACE_MODE', + 'FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM', + 'FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH', + 'FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM', + 'FMT_CRC_CNTL_INTERLACE_MODE_TOP', 'FMT_CRC_CNTL_ONLY_BLANKB', + 'FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD', + 'FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK', + 'FMT_CRC_CNTL_PSR_MODE_ENABLE', + 'FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC', + 'FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL', 'FMT_CTX1', + 'FMT_DEBUG_CNTL_COLOR_SELECT', 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', + 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', + 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', + 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', 'FMT_DYNAMIC_EXP_MODE', + 'FMT_DYNAMIC_EXP_MODE_10to12', 'FMT_DYNAMIC_EXP_MODE_8to12', + 'FMT_GB_GR', 'FMT_INVALID', 'FMT_RESERVED_33', 'FMT_RESERVED_36', + 'FMT_RESERVED_4', 'FMT_RESERVED_63', 'FMT_SPATIAL_DITHER_MODE', + 'FMT_SPATIAL_DITHER_MODE_0', 'FMT_SPATIAL_DITHER_MODE_1', + 'FMT_SPATIAL_DITHER_MODE_2', 'FMT_SPATIAL_DITHER_MODE_3', + 'FMT_STEREOSYNC_OVR_POL', 'FMT_STEREOSYNC_OVR_POL_INVERTED', + 'FMT_STEREOSYNC_OVR_POL_NOT_INVERTED', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN', + 'FMT_X24_8_32_FLOAT', 'FORCE_BINNING_ON', + 'FORCE_DEEP_SLEEP_REQUEST', 'FORCE_DISABLE', 'FORCE_EARLY_Z', + 'FORCE_ENABLE', 'FORCE_LATE_Z', 'FORCE_LIGHT_SLEEP_REQ', + 'FORCE_LIGHT_SLEEP_REQUEST', 'FORCE_OFF', 'FORCE_OPT_AUTO', + 'FORCE_OPT_DISABLE', 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', + 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', 'FORCE_OPT_ENABLE_IF_SRC_A_0', + 'FORCE_OPT_ENABLE_IF_SRC_A_1', 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', + 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', 'FORCE_RESERVED', 'FORCE_RE_Z', + 'FORCE_SENT', 'FORCE_SHUT_DOWN_REQUEST', 'FORCE_SUMM_BOTH', + 'FORCE_SUMM_MAXZ', 'FORCE_SUMM_MINZ', 'FORCE_SUMM_OFF', + 'FORCE_VBI', 'FORCE_VBI_HIGH', 'FORCE_VBI_LOW', 'FRAG_ALWAYS', + 'FRAG_EQUAL', 'FRAG_GEQUAL', 'FRAG_GREATER', 'FRAG_LEQUAL', + 'FRAG_LESS', 'FRAG_NEVER', 'FRAG_NOTEQUAL', 'ForceControl', + 'GAMUT_REMAP_MODE_1', 'GAMUT_REMAP_MODE_2', 'GAMUT_REMAP_MODE_3', + 'GAMUT_REMAP_MODE_BYPASS', 'GATCL1RequestType', + 'GATCL1_TYPE_BYPASS', 'GATCL1_TYPE_NORMAL', + 'GATCL1_TYPE_SHOOTDOWN', 'GB_EDC_DED_MODE', + 'GB_EDC_DED_MODE_HALT', 'GB_EDC_DED_MODE_INT_HALT', + 'GB_EDC_DED_MODE_LOG', 'GB_TILING_CONFIG_MACROTABLE_SIZE', + 'GB_TILING_CONFIG_TABLE_SIZE', 'GDS_PERFCOUNT_SELECT', + 'GDS_PERF_SEL_DS_ADDR_CONFL', 'GDS_PERF_SEL_DS_BANK_CONFL', + 'GDS_PERF_SEL_GWS_BYPASS', 'GDS_PERF_SEL_GWS_RELEASED', + 'GDS_PERF_SEL_RBUF_HIT', 'GDS_PERF_SEL_RBUF_MISS', + 'GDS_PERF_SEL_SE0_SH0_2COMP_REQ', + 'GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE0_SH0_GDS_RD_OP', + 'GDS_PERF_SEL_SE0_SH0_GDS_REL_OP', + 'GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE0_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE0_SH0_NORET', + 'GDS_PERF_SEL_SE0_SH0_ORD_CNT', + 'GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE0_SH0_RET', + 'GDS_PERF_SEL_SE0_SH1_2COMP_REQ', + 'GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE0_SH1_GDS_RD_OP', + 'GDS_PERF_SEL_SE0_SH1_GDS_REL_OP', + 'GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE0_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE0_SH1_NORET', + 'GDS_PERF_SEL_SE0_SH1_ORD_CNT', + 'GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE0_SH1_RET', + 'GDS_PERF_SEL_SE1_SH0_2COMP_REQ', + 'GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE1_SH0_GDS_RD_OP', + 'GDS_PERF_SEL_SE1_SH0_GDS_REL_OP', + 'GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE1_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE1_SH0_NORET', + 'GDS_PERF_SEL_SE1_SH0_ORD_CNT', + 'GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE1_SH0_RET', + 'GDS_PERF_SEL_SE1_SH1_2COMP_REQ', + 'GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE1_SH1_GDS_RD_OP', + 'GDS_PERF_SEL_SE1_SH1_GDS_REL_OP', + 'GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE1_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE1_SH1_NORET', + 'GDS_PERF_SEL_SE1_SH1_ORD_CNT', + 'GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE1_SH1_RET', + 'GDS_PERF_SEL_SE2_SH0_2COMP_REQ', + 'GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE2_SH0_GDS_RD_OP', + 'GDS_PERF_SEL_SE2_SH0_GDS_REL_OP', + 'GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE2_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE2_SH0_NORET', + 'GDS_PERF_SEL_SE2_SH0_ORD_CNT', + 'GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE2_SH0_RET', + 'GDS_PERF_SEL_SE2_SH1_2COMP_REQ', + 'GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE2_SH1_GDS_RD_OP', + 'GDS_PERF_SEL_SE2_SH1_GDS_REL_OP', + 'GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE2_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE2_SH1_NORET', + 'GDS_PERF_SEL_SE2_SH1_ORD_CNT', + 'GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE2_SH1_RET', + 'GDS_PERF_SEL_SE3_SH0_2COMP_REQ', + 'GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE3_SH0_GDS_RD_OP', + 'GDS_PERF_SEL_SE3_SH0_GDS_REL_OP', + 'GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE3_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE3_SH0_NORET', + 'GDS_PERF_SEL_SE3_SH0_ORD_CNT', + 'GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE3_SH0_RET', + 'GDS_PERF_SEL_SE3_SH1_2COMP_REQ', + 'GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE3_SH1_GDS_RD_OP', + 'GDS_PERF_SEL_SE3_SH1_GDS_REL_OP', + 'GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE3_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE3_SH1_NORET', + 'GDS_PERF_SEL_SE3_SH1_ORD_CNT', + 'GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE3_SH1_RET', + 'GDS_PERF_SEL_WBUF_FLUSH', 'GDS_PERF_SEL_WBUF_WR', + 'GDS_PERF_SEL_WR_COMP', 'GENERICA_STEREOSYNC_SEL', + 'GENERICA_STEREOSYNC_SEL_D1', 'GENERICA_STEREOSYNC_SEL_D2', + 'GENERICA_STEREOSYNC_SEL_D3', 'GENERICA_STEREOSYNC_SEL_D4', + 'GENERICA_STEREOSYNC_SEL_D5', 'GENERICA_STEREOSYNC_SEL_D6', + 'GENERICA_STEREOSYNC_SEL_RESERVED', 'GENERICB_STEREOSYNC_SEL', + 'GENERICB_STEREOSYNC_SEL_D1', 'GENERICB_STEREOSYNC_SEL_D2', + 'GENERICB_STEREOSYNC_SEL_D3', 'GENERICB_STEREOSYNC_SEL_D4', + 'GENERICB_STEREOSYNC_SEL_D5', 'GENERICB_STEREOSYNC_SEL_D6', + 'GENERICB_STEREOSYNC_SEL_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', + 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', + 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE', + 'GLOBAL_CONTROL_CONTROLLER_RESET', 'GLOBAL_CONTROL_FLUSH_CONTROL', + 'GLOBAL_STATUS_FLUSH_STATUS', + 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', + 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', + 'GL__CONSTANT_ALPHA', 'GL__CONSTANT_COLOR', 'GL__DST_ALPHA', + 'GL__DST_COLOR', 'GL__ONE', 'GL__ONE_MINUS_CONSTANT_ALPHA', + 'GL__ONE_MINUS_CONSTANT_COLOR', 'GL__ONE_MINUS_DST_ALPHA', + 'GL__ONE_MINUS_DST_COLOR', 'GL__ONE_MINUS_SRC_ALPHA', + 'GL__ONE_MINUS_SRC_COLOR', 'GL__SRC_ALPHA', + 'GL__SRC_ALPHA_SATURATE', 'GL__SRC_COLOR', 'GL__ZERO', + 'GRBM_PERF_SEL', 'GRBM_PERF_SEL_BCI_BUSY', + 'GRBM_PERF_SEL_CB_BUSY', 'GRBM_PERF_SEL_CB_CLEAN', + 'GRBM_PERF_SEL_COUNT', 'GRBM_PERF_SEL_CPAXI_BUSY', + 'GRBM_PERF_SEL_CPC_BUSY', 'GRBM_PERF_SEL_CPF_BUSY', + 'GRBM_PERF_SEL_CPG_BUSY', 'GRBM_PERF_SEL_CP_BUSY', + 'GRBM_PERF_SEL_CP_COHER_BUSY', 'GRBM_PERF_SEL_CP_DMA_BUSY', + 'GRBM_PERF_SEL_DB_BUSY', 'GRBM_PERF_SEL_DB_CLEAN', + 'GRBM_PERF_SEL_EA_BUSY', 'GRBM_PERF_SEL_GDS_BUSY', + 'GRBM_PERF_SEL_GUI_ACTIVE', 'GRBM_PERF_SEL_IA_BUSY', + 'GRBM_PERF_SEL_IA_NO_DMA_BUSY', 'GRBM_PERF_SEL_PA_BUSY', + 'GRBM_PERF_SEL_RESERVED_0', 'GRBM_PERF_SEL_RESERVED_1', + 'GRBM_PERF_SEL_RESERVED_2', 'GRBM_PERF_SEL_RESERVED_3', + 'GRBM_PERF_SEL_RESERVED_4', 'GRBM_PERF_SEL_RESERVED_5', + 'GRBM_PERF_SEL_RESERVED_6', 'GRBM_PERF_SEL_RLC_BUSY', + 'GRBM_PERF_SEL_RMI_BUSY', 'GRBM_PERF_SEL_SC_BUSY', + 'GRBM_PERF_SEL_SPI_BUSY', 'GRBM_PERF_SEL_SX_BUSY', + 'GRBM_PERF_SEL_TA_BUSY', 'GRBM_PERF_SEL_TC_BUSY', + 'GRBM_PERF_SEL_USER_DEFINED', 'GRBM_PERF_SEL_UTCL2_BUSY', + 'GRBM_PERF_SEL_VGT_BUSY', 'GRBM_PERF_SEL_WD_BUSY', + 'GRBM_PERF_SEL_WD_NO_DMA_BUSY', 'GRBM_SE0_PERF_SEL', + 'GRBM_SE0_PERF_SEL_BCI_BUSY', 'GRBM_SE0_PERF_SEL_CB_BUSY', + 'GRBM_SE0_PERF_SEL_CB_CLEAN', 'GRBM_SE0_PERF_SEL_COUNT', + 'GRBM_SE0_PERF_SEL_DB_BUSY', 'GRBM_SE0_PERF_SEL_DB_CLEAN', + 'GRBM_SE0_PERF_SEL_PA_BUSY', 'GRBM_SE0_PERF_SEL_RESERVED_0', + 'GRBM_SE0_PERF_SEL_RESERVED_1', 'GRBM_SE0_PERF_SEL_RMI_BUSY', + 'GRBM_SE0_PERF_SEL_SC_BUSY', 'GRBM_SE0_PERF_SEL_SPI_BUSY', + 'GRBM_SE0_PERF_SEL_SX_BUSY', 'GRBM_SE0_PERF_SEL_TA_BUSY', + 'GRBM_SE0_PERF_SEL_USER_DEFINED', 'GRBM_SE0_PERF_SEL_VGT_BUSY', + 'GRBM_SE1_PERF_SEL', 'GRBM_SE1_PERF_SEL_BCI_BUSY', + 'GRBM_SE1_PERF_SEL_CB_BUSY', 'GRBM_SE1_PERF_SEL_CB_CLEAN', + 'GRBM_SE1_PERF_SEL_COUNT', 'GRBM_SE1_PERF_SEL_DB_BUSY', + 'GRBM_SE1_PERF_SEL_DB_CLEAN', 'GRBM_SE1_PERF_SEL_PA_BUSY', + 'GRBM_SE1_PERF_SEL_RESERVED_0', 'GRBM_SE1_PERF_SEL_RESERVED_1', + 'GRBM_SE1_PERF_SEL_RMI_BUSY', 'GRBM_SE1_PERF_SEL_SC_BUSY', + 'GRBM_SE1_PERF_SEL_SPI_BUSY', 'GRBM_SE1_PERF_SEL_SX_BUSY', + 'GRBM_SE1_PERF_SEL_TA_BUSY', 'GRBM_SE1_PERF_SEL_USER_DEFINED', + 'GRBM_SE1_PERF_SEL_VGT_BUSY', 'GRBM_SE2_PERF_SEL', + 'GRBM_SE2_PERF_SEL_BCI_BUSY', 'GRBM_SE2_PERF_SEL_CB_BUSY', + 'GRBM_SE2_PERF_SEL_CB_CLEAN', 'GRBM_SE2_PERF_SEL_COUNT', + 'GRBM_SE2_PERF_SEL_DB_BUSY', 'GRBM_SE2_PERF_SEL_DB_CLEAN', + 'GRBM_SE2_PERF_SEL_PA_BUSY', 'GRBM_SE2_PERF_SEL_RESERVED_0', + 'GRBM_SE2_PERF_SEL_RESERVED_1', 'GRBM_SE2_PERF_SEL_RMI_BUSY', + 'GRBM_SE2_PERF_SEL_SC_BUSY', 'GRBM_SE2_PERF_SEL_SPI_BUSY', + 'GRBM_SE2_PERF_SEL_SX_BUSY', 'GRBM_SE2_PERF_SEL_TA_BUSY', + 'GRBM_SE2_PERF_SEL_USER_DEFINED', 'GRBM_SE2_PERF_SEL_VGT_BUSY', + 'GRBM_SE3_PERF_SEL', 'GRBM_SE3_PERF_SEL_BCI_BUSY', + 'GRBM_SE3_PERF_SEL_CB_BUSY', 'GRBM_SE3_PERF_SEL_CB_CLEAN', + 'GRBM_SE3_PERF_SEL_COUNT', 'GRBM_SE3_PERF_SEL_DB_BUSY', + 'GRBM_SE3_PERF_SEL_DB_CLEAN', 'GRBM_SE3_PERF_SEL_PA_BUSY', + 'GRBM_SE3_PERF_SEL_RESERVED_0', 'GRBM_SE3_PERF_SEL_RESERVED_1', + 'GRBM_SE3_PERF_SEL_RMI_BUSY', 'GRBM_SE3_PERF_SEL_SC_BUSY', + 'GRBM_SE3_PERF_SEL_SPI_BUSY', 'GRBM_SE3_PERF_SEL_SX_BUSY', + 'GRBM_SE3_PERF_SEL_TA_BUSY', 'GRBM_SE3_PERF_SEL_USER_DEFINED', + 'GRBM_SE3_PERF_SEL_VGT_BUSY', 'GSTHREADID_SIZE', 'GS_CUT_1024', + 'GS_CUT_128', 'GS_CUT_256', 'GS_CUT_512', 'GS_OFF', + 'GS_SCENARIO_A', 'GS_SCENARIO_B', 'GS_SCENARIO_C', + 'GS_SCENARIO_G', 'GS_STAGE_OFF', 'GS_STAGE_ON', 'GroupInterleave', + 'HDMI_ACR_0_MULTIPLE_RESERVED', 'HDMI_ACR_1_MULTIPLE', + 'HDMI_ACR_2_MULTIPLE', 'HDMI_ACR_3_MULTIPLE_RESERVED', + 'HDMI_ACR_4_MULTIPLE', 'HDMI_ACR_5_MULTIPLE_RESERVED', + 'HDMI_ACR_6_MULTIPLE_RESERVED', 'HDMI_ACR_7_MULTIPLE_RESERVED', + 'HDMI_ACR_AUDIO_PRIORITY', 'HDMI_ACR_CONT', + 'HDMI_ACR_CONT_DISABLE', 'HDMI_ACR_CONT_ENABLE', + 'HDMI_ACR_NOT_SEND', 'HDMI_ACR_N_MULTIPLE', + 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', + 'HDMI_ACR_PKT_SEND', 'HDMI_ACR_SELECT', 'HDMI_ACR_SELECT_32K', + 'HDMI_ACR_SELECT_44K', 'HDMI_ACR_SELECT_48K', + 'HDMI_ACR_SELECT_HW', 'HDMI_ACR_SEND', 'HDMI_ACR_SOURCE', + 'HDMI_ACR_SOURCE_HW', 'HDMI_ACR_SOURCE_SW', + 'HDMI_AUDIO_DELAY_56CLK', 'HDMI_AUDIO_DELAY_58CLK', + 'HDMI_AUDIO_DELAY_DISABLE', 'HDMI_AUDIO_DELAY_EN', + 'HDMI_AUDIO_DELAY_RESERVED', 'HDMI_AUDIO_INFO_CONT', + 'HDMI_AUDIO_INFO_CONT_DISABLE', 'HDMI_AUDIO_INFO_CONT_ENABLE', + 'HDMI_AUDIO_INFO_NOT_SEND', 'HDMI_AUDIO_INFO_PKT_SEND', + 'HDMI_AUDIO_INFO_SEND', + 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', + 'HDMI_AUDIO_SEND_MAX_PACKETS', 'HDMI_AVI_INFO_CONT', + 'HDMI_AVI_INFO_CONT_DISABLE', 'HDMI_AVI_INFO_CONT_ENABLE', + 'HDMI_AVI_INFO_NOT_SEND', 'HDMI_AVI_INFO_PKT_SEND', + 'HDMI_AVI_INFO_SEND', + 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', + 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', + 'HDMI_CLOCK_CHANNEL_RATE', 'HDMI_DATA_SCRAMBLE_DISABLE', + 'HDMI_DATA_SCRAMBLE_EN', 'HDMI_DATA_SCRAMBLE_ENABLE', + 'HDMI_DEEP_COLOR_DEPTH', 'HDMI_DEEP_COLOR_DEPTH_24BPP', + 'HDMI_DEEP_COLOR_DEPTH_30BPP', 'HDMI_DEEP_COLOR_DEPTH_36BPP', + 'HDMI_DEEP_COLOR_DEPTH_RESERVED', 'HDMI_DEFAULT_PAHSE', + 'HDMI_DEFAULT_PHASE_IS_0', 'HDMI_DEFAULT_PHASE_IS_1', + 'HDMI_ERROR_ACK', 'HDMI_ERROR_ACK_INT', 'HDMI_ERROR_MASK', + 'HDMI_ERROR_MASK_INT', 'HDMI_ERROR_NOT_ACK', + 'HDMI_ERROR_NOT_MASK', 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', + 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', 'HDMI_GC_AVMUTE', + 'HDMI_GC_AVMUTE_CONT', 'HDMI_GC_AVMUTE_CONT_DISABLE', + 'HDMI_GC_AVMUTE_CONT_ENABLE', 'HDMI_GC_AVMUTE_SET', + 'HDMI_GC_AVMUTE_UNSET', 'HDMI_GC_CONT', 'HDMI_GC_CONT_DISABLE', + 'HDMI_GC_CONT_ENABLE', 'HDMI_GC_NOT_SEND', 'HDMI_GC_PKT_SEND', + 'HDMI_GC_SEND', 'HDMI_GENERIC0_CONT', + 'HDMI_GENERIC0_CONT_DISABLE', 'HDMI_GENERIC0_CONT_ENABLE', + 'HDMI_GENERIC0_NOT_SEND', 'HDMI_GENERIC0_PKT_SEND', + 'HDMI_GENERIC0_SEND', 'HDMI_GENERIC1_CONT', + 'HDMI_GENERIC1_CONT_DISABLE', 'HDMI_GENERIC1_CONT_ENABLE', + 'HDMI_GENERIC1_NOT_SEND', 'HDMI_GENERIC1_PKT_SEND', + 'HDMI_GENERIC1_SEND', 'HDMI_GENERIC2_CONT', + 'HDMI_GENERIC2_CONT_DISABLE', 'HDMI_GENERIC2_CONT_ENABLE', + 'HDMI_GENERIC2_NOT_SEND', 'HDMI_GENERIC2_PKT_SEND', + 'HDMI_GENERIC2_SEND', 'HDMI_GENERIC3_CONT', + 'HDMI_GENERIC3_CONT_DISABLE', 'HDMI_GENERIC3_CONT_ENABLE', + 'HDMI_GENERIC3_NOT_SEND', 'HDMI_GENERIC3_PKT_SEND', + 'HDMI_GENERIC3_SEND', 'HDMI_ISRC_CONT', 'HDMI_ISRC_CONT_DISABLE', + 'HDMI_ISRC_CONT_ENABLE', 'HDMI_ISRC_NOT_SEND', + 'HDMI_ISRC_PKT_SEND', 'HDMI_ISRC_SEND', + 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', + 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', 'HDMI_KEEPOUT_MODE', + 'HDMI_MPEG_INFO_CONT', 'HDMI_MPEG_INFO_CONT_DISABLE', + 'HDMI_MPEG_INFO_CONT_ENABLE', 'HDMI_MPEG_INFO_NOT_SEND', + 'HDMI_MPEG_INFO_PKT_SEND', 'HDMI_MPEG_INFO_SEND', + 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', + 'HDMI_NO_EXTRA_NULL_PACKET_FILLED', 'HDMI_NULL_NOT_SEND', + 'HDMI_NULL_PKT_SEND', 'HDMI_NULL_SEND', 'HDMI_PACKET_GEN_VERSION', + 'HDMI_PACKET_GEN_VERSION_NEW', 'HDMI_PACKET_GEN_VERSION_OLD', + 'HDMI_PACKING_PHASE_OVERRIDE', 'HDMI_PACKING_PHASE_SET_BY_HW', + 'HDMI_PACKING_PHASE_SET_BY_SW', 'HDMI_SEND_MAX_AUDIO_PACKETS', + 'HPD_INT_CONTROL_ACK', 'HPD_INT_CONTROL_ACK_0', + 'HPD_INT_CONTROL_ACK_1', 'HPD_INT_CONTROL_GEN_INT_ON_CON', + 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', 'HPD_INT_CONTROL_POLARITY', + 'HPD_INT_CONTROL_RX_INT_ACK', 'HPD_INT_CONTROL_RX_INT_ACK_0', + 'HPD_INT_CONTROL_RX_INT_ACK_1', 'HS_STAGE_OFF', 'HS_STAGE_ON', + 'HW_SOURCE_SEL_DSC_JPEG', 'HW_SOURCE_SEL_DSC_VLP', + 'HW_SOURCE_SEL_DSC_VUP', 'HW_SOURCE_SEL_NONE', + 'I2S0_SPDIF0_SOFT_RESET', 'I2S0_SPDIF0_SOFT_RESET_0', + 'I2S0_SPDIF0_SOFT_RESET_1', 'I2S1_SOFT_RESET', + 'I2S1_SOFT_RESET_0', 'I2S1_SOFT_RESET_1', 'I2S_LRCLK_HIGH_LEFT', + 'I2S_LRCLK_LOW_LEFT', 'I2S_LRCLK_POLARITY', + 'I2S_SAMPLE_ALIGNMENT', 'I2S_SAMPLE_BIT_ORDER', + 'I2S_SAMPLE_BIT_ORDER_LSB', 'I2S_SAMPLE_BIT_ORDER_MSB', + 'I2S_SAMPLE_LEFT_ALIGNED', 'I2S_SAMPLE_RIGHT_ALIGNED', + 'I2S_WORD_ALIGNMENT', 'I2S_WORD_ALTERNATE_ALIGNMENT', + 'I2S_WORD_I2S_ALIGNMENT', 'I2S_WORD_SIZE', 'I2S_WORD_SIZE_16', + 'I2S_WORD_SIZE_32', 'IA_PERFCOUNT_SELECT', + 'ID_STREAM_DISABLE_ACKED', 'ID_STREAM_DISABLE_NO_ACK', + 'IH_PERF_SEL', 'IH_PERF_SEL_BIF_LINE0_FALLING', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', + 'IH_PERF_SEL_BIF_LINE0_RISING', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', 'IH_PERF_SEL_BUFFER_IDLE', + 'IH_PERF_SEL_CLIENT0_INT', 'IH_PERF_SEL_CLIENT10_INT', + 'IH_PERF_SEL_CLIENT11_INT', 'IH_PERF_SEL_CLIENT12_INT', + 'IH_PERF_SEL_CLIENT13_INT', 'IH_PERF_SEL_CLIENT14_INT', + 'IH_PERF_SEL_CLIENT15_INT', 'IH_PERF_SEL_CLIENT16_INT', + 'IH_PERF_SEL_CLIENT17_INT', 'IH_PERF_SEL_CLIENT18_INT', + 'IH_PERF_SEL_CLIENT19_INT', 'IH_PERF_SEL_CLIENT1_INT', + 'IH_PERF_SEL_CLIENT20_INT', 'IH_PERF_SEL_CLIENT21_INT', + 'IH_PERF_SEL_CLIENT22_INT', 'IH_PERF_SEL_CLIENT23_INT', + 'IH_PERF_SEL_CLIENT24_INT', 'IH_PERF_SEL_CLIENT25_INT', + 'IH_PERF_SEL_CLIENT26_INT', 'IH_PERF_SEL_CLIENT27_INT', + 'IH_PERF_SEL_CLIENT28_INT', 'IH_PERF_SEL_CLIENT29_INT', + 'IH_PERF_SEL_CLIENT2_INT', 'IH_PERF_SEL_CLIENT30_INT', + 'IH_PERF_SEL_CLIENT31_INT', 'IH_PERF_SEL_CLIENT3_INT', + 'IH_PERF_SEL_CLIENT4_INT', 'IH_PERF_SEL_CLIENT5_INT', + 'IH_PERF_SEL_CLIENT6_INT', 'IH_PERF_SEL_CLIENT7_INT', + 'IH_PERF_SEL_CLIENT8_INT', 'IH_PERF_SEL_CLIENT9_INT', + 'IH_PERF_SEL_CYCLE', 'IH_PERF_SEL_IDLE', 'IH_PERF_SEL_INPUT_IDLE', + 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', + 'IH_PERF_SEL_MC_WR_CLEAN_STALL', 'IH_PERF_SEL_MC_WR_COUNT', + 'IH_PERF_SEL_MC_WR_IDLE', 'IH_PERF_SEL_MC_WR_STALL', + 'IH_PERF_SEL_RB0_FULL', 'IH_PERF_SEL_RB0_FULL_VF0', + 'IH_PERF_SEL_RB0_FULL_VF1', 'IH_PERF_SEL_RB0_FULL_VF10', + 'IH_PERF_SEL_RB0_FULL_VF11', 'IH_PERF_SEL_RB0_FULL_VF12', + 'IH_PERF_SEL_RB0_FULL_VF13', 'IH_PERF_SEL_RB0_FULL_VF14', + 'IH_PERF_SEL_RB0_FULL_VF15', 'IH_PERF_SEL_RB0_FULL_VF2', + 'IH_PERF_SEL_RB0_FULL_VF3', 'IH_PERF_SEL_RB0_FULL_VF4', + 'IH_PERF_SEL_RB0_FULL_VF5', 'IH_PERF_SEL_RB0_FULL_VF6', + 'IH_PERF_SEL_RB0_FULL_VF7', 'IH_PERF_SEL_RB0_FULL_VF8', + 'IH_PERF_SEL_RB0_FULL_VF9', 'IH_PERF_SEL_RB0_OVERFLOW', + 'IH_PERF_SEL_RB0_OVERFLOW_VF0', 'IH_PERF_SEL_RB0_OVERFLOW_VF1', + 'IH_PERF_SEL_RB0_OVERFLOW_VF10', 'IH_PERF_SEL_RB0_OVERFLOW_VF11', + 'IH_PERF_SEL_RB0_OVERFLOW_VF12', 'IH_PERF_SEL_RB0_OVERFLOW_VF13', + 'IH_PERF_SEL_RB0_OVERFLOW_VF14', 'IH_PERF_SEL_RB0_OVERFLOW_VF15', + 'IH_PERF_SEL_RB0_OVERFLOW_VF2', 'IH_PERF_SEL_RB0_OVERFLOW_VF3', + 'IH_PERF_SEL_RB0_OVERFLOW_VF4', 'IH_PERF_SEL_RB0_OVERFLOW_VF5', + 'IH_PERF_SEL_RB0_OVERFLOW_VF6', 'IH_PERF_SEL_RB0_OVERFLOW_VF7', + 'IH_PERF_SEL_RB0_OVERFLOW_VF8', 'IH_PERF_SEL_RB0_OVERFLOW_VF9', + 'IH_PERF_SEL_RB0_RPTR_WRAP', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRAP', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', 'IH_PERF_SEL_RB1_FULL', + 'IH_PERF_SEL_RB1_FULL_VF0', 'IH_PERF_SEL_RB1_FULL_VF1', + 'IH_PERF_SEL_RB1_FULL_VF10', 'IH_PERF_SEL_RB1_FULL_VF11', + 'IH_PERF_SEL_RB1_FULL_VF12', 'IH_PERF_SEL_RB1_FULL_VF13', + 'IH_PERF_SEL_RB1_FULL_VF14', 'IH_PERF_SEL_RB1_FULL_VF15', + 'IH_PERF_SEL_RB1_FULL_VF2', 'IH_PERF_SEL_RB1_FULL_VF3', + 'IH_PERF_SEL_RB1_FULL_VF4', 'IH_PERF_SEL_RB1_FULL_VF5', + 'IH_PERF_SEL_RB1_FULL_VF6', 'IH_PERF_SEL_RB1_FULL_VF7', + 'IH_PERF_SEL_RB1_FULL_VF8', 'IH_PERF_SEL_RB1_FULL_VF9', + 'IH_PERF_SEL_RB1_OVERFLOW', 'IH_PERF_SEL_RB1_OVERFLOW_VF0', + 'IH_PERF_SEL_RB1_OVERFLOW_VF1', 'IH_PERF_SEL_RB1_OVERFLOW_VF10', + 'IH_PERF_SEL_RB1_OVERFLOW_VF11', 'IH_PERF_SEL_RB1_OVERFLOW_VF12', + 'IH_PERF_SEL_RB1_OVERFLOW_VF13', 'IH_PERF_SEL_RB1_OVERFLOW_VF14', + 'IH_PERF_SEL_RB1_OVERFLOW_VF15', 'IH_PERF_SEL_RB1_OVERFLOW_VF2', + 'IH_PERF_SEL_RB1_OVERFLOW_VF3', 'IH_PERF_SEL_RB1_OVERFLOW_VF4', + 'IH_PERF_SEL_RB1_OVERFLOW_VF5', 'IH_PERF_SEL_RB1_OVERFLOW_VF6', + 'IH_PERF_SEL_RB1_OVERFLOW_VF7', 'IH_PERF_SEL_RB1_OVERFLOW_VF8', + 'IH_PERF_SEL_RB1_OVERFLOW_VF9', 'IH_PERF_SEL_RB1_RPTR_WRAP', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB1_WPTR_WRAP', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_FULL', + 'IH_PERF_SEL_RB2_FULL_VF0', 'IH_PERF_SEL_RB2_FULL_VF1', + 'IH_PERF_SEL_RB2_FULL_VF10', 'IH_PERF_SEL_RB2_FULL_VF11', + 'IH_PERF_SEL_RB2_FULL_VF12', 'IH_PERF_SEL_RB2_FULL_VF13', + 'IH_PERF_SEL_RB2_FULL_VF14', 'IH_PERF_SEL_RB2_FULL_VF15', + 'IH_PERF_SEL_RB2_FULL_VF2', 'IH_PERF_SEL_RB2_FULL_VF3', + 'IH_PERF_SEL_RB2_FULL_VF4', 'IH_PERF_SEL_RB2_FULL_VF5', + 'IH_PERF_SEL_RB2_FULL_VF6', 'IH_PERF_SEL_RB2_FULL_VF7', + 'IH_PERF_SEL_RB2_FULL_VF8', 'IH_PERF_SEL_RB2_FULL_VF9', + 'IH_PERF_SEL_RB2_OVERFLOW', 'IH_PERF_SEL_RB2_OVERFLOW_VF0', + 'IH_PERF_SEL_RB2_OVERFLOW_VF1', 'IH_PERF_SEL_RB2_OVERFLOW_VF10', + 'IH_PERF_SEL_RB2_OVERFLOW_VF11', 'IH_PERF_SEL_RB2_OVERFLOW_VF12', + 'IH_PERF_SEL_RB2_OVERFLOW_VF13', 'IH_PERF_SEL_RB2_OVERFLOW_VF14', + 'IH_PERF_SEL_RB2_OVERFLOW_VF15', 'IH_PERF_SEL_RB2_OVERFLOW_VF2', + 'IH_PERF_SEL_RB2_OVERFLOW_VF3', 'IH_PERF_SEL_RB2_OVERFLOW_VF4', + 'IH_PERF_SEL_RB2_OVERFLOW_VF5', 'IH_PERF_SEL_RB2_OVERFLOW_VF6', + 'IH_PERF_SEL_RB2_OVERFLOW_VF7', 'IH_PERF_SEL_RB2_OVERFLOW_VF8', + 'IH_PERF_SEL_RB2_OVERFLOW_VF9', 'IH_PERF_SEL_RB2_RPTR_WRAP', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_WPTR_WRAP', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', 'IMG_DATA_FORMAT', + 'IMG_DATA_FORMAT_10_10_10_2', 'IMG_DATA_FORMAT_10_11_11', + 'IMG_DATA_FORMAT_11_11_10', 'IMG_DATA_FORMAT_16', + 'IMG_DATA_FORMAT_16_16', 'IMG_DATA_FORMAT_16_16_16_16', + 'IMG_DATA_FORMAT_16_AS_16_16_16_16', + 'IMG_DATA_FORMAT_16_AS_32_32', + 'IMG_DATA_FORMAT_16_AS_32_32_32_32', 'IMG_DATA_FORMAT_1_5_5_5', + 'IMG_DATA_FORMAT_24_8', 'IMG_DATA_FORMAT_2_10_10_10', + 'IMG_DATA_FORMAT_32', 'IMG_DATA_FORMAT_32_32', + 'IMG_DATA_FORMAT_32_32_32', 'IMG_DATA_FORMAT_32_32_32_32', + 'IMG_DATA_FORMAT_32_AS_32_32_32_32', 'IMG_DATA_FORMAT_4_4', + 'IMG_DATA_FORMAT_4_4_4_4', 'IMG_DATA_FORMAT_5_5_5_1', + 'IMG_DATA_FORMAT_5_6_5', 'IMG_DATA_FORMAT_5_9_9_9', + 'IMG_DATA_FORMAT_6E4', 'IMG_DATA_FORMAT_6_5_5', + 'IMG_DATA_FORMAT_8', 'IMG_DATA_FORMAT_8_24', + 'IMG_DATA_FORMAT_8_8', 'IMG_DATA_FORMAT_8_8_8_8', + 'IMG_DATA_FORMAT_8_AS_32', 'IMG_DATA_FORMAT_8_AS_32_32', + 'IMG_DATA_FORMAT_8_AS_8_8_8_8', 'IMG_DATA_FORMAT_ASTC_2D_HDR', + 'IMG_DATA_FORMAT_ASTC_2D_LDR', 'IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB', + 'IMG_DATA_FORMAT_ASTC_3D_HDR', 'IMG_DATA_FORMAT_ASTC_3D_LDR', + 'IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB', 'IMG_DATA_FORMAT_BC1', + 'IMG_DATA_FORMAT_BC2', 'IMG_DATA_FORMAT_BC3', + 'IMG_DATA_FORMAT_BC4', 'IMG_DATA_FORMAT_BC5', + 'IMG_DATA_FORMAT_BC6', 'IMG_DATA_FORMAT_BC7', + 'IMG_DATA_FORMAT_BG_RG', 'IMG_DATA_FORMAT_ETC2_R', + 'IMG_DATA_FORMAT_ETC2_RG', 'IMG_DATA_FORMAT_ETC2_RGB', + 'IMG_DATA_FORMAT_ETC2_RGBA', 'IMG_DATA_FORMAT_ETC2_RGBA1', + 'IMG_DATA_FORMAT_FMASK', 'IMG_DATA_FORMAT_GB_GR', + 'IMG_DATA_FORMAT_INVALID', 'IMG_DATA_FORMAT_N_IN_16', + 'IMG_DATA_FORMAT_N_IN_16_16', 'IMG_DATA_FORMAT_N_IN_16_16_16_16', + 'IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16', + 'IMG_DATA_FORMAT_RESERVED_15', 'IMG_DATA_FORMAT_RESERVED_29', + 'IMG_DATA_FORMAT_RESERVED_30', 'IMG_DATA_FORMAT_RESERVED_56', + 'IMG_DATA_FORMAT_RESERVED_59', 'IMG_DATA_FORMAT_RESERVED_60', + 'IMG_DATA_FORMAT_X24_8_32', 'IMG_NUM_FORMAT', + 'IMG_NUM_FORMAT_ASTC_2D', 'IMG_NUM_FORMAT_ASTC_2D_10x10', + 'IMG_NUM_FORMAT_ASTC_2D_10x5', 'IMG_NUM_FORMAT_ASTC_2D_10x6', + 'IMG_NUM_FORMAT_ASTC_2D_10x8', 'IMG_NUM_FORMAT_ASTC_2D_12x10', + 'IMG_NUM_FORMAT_ASTC_2D_12x12', 'IMG_NUM_FORMAT_ASTC_2D_4x4', + 'IMG_NUM_FORMAT_ASTC_2D_5x4', 'IMG_NUM_FORMAT_ASTC_2D_5x5', + 'IMG_NUM_FORMAT_ASTC_2D_6x5', 'IMG_NUM_FORMAT_ASTC_2D_6x6', + 'IMG_NUM_FORMAT_ASTC_2D_8x5', 'IMG_NUM_FORMAT_ASTC_2D_8x6', + 'IMG_NUM_FORMAT_ASTC_2D_8x8', + 'IMG_NUM_FORMAT_ASTC_2D_RESERVED_14', + 'IMG_NUM_FORMAT_ASTC_2D_RESERVED_15', 'IMG_NUM_FORMAT_ASTC_3D', + 'IMG_NUM_FORMAT_ASTC_3D_3x3x3', 'IMG_NUM_FORMAT_ASTC_3D_4x3x3', + 'IMG_NUM_FORMAT_ASTC_3D_4x4x3', 'IMG_NUM_FORMAT_ASTC_3D_4x4x4', + 'IMG_NUM_FORMAT_ASTC_3D_5x4x4', 'IMG_NUM_FORMAT_ASTC_3D_5x5x4', + 'IMG_NUM_FORMAT_ASTC_3D_5x5x5', 'IMG_NUM_FORMAT_ASTC_3D_6x5x5', + 'IMG_NUM_FORMAT_ASTC_3D_6x6x5', 'IMG_NUM_FORMAT_ASTC_3D_6x6x6', + 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_10', + 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_11', + 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_12', + 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_13', + 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_14', + 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_15', 'IMG_NUM_FORMAT_FLOAT', + 'IMG_NUM_FORMAT_FMASK', 'IMG_NUM_FORMAT_FMASK_16_16_1', + 'IMG_NUM_FORMAT_FMASK_16_8_2', 'IMG_NUM_FORMAT_FMASK_32_16_2', + 'IMG_NUM_FORMAT_FMASK_32_8_4', 'IMG_NUM_FORMAT_FMASK_32_8_8', + 'IMG_NUM_FORMAT_FMASK_64_16_4', 'IMG_NUM_FORMAT_FMASK_64_16_8', + 'IMG_NUM_FORMAT_FMASK_8_2_1', 'IMG_NUM_FORMAT_FMASK_8_2_2', + 'IMG_NUM_FORMAT_FMASK_8_4_1', 'IMG_NUM_FORMAT_FMASK_8_4_2', + 'IMG_NUM_FORMAT_FMASK_8_4_4', 'IMG_NUM_FORMAT_FMASK_8_8_1', + 'IMG_NUM_FORMAT_FMASK_RESERVED_13', + 'IMG_NUM_FORMAT_FMASK_RESERVED_14', + 'IMG_NUM_FORMAT_FMASK_RESERVED_15', 'IMG_NUM_FORMAT_N_IN_16', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_0', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_10', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_11', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_12', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_13', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_14', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_15', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_3', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_6', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_9', + 'IMG_NUM_FORMAT_N_IN_16_UINT_10', 'IMG_NUM_FORMAT_N_IN_16_UINT_9', + 'IMG_NUM_FORMAT_N_IN_16_UNORM_10', + 'IMG_NUM_FORMAT_N_IN_16_UNORM_9', + 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10', + 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9', + 'IMG_NUM_FORMAT_RESERVED_10', 'IMG_NUM_FORMAT_RESERVED_11', + 'IMG_NUM_FORMAT_RESERVED_12', 'IMG_NUM_FORMAT_RESERVED_13', + 'IMG_NUM_FORMAT_RESERVED_14', 'IMG_NUM_FORMAT_RESERVED_15', + 'IMG_NUM_FORMAT_RESERVED_8', 'IMG_NUM_FORMAT_SINT', + 'IMG_NUM_FORMAT_SNORM', 'IMG_NUM_FORMAT_SRGB', + 'IMG_NUM_FORMAT_SSCALED', 'IMG_NUM_FORMAT_UINT', + 'IMG_NUM_FORMAT_UNORM', 'IMG_NUM_FORMAT_UNORM_UINT', + 'IMG_NUM_FORMAT_USCALED', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', + 'INGAMMA_MODE_BYPASS', 'INGAMMA_MODE_FIX', 'INGAMMA_MODE_FLOAT', + 'INPUTCSC_MODE_A', 'INPUTCSC_MODE_B', 'INPUTCSC_MODE_BYPASS', + 'INPUTCSC_MODE_UNITY', 'INPUTCSC_ROUND', 'INPUTCSC_TRUNCATE', + 'INPUTCSC_TYPE_10_2', 'INPUTCSC_TYPE_12_0', 'INPUTCSC_TYPE_8_4', + 'INPUT_COVERAGE', 'INPUT_DEPTH_COVERAGE', 'INPUT_INNER_COVERAGE', + 'INST_ID_ECC_INTERRUPT_MSG', 'INST_ID_HOST_REG_TRAP_MSG', + 'INST_ID_HW_TRAP', 'INST_ID_KILL_SEQ', 'INST_ID_PRIV_START', + 'INST_ID_SPI_WREXEC', 'INST_ID_TTRACE_NEW_PC_MSG', + 'INTERLACE_SOURCE_INTERLEAVE', 'INTERLACE_SOURCE_PROGRESSIVE', + 'INTERLACE_SOURCE_STACK', 'INTERLEAVE_DIS', 'INTERLEAVE_EN', + 'IQ_DEQUEUE_RETRY', 'IQ_INTR_TYPE_IB', 'IQ_INTR_TYPE_MQD', + 'IQ_INTR_TYPE_PQ', 'IQ_OFFLOAD_RETRY', 'IQ_QUEUE_SLEEP', + 'IQ_SCH_WAVE_MSG', 'IQ_SEM_REARM', 'JITTER_REMOVE_DISABLE', + 'LATE_Z', 'LBV_DITHER_EN', 'LBV_DOWNSCALE_PREFETCH_EN', + 'LBV_DYNAMIC_PIXEL_DEPTH', 'LBV_INTERLEAVE_EN', + 'LBV_MEMORY_CONFIG', 'LBV_PIXEL_DEPTH', 'LBV_PIXEL_EXPAN_MODE', + 'LBV_PIXEL_REDUCE_MODE', 'LBV_SYNC_DURATION', + 'LBV_SYNC_RESET_SEL2', 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK', + 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL', + 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET', + 'LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK', + 'LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL', + 'LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET', + 'LB_DATA_FORMAT_ALPHA_DISABLE', 'LB_DATA_FORMAT_ALPHA_EN', + 'LB_DATA_FORMAT_ALPHA_ENABLE', + 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH', + 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP', + 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP', + 'LB_DATA_FORMAT_INTERLEAVE_DISABLE', + 'LB_DATA_FORMAT_INTERLEAVE_EN', + 'LB_DATA_FORMAT_INTERLEAVE_ENABLE', 'LB_DATA_FORMAT_PIXEL_DEPTH', + 'LB_DATA_FORMAT_PIXEL_DEPTH_18BPP', + 'LB_DATA_FORMAT_PIXEL_DEPTH_24BPP', + 'LB_DATA_FORMAT_PIXEL_DEPTH_30BPP', + 'LB_DATA_FORMAT_PIXEL_DEPTH_36BPP', + 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE', + 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION', + 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION', + 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE', + 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING', + 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION', + 'LB_DATA_FORMAT_REQUEST_MODE', + 'LB_DATA_FORMAT_REQUEST_MODE_NORMAL', + 'LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE', + 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE', + 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE', + 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO', + 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO', + 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE', + 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO', + 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL', + 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0', + 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1', + 'LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE', + 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE', + 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE', + 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK', + 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE', + 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE', + 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK', + 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE', + 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE', + 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK', + 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE', + 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN', + 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE', + 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE', + 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE', + 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN', + 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL', + 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET', + 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK', + 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0', + 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1', + 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE', + 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE', + 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP', + 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP', + 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE', + 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN', + 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE', + 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE', + 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG', + 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE', + 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT', + 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION', + 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS', + 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS', + 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS', + 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS', + 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL', + 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2', + 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK', + 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC', + 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE', + 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET', + 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK', + 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET', + 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN', + 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0', + 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1', + 'LB_VBLANK_STATUS_VBLANK_ACK', 'LB_VBLANK_STATUS_VBLANK_CLEAR', + 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE', + 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED', + 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED', + 'LB_VBLANK_STATUS_VBLANK_NORMAL', + 'LB_VLINE2_START_END_VLINE2_INV', + 'LB_VLINE2_START_END_VLINE2_INVERSE', + 'LB_VLINE2_START_END_VLINE2_NORMAL', + 'LB_VLINE2_STATUS_VLINE2_ACK', 'LB_VLINE2_STATUS_VLINE2_CLEAR', + 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE', + 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED', + 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED', + 'LB_VLINE2_STATUS_VLINE2_NORMAL', 'LB_VLINE_START_END_VLINE_INV', + 'LB_VLINE_START_END_VLINE_INVERSE', + 'LB_VLINE_START_END_VLINE_NORMAL', 'LB_VLINE_STATUS_VLINE_ACK', + 'LB_VLINE_STATUS_VLINE_CLEAR', + 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE', + 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED', + 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED', + 'LB_VLINE_STATUS_VLINE_NORMAL', 'LINESTRIP', + 'LPT_NUM_BANKS_16BANK', 'LPT_NUM_BANKS_2BANK', + 'LPT_NUM_BANKS_32BANK', 'LPT_NUM_BANKS_4BANK', + 'LPT_NUM_BANKS_8BANK', 'LPT_NUM_PIPES_1CH', 'LPT_NUM_PIPES_2CH', + 'LPT_NUM_PIPES_4CH', 'LPT_NUM_PIPES_8CH', 'LS_STAGE_OFF', + 'LS_STAGE_ON', 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', + 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', + 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT', 'LptNumBanks', 'LptNumPipes', + 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK', + 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE', + 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE', + 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK', + 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', + 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', + 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK', + 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE', + 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA', 'MEMORY_CONFIG_0', + 'MEMORY_CONFIG_1', 'MEMORY_CONFIG_2', 'MEMORY_CONFIG_3', + 'MEM_ARB_MODE_AGE', 'MEM_ARB_MODE_BOTH', 'MEM_ARB_MODE_FIXED', + 'MEM_ARB_MODE_WEIGHT', 'MEM_PWR_DIS_CTRL', 'MEM_PWR_FORCE_CTRL', + 'MEM_PWR_FORCE_CTRL2', 'MEM_PWR_SEL_CTRL', 'MEM_PWR_SEL_CTRL2', + 'ME_ID0', 'ME_ID1', 'ME_ID2', 'ME_ID3', + 'MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK', + 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', + 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL', + 'MICRO_TILE_MODE_DISPLAY_2D', 'MICRO_TILE_MODE_DISPLAY_3D', + 'MICRO_TILE_MODE_LINEAR', 'MICRO_TILE_MODE_ROTATED', + 'MICRO_TILE_MODE_STD_2D', 'MICRO_TILE_MODE_STD_3D', + 'MICRO_TILE_MODE_Z_2D', 'MICRO_TILE_MODE_Z_3D', + 'MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK', + 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', + 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL', + 'MSA_MISC0_OVERRIDE_DISABLE', 'MSA_MISC0_OVERRIDE_ENABLE', + 'MSA_MISC1_BIT7_OVERRIDE_DISABLE', + 'MSA_MISC1_BIT7_OVERRIDE_ENABLE', + 'MSA_V_TIMING_OVERRIDE_DISABLED', 'MSA_V_TIMING_OVERRIDE_ENABLED', + 'MTYPE', 'MTYPE_CC', 'MTYPE_NC', 'MTYPE_RW', 'MTYPE_UC', + 'MTYPE_WC', 'MULT_16', 'MULT_8', 'MVP_CLK_SRC_SEL', + 'MVP_CLK_SRC_SEL_IO_1', 'MVP_CLK_SRC_SEL_IO_2', + 'MVP_CLK_SRC_SEL_REFCLK', 'MVP_CLK_SRC_SEL_RSRV', + 'MVP_SOFT_RESET', 'MVP_SOFT_RESET_0', 'MVP_SOFT_RESET_1', + 'MacroTileAspect', 'MemArbMode', 'MicroTileMode', + 'MultiGPUTileSize', 'NOT_SENT', 'NO_DIST', 'NO_FORCE', + 'NO_FORCE_REQ', 'NO_FORCE_REQUEST', 'NUMBER_FLOAT', 'NUMBER_SINT', + 'NUMBER_SNORM', 'NUMBER_SRGB', 'NUMBER_SSCALED', 'NUMBER_UINT', + 'NUMBER_UNORM', 'NUMBER_USCALED', 'NUM_SIMD_PER_CU', + 'NonDispTilingOrder', 'NumBanks', 'NumBanksConfig', 'NumGPUs', + 'NumLowerPipes', 'NumMaxCompressedFragments', 'NumPipes', + 'NumRbPerShaderEngine', 'NumShaderEngines', 'OFFCHIP_HS_DEALLOC', + 'OFF_SEQ', 'ON_SEQ', 'OPT_COMB_ADD', 'OPT_COMB_BLEND_DISABLED', + 'OPT_COMB_MAX', 'OPT_COMB_MIN', 'OPT_COMB_NONE', + 'OPT_COMB_REVSUBTRACT', 'OPT_COMB_SAFE_ADD', 'OPT_COMB_SUBTRACT', + 'OUTPUT_LINE', 'OUTPUT_POINT', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 'OUTPUT_TRIANGLE_CCW', 'OUTPUT_TRIANGLE_CW', + 'OVERRIDE_CGTT_DCEFCLK', 'OVERRIDE_CGTT_DCEFCLK_NOOP', + 'OVERRIDE_CGTT_SCLK', 'OVERRIDE_CGTT_SCLK_NOOP', 'PART_FRAC_EVEN', + 'PART_FRAC_ODD', 'PART_INTEGER', 'PART_POW2', 'PATCHES', + 'PERFCOUNTER_ACTIVE', 'PERFCOUNTER_CNT0_STATE', + 'PERFCOUNTER_CNT0_STATE_FREEZE', 'PERFCOUNTER_CNT0_STATE_HW', + 'PERFCOUNTER_CNT0_STATE_RESET', 'PERFCOUNTER_CNT0_STATE_START', + 'PERFCOUNTER_CNT1_STATE', 'PERFCOUNTER_CNT1_STATE_FREEZE', + 'PERFCOUNTER_CNT1_STATE_HW', 'PERFCOUNTER_CNT1_STATE_RESET', + 'PERFCOUNTER_CNT1_STATE_START', 'PERFCOUNTER_CNT2_STATE', + 'PERFCOUNTER_CNT2_STATE_FREEZE', 'PERFCOUNTER_CNT2_STATE_HW', + 'PERFCOUNTER_CNT2_STATE_RESET', 'PERFCOUNTER_CNT2_STATE_START', + 'PERFCOUNTER_CNT3_STATE', 'PERFCOUNTER_CNT3_STATE_FREEZE', + 'PERFCOUNTER_CNT3_STATE_HW', 'PERFCOUNTER_CNT3_STATE_RESET', + 'PERFCOUNTER_CNT3_STATE_START', 'PERFCOUNTER_CNT4_STATE', + 'PERFCOUNTER_CNT4_STATE_FREEZE', 'PERFCOUNTER_CNT4_STATE_HW', + 'PERFCOUNTER_CNT4_STATE_RESET', 'PERFCOUNTER_CNT4_STATE_START', + 'PERFCOUNTER_CNT5_STATE', 'PERFCOUNTER_CNT5_STATE_FREEZE', + 'PERFCOUNTER_CNT5_STATE_HW', 'PERFCOUNTER_CNT5_STATE_RESET', + 'PERFCOUNTER_CNT5_STATE_START', 'PERFCOUNTER_CNT6_STATE', + 'PERFCOUNTER_CNT6_STATE_FREEZE', 'PERFCOUNTER_CNT6_STATE_HW', + 'PERFCOUNTER_CNT6_STATE_RESET', 'PERFCOUNTER_CNT6_STATE_START', + 'PERFCOUNTER_CNT7_STATE', 'PERFCOUNTER_CNT7_STATE_FREEZE', + 'PERFCOUNTER_CNT7_STATE_HW', 'PERFCOUNTER_CNT7_STATE_RESET', + 'PERFCOUNTER_CNT7_STATE_START', 'PERFCOUNTER_CNTL_SEL', + 'PERFCOUNTER_CNTL_SEL_0', 'PERFCOUNTER_CNTL_SEL_1', + 'PERFCOUNTER_CNTL_SEL_2', 'PERFCOUNTER_CNTL_SEL_3', + 'PERFCOUNTER_CNTL_SEL_4', 'PERFCOUNTER_CNTL_SEL_5', + 'PERFCOUNTER_CNTL_SEL_6', 'PERFCOUNTER_CNTL_SEL_7', + 'PERFCOUNTER_CNTOFF_START_DIS', + 'PERFCOUNTER_CNTOFF_START_DISABLE', + 'PERFCOUNTER_CNTOFF_START_ENABLE', + 'PERFCOUNTER_COUNTED_VALUE_TYPE', + 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', + 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', + 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', 'PERFCOUNTER_CVALUE_SEL', + 'PERFCOUNTER_CVALUE_SEL_11_0', 'PERFCOUNTER_CVALUE_SEL_15_0', + 'PERFCOUNTER_CVALUE_SEL_23_12', 'PERFCOUNTER_CVALUE_SEL_31_16', + 'PERFCOUNTER_CVALUE_SEL_35_24', 'PERFCOUNTER_CVALUE_SEL_47_0', + 'PERFCOUNTER_CVALUE_SEL_47_32', 'PERFCOUNTER_CVALUE_SEL_47_36', + 'PERFCOUNTER_HW_CNTL_SEL', 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', + 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', 'PERFCOUNTER_INC_MODE', + 'PERFCOUNTER_INC_MODE_BOTH_EDGE', 'PERFCOUNTER_INC_MODE_LSB', + 'PERFCOUNTER_INC_MODE_MULTI_BIT', 'PERFCOUNTER_INC_MODE_NEG_EDGE', + 'PERFCOUNTER_INC_MODE_POS_EDGE', 'PERFCOUNTER_INT_DISABLE', + 'PERFCOUNTER_INT_EN', 'PERFCOUNTER_INT_ENABLE', + 'PERFCOUNTER_INT_TYPE', 'PERFCOUNTER_INT_TYPE_LEVEL', + 'PERFCOUNTER_INT_TYPE_PULSE', 'PERFCOUNTER_IS_ACTIVE', + 'PERFCOUNTER_IS_IDLE', 'PERFCOUNTER_OFF_MASK', + 'PERFCOUNTER_OFF_MASK_DISABLE', 'PERFCOUNTER_OFF_MASK_ENABLE', + 'PERFCOUNTER_RESTART_DISABLE', 'PERFCOUNTER_RESTART_EN', + 'PERFCOUNTER_RESTART_ENABLE', 'PERFCOUNTER_RUNEN_MODE', + 'PERFCOUNTER_RUNEN_MODE_EDGE', 'PERFCOUNTER_RUNEN_MODE_LEVEL', + 'PERFCOUNTER_SAMPLE', 'PERFCOUNTER_START', + 'PERFCOUNTER_STATE_SEL0', 'PERFCOUNTER_STATE_SEL0_GLOBAL', + 'PERFCOUNTER_STATE_SEL0_LOCAL', 'PERFCOUNTER_STATE_SEL1', + 'PERFCOUNTER_STATE_SEL1_GLOBAL', 'PERFCOUNTER_STATE_SEL1_LOCAL', + 'PERFCOUNTER_STATE_SEL2', 'PERFCOUNTER_STATE_SEL2_GLOBAL', + 'PERFCOUNTER_STATE_SEL2_LOCAL', 'PERFCOUNTER_STATE_SEL3', + 'PERFCOUNTER_STATE_SEL3_GLOBAL', 'PERFCOUNTER_STATE_SEL3_LOCAL', + 'PERFCOUNTER_STATE_SEL4', 'PERFCOUNTER_STATE_SEL4_GLOBAL', + 'PERFCOUNTER_STATE_SEL4_LOCAL', 'PERFCOUNTER_STATE_SEL5', + 'PERFCOUNTER_STATE_SEL5_GLOBAL', 'PERFCOUNTER_STATE_SEL5_LOCAL', + 'PERFCOUNTER_STATE_SEL6', 'PERFCOUNTER_STATE_SEL6_GLOBAL', + 'PERFCOUNTER_STATE_SEL6_LOCAL', 'PERFCOUNTER_STATE_SEL7', + 'PERFCOUNTER_STATE_SEL7_GLOBAL', 'PERFCOUNTER_STATE_SEL7_LOCAL', + 'PERFCOUNTER_STOP', 'PERFMON_CNTOFF_AND', 'PERFMON_CNTOFF_AND_OR', + 'PERFMON_CNTOFF_INT_DISABLE', 'PERFMON_CNTOFF_INT_EN', + 'PERFMON_CNTOFF_INT_ENABLE', 'PERFMON_CNTOFF_INT_TYPE', + 'PERFMON_CNTOFF_INT_TYPE_LEVEL', 'PERFMON_CNTOFF_INT_TYPE_PULSE', + 'PERFMON_CNTOFF_OR', 'PERFMON_COUNTER_MODE', + 'PERFMON_COUNTER_MODE_ACCUM', + 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', + 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', + 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', + 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', + 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', + 'PERFMON_COUNTER_MODE_DIRTY', + 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', + 'PERFMON_COUNTER_MODE_MAX', 'PERFMON_COUNTER_MODE_RESERVED', + 'PERFMON_COUNTER_MODE_SAMPLE', 'PERFMON_SPM_MODE', + 'PERFMON_SPM_MODE_16BIT_CLAMP', 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', + 'PERFMON_SPM_MODE_32BIT_CLAMP', 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', + 'PERFMON_SPM_MODE_OFF', 'PERFMON_SPM_MODE_RESERVED_5', + 'PERFMON_SPM_MODE_RESERVED_6', 'PERFMON_SPM_MODE_RESERVED_7', + 'PERFMON_SPM_MODE_TEST_MODE_0', 'PERFMON_SPM_MODE_TEST_MODE_1', + 'PERFMON_SPM_MODE_TEST_MODE_2', 'PERFMON_STATE', + 'PERFMON_STATE_FREEZE', 'PERFMON_STATE_HW', 'PERFMON_STATE_RESET', + 'PERFMON_STATE_START', 'PERF_PAPC_CCGSM_BUSY', + 'PERF_PAPC_CCGSM_IDLE', 'PERF_PAPC_CCGSM_STALLED', + 'PERF_PAPC_CLIPGA_BUSY', 'PERF_PAPC_CLIPGA_IDLE', + 'PERF_PAPC_CLIPGA_STALLED', 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', + 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', 'PERF_PAPC_CLIPSM_BUSY', + 'PERF_PAPC_CLIPSM_IDLE', 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', + 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', + 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', + 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', + 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', 'PERF_PAPC_CLIP_BUSY', + 'PERF_PAPC_CLIP_IDLE', 'PERF_PAPC_CLPRIM_BUSY', + 'PERF_PAPC_CLPRIM_IDLE', 'PERF_PAPC_CLPRIM_STALLED', + 'PERF_PAPC_CLPRIM_STARVED_CCGSM', + 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', + 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', + 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', + 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', + 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', 'PERF_PAPC_CLPR_CULL_PRIM', + 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', + 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', + 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', + 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', + 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', 'PERF_PAPC_CLPR_UCP_CULL_PRIM', + 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', + 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', + 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', + 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', 'PERF_PAPC_CLPR_VV_CLIP_PRIM', + 'PERF_PAPC_CLPR_VV_CULL_PRIM', 'PERF_PAPC_CLSM_CLIPPING_PRIM', + 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', 'PERF_PAPC_CLSM_NULL_PRIM', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', + 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', + 'PERF_PAPC_CL_DYN_SCLK_VLD', 'PERF_PAPC_PASX_DISABLE_PIPE', + 'PERF_PAPC_PASX_FIRST_DEAD', 'PERF_PAPC_PASX_FIRST_VECTOR', + 'PERF_PAPC_PASX_REC_BUSY', 'PERF_PAPC_PASX_REC_IDLE', + 'PERF_PAPC_PASX_REC_STALLED', + 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', + 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', + 'PERF_PAPC_PASX_REC_STARVED_SX', 'PERF_PAPC_PASX_REQ', + 'PERF_PAPC_PASX_REQ_BUSY', 'PERF_PAPC_PASX_REQ_IDLE', + 'PERF_PAPC_PASX_REQ_STALLED', 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', + 'PERF_PAPC_PASX_SE0_REQ', 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', + 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', 'PERF_PAPC_PASX_SE1_REQ', + 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', 'PERF_PAPC_PASX_SECOND_DEAD', + 'PERF_PAPC_PASX_SECOND_VECTOR', 'PERF_PAPC_PASX_VTX_KILL_DISCARD', + 'PERF_PAPC_PASX_VTX_NAN_DISCARD', + 'PERF_PAPC_PA_INPUT_END_OF_PACKET', + 'PERF_PAPC_PA_INPUT_EVENT_FLAG', + 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', + 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_PA_INPUT_NULL_PRIM', 'PERF_PAPC_PA_INPUT_PRIM', + 'PERF_PAPC_PA_REG_SCLK_VLD', 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', + 'PERF_PAPC_SU_BUSY', 'PERF_PAPC_SU_CULLED_PRIM', + 'PERF_PAPC_SU_DYN_SCLK_VLD', 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', + 'PERF_PAPC_SU_IDLE', 'PERF_PAPC_SU_INPUT_CLIP_PRIM', + 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', + 'PERF_PAPC_SU_INPUT_NULL_PRIM', 'PERF_PAPC_SU_INPUT_PRIM', + 'PERF_PAPC_SU_INPUT_PRIM_DUAL', + 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', + 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', + 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', + 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', 'PERF_PAPC_SU_OUTPUT_EOPG', + 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', + 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', 'PERF_PAPC_SU_OUTPUT_PRIM', + 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', + 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', + 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', + 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', + 'PERF_PAPC_SU_POLYMODE_BACK_CULL', + 'PERF_PAPC_SU_POLYMODE_FACE_CULL', + 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', + 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', + 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE01_STALLED_SC', + 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE0_STALLED_SC', + 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE1_STALLED_SC', + 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE2_STALLED_SC', + 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE3_STALLED_SC', 'PERF_PAPC_SU_STALLED_SC', + 'PERF_PAPC_SU_STARVED_CLIP', 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', + 'PERSISTENT_SPACE_END', 'PERSISTENT_SPACE_START', + 'PIPELINESTAT_START', 'PIPELINESTAT_STOP', 'PIPE_ID0', 'PIPE_ID1', + 'PIPE_ID2', 'PIPE_ID3', 'PIPE_PHYPLL_PIXEL_RATE_SOURCE', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG', + 'PIPE_PIXEL_RATE_PLL_SOURCE', + 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', + 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', 'PIPE_PIXEL_RATE_SOURCE', + 'PIPE_PIXEL_RATE_SOURCE_P0PLL', 'PIPE_PIXEL_RATE_SOURCE_P1PLL', + 'PIPE_PIXEL_RATE_SOURCE_P2PLL', 'PIXEL_DEPTH_18BPP', + 'PIXEL_DEPTH_24BPP', 'PIXEL_DEPTH_30BPP', 'PIXEL_DEPTH_38BPP', + 'PIXEL_EXPAN_MODE_DYN_EXP', 'PIXEL_EXPAN_MODE_ZERO_EXP', + 'PIXEL_FORMAT_RGB_444', 'PIXEL_FORMAT_YCBCR_422', + 'PIXEL_FORMAT_YCBCR_444', 'PIXEL_FORMAT_Y_ONLY', + 'PIXEL_PIPE_OCCLUSION_COUNT_0', 'PIXEL_PIPE_OCCLUSION_COUNT_1', + 'PIXEL_PIPE_OCCLUSION_COUNT_2', 'PIXEL_PIPE_OCCLUSION_COUNT_3', + 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', + 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', + 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', + 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', 'PIXEL_PIPE_STAT_CONTROL', + 'PIXEL_PIPE_STAT_DUMP', 'PIXEL_PIPE_STAT_RESET', + 'PIXEL_PIPE_STRIDE_128_BITS', 'PIXEL_PIPE_STRIDE_256_BITS', + 'PIXEL_PIPE_STRIDE_32_BITS', 'PIXEL_PIPE_STRIDE_64_BITS', + 'PIXEL_REDUCE_MODE_ROUNDING', 'PIXEL_REDUCE_MODE_TRUNCATION', + 'PLL_CFG_IF_SOFT_RESET', 'PLL_CFG_IF_SOFT_RESET_FORCE', + 'PLL_CFG_IF_SOFT_RESET_NOOP', 'PM_ASSERT_RESET', + 'PM_ASSERT_RESET_0', 'PM_ASSERT_RESET_1', 'POINTLIST', + 'PRESCALE_MODE_BYPASS', 'PRESCALE_MODE_PROGRAM', + 'PRESCALE_MODE_UNITY', 'PROG_SEQ', 'PSLC_ASAP', 'PSLC_AUTO', + 'PSLC_COUNTDOWN', 'PSLC_ON_HANG_ONLY', 'PS_DONE', + 'PS_PARTIAL_FLUSH', 'PULSE_MODE_OPT_NO_HSA', + 'PULSE_MODE_OPT_SEND', 'PerfCounter_Vals', 'PipeConfig', + 'PipeInterleaveSize', 'PipeTiling', 'PixelPipeCounterId', + 'PixelPipeStride', 'PkrMap', 'PkrXsel', 'PkrXsel2', 'PkrYsel', + 'QuadExportFormat', 'QuadExportFormatOld', + 'RASTER_CONFIG_PKR_MAP_0', 'RASTER_CONFIG_PKR_MAP_1', + 'RASTER_CONFIG_PKR_MAP_2', 'RASTER_CONFIG_PKR_MAP_3', + 'RASTER_CONFIG_PKR_XSEL2_0', 'RASTER_CONFIG_PKR_XSEL2_1', + 'RASTER_CONFIG_PKR_XSEL2_2', 'RASTER_CONFIG_PKR_XSEL2_3', + 'RASTER_CONFIG_PKR_XSEL_0', 'RASTER_CONFIG_PKR_XSEL_1', + 'RASTER_CONFIG_PKR_XSEL_2', 'RASTER_CONFIG_PKR_XSEL_3', + 'RASTER_CONFIG_PKR_YSEL_0', 'RASTER_CONFIG_PKR_YSEL_1', + 'RASTER_CONFIG_PKR_YSEL_2', 'RASTER_CONFIG_PKR_YSEL_3', + 'RASTER_CONFIG_RB_MAP_0', 'RASTER_CONFIG_RB_MAP_1', + 'RASTER_CONFIG_RB_MAP_2', 'RASTER_CONFIG_RB_MAP_3', + 'RASTER_CONFIG_RB_XSEL2_0', 'RASTER_CONFIG_RB_XSEL2_1', + 'RASTER_CONFIG_RB_XSEL2_2', 'RASTER_CONFIG_RB_XSEL2_3', + 'RASTER_CONFIG_RB_XSEL_0', 'RASTER_CONFIG_RB_XSEL_1', + 'RASTER_CONFIG_RB_YSEL_0', 'RASTER_CONFIG_RB_YSEL_1', + 'RASTER_CONFIG_SC_MAP_0', 'RASTER_CONFIG_SC_MAP_1', + 'RASTER_CONFIG_SC_MAP_2', 'RASTER_CONFIG_SC_MAP_3', + 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', 'RASTER_CONFIG_SE_MAP_0', + 'RASTER_CONFIG_SE_MAP_1', 'RASTER_CONFIG_SE_MAP_2', + 'RASTER_CONFIG_SE_MAP_3', 'RASTER_CONFIG_SE_PAIR_MAP_0', + 'RASTER_CONFIG_SE_PAIR_MAP_1', 'RASTER_CONFIG_SE_PAIR_MAP_2', + 'RASTER_CONFIG_SE_PAIR_MAP_3', + 'RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_128_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_128_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', 'RAW', 'READ_256_BITS', + 'READ_512_BITS', 'READ_SEQ', 'RECTLIST', 'REFCLK_CLOCK_EN', + 'REFCLK_CLOCK_EN_ALLOW_SRC_SEL', 'REFCLK_CLOCK_EN_XTALIN_CLK', + 'REFCLK_SRC_SEL', 'REFCLK_SRC_SEL_CPL_REFCLK', + 'REFCLK_SRC_SEL_PCIE_REFCLK', 'REF_ALWAYS', 'REF_EQUAL', + 'REF_GEQUAL', 'REF_GREATER', 'REF_LEQUAL', 'REF_LESS', + 'REF_NEVER', 'REF_NOTEQUAL', 'RESERVED_ES', 'RESERVED_LS', + 'RESERVED_VS', 'RESET_TO_LOWEST_VGT', 'RESET_VTX_CNT', 'RE_Z', + 'RINGID0', 'RINGID1', 'RINGID2', 'RINGID3', + 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL', + 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', + 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL', + 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', + 'RMIPerfSel', 'RMI_CID', 'RMI_CID_CC', 'RMI_CID_CM', 'RMI_CID_DC', + 'RMI_CID_FC', 'RMI_CID_S', 'RMI_CID_TILE', 'RMI_CID_Z', + 'RMI_CID_ZPCPSD', 'RMI_PERF_SEL_BUSY', + 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR', + 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB', + 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR', + 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB', + 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0', + 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1', + 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2', + 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3', + 'RMI_PERF_SEL_DYN_CLK_CMN_VLD', 'RMI_PERF_SEL_DYN_CLK_PERF_VLD', + 'RMI_PERF_SEL_DYN_CLK_RB_VLD', 'RMI_PERF_SEL_EVENT_SEND', + 'RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ', + 'RMI_PERF_SEL_LAT_FIFO_FULL', + 'RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ', + 'RMI_PERF_SEL_LAT_FIFO_NUM_USED', 'RMI_PERF_SEL_NONE', + 'RMI_PERF_SEL_PERF_WINDOW', 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTR', + 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB', + 'RMI_PERF_SEL_POP_DEMUX_RTS_RTR', + 'RMI_PERF_SEL_POP_DEMUX_RTS_RTRB', + 'RMI_PERF_SEL_POP_XNACK_RTSB_RTR', + 'RMI_PERF_SEL_POP_XNACK_RTSB_RTRB', + 'RMI_PERF_SEL_POP_XNACK_RTS_RTR', + 'RMI_PERF_SEL_POP_XNACK_RTS_RTRB', + 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR', + 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB', + 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR', + 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB', + 'RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT', + 'RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT', + 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT', + 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY', + 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR', + 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB', + 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR', + 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB', + 'RMI_PERF_SEL_PRT_FIFO_BUSY', 'RMI_PERF_SEL_PRT_FIFO_NUM_USED', + 'RMI_PERF_SEL_PRT_FIFO_REQ', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', + 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_RDREQ_BUSY', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID0', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID1', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID2', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID3', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID4', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID5', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID6', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID7', + 'RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY', + 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', + 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_WRREQ_BUSY', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID0', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID1', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID2', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID3', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID4', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID5', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID6', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID7', + 'RMI_PERF_SEL_RB_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY', + 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR', + 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB', + 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR', + 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB', + 'RMI_PERF_SEL_REG_CLK_VLD', 'RMI_PERF_SEL_REORDER_FIFO_BUSY', + 'RMI_PERF_SEL_REORDER_FIFO_REQ', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3', + 'RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID0', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID1', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID2', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID3', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID4', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID5', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID6', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID7', + 'RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID', + 'RMI_PERF_SEL_RMI_TC_REQ_BUSY', + 'RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID0', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID1', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID2', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID3', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID4', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID5', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID6', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID7', + 'RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID', + 'RMI_PERF_SEL_RMI_UTC_BUSY', 'RMI_PERF_SEL_RMI_UTC_REQ', + 'RMI_PERF_SEL_SKID_FIFO_BUSY', 'RMI_PERF_SEL_SKID_FIFO_DEPTH', + 'RMI_PERF_SEL_SKID_FIFO_IN_RTS', 'RMI_PERF_SEL_SKID_FIFO_IN_RTSB', + 'RMI_PERF_SEL_SKID_FIFO_OUT_RTS', + 'RMI_PERF_SEL_SKID_FIFO_OUT_RTSB', 'RMI_PERF_SEL_SKID_FIFO_REQ', + 'RMI_PERF_SEL_TCIW_BUSY', 'RMI_PERF_SEL_TCIW_INFLIGHT_COUNT', + 'RMI_PERF_SEL_TCIW_REQ', + 'RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID', + 'RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID', + 'RMI_PERF_SEL_UTCL1_BUSY', 'RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL', + 'RMI_PERF_SEL_UTCL1_LFIFO_FULL', + 'RMI_PERF_SEL_UTCL1_PERMISSION_MISS', + 'RMI_PERF_SEL_UTCL1_REQUEST', + 'RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', + 'RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', + 'RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', + 'RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', + 'RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS', + 'RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', + 'RMI_PERF_SEL_UTCL1_TRANSLATION_MISS', + 'RMI_PERF_SEL_UTCL1_UTCL2_REQ', 'RMI_PERF_SEL_UTC_POP_RTSB_RTR', + 'RMI_PERF_SEL_UTC_POP_RTSB_RTRB', 'RMI_PERF_SEL_UTC_POP_RTS_RTR', + 'RMI_PERF_SEL_UTC_POP_RTS_RTRB', + 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR', + 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB', + 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR', + 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB', + 'RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR', + 'RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR', + 'RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR', + 'RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR', + 'RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR', + 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR', + 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB', + 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR', + 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB', + 'RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR', + 'RMI_PERF_SEL_XNACK_FIFO_BUSY', 'RMI_PERF_SEL_XNACK_FIFO_FULL', + 'RMI_PERF_SEL_XNACK_FIFO_NUM_USED', + 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR', + 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB', + 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR', + 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB', 'ROM_SIGNATURE', + 'ROUND_BY_HALF', 'ROUND_TRUNCATE', 'RST_PIX_CNT', 'RSV_TAG_RAM', + 'RbMap', 'RbXsel', 'RbXsel2', 'RbYsel', 'ReadSize', 'Reserved142', + 'Reserved143', 'Reserved144', 'Reserved145', 'Reserved146', + 'Reserved147', 'Reserved148', 'Reserved149', 'Reserved18', + 'Reserved182', 'Reserved183', 'Reserved184', 'Reserved185', + 'Reserved186', 'Reserved187', 'Reserved188', 'Reserved189', + 'Reserved190', 'Reserved191', 'Reserved192', 'Reserved193', + 'Reserved194', 'Reserved195', 'Reserved196', 'Reserved197', + 'Reserved198', 'Reserved199', 'Reserved200', 'Reserved201', + 'Reserved202', 'Reserved203', 'Reserved204', 'Reserved205', + 'Reserved206', 'Reserved207', 'Reserved208', 'Reserved209', + 'Reserved210', 'Reserved211', 'Reserved212', 'Reserved213', + 'Reserved214', 'Reserved215', 'Reserved216', 'Reserved217', + 'Reserved218', 'Reserved219', 'Reserved23', 'Reserved252', + 'Reserved253', 'Reserved254', 'Reserved255', 'Reserved256', + 'Reserved257', 'Reserved258', 'Reserved259', 'Reserved26', + 'Reserved260', 'Reserved261', 'Reserved262', 'Reserved263', + 'Reserved264', 'Reserved265', 'Reserved266', 'Reserved267', + 'Reserved27', 'Reserved28', 'Reserved29', 'Reserved300', + 'Reserved301', 'Reserved302', 'Reserved303', 'Reserved304', + 'Reserved305', 'Reserved306', 'Reserved307', 'Reserved308', + 'Reserved309', 'Reserved310', 'Reserved311', 'Reserved312', + 'Reserved313', 'Reserved314', 'Reserved315', 'Reserved316', + 'Reserved317', 'Reserved318', 'Reserved319', 'Reserved320', + 'Reserved321', 'Reserved322', 'Reserved323', 'Reserved324', + 'Reserved325', 'Reserved326', 'Reserved327', 'Reserved328', + 'Reserved329', 'Reserved330', 'Reserved331', 'Reserved364', + 'Reserved365', 'Reserved366', 'Reserved367', 'Reserved368', + 'Reserved369', 'Reserved370', 'Reserved371', 'Reserved372', + 'Reserved373', 'Reserved374', 'Reserved375', 'Reserved376', + 'Reserved377', 'Reserved378', 'Reserved379', 'Reserved412', + 'Reserved413', 'Reserved414', 'Reserved415', 'Reserved416', + 'Reserved417', 'Reserved418', 'Reserved419', 'Reserved420', + 'Reserved421', 'Reserved422', 'Reserved423', 'Reserved424', + 'Reserved425', 'Reserved426', 'Reserved427', 'Reserved428', + 'Reserved429', 'Reserved430', 'Reserved431', 'Reserved432', + 'Reserved433', 'Reserved434', 'Reserved435', 'Reserved436', + 'Reserved437', 'Reserved438', 'Reserved439', 'Reserved440', + 'Reserved441', 'Reserved442', 'Reserved443', 'Reserved444', + 'Reserved445', 'Reserved446', 'Reserved447', 'Reserved448', + 'Reserved449', 'Reserved450', 'Reserved451', 'Reserved452', + 'Reserved453', 'Reserved454', 'Reserved455', 'Reserved456', + 'Reserved457', 'Reserved458', 'Reserved459', 'Reserved460', + 'Reserved461', 'Reserved462', 'Reserved463', 'Reserved464', + 'Reserved465', 'Reserved466', 'Reserved467', 'Reserved468', + 'Reserved469', 'Reserved470', 'Reserved471', 'Reserved472', + 'Reserved473', 'Reserved474', 'Reserved475', 'Reserved476', + 'Reserved477', 'Reserved478', 'Reserved479', 'Reserved480', + 'Reserved481', 'Reserved482', 'Reserved483', 'Reserved484', + 'Reserved485', 'Reserved486', 'Reserved487', 'Reserved488', + 'Reserved489', 'Reserved490', 'Reserved491', 'Reserved492', + 'Reserved493', 'Reserved494', 'Reserved495', 'Reserved496', + 'Reserved497', 'Reserved498', 'Reserved499', 'Reserved500', + 'Reserved501', 'Reserved502', 'Reserved503', 'Reserved504', + 'Reserved505', 'Reserved506', 'Reserved507', 'Reserved508', + 'Reserved509', 'Reserved510', 'Reserved511', 'Reserved_0x00', + 'Reserved_0x09', 'Reserved_0x3f', 'RingCounterControl', + 'RoundMode', 'RowSize', 'RowTiling', 'SAMPLE_PIPELINESTAT', + 'SAMPLE_STREAMOUTSTATS', 'SAMPLE_STREAMOUTSTATS1', + 'SAMPLE_STREAMOUTSTATS2', 'SAMPLE_STREAMOUTSTATS3', + 'SCLV_COEF_UPDATE_COMPLETE', 'SCLV_INTERLACE_SOURCE', + 'SCLV_MODE_RGB_BYPASS', 'SCLV_MODE_RGB_SCALING', 'SCLV_MODE_SEL', + 'SCLV_MODE_YCBCR_BYPASS', 'SCLV_MODE_YCBCR_SCALING', + 'SCLV_UPDATE_LOCK', 'SCL_ALU_DISABLE', 'SCL_ALU_DISABLED', + 'SCL_ALU_ENABLED', 'SCL_BOUNDARY_MODE', 'SCL_BOUNDARY_MODE_BLACK', + 'SCL_BOUNDARY_MODE_EDGE', 'SCL_BYPASS_MODE', + 'SCL_BYPASS_MODE_AC_AR', 'SCL_BYPASS_MODE_AC_NR', + 'SCL_BYPASS_MODE_MC_MR', 'SCL_BYPASS_MODE_RESERVED', + 'SCL_COEF_UPDATE_COMPLETE', 'SCL_COEF_UPDATE_COMPLETED', + 'SCL_COEF_UPDATE_NOT_COMPLETED', 'SCL_C_RAM_FILTER_TYPE', + 'SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT', + 'SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT', + 'SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT', + 'SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT', 'SCL_C_RAM_PHASE', + 'SCL_C_RAM_PHASE_0', 'SCL_C_RAM_PHASE_1', 'SCL_C_RAM_PHASE_2', + 'SCL_C_RAM_PHASE_3', 'SCL_C_RAM_PHASE_4', 'SCL_C_RAM_PHASE_5', + 'SCL_C_RAM_PHASE_6', 'SCL_C_RAM_PHASE_7', 'SCL_C_RAM_PHASE_8', + 'SCL_C_RAM_TAP_PAIR_ID0', 'SCL_C_RAM_TAP_PAIR_ID1', + 'SCL_C_RAM_TAP_PAIR_ID2', 'SCL_C_RAM_TAP_PAIR_ID3', + 'SCL_C_RAM_TAP_PAIR_ID4', 'SCL_C_RAM_TAP_PAIR_IDX', + 'SCL_EARLY_EOL_MOD', 'SCL_EARLY_EOL_MODE_CRTC', + 'SCL_EARLY_EOL_MODE_INTERNAL', 'SCL_HF_SHARP_DISABLE', + 'SCL_HF_SHARP_EN', 'SCL_HF_SHARP_ENABLE', + 'SCL_HF_SHARP_SCALE_FACTOR', 'SCL_HF_SHARP_SCALE_FACTOR_0', + 'SCL_HF_SHARP_SCALE_FACTOR_1', 'SCL_HF_SHARP_SCALE_FACTOR_2', + 'SCL_HF_SHARP_SCALE_FACTOR_3', 'SCL_HF_SHARP_SCALE_FACTOR_4', + 'SCL_HF_SHARP_SCALE_FACTOR_5', 'SCL_HF_SHARP_SCALE_FACTOR_6', + 'SCL_HF_SHARP_SCALE_FACTOR_7', + 'SCL_HOST_CONFLICT_DISABLE_INTERRUPT', + 'SCL_HOST_CONFLICT_ENABLE_INTERRUPT', 'SCL_HOST_CONFLICT_MASK', + 'SCL_H_2TAP_HARDCODE_COEF_DISABLE', 'SCL_H_2TAP_HARDCODE_COEF_EN', + 'SCL_H_2TAP_HARDCODE_COEF_ENABLE', + 'SCL_H_CALC_AUTO_RATIO_DISABLE', 'SCL_H_CALC_AUTO_RATIO_EN', + 'SCL_H_CALC_AUTO_RATIO_ENABLE', 'SCL_H_FILTER_PICK_NEAREST', + 'SCL_H_FILTER_PICK_NEAREST_DISABLE', + 'SCL_H_FILTER_PICK_NEAREST_ENABLE', + 'SCL_H_MANUAL_REPLICATE_FACTOR', + 'SCL_H_MANUAL_REPLICATE_FACTOR_1', + 'SCL_H_MANUAL_REPLICATE_FACTOR_10', + 'SCL_H_MANUAL_REPLICATE_FACTOR_11', + 'SCL_H_MANUAL_REPLICATE_FACTOR_12', + 'SCL_H_MANUAL_REPLICATE_FACTOR_13', + 'SCL_H_MANUAL_REPLICATE_FACTOR_14', + 'SCL_H_MANUAL_REPLICATE_FACTOR_15', + 'SCL_H_MANUAL_REPLICATE_FACTOR_16', + 'SCL_H_MANUAL_REPLICATE_FACTOR_2', + 'SCL_H_MANUAL_REPLICATE_FACTOR_3', + 'SCL_H_MANUAL_REPLICATE_FACTOR_4', + 'SCL_H_MANUAL_REPLICATE_FACTOR_5', + 'SCL_H_MANUAL_REPLICATE_FACTOR_6', + 'SCL_H_MANUAL_REPLICATE_FACTOR_7', + 'SCL_H_MANUAL_REPLICATE_FACTOR_8', + 'SCL_H_MANUAL_REPLICATE_FACTOR_9', 'SCL_H_NUM_OF_TAPS', + 'SCL_H_NUM_OF_TAPS_1', 'SCL_H_NUM_OF_TAPS_10', + 'SCL_H_NUM_OF_TAPS_2', 'SCL_H_NUM_OF_TAPS_4', + 'SCL_H_NUM_OF_TAPS_6', 'SCL_H_NUM_OF_TAPS_8', + 'SCL_MODE_CHANGE_DISABLE_INTERRUPT', + 'SCL_MODE_CHANGE_ENABLE_INTERRUPT', 'SCL_MODE_RGB_BYPASS', + 'SCL_MODE_RGB_SCALING', 'SCL_MODE_SEL', 'SCL_MODE_YCBCR_BYPASS', + 'SCL_MODE_YCBCR_SCALING', 'SCL_PSCL_DISABLE', 'SCL_PSCL_EN', + 'SCL_PSCL_ENANBLE', 'SCL_SCL_MODE_CHANGE_MASK', 'SCL_UPDATE_LOCK', + 'SCL_UPDATE_LOCKED', 'SCL_UPDATE_TAKEN', 'SCL_UPDATE_TAKEN_NO', + 'SCL_UPDATE_TAKEN_YES', 'SCL_UPDATE_UNLOCKED', + 'SCL_VF_SHARP_DISABLE', 'SCL_VF_SHARP_EN', 'SCL_VF_SHARP_ENABLE', + 'SCL_VF_SHARP_SCALE_FACTOR', 'SCL_VF_SHARP_SCALE_FACTOR_0', + 'SCL_VF_SHARP_SCALE_FACTOR_1', 'SCL_VF_SHARP_SCALE_FACTOR_2', + 'SCL_VF_SHARP_SCALE_FACTOR_3', 'SCL_VF_SHARP_SCALE_FACTOR_4', + 'SCL_VF_SHARP_SCALE_FACTOR_5', 'SCL_VF_SHARP_SCALE_FACTOR_6', + 'SCL_VF_SHARP_SCALE_FACTOR_7', 'SCL_V_2TAP_HARDCODE_COEF_DISABLE', + 'SCL_V_2TAP_HARDCODE_COEF_EN', 'SCL_V_2TAP_HARDCODE_COEF_ENABLE', + 'SCL_V_CALC_AUTO_RATIO_DISABLE', 'SCL_V_CALC_AUTO_RATIO_EN', + 'SCL_V_CALC_AUTO_RATIO_ENABLE', 'SCL_V_FILTER_PICK_NEAREST', + 'SCL_V_FILTER_PICK_NEAREST_DISABLE', + 'SCL_V_FILTER_PICK_NEAREST_ENABLE', + 'SCL_V_MANUAL_REPLICATE_FACTOR', + 'SCL_V_MANUAL_REPLICATE_FACTOR_1', + 'SCL_V_MANUAL_REPLICATE_FACTOR_10', + 'SCL_V_MANUAL_REPLICATE_FACTOR_11', + 'SCL_V_MANUAL_REPLICATE_FACTOR_12', + 'SCL_V_MANUAL_REPLICATE_FACTOR_13', + 'SCL_V_MANUAL_REPLICATE_FACTOR_14', + 'SCL_V_MANUAL_REPLICATE_FACTOR_15', + 'SCL_V_MANUAL_REPLICATE_FACTOR_16', + 'SCL_V_MANUAL_REPLICATE_FACTOR_2', + 'SCL_V_MANUAL_REPLICATE_FACTOR_3', + 'SCL_V_MANUAL_REPLICATE_FACTOR_4', + 'SCL_V_MANUAL_REPLICATE_FACTOR_5', + 'SCL_V_MANUAL_REPLICATE_FACTOR_6', + 'SCL_V_MANUAL_REPLICATE_FACTOR_7', + 'SCL_V_MANUAL_REPLICATE_FACTOR_8', + 'SCL_V_MANUAL_REPLICATE_FACTOR_9', 'SCL_V_NUM_OF_TAPS', + 'SCL_V_NUM_OF_TAPS_1', 'SCL_V_NUM_OF_TAPS_2', + 'SCL_V_NUM_OF_TAPS_3', 'SCL_V_NUM_OF_TAPS_4', + 'SCL_V_NUM_OF_TAPS_5', 'SCL_V_NUM_OF_TAPS_6', 'SC_BACKEND_BUSY', + 'SC_BB_DISCARD', 'SC_BM_BUSY', 'SC_BUSY_CNT_NOT_ZERO', + 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', 'SC_EARLYZ_QUAD_COUNT', + 'SC_EARLYZ_QUAD_WITH_1_PIX', 'SC_EARLYZ_QUAD_WITH_2_PIX', + 'SC_EARLYZ_QUAD_WITH_3_PIX', 'SC_EARLYZ_QUAD_WITH_4_PIX', + 'SC_EOP_SYNC_WINDOW', 'SC_GRP0_DYN_SCLK_BUSY', + 'SC_GRP1_DYN_SCLK_BUSY', 'SC_GRP2_DYN_SCLK_BUSY', + 'SC_GRP3_DYN_SCLK_BUSY', 'SC_GRP4_DYN_SCLK_BUSY', + 'SC_MULTICYCLE_BUBBLE_FREEZE', 'SC_P0_DETAIL_QUAD_COUNT', + 'SC_P0_DETAIL_QUAD_WITH_1_PIX', 'SC_P0_DETAIL_QUAD_WITH_2_PIX', + 'SC_P0_DETAIL_QUAD_WITH_3_PIX', 'SC_P0_DETAIL_QUAD_WITH_4_PIX', + 'SC_P0_HIZ_QUAD_COUNT', 'SC_P0_HIZ_QUAD_PER_TILE_H0', + 'SC_P0_HIZ_QUAD_PER_TILE_H1', 'SC_P0_HIZ_QUAD_PER_TILE_H10', + 'SC_P0_HIZ_QUAD_PER_TILE_H11', 'SC_P0_HIZ_QUAD_PER_TILE_H12', + 'SC_P0_HIZ_QUAD_PER_TILE_H13', 'SC_P0_HIZ_QUAD_PER_TILE_H14', + 'SC_P0_HIZ_QUAD_PER_TILE_H15', 'SC_P0_HIZ_QUAD_PER_TILE_H16', + 'SC_P0_HIZ_QUAD_PER_TILE_H2', 'SC_P0_HIZ_QUAD_PER_TILE_H3', + 'SC_P0_HIZ_QUAD_PER_TILE_H4', 'SC_P0_HIZ_QUAD_PER_TILE_H5', + 'SC_P0_HIZ_QUAD_PER_TILE_H6', 'SC_P0_HIZ_QUAD_PER_TILE_H7', + 'SC_P0_HIZ_QUAD_PER_TILE_H8', 'SC_P0_HIZ_QUAD_PER_TILE_H9', + 'SC_P0_HIZ_TILE_COUNT', 'SC_P1_DETAIL_QUAD_COUNT', + 'SC_P1_DETAIL_QUAD_WITH_1_PIX', 'SC_P1_DETAIL_QUAD_WITH_2_PIX', + 'SC_P1_DETAIL_QUAD_WITH_3_PIX', 'SC_P1_DETAIL_QUAD_WITH_4_PIX', + 'SC_P1_HIZ_QUAD_COUNT', 'SC_P1_HIZ_QUAD_PER_TILE_H0', + 'SC_P1_HIZ_QUAD_PER_TILE_H1', 'SC_P1_HIZ_QUAD_PER_TILE_H10', + 'SC_P1_HIZ_QUAD_PER_TILE_H11', 'SC_P1_HIZ_QUAD_PER_TILE_H12', + 'SC_P1_HIZ_QUAD_PER_TILE_H13', 'SC_P1_HIZ_QUAD_PER_TILE_H14', + 'SC_P1_HIZ_QUAD_PER_TILE_H15', 'SC_P1_HIZ_QUAD_PER_TILE_H16', + 'SC_P1_HIZ_QUAD_PER_TILE_H2', 'SC_P1_HIZ_QUAD_PER_TILE_H3', + 'SC_P1_HIZ_QUAD_PER_TILE_H4', 'SC_P1_HIZ_QUAD_PER_TILE_H5', + 'SC_P1_HIZ_QUAD_PER_TILE_H6', 'SC_P1_HIZ_QUAD_PER_TILE_H7', + 'SC_P1_HIZ_QUAD_PER_TILE_H8', 'SC_P1_HIZ_QUAD_PER_TILE_H9', + 'SC_P1_HIZ_TILE_COUNT', 'SC_P2_DETAIL_QUAD_COUNT', + 'SC_P2_DETAIL_QUAD_WITH_1_PIX', 'SC_P2_DETAIL_QUAD_WITH_2_PIX', + 'SC_P2_DETAIL_QUAD_WITH_3_PIX', 'SC_P2_DETAIL_QUAD_WITH_4_PIX', + 'SC_P2_HIZ_QUAD_COUNT', 'SC_P2_HIZ_QUAD_PER_TILE_H0', + 'SC_P2_HIZ_QUAD_PER_TILE_H1', 'SC_P2_HIZ_QUAD_PER_TILE_H10', + 'SC_P2_HIZ_QUAD_PER_TILE_H11', 'SC_P2_HIZ_QUAD_PER_TILE_H12', + 'SC_P2_HIZ_QUAD_PER_TILE_H13', 'SC_P2_HIZ_QUAD_PER_TILE_H14', + 'SC_P2_HIZ_QUAD_PER_TILE_H15', 'SC_P2_HIZ_QUAD_PER_TILE_H16', + 'SC_P2_HIZ_QUAD_PER_TILE_H2', 'SC_P2_HIZ_QUAD_PER_TILE_H3', + 'SC_P2_HIZ_QUAD_PER_TILE_H4', 'SC_P2_HIZ_QUAD_PER_TILE_H5', + 'SC_P2_HIZ_QUAD_PER_TILE_H6', 'SC_P2_HIZ_QUAD_PER_TILE_H7', + 'SC_P2_HIZ_QUAD_PER_TILE_H8', 'SC_P2_HIZ_QUAD_PER_TILE_H9', + 'SC_P2_HIZ_TILE_COUNT', 'SC_P3_DETAIL_QUAD_COUNT', + 'SC_P3_DETAIL_QUAD_WITH_1_PIX', 'SC_P3_DETAIL_QUAD_WITH_2_PIX', + 'SC_P3_DETAIL_QUAD_WITH_3_PIX', 'SC_P3_DETAIL_QUAD_WITH_4_PIX', + 'SC_P3_HIZ_QUAD_COUNT', 'SC_P3_HIZ_QUAD_PER_TILE_H0', + 'SC_P3_HIZ_QUAD_PER_TILE_H1', 'SC_P3_HIZ_QUAD_PER_TILE_H10', + 'SC_P3_HIZ_QUAD_PER_TILE_H11', 'SC_P3_HIZ_QUAD_PER_TILE_H12', + 'SC_P3_HIZ_QUAD_PER_TILE_H13', 'SC_P3_HIZ_QUAD_PER_TILE_H14', + 'SC_P3_HIZ_QUAD_PER_TILE_H15', 'SC_P3_HIZ_QUAD_PER_TILE_H16', + 'SC_P3_HIZ_QUAD_PER_TILE_H2', 'SC_P3_HIZ_QUAD_PER_TILE_H3', + 'SC_P3_HIZ_QUAD_PER_TILE_H4', 'SC_P3_HIZ_QUAD_PER_TILE_H5', + 'SC_P3_HIZ_QUAD_PER_TILE_H6', 'SC_P3_HIZ_QUAD_PER_TILE_H7', + 'SC_P3_HIZ_QUAD_PER_TILE_H8', 'SC_P3_HIZ_QUAD_PER_TILE_H9', + 'SC_P3_HIZ_TILE_COUNT', 'SC_PA0_PS_DATA_SEND', + 'SC_PA0_SC_DATA_FIFO_EOPG_RD', 'SC_PA0_SC_DATA_FIFO_EOP_RD', + 'SC_PA0_SC_DATA_FIFO_RD', 'SC_PA0_SC_DATA_FIFO_WE', + 'SC_PA0_SC_DEALLOC_0_RD', 'SC_PA0_SC_DEALLOC_1_RD', + 'SC_PA0_SC_EOPG_WE', 'SC_PA0_SC_EOP_WE', 'SC_PA0_SC_EVENT_WE', + 'SC_PA0_SC_FPOV_WE', 'SC_PA0_SC_LPOV_WE', + 'SC_PA0_SC_NULL_DEALLOC_WE', 'SC_PA0_SC_NULL_WE', + 'SC_PA1_PS_DATA_SEND', 'SC_PA1_SC_DATA_FIFO_EOPG_RD', + 'SC_PA1_SC_DATA_FIFO_EOP_RD', 'SC_PA1_SC_DATA_FIFO_RD', + 'SC_PA1_SC_DATA_FIFO_WE', 'SC_PA1_SC_DEALLOC_0_RD', + 'SC_PA1_SC_DEALLOC_1_RD', 'SC_PA1_SC_EOPG_WE', 'SC_PA1_SC_EOP_WE', + 'SC_PA1_SC_EVENT_WE', 'SC_PA1_SC_FPOV_WE', 'SC_PA1_SC_LPOV_WE', + 'SC_PA1_SC_NULL_DEALLOC_WE', 'SC_PA1_SC_NULL_WE', + 'SC_PA2_PS_DATA_SEND', 'SC_PA2_SC_DATA_FIFO_EOPG_RD', + 'SC_PA2_SC_DATA_FIFO_EOP_RD', 'SC_PA2_SC_DATA_FIFO_RD', + 'SC_PA2_SC_DATA_FIFO_WE', 'SC_PA2_SC_DEALLOC_0_RD', + 'SC_PA2_SC_DEALLOC_1_RD', 'SC_PA2_SC_EOPG_WE', 'SC_PA2_SC_EOP_WE', + 'SC_PA2_SC_EVENT_WE', 'SC_PA2_SC_FPOV_WE', 'SC_PA2_SC_LPOV_WE', + 'SC_PA2_SC_NULL_DEALLOC_WE', 'SC_PA2_SC_NULL_WE', + 'SC_PA3_PS_DATA_SEND', 'SC_PA3_SC_DATA_FIFO_EOPG_RD', + 'SC_PA3_SC_DATA_FIFO_EOP_RD', 'SC_PA3_SC_DATA_FIFO_RD', + 'SC_PA3_SC_DATA_FIFO_WE', 'SC_PA3_SC_DEALLOC_0_RD', + 'SC_PA3_SC_DEALLOC_1_RD', 'SC_PA3_SC_EOPG_WE', 'SC_PA3_SC_EOP_WE', + 'SC_PA3_SC_EVENT_WE', 'SC_PA3_SC_FPOV_WE', 'SC_PA3_SC_LPOV_WE', + 'SC_PA3_SC_NULL_DEALLOC_WE', 'SC_PA3_SC_NULL_WE', + 'SC_PA_SC_DEALLOC_0_0_WE', 'SC_PA_SC_DEALLOC_0_1_WE', + 'SC_PA_SC_DEALLOC_1_0_WE', 'SC_PA_SC_DEALLOC_1_1_WE', + 'SC_PA_SC_DEALLOC_2_0_WE', 'SC_PA_SC_DEALLOC_2_1_WE', + 'SC_PA_SC_DEALLOC_3_0_WE', 'SC_PA_SC_DEALLOC_3_1_WE', + 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', + 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', + 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', + 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', + 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', + 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', + 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', + 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', + 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', + 'SC_PBB_BATCH_HIST_NUM_PRIMS', + 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', + 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', + 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', + 'SC_PBB_BIN_HIST_NUM_CONTEXTS', + 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', + 'SC_PBB_BIN_HIST_NUM_PRIMS', 'SC_PBB_BUSY', 'SC_PBB_BUSY_AND_RTR', + 'SC_PBB_END_OF_BATCH', 'SC_PBB_END_OF_BIN', + 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', + 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', + 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', + 'SC_PBB_NONBINNED_PRIM', 'SC_PBB_NUM_BINS', + 'SC_PBB_PRIMBIN_PROCESSED', 'SC_PBB_PRIM_ADDED_TO_BATCH', + 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', + 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', + 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', 'SC_PERFCNT_SEL', + 'SC_PKR_4X2_FILL_QUAD', 'SC_PKR_4X2_QUAD_SPLIT', + 'SC_PKR_CONTROL_XFER', 'SC_PKR_DBHANG_FORCE_EOV', + 'SC_PKR_END_OF_VECTOR', 'SC_PKR_QUAD_OVERLAP_FOUND_IN_WAVE_TABLE', + 'SC_PKR_QUAD_OVERLAP_NOT_FOUND_IN_WAVE_TABLE', + 'SC_PKR_QUAD_PER_ROW_H1', 'SC_PKR_QUAD_PER_ROW_H2', + 'SC_POPS_FORCE_EOV', 'SC_POPS_INTRA_WAVE_OVERLAPS', + 'SC_PSSW_WINDOW_VALID', 'SC_PSSW_WINDOW_VALID_BUSY', + 'SC_PS_ARB_EOP_POP_SYNC_POP', 'SC_PS_ARB_EVENT_SYNC_POP', + 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', + 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', + 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', + 'SC_PS_ARB_PA_SC_BUSY', 'SC_PS_ARB_SC_BUSY', + 'SC_PS_ARB_STALLED_FROM_BELOW', 'SC_PS_ARB_STARVED_FROM_ABOVE', + 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', 'SC_PS_CTX_DONE_FIFO_POP', + 'SC_PS_CTX_DONE_FIFO_PUSH', 'SC_PS_PA0_SC_FIFO_EMPTY', + 'SC_PS_PA0_SC_FIFO_FULL', 'SC_PS_PA1_SC_FIFO_EMPTY', + 'SC_PS_PA1_SC_FIFO_FULL', 'SC_PS_PA2_SC_FIFO_EMPTY', + 'SC_PS_PA2_SC_FIFO_FULL', 'SC_PS_PA3_SC_FIFO_EMPTY', + 'SC_PS_PA3_SC_FIFO_FULL', 'SC_PS_TS_EVENT_FIFO_POP', + 'SC_PS_TS_EVENT_FIFO_PUSH', 'SC_QZ0_MULTI_GPU_TILE_DISCARD', + 'SC_QZ0_QUAD_COUNT', 'SC_QZ0_QUAD_PER_TILE_H0', + 'SC_QZ0_QUAD_PER_TILE_H1', 'SC_QZ0_QUAD_PER_TILE_H10', + 'SC_QZ0_QUAD_PER_TILE_H11', 'SC_QZ0_QUAD_PER_TILE_H12', + 'SC_QZ0_QUAD_PER_TILE_H13', 'SC_QZ0_QUAD_PER_TILE_H14', + 'SC_QZ0_QUAD_PER_TILE_H15', 'SC_QZ0_QUAD_PER_TILE_H16', + 'SC_QZ0_QUAD_PER_TILE_H2', 'SC_QZ0_QUAD_PER_TILE_H3', + 'SC_QZ0_QUAD_PER_TILE_H4', 'SC_QZ0_QUAD_PER_TILE_H5', + 'SC_QZ0_QUAD_PER_TILE_H6', 'SC_QZ0_QUAD_PER_TILE_H7', + 'SC_QZ0_QUAD_PER_TILE_H8', 'SC_QZ0_QUAD_PER_TILE_H9', + 'SC_QZ0_TILE_COUNT', 'SC_QZ0_TILE_COVERED_COUNT', + 'SC_QZ0_TILE_NOT_COVERED_COUNT', 'SC_QZ1_MULTI_GPU_TILE_DISCARD', + 'SC_QZ1_QUAD_COUNT', 'SC_QZ1_QUAD_PER_TILE_H0', + 'SC_QZ1_QUAD_PER_TILE_H1', 'SC_QZ1_QUAD_PER_TILE_H10', + 'SC_QZ1_QUAD_PER_TILE_H11', 'SC_QZ1_QUAD_PER_TILE_H12', + 'SC_QZ1_QUAD_PER_TILE_H13', 'SC_QZ1_QUAD_PER_TILE_H14', + 'SC_QZ1_QUAD_PER_TILE_H15', 'SC_QZ1_QUAD_PER_TILE_H16', + 'SC_QZ1_QUAD_PER_TILE_H2', 'SC_QZ1_QUAD_PER_TILE_H3', + 'SC_QZ1_QUAD_PER_TILE_H4', 'SC_QZ1_QUAD_PER_TILE_H5', + 'SC_QZ1_QUAD_PER_TILE_H6', 'SC_QZ1_QUAD_PER_TILE_H7', + 'SC_QZ1_QUAD_PER_TILE_H8', 'SC_QZ1_QUAD_PER_TILE_H9', + 'SC_QZ1_TILE_COUNT', 'SC_QZ1_TILE_COVERED_COUNT', + 'SC_QZ1_TILE_NOT_COVERED_COUNT', 'SC_QZ2_MULTI_GPU_TILE_DISCARD', + 'SC_QZ2_QUAD_COUNT', 'SC_QZ2_QUAD_PER_TILE_H0', + 'SC_QZ2_QUAD_PER_TILE_H1', 'SC_QZ2_QUAD_PER_TILE_H10', + 'SC_QZ2_QUAD_PER_TILE_H11', 'SC_QZ2_QUAD_PER_TILE_H12', + 'SC_QZ2_QUAD_PER_TILE_H13', 'SC_QZ2_QUAD_PER_TILE_H14', + 'SC_QZ2_QUAD_PER_TILE_H15', 'SC_QZ2_QUAD_PER_TILE_H16', + 'SC_QZ2_QUAD_PER_TILE_H2', 'SC_QZ2_QUAD_PER_TILE_H3', + 'SC_QZ2_QUAD_PER_TILE_H4', 'SC_QZ2_QUAD_PER_TILE_H5', + 'SC_QZ2_QUAD_PER_TILE_H6', 'SC_QZ2_QUAD_PER_TILE_H7', + 'SC_QZ2_QUAD_PER_TILE_H8', 'SC_QZ2_QUAD_PER_TILE_H9', + 'SC_QZ2_TILE_COUNT', 'SC_QZ2_TILE_COVERED_COUNT', + 'SC_QZ2_TILE_NOT_COVERED_COUNT', 'SC_QZ3_MULTI_GPU_TILE_DISCARD', + 'SC_QZ3_QUAD_COUNT', 'SC_QZ3_QUAD_PER_TILE_H0', + 'SC_QZ3_QUAD_PER_TILE_H1', 'SC_QZ3_QUAD_PER_TILE_H10', + 'SC_QZ3_QUAD_PER_TILE_H11', 'SC_QZ3_QUAD_PER_TILE_H12', + 'SC_QZ3_QUAD_PER_TILE_H13', 'SC_QZ3_QUAD_PER_TILE_H14', + 'SC_QZ3_QUAD_PER_TILE_H15', 'SC_QZ3_QUAD_PER_TILE_H16', + 'SC_QZ3_QUAD_PER_TILE_H2', 'SC_QZ3_QUAD_PER_TILE_H3', + 'SC_QZ3_QUAD_PER_TILE_H4', 'SC_QZ3_QUAD_PER_TILE_H5', + 'SC_QZ3_QUAD_PER_TILE_H6', 'SC_QZ3_QUAD_PER_TILE_H7', + 'SC_QZ3_QUAD_PER_TILE_H8', 'SC_QZ3_QUAD_PER_TILE_H9', + 'SC_QZ3_TILE_COUNT', 'SC_QZ3_TILE_COVERED_COUNT', + 'SC_QZ3_TILE_NOT_COVERED_COUNT', 'SC_QZQP_WINDOW_VALID', + 'SC_QZQP_WINDOW_VALID_BUSY', 'SC_REG_SCLK_BUSY', 'SC_SCB_BUSY', + 'SC_SCF_SCB_INTERFACE_BUSY', 'SC_SCISSOR_DISCARD', + 'SC_SC_PS_ENG_MULTICYCLE_BUBBLE', 'SC_SC_SPI_DEALLOC_0_0', + 'SC_SC_SPI_DEALLOC_0_1', 'SC_SC_SPI_DEALLOC_0_2', + 'SC_SC_SPI_DEALLOC_1_0', 'SC_SC_SPI_DEALLOC_1_1', + 'SC_SC_SPI_DEALLOC_1_2', 'SC_SC_SPI_DEALLOC_2_0', + 'SC_SC_SPI_DEALLOC_2_1', 'SC_SC_SPI_DEALLOC_2_2', + 'SC_SC_SPI_DEALLOC_3_0', 'SC_SC_SPI_DEALLOC_3_1', + 'SC_SC_SPI_DEALLOC_3_2', 'SC_SC_SPI_EVENT', 'SC_SC_SPI_FPOV_0', + 'SC_SC_SPI_FPOV_1', 'SC_SC_SPI_FPOV_2', 'SC_SC_SPI_FPOV_3', + 'SC_SEND_DB_VPZ', 'SC_SRPS_WINDOW_VALID', + 'SC_SRPS_WINDOW_VALID_BUSY', 'SC_STALLED_BY_BCI', + 'SC_STALLED_BY_DB_QUAD', 'SC_STALLED_BY_DB_TILE', + 'SC_STALLED_BY_PRIMFIFO', 'SC_STALLED_BY_QUADFIFO', + 'SC_STALLED_BY_SPI', 'SC_STALLED_BY_TILEFIFO', + 'SC_STALLED_BY_TILEORDERFIFO', 'SC_STARVED_BY_DB_QUAD', + 'SC_STARVED_BY_DB_TILE', 'SC_STARVED_BY_PA', + 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', + 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', + 'SC_SUPERTILE_COUNT', 'SC_SUPERTILE_PER_PRIM_H0', + 'SC_SUPERTILE_PER_PRIM_H1', 'SC_SUPERTILE_PER_PRIM_H10', + 'SC_SUPERTILE_PER_PRIM_H11', 'SC_SUPERTILE_PER_PRIM_H12', + 'SC_SUPERTILE_PER_PRIM_H13', 'SC_SUPERTILE_PER_PRIM_H14', + 'SC_SUPERTILE_PER_PRIM_H15', 'SC_SUPERTILE_PER_PRIM_H16', + 'SC_SUPERTILE_PER_PRIM_H2', 'SC_SUPERTILE_PER_PRIM_H3', + 'SC_SUPERTILE_PER_PRIM_H4', 'SC_SUPERTILE_PER_PRIM_H5', + 'SC_SUPERTILE_PER_PRIM_H6', 'SC_SUPERTILE_PER_PRIM_H7', + 'SC_SUPERTILE_PER_PRIM_H8', 'SC_SUPERTILE_PER_PRIM_H9', + 'SC_TILE_PER_PRIM_H0', 'SC_TILE_PER_PRIM_H1', + 'SC_TILE_PER_PRIM_H10', 'SC_TILE_PER_PRIM_H11', + 'SC_TILE_PER_PRIM_H12', 'SC_TILE_PER_PRIM_H13', + 'SC_TILE_PER_PRIM_H14', 'SC_TILE_PER_PRIM_H15', + 'SC_TILE_PER_PRIM_H16', 'SC_TILE_PER_PRIM_H2', + 'SC_TILE_PER_PRIM_H3', 'SC_TILE_PER_PRIM_H4', + 'SC_TILE_PER_PRIM_H5', 'SC_TILE_PER_PRIM_H6', + 'SC_TILE_PER_PRIM_H7', 'SC_TILE_PER_PRIM_H8', + 'SC_TILE_PER_PRIM_H9', 'SC_TILE_PER_SUPERTILE_H0', + 'SC_TILE_PER_SUPERTILE_H1', 'SC_TILE_PER_SUPERTILE_H10', + 'SC_TILE_PER_SUPERTILE_H11', 'SC_TILE_PER_SUPERTILE_H12', + 'SC_TILE_PER_SUPERTILE_H13', 'SC_TILE_PER_SUPERTILE_H14', + 'SC_TILE_PER_SUPERTILE_H15', 'SC_TILE_PER_SUPERTILE_H16', + 'SC_TILE_PER_SUPERTILE_H2', 'SC_TILE_PER_SUPERTILE_H3', + 'SC_TILE_PER_SUPERTILE_H4', 'SC_TILE_PER_SUPERTILE_H5', + 'SC_TILE_PER_SUPERTILE_H6', 'SC_TILE_PER_SUPERTILE_H7', + 'SC_TILE_PER_SUPERTILE_H8', 'SC_TILE_PER_SUPERTILE_H9', + 'SC_TILE_PICKED_H1', 'SC_TILE_PICKED_H2', 'SC_TILE_PICKED_H3', + 'SC_TILE_PICKED_H4', 'SC_TPQZ_WINDOW_VALID', + 'SC_TPQZ_WINDOW_VALID_BUSY', 'SC_TRPK_WINDOW_VALID', + 'SC_TRPK_WINDOW_VALID_BUSY', 'SDMA_PERF_SEL', + 'SDMA_PERF_SEL_ATCL2_FREE', 'SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', + 'SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', + 'SDMA_PERF_SEL_ATCL2_RET_ACK', 'SDMA_PERF_SEL_ATCL2_RET_XNACK', + 'SDMA_PERF_SEL_CE_AFIFO_FULL', 'SDMA_PERF_SEL_CE_DST_IDLE', + 'SDMA_PERF_SEL_CE_INFO1_FULL', 'SDMA_PERF_SEL_CE_INFO_FULL', + 'SDMA_PERF_SEL_CE_IN_IDLE', 'SDMA_PERF_SEL_CE_L1_STALL', + 'SDMA_PERF_SEL_CE_L1_WR_VLD', 'SDMA_PERF_SEL_CE_OUT_IDLE', + 'SDMA_PERF_SEL_CE_RD_STALL', 'SDMA_PERF_SEL_CE_RREQ_IDLE', + 'SDMA_PERF_SEL_CE_SPLIT_IDLE', 'SDMA_PERF_SEL_CE_WREQ_IDLE', + 'SDMA_PERF_SEL_CE_WR_IDLE', 'SDMA_PERF_SEL_CE_WR_STALL', + 'SDMA_PERF_SEL_CTX_CHANGE', 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERF_SEL_CYCLE', + 'SDMA_PERF_SEL_DMA_L1_RD_SEND', 'SDMA_PERF_SEL_DMA_L1_WR_SEND', + 'SDMA_PERF_SEL_DMA_MC_RD_SEND', 'SDMA_PERF_SEL_DMA_MC_WR_SEND', + 'SDMA_PERF_SEL_DOORBELL', 'SDMA_PERF_SEL_EX_IDLE', + 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 'SDMA_PERF_SEL_F32_L1_WR_VLD', 'SDMA_PERF_SEL_GFX_SELECT', + 'SDMA_PERF_SEL_IB_CMD_FULL', 'SDMA_PERF_SEL_IB_CMD_IDLE', + 'SDMA_PERF_SEL_IDLE', 'SDMA_PERF_SEL_INT_IDLE', + 'SDMA_PERF_SEL_INT_REQ_COUNT', 'SDMA_PERF_SEL_INT_REQ_STALL', + 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', 'SDMA_PERF_SEL_INT_RESP_RETRY', + 'SDMA_PERF_SEL_IS_INVREQ_ADDR_RD', + 'SDMA_PERF_SEL_IS_INVREQ_ADDR_WR', 'SDMA_PERF_SEL_L1_INV_MIDDLE', + 'SDMA_PERF_SEL_L1_RDL2_IDLE', 'SDMA_PERF_SEL_L1_RDMC_IDLE', + 'SDMA_PERF_SEL_L1_RD_FIFO_IDLE', 'SDMA_PERF_SEL_L1_RD_INV_EN', + 'SDMA_PERF_SEL_L1_RD_INV_IDLE', 'SDMA_PERF_SEL_L1_RD_WAIT_INVADR', + 'SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', 'SDMA_PERF_SEL_L1_WRL2_IDLE', + 'SDMA_PERF_SEL_L1_WRMC_IDLE', 'SDMA_PERF_SEL_L1_WR_FIFO_IDLE', + 'SDMA_PERF_SEL_L1_WR_INV_EN', 'SDMA_PERF_SEL_L1_WR_INV_IDLE', + 'SDMA_PERF_SEL_L1_WR_WAIT_INVADR', + 'SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', 'SDMA_PERF_SEL_MC_RD_COUNT', + 'SDMA_PERF_SEL_MC_RD_IDLE', 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 'SDMA_PERF_SEL_MC_RD_RET_STALL', 'SDMA_PERF_SEL_MC_WR_COUNT', + 'SDMA_PERF_SEL_MC_WR_IDLE', + 'SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER', + 'SDMA_PERF_SEL_NUM_PACKET', 'SDMA_PERF_SEL_PAGE_SELECT', + 'SDMA_PERF_SEL_RB_CMD_FULL', 'SDMA_PERF_SEL_RB_CMD_IDLE', + 'SDMA_PERF_SEL_RB_EMPTY', 'SDMA_PERF_SEL_RB_FULL', + 'SDMA_PERF_SEL_RB_RPTR_WB', 'SDMA_PERF_SEL_RB_RPTR_WRAP', + 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', 'SDMA_PERF_SEL_RB_WPTR_WRAP', + 'SDMA_PERF_SEL_RD_BA_RTR', 'SDMA_PERF_SEL_REG_IDLE', + 'SDMA_PERF_SEL_RLC0_SELECT', 'SDMA_PERF_SEL_RLC1_SELECT', + 'SDMA_PERF_SEL_SDMA_ATCL2_SEND', + 'SDMA_PERF_SEL_SDMA_INVACK_FLUSH', + 'SDMA_PERF_SEL_SDMA_INVACK_NFLUSH', 'SDMA_PERF_SEL_SEM_IDLE', + 'SDMA_PERF_SEL_SEM_REQ_COUNT', 'SDMA_PERF_SEL_SEM_REQ_STALL', + 'SDMA_PERF_SEL_SEM_RESP_FAIL', + 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 'SDMA_PERF_SEL_SEM_RESP_PASS', 'SDMA_PERF_SEL_SRBM_REG_SEND', + 'SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER', + 'SDMA_PERF_SEL_WR_BA_RTR', 'SEC_GSP0_PRIORITY_HIGH', + 'SEC_GSP0_PRIORITY_LOW', 'SEM_ECC_ERROR', 'SEM_FAILED', + 'SEM_PASSED', 'SEM_PERF_SEL', 'SEM_PERF_SEL_ACP_REQ_SIGNAL', + 'SEM_PERF_SEL_ACP_REQ_WAIT', 'SEM_PERF_SEL_ATC_INVALIDATION', + 'SEM_PERF_SEL_ATC_REQ', 'SEM_PERF_SEL_ATC_RET', + 'SEM_PERF_SEL_ATC_XNACK', 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', + 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', + 'SEM_PERF_SEL_CYCLE', 'SEM_PERF_SEL_IDLE', + 'SEM_PERF_SEL_ISP_REQ_SIGNAL', 'SEM_PERF_SEL_ISP_REQ_WAIT', + 'SEM_PERF_SEL_MC_RD_REQ', 'SEM_PERF_SEL_MC_RD_RET', + 'SEM_PERF_SEL_MC_WR_REQ', 'SEM_PERF_SEL_MC_WR_RET', + 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA0_REQ_WAIT', + 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA1_REQ_WAIT', + 'SEM_PERF_SEL_UVD_REQ_SIGNAL', 'SEM_PERF_SEL_UVD_REQ_WAIT', + 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', 'SEM_PERF_SEL_VCE0_REQ_WAIT', + 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', 'SEM_PERF_SEL_VCE1_REQ_WAIT', + 'SEM_PERF_SEL_VP8_REQ_SIGNAL', 'SEM_PERF_SEL_VP8_REQ_WAIT', + 'SEM_TRANS_ERROR', 'SET_OVERRIDE_CGTT_DCEFCLK', + 'SET_OVERRIDE_CGTT_SCLK', 'SET_STATIC_SCREEN_SMU_INTR', + 'SH_MEM_ADDRESS_MODE', 'SH_MEM_ADDRESS_MODE_32', + 'SH_MEM_ADDRESS_MODE_64', 'SH_MEM_ALIGNMENT_MODE', + 'SH_MEM_ALIGNMENT_MODE_DWORD', + 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', + 'SH_MEM_ALIGNMENT_MODE_STRICT', 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', + 'SIMM16_WAITCNT_EXP_CNT_SIZE', 'SIMM16_WAITCNT_EXP_CNT_START', + 'SIMM16_WAITCNT_LGKM_CNT_SIZE', 'SIMM16_WAITCNT_LGKM_CNT_START', + 'SIMM16_WAITCNT_VM_CNT_HI_SIZE', 'SIMM16_WAITCNT_VM_CNT_HI_START', + 'SIMM16_WAITCNT_VM_CNT_SIZE', 'SIMM16_WAITCNT_VM_CNT_START', + 'SMU_INTR_STATUS_CLEAR', 'SMU_INTR_STATUS_NOOP', + 'SM_MODE_RESERVED', 'SO_VGTSTREAMOUT_FLUSH', 'SPDIF1_SOFT_RESET', + 'SPDIF1_SOFT_RESET_0', 'SPDIF1_SOFT_RESET_1', + 'SPDIF_INVERT_DISABLE', 'SPDIF_INVERT_EN', 'SPDIF_INVERT_ENABLE', + 'SPI_FOG_EXP', 'SPI_FOG_EXP2', 'SPI_FOG_LINEAR', 'SPI_FOG_MODE', + 'SPI_FOG_NONE', 'SPI_PERFCNT_SEL', + 'SPI_PERF_CLKGATE_ACTIVE_STALL', 'SPI_PERF_CLKGATE_ALL_CLOCKS_ON', + 'SPI_PERF_CLKGATE_BUSY_STALL', 'SPI_PERF_CLKGATE_CGTT_DYN_ON', + 'SPI_PERF_CLKGATE_CGTT_REG_ON', 'SPI_PERF_CSG_BUSY', + 'SPI_PERF_CSG_CRAWLER_STALL', 'SPI_PERF_CSG_EVENT_WAVE', + 'SPI_PERF_CSG_NUM_THREADGROUPS', 'SPI_PERF_CSG_WAVE', + 'SPI_PERF_CSG_WINDOW_VALID', 'SPI_PERF_CSN_BUSY', + 'SPI_PERF_CSN_CRAWLER_STALL', 'SPI_PERF_CSN_EVENT_WAVE', + 'SPI_PERF_CSN_NUM_THREADGROUPS', 'SPI_PERF_CSN_WAVE', + 'SPI_PERF_CSN_WINDOW_VALID', 'SPI_PERF_ES_BUSY', + 'SPI_PERF_ES_CRAWLER_STALL', 'SPI_PERF_ES_EVENT_WAVE', + 'SPI_PERF_ES_FIRST_SUBGRP', 'SPI_PERF_ES_FIRST_WAVE', + 'SPI_PERF_ES_GRP_FIFO_FULL', 'SPI_PERF_ES_LAST_SUBGRP', + 'SPI_PERF_ES_LAST_WAVE', 'SPI_PERF_ES_LSHS_DEALLOC', + 'SPI_PERF_ES_PERS_UPD_FULL0', 'SPI_PERF_ES_PERS_UPD_FULL1', + 'SPI_PERF_ES_WAVE', 'SPI_PERF_ES_WINDOW_VALID', + 'SPI_PERF_EXP_ARB_COL_CNT', 'SPI_PERF_EXP_ARB_GDS_CNT', + 'SPI_PERF_EXP_ARB_PAR_CNT', 'SPI_PERF_EXP_ARB_POS_CNT', + 'SPI_PERF_GS_BUSY', 'SPI_PERF_GS_CRAWLER_STALL', + 'SPI_PERF_GS_EVENT_WAVE', 'SPI_PERF_GS_FIRST_SUBGRP', + 'SPI_PERF_GS_GRP_FIFO_FULL', 'SPI_PERF_GS_LAST_SUBGRP', + 'SPI_PERF_GS_PERS_UPD_FULL0', 'SPI_PERF_GS_PERS_UPD_FULL1', + 'SPI_PERF_GS_WAVE', 'SPI_PERF_GS_WINDOW_VALID', + 'SPI_PERF_HS_BUSY', 'SPI_PERF_HS_CRAWLER_STALL', + 'SPI_PERF_HS_EVENT_WAVE', 'SPI_PERF_HS_FIRST_WAVE', + 'SPI_PERF_HS_GRP_FIFO_FULL', 'SPI_PERF_HS_LAST_WAVE', + 'SPI_PERF_HS_LSHS_DEALLOC', 'SPI_PERF_HS_PERS_UPD_FULL0', + 'SPI_PERF_HS_PERS_UPD_FULL1', 'SPI_PERF_HS_WAVE', + 'SPI_PERF_HS_WINDOW_VALID', 'SPI_PERF_LDS0_PC_VALID', + 'SPI_PERF_LDS1_PC_VALID', 'SPI_PERF_LS_BUSY', + 'SPI_PERF_LS_CRAWLER_STALL', 'SPI_PERF_LS_EVENT_WAVE', + 'SPI_PERF_LS_FIRST_WAVE', 'SPI_PERF_LS_GRP_FIFO_FULL', + 'SPI_PERF_LS_LAST_WAVE', 'SPI_PERF_LS_PERS_UPD_FULL0', + 'SPI_PERF_LS_PERS_UPD_FULL1', 'SPI_PERF_LS_WAVE', + 'SPI_PERF_LS_WINDOW_VALID', 'SPI_PERF_NUM_PS_COL_EXPORTS', + 'SPI_PERF_NUM_VS_PARAM_EXPORTS', 'SPI_PERF_NUM_VS_POS_EXPORTS', + 'SPI_PERF_OFFCHIP_LDS_STALL_LS', 'SPI_PERF_PC_ALLOC_ACCUM', + 'SPI_PERF_PC_ALLOC_CNT', 'SPI_PERF_PIX_ALLOC_DB0_STALL', + 'SPI_PERF_PIX_ALLOC_DB1_STALL', 'SPI_PERF_PIX_ALLOC_DB2_STALL', + 'SPI_PERF_PIX_ALLOC_DB3_STALL', 'SPI_PERF_PIX_ALLOC_PEND_CNT', + 'SPI_PERF_PIX_ALLOC_SCB_STALL', 'SPI_PERF_PS_CTL_ACTIVE', + 'SPI_PERF_PS_CTL_BUSY', 'SPI_PERF_PS_CTL_CNF_BIN2', + 'SPI_PERF_PS_CTL_CNF_BIN3', 'SPI_PERF_PS_CTL_CRAWLER_STALL', + 'SPI_PERF_PS_CTL_DEALLOC_BIN0', 'SPI_PERF_PS_CTL_EVENT_WAVE', + 'SPI_PERF_PS_CTL_FPOS_BIN1_STALL', 'SPI_PERF_PS_CTL_FPOS_BIN2', + 'SPI_PERF_PS_CTL_LDS_RES_FULL', 'SPI_PERF_PS_CTL_OPT_WAVE', + 'SPI_PERF_PS_CTL_PASS_BIN0', 'SPI_PERF_PS_CTL_PASS_BIN1', + 'SPI_PERF_PS_CTL_PRIM_BIN0', 'SPI_PERF_PS_CTL_PRIM_BIN1', + 'SPI_PERF_PS_CTL_WAVE', 'SPI_PERF_PS_CTL_WINDOW_VALID', + 'SPI_PERF_PS_PERS_UPD_FULL0', 'SPI_PERF_PS_PERS_UPD_FULL1', + 'SPI_PERF_RA_BAR_CU_FULL_CSG', 'SPI_PERF_RA_BAR_CU_FULL_CSN', + 'SPI_PERF_RA_BAR_CU_FULL_HS', 'SPI_PERF_RA_BULKY_CU_FULL_CSG', + 'SPI_PERF_RA_BULKY_CU_FULL_CSN', 'SPI_PERF_RA_CSG_LOCK', + 'SPI_PERF_RA_CSN_LOCK', 'SPI_PERF_RA_ES_LOCK', + 'SPI_PERF_RA_GS_LOCK', 'SPI_PERF_RA_HS_LOCK', + 'SPI_PERF_RA_LDS_CU_FULL_CSG', 'SPI_PERF_RA_LDS_CU_FULL_CSN', + 'SPI_PERF_RA_LDS_CU_FULL_ES', 'SPI_PERF_RA_LDS_CU_FULL_LS', + 'SPI_PERF_RA_LDS_CU_FULL_PS', 'SPI_PERF_RA_LS_LOCK', + 'SPI_PERF_RA_PIPE_REQ_BIN2', 'SPI_PERF_RA_PS_LOCK_NA', + 'SPI_PERF_RA_REQ_NO_ALLOC', 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', + 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', 'SPI_PERF_RA_REQ_NO_ALLOC_ES', + 'SPI_PERF_RA_REQ_NO_ALLOC_GS', 'SPI_PERF_RA_REQ_NO_ALLOC_HS', + 'SPI_PERF_RA_REQ_NO_ALLOC_LS', 'SPI_PERF_RA_REQ_NO_ALLOC_PS', + 'SPI_PERF_RA_REQ_NO_ALLOC_VS', 'SPI_PERF_RA_RES_STALL_CSG', + 'SPI_PERF_RA_RES_STALL_CSN', 'SPI_PERF_RA_RES_STALL_ES', + 'SPI_PERF_RA_RES_STALL_GS', 'SPI_PERF_RA_RES_STALL_HS', + 'SPI_PERF_RA_RES_STALL_LS', 'SPI_PERF_RA_RES_STALL_PS', + 'SPI_PERF_RA_RES_STALL_VS', 'SPI_PERF_RA_RSV_UPD', + 'SPI_PERF_RA_SGPR_SIMD_FULL_CSG', + 'SPI_PERF_RA_SGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_SGPR_SIMD_FULL_ES', + 'SPI_PERF_RA_SGPR_SIMD_FULL_GS', 'SPI_PERF_RA_SGPR_SIMD_FULL_HS', + 'SPI_PERF_RA_SGPR_SIMD_FULL_LS', 'SPI_PERF_RA_SGPR_SIMD_FULL_PS', + 'SPI_PERF_RA_SGPR_SIMD_FULL_VS', 'SPI_PERF_RA_TASK_REQ_BIN3', + 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', + 'SPI_PERF_RA_TMP_STALL_CSG', 'SPI_PERF_RA_TMP_STALL_CSN', + 'SPI_PERF_RA_TMP_STALL_ES', 'SPI_PERF_RA_TMP_STALL_GS', + 'SPI_PERF_RA_TMP_STALL_HS', 'SPI_PERF_RA_TMP_STALL_LS', + 'SPI_PERF_RA_TMP_STALL_PS', 'SPI_PERF_RA_TMP_STALL_VS', + 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', + 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_VGPR_SIMD_FULL_ES', + 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', + 'SPI_PERF_RA_VGPR_SIMD_FULL_LS', 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', + 'SPI_PERF_RA_VGPR_SIMD_FULL_VS', 'SPI_PERF_RA_VS_LOCK', + 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', + 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', 'SPI_PERF_RA_WAVE_SIMD_FULL_ES', + 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', + 'SPI_PERF_RA_WAVE_SIMD_FULL_LS', 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', + 'SPI_PERF_RA_WAVE_SIMD_FULL_VS', 'SPI_PERF_RA_WR_CTL_FULL', + 'SPI_PERF_RA_WVLIM_STALL_CSG', 'SPI_PERF_RA_WVLIM_STALL_CSN', + 'SPI_PERF_RA_WVLIM_STALL_ES', 'SPI_PERF_RA_WVLIM_STALL_GS', + 'SPI_PERF_RA_WVLIM_STALL_HS', 'SPI_PERF_RA_WVLIM_STALL_LS', + 'SPI_PERF_RA_WVLIM_STALL_PS', 'SPI_PERF_RA_WVLIM_STALL_VS', + 'SPI_PERF_VS_ALLOC_CNT', 'SPI_PERF_VS_BUSY', + 'SPI_PERF_VS_CRAWLER_STALL', 'SPI_PERF_VS_EVENT_WAVE', + 'SPI_PERF_VS_FIRST_SUBGRP', 'SPI_PERF_VS_FIRST_WAVE', + 'SPI_PERF_VS_LAST_SUBGRP', 'SPI_PERF_VS_LAST_WAVE', + 'SPI_PERF_VS_LATE_ALLOC_ACCUM', 'SPI_PERF_VS_LATE_ALLOC_FULL', + 'SPI_PERF_VS_LSHS_DEALLOC', 'SPI_PERF_VS_PC_STALL', + 'SPI_PERF_VS_PERS_UPD_FULL0', 'SPI_PERF_VS_PERS_UPD_FULL1', + 'SPI_PERF_VS_POS0_STALL', 'SPI_PERF_VS_POS1_STALL', + 'SPI_PERF_VS_WAVE', 'SPI_PERF_VS_WINDOW_VALID', + 'SPI_PNT_SPRITE_OVERRIDE', 'SPI_PNT_SPRITE_SEL_0', + 'SPI_PNT_SPRITE_SEL_1', 'SPI_PNT_SPRITE_SEL_NONE', + 'SPI_PNT_SPRITE_SEL_S', 'SPI_PNT_SPRITE_SEL_T', 'SPI_SAMPLE_CNTL', + 'SPI_SHADER_1COMP', 'SPI_SHADER_2COMP', 'SPI_SHADER_32_ABGR', + 'SPI_SHADER_32_AR', 'SPI_SHADER_32_GR', 'SPI_SHADER_32_R', + 'SPI_SHADER_4COMP', 'SPI_SHADER_4COMPRESS', + 'SPI_SHADER_EX_FORMAT', 'SPI_SHADER_FORMAT', + 'SPI_SHADER_FP16_ABGR', 'SPI_SHADER_NONE', + 'SPI_SHADER_SINT16_ABGR', 'SPI_SHADER_SNORM16_ABGR', + 'SPI_SHADER_UINT16_ABGR', 'SPI_SHADER_UNORM16_ABGR', + 'SPI_SHADER_ZERO', 'SPM_PERFMON_STATE', 'SPRITE_EN', + 'SQC_PERF_SEL_DCACHE_ATOMIC', 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', + 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED', + 'SQC_PERF_SEL_DCACHE_FLAT_REQ', + 'SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT', + 'SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL', + 'SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL', + 'SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS', + 'SQC_PERF_SEL_DCACHE_GATCL1_REQUEST', + 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS', + 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX', + 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES', + 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT', + 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL', + 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS', + 'SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS', + 'SQC_PERF_SEL_DCACHE_HITS', 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', + 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', + 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', + 'SQC_PERF_SEL_DCACHE_INPUT_VALIDB', + 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READY', + 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', + 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', + 'SQC_PERF_SEL_DCACHE_INVAL_INST', + 'SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC', + 'SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST', + 'SQC_PERF_SEL_DCACHE_MISSES', + 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', + 'SQC_PERF_SEL_DCACHE_MISS_EVICT_READ', + 'SQC_PERF_SEL_DCACHE_NONFLAT_REQ', 'SQC_PERF_SEL_DCACHE_REQ', + 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', + 'SQC_PERF_SEL_DCACHE_REQ_READ_1', + 'SQC_PERF_SEL_DCACHE_REQ_READ_16', + 'SQC_PERF_SEL_DCACHE_REQ_READ_2', + 'SQC_PERF_SEL_DCACHE_REQ_READ_4', + 'SQC_PERF_SEL_DCACHE_REQ_READ_8', 'SQC_PERF_SEL_DCACHE_REQ_TIME', + 'SQC_PERF_SEL_DCACHE_REQ_WRITE_1', + 'SQC_PERF_SEL_DCACHE_REQ_WRITE_2', + 'SQC_PERF_SEL_DCACHE_REQ_WRITE_4', + 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_DCACHE_VOLATILE', 'SQC_PERF_SEL_DCACHE_WB_ASYNC', + 'SQC_PERF_SEL_DCACHE_WB_INST', + 'SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC', + 'SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST', + 'SQC_PERF_SEL_DCACHE_WC_LRU_WRITE', + 'SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE', 'SQC_PERF_SEL_DUMMY_LAST', + 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', + 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF', + 'SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT', + 'SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL', + 'SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS', + 'SQC_PERF_SEL_ICACHE_GATCL1_REQUEST', + 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS', + 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX', + 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES', + 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT', + 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL', + 'SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS', + 'SQC_PERF_SEL_ICACHE_HITS', 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', + 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', + 'SQC_PERF_SEL_ICACHE_INPUT_VALIDB', + 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READY', + 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', + 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', + 'SQC_PERF_SEL_ICACHE_INVAL_INST', 'SQC_PERF_SEL_ICACHE_MISSES', + 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', + 'SQC_PERF_SEL_ICACHE_PREFETCH_1', + 'SQC_PERF_SEL_ICACHE_PREFETCH_2', + 'SQC_PERF_SEL_ICACHE_PREFETCH_FILTERED', + 'SQC_PERF_SEL_ICACHE_REQ', + 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_SQ_DCACHE_REQS', 'SQC_PERF_SEL_TC_DATA_ATOMIC_REQ', + 'SQC_PERF_SEL_TC_DATA_READ_REQ', 'SQC_PERF_SEL_TC_DATA_WRITE_REQ', + 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', 'SQC_PERF_SEL_TC_INST_REQ', + 'SQC_PERF_SEL_TC_REQ', 'SQC_PERF_SEL_TC_STALL', + 'SQC_PERF_SEL_TC_STARVE', 'SQDEC_BEGIN', 'SQDEC_END', + 'SQGFXUDEC_BEGIN', 'SQGFXUDEC_END', 'SQIND_GLOBAL_REGS_OFFSET', + 'SQIND_GLOBAL_REGS_SIZE', 'SQIND_LOCAL_REGS_OFFSET', + 'SQIND_LOCAL_REGS_SIZE', 'SQIND_WAVE_HWREGS_OFFSET', + 'SQIND_WAVE_HWREGS_SIZE', 'SQIND_WAVE_SGPRS_OFFSET', + 'SQIND_WAVE_SGPRS_SIZE', 'SQIND_WAVE_VGPRS_OFFSET', + 'SQIND_WAVE_VGPRS_SIZE', 'SQPERFDDEC_BEGIN', 'SQPERFDDEC_END', + 'SQPERFSDEC_BEGIN', 'SQPERFSDEC_END', 'SQPWRDEC_BEGIN', + 'SQPWRDEC_END', 'SQ_ATTR0', 'SQ_BUFFER_ATOMIC_ADD', + 'SQ_BUFFER_ATOMIC_ADD_X2', 'SQ_BUFFER_ATOMIC_AND', + 'SQ_BUFFER_ATOMIC_AND_X2', 'SQ_BUFFER_ATOMIC_CMPSWAP', + 'SQ_BUFFER_ATOMIC_CMPSWAP_X2', 'SQ_BUFFER_ATOMIC_DEC', + 'SQ_BUFFER_ATOMIC_DEC_X2', 'SQ_BUFFER_ATOMIC_INC', + 'SQ_BUFFER_ATOMIC_INC_X2', 'SQ_BUFFER_ATOMIC_OR', + 'SQ_BUFFER_ATOMIC_OR_X2', 'SQ_BUFFER_ATOMIC_SMAX', + 'SQ_BUFFER_ATOMIC_SMAX_X2', 'SQ_BUFFER_ATOMIC_SMIN', + 'SQ_BUFFER_ATOMIC_SMIN_X2', 'SQ_BUFFER_ATOMIC_SUB', + 'SQ_BUFFER_ATOMIC_SUB_X2', 'SQ_BUFFER_ATOMIC_SWAP', + 'SQ_BUFFER_ATOMIC_SWAP_X2', 'SQ_BUFFER_ATOMIC_UMAX', + 'SQ_BUFFER_ATOMIC_UMAX_X2', 'SQ_BUFFER_ATOMIC_UMIN', + 'SQ_BUFFER_ATOMIC_UMIN_X2', 'SQ_BUFFER_ATOMIC_XOR', + 'SQ_BUFFER_ATOMIC_XOR_X2', 'SQ_BUFFER_LOAD_DWORD', + 'SQ_BUFFER_LOAD_DWORDX2', 'SQ_BUFFER_LOAD_DWORDX3', + 'SQ_BUFFER_LOAD_DWORDX4', 'SQ_BUFFER_LOAD_FORMAT_D16_X', + 'SQ_BUFFER_LOAD_FORMAT_D16_XY', 'SQ_BUFFER_LOAD_FORMAT_D16_XYZ', + 'SQ_BUFFER_LOAD_FORMAT_D16_XYZW', 'SQ_BUFFER_LOAD_FORMAT_X', + 'SQ_BUFFER_LOAD_FORMAT_XY', 'SQ_BUFFER_LOAD_FORMAT_XYZ', + 'SQ_BUFFER_LOAD_FORMAT_XYZW', 'SQ_BUFFER_LOAD_SBYTE', + 'SQ_BUFFER_LOAD_SSHORT', 'SQ_BUFFER_LOAD_UBYTE', + 'SQ_BUFFER_LOAD_USHORT', 'SQ_BUFFER_STORE_BYTE', + 'SQ_BUFFER_STORE_DWORD', 'SQ_BUFFER_STORE_DWORDX2', + 'SQ_BUFFER_STORE_DWORDX3', 'SQ_BUFFER_STORE_DWORDX4', + 'SQ_BUFFER_STORE_FORMAT_D16_X', 'SQ_BUFFER_STORE_FORMAT_D16_XY', + 'SQ_BUFFER_STORE_FORMAT_D16_XYZ', + 'SQ_BUFFER_STORE_FORMAT_D16_XYZW', 'SQ_BUFFER_STORE_FORMAT_X', + 'SQ_BUFFER_STORE_FORMAT_XY', 'SQ_BUFFER_STORE_FORMAT_XYZ', + 'SQ_BUFFER_STORE_FORMAT_XYZW', 'SQ_BUFFER_STORE_LDS_DWORD', + 'SQ_BUFFER_STORE_SHORT', 'SQ_BUFFER_WBINVL1', + 'SQ_BUFFER_WBINVL1_VOL', 'SQ_CAC_POWER_ALU_BUSY', + 'SQ_CAC_POWER_GPR_RD', 'SQ_CAC_POWER_GPR_WR', + 'SQ_CAC_POWER_LDS_BUSY', 'SQ_CAC_POWER_SEL', + 'SQ_CAC_POWER_TEX_BUSY', 'SQ_CAC_POWER_VALU', + 'SQ_CAC_POWER_VALU0', 'SQ_CAC_POWER_VALU1', 'SQ_CAC_POWER_VALU2', + 'SQ_CHAN_W', 'SQ_CHAN_X', 'SQ_CHAN_Y', 'SQ_CHAN_Z', 'SQ_CNT1', + 'SQ_CNT2', 'SQ_CNT3', 'SQ_CNT4', 'SQ_DISPATCHER_GFX_CNT_PER_RING', + 'SQ_DISPATCHER_GFX_MIN', 'SQ_DPP_BOUND_OFF', 'SQ_DPP_BOUND_ZERO', + 'SQ_DPP_QUAD_PERM', 'SQ_DPP_ROW_BCAST15', 'SQ_DPP_ROW_BCAST31', + 'SQ_DPP_ROW_HALF_MIRROR', 'SQ_DPP_ROW_MIRROR', 'SQ_DPP_ROW_RR1', + 'SQ_DPP_ROW_RR10', 'SQ_DPP_ROW_RR11', 'SQ_DPP_ROW_RR12', + 'SQ_DPP_ROW_RR13', 'SQ_DPP_ROW_RR14', 'SQ_DPP_ROW_RR15', + 'SQ_DPP_ROW_RR2', 'SQ_DPP_ROW_RR3', 'SQ_DPP_ROW_RR4', + 'SQ_DPP_ROW_RR5', 'SQ_DPP_ROW_RR6', 'SQ_DPP_ROW_RR7', + 'SQ_DPP_ROW_RR8', 'SQ_DPP_ROW_RR9', 'SQ_DPP_ROW_SL1', + 'SQ_DPP_ROW_SL10', 'SQ_DPP_ROW_SL11', 'SQ_DPP_ROW_SL12', + 'SQ_DPP_ROW_SL13', 'SQ_DPP_ROW_SL14', 'SQ_DPP_ROW_SL15', + 'SQ_DPP_ROW_SL2', 'SQ_DPP_ROW_SL3', 'SQ_DPP_ROW_SL4', + 'SQ_DPP_ROW_SL5', 'SQ_DPP_ROW_SL6', 'SQ_DPP_ROW_SL7', + 'SQ_DPP_ROW_SL8', 'SQ_DPP_ROW_SL9', 'SQ_DPP_ROW_SR1', + 'SQ_DPP_ROW_SR10', 'SQ_DPP_ROW_SR11', 'SQ_DPP_ROW_SR12', + 'SQ_DPP_ROW_SR13', 'SQ_DPP_ROW_SR14', 'SQ_DPP_ROW_SR15', + 'SQ_DPP_ROW_SR2', 'SQ_DPP_ROW_SR3', 'SQ_DPP_ROW_SR4', + 'SQ_DPP_ROW_SR5', 'SQ_DPP_ROW_SR6', 'SQ_DPP_ROW_SR7', + 'SQ_DPP_ROW_SR8', 'SQ_DPP_ROW_SR9', 'SQ_DPP_WF_RL1', + 'SQ_DPP_WF_RR1', 'SQ_DPP_WF_SL1', 'SQ_DPP_WF_SR1', + 'SQ_DS_ADD_F32', 'SQ_DS_ADD_RTN_F32', 'SQ_DS_ADD_RTN_U32', + 'SQ_DS_ADD_RTN_U64', 'SQ_DS_ADD_SRC2_F32', 'SQ_DS_ADD_SRC2_U32', + 'SQ_DS_ADD_SRC2_U64', 'SQ_DS_ADD_U32', 'SQ_DS_ADD_U64', + 'SQ_DS_AND_B32', 'SQ_DS_AND_B64', 'SQ_DS_AND_RTN_B32', + 'SQ_DS_AND_RTN_B64', 'SQ_DS_AND_SRC2_B32', 'SQ_DS_AND_SRC2_B64', + 'SQ_DS_APPEND', 'SQ_DS_BPERMUTE_B32', 'SQ_DS_CMPST_B32', + 'SQ_DS_CMPST_B64', 'SQ_DS_CMPST_F32', 'SQ_DS_CMPST_F64', + 'SQ_DS_CMPST_RTN_B32', 'SQ_DS_CMPST_RTN_B64', + 'SQ_DS_CMPST_RTN_F32', 'SQ_DS_CMPST_RTN_F64', + 'SQ_DS_CONDXCHG32_RTN_B128', 'SQ_DS_CONDXCHG32_RTN_B64', + 'SQ_DS_CONSUME', 'SQ_DS_DEC_RTN_U32', 'SQ_DS_DEC_RTN_U64', + 'SQ_DS_DEC_SRC2_U32', 'SQ_DS_DEC_SRC2_U64', 'SQ_DS_DEC_U32', + 'SQ_DS_DEC_U64', 'SQ_DS_GWS_BARRIER', 'SQ_DS_GWS_INIT', + 'SQ_DS_GWS_SEMA_BR', 'SQ_DS_GWS_SEMA_P', + 'SQ_DS_GWS_SEMA_RELEASE_ALL', 'SQ_DS_GWS_SEMA_V', + 'SQ_DS_INC_RTN_U32', 'SQ_DS_INC_RTN_U64', 'SQ_DS_INC_SRC2_U32', + 'SQ_DS_INC_SRC2_U64', 'SQ_DS_INC_U32', 'SQ_DS_INC_U64', + 'SQ_DS_MAX_F32', 'SQ_DS_MAX_F64', 'SQ_DS_MAX_I32', + 'SQ_DS_MAX_I64', 'SQ_DS_MAX_RTN_F32', 'SQ_DS_MAX_RTN_F64', + 'SQ_DS_MAX_RTN_I32', 'SQ_DS_MAX_RTN_I64', 'SQ_DS_MAX_RTN_U32', + 'SQ_DS_MAX_RTN_U64', 'SQ_DS_MAX_SRC2_F32', 'SQ_DS_MAX_SRC2_F64', + 'SQ_DS_MAX_SRC2_I32', 'SQ_DS_MAX_SRC2_I64', 'SQ_DS_MAX_SRC2_U32', + 'SQ_DS_MAX_SRC2_U64', 'SQ_DS_MAX_U32', 'SQ_DS_MAX_U64', + 'SQ_DS_MIN_F32', 'SQ_DS_MIN_F64', 'SQ_DS_MIN_I32', + 'SQ_DS_MIN_I64', 'SQ_DS_MIN_RTN_F32', 'SQ_DS_MIN_RTN_F64', + 'SQ_DS_MIN_RTN_I32', 'SQ_DS_MIN_RTN_I64', 'SQ_DS_MIN_RTN_U32', + 'SQ_DS_MIN_RTN_U64', 'SQ_DS_MIN_SRC2_F32', 'SQ_DS_MIN_SRC2_F64', + 'SQ_DS_MIN_SRC2_I32', 'SQ_DS_MIN_SRC2_I64', 'SQ_DS_MIN_SRC2_U32', + 'SQ_DS_MIN_SRC2_U64', 'SQ_DS_MIN_U32', 'SQ_DS_MIN_U64', + 'SQ_DS_MSKOR_B32', 'SQ_DS_MSKOR_B64', 'SQ_DS_MSKOR_RTN_B32', + 'SQ_DS_MSKOR_RTN_B64', 'SQ_DS_NOP', 'SQ_DS_ORDERED_COUNT', + 'SQ_DS_OR_B32', 'SQ_DS_OR_B64', 'SQ_DS_OR_RTN_B32', + 'SQ_DS_OR_RTN_B64', 'SQ_DS_OR_SRC2_B32', 'SQ_DS_OR_SRC2_B64', + 'SQ_DS_PERMUTE_B32', 'SQ_DS_READ2ST64_B32', 'SQ_DS_READ2ST64_B64', + 'SQ_DS_READ2_B32', 'SQ_DS_READ2_B64', 'SQ_DS_READ_ADDTID_B32', + 'SQ_DS_READ_B128', 'SQ_DS_READ_B32', 'SQ_DS_READ_B64', + 'SQ_DS_READ_B96', 'SQ_DS_READ_I16', 'SQ_DS_READ_I8', + 'SQ_DS_READ_U16', 'SQ_DS_READ_U8', 'SQ_DS_RSUB_RTN_U32', + 'SQ_DS_RSUB_RTN_U64', 'SQ_DS_RSUB_SRC2_U32', + 'SQ_DS_RSUB_SRC2_U64', 'SQ_DS_RSUB_U32', 'SQ_DS_RSUB_U64', + 'SQ_DS_SUB_RTN_U32', 'SQ_DS_SUB_RTN_U64', 'SQ_DS_SUB_SRC2_U32', + 'SQ_DS_SUB_SRC2_U64', 'SQ_DS_SUB_U32', 'SQ_DS_SUB_U64', + 'SQ_DS_SWIZZLE_B32', 'SQ_DS_WRAP_RTN_B32', 'SQ_DS_WRITE2ST64_B32', + 'SQ_DS_WRITE2ST64_B64', 'SQ_DS_WRITE2_B32', 'SQ_DS_WRITE2_B64', + 'SQ_DS_WRITE_ADDTID_B32', 'SQ_DS_WRITE_B128', 'SQ_DS_WRITE_B16', + 'SQ_DS_WRITE_B32', 'SQ_DS_WRITE_B64', 'SQ_DS_WRITE_B8', + 'SQ_DS_WRITE_B96', 'SQ_DS_WRITE_SRC2_B32', 'SQ_DS_WRITE_SRC2_B64', + 'SQ_DS_WRXCHG2ST64_RTN_B32', 'SQ_DS_WRXCHG2ST64_RTN_B64', + 'SQ_DS_WRXCHG2_RTN_B32', 'SQ_DS_WRXCHG2_RTN_B64', + 'SQ_DS_WRXCHG_RTN_B32', 'SQ_DS_WRXCHG_RTN_B64', 'SQ_DS_XOR_B32', + 'SQ_DS_XOR_B64', 'SQ_DS_XOR_RTN_B32', 'SQ_DS_XOR_RTN_B64', + 'SQ_DS_XOR_SRC2_B32', 'SQ_DS_XOR_SRC2_B64', 'SQ_EDC_FUE_CNTL_LDS', + 'SQ_EDC_FUE_CNTL_SIMD0', 'SQ_EDC_FUE_CNTL_SIMD1', + 'SQ_EDC_FUE_CNTL_SIMD2', 'SQ_EDC_FUE_CNTL_SIMD3', + 'SQ_EDC_FUE_CNTL_SQ', 'SQ_EDC_FUE_CNTL_TA', 'SQ_EDC_FUE_CNTL_TCP', + 'SQ_EDC_FUE_CNTL_TD', 'SQ_EDC_INFO_SOURCE', + 'SQ_EDC_INFO_SOURCE_GDS', 'SQ_EDC_INFO_SOURCE_INST', + 'SQ_EDC_INFO_SOURCE_INVALID', 'SQ_EDC_INFO_SOURCE_LDS', + 'SQ_EDC_INFO_SOURCE_SGPR', 'SQ_EDC_INFO_SOURCE_TA', + 'SQ_EDC_INFO_SOURCE_VGPR', 'SQ_ENC_DS_BITS', 'SQ_ENC_DS_FIELD', + 'SQ_ENC_DS_MASK', 'SQ_ENC_EXP_BITS', 'SQ_ENC_EXP_FIELD', + 'SQ_ENC_EXP_MASK', 'SQ_ENC_FLAT_BITS', 'SQ_ENC_FLAT_FIELD', + 'SQ_ENC_FLAT_MASK', 'SQ_ENC_MIMG_BITS', 'SQ_ENC_MIMG_FIELD', + 'SQ_ENC_MIMG_MASK', 'SQ_ENC_MTBUF_BITS', 'SQ_ENC_MTBUF_FIELD', + 'SQ_ENC_MTBUF_MASK', 'SQ_ENC_MUBUF_BITS', 'SQ_ENC_MUBUF_FIELD', + 'SQ_ENC_MUBUF_MASK', 'SQ_ENC_SMEM_BITS', 'SQ_ENC_SMEM_FIELD', + 'SQ_ENC_SMEM_MASK', 'SQ_ENC_SOP1_BITS', 'SQ_ENC_SOP1_FIELD', + 'SQ_ENC_SOP1_MASK', 'SQ_ENC_SOP2_BITS', 'SQ_ENC_SOP2_FIELD', + 'SQ_ENC_SOP2_MASK', 'SQ_ENC_SOPC_BITS', 'SQ_ENC_SOPC_FIELD', + 'SQ_ENC_SOPC_MASK', 'SQ_ENC_SOPK_BITS', 'SQ_ENC_SOPK_FIELD', + 'SQ_ENC_SOPK_MASK', 'SQ_ENC_SOPP_BITS', 'SQ_ENC_SOPP_FIELD', + 'SQ_ENC_SOPP_MASK', 'SQ_ENC_VINTRP_BITS', 'SQ_ENC_VINTRP_FIELD', + 'SQ_ENC_VINTRP_MASK', 'SQ_ENC_VOP1_BITS', 'SQ_ENC_VOP1_FIELD', + 'SQ_ENC_VOP1_MASK', 'SQ_ENC_VOP2_BITS', 'SQ_ENC_VOP2_FIELD', + 'SQ_ENC_VOP2_MASK', 'SQ_ENC_VOP3P_BITS', 'SQ_ENC_VOP3P_FIELD', + 'SQ_ENC_VOP3P_MASK', 'SQ_ENC_VOP3_BITS', 'SQ_ENC_VOP3_FIELD', + 'SQ_ENC_VOP3_MASK', 'SQ_ENC_VOPC_BITS', 'SQ_ENC_VOPC_FIELD', + 'SQ_ENC_VOPC_MASK', 'SQ_EQ', 'SQ_EXEC_HI', 'SQ_EXEC_LO', 'SQ_EXP', + 'SQ_EXPORT_RAT_INST_ADD', 'SQ_EXPORT_RAT_INST_ADD_RTN', + 'SQ_EXPORT_RAT_INST_AND', 'SQ_EXPORT_RAT_INST_AND_RTN', + 'SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM', + 'SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN', + 'SQ_EXPORT_RAT_INST_CMPXCHG_FLT', + 'SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN', + 'SQ_EXPORT_RAT_INST_CMPXCHG_INT', + 'SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN', + 'SQ_EXPORT_RAT_INST_DEC_UINT', 'SQ_EXPORT_RAT_INST_DEC_UINT_RTN', + 'SQ_EXPORT_RAT_INST_INC_UINT', 'SQ_EXPORT_RAT_INST_INC_UINT_RTN', + 'SQ_EXPORT_RAT_INST_MAX_INT', 'SQ_EXPORT_RAT_INST_MAX_INT_RTN', + 'SQ_EXPORT_RAT_INST_MAX_UINT', 'SQ_EXPORT_RAT_INST_MAX_UINT_RTN', + 'SQ_EXPORT_RAT_INST_MIN_INT', 'SQ_EXPORT_RAT_INST_MIN_INT_RTN', + 'SQ_EXPORT_RAT_INST_MIN_UINT', 'SQ_EXPORT_RAT_INST_MIN_UINT_RTN', + 'SQ_EXPORT_RAT_INST_MSKOR', 'SQ_EXPORT_RAT_INST_MSKOR_RTN', + 'SQ_EXPORT_RAT_INST_NOP', 'SQ_EXPORT_RAT_INST_NOP_RTN', + 'SQ_EXPORT_RAT_INST_OR', 'SQ_EXPORT_RAT_INST_OR_RTN', + 'SQ_EXPORT_RAT_INST_RSUB', 'SQ_EXPORT_RAT_INST_RSUB_RTN', + 'SQ_EXPORT_RAT_INST_STORE_BYTE', 'SQ_EXPORT_RAT_INST_STORE_DWORD', + 'SQ_EXPORT_RAT_INST_STORE_RAW', + 'SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM', + 'SQ_EXPORT_RAT_INST_STORE_SHORT', + 'SQ_EXPORT_RAT_INST_STORE_TYPED', 'SQ_EXPORT_RAT_INST_SUB', + 'SQ_EXPORT_RAT_INST_SUB_RTN', + 'SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN', + 'SQ_EXPORT_RAT_INST_XCHG_RTN', 'SQ_EXPORT_RAT_INST_XOR', + 'SQ_EXPORT_RAT_INST_XOR_RTN', 'SQ_EXP_GDS0', 'SQ_EXP_MRT0', + 'SQ_EXP_MRTZ', 'SQ_EXP_NULL', 'SQ_EXP_NUM_GDS', 'SQ_EXP_NUM_MRT', + 'SQ_EXP_NUM_PARAM', 'SQ_EXP_NUM_POS', 'SQ_EXP_PARAM0', + 'SQ_EXP_POS0', 'SQ_EX_MODE_EXCP_ADDR_WATCH0', + 'SQ_EX_MODE_EXCP_DIV0', 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH1', + 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH2', + 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH3', 'SQ_EX_MODE_EXCP_INEXACT', + 'SQ_EX_MODE_EXCP_INPUT_DENORM', 'SQ_EX_MODE_EXCP_INT_DIV0', + 'SQ_EX_MODE_EXCP_INVALID', 'SQ_EX_MODE_EXCP_MEM_VIOL', + 'SQ_EX_MODE_EXCP_OVERFLOW', 'SQ_EX_MODE_EXCP_UNDERFLOW', + 'SQ_EX_MODE_EXCP_VALU_BASE', 'SQ_EX_MODE_EXCP_VALU_SIZE', 'SQ_F', + 'SQ_FLAT', 'SQ_FLAT_ATOMIC_ADD', 'SQ_FLAT_ATOMIC_ADD_X2', + 'SQ_FLAT_ATOMIC_AND', 'SQ_FLAT_ATOMIC_AND_X2', + 'SQ_FLAT_ATOMIC_CMPSWAP', 'SQ_FLAT_ATOMIC_CMPSWAP_X2', + 'SQ_FLAT_ATOMIC_DEC', 'SQ_FLAT_ATOMIC_DEC_X2', + 'SQ_FLAT_ATOMIC_INC', 'SQ_FLAT_ATOMIC_INC_X2', + 'SQ_FLAT_ATOMIC_OR', 'SQ_FLAT_ATOMIC_OR_X2', + 'SQ_FLAT_ATOMIC_SMAX', 'SQ_FLAT_ATOMIC_SMAX_X2', + 'SQ_FLAT_ATOMIC_SMIN', 'SQ_FLAT_ATOMIC_SMIN_X2', + 'SQ_FLAT_ATOMIC_SUB', 'SQ_FLAT_ATOMIC_SUB_X2', + 'SQ_FLAT_ATOMIC_SWAP', 'SQ_FLAT_ATOMIC_SWAP_X2', + 'SQ_FLAT_ATOMIC_UMAX', 'SQ_FLAT_ATOMIC_UMAX_X2', + 'SQ_FLAT_ATOMIC_UMIN', 'SQ_FLAT_ATOMIC_UMIN_X2', + 'SQ_FLAT_ATOMIC_XOR', 'SQ_FLAT_ATOMIC_XOR_X2', + 'SQ_FLAT_LOAD_DWORD', 'SQ_FLAT_LOAD_DWORDX2', + 'SQ_FLAT_LOAD_DWORDX3', 'SQ_FLAT_LOAD_DWORDX4', + 'SQ_FLAT_LOAD_SBYTE', 'SQ_FLAT_LOAD_SSHORT', 'SQ_FLAT_LOAD_UBYTE', + 'SQ_FLAT_LOAD_USHORT', 'SQ_FLAT_SCRATCH_HI', 'SQ_FLAT_SCRATCH_LO', + 'SQ_FLAT_STORE_BYTE', 'SQ_FLAT_STORE_DWORD', + 'SQ_FLAT_STORE_DWORDX2', 'SQ_FLAT_STORE_DWORDX3', + 'SQ_FLAT_STORE_DWORDX4', 'SQ_FLAT_STORE_SHORT', 'SQ_GE', + 'SQ_GFXDEC_BEGIN', 'SQ_GFXDEC_END', 'SQ_GFXDEC_STATE_ID_SHIFT', + 'SQ_GLOBAL', 'SQ_GLOBAL_ATOMIC_ADD', 'SQ_GLOBAL_ATOMIC_ADD_X2', + 'SQ_GLOBAL_ATOMIC_AND', 'SQ_GLOBAL_ATOMIC_AND_X2', + 'SQ_GLOBAL_ATOMIC_CMPSWAP', 'SQ_GLOBAL_ATOMIC_CMPSWAP_X2', + 'SQ_GLOBAL_ATOMIC_DEC', 'SQ_GLOBAL_ATOMIC_DEC_X2', + 'SQ_GLOBAL_ATOMIC_INC', 'SQ_GLOBAL_ATOMIC_INC_X2', + 'SQ_GLOBAL_ATOMIC_OR', 'SQ_GLOBAL_ATOMIC_OR_X2', + 'SQ_GLOBAL_ATOMIC_SMAX', 'SQ_GLOBAL_ATOMIC_SMAX_X2', + 'SQ_GLOBAL_ATOMIC_SMIN', 'SQ_GLOBAL_ATOMIC_SMIN_X2', + 'SQ_GLOBAL_ATOMIC_SUB', 'SQ_GLOBAL_ATOMIC_SUB_X2', + 'SQ_GLOBAL_ATOMIC_SWAP', 'SQ_GLOBAL_ATOMIC_SWAP_X2', + 'SQ_GLOBAL_ATOMIC_UMAX', 'SQ_GLOBAL_ATOMIC_UMAX_X2', + 'SQ_GLOBAL_ATOMIC_UMIN', 'SQ_GLOBAL_ATOMIC_UMIN_X2', + 'SQ_GLOBAL_ATOMIC_XOR', 'SQ_GLOBAL_ATOMIC_XOR_X2', + 'SQ_GLOBAL_LOAD_DWORD', 'SQ_GLOBAL_LOAD_DWORDX2', + 'SQ_GLOBAL_LOAD_DWORDX3', 'SQ_GLOBAL_LOAD_DWORDX4', + 'SQ_GLOBAL_LOAD_SBYTE', 'SQ_GLOBAL_LOAD_SSHORT', + 'SQ_GLOBAL_LOAD_UBYTE', 'SQ_GLOBAL_LOAD_USHORT', + 'SQ_GLOBAL_STORE_BYTE', 'SQ_GLOBAL_STORE_DWORD', + 'SQ_GLOBAL_STORE_DWORDX2', 'SQ_GLOBAL_STORE_DWORDX3', + 'SQ_GLOBAL_STORE_DWORDX4', 'SQ_GLOBAL_STORE_SHORT', + 'SQ_GS_OP_CUT', 'SQ_GS_OP_EMIT', 'SQ_GS_OP_EMIT_CUT', + 'SQ_GS_OP_NOP', 'SQ_GT', 'SQ_HWREG_ID_SHIFT', 'SQ_HWREG_ID_SIZE', + 'SQ_HWREG_OFFSET_SHIFT', 'SQ_HWREG_OFFSET_SIZE', + 'SQ_HWREG_SIZE_SHIFT', 'SQ_HWREG_SIZE_SIZE', 'SQ_HW_REG_FLUSH_IB', + 'SQ_HW_REG_GPR_ALLOC', 'SQ_HW_REG_HW_ID', 'SQ_HW_REG_IB_DBG0', + 'SQ_HW_REG_IB_DBG1', 'SQ_HW_REG_IB_STS', 'SQ_HW_REG_INST_DW0', + 'SQ_HW_REG_INST_DW1', 'SQ_HW_REG_LDS_ALLOC', 'SQ_HW_REG_MODE', + 'SQ_HW_REG_PC_HI', 'SQ_HW_REG_PC_LO', 'SQ_HW_REG_SH_MEM_BASES', + 'SQ_HW_REG_SQ_SHADER_TBA_HI', 'SQ_HW_REG_SQ_SHADER_TBA_LO', + 'SQ_HW_REG_SQ_SHADER_TMA_HI', 'SQ_HW_REG_SQ_SHADER_TMA_LO', + 'SQ_HW_REG_STATUS', 'SQ_HW_REG_TRAPSTS', 'SQ_IBUF_IB_DRET', + 'SQ_IBUF_IB_EMPTY_WAIT_DRET', 'SQ_IBUF_IB_EMPTY_WAIT_GNT', + 'SQ_IBUF_IB_IDLE', 'SQ_IBUF_IB_INI_WAIT_DRET', + 'SQ_IBUF_IB_INI_WAIT_GNT', 'SQ_IBUF_IB_LE_4DW', + 'SQ_IBUF_IB_WAIT_DRET', 'SQ_IBUF_ST', 'SQ_IMAGE_ATOMIC_ADD', + 'SQ_IMAGE_ATOMIC_AND', 'SQ_IMAGE_ATOMIC_CMPSWAP', + 'SQ_IMAGE_ATOMIC_DEC', 'SQ_IMAGE_ATOMIC_INC', + 'SQ_IMAGE_ATOMIC_OR', 'SQ_IMAGE_ATOMIC_SMAX', + 'SQ_IMAGE_ATOMIC_SMIN', 'SQ_IMAGE_ATOMIC_SUB', + 'SQ_IMAGE_ATOMIC_SWAP', 'SQ_IMAGE_ATOMIC_UMAX', + 'SQ_IMAGE_ATOMIC_UMIN', 'SQ_IMAGE_ATOMIC_XOR', 'SQ_IMAGE_GATHER4', + 'SQ_IMAGE_GATHER4H', 'SQ_IMAGE_GATHER4H_PCK', + 'SQ_IMAGE_GATHER4_B', 'SQ_IMAGE_GATHER4_B_CL', + 'SQ_IMAGE_GATHER4_B_CL_O', 'SQ_IMAGE_GATHER4_B_O', + 'SQ_IMAGE_GATHER4_C', 'SQ_IMAGE_GATHER4_CL', + 'SQ_IMAGE_GATHER4_CL_O', 'SQ_IMAGE_GATHER4_C_B', + 'SQ_IMAGE_GATHER4_C_B_CL', 'SQ_IMAGE_GATHER4_C_B_CL_O', + 'SQ_IMAGE_GATHER4_C_B_O', 'SQ_IMAGE_GATHER4_C_CL', + 'SQ_IMAGE_GATHER4_C_CL_O', 'SQ_IMAGE_GATHER4_C_L', + 'SQ_IMAGE_GATHER4_C_LZ', 'SQ_IMAGE_GATHER4_C_LZ_O', + 'SQ_IMAGE_GATHER4_C_L_O', 'SQ_IMAGE_GATHER4_C_O', + 'SQ_IMAGE_GATHER4_L', 'SQ_IMAGE_GATHER4_LZ', + 'SQ_IMAGE_GATHER4_LZ_O', 'SQ_IMAGE_GATHER4_L_O', + 'SQ_IMAGE_GATHER4_O', 'SQ_IMAGE_GATHER8H_PCK', 'SQ_IMAGE_GET_LOD', + 'SQ_IMAGE_GET_RESINFO', 'SQ_IMAGE_LOAD', 'SQ_IMAGE_LOAD_MIP', + 'SQ_IMAGE_LOAD_MIP_PCK', 'SQ_IMAGE_LOAD_MIP_PCK_SGN', + 'SQ_IMAGE_LOAD_PCK', 'SQ_IMAGE_LOAD_PCK_SGN', 'SQ_IMAGE_RSRC256', + 'SQ_IMAGE_SAMPLE', 'SQ_IMAGE_SAMPLER', 'SQ_IMAGE_SAMPLE_B', + 'SQ_IMAGE_SAMPLE_B_CL', 'SQ_IMAGE_SAMPLE_B_CL_O', + 'SQ_IMAGE_SAMPLE_B_O', 'SQ_IMAGE_SAMPLE_C', 'SQ_IMAGE_SAMPLE_CD', + 'SQ_IMAGE_SAMPLE_CD_CL', 'SQ_IMAGE_SAMPLE_CD_CL_O', + 'SQ_IMAGE_SAMPLE_CD_O', 'SQ_IMAGE_SAMPLE_CL', + 'SQ_IMAGE_SAMPLE_CL_O', 'SQ_IMAGE_SAMPLE_C_B', + 'SQ_IMAGE_SAMPLE_C_B_CL', 'SQ_IMAGE_SAMPLE_C_B_CL_O', + 'SQ_IMAGE_SAMPLE_C_B_O', 'SQ_IMAGE_SAMPLE_C_CD', + 'SQ_IMAGE_SAMPLE_C_CD_CL', 'SQ_IMAGE_SAMPLE_C_CD_CL_O', + 'SQ_IMAGE_SAMPLE_C_CD_O', 'SQ_IMAGE_SAMPLE_C_CL', + 'SQ_IMAGE_SAMPLE_C_CL_O', 'SQ_IMAGE_SAMPLE_C_D', + 'SQ_IMAGE_SAMPLE_C_D_CL', 'SQ_IMAGE_SAMPLE_C_D_CL_O', + 'SQ_IMAGE_SAMPLE_C_D_O', 'SQ_IMAGE_SAMPLE_C_L', + 'SQ_IMAGE_SAMPLE_C_LZ', 'SQ_IMAGE_SAMPLE_C_LZ_O', + 'SQ_IMAGE_SAMPLE_C_L_O', 'SQ_IMAGE_SAMPLE_C_O', + 'SQ_IMAGE_SAMPLE_D', 'SQ_IMAGE_SAMPLE_D_CL', + 'SQ_IMAGE_SAMPLE_D_CL_O', 'SQ_IMAGE_SAMPLE_D_O', + 'SQ_IMAGE_SAMPLE_L', 'SQ_IMAGE_SAMPLE_LZ', 'SQ_IMAGE_SAMPLE_LZ_O', + 'SQ_IMAGE_SAMPLE_L_O', 'SQ_IMAGE_SAMPLE_O', 'SQ_IMAGE_STORE', + 'SQ_IMAGE_STORE_MIP', 'SQ_IMAGE_STORE_MIP_PCK', + 'SQ_IMAGE_STORE_PCK', 'SQ_IMG_FILTER_MODE_BLEND', + 'SQ_IMG_FILTER_MODE_MAX', 'SQ_IMG_FILTER_MODE_MIN', + 'SQ_IMG_FILTER_TYPE', 'SQ_IND_CMD_CMD', 'SQ_IND_CMD_CMD_DEBUG', + 'SQ_IND_CMD_CMD_KILL', 'SQ_IND_CMD_CMD_NULL', + 'SQ_IND_CMD_CMD_SAVECTX', 'SQ_IND_CMD_CMD_SETFATALHALT', + 'SQ_IND_CMD_CMD_SETHALT', 'SQ_IND_CMD_CMD_SET_SPI_PRIO', + 'SQ_IND_CMD_CMD_TRAP', 'SQ_IND_CMD_MODE', + 'SQ_IND_CMD_MODE_BROADCAST', 'SQ_IND_CMD_MODE_BROADCAST_ME', + 'SQ_IND_CMD_MODE_BROADCAST_PIPE', + 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', 'SQ_IND_CMD_MODE_SINGLE', + 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', + 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', + 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', + 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', 'SQ_INST_STR_IB_WAVE_NORML', + 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', + 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST0', + 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST1', 'SQ_INST_STR_ST', + 'SQ_INTERRUPT_WORD_ENCODING', 'SQ_INTERRUPT_WORD_ENCODING_AUTO', + 'SQ_INTERRUPT_WORD_ENCODING_ERROR', + 'SQ_INTERRUPT_WORD_ENCODING_INST', 'SQ_L1', 'SQ_L10', 'SQ_L11', + 'SQ_L12', 'SQ_L13', 'SQ_L14', 'SQ_L15', 'SQ_L2', 'SQ_L3', 'SQ_L4', + 'SQ_L5', 'SQ_L6', 'SQ_L7', 'SQ_L8', 'SQ_L9', + 'SQ_LB_CTR_SEL_ALU_CYCLES', 'SQ_LB_CTR_SEL_ALU_STALLS', + 'SQ_LB_CTR_SEL_DCACHE_STALLS', 'SQ_LB_CTR_SEL_ICACHE_STALLS', + 'SQ_LB_CTR_SEL_RESERVED0', 'SQ_LB_CTR_SEL_RESERVED1', + 'SQ_LB_CTR_SEL_RESERVED2', 'SQ_LB_CTR_SEL_RESERVED3', + 'SQ_LB_CTR_SEL_RESERVED4', 'SQ_LB_CTR_SEL_RESERVED5', + 'SQ_LB_CTR_SEL_RESERVED6', 'SQ_LB_CTR_SEL_SALU_CYCLES', + 'SQ_LB_CTR_SEL_SCALAR_STALLS', 'SQ_LB_CTR_SEL_SMEM_CYCLES', + 'SQ_LB_CTR_SEL_TEX_CYCLES', 'SQ_LB_CTR_SEL_TEX_STALLS', + 'SQ_LB_CTR_SEL_VALUES', 'SQ_LE', 'SQ_LG', 'SQ_LT', 'SQ_M0', + 'SQ_MAX_PGM_SGPRS', 'SQ_MAX_PGM_VGPRS', + 'SQ_MSG_EARLY_PRIM_DEALLOC', 'SQ_MSG_GS', 'SQ_MSG_GS_ALLOC_REQ', + 'SQ_MSG_GS_DONE', 'SQ_MSG_HALT_WAVES', 'SQ_MSG_INTERRUPT', + 'SQ_MSG_ORDERED_PS_DONE', 'SQ_MSG_SAVEWAVE', + 'SQ_MSG_STALL_WAVE_GEN', 'SQ_MSG_SYSMSG', 'SQ_NE', 'SQ_NEQ', + 'SQ_NGE', 'SQ_NGT', 'SQ_NLE', 'SQ_NLG', 'SQ_NLT', 'SQ_NON_EVENT', + 'SQ_NUM_ATTR', 'SQ_NUM_SGPR', 'SQ_NUM_TTMP', 'SQ_NUM_VGPR', + 'SQ_O', 'SQ_OMOD_D2', 'SQ_OMOD_M2', 'SQ_OMOD_M4', 'SQ_OMOD_OFF', + 'SQ_PARAM_P0', 'SQ_PARAM_P10', 'SQ_PARAM_P20', 'SQ_PERF_SEL', + 'SQ_PERF_SEL_ACCUM_PREV', 'SQ_PERF_SEL_ACCUM_PREV_HIRES', + 'SQ_PERF_SEL_ACTIVE_INST_ANY', 'SQ_PERF_SEL_ACTIVE_INST_EXP_GDS', + 'SQ_PERF_SEL_ACTIVE_INST_FLAT', 'SQ_PERF_SEL_ACTIVE_INST_LDS', + 'SQ_PERF_SEL_ACTIVE_INST_MISC', 'SQ_PERF_SEL_ACTIVE_INST_SCA', + 'SQ_PERF_SEL_ACTIVE_INST_VALU', 'SQ_PERF_SEL_ACTIVE_INST_VMEM', + 'SQ_PERF_SEL_ATC_INSTS_SMEM', 'SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY', + 'SQ_PERF_SEL_ATC_INSTS_VMEM', 'SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY', + 'SQ_PERF_SEL_ATC_INST_LEVEL_SMEM', + 'SQ_PERF_SEL_ATC_INST_LEVEL_VMEM', 'SQ_PERF_SEL_ATC_XNACK_ALL', + 'SQ_PERF_SEL_ATC_XNACK_FIFO_FULL', 'SQ_PERF_SEL_ATC_XNACK_FIRST', + 'SQ_PERF_SEL_BUSY_CU_CYCLES', 'SQ_PERF_SEL_BUSY_CYCLES', + 'SQ_PERF_SEL_CBRANCH_FORK', 'SQ_PERF_SEL_CBRANCH_FORK_SPLIT', + 'SQ_PERF_SEL_CYCLES', 'SQ_PERF_SEL_DUMMY_END', + 'SQ_PERF_SEL_DUMMY_LAST', 'SQ_PERF_SEL_EVENTS', + 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', + 'SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT', 'SQ_PERF_SEL_IFETCH', + 'SQ_PERF_SEL_IFETCH_LEVEL', 'SQ_PERF_SEL_IFETCH_XNACK', + 'SQ_PERF_SEL_INSTS', 'SQ_PERF_SEL_INSTS_BRANCH', + 'SQ_PERF_SEL_INSTS_EXP', 'SQ_PERF_SEL_INSTS_EXP_GDS', + 'SQ_PERF_SEL_INSTS_FLAT', 'SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY', + 'SQ_PERF_SEL_INSTS_FLAT_REPLAY', 'SQ_PERF_SEL_INSTS_GDS', + 'SQ_PERF_SEL_INSTS_LDS', 'SQ_PERF_SEL_INSTS_SALU', + 'SQ_PERF_SEL_INSTS_SENDMSG', 'SQ_PERF_SEL_INSTS_SMEM', + 'SQ_PERF_SEL_INSTS_SMEM_NORM', + 'SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY', + 'SQ_PERF_SEL_INSTS_SMEM_REPLAY', 'SQ_PERF_SEL_INSTS_VALU', + 'SQ_PERF_SEL_INSTS_VMEM', 'SQ_PERF_SEL_INSTS_VMEM_RD', + 'SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY', + 'SQ_PERF_SEL_INSTS_VMEM_REPLAY', 'SQ_PERF_SEL_INSTS_VMEM_WR', + 'SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY', 'SQ_PERF_SEL_INSTS_VSKIPPED', + 'SQ_PERF_SEL_INST_CYCLES_EXP', 'SQ_PERF_SEL_INST_CYCLES_GDS', + 'SQ_PERF_SEL_INST_CYCLES_SALU', 'SQ_PERF_SEL_INST_CYCLES_SMEM', + 'SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR', + 'SQ_PERF_SEL_INST_CYCLES_VMEM_CMD', + 'SQ_PERF_SEL_INST_CYCLES_VMEM_DATA', + 'SQ_PERF_SEL_INST_CYCLES_VMEM_RD', + 'SQ_PERF_SEL_INST_CYCLES_VMEM_WR', 'SQ_PERF_SEL_INST_LEVEL_EXP', + 'SQ_PERF_SEL_INST_LEVEL_GDS', 'SQ_PERF_SEL_INST_LEVEL_LDS', + 'SQ_PERF_SEL_INST_LEVEL_SMEM', 'SQ_PERF_SEL_INST_LEVEL_VMEM', + 'SQ_PERF_SEL_ITEMS', 'SQ_PERF_SEL_LDS_ADDR_CONFLICT', + 'SQ_PERF_SEL_LDS_ATOMIC_RETURN', 'SQ_PERF_SEL_LDS_BANK_CONFLICT', + 'SQ_PERF_SEL_LDS_CMD_FIFO_FULL', 'SQ_PERF_SEL_LDS_DATA_FIFO_FULL', + 'SQ_PERF_SEL_LDS_IDX_ACTIVE', 'SQ_PERF_SEL_LDS_MEM_VIOLATIONS', + 'SQ_PERF_SEL_LDS_SRC_CD_CONFLICT', + 'SQ_PERF_SEL_LDS_UNALIGNED_STALL', 'SQ_PERF_SEL_LEVEL_WAVES', + 'SQ_PERF_SEL_LEVEL_WAVES_CU', 'SQ_PERF_SEL_MSG_CNTR', + 'SQ_PERF_SEL_MSG_GSCNT', 'SQ_PERF_SEL_MSG_INTERRUPT', + 'SQ_PERF_SEL_MSG_PERF', 'SQ_PERF_SEL_NONE', + 'SQ_PERF_SEL_POWER_ALU_BUSY', 'SQ_PERF_SEL_POWER_GPR_RD', + 'SQ_PERF_SEL_POWER_GPR_WR', 'SQ_PERF_SEL_POWER_LDS_BUSY', + 'SQ_PERF_SEL_POWER_TEX_BUSY', 'SQ_PERF_SEL_POWER_VALU', + 'SQ_PERF_SEL_POWER_VALU0', 'SQ_PERF_SEL_POWER_VALU1', + 'SQ_PERF_SEL_POWER_VALU2', 'SQ_PERF_SEL_PT_POWER_STALL', + 'SQ_PERF_SEL_QUADS', 'SQ_PERF_SEL_SRC_CD_BUSY', + 'SQ_PERF_SEL_SURF_SYNCS', 'SQ_PERF_SEL_THREAD_CYCLES_VALU', + 'SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX', 'SQ_PERF_SEL_TLB_SHOOTDOWN', + 'SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES', + 'SQ_PERF_SEL_TTRACE_INFLIGHT_REQS', 'SQ_PERF_SEL_TTRACE_REQS', + 'SQ_PERF_SEL_TTRACE_STALL', 'SQ_PERF_SEL_USER0', + 'SQ_PERF_SEL_USER1', 'SQ_PERF_SEL_USER10', 'SQ_PERF_SEL_USER11', + 'SQ_PERF_SEL_USER12', 'SQ_PERF_SEL_USER13', 'SQ_PERF_SEL_USER14', + 'SQ_PERF_SEL_USER15', 'SQ_PERF_SEL_USER2', 'SQ_PERF_SEL_USER3', + 'SQ_PERF_SEL_USER4', 'SQ_PERF_SEL_USER5', 'SQ_PERF_SEL_USER6', + 'SQ_PERF_SEL_USER7', 'SQ_PERF_SEL_USER8', 'SQ_PERF_SEL_USER9', + 'SQ_PERF_SEL_USER_LEVEL0', 'SQ_PERF_SEL_USER_LEVEL1', + 'SQ_PERF_SEL_USER_LEVEL10', 'SQ_PERF_SEL_USER_LEVEL11', + 'SQ_PERF_SEL_USER_LEVEL12', 'SQ_PERF_SEL_USER_LEVEL13', + 'SQ_PERF_SEL_USER_LEVEL14', 'SQ_PERF_SEL_USER_LEVEL15', + 'SQ_PERF_SEL_USER_LEVEL2', 'SQ_PERF_SEL_USER_LEVEL3', + 'SQ_PERF_SEL_USER_LEVEL4', 'SQ_PERF_SEL_USER_LEVEL5', + 'SQ_PERF_SEL_USER_LEVEL6', 'SQ_PERF_SEL_USER_LEVEL7', + 'SQ_PERF_SEL_USER_LEVEL8', 'SQ_PERF_SEL_USER_LEVEL9', + 'SQ_PERF_SEL_UTCL1_LFIFO_FULL', + 'SQ_PERF_SEL_UTCL1_PERMISSION_MISS', 'SQ_PERF_SEL_UTCL1_REQUEST', + 'SQ_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', + 'SQ_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', + 'SQ_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', + 'SQ_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', + 'SQ_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', + 'SQ_PERF_SEL_UTCL1_TRANSLATION_MISS', + 'SQ_PERF_SEL_VALU_DEP_STALL', 'SQ_PERF_SEL_VALU_LDS_DIRECT_RD', + 'SQ_PERF_SEL_VALU_LDS_INTERP_OP', + 'SQ_PERF_SEL_VALU_SRC_C_CONFLICT', 'SQ_PERF_SEL_VALU_STARVE', + 'SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY', + 'SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT', + 'SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT', + 'SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL', 'SQ_PERF_SEL_WAIT_ANY', + 'SQ_PERF_SEL_WAIT_BARRIER', 'SQ_PERF_SEL_WAIT_CNT_ANY', + 'SQ_PERF_SEL_WAIT_CNT_EXP', 'SQ_PERF_SEL_WAIT_CNT_LGKM', + 'SQ_PERF_SEL_WAIT_CNT_VM', 'SQ_PERF_SEL_WAIT_EXP_ALLOC', + 'SQ_PERF_SEL_WAIT_IFETCH', 'SQ_PERF_SEL_WAIT_INST_ANY', + 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', 'SQ_PERF_SEL_WAIT_INST_FLAT', + 'SQ_PERF_SEL_WAIT_INST_LDS', 'SQ_PERF_SEL_WAIT_INST_MISC', + 'SQ_PERF_SEL_WAIT_INST_SCA', 'SQ_PERF_SEL_WAIT_INST_VALU', + 'SQ_PERF_SEL_WAIT_INST_VMEM', 'SQ_PERF_SEL_WAIT_OTHER', + 'SQ_PERF_SEL_WAIT_SLEEP', 'SQ_PERF_SEL_WAIT_SLEEP_XNACK', + 'SQ_PERF_SEL_WAIT_TTRACE', 'SQ_PERF_SEL_WAVES', + 'SQ_PERF_SEL_WAVES_CU', 'SQ_PERF_SEL_WAVES_EQ_64', + 'SQ_PERF_SEL_WAVES_LT_16', 'SQ_PERF_SEL_WAVES_LT_32', + 'SQ_PERF_SEL_WAVES_LT_48', 'SQ_PERF_SEL_WAVES_LT_64', + 'SQ_PERF_SEL_WAVES_RESTORED', 'SQ_PERF_SEL_WAVES_SAVED', + 'SQ_PERF_SEL_WAVE_CYCLES', 'SQ_PERF_SEL_WAVE_READY', 'SQ_R1', + 'SQ_R10', 'SQ_R11', 'SQ_R12', 'SQ_R13', 'SQ_R14', 'SQ_R15', + 'SQ_R2', 'SQ_R3', 'SQ_R4', 'SQ_R5', 'SQ_R6', 'SQ_R7', 'SQ_R8', + 'SQ_R9', 'SQ_ROUND_MINUS_INFINITY', 'SQ_ROUND_MODE', + 'SQ_ROUND_NEAREST_EVEN', 'SQ_ROUND_PLUS_INFINITY', + 'SQ_ROUND_TO_ZERO', 'SQ_RSRC_BUF', 'SQ_RSRC_BUF_RSVD_1', + 'SQ_RSRC_BUF_RSVD_2', 'SQ_RSRC_BUF_RSVD_3', 'SQ_RSRC_BUF_TYPE', + 'SQ_RSRC_FLAT', 'SQ_RSRC_FLAT_RSVD_0', 'SQ_RSRC_FLAT_RSVD_2', + 'SQ_RSRC_FLAT_RSVD_3', 'SQ_RSRC_FLAT_TYPE', 'SQ_RSRC_IMG_1D', + 'SQ_RSRC_IMG_1D_ARRAY', 'SQ_RSRC_IMG_2D', 'SQ_RSRC_IMG_2D_ARRAY', + 'SQ_RSRC_IMG_2D_MSAA', 'SQ_RSRC_IMG_2D_MSAA_ARRAY', + 'SQ_RSRC_IMG_3D', 'SQ_RSRC_IMG_CUBE', 'SQ_RSRC_IMG_RSVD_0', + 'SQ_RSRC_IMG_RSVD_1', 'SQ_RSRC_IMG_RSVD_2', 'SQ_RSRC_IMG_RSVD_3', + 'SQ_RSRC_IMG_RSVD_4', 'SQ_RSRC_IMG_RSVD_5', 'SQ_RSRC_IMG_RSVD_6', + 'SQ_RSRC_IMG_RSVD_7', 'SQ_RSRC_IMG_TYPE', 'SQ_SCRATCH', + 'SQ_SCRATCH_LOAD_DWORD', 'SQ_SCRATCH_LOAD_DWORDX2', + 'SQ_SCRATCH_LOAD_DWORDX3', 'SQ_SCRATCH_LOAD_DWORDX4', + 'SQ_SCRATCH_LOAD_SBYTE', 'SQ_SCRATCH_LOAD_SSHORT', + 'SQ_SCRATCH_LOAD_UBYTE', 'SQ_SCRATCH_LOAD_USHORT', + 'SQ_SCRATCH_STORE_BYTE', 'SQ_SCRATCH_STORE_DWORD', + 'SQ_SCRATCH_STORE_DWORDX2', 'SQ_SCRATCH_STORE_DWORDX3', + 'SQ_SCRATCH_STORE_DWORDX4', 'SQ_SCRATCH_STORE_SHORT', + 'SQ_SDWA_BYTE_0', 'SQ_SDWA_BYTE_1', 'SQ_SDWA_BYTE_2', + 'SQ_SDWA_BYTE_3', 'SQ_SDWA_DWORD', 'SQ_SDWA_UNUSED_PAD', + 'SQ_SDWA_UNUSED_PRESERVE', 'SQ_SDWA_UNUSED_SEXT', + 'SQ_SDWA_WORD_0', 'SQ_SDWA_WORD_1', 'SQ_SEL_0', 'SQ_SEL_1', + 'SQ_SEL_RESERVED_0', 'SQ_SEL_RESERVED_1', 'SQ_SEL_W', 'SQ_SEL_X', + 'SQ_SEL_XYZW01', 'SQ_SEL_Y', 'SQ_SEL_Z', 'SQ_SENDMSG_GSOP_SHIFT', + 'SQ_SENDMSG_GSOP_SIZE', 'SQ_SENDMSG_MSG_SHIFT', + 'SQ_SENDMSG_MSG_SIZE', 'SQ_SENDMSG_STREAMID_SHIFT', + 'SQ_SENDMSG_STREAMID_SIZE', 'SQ_SENDMSG_SYSTEM_SHIFT', + 'SQ_SENDMSG_SYSTEM_SIZE', 'SQ_SGPR0', 'SQ_SRC_0', 'SQ_SRC_0_5', + 'SQ_SRC_1', 'SQ_SRC_10_INT', 'SQ_SRC_11_INT', 'SQ_SRC_12_INT', + 'SQ_SRC_13_INT', 'SQ_SRC_14_INT', 'SQ_SRC_15_INT', + 'SQ_SRC_16_INT', 'SQ_SRC_17_INT', 'SQ_SRC_18_INT', + 'SQ_SRC_19_INT', 'SQ_SRC_1_INT', 'SQ_SRC_2', 'SQ_SRC_20_INT', + 'SQ_SRC_21_INT', 'SQ_SRC_22_INT', 'SQ_SRC_23_INT', + 'SQ_SRC_24_INT', 'SQ_SRC_25_INT', 'SQ_SRC_26_INT', + 'SQ_SRC_27_INT', 'SQ_SRC_28_INT', 'SQ_SRC_29_INT', 'SQ_SRC_2_INT', + 'SQ_SRC_30_INT', 'SQ_SRC_31_INT', 'SQ_SRC_32_INT', + 'SQ_SRC_33_INT', 'SQ_SRC_34_INT', 'SQ_SRC_35_INT', + 'SQ_SRC_36_INT', 'SQ_SRC_37_INT', 'SQ_SRC_38_INT', + 'SQ_SRC_39_INT', 'SQ_SRC_3_INT', 'SQ_SRC_4', 'SQ_SRC_40_INT', + 'SQ_SRC_41_INT', 'SQ_SRC_42_INT', 'SQ_SRC_43_INT', + 'SQ_SRC_44_INT', 'SQ_SRC_45_INT', 'SQ_SRC_46_INT', + 'SQ_SRC_47_INT', 'SQ_SRC_48_INT', 'SQ_SRC_49_INT', 'SQ_SRC_4_INT', + 'SQ_SRC_50_INT', 'SQ_SRC_51_INT', 'SQ_SRC_52_INT', + 'SQ_SRC_53_INT', 'SQ_SRC_54_INT', 'SQ_SRC_55_INT', + 'SQ_SRC_56_INT', 'SQ_SRC_57_INT', 'SQ_SRC_58_INT', + 'SQ_SRC_59_INT', 'SQ_SRC_5_INT', 'SQ_SRC_60_INT', 'SQ_SRC_61_INT', + 'SQ_SRC_62_INT', 'SQ_SRC_63_INT', 'SQ_SRC_64_INT', 'SQ_SRC_6_INT', + 'SQ_SRC_7_INT', 'SQ_SRC_8_INT', 'SQ_SRC_9_INT', 'SQ_SRC_DPP', + 'SQ_SRC_EXECZ', 'SQ_SRC_INV_2PI', 'SQ_SRC_LDS_DIRECT', + 'SQ_SRC_LITERAL', 'SQ_SRC_M_0_5', 'SQ_SRC_M_1', 'SQ_SRC_M_10_INT', + 'SQ_SRC_M_11_INT', 'SQ_SRC_M_12_INT', 'SQ_SRC_M_13_INT', + 'SQ_SRC_M_14_INT', 'SQ_SRC_M_15_INT', 'SQ_SRC_M_16_INT', + 'SQ_SRC_M_1_INT', 'SQ_SRC_M_2', 'SQ_SRC_M_2_INT', + 'SQ_SRC_M_3_INT', 'SQ_SRC_M_4', 'SQ_SRC_M_4_INT', + 'SQ_SRC_M_5_INT', 'SQ_SRC_M_6_INT', 'SQ_SRC_M_7_INT', + 'SQ_SRC_M_8_INT', 'SQ_SRC_M_9_INT', 'SQ_SRC_POPS_EXITING_WAVE_ID', + 'SQ_SRC_PRIVATE_BASE', 'SQ_SRC_PRIVATE_LIMIT', 'SQ_SRC_SCC', + 'SQ_SRC_SDWA', 'SQ_SRC_SHARED_BASE', 'SQ_SRC_SHARED_LIMIT', + 'SQ_SRC_VCCZ', 'SQ_SRC_VGPR0', 'SQ_SRC_VGPR_BIT', + 'SQ_SYSMSG_OP_ECC_ERR_INTERRUPT', 'SQ_SYSMSG_OP_HOST_TRAP_ACK', + 'SQ_SYSMSG_OP_ILLEGAL_INST_INTERRUPT', + 'SQ_SYSMSG_OP_MEMVIOL_INTERRUPT', 'SQ_SYSMSG_OP_REG_RD', + 'SQ_SYSMSG_OP_TTRACE_PC', 'SQ_S_ABSDIFF_I32', 'SQ_S_ABS_I32', + 'SQ_S_ADDC_U32', 'SQ_S_ADDK_I32', 'SQ_S_ADD_I32', 'SQ_S_ADD_U32', + 'SQ_S_ANDN1_SAVEEXEC_B64', 'SQ_S_ANDN1_WREXEC_B64', + 'SQ_S_ANDN2_B32', 'SQ_S_ANDN2_B64', 'SQ_S_ANDN2_SAVEEXEC_B64', + 'SQ_S_ANDN2_WREXEC_B64', 'SQ_S_AND_B32', 'SQ_S_AND_B64', + 'SQ_S_AND_SAVEEXEC_B64', 'SQ_S_ASHR_I32', 'SQ_S_ASHR_I64', + 'SQ_S_ATC_PROBE', 'SQ_S_ATC_PROBE_BUFFER', 'SQ_S_ATOMIC_ADD', + 'SQ_S_ATOMIC_ADD_X2', 'SQ_S_ATOMIC_AND', 'SQ_S_ATOMIC_AND_X2', + 'SQ_S_ATOMIC_CMPSWAP', 'SQ_S_ATOMIC_CMPSWAP_X2', + 'SQ_S_ATOMIC_DEC', 'SQ_S_ATOMIC_DEC_X2', 'SQ_S_ATOMIC_INC', + 'SQ_S_ATOMIC_INC_X2', 'SQ_S_ATOMIC_OR', 'SQ_S_ATOMIC_OR_X2', + 'SQ_S_ATOMIC_SMAX', 'SQ_S_ATOMIC_SMAX_X2', 'SQ_S_ATOMIC_SMIN', + 'SQ_S_ATOMIC_SMIN_X2', 'SQ_S_ATOMIC_SUB', 'SQ_S_ATOMIC_SUB_X2', + 'SQ_S_ATOMIC_SWAP', 'SQ_S_ATOMIC_SWAP_X2', 'SQ_S_ATOMIC_UMAX', + 'SQ_S_ATOMIC_UMAX_X2', 'SQ_S_ATOMIC_UMIN', 'SQ_S_ATOMIC_UMIN_X2', + 'SQ_S_ATOMIC_XOR', 'SQ_S_ATOMIC_XOR_X2', 'SQ_S_BARRIER', + 'SQ_S_BCNT0_I32_B32', 'SQ_S_BCNT0_I32_B64', 'SQ_S_BCNT1_I32_B32', + 'SQ_S_BCNT1_I32_B64', 'SQ_S_BFE_I32', 'SQ_S_BFE_I64', + 'SQ_S_BFE_U32', 'SQ_S_BFE_U64', 'SQ_S_BFM_B32', 'SQ_S_BFM_B64', + 'SQ_S_BITCMP0_B32', 'SQ_S_BITCMP0_B64', 'SQ_S_BITCMP1_B32', + 'SQ_S_BITCMP1_B64', 'SQ_S_BITREPLICATE_B64_B32', + 'SQ_S_BITSET0_B32', 'SQ_S_BITSET0_B64', 'SQ_S_BITSET1_B32', + 'SQ_S_BITSET1_B64', 'SQ_S_BRANCH', 'SQ_S_BREV_B32', + 'SQ_S_BREV_B64', 'SQ_S_BUFFER_ATOMIC_ADD', + 'SQ_S_BUFFER_ATOMIC_ADD_X2', 'SQ_S_BUFFER_ATOMIC_AND', + 'SQ_S_BUFFER_ATOMIC_AND_X2', 'SQ_S_BUFFER_ATOMIC_CMPSWAP', + 'SQ_S_BUFFER_ATOMIC_CMPSWAP_X2', 'SQ_S_BUFFER_ATOMIC_DEC', + 'SQ_S_BUFFER_ATOMIC_DEC_X2', 'SQ_S_BUFFER_ATOMIC_INC', + 'SQ_S_BUFFER_ATOMIC_INC_X2', 'SQ_S_BUFFER_ATOMIC_OR', + 'SQ_S_BUFFER_ATOMIC_OR_X2', 'SQ_S_BUFFER_ATOMIC_SMAX', + 'SQ_S_BUFFER_ATOMIC_SMAX_X2', 'SQ_S_BUFFER_ATOMIC_SMIN', + 'SQ_S_BUFFER_ATOMIC_SMIN_X2', 'SQ_S_BUFFER_ATOMIC_SUB', + 'SQ_S_BUFFER_ATOMIC_SUB_X2', 'SQ_S_BUFFER_ATOMIC_SWAP', + 'SQ_S_BUFFER_ATOMIC_SWAP_X2', 'SQ_S_BUFFER_ATOMIC_UMAX', + 'SQ_S_BUFFER_ATOMIC_UMAX_X2', 'SQ_S_BUFFER_ATOMIC_UMIN', + 'SQ_S_BUFFER_ATOMIC_UMIN_X2', 'SQ_S_BUFFER_ATOMIC_XOR', + 'SQ_S_BUFFER_ATOMIC_XOR_X2', 'SQ_S_BUFFER_LOAD_DWORD', + 'SQ_S_BUFFER_LOAD_DWORDX16', 'SQ_S_BUFFER_LOAD_DWORDX2', + 'SQ_S_BUFFER_LOAD_DWORDX4', 'SQ_S_BUFFER_LOAD_DWORDX8', + 'SQ_S_BUFFER_STORE_DWORD', 'SQ_S_BUFFER_STORE_DWORDX2', + 'SQ_S_BUFFER_STORE_DWORDX4', 'SQ_S_CALL_B64', + 'SQ_S_CBRANCH_CDBGSYS', 'SQ_S_CBRANCH_CDBGSYS_AND_USER', + 'SQ_S_CBRANCH_CDBGSYS_OR_USER', 'SQ_S_CBRANCH_CDBGUSER', + 'SQ_S_CBRANCH_EXECNZ', 'SQ_S_CBRANCH_EXECZ', + 'SQ_S_CBRANCH_G_FORK', 'SQ_S_CBRANCH_I_FORK', 'SQ_S_CBRANCH_JOIN', + 'SQ_S_CBRANCH_SCC0', 'SQ_S_CBRANCH_SCC1', 'SQ_S_CBRANCH_VCCNZ', + 'SQ_S_CBRANCH_VCCZ', 'SQ_S_CMOVK_I32', 'SQ_S_CMOV_B32', + 'SQ_S_CMOV_B64', 'SQ_S_CMPK_EQ_I32', 'SQ_S_CMPK_EQ_U32', + 'SQ_S_CMPK_GE_I32', 'SQ_S_CMPK_GE_U32', 'SQ_S_CMPK_GT_I32', + 'SQ_S_CMPK_GT_U32', 'SQ_S_CMPK_LE_I32', 'SQ_S_CMPK_LE_U32', + 'SQ_S_CMPK_LG_I32', 'SQ_S_CMPK_LG_U32', 'SQ_S_CMPK_LT_I32', + 'SQ_S_CMPK_LT_U32', 'SQ_S_CMP_EQ_I32', 'SQ_S_CMP_EQ_U32', + 'SQ_S_CMP_EQ_U64', 'SQ_S_CMP_GE_I32', 'SQ_S_CMP_GE_U32', + 'SQ_S_CMP_GT_I32', 'SQ_S_CMP_GT_U32', 'SQ_S_CMP_LE_I32', + 'SQ_S_CMP_LE_U32', 'SQ_S_CMP_LG_I32', 'SQ_S_CMP_LG_U32', + 'SQ_S_CMP_LG_U64', 'SQ_S_CMP_LT_I32', 'SQ_S_CMP_LT_U32', + 'SQ_S_CSELECT_B32', 'SQ_S_CSELECT_B64', 'SQ_S_DCACHE_INV', + 'SQ_S_DCACHE_INV_VOL', 'SQ_S_DCACHE_WB', 'SQ_S_DCACHE_WB_VOL', + 'SQ_S_DECPERFLEVEL', 'SQ_S_ENDPGM', 'SQ_S_ENDPGM_ORDERED_PS_DONE', + 'SQ_S_ENDPGM_SAVED', 'SQ_S_FF0_I32_B32', 'SQ_S_FF0_I32_B64', + 'SQ_S_FF1_I32_B32', 'SQ_S_FF1_I32_B64', 'SQ_S_FLBIT_I32', + 'SQ_S_FLBIT_I32_B32', 'SQ_S_FLBIT_I32_B64', 'SQ_S_FLBIT_I32_I64', + 'SQ_S_GETPC_B64', 'SQ_S_GETREG_B32', 'SQ_S_GETREG_REGRD_B32', + 'SQ_S_ICACHE_INV', 'SQ_S_INCPERFLEVEL', 'SQ_S_LOAD_DWORD', + 'SQ_S_LOAD_DWORDX16', 'SQ_S_LOAD_DWORDX2', 'SQ_S_LOAD_DWORDX4', + 'SQ_S_LOAD_DWORDX8', 'SQ_S_LSHL1_ADD_U32', 'SQ_S_LSHL2_ADD_U32', + 'SQ_S_LSHL3_ADD_U32', 'SQ_S_LSHL4_ADD_U32', 'SQ_S_LSHL_B32', + 'SQ_S_LSHL_B64', 'SQ_S_LSHR_B32', 'SQ_S_LSHR_B64', 'SQ_S_MAX_I32', + 'SQ_S_MAX_U32', 'SQ_S_MEMREALTIME', 'SQ_S_MEMTIME', + 'SQ_S_MIN_I32', 'SQ_S_MIN_U32', 'SQ_S_MOVK_I32', + 'SQ_S_MOVRELD_B32', 'SQ_S_MOVRELD_B64', 'SQ_S_MOVRELS_B32', + 'SQ_S_MOVRELS_B64', 'SQ_S_MOV_B32', 'SQ_S_MOV_B64', + 'SQ_S_MOV_FED_B32', 'SQ_S_MOV_REGRD_B32', 'SQ_S_MULK_I32', + 'SQ_S_MUL_HI_I32', 'SQ_S_MUL_HI_U32', 'SQ_S_MUL_I32', + 'SQ_S_NAND_B32', 'SQ_S_NAND_B64', 'SQ_S_NAND_SAVEEXEC_B64', + 'SQ_S_NOP', 'SQ_S_NOR_B32', 'SQ_S_NOR_B64', + 'SQ_S_NOR_SAVEEXEC_B64', 'SQ_S_NOT_B32', 'SQ_S_NOT_B64', + 'SQ_S_ORN1_SAVEEXEC_B64', 'SQ_S_ORN2_B32', 'SQ_S_ORN2_B64', + 'SQ_S_ORN2_SAVEEXEC_B64', 'SQ_S_OR_B32', 'SQ_S_OR_B64', + 'SQ_S_OR_SAVEEXEC_B64', 'SQ_S_PACK_HH_B32_B16', + 'SQ_S_PACK_LH_B32_B16', 'SQ_S_PACK_LL_B32_B16', + 'SQ_S_QUADMASK_B32', 'SQ_S_QUADMASK_B64', 'SQ_S_RFE_B64', + 'SQ_S_RFE_RESTORE_B64', 'SQ_S_SCRATCH_LOAD_DWORD', + 'SQ_S_SCRATCH_LOAD_DWORDX2', 'SQ_S_SCRATCH_LOAD_DWORDX4', + 'SQ_S_SCRATCH_STORE_DWORD', 'SQ_S_SCRATCH_STORE_DWORDX2', + 'SQ_S_SCRATCH_STORE_DWORDX4', 'SQ_S_SENDMSG', 'SQ_S_SENDMSGHALT', + 'SQ_S_SETHALT', 'SQ_S_SETKILL', 'SQ_S_SETPC_B64', 'SQ_S_SETPRIO', + 'SQ_S_SETREG_B32', 'SQ_S_SETREG_IMM32_B32', 'SQ_S_SETVSKIP', + 'SQ_S_SET_GPR_IDX_IDX', 'SQ_S_SET_GPR_IDX_MODE', + 'SQ_S_SET_GPR_IDX_OFF', 'SQ_S_SET_GPR_IDX_ON', + 'SQ_S_SEXT_I32_I16', 'SQ_S_SEXT_I32_I8', 'SQ_S_SLEEP', + 'SQ_S_STORE_DWORD', 'SQ_S_STORE_DWORDX2', 'SQ_S_STORE_DWORDX4', + 'SQ_S_SUBB_U32', 'SQ_S_SUB_I32', 'SQ_S_SUB_U32', + 'SQ_S_SWAPPC_B64', 'SQ_S_TRAP', 'SQ_S_TTRACEDATA', 'SQ_S_WAITCNT', + 'SQ_S_WAKEUP', 'SQ_S_WQM_B32', 'SQ_S_WQM_B64', 'SQ_S_XNOR_B32', + 'SQ_S_XNOR_B64', 'SQ_S_XNOR_SAVEEXEC_B64', 'SQ_S_XOR_B32', + 'SQ_S_XOR_B64', 'SQ_S_XOR_SAVEEXEC_B64', 'SQ_T', + 'SQ_TBUFFER_LOAD_FORMAT_D16_X', 'SQ_TBUFFER_LOAD_FORMAT_D16_XY', + 'SQ_TBUFFER_LOAD_FORMAT_D16_XYZ', + 'SQ_TBUFFER_LOAD_FORMAT_D16_XYZW', 'SQ_TBUFFER_LOAD_FORMAT_X', + 'SQ_TBUFFER_LOAD_FORMAT_XY', 'SQ_TBUFFER_LOAD_FORMAT_XYZ', + 'SQ_TBUFFER_LOAD_FORMAT_XYZW', 'SQ_TBUFFER_STORE_FORMAT_D16_X', + 'SQ_TBUFFER_STORE_FORMAT_D16_XY', + 'SQ_TBUFFER_STORE_FORMAT_D16_XYZ', + 'SQ_TBUFFER_STORE_FORMAT_D16_XYZW', 'SQ_TBUFFER_STORE_FORMAT_X', + 'SQ_TBUFFER_STORE_FORMAT_XY', 'SQ_TBUFFER_STORE_FORMAT_XYZ', + 'SQ_TBUFFER_STORE_FORMAT_XYZW', 'SQ_TEX_ANISO_RATIO', + 'SQ_TEX_ANISO_RATIO_1', 'SQ_TEX_ANISO_RATIO_16', + 'SQ_TEX_ANISO_RATIO_2', 'SQ_TEX_ANISO_RATIO_4', + 'SQ_TEX_ANISO_RATIO_8', 'SQ_TEX_BORDER_COLOR', + 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', + 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', + 'SQ_TEX_BORDER_COLOR_REGISTER', 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', + 'SQ_TEX_CLAMP', 'SQ_TEX_CLAMP_BORDER', 'SQ_TEX_CLAMP_HALF_BORDER', + 'SQ_TEX_CLAMP_LAST_TEXEL', 'SQ_TEX_DEPTH_COMPARE', + 'SQ_TEX_DEPTH_COMPARE_ALWAYS', 'SQ_TEX_DEPTH_COMPARE_EQUAL', + 'SQ_TEX_DEPTH_COMPARE_GREATER', + 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', 'SQ_TEX_DEPTH_COMPARE_LESS', + 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', 'SQ_TEX_DEPTH_COMPARE_NEVER', + 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', 'SQ_TEX_MIP_FILTER', + 'SQ_TEX_MIP_FILTER_LINEAR', 'SQ_TEX_MIP_FILTER_NONE', + 'SQ_TEX_MIP_FILTER_POINT', 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', + 'SQ_TEX_MIRROR', 'SQ_TEX_MIRROR_ONCE_BORDER', + 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', + 'SQ_TEX_WRAP', 'SQ_TEX_XY_FILTER', + 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', 'SQ_TEX_XY_FILTER_ANISO_POINT', + 'SQ_TEX_XY_FILTER_BILINEAR', 'SQ_TEX_XY_FILTER_POINT', + 'SQ_TEX_Z_FILTER', 'SQ_TEX_Z_FILTER_LINEAR', + 'SQ_TEX_Z_FILTER_NONE', 'SQ_TEX_Z_FILTER_POINT', + 'SQ_THREAD_TRACE_CAPTURE_MODE', + 'SQ_THREAD_TRACE_CAPTURE_MODE_ALL', + 'SQ_THREAD_TRACE_CAPTURE_MODE_SELECT', + 'SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL', + 'SQ_THREAD_TRACE_INST_TYPE', + 'SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL', + 'SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS', + 'SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS', + 'SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX', + 'SQ_THREAD_TRACE_INST_TYPE_FATAL_HALT', + 'SQ_THREAD_TRACE_INST_TYPE_FLAT_RD', + 'SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY', + 'SQ_THREAD_TRACE_INST_TYPE_FLAT_WR', + 'SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY', + 'SQ_THREAD_TRACE_INST_TYPE_JUMP', 'SQ_THREAD_TRACE_INST_TYPE_LDS', + 'SQ_THREAD_TRACE_INST_TYPE_NEXT', + 'SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG', + 'SQ_THREAD_TRACE_INST_TYPE_PC', + 'SQ_THREAD_TRACE_INST_TYPE_SALU_32', + 'SQ_THREAD_TRACE_INST_TYPE_SALU_64', + 'SQ_THREAD_TRACE_INST_TYPE_SMEM_RD', + 'SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY', + 'SQ_THREAD_TRACE_INST_TYPE_SMEM_WR', + 'SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY', + 'SQ_THREAD_TRACE_INST_TYPE_VALU_32', + 'SQ_THREAD_TRACE_INST_TYPE_VALU_64', + 'SQ_THREAD_TRACE_INST_TYPE_VMEM_RD', + 'SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY', + 'SQ_THREAD_TRACE_INST_TYPE_VMEM_WR', + 'SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY', + 'SQ_THREAD_TRACE_ISSUE', 'SQ_THREAD_TRACE_ISSUE_IMMED', + 'SQ_THREAD_TRACE_ISSUE_INST', 'SQ_THREAD_TRACE_ISSUE_MASK', + 'SQ_THREAD_TRACE_ISSUE_MASK_ALL', + 'SQ_THREAD_TRACE_ISSUE_MASK_IMMED', + 'SQ_THREAD_TRACE_ISSUE_MASK_STALLED', + 'SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED', + 'SQ_THREAD_TRACE_ISSUE_NULL', 'SQ_THREAD_TRACE_ISSUE_STALL', + 'SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST', + 'SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX', + 'SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN', + 'SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC', + 'SQ_THREAD_TRACE_MISC_TOKEN_TIME', + 'SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET', + 'SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN', + 'SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END', + 'SQ_THREAD_TRACE_MISC_TOKEN_TYPE', 'SQ_THREAD_TRACE_MODE_OFF', + 'SQ_THREAD_TRACE_MODE_ON', 'SQ_THREAD_TRACE_MODE_SEL', + 'SQ_THREAD_TRACE_REG_OP', 'SQ_THREAD_TRACE_REG_OP_READ', + 'SQ_THREAD_TRACE_REG_OP_WRITE', 'SQ_THREAD_TRACE_REG_TYPE', + 'SQ_THREAD_TRACE_REG_TYPE_DISPATCH', + 'SQ_THREAD_TRACE_REG_TYPE_DRAW', 'SQ_THREAD_TRACE_REG_TYPE_EVENT', + 'SQ_THREAD_TRACE_REG_TYPE_GFXDEC', + 'SQ_THREAD_TRACE_REG_TYPE_MARKER', + 'SQ_THREAD_TRACE_REG_TYPE_OTHER', + 'SQ_THREAD_TRACE_REG_TYPE_SHDEC', + 'SQ_THREAD_TRACE_REG_TYPE_USERDATA', 'SQ_THREAD_TRACE_TIME_UNIT', + 'SQ_THREAD_TRACE_TOKEN_EVENT', 'SQ_THREAD_TRACE_TOKEN_EVENT_CS', + 'SQ_THREAD_TRACE_TOKEN_EVENT_GFX1', 'SQ_THREAD_TRACE_TOKEN_INST', + 'SQ_THREAD_TRACE_TOKEN_INST_PC', + 'SQ_THREAD_TRACE_TOKEN_INST_USERDATA', + 'SQ_THREAD_TRACE_TOKEN_ISSUE', 'SQ_THREAD_TRACE_TOKEN_MISC', + 'SQ_THREAD_TRACE_TOKEN_PERF', 'SQ_THREAD_TRACE_TOKEN_REG', + 'SQ_THREAD_TRACE_TOKEN_REG_CS', + 'SQ_THREAD_TRACE_TOKEN_REG_CSPRIV', + 'SQ_THREAD_TRACE_TOKEN_TIMESTAMP', 'SQ_THREAD_TRACE_TOKEN_TYPE', + 'SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC', + 'SQ_THREAD_TRACE_TOKEN_WAVE_END', + 'SQ_THREAD_TRACE_TOKEN_WAVE_START', 'SQ_THREAD_TRACE_VM_ID_MASK', + 'SQ_THREAD_TRACE_VM_ID_MASK_ALL', + 'SQ_THREAD_TRACE_VM_ID_MASK_SINGLE', + 'SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL', + 'SQ_THREAD_TRACE_WAVE_MASK', 'SQ_THREAD_TRACE_WAVE_MASK_ALL', + 'SQ_THREAD_TRACE_WAVE_MASK_NONE', + 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX', + 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE', + 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC', 'SQ_TRU', + 'SQ_TTMP0', 'SQ_TTMP1', 'SQ_TTMP10', 'SQ_TTMP11', 'SQ_TTMP12', + 'SQ_TTMP13', 'SQ_TTMP14', 'SQ_TTMP15', 'SQ_TTMP2', 'SQ_TTMP3', + 'SQ_TTMP4', 'SQ_TTMP5', 'SQ_TTMP6', 'SQ_TTMP7', 'SQ_TTMP8', + 'SQ_TTMP9', 'SQ_U', 'SQ_VCC_ALL', 'SQ_VCC_HI', 'SQ_VCC_LO', + 'SQ_VGPR0', 'SQ_V_ADD3_U32', 'SQ_V_ADDC_CO_U32', + 'SQ_V_ADD_CO_U32', 'SQ_V_ADD_F16', 'SQ_V_ADD_F32', 'SQ_V_ADD_F64', + 'SQ_V_ADD_I16', 'SQ_V_ADD_I32', 'SQ_V_ADD_LSHL_U32', + 'SQ_V_ADD_U16', 'SQ_V_ADD_U32', 'SQ_V_ALIGNBIT_B32', + 'SQ_V_ALIGNBYTE_B32', 'SQ_V_AND_B32', 'SQ_V_AND_OR_B32', + 'SQ_V_ASHRREV_I16', 'SQ_V_ASHRREV_I32', 'SQ_V_ASHRREV_I64', + 'SQ_V_BCNT_U32_B32', 'SQ_V_BFE_I32', 'SQ_V_BFE_U32', + 'SQ_V_BFI_B32', 'SQ_V_BFM_B32', 'SQ_V_BFREV_B32', 'SQ_V_CEIL_F16', + 'SQ_V_CEIL_F32', 'SQ_V_CEIL_F64', 'SQ_V_CLREXCP', + 'SQ_V_CMPX_CLASS_F16', 'SQ_V_CMPX_CLASS_F32', + 'SQ_V_CMPX_CLASS_F64', 'SQ_V_CMPX_EQ_F16', 'SQ_V_CMPX_EQ_F32', + 'SQ_V_CMPX_EQ_F64', 'SQ_V_CMPX_EQ_I16', 'SQ_V_CMPX_EQ_I32', + 'SQ_V_CMPX_EQ_I64', 'SQ_V_CMPX_EQ_U16', 'SQ_V_CMPX_EQ_U32', + 'SQ_V_CMPX_EQ_U64', 'SQ_V_CMPX_F_F16', 'SQ_V_CMPX_F_F32', + 'SQ_V_CMPX_F_F64', 'SQ_V_CMPX_F_I16', 'SQ_V_CMPX_F_I32', + 'SQ_V_CMPX_F_I64', 'SQ_V_CMPX_F_U16', 'SQ_V_CMPX_F_U32', + 'SQ_V_CMPX_F_U64', 'SQ_V_CMPX_GE_F16', 'SQ_V_CMPX_GE_F32', + 'SQ_V_CMPX_GE_F64', 'SQ_V_CMPX_GE_I16', 'SQ_V_CMPX_GE_I32', + 'SQ_V_CMPX_GE_I64', 'SQ_V_CMPX_GE_U16', 'SQ_V_CMPX_GE_U32', + 'SQ_V_CMPX_GE_U64', 'SQ_V_CMPX_GT_F16', 'SQ_V_CMPX_GT_F32', + 'SQ_V_CMPX_GT_F64', 'SQ_V_CMPX_GT_I16', 'SQ_V_CMPX_GT_I32', + 'SQ_V_CMPX_GT_I64', 'SQ_V_CMPX_GT_U16', 'SQ_V_CMPX_GT_U32', + 'SQ_V_CMPX_GT_U64', 'SQ_V_CMPX_LE_F16', 'SQ_V_CMPX_LE_F32', + 'SQ_V_CMPX_LE_F64', 'SQ_V_CMPX_LE_I16', 'SQ_V_CMPX_LE_I32', + 'SQ_V_CMPX_LE_I64', 'SQ_V_CMPX_LE_U16', 'SQ_V_CMPX_LE_U32', + 'SQ_V_CMPX_LE_U64', 'SQ_V_CMPX_LG_F16', 'SQ_V_CMPX_LG_F32', + 'SQ_V_CMPX_LG_F64', 'SQ_V_CMPX_LT_F16', 'SQ_V_CMPX_LT_F32', + 'SQ_V_CMPX_LT_F64', 'SQ_V_CMPX_LT_I16', 'SQ_V_CMPX_LT_I32', + 'SQ_V_CMPX_LT_I64', 'SQ_V_CMPX_LT_U16', 'SQ_V_CMPX_LT_U32', + 'SQ_V_CMPX_LT_U64', 'SQ_V_CMPX_NEQ_F16', 'SQ_V_CMPX_NEQ_F32', + 'SQ_V_CMPX_NEQ_F64', 'SQ_V_CMPX_NE_I16', 'SQ_V_CMPX_NE_I32', + 'SQ_V_CMPX_NE_I64', 'SQ_V_CMPX_NE_U16', 'SQ_V_CMPX_NE_U32', + 'SQ_V_CMPX_NE_U64', 'SQ_V_CMPX_NGE_F16', 'SQ_V_CMPX_NGE_F32', + 'SQ_V_CMPX_NGE_F64', 'SQ_V_CMPX_NGT_F16', 'SQ_V_CMPX_NGT_F32', + 'SQ_V_CMPX_NGT_F64', 'SQ_V_CMPX_NLE_F16', 'SQ_V_CMPX_NLE_F32', + 'SQ_V_CMPX_NLE_F64', 'SQ_V_CMPX_NLG_F16', 'SQ_V_CMPX_NLG_F32', + 'SQ_V_CMPX_NLG_F64', 'SQ_V_CMPX_NLT_F16', 'SQ_V_CMPX_NLT_F32', + 'SQ_V_CMPX_NLT_F64', 'SQ_V_CMPX_O_F16', 'SQ_V_CMPX_O_F32', + 'SQ_V_CMPX_O_F64', 'SQ_V_CMPX_TRU_F16', 'SQ_V_CMPX_TRU_F32', + 'SQ_V_CMPX_TRU_F64', 'SQ_V_CMPX_T_I16', 'SQ_V_CMPX_T_I32', + 'SQ_V_CMPX_T_I64', 'SQ_V_CMPX_T_U16', 'SQ_V_CMPX_T_U32', + 'SQ_V_CMPX_T_U64', 'SQ_V_CMPX_U_F16', 'SQ_V_CMPX_U_F32', + 'SQ_V_CMPX_U_F64', 'SQ_V_CMP_CLASS_F16', 'SQ_V_CMP_CLASS_F32', + 'SQ_V_CMP_CLASS_F64', 'SQ_V_CMP_EQ_F16', 'SQ_V_CMP_EQ_F32', + 'SQ_V_CMP_EQ_F64', 'SQ_V_CMP_EQ_I16', 'SQ_V_CMP_EQ_I32', + 'SQ_V_CMP_EQ_I64', 'SQ_V_CMP_EQ_U16', 'SQ_V_CMP_EQ_U32', + 'SQ_V_CMP_EQ_U64', 'SQ_V_CMP_F_F16', 'SQ_V_CMP_F_F32', + 'SQ_V_CMP_F_F64', 'SQ_V_CMP_F_I16', 'SQ_V_CMP_F_I32', + 'SQ_V_CMP_F_I64', 'SQ_V_CMP_F_U16', 'SQ_V_CMP_F_U32', + 'SQ_V_CMP_F_U64', 'SQ_V_CMP_GE_F16', 'SQ_V_CMP_GE_F32', + 'SQ_V_CMP_GE_F64', 'SQ_V_CMP_GE_I16', 'SQ_V_CMP_GE_I32', + 'SQ_V_CMP_GE_I64', 'SQ_V_CMP_GE_U16', 'SQ_V_CMP_GE_U32', + 'SQ_V_CMP_GE_U64', 'SQ_V_CMP_GT_F16', 'SQ_V_CMP_GT_F32', + 'SQ_V_CMP_GT_F64', 'SQ_V_CMP_GT_I16', 'SQ_V_CMP_GT_I32', + 'SQ_V_CMP_GT_I64', 'SQ_V_CMP_GT_U16', 'SQ_V_CMP_GT_U32', + 'SQ_V_CMP_GT_U64', 'SQ_V_CMP_LE_F16', 'SQ_V_CMP_LE_F32', + 'SQ_V_CMP_LE_F64', 'SQ_V_CMP_LE_I16', 'SQ_V_CMP_LE_I32', + 'SQ_V_CMP_LE_I64', 'SQ_V_CMP_LE_U16', 'SQ_V_CMP_LE_U32', + 'SQ_V_CMP_LE_U64', 'SQ_V_CMP_LG_F16', 'SQ_V_CMP_LG_F32', + 'SQ_V_CMP_LG_F64', 'SQ_V_CMP_LT_F16', 'SQ_V_CMP_LT_F32', + 'SQ_V_CMP_LT_F64', 'SQ_V_CMP_LT_I16', 'SQ_V_CMP_LT_I32', + 'SQ_V_CMP_LT_I64', 'SQ_V_CMP_LT_U16', 'SQ_V_CMP_LT_U32', + 'SQ_V_CMP_LT_U64', 'SQ_V_CMP_NEQ_F16', 'SQ_V_CMP_NEQ_F32', + 'SQ_V_CMP_NEQ_F64', 'SQ_V_CMP_NE_I16', 'SQ_V_CMP_NE_I32', + 'SQ_V_CMP_NE_I64', 'SQ_V_CMP_NE_U16', 'SQ_V_CMP_NE_U32', + 'SQ_V_CMP_NE_U64', 'SQ_V_CMP_NGE_F16', 'SQ_V_CMP_NGE_F32', + 'SQ_V_CMP_NGE_F64', 'SQ_V_CMP_NGT_F16', 'SQ_V_CMP_NGT_F32', + 'SQ_V_CMP_NGT_F64', 'SQ_V_CMP_NLE_F16', 'SQ_V_CMP_NLE_F32', + 'SQ_V_CMP_NLE_F64', 'SQ_V_CMP_NLG_F16', 'SQ_V_CMP_NLG_F32', + 'SQ_V_CMP_NLG_F64', 'SQ_V_CMP_NLT_F16', 'SQ_V_CMP_NLT_F32', + 'SQ_V_CMP_NLT_F64', 'SQ_V_CMP_O_F16', 'SQ_V_CMP_O_F32', + 'SQ_V_CMP_O_F64', 'SQ_V_CMP_TRU_F16', 'SQ_V_CMP_TRU_F32', + 'SQ_V_CMP_TRU_F64', 'SQ_V_CMP_T_I16', 'SQ_V_CMP_T_I32', + 'SQ_V_CMP_T_I64', 'SQ_V_CMP_T_U16', 'SQ_V_CMP_T_U32', + 'SQ_V_CMP_T_U64', 'SQ_V_CMP_U_F16', 'SQ_V_CMP_U_F32', + 'SQ_V_CMP_U_F64', 'SQ_V_CNDMASK_B32', 'SQ_V_COS_F16', + 'SQ_V_COS_F32', 'SQ_V_CUBEID_F32', 'SQ_V_CUBEMA_F32', + 'SQ_V_CUBESC_F32', 'SQ_V_CUBETC_F32', 'SQ_V_CVT_F16_F32', + 'SQ_V_CVT_F16_I16', 'SQ_V_CVT_F16_U16', 'SQ_V_CVT_F32_F16', + 'SQ_V_CVT_F32_F64', 'SQ_V_CVT_F32_I32', 'SQ_V_CVT_F32_U32', + 'SQ_V_CVT_F32_UBYTE0', 'SQ_V_CVT_F32_UBYTE1', + 'SQ_V_CVT_F32_UBYTE2', 'SQ_V_CVT_F32_UBYTE3', 'SQ_V_CVT_F64_F32', + 'SQ_V_CVT_F64_I32', 'SQ_V_CVT_F64_U32', 'SQ_V_CVT_FLR_I32_F32', + 'SQ_V_CVT_I16_F16', 'SQ_V_CVT_I32_F32', 'SQ_V_CVT_I32_F64', + 'SQ_V_CVT_NORM_I16_F16', 'SQ_V_CVT_NORM_U16_F16', + 'SQ_V_CVT_OFF_F32_I4', 'SQ_V_CVT_PKACCUM_U8_F32', + 'SQ_V_CVT_PKNORM_I16_F16', 'SQ_V_CVT_PKNORM_I16_F32', + 'SQ_V_CVT_PKNORM_U16_F16', 'SQ_V_CVT_PKNORM_U16_F32', + 'SQ_V_CVT_PKRTZ_F16_F32', 'SQ_V_CVT_PK_I16_I32', + 'SQ_V_CVT_PK_U16_U32', 'SQ_V_CVT_PK_U8_F32', + 'SQ_V_CVT_RPI_I32_F32', 'SQ_V_CVT_U16_F16', 'SQ_V_CVT_U32_F32', + 'SQ_V_CVT_U32_F64', 'SQ_V_DIV_FIXUP_F16', 'SQ_V_DIV_FIXUP_F32', + 'SQ_V_DIV_FIXUP_F64', 'SQ_V_DIV_FIXUP_LEGACY_F16', + 'SQ_V_DIV_FMAS_F32', 'SQ_V_DIV_FMAS_F64', 'SQ_V_DIV_SCALE_F32', + 'SQ_V_DIV_SCALE_F64', 'SQ_V_EXP_F16', 'SQ_V_EXP_F32', + 'SQ_V_EXP_LEGACY_F32', 'SQ_V_FFBH_I32', 'SQ_V_FFBH_U32', + 'SQ_V_FFBL_B32', 'SQ_V_FLOOR_F16', 'SQ_V_FLOOR_F32', + 'SQ_V_FLOOR_F64', 'SQ_V_FMA_F16', 'SQ_V_FMA_F32', 'SQ_V_FMA_F64', + 'SQ_V_FMA_LEGACY_F16', 'SQ_V_FRACT_F16', 'SQ_V_FRACT_F32', + 'SQ_V_FRACT_F64', 'SQ_V_FREXP_EXP_I16_F16', + 'SQ_V_FREXP_EXP_I32_F32', 'SQ_V_FREXP_EXP_I32_F64', + 'SQ_V_FREXP_MANT_F16', 'SQ_V_FREXP_MANT_F32', + 'SQ_V_FREXP_MANT_F64', 'SQ_V_INTERP_MOV_F32', + 'SQ_V_INTERP_P1LL_F16', 'SQ_V_INTERP_P1LV_F16', + 'SQ_V_INTERP_P1_F32', 'SQ_V_INTERP_P2_F16', 'SQ_V_INTERP_P2_F32', + 'SQ_V_INTERP_P2_LEGACY_F16', 'SQ_V_INTRP_COUNT', + 'SQ_V_INTRP_OFFSET', 'SQ_V_LDEXP_F16', 'SQ_V_LDEXP_F32', + 'SQ_V_LDEXP_F64', 'SQ_V_LERP_U8', 'SQ_V_LOG_F16', 'SQ_V_LOG_F32', + 'SQ_V_LOG_LEGACY_F32', 'SQ_V_LSHLREV_B16', 'SQ_V_LSHLREV_B32', + 'SQ_V_LSHLREV_B64', 'SQ_V_LSHL_ADD_U32', 'SQ_V_LSHL_OR_B32', + 'SQ_V_LSHRREV_B16', 'SQ_V_LSHRREV_B32', 'SQ_V_LSHRREV_B64', + 'SQ_V_MAC_F16', 'SQ_V_MAC_F32', 'SQ_V_MAC_LEGACY_F32', + 'SQ_V_MADAK_F16', 'SQ_V_MADAK_F32', 'SQ_V_MADMK_F16', + 'SQ_V_MADMK_F32', 'SQ_V_MAD_F16', 'SQ_V_MAD_F32', 'SQ_V_MAD_I16', + 'SQ_V_MAD_I32_I16', 'SQ_V_MAD_I32_I24', 'SQ_V_MAD_I64_I32', + 'SQ_V_MAD_LEGACY_F16', 'SQ_V_MAD_LEGACY_F32', + 'SQ_V_MAD_LEGACY_I16', 'SQ_V_MAD_LEGACY_U16', + 'SQ_V_MAD_MIXHI_F16', 'SQ_V_MAD_MIXLO_F16', 'SQ_V_MAD_MIX_F32', + 'SQ_V_MAD_U16', 'SQ_V_MAD_U32_U16', 'SQ_V_MAD_U32_U24', + 'SQ_V_MAD_U64_U32', 'SQ_V_MAX3_F16', 'SQ_V_MAX3_F32', + 'SQ_V_MAX3_I16', 'SQ_V_MAX3_I32', 'SQ_V_MAX3_U16', + 'SQ_V_MAX3_U32', 'SQ_V_MAX_F16', 'SQ_V_MAX_F32', 'SQ_V_MAX_F64', + 'SQ_V_MAX_I16', 'SQ_V_MAX_I32', 'SQ_V_MAX_U16', 'SQ_V_MAX_U32', + 'SQ_V_MBCNT_HI_U32_B32', 'SQ_V_MBCNT_LO_U32_B32', 'SQ_V_MED3_F16', + 'SQ_V_MED3_F32', 'SQ_V_MED3_I16', 'SQ_V_MED3_I32', + 'SQ_V_MED3_U16', 'SQ_V_MED3_U32', 'SQ_V_MIN3_F16', + 'SQ_V_MIN3_F32', 'SQ_V_MIN3_I16', 'SQ_V_MIN3_I32', + 'SQ_V_MIN3_U16', 'SQ_V_MIN3_U32', 'SQ_V_MIN_F16', 'SQ_V_MIN_F32', + 'SQ_V_MIN_F64', 'SQ_V_MIN_I16', 'SQ_V_MIN_I32', 'SQ_V_MIN_U16', + 'SQ_V_MIN_U32', 'SQ_V_MOV_B32', 'SQ_V_MOV_FED_B32', + 'SQ_V_MOV_PRSV_B32', 'SQ_V_MQSAD_PK_U16_U8', 'SQ_V_MQSAD_U32_U8', + 'SQ_V_MSAD_U8', 'SQ_V_MUL_F16', 'SQ_V_MUL_F32', 'SQ_V_MUL_F64', + 'SQ_V_MUL_HI_I32', 'SQ_V_MUL_HI_I32_I24', 'SQ_V_MUL_HI_U32', + 'SQ_V_MUL_HI_U32_U24', 'SQ_V_MUL_I32_I24', 'SQ_V_MUL_LEGACY_F32', + 'SQ_V_MUL_LO_U16', 'SQ_V_MUL_LO_U32', 'SQ_V_MUL_U32_U24', + 'SQ_V_NOP', 'SQ_V_NOT_B32', 'SQ_V_OP1_COUNT', 'SQ_V_OP1_OFFSET', + 'SQ_V_OP2_COUNT', 'SQ_V_OP2_OFFSET', 'SQ_V_OP3P_COUNT', + 'SQ_V_OP3P_OFFSET', 'SQ_V_OP3_2IN_COUNT', 'SQ_V_OP3_2IN_OFFSET', + 'SQ_V_OP3_3IN_COUNT', 'SQ_V_OP3_3IN_OFFSET', + 'SQ_V_OP3_INTRP_COUNT', 'SQ_V_OP3_INTRP_OFFSET', 'SQ_V_OPC_COUNT', + 'SQ_V_OPC_OFFSET', 'SQ_V_OR3_B32', 'SQ_V_OR_B32', + 'SQ_V_PACK_B32_F16', 'SQ_V_PERM_B32', 'SQ_V_PK_ADD_F16', + 'SQ_V_PK_ADD_I16', 'SQ_V_PK_ADD_U16', 'SQ_V_PK_ASHRREV_I16', + 'SQ_V_PK_LSHLREV_B16', 'SQ_V_PK_LSHRREV_B16', 'SQ_V_PK_MAD_F16', + 'SQ_V_PK_MAD_I16', 'SQ_V_PK_MAD_U16', 'SQ_V_PK_MAX_F16', + 'SQ_V_PK_MAX_I16', 'SQ_V_PK_MAX_U16', 'SQ_V_PK_MIN_F16', + 'SQ_V_PK_MIN_I16', 'SQ_V_PK_MIN_U16', 'SQ_V_PK_MUL_F16', + 'SQ_V_PK_MUL_LO_U16', 'SQ_V_PK_SUB_I16', 'SQ_V_PK_SUB_U16', + 'SQ_V_QSAD_PK_U16_U8', 'SQ_V_RCP_F16', 'SQ_V_RCP_F32', + 'SQ_V_RCP_F64', 'SQ_V_RCP_IFLAG_F32', 'SQ_V_READFIRSTLANE_B32', + 'SQ_V_READLANE_B32', 'SQ_V_READLANE_REGRD_B32', 'SQ_V_RNDNE_F16', + 'SQ_V_RNDNE_F32', 'SQ_V_RNDNE_F64', 'SQ_V_RSQ_F16', + 'SQ_V_RSQ_F32', 'SQ_V_RSQ_F64', 'SQ_V_SAD_HI_U8', 'SQ_V_SAD_U16', + 'SQ_V_SAD_U32', 'SQ_V_SAD_U8', 'SQ_V_SAT_PK_U8_I16', + 'SQ_V_SIN_F16', 'SQ_V_SIN_F32', 'SQ_V_SQRT_F16', 'SQ_V_SQRT_F32', + 'SQ_V_SQRT_F64', 'SQ_V_SUBBREV_CO_U32', 'SQ_V_SUBB_CO_U32', + 'SQ_V_SUBREV_CO_U32', 'SQ_V_SUBREV_F16', 'SQ_V_SUBREV_F32', + 'SQ_V_SUBREV_U16', 'SQ_V_SUBREV_U32', 'SQ_V_SUB_CO_U32', + 'SQ_V_SUB_F16', 'SQ_V_SUB_F32', 'SQ_V_SUB_I16', 'SQ_V_SUB_I32', + 'SQ_V_SUB_U16', 'SQ_V_SUB_U32', 'SQ_V_SWAP_B32', + 'SQ_V_TRIG_PREOP_F64', 'SQ_V_TRUNC_F16', 'SQ_V_TRUNC_F32', + 'SQ_V_TRUNC_F64', 'SQ_V_WRITELANE_B32', 'SQ_V_WRITELANE_IMM32', + 'SQ_V_XAD_U32', 'SQ_V_XOR_B32', 'SQ_WAITCNT_EXP_SHIFT', + 'SQ_WAITCNT_EXP_SIZE', 'SQ_WAITCNT_LGKM_SHIFT', + 'SQ_WAITCNT_LGKM_SIZE', 'SQ_WAITCNT_VM_SHIFT', + 'SQ_WAITCNT_VM_SIZE', 'SQ_WAVE_IB_ECC_CLEAN', + 'SQ_WAVE_IB_ECC_ERR_CONTINUE', 'SQ_WAVE_IB_ECC_ERR_HALT', + 'SQ_WAVE_IB_ECC_ST', 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', + 'SQ_WAVE_TYPE', 'SQ_WAVE_TYPE_CS', 'SQ_WAVE_TYPE_ES', + 'SQ_WAVE_TYPE_GS', 'SQ_WAVE_TYPE_HS', 'SQ_WAVE_TYPE_LS', + 'SQ_WAVE_TYPE_PS', 'SQ_WAVE_TYPE_PS0', 'SQ_WAVE_TYPE_PS1', + 'SQ_WAVE_TYPE_VS', 'SQ_XLATE_VOP3_TO_VINTRP_COUNT', + 'SQ_XLATE_VOP3_TO_VINTRP_OFFSET', 'SQ_XLATE_VOP3_TO_VOP1_COUNT', + 'SQ_XLATE_VOP3_TO_VOP1_OFFSET', 'SQ_XLATE_VOP3_TO_VOP2_COUNT', + 'SQ_XLATE_VOP3_TO_VOP2_OFFSET', 'SQ_XLATE_VOP3_TO_VOP3P_COUNT', + 'SQ_XLATE_VOP3_TO_VOP3P_OFFSET', 'SQ_XLATE_VOP3_TO_VOPC_COUNT', + 'SQ_XLATE_VOP3_TO_VOPC_OFFSET', 'SQ_XNACK_MASK_HI', + 'SQ_XNACK_MASK_LO', 'STATIC_SCREEN_SMU_INTR', + 'STATIC_SCREEN_SMU_INTR_NOOP', 'STENCIL_8', 'STENCIL_ADD_CLAMP', + 'STENCIL_ADD_WRAP', 'STENCIL_AND', 'STENCIL_INVALID', + 'STENCIL_INVERT', 'STENCIL_KEEP', 'STENCIL_NAND', 'STENCIL_NOR', + 'STENCIL_ONES', 'STENCIL_OR', 'STENCIL_REPLACE_OP', + 'STENCIL_REPLACE_TEST', 'STENCIL_SUB_CLAMP', 'STENCIL_SUB_WRAP', + 'STENCIL_XNOR', 'STENCIL_XOR', 'STENCIL_ZERO', + 'STREAM_0_SYNCHRONIZATION', + 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_10_SYNCHRONIZATION', + 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_11_SYNCHRONIZATION', + 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_12_SYNCHRONIZATION', + 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_13_SYNCHRONIZATION', + 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_14_SYNCHRONIZATION', + 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_15_SYNCHRONIZATION', + 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_1_SYNCHRONIZATION', + 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_2_SYNCHRONIZATION', + 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_3_SYNCHRONIZATION', + 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_4_SYNCHRONIZATION', + 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_5_SYNCHRONIZATION', + 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_6_SYNCHRONIZATION', + 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_7_SYNCHRONIZATION', + 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_8_SYNCHRONIZATION', + 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_9_SYNCHRONIZATION', + 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', + 'STRM_PERFMON_STATE_DISABLE_AND_RESET', + 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 'STRM_PERFMON_STATE_RESERVED_3', + 'STRM_PERFMON_STATE_START_COUNTING', + 'STRM_PERFMON_STATE_STOP_COUNTING', 'SU_PERFCNT_SEL', 'SWAP_ALT', + 'SWAP_ALT_REV', 'SWAP_STD', 'SWAP_STD_REV', 'SWIZZLE_MODE_ENUM', + 'SWIZZLE_TYPE_ENUM', 'SW_256B_D', 'SW_256B_R', 'SW_256B_S', + 'SW_4KB_D', 'SW_4KB_D_X', 'SW_4KB_R', 'SW_4KB_R_X', 'SW_4KB_S', + 'SW_4KB_S_X', 'SW_4KB_Z', 'SW_4KB_Z_X', 'SW_64KB_D', + 'SW_64KB_D_X', 'SW_64KB_R', 'SW_64KB_R_X', 'SW_64KB_S', + 'SW_64KB_S_X', 'SW_64KB_Z', 'SW_64KB_Z_X', 'SW_D', 'SW_L', + 'SW_LINEAR', 'SW_R', 'SW_RESERVED_12', 'SW_RESERVED_13', + 'SW_RESERVED_14', 'SW_RESERVED_15', 'SW_RESERVED_16', + 'SW_RESERVED_17', 'SW_RESERVED_18', 'SW_RESERVED_19', 'SW_S', + 'SW_VAR_D', 'SW_VAR_D_X', 'SW_VAR_R', 'SW_VAR_R_X', 'SW_VAR_S', + 'SW_VAR_S_X', 'SW_VAR_Z', 'SW_VAR_Z_X', 'SW_Z', 'SX_BLEND_OPT', + 'SX_CB_RAT_ACK_REQUEST', 'SX_DOWNCONVERT_FORMAT', + 'SX_OPT_COMB_FCN', 'SX_PERFCOUNTER_VALS', 'SX_PERF_SEL_CLOCK', + 'SX_PERF_SEL_COL_BUSY', 'SX_PERF_SEL_DB0_A2M_DISCARD_QUADS', + 'SX_PERF_SEL_DB0_HALF_QUADS', 'SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT0_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS', + 'SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT1_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS', + 'SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT2_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS', + 'SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT3_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS', + 'SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT4_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS', + 'SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT5_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS', + 'SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT6_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS', + 'SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT7_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB0_PIXELS', + 'SX_PERF_SEL_DB0_PIXEL_IDLE', 'SX_PERF_SEL_DB0_PIXEL_STALL', + 'SX_PERF_SEL_DB0_PRED_PIXELS', + 'SX_PERF_SEL_DB1_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB1_HALF_QUADS', + 'SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT0_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS', + 'SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT1_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS', + 'SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT2_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS', + 'SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT3_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS', + 'SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT4_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS', + 'SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT5_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS', + 'SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT6_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS', + 'SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT7_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB1_PIXELS', + 'SX_PERF_SEL_DB1_PIXEL_IDLE', 'SX_PERF_SEL_DB1_PIXEL_STALL', + 'SX_PERF_SEL_DB1_PRED_PIXELS', + 'SX_PERF_SEL_DB2_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB2_HALF_QUADS', + 'SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT0_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS', + 'SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT1_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS', + 'SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT2_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS', + 'SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT3_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS', + 'SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT4_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS', + 'SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT5_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS', + 'SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT6_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS', + 'SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT7_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB2_PIXELS', + 'SX_PERF_SEL_DB2_PIXEL_IDLE', 'SX_PERF_SEL_DB2_PIXEL_STALL', + 'SX_PERF_SEL_DB2_PRED_PIXELS', + 'SX_PERF_SEL_DB3_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB3_HALF_QUADS', + 'SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT0_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS', + 'SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT1_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS', + 'SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT2_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS', + 'SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT3_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS', + 'SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT4_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS', + 'SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT5_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS', + 'SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT6_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS', + 'SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT7_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB3_PIXELS', + 'SX_PERF_SEL_DB3_PIXEL_IDLE', 'SX_PERF_SEL_DB3_PIXEL_STALL', + 'SX_PERF_SEL_DB3_PRED_PIXELS', 'SX_PERF_SEL_GATE_EN1', + 'SX_PERF_SEL_GATE_EN2', 'SX_PERF_SEL_GATE_EN3', + 'SX_PERF_SEL_GATE_EN4', 'SX_PERF_SEL_PA_IDLE_CYCLES', + 'SX_PERF_SEL_PA_POS', 'SX_PERF_SEL_PA_REQ', + 'SX_PERF_SEL_POS_BUSY', 'SX_PERF_SEL_SH_COLOR_STALL', + 'SX_PERF_SEL_SH_COLOR_STARVE', 'SX_PERF_SEL_SH_POS_STALL', + 'SX_PERF_SEL_SH_POS_STARVE', 'SX_RT_EXPORT_10_11_11', + 'SX_RT_EXPORT_16_16_AR', 'SX_RT_EXPORT_16_16_GR', + 'SX_RT_EXPORT_1_5_5_5', 'SX_RT_EXPORT_2_10_10_10', + 'SX_RT_EXPORT_32_A', 'SX_RT_EXPORT_32_R', 'SX_RT_EXPORT_4_4_4_4', + 'SX_RT_EXPORT_5_6_5', 'SX_RT_EXPORT_8_8_8_8', + 'SX_RT_EXPORT_NO_CONVERSION', 'SYMCLK_FE_FORCE_EN', + 'SYMCLK_FE_FORCE_EN_DISABLE', 'SYMCLK_FE_FORCE_EN_ENABLE', + 'SYMCLK_FE_FORCE_SRC', 'SYMCLK_FE_FORCE_SRC_UNIPHYA', + 'SYMCLK_FE_FORCE_SRC_UNIPHYB', 'SYMCLK_FE_FORCE_SRC_UNIPHYC', + 'SYMCLK_FE_FORCE_SRC_UNIPHYD', 'SYMCLK_FE_FORCE_SRC_UNIPHYE', + 'SYMCLK_FE_FORCE_SRC_UNIPHYF', 'SYMCLK_FE_FORCE_SRC_UNIPHYG', + 'SYNC_DURATION_128', 'SYNC_DURATION_16', 'SYNC_DURATION_32', + 'SYNC_DURATION_64', 'SYNC_RESET_SEL2_VBLANK', + 'SYNC_RESET_SEL2_VSYNC', 'SampleSplit', 'SampleSplitBytes', + 'ScMap', 'ScXsel', 'ScYsel', 'SeEnable', 'SeMap', 'SePairMap', + 'SePairXsel', 'SePairYsel', 'SeXsel', 'SeYsel', + 'ShaderEngineTileSize', 'SourceFormat', 'StencilFormat', + 'StencilOp', 'SurfaceArray', 'SurfaceEndian', 'SurfaceFormat', + 'SurfaceNumber', 'SurfaceSwap', 'SurfaceTiling', + 'TA_PERFCOUNT_SEL', 'TA_PERF_SEL_NULL', 'TA_PERF_SEL_RESERVED_28', + 'TA_PERF_SEL_RESERVED_29', 'TA_PERF_SEL_RESERVED_41', + 'TA_PERF_SEL_RESERVED_42', 'TA_PERF_SEL_RESERVED_43', + 'TA_PERF_SEL_addr_stalled_by_tc_cycles', + 'TA_PERF_SEL_addr_stalled_by_td_cycles', + 'TA_PERF_SEL_addresser_busy', 'TA_PERF_SEL_addresser_fifo_busy', + 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', + 'TA_PERF_SEL_addresser_stalled_cycles', + 'TA_PERF_SEL_aligner_busy', 'TA_PERF_SEL_aligner_cycles', + 'TA_PERF_SEL_aniso_10_cycle_quads', + 'TA_PERF_SEL_aniso_12_cycle_quads', + 'TA_PERF_SEL_aniso_14_cycle_quads', + 'TA_PERF_SEL_aniso_16_cycle_quads', + 'TA_PERF_SEL_aniso_1_cycle_quads', + 'TA_PERF_SEL_aniso_2_cycle_quads', + 'TA_PERF_SEL_aniso_4_cycle_quads', + 'TA_PERF_SEL_aniso_6_cycle_quads', + 'TA_PERF_SEL_aniso_8_cycle_quads', + 'TA_PERF_SEL_aniso_gt1_cycle_quads', + 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', + 'TA_PERF_SEL_aniso_stalled_cycles', + 'TA_PERF_SEL_bilin_point_1_cycle_pixels', + 'TA_PERF_SEL_buffer_atomic_wavefronts', + 'TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles', + 'TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles', + 'TA_PERF_SEL_buffer_coalescable_wavefronts', + 'TA_PERF_SEL_buffer_coalesced_read_cycles', + 'TA_PERF_SEL_buffer_coalesced_write_cycles', + 'TA_PERF_SEL_buffer_read_wavefronts', + 'TA_PERF_SEL_buffer_total_cycles', + 'TA_PERF_SEL_buffer_wavefronts', + 'TA_PERF_SEL_buffer_write_wavefronts', + 'TA_PERF_SEL_color_1_cycle_pixels', + 'TA_PERF_SEL_color_2_cycle_pixels', + 'TA_PERF_SEL_color_3_cycle_pixels', + 'TA_PERF_SEL_color_4_cycle_pixels', + 'TA_PERF_SEL_data_stalled_by_tc_cycles', + 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', + 'TA_PERF_SEL_deriv_stalled_cycles', + 'TA_PERF_SEL_first_xnack_on_phase0', + 'TA_PERF_SEL_first_xnack_on_phase1', + 'TA_PERF_SEL_first_xnack_on_phase2', + 'TA_PERF_SEL_first_xnack_on_phase3', + 'TA_PERF_SEL_flat_atomic_wavefronts', + 'TA_PERF_SEL_flat_coalesceable_wavefronts', + 'TA_PERF_SEL_flat_read_wavefronts', 'TA_PERF_SEL_flat_wavefronts', + 'TA_PERF_SEL_flat_write_wavefronts', 'TA_PERF_SEL_gradient_busy', + 'TA_PERF_SEL_gradient_cycles', 'TA_PERF_SEL_gradient_fifo_busy', + 'TA_PERF_SEL_image_atomic_wavefronts', + 'TA_PERF_SEL_image_read_wavefronts', + 'TA_PERF_SEL_image_total_cycles', 'TA_PERF_SEL_image_wavefronts', + 'TA_PERF_SEL_image_write_wavefronts', + 'TA_PERF_SEL_local_cg_dyn_sclk_grp0_en', + 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_en', + 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en', + 'TA_PERF_SEL_local_cg_dyn_sclk_grp4_en', + 'TA_PERF_SEL_local_cg_dyn_sclk_grp5_en', 'TA_PERF_SEL_lod_busy', + 'TA_PERF_SEL_lod_fifo_busy', 'TA_PERF_SEL_mip_1_cycle_pixels', + 'TA_PERF_SEL_mip_2_cycle_pixels', + 'TA_PERF_SEL_mipmap_invalid_samples', + 'TA_PERF_SEL_mipmap_lod_0_samples', + 'TA_PERF_SEL_mipmap_lod_10_samples', + 'TA_PERF_SEL_mipmap_lod_11_samples', + 'TA_PERF_SEL_mipmap_lod_12_samples', + 'TA_PERF_SEL_mipmap_lod_13_samples', + 'TA_PERF_SEL_mipmap_lod_14_samples', + 'TA_PERF_SEL_mipmap_lod_1_samples', + 'TA_PERF_SEL_mipmap_lod_2_samples', + 'TA_PERF_SEL_mipmap_lod_3_samples', + 'TA_PERF_SEL_mipmap_lod_4_samples', + 'TA_PERF_SEL_mipmap_lod_5_samples', + 'TA_PERF_SEL_mipmap_lod_6_samples', + 'TA_PERF_SEL_mipmap_lod_7_samples', + 'TA_PERF_SEL_mipmap_lod_8_samples', + 'TA_PERF_SEL_mipmap_lod_9_samples', 'TA_PERF_SEL_reg_sclk_vld', + 'TA_PERF_SEL_sh_fifo_addr_busy', + 'TA_PERF_SEL_sh_fifo_addr_cycles', + 'TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles', + 'TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles', + 'TA_PERF_SEL_sh_fifo_busy', 'TA_PERF_SEL_sh_fifo_cmd_busy', + 'TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles', + 'TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles', + 'TA_PERF_SEL_sh_fifo_data_busy', + 'TA_PERF_SEL_sh_fifo_data_cycles', + 'TA_PERF_SEL_sh_fifo_data_sfifo_busy', + 'TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles', + 'TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles', + 'TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles', + 'TA_PERF_SEL_sh_fifo_data_tfifo_busy', + 'TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles', + 'TA_PERF_SEL_sp_ta_addr_cycles', 'TA_PERF_SEL_sp_ta_data_cycles', + 'TA_PERF_SEL_sq_ta_cmd_cycles', 'TA_PERF_SEL_ta_busy', + 'TA_PERF_SEL_ta_fa_data_state_cycles', + 'TA_PERF_SEL_total_wavefronts', 'TA_PERF_SEL_vol_1_cycle_pixels', + 'TA_PERF_SEL_vol_2_cycle_pixels', 'TA_PERF_SEL_walker_cycles', + 'TA_PERF_SEL_write_path_busy', + 'TA_PERF_SEL_write_path_input_cycles', + 'TA_PERF_SEL_write_path_output_cycles', + 'TA_PERF_SEL_xnack_on_phase0', 'TA_PERF_SEL_xnack_on_phase1', + 'TA_PERF_SEL_xnack_on_phase2', 'TA_PERF_SEL_xnack_on_phase3', + 'TA_TC_ADDR_MODES', 'TA_TC_ADDR_MODE_BORDER_COLOR', + 'TA_TC_ADDR_MODE_COMP0', 'TA_TC_ADDR_MODE_COMP1', + 'TA_TC_ADDR_MODE_COMP2', 'TA_TC_ADDR_MODE_COMP3', + 'TA_TC_ADDR_MODE_DEFAULT', 'TA_TC_ADDR_MODE_UNALIGNED', + 'TCA_PERF_SEL', 'TCA_PERF_SEL_BUSY', + 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0', + 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1', + 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2', + 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3', + 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4', + 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5', + 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6', + 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7', + 'TCA_PERF_SEL_CROSSBAR_STALL_TCC0', + 'TCA_PERF_SEL_CROSSBAR_STALL_TCC1', + 'TCA_PERF_SEL_CROSSBAR_STALL_TCC2', + 'TCA_PERF_SEL_CROSSBAR_STALL_TCC3', + 'TCA_PERF_SEL_CROSSBAR_STALL_TCC4', + 'TCA_PERF_SEL_CROSSBAR_STALL_TCC5', + 'TCA_PERF_SEL_CROSSBAR_STALL_TCC6', + 'TCA_PERF_SEL_CROSSBAR_STALL_TCC7', 'TCA_PERF_SEL_CYCLE', + 'TCA_PERF_SEL_FORCED_HOLE_TCC0', 'TCA_PERF_SEL_FORCED_HOLE_TCC1', + 'TCA_PERF_SEL_FORCED_HOLE_TCC2', 'TCA_PERF_SEL_FORCED_HOLE_TCC3', + 'TCA_PERF_SEL_FORCED_HOLE_TCC4', 'TCA_PERF_SEL_FORCED_HOLE_TCC5', + 'TCA_PERF_SEL_FORCED_HOLE_TCC6', 'TCA_PERF_SEL_FORCED_HOLE_TCC7', + 'TCA_PERF_SEL_NONE', 'TCA_PERF_SEL_REQ_TCC0', + 'TCA_PERF_SEL_REQ_TCC1', 'TCA_PERF_SEL_REQ_TCC2', + 'TCA_PERF_SEL_REQ_TCC3', 'TCA_PERF_SEL_REQ_TCC4', + 'TCA_PERF_SEL_REQ_TCC5', 'TCA_PERF_SEL_REQ_TCC6', + 'TCA_PERF_SEL_REQ_TCC7', 'TCC_CACHE_POLICIES', + 'TCC_CACHE_POLICY_LRU', 'TCC_CACHE_POLICY_STREAM', 'TCC_PERF_SEL', + 'TCC_PERF_SEL_ALL_TC_OP_INV_EVICT', + 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE', + 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH', + 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', + 'TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK', 'TCC_PERF_SEL_ATOMIC', + 'TCC_PERF_SEL_BUBBLE', 'TCC_PERF_SEL_BUSY', + 'TCC_PERF_SEL_CC_PHYSICAL_REQ', 'TCC_PERF_SEL_CLIENT0_REQ', + 'TCC_PERF_SEL_CLIENT100_REQ', 'TCC_PERF_SEL_CLIENT101_REQ', + 'TCC_PERF_SEL_CLIENT102_REQ', 'TCC_PERF_SEL_CLIENT103_REQ', + 'TCC_PERF_SEL_CLIENT104_REQ', 'TCC_PERF_SEL_CLIENT105_REQ', + 'TCC_PERF_SEL_CLIENT106_REQ', 'TCC_PERF_SEL_CLIENT107_REQ', + 'TCC_PERF_SEL_CLIENT108_REQ', 'TCC_PERF_SEL_CLIENT109_REQ', + 'TCC_PERF_SEL_CLIENT10_REQ', 'TCC_PERF_SEL_CLIENT110_REQ', + 'TCC_PERF_SEL_CLIENT111_REQ', 'TCC_PERF_SEL_CLIENT112_REQ', + 'TCC_PERF_SEL_CLIENT113_REQ', 'TCC_PERF_SEL_CLIENT114_REQ', + 'TCC_PERF_SEL_CLIENT115_REQ', 'TCC_PERF_SEL_CLIENT116_REQ', + 'TCC_PERF_SEL_CLIENT117_REQ', 'TCC_PERF_SEL_CLIENT118_REQ', + 'TCC_PERF_SEL_CLIENT119_REQ', 'TCC_PERF_SEL_CLIENT11_REQ', + 'TCC_PERF_SEL_CLIENT120_REQ', 'TCC_PERF_SEL_CLIENT121_REQ', + 'TCC_PERF_SEL_CLIENT122_REQ', 'TCC_PERF_SEL_CLIENT123_REQ', + 'TCC_PERF_SEL_CLIENT124_REQ', 'TCC_PERF_SEL_CLIENT125_REQ', + 'TCC_PERF_SEL_CLIENT126_REQ', 'TCC_PERF_SEL_CLIENT127_REQ', + 'TCC_PERF_SEL_CLIENT12_REQ', 'TCC_PERF_SEL_CLIENT13_REQ', + 'TCC_PERF_SEL_CLIENT14_REQ', 'TCC_PERF_SEL_CLIENT15_REQ', + 'TCC_PERF_SEL_CLIENT16_REQ', 'TCC_PERF_SEL_CLIENT17_REQ', + 'TCC_PERF_SEL_CLIENT18_REQ', 'TCC_PERF_SEL_CLIENT19_REQ', + 'TCC_PERF_SEL_CLIENT1_REQ', 'TCC_PERF_SEL_CLIENT20_REQ', + 'TCC_PERF_SEL_CLIENT21_REQ', 'TCC_PERF_SEL_CLIENT22_REQ', + 'TCC_PERF_SEL_CLIENT23_REQ', 'TCC_PERF_SEL_CLIENT24_REQ', + 'TCC_PERF_SEL_CLIENT25_REQ', 'TCC_PERF_SEL_CLIENT26_REQ', + 'TCC_PERF_SEL_CLIENT27_REQ', 'TCC_PERF_SEL_CLIENT28_REQ', + 'TCC_PERF_SEL_CLIENT29_REQ', 'TCC_PERF_SEL_CLIENT2_REQ', + 'TCC_PERF_SEL_CLIENT30_REQ', 'TCC_PERF_SEL_CLIENT31_REQ', + 'TCC_PERF_SEL_CLIENT32_REQ', 'TCC_PERF_SEL_CLIENT33_REQ', + 'TCC_PERF_SEL_CLIENT34_REQ', 'TCC_PERF_SEL_CLIENT35_REQ', + 'TCC_PERF_SEL_CLIENT36_REQ', 'TCC_PERF_SEL_CLIENT37_REQ', + 'TCC_PERF_SEL_CLIENT38_REQ', 'TCC_PERF_SEL_CLIENT39_REQ', + 'TCC_PERF_SEL_CLIENT3_REQ', 'TCC_PERF_SEL_CLIENT40_REQ', + 'TCC_PERF_SEL_CLIENT41_REQ', 'TCC_PERF_SEL_CLIENT42_REQ', + 'TCC_PERF_SEL_CLIENT43_REQ', 'TCC_PERF_SEL_CLIENT44_REQ', + 'TCC_PERF_SEL_CLIENT45_REQ', 'TCC_PERF_SEL_CLIENT46_REQ', + 'TCC_PERF_SEL_CLIENT47_REQ', 'TCC_PERF_SEL_CLIENT48_REQ', + 'TCC_PERF_SEL_CLIENT49_REQ', 'TCC_PERF_SEL_CLIENT4_REQ', + 'TCC_PERF_SEL_CLIENT50_REQ', 'TCC_PERF_SEL_CLIENT51_REQ', + 'TCC_PERF_SEL_CLIENT52_REQ', 'TCC_PERF_SEL_CLIENT53_REQ', + 'TCC_PERF_SEL_CLIENT54_REQ', 'TCC_PERF_SEL_CLIENT55_REQ', + 'TCC_PERF_SEL_CLIENT56_REQ', 'TCC_PERF_SEL_CLIENT57_REQ', + 'TCC_PERF_SEL_CLIENT58_REQ', 'TCC_PERF_SEL_CLIENT59_REQ', + 'TCC_PERF_SEL_CLIENT5_REQ', 'TCC_PERF_SEL_CLIENT60_REQ', + 'TCC_PERF_SEL_CLIENT61_REQ', 'TCC_PERF_SEL_CLIENT62_REQ', + 'TCC_PERF_SEL_CLIENT63_REQ', 'TCC_PERF_SEL_CLIENT64_REQ', + 'TCC_PERF_SEL_CLIENT65_REQ', 'TCC_PERF_SEL_CLIENT66_REQ', + 'TCC_PERF_SEL_CLIENT67_REQ', 'TCC_PERF_SEL_CLIENT68_REQ', + 'TCC_PERF_SEL_CLIENT69_REQ', 'TCC_PERF_SEL_CLIENT6_REQ', + 'TCC_PERF_SEL_CLIENT70_REQ', 'TCC_PERF_SEL_CLIENT71_REQ', + 'TCC_PERF_SEL_CLIENT72_REQ', 'TCC_PERF_SEL_CLIENT73_REQ', + 'TCC_PERF_SEL_CLIENT74_REQ', 'TCC_PERF_SEL_CLIENT75_REQ', + 'TCC_PERF_SEL_CLIENT76_REQ', 'TCC_PERF_SEL_CLIENT77_REQ', + 'TCC_PERF_SEL_CLIENT78_REQ', 'TCC_PERF_SEL_CLIENT79_REQ', + 'TCC_PERF_SEL_CLIENT7_REQ', 'TCC_PERF_SEL_CLIENT80_REQ', + 'TCC_PERF_SEL_CLIENT81_REQ', 'TCC_PERF_SEL_CLIENT82_REQ', + 'TCC_PERF_SEL_CLIENT83_REQ', 'TCC_PERF_SEL_CLIENT84_REQ', + 'TCC_PERF_SEL_CLIENT85_REQ', 'TCC_PERF_SEL_CLIENT86_REQ', + 'TCC_PERF_SEL_CLIENT87_REQ', 'TCC_PERF_SEL_CLIENT88_REQ', + 'TCC_PERF_SEL_CLIENT89_REQ', 'TCC_PERF_SEL_CLIENT8_REQ', + 'TCC_PERF_SEL_CLIENT90_REQ', 'TCC_PERF_SEL_CLIENT91_REQ', + 'TCC_PERF_SEL_CLIENT92_REQ', 'TCC_PERF_SEL_CLIENT93_REQ', + 'TCC_PERF_SEL_CLIENT94_REQ', 'TCC_PERF_SEL_CLIENT95_REQ', + 'TCC_PERF_SEL_CLIENT96_REQ', 'TCC_PERF_SEL_CLIENT97_REQ', + 'TCC_PERF_SEL_CLIENT98_REQ', 'TCC_PERF_SEL_CLIENT99_REQ', + 'TCC_PERF_SEL_CLIENT9_REQ', 'TCC_PERF_SEL_COMPRESSED_0_REQ', + 'TCC_PERF_SEL_COMPRESSED_REQ', 'TCC_PERF_SEL_CYCLE', + 'TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT', 'TCC_PERF_SEL_EA_ATOMIC', + 'TCC_PERF_SEL_EA_ATOMIC_LEVEL', 'TCC_PERF_SEL_EA_RDREQ', + 'TCC_PERF_SEL_EA_RDREQ_32B', 'TCC_PERF_SEL_EA_RDREQ_CREDIT_STALL', + 'TCC_PERF_SEL_EA_RDREQ_LEVEL', + 'TCC_PERF_SEL_EA_RD_COMPRESSED_32B', 'TCC_PERF_SEL_EA_RD_MDC_32B', + 'TCC_PERF_SEL_EA_RD_UNCACHED_32B', 'TCC_PERF_SEL_EA_WRREQ', + 'TCC_PERF_SEL_EA_WRREQ_64B', 'TCC_PERF_SEL_EA_WRREQ_CREDIT_STALL', + 'TCC_PERF_SEL_EA_WRREQ_LEVEL', + 'TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND', + 'TCC_PERF_SEL_EA_WRREQ_STALL', 'TCC_PERF_SEL_EA_WR_UNCACHED_32B', + 'TCC_PERF_SEL_EXE_REQ', 'TCC_PERF_SEL_FULLY_WRITTEN_HIT', + 'TCC_PERF_SEL_HIT', 'TCC_PERF_SEL_HOLE_FIFO_FULL', + 'TCC_PERF_SEL_HOLE_LEVEL', 'TCC_PERF_SEL_IB_MDC_STALL', + 'TCC_PERF_SEL_IB_REQ', 'TCC_PERF_SEL_IB_STALL', + 'TCC_PERF_SEL_IB_TAG_STALL', 'TCC_PERF_SEL_LATENCY_FIFO_FULL', + 'TCC_PERF_SEL_MDC_LEVEL', 'TCC_PERF_SEL_MDC_REQ', + 'TCC_PERF_SEL_MDC_SECTOR_HIT', 'TCC_PERF_SEL_MDC_SECTOR_MISS', + 'TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', + 'TCC_PERF_SEL_MDC_TAG_HIT', + 'TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', + 'TCC_PERF_SEL_MDC_TAG_STALL', + 'TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', + 'TCC_PERF_SEL_METADATA_REQ', 'TCC_PERF_SEL_MISS', + 'TCC_PERF_SEL_NC_VIRTUAL_REQ', 'TCC_PERF_SEL_NONE', + 'TCC_PERF_SEL_NORMAL_EVICT', 'TCC_PERF_SEL_NORMAL_WRITEBACK', + 'TCC_PERF_SEL_PROBE', 'TCC_PERF_SEL_PROBE_ALL', + 'TCC_PERF_SEL_PROBE_EVICT', 'TCC_PERF_SEL_PROBE_FILTER_DISABLED', + 'TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', + 'TCC_PERF_SEL_READ', 'TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE', + 'TCC_PERF_SEL_READ_RETURN_TIMEOUT', 'TCC_PERF_SEL_REQ', + 'TCC_PERF_SEL_RETURN_ACK', 'TCC_PERF_SEL_RETURN_ACK_HOLE', + 'TCC_PERF_SEL_RETURN_DATA', 'TCC_PERF_SEL_RETURN_HOLE', + 'TCC_PERF_SEL_SECTOR_HIT', 'TCC_PERF_SEL_SRC_FIFO_FULL', + 'TCC_PERF_SEL_STREAMING_REQ', + 'TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', + 'TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', + 'TCC_PERF_SEL_TAG_PROBE_FILTER_STALL', + 'TCC_PERF_SEL_TAG_PROBE_STALL', 'TCC_PERF_SEL_TAG_STALL', + 'TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', + 'TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', + 'TCC_PERF_SEL_TCA_LEVEL', 'TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE', + 'TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT', + 'TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH', + 'TCC_PERF_SEL_TC_OP_INVL2_NC_START', + 'TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE', + 'TCC_PERF_SEL_TC_OP_WBINVL2_EVICT', + 'TCC_PERF_SEL_TC_OP_WBINVL2_FINISH', + 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE', + 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT', + 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH', + 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_START', + 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK', + 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE', + 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT', + 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH', + 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_START', + 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK', + 'TCC_PERF_SEL_TC_OP_WBINVL2_START', + 'TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK', + 'TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE', + 'TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT', + 'TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH', + 'TCC_PERF_SEL_TC_OP_WBL2_NC_START', + 'TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK', + 'TCC_PERF_SEL_TC_OP_WBL2_WC_CYCLE', + 'TCC_PERF_SEL_TC_OP_WBL2_WC_EVICT', + 'TCC_PERF_SEL_TC_OP_WBL2_WC_FINISH', + 'TCC_PERF_SEL_TC_OP_WBL2_WC_START', + 'TCC_PERF_SEL_TC_OP_WBL2_WC_WRITEBACK', + 'TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', + 'TCC_PERF_SEL_UC_VIRTUAL_REQ', 'TCC_PERF_SEL_WRITE', + 'TCC_PERF_SEL_WRITEBACK', 'TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT', + 'TCP_CACHE_POLICIES', 'TCP_CACHE_POLICY_HIT_EVICT', + 'TCP_CACHE_POLICY_HIT_LRU', 'TCP_CACHE_POLICY_MISS_EVICT', + 'TCP_CACHE_POLICY_MISS_LRU', 'TCP_CACHE_STORE_POLICIES', + 'TCP_CACHE_STORE_POLICY_WT_EVICT', + 'TCP_CACHE_STORE_POLICY_WT_LRU', 'TCP_DSM_DATA_SEL', + 'TCP_DSM_DISABLE', 'TCP_DSM_INJECT_SEL', 'TCP_DSM_INJECT_SEL0', + 'TCP_DSM_INJECT_SEL1', 'TCP_DSM_INJECT_SEL2', + 'TCP_DSM_INJECT_SEL3', 'TCP_DSM_SEL0', 'TCP_DSM_SEL1', + 'TCP_DSM_SEL_BOTH', 'TCP_DSM_SINGLE_WRITE', + 'TCP_DSM_SINGLE_WRITE_DIS', 'TCP_DSM_SINGLE_WRITE_EN', + 'TCP_PERFCOUNT_SELECT', 'TCP_PERF_SEL_ALLOC_STALL_CYCLES', + 'TCP_PERF_SEL_ARR_1D_THICK', 'TCP_PERF_SEL_ARR_1D_THIN1', + 'TCP_PERF_SEL_ARR_2D_THICK', 'TCP_PERF_SEL_ARR_2D_THIN1', + 'TCP_PERF_SEL_ARR_2D_XTHICK', 'TCP_PERF_SEL_ARR_3D_THICK', + 'TCP_PERF_SEL_ARR_3D_THIN1', 'TCP_PERF_SEL_ARR_3D_XTHICK', + 'TCP_PERF_SEL_ARR_LINEAR_ALIGNED', + 'TCP_PERF_SEL_ARR_LINEAR_GENERAL', + 'TCP_PERF_SEL_ARR_PRT_2D_THICK', 'TCP_PERF_SEL_ARR_PRT_2D_THIN1', + 'TCP_PERF_SEL_ARR_PRT_3D_THICK', 'TCP_PERF_SEL_ARR_PRT_3D_THIN1', + 'TCP_PERF_SEL_ARR_PRT_THICK', 'TCP_PERF_SEL_ARR_PRT_THIN1', + 'TCP_PERF_SEL_ATC', + 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES', + 'TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32', + 'TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64', + 'TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32', + 'TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64', + 'TCP_PERF_SEL_BUF_READ_FMT_16', 'TCP_PERF_SEL_BUF_READ_FMT_32', + 'TCP_PERF_SEL_BUF_READ_FMT_8', 'TCP_PERF_SEL_BUF_WRITE_FMT_16', + 'TCP_PERF_SEL_BUF_WRITE_FMT_32', 'TCP_PERF_SEL_BUF_WRITE_FMT_8', + 'TCP_PERF_SEL_CORE_REG_SCLK_VLD', + 'TCP_PERF_SEL_CP_TCP_INVALIDATE', + 'TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL', + 'TCP_PERF_SEL_DEPTH_MICROTILING', 'TCP_PERF_SEL_DIM_1D', + 'TCP_PERF_SEL_DIM_1D_ARRAY', 'TCP_PERF_SEL_DIM_2D', + 'TCP_PERF_SEL_DIM_2D_ARRAY', 'TCP_PERF_SEL_DIM_2D_ARRAY_MSAA', + 'TCP_PERF_SEL_DIM_2D_MSAA', 'TCP_PERF_SEL_DIM_3D', + 'TCP_PERF_SEL_DIM_CUBE_ARRAY', 'TCP_PERF_SEL_DISPLAY_MICROTILING', + 'TCP_PERF_SEL_GATE_EN1', 'TCP_PERF_SEL_GATE_EN2', + 'TCP_PERF_SEL_HOLE_READ_STALL', + 'TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32', + 'TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64', + 'TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32', + 'TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64', + 'TCP_PERF_SEL_IMG_READ_FMT_1', + 'TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE', + 'TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE', + 'TCP_PERF_SEL_IMG_READ_FMT_16', + 'TCP_PERF_SEL_IMG_READ_FMT_16_AS_128', + 'TCP_PERF_SEL_IMG_READ_FMT_16_AS_64', + 'TCP_PERF_SEL_IMG_READ_FMT_32', + 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_128', + 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_16', + 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_8', + 'TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE', + 'TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE', + 'TCP_PERF_SEL_IMG_READ_FMT_8', + 'TCP_PERF_SEL_IMG_READ_FMT_8_AS_32', + 'TCP_PERF_SEL_IMG_READ_FMT_8_AS_64', + 'TCP_PERF_SEL_IMG_READ_FMT_96', 'TCP_PERF_SEL_IMG_READ_FMT_BC1', + 'TCP_PERF_SEL_IMG_READ_FMT_BC2', 'TCP_PERF_SEL_IMG_READ_FMT_BC3', + 'TCP_PERF_SEL_IMG_READ_FMT_BC4', 'TCP_PERF_SEL_IMG_READ_FMT_BC5', + 'TCP_PERF_SEL_IMG_READ_FMT_BC6', 'TCP_PERF_SEL_IMG_READ_FMT_BC7', + 'TCP_PERF_SEL_IMG_READ_FMT_D16', 'TCP_PERF_SEL_IMG_READ_FMT_D32', + 'TCP_PERF_SEL_IMG_READ_FMT_D8', + 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_R', + 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG', + 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB', + 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA', + 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1', + 'TCP_PERF_SEL_IMG_READ_FMT_I16', 'TCP_PERF_SEL_IMG_READ_FMT_I32', + 'TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16', + 'TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8', + 'TCP_PERF_SEL_IMG_READ_FMT_I8', 'TCP_PERF_SEL_IMG_WRITE_FMT_128', + 'TCP_PERF_SEL_IMG_WRITE_FMT_16', + 'TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128', + 'TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64', + 'TCP_PERF_SEL_IMG_WRITE_FMT_32', 'TCP_PERF_SEL_IMG_WRITE_FMT_64', + 'TCP_PERF_SEL_IMG_WRITE_FMT_8', + 'TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32', + 'TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64', + 'TCP_PERF_SEL_IMG_WRITE_FMT_D16', + 'TCP_PERF_SEL_IMG_WRITE_FMT_D32', 'TCP_PERF_SEL_IMG_WRITE_FMT_D8', + 'TCP_PERF_SEL_LFIFO_STALL_CYCLES', + 'TCP_PERF_SEL_LOD_STALL_CYCLES', + 'TCP_PERF_SEL_PENDING_STALL_CYCLES', 'TCP_PERF_SEL_POWER_STALL', + 'TCP_PERF_SEL_READCONFLICT_STALL_CYCLES', + 'TCP_PERF_SEL_READFIFO_STALL_CYCLES', + 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES', + 'TCP_PERF_SEL_RESERVED_154', 'TCP_PERF_SEL_RFIFO_STALL_CYCLES', + 'TCP_PERF_SEL_ROTATED_MICROTILING', 'TCP_PERF_SEL_SHOOTDOWN', + 'TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL', 'TCP_PERF_SEL_TAGRAM0_REQ', + 'TCP_PERF_SEL_TAGRAM1_REQ', 'TCP_PERF_SEL_TAGRAM2_REQ', + 'TCP_PERF_SEL_TAGRAM3_REQ', + 'TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES', + 'TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES', + 'TCP_PERF_SEL_TA_TCP_STATE_READ', 'TCP_PERF_SEL_TCC_ATOMIC_REQ', + 'TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ', + 'TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ', + 'TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ', + 'TCP_PERF_SEL_TCC_BYPASS_READ_REQ', + 'TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ', + 'TCP_PERF_SEL_TCC_CC_ATOMIC_REQ', 'TCP_PERF_SEL_TCC_CC_READ_REQ', + 'TCP_PERF_SEL_TCC_CC_WRITE_REQ', 'TCP_PERF_SEL_TCC_DATA_BUS_BUSY', + 'TCP_PERF_SEL_TCC_DCC_REQ', 'TCP_PERF_SEL_TCC_LRU_REQ', + 'TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ', + 'TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ', + 'TCP_PERF_SEL_TCC_NC_ATOMIC_REQ', 'TCP_PERF_SEL_TCC_NC_READ_REQ', + 'TCP_PERF_SEL_TCC_NC_WRITE_REQ', 'TCP_PERF_SEL_TCC_NON_READ_REQ', + 'TCP_PERF_SEL_TCC_PHYSICAL_REQ', 'TCP_PERF_SEL_TCC_READ_REQ', + 'TCP_PERF_SEL_TCC_READ_REQ_LATENCY', 'TCP_PERF_SEL_TCC_REQ', + 'TCP_PERF_SEL_TCC_STREAM_REQ', 'TCP_PERF_SEL_TCC_UC_ATOMIC_REQ', + 'TCP_PERF_SEL_TCC_UC_READ_REQ', 'TCP_PERF_SEL_TCC_UC_WRITE_REQ', + 'TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ', + 'TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ', + 'TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ', + 'TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ', + 'TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ', + 'TCP_PERF_SEL_TCC_VOLATILE_READ_REQ', + 'TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ', + 'TCP_PERF_SEL_TCC_WRITE_REQ', + 'TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY', + 'TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY', 'TCP_PERF_SEL_TCP_LATENCY', + 'TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES', + 'TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES', + 'TCP_PERF_SEL_TCR_RDRET_STALL', + 'TCP_PERF_SEL_TCR_TCP_STALL_CYCLES', + 'TCP_PERF_SEL_TC_TA_XNACK_STALL', + 'TCP_PERF_SEL_TD_TCP_STALL_CYCLES', + 'TCP_PERF_SEL_THICK_MICROTILING', 'TCP_PERF_SEL_THIN_MICROTILING', + 'TCP_PERF_SEL_TOTAL_ACCESSES', + 'TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET', + 'TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET', + 'TCP_PERF_SEL_TOTAL_GLOBAL_READ', + 'TCP_PERF_SEL_TOTAL_GLOBAL_WRITE', + 'TCP_PERF_SEL_TOTAL_HIT_EVICT_READ', + 'TCP_PERF_SEL_TOTAL_HIT_LRU_READ', + 'TCP_PERF_SEL_TOTAL_LOCAL_READ', 'TCP_PERF_SEL_TOTAL_LOCAL_WRITE', + 'TCP_PERF_SEL_TOTAL_MISS_EVICT_READ', + 'TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE', + 'TCP_PERF_SEL_TOTAL_MISS_LRU_READ', + 'TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE', + 'TCP_PERF_SEL_TOTAL_NON_READ', 'TCP_PERF_SEL_TOTAL_READ', + 'TCP_PERF_SEL_TOTAL_WBINVL1', 'TCP_PERF_SEL_TOTAL_WBINVL1_VOL', + 'TCP_PERF_SEL_TOTAL_WRITE', + 'TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES', + 'TCP_PERF_SEL_UNALIGNED', 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', + 'TCP_PERF_SEL_UTCL1_LFIFO_FULL', + 'TCP_PERF_SEL_UTCL1_PERMISSION_MISS', + 'TCP_PERF_SEL_UTCL1_REQUEST', + 'TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL', + 'TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', + 'TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', + 'TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', + 'TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', + 'TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', + 'TCP_PERF_SEL_UTCL1_TRANSLATION_MISS', + 'TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT', 'TCP_PERF_SEL_VOLATILE', + 'TCP_PERF_SEL_WRITE_CONFLICT_STALL', + 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES', 'TCP_WATCH_MODES', + 'TCP_WATCH_MODE_ALL', 'TCP_WATCH_MODE_ATOMIC', + 'TCP_WATCH_MODE_NONREAD', 'TCP_WATCH_MODE_READ', + 'TC_CHUB_REQ_CREDITS', 'TC_CHUB_REQ_CREDITS_ENUM', 'TC_EA_CID', + 'TC_EA_CID_CPF', 'TC_EA_CID_CPG', 'TC_EA_CID_DCC', + 'TC_EA_CID_FMASK', 'TC_EA_CID_HTILE', 'TC_EA_CID_IA', + 'TC_EA_CID_MISC', 'TC_EA_CID_PA', 'TC_EA_CID_RT', 'TC_EA_CID_SQC', + 'TC_EA_CID_STENCIL', 'TC_EA_CID_TCP', 'TC_EA_CID_TCPMETA', + 'TC_EA_CID_UTCL2_TPI', 'TC_EA_CID_WD', 'TC_EA_CID_Z', + 'TC_MICRO_TILE_MODE', 'TC_NACKS', 'TC_NACK_DATA_ERROR', + 'TC_NACK_NO_FAULT', 'TC_NACK_PAGE_FAULT', + 'TC_NACK_PROTECTION_FAULT', 'TC_ONLY', 'TC_OP', + 'TC_OP_ATOMIC_ADD_32', 'TC_OP_ATOMIC_ADD_64', + 'TC_OP_ATOMIC_ADD_RTN_32', 'TC_OP_ATOMIC_ADD_RTN_64', + 'TC_OP_ATOMIC_AND_32', 'TC_OP_ATOMIC_AND_64', + 'TC_OP_ATOMIC_AND_RTN_32', 'TC_OP_ATOMIC_AND_RTN_64', + 'TC_OP_ATOMIC_CMPSWAP_32', 'TC_OP_ATOMIC_CMPSWAP_64', + 'TC_OP_ATOMIC_CMPSWAP_RTN_32', 'TC_OP_ATOMIC_CMPSWAP_RTN_64', + 'TC_OP_ATOMIC_DEC_32', 'TC_OP_ATOMIC_DEC_64', + 'TC_OP_ATOMIC_DEC_RTN_32', 'TC_OP_ATOMIC_DEC_RTN_64', + 'TC_OP_ATOMIC_FCMPSWAP_32', 'TC_OP_ATOMIC_FCMPSWAP_64', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', + 'TC_OP_ATOMIC_FMAX_32', 'TC_OP_ATOMIC_FMAX_64', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 'TC_OP_ATOMIC_FMAX_RTN_32', 'TC_OP_ATOMIC_FMAX_RTN_64', + 'TC_OP_ATOMIC_FMIN_32', 'TC_OP_ATOMIC_FMIN_64', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 'TC_OP_ATOMIC_FMIN_RTN_32', 'TC_OP_ATOMIC_FMIN_RTN_64', + 'TC_OP_ATOMIC_INC_32', 'TC_OP_ATOMIC_INC_64', + 'TC_OP_ATOMIC_INC_RTN_32', 'TC_OP_ATOMIC_INC_RTN_64', + 'TC_OP_ATOMIC_OR_32', 'TC_OP_ATOMIC_OR_64', + 'TC_OP_ATOMIC_OR_RTN_32', 'TC_OP_ATOMIC_OR_RTN_64', + 'TC_OP_ATOMIC_SMAX_32', 'TC_OP_ATOMIC_SMAX_64', + 'TC_OP_ATOMIC_SMAX_RTN_32', 'TC_OP_ATOMIC_SMAX_RTN_64', + 'TC_OP_ATOMIC_SMIN_32', 'TC_OP_ATOMIC_SMIN_64', + 'TC_OP_ATOMIC_SMIN_RTN_32', 'TC_OP_ATOMIC_SMIN_RTN_64', + 'TC_OP_ATOMIC_SUB_32', 'TC_OP_ATOMIC_SUB_64', + 'TC_OP_ATOMIC_SUB_RTN_32', 'TC_OP_ATOMIC_SUB_RTN_64', + 'TC_OP_ATOMIC_SWAP_32', 'TC_OP_ATOMIC_SWAP_64', + 'TC_OP_ATOMIC_SWAP_RTN_32', 'TC_OP_ATOMIC_SWAP_RTN_64', + 'TC_OP_ATOMIC_UMAX_32', 'TC_OP_ATOMIC_UMAX_64', + 'TC_OP_ATOMIC_UMAX_RTN_32', 'TC_OP_ATOMIC_UMAX_RTN_64', + 'TC_OP_ATOMIC_UMIN_32', 'TC_OP_ATOMIC_UMIN_64', + 'TC_OP_ATOMIC_UMIN_RTN_32', 'TC_OP_ATOMIC_UMIN_RTN_64', + 'TC_OP_ATOMIC_XOR_32', 'TC_OP_ATOMIC_XOR_64', + 'TC_OP_ATOMIC_XOR_RTN_32', 'TC_OP_ATOMIC_XOR_RTN_64', + 'TC_OP_INVL2_NC', 'TC_OP_INV_METADATA', 'TC_OP_MASKS', + 'TC_OP_MASK_64', 'TC_OP_MASK_FLUSH_DENROM', 'TC_OP_MASK_NO_RTN', + 'TC_OP_NOP_ACK', 'TC_OP_NOP_RTN0', 'TC_OP_PROBE_FILTER', + 'TC_OP_READ', 'TC_OP_RESERVED_FOP_32_0', + 'TC_OP_RESERVED_FOP_32_1', 'TC_OP_RESERVED_FOP_32_2', + 'TC_OP_RESERVED_FOP_64_0', 'TC_OP_RESERVED_FOP_64_1', + 'TC_OP_RESERVED_FOP_64_2', 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', + 'TC_OP_RESERVED_FOP_RTN_32_0', 'TC_OP_RESERVED_FOP_RTN_32_1', + 'TC_OP_RESERVED_FOP_RTN_32_2', 'TC_OP_RESERVED_FOP_RTN_64_0', + 'TC_OP_RESERVED_FOP_RTN_64_1', 'TC_OP_RESERVED_FOP_RTN_64_2', + 'TC_OP_RESERVED_NON_FLOAT_32_1', 'TC_OP_RESERVED_NON_FLOAT_32_2', + 'TC_OP_RESERVED_NON_FLOAT_32_3', 'TC_OP_RESERVED_NON_FLOAT_32_4', + 'TC_OP_RESERVED_NON_FLOAT_64_1', 'TC_OP_RESERVED_NON_FLOAT_64_2', + 'TC_OP_RESERVED_NON_FLOAT_64_3', 'TC_OP_RESERVED_NON_FLOAT_64_4', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', 'TC_OP_WBINVL1', + 'TC_OP_WBINVL1_SD', 'TC_OP_WBINVL1_VOL', 'TC_OP_WBINVL2', + 'TC_OP_WBINVL2_NC', 'TC_OP_WBINVL2_SD', 'TC_OP_WBL2_NC', + 'TC_OP_WBL2_WC', 'TC_OP_WRITE', 'TD_PERFCOUNT_SEL', + 'TD_PERF_SEL_RESERVED_14', 'TD_PERF_SEL_RESERVED_18', + 'TD_PERF_SEL_RESERVED_19', 'TD_PERF_SEL_RESERVED_39', + 'TD_PERF_SEL_RESERVED_43', 'TD_PERF_SEL_RESERVED_44', + 'TD_PERF_SEL_addresscmd_poison', 'TD_PERF_SEL_atomic_wavefront', + 'TD_PERF_SEL_bypass_filter_wavefront', + 'TD_PERF_SEL_coalescable_wavefront', + 'TD_PERF_SEL_coalesced_phase', 'TD_PERF_SEL_constant_state_full', + 'TD_PERF_SEL_consume_gds_traffic', 'TD_PERF_SEL_d16_data_packed', + 'TD_PERF_SEL_d16_en_wavefront', 'TD_PERF_SEL_data_poison', + 'TD_PERF_SEL_eight_phase_wavefront', + 'TD_PERF_SEL_four_phase_forward_wavefront', + 'TD_PERF_SEL_four_phase_wavefront', + 'TD_PERF_SEL_gather4_wavefront', + 'TD_PERF_SEL_gather4h_packed_wavefront', + 'TD_PERF_SEL_gather4h_wavefront', + 'TD_PERF_SEL_gather8h_packed_wavefront', 'TD_PERF_SEL_gds_stall', + 'TD_PERF_SEL_input_busy', 'TD_PERF_SEL_ldfptr_wavefront', + 'TD_PERF_SEL_lerp_busy', 'TD_PERF_SEL_load_wavefront', + 'TD_PERF_SEL_local_cg_dyn_sclk_grp0_en', + 'TD_PERF_SEL_local_cg_dyn_sclk_grp1_en', + 'TD_PERF_SEL_local_cg_dyn_sclk_grp4_en', + 'TD_PERF_SEL_local_cg_dyn_sclk_grp5_en', + 'TD_PERF_SEL_min_max_filter_wavefront', 'TD_PERF_SEL_nack', + 'TD_PERF_SEL_none', 'TD_PERF_SEL_null_cycle_output', + 'TD_PERF_SEL_opaque_black_border', 'TD_PERF_SEL_output_busy', + 'TD_PERF_SEL_output_fifo_full', 'TD_PERF_SEL_pc_stall', + 'TD_PERF_SEL_reg_sclk_vld', 'TD_PERF_SEL_sample_c_wavefront', + 'TD_PERF_SEL_sample_state_full', + 'TD_PERF_SEL_sixteen_phase_wavefront', + 'TD_PERF_SEL_start_cycle_0', 'TD_PERF_SEL_start_cycle_1', + 'TD_PERF_SEL_start_cycle_2', 'TD_PERF_SEL_start_cycle_3', + 'TD_PERF_SEL_store_wavefront', 'TD_PERF_SEL_tc_stall', + 'TD_PERF_SEL_tc_td_fifo_full', 'TD_PERF_SEL_td_busy', + 'TD_PERF_SEL_td_sp_traffic', + 'TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt', + 'TD_PERF_SEL_user_defined_border', 'TD_PERF_SEL_white_border', + 'TD_PERF_SEL_write_ack_wavefront', 'TESS_ISOLINE', 'TESS_QUAD', + 'TESS_TRIANGLE', 'TEX_BORDER_COLOR_TYPE', + 'TEX_BorderColor_OpaqueBlack', 'TEX_BorderColor_OpaqueWhite', + 'TEX_BorderColor_Register', 'TEX_BorderColor_TransparentBlack', + 'TEX_CHROMA_KEY', 'TEX_CLAMP', 'TEX_COORD_TYPE', + 'TEX_ChromaKey_Blend', 'TEX_ChromaKey_Disabled', + 'TEX_ChromaKey_Kill', 'TEX_ChromaKey_RESERVED_3', + 'TEX_Clamp_ClampHalfToBorder', 'TEX_Clamp_ClampToBorder', + 'TEX_Clamp_ClampToLast', 'TEX_Clamp_Mirror', + 'TEX_Clamp_MirrorOnceHalfToBorder', + 'TEX_Clamp_MirrorOnceToBorder', 'TEX_Clamp_MirrorOnceToLast', + 'TEX_Clamp_Repeat', 'TEX_CoordType_Normalized', + 'TEX_CoordType_Unnormalized', 'TEX_DEPTH_COMPARE_FUNCTION', + 'TEX_DIM', 'TEX_DepthCompareFunction_Always', + 'TEX_DepthCompareFunction_Equal', + 'TEX_DepthCompareFunction_Greater', + 'TEX_DepthCompareFunction_GreaterEqual', + 'TEX_DepthCompareFunction_Less', + 'TEX_DepthCompareFunction_LessEqual', + 'TEX_DepthCompareFunction_Never', + 'TEX_DepthCompareFunction_NotEqual', 'TEX_Dim_1D', + 'TEX_Dim_1DArray', 'TEX_Dim_2D', 'TEX_Dim_2DArray', + 'TEX_Dim_2DArray_MSAA', 'TEX_Dim_2D_MSAA', 'TEX_Dim_3D', + 'TEX_Dim_CubeMap', 'TEX_FORMAT_COMP', 'TEX_FormatComp_RESERVED_3', + 'TEX_FormatComp_Signed', 'TEX_FormatComp_Unsigned', + 'TEX_FormatComp_UnsignedBiased', 'TEX_MAX_ANISO_RATIO', + 'TEX_MIP_FILTER', 'TEX_MaxAnisoRatio_16to1', + 'TEX_MaxAnisoRatio_1to1', 'TEX_MaxAnisoRatio_2to1', + 'TEX_MaxAnisoRatio_4to1', 'TEX_MaxAnisoRatio_8to1', + 'TEX_MaxAnisoRatio_RESERVED_5', 'TEX_MaxAnisoRatio_RESERVED_6', + 'TEX_MaxAnisoRatio_RESERVED_7', 'TEX_MipFilter_Linear', + 'TEX_MipFilter_None', 'TEX_MipFilter_Point', + 'TEX_MipFilter_Point_Aniso_Adj', 'TEX_REQUEST_SIZE', + 'TEX_RequestSize_128B', 'TEX_RequestSize_2X64B', + 'TEX_RequestSize_32B', 'TEX_RequestSize_64B', 'TEX_SAMPLER_TYPE', + 'TEX_SamplerType_Invalid', 'TEX_SamplerType_Valid', + 'TEX_XYFilter_AnisoLinear', 'TEX_XYFilter_AnisoPoint', + 'TEX_XYFilter_Linear', 'TEX_XYFilter_Point', 'TEX_XY_FILTER', + 'TEX_ZFilter_Linear', 'TEX_ZFilter_None', 'TEX_ZFilter_Point', + 'TEX_ZFilter_RESERVED_3', 'TEX_Z_FILTER', 'TGID_ROLLOVER', + 'THREAD_TRACE_FINISH', 'THREAD_TRACE_FLUSH', + 'THREAD_TRACE_MARKER', 'THREAD_TRACE_START', 'THREAD_TRACE_STOP', + 'TMDS_COLOR_FORMAT', 'TMDS_COLOR_FORMAT_DUAL30BPP', + 'TMDS_COLOR_FORMAT_RESERVED', 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', + 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', + 'TMDS_CTL0_DATA_INVERT', 'TMDS_CTL0_DATA_INVERT_EN', + 'TMDS_CTL0_DATA_MODULATION', 'TMDS_CTL0_DATA_MODULATION_BIT0', + 'TMDS_CTL0_DATA_MODULATION_BIT1', + 'TMDS_CTL0_DATA_MODULATION_BIT2', + 'TMDS_CTL0_DATA_MODULATION_DISABLE', 'TMDS_CTL0_DATA_NORMAL', + 'TMDS_CTL0_DATA_SEL', 'TMDS_CTL0_DATA_SEL0_RESERVED', + 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL0_DATA_SEL2_VSYNC', + 'TMDS_CTL0_DATA_SEL3_RESERVED', 'TMDS_CTL0_DATA_SEL4_HSYNC', + 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', + 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', + 'TMDS_CTL0_PATTERN_OUT_DISABLE', 'TMDS_CTL0_PATTERN_OUT_EN', + 'TMDS_CTL0_PATTERN_OUT_ENABLE', 'TMDS_CTL1_DATA_INVERT', + 'TMDS_CTL1_DATA_INVERT_EN', 'TMDS_CTL1_DATA_MODULATION', + 'TMDS_CTL1_DATA_MODULATION_BIT0', + 'TMDS_CTL1_DATA_MODULATION_BIT1', + 'TMDS_CTL1_DATA_MODULATION_BIT2', + 'TMDS_CTL1_DATA_MODULATION_DISABLE', 'TMDS_CTL1_DATA_NORMAL', + 'TMDS_CTL1_DATA_SEL', 'TMDS_CTL1_DATA_SEL0_RESERVED', + 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL1_DATA_SEL2_VSYNC', + 'TMDS_CTL1_DATA_SEL3_RESERVED', 'TMDS_CTL1_DATA_SEL4_HSYNC', + 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', + 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', + 'TMDS_CTL1_PATTERN_OUT_DISABLE', 'TMDS_CTL1_PATTERN_OUT_EN', + 'TMDS_CTL1_PATTERN_OUT_ENABLE', 'TMDS_CTL2_DATA_INVERT', + 'TMDS_CTL2_DATA_INVERT_EN', 'TMDS_CTL2_DATA_MODULATION', + 'TMDS_CTL2_DATA_MODULATION_BIT0', + 'TMDS_CTL2_DATA_MODULATION_BIT1', + 'TMDS_CTL2_DATA_MODULATION_BIT2', + 'TMDS_CTL2_DATA_MODULATION_DISABLE', 'TMDS_CTL2_DATA_NORMAL', + 'TMDS_CTL2_DATA_SEL', 'TMDS_CTL2_DATA_SEL0_RESERVED', + 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL2_DATA_SEL2_VSYNC', + 'TMDS_CTL2_DATA_SEL3_RESERVED', 'TMDS_CTL2_DATA_SEL4_HSYNC', + 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', + 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', + 'TMDS_CTL2_PATTERN_OUT_DISABLE', 'TMDS_CTL2_PATTERN_OUT_EN', + 'TMDS_CTL2_PATTERN_OUT_ENABLE', 'TMDS_CTL3_DATA_INVERT', + 'TMDS_CTL3_DATA_INVERT_EN', 'TMDS_CTL3_DATA_MODULATION', + 'TMDS_CTL3_DATA_MODULATION_BIT0', + 'TMDS_CTL3_DATA_MODULATION_BIT1', + 'TMDS_CTL3_DATA_MODULATION_BIT2', + 'TMDS_CTL3_DATA_MODULATION_DISABLE', 'TMDS_CTL3_DATA_NORMAL', + 'TMDS_CTL3_DATA_SEL', 'TMDS_CTL3_DATA_SEL0_RESERVED', + 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL3_DATA_SEL2_VSYNC', + 'TMDS_CTL3_DATA_SEL3_RESERVED', 'TMDS_CTL3_DATA_SEL4_HSYNC', + 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', + 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', + 'TMDS_CTL3_PATTERN_OUT_DISABLE', 'TMDS_CTL3_PATTERN_OUT_EN', + 'TMDS_CTL3_PATTERN_OUT_ENABLE', + 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL', + 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', + 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', + 'TMDS_DVO_MUX_SELECT', 'TMDS_DVO_MUX_SELECT_B', + 'TMDS_DVO_MUX_SELECT_G', 'TMDS_DVO_MUX_SELECT_R', + 'TMDS_DVO_MUX_SELECT_RESERVED', + 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', 'TMDS_PIXEL_ENCODING', + 'TMDS_PIXEL_ENCODING_422', 'TMDS_PIXEL_ENCODING_444_OR_420', + 'TMDS_REG_TEST_OUTPUTA_CNTLA', 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', + 'TMDS_REG_TEST_OUTPUTB_CNTLB', 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', + 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', + 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', + 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', 'TMDS_STEREOSYNC_CTL0', + 'TMDS_STEREOSYNC_CTL1', 'TMDS_STEREOSYNC_CTL2', + 'TMDS_STEREOSYNC_CTL3', 'TMDS_STEREOSYNC_CTL_SEL_REG', + 'TMDS_SYNC_PHASE', 'TMDS_SYNC_PHASE_ON_FRAME_START', + 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', + 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', + 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', + 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', + 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA', + 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB', + 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA', + 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB', + 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN', + 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK', + 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN', + 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK', + 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS', + 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS', + 'TMDS_TRANSMITTER_ENABLE_HPD_MASK', + 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK', + 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK', + 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', + 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', + 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', + 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', + 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', + 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', + 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', + 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', + 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', + 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', + 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', + 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', + 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', + 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', + 'TMDS_TRANSMITTER_PLLSEL_BY_HW', + 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', + 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', + 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', + 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', + 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', + 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', + 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', + 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', + 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', + 'TRANSFERRED_1024_BYTES', 'TRANSFERRED_128_BYTES', + 'TRANSFERRED_2048_BYTES', 'TRANSFERRED_256_BYTES', + 'TRANSFERRED_4096_BYTES', 'TRANSFERRED_512_BYTES', + 'TRANSFERRED_64_BYTES', 'TRANSFERRED_8192_BYTES', 'TRAPEZOIDS', + 'TRISTRIP', 'TVX_DATA_FORMAT', 'TVX_DST_SEL', 'TVX_DstSel_0f', + 'TVX_DstSel_1f', 'TVX_DstSel_Mask', 'TVX_DstSel_RESERVED_6', + 'TVX_DstSel_W', 'TVX_DstSel_X', 'TVX_DstSel_Y', 'TVX_DstSel_Z', + 'TVX_ENDIAN_SWAP', 'TVX_EndianSwap_8in16', 'TVX_EndianSwap_8in32', + 'TVX_EndianSwap_8in64', 'TVX_EndianSwap_None', 'TVX_FMT_1', + 'TVX_FMT_10_10_10_2', 'TVX_FMT_10_11_11', + 'TVX_FMT_10_11_11_FLOAT', 'TVX_FMT_11_11_10', + 'TVX_FMT_11_11_10_FLOAT', 'TVX_FMT_16', 'TVX_FMT_16_16', + 'TVX_FMT_16_16_16', 'TVX_FMT_16_16_16_16', + 'TVX_FMT_16_16_16_16_FLOAT', 'TVX_FMT_16_16_16_FLOAT', + 'TVX_FMT_16_16_FLOAT', 'TVX_FMT_16_FLOAT', 'TVX_FMT_1_5_5_5', + 'TVX_FMT_1_REVERSED', 'TVX_FMT_24_8', 'TVX_FMT_24_8_FLOAT', + 'TVX_FMT_2_10_10_10', 'TVX_FMT_32', 'TVX_FMT_32_32', + 'TVX_FMT_32_32_32', 'TVX_FMT_32_32_32_32', + 'TVX_FMT_32_32_32_32_FLOAT', 'TVX_FMT_32_32_32_FLOAT', + 'TVX_FMT_32_32_FLOAT', 'TVX_FMT_32_AS_8', 'TVX_FMT_32_AS_8_8', + 'TVX_FMT_32_FLOAT', 'TVX_FMT_3_3_2', 'TVX_FMT_4_4', + 'TVX_FMT_4_4_4_4', 'TVX_FMT_5_5_5_1', 'TVX_FMT_5_6_5', + 'TVX_FMT_5_9_9_9_SHAREDEXP', 'TVX_FMT_6_5_5', 'TVX_FMT_8', + 'TVX_FMT_8_24', 'TVX_FMT_8_24_FLOAT', 'TVX_FMT_8_8', + 'TVX_FMT_8_8_8', 'TVX_FMT_8_8_8_8', 'TVX_FMT_APC0', + 'TVX_FMT_APC1', 'TVX_FMT_APC2', 'TVX_FMT_APC3', 'TVX_FMT_APC4', + 'TVX_FMT_APC5', 'TVX_FMT_APC6', 'TVX_FMT_APC7', 'TVX_FMT_BC1', + 'TVX_FMT_BC2', 'TVX_FMT_BC3', 'TVX_FMT_BC4', 'TVX_FMT_BC5', + 'TVX_FMT_BG_RG', 'TVX_FMT_CTX1', 'TVX_FMT_GB_GR', + 'TVX_FMT_INVALID', 'TVX_FMT_RESERVED_33', 'TVX_FMT_RESERVED_36', + 'TVX_FMT_RESERVED_4', 'TVX_FMT_RESERVED_63', + 'TVX_FMT_X24_8_32_FLOAT', 'TVX_INST', 'TVX_Inst_Gather4', + 'TVX_Inst_Gather4_C', 'TVX_Inst_Gather4_C_O', + 'TVX_Inst_Gather4_O', 'TVX_Inst_GetBufferResInfo', + 'TVX_Inst_GetGradientsH', 'TVX_Inst_GetGradientsV', + 'TVX_Inst_GetLOD', 'TVX_Inst_GetNumberOfSamples', + 'TVX_Inst_GetTextureResInfo', 'TVX_Inst_KeepGradients', + 'TVX_Inst_LD', 'TVX_Inst_NormalVertexFetch', 'TVX_Inst_Pass', + 'TVX_Inst_RESERVED_15', 'TVX_Inst_RESERVED_2', 'TVX_Inst_Sample', + 'TVX_Inst_Sample_C', 'TVX_Inst_Sample_C_G', + 'TVX_Inst_Sample_C_G_LB', 'TVX_Inst_Sample_C_L', + 'TVX_Inst_Sample_C_LB', 'TVX_Inst_Sample_C_LZ', + 'TVX_Inst_Sample_G', 'TVX_Inst_Sample_G_LB', 'TVX_Inst_Sample_L', + 'TVX_Inst_Sample_LB', 'TVX_Inst_Sample_LZ', + 'TVX_Inst_SemanticVertexFetch', 'TVX_Inst_SetGradientsH', + 'TVX_Inst_SetGradientsV', 'TVX_Inst_SetTextureOffsets', + 'TVX_NUM_FORMAT_ALL', 'TVX_NumFormatAll_Int', + 'TVX_NumFormatAll_Norm', 'TVX_NumFormatAll_RESERVED_3', + 'TVX_NumFormatAll_Scaled', 'TVX_SRC_SEL', 'TVX_SRFModeAll_NZ', + 'TVX_SRFModeAll_ZCMO', 'TVX_SRF_MODE_ALL', 'TVX_SrcSel_0f', + 'TVX_SrcSel_1f', 'TVX_SrcSel_W', 'TVX_SrcSel_X', 'TVX_SrcSel_Y', + 'TVX_SrcSel_Z', 'TVX_TYPE', 'TVX_Type_InvalidTextureResource', + 'TVX_Type_InvalidVertexBuffer', 'TVX_Type_ValidTextureResource', + 'TVX_Type_ValidVertexBuffer', 'TileSplit', 'TileType', + 'UCONFIG_SPACE_END', 'UCONFIG_SPACE_START', 'UNDEF', + 'UNP_ADDR_SURF_MACRO_ASPECT_1', 'UNP_ADDR_SURF_MACRO_ASPECT_2', + 'UNP_ADDR_SURF_MACRO_ASPECT_4', 'UNP_ADDR_SURF_MACRO_ASPECT_8', + 'UNP_ADDR_SURF_TILE_SPLIT_128B', 'UNP_ADDR_SURF_TILE_SPLIT_1KB', + 'UNP_ADDR_SURF_TILE_SPLIT_256B', 'UNP_ADDR_SURF_TILE_SPLIT_2KB', + 'UNP_ADDR_SURF_TILE_SPLIT_4KB', 'UNP_ADDR_SURF_TILE_SPLIT_512B', + 'UNP_ADDR_SURF_TILE_SPLIT_64B', 'UNP_BUFFER_MODE', + 'UNP_BUFFER_MODE_LUMA', 'UNP_BUFFER_MODE_LUMA_CHROMA', + 'UNP_CRC_LINE_SEL', 'UNP_CRC_LINE_SEL_EVEN_ONLY', + 'UNP_CRC_LINE_SEL_ODD_EVEN', 'UNP_CRC_LINE_SEL_ODD_ONLY', + 'UNP_CRC_LINE_SEL_RESERVED', 'UNP_CRC_SOURCE_SEL', + 'UNP_CRC_SOURCE_SEL_LOWER16', 'UNP_CRC_SOURCE_SEL_LOWER32', + 'UNP_CRC_SOURCE_SEL_NP_TO_LBV', 'UNP_CRC_SOURCE_SEL_RESERVED', + 'UNP_CRC_SOURCE_SEL_UNP_TO_LBV', 'UNP_GRPH_16BPP', + 'UNP_GRPH_32BPP', 'UNP_GRPH_8BPP', + 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE', + 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0', + 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1', + 'UNP_GRPH_ADDR_SURF_16_BANK', 'UNP_GRPH_ADDR_SURF_2_BANK', + 'UNP_GRPH_ADDR_SURF_4_BANK', 'UNP_GRPH_ADDR_SURF_8_BANK', + 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1', + 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2', + 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4', + 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8', + 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_1', + 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_2', + 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_4', + 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_8', 'UNP_GRPH_BANK_HEIGHT', + 'UNP_GRPH_BANK_WIDTH', 'UNP_GRPH_BLUE_CROSSBAR', + 'UNP_GRPH_BLUE_CROSSBAR_A', 'UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C', + 'UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y', 'UNP_GRPH_BLUE_CROSSBAR_R_Cr', + 'UNP_GRPH_COLOR_EXPANSION_MODE', 'UNP_GRPH_DEPTH', + 'UNP_GRPH_DISABLED', 'UNP_GRPH_DYNAMIC_EXPANSION', 'UNP_GRPH_EN', + 'UNP_GRPH_ENABLED', 'UNP_GRPH_ENDIAN_SWAP', + 'UNP_GRPH_ENDIAN_SWAP_8IN16', 'UNP_GRPH_ENDIAN_SWAP_8IN32', + 'UNP_GRPH_ENDIAN_SWAP_8IN43', 'UNP_GRPH_ENDIAN_SWAP_NONE', + 'UNP_GRPH_GREEN_CROSSBAR', 'UNP_GRPH_MACRO_TILE_ASPECT', + 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE', + 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0', + 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1', + 'UNP_GRPH_MODE_UPDATE_LOCKG', 'UNP_GRPH_NUM_BANKS', + 'UNP_GRPH_RED_CROSSBAR', 'UNP_GRPH_RED_CROSSBAR_A', + 'UNP_GRPH_RED_CROSSBAR_B_Cb', 'UNP_GRPH_RED_CROSSBAR_G_Y', + 'UNP_GRPH_RED_CROSSBAR_R_Cr', + 'UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE', + 'UNP_GRPH_STACK_INTERLACE_FLIP_EN', + 'UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE', + 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE', + 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0', + 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1', + 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2', + 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3', + 'UNP_GRPH_STEREOSYNC_FLIP_DISABLE', 'UNP_GRPH_STEREOSYNC_FLIP_EN', + 'UNP_GRPH_STEREOSYNC_FLIP_ENABLE', + 'UNP_GRPH_STEREOSYNC_FLIP_MODE', + 'UNP_GRPH_STEREOSYNC_FLIP_MODE_0', + 'UNP_GRPH_STEREOSYNC_FLIP_MODE_1', + 'UNP_GRPH_STEREOSYNC_FLIP_MODE_2', + 'UNP_GRPH_STEREOSYNC_FLIP_MODE_3', + 'UNP_GRPH_STEREOSYNC_SELECT_DIS', + 'UNP_GRPH_STEREOSYNC_SELECT_DISABLE', + 'UNP_GRPH_STEREOSYNC_SELECT_EN', + 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE', + 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0', + 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1', + 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK', + 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0', + 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1', 'UNP_GRPH_TILE_SPLIT', + 'UNP_GRPH_UPDATE_LOCK_0', 'UNP_GRPH_UPDATE_LOCK_1', + 'UNP_GRPH_ZERO_EXPANSION', 'UNP_PIXEL_DROP', 'UNP_PIXEL_DROPPING', + 'UNP_PIXEL_NO_DROP', 'UNP_ROTATION_ANGLE', 'UNP_ROTATION_ANGLE_0', + 'UNP_ROTATION_ANGLE_0m', 'UNP_ROTATION_ANGLE_180', + 'UNP_ROTATION_ANGLE_180m', 'UNP_ROTATION_ANGLE_270', + 'UNP_ROTATION_ANGLE_270m', 'UNP_ROTATION_ANGLE_90', + 'UNP_ROTATION_ANGLE_90m', 'UNP_UNP_GRPH_GREEN_CROSSBAR_A', + 'UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C', + 'UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y', + 'UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr', 'UNP_VIDEO_FORMAT', + 'UNP_VIDEO_FORMAT0', 'UNP_VIDEO_FORMAT1', + 'UNP_VIDEO_FORMAT_YUV420_YCbCr', 'UNP_VIDEO_FORMAT_YUV420_YCrCb', + 'UNP_VIDEO_FORMAT_YUV422_CbY', 'UNP_VIDEO_FORMAT_YUV422_CrY', + 'UNP_VIDEO_FORMAT_YUV422_YCb', 'UNP_VIDEO_FORMAT_YUV422_YCr', + 'UPDATE_LOCKED', 'UPDATE_UNLOCKED', 'UTCL1FaultType', + 'UTCL1RequestType', 'UTCL1_TYPE_BYPASS', 'UTCL1_TYPE_NORMAL', + 'UTCL1_TYPE_SHOOTDOWN', 'UTCL1_XNACK_NO_RETRY', 'UTCL1_XNACK_PRT', + 'UTCL1_XNACK_RETRY', 'UTCL1_XNACK_SUCCESS', 'VC_AND_TC', + 'VC_ONLY', 'VGT_CACHE_INVALID_MODE', 'VGT_DIST_MODE', + 'VGT_DI_INDEX_SIZE', 'VGT_DI_MAJOR_MODE_SELECT', + 'VGT_DI_PRIM_TYPE', 'VGT_DI_SOURCE_SELECT', 'VGT_DMA_BUF_MEM', + 'VGT_DMA_BUF_RING', 'VGT_DMA_BUF_SETUP', 'VGT_DMA_BUF_TYPE', + 'VGT_DMA_PTR_UPDATE', 'VGT_DMA_SWAP_16_BIT', + 'VGT_DMA_SWAP_32_BIT', 'VGT_DMA_SWAP_MODE', 'VGT_DMA_SWAP_NONE', + 'VGT_DMA_SWAP_WORD', 'VGT_EVENT_TYPE', 'VGT_FLUSH', + 'VGT_GROUP_CONV_SEL', 'VGT_GRP_2D_COPY_RECT_V0', + 'VGT_GRP_2D_COPY_RECT_V1', 'VGT_GRP_2D_COPY_RECT_V2', + 'VGT_GRP_2D_COPY_RECT_V3', 'VGT_GRP_2D_FILL_RECT', + 'VGT_GRP_2D_LINE', 'VGT_GRP_2D_RECT', 'VGT_GRP_2D_TRI', + 'VGT_GRP_3D_LINE', 'VGT_GRP_3D_LINE_ADJ', 'VGT_GRP_3D_PATCH', + 'VGT_GRP_3D_POINT', 'VGT_GRP_3D_QUAD', 'VGT_GRP_3D_RECT', + 'VGT_GRP_3D_TRI', 'VGT_GRP_3D_TRI_ADJ', 'VGT_GRP_AUTO_PRIM', + 'VGT_GRP_FAN', 'VGT_GRP_FIX_1_23_TO_FLOAT', 'VGT_GRP_FLOAT_32', + 'VGT_GRP_INDEX_16', 'VGT_GRP_INDEX_32', 'VGT_GRP_LIST', + 'VGT_GRP_LOOP', 'VGT_GRP_POLYGON', 'VGT_GRP_PRIM_INDEX_LINE', + 'VGT_GRP_PRIM_INDEX_QUAD', 'VGT_GRP_PRIM_INDEX_TRI', + 'VGT_GRP_PRIM_ORDER', 'VGT_GRP_PRIM_TYPE', 'VGT_GRP_SINT_16', + 'VGT_GRP_SINT_32', 'VGT_GRP_STRIP', 'VGT_GRP_UINT_16', + 'VGT_GRP_UINT_32', 'VGT_GS_CUT_MODE', 'VGT_GS_MODE_TYPE', + 'VGT_GS_OUTPRIM_TYPE', 'VGT_INDEX_16', 'VGT_INDEX_32', + 'VGT_INDEX_8', 'VGT_INDEX_TYPE_MODE', 'VGT_OUTPATH_GS_BLOCK', + 'VGT_OUTPATH_HS_BLOCK', 'VGT_OUTPATH_PASSTHRU', + 'VGT_OUTPATH_PRIM_GEN', 'VGT_OUTPATH_SELECT', + 'VGT_OUTPATH_TESS_EN', 'VGT_OUTPATH_VTX_REUSE', 'VGT_OUT_2D_RECT', + 'VGT_OUT_LINE', 'VGT_OUT_LINE_ADJ', 'VGT_OUT_PATCH', + 'VGT_OUT_POINT', 'VGT_OUT_PRIM_TYPE', 'VGT_OUT_RECT_V0', + 'VGT_OUT_RECT_V1', 'VGT_OUT_RECT_V2', 'VGT_OUT_RECT_V3', + 'VGT_OUT_TRI', 'VGT_OUT_TRI_ADJ', 'VGT_PERFCOUNT_SELECT', + 'VGT_POLICY_LRU', 'VGT_POLICY_STREAM', 'VGT_RDREQ_POLICY', + 'VGT_STAGES_ES_EN', 'VGT_STAGES_GS_EN', 'VGT_STAGES_HS_EN', + 'VGT_STAGES_LS_EN', 'VGT_STAGES_VS_EN', 'VGT_STREAMOUT_RESET', + 'VGT_STREAMOUT_SYNC', 'VGT_TESS_PARTITION', 'VGT_TESS_TOPOLOGY', + 'VGT_TESS_TYPE', 'VGT_TE_PRIM_INDEX_LINE', + 'VGT_TE_PRIM_INDEX_QUAD', 'VGT_TE_PRIM_INDEX_TRI', 'VGT_TE_QUAD', + 'VID_ENHANCED_MODE', 'VID_NORMAL_FRAME_MODE', + 'VID_STREAM_DISABLE_MASKED', 'VID_STREAM_DISABLE_UNMASK', + 'VMID_SZ', 'VS_PARTIAL_FLUSH', 'VS_STAGE_COPY_SHADER', + 'VS_STAGE_DS', 'VS_STAGE_REAL', 'VTX_CLAMP', + 'VTX_Clamp_ClampToNAN', 'VTX_Clamp_ClampToZero', 'VTX_FETCH_TYPE', + 'VTX_FORMAT_COMP_ALL', 'VTX_FetchType_InstanceData', + 'VTX_FetchType_NoIndexOffset', 'VTX_FetchType_RESERVED_3', + 'VTX_FetchType_VertexData', 'VTX_FormatCompAll_Signed', + 'VTX_FormatCompAll_Unsigned', 'VTX_MEM_REQUEST_SIZE', + 'VTX_MemRequestSize_32B', 'VTX_MemRequestSize_64B', + 'WD_IA_DRAW_REG_XFER', 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', + 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', + 'WD_IA_DRAW_SOURCE', 'WD_IA_DRAW_SOURCE_AUTO', + 'WD_IA_DRAW_SOURCE_DMA', 'WD_IA_DRAW_SOURCE_IMMD', + 'WD_IA_DRAW_SOURCE_OPAQ', 'WD_IA_DRAW_TYPE', + 'WD_IA_DRAW_TYPE_DI_MM0', 'WD_IA_DRAW_TYPE_EVENT_ADDR', + 'WD_IA_DRAW_TYPE_EVENT_INIT', 'WD_IA_DRAW_TYPE_IMM_DATA', + 'WD_IA_DRAW_TYPE_INDX_OFF', 'WD_IA_DRAW_TYPE_MAX_INDX', + 'WD_IA_DRAW_TYPE_MIN_INDX', 'WD_IA_DRAW_TYPE_REG_XFER', + 'WD_PERFCOUNT_SELECT', 'XDMA_LOCAL_SW_MODE_SW_256B_D', + 'XDMA_LOCAL_SW_MODE_SW_64KB_D', 'XDMA_LOCAL_SW_MODE_SW_64KB_D_X', + 'XDMA_MSTR_ALPHA_POSITION_15_8', 'XDMA_MSTR_ALPHA_POSITION_23_16', + 'XDMA_MSTR_ALPHA_POSITION_31_24', 'XDMA_MSTR_ALPHA_POSITION_7_0', + 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE0', + 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE1', + 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE2', + 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE3', + 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE4', + 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE5', + 'XDMA_SLV_ALPHA_POSITION_15_8', 'XDMA_SLV_ALPHA_POSITION_23_16', + 'XDMA_SLV_ALPHA_POSITION_31_24', 'XDMA_SLV_ALPHA_POSITION_7_0', + 'XTAL_REF_CLOCK_SOURCE_SEL', 'XTAL_REF_CLOCK_SOURCE_SEL_PPLL', + 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', 'XTAL_REF_SEL', + 'XTAL_REF_SEL_1X', 'XTAL_REF_SEL_2X', 'ZFormat', 'ZLimitSumm', + 'ZModeForce', 'ZOrder', 'ZPASS_DISABLE', 'ZPASS_DONE', + 'ZPASS_PIXELS', 'ZPASS_SAMPLES', 'ZSamplePosition', 'Z_16', + 'Z_24', 'Z_32_FLOAT', 'Z_INVALID', 'Z_SAMPLE_CENTER', + 'Z_SAMPLE_CENTROID', 'ZpassControl', '_vega10_ENUM_HEADER', + 'ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE', 'ia_perf_MC_LAT_BIN_0', + 'ia_perf_MC_LAT_BIN_1', 'ia_perf_MC_LAT_BIN_2', + 'ia_perf_MC_LAT_BIN_3', 'ia_perf_MC_LAT_BIN_4', + 'ia_perf_MC_LAT_BIN_5', 'ia_perf_MC_LAT_BIN_6', + 'ia_perf_MC_LAT_BIN_7', 'ia_perf_RESERVED1', 'ia_perf_RESERVED2', + 'ia_perf_RESERVED3', 'ia_perf_RESERVED4', 'ia_perf_RESERVED5', + 'ia_perf_RESERVED6', 'ia_perf_RESERVED7', + 'ia_perf_dma_data_fifo_full', 'ia_perf_ia_busy', + 'ia_perf_ia_dma_return', 'ia_perf_ia_sclk_core_vld_event', + 'ia_perf_ia_sclk_reg_vld_event', 'ia_perf_ia_stalled', + 'ia_perf_shift_starved_pipe0_event', + 'ia_perf_shift_starved_pipe1_event', 'vgt_perf_VGT_PA_CLIPP_EOP', + 'vgt_perf_VGT_PA_CLIPP_IS_EVENT', + 'vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT', + 'vgt_perf_VGT_PA_CLIPP_NULL_PRIM', 'vgt_perf_VGT_PA_CLIPP_SEND', + 'vgt_perf_VGT_PA_CLIPP_STALLED', + 'vgt_perf_VGT_PA_CLIPP_STARVED_BUSY', + 'vgt_perf_VGT_PA_CLIPP_STARVED_IDLE', + 'vgt_perf_VGT_PA_CLIPP_STATIC', 'vgt_perf_VGT_PA_CLIPS_SEND', + 'vgt_perf_VGT_PA_CLIPS_STALLED', + 'vgt_perf_VGT_PA_CLIPS_STARVED_BUSY', + 'vgt_perf_VGT_PA_CLIPS_STARVED_IDLE', + 'vgt_perf_VGT_PA_CLIPS_STATIC', 'vgt_perf_VGT_PA_CLIPV_FIRSTVERT', + 'vgt_perf_VGT_PA_CLIPV_SEND', 'vgt_perf_VGT_PA_CLIPV_STALLED', + 'vgt_perf_VGT_PA_CLIPV_STARVED_BUSY', + 'vgt_perf_VGT_PA_CLIPV_STARVED_IDLE', + 'vgt_perf_VGT_PA_CLIPV_STATIC', + 'vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE', + 'vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE', + 'vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT', + 'vgt_perf_VGT_SPI_ESTHREAD_SEND', 'vgt_perf_VGT_SPI_ESVERT_EOV', + 'vgt_perf_VGT_SPI_ESVERT_STALLED', + 'vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY', + 'vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE', + 'vgt_perf_VGT_SPI_ESVERT_STATIC', 'vgt_perf_VGT_SPI_ESVERT_VALID', + 'vgt_perf_VGT_SPI_GSPRIM_CONT', 'vgt_perf_VGT_SPI_GSPRIM_EOV', + 'vgt_perf_VGT_SPI_GSPRIM_STALLED', + 'vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY', + 'vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE', + 'vgt_perf_VGT_SPI_GSPRIM_STATIC', 'vgt_perf_VGT_SPI_GSPRIM_VALID', + 'vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE', + 'vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT', + 'vgt_perf_VGT_SPI_GSTHREAD_SEND', 'vgt_perf_VGT_SPI_HSVERT_EOV', + 'vgt_perf_VGT_SPI_HSVERT_STALLED', + 'vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY', + 'vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE', + 'vgt_perf_VGT_SPI_HSVERT_STATIC', 'vgt_perf_VGT_SPI_HSVERT_VALID', + 'vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE', + 'vgt_perf_VGT_SPI_HSWAVE_IS_EVENT', + 'vgt_perf_VGT_SPI_HSWAVE_SEND', 'vgt_perf_VGT_SPI_LSVERT_EOV', + 'vgt_perf_VGT_SPI_LSVERT_STALLED', + 'vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY', + 'vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE', + 'vgt_perf_VGT_SPI_LSVERT_STATIC', 'vgt_perf_VGT_SPI_LSVERT_VALID', + 'vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE', + 'vgt_perf_VGT_SPI_LSWAVE_IS_EVENT', + 'vgt_perf_VGT_SPI_LSWAVE_SEND', + 'vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE', + 'vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT', + 'vgt_perf_VGT_SPI_VSTHREAD_SEND', 'vgt_perf_VGT_SPI_VSVERT_EOV', + 'vgt_perf_VGT_SPI_VSVERT_SEND', 'vgt_perf_VGT_SPI_VSVERT_STALLED', + 'vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY', + 'vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE', + 'vgt_perf_VGT_SPI_VSVERT_STATIC', 'vgt_perf_cm_reading_stalled', + 'vgt_perf_cm_stalled_by_gog', + 'vgt_perf_cm_stalled_by_gsfetch_done', + 'vgt_perf_counters_avail_stalled', + 'vgt_perf_cut_mem_flush_stalled', 'vgt_perf_ds_RESERVED', + 'vgt_perf_ds_cache_hits', 'vgt_perf_ds_prims', 'vgt_perf_es_done', + 'vgt_perf_es_done_latency', 'vgt_perf_es_flush', + 'vgt_perf_es_ring_high_water_mark', 'vgt_perf_es_thread_groups', + 'vgt_perf_esthread_stalled_es_rb_full', + 'vgt_perf_esthread_stalled_spi_bp', + 'vgt_perf_esvert_stalled_es_tbl', + 'vgt_perf_esvert_stalled_gs_event', + 'vgt_perf_esvert_stalled_gs_tbl', + 'vgt_perf_esvert_stalled_gsprim', 'vgt_perf_gog_busy', + 'vgt_perf_gog_out_indx_stalled', 'vgt_perf_gog_out_prim_stalled', + 'vgt_perf_gog_vs_tbl_stalled', 'vgt_perf_gs_cache_hits', + 'vgt_perf_gs_done', 'vgt_perf_gs_done_latency', + 'vgt_perf_gs_done_received', 'vgt_perf_gs_event_stall', + 'vgt_perf_gs_issue_rtr_stalled', + 'vgt_perf_gs_rb_space_avail_stalled', + 'vgt_perf_gs_ring_high_water_mark', + 'vgt_perf_gsprim_stalled_es_tbl', + 'vgt_perf_gsprim_stalled_esvert', + 'vgt_perf_gsprim_stalled_gs_event', + 'vgt_perf_gsprim_stalled_gs_tbl', 'vgt_perf_gsthread_stalled', + 'vgt_perf_hs_done', 'vgt_perf_hs_done_latency', + 'vgt_perf_hs_flush', 'vgt_perf_hs_input_stall', + 'vgt_perf_hs_interface_stall', 'vgt_perf_hs_tfm_stall', + 'vgt_perf_hs_tgs_active_high_water_mark', + 'vgt_perf_hs_thread_groups', 'vgt_perf_hs_tif_stall', + 'vgt_perf_hs_waiting_on_ls_done_stall', 'vgt_perf_hswave_stalled', + 'vgt_perf_ls_done', 'vgt_perf_ls_done_latency', + 'vgt_perf_ls_flush', 'vgt_perf_ls_thread_groups', + 'vgt_perf_pa_clipp_dealloc', 'vgt_perf_reused_es_indices', + 'vgt_perf_reused_vs_indices', 'vgt_perf_sclk_core_vld_event', + 'vgt_perf_sclk_gs_vld_event', 'vgt_perf_sclk_reg_vld_event', + 'vgt_perf_strmout_stalled', + 'vgt_perf_te11_con_starved_after_work', 'vgt_perf_te11_starved', + 'vgt_perf_total_cache_hits', 'vgt_perf_vgt_busy', + 'vgt_perf_vgt_gs_busy', 'vgt_perf_vgt_hs_busy', + 'vgt_perf_vgt_pa_clipp_eopg', + 'vgt_perf_vgt_pa_clipp_send_not_event', + 'vgt_perf_vgt_pa_clipp_starved_after_work', + 'vgt_perf_vgt_pa_clipp_valid_prim', 'vgt_perf_vgt_te11_busy', + 'vgt_perf_vs_cache_hits', 'vgt_perf_vs_conflicting_indices', + 'vgt_perf_vs_table_high_water_mark', 'vgt_perf_vs_thread_groups', + 'vgt_perf_vsfetch_done', 'vgt_perf_vsvert_api_send', + 'vgt_perf_vsvert_ds_send', 'vgt_perf_vsvert_work_received', + 'vgt_perf_wait_for_es_done_stalled', 'vgt_perf_waveid_stalled', + 'vgt_spi_vsvert_valid', 'wd_perf_RBIU_DI_FIFO_STALLED', + 'wd_perf_RBIU_DI_FIFO_STARVED', 'wd_perf_RBIU_DR_FIFO_STALLED', + 'wd_perf_RBIU_DR_FIFO_STARVED', + 'wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE', 'wd_perf_hs_done_se0', + 'wd_perf_hs_done_se1', 'wd_perf_hs_done_se2', + 'wd_perf_hs_done_se3', 'wd_perf_inside_tf_bin_0', + 'wd_perf_inside_tf_bin_1', 'wd_perf_inside_tf_bin_2', + 'wd_perf_inside_tf_bin_3', 'wd_perf_inside_tf_bin_4', + 'wd_perf_inside_tf_bin_5', 'wd_perf_inside_tf_bin_6', + 'wd_perf_inside_tf_bin_7', 'wd_perf_inside_tf_bin_8', + 'wd_perf_null_patches', 'wd_perf_se0_hs_done_latency', + 'wd_perf_se1_hs_done_latency', 'wd_perf_se2_hs_done_latency', + 'wd_perf_se3_hs_done_latency', 'wd_perf_tfreq_lat_bin_0', + 'wd_perf_tfreq_lat_bin_1', 'wd_perf_tfreq_lat_bin_2', + 'wd_perf_tfreq_lat_bin_3', 'wd_perf_tfreq_lat_bin_4', + 'wd_perf_tfreq_lat_bin_5', 'wd_perf_tfreq_lat_bin_6', + 'wd_perf_tfreq_lat_bin_7', 'wd_perf_wd_busy', + 'wd_perf_wd_sclk_core_vld_event', + 'wd_perf_wd_sclk_input_vld_event', + 'wd_perf_wd_sclk_reg_vld_event', 'wd_perf_wd_stalled', + 'wd_starved_on_hs_done'] diff --git a/tinygrad/runtime/ops_amd.py b/tinygrad/runtime/ops_amd.py index 599c30071b..cd84a531a8 100644 --- a/tinygrad/runtime/ops_amd.py +++ b/tinygrad/runtime/ops_amd.py @@ -6,7 +6,7 @@ from dataclasses import dataclass from tinygrad.runtime.support.hcq import HCQCompiled, HCQAllocator, HCQBuffer, HWQueue, CLikeArgsState, HCQSignal, HCQProgram, HWInterface from tinygrad.ops import sint from tinygrad.device import Compiled, ProfileEvent, BufferSpec, CPUProgram, PROFILE -from tinygrad.helpers import getenv, to_mv, round_up, data64_le, mv_address, DEBUG, OSX +from tinygrad.helpers import getenv, to_mv, round_up, data64_le, mv_address, all_same, flatten, DEBUG, OSX from tinygrad.renderer.cstyle import AMDRenderer from tinygrad.renderer.llvmir import AMDLLVMRenderer from tinygrad.runtime.autogen import kfd, hsa, libc, pci, vfio, sqtt @@ -32,7 +32,7 @@ class AMDSignal(HCQSignal): class AMDComputeQueue(HWQueue): def __init__(self, dev:AMDDevice): - self.soc, self.pm4, self.gc, self.nbio = dev.soc, dev.pm4, dev.gc, dev.nbio + self.dev, self.soc, self.pm4, self.gc, self.nbio = dev, dev.soc, dev.pm4, dev.gc, dev.nbio super().__init__() def __del__(self): @@ -44,6 +44,15 @@ class AMDComputeQueue(HWQueue): def gfxreg(self, reg:AMDReg): return reg.addr - self.pm4.PACKET3_SET_SH_REG_START def ucfgreg(self, reg:AMDReg): return reg.addr - self.pm4.PACKET3_SET_UCONFIG_REG_START + @contextlib.contextmanager + def pred_exec(self, xcc_mask:int): + if self.dev.xccs > 1: + self.pkt3(self.pm4.PACKET3_PRED_EXEC, xcc_mask << 24) + prev_len = len(self._q) + yield + if self.dev.xccs > 1: + self._q[prev_len-1] |= (len(self._q) - prev_len) + def sqtt_userdata(self, data, *extra_dwords): data_ints = [x[0] for x in struct.iter_unpack('= 10: + cache_flags_dw = self.pm4.PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(gli) \ + | self.pm4.PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(glm) | self.pm4.PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(glm) \ + | self.pm4.PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(glk) | self.pm4.PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(glk) \ + | self.pm4.PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(glv) | self.pm4.PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(gl1) \ + | self.pm4.PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(gl2) | self.pm4.PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(gl2) - self.pkt3(self.pm4.PACKET3_ACQUIRE_MEM, 0, *data64_le(sz), *data64_le(addr), 0, cache_flags_dw) + self.pkt3(self.pm4.PACKET3_ACQUIRE_MEM, 0, *data64_le(sz), *data64_le(addr), 0, cache_flags_dw) + else: + cp_coher_cntl = self.pm4.PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(gli) | \ + self.pm4.PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(glk) | \ + self.pm4.PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | \ + self.pm4.PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | \ + self.pm4.PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1) + self.pkt3(self.pm4.PACKET3_ACQUIRE_MEM, cp_coher_cntl, *data64_le(sz), *data64_le(addr), 0x0000000A) - def release_mem(self, address, value, data_sel, int_sel, ctxid=0, cache_flush=False): - cache_flags_dw = 0 if not cache_flush else (self.pm4.PACKET3_RELEASE_MEM_GCR_GLV_INV | self.pm4.PACKET3_RELEASE_MEM_GCR_GL1_INV \ - | self.pm4.PACKET3_RELEASE_MEM_GCR_GL2_INV | self.pm4.PACKET3_RELEASE_MEM_GCR_GLM_WB \ - | self.pm4.PACKET3_RELEASE_MEM_GCR_GLM_INV | self.pm4.PACKET3_RELEASE_MEM_GCR_GL2_WB | self.pm4.PACKET3_RELEASE_MEM_GCR_SEQ) + def release_mem(self, address=0x0, value=0, data_sel=0, int_sel=2, ctxid=0, cache_flush=False): + if self.dev.gfxver >= 10: + cache_flags_dw = 0 if not cache_flush else (self.pm4.PACKET3_RELEASE_MEM_GCR_GLV_INV | self.pm4.PACKET3_RELEASE_MEM_GCR_GL1_INV \ + | self.pm4.PACKET3_RELEASE_MEM_GCR_GL2_INV | self.pm4.PACKET3_RELEASE_MEM_GCR_GLM_WB \ + | self.pm4.PACKET3_RELEASE_MEM_GCR_GLM_INV | self.pm4.PACKET3_RELEASE_MEM_GCR_GL2_WB | self.pm4.PACKET3_RELEASE_MEM_GCR_SEQ) - event_dw = self.pm4.PACKET3_RELEASE_MEM_EVENT_TYPE(self.pm4.CACHE_FLUSH_AND_INV_TS_EVENT) \ - | self.pm4.PACKET3_RELEASE_MEM_EVENT_INDEX(self.pm4.event_index__mec_release_mem__end_of_pipe) + event_dw = self.pm4.PACKET3_RELEASE_MEM_EVENT_TYPE(self.pm4.CACHE_FLUSH_AND_INV_TS_EVENT) \ + | self.pm4.PACKET3_RELEASE_MEM_EVENT_INDEX(self.pm4.event_index__mec_release_mem__end_of_pipe) - memsel_dw = self.pm4.PACKET3_RELEASE_MEM_DATA_SEL(data_sel) | self.pm4.PACKET3_RELEASE_MEM_INT_SEL(int_sel) \ - | self.pm4.PACKET3_RELEASE_MEM_DST_SEL(0) + memsel_dw = self.pm4.PACKET3_RELEASE_MEM_DATA_SEL(data_sel) | self.pm4.PACKET3_RELEASE_MEM_INT_SEL(int_sel) \ + | self.pm4.PACKET3_RELEASE_MEM_DST_SEL(0) + else: + cache_flags_dw = 0 if not cache_flush else (self.pm4.EOP_TC_WB_ACTION_EN | self.pm4.EOP_TC_NC_ACTION_EN) + + event_dw = self.pm4.EVENT_TYPE(self.pm4.CACHE_FLUSH_AND_INV_TS_EVENT) | self.pm4.EVENT_INDEX(self.pm4.event_index__mec_release_mem__end_of_pipe) + + memsel_dw = self.pm4.DATA_SEL(data_sel) | self.pm4.INT_SEL(int_sel) + + ctxid = 0 self.pkt3(self.pm4.PACKET3_RELEASE_MEM, event_dw | cache_flags_dw, memsel_dw, *data64_le(address), *data64_le(value), ctxid) + def xcc_barrier(self): + if self.dev.xcc_sync is None: return self + assert self.dev.xccs == 8, 'only 8 XCCs supported' + a, b = self.dev.xcc_sync + mem_eq = self.pm4.WAIT_REG_MEM_FUNCTION(WAIT_REG_MEM_FUNCTION_EQ) | self.pm4.WAIT_REG_MEM_MEM_SPACE(1) + self.pkt3(self.pm4.PACKET3_ATOMIC_MEM, self.soc.TC_OP_ATOMIC_ADD_RTN_32, *data64_le(a.value_addr), *data64_le(1), *data64_le(0), 10) # a += 1 + self.pkt3(self.pm4.PACKET3_WAIT_REG_MEM, mem_eq, *data64_le(a.value_addr), 0, 0b111, 10) # a == 0 (mod 8) via bitmask + self.pkt3(self.pm4.PACKET3_ATOMIC_MEM, self.soc.TC_OP_ATOMIC_ADD_RTN_32, *data64_le(b.value_addr), *data64_le(1), *data64_le(0), 10) # b += 1 + self.pkt3(self.pm4.PACKET3_WAIT_REG_MEM, mem_eq, *data64_le(b.value_addr), 0, 0b111, 10) # b == 0 (mod 8) via bitmask + return self + def memory_barrier(self): self.wait_reg_mem(reg_req=self.nbio.regBIF_BX_PF0_GPU_HDP_FLUSH_REQ.addr, reg_done=self.nbio.regBIF_BX_PF0_GPU_HDP_FLUSH_DONE.addr, value=0xffffffff) self.acquire_mem() return self + def xcc_config(self): + self.pkt3(self.pm4.PACKET3_SET_SH_REG, self.gfxreg(self.gc.regCOMPUTE_TG_CHUNK_SIZE), 1) + for xcc_id in range(self.dev.xccs): + with self.pred_exec(xcc_mask=1 << xcc_id): + self.pkt3(self.pm4.PACKET3_SET_SH_REG, self.gfxreg(self.gc.regCOMPUTE_CURRENT_LOGIC_XCC_ID), xcc_id) + return self + def spi_config(self, tracing:bool): spi_config_cntl = self.gc.regSPI_CONFIG_CNTL.encode(ps_pkr_priority_cntl=3, exp_priority_order=3, gpr_write_priority=0x2c688, enable_sqg_bop_events=int(tracing), enable_sqg_top_events=int(tracing)) @@ -167,6 +211,7 @@ class AMDComputeQueue(HWQueue): self.acquire_mem(gli=0, gl2=0) if prg.enable_private_segment_sgpr: + assert self.dev.xccs == 1, "Only architected flat scratch is suppored on multi-xcc" scratch_hilo = data64_le(prg.dev.scratch.va_addr) # sgpr word1 bit31 enables swizzle # sgpr word3 = 0x14 << 12 | 2 << 28 | 2 << 21 | 1 << 23 @@ -198,42 +243,52 @@ class AMDComputeQueue(HWQueue): self.pkt3(self.pm4.PACKET3_SET_SH_REG, self.gfxreg(self.gc.regCOMPUTE_PGM_LO), *data64_le(prg.prog_addr >> 8)) self.pkt3(self.pm4.PACKET3_SET_SH_REG, self.gfxreg(self.gc.regCOMPUTE_PGM_RSRC1), prg.rsrc1, prg.rsrc2) - self.pkt3(self.pm4.PACKET3_SET_SH_REG, self.gfxreg(self.gc.regCOMPUTE_PGM_RSRC3), 0) + self.pkt3(self.pm4.PACKET3_SET_SH_REG, self.gfxreg(self.gc.regCOMPUTE_PGM_RSRC3), prg.rsrc3) self.pkt3(self.pm4.PACKET3_SET_SH_REG, self.gfxreg(self.gc.regCOMPUTE_TMPRING_SIZE), prg.dev.tmpring_size) if prg.dev.has_scratch_base_registers: - self.pkt3(self.pm4.PACKET3_SET_SH_REG, self.gfxreg(self.gc.regCOMPUTE_DISPATCH_SCRATCH_BASE_LO), *data64_le(prg.dev.scratch.va_addr >> 8)) - if prg.dev.target < 110000: self.pkt3(self.pm4.PACKET3_SET_SH_REG, self.gfxreg(self.gc.mmCP_COHER_START_DELAY), 0x20) + for xcc_id in range(self.dev.xccs): + with self.pred_exec(xcc_mask=1<> 8)) + if 100000 <= prg.dev.target < 110000: self.pkt3(self.pm4.PACKET3_SET_SH_REG, self.gfxreg(self.gc.mmCP_COHER_START_DELAY), 0x20) self.pkt3(self.pm4.PACKET3_SET_SH_REG, self.gfxreg(self.gc.regCOMPUTE_RESTART_X), 0, 0, 0) self.pkt3(self.pm4.PACKET3_SET_SH_REG, self.gfxreg(self.gc.regCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xFFFFFFFF, 0xFFFFFFFF) self.pkt3(self.pm4.PACKET3_SET_SH_REG, self.gfxreg(self.gc.regCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xFFFFFFFF, 0xFFFFFFFF) - self.pkt3(self.pm4.PACKET3_SET_SH_REG, self.gfxreg(self.gc.regCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) + if prg.dev.target >= 100000: + self.pkt3(self.pm4.PACKET3_SET_SH_REG, self.gfxreg(self.gc.regCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) self.pkt3(self.pm4.PACKET3_SET_SH_REG, self.gfxreg(self.gc.regCOMPUTE_USER_DATA_0), *user_regs) self.pkt3(self.pm4.PACKET3_SET_SH_REG, self.gfxreg(self.gc.regCOMPUTE_START_X), 0, 0, 0, *local_size, 0, 0) self.pkt3(self.pm4.PACKET3_SET_SH_REG, self.gfxreg(self.gc.regCOMPUTE_RESOURCE_LIMITS), 0) - DISPATCH_INITIATOR = self.gc.regCOMPUTE_DISPATCH_INITIATOR.encode(cs_w32_en=1, force_start_at_000=1, compute_shader_en=1) + gfx10p = {'cs_w32_en': int(prg.wave32)} if prg.dev.target >= 100000 else {} + DISPATCH_INITIATOR = self.gc.regCOMPUTE_DISPATCH_INITIATOR.encode(**gfx10p, force_start_at_000=1, compute_shader_en=1) self.pkt3(self.pm4.PACKET3_DISPATCH_DIRECT, *global_size, DISPATCH_INITIATOR) if prg.dev.sqtt_enabled: self.pkt3(self.pm4.PACKET3_EVENT_WRITE, self.pm4.EVENT_TYPE(self.soc.THREAD_TRACE_MARKER) | self.pm4.EVENT_INDEX(0)) self.pkt3(self.pm4.PACKET3_EVENT_WRITE, self.pm4.EVENT_TYPE(self.soc.CS_PARTIAL_FLUSH) | self.pm4.EVENT_INDEX(EVENT_INDEX_PARTIAL_FLUSH)) + if self.dev.xccs > 1: self.release_mem(cache_flush=True) + self.xcc_barrier() return self def wait(self, signal:AMDSignal, value:sint=0): self.wait_reg_mem(mem=signal.value_addr, value=value, mask=0xffffffff) + self.xcc_barrier() return self def timestamp(self, signal:AMDSignal): - self.release_mem(signal.timestamp_addr, 0, self.pm4.data_sel__mec_release_mem__send_gpu_clock_counter, self.pm4.int_sel__mec_release_mem__none) + with self.pred_exec(xcc_mask=0b1): + self.release_mem(signal.timestamp_addr, 0, self.pm4.data_sel__mec_release_mem__send_gpu_clock_counter, self.pm4.int_sel__mec_release_mem__none) return self def signal(self, signal:AMDSignal, value:sint=0): - # NOTE: this needs an EOP buffer on the queue or it will NULL pointer - self.release_mem(signal.value_addr, value, self.pm4.data_sel__mec_release_mem__send_32_bit_low, - self.pm4.int_sel__mec_release_mem__send_interrupt_after_write_confirm, cache_flush=True) + with self.pred_exec(xcc_mask=0b1): + # NOTE: this needs an EOP buffer on the queue or it will NULL pointer + self.release_mem(signal.value_addr, value, self.pm4.data_sel__mec_release_mem__send_32_bit_low, + self.pm4.int_sel__mec_release_mem__send_interrupt_after_write_confirm, cache_flush=True) - if not AMDDevice.driverless and (dev:=signal.timeline_for_device) is not None: - self.release_mem(dev.queue_event_mailbox_ptr, dev.queue_event.event_id, self.pm4.data_sel__mec_release_mem__send_32_bit_low, - self.pm4.int_sel__mec_release_mem__send_interrupt_after_write_confirm, ctxid=dev.queue_event.event_id) + if not AMDDevice.driverless and (dev:=signal.timeline_for_device) is not None: + self.release_mem(dev.queue_event_mailbox_ptr, dev.queue_event.event_id, self.pm4.data_sel__mec_release_mem__send_32_bit_low, + self.pm4.int_sel__mec_release_mem__send_interrupt_after_write_confirm, ctxid=dev.queue_event.event_id) return self def bind(self, dev:AMDDevice): @@ -249,6 +304,13 @@ class AMDComputeQueue(HWQueue): def _submit(self, dev:AMDDevice): cmds = self.indirect_cmd if dev == self.binded_device else self._q + # WORKAROUND: PACKET3_PRED_EXEC doesn't work in rings, only in IBs, create a fake IB inside a ring to work around that + if self.dev.xccs > 1 and dev != self.binded_device: + ib_end = ((dev.compute_queue.put_value + 5) % len(dev.compute_queue.ring)) + len(cmds) + ib_pad = len(dev.compute_queue.ring) - (ib_end - len(cmds)) if ib_end > len(dev.compute_queue.ring) else 0 + ib_ptr = mv_address(dev.compute_queue.ring) + ((dev.compute_queue.put_value + 5 + ib_pad) % len(dev.compute_queue.ring)) * 4 + cmds = [self.pm4.PACKET3(self.pm4.PACKET3_INDIRECT_BUFFER, 2), *data64_le(ib_ptr), len(cmds) | self.pm4.INDIRECT_BUFFER_VALID, + self.pm4.PACKET3(self.pm4.PACKET3_NOP, ib_pad + len(cmds) - 1), *((0,) * ib_pad), *cmds] for i, value in enumerate(cmds): dev.compute_queue.ring[(dev.compute_queue.put_value + i) % len(dev.compute_queue.ring)] = value @@ -257,7 +319,7 @@ class AMDComputeQueue(HWQueue): class AMDCopyQueue(HWQueue): def __init__(self, dev, max_copy_size=0x40000000): - self.sdma, self.internal_cmd_sizes, self.max_copy_size = dev.sdma, [], max_copy_size + self.dev, self.sdma, self.internal_cmd_sizes, self.max_copy_size = dev, dev.sdma, [], max_copy_size super().__init__() def q(self, *arr): @@ -277,10 +339,12 @@ class AMDCopyQueue(HWQueue): return self def signal(self, signal:AMDSignal, value:sint=0): - self.q(self.sdma.SDMA_OP_FENCE | self.sdma.SDMA_PKT_FENCE_HEADER_MTYPE(3), *data64_le(signal.value_addr), value) + fence_flags = self.sdma.SDMA_PKT_FENCE_HEADER_MTYPE(3) if self.dev.gfxver >= 10 else 0 + self.q(self.sdma.SDMA_OP_FENCE | fence_flags, *data64_le(signal.value_addr), value) + self.q(self.sdma.SDMA_OP_FENCE, *data64_le(signal.value_addr), value) if not AMDDevice.driverless and (dev:=signal.timeline_for_device) is not None: - self.q(self.sdma.SDMA_OP_FENCE | self.sdma.SDMA_PKT_FENCE_HEADER_MTYPE(3), *data64_le(dev.queue_event_mailbox_ptr), dev.queue_event.event_id) + self.q(self.sdma.SDMA_OP_FENCE | fence_flags, *data64_le(dev.queue_event_mailbox_ptr), dev.queue_event.event_id) self.q(self.sdma.SDMA_OP_TRAP, self.sdma.SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(dev.queue_event.event_id)) elif AMDDevice.driverless: self.q(self.sdma.SDMA_OP_TRAP, self.sdma.SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)) @@ -310,7 +374,7 @@ class AMDCopyQueue(HWQueue): self._q, self.cmd_sizes = hw_view, [len(self.indirect_cmd)] def _submit(self, dev:AMDDevice): - if dev.sdma_queue.put_value - dev.sdma_queue.read_ptr[0] > dev.sdma_queue.ring.nbytes: raise RuntimeError("SDMA queue overrun") + if dev.sdma_queue.put_value - dev.sdma_queue.read_ptr > dev.sdma_queue.ring.nbytes: raise RuntimeError("SDMA queue overrun") if self.binded_device == dev: # An IB packet must end on a 8 DW boundary. @@ -361,11 +425,12 @@ class AMDProgram(HCQProgram): self.dev._ensure_has_local_memory(self.private_segment_size) code = hsa.amd_kernel_code_t.from_address(self.lib_gpu.va_addr + rodata_entry) # NOTE: this is wrong, it's not this object - assert code.kernel_code_properties & 0x400 == 0x400 # ENABLE_WAVEFRONT_SIZE32 + self.wave32: bool = code.kernel_code_properties & 0x400 == 0x400 # Set rsrc1.priv=1 on gfx11 to workaround cwsr. self.rsrc1: int = code.compute_pgm_rsrc1 | ((1 << 20) if 110000 <= self.dev.target < 120000 else 0) self.rsrc2: int = code.compute_pgm_rsrc2 | (lds_size << 15) + self.rsrc3: int = image[rodata_entry+44:rodata_entry+48].cast("I")[0] # NOTE: kernel descriptor, not in amd_kernel_code_t struct self.prog_addr: int = self.lib_gpu.va_addr + rodata_entry + code.kernel_code_entry_byte_offset if code.kernel_code_entry_byte_offset == 0: self.prog_addr = self.lib_gpu.va_addr + text_entry # Some programs use hsa_kernel_dispatch_packet_t to read workgroup sizes during execution. @@ -400,20 +465,29 @@ class ProfileSQTTEvent(ProfileEvent): device:str; se:int; blob:bytes; itrace:boo @dataclass class AMDQueueDesc: ring: memoryview - read_ptr: memoryview - write_ptr: memoryview - doorbell: memoryview + read_ptrs: list[memoryview] + write_ptrs: list[memoryview] + doorbells: list[memoryview] put_value: int = 0 + @property + def read_ptr(self): return min(p[0] for p in self.read_ptrs) + + @classmethod + def multi(cls, *queues: AMDQueueDesc): + assert all_same([(mv_address(q.ring), q.put_value) for q in queues]), f"All queues must have the same ring and put_value: {queues}" + return cls(ring=queues[0].ring, put_value=queues[0].put_value, doorbells=flatten(q.doorbells for q in queues), + read_ptrs=flatten(q.read_ptrs for q in queues), write_ptrs=flatten(q.write_ptrs for q in queues)) + def signal_doorbell(self, dev): - self.write_ptr[0] = self.put_value + for write_ptr in self.write_ptrs: write_ptr[0] = self.put_value # Ensure all prior writes are visible to the GPU. if CPUProgram.atomic_lib is not None: CPUProgram.atomic_lib.atomic_thread_fence(__ATOMIC_SEQ_CST:=5) # Flush hdp if queue is in dev mem. if dev.driverless and getenv("AMD_ALLOC_QUEUE_DEV_MEM", 1): dev.dev_iface.adev.gmc.flush_hdp() - self.doorbell[0] = self.put_value + for doorbell in self.doorbells: doorbell[0] = self.put_value @dataclass(frozen=True) class AMDReg(AMDRegBase): @@ -530,21 +604,20 @@ class KFDIface: n_devices=len(mem.meta.mapped_gpu_ids)) assert stm.n_success == len(mem.meta.mapped_gpu_ids) - def create_queue(self, queue_type, ring, gart, eop_buffer=None, ctl_stack_size=0, ctx_save_restore_size=0, debug_memory_size=0): - cwsr_ctx = self.alloc(round_up(ctx_save_restore_size + debug_memory_size, mmap.PAGESIZE)) if ctx_save_restore_size else None + def create_queue(self, queue_type, ring, gart, eop_buffer=None, cwsr_buffer=None, ctl_stack_size=0, ctx_save_restore_size=0, xcc_id=0): queue = kfd.AMDKFD_IOC_CREATE_QUEUE(KFDIface.kfd, ring_base_address=ring.va_addr, ring_size=ring.size, gpu_id=self.gpu_id, - queue_type=queue_type, queue_percentage=kfd.KFD_MAX_QUEUE_PERCENTAGE, queue_priority=kfd.KFD_MAX_QUEUE_PRIORITY, + queue_type=queue_type, queue_percentage=kfd.KFD_MAX_QUEUE_PERCENTAGE|(xcc_id<<8), queue_priority=kfd.KFD_MAX_QUEUE_PRIORITY, eop_buffer_address=eop_buffer.va_addr if eop_buffer else 0, eop_buffer_size=eop_buffer.size if eop_buffer else 0, ctl_stack_size=ctl_stack_size, - ctx_save_restore_address=cwsr_ctx.va_addr if cwsr_ctx else 0, ctx_save_restore_size=ctx_save_restore_size, - write_pointer_address=gart.va_addr, read_pointer_address=gart.va_addr + 8) + ctx_save_restore_address=cwsr_buffer.va_addr if cwsr_buffer else 0, ctx_save_restore_size=ctx_save_restore_size, + write_pointer_address=gart.va_addr, read_pointer_address=gart.va_addr + 8 * (xcc_id + 1)) if not hasattr(self, 'doorbells'): self.doorbells_base = queue.doorbell_offset & (~0x1fff) # doorbell is two pages self.doorbells = cast(HWInterface, KFDIface.kfd).mmap(0, 0x2000, mmap.PROT_READ|mmap.PROT_WRITE, mmap.MAP_SHARED, self.doorbells_base) return AMDQueueDesc(ring=to_mv(ring.va_addr, ring.size).cast("I"), - read_ptr=to_mv(queue.read_pointer_address, 8).cast("Q"), write_ptr=to_mv(queue.write_pointer_address, 8).cast("Q"), - doorbell=to_mv(self.doorbells + queue.doorbell_offset - self.doorbells_base, 8).cast("Q")) + read_ptrs=[to_mv(queue.read_pointer_address, 8).cast("Q")], write_ptrs=[to_mv(queue.write_pointer_address, 8).cast("Q")], + doorbells=[to_mv(self.doorbells + queue.doorbell_offset - self.doorbells_base, 8).cast("Q")]) def sleep(self, tm:int): kfd.AMDKFD_IOC_WAIT_EVENTS(KFDIface.kfd, events_ptr=self.queue_event_arr_ptr, num_events=1, wait_for_all=1, timeout=tm) @@ -680,7 +753,7 @@ class PCIIface: paddrs = [(paddr if mem.meta.mapping.system else (paddr+mem.meta.owner.dev_iface.bar_info[0][0]), size) for paddr,size in mem.meta.mapping.paddrs] self.adev.mm.map_range(mem.va_addr, mem.size, paddrs, system=True, snooped=mem.meta.mapping.snooped, uncached=mem.meta.mapping.uncached) - def create_queue(self, queue_type, ring, gart, eop_buffer=None, ctl_stack_size=0, ctx_save_restore_size=0, debug_memory_size=0): + def create_queue(self, queue_type, ring, gart, eop_buffer=None, cwsr_buffer=None, ctl_stack_size=0, ctx_save_restore_size=0, xcc_id=0): if queue_type == kfd.KFD_IOC_QUEUE_TYPE_SDMA: self.adev.sdma.setup_ring(ring_addr=ring.va_addr, ring_size=ring.size, rptr_addr=gart.va_addr, wptr_addr=gart.va_addr+0x10, doorbell=(doorbell_index:=am.AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0), pipe=0, queue=0) @@ -688,9 +761,8 @@ class PCIIface: self.adev.gfx.setup_ring(ring_addr=ring.va_addr, ring_size=ring.size, rptr_addr=gart.va_addr, wptr_addr=gart.va_addr+0x10, eop_addr=eop_buffer.va_addr, eop_size=eop_buffer.size, doorbell=(doorbell_index:=am.AMDGPU_NAVI10_DOORBELL_MEC_RING0), pipe=0, queue=0) - return AMDQueueDesc(ring=to_mv(ring.va_addr, ring.size).cast("I"), doorbell=to_mv(self.doorbell_cpu_addr + doorbell_index * 8, 8).cast("Q"), - read_ptr=to_mv(gart.va_addr, 8).cast("Q"), write_ptr=to_mv(gart.va_addr+0x10, 8).cast("Q")) - + return AMDQueueDesc(ring=to_mv(ring.va_addr, ring.size).cast("I"), doorbells=[to_mv(self.doorbell_cpu_addr + doorbell_index * 8, 8).cast("Q")], + read_ptrs=[to_mv(gart.va_addr, 8).cast("Q")], write_ptrs=[to_mv(gart.va_addr+0x10, 8).cast("Q")]) def sleep(self, timeout): if PCIIface.vfio and (events_cnt:=len(self.irq_poller.poll(timeout))): self.irq_fd.read(8 * events_cnt) @@ -713,41 +785,52 @@ class AMDDevice(HCQCompiled): self.device_id = int(device.split(":")[1]) if ":" in device else 0 self.dev_iface = PCIIface(self, self.device_id) if AMDDevice.driverless else KFDIface(self, self.device_id) self.target = int(self.dev_iface.props['gfx_target_version']) + self.gfxver = self.target // 10000 self.arch = "gfx%d%x%x" % (self.target // 10000, (self.target // 100) % 100, self.target % 100) - if self.target < 100300 or self.target >= 130000: raise RuntimeError(f"Unsupported arch: {self.arch}") + if self.target < 90402 or self.target >= 120000: raise RuntimeError(f"Unsupported arch: {self.arch}") if DEBUG >= 1: print(f"AMDDevice: opening {self.device_id} with target {self.target} arch {self.arch}") - self.max_cu_id = self.dev_iface.props['simd_count'] // self.dev_iface.props['simd_per_cu'] - 1 - self.max_wave_id = self.dev_iface.props['max_waves_per_simd'] * self.dev_iface.props['simd_per_cu'] - 1 - self.has_scratch_base_registers = self.target >= 110000 + self.max_cu_id = self.dev_iface.props['simd_count'] // self.dev_iface.props['simd_per_cu'] // self.dev_iface.props.get('num_xcc', 1) - 1 + self.max_wave_id = (self.dev_iface.props['max_waves_per_simd'] * self.dev_iface.props['simd_per_cu'] - 1) if self.target >= 100100 else \ + (min((self.max_cu_id+1)*40, self.dev_iface.props['array_count'] // self.dev_iface.props['simd_arrays_per_engine'] * 512) - 1) + self.xccs = self.dev_iface.props.get('num_xcc', 1) if getenv("XCCS", 1) else 1 + self.has_scratch_base_registers = self.target >= 110000 or self.target == 90402 # this is what llvm refers to as "architected flat scratch" # https://gitlab.freedesktop.org/agd5f/linux/-/blob/a1fc9f584c4aaf8bc1ebfa459fc57a3f26a290d8/drivers/gpu/drm/amd/amdkfd/kfd_queue.c#L391 sgrp_size_per_cu, lds_size_per_cu, hwreg_size_per_cu = 0x4000, 0x10000, 0x1000 - vgpr_size_per_cu = 0x60000 if self.target in {110000, 110001, 120000, 120001} else 0x40000 + vgpr_size_per_cu = 0x60000 if self.target in {110000, 110001, 120000, 120001} else \ + 0x80000 if (self.target//100)*100 == 90400 or self.target in {90008, 90010} else 0x40000 wg_data_size = round_up((vgpr_size_per_cu + sgrp_size_per_cu + lds_size_per_cu + hwreg_size_per_cu) * (self.max_cu_id + 1), mmap.PAGESIZE) - ctl_stack_size = round_up(12 * (self.max_cu_id + 1) * (self.max_wave_id + 1) + 8 + 40, mmap.PAGESIZE) - if self.target//10000 == 10: ctl_stack_size = min(ctl_stack_size, 0x7000) - debug_memory_size = round_up((self.max_cu_id + 1) * (self.max_wave_id + 1) * 32, 64) + ctl_stack_size = round_up(12 * (self.max_cu_id + 1) * (self.max_wave_id + 1) + 8 + 40, mmap.PAGESIZE) if self.target >= 100100 else \ + round_up((self.max_wave_id + 1) * 8 + 8 + 40, mmap.PAGESIZE) + debug_memory_size = round_up((self.max_cu_id + 1 if self.target >= 100100 else 1) * (self.max_wave_id + 1) * 32, 64) + if self.gfxver == 10: ctl_stack_size = min(ctl_stack_size, 0x7000) - self.soc = importlib.import_module(f"tinygrad.runtime.autogen.am.{({10: 'navi10', 11: 'soc21', 12: 'soc24'}[self.target//10000])}") - self.pm4 = importlib.import_module("tinygrad.runtime.autogen.am.pm4_nv") + self.soc = importlib.import_module(f"tinygrad.runtime.autogen.am.{({9: 'vega10', 10: 'navi10', 11: 'soc21', 12: 'soc24'}[self.gfxver])}") + self.pm4 = importlib.import_module(f"tinygrad.runtime.autogen.am.pm4_{'nv' if self.gfxver >= 10 else 'soc15'}") self.sdma = import_module('sdma', self.dev_iface.ip_versions[am.SDMA0_HWIP]) self.gc = AMDIP('gc', self.dev_iface.ip_versions[am.GC_HWIP], self.dev_iface.ip_offsets[am.GC_HWIP]) - self.nbio = AMDIP('nbio' if self.target < 120000 else 'nbif', self.dev_iface.ip_versions[am.NBIF_HWIP], self.dev_iface.ip_offsets[am.NBIF_HWIP]) + pad = (0,) if self.gfxver == 9 else () # ?!?!?!?!??!?!?! + self.nbio = AMDIP('nbio' if self.gfxver < 12 else 'nbif', self.dev_iface.ip_versions[am.NBIF_HWIP], pad+self.dev_iface.ip_offsets[am.NBIF_HWIP]) self.compute_queue = self.create_queue(kfd.KFD_IOC_QUEUE_TYPE_COMPUTE, 0x800000, ctx_save_restore_size=wg_data_size + ctl_stack_size, eop_buffer_size=0x1000, ctl_stack_size=ctl_stack_size, debug_memory_size=debug_memory_size) + max_copy_size = 0x40000000 if self.dev_iface.ip_versions[am.SDMA0_HWIP][0] >= 5 else 0x400000 self.sdma_queue = self.create_queue(kfd.KFD_IOC_QUEUE_TYPE_SDMA, 0x800000) super().__init__(device, AMDAllocator(self), AMDLLVMRenderer() if getenv("AMD_LLVM", 0) else AMDRenderer(self.arch), AMDLLVMCompiler(self.arch) if getenv("AMD_LLVM", 0) else HIPCompiler(self.arch), functools.partial(AMDProgram, self), - AMDSignal, functools.partial(AMDComputeQueue, self), functools.partial(AMDCopyQueue, self)) + AMDSignal, functools.partial(AMDComputeQueue, self), functools.partial(AMDCopyQueue, self, max_copy_size=max_copy_size)) # Scratch setup self.max_private_segment_size = 0 self._ensure_has_local_memory(128) # set default scratch size to 128 bytes per thread + # XCC setup + self.xcc_sync: tuple[AMDSignal, AMDSignal]|None = (AMDSignal(), AMDSignal()) if self.xccs > 1 else None + if self.xccs > 1: AMDComputeQueue(self).xcc_config().submit(self) + # SQTT is disabled by default because of runtime overhead and big file sizes (~200mb to Tensor.full() two 4096x4096 tensors and matmul them) self.sqtt_enabled = PROFILE and bool(getenv("SQTT", 0)) if self.sqtt_enabled: @@ -767,8 +850,11 @@ class AMDDevice(HCQCompiled): ring = self.dev_iface.alloc(ring_size, uncached=True, cpu_access=True) gart = self.dev_iface.alloc(0x1000, uncached=True, cpu_access=True) eop_buffer = self.dev_iface.alloc(eop_buffer_size) if eop_buffer_size else None - return self.dev_iface.create_queue(queue_type, ring, gart, eop_buffer=eop_buffer, debug_memory_size=debug_memory_size, - ctx_save_restore_size=ctx_save_restore_size, ctl_stack_size=ctl_stack_size) + cwsr_buffer_size = round_up((ctx_save_restore_size + debug_memory_size) * self.dev_iface.props.get('num_xcc', 1), mmap.PAGESIZE) + return AMDQueueDesc.multi(*(self.dev_iface.create_queue(queue_type, ring, gart, eop_buffer=eop_buffer, xcc_id=xcc_id, + ctx_save_restore_size=ctx_save_restore_size, ctl_stack_size=ctl_stack_size, + cwsr_buffer=(self.dev_iface.alloc(cwsr_buffer_size) if ctx_save_restore_size else None)) + for xcc_id in range(self.xccs if queue_type == kfd.KFD_IOC_QUEUE_TYPE_COMPUTE else 1))) def _ensure_has_local_memory(self, required): if self.max_private_segment_size >= required: return @@ -776,12 +862,13 @@ class AMDDevice(HCQCompiled): # =gfx11 requires 256 wave_scratch_len = round_up(((self.max_wave_id + 1) * required), 256 if self.target >= 110000 else 1024) - self.scratch, ok = self._realloc(getattr(self, 'scratch', None), (self.max_cu_id+1)*self.dev_iface.props['max_slots_scratch_cu']*wave_scratch_len) + scratch_size = (self.max_cu_id+1)*self.dev_iface.props['max_slots_scratch_cu']*wave_scratch_len # per xcc + self.scratch, ok = self._realloc(getattr(self, 'scratch', None), scratch_size*self.xccs) if ok: engines = self.dev_iface.props['array_count'] // self.dev_iface.props['simd_arrays_per_engine'] waves = wave_scratch_len // (256 if self.target >= 110000 else 1024) # >=gfx11 wavesize is per SE - wavesize = self.scratch.size // ((wave_scratch_len * engines) if self.target >= 110000 else wave_scratch_len) + wavesize = scratch_size // ((wave_scratch_len * engines) if self.target >= 110000 else wave_scratch_len) self.tmpring_size = waves << 12 | wavesize self.max_private_segment_size = required